1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Register Bank Source Fragments *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_REGBANK_DECLARATIONS
10#undef GET_REGBANK_DECLARATIONS
11namespace llvm {
12namespace AArch64 {
13enum : unsigned {
14 InvalidRegBankID = ~0u,
15 CCRegBankID = 0,
16 FPRRegBankID = 1,
17 GPRRegBankID = 2,
18 NumRegisterBanks,
19};
20} // end namespace AArch64
21} // end namespace llvm
22#endif // GET_REGBANK_DECLARATIONS
23
24#ifdef GET_TARGET_REGBANK_CLASS
25#undef GET_TARGET_REGBANK_CLASS
26private:
27 static const RegisterBank *RegBanks[];
28 static const unsigned Sizes[];
29
30public:
31 const RegisterBank &getRegBankFromRegClass(const TargetRegisterClass &RC, LLT Ty) const override;
32protected:
33 AArch64GenRegisterBankInfo(unsigned HwMode = 0);
34
35#endif // GET_TARGET_REGBANK_CLASS
36
37#ifdef GET_TARGET_REGBANK_IMPL
38#undef GET_TARGET_REGBANK_IMPL
39namespace llvm {
40namespace AArch64 {
41const uint32_t CCRegBankCoverageData[] = {
42 // 0-31
43 0,
44 // 32-63
45 (1u << (AArch64::CCRRegClassID - 32)) |
46 0,
47 // 64-95
48 0,
49 // 96-127
50 0,
51 // 128-159
52 0,
53 // 160-191
54 0,
55 // 192-223
56 0,
57 // 224-255
58 0,
59 // 256-287
60 0,
61 // 288-319
62 0,
63 // 320-351
64 0,
65 // 352-383
66 0,
67 // 384-415
68 0,
69 // 416-447
70 0,
71 // 448-479
72 0,
73 // 480-511
74 0,
75 // 512-543
76 0,
77};
78const uint32_t FPRRegBankCoverageData[] = {
79 // 0-31
80 (1u << (AArch64::FPR8RegClassID - 0)) |
81 (1u << (AArch64::FPR16RegClassID - 0)) |
82 (1u << (AArch64::FPR16_loRegClassID - 0)) |
83 0,
84 // 32-63
85 (1u << (AArch64::FPR32RegClassID - 32)) |
86 (1u << (AArch64::FPR64RegClassID - 32)) |
87 (1u << (AArch64::FPR32_with_hsub_in_FPR16_loRegClassID - 32)) |
88 0,
89 // 64-95
90 (1u << (AArch64::DDRegClassID - 64)) |
91 (1u << (AArch64::FPR128RegClassID - 64)) |
92 (1u << (AArch64::FPR64_loRegClassID - 64)) |
93 (1u << (AArch64::DD_with_dsub0_in_FPR64_loRegClassID - 64)) |
94 (1u << (AArch64::DD_with_dsub1_in_FPR64_loRegClassID - 64)) |
95 (1u << (AArch64::FPR128_loRegClassID - 64)) |
96 (1u << (AArch64::DD_with_dsub0_in_FPR64_lo_and_DD_with_dsub1_in_FPR64_loRegClassID - 64)) |
97 (1u << (AArch64::ZPRRegClassID - 64)) |
98 (1u << (AArch64::ZPRMul2RegClassID - 64)) |
99 0,
100 // 96-127
101 (1u << (AArch64::DDDRegClassID - 96)) |
102 (1u << (AArch64::DDDDRegClassID - 96)) |
103 (1u << (AArch64::QQRegClassID - 96)) |
104 (1u << (AArch64::DDD_with_dsub0_in_FPR64_loRegClassID - 96)) |
105 (1u << (AArch64::DDD_with_dsub1_in_FPR64_loRegClassID - 96)) |
106 (1u << (AArch64::DDDD_with_dsub1_in_FPR64_loRegClassID - 96)) |
107 (1u << (AArch64::DDD_with_dsub2_in_FPR64_loRegClassID - 96)) |
108 (1u << (AArch64::DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub1_in_FPR64_loRegClassID - 96)) |
109 (1u << (AArch64::DDD_with_dsub1_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_loRegClassID - 96)) |
110 (1u << (AArch64::DDDD_with_dsub2_in_FPR64_loRegClassID - 96)) |
111 (1u << (AArch64::DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_loRegClassID - 96)) |
112 (1u << (AArch64::DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_loRegClassID - 96)) |
113 (1u << (AArch64::DDDD_with_dsub3_in_FPR64_loRegClassID - 96)) |
114 (1u << (AArch64::DDDD_with_dsub2_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_loRegClassID - 96)) |
115 (1u << (AArch64::DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_loRegClassID - 96)) |
116 (1u << (AArch64::DDDD_with_dsub0_in_FPR64_loRegClassID - 96)) |
117 (1u << (AArch64::DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub1_in_FPR64_loRegClassID - 96)) |
118 (1u << (AArch64::DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_loRegClassID - 96)) |
119 (1u << (AArch64::DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_loRegClassID - 96)) |
120 (1u << (AArch64::FPR128_0to7RegClassID - 96)) |
121 (1u << (AArch64::ZPRMul2_HiRegClassID - 96)) |
122 (1u << (AArch64::ZPRMul2_Hi_and_ZPRMul4RegClassID - 96)) |
123 (1u << (AArch64::ZPRMul4_and_ZPR_KRegClassID - 96)) |
124 (1u << (AArch64::ZPRMul2_and_ZPR_KRegClassID - 96)) |
125 (1u << (AArch64::ZPRMul2_LoRegClassID - 96)) |
126 (1u << (AArch64::ZPRMul2_Lo_and_ZPRMul4RegClassID - 96)) |
127 (1u << (AArch64::ZPRMul4_and_ZPR_3bRegClassID - 96)) |
128 (1u << (AArch64::ZPRMul2_and_ZPR_3bRegClassID - 96)) |
129 (1u << (AArch64::ZPRMul4RegClassID - 96)) |
130 (1u << (AArch64::ZPR_4bRegClassID - 96)) |
131 (1u << (AArch64::ZPR_3bRegClassID - 96)) |
132 (1u << (AArch64::ZPR_KRegClassID - 96)) |
133 0,
134 // 128-159
135 (1u << (AArch64::QQ_with_dsub1_in_FPR64_loRegClassID - 128)) |
136 (1u << (AArch64::QQ_with_qsub0_in_FPR128_loRegClassID - 128)) |
137 (1u << (AArch64::QQ_with_qsub0_in_FPR128_lo_and_QQ_with_dsub1_in_FPR64_loRegClassID - 128)) |
138 (1u << (AArch64::QQ_with_qsub0_in_FPR128_0to7RegClassID - 128)) |
139 (1u << (AArch64::QQ_with_qsub1_in_FPR128_0to7RegClassID - 128)) |
140 0,
141 // 160-191
142 (1u << (AArch64::QQ_with_qsub0_in_FPR128_0to7_and_QQ_with_qsub1_in_FPR128_0to7RegClassID - 160)) |
143 0,
144 // 192-223
145 (1u << (AArch64::QQQRegClassID - 192)) |
146 (1u << (AArch64::QQQ_with_dsub1_in_FPR64_loRegClassID - 192)) |
147 (1u << (AArch64::QQQ_with_qsub0_in_FPR128_loRegClassID - 192)) |
148 (1u << (AArch64::QQQ_with_dsub2_in_FPR64_loRegClassID - 192)) |
149 (1u << (AArch64::QQQ_with_dsub1_in_FPR64_lo_and_QQQ_with_dsub2_in_FPR64_loRegClassID - 192)) |
150 (1u << (AArch64::QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_dsub1_in_FPR64_loRegClassID - 192)) |
151 (1u << (AArch64::QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_dsub2_in_FPR64_loRegClassID - 192)) |
152 (1u << (AArch64::QQQ_with_qsub0_in_FPR128_0to7RegClassID - 192)) |
153 (1u << (AArch64::QQQ_with_qsub1_in_FPR128_0to7RegClassID - 192)) |
154 (1u << (AArch64::QQQ_with_qsub2_in_FPR128_0to7RegClassID - 192)) |
155 0,
156 // 224-255
157 (1u << (AArch64::QQQ_with_qsub0_in_FPR128_0to7_and_QQQ_with_qsub1_in_FPR128_0to7RegClassID - 224)) |
158 (1u << (AArch64::QQQ_with_dsub1_in_FPR64_lo_and_QQQ_with_qsub2_in_FPR128_0to7RegClassID - 224)) |
159 (1u << (AArch64::QQQ_with_qsub0_in_FPR128_0to7_and_QQQ_with_qsub2_in_FPR128_0to7RegClassID - 224)) |
160 0,
161 // 256-287
162 0,
163 // 288-319
164 (1u << (AArch64::QQQQRegClassID - 288)) |
165 (1u << (AArch64::QQQQ_with_dsub1_in_FPR64_loRegClassID - 288)) |
166 (1u << (AArch64::QQQQ_with_dsub1_in_FPR64_lo_and_QQQQ_with_dsub2_in_FPR64_loRegClassID - 288)) |
167 (1u << (AArch64::QQQQ_with_dsub1_in_FPR64_lo_and_QQQQ_with_dsub3_in_FPR64_loRegClassID - 288)) |
168 (1u << (AArch64::QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_dsub3_in_FPR64_loRegClassID - 288)) |
169 (1u << (AArch64::QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_dsub2_in_FPR64_loRegClassID - 288)) |
170 (1u << (AArch64::QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_dsub1_in_FPR64_loRegClassID - 288)) |
171 (1u << (AArch64::QQQQ_with_dsub2_in_FPR64_loRegClassID - 288)) |
172 (1u << (AArch64::QQQQ_with_dsub2_in_FPR64_lo_and_QQQQ_with_dsub3_in_FPR64_loRegClassID - 288)) |
173 (1u << (AArch64::QQQQ_with_dsub3_in_FPR64_loRegClassID - 288)) |
174 (1u << (AArch64::QQQQ_with_qsub0_in_FPR128_loRegClassID - 288)) |
175 0,
176 // 320-351
177 (1u << (AArch64::QQQQ_with_qsub0_in_FPR128_0to7RegClassID - 320)) |
178 (1u << (AArch64::QQQQ_with_qsub1_in_FPR128_0to7RegClassID - 320)) |
179 (1u << (AArch64::QQQQ_with_dsub1_in_FPR64_lo_and_QQQQ_with_qsub2_in_FPR128_0to7RegClassID - 320)) |
180 (1u << (AArch64::QQQQ_with_qsub2_in_FPR128_0to7RegClassID - 320)) |
181 (1u << (AArch64::QQQQ_with_dsub2_in_FPR64_lo_and_QQQQ_with_qsub3_in_FPR128_0to7RegClassID - 320)) |
182 (1u << (AArch64::QQQQ_with_qsub3_in_FPR128_0to7RegClassID - 320)) |
183 0,
184 // 352-383
185 (1u << (AArch64::QQQQ_with_qsub0_in_FPR128_0to7_and_QQQQ_with_qsub1_in_FPR128_0to7RegClassID - 352)) |
186 (1u << (AArch64::QQQQ_with_qsub0_in_FPR128_0to7_and_QQQQ_with_qsub2_in_FPR128_0to7RegClassID - 352)) |
187 (1u << (AArch64::QQQQ_with_qsub0_in_FPR128_0to7_and_QQQQ_with_qsub3_in_FPR128_0to7RegClassID - 352)) |
188 (1u << (AArch64::QQQQ_with_dsub1_in_FPR64_lo_and_QQQQ_with_qsub3_in_FPR128_0to7RegClassID - 352)) |
189 0,
190 // 384-415
191 0,
192 // 416-447
193 0,
194 // 448-479
195 0,
196 // 480-511
197 0,
198 // 512-543
199 0,
200};
201const uint32_t GPRRegBankCoverageData[] = {
202 // 0-31
203 0,
204 // 32-63
205 (1u << (AArch64::GPR32allRegClassID - 32)) |
206 (1u << (AArch64::GPR32RegClassID - 32)) |
207 (1u << (AArch64::GPR32spRegClassID - 32)) |
208 (1u << (AArch64::GPR32commonRegClassID - 32)) |
209 (1u << (AArch64::WSeqPairsClassRegClassID - 32)) |
210 (1u << (AArch64::GPR64allRegClassID - 32)) |
211 (1u << (AArch64::GPR64RegClassID - 32)) |
212 (1u << (AArch64::GPR64spRegClassID - 32)) |
213 (1u << (AArch64::GPR64commonRegClassID - 32)) |
214 (1u << (AArch64::WSeqPairsClass_with_subo32_in_GPR32commonRegClassID - 32)) |
215 (1u << (AArch64::GPR64noipRegClassID - 32)) |
216 (1u << (AArch64::GPR64common_and_GPR64noipRegClassID - 32)) |
217 (1u << (AArch64::tcGPR64RegClassID - 32)) |
218 (1u << (AArch64::tcGPRnotx16RegClassID - 32)) |
219 (1u << (AArch64::tcGPRnotx16x17RegClassID - 32)) |
220 (1u << (AArch64::GPR32argRegClassID - 32)) |
221 (1u << (AArch64::WSeqPairsClass_with_sube32_in_GPR32argRegClassID - 32)) |
222 (1u << (AArch64::MatrixIndexGPR32_12_15RegClassID - 32)) |
223 (1u << (AArch64::WSeqPairsClass_with_sube32_in_MatrixIndexGPR32_12_15RegClassID - 32)) |
224 (1u << (AArch64::MatrixIndexGPR32_8_11RegClassID - 32)) |
225 (1u << (AArch64::WSeqPairsClass_with_sube32_in_MatrixIndexGPR32_8_11RegClassID - 32)) |
226 0,
227 // 64-95
228 (1u << (AArch64::XSeqPairsClassRegClassID - 64)) |
229 (1u << (AArch64::XSeqPairsClass_with_subo64_in_GPR64commonRegClassID - 64)) |
230 (1u << (AArch64::XSeqPairsClass_with_sube64_in_GPR64noipRegClassID - 64)) |
231 (1u << (AArch64::XSeqPairsClass_with_sube64_in_tcGPRnotx16RegClassID - 64)) |
232 (1u << (AArch64::XSeqPairsClass_with_subo64_in_tcGPRnotx16x17RegClassID - 64)) |
233 (1u << (AArch64::XSeqPairsClass_with_sube64_in_GPR64argRegClassID - 64)) |
234 (1u << (AArch64::GPR64argRegClassID - 64)) |
235 (1u << (AArch64::XSeqPairsClass_with_sube64_in_GPR64_with_sub_32_in_MatrixIndexGPR32_12_15RegClassID - 64)) |
236 (1u << (AArch64::GPR64_with_sub_32_in_MatrixIndexGPR32_12_15RegClassID - 64)) |
237 (1u << (AArch64::XSeqPairsClass_with_sube64_in_GPR64_with_sub_32_in_MatrixIndexGPR32_8_11RegClassID - 64)) |
238 (1u << (AArch64::GPR64_with_sub_32_in_MatrixIndexGPR32_8_11RegClassID - 64)) |
239 (1u << (AArch64::XSeqPairsClass_with_subo64_in_FIXED_REGSRegClassID - 64)) |
240 (1u << (AArch64::FIXED_REGSRegClassID - 64)) |
241 (1u << (AArch64::FIXED_REGS_with_sub_32RegClassID - 64)) |
242 (1u << (AArch64::FIXED_REGS_and_GPR64RegClassID - 64)) |
243 (1u << (AArch64::XSeqPairsClass_with_sube64_in_tcGPR64RegClassID - 64)) |
244 (1u << (AArch64::XSeqPairsClass_with_subo64_in_tcGPR64RegClassID - 64)) |
245 (1u << (AArch64::XSeqPairsClass_with_sube64_in_tcGPRx16x17RegClassID - 64)) |
246 (1u << (AArch64::tcGPRx16x17RegClassID - 64)) |
247 (1u << (AArch64::tcGPRx17RegClassID - 64)) |
248 (1u << (AArch64::XSeqPairsClass_with_subo64_in_GPR64noipRegClassID - 64)) |
249 0,
250 // 96-127
251 0,
252 // 128-159
253 0,
254 // 160-191
255 0,
256 // 192-223
257 0,
258 // 224-255
259 0,
260 // 256-287
261 0,
262 // 288-319
263 0,
264 // 320-351
265 0,
266 // 352-383
267 0,
268 // 384-415
269 0,
270 // 416-447
271 0,
272 // 448-479
273 0,
274 // 480-511
275 0,
276 // 512-543
277 0,
278};
279
280constexpr RegisterBank CCRegBank(/* ID */ AArch64::CCRegBankID, /* Name */ "CC", /* CoveredRegClasses */ CCRegBankCoverageData, /* NumRegClasses */ 530);
281constexpr RegisterBank FPRRegBank(/* ID */ AArch64::FPRRegBankID, /* Name */ "FPR", /* CoveredRegClasses */ FPRRegBankCoverageData, /* NumRegClasses */ 530);
282constexpr RegisterBank GPRRegBank(/* ID */ AArch64::GPRRegBankID, /* Name */ "GPR", /* CoveredRegClasses */ GPRRegBankCoverageData, /* NumRegClasses */ 530);
283} // end namespace AArch64
284
285const RegisterBank *AArch64GenRegisterBankInfo::RegBanks[] = {
286 &AArch64::CCRegBank,
287 &AArch64::FPRRegBank,
288 &AArch64::GPRRegBank,
289};
290
291const unsigned AArch64GenRegisterBankInfo::Sizes[] = {
292 // Mode = 0 (Default)
293 32,
294 512,
295 128,
296 // Mode = 1 (SMEWithZPRPredicateSpills)
297 32,
298 512,
299 128,
300};
301
302AArch64GenRegisterBankInfo::AArch64GenRegisterBankInfo(unsigned HwMode)
303 : RegisterBankInfo(RegBanks, AArch64::NumRegisterBanks, Sizes, HwMode) {
304 // Assert that RegBank indices match their ID's
305#ifndef NDEBUG
306 for (auto RB : enumerate(RegBanks))
307 assert(RB.index() == RB.value()->getID() && "Index != ID");
308#endif // NDEBUG
309}
310const RegisterBank &
311AArch64GenRegisterBankInfo::getRegBankFromRegClass(const TargetRegisterClass &RC, LLT) const {
312 constexpr uint32_t InvalidRegBankID = uint32_t(AArch64::InvalidRegBankID) & 3;
313 static const uint32_t RegClass2RegBank[24] = {
314 (uint32_t(InvalidRegBankID) << 0) |
315 (uint32_t(InvalidRegBankID) << 2) |
316 (uint32_t(InvalidRegBankID) << 4) |
317 (uint32_t(InvalidRegBankID) << 6) |
318 (uint32_t(InvalidRegBankID) << 8) |
319 (uint32_t(InvalidRegBankID) << 10) |
320 (uint32_t(AArch64::FPRRegBankID) << 12) | // FPR8RegClassID
321 (uint32_t(AArch64::FPRRegBankID) << 14) | // FPR16RegClassID
322 (uint32_t(InvalidRegBankID) << 16) |
323 (uint32_t(AArch64::FPRRegBankID) << 18) | // FPR16_loRegClassID
324 (uint32_t(InvalidRegBankID) << 20) |
325 (uint32_t(InvalidRegBankID) << 22) |
326 (uint32_t(InvalidRegBankID) << 24) |
327 (uint32_t(InvalidRegBankID) << 26) |
328 (uint32_t(InvalidRegBankID) << 28) |
329 (uint32_t(InvalidRegBankID) << 30),
330 (uint32_t(InvalidRegBankID) << 0) |
331 (uint32_t(InvalidRegBankID) << 2) |
332 (uint32_t(InvalidRegBankID) << 4) |
333 (uint32_t(InvalidRegBankID) << 6) |
334 (uint32_t(InvalidRegBankID) << 8) |
335 (uint32_t(InvalidRegBankID) << 10) |
336 (uint32_t(InvalidRegBankID) << 12) |
337 (uint32_t(InvalidRegBankID) << 14) |
338 (uint32_t(InvalidRegBankID) << 16) |
339 (uint32_t(InvalidRegBankID) << 18) |
340 (uint32_t(InvalidRegBankID) << 20) |
341 (uint32_t(InvalidRegBankID) << 22) |
342 (uint32_t(InvalidRegBankID) << 24) |
343 (uint32_t(InvalidRegBankID) << 26) |
344 (uint32_t(InvalidRegBankID) << 28) |
345 (uint32_t(InvalidRegBankID) << 30),
346 (uint32_t(InvalidRegBankID) << 0) |
347 (uint32_t(InvalidRegBankID) << 2) |
348 (uint32_t(InvalidRegBankID) << 4) |
349 (uint32_t(InvalidRegBankID) << 6) |
350 (uint32_t(InvalidRegBankID) << 8) |
351 (uint32_t(InvalidRegBankID) << 10) |
352 (uint32_t(AArch64::GPRRegBankID) << 12) | // GPR32allRegClassID
353 (uint32_t(AArch64::FPRRegBankID) << 14) | // FPR32RegClassID
354 (uint32_t(AArch64::GPRRegBankID) << 16) | // GPR32RegClassID
355 (uint32_t(AArch64::GPRRegBankID) << 18) | // GPR32spRegClassID
356 (uint32_t(AArch64::GPRRegBankID) << 20) | // GPR32commonRegClassID
357 (uint32_t(AArch64::FPRRegBankID) << 22) | // FPR32_with_hsub_in_FPR16_loRegClassID
358 (uint32_t(AArch64::GPRRegBankID) << 24) | // GPR32argRegClassID
359 (uint32_t(AArch64::GPRRegBankID) << 26) | // MatrixIndexGPR32_12_15RegClassID
360 (uint32_t(AArch64::GPRRegBankID) << 28) | // MatrixIndexGPR32_8_11RegClassID
361 (uint32_t(AArch64::CCRegBankID) << 30), // CCRRegClassID
362 (uint32_t(InvalidRegBankID) << 0) |
363 (uint32_t(AArch64::GPRRegBankID) << 2) | // WSeqPairsClassRegClassID
364 (uint32_t(AArch64::GPRRegBankID) << 4) | // WSeqPairsClass_with_subo32_in_GPR32commonRegClassID
365 (uint32_t(AArch64::GPRRegBankID) << 6) | // WSeqPairsClass_with_sube32_in_GPR32argRegClassID
366 (uint32_t(AArch64::GPRRegBankID) << 8) | // WSeqPairsClass_with_sube32_in_MatrixIndexGPR32_12_15RegClassID
367 (uint32_t(AArch64::GPRRegBankID) << 10) | // WSeqPairsClass_with_sube32_in_MatrixIndexGPR32_8_11RegClassID
368 (uint32_t(AArch64::GPRRegBankID) << 12) | // GPR64allRegClassID
369 (uint32_t(AArch64::FPRRegBankID) << 14) | // FPR64RegClassID
370 (uint32_t(AArch64::GPRRegBankID) << 16) | // GPR64RegClassID
371 (uint32_t(AArch64::GPRRegBankID) << 18) | // GPR64spRegClassID
372 (uint32_t(AArch64::GPRRegBankID) << 20) | // GPR64commonRegClassID
373 (uint32_t(AArch64::GPRRegBankID) << 22) | // GPR64noipRegClassID
374 (uint32_t(AArch64::GPRRegBankID) << 24) | // GPR64common_and_GPR64noipRegClassID
375 (uint32_t(AArch64::GPRRegBankID) << 26) | // tcGPR64RegClassID
376 (uint32_t(AArch64::GPRRegBankID) << 28) | // tcGPRnotx16RegClassID
377 (uint32_t(AArch64::GPRRegBankID) << 30), // tcGPRnotx16x17RegClassID
378 (uint32_t(AArch64::FPRRegBankID) << 0) | // FPR64_loRegClassID
379 (uint32_t(AArch64::GPRRegBankID) << 2) | // GPR64argRegClassID
380 (uint32_t(AArch64::GPRRegBankID) << 4) | // FIXED_REGSRegClassID
381 (uint32_t(AArch64::GPRRegBankID) << 6) | // GPR64_with_sub_32_in_MatrixIndexGPR32_12_15RegClassID
382 (uint32_t(AArch64::GPRRegBankID) << 8) | // GPR64_with_sub_32_in_MatrixIndexGPR32_8_11RegClassID
383 (uint32_t(AArch64::GPRRegBankID) << 10) | // FIXED_REGS_with_sub_32RegClassID
384 (uint32_t(AArch64::GPRRegBankID) << 12) | // tcGPRx16x17RegClassID
385 (uint32_t(AArch64::GPRRegBankID) << 14) | // FIXED_REGS_and_GPR64RegClassID
386 (uint32_t(InvalidRegBankID) << 16) |
387 (uint32_t(AArch64::GPRRegBankID) << 18) | // tcGPRx17RegClassID
388 (uint32_t(AArch64::FPRRegBankID) << 20) | // DDRegClassID
389 (uint32_t(AArch64::FPRRegBankID) << 22) | // DD_with_dsub0_in_FPR64_loRegClassID
390 (uint32_t(AArch64::FPRRegBankID) << 24) | // DD_with_dsub1_in_FPR64_loRegClassID
391 (uint32_t(AArch64::GPRRegBankID) << 26) | // XSeqPairsClassRegClassID
392 (uint32_t(AArch64::FPRRegBankID) << 28) | // DD_with_dsub0_in_FPR64_lo_and_DD_with_dsub1_in_FPR64_loRegClassID
393 (uint32_t(AArch64::GPRRegBankID) << 30), // XSeqPairsClass_with_subo64_in_GPR64commonRegClassID
394 (uint32_t(AArch64::GPRRegBankID) << 0) | // XSeqPairsClass_with_subo64_in_GPR64noipRegClassID
395 (uint32_t(AArch64::GPRRegBankID) << 2) | // XSeqPairsClass_with_sube64_in_GPR64noipRegClassID
396 (uint32_t(AArch64::GPRRegBankID) << 4) | // XSeqPairsClass_with_sube64_in_tcGPR64RegClassID
397 (uint32_t(AArch64::GPRRegBankID) << 6) | // XSeqPairsClass_with_sube64_in_tcGPRnotx16RegClassID
398 (uint32_t(AArch64::GPRRegBankID) << 8) | // XSeqPairsClass_with_subo64_in_tcGPR64RegClassID
399 (uint32_t(AArch64::GPRRegBankID) << 10) | // XSeqPairsClass_with_subo64_in_tcGPRnotx16x17RegClassID
400 (uint32_t(AArch64::GPRRegBankID) << 12) | // XSeqPairsClass_with_sube64_in_GPR64argRegClassID
401 (uint32_t(AArch64::GPRRegBankID) << 14) | // XSeqPairsClass_with_sube64_in_GPR64_with_sub_32_in_MatrixIndexGPR32_12_15RegClassID
402 (uint32_t(AArch64::GPRRegBankID) << 16) | // XSeqPairsClass_with_sube64_in_GPR64_with_sub_32_in_MatrixIndexGPR32_8_11RegClassID
403 (uint32_t(AArch64::GPRRegBankID) << 18) | // XSeqPairsClass_with_sube64_in_tcGPRx16x17RegClassID
404 (uint32_t(AArch64::GPRRegBankID) << 20) | // XSeqPairsClass_with_subo64_in_FIXED_REGSRegClassID
405 (uint32_t(AArch64::FPRRegBankID) << 22) | // FPR128RegClassID
406 (uint32_t(AArch64::FPRRegBankID) << 24) | // ZPRRegClassID
407 (uint32_t(AArch64::FPRRegBankID) << 26) | // FPR128_loRegClassID
408 (uint32_t(InvalidRegBankID) << 28) |
409 (uint32_t(AArch64::FPRRegBankID) << 30), // ZPRMul2RegClassID
410 (uint32_t(AArch64::FPRRegBankID) << 0) | // ZPR_4bRegClassID
411 (uint32_t(AArch64::FPRRegBankID) << 2) | // FPR128_0to7RegClassID
412 (uint32_t(AArch64::FPRRegBankID) << 4) | // ZPRMul2_HiRegClassID
413 (uint32_t(AArch64::FPRRegBankID) << 6) | // ZPRMul2_LoRegClassID
414 (uint32_t(AArch64::FPRRegBankID) << 8) | // ZPRMul4RegClassID
415 (uint32_t(AArch64::FPRRegBankID) << 10) | // ZPR_3bRegClassID
416 (uint32_t(AArch64::FPRRegBankID) << 12) | // ZPR_KRegClassID
417 (uint32_t(AArch64::FPRRegBankID) << 14) | // ZPRMul2_Hi_and_ZPRMul4RegClassID
418 (uint32_t(AArch64::FPRRegBankID) << 16) | // ZPRMul2_Lo_and_ZPRMul4RegClassID
419 (uint32_t(AArch64::FPRRegBankID) << 18) | // ZPRMul2_and_ZPR_3bRegClassID
420 (uint32_t(AArch64::FPRRegBankID) << 20) | // ZPRMul2_and_ZPR_KRegClassID
421 (uint32_t(AArch64::FPRRegBankID) << 22) | // ZPRMul4_and_ZPR_3bRegClassID
422 (uint32_t(AArch64::FPRRegBankID) << 24) | // ZPRMul4_and_ZPR_KRegClassID
423 (uint32_t(AArch64::FPRRegBankID) << 26) | // DDDRegClassID
424 (uint32_t(AArch64::FPRRegBankID) << 28) | // DDD_with_dsub0_in_FPR64_loRegClassID
425 (uint32_t(AArch64::FPRRegBankID) << 30), // DDD_with_dsub1_in_FPR64_loRegClassID
426 (uint32_t(AArch64::FPRRegBankID) << 0) | // DDD_with_dsub2_in_FPR64_loRegClassID
427 (uint32_t(AArch64::FPRRegBankID) << 2) | // DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub1_in_FPR64_loRegClassID
428 (uint32_t(AArch64::FPRRegBankID) << 4) | // DDD_with_dsub1_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_loRegClassID
429 (uint32_t(AArch64::FPRRegBankID) << 6) | // DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_loRegClassID
430 (uint32_t(AArch64::FPRRegBankID) << 8) | // DDDDRegClassID
431 (uint32_t(AArch64::FPRRegBankID) << 10) | // DDDD_with_dsub0_in_FPR64_loRegClassID
432 (uint32_t(AArch64::FPRRegBankID) << 12) | // DDDD_with_dsub1_in_FPR64_loRegClassID
433 (uint32_t(AArch64::FPRRegBankID) << 14) | // DDDD_with_dsub2_in_FPR64_loRegClassID
434 (uint32_t(AArch64::FPRRegBankID) << 16) | // DDDD_with_dsub3_in_FPR64_loRegClassID
435 (uint32_t(AArch64::FPRRegBankID) << 18) | // DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub1_in_FPR64_loRegClassID
436 (uint32_t(AArch64::FPRRegBankID) << 20) | // DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_loRegClassID
437 (uint32_t(AArch64::FPRRegBankID) << 22) | // DDDD_with_dsub2_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_loRegClassID
438 (uint32_t(AArch64::FPRRegBankID) << 24) | // DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_loRegClassID
439 (uint32_t(AArch64::FPRRegBankID) << 26) | // DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_loRegClassID
440 (uint32_t(AArch64::FPRRegBankID) << 28) | // DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_loRegClassID
441 (uint32_t(AArch64::FPRRegBankID) << 30), // QQRegClassID
442 (uint32_t(InvalidRegBankID) << 0) |
443 (uint32_t(InvalidRegBankID) << 2) |
444 (uint32_t(InvalidRegBankID) << 4) |
445 (uint32_t(AArch64::FPRRegBankID) << 6) | // QQ_with_dsub1_in_FPR64_loRegClassID
446 (uint32_t(AArch64::FPRRegBankID) << 8) | // QQ_with_qsub0_in_FPR128_loRegClassID
447 (uint32_t(InvalidRegBankID) << 10) |
448 (uint32_t(InvalidRegBankID) << 12) |
449 (uint32_t(InvalidRegBankID) << 14) |
450 (uint32_t(InvalidRegBankID) << 16) |
451 (uint32_t(InvalidRegBankID) << 18) |
452 (uint32_t(InvalidRegBankID) << 20) |
453 (uint32_t(AArch64::FPRRegBankID) << 22) | // QQ_with_qsub0_in_FPR128_lo_and_QQ_with_dsub1_in_FPR64_loRegClassID
454 (uint32_t(InvalidRegBankID) << 24) |
455 (uint32_t(InvalidRegBankID) << 26) |
456 (uint32_t(InvalidRegBankID) << 28) |
457 (uint32_t(InvalidRegBankID) << 30),
458 (uint32_t(InvalidRegBankID) << 0) |
459 (uint32_t(AArch64::FPRRegBankID) << 2) | // QQ_with_qsub0_in_FPR128_0to7RegClassID
460 (uint32_t(AArch64::FPRRegBankID) << 4) | // QQ_with_qsub1_in_FPR128_0to7RegClassID
461 (uint32_t(InvalidRegBankID) << 6) |
462 (uint32_t(InvalidRegBankID) << 8) |
463 (uint32_t(InvalidRegBankID) << 10) |
464 (uint32_t(InvalidRegBankID) << 12) |
465 (uint32_t(InvalidRegBankID) << 14) |
466 (uint32_t(InvalidRegBankID) << 16) |
467 (uint32_t(InvalidRegBankID) << 18) |
468 (uint32_t(InvalidRegBankID) << 20) |
469 (uint32_t(InvalidRegBankID) << 22) |
470 (uint32_t(InvalidRegBankID) << 24) |
471 (uint32_t(InvalidRegBankID) << 26) |
472 (uint32_t(InvalidRegBankID) << 28) |
473 (uint32_t(InvalidRegBankID) << 30),
474 (uint32_t(InvalidRegBankID) << 0) |
475 (uint32_t(InvalidRegBankID) << 2) |
476 (uint32_t(AArch64::FPRRegBankID) << 4) | // QQ_with_qsub0_in_FPR128_0to7_and_QQ_with_qsub1_in_FPR128_0to7RegClassID
477 (uint32_t(InvalidRegBankID) << 6) |
478 (uint32_t(InvalidRegBankID) << 8) |
479 (uint32_t(InvalidRegBankID) << 10) |
480 (uint32_t(InvalidRegBankID) << 12) |
481 (uint32_t(InvalidRegBankID) << 14) |
482 (uint32_t(InvalidRegBankID) << 16) |
483 (uint32_t(InvalidRegBankID) << 18) |
484 (uint32_t(InvalidRegBankID) << 20) |
485 (uint32_t(InvalidRegBankID) << 22) |
486 (uint32_t(InvalidRegBankID) << 24) |
487 (uint32_t(InvalidRegBankID) << 26) |
488 (uint32_t(InvalidRegBankID) << 28) |
489 (uint32_t(InvalidRegBankID) << 30),
490 (uint32_t(InvalidRegBankID) << 0) |
491 (uint32_t(InvalidRegBankID) << 2) |
492 (uint32_t(InvalidRegBankID) << 4) |
493 (uint32_t(InvalidRegBankID) << 6) |
494 (uint32_t(InvalidRegBankID) << 8) |
495 (uint32_t(InvalidRegBankID) << 10) |
496 (uint32_t(InvalidRegBankID) << 12) |
497 (uint32_t(InvalidRegBankID) << 14) |
498 (uint32_t(InvalidRegBankID) << 16) |
499 (uint32_t(InvalidRegBankID) << 18) |
500 (uint32_t(InvalidRegBankID) << 20) |
501 (uint32_t(InvalidRegBankID) << 22) |
502 (uint32_t(InvalidRegBankID) << 24) |
503 (uint32_t(InvalidRegBankID) << 26) |
504 (uint32_t(InvalidRegBankID) << 28) |
505 (uint32_t(InvalidRegBankID) << 30),
506 (uint32_t(InvalidRegBankID) << 0) |
507 (uint32_t(InvalidRegBankID) << 2) |
508 (uint32_t(InvalidRegBankID) << 4) |
509 (uint32_t(InvalidRegBankID) << 6) |
510 (uint32_t(InvalidRegBankID) << 8) |
511 (uint32_t(InvalidRegBankID) << 10) |
512 (uint32_t(InvalidRegBankID) << 12) |
513 (uint32_t(InvalidRegBankID) << 14) |
514 (uint32_t(InvalidRegBankID) << 16) |
515 (uint32_t(InvalidRegBankID) << 18) |
516 (uint32_t(InvalidRegBankID) << 20) |
517 (uint32_t(InvalidRegBankID) << 22) |
518 (uint32_t(InvalidRegBankID) << 24) |
519 (uint32_t(AArch64::FPRRegBankID) << 26) | // QQQRegClassID
520 (uint32_t(InvalidRegBankID) << 28) |
521 (uint32_t(AArch64::FPRRegBankID) << 30), // QQQ_with_dsub1_in_FPR64_loRegClassID
522 (uint32_t(AArch64::FPRRegBankID) << 0) | // QQQ_with_dsub2_in_FPR64_loRegClassID
523 (uint32_t(AArch64::FPRRegBankID) << 2) | // QQQ_with_qsub0_in_FPR128_loRegClassID
524 (uint32_t(InvalidRegBankID) << 4) |
525 (uint32_t(InvalidRegBankID) << 6) |
526 (uint32_t(InvalidRegBankID) << 8) |
527 (uint32_t(InvalidRegBankID) << 10) |
528 (uint32_t(InvalidRegBankID) << 12) |
529 (uint32_t(AArch64::FPRRegBankID) << 14) | // QQQ_with_dsub1_in_FPR64_lo_and_QQQ_with_dsub2_in_FPR64_loRegClassID
530 (uint32_t(AArch64::FPRRegBankID) << 16) | // QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_dsub1_in_FPR64_loRegClassID
531 (uint32_t(InvalidRegBankID) << 18) |
532 (uint32_t(InvalidRegBankID) << 20) |
533 (uint32_t(AArch64::FPRRegBankID) << 22) | // QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_dsub2_in_FPR64_loRegClassID
534 (uint32_t(InvalidRegBankID) << 24) |
535 (uint32_t(AArch64::FPRRegBankID) << 26) | // QQQ_with_qsub0_in_FPR128_0to7RegClassID
536 (uint32_t(AArch64::FPRRegBankID) << 28) | // QQQ_with_qsub1_in_FPR128_0to7RegClassID
537 (uint32_t(AArch64::FPRRegBankID) << 30), // QQQ_with_qsub2_in_FPR128_0to7RegClassID
538 (uint32_t(InvalidRegBankID) << 0) |
539 (uint32_t(InvalidRegBankID) << 2) |
540 (uint32_t(InvalidRegBankID) << 4) |
541 (uint32_t(InvalidRegBankID) << 6) |
542 (uint32_t(InvalidRegBankID) << 8) |
543 (uint32_t(InvalidRegBankID) << 10) |
544 (uint32_t(InvalidRegBankID) << 12) |
545 (uint32_t(InvalidRegBankID) << 14) |
546 (uint32_t(InvalidRegBankID) << 16) |
547 (uint32_t(InvalidRegBankID) << 18) |
548 (uint32_t(InvalidRegBankID) << 20) |
549 (uint32_t(InvalidRegBankID) << 22) |
550 (uint32_t(InvalidRegBankID) << 24) |
551 (uint32_t(InvalidRegBankID) << 26) |
552 (uint32_t(InvalidRegBankID) << 28) |
553 (uint32_t(InvalidRegBankID) << 30),
554 (uint32_t(AArch64::FPRRegBankID) << 0) | // QQQ_with_dsub1_in_FPR64_lo_and_QQQ_with_qsub2_in_FPR128_0to7RegClassID
555 (uint32_t(AArch64::FPRRegBankID) << 2) | // QQQ_with_qsub0_in_FPR128_0to7_and_QQQ_with_qsub1_in_FPR128_0to7RegClassID
556 (uint32_t(InvalidRegBankID) << 4) |
557 (uint32_t(InvalidRegBankID) << 6) |
558 (uint32_t(InvalidRegBankID) << 8) |
559 (uint32_t(InvalidRegBankID) << 10) |
560 (uint32_t(InvalidRegBankID) << 12) |
561 (uint32_t(AArch64::FPRRegBankID) << 14) | // QQQ_with_qsub0_in_FPR128_0to7_and_QQQ_with_qsub2_in_FPR128_0to7RegClassID
562 (uint32_t(InvalidRegBankID) << 16) |
563 (uint32_t(InvalidRegBankID) << 18) |
564 (uint32_t(InvalidRegBankID) << 20) |
565 (uint32_t(InvalidRegBankID) << 22) |
566 (uint32_t(InvalidRegBankID) << 24) |
567 (uint32_t(InvalidRegBankID) << 26) |
568 (uint32_t(InvalidRegBankID) << 28) |
569 (uint32_t(InvalidRegBankID) << 30),
570 (uint32_t(InvalidRegBankID) << 0) |
571 (uint32_t(InvalidRegBankID) << 2) |
572 (uint32_t(InvalidRegBankID) << 4) |
573 (uint32_t(InvalidRegBankID) << 6) |
574 (uint32_t(InvalidRegBankID) << 8) |
575 (uint32_t(InvalidRegBankID) << 10) |
576 (uint32_t(InvalidRegBankID) << 12) |
577 (uint32_t(InvalidRegBankID) << 14) |
578 (uint32_t(InvalidRegBankID) << 16) |
579 (uint32_t(InvalidRegBankID) << 18) |
580 (uint32_t(InvalidRegBankID) << 20) |
581 (uint32_t(InvalidRegBankID) << 22) |
582 (uint32_t(InvalidRegBankID) << 24) |
583 (uint32_t(InvalidRegBankID) << 26) |
584 (uint32_t(InvalidRegBankID) << 28) |
585 (uint32_t(InvalidRegBankID) << 30),
586 (uint32_t(InvalidRegBankID) << 0) |
587 (uint32_t(InvalidRegBankID) << 2) |
588 (uint32_t(InvalidRegBankID) << 4) |
589 (uint32_t(InvalidRegBankID) << 6) |
590 (uint32_t(InvalidRegBankID) << 8) |
591 (uint32_t(InvalidRegBankID) << 10) |
592 (uint32_t(InvalidRegBankID) << 12) |
593 (uint32_t(InvalidRegBankID) << 14) |
594 (uint32_t(InvalidRegBankID) << 16) |
595 (uint32_t(InvalidRegBankID) << 18) |
596 (uint32_t(InvalidRegBankID) << 20) |
597 (uint32_t(InvalidRegBankID) << 22) |
598 (uint32_t(InvalidRegBankID) << 24) |
599 (uint32_t(InvalidRegBankID) << 26) |
600 (uint32_t(InvalidRegBankID) << 28) |
601 (uint32_t(InvalidRegBankID) << 30),
602 (uint32_t(InvalidRegBankID) << 0) |
603 (uint32_t(InvalidRegBankID) << 2) |
604 (uint32_t(InvalidRegBankID) << 4) |
605 (uint32_t(InvalidRegBankID) << 6) |
606 (uint32_t(InvalidRegBankID) << 8) |
607 (uint32_t(InvalidRegBankID) << 10) |
608 (uint32_t(InvalidRegBankID) << 12) |
609 (uint32_t(InvalidRegBankID) << 14) |
610 (uint32_t(AArch64::FPRRegBankID) << 16) | // QQQQRegClassID
611 (uint32_t(InvalidRegBankID) << 18) |
612 (uint32_t(AArch64::FPRRegBankID) << 20) | // QQQQ_with_dsub1_in_FPR64_loRegClassID
613 (uint32_t(AArch64::FPRRegBankID) << 22) | // QQQQ_with_dsub2_in_FPR64_loRegClassID
614 (uint32_t(AArch64::FPRRegBankID) << 24) | // QQQQ_with_dsub3_in_FPR64_loRegClassID
615 (uint32_t(AArch64::FPRRegBankID) << 26) | // QQQQ_with_qsub0_in_FPR128_loRegClassID
616 (uint32_t(InvalidRegBankID) << 28) |
617 (uint32_t(InvalidRegBankID) << 30),
618 (uint32_t(InvalidRegBankID) << 0) |
619 (uint32_t(InvalidRegBankID) << 2) |
620 (uint32_t(InvalidRegBankID) << 4) |
621 (uint32_t(InvalidRegBankID) << 6) |
622 (uint32_t(InvalidRegBankID) << 8) |
623 (uint32_t(AArch64::FPRRegBankID) << 10) | // QQQQ_with_dsub1_in_FPR64_lo_and_QQQQ_with_dsub2_in_FPR64_loRegClassID
624 (uint32_t(AArch64::FPRRegBankID) << 12) | // QQQQ_with_dsub2_in_FPR64_lo_and_QQQQ_with_dsub3_in_FPR64_loRegClassID
625 (uint32_t(AArch64::FPRRegBankID) << 14) | // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_dsub1_in_FPR64_loRegClassID
626 (uint32_t(InvalidRegBankID) << 16) |
627 (uint32_t(InvalidRegBankID) << 18) |
628 (uint32_t(InvalidRegBankID) << 20) |
629 (uint32_t(AArch64::FPRRegBankID) << 22) | // QQQQ_with_dsub1_in_FPR64_lo_and_QQQQ_with_dsub3_in_FPR64_loRegClassID
630 (uint32_t(AArch64::FPRRegBankID) << 24) | // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_dsub2_in_FPR64_loRegClassID
631 (uint32_t(InvalidRegBankID) << 26) |
632 (uint32_t(InvalidRegBankID) << 28) |
633 (uint32_t(AArch64::FPRRegBankID) << 30), // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_dsub3_in_FPR64_loRegClassID
634 (uint32_t(InvalidRegBankID) << 0) |
635 (uint32_t(InvalidRegBankID) << 2) |
636 (uint32_t(InvalidRegBankID) << 4) |
637 (uint32_t(AArch64::FPRRegBankID) << 6) | // QQQQ_with_qsub0_in_FPR128_0to7RegClassID
638 (uint32_t(AArch64::FPRRegBankID) << 8) | // QQQQ_with_qsub1_in_FPR128_0to7RegClassID
639 (uint32_t(AArch64::FPRRegBankID) << 10) | // QQQQ_with_qsub2_in_FPR128_0to7RegClassID
640 (uint32_t(AArch64::FPRRegBankID) << 12) | // QQQQ_with_qsub3_in_FPR128_0to7RegClassID
641 (uint32_t(InvalidRegBankID) << 14) |
642 (uint32_t(InvalidRegBankID) << 16) |
643 (uint32_t(InvalidRegBankID) << 18) |
644 (uint32_t(InvalidRegBankID) << 20) |
645 (uint32_t(InvalidRegBankID) << 22) |
646 (uint32_t(InvalidRegBankID) << 24) |
647 (uint32_t(InvalidRegBankID) << 26) |
648 (uint32_t(InvalidRegBankID) << 28) |
649 (uint32_t(InvalidRegBankID) << 30),
650 (uint32_t(InvalidRegBankID) << 0) |
651 (uint32_t(InvalidRegBankID) << 2) |
652 (uint32_t(InvalidRegBankID) << 4) |
653 (uint32_t(InvalidRegBankID) << 6) |
654 (uint32_t(InvalidRegBankID) << 8) |
655 (uint32_t(InvalidRegBankID) << 10) |
656 (uint32_t(InvalidRegBankID) << 12) |
657 (uint32_t(InvalidRegBankID) << 14) |
658 (uint32_t(InvalidRegBankID) << 16) |
659 (uint32_t(InvalidRegBankID) << 18) |
660 (uint32_t(InvalidRegBankID) << 20) |
661 (uint32_t(InvalidRegBankID) << 22) |
662 (uint32_t(InvalidRegBankID) << 24) |
663 (uint32_t(InvalidRegBankID) << 26) |
664 (uint32_t(AArch64::FPRRegBankID) << 28) | // QQQQ_with_dsub1_in_FPR64_lo_and_QQQQ_with_qsub2_in_FPR128_0to7RegClassID
665 (uint32_t(AArch64::FPRRegBankID) << 30), // QQQQ_with_dsub2_in_FPR64_lo_and_QQQQ_with_qsub3_in_FPR128_0to7RegClassID
666 (uint32_t(AArch64::FPRRegBankID) << 0) | // QQQQ_with_qsub0_in_FPR128_0to7_and_QQQQ_with_qsub1_in_FPR128_0to7RegClassID
667 (uint32_t(InvalidRegBankID) << 2) |
668 (uint32_t(InvalidRegBankID) << 4) |
669 (uint32_t(InvalidRegBankID) << 6) |
670 (uint32_t(InvalidRegBankID) << 8) |
671 (uint32_t(InvalidRegBankID) << 10) |
672 (uint32_t(InvalidRegBankID) << 12) |
673 (uint32_t(InvalidRegBankID) << 14) |
674 (uint32_t(InvalidRegBankID) << 16) |
675 (uint32_t(AArch64::FPRRegBankID) << 18) | // QQQQ_with_dsub1_in_FPR64_lo_and_QQQQ_with_qsub3_in_FPR128_0to7RegClassID
676 (uint32_t(AArch64::FPRRegBankID) << 20) | // QQQQ_with_qsub0_in_FPR128_0to7_and_QQQQ_with_qsub2_in_FPR128_0to7RegClassID
677 (uint32_t(InvalidRegBankID) << 22) |
678 (uint32_t(InvalidRegBankID) << 24) |
679 (uint32_t(InvalidRegBankID) << 26) |
680 (uint32_t(InvalidRegBankID) << 28) |
681 (uint32_t(InvalidRegBankID) << 30),
682 (uint32_t(InvalidRegBankID) << 0) |
683 (uint32_t(InvalidRegBankID) << 2) |
684 (uint32_t(InvalidRegBankID) << 4) |
685 (uint32_t(InvalidRegBankID) << 6) |
686 (uint32_t(InvalidRegBankID) << 8) |
687 (uint32_t(AArch64::FPRRegBankID) << 10) // QQQQ_with_qsub0_in_FPR128_0to7_and_QQQQ_with_qsub3_in_FPR128_0to7RegClassID
688 };
689 const unsigned RegClassID = RC.getID();
690 if (LLVM_LIKELY(RegClassID < 374)) {
691 unsigned RegBankID = (RegClass2RegBank[RegClassID / 16] >> ((RegClassID % 16) * 2)) & 3;
692 if (RegBankID != InvalidRegBankID)
693 return getRegBank(RegBankID);
694 }
695 llvm_unreachable(llvm::Twine("Target needs to handle register class ID 0x").concat(llvm::Twine::utohexstr(RegClassID)).str().c_str());
696}
697} // end namespace llvm
698#endif // GET_TARGET_REGBANK_IMPL
699