1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target SDNode descriptions *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* From: AArch64.td *|
7|* *|
8\*===----------------------------------------------------------------------===*/
9
10#ifdef GET_SDNODE_ENUM
11#undef GET_SDNODE_ENUM
12
13namespace llvm::AArch64ISD {
14
15enum GenNodeType : unsigned {
16 ABDS_PRED = ISD::BUILTIN_OP_END,
17 ABDU_PRED,
18 ABS_MERGE_PASSTHRU,
19 ADC,
20 ADCS,
21 ADDP,
22 ADDS,
23 ADDlow,
24 ADR,
25 ADRP,
26 ALLOCATE_ZA_BUFFER,
27 ALLOC_SME_SAVE_BUFFER,
28 ANDS,
29 ANDV_PRED,
30 ASSERT_ZEXT_BOOL,
31 AUTH_CALL,
32 AUTH_CALL_RVMARKER,
33 AUTH_TC_RETURN,
34 BIC,
35 BICi,
36 BITREVERSE_MERGE_PASSTHRU,
37 BRCOND,
38 BSP,
39 BSWAP_MERGE_PASSTHRU,
40 CALL,
41 CALL_ARM64EC_TO_X64,
42 CALL_BTI,
43 CALL_RVMARKER,
44 CB,
45 CBNZ,
46 CBZ,
47 CCMN,
48 CCMP,
49 CLASTA_N,
50 CLASTB_N,
51 COALESCER_BARRIER,
52 COND_SMSTART,
53 COND_SMSTOP,
54 CSEL,
55 CSINC,
56 CSINV,
57 CSNEG,
58 CTLZ_MERGE_PASSTHRU,
59 CTPOP_MERGE_PASSTHRU,
60 CTTZ_ELTS,
61 DUP,
62 DUPLANE128,
63 DUPLANE16,
64 DUPLANE32,
65 DUPLANE64,
66 DUPLANE8,
67 DUP_MERGE_PASSTHRU,
68 EORV_PRED,
69 EXT,
70 EXTR,
71 FABS_MERGE_PASSTHRU,
72 FADDA_PRED,
73 FADDV_PRED,
74 FADD_PRED,
75 FCCMP,
76 FCEIL_MERGE_PASSTHRU,
77 FCMEQ,
78 FCMGE,
79 FCMGT,
80 FCMP,
81 FCVTXN,
82 FCVTX_MERGE_PASSTHRU,
83 FCVTZS_MERGE_PASSTHRU,
84 FCVTZU_MERGE_PASSTHRU,
85 FDIV_PRED,
86 FFLOOR_MERGE_PASSTHRU,
87 FMAXNMV_PRED,
88 FMAXNM_PRED,
89 FMAXV_PRED,
90 FMAX_PRED,
91 FMA_PRED,
92 FMINNMV_PRED,
93 FMINNM_PRED,
94 FMINV_PRED,
95 FMIN_PRED,
96 FMOV,
97 FMUL_PRED,
98 FNEARBYINT_MERGE_PASSTHRU,
99 FNEG_MERGE_PASSTHRU,
100 FP_EXTEND_MERGE_PASSTHRU,
101 FP_ROUND_MERGE_PASSTHRU,
102 FRECPE,
103 FRECPS,
104 FRECPX_MERGE_PASSTHRU,
105 FRINT_MERGE_PASSTHRU,
106 FROUNDEVEN_MERGE_PASSTHRU,
107 FROUND_MERGE_PASSTHRU,
108 FRSQRTE,
109 FRSQRTS,
110 FSQRT_MERGE_PASSTHRU,
111 FSUB_PRED,
112 FTRUNC_MERGE_PASSTHRU,
113 GET_SME_SAVE_SIZE,
114 GLD1Q_INDEX_MERGE_ZERO,
115 GLD1Q_MERGE_ZERO,
116 GLD1S_IMM_MERGE_ZERO,
117 GLD1S_MERGE_ZERO,
118 GLD1S_SCALED_MERGE_ZERO,
119 GLD1S_SXTW_MERGE_ZERO,
120 GLD1S_SXTW_SCALED_MERGE_ZERO,
121 GLD1S_UXTW_MERGE_ZERO,
122 GLD1S_UXTW_SCALED_MERGE_ZERO,
123 GLD1_IMM_MERGE_ZERO,
124 GLD1_MERGE_ZERO,
125 GLD1_SCALED_MERGE_ZERO,
126 GLD1_SXTW_MERGE_ZERO,
127 GLD1_SXTW_SCALED_MERGE_ZERO,
128 GLD1_UXTW_MERGE_ZERO,
129 GLD1_UXTW_SCALED_MERGE_ZERO,
130 GLDFF1S_IMM_MERGE_ZERO,
131 GLDFF1S_MERGE_ZERO,
132 GLDFF1S_SCALED_MERGE_ZERO,
133 GLDFF1S_SXTW_MERGE_ZERO,
134 GLDFF1S_SXTW_SCALED_MERGE_ZERO,
135 GLDFF1S_UXTW_MERGE_ZERO,
136 GLDFF1S_UXTW_SCALED_MERGE_ZERO,
137 GLDFF1_IMM_MERGE_ZERO,
138 GLDFF1_MERGE_ZERO,
139 GLDFF1_SCALED_MERGE_ZERO,
140 GLDFF1_SXTW_MERGE_ZERO,
141 GLDFF1_SXTW_SCALED_MERGE_ZERO,
142 GLDFF1_UXTW_MERGE_ZERO,
143 GLDFF1_UXTW_SCALED_MERGE_ZERO,
144 GLDNT1S_MERGE_ZERO,
145 GLDNT1_INDEX_MERGE_ZERO,
146 GLDNT1_MERGE_ZERO,
147 HADDS_PRED,
148 HADDU_PRED,
149 INIT_TPIDR2OBJ,
150 INSR,
151 LASTA,
152 LASTB,
153 LD1DUPpost,
154 LD1LANEpost,
155 LD1RO_MERGE_ZERO,
156 LD1RQ_MERGE_ZERO,
157 LD1S_MERGE_ZERO,
158 LD1_MERGE_ZERO,
159 LD1x2post,
160 LD1x3post,
161 LD1x4post,
162 LD2DUPpost,
163 LD2LANEpost,
164 LD2post,
165 LD3DUPpost,
166 LD3LANEpost,
167 LD3post,
168 LD4DUPpost,
169 LD4LANEpost,
170 LD4post,
171 LDFF1S_MERGE_ZERO,
172 LDFF1_MERGE_ZERO,
173 LDIAPP,
174 LDNF1S_MERGE_ZERO,
175 LDNF1_MERGE_ZERO,
176 LDNP,
177 LDP,
178 LOADgot,
179 LS64_BUILD,
180 LS64_EXTRACT,
181 MOVI,
182 MOVIedit,
183 MOVImsl,
184 MOVIshift,
185 MRRS,
186 MRS,
187 MSRR,
188 MULHS_PRED,
189 MULHU_PRED,
190 MUL_PRED,
191 MVNImsl,
192 MVNIshift,
193 NEG_MERGE_PASSTHRU,
194 NVCAST,
195 ORRi,
196 ORV_PRED,
197 PMULL,
198 PREFETCH,
199 PROBED_ALLOCA,
200 PTEST,
201 PTEST_ANY,
202 PTRUE,
203 RDSVL,
204 REINTERPRET_CAST,
205 RESTORE_ZA,
206 RESTORE_ZT,
207 RET_GLUE,
208 REV16,
209 REV32,
210 REV64,
211 REVD_MERGE_PASSTHRU,
212 REVH_MERGE_PASSTHRU,
213 REVW_MERGE_PASSTHRU,
214 RHADDS_PRED,
215 RHADDU_PRED,
216 RSHRNB_I,
217 SADDLP,
218 SADDLV,
219 SADDV,
220 SADDV_PRED,
221 SADDWB,
222 SADDWT,
223 SAVE_ZT,
224 SBC,
225 SBCS,
226 SDIV_PRED,
227 SDOT,
228 SETCC_MERGE_ZERO,
229 SHL_PRED,
230 SIGN_EXTEND_INREG_MERGE_PASSTHRU,
231 SINT_TO_FP_MERGE_PASSTHRU,
232 SITOF,
233 SMAXV,
234 SMAXV_PRED,
235 SMAX_PRED,
236 SME_ZA_LDR,
237 SME_ZA_STR,
238 SMINV,
239 SMINV_PRED,
240 SMIN_PRED,
241 SMSTART,
242 SMSTOP,
243 SMULL,
244 SPLICE,
245 SQSHLU_I,
246 SQSHL_I,
247 SRAD_MERGE_OP1,
248 SRA_PRED,
249 SRL_PRED,
250 SRSHR_I,
251 SST1Q_INDEX_PRED,
252 SST1Q_PRED,
253 SST1_IMM_PRED,
254 SST1_PRED,
255 SST1_SCALED_PRED,
256 SST1_SXTW_PRED,
257 SST1_SXTW_SCALED_PRED,
258 SST1_UXTW_PRED,
259 SST1_UXTW_SCALED_PRED,
260 SSTNT1_INDEX_PRED,
261 SSTNT1_PRED,
262 ST1_PRED,
263 ST1x2post,
264 ST1x3post,
265 ST1x4post,
266 ST2G,
267 ST2LANEpost,
268 ST2post,
269 ST3LANEpost,
270 ST3post,
271 ST4LANEpost,
272 ST4post,
273 STG,
274 STILP,
275 STNP,
276 STP,
277 STRICT_FCMP,
278 STRICT_FCMPE,
279 STZ2G,
280 STZG,
281 SUBS,
282 SUNPKHI,
283 SUNPKLO,
284 TBL,
285 TBNZ,
286 TBZ,
287 TC_RETURN,
288 THREAD_POINTER,
289 TLSDESC_AUTH_CALLSEQ,
290 TLSDESC_CALLSEQ,
291 TRN1,
292 TRN2,
293 UADDLP,
294 UADDLV,
295 UADDV,
296 UADDV_PRED,
297 UADDWB,
298 UADDWT,
299 UDIV_PRED,
300 UDOT,
301 UINT_TO_FP_MERGE_PASSTHRU,
302 UITOF,
303 UMAXV,
304 UMAXV_PRED,
305 UMAX_PRED,
306 UMINV,
307 UMINV_PRED,
308 UMIN_PRED,
309 UMULL,
310 UQSHL_I,
311 URSHR_I,
312 URSHR_I_PRED,
313 USDOT,
314 UUNPKHI,
315 UUNPKLO,
316 UZP1,
317 UZP2,
318 VASHR,
319 VG_RESTORE,
320 VG_SAVE,
321 VLSHR,
322 VSHL,
323 VSLI,
324 VSRI,
325 WrapperLarge,
326 ZERO_EXTEND_INREG_MERGE_PASSTHRU,
327 ZIP1,
328 ZIP2,
329};
330
331static constexpr unsigned GENERATED_OPCODE_END = ZIP2 + 1;
332
333} // namespace llvm::AArch64ISD
334
335#endif // GET_SDNODE_ENUM
336
337#ifdef GET_SDNODE_DESC
338#undef GET_SDNODE_DESC
339
340namespace llvm {
341
342#ifdef __GNUC__
343#pragma GCC diagnostic push
344#pragma GCC diagnostic ignored "-Woverlength-strings"
345#endif
346static constexpr char AArch64SDNodeNamesStorage[] =
347 "\0"
348 "AArch64ISD::ABDS_PRED\0"
349 "AArch64ISD::ABDU_PRED\0"
350 "AArch64ISD::ABS_MERGE_PASSTHRU\0"
351 "AArch64ISD::ADC\0"
352 "AArch64ISD::ADCS\0"
353 "AArch64ISD::ADDP\0"
354 "AArch64ISD::ADDS\0"
355 "AArch64ISD::ADDlow\0"
356 "AArch64ISD::ADR\0"
357 "AArch64ISD::ADRP\0"
358 "AArch64ISD::ALLOCATE_ZA_BUFFER\0"
359 "AArch64ISD::ALLOC_SME_SAVE_BUFFER\0"
360 "AArch64ISD::ANDS\0"
361 "AArch64ISD::ANDV_PRED\0"
362 "AArch64ISD::ASSERT_ZEXT_BOOL\0"
363 "AArch64ISD::AUTH_CALL\0"
364 "AArch64ISD::AUTH_CALL_RVMARKER\0"
365 "AArch64ISD::AUTH_TC_RETURN\0"
366 "AArch64ISD::BIC\0"
367 "AArch64ISD::BICi\0"
368 "AArch64ISD::BITREVERSE_MERGE_PASSTHRU\0"
369 "AArch64ISD::BRCOND\0"
370 "AArch64ISD::BSP\0"
371 "AArch64ISD::BSWAP_MERGE_PASSTHRU\0"
372 "AArch64ISD::CALL\0"
373 "AArch64ISD::CALL_ARM64EC_TO_X64\0"
374 "AArch64ISD::CALL_BTI\0"
375 "AArch64ISD::CALL_RVMARKER\0"
376 "AArch64ISD::CB\0"
377 "AArch64ISD::CBNZ\0"
378 "AArch64ISD::CBZ\0"
379 "AArch64ISD::CCMN\0"
380 "AArch64ISD::CCMP\0"
381 "AArch64ISD::CLASTA_N\0"
382 "AArch64ISD::CLASTB_N\0"
383 "AArch64ISD::COALESCER_BARRIER\0"
384 "AArch64ISD::COND_SMSTART\0"
385 "AArch64ISD::COND_SMSTOP\0"
386 "AArch64ISD::CSEL\0"
387 "AArch64ISD::CSINC\0"
388 "AArch64ISD::CSINV\0"
389 "AArch64ISD::CSNEG\0"
390 "AArch64ISD::CTLZ_MERGE_PASSTHRU\0"
391 "AArch64ISD::CTPOP_MERGE_PASSTHRU\0"
392 "AArch64ISD::CTTZ_ELTS\0"
393 "AArch64ISD::DUP\0"
394 "AArch64ISD::DUPLANE128\0"
395 "AArch64ISD::DUPLANE16\0"
396 "AArch64ISD::DUPLANE32\0"
397 "AArch64ISD::DUPLANE64\0"
398 "AArch64ISD::DUPLANE8\0"
399 "AArch64ISD::DUP_MERGE_PASSTHRU\0"
400 "AArch64ISD::EORV_PRED\0"
401 "AArch64ISD::EXT\0"
402 "AArch64ISD::EXTR\0"
403 "AArch64ISD::FABS_MERGE_PASSTHRU\0"
404 "AArch64ISD::FADDA_PRED\0"
405 "AArch64ISD::FADDV_PRED\0"
406 "AArch64ISD::FADD_PRED\0"
407 "AArch64ISD::FCCMP\0"
408 "AArch64ISD::FCEIL_MERGE_PASSTHRU\0"
409 "AArch64ISD::FCMEQ\0"
410 "AArch64ISD::FCMGE\0"
411 "AArch64ISD::FCMGT\0"
412 "AArch64ISD::FCMP\0"
413 "AArch64ISD::FCVTXN\0"
414 "AArch64ISD::FCVTX_MERGE_PASSTHRU\0"
415 "AArch64ISD::FCVTZS_MERGE_PASSTHRU\0"
416 "AArch64ISD::FCVTZU_MERGE_PASSTHRU\0"
417 "AArch64ISD::FDIV_PRED\0"
418 "AArch64ISD::FFLOOR_MERGE_PASSTHRU\0"
419 "AArch64ISD::FMAXNMV_PRED\0"
420 "AArch64ISD::FMAXNM_PRED\0"
421 "AArch64ISD::FMAXV_PRED\0"
422 "AArch64ISD::FMAX_PRED\0"
423 "AArch64ISD::FMA_PRED\0"
424 "AArch64ISD::FMINNMV_PRED\0"
425 "AArch64ISD::FMINNM_PRED\0"
426 "AArch64ISD::FMINV_PRED\0"
427 "AArch64ISD::FMIN_PRED\0"
428 "AArch64ISD::FMOV\0"
429 "AArch64ISD::FMUL_PRED\0"
430 "AArch64ISD::FNEARBYINT_MERGE_PASSTHRU\0"
431 "AArch64ISD::FNEG_MERGE_PASSTHRU\0"
432 "AArch64ISD::FP_EXTEND_MERGE_PASSTHRU\0"
433 "AArch64ISD::FP_ROUND_MERGE_PASSTHRU\0"
434 "AArch64ISD::FRECPE\0"
435 "AArch64ISD::FRECPS\0"
436 "AArch64ISD::FRECPX_MERGE_PASSTHRU\0"
437 "AArch64ISD::FRINT_MERGE_PASSTHRU\0"
438 "AArch64ISD::FROUNDEVEN_MERGE_PASSTHRU\0"
439 "AArch64ISD::FROUND_MERGE_PASSTHRU\0"
440 "AArch64ISD::FRSQRTE\0"
441 "AArch64ISD::FRSQRTS\0"
442 "AArch64ISD::FSQRT_MERGE_PASSTHRU\0"
443 "AArch64ISD::FSUB_PRED\0"
444 "AArch64ISD::FTRUNC_MERGE_PASSTHRU\0"
445 "AArch64ISD::GET_SME_SAVE_SIZE\0"
446 "AArch64ISD::GLD1Q_INDEX_MERGE_ZERO\0"
447 "AArch64ISD::GLD1Q_MERGE_ZERO\0"
448 "AArch64ISD::GLD1S_IMM_MERGE_ZERO\0"
449 "AArch64ISD::GLD1S_MERGE_ZERO\0"
450 "AArch64ISD::GLD1S_SCALED_MERGE_ZERO\0"
451 "AArch64ISD::GLD1S_SXTW_MERGE_ZERO\0"
452 "AArch64ISD::GLD1S_SXTW_SCALED_MERGE_ZERO\0"
453 "AArch64ISD::GLD1S_UXTW_MERGE_ZERO\0"
454 "AArch64ISD::GLD1S_UXTW_SCALED_MERGE_ZERO\0"
455 "AArch64ISD::GLD1_IMM_MERGE_ZERO\0"
456 "AArch64ISD::GLD1_MERGE_ZERO\0"
457 "AArch64ISD::GLD1_SCALED_MERGE_ZERO\0"
458 "AArch64ISD::GLD1_SXTW_MERGE_ZERO\0"
459 "AArch64ISD::GLD1_SXTW_SCALED_MERGE_ZERO\0"
460 "AArch64ISD::GLD1_UXTW_MERGE_ZERO\0"
461 "AArch64ISD::GLD1_UXTW_SCALED_MERGE_ZERO\0"
462 "AArch64ISD::GLDFF1S_IMM_MERGE_ZERO\0"
463 "AArch64ISD::GLDFF1S_MERGE_ZERO\0"
464 "AArch64ISD::GLDFF1S_SCALED_MERGE_ZERO\0"
465 "AArch64ISD::GLDFF1S_SXTW_MERGE_ZERO\0"
466 "AArch64ISD::GLDFF1S_SXTW_SCALED_MERGE_ZERO\0"
467 "AArch64ISD::GLDFF1S_UXTW_MERGE_ZERO\0"
468 "AArch64ISD::GLDFF1S_UXTW_SCALED_MERGE_ZERO\0"
469 "AArch64ISD::GLDFF1_IMM_MERGE_ZERO\0"
470 "AArch64ISD::GLDFF1_MERGE_ZERO\0"
471 "AArch64ISD::GLDFF1_SCALED_MERGE_ZERO\0"
472 "AArch64ISD::GLDFF1_SXTW_MERGE_ZERO\0"
473 "AArch64ISD::GLDFF1_SXTW_SCALED_MERGE_ZERO\0"
474 "AArch64ISD::GLDFF1_UXTW_MERGE_ZERO\0"
475 "AArch64ISD::GLDFF1_UXTW_SCALED_MERGE_ZERO\0"
476 "AArch64ISD::GLDNT1S_MERGE_ZERO\0"
477 "AArch64ISD::GLDNT1_INDEX_MERGE_ZERO\0"
478 "AArch64ISD::GLDNT1_MERGE_ZERO\0"
479 "AArch64ISD::HADDS_PRED\0"
480 "AArch64ISD::HADDU_PRED\0"
481 "AArch64ISD::INIT_TPIDR2OBJ\0"
482 "AArch64ISD::INSR\0"
483 "AArch64ISD::LASTA\0"
484 "AArch64ISD::LASTB\0"
485 "AArch64ISD::LD1DUPpost\0"
486 "AArch64ISD::LD1LANEpost\0"
487 "AArch64ISD::LD1RO_MERGE_ZERO\0"
488 "AArch64ISD::LD1RQ_MERGE_ZERO\0"
489 "AArch64ISD::LD1S_MERGE_ZERO\0"
490 "AArch64ISD::LD1_MERGE_ZERO\0"
491 "AArch64ISD::LD1x2post\0"
492 "AArch64ISD::LD1x3post\0"
493 "AArch64ISD::LD1x4post\0"
494 "AArch64ISD::LD2DUPpost\0"
495 "AArch64ISD::LD2LANEpost\0"
496 "AArch64ISD::LD2post\0"
497 "AArch64ISD::LD3DUPpost\0"
498 "AArch64ISD::LD3LANEpost\0"
499 "AArch64ISD::LD3post\0"
500 "AArch64ISD::LD4DUPpost\0"
501 "AArch64ISD::LD4LANEpost\0"
502 "AArch64ISD::LD4post\0"
503 "AArch64ISD::LDFF1S_MERGE_ZERO\0"
504 "AArch64ISD::LDFF1_MERGE_ZERO\0"
505 "AArch64ISD::LDIAPP\0"
506 "AArch64ISD::LDNF1S_MERGE_ZERO\0"
507 "AArch64ISD::LDNF1_MERGE_ZERO\0"
508 "AArch64ISD::LDNP\0"
509 "AArch64ISD::LDP\0"
510 "AArch64ISD::LOADgot\0"
511 "AArch64ISD::LS64_BUILD\0"
512 "AArch64ISD::LS64_EXTRACT\0"
513 "AArch64ISD::MOVI\0"
514 "AArch64ISD::MOVIedit\0"
515 "AArch64ISD::MOVImsl\0"
516 "AArch64ISD::MOVIshift\0"
517 "AArch64ISD::MRRS\0"
518 "AArch64ISD::MRS\0"
519 "AArch64ISD::MSRR\0"
520 "AArch64ISD::MULHS_PRED\0"
521 "AArch64ISD::MULHU_PRED\0"
522 "AArch64ISD::MUL_PRED\0"
523 "AArch64ISD::MVNImsl\0"
524 "AArch64ISD::MVNIshift\0"
525 "AArch64ISD::NEG_MERGE_PASSTHRU\0"
526 "AArch64ISD::NVCAST\0"
527 "AArch64ISD::ORRi\0"
528 "AArch64ISD::ORV_PRED\0"
529 "AArch64ISD::PMULL\0"
530 "AArch64ISD::PREFETCH\0"
531 "AArch64ISD::PROBED_ALLOCA\0"
532 "AArch64ISD::PTEST\0"
533 "AArch64ISD::PTEST_ANY\0"
534 "AArch64ISD::PTRUE\0"
535 "AArch64ISD::RDSVL\0"
536 "AArch64ISD::REINTERPRET_CAST\0"
537 "AArch64ISD::RESTORE_ZA\0"
538 "AArch64ISD::RESTORE_ZT\0"
539 "AArch64ISD::RET_GLUE\0"
540 "AArch64ISD::REV16\0"
541 "AArch64ISD::REV32\0"
542 "AArch64ISD::REV64\0"
543 "AArch64ISD::REVD_MERGE_PASSTHRU\0"
544 "AArch64ISD::REVH_MERGE_PASSTHRU\0"
545 "AArch64ISD::REVW_MERGE_PASSTHRU\0"
546 "AArch64ISD::RHADDS_PRED\0"
547 "AArch64ISD::RHADDU_PRED\0"
548 "AArch64ISD::RSHRNB_I\0"
549 "AArch64ISD::SADDLP\0"
550 "AArch64ISD::SADDLV\0"
551 "AArch64ISD::SADDV\0"
552 "AArch64ISD::SADDV_PRED\0"
553 "AArch64ISD::SADDWB\0"
554 "AArch64ISD::SADDWT\0"
555 "AArch64ISD::SAVE_ZT\0"
556 "AArch64ISD::SBC\0"
557 "AArch64ISD::SBCS\0"
558 "AArch64ISD::SDIV_PRED\0"
559 "AArch64ISD::SDOT\0"
560 "AArch64ISD::SETCC_MERGE_ZERO\0"
561 "AArch64ISD::SHL_PRED\0"
562 "AArch64ISD::SIGN_EXTEND_INREG_MERGE_PASSTHRU\0"
563 "AArch64ISD::SINT_TO_FP_MERGE_PASSTHRU\0"
564 "AArch64ISD::SITOF\0"
565 "AArch64ISD::SMAXV\0"
566 "AArch64ISD::SMAXV_PRED\0"
567 "AArch64ISD::SMAX_PRED\0"
568 "AArch64ISD::SME_ZA_LDR\0"
569 "AArch64ISD::SME_ZA_STR\0"
570 "AArch64ISD::SMINV\0"
571 "AArch64ISD::SMINV_PRED\0"
572 "AArch64ISD::SMIN_PRED\0"
573 "AArch64ISD::SMSTART\0"
574 "AArch64ISD::SMSTOP\0"
575 "AArch64ISD::SMULL\0"
576 "AArch64ISD::SPLICE\0"
577 "AArch64ISD::SQSHLU_I\0"
578 "AArch64ISD::SQSHL_I\0"
579 "AArch64ISD::SRAD_MERGE_OP1\0"
580 "AArch64ISD::SRA_PRED\0"
581 "AArch64ISD::SRL_PRED\0"
582 "AArch64ISD::SRSHR_I\0"
583 "AArch64ISD::SST1Q_INDEX_PRED\0"
584 "AArch64ISD::SST1Q_PRED\0"
585 "AArch64ISD::SST1_IMM_PRED\0"
586 "AArch64ISD::SST1_PRED\0"
587 "AArch64ISD::SST1_SCALED_PRED\0"
588 "AArch64ISD::SST1_SXTW_PRED\0"
589 "AArch64ISD::SST1_SXTW_SCALED_PRED\0"
590 "AArch64ISD::SST1_UXTW_PRED\0"
591 "AArch64ISD::SST1_UXTW_SCALED_PRED\0"
592 "AArch64ISD::SSTNT1_INDEX_PRED\0"
593 "AArch64ISD::SSTNT1_PRED\0"
594 "AArch64ISD::ST1_PRED\0"
595 "AArch64ISD::ST1x2post\0"
596 "AArch64ISD::ST1x3post\0"
597 "AArch64ISD::ST1x4post\0"
598 "AArch64ISD::ST2G\0"
599 "AArch64ISD::ST2LANEpost\0"
600 "AArch64ISD::ST2post\0"
601 "AArch64ISD::ST3LANEpost\0"
602 "AArch64ISD::ST3post\0"
603 "AArch64ISD::ST4LANEpost\0"
604 "AArch64ISD::ST4post\0"
605 "AArch64ISD::STG\0"
606 "AArch64ISD::STILP\0"
607 "AArch64ISD::STNP\0"
608 "AArch64ISD::STP\0"
609 "AArch64ISD::STRICT_FCMP\0"
610 "AArch64ISD::STRICT_FCMPE\0"
611 "AArch64ISD::STZ2G\0"
612 "AArch64ISD::STZG\0"
613 "AArch64ISD::SUBS\0"
614 "AArch64ISD::SUNPKHI\0"
615 "AArch64ISD::SUNPKLO\0"
616 "AArch64ISD::TBL\0"
617 "AArch64ISD::TBNZ\0"
618 "AArch64ISD::TBZ\0"
619 "AArch64ISD::TC_RETURN\0"
620 "AArch64ISD::THREAD_POINTER\0"
621 "AArch64ISD::TLSDESC_AUTH_CALLSEQ\0"
622 "AArch64ISD::TLSDESC_CALLSEQ\0"
623 "AArch64ISD::TRN1\0"
624 "AArch64ISD::TRN2\0"
625 "AArch64ISD::UADDLP\0"
626 "AArch64ISD::UADDLV\0"
627 "AArch64ISD::UADDV\0"
628 "AArch64ISD::UADDV_PRED\0"
629 "AArch64ISD::UADDWB\0"
630 "AArch64ISD::UADDWT\0"
631 "AArch64ISD::UDIV_PRED\0"
632 "AArch64ISD::UDOT\0"
633 "AArch64ISD::UINT_TO_FP_MERGE_PASSTHRU\0"
634 "AArch64ISD::UITOF\0"
635 "AArch64ISD::UMAXV\0"
636 "AArch64ISD::UMAXV_PRED\0"
637 "AArch64ISD::UMAX_PRED\0"
638 "AArch64ISD::UMINV\0"
639 "AArch64ISD::UMINV_PRED\0"
640 "AArch64ISD::UMIN_PRED\0"
641 "AArch64ISD::UMULL\0"
642 "AArch64ISD::UQSHL_I\0"
643 "AArch64ISD::URSHR_I\0"
644 "AArch64ISD::URSHR_I_PRED\0"
645 "AArch64ISD::USDOT\0"
646 "AArch64ISD::UUNPKHI\0"
647 "AArch64ISD::UUNPKLO\0"
648 "AArch64ISD::UZP1\0"
649 "AArch64ISD::UZP2\0"
650 "AArch64ISD::VASHR\0"
651 "AArch64ISD::VG_RESTORE\0"
652 "AArch64ISD::VG_SAVE\0"
653 "AArch64ISD::VLSHR\0"
654 "AArch64ISD::VSHL\0"
655 "AArch64ISD::VSLI\0"
656 "AArch64ISD::VSRI\0"
657 "AArch64ISD::WrapperLarge\0"
658 "AArch64ISD::ZERO_EXTEND_INREG_MERGE_PASSTHRU\0"
659 "AArch64ISD::ZIP1\0"
660 "AArch64ISD::ZIP2\0"
661 ;
662#ifdef __GNUC__
663#pragma GCC diagnostic pop
664#endif
665
666static constexpr llvm::StringTable AArch64SDNodeNames =
667 AArch64SDNodeNamesStorage;
668
669static const SDTypeConstraint AArch64SDTypeConstraints[] = {
670 /* 0 */ {SDTCisVT, 2, 0, MVT::i32}, {SDTCisVT, 1, 0, MVT::i32}, {SDTCisVT, 0, 0, MVT::Other},
671 /* 3 */ {SDTCisPtrTy, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 0, 0, MVT::i32},
672 /* 5 */ {SDTCisVT, 5, 0, MVT::i32}, {SDTCisInt, 4, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 3, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 1, 2, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 0, 0, MVT::i32},
673 /* 11 */ {SDTCisVT, 3, 0, MVT::Other}, {SDTCisInt, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 0, 0, MVT::i32},
674 /* 15 */ {SDTCisVT, 5, 0, MVT::i32}, {SDTCisInt, 4, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 3, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 1, 2, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 0, 0, MVT::i32},
675 /* 21 */ {SDTCisSameAs, 2, 1, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 0, 0, MVT::i32},
676 /* 24 */ {SDTCisSameAs, 2, 1, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 0, 0, MVT::i32},
677 /* 27 */ {SDTCisPtrTy, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 0, 0, MVT::i64},
678 /* 30 */ {SDTCisSameAs, 1, 4, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 1, 3, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 1, 2, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 1, 0, MVT::i32}, {SDTCisVT, 0, 0, MVT::i64},
679 /* 35 */ {SDTCisVT, 2, 0, MVT::i32}, {SDTCisVT, 1, 0, MVT::i32}, {SDTCisVT, 0, 0, MVT::i64},
680 /* 38 */ {SDTCisVT, 1, 0, MVT::i64}, {SDTCisVT, 0, 0, MVT::i64},
681 /* 40 */ {SDTCisPtrTy, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 0, 0, MVT::v4i32},
682 /* 43 */ {SDTCisVT, 3, 0, MVT::i64}, {SDTCisVT, 2, 0, MVT::i64}, {SDTCisVT, 1, 0, MVT::i32}, {SDTCisPtrTy, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
683 /* 47 */ {SDTCisVT, 5, 0, MVT::i64}, {SDTCisVT, 4, 0, MVT::i64}, {SDTCisVT, 3, 0, MVT::i32}, {SDTCisPtrTy, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 1, 0, MVT::i32}, {SDTCisPtrTy, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
684 /* 53 */ {SDTCisPtrTy, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisPtrTy, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
685 /* 55 */ {SDTCisVT, 4, 0, MVT::i64}, {SDTCisVT, 3, 0, MVT::i64}, {SDTCisVT, 2, 0, MVT::i32}, {SDTCisPtrTy, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
686 /* 59 */ {SDTCisVT, 1, 0, MVT::Other}, {SDTCisInt, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
687 /* 61 */ {SDTCisInt, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisPtrTy, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
688 /* 64 */ {SDTCisSameAs, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
689 /* 67 */ {SDTCisSameAs, 1, 2, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
690 /* 70 */ {SDTCisOpSmallerThanOp, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
691 /* 73 */ {SDTCisVT, 2, 0, MVT::Other}, {SDTCisInt, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
692 /* 76 */ {SDTCisInt, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
693 /* 79 */ {SDTCisVec, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
694 /* 81 */ {SDTCisSameAs, 0, 1, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
695 /* 83 */ {SDTCisSameNumEltsAs, 0, 1, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisOpSmallerThanOp, 0, 1, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
696 /* 87 */ {SDTCisSameAs, 0, 3, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 2, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
697 /* 91 */ {SDTCisInt, 3, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 2, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
698 /* 95 */ {SDTCisInt, 3, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
699 /* 99 */ {SDTCisSameAs, 2, 3, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
700 /* 103 */ {SDTCisSameNumEltsAs, 0, 1, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCVecEltisVT, 1, 0, MVT::i1}, {SDTCisVec, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 3, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
701 /* 108 */ {SDTCisVT, 1, 0, MVT::i32}, {SDTCisVec, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
702 /* 110 */ {SDTCisSameNumEltsAs, 0, 2, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCVecEltisVT, 2, 0, MVT::i1}, {SDTCisVec, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisPtrTy, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
703 /* 115 */ {SDTCisSameNumEltsAs, 0, 1, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCVecEltisVT, 1, 0, MVT::i1}, {SDTCisPtrTy, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
704 /* 120 */ {SDTCisSameNumEltsAs, 0, 1, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCVecEltisVT, 1, 0, MVT::i1}, {SDTCisVT, 4, 0, MVT::Other}, {SDTCisVec, 3, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisPtrTy, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
705 /* 127 */ {SDTCisInt, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
706 /* 130 */ {SDTCisSameAs, 1, 2, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
707 /* 135 */ {SDTCisSameAs, 0, 4, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVTSmallerThanOp, 3, 2, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 2, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCVecEltisVT, 1, 0, MVT::i1}, {SDTCisVec, 4, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 3, 0, MVT::Other}, {SDTCisVec, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
708 /* 144 */ {SDTCisSameAs, 0, 2, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCVecEltisVT, 1, 0, MVT::i1}, {SDTCisVT, 3, 0, MVT::i32}, {SDTCisVec, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
709 /* 150 */ {SDTCisSameNumEltsAs, 0, 1, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCVecEltisVT, 1, 0, MVT::i1}, {SDTCisVT, 4, 0, MVT::Other}, {SDTCisInt, 3, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
710 /* 157 */ {SDTCVecEltisVT, 1, 0, MVT::i1}, {SDTCisVec, 4, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 3, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
711 /* 163 */ {SDTCisVT, 4, 0, MVT::Other}, {SDTCisSameAs, 2, 3, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCVecEltisVT, 1, 0, MVT::i1}, {SDTCVecEltisVT, 0, 0, MVT::i1}, {SDTCisVec, 3, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
712 /* 171 */ {SDTCisSameAs, 0, 3, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameNumEltsAs, 0, 1, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCVecEltisVT, 1, 0, MVT::i1}, {SDTCisVec, 3, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
713 /* 178 */ {SDTCisSameAs, 0, 4, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 3, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 2, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameNumEltsAs, 0, 1, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCVecEltisVT, 1, 0, MVT::i1}, {SDTCisVec, 4, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 3, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
714 /* 188 */ {SDTCisSameNumEltsAs, 0, 1, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 2, 3, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 2, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCVecEltisVT, 1, 0, MVT::i1}, {SDTCisVec, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
715 /* 193 */ {SDTCisInt, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
716 /* 195 */ {SDTCisSameAs, 0, 2, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 3, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
717 /* 199 */ {SDTCisInt, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, MVT::INVALID_SIMPLE_VALUE_TYPE},
718 /* 201 */ {SDTCisFP, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, MVT::INVALID_SIMPLE_VALUE_TYPE},
719 /* 203 */ {SDTCisVT, 3, 0, MVT::i32}, {SDTCisInt, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 2, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, MVT::INVALID_SIMPLE_VALUE_TYPE},
720 /* 207 */ {SDTCisFP, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 2, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, MVT::INVALID_SIMPLE_VALUE_TYPE},
721 /* 210 */ {SDTCisPtrTy, 3, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 2, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, MVT::INVALID_SIMPLE_VALUE_TYPE},
722 /* 213 */ {SDTCisVT, 4, 0, MVT::i32}, {SDTCisInt, 3, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 2, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, MVT::INVALID_SIMPLE_VALUE_TYPE},
723 /* 217 */ {SDTCisInt, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, MVT::INVALID_SIMPLE_VALUE_TYPE},
724 /* 219 */ {SDTCisVT, 4, 0, MVT::i32}, {SDTCisVT, 1, 0, MVT::i32}, {SDTCisInt, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 3, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 2, MVT::INVALID_SIMPLE_VALUE_TYPE},
725 /* 224 */ {SDTCisVT, 2, 0, MVT::i64}, {SDTCisVT, 1, 0, MVT::i64},
726 /* 226 */ {SDTCisInt, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
727 /* 228 */ {SDTCisSameNumEltsAs, 1, 3, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 3, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCVecEltisVT, 1, 0, MVT::i1}, {SDTCisVec, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
728 /* 232 */ {SDTCisVec, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
729 /* 234 */ {SDTCisSameAs, 1, 2, MVT::INVALID_SIMPLE_VALUE_TYPE},
730};
731
732static const SDNodeDesc AArch64SDNodeDescs[] = {
733 {1, 3, 0, 0, 0, 1, 188, 5}, // ABDS_PRED
734 {1, 3, 0, 0, 0, 23, 188, 5}, // ABDU_PRED
735 {1, 3, 0, 0, 0, 45, 188, 5}, // ABS_MERGE_PASSTHRU
736 {1, 3, 0, 0, 0, 76, 203, 4}, // ADC
737 {2, 3, 0, 0, 0, 92, 219, 5}, // ADCS
738 {1, 2, 0, 0, 0, 109, 88, 3}, // ADDP
739 {2, 2, 0, 0, 0, 126, 220, 4}, // ADDS
740 {1, 2, 0, 0, 0, 143, 204, 3}, // ADDlow
741 {1, 1, 0, 0, 0, 162, 199, 2}, // ADR
742 {1, 1, 0, 0, 0, 178, 199, 2}, // ADRP
743 {1, 1, 0|1<<SDNPHasChain, 0, 0, 195, 65, 2}, // ALLOCATE_ZA_BUFFER
744 {1, 1, 0|1<<SDNPHasChain, 0, 0, 226, 65, 2}, // ALLOC_SME_SAVE_BUFFER
745 {2, 2, 0, 0, 0, 260, 220, 4}, // ANDS
746 {1, 2, 0, 0, 0, 277, 232, 2}, // ANDV_PRED
747 {1, 1, 0, 0, 0, 299, 64, 3}, // ASSERT_ZEXT_BOOL
748 {0, -1, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 328, 43, 4}, // AUTH_CALL
749 {0, -1, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 350, 47, 6}, // AUTH_CALL_RVMARKER
750 {0, 5, 0|1<<SDNPHasChain|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 381, 55, 4}, // AUTH_TC_RETURN
751 {1, 2, 0, 0, 0, 408, 130, 5}, // BIC
752 {1, 3, 0, 0, 0, 424, 95, 4}, // BICi
753 {1, 3, 0, 0, 0, 441, 188, 5}, // BITREVERSE_MERGE_PASSTHRU
754 {0, 3, 0|1<<SDNPHasChain, 0, 0, 479, 0, 3}, // BRCOND
755 {1, 3, 0, 0, 0, 498, 87, 4}, // BSP
756 {1, 3, 0, 0, 0, 514, 188, 5}, // BSWAP_MERGE_PASSTHRU
757 {0, -1, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 547, 46, 1}, // CALL
758 {0, -1, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 564, 46, 1}, // CALL_ARM64EC_TO_X64
759 {0, -1, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 596, 46, 1}, // CALL_BTI
760 {0, -1, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 617, 46, 1}, // CALL_RVMARKER
761 {0, 4, 0|1<<SDNPHasChain, 0, 0, 643, 11, 4}, // CB
762 {0, 2, 0|1<<SDNPHasChain, 0, 0, 658, 59, 2}, // CBNZ
763 {0, 2, 0|1<<SDNPHasChain, 0, 0, 675, 59, 2}, // CBZ
764 {1, 5, 0, 0, 0, 691, 5, 6}, // CCMN
765 {1, 5, 0, 0, 0, 708, 5, 6}, // CCMP
766 {1, 3, 0, 0, 0, 725, 228, 4}, // CLASTA_N
767 {1, 3, 0, 0, 0, 746, 228, 4}, // CLASTB_N
768 {1, 1, 0|1<<SDNPOutGlue|1<<SDNPOptInGlue, 0, 0, 767, 0, 0}, // COALESCER_BARRIER
769 {0, 3, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 797, 76, 3}, // COND_SMSTART
770 {0, 3, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 822, 76, 3}, // COND_SMSTOP
771 {1, 4, 0, 0, 0, 846, 213, 4}, // CSEL
772 {1, 4, 0, 0, 0, 863, 213, 4}, // CSINC
773 {1, 4, 0, 0, 0, 881, 213, 4}, // CSINV
774 {1, 4, 0, 0, 0, 899, 213, 4}, // CSNEG
775 {1, 3, 0, 0, 0, 917, 188, 5}, // CTLZ_MERGE_PASSTHRU
776 {1, 3, 0, 0, 0, 949, 188, 5}, // CTPOP_MERGE_PASSTHRU
777 {1, 1, 0, 0, 0, 982, 79, 2}, // CTTZ_ELTS
778 {1, 1, 0, 0, 0, 1004, 90, 1}, // DUP
779 {1, 2, 0, 0, 0, 1020, 193, 2}, // DUPLANE128
780 {1, 2, 0, 0, 0, 1043, 193, 2}, // DUPLANE16
781 {1, 2, 0, 0, 0, 1065, 193, 2}, // DUPLANE32
782 {1, 2, 0, 0, 0, 1087, 193, 2}, // DUPLANE64
783 {1, 2, 0, 0, 0, 1109, 193, 2}, // DUPLANE8
784 {1, 3, 0, 0, 0, 1130, 103, 5}, // DUP_MERGE_PASSTHRU
785 {1, 2, 0, 0, 0, 1161, 232, 2}, // EORV_PRED
786 {1, 3, 0, 0, 0, 1183, 91, 4}, // EXT
787 {1, 3, 0, 0, 0, 1199, 210, 3}, // EXTR
788 {1, 3, 0, 0, 0, 1216, 188, 5}, // FABS_MERGE_PASSTHRU
789 {1, 3, 0, 0, 0, 1248, 228, 4}, // FADDA_PRED
790 {1, 2, 0, 0, 0, 1271, 232, 2}, // FADDV_PRED
791 {1, 3, 0, 0, 0, 1294, 188, 5}, // FADD_PRED
792 {1, 5, 0, 0, 0, 1316, 15, 6}, // FCCMP
793 {1, 3, 0, 0, 0, 1334, 188, 5}, // FCEIL_MERGE_PASSTHRU
794 {1, 2, 0, 0, 0, 1367, 234, 1}, // FCMEQ
795 {1, 2, 0, 0, 0, 1385, 234, 1}, // FCMGE
796 {1, 2, 0, 0, 0, 1403, 234, 1}, // FCMGT
797 {1, 2, 0, 0, 0, 1421, 21, 3}, // FCMP
798 {1, 1, 0, 0, 0, 1438, 83, 4}, // FCVTXN
799 {1, 3, 0, 0, 0, 1457, 171, 7}, // FCVTX_MERGE_PASSTHRU
800 {1, 3, 0, 0, 0, 1490, 171, 7}, // FCVTZS_MERGE_PASSTHRU
801 {1, 3, 0, 0, 0, 1524, 171, 7}, // FCVTZU_MERGE_PASSTHRU
802 {1, 3, 0, 0, 0, 1558, 188, 5}, // FDIV_PRED
803 {1, 3, 0, 0, 0, 1580, 188, 5}, // FFLOOR_MERGE_PASSTHRU
804 {1, 2, 0, 0, 0, 1614, 232, 2}, // FMAXNMV_PRED
805 {1, 3, 0, 0, 0, 1639, 188, 5}, // FMAXNM_PRED
806 {1, 2, 0, 0, 0, 1663, 232, 2}, // FMAXV_PRED
807 {1, 3, 0, 0, 0, 1686, 188, 5}, // FMAX_PRED
808 {1, 4, 0, 0, 0, 1708, 178, 10}, // FMA_PRED
809 {1, 2, 0, 0, 0, 1729, 232, 2}, // FMINNMV_PRED
810 {1, 3, 0, 0, 0, 1754, 188, 5}, // FMINNM_PRED
811 {1, 2, 0, 0, 0, 1778, 232, 2}, // FMINV_PRED
812 {1, 3, 0, 0, 0, 1801, 188, 5}, // FMIN_PRED
813 {1, 1, 0, 0, 0, 1823, 227, 1}, // FMOV
814 {1, 3, 0, 0, 0, 1840, 188, 5}, // FMUL_PRED
815 {1, 3, 0, 0, 0, 1862, 188, 5}, // FNEARBYINT_MERGE_PASSTHRU
816 {1, 3, 0, 0, 0, 1900, 188, 5}, // FNEG_MERGE_PASSTHRU
817 {1, 3, 0, 0, 0, 1932, 171, 7}, // FP_EXTEND_MERGE_PASSTHRU
818 {1, 4, 0, 0, 0, 1969, 157, 6}, // FP_ROUND_MERGE_PASSTHRU
819 {1, 1, 0, 0, 0, 2005, 201, 2}, // FRECPE
820 {1, 2, 0, 0, 0, 2024, 207, 3}, // FRECPS
821 {1, 3, 0, 0, 0, 2043, 188, 5}, // FRECPX_MERGE_PASSTHRU
822 {1, 3, 0, 0, 0, 2077, 188, 5}, // FRINT_MERGE_PASSTHRU
823 {1, 3, 0, 0, 0, 2110, 188, 5}, // FROUNDEVEN_MERGE_PASSTHRU
824 {1, 3, 0, 0, 0, 2148, 188, 5}, // FROUND_MERGE_PASSTHRU
825 {1, 1, 0, 0, 0, 2182, 201, 2}, // FRSQRTE
826 {1, 2, 0, 0, 0, 2202, 207, 3}, // FRSQRTS
827 {1, 3, 0, 0, 0, 2222, 188, 5}, // FSQRT_MERGE_PASSTHRU
828 {1, 3, 0, 0, 0, 2255, 188, 5}, // FSUB_PRED
829 {1, 3, 0, 0, 0, 2277, 188, 5}, // FTRUNC_MERGE_PASSTHRU
830 {1, 0, 0|1<<SDNPHasChain, 0, 0, 2311, 60, 1}, // GET_SME_SAVE_SIZE
831 {1, 4, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2341, 0, 0}, // GLD1Q_INDEX_MERGE_ZERO
832 {1, 4, 0|1<<SDNPHasChain, 0, 0, 2376, 150, 7}, // GLD1Q_MERGE_ZERO
833 {1, 4, 0|1<<SDNPHasChain, 0, 0, 2405, 150, 7}, // GLD1S_IMM_MERGE_ZERO
834 {1, 4, 0|1<<SDNPHasChain, 0, 0, 2438, 120, 7}, // GLD1S_MERGE_ZERO
835 {1, 4, 0|1<<SDNPHasChain, 0, 0, 2467, 120, 7}, // GLD1S_SCALED_MERGE_ZERO
836 {1, 4, 0|1<<SDNPHasChain, 0, 0, 2503, 120, 7}, // GLD1S_SXTW_MERGE_ZERO
837 {1, 4, 0|1<<SDNPHasChain, 0, 0, 2537, 120, 7}, // GLD1S_SXTW_SCALED_MERGE_ZERO
838 {1, 4, 0|1<<SDNPHasChain, 0, 0, 2578, 120, 7}, // GLD1S_UXTW_MERGE_ZERO
839 {1, 4, 0|1<<SDNPHasChain, 0, 0, 2612, 120, 7}, // GLD1S_UXTW_SCALED_MERGE_ZERO
840 {1, 4, 0|1<<SDNPHasChain, 0, 0, 2653, 150, 7}, // GLD1_IMM_MERGE_ZERO
841 {1, 4, 0|1<<SDNPHasChain, 0, 0, 2685, 120, 7}, // GLD1_MERGE_ZERO
842 {1, 4, 0|1<<SDNPHasChain, 0, 0, 2713, 120, 7}, // GLD1_SCALED_MERGE_ZERO
843 {1, 4, 0|1<<SDNPHasChain, 0, 0, 2748, 120, 7}, // GLD1_SXTW_MERGE_ZERO
844 {1, 4, 0|1<<SDNPHasChain, 0, 0, 2781, 120, 7}, // GLD1_SXTW_SCALED_MERGE_ZERO
845 {1, 4, 0|1<<SDNPHasChain, 0, 0, 2821, 120, 7}, // GLD1_UXTW_MERGE_ZERO
846 {1, 4, 0|1<<SDNPHasChain, 0, 0, 2854, 120, 7}, // GLD1_UXTW_SCALED_MERGE_ZERO
847 {1, 4, 0|1<<SDNPHasChain, 0, 0, 2894, 150, 7}, // GLDFF1S_IMM_MERGE_ZERO
848 {1, 4, 0|1<<SDNPHasChain, 0, 0, 2929, 120, 7}, // GLDFF1S_MERGE_ZERO
849 {1, 4, 0|1<<SDNPHasChain, 0, 0, 2960, 120, 7}, // GLDFF1S_SCALED_MERGE_ZERO
850 {1, 4, 0|1<<SDNPHasChain, 0, 0, 2998, 120, 7}, // GLDFF1S_SXTW_MERGE_ZERO
851 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3034, 120, 7}, // GLDFF1S_SXTW_SCALED_MERGE_ZERO
852 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3077, 120, 7}, // GLDFF1S_UXTW_MERGE_ZERO
853 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3113, 120, 7}, // GLDFF1S_UXTW_SCALED_MERGE_ZERO
854 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3156, 150, 7}, // GLDFF1_IMM_MERGE_ZERO
855 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3190, 120, 7}, // GLDFF1_MERGE_ZERO
856 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3220, 120, 7}, // GLDFF1_SCALED_MERGE_ZERO
857 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3257, 120, 7}, // GLDFF1_SXTW_MERGE_ZERO
858 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3292, 120, 7}, // GLDFF1_SXTW_SCALED_MERGE_ZERO
859 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3334, 120, 7}, // GLDFF1_UXTW_MERGE_ZERO
860 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3369, 120, 7}, // GLDFF1_UXTW_SCALED_MERGE_ZERO
861 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3411, 150, 7}, // GLDNT1S_MERGE_ZERO
862 {1, 4, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 3442, 0, 0}, // GLDNT1_INDEX_MERGE_ZERO
863 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3478, 150, 7}, // GLDNT1_MERGE_ZERO
864 {1, 3, 0, 0, 0, 3508, 188, 5}, // HADDS_PRED
865 {1, 3, 0, 0, 0, 3531, 188, 5}, // HADDU_PRED
866 {0, 1, 0|1<<SDNPHasChain, 0, 0, 3554, 60, 1}, // INIT_TPIDR2OBJ
867 {1, 2, 0, 0, 0, 3581, 90, 1}, // INSR
868 {1, 2, 0, 0, 0, 3598, 232, 2}, // LASTA
869 {1, 2, 0, 0, 0, 3616, 232, 2}, // LASTB
870 {2, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 3634, 0, 0}, // LD1DUPpost
871 {2, 4, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 3657, 0, 0}, // LD1LANEpost
872 {1, 2, 0|1<<SDNPHasChain, 0, 0, 3681, 115, 5}, // LD1RO_MERGE_ZERO
873 {1, 2, 0|1<<SDNPHasChain, 0, 0, 3710, 115, 5}, // LD1RQ_MERGE_ZERO
874 {1, 3, 0|1<<SDNPHasChain, 0, 0, 3739, 115, 5}, // LD1S_MERGE_ZERO
875 {1, 3, 0|1<<SDNPHasChain, 0, 0, 3767, 115, 5}, // LD1_MERGE_ZERO
876 {3, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 3794, 0, 0}, // LD1x2post
877 {4, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 3816, 0, 0}, // LD1x3post
878 {5, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 3838, 0, 0}, // LD1x4post
879 {3, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 3860, 0, 0}, // LD2DUPpost
880 {3, 5, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 3883, 0, 0}, // LD2LANEpost
881 {3, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 3907, 0, 0}, // LD2post
882 {4, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 3927, 0, 0}, // LD3DUPpost
883 {4, 6, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 3950, 0, 0}, // LD3LANEpost
884 {4, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 3974, 0, 0}, // LD3post
885 {5, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 3994, 0, 0}, // LD4DUPpost
886 {5, 7, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 4017, 0, 0}, // LD4LANEpost
887 {5, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 4041, 0, 0}, // LD4post
888 {1, 3, 0|1<<SDNPHasChain, 0, 0, 4061, 115, 5}, // LDFF1S_MERGE_ZERO
889 {1, 3, 0|1<<SDNPHasChain, 0, 0, 4091, 115, 5}, // LDFF1_MERGE_ZERO
890 {2, 1, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 4120, 27, 3}, // LDIAPP
891 {1, 3, 0|1<<SDNPHasChain, 0, 0, 4139, 115, 5}, // LDNF1S_MERGE_ZERO
892 {1, 3, 0|1<<SDNPHasChain, 0, 0, 4169, 115, 5}, // LDNF1_MERGE_ZERO
893 {2, 1, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 4198, 40, 3}, // LDNP
894 {2, 1, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 4215, 27, 3}, // LDP
895 {1, 1, 0, 0, 0, 4231, 199, 2}, // LOADgot
896 {1, 8, 0, 0, 0, 4251, 0, 0}, // LS64_BUILD
897 {1, 2, 0, 0, 0, 4274, 0, 0}, // LS64_EXTRACT
898 {1, 1, 0, 0, 0, 4299, 227, 1}, // MOVI
899 {1, 1, 0, 0, 0, 4316, 227, 1}, // MOVIedit
900 {1, 2, 0, 0, 0, 4337, 226, 2}, // MOVImsl
901 {1, 2, 0, 0, 0, 4357, 226, 2}, // MOVIshift
902 {2, 1, 0|1<<SDNPHasChain, 0, 0, 4379, 38, 2}, // MRRS
903 {2, 1, 0|1<<SDNPHasChain, 0, 0, 4396, 35, 3}, // MRS
904 {0, 3, 0|1<<SDNPHasChain, 0, 0, 4412, 224, 2}, // MSRR
905 {1, 3, 0, 0, 0, 4429, 188, 5}, // MULHS_PRED
906 {1, 3, 0, 0, 0, 4452, 188, 5}, // MULHU_PRED
907 {1, 3, 0, 0, 0, 4475, 188, 5}, // MUL_PRED
908 {1, 2, 0, 0, 0, 4496, 226, 2}, // MVNImsl
909 {1, 2, 0, 0, 0, 4516, 226, 2}, // MVNIshift
910 {1, 3, 0, 0, 0, 4538, 188, 5}, // NEG_MERGE_PASSTHRU
911 {1, 1, 0, 0, 0, 4569, 0, 0}, // NVCAST
912 {1, 3, 0, 0, 0, 4588, 95, 4}, // ORRi
913 {1, 2, 0, 0, 0, 4605, 232, 2}, // ORV_PRED
914 {1, 2, 0, 0, 0, 4626, 67, 3}, // PMULL
915 {0, 2, 0|1<<SDNPHasChain, 0, 0, 4644, 3, 2}, // PREFETCH
916 {0, 1, 0|1<<SDNPHasChain, 0, 0, 4665, 46, 1}, // PROBED_ALLOCA
917 {1, 2, 0, 0, 0, 4691, 24, 3}, // PTEST
918 {1, 2, 0, 0, 0, 4709, 24, 3}, // PTEST_ANY
919 {1, 1, 0, 0, 0, 4731, 108, 2}, // PTRUE
920 {1, 1, 0, 0, 0, 4749, 65, 2}, // RDSVL
921 {1, 1, 0, 0, 0, 4767, 0, 0}, // REINTERPRET_CAST
922 {0, 3, 0|1<<SDNPHasChain|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 4796, 62, 2}, // RESTORE_ZA
923 {0, 2, 0|1<<SDNPHasChain, 0, 0, 4819, 62, 2}, // RESTORE_ZT
924 {0, 0, 0|1<<SDNPHasChain|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 4842, 0, 0}, // RET_GLUE
925 {1, 1, 0, 0, 0, 4863, 200, 1}, // REV16
926 {1, 1, 0, 0, 0, 4881, 200, 1}, // REV32
927 {1, 1, 0, 0, 0, 4899, 200, 1}, // REV64
928 {1, 3, 0, 0, 0, 4917, 188, 5}, // REVD_MERGE_PASSTHRU
929 {1, 3, 0, 0, 0, 4949, 188, 5}, // REVH_MERGE_PASSTHRU
930 {1, 3, 0, 0, 0, 4981, 188, 5}, // REVW_MERGE_PASSTHRU
931 {1, 3, 0, 0, 0, 5013, 188, 5}, // RHADDS_PRED
932 {1, 3, 0, 0, 0, 5037, 188, 5}, // RHADDU_PRED
933 {1, 2, 0, 0, 0, 5061, 127, 3}, // RSHRNB_I
934 {1, 1, 0, 0, 0, 5082, 118, 2}, // SADDLP
935 {1, 1, 0, 0, 0, 5101, 118, 2}, // SADDLV
936 {1, 1, 0, 0, 0, 5120, 89, 2}, // SADDV
937 {1, 2, 0, 0, 0, 5138, 232, 2}, // SADDV_PRED
938 {1, 2, 0, 0, 0, 5161, 118, 2}, // SADDWB
939 {1, 2, 0, 0, 0, 5180, 118, 2}, // SADDWT
940 {0, 2, 0|1<<SDNPHasChain, 0, 0, 5199, 62, 2}, // SAVE_ZT
941 {1, 3, 0, 0, 0, 5219, 203, 4}, // SBC
942 {2, 3, 0, 0, 0, 5235, 219, 5}, // SBCS
943 {1, 3, 0, 0, 0, 5252, 188, 5}, // SDIV_PRED
944 {1, 3, 0, 0, 0, 5274, 99, 4}, // SDOT
945 {1, 4, 0, 0, 0, 5291, 163, 8}, // SETCC_MERGE_ZERO
946 {1, 3, 0, 0, 0, 5320, 188, 5}, // SHL_PRED
947 {1, 4, 0, 0, 0, 5341, 135, 9}, // SIGN_EXTEND_INREG_MERGE_PASSTHRU
948 {1, 3, 0, 0, 0, 5386, 171, 7}, // SINT_TO_FP_MERGE_PASSTHRU
949 {1, 1, 0, 0, 0, 5424, 81, 2}, // SITOF
950 {1, 1, 0, 0, 0, 5442, 89, 2}, // SMAXV
951 {1, 2, 0, 0, 0, 5460, 232, 2}, // SMAXV_PRED
952 {1, 3, 0, 0, 0, 5483, 188, 5}, // SMAX_PRED
953 {0, 3, 0|1<<SDNPHasChain, 0, 0, 5505, 61, 3}, // SME_ZA_LDR
954 {0, 3, 0|1<<SDNPHasChain, 0, 0, 5528, 61, 3}, // SME_ZA_STR
955 {1, 1, 0, 0, 0, 5551, 89, 2}, // SMINV
956 {1, 2, 0, 0, 0, 5569, 232, 2}, // SMINV_PRED
957 {1, 3, 0, 0, 0, 5592, 188, 5}, // SMIN_PRED
958 {0, 1, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 5614, 60, 1}, // SMSTART
959 {0, 1, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 5634, 60, 1}, // SMSTOP
960 {1, 2, 0, 0, 0, 5653, 67, 3}, // SMULL
961 {1, 3, 0, 0, 0, 5671, 188, 5}, // SPLICE
962 {1, 2, 0, 0, 0, 5690, 217, 2}, // SQSHLU_I
963 {1, 2, 0, 0, 0, 5711, 217, 2}, // SQSHL_I
964 {1, 3, 0, 0, 0, 5731, 144, 6}, // SRAD_MERGE_OP1
965 {1, 3, 0, 0, 0, 5758, 188, 5}, // SRA_PRED
966 {1, 3, 0, 0, 0, 5779, 188, 5}, // SRL_PRED
967 {1, 2, 0, 0, 0, 5800, 217, 2}, // SRSHR_I
968 {0, 5, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 5820, 0, 0}, // SST1Q_INDEX_PRED
969 {0, 5, 0|1<<SDNPHasChain, 0, 0, 5849, 150, 7}, // SST1Q_PRED
970 {0, 5, 0|1<<SDNPHasChain, 0, 0, 5872, 150, 7}, // SST1_IMM_PRED
971 {0, 5, 0|1<<SDNPHasChain, 0, 0, 5898, 120, 7}, // SST1_PRED
972 {0, 5, 0|1<<SDNPHasChain, 0, 0, 5920, 120, 7}, // SST1_SCALED_PRED
973 {0, 5, 0|1<<SDNPHasChain, 0, 0, 5949, 120, 7}, // SST1_SXTW_PRED
974 {0, 5, 0|1<<SDNPHasChain, 0, 0, 5976, 120, 7}, // SST1_SXTW_SCALED_PRED
975 {0, 5, 0|1<<SDNPHasChain, 0, 0, 6010, 120, 7}, // SST1_UXTW_PRED
976 {0, 5, 0|1<<SDNPHasChain, 0, 0, 6037, 120, 7}, // SST1_UXTW_SCALED_PRED
977 {0, 5, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 6071, 0, 0}, // SSTNT1_INDEX_PRED
978 {0, 5, 0|1<<SDNPHasChain, 0, 0, 6101, 150, 7}, // SSTNT1_PRED
979 {0, 4, 0|1<<SDNPHasChain, 0, 0, 6125, 110, 5}, // ST1_PRED
980 {1, 4, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 6146, 0, 0}, // ST1x2post
981 {1, 5, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 6168, 0, 0}, // ST1x3post
982 {1, 6, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 6190, 0, 0}, // ST1x4post
983 {0, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 6212, 53, 2}, // ST2G
984 {1, 5, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 6229, 0, 0}, // ST2LANEpost
985 {1, 4, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 6253, 0, 0}, // ST2post
986 {1, 6, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 6273, 0, 0}, // ST3LANEpost
987 {1, 5, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 6297, 0, 0}, // ST3post
988 {1, 7, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 6317, 0, 0}, // ST4LANEpost
989 {1, 6, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 6341, 0, 0}, // ST4post
990 {0, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 6361, 53, 2}, // STG
991 {0, 3, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 6377, 27, 3}, // STILP
992 {0, 3, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 6395, 40, 3}, // STNP
993 {0, 3, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 6412, 27, 3}, // STP
994 {1, 2, 0|1<<SDNPHasChain, 0|1<<SDNFIsStrictFP, 0, 6428, 21, 3}, // STRICT_FCMP
995 {1, 2, 0|1<<SDNPHasChain, 0|1<<SDNFIsStrictFP, 0, 6452, 21, 3}, // STRICT_FCMPE
996 {0, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 6477, 53, 2}, // STZ2G
997 {0, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 6495, 53, 2}, // STZG
998 {2, 2, 0, 0, 0, 6512, 220, 4}, // SUBS
999 {1, 1, 0, 0, 0, 6529, 70, 3}, // SUNPKHI
1000 {1, 1, 0, 0, 0, 6549, 70, 3}, // SUNPKLO
1001 {1, 2, 0, 0, 0, 6569, 96, 3}, // TBL
1002 {0, 3, 0|1<<SDNPHasChain, 0, 0, 6585, 73, 3}, // TBNZ
1003 {0, 3, 0|1<<SDNPHasChain, 0, 0, 6602, 73, 3}, // TBZ
1004 {0, 2, 0|1<<SDNPHasChain|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 6618, 46, 1}, // TC_RETURN
1005 {1, 0, 0, 0, 0, 6640, 46, 1}, // THREAD_POINTER
1006 {0, 1, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPVariadic, 0, 0, 6667, 46, 1}, // TLSDESC_AUTH_CALLSEQ
1007 {0, 1, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPVariadic, 0, 0, 6700, 46, 1}, // TLSDESC_CALLSEQ
1008 {1, 2, 0, 0, 0, 6728, 88, 3}, // TRN1
1009 {1, 2, 0, 0, 0, 6745, 88, 3}, // TRN2
1010 {1, 1, 0, 0, 0, 6762, 118, 2}, // UADDLP
1011 {1, 1, 0, 0, 0, 6781, 118, 2}, // UADDLV
1012 {1, 1, 0, 0, 0, 6800, 89, 2}, // UADDV
1013 {1, 2, 0, 0, 0, 6818, 232, 2}, // UADDV_PRED
1014 {1, 2, 0, 0, 0, 6841, 118, 2}, // UADDWB
1015 {1, 2, 0, 0, 0, 6860, 118, 2}, // UADDWT
1016 {1, 3, 0, 0, 0, 6879, 188, 5}, // UDIV_PRED
1017 {1, 3, 0, 0, 0, 6901, 99, 4}, // UDOT
1018 {1, 3, 0, 0, 0, 6918, 171, 7}, // UINT_TO_FP_MERGE_PASSTHRU
1019 {1, 1, 0, 0, 0, 6956, 81, 2}, // UITOF
1020 {1, 1, 0, 0, 0, 6974, 89, 2}, // UMAXV
1021 {1, 2, 0, 0, 0, 6992, 232, 2}, // UMAXV_PRED
1022 {1, 3, 0, 0, 0, 7015, 188, 5}, // UMAX_PRED
1023 {1, 1, 0, 0, 0, 7037, 89, 2}, // UMINV
1024 {1, 2, 0, 0, 0, 7055, 232, 2}, // UMINV_PRED
1025 {1, 3, 0, 0, 0, 7078, 188, 5}, // UMIN_PRED
1026 {1, 2, 0, 0, 0, 7100, 67, 3}, // UMULL
1027 {1, 2, 0, 0, 0, 7118, 217, 2}, // UQSHL_I
1028 {1, 2, 0, 0, 0, 7138, 217, 2}, // URSHR_I
1029 {1, 3, 0, 0, 0, 7158, 144, 6}, // URSHR_I_PRED
1030 {1, 3, 0, 0, 0, 7183, 99, 4}, // USDOT
1031 {1, 1, 0, 0, 0, 7201, 70, 3}, // UUNPKHI
1032 {1, 1, 0, 0, 0, 7221, 70, 3}, // UUNPKLO
1033 {1, 2, 0, 0, 0, 7241, 88, 3}, // UZP1
1034 {1, 2, 0, 0, 0, 7258, 88, 3}, // UZP2
1035 {1, 2, 0, 0, 0, 7275, 217, 2}, // VASHR
1036 {0, 0, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPOptInGlue, 0, 0, 7293, 0, 0}, // VG_RESTORE
1037 {0, 0, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPOptInGlue, 0, 0, 7316, 0, 0}, // VG_SAVE
1038 {1, 2, 0, 0, 0, 7336, 217, 2}, // VLSHR
1039 {1, 2, 0, 0, 0, 7354, 217, 2}, // VSHL
1040 {1, 3, 0, 0, 0, 7371, 195, 4}, // VSLI
1041 {1, 3, 0, 0, 0, 7388, 195, 4}, // VSRI
1042 {1, 4, 0, 0, 0, 7405, 30, 5}, // WrapperLarge
1043 {1, 4, 0, 0, 0, 7430, 135, 9}, // ZERO_EXTEND_INREG_MERGE_PASSTHRU
1044 {1, 2, 0, 0, 0, 7475, 88, 3}, // ZIP1
1045 {1, 2, 0, 0, 0, 7492, 88, 3}, // ZIP2
1046};
1047
1048static const SDNodeInfo AArch64GenSDNodeInfo(
1049 /*NumOpcodes=*/313, AArch64SDNodeDescs,
1050 AArch64SDNodeNames, AArch64SDTypeConstraints);
1051
1052} // namespace llvm
1053
1054#endif // GET_SDNODE_DESC
1055
1056