1 | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
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2 | |* *| |
3 | |* Pseudo-instruction MC lowering Source Fragment *| |
4 | |* *| |
5 | |* Automatically generated file, do not edit! *| |
6 | |* *| |
7 | \*===----------------------------------------------------------------------===*/ |
8 | |
9 | bool AMDGPUAsmPrinter:: |
10 | lowerPseudoInstExpansion(const MachineInstr *MI, MCInst &Inst) { |
11 | Inst.clear(); |
12 | switch (MI->getOpcode()) { |
13 | default: return false; |
14 | case AMDGPU::V_MOV_B32_indirect_read: { |
15 | MCOperand MCOp; |
16 | Inst.setOpcode(AMDGPU::V_MOV_B32_e32_vi); |
17 | // Operand: vdst |
18 | lowerOperand(MO: MI->getOperand(i: 0), MCOp); |
19 | Inst.addOperand(Op: MCOp); |
20 | // Operand: src0 |
21 | lowerOperand(MO: MI->getOperand(i: 1), MCOp); |
22 | Inst.addOperand(Op: MCOp); |
23 | break; |
24 | } |
25 | case AMDGPU::V_MOV_B32_indirect_write: { |
26 | MCOperand MCOp; |
27 | Inst.setOpcode(AMDGPU::V_MOV_B32_e32_vi); |
28 | // Operand: vdst |
29 | lowerOperand(MO: MI->getOperand(i: 0), MCOp); |
30 | Inst.addOperand(Op: MCOp); |
31 | // Operand: src0 |
32 | lowerOperand(MO: MI->getOperand(i: 1), MCOp); |
33 | Inst.addOperand(Op: MCOp); |
34 | break; |
35 | } |
36 | } |
37 | return true; |
38 | } |
39 | |
40 |