| 1 | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
|---|---|
| 2 | |* *| |
| 3 | |* Register Bank Source Fragments *| |
| 4 | |* *| |
| 5 | |* Automatically generated file, do not edit! *| |
| 6 | |* *| |
| 7 | \*===----------------------------------------------------------------------===*/ |
| 8 | |
| 9 | #ifdef GET_REGBANK_DECLARATIONS |
| 10 | #undef GET_REGBANK_DECLARATIONS |
| 11 | namespace llvm { |
| 12 | namespace AMDGPU { |
| 13 | enum : unsigned { |
| 14 | InvalidRegBankID = ~0u, |
| 15 | AGPRRegBankID = 0, |
| 16 | SGPRRegBankID = 1, |
| 17 | VCCRegBankID = 2, |
| 18 | VGPRRegBankID = 3, |
| 19 | NumRegisterBanks, |
| 20 | }; |
| 21 | } // end namespace AMDGPU |
| 22 | } // end namespace llvm |
| 23 | #endif // GET_REGBANK_DECLARATIONS |
| 24 | |
| 25 | #ifdef GET_TARGET_REGBANK_CLASS |
| 26 | #undef GET_TARGET_REGBANK_CLASS |
| 27 | private: |
| 28 | static const RegisterBank *RegBanks[]; |
| 29 | static const unsigned Sizes[]; |
| 30 | |
| 31 | public: |
| 32 | const RegisterBank &getRegBankFromRegClass(const TargetRegisterClass &RC, LLT Ty) const override; |
| 33 | protected: |
| 34 | AMDGPUGenRegisterBankInfo(unsigned HwMode = 0); |
| 35 | |
| 36 | #endif // GET_TARGET_REGBANK_CLASS |
| 37 | |
| 38 | #ifdef GET_TARGET_REGBANK_IMPL |
| 39 | #undef GET_TARGET_REGBANK_IMPL |
| 40 | namespace llvm { |
| 41 | namespace AMDGPU { |
| 42 | const uint32_t AGPRRegBankCoverageData[] = { |
| 43 | // 0-31 |
| 44 | (1u << (AMDGPU::AGPR_LO16RegClassID - 0)) | |
| 45 | (1u << (AMDGPU::AV_32RegClassID - 0)) | |
| 46 | 0, |
| 47 | // 32-63 |
| 48 | (1u << (AMDGPU::AGPR_32RegClassID - 32)) | |
| 49 | (1u << (AMDGPU::AReg_64RegClassID - 32)) | |
| 50 | (1u << (AMDGPU::AReg_64_Align2RegClassID - 32)) | |
| 51 | (1u << (AMDGPU::AV_64RegClassID - 32)) | |
| 52 | (1u << (AMDGPU::AV_64_Align2RegClassID - 32)) | |
| 53 | 0, |
| 54 | // 64-95 |
| 55 | (1u << (AMDGPU::AReg_96RegClassID - 64)) | |
| 56 | (1u << (AMDGPU::AReg_96_Align2RegClassID - 64)) | |
| 57 | (1u << (AMDGPU::AReg_96_with_sub1_sub2_in_AReg_64_Align2RegClassID - 64)) | |
| 58 | (1u << (AMDGPU::AReg_128RegClassID - 64)) | |
| 59 | (1u << (AMDGPU::AV_96RegClassID - 64)) | |
| 60 | (1u << (AMDGPU::AReg_128_Align2RegClassID - 64)) | |
| 61 | (1u << (AMDGPU::AV_96_Align2RegClassID - 64)) | |
| 62 | (1u << (AMDGPU::AV_96_with_sub1_sub2_in_AV_64_Align2RegClassID - 64)) | |
| 63 | (1u << (AMDGPU::AV_128RegClassID - 64)) | |
| 64 | (1u << (AMDGPU::AV_128_Align2RegClassID - 64)) | |
| 65 | (1u << (AMDGPU::AV_128_with_sub1_sub2_in_AV_64_Align2RegClassID - 64)) | |
| 66 | 0, |
| 67 | // 96-127 |
| 68 | (1u << (AMDGPU::AReg_128_with_sub1_sub2_in_AReg_64_Align2RegClassID - 96)) | |
| 69 | (1u << (AMDGPU::AReg_160RegClassID - 96)) | |
| 70 | (1u << (AMDGPU::AReg_160_Align2RegClassID - 96)) | |
| 71 | (1u << (AMDGPU::AReg_160_with_sub1_sub2_in_AReg_64_Align2RegClassID - 96)) | |
| 72 | (1u << (AMDGPU::AV_160RegClassID - 96)) | |
| 73 | (1u << (AMDGPU::AV_160_Align2RegClassID - 96)) | |
| 74 | (1u << (AMDGPU::AV_160_with_sub1_sub2_in_AV_64_Align2RegClassID - 96)) | |
| 75 | 0, |
| 76 | // 128-159 |
| 77 | (1u << (AMDGPU::AReg_192RegClassID - 128)) | |
| 78 | (1u << (AMDGPU::AReg_192_Align2RegClassID - 128)) | |
| 79 | (1u << (AMDGPU::AReg_192_with_sub1_sub2_in_AReg_64_Align2RegClassID - 128)) | |
| 80 | (1u << (AMDGPU::AV_192RegClassID - 128)) | |
| 81 | (1u << (AMDGPU::AV_192_Align2RegClassID - 128)) | |
| 82 | (1u << (AMDGPU::AV_192_with_sub1_sub2_in_AV_64_Align2RegClassID - 128)) | |
| 83 | 0, |
| 84 | // 160-191 |
| 85 | (1u << (AMDGPU::AReg_224RegClassID - 160)) | |
| 86 | (1u << (AMDGPU::AReg_224_Align2RegClassID - 160)) | |
| 87 | (1u << (AMDGPU::AReg_224_with_sub1_sub2_in_AReg_64_Align2RegClassID - 160)) | |
| 88 | (1u << (AMDGPU::AV_224RegClassID - 160)) | |
| 89 | (1u << (AMDGPU::AV_224_Align2RegClassID - 160)) | |
| 90 | (1u << (AMDGPU::AV_224_with_sub1_sub2_in_AV_64_Align2RegClassID - 160)) | |
| 91 | 0, |
| 92 | // 192-223 |
| 93 | (1u << (AMDGPU::AReg_256RegClassID - 192)) | |
| 94 | (1u << (AMDGPU::AReg_256_Align2RegClassID - 192)) | |
| 95 | (1u << (AMDGPU::AReg_256_with_sub1_sub2_in_AReg_64_Align2RegClassID - 192)) | |
| 96 | (1u << (AMDGPU::AV_256RegClassID - 192)) | |
| 97 | (1u << (AMDGPU::AV_256_Align2RegClassID - 192)) | |
| 98 | (1u << (AMDGPU::AV_256_with_sub1_sub2_in_AV_64_Align2RegClassID - 192)) | |
| 99 | 0, |
| 100 | // 224-255 |
| 101 | (1u << (AMDGPU::AReg_288RegClassID - 224)) | |
| 102 | (1u << (AMDGPU::AReg_288_Align2RegClassID - 224)) | |
| 103 | (1u << (AMDGPU::AReg_288_with_sub1_sub2_in_AReg_64_Align2RegClassID - 224)) | |
| 104 | (1u << (AMDGPU::AV_288RegClassID - 224)) | |
| 105 | (1u << (AMDGPU::AV_288_Align2RegClassID - 224)) | |
| 106 | (1u << (AMDGPU::AV_288_with_sub1_sub2_in_AV_64_Align2RegClassID - 224)) | |
| 107 | 0, |
| 108 | // 256-287 |
| 109 | (1u << (AMDGPU::AReg_320RegClassID - 256)) | |
| 110 | (1u << (AMDGPU::AReg_320_Align2RegClassID - 256)) | |
| 111 | (1u << (AMDGPU::AV_320RegClassID - 256)) | |
| 112 | (1u << (AMDGPU::AV_320_Align2RegClassID - 256)) | |
| 113 | (1u << (AMDGPU::AV_320_with_sub1_sub2_in_AV_64_Align2RegClassID - 256)) | |
| 114 | 0, |
| 115 | // 288-319 |
| 116 | (1u << (AMDGPU::AReg_320_with_sub1_sub2_in_AReg_64_Align2RegClassID - 288)) | |
| 117 | (1u << (AMDGPU::AV_352RegClassID - 288)) | |
| 118 | 0, |
| 119 | // 320-351 |
| 120 | (1u << (AMDGPU::AReg_352RegClassID - 320)) | |
| 121 | (1u << (AMDGPU::AReg_352_Align2RegClassID - 320)) | |
| 122 | (1u << (AMDGPU::AReg_352_with_sub1_sub2_in_AReg_64_Align2RegClassID - 320)) | |
| 123 | (1u << (AMDGPU::AV_352_Align2RegClassID - 320)) | |
| 124 | (1u << (AMDGPU::AV_352_with_sub1_sub2_in_AV_64_Align2RegClassID - 320)) | |
| 125 | 0, |
| 126 | // 352-383 |
| 127 | (1u << (AMDGPU::AReg_384RegClassID - 352)) | |
| 128 | (1u << (AMDGPU::AReg_384_Align2RegClassID - 352)) | |
| 129 | (1u << (AMDGPU::AReg_384_with_sub1_sub2_in_AReg_64_Align2RegClassID - 352)) | |
| 130 | (1u << (AMDGPU::AV_384RegClassID - 352)) | |
| 131 | (1u << (AMDGPU::AV_384_Align2RegClassID - 352)) | |
| 132 | (1u << (AMDGPU::AV_384_with_sub1_sub2_in_AV_64_Align2RegClassID - 352)) | |
| 133 | 0, |
| 134 | // 384-415 |
| 135 | (1u << (AMDGPU::AReg_512RegClassID - 384)) | |
| 136 | (1u << (AMDGPU::AV_512RegClassID - 384)) | |
| 137 | (1u << (AMDGPU::AV_512_Align2RegClassID - 384)) | |
| 138 | 0, |
| 139 | // 416-447 |
| 140 | (1u << (AMDGPU::AReg_512_Align2RegClassID - 416)) | |
| 141 | (1u << (AMDGPU::AReg_512_with_sub1_sub2_in_AReg_64_Align2RegClassID - 416)) | |
| 142 | (1u << (AMDGPU::AV_512_with_sub1_sub2_in_AV_64_Align2RegClassID - 416)) | |
| 143 | 0, |
| 144 | // 448-479 |
| 145 | (1u << (AMDGPU::AReg_1024RegClassID - 448)) | |
| 146 | 0, |
| 147 | // 480-511 |
| 148 | (1u << (AMDGPU::AReg_1024_Align2RegClassID - 480)) | |
| 149 | (1u << (AMDGPU::AReg_1024_with_sub1_sub2_in_AReg_64_Align2RegClassID - 480)) | |
| 150 | 0, |
| 151 | // 512-543 |
| 152 | 0, |
| 153 | // 544-575 |
| 154 | 0, |
| 155 | // 576-607 |
| 156 | 0, |
| 157 | // 608-639 |
| 158 | 0, |
| 159 | }; |
| 160 | const uint32_t SGPRRegBankCoverageData[] = { |
| 161 | // 0-31 |
| 162 | (1u << (AMDGPU::SReg_LO16RegClassID - 0)) | |
| 163 | (1u << (AMDGPU::SGPR_LO16RegClassID - 0)) | |
| 164 | (1u << (AMDGPU::TTMP_LO16RegClassID - 0)) | |
| 165 | (1u << (AMDGPU::M0_CLASS_LO16RegClassID - 0)) | |
| 166 | (1u << (AMDGPU::SReg_1RegClassID - 0)) | |
| 167 | (1u << (AMDGPU::VS_16RegClassID - 0)) | |
| 168 | (1u << (AMDGPU::VS_16_Lo128RegClassID - 0)) | |
| 169 | (1u << (AMDGPU::VS_16_and_SReg_1RegClassID - 0)) | |
| 170 | (1u << (AMDGPU::VS_32RegClassID - 0)) | |
| 171 | (1u << (AMDGPU::VS_32_with_hi16RegClassID - 0)) | |
| 172 | (1u << (AMDGPU::VS_32_Lo128RegClassID - 0)) | |
| 173 | (1u << (AMDGPU::VS_32_Lo128_with_hi16RegClassID - 0)) | |
| 174 | (1u << (AMDGPU::SReg_1_XEXECRegClassID - 0)) | |
| 175 | (1u << (AMDGPU::VS_16_and_SReg_1_XEXECRegClassID - 0)) | |
| 176 | (1u << (AMDGPU::SReg_1_with_lo16_in_SGPR_LO16RegClassID - 0)) | |
| 177 | (1u << (AMDGPU::VS_16_and_SReg_1_with_lo16_in_SGPR_LO16RegClassID - 0)) | |
| 178 | (1u << (AMDGPU::SReg_1_with_lo16_in_TTMP_LO16RegClassID - 0)) | |
| 179 | (1u << (AMDGPU::VS_16_and_SReg_1_with_lo16_in_TTMP_LO16RegClassID - 0)) | |
| 180 | (1u << (AMDGPU::SReg_1_with_sub0RegClassID - 0)) | |
| 181 | (1u << (AMDGPU::SReg_1_XEXEC_with_sub0RegClassID - 0)) | |
| 182 | (1u << (AMDGPU::SReg_1_with_sub0_and_SReg_1_with_lo16_in_SGPR_LO16RegClassID - 0)) | |
| 183 | (1u << (AMDGPU::SReg_1_with_sub0_and_SReg_1_with_lo16_in_TTMP_LO16RegClassID - 0)) | |
| 184 | 0, |
| 185 | // 32-63 |
| 186 | (1u << (AMDGPU::SReg_32RegClassID - 32)) | |
| 187 | (1u << (AMDGPU::SReg_32_XEXEC_HIRegClassID - 32)) | |
| 188 | (1u << (AMDGPU::SReg_32_XEXECRegClassID - 32)) | |
| 189 | (1u << (AMDGPU::SReg_32_XM0_XEXECRegClassID - 32)) | |
| 190 | (1u << (AMDGPU::SGPR_32RegClassID - 32)) | |
| 191 | (1u << (AMDGPU::TTMP_32RegClassID - 32)) | |
| 192 | (1u << (AMDGPU::M0_CLASSRegClassID - 32)) | |
| 193 | (1u << (AMDGPU::SReg_32_XEXEC_HI_and_SReg_32_XM0RegClassID - 32)) | |
| 194 | (1u << (AMDGPU::SReg_32_XM0RegClassID - 32)) | |
| 195 | (1u << (AMDGPU::SReg_64RegClassID - 32)) | |
| 196 | (1u << (AMDGPU::SRegOrLds_32RegClassID - 32)) | |
| 197 | (1u << (AMDGPU::SReg_64_XEXECRegClassID - 32)) | |
| 198 | (1u << (AMDGPU::SReg_64_XEXEC_XNULLRegClassID - 32)) | |
| 199 | (1u << (AMDGPU::VS_64RegClassID - 32)) | |
| 200 | (1u << (AMDGPU::VS_64_with_sub0_in_VS_32_Lo128RegClassID - 32)) | |
| 201 | (1u << (AMDGPU::VS_64_with_sub1_in_VS_32_Lo128RegClassID - 32)) | |
| 202 | 0, |
| 203 | // 64-95 |
| 204 | (1u << (AMDGPU::SGPR_64RegClassID - 64)) | |
| 205 | (1u << (AMDGPU::CCR_SGPR_64RegClassID - 64)) | |
| 206 | (1u << (AMDGPU::Gfx_CCR_SGPR_64RegClassID - 64)) | |
| 207 | (1u << (AMDGPU::TTMP_64RegClassID - 64)) | |
| 208 | (1u << (AMDGPU::SReg_96RegClassID - 64)) | |
| 209 | (1u << (AMDGPU::SGPR_96RegClassID - 64)) | |
| 210 | (1u << (AMDGPU::SGPR_96_with_sub0_sub1_in_CCR_SGPR_64RegClassID - 64)) | |
| 211 | (1u << (AMDGPU::SGPR_96_with_sub0_sub1_in_Gfx_CCR_SGPR_64RegClassID - 64)) | |
| 212 | (1u << (AMDGPU::TTMP_96RegClassID - 64)) | |
| 213 | 0, |
| 214 | // 96-127 |
| 215 | (1u << (AMDGPU::SReg_128RegClassID - 96)) | |
| 216 | (1u << (AMDGPU::SReg_128_XNULLRegClassID - 96)) | |
| 217 | (1u << (AMDGPU::SGPR_128RegClassID - 96)) | |
| 218 | (1u << (AMDGPU::SGPR_128_with_sub0_sub1_in_CCR_SGPR_64RegClassID - 96)) | |
| 219 | (1u << (AMDGPU::SGPR_128_with_sub2_sub3_in_CCR_SGPR_64RegClassID - 96)) | |
| 220 | (1u << (AMDGPU::SGPR_128_with_sub0_sub1_in_Gfx_CCR_SGPR_64RegClassID - 96)) | |
| 221 | (1u << (AMDGPU::TTMP_128RegClassID - 96)) | |
| 222 | 0, |
| 223 | // 128-159 |
| 224 | (1u << (AMDGPU::SReg_160RegClassID - 128)) | |
| 225 | (1u << (AMDGPU::SGPR_160RegClassID - 128)) | |
| 226 | (1u << (AMDGPU::SGPR_160_with_sub0_sub1_in_CCR_SGPR_64RegClassID - 128)) | |
| 227 | (1u << (AMDGPU::SGPR_160_with_sub2_sub3_in_CCR_SGPR_64RegClassID - 128)) | |
| 228 | (1u << (AMDGPU::SGPR_160_with_sub0_sub1_in_Gfx_CCR_SGPR_64RegClassID - 128)) | |
| 229 | (1u << (AMDGPU::TTMP_160RegClassID - 128)) | |
| 230 | 0, |
| 231 | // 160-191 |
| 232 | (1u << (AMDGPU::SReg_192RegClassID - 160)) | |
| 233 | (1u << (AMDGPU::SGPR_192RegClassID - 160)) | |
| 234 | (1u << (AMDGPU::SGPR_192_with_sub0_sub1_in_CCR_SGPR_64RegClassID - 160)) | |
| 235 | (1u << (AMDGPU::SGPR_192_with_sub2_sub3_in_CCR_SGPR_64RegClassID - 160)) | |
| 236 | (1u << (AMDGPU::SGPR_192_with_sub0_sub1_in_Gfx_CCR_SGPR_64RegClassID - 160)) | |
| 237 | (1u << (AMDGPU::SGPR_192_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 160)) | |
| 238 | (1u << (AMDGPU::SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 160)) | |
| 239 | (1u << (AMDGPU::TTMP_192RegClassID - 160)) | |
| 240 | 0, |
| 241 | // 192-223 |
| 242 | (1u << (AMDGPU::SReg_224RegClassID - 192)) | |
| 243 | (1u << (AMDGPU::SGPR_224RegClassID - 192)) | |
| 244 | (1u << (AMDGPU::SGPR_224_with_sub0_sub1_in_CCR_SGPR_64RegClassID - 192)) | |
| 245 | (1u << (AMDGPU::SGPR_224_with_sub2_sub3_in_CCR_SGPR_64RegClassID - 192)) | |
| 246 | (1u << (AMDGPU::SGPR_224_with_sub0_sub1_in_Gfx_CCR_SGPR_64RegClassID - 192)) | |
| 247 | (1u << (AMDGPU::SGPR_224_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_224_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 192)) | |
| 248 | (1u << (AMDGPU::SGPR_224_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 192)) | |
| 249 | (1u << (AMDGPU::TTMP_224RegClassID - 192)) | |
| 250 | 0, |
| 251 | // 224-255 |
| 252 | (1u << (AMDGPU::SReg_256RegClassID - 224)) | |
| 253 | (1u << (AMDGPU::SReg_256_XNULLRegClassID - 224)) | |
| 254 | (1u << (AMDGPU::SGPR_256RegClassID - 224)) | |
| 255 | (1u << (AMDGPU::SGPR_256_with_sub0_sub1_in_CCR_SGPR_64RegClassID - 224)) | |
| 256 | (1u << (AMDGPU::SGPR_256_with_sub2_sub3_in_CCR_SGPR_64RegClassID - 224)) | |
| 257 | (1u << (AMDGPU::SGPR_256_with_sub6_sub7_in_CCR_SGPR_64RegClassID - 224)) | |
| 258 | (1u << (AMDGPU::SGPR_256_with_sub0_sub1_in_Gfx_CCR_SGPR_64RegClassID - 224)) | |
| 259 | (1u << (AMDGPU::SGPR_256_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_256_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 224)) | |
| 260 | (1u << (AMDGPU::SGPR_256_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 224)) | |
| 261 | (1u << (AMDGPU::TTMP_256RegClassID - 224)) | |
| 262 | 0, |
| 263 | // 256-287 |
| 264 | (1u << (AMDGPU::SReg_288RegClassID - 256)) | |
| 265 | (1u << (AMDGPU::SGPR_288RegClassID - 256)) | |
| 266 | (1u << (AMDGPU::SGPR_288_with_sub0_sub1_in_CCR_SGPR_64RegClassID - 256)) | |
| 267 | (1u << (AMDGPU::SGPR_288_with_sub2_sub3_in_CCR_SGPR_64RegClassID - 256)) | |
| 268 | (1u << (AMDGPU::SGPR_288_with_sub6_sub7_in_CCR_SGPR_64RegClassID - 256)) | |
| 269 | (1u << (AMDGPU::SGPR_288_with_sub0_sub1_in_Gfx_CCR_SGPR_64RegClassID - 256)) | |
| 270 | (1u << (AMDGPU::SGPR_288_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_288_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 256)) | |
| 271 | (1u << (AMDGPU::SGPR_288_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 256)) | |
| 272 | (1u << (AMDGPU::TTMP_288RegClassID - 256)) | |
| 273 | 0, |
| 274 | // 288-319 |
| 275 | (1u << (AMDGPU::SReg_320RegClassID - 288)) | |
| 276 | (1u << (AMDGPU::SGPR_320RegClassID - 288)) | |
| 277 | (1u << (AMDGPU::SGPR_320_with_sub0_sub1_in_CCR_SGPR_64RegClassID - 288)) | |
| 278 | (1u << (AMDGPU::SGPR_320_with_sub2_sub3_in_CCR_SGPR_64RegClassID - 288)) | |
| 279 | (1u << (AMDGPU::SGPR_320_with_sub6_sub7_in_CCR_SGPR_64RegClassID - 288)) | |
| 280 | (1u << (AMDGPU::SGPR_320_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_320_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClassID - 288)) | |
| 281 | (1u << (AMDGPU::SGPR_320_with_sub0_sub1_in_Gfx_CCR_SGPR_64RegClassID - 288)) | |
| 282 | (1u << (AMDGPU::SGPR_320_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_320_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 288)) | |
| 283 | (1u << (AMDGPU::SGPR_320_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_320_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClassID - 288)) | |
| 284 | (1u << (AMDGPU::SGPR_320_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 288)) | |
| 285 | (1u << (AMDGPU::SGPR_320_with_sub4_sub5_in_Gfx_CCR_SGPR_64_and_SGPR_320_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClassID - 288)) | |
| 286 | (1u << (AMDGPU::SGPR_320_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClassID - 288)) | |
| 287 | (1u << (AMDGPU::TTMP_320RegClassID - 288)) | |
| 288 | 0, |
| 289 | // 320-351 |
| 290 | (1u << (AMDGPU::SReg_352RegClassID - 320)) | |
| 291 | 0, |
| 292 | // 352-383 |
| 293 | (1u << (AMDGPU::SGPR_352RegClassID - 352)) | |
| 294 | (1u << (AMDGPU::SGPR_352_with_sub0_sub1_in_CCR_SGPR_64RegClassID - 352)) | |
| 295 | (1u << (AMDGPU::SGPR_352_with_sub2_sub3_in_CCR_SGPR_64RegClassID - 352)) | |
| 296 | (1u << (AMDGPU::SGPR_352_with_sub6_sub7_in_CCR_SGPR_64RegClassID - 352)) | |
| 297 | (1u << (AMDGPU::SGPR_352_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_352_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClassID - 352)) | |
| 298 | (1u << (AMDGPU::SGPR_352_with_sub0_sub1_in_Gfx_CCR_SGPR_64RegClassID - 352)) | |
| 299 | (1u << (AMDGPU::SGPR_352_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_352_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 352)) | |
| 300 | (1u << (AMDGPU::SGPR_352_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_352_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClassID - 352)) | |
| 301 | (1u << (AMDGPU::SGPR_352_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 352)) | |
| 302 | (1u << (AMDGPU::SGPR_352_with_sub4_sub5_in_Gfx_CCR_SGPR_64_and_SGPR_352_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClassID - 352)) | |
| 303 | (1u << (AMDGPU::SGPR_352_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClassID - 352)) | |
| 304 | (1u << (AMDGPU::TTMP_352RegClassID - 352)) | |
| 305 | 0, |
| 306 | // 384-415 |
| 307 | (1u << (AMDGPU::SReg_384RegClassID - 384)) | |
| 308 | (1u << (AMDGPU::SGPR_384RegClassID - 384)) | |
| 309 | (1u << (AMDGPU::SGPR_384_with_sub0_sub1_in_CCR_SGPR_64RegClassID - 384)) | |
| 310 | (1u << (AMDGPU::SGPR_384_with_sub2_sub3_in_CCR_SGPR_64RegClassID - 384)) | |
| 311 | (1u << (AMDGPU::SGPR_384_with_sub6_sub7_in_CCR_SGPR_64RegClassID - 384)) | |
| 312 | (1u << (AMDGPU::SGPR_384_with_sub10_sub11_in_CCR_SGPR_64RegClassID - 384)) | |
| 313 | (1u << (AMDGPU::SGPR_384_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_384_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClassID - 384)) | |
| 314 | (1u << (AMDGPU::SGPR_384_with_sub0_sub1_in_Gfx_CCR_SGPR_64RegClassID - 384)) | |
| 315 | (1u << (AMDGPU::SGPR_384_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_384_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 384)) | |
| 316 | (1u << (AMDGPU::SGPR_384_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_384_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClassID - 384)) | |
| 317 | (1u << (AMDGPU::SGPR_384_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 384)) | |
| 318 | (1u << (AMDGPU::SGPR_384_with_sub4_sub5_in_Gfx_CCR_SGPR_64_and_SGPR_384_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClassID - 384)) | |
| 319 | (1u << (AMDGPU::SGPR_384_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClassID - 384)) | |
| 320 | (1u << (AMDGPU::TTMP_384RegClassID - 384)) | |
| 321 | 0, |
| 322 | // 416-447 |
| 323 | 0, |
| 324 | // 448-479 |
| 325 | (1u << (AMDGPU::SReg_512RegClassID - 448)) | |
| 326 | (1u << (AMDGPU::SGPR_512RegClassID - 448)) | |
| 327 | (1u << (AMDGPU::SGPR_512_with_sub0_sub1_in_CCR_SGPR_64RegClassID - 448)) | |
| 328 | (1u << (AMDGPU::SGPR_512_with_sub2_sub3_in_CCR_SGPR_64RegClassID - 448)) | |
| 329 | (1u << (AMDGPU::SGPR_512_with_sub6_sub7_in_CCR_SGPR_64RegClassID - 448)) | |
| 330 | (1u << (AMDGPU::SGPR_512_with_sub10_sub11_in_CCR_SGPR_64RegClassID - 448)) | |
| 331 | (1u << (AMDGPU::SGPR_512_with_sub14_sub15_in_CCR_SGPR_64RegClassID - 448)) | |
| 332 | (1u << (AMDGPU::SGPR_512_with_sub0_sub1_in_CCR_SGPR_64_with_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16_sub12_lo16_sub12_hi16_sub13_lo16_sub13_hi16_sub14_lo16_sub14_hi16_sub15_lo16_sub15_hi16_in_SGPR_384_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_384_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClassID - 448)) | |
| 333 | (1u << (AMDGPU::SGPR_512_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_512_with_sub12_sub13_in_Gfx_CCR_SGPR_64RegClassID - 448)) | |
| 334 | (1u << (AMDGPU::SGPR_512_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_512_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClassID - 448)) | |
| 335 | (1u << (AMDGPU::SGPR_512_with_sub0_sub1_in_Gfx_CCR_SGPR_64RegClassID - 448)) | |
| 336 | (1u << (AMDGPU::SGPR_512_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_512_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 448)) | |
| 337 | (1u << (AMDGPU::SGPR_512_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_512_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClassID - 448)) | |
| 338 | (1u << (AMDGPU::SGPR_512_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_512_with_sub12_sub13_in_Gfx_CCR_SGPR_64RegClassID - 448)) | |
| 339 | (1u << (AMDGPU::SGPR_512_with_sub12_sub13_in_Gfx_CCR_SGPR_64RegClassID - 448)) | |
| 340 | (1u << (AMDGPU::SGPR_512_with_sub8_sub9_in_Gfx_CCR_SGPR_64_and_SGPR_512_with_sub12_sub13_in_Gfx_CCR_SGPR_64RegClassID - 448)) | |
| 341 | (1u << (AMDGPU::SGPR_512_with_sub4_sub5_in_Gfx_CCR_SGPR_64_and_SGPR_512_with_sub12_sub13_in_Gfx_CCR_SGPR_64RegClassID - 448)) | |
| 342 | (1u << (AMDGPU::SGPR_512_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 448)) | |
| 343 | (1u << (AMDGPU::SGPR_512_with_sub4_sub5_in_Gfx_CCR_SGPR_64_and_SGPR_512_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClassID - 448)) | |
| 344 | (1u << (AMDGPU::SGPR_512_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClassID - 448)) | |
| 345 | (1u << (AMDGPU::TTMP_512RegClassID - 448)) | |
| 346 | 0, |
| 347 | // 480-511 |
| 348 | 0, |
| 349 | // 512-543 |
| 350 | 0, |
| 351 | // 544-575 |
| 352 | (1u << (AMDGPU::SReg_1024RegClassID - 544)) | |
| 353 | (1u << (AMDGPU::SGPR_1024RegClassID - 544)) | |
| 354 | (1u << (AMDGPU::SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64RegClassID - 544)) | |
| 355 | (1u << (AMDGPU::SGPR_1024_with_sub2_sub3_in_CCR_SGPR_64RegClassID - 544)) | |
| 356 | (1u << (AMDGPU::SGPR_1024_with_sub6_sub7_in_CCR_SGPR_64RegClassID - 544)) | |
| 357 | (1u << (AMDGPU::SGPR_1024_with_sub10_sub11_in_CCR_SGPR_64RegClassID - 544)) | |
| 358 | (1u << (AMDGPU::SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_1024_with_sub28_sub29_in_Gfx_CCR_SGPR_64RegClassID - 544)) | |
| 359 | (1u << (AMDGPU::SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_1024_with_sub24_sub25_in_Gfx_CCR_SGPR_64RegClassID - 544)) | |
| 360 | (1u << (AMDGPU::SGPR_1024_with_sub0_sub1_in_Gfx_CCR_SGPR_64RegClassID - 544)) | |
| 361 | (1u << (AMDGPU::SGPR_1024_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 544)) | |
| 362 | (1u << (AMDGPU::SGPR_1024_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClassID - 544)) | |
| 363 | (1u << (AMDGPU::SGPR_1024_with_sub12_sub13_in_Gfx_CCR_SGPR_64RegClassID - 544)) | |
| 364 | (1u << (AMDGPU::SGPR_1024_with_sub12_sub13_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub16_sub17_in_Gfx_CCR_SGPR_64RegClassID - 544)) | |
| 365 | (1u << (AMDGPU::SGPR_1024_with_sub12_sub13_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub20_sub21_in_Gfx_CCR_SGPR_64RegClassID - 544)) | |
| 366 | (1u << (AMDGPU::SGPR_1024_with_sub8_sub9_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub12_sub13_in_Gfx_CCR_SGPR_64RegClassID - 544)) | |
| 367 | (1u << (AMDGPU::SGPR_1024_with_sub16_sub17_in_Gfx_CCR_SGPR_64RegClassID - 544)) | |
| 368 | (1u << (AMDGPU::SGPR_1024_with_sub16_sub17_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub20_sub21_in_Gfx_CCR_SGPR_64RegClassID - 544)) | |
| 369 | (1u << (AMDGPU::SGPR_1024_with_sub16_sub17_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub24_sub25_in_Gfx_CCR_SGPR_64RegClassID - 544)) | |
| 370 | (1u << (AMDGPU::SGPR_1024_with_sub20_sub21_in_Gfx_CCR_SGPR_64RegClassID - 544)) | |
| 371 | (1u << (AMDGPU::SGPR_1024_with_sub20_sub21_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub24_sub25_in_Gfx_CCR_SGPR_64RegClassID - 544)) | |
| 372 | (1u << (AMDGPU::SGPR_1024_with_sub20_sub21_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub28_sub29_in_Gfx_CCR_SGPR_64RegClassID - 544)) | |
| 373 | (1u << (AMDGPU::SGPR_1024_with_sub24_sub25_in_Gfx_CCR_SGPR_64RegClassID - 544)) | |
| 374 | (1u << (AMDGPU::SGPR_1024_with_sub24_sub25_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub28_sub29_in_Gfx_CCR_SGPR_64RegClassID - 544)) | |
| 375 | (1u << (AMDGPU::SGPR_1024_with_sub28_sub29_in_Gfx_CCR_SGPR_64RegClassID - 544)) | |
| 376 | (1u << (AMDGPU::SGPR_1024_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 544)) | |
| 377 | (1u << (AMDGPU::SGPR_1024_with_sub4_sub5_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClassID - 544)) | |
| 378 | (1u << (AMDGPU::SGPR_1024_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClassID - 544)) | |
| 379 | 0, |
| 380 | // 576-607 |
| 381 | (1u << (AMDGPU::SGPR_1024_with_sub14_sub15_in_CCR_SGPR_64RegClassID - 576)) | |
| 382 | (1u << (AMDGPU::SGPR_1024_with_sub18_sub19_in_CCR_SGPR_64RegClassID - 576)) | |
| 383 | (1u << (AMDGPU::SGPR_1024_with_sub22_sub23_in_CCR_SGPR_64RegClassID - 576)) | |
| 384 | (1u << (AMDGPU::SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64_with_sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23_sub24_sub25_sub26_sub27_sub28_sub29_sub30_sub31_in_SGPR_512_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_512_with_sub12_sub13_in_Gfx_CCR_SGPR_64RegClassID - 576)) | |
| 385 | (1u << (AMDGPU::SGPR_1024_with_sub10_sub11_in_CCR_SGPR_64_and_SGPR_1024_with_sub28_sub29_in_Gfx_CCR_SGPR_64RegClassID - 576)) | |
| 386 | (1u << (AMDGPU::SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64_with_sub12_sub13_sub14_sub15_sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23_sub24_sub25_sub26_sub27_in_SGPR_512_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_512_with_sub12_sub13_in_Gfx_CCR_SGPR_64RegClassID - 576)) | |
| 387 | (1u << (AMDGPU::SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64_with_sub12_lo16_sub12_hi16_sub13_lo16_sub13_hi16_sub14_lo16_sub14_hi16_sub15_lo16_sub15_hi16_sub16_lo16_sub16_hi16_sub17_lo16_sub17_hi16_sub18_lo16_sub18_hi16_sub19_lo16_sub19_hi16_sub20_lo16_sub20_hi16_sub21_lo16_sub21_hi16_sub22_lo16_sub22_hi16_sub23_lo16_sub23_hi16_in_SGPR_384_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_384_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClassID - 576)) | |
| 388 | (1u << (AMDGPU::SGPR_1024_with_sub6_sub7_in_CCR_SGPR_64_and_SGPR_1024_with_sub28_sub29_in_Gfx_CCR_SGPR_64RegClassID - 576)) | |
| 389 | (1u << (AMDGPU::SGPR_1024_with_sub6_sub7_in_CCR_SGPR_64_and_SGPR_1024_with_sub24_sub25_in_Gfx_CCR_SGPR_64RegClassID - 576)) | |
| 390 | (1u << (AMDGPU::SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64_with_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23_in_SGPR_512_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_512_with_sub12_sub13_in_Gfx_CCR_SGPR_64RegClassID - 576)) | |
| 391 | (1u << (AMDGPU::SGPR_1024_with_sub2_sub3_in_CCR_SGPR_64_and_SGPR_1024_with_sub28_sub29_in_Gfx_CCR_SGPR_64RegClassID - 576)) | |
| 392 | (1u << (AMDGPU::SGPR_1024_with_sub2_sub3_in_CCR_SGPR_64_and_SGPR_1024_with_sub24_sub25_in_Gfx_CCR_SGPR_64RegClassID - 576)) | |
| 393 | (1u << (AMDGPU::SGPR_1024_with_sub2_sub3_in_CCR_SGPR_64_and_SGPR_1024_with_sub20_sub21_in_Gfx_CCR_SGPR_64RegClassID - 576)) | |
| 394 | (1u << (AMDGPU::SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64_with_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_sub16_sub17_sub18_sub19_in_SGPR_512_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_512_with_sub12_sub13_in_Gfx_CCR_SGPR_64RegClassID - 576)) | |
| 395 | (1u << (AMDGPU::SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_1024_with_sub20_sub21_in_Gfx_CCR_SGPR_64RegClassID - 576)) | |
| 396 | (1u << (AMDGPU::SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_1024_with_sub16_sub17_in_Gfx_CCR_SGPR_64RegClassID - 576)) | |
| 397 | (1u << (AMDGPU::SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_1024_with_sub12_sub13_in_Gfx_CCR_SGPR_64RegClassID - 576)) | |
| 398 | (1u << (AMDGPU::SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_1024_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClassID - 576)) | |
| 399 | (1u << (AMDGPU::SGPR_1024_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub12_sub13_in_Gfx_CCR_SGPR_64RegClassID - 576)) | |
| 400 | (1u << (AMDGPU::SGPR_1024_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub16_sub17_in_Gfx_CCR_SGPR_64RegClassID - 576)) | |
| 401 | (1u << (AMDGPU::SGPR_1024_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub20_sub21_in_Gfx_CCR_SGPR_64RegClassID - 576)) | |
| 402 | (1u << (AMDGPU::SGPR_1024_with_sub12_sub13_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub24_sub25_in_Gfx_CCR_SGPR_64RegClassID - 576)) | |
| 403 | (1u << (AMDGPU::SGPR_1024_with_sub12_sub13_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub28_sub29_in_Gfx_CCR_SGPR_64RegClassID - 576)) | |
| 404 | (1u << (AMDGPU::SGPR_1024_with_sub8_sub9_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub28_sub29_in_Gfx_CCR_SGPR_64RegClassID - 576)) | |
| 405 | (1u << (AMDGPU::SGPR_1024_with_sub8_sub9_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub24_sub25_in_Gfx_CCR_SGPR_64RegClassID - 576)) | |
| 406 | (1u << (AMDGPU::SGPR_1024_with_sub4_sub5_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub24_sub25_in_Gfx_CCR_SGPR_64RegClassID - 576)) | |
| 407 | (1u << (AMDGPU::SGPR_1024_with_sub8_sub9_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub20_sub21_in_Gfx_CCR_SGPR_64RegClassID - 576)) | |
| 408 | (1u << (AMDGPU::SGPR_1024_with_sub4_sub5_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub20_sub21_in_Gfx_CCR_SGPR_64RegClassID - 576)) | |
| 409 | (1u << (AMDGPU::SGPR_1024_with_sub8_sub9_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub16_sub17_in_Gfx_CCR_SGPR_64RegClassID - 576)) | |
| 410 | (1u << (AMDGPU::SGPR_1024_with_sub4_sub5_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub16_sub17_in_Gfx_CCR_SGPR_64RegClassID - 576)) | |
| 411 | (1u << (AMDGPU::SGPR_1024_with_sub4_sub5_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub12_sub13_in_Gfx_CCR_SGPR_64RegClassID - 576)) | |
| 412 | (1u << (AMDGPU::SGPR_1024_with_sub16_sub17_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub28_sub29_in_Gfx_CCR_SGPR_64RegClassID - 576)) | |
| 413 | 0, |
| 414 | // 608-639 |
| 415 | (1u << (AMDGPU::SGPR_1024_with_sub26_sub27_in_CCR_SGPR_64RegClassID - 608)) | |
| 416 | (1u << (AMDGPU::SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64_with_sub20_lo16_sub20_hi16_sub21_lo16_sub21_hi16_sub22_lo16_sub22_hi16_sub23_lo16_sub23_hi16_sub24_lo16_sub24_hi16_sub25_lo16_sub25_hi16_sub26_lo16_sub26_hi16_sub27_lo16_sub27_hi16_sub28_lo16_sub28_hi16_sub29_lo16_sub29_hi16_sub30_lo16_sub30_hi16_sub31_lo16_sub31_hi16_in_SGPR_384_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_384_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClassID - 608)) | |
| 417 | (1u << (AMDGPU::SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64_with_sub16_lo16_sub16_hi16_sub17_lo16_sub17_hi16_sub18_lo16_sub18_hi16_sub19_lo16_sub19_hi16_sub20_lo16_sub20_hi16_sub21_lo16_sub21_hi16_sub22_lo16_sub22_hi16_sub23_lo16_sub23_hi16_sub24_lo16_sub24_hi16_sub25_lo16_sub25_hi16_sub26_lo16_sub26_hi16_sub27_lo16_sub27_hi16_in_SGPR_384_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_384_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClassID - 608)) | |
| 418 | (1u << (AMDGPU::SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64_with_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16_sub12_lo16_sub12_hi16_sub13_lo16_sub13_hi16_sub14_lo16_sub14_hi16_sub15_lo16_sub15_hi16_sub16_lo16_sub16_hi16_sub17_lo16_sub17_hi16_sub18_lo16_sub18_hi16_sub19_lo16_sub19_hi16_in_SGPR_384_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_384_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClassID - 608)) | |
| 419 | (1u << (AMDGPU::SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64_with_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16_sub12_lo16_sub12_hi16_sub13_lo16_sub13_hi16_sub14_lo16_sub14_hi16_sub15_lo16_sub15_hi16_in_SGPR_384_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_384_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClassID - 608)) | |
| 420 | (1u << (AMDGPU::SGPR_1024_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub24_sub25_in_Gfx_CCR_SGPR_64RegClassID - 608)) | |
| 421 | (1u << (AMDGPU::SGPR_1024_with_sub4_sub5_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub28_sub29_in_Gfx_CCR_SGPR_64RegClassID - 608)) | |
| 422 | 0, |
| 423 | }; |
| 424 | const uint32_t VCCRegBankCoverageData[] = { |
| 425 | // 0-31 |
| 426 | (1u << (AMDGPU::SReg_1RegClassID - 0)) | |
| 427 | (1u << (AMDGPU::SReg_1_XEXECRegClassID - 0)) | |
| 428 | (1u << (AMDGPU::SReg_1_with_lo16_in_SGPR_LO16RegClassID - 0)) | |
| 429 | (1u << (AMDGPU::SReg_1_with_sub0_and_SReg_1_with_lo16_in_SGPR_LO16RegClassID - 0)) | |
| 430 | (1u << (AMDGPU::VReg_1RegClassID - 0)) | |
| 431 | (1u << (AMDGPU::VS_16RegClassID - 0)) | |
| 432 | (1u << (AMDGPU::VS_16_Lo128RegClassID - 0)) | |
| 433 | (1u << (AMDGPU::SReg_LO16RegClassID - 0)) | |
| 434 | (1u << (AMDGPU::VS_16_and_SReg_1RegClassID - 0)) | |
| 435 | (1u << (AMDGPU::VS_16_and_SReg_1_XEXECRegClassID - 0)) | |
| 436 | (1u << (AMDGPU::SGPR_LO16RegClassID - 0)) | |
| 437 | (1u << (AMDGPU::VS_16_and_SReg_1_with_lo16_in_SGPR_LO16RegClassID - 0)) | |
| 438 | (1u << (AMDGPU::VS_32RegClassID - 0)) | |
| 439 | (1u << (AMDGPU::VS_32_with_hi16RegClassID - 0)) | |
| 440 | (1u << (AMDGPU::VS_32_Lo128RegClassID - 0)) | |
| 441 | (1u << (AMDGPU::VS_32_Lo128_with_hi16RegClassID - 0)) | |
| 442 | (1u << (AMDGPU::SReg_1_XEXEC_with_sub0RegClassID - 0)) | |
| 443 | (1u << (AMDGPU::SReg_1_with_sub0_and_SReg_1_with_lo16_in_TTMP_LO16RegClassID - 0)) | |
| 444 | (1u << (AMDGPU::SReg_1_with_lo16_in_TTMP_LO16RegClassID - 0)) | |
| 445 | (1u << (AMDGPU::TTMP_LO16RegClassID - 0)) | |
| 446 | (1u << (AMDGPU::VS_16_and_SReg_1_with_lo16_in_TTMP_LO16RegClassID - 0)) | |
| 447 | (1u << (AMDGPU::SReg_1_with_lo16_in_M0_CLASS_LO16RegClassID - 0)) | |
| 448 | (1u << (AMDGPU::M0_CLASS_LO16RegClassID - 0)) | |
| 449 | (1u << (AMDGPU::SReg_1_with_sub0RegClassID - 0)) | |
| 450 | 0, |
| 451 | // 32-63 |
| 452 | (1u << (AMDGPU::SRegOrLds_32RegClassID - 32)) | |
| 453 | (1u << (AMDGPU::SReg_32RegClassID - 32)) | |
| 454 | (1u << (AMDGPU::SReg_32_XEXEC_HIRegClassID - 32)) | |
| 455 | (1u << (AMDGPU::SReg_32_XM0RegClassID - 32)) | |
| 456 | (1u << (AMDGPU::SReg_32_XEXECRegClassID - 32)) | |
| 457 | (1u << (AMDGPU::SReg_32_XEXEC_HI_and_SReg_32_XM0RegClassID - 32)) | |
| 458 | (1u << (AMDGPU::SReg_32_XM0_XEXECRegClassID - 32)) | |
| 459 | (1u << (AMDGPU::SGPR_32RegClassID - 32)) | |
| 460 | (1u << (AMDGPU::TTMP_32RegClassID - 32)) | |
| 461 | (1u << (AMDGPU::SReg_64_XEXECRegClassID - 32)) | |
| 462 | (1u << (AMDGPU::SReg_64_XEXEC_XNULLRegClassID - 32)) | |
| 463 | (1u << (AMDGPU::M0_CLASSRegClassID - 32)) | |
| 464 | (1u << (AMDGPU::SReg_64RegClassID - 32)) | |
| 465 | 0, |
| 466 | // 64-95 |
| 467 | (1u << (AMDGPU::SGPR_64RegClassID - 64)) | |
| 468 | (1u << (AMDGPU::CCR_SGPR_64RegClassID - 64)) | |
| 469 | (1u << (AMDGPU::Gfx_CCR_SGPR_64RegClassID - 64)) | |
| 470 | (1u << (AMDGPU::TTMP_64RegClassID - 64)) | |
| 471 | 0, |
| 472 | // 96-127 |
| 473 | 0, |
| 474 | // 128-159 |
| 475 | 0, |
| 476 | // 160-191 |
| 477 | 0, |
| 478 | // 192-223 |
| 479 | 0, |
| 480 | // 224-255 |
| 481 | 0, |
| 482 | // 256-287 |
| 483 | 0, |
| 484 | // 288-319 |
| 485 | 0, |
| 486 | // 320-351 |
| 487 | 0, |
| 488 | // 352-383 |
| 489 | 0, |
| 490 | // 384-415 |
| 491 | 0, |
| 492 | // 416-447 |
| 493 | 0, |
| 494 | // 448-479 |
| 495 | 0, |
| 496 | // 480-511 |
| 497 | 0, |
| 498 | // 512-543 |
| 499 | 0, |
| 500 | // 544-575 |
| 501 | 0, |
| 502 | // 576-607 |
| 503 | 0, |
| 504 | // 608-639 |
| 505 | 0, |
| 506 | }; |
| 507 | const uint32_t VGPRRegBankCoverageData[] = { |
| 508 | // 0-31 |
| 509 | (1u << (AMDGPU::VGPR_16_Lo128RegClassID - 0)) | |
| 510 | (1u << (AMDGPU::VGPR_16RegClassID - 0)) | |
| 511 | (1u << (AMDGPU::VS_16RegClassID - 0)) | |
| 512 | (1u << (AMDGPU::VS_16_Lo128RegClassID - 0)) | |
| 513 | (1u << (AMDGPU::AV_32RegClassID - 0)) | |
| 514 | (1u << (AMDGPU::VS_32RegClassID - 0)) | |
| 515 | (1u << (AMDGPU::VS_32_with_hi16RegClassID - 0)) | |
| 516 | (1u << (AMDGPU::VRegOrLds_32RegClassID - 0)) | |
| 517 | (1u << (AMDGPU::VS_32_Lo128RegClassID - 0)) | |
| 518 | (1u << (AMDGPU::VS_32_Lo128_with_hi16RegClassID - 0)) | |
| 519 | 0, |
| 520 | // 32-63 |
| 521 | (1u << (AMDGPU::VGPR_32RegClassID - 32)) | |
| 522 | (1u << (AMDGPU::VGPR_32_Lo128RegClassID - 32)) | |
| 523 | (1u << (AMDGPU::VReg_64RegClassID - 32)) | |
| 524 | (1u << (AMDGPU::AV_64_with_hi16_in_VGPR_16_Lo128RegClassID - 32)) | |
| 525 | (1u << (AMDGPU::VRegOrLds_32_and_VS_32_Lo128RegClassID - 32)) | |
| 526 | (1u << (AMDGPU::AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 32)) | |
| 527 | (1u << (AMDGPU::AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID - 32)) | |
| 528 | (1u << (AMDGPU::VReg_64_Align2RegClassID - 32)) | |
| 529 | (1u << (AMDGPU::AV_64RegClassID - 32)) | |
| 530 | (1u << (AMDGPU::VS_64RegClassID - 32)) | |
| 531 | (1u << (AMDGPU::VS_64_with_sub0_in_VS_32_Lo128RegClassID - 32)) | |
| 532 | (1u << (AMDGPU::VS_64_with_sub1_in_VS_32_Lo128RegClassID - 32)) | |
| 533 | (1u << (AMDGPU::AV_64_Align2RegClassID - 32)) | |
| 534 | 0, |
| 535 | // 64-95 |
| 536 | (1u << (AMDGPU::VReg_96RegClassID - 64)) | |
| 537 | (1u << (AMDGPU::AV_96_with_hi16_in_VGPR_16_Lo128RegClassID - 64)) | |
| 538 | (1u << (AMDGPU::AV_96_with_sub1_in_VGPR_32_Lo128RegClassID - 64)) | |
| 539 | (1u << (AMDGPU::AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 64)) | |
| 540 | (1u << (AMDGPU::AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 64)) | |
| 541 | (1u << (AMDGPU::AV_96_with_sub1_sub2_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID - 64)) | |
| 542 | (1u << (AMDGPU::AV_96_with_sub0_sub1_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID - 64)) | |
| 543 | (1u << (AMDGPU::AV_96_with_hi16_in_VGPR_16_Lo128_and_AV_96_with_sub1_sub2_in_AV_64_Align2RegClassID - 64)) | |
| 544 | (1u << (AMDGPU::AV_96_with_sub1_sub2_in_VReg_64_Align2RegClassID - 64)) | |
| 545 | (1u << (AMDGPU::VReg_96_Align2RegClassID - 64)) | |
| 546 | (1u << (AMDGPU::VReg_128RegClassID - 64)) | |
| 547 | (1u << (AMDGPU::AV_96RegClassID - 64)) | |
| 548 | (1u << (AMDGPU::AV_128_with_hi16_in_VGPR_16_Lo128RegClassID - 64)) | |
| 549 | (1u << (AMDGPU::AV_96_Align2RegClassID - 64)) | |
| 550 | (1u << (AMDGPU::AV_96_with_sub1_sub2_in_AV_64_Align2RegClassID - 64)) | |
| 551 | (1u << (AMDGPU::AV_128RegClassID - 64)) | |
| 552 | (1u << (AMDGPU::AV_128_Align2RegClassID - 64)) | |
| 553 | (1u << (AMDGPU::AV_128_with_sub1_sub2_in_AV_64_Align2RegClassID - 64)) | |
| 554 | 0, |
| 555 | // 96-127 |
| 556 | (1u << (AMDGPU::AV_128_with_sub1_in_VGPR_32_Lo128RegClassID - 96)) | |
| 557 | (1u << (AMDGPU::AV_128_with_sub2_in_VGPR_32_Lo128RegClassID - 96)) | |
| 558 | (1u << (AMDGPU::AV_128_with_sub3_in_VGPR_32_Lo128RegClassID - 96)) | |
| 559 | (1u << (AMDGPU::AV_128_with_sub0_sub1_sub2_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 96)) | |
| 560 | (1u << (AMDGPU::AV_128_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 96)) | |
| 561 | (1u << (AMDGPU::AV_128_with_sub1_sub2_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID - 96)) | |
| 562 | (1u << (AMDGPU::AV_128_with_sub0_sub1_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID - 96)) | |
| 563 | (1u << (AMDGPU::AV_128_with_hi16_in_VGPR_16_Lo128_and_AV_128_with_sub1_sub2_in_AV_64_Align2RegClassID - 96)) | |
| 564 | (1u << (AMDGPU::VReg_128_Align2RegClassID - 96)) | |
| 565 | (1u << (AMDGPU::AV_128_with_sub1_sub2_in_VReg_64_Align2RegClassID - 96)) | |
| 566 | (1u << (AMDGPU::VReg_160RegClassID - 96)) | |
| 567 | (1u << (AMDGPU::AV_160_with_hi16_in_VGPR_16_Lo128RegClassID - 96)) | |
| 568 | (1u << (AMDGPU::AV_160_with_sub1_in_VGPR_32_Lo128RegClassID - 96)) | |
| 569 | (1u << (AMDGPU::AV_160_with_sub2_in_VGPR_32_Lo128RegClassID - 96)) | |
| 570 | (1u << (AMDGPU::AV_160_with_sub3_in_VGPR_32_Lo128RegClassID - 96)) | |
| 571 | (1u << (AMDGPU::AV_160_with_sub1_sub2_in_VReg_64_Align2RegClassID - 96)) | |
| 572 | (1u << (AMDGPU::VReg_160_Align2RegClassID - 96)) | |
| 573 | (1u << (AMDGPU::AV_160RegClassID - 96)) | |
| 574 | (1u << (AMDGPU::AV_160_Align2RegClassID - 96)) | |
| 575 | (1u << (AMDGPU::AV_160_with_sub1_sub2_in_AV_64_Align2RegClassID - 96)) | |
| 576 | 0, |
| 577 | // 128-159 |
| 578 | (1u << (AMDGPU::AV_160_with_sub4_in_VGPR_32_Lo128RegClassID - 128)) | |
| 579 | (1u << (AMDGPU::AV_160_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 128)) | |
| 580 | (1u << (AMDGPU::AV_160_with_sub2_sub3_sub4_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 128)) | |
| 581 | (1u << (AMDGPU::AV_160_with_sub0_sub1_sub2_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 128)) | |
| 582 | (1u << (AMDGPU::AV_160_with_sub1_sub2_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID - 128)) | |
| 583 | (1u << (AMDGPU::AV_160_with_sub0_sub1_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID - 128)) | |
| 584 | (1u << (AMDGPU::AV_160_with_hi16_in_VGPR_16_Lo128_and_AV_160_with_sub1_sub2_in_AV_64_Align2RegClassID - 128)) | |
| 585 | (1u << (AMDGPU::VReg_192RegClassID - 128)) | |
| 586 | (1u << (AMDGPU::AV_192_with_hi16_in_VGPR_16_Lo128RegClassID - 128)) | |
| 587 | (1u << (AMDGPU::AV_192_with_sub1_in_VGPR_32_Lo128RegClassID - 128)) | |
| 588 | (1u << (AMDGPU::AV_192_with_sub2_in_VGPR_32_Lo128RegClassID - 128)) | |
| 589 | (1u << (AMDGPU::AV_192_with_sub3_in_VGPR_32_Lo128RegClassID - 128)) | |
| 590 | (1u << (AMDGPU::AV_192_with_sub4_in_VGPR_32_Lo128RegClassID - 128)) | |
| 591 | (1u << (AMDGPU::AV_192_with_sub5_in_VGPR_32_Lo128RegClassID - 128)) | |
| 592 | (1u << (AMDGPU::AV_192_with_sub0_sub1_sub2_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 128)) | |
| 593 | (1u << (AMDGPU::AV_192_with_sub1_sub2_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID - 128)) | |
| 594 | (1u << (AMDGPU::AV_192_with_sub0_sub1_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID - 128)) | |
| 595 | (1u << (AMDGPU::AV_192_with_hi16_in_VGPR_16_Lo128_and_AV_192_with_sub1_sub2_in_AV_64_Align2RegClassID - 128)) | |
| 596 | (1u << (AMDGPU::VReg_192_Align2RegClassID - 128)) | |
| 597 | (1u << (AMDGPU::AV_192_with_sub1_sub2_in_VReg_64_Align2RegClassID - 128)) | |
| 598 | (1u << (AMDGPU::AV_192RegClassID - 128)) | |
| 599 | (1u << (AMDGPU::AV_192_Align2RegClassID - 128)) | |
| 600 | (1u << (AMDGPU::AV_192_with_sub1_sub2_in_AV_64_Align2RegClassID - 128)) | |
| 601 | 0, |
| 602 | // 160-191 |
| 603 | (1u << (AMDGPU::AV_192_with_sub2_sub3_sub4_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 160)) | |
| 604 | (1u << (AMDGPU::AV_192_with_sub3_sub4_sub5_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 160)) | |
| 605 | (1u << (AMDGPU::AV_192_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 160)) | |
| 606 | (1u << (AMDGPU::VReg_224RegClassID - 160)) | |
| 607 | (1u << (AMDGPU::AV_224_with_hi16_in_VGPR_16_Lo128RegClassID - 160)) | |
| 608 | (1u << (AMDGPU::AV_224_with_sub1_in_VGPR_32_Lo128RegClassID - 160)) | |
| 609 | (1u << (AMDGPU::AV_224_with_sub2_in_VGPR_32_Lo128RegClassID - 160)) | |
| 610 | (1u << (AMDGPU::AV_224_with_sub3_in_VGPR_32_Lo128RegClassID - 160)) | |
| 611 | (1u << (AMDGPU::AV_224_with_sub4_in_VGPR_32_Lo128RegClassID - 160)) | |
| 612 | (1u << (AMDGPU::AV_224_with_sub5_in_VGPR_32_Lo128RegClassID - 160)) | |
| 613 | (1u << (AMDGPU::AV_224_with_sub6_in_VGPR_32_Lo128RegClassID - 160)) | |
| 614 | (1u << (AMDGPU::AV_224_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 160)) | |
| 615 | (1u << (AMDGPU::AV_224_with_sub0_sub1_sub2_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 160)) | |
| 616 | (1u << (AMDGPU::AV_224_with_sub1_sub2_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID - 160)) | |
| 617 | (1u << (AMDGPU::AV_224_with_sub0_sub1_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID - 160)) | |
| 618 | (1u << (AMDGPU::AV_224_with_hi16_in_VGPR_16_Lo128_and_AV_224_with_sub1_sub2_in_AV_64_Align2RegClassID - 160)) | |
| 619 | (1u << (AMDGPU::AV_224_with_sub1_sub2_in_VReg_64_Align2RegClassID - 160)) | |
| 620 | (1u << (AMDGPU::VReg_224_Align2RegClassID - 160)) | |
| 621 | (1u << (AMDGPU::AV_224RegClassID - 160)) | |
| 622 | (1u << (AMDGPU::AV_224_Align2RegClassID - 160)) | |
| 623 | (1u << (AMDGPU::AV_224_with_sub1_sub2_in_AV_64_Align2RegClassID - 160)) | |
| 624 | 0, |
| 625 | // 192-223 |
| 626 | (1u << (AMDGPU::AV_224_with_sub3_sub4_sub5_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 192)) | |
| 627 | (1u << (AMDGPU::AV_224_with_sub4_sub5_sub6_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 192)) | |
| 628 | (1u << (AMDGPU::AV_224_with_sub2_sub3_sub4_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 192)) | |
| 629 | (1u << (AMDGPU::VReg_256RegClassID - 192)) | |
| 630 | (1u << (AMDGPU::AV_256_with_hi16_in_VGPR_16_Lo128RegClassID - 192)) | |
| 631 | (1u << (AMDGPU::AV_256_with_sub1_in_VGPR_32_Lo128RegClassID - 192)) | |
| 632 | (1u << (AMDGPU::AV_256_with_sub2_in_VGPR_32_Lo128RegClassID - 192)) | |
| 633 | (1u << (AMDGPU::AV_256_with_sub3_in_VGPR_32_Lo128RegClassID - 192)) | |
| 634 | (1u << (AMDGPU::AV_256_with_sub4_in_VGPR_32_Lo128RegClassID - 192)) | |
| 635 | (1u << (AMDGPU::AV_256_with_sub5_in_VGPR_32_Lo128RegClassID - 192)) | |
| 636 | (1u << (AMDGPU::AV_256_with_sub6_in_VGPR_32_Lo128RegClassID - 192)) | |
| 637 | (1u << (AMDGPU::AV_256_with_sub7_in_VGPR_32_Lo128RegClassID - 192)) | |
| 638 | (1u << (AMDGPU::AV_256_with_sub0_sub1_sub2_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 192)) | |
| 639 | (1u << (AMDGPU::AV_256_with_sub1_sub2_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID - 192)) | |
| 640 | (1u << (AMDGPU::AV_256_with_sub0_sub1_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID - 192)) | |
| 641 | (1u << (AMDGPU::AV_256_with_hi16_in_VGPR_16_Lo128_and_AV_256_with_sub1_sub2_in_AV_64_Align2RegClassID - 192)) | |
| 642 | (1u << (AMDGPU::VReg_256_Align2RegClassID - 192)) | |
| 643 | (1u << (AMDGPU::AV_256_with_sub1_sub2_in_VReg_64_Align2RegClassID - 192)) | |
| 644 | (1u << (AMDGPU::AV_256RegClassID - 192)) | |
| 645 | (1u << (AMDGPU::AV_256_Align2RegClassID - 192)) | |
| 646 | (1u << (AMDGPU::AV_256_with_sub1_sub2_in_AV_64_Align2RegClassID - 192)) | |
| 647 | 0, |
| 648 | // 224-255 |
| 649 | (1u << (AMDGPU::AV_256_with_sub4_sub5_sub6_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 224)) | |
| 650 | (1u << (AMDGPU::AV_256_with_sub5_sub6_sub7_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 224)) | |
| 651 | (1u << (AMDGPU::AV_256_with_sub3_sub4_sub5_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 224)) | |
| 652 | (1u << (AMDGPU::AV_256_with_sub2_sub3_sub4_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 224)) | |
| 653 | (1u << (AMDGPU::AV_256_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 224)) | |
| 654 | (1u << (AMDGPU::VReg_288RegClassID - 224)) | |
| 655 | (1u << (AMDGPU::AV_288_with_hi16_in_VGPR_16_Lo128RegClassID - 224)) | |
| 656 | (1u << (AMDGPU::AV_288_with_sub1_in_VGPR_32_Lo128RegClassID - 224)) | |
| 657 | (1u << (AMDGPU::AV_288_with_sub2_in_VGPR_32_Lo128RegClassID - 224)) | |
| 658 | (1u << (AMDGPU::AV_288_with_sub3_in_VGPR_32_Lo128RegClassID - 224)) | |
| 659 | (1u << (AMDGPU::AV_288_with_sub4_in_VGPR_32_Lo128RegClassID - 224)) | |
| 660 | (1u << (AMDGPU::AV_288_with_sub5_in_VGPR_32_Lo128RegClassID - 224)) | |
| 661 | (1u << (AMDGPU::AV_288_with_sub6_in_VGPR_32_Lo128RegClassID - 224)) | |
| 662 | (1u << (AMDGPU::AV_288_with_sub7_in_VGPR_32_Lo128RegClassID - 224)) | |
| 663 | (1u << (AMDGPU::AV_288_with_sub1_sub2_in_VReg_64_Align2RegClassID - 224)) | |
| 664 | (1u << (AMDGPU::VReg_288_Align2RegClassID - 224)) | |
| 665 | (1u << (AMDGPU::AV_288RegClassID - 224)) | |
| 666 | (1u << (AMDGPU::AV_288_Align2RegClassID - 224)) | |
| 667 | (1u << (AMDGPU::AV_288_with_sub1_sub2_in_AV_64_Align2RegClassID - 224)) | |
| 668 | 0, |
| 669 | // 256-287 |
| 670 | (1u << (AMDGPU::AV_288_with_sub8_in_VGPR_32_Lo128RegClassID - 256)) | |
| 671 | (1u << (AMDGPU::AV_288_with_sub5_sub6_sub7_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 256)) | |
| 672 | (1u << (AMDGPU::AV_288_with_sub6_sub7_sub8_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 256)) | |
| 673 | (1u << (AMDGPU::AV_288_with_sub4_sub5_sub6_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 256)) | |
| 674 | (1u << (AMDGPU::AV_288_with_sub3_sub4_sub5_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 256)) | |
| 675 | (1u << (AMDGPU::AV_288_with_sub2_sub3_sub4_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 256)) | |
| 676 | (1u << (AMDGPU::AV_288_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 256)) | |
| 677 | (1u << (AMDGPU::AV_288_with_sub0_sub1_sub2_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 256)) | |
| 678 | (1u << (AMDGPU::AV_288_with_sub1_sub2_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID - 256)) | |
| 679 | (1u << (AMDGPU::AV_288_with_sub0_sub1_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID - 256)) | |
| 680 | (1u << (AMDGPU::AV_288_with_hi16_in_VGPR_16_Lo128_and_AV_288_with_sub1_sub2_in_AV_64_Align2RegClassID - 256)) | |
| 681 | (1u << (AMDGPU::VReg_320RegClassID - 256)) | |
| 682 | (1u << (AMDGPU::AV_320_with_hi16_in_VGPR_16_Lo128RegClassID - 256)) | |
| 683 | (1u << (AMDGPU::AV_320_with_sub1_in_VGPR_32_Lo128RegClassID - 256)) | |
| 684 | (1u << (AMDGPU::AV_320_with_sub2_in_VGPR_32_Lo128RegClassID - 256)) | |
| 685 | (1u << (AMDGPU::AV_320_with_sub3_in_VGPR_32_Lo128RegClassID - 256)) | |
| 686 | (1u << (AMDGPU::AV_320_with_sub4_in_VGPR_32_Lo128RegClassID - 256)) | |
| 687 | (1u << (AMDGPU::VReg_320_Align2RegClassID - 256)) | |
| 688 | (1u << (AMDGPU::AV_320RegClassID - 256)) | |
| 689 | (1u << (AMDGPU::AV_320_Align2RegClassID - 256)) | |
| 690 | (1u << (AMDGPU::AV_320_with_sub1_sub2_in_AV_64_Align2RegClassID - 256)) | |
| 691 | 0, |
| 692 | // 288-319 |
| 693 | (1u << (AMDGPU::AV_320_with_sub5_in_VGPR_32_Lo128RegClassID - 288)) | |
| 694 | (1u << (AMDGPU::AV_320_with_sub6_in_VGPR_32_Lo128RegClassID - 288)) | |
| 695 | (1u << (AMDGPU::AV_320_with_sub7_in_VGPR_32_Lo128RegClassID - 288)) | |
| 696 | (1u << (AMDGPU::AV_320_with_sub8_in_VGPR_32_Lo128RegClassID - 288)) | |
| 697 | (1u << (AMDGPU::AV_320_with_sub9_in_VGPR_32_Lo128RegClassID - 288)) | |
| 698 | (1u << (AMDGPU::AV_320_with_sub6_sub7_sub8_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 288)) | |
| 699 | (1u << (AMDGPU::AV_320_with_sub7_sub8_sub9_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 288)) | |
| 700 | (1u << (AMDGPU::AV_320_with_sub5_sub6_sub7_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 288)) | |
| 701 | (1u << (AMDGPU::AV_320_with_sub4_sub5_sub6_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 288)) | |
| 702 | (1u << (AMDGPU::AV_320_with_sub3_sub4_sub5_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 288)) | |
| 703 | (1u << (AMDGPU::AV_320_with_sub2_sub3_sub4_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 288)) | |
| 704 | (1u << (AMDGPU::AV_320_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 288)) | |
| 705 | (1u << (AMDGPU::AV_320_with_sub0_sub1_sub2_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 288)) | |
| 706 | (1u << (AMDGPU::AV_320_with_sub1_sub2_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID - 288)) | |
| 707 | (1u << (AMDGPU::AV_320_with_sub0_sub1_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID - 288)) | |
| 708 | (1u << (AMDGPU::AV_320_with_hi16_in_VGPR_16_Lo128_and_AV_320_with_sub1_sub2_in_AV_64_Align2RegClassID - 288)) | |
| 709 | (1u << (AMDGPU::AV_320_with_sub1_sub2_in_VReg_64_Align2RegClassID - 288)) | |
| 710 | (1u << (AMDGPU::AV_352RegClassID - 288)) | |
| 711 | 0, |
| 712 | // 320-351 |
| 713 | (1u << (AMDGPU::VReg_352RegClassID - 320)) | |
| 714 | (1u << (AMDGPU::AV_352_with_hi16_in_VGPR_16_Lo128RegClassID - 320)) | |
| 715 | (1u << (AMDGPU::AV_352_with_sub1_in_VGPR_32_Lo128RegClassID - 320)) | |
| 716 | (1u << (AMDGPU::AV_352_with_sub2_in_VGPR_32_Lo128RegClassID - 320)) | |
| 717 | (1u << (AMDGPU::AV_352_with_sub3_in_VGPR_32_Lo128RegClassID - 320)) | |
| 718 | (1u << (AMDGPU::AV_352_with_sub4_in_VGPR_32_Lo128RegClassID - 320)) | |
| 719 | (1u << (AMDGPU::AV_352_with_sub5_in_VGPR_32_Lo128RegClassID - 320)) | |
| 720 | (1u << (AMDGPU::AV_352_with_sub6_in_VGPR_32_Lo128RegClassID - 320)) | |
| 721 | (1u << (AMDGPU::AV_352_with_sub7_in_VGPR_32_Lo128RegClassID - 320)) | |
| 722 | (1u << (AMDGPU::AV_352_with_sub8_in_VGPR_32_Lo128RegClassID - 320)) | |
| 723 | (1u << (AMDGPU::AV_352_with_sub9_in_VGPR_32_Lo128RegClassID - 320)) | |
| 724 | (1u << (AMDGPU::AV_352_with_sub10_in_VGPR_32_Lo128RegClassID - 320)) | |
| 725 | (1u << (AMDGPU::AV_352_with_sub7_sub8_sub9_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 320)) | |
| 726 | (1u << (AMDGPU::AV_352_with_sub8_sub9_sub10_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 320)) | |
| 727 | (1u << (AMDGPU::AV_352_with_sub6_sub7_sub8_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 320)) | |
| 728 | (1u << (AMDGPU::AV_352_with_sub5_sub6_sub7_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 320)) | |
| 729 | (1u << (AMDGPU::AV_352_with_sub4_sub5_sub6_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 320)) | |
| 730 | (1u << (AMDGPU::AV_352_with_sub3_sub4_sub5_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 320)) | |
| 731 | (1u << (AMDGPU::AV_352_with_sub2_sub3_sub4_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 320)) | |
| 732 | (1u << (AMDGPU::AV_352_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 320)) | |
| 733 | (1u << (AMDGPU::AV_352_with_sub0_sub1_sub2_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 320)) | |
| 734 | (1u << (AMDGPU::AV_352_with_sub1_sub2_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID - 320)) | |
| 735 | (1u << (AMDGPU::AV_352_with_sub0_sub1_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID - 320)) | |
| 736 | (1u << (AMDGPU::AV_352_with_hi16_in_VGPR_16_Lo128_and_AV_352_with_sub1_sub2_in_AV_64_Align2RegClassID - 320)) | |
| 737 | (1u << (AMDGPU::AV_352_with_sub1_sub2_in_VReg_64_Align2RegClassID - 320)) | |
| 738 | (1u << (AMDGPU::VReg_352_Align2RegClassID - 320)) | |
| 739 | (1u << (AMDGPU::AV_352_Align2RegClassID - 320)) | |
| 740 | (1u << (AMDGPU::AV_352_with_sub1_sub2_in_AV_64_Align2RegClassID - 320)) | |
| 741 | 0, |
| 742 | // 352-383 |
| 743 | (1u << (AMDGPU::VReg_384RegClassID - 352)) | |
| 744 | (1u << (AMDGPU::AV_384_with_hi16_in_VGPR_16_Lo128RegClassID - 352)) | |
| 745 | (1u << (AMDGPU::AV_384_with_sub1_in_VGPR_32_Lo128RegClassID - 352)) | |
| 746 | (1u << (AMDGPU::AV_384_with_sub2_in_VGPR_32_Lo128RegClassID - 352)) | |
| 747 | (1u << (AMDGPU::AV_384_with_sub3_in_VGPR_32_Lo128RegClassID - 352)) | |
| 748 | (1u << (AMDGPU::AV_384_with_sub4_in_VGPR_32_Lo128RegClassID - 352)) | |
| 749 | (1u << (AMDGPU::AV_384_with_sub5_in_VGPR_32_Lo128RegClassID - 352)) | |
| 750 | (1u << (AMDGPU::AV_384_with_sub6_in_VGPR_32_Lo128RegClassID - 352)) | |
| 751 | (1u << (AMDGPU::AV_384_with_sub7_in_VGPR_32_Lo128RegClassID - 352)) | |
| 752 | (1u << (AMDGPU::AV_384_with_sub8_in_VGPR_32_Lo128RegClassID - 352)) | |
| 753 | (1u << (AMDGPU::AV_384_with_sub9_in_VGPR_32_Lo128RegClassID - 352)) | |
| 754 | (1u << (AMDGPU::AV_384_with_sub10_in_VGPR_32_Lo128RegClassID - 352)) | |
| 755 | (1u << (AMDGPU::VReg_384_Align2RegClassID - 352)) | |
| 756 | (1u << (AMDGPU::AV_384_with_sub1_sub2_in_VReg_64_Align2RegClassID - 352)) | |
| 757 | (1u << (AMDGPU::AV_384RegClassID - 352)) | |
| 758 | (1u << (AMDGPU::AV_384_Align2RegClassID - 352)) | |
| 759 | (1u << (AMDGPU::AV_384_with_sub1_sub2_in_AV_64_Align2RegClassID - 352)) | |
| 760 | 0, |
| 761 | // 384-415 |
| 762 | (1u << (AMDGPU::AV_384_with_sub11_in_VGPR_32_Lo128RegClassID - 384)) | |
| 763 | (1u << (AMDGPU::AV_384_with_sub8_sub9_sub10_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 384)) | |
| 764 | (1u << (AMDGPU::AV_384_with_sub9_sub10_sub11_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 384)) | |
| 765 | (1u << (AMDGPU::AV_384_with_sub7_sub8_sub9_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 384)) | |
| 766 | (1u << (AMDGPU::AV_384_with_sub6_sub7_sub8_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 384)) | |
| 767 | (1u << (AMDGPU::AV_384_with_sub5_sub6_sub7_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 384)) | |
| 768 | (1u << (AMDGPU::AV_384_with_sub4_sub5_sub6_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 384)) | |
| 769 | (1u << (AMDGPU::AV_384_with_sub3_sub4_sub5_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 384)) | |
| 770 | (1u << (AMDGPU::AV_384_with_sub2_sub3_sub4_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 384)) | |
| 771 | (1u << (AMDGPU::AV_384_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 384)) | |
| 772 | (1u << (AMDGPU::AV_384_with_sub0_sub1_sub2_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 384)) | |
| 773 | (1u << (AMDGPU::AV_384_with_sub1_sub2_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID - 384)) | |
| 774 | (1u << (AMDGPU::AV_384_with_sub0_sub1_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID - 384)) | |
| 775 | (1u << (AMDGPU::AV_384_with_hi16_in_VGPR_16_Lo128_and_AV_384_with_sub1_sub2_in_AV_64_Align2RegClassID - 384)) | |
| 776 | (1u << (AMDGPU::VReg_512RegClassID - 384)) | |
| 777 | (1u << (AMDGPU::AV_512RegClassID - 384)) | |
| 778 | (1u << (AMDGPU::AV_512_Align2RegClassID - 384)) | |
| 779 | 0, |
| 780 | // 416-447 |
| 781 | (1u << (AMDGPU::AV_512_with_hi16_in_VGPR_16_Lo128RegClassID - 416)) | |
| 782 | (1u << (AMDGPU::AV_512_with_sub1_in_VGPR_32_Lo128RegClassID - 416)) | |
| 783 | (1u << (AMDGPU::AV_512_with_sub2_in_VGPR_32_Lo128RegClassID - 416)) | |
| 784 | (1u << (AMDGPU::AV_512_with_sub3_in_VGPR_32_Lo128RegClassID - 416)) | |
| 785 | (1u << (AMDGPU::AV_512_with_sub4_in_VGPR_32_Lo128RegClassID - 416)) | |
| 786 | (1u << (AMDGPU::AV_512_with_sub5_in_VGPR_32_Lo128RegClassID - 416)) | |
| 787 | (1u << (AMDGPU::AV_512_with_sub6_in_VGPR_32_Lo128RegClassID - 416)) | |
| 788 | (1u << (AMDGPU::AV_512_with_sub7_in_VGPR_32_Lo128RegClassID - 416)) | |
| 789 | (1u << (AMDGPU::AV_512_with_sub8_in_VGPR_32_Lo128RegClassID - 416)) | |
| 790 | (1u << (AMDGPU::AV_512_with_sub9_in_VGPR_32_Lo128RegClassID - 416)) | |
| 791 | (1u << (AMDGPU::AV_512_with_sub10_in_VGPR_32_Lo128RegClassID - 416)) | |
| 792 | (1u << (AMDGPU::AV_512_with_sub11_in_VGPR_32_Lo128RegClassID - 416)) | |
| 793 | (1u << (AMDGPU::AV_512_with_sub12_in_VGPR_32_Lo128RegClassID - 416)) | |
| 794 | (1u << (AMDGPU::AV_512_with_sub13_in_VGPR_32_Lo128RegClassID - 416)) | |
| 795 | (1u << (AMDGPU::AV_512_with_sub14_in_VGPR_32_Lo128RegClassID - 416)) | |
| 796 | (1u << (AMDGPU::AV_512_with_sub15_in_VGPR_32_Lo128RegClassID - 416)) | |
| 797 | (1u << (AMDGPU::AV_512_with_sub7_sub8_sub9_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 416)) | |
| 798 | (1u << (AMDGPU::AV_512_with_sub6_sub7_sub8_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 416)) | |
| 799 | (1u << (AMDGPU::AV_512_with_sub5_sub6_sub7_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 416)) | |
| 800 | (1u << (AMDGPU::AV_512_with_sub4_sub5_sub6_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 416)) | |
| 801 | (1u << (AMDGPU::AV_512_with_sub3_sub4_sub5_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 416)) | |
| 802 | (1u << (AMDGPU::AV_512_with_sub2_sub3_sub4_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 416)) | |
| 803 | (1u << (AMDGPU::AV_512_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 416)) | |
| 804 | (1u << (AMDGPU::AV_512_with_sub0_sub1_sub2_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 416)) | |
| 805 | (1u << (AMDGPU::AV_512_with_sub1_sub2_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID - 416)) | |
| 806 | (1u << (AMDGPU::AV_512_with_sub0_sub1_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID - 416)) | |
| 807 | (1u << (AMDGPU::AV_512_with_hi16_in_VGPR_16_Lo128_and_AV_512_with_sub1_sub2_in_AV_64_Align2RegClassID - 416)) | |
| 808 | (1u << (AMDGPU::VReg_512_Align2RegClassID - 416)) | |
| 809 | (1u << (AMDGPU::AV_512_with_sub1_sub2_in_VReg_64_Align2RegClassID - 416)) | |
| 810 | (1u << (AMDGPU::AV_512_with_sub1_sub2_in_AV_64_Align2RegClassID - 416)) | |
| 811 | 0, |
| 812 | // 448-479 |
| 813 | (1u << (AMDGPU::AV_512_with_sub12_sub13_sub14_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 448)) | |
| 814 | (1u << (AMDGPU::AV_512_with_sub13_sub14_sub15_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 448)) | |
| 815 | (1u << (AMDGPU::AV_512_with_sub11_sub12_sub13_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 448)) | |
| 816 | (1u << (AMDGPU::AV_512_with_sub10_sub11_sub12_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 448)) | |
| 817 | (1u << (AMDGPU::AV_512_with_sub9_sub10_sub11_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 448)) | |
| 818 | (1u << (AMDGPU::AV_512_with_sub8_sub9_sub10_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 448)) | |
| 819 | (1u << (AMDGPU::VReg_1024RegClassID - 448)) | |
| 820 | 0, |
| 821 | // 480-511 |
| 822 | (1u << (AMDGPU::AV_1024_with_hi16_in_VGPR_16_Lo128RegClassID - 480)) | |
| 823 | (1u << (AMDGPU::AV_1024_with_sub1_in_VGPR_32_Lo128RegClassID - 480)) | |
| 824 | (1u << (AMDGPU::AV_1024_with_sub2_in_VGPR_32_Lo128RegClassID - 480)) | |
| 825 | (1u << (AMDGPU::AV_1024_with_sub3_in_VGPR_32_Lo128RegClassID - 480)) | |
| 826 | (1u << (AMDGPU::AV_1024_with_sub4_in_VGPR_32_Lo128RegClassID - 480)) | |
| 827 | (1u << (AMDGPU::AV_1024_with_sub5_in_VGPR_32_Lo128RegClassID - 480)) | |
| 828 | (1u << (AMDGPU::AV_1024_with_sub6_in_VGPR_32_Lo128RegClassID - 480)) | |
| 829 | (1u << (AMDGPU::AV_1024_with_sub7_in_VGPR_32_Lo128RegClassID - 480)) | |
| 830 | (1u << (AMDGPU::AV_1024_with_sub8_in_VGPR_32_Lo128RegClassID - 480)) | |
| 831 | (1u << (AMDGPU::AV_1024_with_sub9_in_VGPR_32_Lo128RegClassID - 480)) | |
| 832 | (1u << (AMDGPU::AV_1024_with_sub10_in_VGPR_32_Lo128RegClassID - 480)) | |
| 833 | (1u << (AMDGPU::AV_1024_with_sub11_in_VGPR_32_Lo128RegClassID - 480)) | |
| 834 | (1u << (AMDGPU::AV_1024_with_sub12_in_VGPR_32_Lo128RegClassID - 480)) | |
| 835 | (1u << (AMDGPU::AV_1024_with_sub13_in_VGPR_32_Lo128RegClassID - 480)) | |
| 836 | (1u << (AMDGPU::AV_1024_with_sub14_in_VGPR_32_Lo128RegClassID - 480)) | |
| 837 | (1u << (AMDGPU::AV_1024_with_sub15_in_VGPR_32_Lo128RegClassID - 480)) | |
| 838 | (1u << (AMDGPU::AV_1024_with_sub16_in_VGPR_32_Lo128RegClassID - 480)) | |
| 839 | (1u << (AMDGPU::AV_1024_with_sub17_in_VGPR_32_Lo128RegClassID - 480)) | |
| 840 | (1u << (AMDGPU::AV_1024_with_sub18_in_VGPR_32_Lo128RegClassID - 480)) | |
| 841 | (1u << (AMDGPU::AV_1024_with_sub19_in_VGPR_32_Lo128RegClassID - 480)) | |
| 842 | (1u << (AMDGPU::AV_1024_with_sub20_in_VGPR_32_Lo128RegClassID - 480)) | |
| 843 | (1u << (AMDGPU::AV_1024_with_sub21_in_VGPR_32_Lo128RegClassID - 480)) | |
| 844 | (1u << (AMDGPU::AV_1024_with_sub22_in_VGPR_32_Lo128RegClassID - 480)) | |
| 845 | (1u << (AMDGPU::AV_1024_with_sub23_in_VGPR_32_Lo128RegClassID - 480)) | |
| 846 | (1u << (AMDGPU::AV_1024_with_sub24_in_VGPR_32_Lo128RegClassID - 480)) | |
| 847 | (1u << (AMDGPU::AV_1024_with_sub25_in_VGPR_32_Lo128RegClassID - 480)) | |
| 848 | (1u << (AMDGPU::AV_1024_with_sub26_in_VGPR_32_Lo128RegClassID - 480)) | |
| 849 | (1u << (AMDGPU::AV_1024_with_sub27_in_VGPR_32_Lo128RegClassID - 480)) | |
| 850 | (1u << (AMDGPU::VReg_1024_Align2RegClassID - 480)) | |
| 851 | (1u << (AMDGPU::AV_1024_with_sub1_sub2_in_VReg_64_Align2RegClassID - 480)) | |
| 852 | 0, |
| 853 | // 512-543 |
| 854 | (1u << (AMDGPU::AV_1024_with_sub28_in_VGPR_32_Lo128RegClassID - 512)) | |
| 855 | (1u << (AMDGPU::AV_1024_with_sub29_in_VGPR_32_Lo128RegClassID - 512)) | |
| 856 | (1u << (AMDGPU::AV_1024_with_sub30_in_VGPR_32_Lo128RegClassID - 512)) | |
| 857 | (1u << (AMDGPU::AV_1024_with_sub31_in_VGPR_32_Lo128RegClassID - 512)) | |
| 858 | (1u << (AMDGPU::AV_1024_with_sub24_sub25_sub26_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 512)) | |
| 859 | (1u << (AMDGPU::AV_1024_with_sub23_sub24_sub25_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 512)) | |
| 860 | (1u << (AMDGPU::AV_1024_with_sub22_sub23_sub24_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 512)) | |
| 861 | (1u << (AMDGPU::AV_1024_with_sub21_sub22_sub23_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 512)) | |
| 862 | (1u << (AMDGPU::AV_1024_with_sub20_sub21_sub22_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 512)) | |
| 863 | (1u << (AMDGPU::AV_1024_with_sub19_sub20_sub21_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 512)) | |
| 864 | (1u << (AMDGPU::AV_1024_with_sub18_sub19_sub20_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 512)) | |
| 865 | (1u << (AMDGPU::AV_1024_with_sub17_sub18_sub19_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 512)) | |
| 866 | (1u << (AMDGPU::AV_1024_with_sub16_sub17_sub18_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 512)) | |
| 867 | (1u << (AMDGPU::AV_1024_with_sub15_sub16_sub17_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 512)) | |
| 868 | (1u << (AMDGPU::AV_1024_with_sub14_sub15_sub16_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 512)) | |
| 869 | (1u << (AMDGPU::AV_1024_with_sub13_sub14_sub15_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 512)) | |
| 870 | (1u << (AMDGPU::AV_1024_with_sub12_sub13_sub14_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 512)) | |
| 871 | (1u << (AMDGPU::AV_1024_with_sub11_sub12_sub13_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 512)) | |
| 872 | (1u << (AMDGPU::AV_1024_with_sub10_sub11_sub12_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 512)) | |
| 873 | (1u << (AMDGPU::AV_1024_with_sub9_sub10_sub11_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 512)) | |
| 874 | (1u << (AMDGPU::AV_1024_with_sub8_sub9_sub10_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 512)) | |
| 875 | (1u << (AMDGPU::AV_1024_with_sub7_sub8_sub9_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 512)) | |
| 876 | (1u << (AMDGPU::AV_1024_with_sub6_sub7_sub8_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 512)) | |
| 877 | (1u << (AMDGPU::AV_1024_with_sub5_sub6_sub7_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 512)) | |
| 878 | (1u << (AMDGPU::AV_1024_with_sub4_sub5_sub6_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 512)) | |
| 879 | (1u << (AMDGPU::AV_1024_with_sub3_sub4_sub5_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 512)) | |
| 880 | (1u << (AMDGPU::AV_1024_with_sub2_sub3_sub4_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 512)) | |
| 881 | (1u << (AMDGPU::AV_1024_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 512)) | |
| 882 | (1u << (AMDGPU::AV_1024_with_sub0_sub1_sub2_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 512)) | |
| 883 | (1u << (AMDGPU::AV_1024_with_sub1_sub2_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID - 512)) | |
| 884 | (1u << (AMDGPU::AV_1024_with_sub0_sub1_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID - 512)) | |
| 885 | (1u << (AMDGPU::AV_1024_with_hi16_in_VGPR_16_Lo128_and_AV_1024_with_sub1_sub2_in_AV_64_Align2RegClassID - 512)) | |
| 886 | 0, |
| 887 | // 544-575 |
| 888 | (1u << (AMDGPU::AV_1024_with_sub28_sub29_sub30_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 544)) | |
| 889 | (1u << (AMDGPU::AV_1024_with_sub29_sub30_sub31_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 544)) | |
| 890 | (1u << (AMDGPU::AV_1024_with_sub27_sub28_sub29_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 544)) | |
| 891 | (1u << (AMDGPU::AV_1024_with_sub26_sub27_sub28_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 544)) | |
| 892 | (1u << (AMDGPU::AV_1024_with_sub25_sub26_sub27_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 544)) | |
| 893 | 0, |
| 894 | // 576-607 |
| 895 | 0, |
| 896 | // 608-639 |
| 897 | 0, |
| 898 | }; |
| 899 | |
| 900 | constexpr RegisterBank AGPRRegBank(/* ID */ AMDGPU::AGPRRegBankID, /* Name */ "AGPR", /* CoveredRegClasses */ AGPRRegBankCoverageData, /* NumRegClasses */ 615); |
| 901 | constexpr RegisterBank SGPRRegBank(/* ID */ AMDGPU::SGPRRegBankID, /* Name */ "SGPR", /* CoveredRegClasses */ SGPRRegBankCoverageData, /* NumRegClasses */ 615); |
| 902 | constexpr RegisterBank VCCRegBank(/* ID */ AMDGPU::VCCRegBankID, /* Name */ "VCC", /* CoveredRegClasses */ VCCRegBankCoverageData, /* NumRegClasses */ 615); |
| 903 | constexpr RegisterBank VGPRRegBank(/* ID */ AMDGPU::VGPRRegBankID, /* Name */ "VGPR", /* CoveredRegClasses */ VGPRRegBankCoverageData, /* NumRegClasses */ 615); |
| 904 | } // end namespace AMDGPU |
| 905 | |
| 906 | const RegisterBank *AMDGPUGenRegisterBankInfo::RegBanks[] = { |
| 907 | &AMDGPU::AGPRRegBank, |
| 908 | &AMDGPU::SGPRRegBank, |
| 909 | &AMDGPU::VCCRegBank, |
| 910 | &AMDGPU::VGPRRegBank, |
| 911 | }; |
| 912 | |
| 913 | const unsigned AMDGPUGenRegisterBankInfo::Sizes[] = { |
| 914 | // Mode = 0 (Default) |
| 915 | 1024, |
| 916 | 1024, |
| 917 | 64, |
| 918 | 1024, |
| 919 | }; |
| 920 | |
| 921 | AMDGPUGenRegisterBankInfo::AMDGPUGenRegisterBankInfo(unsigned HwMode) |
| 922 | : RegisterBankInfo(RegBanks, AMDGPU::NumRegisterBanks, Sizes, HwMode) { |
| 923 | // Assert that RegBank indices match their ID's |
| 924 | #ifndef NDEBUG |
| 925 | for (auto RB : enumerate(RegBanks)) |
| 926 | assert(RB.index() == RB.value()->getID() && "Index != ID"); |
| 927 | #endif // NDEBUG |
| 928 | } |
| 929 | const RegisterBank & |
| 930 | AMDGPUGenRegisterBankInfo::getRegBankFromRegClass(const TargetRegisterClass &RC, LLT) const { |
| 931 | constexpr uint32_t InvalidRegBankID = uint32_t(AMDGPU::InvalidRegBankID) & 15; |
| 932 | static const uint32_t RegClass2RegBank[77] = { |
| 933 | (uint32_t(InvalidRegBankID) << 0) | |
| 934 | (uint32_t(InvalidRegBankID) << 4) | // SReg_1RegClassID |
| 935 | (uint32_t(InvalidRegBankID) << 8) | // SReg_1_XEXECRegClassID |
| 936 | (uint32_t(InvalidRegBankID) << 12) | // SReg_1_with_lo16_in_SGPR_LO16RegClassID |
| 937 | (uint32_t(InvalidRegBankID) << 16) | // SReg_1_with_sub0RegClassID |
| 938 | (uint32_t(InvalidRegBankID) << 20) | // SReg_1_XEXEC_with_sub0RegClassID |
| 939 | (uint32_t(InvalidRegBankID) << 24) | // SReg_1_with_sub0_and_SReg_1_with_lo16_in_SGPR_LO16RegClassID |
| 940 | (uint32_t(InvalidRegBankID) << 28), // SReg_1_with_lo16_in_TTMP_LO16RegClassID |
| 941 | (uint32_t(InvalidRegBankID) << 0) | // SReg_1_with_sub0_and_SReg_1_with_lo16_in_TTMP_LO16RegClassID |
| 942 | (uint32_t(AMDGPU::VCCRegBankID) << 4) | // SReg_1_with_lo16_in_M0_CLASS_LO16RegClassID |
| 943 | (uint32_t(AMDGPU::VCCRegBankID) << 8) | // VReg_1RegClassID |
| 944 | (uint32_t(InvalidRegBankID) << 12) | // VS_16RegClassID |
| 945 | (uint32_t(AMDGPU::VGPRRegBankID) << 16) | // VGPR_16RegClassID |
| 946 | (uint32_t(InvalidRegBankID) << 20) | // VS_16_Lo128RegClassID |
| 947 | (uint32_t(AMDGPU::AGPRRegBankID) << 24) | // AGPR_LO16RegClassID |
| 948 | (uint32_t(AMDGPU::VGPRRegBankID) << 28), // VGPR_16_Lo128RegClassID |
| 949 | (uint32_t(InvalidRegBankID) << 0) | // SReg_LO16RegClassID |
| 950 | (uint32_t(InvalidRegBankID) << 4) | // VS_16_and_SReg_1RegClassID |
| 951 | (uint32_t(InvalidRegBankID) << 8) | // VS_16_and_SReg_1_XEXECRegClassID |
| 952 | (uint32_t(InvalidRegBankID) << 12) | |
| 953 | (uint32_t(InvalidRegBankID) << 16) | // SGPR_LO16RegClassID |
| 954 | (uint32_t(InvalidRegBankID) << 20) | // VS_16_and_SReg_1_with_lo16_in_SGPR_LO16RegClassID |
| 955 | (uint32_t(InvalidRegBankID) << 24) | // TTMP_LO16RegClassID |
| 956 | (uint32_t(InvalidRegBankID) << 28), // VS_16_and_SReg_1_with_lo16_in_TTMP_LO16RegClassID |
| 957 | (uint32_t(InvalidRegBankID) << 0) | // M0_CLASS_LO16RegClassID |
| 958 | (uint32_t(InvalidRegBankID) << 4) | |
| 959 | (uint32_t(InvalidRegBankID) << 8) | // AV_32RegClassID |
| 960 | (uint32_t(InvalidRegBankID) << 12) | // VS_32RegClassID |
| 961 | (uint32_t(InvalidRegBankID) << 16) | // VS_32_with_hi16RegClassID |
| 962 | (uint32_t(InvalidRegBankID) << 20) | // VS_32_Lo128RegClassID |
| 963 | (uint32_t(InvalidRegBankID) << 24) | // VS_32_Lo128_with_hi16RegClassID |
| 964 | (uint32_t(AMDGPU::VGPRRegBankID) << 28), // VRegOrLds_32RegClassID |
| 965 | (uint32_t(AMDGPU::AGPRRegBankID) << 0) | // AGPR_32RegClassID |
| 966 | (uint32_t(AMDGPU::VGPRRegBankID) << 4) | // VGPR_32RegClassID |
| 967 | (uint32_t(InvalidRegBankID) << 8) | // SRegOrLds_32RegClassID |
| 968 | (uint32_t(InvalidRegBankID) << 12) | // SReg_32RegClassID |
| 969 | (uint32_t(InvalidRegBankID) << 16) | // SReg_32_XEXEC_HIRegClassID |
| 970 | (uint32_t(InvalidRegBankID) << 20) | // SReg_32_XM0RegClassID |
| 971 | (uint32_t(InvalidRegBankID) << 24) | // SReg_32_XEXECRegClassID |
| 972 | (uint32_t(InvalidRegBankID) << 28), // SReg_32_XEXEC_HI_and_SReg_32_XM0RegClassID |
| 973 | (uint32_t(InvalidRegBankID) << 0) | // SReg_32_XM0_XEXECRegClassID |
| 974 | (uint32_t(AMDGPU::VGPRRegBankID) << 4) | // VRegOrLds_32_and_VS_32_Lo128RegClassID |
| 975 | (uint32_t(AMDGPU::VGPRRegBankID) << 8) | // VGPR_32_Lo128RegClassID |
| 976 | (uint32_t(InvalidRegBankID) << 12) | // SGPR_32RegClassID |
| 977 | (uint32_t(InvalidRegBankID) << 16) | // TTMP_32RegClassID |
| 978 | (uint32_t(InvalidRegBankID) << 20) | |
| 979 | (uint32_t(InvalidRegBankID) << 24) | |
| 980 | (uint32_t(InvalidRegBankID) << 28), // M0_CLASSRegClassID |
| 981 | (uint32_t(InvalidRegBankID) << 0) | |
| 982 | (uint32_t(InvalidRegBankID) << 4) | // AV_64RegClassID |
| 983 | (uint32_t(InvalidRegBankID) << 8) | // VS_64RegClassID |
| 984 | (uint32_t(InvalidRegBankID) << 12) | // AV_64_Align2RegClassID |
| 985 | (uint32_t(AMDGPU::AGPRRegBankID) << 16) | // AReg_64RegClassID |
| 986 | (uint32_t(AMDGPU::VGPRRegBankID) << 20) | // VReg_64RegClassID |
| 987 | (uint32_t(InvalidRegBankID) << 24) | // VS_64_with_sub0_in_VS_32_Lo128RegClassID |
| 988 | (uint32_t(InvalidRegBankID) << 28), // VS_64_with_sub1_in_VS_32_Lo128RegClassID |
| 989 | (uint32_t(AMDGPU::AGPRRegBankID) << 0) | // AReg_64_Align2RegClassID |
| 990 | (uint32_t(AMDGPU::VGPRRegBankID) << 4) | // AV_64_with_hi16_in_VGPR_16_Lo128RegClassID |
| 991 | (uint32_t(AMDGPU::VGPRRegBankID) << 8) | // VReg_64_Align2RegClassID |
| 992 | (uint32_t(AMDGPU::VGPRRegBankID) << 12) | // AV_64_with_sub1_in_VGPR_32_Lo128RegClassID |
| 993 | (uint32_t(InvalidRegBankID) << 16) | // SReg_64RegClassID |
| 994 | (uint32_t(InvalidRegBankID) << 20) | // SReg_64_XEXECRegClassID |
| 995 | (uint32_t(InvalidRegBankID) << 24) | // SReg_64_XEXEC_XNULLRegClassID |
| 996 | (uint32_t(AMDGPU::VGPRRegBankID) << 28), // AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID |
| 997 | (uint32_t(InvalidRegBankID) << 0) | // SGPR_64RegClassID |
| 998 | (uint32_t(InvalidRegBankID) << 4) | // CCR_SGPR_64RegClassID |
| 999 | (uint32_t(InvalidRegBankID) << 8) | // Gfx_CCR_SGPR_64RegClassID |
| 1000 | (uint32_t(InvalidRegBankID) << 12) | // TTMP_64RegClassID |
| 1001 | (uint32_t(InvalidRegBankID) << 16) | // AV_96RegClassID |
| 1002 | (uint32_t(AMDGPU::AGPRRegBankID) << 20) | // AReg_96RegClassID |
| 1003 | (uint32_t(InvalidRegBankID) << 24) | // AV_96_Align2RegClassID |
| 1004 | (uint32_t(InvalidRegBankID) << 28), // AV_96_with_sub1_sub2_in_AV_64_Align2RegClassID |
| 1005 | (uint32_t(AMDGPU::VGPRRegBankID) << 0) | // VReg_96RegClassID |
| 1006 | (uint32_t(AMDGPU::VGPRRegBankID) << 4) | // AV_96_with_hi16_in_VGPR_16_Lo128RegClassID |
| 1007 | (uint32_t(AMDGPU::AGPRRegBankID) << 8) | // AReg_96_Align2RegClassID |
| 1008 | (uint32_t(AMDGPU::AGPRRegBankID) << 12) | // AReg_96_with_sub1_sub2_in_AReg_64_Align2RegClassID |
| 1009 | (uint32_t(AMDGPU::VGPRRegBankID) << 16) | // AV_96_with_sub1_in_VGPR_32_Lo128RegClassID |
| 1010 | (uint32_t(AMDGPU::VGPRRegBankID) << 20) | // AV_96_with_sub1_sub2_in_VReg_64_Align2RegClassID |
| 1011 | (uint32_t(AMDGPU::VGPRRegBankID) << 24) | // VReg_96_Align2RegClassID |
| 1012 | (uint32_t(AMDGPU::VGPRRegBankID) << 28), // AV_96_with_sub2_in_VGPR_32_Lo128RegClassID |
| 1013 | (uint32_t(AMDGPU::VGPRRegBankID) << 0) | // AV_96_with_hi16_in_VGPR_16_Lo128_and_AV_96_with_sub1_sub2_in_AV_64_Align2RegClassID |
| 1014 | (uint32_t(AMDGPU::VGPRRegBankID) << 4) | // AV_96_with_sub0_sub1_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID |
| 1015 | (uint32_t(AMDGPU::VGPRRegBankID) << 8) | // AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID |
| 1016 | (uint32_t(AMDGPU::VGPRRegBankID) << 12) | // AV_96_with_sub1_sub2_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID |
| 1017 | (uint32_t(AMDGPU::SGPRRegBankID) << 16) | // SReg_96RegClassID |
| 1018 | (uint32_t(AMDGPU::SGPRRegBankID) << 20) | // SGPR_96RegClassID |
| 1019 | (uint32_t(AMDGPU::SGPRRegBankID) << 24) | // SGPR_96_with_sub0_sub1_in_CCR_SGPR_64RegClassID |
| 1020 | (uint32_t(AMDGPU::SGPRRegBankID) << 28), // SGPR_96_with_sub0_sub1_in_Gfx_CCR_SGPR_64RegClassID |
| 1021 | (uint32_t(AMDGPU::SGPRRegBankID) << 0) | // TTMP_96RegClassID |
| 1022 | (uint32_t(InvalidRegBankID) << 4) | // AV_128RegClassID |
| 1023 | (uint32_t(InvalidRegBankID) << 8) | // AV_128_Align2RegClassID |
| 1024 | (uint32_t(AMDGPU::AGPRRegBankID) << 12) | // AReg_128RegClassID |
| 1025 | (uint32_t(AMDGPU::VGPRRegBankID) << 16) | // VReg_128RegClassID |
| 1026 | (uint32_t(InvalidRegBankID) << 20) | // AV_128_with_sub1_sub2_in_AV_64_Align2RegClassID |
| 1027 | (uint32_t(AMDGPU::VGPRRegBankID) << 24) | // AV_128_with_hi16_in_VGPR_16_Lo128RegClassID |
| 1028 | (uint32_t(AMDGPU::AGPRRegBankID) << 28), // AReg_128_Align2RegClassID |
| 1029 | (uint32_t(AMDGPU::VGPRRegBankID) << 0) | // AV_128_with_sub1_in_VGPR_32_Lo128RegClassID |
| 1030 | (uint32_t(AMDGPU::VGPRRegBankID) << 4) | // VReg_128_Align2RegClassID |
| 1031 | (uint32_t(AMDGPU::AGPRRegBankID) << 8) | // AReg_128_with_sub1_sub2_in_AReg_64_Align2RegClassID |
| 1032 | (uint32_t(AMDGPU::VGPRRegBankID) << 12) | // AV_128_with_sub1_sub2_in_VReg_64_Align2RegClassID |
| 1033 | (uint32_t(AMDGPU::VGPRRegBankID) << 16) | // AV_128_with_sub2_in_VGPR_32_Lo128RegClassID |
| 1034 | (uint32_t(AMDGPU::VGPRRegBankID) << 20) | // AV_128_with_sub3_in_VGPR_32_Lo128RegClassID |
| 1035 | (uint32_t(AMDGPU::VGPRRegBankID) << 24) | // AV_128_with_hi16_in_VGPR_16_Lo128_and_AV_128_with_sub1_sub2_in_AV_64_Align2RegClassID |
| 1036 | (uint32_t(AMDGPU::VGPRRegBankID) << 28), // AV_128_with_sub0_sub1_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID |
| 1037 | (uint32_t(AMDGPU::VGPRRegBankID) << 0) | // AV_128_with_sub0_sub1_sub2_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID |
| 1038 | (uint32_t(AMDGPU::VGPRRegBankID) << 4) | // AV_128_with_sub1_sub2_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID |
| 1039 | (uint32_t(AMDGPU::VGPRRegBankID) << 8) | // AV_128_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID |
| 1040 | (uint32_t(AMDGPU::SGPRRegBankID) << 12) | // SReg_128RegClassID |
| 1041 | (uint32_t(AMDGPU::SGPRRegBankID) << 16) | // SReg_128_XNULLRegClassID |
| 1042 | (uint32_t(AMDGPU::SGPRRegBankID) << 20) | // SGPR_128RegClassID |
| 1043 | (uint32_t(AMDGPU::SGPRRegBankID) << 24) | // SGPR_128_with_sub0_sub1_in_CCR_SGPR_64RegClassID |
| 1044 | (uint32_t(AMDGPU::SGPRRegBankID) << 28), // SGPR_128_with_sub0_sub1_in_Gfx_CCR_SGPR_64RegClassID |
| 1045 | (uint32_t(AMDGPU::SGPRRegBankID) << 0) | // SGPR_128_with_sub2_sub3_in_CCR_SGPR_64RegClassID |
| 1046 | (uint32_t(AMDGPU::SGPRRegBankID) << 4) | // TTMP_128RegClassID |
| 1047 | (uint32_t(InvalidRegBankID) << 8) | |
| 1048 | (uint32_t(InvalidRegBankID) << 12) | // AV_160RegClassID |
| 1049 | (uint32_t(AMDGPU::AGPRRegBankID) << 16) | // AReg_160RegClassID |
| 1050 | (uint32_t(InvalidRegBankID) << 20) | // AV_160_Align2RegClassID |
| 1051 | (uint32_t(InvalidRegBankID) << 24) | // AV_160_with_sub1_sub2_in_AV_64_Align2RegClassID |
| 1052 | (uint32_t(AMDGPU::VGPRRegBankID) << 28), // VReg_160RegClassID |
| 1053 | (uint32_t(AMDGPU::VGPRRegBankID) << 0) | // AV_160_with_hi16_in_VGPR_16_Lo128RegClassID |
| 1054 | (uint32_t(AMDGPU::VGPRRegBankID) << 4) | // AV_160_with_sub1_in_VGPR_32_Lo128RegClassID |
| 1055 | (uint32_t(AMDGPU::AGPRRegBankID) << 8) | // AReg_160_Align2RegClassID |
| 1056 | (uint32_t(AMDGPU::AGPRRegBankID) << 12) | // AReg_160_with_sub1_sub2_in_AReg_64_Align2RegClassID |
| 1057 | (uint32_t(AMDGPU::VGPRRegBankID) << 16) | // AV_160_with_sub1_sub2_in_VReg_64_Align2RegClassID |
| 1058 | (uint32_t(AMDGPU::VGPRRegBankID) << 20) | // AV_160_with_sub2_in_VGPR_32_Lo128RegClassID |
| 1059 | (uint32_t(AMDGPU::VGPRRegBankID) << 24) | // VReg_160_Align2RegClassID |
| 1060 | (uint32_t(AMDGPU::VGPRRegBankID) << 28), // AV_160_with_sub3_in_VGPR_32_Lo128RegClassID |
| 1061 | (uint32_t(AMDGPU::VGPRRegBankID) << 0) | // AV_160_with_sub4_in_VGPR_32_Lo128RegClassID |
| 1062 | (uint32_t(AMDGPU::VGPRRegBankID) << 4) | // AV_160_with_hi16_in_VGPR_16_Lo128_and_AV_160_with_sub1_sub2_in_AV_64_Align2RegClassID |
| 1063 | (uint32_t(AMDGPU::VGPRRegBankID) << 8) | // AV_160_with_sub0_sub1_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID |
| 1064 | (uint32_t(AMDGPU::VGPRRegBankID) << 12) | // AV_160_with_sub0_sub1_sub2_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID |
| 1065 | (uint32_t(AMDGPU::VGPRRegBankID) << 16) | // AV_160_with_sub1_sub2_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID |
| 1066 | (uint32_t(AMDGPU::VGPRRegBankID) << 20) | // AV_160_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID |
| 1067 | (uint32_t(AMDGPU::VGPRRegBankID) << 24) | // AV_160_with_sub2_sub3_sub4_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID |
| 1068 | (uint32_t(AMDGPU::SGPRRegBankID) << 28), // SReg_160RegClassID |
| 1069 | (uint32_t(AMDGPU::SGPRRegBankID) << 0) | // SGPR_160RegClassID |
| 1070 | (uint32_t(AMDGPU::SGPRRegBankID) << 4) | // SGPR_160_with_sub0_sub1_in_CCR_SGPR_64RegClassID |
| 1071 | (uint32_t(AMDGPU::SGPRRegBankID) << 8) | // SGPR_160_with_sub0_sub1_in_Gfx_CCR_SGPR_64RegClassID |
| 1072 | (uint32_t(AMDGPU::SGPRRegBankID) << 12) | // SGPR_160_with_sub2_sub3_in_CCR_SGPR_64RegClassID |
| 1073 | (uint32_t(AMDGPU::SGPRRegBankID) << 16) | // TTMP_160RegClassID |
| 1074 | (uint32_t(InvalidRegBankID) << 20) | // AV_192RegClassID |
| 1075 | (uint32_t(InvalidRegBankID) << 24) | // AV_192_Align2RegClassID |
| 1076 | (uint32_t(AMDGPU::AGPRRegBankID) << 28), // AReg_192RegClassID |
| 1077 | (uint32_t(AMDGPU::VGPRRegBankID) << 0) | // VReg_192RegClassID |
| 1078 | (uint32_t(InvalidRegBankID) << 4) | // AV_192_with_sub1_sub2_in_AV_64_Align2RegClassID |
| 1079 | (uint32_t(AMDGPU::VGPRRegBankID) << 8) | // AV_192_with_hi16_in_VGPR_16_Lo128RegClassID |
| 1080 | (uint32_t(AMDGPU::VGPRRegBankID) << 12) | // AV_192_with_sub1_in_VGPR_32_Lo128RegClassID |
| 1081 | (uint32_t(AMDGPU::AGPRRegBankID) << 16) | // AReg_192_Align2RegClassID |
| 1082 | (uint32_t(AMDGPU::VGPRRegBankID) << 20) | // AV_192_with_sub2_in_VGPR_32_Lo128RegClassID |
| 1083 | (uint32_t(AMDGPU::VGPRRegBankID) << 24) | // VReg_192_Align2RegClassID |
| 1084 | (uint32_t(AMDGPU::AGPRRegBankID) << 28), // AReg_192_with_sub1_sub2_in_AReg_64_Align2RegClassID |
| 1085 | (uint32_t(AMDGPU::VGPRRegBankID) << 0) | // AV_192_with_sub1_sub2_in_VReg_64_Align2RegClassID |
| 1086 | (uint32_t(AMDGPU::VGPRRegBankID) << 4) | // AV_192_with_sub3_in_VGPR_32_Lo128RegClassID |
| 1087 | (uint32_t(AMDGPU::VGPRRegBankID) << 8) | // AV_192_with_sub4_in_VGPR_32_Lo128RegClassID |
| 1088 | (uint32_t(AMDGPU::VGPRRegBankID) << 12) | // AV_192_with_sub5_in_VGPR_32_Lo128RegClassID |
| 1089 | (uint32_t(AMDGPU::VGPRRegBankID) << 16) | // AV_192_with_hi16_in_VGPR_16_Lo128_and_AV_192_with_sub1_sub2_in_AV_64_Align2RegClassID |
| 1090 | (uint32_t(AMDGPU::VGPRRegBankID) << 20) | // AV_192_with_sub0_sub1_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID |
| 1091 | (uint32_t(AMDGPU::VGPRRegBankID) << 24) | // AV_192_with_sub0_sub1_sub2_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID |
| 1092 | (uint32_t(AMDGPU::VGPRRegBankID) << 28), // AV_192_with_sub1_sub2_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID |
| 1093 | (uint32_t(AMDGPU::VGPRRegBankID) << 0) | // AV_192_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID |
| 1094 | (uint32_t(AMDGPU::VGPRRegBankID) << 4) | // AV_192_with_sub2_sub3_sub4_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID |
| 1095 | (uint32_t(AMDGPU::VGPRRegBankID) << 8) | // AV_192_with_sub3_sub4_sub5_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID |
| 1096 | (uint32_t(AMDGPU::SGPRRegBankID) << 12) | // SReg_192RegClassID |
| 1097 | (uint32_t(AMDGPU::SGPRRegBankID) << 16) | // SGPR_192RegClassID |
| 1098 | (uint32_t(AMDGPU::SGPRRegBankID) << 20) | // SGPR_192_with_sub0_sub1_in_CCR_SGPR_64RegClassID |
| 1099 | (uint32_t(AMDGPU::SGPRRegBankID) << 24) | // SGPR_192_with_sub0_sub1_in_Gfx_CCR_SGPR_64RegClassID |
| 1100 | (uint32_t(AMDGPU::SGPRRegBankID) << 28), // SGPR_192_with_sub2_sub3_in_CCR_SGPR_64RegClassID |
| 1101 | (uint32_t(AMDGPU::SGPRRegBankID) << 0) | // SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID |
| 1102 | (uint32_t(AMDGPU::SGPRRegBankID) << 4) | // SGPR_192_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID |
| 1103 | (uint32_t(AMDGPU::SGPRRegBankID) << 8) | // TTMP_192RegClassID |
| 1104 | (uint32_t(InvalidRegBankID) << 12) | // AV_224RegClassID |
| 1105 | (uint32_t(AMDGPU::AGPRRegBankID) << 16) | // AReg_224RegClassID |
| 1106 | (uint32_t(InvalidRegBankID) << 20) | // AV_224_Align2RegClassID |
| 1107 | (uint32_t(InvalidRegBankID) << 24) | // AV_224_with_sub1_sub2_in_AV_64_Align2RegClassID |
| 1108 | (uint32_t(AMDGPU::VGPRRegBankID) << 28), // VReg_224RegClassID |
| 1109 | (uint32_t(AMDGPU::VGPRRegBankID) << 0) | // AV_224_with_hi16_in_VGPR_16_Lo128RegClassID |
| 1110 | (uint32_t(AMDGPU::VGPRRegBankID) << 4) | // AV_224_with_sub1_in_VGPR_32_Lo128RegClassID |
| 1111 | (uint32_t(AMDGPU::VGPRRegBankID) << 8) | // AV_224_with_sub2_in_VGPR_32_Lo128RegClassID |
| 1112 | (uint32_t(AMDGPU::AGPRRegBankID) << 12) | // AReg_224_Align2RegClassID |
| 1113 | (uint32_t(AMDGPU::AGPRRegBankID) << 16) | // AReg_224_with_sub1_sub2_in_AReg_64_Align2RegClassID |
| 1114 | (uint32_t(AMDGPU::VGPRRegBankID) << 20) | // AV_224_with_sub1_sub2_in_VReg_64_Align2RegClassID |
| 1115 | (uint32_t(AMDGPU::VGPRRegBankID) << 24) | // AV_224_with_sub3_in_VGPR_32_Lo128RegClassID |
| 1116 | (uint32_t(AMDGPU::VGPRRegBankID) << 28), // VReg_224_Align2RegClassID |
| 1117 | (uint32_t(AMDGPU::VGPRRegBankID) << 0) | // AV_224_with_sub4_in_VGPR_32_Lo128RegClassID |
| 1118 | (uint32_t(AMDGPU::VGPRRegBankID) << 4) | // AV_224_with_sub5_in_VGPR_32_Lo128RegClassID |
| 1119 | (uint32_t(AMDGPU::VGPRRegBankID) << 8) | // AV_224_with_sub6_in_VGPR_32_Lo128RegClassID |
| 1120 | (uint32_t(AMDGPU::VGPRRegBankID) << 12) | // AV_224_with_hi16_in_VGPR_16_Lo128_and_AV_224_with_sub1_sub2_in_AV_64_Align2RegClassID |
| 1121 | (uint32_t(AMDGPU::VGPRRegBankID) << 16) | // AV_224_with_sub0_sub1_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID |
| 1122 | (uint32_t(AMDGPU::VGPRRegBankID) << 20) | // AV_224_with_sub0_sub1_sub2_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID |
| 1123 | (uint32_t(AMDGPU::VGPRRegBankID) << 24) | // AV_224_with_sub1_sub2_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID |
| 1124 | (uint32_t(AMDGPU::VGPRRegBankID) << 28), // AV_224_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID |
| 1125 | (uint32_t(AMDGPU::VGPRRegBankID) << 0) | // AV_224_with_sub2_sub3_sub4_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID |
| 1126 | (uint32_t(AMDGPU::VGPRRegBankID) << 4) | // AV_224_with_sub3_sub4_sub5_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID |
| 1127 | (uint32_t(AMDGPU::VGPRRegBankID) << 8) | // AV_224_with_sub4_sub5_sub6_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID |
| 1128 | (uint32_t(AMDGPU::SGPRRegBankID) << 12) | // SReg_224RegClassID |
| 1129 | (uint32_t(AMDGPU::SGPRRegBankID) << 16) | // SGPR_224RegClassID |
| 1130 | (uint32_t(AMDGPU::SGPRRegBankID) << 20) | // SGPR_224_with_sub0_sub1_in_CCR_SGPR_64RegClassID |
| 1131 | (uint32_t(AMDGPU::SGPRRegBankID) << 24) | // SGPR_224_with_sub0_sub1_in_Gfx_CCR_SGPR_64RegClassID |
| 1132 | (uint32_t(AMDGPU::SGPRRegBankID) << 28), // SGPR_224_with_sub2_sub3_in_CCR_SGPR_64RegClassID |
| 1133 | (uint32_t(AMDGPU::SGPRRegBankID) << 0) | // SGPR_224_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID |
| 1134 | (uint32_t(AMDGPU::SGPRRegBankID) << 4) | // SGPR_224_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_224_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID |
| 1135 | (uint32_t(AMDGPU::SGPRRegBankID) << 8) | // TTMP_224RegClassID |
| 1136 | (uint32_t(InvalidRegBankID) << 12) | // AV_256RegClassID |
| 1137 | (uint32_t(InvalidRegBankID) << 16) | // AV_256_Align2RegClassID |
| 1138 | (uint32_t(AMDGPU::AGPRRegBankID) << 20) | // AReg_256RegClassID |
| 1139 | (uint32_t(AMDGPU::VGPRRegBankID) << 24) | // VReg_256RegClassID |
| 1140 | (uint32_t(InvalidRegBankID) << 28), // AV_256_with_sub1_sub2_in_AV_64_Align2RegClassID |
| 1141 | (uint32_t(AMDGPU::VGPRRegBankID) << 0) | // AV_256_with_hi16_in_VGPR_16_Lo128RegClassID |
| 1142 | (uint32_t(AMDGPU::VGPRRegBankID) << 4) | // AV_256_with_sub1_in_VGPR_32_Lo128RegClassID |
| 1143 | (uint32_t(AMDGPU::VGPRRegBankID) << 8) | // AV_256_with_sub2_in_VGPR_32_Lo128RegClassID |
| 1144 | (uint32_t(AMDGPU::AGPRRegBankID) << 12) | // AReg_256_Align2RegClassID |
| 1145 | (uint32_t(AMDGPU::VGPRRegBankID) << 16) | // AV_256_with_sub3_in_VGPR_32_Lo128RegClassID |
| 1146 | (uint32_t(AMDGPU::VGPRRegBankID) << 20) | // VReg_256_Align2RegClassID |
| 1147 | (uint32_t(AMDGPU::AGPRRegBankID) << 24) | // AReg_256_with_sub1_sub2_in_AReg_64_Align2RegClassID |
| 1148 | (uint32_t(AMDGPU::VGPRRegBankID) << 28), // AV_256_with_sub1_sub2_in_VReg_64_Align2RegClassID |
| 1149 | (uint32_t(AMDGPU::VGPRRegBankID) << 0) | // AV_256_with_sub4_in_VGPR_32_Lo128RegClassID |
| 1150 | (uint32_t(AMDGPU::VGPRRegBankID) << 4) | // AV_256_with_sub5_in_VGPR_32_Lo128RegClassID |
| 1151 | (uint32_t(AMDGPU::VGPRRegBankID) << 8) | // AV_256_with_sub6_in_VGPR_32_Lo128RegClassID |
| 1152 | (uint32_t(AMDGPU::VGPRRegBankID) << 12) | // AV_256_with_sub7_in_VGPR_32_Lo128RegClassID |
| 1153 | (uint32_t(AMDGPU::VGPRRegBankID) << 16) | // AV_256_with_hi16_in_VGPR_16_Lo128_and_AV_256_with_sub1_sub2_in_AV_64_Align2RegClassID |
| 1154 | (uint32_t(AMDGPU::VGPRRegBankID) << 20) | // AV_256_with_sub0_sub1_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID |
| 1155 | (uint32_t(AMDGPU::VGPRRegBankID) << 24) | // AV_256_with_sub0_sub1_sub2_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID |
| 1156 | (uint32_t(AMDGPU::VGPRRegBankID) << 28), // AV_256_with_sub1_sub2_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID |
| 1157 | (uint32_t(AMDGPU::VGPRRegBankID) << 0) | // AV_256_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID |
| 1158 | (uint32_t(AMDGPU::VGPRRegBankID) << 4) | // AV_256_with_sub2_sub3_sub4_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID |
| 1159 | (uint32_t(AMDGPU::VGPRRegBankID) << 8) | // AV_256_with_sub3_sub4_sub5_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID |
| 1160 | (uint32_t(AMDGPU::VGPRRegBankID) << 12) | // AV_256_with_sub4_sub5_sub6_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID |
| 1161 | (uint32_t(AMDGPU::VGPRRegBankID) << 16) | // AV_256_with_sub5_sub6_sub7_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID |
| 1162 | (uint32_t(AMDGPU::SGPRRegBankID) << 20) | // SReg_256RegClassID |
| 1163 | (uint32_t(AMDGPU::SGPRRegBankID) << 24) | // SReg_256_XNULLRegClassID |
| 1164 | (uint32_t(AMDGPU::SGPRRegBankID) << 28), // SGPR_256RegClassID |
| 1165 | (uint32_t(AMDGPU::SGPRRegBankID) << 0) | // SGPR_256_with_sub0_sub1_in_CCR_SGPR_64RegClassID |
| 1166 | (uint32_t(AMDGPU::SGPRRegBankID) << 4) | // SGPR_256_with_sub0_sub1_in_Gfx_CCR_SGPR_64RegClassID |
| 1167 | (uint32_t(AMDGPU::SGPRRegBankID) << 8) | // SGPR_256_with_sub2_sub3_in_CCR_SGPR_64RegClassID |
| 1168 | (uint32_t(AMDGPU::SGPRRegBankID) << 12) | // SGPR_256_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID |
| 1169 | (uint32_t(AMDGPU::SGPRRegBankID) << 16) | // SGPR_256_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_256_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID |
| 1170 | (uint32_t(AMDGPU::SGPRRegBankID) << 20) | // SGPR_256_with_sub6_sub7_in_CCR_SGPR_64RegClassID |
| 1171 | (uint32_t(AMDGPU::SGPRRegBankID) << 24) | // TTMP_256RegClassID |
| 1172 | (uint32_t(InvalidRegBankID) << 28), // AV_288RegClassID |
| 1173 | (uint32_t(AMDGPU::AGPRRegBankID) << 0) | // AReg_288RegClassID |
| 1174 | (uint32_t(InvalidRegBankID) << 4) | // AV_288_Align2RegClassID |
| 1175 | (uint32_t(InvalidRegBankID) << 8) | // AV_288_with_sub1_sub2_in_AV_64_Align2RegClassID |
| 1176 | (uint32_t(AMDGPU::VGPRRegBankID) << 12) | // VReg_288RegClassID |
| 1177 | (uint32_t(AMDGPU::VGPRRegBankID) << 16) | // AV_288_with_hi16_in_VGPR_16_Lo128RegClassID |
| 1178 | (uint32_t(AMDGPU::VGPRRegBankID) << 20) | // AV_288_with_sub1_in_VGPR_32_Lo128RegClassID |
| 1179 | (uint32_t(AMDGPU::VGPRRegBankID) << 24) | // AV_288_with_sub2_in_VGPR_32_Lo128RegClassID |
| 1180 | (uint32_t(AMDGPU::VGPRRegBankID) << 28), // AV_288_with_sub3_in_VGPR_32_Lo128RegClassID |
| 1181 | (uint32_t(AMDGPU::AGPRRegBankID) << 0) | // AReg_288_Align2RegClassID |
| 1182 | (uint32_t(AMDGPU::AGPRRegBankID) << 4) | // AReg_288_with_sub1_sub2_in_AReg_64_Align2RegClassID |
| 1183 | (uint32_t(AMDGPU::VGPRRegBankID) << 8) | // AV_288_with_sub1_sub2_in_VReg_64_Align2RegClassID |
| 1184 | (uint32_t(AMDGPU::VGPRRegBankID) << 12) | // AV_288_with_sub4_in_VGPR_32_Lo128RegClassID |
| 1185 | (uint32_t(AMDGPU::VGPRRegBankID) << 16) | // VReg_288_Align2RegClassID |
| 1186 | (uint32_t(AMDGPU::VGPRRegBankID) << 20) | // AV_288_with_sub5_in_VGPR_32_Lo128RegClassID |
| 1187 | (uint32_t(AMDGPU::VGPRRegBankID) << 24) | // AV_288_with_sub6_in_VGPR_32_Lo128RegClassID |
| 1188 | (uint32_t(AMDGPU::VGPRRegBankID) << 28), // AV_288_with_sub7_in_VGPR_32_Lo128RegClassID |
| 1189 | (uint32_t(AMDGPU::VGPRRegBankID) << 0) | // AV_288_with_sub8_in_VGPR_32_Lo128RegClassID |
| 1190 | (uint32_t(AMDGPU::VGPRRegBankID) << 4) | // AV_288_with_hi16_in_VGPR_16_Lo128_and_AV_288_with_sub1_sub2_in_AV_64_Align2RegClassID |
| 1191 | (uint32_t(AMDGPU::VGPRRegBankID) << 8) | // AV_288_with_sub0_sub1_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID |
| 1192 | (uint32_t(AMDGPU::VGPRRegBankID) << 12) | // AV_288_with_sub0_sub1_sub2_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID |
| 1193 | (uint32_t(AMDGPU::VGPRRegBankID) << 16) | // AV_288_with_sub1_sub2_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID |
| 1194 | (uint32_t(AMDGPU::VGPRRegBankID) << 20) | // AV_288_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID |
| 1195 | (uint32_t(AMDGPU::VGPRRegBankID) << 24) | // AV_288_with_sub2_sub3_sub4_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID |
| 1196 | (uint32_t(AMDGPU::VGPRRegBankID) << 28), // AV_288_with_sub3_sub4_sub5_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID |
| 1197 | (uint32_t(AMDGPU::VGPRRegBankID) << 0) | // AV_288_with_sub4_sub5_sub6_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID |
| 1198 | (uint32_t(AMDGPU::VGPRRegBankID) << 4) | // AV_288_with_sub5_sub6_sub7_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID |
| 1199 | (uint32_t(AMDGPU::VGPRRegBankID) << 8) | // AV_288_with_sub6_sub7_sub8_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID |
| 1200 | (uint32_t(AMDGPU::SGPRRegBankID) << 12) | // SReg_288RegClassID |
| 1201 | (uint32_t(AMDGPU::SGPRRegBankID) << 16) | // SGPR_288RegClassID |
| 1202 | (uint32_t(AMDGPU::SGPRRegBankID) << 20) | // SGPR_288_with_sub0_sub1_in_CCR_SGPR_64RegClassID |
| 1203 | (uint32_t(AMDGPU::SGPRRegBankID) << 24) | // SGPR_288_with_sub0_sub1_in_Gfx_CCR_SGPR_64RegClassID |
| 1204 | (uint32_t(AMDGPU::SGPRRegBankID) << 28), // SGPR_288_with_sub2_sub3_in_CCR_SGPR_64RegClassID |
| 1205 | (uint32_t(AMDGPU::SGPRRegBankID) << 0) | // SGPR_288_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID |
| 1206 | (uint32_t(AMDGPU::SGPRRegBankID) << 4) | // SGPR_288_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_288_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID |
| 1207 | (uint32_t(AMDGPU::SGPRRegBankID) << 8) | // SGPR_288_with_sub6_sub7_in_CCR_SGPR_64RegClassID |
| 1208 | (uint32_t(AMDGPU::SGPRRegBankID) << 12) | // TTMP_288RegClassID |
| 1209 | (uint32_t(InvalidRegBankID) << 16) | // AV_320RegClassID |
| 1210 | (uint32_t(InvalidRegBankID) << 20) | // AV_320_Align2RegClassID |
| 1211 | (uint32_t(AMDGPU::AGPRRegBankID) << 24) | // AReg_320RegClassID |
| 1212 | (uint32_t(AMDGPU::VGPRRegBankID) << 28), // VReg_320RegClassID |
| 1213 | (uint32_t(InvalidRegBankID) << 0) | // AV_320_with_sub1_sub2_in_AV_64_Align2RegClassID |
| 1214 | (uint32_t(AMDGPU::VGPRRegBankID) << 4) | // AV_320_with_hi16_in_VGPR_16_Lo128RegClassID |
| 1215 | (uint32_t(AMDGPU::VGPRRegBankID) << 8) | // AV_320_with_sub1_in_VGPR_32_Lo128RegClassID |
| 1216 | (uint32_t(AMDGPU::VGPRRegBankID) << 12) | // AV_320_with_sub2_in_VGPR_32_Lo128RegClassID |
| 1217 | (uint32_t(AMDGPU::VGPRRegBankID) << 16) | // AV_320_with_sub3_in_VGPR_32_Lo128RegClassID |
| 1218 | (uint32_t(AMDGPU::AGPRRegBankID) << 20) | // AReg_320_Align2RegClassID |
| 1219 | (uint32_t(AMDGPU::VGPRRegBankID) << 24) | // AV_320_with_sub4_in_VGPR_32_Lo128RegClassID |
| 1220 | (uint32_t(AMDGPU::VGPRRegBankID) << 28), // VReg_320_Align2RegClassID |
| 1221 | (uint32_t(AMDGPU::AGPRRegBankID) << 0) | // AReg_320_with_sub1_sub2_in_AReg_64_Align2RegClassID |
| 1222 | (uint32_t(AMDGPU::VGPRRegBankID) << 4) | // AV_320_with_sub1_sub2_in_VReg_64_Align2RegClassID |
| 1223 | (uint32_t(AMDGPU::VGPRRegBankID) << 8) | // AV_320_with_sub5_in_VGPR_32_Lo128RegClassID |
| 1224 | (uint32_t(AMDGPU::VGPRRegBankID) << 12) | // AV_320_with_sub6_in_VGPR_32_Lo128RegClassID |
| 1225 | (uint32_t(AMDGPU::VGPRRegBankID) << 16) | // AV_320_with_sub7_in_VGPR_32_Lo128RegClassID |
| 1226 | (uint32_t(AMDGPU::VGPRRegBankID) << 20) | // AV_320_with_sub8_in_VGPR_32_Lo128RegClassID |
| 1227 | (uint32_t(AMDGPU::VGPRRegBankID) << 24) | // AV_320_with_sub9_in_VGPR_32_Lo128RegClassID |
| 1228 | (uint32_t(AMDGPU::VGPRRegBankID) << 28), // AV_320_with_hi16_in_VGPR_16_Lo128_and_AV_320_with_sub1_sub2_in_AV_64_Align2RegClassID |
| 1229 | (uint32_t(AMDGPU::VGPRRegBankID) << 0) | // AV_320_with_sub0_sub1_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID |
| 1230 | (uint32_t(AMDGPU::VGPRRegBankID) << 4) | // AV_320_with_sub0_sub1_sub2_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID |
| 1231 | (uint32_t(AMDGPU::VGPRRegBankID) << 8) | // AV_320_with_sub1_sub2_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID |
| 1232 | (uint32_t(AMDGPU::VGPRRegBankID) << 12) | // AV_320_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID |
| 1233 | (uint32_t(AMDGPU::VGPRRegBankID) << 16) | // AV_320_with_sub2_sub3_sub4_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID |
| 1234 | (uint32_t(AMDGPU::VGPRRegBankID) << 20) | // AV_320_with_sub3_sub4_sub5_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID |
| 1235 | (uint32_t(AMDGPU::VGPRRegBankID) << 24) | // AV_320_with_sub4_sub5_sub6_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID |
| 1236 | (uint32_t(AMDGPU::VGPRRegBankID) << 28), // AV_320_with_sub5_sub6_sub7_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID |
| 1237 | (uint32_t(AMDGPU::VGPRRegBankID) << 0) | // AV_320_with_sub6_sub7_sub8_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID |
| 1238 | (uint32_t(AMDGPU::VGPRRegBankID) << 4) | // AV_320_with_sub7_sub8_sub9_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID |
| 1239 | (uint32_t(AMDGPU::SGPRRegBankID) << 8) | // SReg_320RegClassID |
| 1240 | (uint32_t(AMDGPU::SGPRRegBankID) << 12) | // SGPR_320RegClassID |
| 1241 | (uint32_t(AMDGPU::SGPRRegBankID) << 16) | // SGPR_320_with_sub0_sub1_in_CCR_SGPR_64RegClassID |
| 1242 | (uint32_t(AMDGPU::SGPRRegBankID) << 20) | // SGPR_320_with_sub0_sub1_in_Gfx_CCR_SGPR_64RegClassID |
| 1243 | (uint32_t(AMDGPU::SGPRRegBankID) << 24) | // SGPR_320_with_sub2_sub3_in_CCR_SGPR_64RegClassID |
| 1244 | (uint32_t(AMDGPU::SGPRRegBankID) << 28), // SGPR_320_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID |
| 1245 | (uint32_t(AMDGPU::SGPRRegBankID) << 0) | // SGPR_320_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClassID |
| 1246 | (uint32_t(AMDGPU::SGPRRegBankID) << 4) | // SGPR_320_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_320_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID |
| 1247 | (uint32_t(AMDGPU::SGPRRegBankID) << 8) | // SGPR_320_with_sub4_sub5_in_Gfx_CCR_SGPR_64_and_SGPR_320_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClassID |
| 1248 | (uint32_t(AMDGPU::SGPRRegBankID) << 12) | // SGPR_320_with_sub6_sub7_in_CCR_SGPR_64RegClassID |
| 1249 | (uint32_t(AMDGPU::SGPRRegBankID) << 16) | // SGPR_320_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_320_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClassID |
| 1250 | (uint32_t(AMDGPU::SGPRRegBankID) << 20) | // TTMP_320RegClassID |
| 1251 | (uint32_t(AMDGPU::SGPRRegBankID) << 24) | // SGPR_320_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_320_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClassID |
| 1252 | (uint32_t(InvalidRegBankID) << 28), // AV_352RegClassID |
| 1253 | (uint32_t(AMDGPU::AGPRRegBankID) << 0) | // AReg_352RegClassID |
| 1254 | (uint32_t(InvalidRegBankID) << 4) | // AV_352_Align2RegClassID |
| 1255 | (uint32_t(InvalidRegBankID) << 8) | // AV_352_with_sub1_sub2_in_AV_64_Align2RegClassID |
| 1256 | (uint32_t(AMDGPU::VGPRRegBankID) << 12) | // VReg_352RegClassID |
| 1257 | (uint32_t(AMDGPU::VGPRRegBankID) << 16) | // AV_352_with_hi16_in_VGPR_16_Lo128RegClassID |
| 1258 | (uint32_t(AMDGPU::VGPRRegBankID) << 20) | // AV_352_with_sub1_in_VGPR_32_Lo128RegClassID |
| 1259 | (uint32_t(AMDGPU::VGPRRegBankID) << 24) | // AV_352_with_sub2_in_VGPR_32_Lo128RegClassID |
| 1260 | (uint32_t(AMDGPU::VGPRRegBankID) << 28), // AV_352_with_sub3_in_VGPR_32_Lo128RegClassID |
| 1261 | (uint32_t(AMDGPU::VGPRRegBankID) << 0) | // AV_352_with_sub4_in_VGPR_32_Lo128RegClassID |
| 1262 | (uint32_t(AMDGPU::AGPRRegBankID) << 4) | // AReg_352_Align2RegClassID |
| 1263 | (uint32_t(AMDGPU::AGPRRegBankID) << 8) | // AReg_352_with_sub1_sub2_in_AReg_64_Align2RegClassID |
| 1264 | (uint32_t(AMDGPU::VGPRRegBankID) << 12) | // AV_352_with_sub1_sub2_in_VReg_64_Align2RegClassID |
| 1265 | (uint32_t(AMDGPU::VGPRRegBankID) << 16) | // AV_352_with_sub5_in_VGPR_32_Lo128RegClassID |
| 1266 | (uint32_t(AMDGPU::VGPRRegBankID) << 20) | // VReg_352_Align2RegClassID |
| 1267 | (uint32_t(AMDGPU::VGPRRegBankID) << 24) | // AV_352_with_sub6_in_VGPR_32_Lo128RegClassID |
| 1268 | (uint32_t(AMDGPU::VGPRRegBankID) << 28), // AV_352_with_sub7_in_VGPR_32_Lo128RegClassID |
| 1269 | (uint32_t(AMDGPU::VGPRRegBankID) << 0) | // AV_352_with_sub8_in_VGPR_32_Lo128RegClassID |
| 1270 | (uint32_t(AMDGPU::VGPRRegBankID) << 4) | // AV_352_with_sub9_in_VGPR_32_Lo128RegClassID |
| 1271 | (uint32_t(AMDGPU::VGPRRegBankID) << 8) | // AV_352_with_sub10_in_VGPR_32_Lo128RegClassID |
| 1272 | (uint32_t(AMDGPU::VGPRRegBankID) << 12) | // AV_352_with_hi16_in_VGPR_16_Lo128_and_AV_352_with_sub1_sub2_in_AV_64_Align2RegClassID |
| 1273 | (uint32_t(AMDGPU::VGPRRegBankID) << 16) | // AV_352_with_sub0_sub1_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID |
| 1274 | (uint32_t(AMDGPU::VGPRRegBankID) << 20) | // AV_352_with_sub0_sub1_sub2_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID |
| 1275 | (uint32_t(AMDGPU::VGPRRegBankID) << 24) | // AV_352_with_sub1_sub2_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID |
| 1276 | (uint32_t(AMDGPU::VGPRRegBankID) << 28), // AV_352_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID |
| 1277 | (uint32_t(AMDGPU::VGPRRegBankID) << 0) | // AV_352_with_sub2_sub3_sub4_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID |
| 1278 | (uint32_t(AMDGPU::VGPRRegBankID) << 4) | // AV_352_with_sub3_sub4_sub5_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID |
| 1279 | (uint32_t(AMDGPU::VGPRRegBankID) << 8) | // AV_352_with_sub4_sub5_sub6_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID |
| 1280 | (uint32_t(AMDGPU::VGPRRegBankID) << 12) | // AV_352_with_sub5_sub6_sub7_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID |
| 1281 | (uint32_t(AMDGPU::VGPRRegBankID) << 16) | // AV_352_with_sub6_sub7_sub8_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID |
| 1282 | (uint32_t(AMDGPU::VGPRRegBankID) << 20) | // AV_352_with_sub7_sub8_sub9_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID |
| 1283 | (uint32_t(AMDGPU::VGPRRegBankID) << 24) | // AV_352_with_sub8_sub9_sub10_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID |
| 1284 | (uint32_t(AMDGPU::SGPRRegBankID) << 28), // SReg_352RegClassID |
| 1285 | (uint32_t(AMDGPU::SGPRRegBankID) << 0) | // SGPR_352RegClassID |
| 1286 | (uint32_t(AMDGPU::SGPRRegBankID) << 4) | // SGPR_352_with_sub0_sub1_in_CCR_SGPR_64RegClassID |
| 1287 | (uint32_t(AMDGPU::SGPRRegBankID) << 8) | // SGPR_352_with_sub0_sub1_in_Gfx_CCR_SGPR_64RegClassID |
| 1288 | (uint32_t(AMDGPU::SGPRRegBankID) << 12) | // SGPR_352_with_sub2_sub3_in_CCR_SGPR_64RegClassID |
| 1289 | (uint32_t(AMDGPU::SGPRRegBankID) << 16) | // SGPR_352_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID |
| 1290 | (uint32_t(AMDGPU::SGPRRegBankID) << 20) | // SGPR_352_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClassID |
| 1291 | (uint32_t(AMDGPU::SGPRRegBankID) << 24) | // SGPR_352_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_352_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID |
| 1292 | (uint32_t(AMDGPU::SGPRRegBankID) << 28), // SGPR_352_with_sub4_sub5_in_Gfx_CCR_SGPR_64_and_SGPR_352_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClassID |
| 1293 | (uint32_t(AMDGPU::SGPRRegBankID) << 0) | // SGPR_352_with_sub6_sub7_in_CCR_SGPR_64RegClassID |
| 1294 | (uint32_t(AMDGPU::SGPRRegBankID) << 4) | // SGPR_352_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_352_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClassID |
| 1295 | (uint32_t(AMDGPU::SGPRRegBankID) << 8) | // TTMP_352RegClassID |
| 1296 | (uint32_t(AMDGPU::SGPRRegBankID) << 12) | // SGPR_352_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_352_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClassID |
| 1297 | (uint32_t(InvalidRegBankID) << 16) | // AV_384RegClassID |
| 1298 | (uint32_t(InvalidRegBankID) << 20) | // AV_384_Align2RegClassID |
| 1299 | (uint32_t(AMDGPU::AGPRRegBankID) << 24) | // AReg_384RegClassID |
| 1300 | (uint32_t(AMDGPU::VGPRRegBankID) << 28), // VReg_384RegClassID |
| 1301 | (uint32_t(InvalidRegBankID) << 0) | // AV_384_with_sub1_sub2_in_AV_64_Align2RegClassID |
| 1302 | (uint32_t(AMDGPU::VGPRRegBankID) << 4) | // AV_384_with_hi16_in_VGPR_16_Lo128RegClassID |
| 1303 | (uint32_t(AMDGPU::VGPRRegBankID) << 8) | // AV_384_with_sub1_in_VGPR_32_Lo128RegClassID |
| 1304 | (uint32_t(AMDGPU::VGPRRegBankID) << 12) | // AV_384_with_sub2_in_VGPR_32_Lo128RegClassID |
| 1305 | (uint32_t(AMDGPU::VGPRRegBankID) << 16) | // AV_384_with_sub3_in_VGPR_32_Lo128RegClassID |
| 1306 | (uint32_t(AMDGPU::VGPRRegBankID) << 20) | // AV_384_with_sub4_in_VGPR_32_Lo128RegClassID |
| 1307 | (uint32_t(AMDGPU::AGPRRegBankID) << 24) | // AReg_384_Align2RegClassID |
| 1308 | (uint32_t(AMDGPU::VGPRRegBankID) << 28), // AV_384_with_sub5_in_VGPR_32_Lo128RegClassID |
| 1309 | (uint32_t(AMDGPU::VGPRRegBankID) << 0) | // VReg_384_Align2RegClassID |
| 1310 | (uint32_t(AMDGPU::AGPRRegBankID) << 4) | // AReg_384_with_sub1_sub2_in_AReg_64_Align2RegClassID |
| 1311 | (uint32_t(AMDGPU::VGPRRegBankID) << 8) | // AV_384_with_sub1_sub2_in_VReg_64_Align2RegClassID |
| 1312 | (uint32_t(AMDGPU::VGPRRegBankID) << 12) | // AV_384_with_sub6_in_VGPR_32_Lo128RegClassID |
| 1313 | (uint32_t(AMDGPU::VGPRRegBankID) << 16) | // AV_384_with_sub7_in_VGPR_32_Lo128RegClassID |
| 1314 | (uint32_t(AMDGPU::VGPRRegBankID) << 20) | // AV_384_with_sub8_in_VGPR_32_Lo128RegClassID |
| 1315 | (uint32_t(AMDGPU::VGPRRegBankID) << 24) | // AV_384_with_sub9_in_VGPR_32_Lo128RegClassID |
| 1316 | (uint32_t(AMDGPU::VGPRRegBankID) << 28), // AV_384_with_sub10_in_VGPR_32_Lo128RegClassID |
| 1317 | (uint32_t(AMDGPU::VGPRRegBankID) << 0) | // AV_384_with_sub11_in_VGPR_32_Lo128RegClassID |
| 1318 | (uint32_t(AMDGPU::VGPRRegBankID) << 4) | // AV_384_with_hi16_in_VGPR_16_Lo128_and_AV_384_with_sub1_sub2_in_AV_64_Align2RegClassID |
| 1319 | (uint32_t(AMDGPU::VGPRRegBankID) << 8) | // AV_384_with_sub0_sub1_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID |
| 1320 | (uint32_t(AMDGPU::VGPRRegBankID) << 12) | // AV_384_with_sub0_sub1_sub2_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID |
| 1321 | (uint32_t(AMDGPU::VGPRRegBankID) << 16) | // AV_384_with_sub1_sub2_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID |
| 1322 | (uint32_t(AMDGPU::VGPRRegBankID) << 20) | // AV_384_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID |
| 1323 | (uint32_t(AMDGPU::VGPRRegBankID) << 24) | // AV_384_with_sub2_sub3_sub4_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID |
| 1324 | (uint32_t(AMDGPU::VGPRRegBankID) << 28), // AV_384_with_sub3_sub4_sub5_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID |
| 1325 | (uint32_t(AMDGPU::VGPRRegBankID) << 0) | // AV_384_with_sub4_sub5_sub6_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID |
| 1326 | (uint32_t(AMDGPU::VGPRRegBankID) << 4) | // AV_384_with_sub5_sub6_sub7_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID |
| 1327 | (uint32_t(AMDGPU::VGPRRegBankID) << 8) | // AV_384_with_sub6_sub7_sub8_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID |
| 1328 | (uint32_t(AMDGPU::VGPRRegBankID) << 12) | // AV_384_with_sub7_sub8_sub9_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID |
| 1329 | (uint32_t(AMDGPU::VGPRRegBankID) << 16) | // AV_384_with_sub8_sub9_sub10_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID |
| 1330 | (uint32_t(AMDGPU::VGPRRegBankID) << 20) | // AV_384_with_sub9_sub10_sub11_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID |
| 1331 | (uint32_t(AMDGPU::SGPRRegBankID) << 24) | // SReg_384RegClassID |
| 1332 | (uint32_t(AMDGPU::SGPRRegBankID) << 28), // SGPR_384RegClassID |
| 1333 | (uint32_t(AMDGPU::SGPRRegBankID) << 0) | // SGPR_384_with_sub0_sub1_in_CCR_SGPR_64RegClassID |
| 1334 | (uint32_t(AMDGPU::SGPRRegBankID) << 4) | // SGPR_384_with_sub0_sub1_in_Gfx_CCR_SGPR_64RegClassID |
| 1335 | (uint32_t(AMDGPU::SGPRRegBankID) << 8) | // SGPR_384_with_sub2_sub3_in_CCR_SGPR_64RegClassID |
| 1336 | (uint32_t(AMDGPU::SGPRRegBankID) << 12) | // SGPR_384_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID |
| 1337 | (uint32_t(AMDGPU::SGPRRegBankID) << 16) | // SGPR_384_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClassID |
| 1338 | (uint32_t(AMDGPU::SGPRRegBankID) << 20) | // SGPR_384_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_384_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID |
| 1339 | (uint32_t(AMDGPU::SGPRRegBankID) << 24) | // SGPR_384_with_sub4_sub5_in_Gfx_CCR_SGPR_64_and_SGPR_384_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClassID |
| 1340 | (uint32_t(AMDGPU::SGPRRegBankID) << 28), // SGPR_384_with_sub6_sub7_in_CCR_SGPR_64RegClassID |
| 1341 | (uint32_t(AMDGPU::SGPRRegBankID) << 0) | // SGPR_384_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_384_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClassID |
| 1342 | (uint32_t(AMDGPU::SGPRRegBankID) << 4) | // SGPR_384_with_sub10_sub11_in_CCR_SGPR_64RegClassID |
| 1343 | (uint32_t(AMDGPU::SGPRRegBankID) << 8) | // TTMP_384RegClassID |
| 1344 | (uint32_t(AMDGPU::SGPRRegBankID) << 12) | // SGPR_384_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_384_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClassID |
| 1345 | (uint32_t(InvalidRegBankID) << 16) | // AV_512RegClassID |
| 1346 | (uint32_t(InvalidRegBankID) << 20) | // AV_512_Align2RegClassID |
| 1347 | (uint32_t(AMDGPU::AGPRRegBankID) << 24) | // AReg_512RegClassID |
| 1348 | (uint32_t(AMDGPU::VGPRRegBankID) << 28), // VReg_512RegClassID |
| 1349 | (uint32_t(InvalidRegBankID) << 0) | // AV_512_with_sub1_sub2_in_AV_64_Align2RegClassID |
| 1350 | (uint32_t(AMDGPU::VGPRRegBankID) << 4) | // AV_512_with_hi16_in_VGPR_16_Lo128RegClassID |
| 1351 | (uint32_t(AMDGPU::VGPRRegBankID) << 8) | // AV_512_with_sub1_in_VGPR_32_Lo128RegClassID |
| 1352 | (uint32_t(AMDGPU::VGPRRegBankID) << 12) | // AV_512_with_sub2_in_VGPR_32_Lo128RegClassID |
| 1353 | (uint32_t(AMDGPU::VGPRRegBankID) << 16) | // AV_512_with_sub3_in_VGPR_32_Lo128RegClassID |
| 1354 | (uint32_t(AMDGPU::VGPRRegBankID) << 20) | // AV_512_with_sub4_in_VGPR_32_Lo128RegClassID |
| 1355 | (uint32_t(AMDGPU::VGPRRegBankID) << 24) | // AV_512_with_sub5_in_VGPR_32_Lo128RegClassID |
| 1356 | (uint32_t(AMDGPU::VGPRRegBankID) << 28), // AV_512_with_sub6_in_VGPR_32_Lo128RegClassID |
| 1357 | (uint32_t(AMDGPU::AGPRRegBankID) << 0) | // AReg_512_Align2RegClassID |
| 1358 | (uint32_t(AMDGPU::VGPRRegBankID) << 4) | // AV_512_with_sub7_in_VGPR_32_Lo128RegClassID |
| 1359 | (uint32_t(AMDGPU::VGPRRegBankID) << 8) | // VReg_512_Align2RegClassID |
| 1360 | (uint32_t(AMDGPU::AGPRRegBankID) << 12) | // AReg_512_with_sub1_sub2_in_AReg_64_Align2RegClassID |
| 1361 | (uint32_t(AMDGPU::VGPRRegBankID) << 16) | // AV_512_with_sub1_sub2_in_VReg_64_Align2RegClassID |
| 1362 | (uint32_t(AMDGPU::VGPRRegBankID) << 20) | // AV_512_with_sub8_in_VGPR_32_Lo128RegClassID |
| 1363 | (uint32_t(AMDGPU::VGPRRegBankID) << 24) | // AV_512_with_sub9_in_VGPR_32_Lo128RegClassID |
| 1364 | (uint32_t(AMDGPU::VGPRRegBankID) << 28), // AV_512_with_sub10_in_VGPR_32_Lo128RegClassID |
| 1365 | (uint32_t(AMDGPU::VGPRRegBankID) << 0) | // AV_512_with_sub11_in_VGPR_32_Lo128RegClassID |
| 1366 | (uint32_t(AMDGPU::VGPRRegBankID) << 4) | // AV_512_with_sub12_in_VGPR_32_Lo128RegClassID |
| 1367 | (uint32_t(AMDGPU::VGPRRegBankID) << 8) | // AV_512_with_sub13_in_VGPR_32_Lo128RegClassID |
| 1368 | (uint32_t(AMDGPU::VGPRRegBankID) << 12) | // AV_512_with_sub14_in_VGPR_32_Lo128RegClassID |
| 1369 | (uint32_t(AMDGPU::VGPRRegBankID) << 16) | // AV_512_with_sub15_in_VGPR_32_Lo128RegClassID |
| 1370 | (uint32_t(AMDGPU::VGPRRegBankID) << 20) | // AV_512_with_hi16_in_VGPR_16_Lo128_and_AV_512_with_sub1_sub2_in_AV_64_Align2RegClassID |
| 1371 | (uint32_t(AMDGPU::VGPRRegBankID) << 24) | // AV_512_with_sub0_sub1_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID |
| 1372 | (uint32_t(AMDGPU::VGPRRegBankID) << 28), // AV_512_with_sub0_sub1_sub2_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID |
| 1373 | (uint32_t(AMDGPU::VGPRRegBankID) << 0) | // AV_512_with_sub1_sub2_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID |
| 1374 | (uint32_t(AMDGPU::VGPRRegBankID) << 4) | // AV_512_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID |
| 1375 | (uint32_t(AMDGPU::VGPRRegBankID) << 8) | // AV_512_with_sub2_sub3_sub4_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID |
| 1376 | (uint32_t(AMDGPU::VGPRRegBankID) << 12) | // AV_512_with_sub3_sub4_sub5_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID |
| 1377 | (uint32_t(AMDGPU::VGPRRegBankID) << 16) | // AV_512_with_sub4_sub5_sub6_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID |
| 1378 | (uint32_t(AMDGPU::VGPRRegBankID) << 20) | // AV_512_with_sub5_sub6_sub7_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID |
| 1379 | (uint32_t(AMDGPU::VGPRRegBankID) << 24) | // AV_512_with_sub6_sub7_sub8_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID |
| 1380 | (uint32_t(AMDGPU::VGPRRegBankID) << 28), // AV_512_with_sub7_sub8_sub9_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID |
| 1381 | (uint32_t(AMDGPU::VGPRRegBankID) << 0) | // AV_512_with_sub8_sub9_sub10_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID |
| 1382 | (uint32_t(AMDGPU::VGPRRegBankID) << 4) | // AV_512_with_sub10_sub11_sub12_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID |
| 1383 | (uint32_t(AMDGPU::VGPRRegBankID) << 8) | // AV_512_with_sub9_sub10_sub11_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID |
| 1384 | (uint32_t(AMDGPU::VGPRRegBankID) << 12) | // AV_512_with_sub11_sub12_sub13_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID |
| 1385 | (uint32_t(AMDGPU::VGPRRegBankID) << 16) | // AV_512_with_sub12_sub13_sub14_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID |
| 1386 | (uint32_t(AMDGPU::VGPRRegBankID) << 20) | // AV_512_with_sub13_sub14_sub15_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID |
| 1387 | (uint32_t(AMDGPU::SGPRRegBankID) << 24) | // SReg_512RegClassID |
| 1388 | (uint32_t(AMDGPU::SGPRRegBankID) << 28), // SGPR_512RegClassID |
| 1389 | (uint32_t(AMDGPU::SGPRRegBankID) << 0) | // SGPR_512_with_sub0_sub1_in_CCR_SGPR_64RegClassID |
| 1390 | (uint32_t(AMDGPU::SGPRRegBankID) << 4) | // SGPR_512_with_sub0_sub1_in_Gfx_CCR_SGPR_64RegClassID |
| 1391 | (uint32_t(AMDGPU::SGPRRegBankID) << 8) | // SGPR_512_with_sub12_sub13_in_Gfx_CCR_SGPR_64RegClassID |
| 1392 | (uint32_t(AMDGPU::SGPRRegBankID) << 12) | // SGPR_512_with_sub2_sub3_in_CCR_SGPR_64RegClassID |
| 1393 | (uint32_t(AMDGPU::SGPRRegBankID) << 16) | // SGPR_512_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID |
| 1394 | (uint32_t(AMDGPU::SGPRRegBankID) << 20) | // SGPR_512_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClassID |
| 1395 | (uint32_t(AMDGPU::SGPRRegBankID) << 24) | // SGPR_512_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_512_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID |
| 1396 | (uint32_t(AMDGPU::SGPRRegBankID) << 28), // SGPR_512_with_sub4_sub5_in_Gfx_CCR_SGPR_64_and_SGPR_512_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClassID |
| 1397 | (uint32_t(AMDGPU::SGPRRegBankID) << 0) | // SGPR_512_with_sub6_sub7_in_CCR_SGPR_64RegClassID |
| 1398 | (uint32_t(AMDGPU::SGPRRegBankID) << 4) | // SGPR_512_with_sub8_sub9_in_Gfx_CCR_SGPR_64_and_SGPR_512_with_sub12_sub13_in_Gfx_CCR_SGPR_64RegClassID |
| 1399 | (uint32_t(AMDGPU::SGPRRegBankID) << 8) | // SGPR_512_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_512_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClassID |
| 1400 | (uint32_t(AMDGPU::SGPRRegBankID) << 12) | // SGPR_512_with_sub10_sub11_in_CCR_SGPR_64RegClassID |
| 1401 | (uint32_t(AMDGPU::SGPRRegBankID) << 16) | // SGPR_512_with_sub4_sub5_in_Gfx_CCR_SGPR_64_and_SGPR_512_with_sub12_sub13_in_Gfx_CCR_SGPR_64RegClassID |
| 1402 | (uint32_t(AMDGPU::SGPRRegBankID) << 20) | // SGPR_512_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_512_with_sub12_sub13_in_Gfx_CCR_SGPR_64RegClassID |
| 1403 | (uint32_t(AMDGPU::SGPRRegBankID) << 24) | // SGPR_512_with_sub14_sub15_in_CCR_SGPR_64RegClassID |
| 1404 | (uint32_t(AMDGPU::SGPRRegBankID) << 28), // SGPR_512_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_512_with_sub12_sub13_in_Gfx_CCR_SGPR_64RegClassID |
| 1405 | (uint32_t(AMDGPU::SGPRRegBankID) << 0) | // SGPR_512_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_512_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClassID |
| 1406 | (uint32_t(AMDGPU::SGPRRegBankID) << 4) | // SGPR_512_with_sub0_sub1_in_CCR_SGPR_64_with_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16_sub12_lo16_sub12_hi16_sub13_lo16_sub13_hi16_sub14_lo16_sub14_hi16_sub15_lo16_sub15_hi16_in_SGPR_384_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_384_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClassID |
| 1407 | (uint32_t(AMDGPU::SGPRRegBankID) << 8) | // TTMP_512RegClassID |
| 1408 | (uint32_t(InvalidRegBankID) << 12) | |
| 1409 | (uint32_t(InvalidRegBankID) << 16) | |
| 1410 | (uint32_t(AMDGPU::AGPRRegBankID) << 20) | // AReg_1024RegClassID |
| 1411 | (uint32_t(AMDGPU::VGPRRegBankID) << 24) | // VReg_1024RegClassID |
| 1412 | (uint32_t(InvalidRegBankID) << 28), |
| 1413 | (uint32_t(AMDGPU::VGPRRegBankID) << 0) | // AV_1024_with_hi16_in_VGPR_16_Lo128RegClassID |
| 1414 | (uint32_t(AMDGPU::VGPRRegBankID) << 4) | // AV_1024_with_sub1_in_VGPR_32_Lo128RegClassID |
| 1415 | (uint32_t(AMDGPU::VGPRRegBankID) << 8) | // AV_1024_with_sub2_in_VGPR_32_Lo128RegClassID |
| 1416 | (uint32_t(AMDGPU::VGPRRegBankID) << 12) | // AV_1024_with_sub3_in_VGPR_32_Lo128RegClassID |
| 1417 | (uint32_t(AMDGPU::VGPRRegBankID) << 16) | // AV_1024_with_sub4_in_VGPR_32_Lo128RegClassID |
| 1418 | (uint32_t(AMDGPU::VGPRRegBankID) << 20) | // AV_1024_with_sub5_in_VGPR_32_Lo128RegClassID |
| 1419 | (uint32_t(AMDGPU::VGPRRegBankID) << 24) | // AV_1024_with_sub6_in_VGPR_32_Lo128RegClassID |
| 1420 | (uint32_t(AMDGPU::VGPRRegBankID) << 28), // AV_1024_with_sub7_in_VGPR_32_Lo128RegClassID |
| 1421 | (uint32_t(AMDGPU::VGPRRegBankID) << 0) | // AV_1024_with_sub8_in_VGPR_32_Lo128RegClassID |
| 1422 | (uint32_t(AMDGPU::VGPRRegBankID) << 4) | // AV_1024_with_sub9_in_VGPR_32_Lo128RegClassID |
| 1423 | (uint32_t(AMDGPU::VGPRRegBankID) << 8) | // AV_1024_with_sub10_in_VGPR_32_Lo128RegClassID |
| 1424 | (uint32_t(AMDGPU::VGPRRegBankID) << 12) | // AV_1024_with_sub11_in_VGPR_32_Lo128RegClassID |
| 1425 | (uint32_t(AMDGPU::VGPRRegBankID) << 16) | // AV_1024_with_sub12_in_VGPR_32_Lo128RegClassID |
| 1426 | (uint32_t(AMDGPU::VGPRRegBankID) << 20) | // AV_1024_with_sub13_in_VGPR_32_Lo128RegClassID |
| 1427 | (uint32_t(AMDGPU::VGPRRegBankID) << 24) | // AV_1024_with_sub14_in_VGPR_32_Lo128RegClassID |
| 1428 | (uint32_t(AMDGPU::AGPRRegBankID) << 28), // AReg_1024_Align2RegClassID |
| 1429 | (uint32_t(AMDGPU::VGPRRegBankID) << 0) | // AV_1024_with_sub15_in_VGPR_32_Lo128RegClassID |
| 1430 | (uint32_t(AMDGPU::VGPRRegBankID) << 4) | // VReg_1024_Align2RegClassID |
| 1431 | (uint32_t(AMDGPU::AGPRRegBankID) << 8) | // AReg_1024_with_sub1_sub2_in_AReg_64_Align2RegClassID |
| 1432 | (uint32_t(AMDGPU::VGPRRegBankID) << 12) | // AV_1024_with_sub16_in_VGPR_32_Lo128RegClassID |
| 1433 | (uint32_t(AMDGPU::VGPRRegBankID) << 16) | // AV_1024_with_sub1_sub2_in_VReg_64_Align2RegClassID |
| 1434 | (uint32_t(AMDGPU::VGPRRegBankID) << 20) | // AV_1024_with_sub17_in_VGPR_32_Lo128RegClassID |
| 1435 | (uint32_t(AMDGPU::VGPRRegBankID) << 24) | // AV_1024_with_sub18_in_VGPR_32_Lo128RegClassID |
| 1436 | (uint32_t(AMDGPU::VGPRRegBankID) << 28), // AV_1024_with_sub19_in_VGPR_32_Lo128RegClassID |
| 1437 | (uint32_t(AMDGPU::VGPRRegBankID) << 0) | // AV_1024_with_sub20_in_VGPR_32_Lo128RegClassID |
| 1438 | (uint32_t(AMDGPU::VGPRRegBankID) << 4) | // AV_1024_with_sub21_in_VGPR_32_Lo128RegClassID |
| 1439 | (uint32_t(AMDGPU::VGPRRegBankID) << 8) | // AV_1024_with_sub22_in_VGPR_32_Lo128RegClassID |
| 1440 | (uint32_t(AMDGPU::VGPRRegBankID) << 12) | // AV_1024_with_sub23_in_VGPR_32_Lo128RegClassID |
| 1441 | (uint32_t(AMDGPU::VGPRRegBankID) << 16) | // AV_1024_with_sub24_in_VGPR_32_Lo128RegClassID |
| 1442 | (uint32_t(AMDGPU::VGPRRegBankID) << 20) | // AV_1024_with_sub25_in_VGPR_32_Lo128RegClassID |
| 1443 | (uint32_t(AMDGPU::VGPRRegBankID) << 24) | // AV_1024_with_sub26_in_VGPR_32_Lo128RegClassID |
| 1444 | (uint32_t(AMDGPU::VGPRRegBankID) << 28), // AV_1024_with_sub27_in_VGPR_32_Lo128RegClassID |
| 1445 | (uint32_t(AMDGPU::VGPRRegBankID) << 0) | // AV_1024_with_sub28_in_VGPR_32_Lo128RegClassID |
| 1446 | (uint32_t(AMDGPU::VGPRRegBankID) << 4) | // AV_1024_with_sub29_in_VGPR_32_Lo128RegClassID |
| 1447 | (uint32_t(AMDGPU::VGPRRegBankID) << 8) | // AV_1024_with_sub30_in_VGPR_32_Lo128RegClassID |
| 1448 | (uint32_t(AMDGPU::VGPRRegBankID) << 12) | // AV_1024_with_sub31_in_VGPR_32_Lo128RegClassID |
| 1449 | (uint32_t(AMDGPU::VGPRRegBankID) << 16) | // AV_1024_with_hi16_in_VGPR_16_Lo128_and_AV_1024_with_sub1_sub2_in_AV_64_Align2RegClassID |
| 1450 | (uint32_t(AMDGPU::VGPRRegBankID) << 20) | // AV_1024_with_sub0_sub1_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID |
| 1451 | (uint32_t(AMDGPU::VGPRRegBankID) << 24) | // AV_1024_with_sub0_sub1_sub2_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID |
| 1452 | (uint32_t(AMDGPU::VGPRRegBankID) << 28), // AV_1024_with_sub1_sub2_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID |
| 1453 | (uint32_t(AMDGPU::VGPRRegBankID) << 0) | // AV_1024_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID |
| 1454 | (uint32_t(AMDGPU::VGPRRegBankID) << 4) | // AV_1024_with_sub2_sub3_sub4_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID |
| 1455 | (uint32_t(AMDGPU::VGPRRegBankID) << 8) | // AV_1024_with_sub3_sub4_sub5_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID |
| 1456 | (uint32_t(AMDGPU::VGPRRegBankID) << 12) | // AV_1024_with_sub4_sub5_sub6_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID |
| 1457 | (uint32_t(AMDGPU::VGPRRegBankID) << 16) | // AV_1024_with_sub5_sub6_sub7_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID |
| 1458 | (uint32_t(AMDGPU::VGPRRegBankID) << 20) | // AV_1024_with_sub6_sub7_sub8_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID |
| 1459 | (uint32_t(AMDGPU::VGPRRegBankID) << 24) | // AV_1024_with_sub7_sub8_sub9_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID |
| 1460 | (uint32_t(AMDGPU::VGPRRegBankID) << 28), // AV_1024_with_sub8_sub9_sub10_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID |
| 1461 | (uint32_t(AMDGPU::VGPRRegBankID) << 0) | // AV_1024_with_sub10_sub11_sub12_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID |
| 1462 | (uint32_t(AMDGPU::VGPRRegBankID) << 4) | // AV_1024_with_sub9_sub10_sub11_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID |
| 1463 | (uint32_t(AMDGPU::VGPRRegBankID) << 8) | // AV_1024_with_sub11_sub12_sub13_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID |
| 1464 | (uint32_t(AMDGPU::VGPRRegBankID) << 12) | // AV_1024_with_sub12_sub13_sub14_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID |
| 1465 | (uint32_t(AMDGPU::VGPRRegBankID) << 16) | // AV_1024_with_sub13_sub14_sub15_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID |
| 1466 | (uint32_t(AMDGPU::VGPRRegBankID) << 20) | // AV_1024_with_sub14_sub15_sub16_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID |
| 1467 | (uint32_t(AMDGPU::VGPRRegBankID) << 24) | // AV_1024_with_sub15_sub16_sub17_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID |
| 1468 | (uint32_t(AMDGPU::VGPRRegBankID) << 28), // AV_1024_with_sub16_sub17_sub18_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID |
| 1469 | (uint32_t(AMDGPU::VGPRRegBankID) << 0) | // AV_1024_with_sub17_sub18_sub19_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID |
| 1470 | (uint32_t(AMDGPU::VGPRRegBankID) << 4) | // AV_1024_with_sub18_sub19_sub20_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID |
| 1471 | (uint32_t(AMDGPU::VGPRRegBankID) << 8) | // AV_1024_with_sub19_sub20_sub21_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID |
| 1472 | (uint32_t(AMDGPU::VGPRRegBankID) << 12) | // AV_1024_with_sub20_sub21_sub22_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID |
| 1473 | (uint32_t(AMDGPU::VGPRRegBankID) << 16) | // AV_1024_with_sub21_sub22_sub23_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID |
| 1474 | (uint32_t(AMDGPU::VGPRRegBankID) << 20) | // AV_1024_with_sub22_sub23_sub24_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID |
| 1475 | (uint32_t(AMDGPU::VGPRRegBankID) << 24) | // AV_1024_with_sub23_sub24_sub25_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID |
| 1476 | (uint32_t(AMDGPU::VGPRRegBankID) << 28), // AV_1024_with_sub24_sub25_sub26_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID |
| 1477 | (uint32_t(AMDGPU::VGPRRegBankID) << 0) | // AV_1024_with_sub25_sub26_sub27_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID |
| 1478 | (uint32_t(AMDGPU::VGPRRegBankID) << 4) | // AV_1024_with_sub26_sub27_sub28_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID |
| 1479 | (uint32_t(AMDGPU::VGPRRegBankID) << 8) | // AV_1024_with_sub27_sub28_sub29_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID |
| 1480 | (uint32_t(AMDGPU::VGPRRegBankID) << 12) | // AV_1024_with_sub28_sub29_sub30_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID |
| 1481 | (uint32_t(AMDGPU::VGPRRegBankID) << 16) | // AV_1024_with_sub29_sub30_sub31_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID |
| 1482 | (uint32_t(AMDGPU::SGPRRegBankID) << 20) | // SGPR_1024RegClassID |
| 1483 | (uint32_t(AMDGPU::SGPRRegBankID) << 24) | // SReg_1024RegClassID |
| 1484 | (uint32_t(AMDGPU::SGPRRegBankID) << 28), // SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64RegClassID |
| 1485 | (uint32_t(AMDGPU::SGPRRegBankID) << 0) | // SGPR_1024_with_sub0_sub1_in_Gfx_CCR_SGPR_64RegClassID |
| 1486 | (uint32_t(AMDGPU::SGPRRegBankID) << 4) | // SGPR_1024_with_sub12_sub13_in_Gfx_CCR_SGPR_64RegClassID |
| 1487 | (uint32_t(AMDGPU::SGPRRegBankID) << 8) | // SGPR_1024_with_sub16_sub17_in_Gfx_CCR_SGPR_64RegClassID |
| 1488 | (uint32_t(AMDGPU::SGPRRegBankID) << 12) | // SGPR_1024_with_sub20_sub21_in_Gfx_CCR_SGPR_64RegClassID |
| 1489 | (uint32_t(AMDGPU::SGPRRegBankID) << 16) | // SGPR_1024_with_sub24_sub25_in_Gfx_CCR_SGPR_64RegClassID |
| 1490 | (uint32_t(AMDGPU::SGPRRegBankID) << 20) | // SGPR_1024_with_sub28_sub29_in_Gfx_CCR_SGPR_64RegClassID |
| 1491 | (uint32_t(AMDGPU::SGPRRegBankID) << 24) | // SGPR_1024_with_sub2_sub3_in_CCR_SGPR_64RegClassID |
| 1492 | (uint32_t(AMDGPU::SGPRRegBankID) << 28), // SGPR_1024_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID |
| 1493 | (uint32_t(AMDGPU::SGPRRegBankID) << 0) | // SGPR_1024_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClassID |
| 1494 | (uint32_t(AMDGPU::SGPRRegBankID) << 4) | // SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_1024_with_sub28_sub29_in_Gfx_CCR_SGPR_64RegClassID |
| 1495 | (uint32_t(AMDGPU::SGPRRegBankID) << 8) | // SGPR_1024_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID |
| 1496 | (uint32_t(AMDGPU::SGPRRegBankID) << 12) | // SGPR_1024_with_sub12_sub13_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub16_sub17_in_Gfx_CCR_SGPR_64RegClassID |
| 1497 | (uint32_t(AMDGPU::SGPRRegBankID) << 16) | // SGPR_1024_with_sub16_sub17_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub20_sub21_in_Gfx_CCR_SGPR_64RegClassID |
| 1498 | (uint32_t(AMDGPU::SGPRRegBankID) << 20) | // SGPR_1024_with_sub20_sub21_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub24_sub25_in_Gfx_CCR_SGPR_64RegClassID |
| 1499 | (uint32_t(AMDGPU::SGPRRegBankID) << 24) | // SGPR_1024_with_sub24_sub25_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub28_sub29_in_Gfx_CCR_SGPR_64RegClassID |
| 1500 | (uint32_t(AMDGPU::SGPRRegBankID) << 28), // SGPR_1024_with_sub4_sub5_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClassID |
| 1501 | (uint32_t(AMDGPU::SGPRRegBankID) << 0) | // SGPR_1024_with_sub6_sub7_in_CCR_SGPR_64RegClassID |
| 1502 | (uint32_t(AMDGPU::SGPRRegBankID) << 4) | // SGPR_1024_with_sub8_sub9_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub12_sub13_in_Gfx_CCR_SGPR_64RegClassID |
| 1503 | (uint32_t(AMDGPU::SGPRRegBankID) << 8) | // SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_1024_with_sub24_sub25_in_Gfx_CCR_SGPR_64RegClassID |
| 1504 | (uint32_t(AMDGPU::SGPRRegBankID) << 12) | // SGPR_1024_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClassID |
| 1505 | (uint32_t(AMDGPU::SGPRRegBankID) << 16) | // SGPR_1024_with_sub10_sub11_in_CCR_SGPR_64RegClassID |
| 1506 | (uint32_t(AMDGPU::SGPRRegBankID) << 20) | // SGPR_1024_with_sub12_sub13_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub20_sub21_in_Gfx_CCR_SGPR_64RegClassID |
| 1507 | (uint32_t(AMDGPU::SGPRRegBankID) << 24) | // SGPR_1024_with_sub16_sub17_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub24_sub25_in_Gfx_CCR_SGPR_64RegClassID |
| 1508 | (uint32_t(AMDGPU::SGPRRegBankID) << 28), // SGPR_1024_with_sub20_sub21_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub28_sub29_in_Gfx_CCR_SGPR_64RegClassID |
| 1509 | (uint32_t(AMDGPU::SGPRRegBankID) << 0) | // SGPR_1024_with_sub2_sub3_in_CCR_SGPR_64_and_SGPR_1024_with_sub28_sub29_in_Gfx_CCR_SGPR_64RegClassID |
| 1510 | (uint32_t(AMDGPU::SGPRRegBankID) << 4) | // SGPR_1024_with_sub4_sub5_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub12_sub13_in_Gfx_CCR_SGPR_64RegClassID |
| 1511 | (uint32_t(AMDGPU::SGPRRegBankID) << 8) | // SGPR_1024_with_sub8_sub9_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub16_sub17_in_Gfx_CCR_SGPR_64RegClassID |
| 1512 | (uint32_t(AMDGPU::SGPRRegBankID) << 12) | // SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_1024_with_sub20_sub21_in_Gfx_CCR_SGPR_64RegClassID |
| 1513 | (uint32_t(AMDGPU::SGPRRegBankID) << 16) | // SGPR_1024_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub12_sub13_in_Gfx_CCR_SGPR_64RegClassID |
| 1514 | (uint32_t(AMDGPU::SGPRRegBankID) << 20) | // SGPR_1024_with_sub12_sub13_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub24_sub25_in_Gfx_CCR_SGPR_64RegClassID |
| 1515 | (uint32_t(AMDGPU::SGPRRegBankID) << 24) | // SGPR_1024_with_sub14_sub15_in_CCR_SGPR_64RegClassID |
| 1516 | (uint32_t(AMDGPU::SGPRRegBankID) << 28), // SGPR_1024_with_sub16_sub17_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub28_sub29_in_Gfx_CCR_SGPR_64RegClassID |
| 1517 | (uint32_t(AMDGPU::SGPRRegBankID) << 0) | // SGPR_1024_with_sub2_sub3_in_CCR_SGPR_64_and_SGPR_1024_with_sub24_sub25_in_Gfx_CCR_SGPR_64RegClassID |
| 1518 | (uint32_t(AMDGPU::SGPRRegBankID) << 4) | // SGPR_1024_with_sub4_sub5_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub16_sub17_in_Gfx_CCR_SGPR_64RegClassID |
| 1519 | (uint32_t(AMDGPU::SGPRRegBankID) << 8) | // SGPR_1024_with_sub6_sub7_in_CCR_SGPR_64_and_SGPR_1024_with_sub28_sub29_in_Gfx_CCR_SGPR_64RegClassID |
| 1520 | (uint32_t(AMDGPU::SGPRRegBankID) << 12) | // SGPR_1024_with_sub8_sub9_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub20_sub21_in_Gfx_CCR_SGPR_64RegClassID |
| 1521 | (uint32_t(AMDGPU::SGPRRegBankID) << 16) | // SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_1024_with_sub16_sub17_in_Gfx_CCR_SGPR_64RegClassID |
| 1522 | (uint32_t(AMDGPU::SGPRRegBankID) << 20) | // SGPR_1024_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub16_sub17_in_Gfx_CCR_SGPR_64RegClassID |
| 1523 | (uint32_t(AMDGPU::SGPRRegBankID) << 24) | // SGPR_1024_with_sub10_sub11_in_CCR_SGPR_64_and_SGPR_1024_with_sub28_sub29_in_Gfx_CCR_SGPR_64RegClassID |
| 1524 | (uint32_t(AMDGPU::SGPRRegBankID) << 28), // SGPR_1024_with_sub12_sub13_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub28_sub29_in_Gfx_CCR_SGPR_64RegClassID |
| 1525 | (uint32_t(AMDGPU::SGPRRegBankID) << 0) | // SGPR_1024_with_sub18_sub19_in_CCR_SGPR_64RegClassID |
| 1526 | (uint32_t(AMDGPU::SGPRRegBankID) << 4) | // SGPR_1024_with_sub2_sub3_in_CCR_SGPR_64_and_SGPR_1024_with_sub20_sub21_in_Gfx_CCR_SGPR_64RegClassID |
| 1527 | (uint32_t(AMDGPU::SGPRRegBankID) << 8) | // SGPR_1024_with_sub4_sub5_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub20_sub21_in_Gfx_CCR_SGPR_64RegClassID |
| 1528 | (uint32_t(AMDGPU::SGPRRegBankID) << 12) | // SGPR_1024_with_sub6_sub7_in_CCR_SGPR_64_and_SGPR_1024_with_sub24_sub25_in_Gfx_CCR_SGPR_64RegClassID |
| 1529 | (uint32_t(AMDGPU::SGPRRegBankID) << 16) | // SGPR_1024_with_sub8_sub9_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub24_sub25_in_Gfx_CCR_SGPR_64RegClassID |
| 1530 | (uint32_t(AMDGPU::SGPRRegBankID) << 20) | // SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_1024_with_sub12_sub13_in_Gfx_CCR_SGPR_64RegClassID |
| 1531 | (uint32_t(AMDGPU::SGPRRegBankID) << 24) | // SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64_with_sub12_sub13_sub14_sub15_sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23_sub24_sub25_sub26_sub27_in_SGPR_512_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_512_with_sub12_sub13_in_Gfx_CCR_SGPR_64RegClassID |
| 1532 | (uint32_t(AMDGPU::SGPRRegBankID) << 28), // SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64_with_sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23_sub24_sub25_sub26_sub27_sub28_sub29_sub30_sub31_in_SGPR_512_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_512_with_sub12_sub13_in_Gfx_CCR_SGPR_64RegClassID |
| 1533 | (uint32_t(AMDGPU::SGPRRegBankID) << 0) | // SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64_with_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_sub16_sub17_sub18_sub19_in_SGPR_512_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_512_with_sub12_sub13_in_Gfx_CCR_SGPR_64RegClassID |
| 1534 | (uint32_t(AMDGPU::SGPRRegBankID) << 4) | // SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64_with_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23_in_SGPR_512_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_512_with_sub12_sub13_in_Gfx_CCR_SGPR_64RegClassID |
| 1535 | (uint32_t(AMDGPU::SGPRRegBankID) << 8) | // SGPR_1024_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub20_sub21_in_Gfx_CCR_SGPR_64RegClassID |
| 1536 | (uint32_t(AMDGPU::SGPRRegBankID) << 12) | // SGPR_1024_with_sub22_sub23_in_CCR_SGPR_64RegClassID |
| 1537 | (uint32_t(AMDGPU::SGPRRegBankID) << 16) | // SGPR_1024_with_sub4_sub5_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub24_sub25_in_Gfx_CCR_SGPR_64RegClassID |
| 1538 | (uint32_t(AMDGPU::SGPRRegBankID) << 20) | // SGPR_1024_with_sub8_sub9_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub28_sub29_in_Gfx_CCR_SGPR_64RegClassID |
| 1539 | (uint32_t(AMDGPU::SGPRRegBankID) << 24) | // SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_1024_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClassID |
| 1540 | (uint32_t(AMDGPU::SGPRRegBankID) << 28), // SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64_with_sub12_lo16_sub12_hi16_sub13_lo16_sub13_hi16_sub14_lo16_sub14_hi16_sub15_lo16_sub15_hi16_sub16_lo16_sub16_hi16_sub17_lo16_sub17_hi16_sub18_lo16_sub18_hi16_sub19_lo16_sub19_hi16_sub20_lo16_sub20_hi16_sub21_lo16_sub21_hi16_sub22_lo16_sub22_hi16_sub23_lo16_sub23_hi16_in_SGPR_384_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_384_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClassID |
| 1541 | (uint32_t(AMDGPU::SGPRRegBankID) << 0) | // SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64_with_sub16_lo16_sub16_hi16_sub17_lo16_sub17_hi16_sub18_lo16_sub18_hi16_sub19_lo16_sub19_hi16_sub20_lo16_sub20_hi16_sub21_lo16_sub21_hi16_sub22_lo16_sub22_hi16_sub23_lo16_sub23_hi16_sub24_lo16_sub24_hi16_sub25_lo16_sub25_hi16_sub26_lo16_sub26_hi16_sub27_lo16_sub27_hi16_in_SGPR_384_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_384_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClassID |
| 1542 | (uint32_t(AMDGPU::SGPRRegBankID) << 4) | // SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64_with_sub20_lo16_sub20_hi16_sub21_lo16_sub21_hi16_sub22_lo16_sub22_hi16_sub23_lo16_sub23_hi16_sub24_lo16_sub24_hi16_sub25_lo16_sub25_hi16_sub26_lo16_sub26_hi16_sub27_lo16_sub27_hi16_sub28_lo16_sub28_hi16_sub29_lo16_sub29_hi16_sub30_lo16_sub30_hi16_sub31_lo16_sub31_hi16_in_SGPR_384_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_384_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClassID |
| 1543 | (uint32_t(AMDGPU::SGPRRegBankID) << 8) | // SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64_with_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16_sub12_lo16_sub12_hi16_sub13_lo16_sub13_hi16_sub14_lo16_sub14_hi16_sub15_lo16_sub15_hi16_in_SGPR_384_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_384_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClassID |
| 1544 | (uint32_t(AMDGPU::SGPRRegBankID) << 12) | // SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64_with_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16_sub12_lo16_sub12_hi16_sub13_lo16_sub13_hi16_sub14_lo16_sub14_hi16_sub15_lo16_sub15_hi16_sub16_lo16_sub16_hi16_sub17_lo16_sub17_hi16_sub18_lo16_sub18_hi16_sub19_lo16_sub19_hi16_in_SGPR_384_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_384_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClassID |
| 1545 | (uint32_t(AMDGPU::SGPRRegBankID) << 16) | // SGPR_1024_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub24_sub25_in_Gfx_CCR_SGPR_64RegClassID |
| 1546 | (uint32_t(AMDGPU::SGPRRegBankID) << 20) | // SGPR_1024_with_sub26_sub27_in_CCR_SGPR_64RegClassID |
| 1547 | (uint32_t(AMDGPU::SGPRRegBankID) << 24) // SGPR_1024_with_sub4_sub5_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub28_sub29_in_Gfx_CCR_SGPR_64RegClassID |
| 1548 | }; |
| 1549 | const unsigned RegClassID = RC.getID(); |
| 1550 | if (LLVM_LIKELY(RegClassID < 615)) { |
| 1551 | unsigned RegBankID = (RegClass2RegBank[RegClassID / 8] >> ((RegClassID % 8) * 4)) & 15; |
| 1552 | if (RegBankID != InvalidRegBankID) |
| 1553 | return getRegBank(RegBankID); |
| 1554 | } |
| 1555 | llvm_unreachable(llvm::Twine("Target needs to handle register class ID 0x").concat(llvm::Twine::utohexstr(RegClassID)).str().c_str()); |
| 1556 | } |
| 1557 | } // end namespace llvm |
| 1558 | #endif // GET_TARGET_REGBANK_IMPL |
| 1559 |
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