| 1 | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
|---|---|
| 2 | |* *| |
| 3 | |* Global Instruction Selector for the ARM target *| |
| 4 | |* *| |
| 5 | |* Automatically generated file, do not edit! *| |
| 6 | |* *| |
| 7 | \*===----------------------------------------------------------------------===*/ |
| 8 | |
| 9 | #ifdef GET_GLOBALISEL_PREDICATE_BITSET |
| 10 | const unsigned MAX_SUBTARGET_PREDICATES = 85; |
| 11 | using PredicateBitset = llvm::Bitset<MAX_SUBTARGET_PREDICATES>; |
| 12 | #endif // ifdef GET_GLOBALISEL_PREDICATE_BITSET |
| 13 | |
| 14 | #ifdef GET_GLOBALISEL_TEMPORARIES_DECL |
| 15 | mutable MatcherState State; |
| 16 | typedef ComplexRendererFns(ARMInstructionSelector::*ComplexMatcherMemFn)(MachineOperand &) const; |
| 17 | typedef void(ARMInstructionSelector::*CustomRendererFn)(MachineInstrBuilder &, const MachineInstr &, int) const; |
| 18 | const ExecInfoTy<PredicateBitset, ComplexMatcherMemFn, CustomRendererFn> ExecInfo; |
| 19 | static ARMInstructionSelector::ComplexMatcherMemFn ComplexPredicateFns[]; |
| 20 | static ARMInstructionSelector::CustomRendererFn CustomRenderers[]; |
| 21 | bool testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const override; |
| 22 | bool testImmPredicate_APInt(unsigned PredicateID, const APInt &Imm) const override; |
| 23 | bool testImmPredicate_APFloat(unsigned PredicateID, const APFloat &Imm) const override; |
| 24 | const uint8_t *getMatchTable() const override; |
| 25 | bool testMIPredicate_MI(unsigned PredicateID, const MachineInstr &MI, const MatcherState &State) const override; |
| 26 | bool testMOPredicate_MO(unsigned PredicateID, const MachineOperand &MO, const MatcherState &State) const override; |
| 27 | bool testSimplePredicate(unsigned PredicateID) const override; |
| 28 | bool runCustomAction(unsigned FnID, const MatcherState &State, NewMIVector &OutMIs) const override; |
| 29 | #endif // ifdef GET_GLOBALISEL_TEMPORARIES_DECL |
| 30 | |
| 31 | #ifdef GET_GLOBALISEL_TEMPORARIES_INIT |
| 32 | , State(0), |
| 33 | ExecInfo(TypeObjects, NumTypeObjects, FeatureBitsets, ComplexPredicateFns, CustomRenderers) |
| 34 | #endif // ifdef GET_GLOBALISEL_TEMPORARIES_INIT |
| 35 | |
| 36 | #ifdef GET_GLOBALISEL_IMPL |
| 37 | // LLT Objects. |
| 38 | enum { |
| 39 | GILLT_s16, |
| 40 | GILLT_s32, |
| 41 | GILLT_s64, |
| 42 | GILLT_v2s1, |
| 43 | GILLT_v2s32, |
| 44 | GILLT_v2s64, |
| 45 | GILLT_v4s1, |
| 46 | GILLT_v4s16, |
| 47 | GILLT_v4s32, |
| 48 | GILLT_v4s64, |
| 49 | GILLT_v8s1, |
| 50 | GILLT_v8s8, |
| 51 | GILLT_v8s16, |
| 52 | GILLT_v8s64, |
| 53 | GILLT_v16s1, |
| 54 | GILLT_v16s8, |
| 55 | }; |
| 56 | const static size_t NumTypeObjects = 16; |
| 57 | const static LLT TypeObjects[] = { |
| 58 | LLT::scalar(16), |
| 59 | LLT::scalar(32), |
| 60 | LLT::scalar(64), |
| 61 | LLT::vector(ElementCount::getFixed(2), 1), |
| 62 | LLT::vector(ElementCount::getFixed(2), 32), |
| 63 | LLT::vector(ElementCount::getFixed(2), 64), |
| 64 | LLT::vector(ElementCount::getFixed(4), 1), |
| 65 | LLT::vector(ElementCount::getFixed(4), 16), |
| 66 | LLT::vector(ElementCount::getFixed(4), 32), |
| 67 | LLT::vector(ElementCount::getFixed(4), 64), |
| 68 | LLT::vector(ElementCount::getFixed(8), 1), |
| 69 | LLT::vector(ElementCount::getFixed(8), 8), |
| 70 | LLT::vector(ElementCount::getFixed(8), 16), |
| 71 | LLT::vector(ElementCount::getFixed(8), 64), |
| 72 | LLT::vector(ElementCount::getFixed(16), 1), |
| 73 | LLT::vector(ElementCount::getFixed(16), 8), |
| 74 | }; |
| 75 | |
| 76 | // Bits for subtarget features that participate in instruction matching. |
| 77 | enum SubtargetFeatureBits : uint8_t { |
| 78 | Feature_NoHonorSignDependentRoundingBit = 75, |
| 79 | Feature_HasV4TBit = 6, |
| 80 | Feature_NoV4TBit = 7, |
| 81 | Feature_HasV5TBit = 13, |
| 82 | Feature_NoV5TBit = 65, |
| 83 | Feature_HasV5TEBit = 11, |
| 84 | Feature_HasV6Bit = 0, |
| 85 | Feature_NoV6Bit = 9, |
| 86 | Feature_HasV6MBit = 28, |
| 87 | Feature_HasV8MBaselineBit = 35, |
| 88 | Feature_HasV8_1MMainlineBit = 41, |
| 89 | Feature_HasMVEIntBit = 63, |
| 90 | Feature_HasMVEFloatBit = 64, |
| 91 | Feature_HasCDEBit = 84, |
| 92 | Feature_HasFPRegsBit = 42, |
| 93 | Feature_HasFPRegs16Bit = 43, |
| 94 | Feature_HasFPRegs64Bit = 76, |
| 95 | Feature_HasV6T2Bit = 8, |
| 96 | Feature_HasV6KBit = 18, |
| 97 | Feature_HasV7Bit = 3, |
| 98 | Feature_HasV8Bit = 55, |
| 99 | Feature_PreV8Bit = 19, |
| 100 | Feature_HasV8_1aBit = 78, |
| 101 | Feature_HasV8_3aBit = 79, |
| 102 | Feature_NoVFPBit = 22, |
| 103 | Feature_HasVFP2Bit = 21, |
| 104 | Feature_HasVFP3Bit = 52, |
| 105 | Feature_HasVFP4Bit = 50, |
| 106 | Feature_HasDPVFPBit = 44, |
| 107 | Feature_HasFPARMv8Bit = 47, |
| 108 | Feature_HasNEONBit = 53, |
| 109 | Feature_HasSHA2Bit = 62, |
| 110 | Feature_HasAESBit = 54, |
| 111 | Feature_HasDotProdBit = 56, |
| 112 | Feature_HasCRCBit = 14, |
| 113 | Feature_HasLOBBit = 40, |
| 114 | Feature_HasFP16Bit = 61, |
| 115 | Feature_HasFullFP16Bit = 46, |
| 116 | Feature_HasMatMulInt8Bit = 57, |
| 117 | Feature_HasDivideInThumbBit = 37, |
| 118 | Feature_HasDivideInARMBit = 12, |
| 119 | Feature_HasDSPBit = 36, |
| 120 | Feature_HasDBBit = 15, |
| 121 | Feature_HasV7ClrexBit = 17, |
| 122 | Feature_HasAcquireReleaseBit = 16, |
| 123 | Feature_HasMPBit = 2, |
| 124 | Feature_Has8MSecExtBit = 29, |
| 125 | Feature_HasZCZBit = 58, |
| 126 | Feature_UseNEONForFPBit = 82, |
| 127 | Feature_DontUseNEONForFPBit = 45, |
| 128 | Feature_IsThumbBit = 26, |
| 129 | Feature_IsThumb1OnlyBit = 27, |
| 130 | Feature_IsThumb2Bit = 34, |
| 131 | Feature_IsNotMClassBit = 38, |
| 132 | Feature_IsARMBit = 1, |
| 133 | Feature_IsWindowsBit = 30, |
| 134 | Feature_IsNotWindowsBit = 31, |
| 135 | Feature_IsReadTPTPIDRURWBit = 68, |
| 136 | Feature_IsReadTPTPIDRUROBit = 69, |
| 137 | Feature_IsReadTPTPIDRPRWBit = 70, |
| 138 | Feature_IsReadTPSoftBit = 20, |
| 139 | Feature_UseNaClTrapBit = 4, |
| 140 | Feature_DontUseNaClTrapBit = 5, |
| 141 | Feature_UseMovtBit = 39, |
| 142 | Feature_DontUseMovtBit = 23, |
| 143 | Feature_UseMovtInPicBit = 24, |
| 144 | Feature_DontUseMovtInPicBit = 25, |
| 145 | Feature_UseFPVMLxBit = 49, |
| 146 | Feature_SLSBLRMitigationBit = 67, |
| 147 | Feature_NoSLSBLRMitigationBit = 66, |
| 148 | Feature_UseMulOpsBit = 10, |
| 149 | Feature_UseFusedMACBit = 51, |
| 150 | Feature_HasFastVGETLNi32Bit = 59, |
| 151 | Feature_HasSlowVGETLNi32Bit = 80, |
| 152 | Feature_HasFastVDUP32Bit = 60, |
| 153 | Feature_HasSlowVDUP32Bit = 81, |
| 154 | Feature_UseVMOVSRBit = 48, |
| 155 | Feature_DontUseVMOVSRBit = 83, |
| 156 | Feature_IsLEBit = 74, |
| 157 | Feature_IsBEBit = 77, |
| 158 | Feature_GenExecuteOnlyBit = 33, |
| 159 | Feature_DontGenExecuteOnlyBit = 32, |
| 160 | Feature_GenT1ExecuteOnlyBit = 73, |
| 161 | Feature_SignRetAddrBit = 72, |
| 162 | Feature_NoSignRetAddrBit = 71, |
| 163 | }; |
| 164 | |
| 165 | PredicateBitset ARMInstructionSelector:: |
| 166 | computeAvailableModuleFeatures(const ARMSubtarget *Subtarget) const { |
| 167 | PredicateBitset Features{}; |
| 168 | if (!TM.Options.HonorSignDependentRoundingFPMath()) |
| 169 | Features.set(Feature_NoHonorSignDependentRoundingBit); |
| 170 | if (Subtarget->hasV4TOps()) |
| 171 | Features.set(Feature_HasV4TBit); |
| 172 | if (!Subtarget->hasV4TOps()) |
| 173 | Features.set(Feature_NoV4TBit); |
| 174 | if (Subtarget->hasV5TOps()) |
| 175 | Features.set(Feature_HasV5TBit); |
| 176 | if (!Subtarget->hasV5TOps()) |
| 177 | Features.set(Feature_NoV5TBit); |
| 178 | if (Subtarget->hasV5TEOps()) |
| 179 | Features.set(Feature_HasV5TEBit); |
| 180 | if (Subtarget->hasV6Ops()) |
| 181 | Features.set(Feature_HasV6Bit); |
| 182 | if (!Subtarget->hasV6Ops()) |
| 183 | Features.set(Feature_NoV6Bit); |
| 184 | if (Subtarget->hasV6MOps()) |
| 185 | Features.set(Feature_HasV6MBit); |
| 186 | if (Subtarget->hasV8MBaselineOps()) |
| 187 | Features.set(Feature_HasV8MBaselineBit); |
| 188 | if (Subtarget->hasV8_1MMainlineOps()) |
| 189 | Features.set(Feature_HasV8_1MMainlineBit); |
| 190 | if (Subtarget->hasMVEIntegerOps()) |
| 191 | Features.set(Feature_HasMVEIntBit); |
| 192 | if (Subtarget->hasMVEFloatOps()) |
| 193 | Features.set(Feature_HasMVEFloatBit); |
| 194 | if (Subtarget->hasCDEOps()) |
| 195 | Features.set(Feature_HasCDEBit); |
| 196 | if (Subtarget->hasFPRegs()) |
| 197 | Features.set(Feature_HasFPRegsBit); |
| 198 | if (Subtarget->hasFPRegs16()) |
| 199 | Features.set(Feature_HasFPRegs16Bit); |
| 200 | if (Subtarget->hasFPRegs64()) |
| 201 | Features.set(Feature_HasFPRegs64Bit); |
| 202 | if (Subtarget->hasV6T2Ops()) |
| 203 | Features.set(Feature_HasV6T2Bit); |
| 204 | if (Subtarget->hasV6KOps()) |
| 205 | Features.set(Feature_HasV6KBit); |
| 206 | if (Subtarget->hasV7Ops()) |
| 207 | Features.set(Feature_HasV7Bit); |
| 208 | if (Subtarget->hasV8Ops()) |
| 209 | Features.set(Feature_HasV8Bit); |
| 210 | if (!Subtarget->hasV8Ops()) |
| 211 | Features.set(Feature_PreV8Bit); |
| 212 | if (Subtarget->hasV8_1aOps()) |
| 213 | Features.set(Feature_HasV8_1aBit); |
| 214 | if (Subtarget->hasV8_3aOps()) |
| 215 | Features.set(Feature_HasV8_3aBit); |
| 216 | if (!Subtarget->hasVFP2Base()) |
| 217 | Features.set(Feature_NoVFPBit); |
| 218 | if (Subtarget->hasVFP2Base()) |
| 219 | Features.set(Feature_HasVFP2Bit); |
| 220 | if (Subtarget->hasVFP3Base()) |
| 221 | Features.set(Feature_HasVFP3Bit); |
| 222 | if (Subtarget->hasVFP4Base()) |
| 223 | Features.set(Feature_HasVFP4Bit); |
| 224 | if (Subtarget->hasFP64()) |
| 225 | Features.set(Feature_HasDPVFPBit); |
| 226 | if (Subtarget->hasFPARMv8Base()) |
| 227 | Features.set(Feature_HasFPARMv8Bit); |
| 228 | if (Subtarget->hasNEON()) |
| 229 | Features.set(Feature_HasNEONBit); |
| 230 | if (Subtarget->hasSHA2()) |
| 231 | Features.set(Feature_HasSHA2Bit); |
| 232 | if (Subtarget->hasAES()) |
| 233 | Features.set(Feature_HasAESBit); |
| 234 | if (Subtarget->hasDotProd()) |
| 235 | Features.set(Feature_HasDotProdBit); |
| 236 | if (Subtarget->hasCRC()) |
| 237 | Features.set(Feature_HasCRCBit); |
| 238 | if (Subtarget->hasLOB()) |
| 239 | Features.set(Feature_HasLOBBit); |
| 240 | if (Subtarget->hasFP16()) |
| 241 | Features.set(Feature_HasFP16Bit); |
| 242 | if (Subtarget->hasFullFP16()) |
| 243 | Features.set(Feature_HasFullFP16Bit); |
| 244 | if (Subtarget->hasMatMulInt8()) |
| 245 | Features.set(Feature_HasMatMulInt8Bit); |
| 246 | if (Subtarget->hasDivideInThumbMode()) |
| 247 | Features.set(Feature_HasDivideInThumbBit); |
| 248 | if (Subtarget->hasDivideInARMMode()) |
| 249 | Features.set(Feature_HasDivideInARMBit); |
| 250 | if (Subtarget->hasDSP()) |
| 251 | Features.set(Feature_HasDSPBit); |
| 252 | if (Subtarget->hasDataBarrier()) |
| 253 | Features.set(Feature_HasDBBit); |
| 254 | if (Subtarget->hasV7Clrex()) |
| 255 | Features.set(Feature_HasV7ClrexBit); |
| 256 | if (Subtarget->hasAcquireRelease()) |
| 257 | Features.set(Feature_HasAcquireReleaseBit); |
| 258 | if (Subtarget->hasMPExtension()) |
| 259 | Features.set(Feature_HasMPBit); |
| 260 | if (Subtarget->has8MSecExt()) |
| 261 | Features.set(Feature_Has8MSecExtBit); |
| 262 | if (Subtarget->hasZeroCycleZeroing()) |
| 263 | Features.set(Feature_HasZCZBit); |
| 264 | if (Subtarget->useNEONForSinglePrecisionFP()) |
| 265 | Features.set(Feature_UseNEONForFPBit); |
| 266 | if (!Subtarget->useNEONForSinglePrecisionFP()) |
| 267 | Features.set(Feature_DontUseNEONForFPBit); |
| 268 | if (Subtarget->isThumb()) |
| 269 | Features.set(Feature_IsThumbBit); |
| 270 | if (Subtarget->isThumb1Only()) |
| 271 | Features.set(Feature_IsThumb1OnlyBit); |
| 272 | if (Subtarget->isThumb2()) |
| 273 | Features.set(Feature_IsThumb2Bit); |
| 274 | if (!Subtarget->isMClass()) |
| 275 | Features.set(Feature_IsNotMClassBit); |
| 276 | if (!Subtarget->isThumb()) |
| 277 | Features.set(Feature_IsARMBit); |
| 278 | if (Subtarget->isTargetWindows()) |
| 279 | Features.set(Feature_IsWindowsBit); |
| 280 | if (!Subtarget->isTargetWindows()) |
| 281 | Features.set(Feature_IsNotWindowsBit); |
| 282 | if (Subtarget->isReadTPTPIDRURW()) |
| 283 | Features.set(Feature_IsReadTPTPIDRURWBit); |
| 284 | if (Subtarget->isReadTPTPIDRURO()) |
| 285 | Features.set(Feature_IsReadTPTPIDRUROBit); |
| 286 | if (Subtarget->isReadTPTPIDRPRW()) |
| 287 | Features.set(Feature_IsReadTPTPIDRPRWBit); |
| 288 | if (Subtarget->isReadTPSoft()) |
| 289 | Features.set(Feature_IsReadTPSoftBit); |
| 290 | if (Subtarget->useNaClTrap()) |
| 291 | Features.set(Feature_UseNaClTrapBit); |
| 292 | if (!Subtarget->useNaClTrap()) |
| 293 | Features.set(Feature_DontUseNaClTrapBit); |
| 294 | if (Subtarget->useMulOps()) |
| 295 | Features.set(Feature_UseMulOpsBit); |
| 296 | if (TM.Options.AllowFPOpFusion == FPOpFusion::Fast && Subtarget->useFPVFMx()) |
| 297 | Features.set(Feature_UseFusedMACBit); |
| 298 | if (!Subtarget->hasSlowVGETLNi32()) |
| 299 | Features.set(Feature_HasFastVGETLNi32Bit); |
| 300 | if (Subtarget->hasSlowVGETLNi32()) |
| 301 | Features.set(Feature_HasSlowVGETLNi32Bit); |
| 302 | if (!Subtarget->hasSlowVDUP32()) |
| 303 | Features.set(Feature_HasFastVDUP32Bit); |
| 304 | if (Subtarget->hasSlowVDUP32()) |
| 305 | Features.set(Feature_HasSlowVDUP32Bit); |
| 306 | if (Subtarget->preferVMOVSR() ||!Subtarget->useNEONForSinglePrecisionFP()) |
| 307 | Features.set(Feature_UseVMOVSRBit); |
| 308 | if (!Subtarget->preferVMOVSR() &&Subtarget->useNEONForSinglePrecisionFP()) |
| 309 | Features.set(Feature_DontUseVMOVSRBit); |
| 310 | if (Subtarget->genExecuteOnly()) |
| 311 | Features.set(Feature_GenExecuteOnlyBit); |
| 312 | if (!Subtarget->genExecuteOnly()) |
| 313 | Features.set(Feature_DontGenExecuteOnlyBit); |
| 314 | if (Subtarget->genExecuteOnly() && Subtarget->isThumb1Only() && !Subtarget->hasV8MBaselineOps()) |
| 315 | Features.set(Feature_GenT1ExecuteOnlyBit); |
| 316 | return Features; |
| 317 | } |
| 318 | |
| 319 | void ARMInstructionSelector::setupGeneratedPerFunctionState(MachineFunction &MF) { |
| 320 | AvailableFunctionFeatures = computeAvailableFunctionFeatures((const ARMSubtarget *)&MF.getSubtarget(), &MF); |
| 321 | } |
| 322 | PredicateBitset ARMInstructionSelector:: |
| 323 | computeAvailableFunctionFeatures(const ARMSubtarget *Subtarget, const MachineFunction *MF) const { |
| 324 | PredicateBitset Features{}; |
| 325 | if (Subtarget->useMovt()) |
| 326 | Features.set(Feature_UseMovtBit); |
| 327 | if (!Subtarget->useMovt()) |
| 328 | Features.set(Feature_DontUseMovtBit); |
| 329 | if (Subtarget->useMovt() && Subtarget->allowPositionIndependentMovt()) |
| 330 | Features.set(Feature_UseMovtInPicBit); |
| 331 | if (!Subtarget->useMovt() || !Subtarget->allowPositionIndependentMovt()) |
| 332 | Features.set(Feature_DontUseMovtInPicBit); |
| 333 | if (((Subtarget->useFPVMLx() && TM.Options.AllowFPOpFusion != FPOpFusion::Fast) ||Subtarget->hasMinSize())) |
| 334 | Features.set(Feature_UseFPVMLxBit); |
| 335 | if ( MF->getSubtarget<ARMSubtarget>().hardenSlsBlr() ) |
| 336 | Features.set(Feature_SLSBLRMitigationBit); |
| 337 | if ( !MF->getSubtarget<ARMSubtarget>().hardenSlsBlr() ) |
| 338 | Features.set(Feature_NoSLSBLRMitigationBit); |
| 339 | if (MF->getDataLayout().isLittleEndian()) |
| 340 | Features.set(Feature_IsLEBit); |
| 341 | if (MF->getDataLayout().isBigEndian()) |
| 342 | Features.set(Feature_IsBEBit); |
| 343 | if ( MF->getInfo<ARMFunctionInfo>()->shouldSignReturnAddress(true) ) |
| 344 | Features.set(Feature_SignRetAddrBit); |
| 345 | if ( !MF->getInfo<ARMFunctionInfo>()->shouldSignReturnAddress(true) ) |
| 346 | Features.set(Feature_NoSignRetAddrBit); |
| 347 | return Features; |
| 348 | } |
| 349 | |
| 350 | // Feature bitsets. |
| 351 | enum { |
| 352 | GIFBS_Invalid, |
| 353 | GIFBS_HasDotProd, |
| 354 | GIFBS_HasFP16, |
| 355 | GIFBS_HasFPARMv8, |
| 356 | GIFBS_HasFPRegs, |
| 357 | GIFBS_HasFullFP16, |
| 358 | GIFBS_HasMVEFloat, |
| 359 | GIFBS_HasMVEInt, |
| 360 | GIFBS_HasMatMulInt8, |
| 361 | GIFBS_HasNEON, |
| 362 | GIFBS_HasVFP2, |
| 363 | GIFBS_HasVFP3, |
| 364 | GIFBS_HasVFP4, |
| 365 | GIFBS_IsARM, |
| 366 | GIFBS_IsThumb, |
| 367 | GIFBS_IsThumb2, |
| 368 | GIFBS_NoHonorSignDependentRounding, |
| 369 | GIFBS_DontUseNEONForFP_HasVFP2, |
| 370 | GIFBS_DontUseNaClTrap_IsARM, |
| 371 | GIFBS_DontUseVMOVSR_HasNEON, |
| 372 | GIFBS_Has8MSecExt_IsThumb, |
| 373 | GIFBS_HasAES_HasV8, |
| 374 | GIFBS_HasCRC_IsARM, |
| 375 | GIFBS_HasCRC_IsThumb2, |
| 376 | GIFBS_HasDB_IsARM, |
| 377 | GIFBS_HasDB_IsThumb, |
| 378 | GIFBS_HasDPVFP_HasFPARMv8, |
| 379 | GIFBS_HasDPVFP_HasVFP2, |
| 380 | GIFBS_HasDPVFP_HasVFP3, |
| 381 | GIFBS_HasDPVFP_HasVFP4, |
| 382 | GIFBS_HasDPVFP_NoHonorSignDependentRounding, |
| 383 | GIFBS_HasDSP_IsThumb2, |
| 384 | GIFBS_HasDivideInARM_IsARM, |
| 385 | GIFBS_HasFP16_HasNEON, |
| 386 | GIFBS_HasFPARMv8_HasNEON, |
| 387 | GIFBS_HasFPRegs_HasFastVGETLNi32, |
| 388 | GIFBS_HasFPRegs_UseVMOVSR, |
| 389 | GIFBS_HasFullFP16_HasNEON, |
| 390 | GIFBS_HasMVEInt_HasV8_1MMainline, |
| 391 | GIFBS_HasMVEInt_IsBE, |
| 392 | GIFBS_HasMVEInt_IsLE, |
| 393 | GIFBS_HasNEON_HasV8, |
| 394 | GIFBS_HasNEON_HasV8_1a, |
| 395 | GIFBS_HasNEON_HasV8_3a, |
| 396 | GIFBS_HasNEON_HasVFP4, |
| 397 | GIFBS_HasNEON_IsBE, |
| 398 | GIFBS_HasNEON_IsLE, |
| 399 | GIFBS_HasNEON_UseNEONForFP, |
| 400 | GIFBS_HasSHA2_HasV8, |
| 401 | GIFBS_HasV5T_IsARM, |
| 402 | GIFBS_HasV5T_IsThumb, |
| 403 | GIFBS_HasV5TE_IsARM, |
| 404 | GIFBS_HasV6_IsARM, |
| 405 | GIFBS_HasV6K_IsARM, |
| 406 | GIFBS_HasV6M_IsThumb, |
| 407 | GIFBS_HasV6T2_IsARM, |
| 408 | GIFBS_HasV7_IsARM, |
| 409 | GIFBS_HasV7Clrex_IsThumb, |
| 410 | GIFBS_HasV8MBaseline_IsThumb, |
| 411 | GIFBS_IsARM_NoV5T, |
| 412 | GIFBS_IsARM_NoV6, |
| 413 | GIFBS_IsARM_PreV8, |
| 414 | GIFBS_IsARM_UseNaClTrap, |
| 415 | GIFBS_IsThumb_IsThumb1Only, |
| 416 | GIFBS_IsThumb_IsWindows, |
| 417 | GIFBS_IsThumb_NoV5T, |
| 418 | GIFBS_IsThumb_UseMovt, |
| 419 | GIFBS_IsThumb2_PreV8, |
| 420 | GIFBS_IsThumb2_UseMulOps, |
| 421 | GIFBS_DontUseMovt_GenExecuteOnly_IsThumb1Only, |
| 422 | GIFBS_HasDSP_IsThumb2_UseMulOps, |
| 423 | GIFBS_HasDivideInThumb_HasV8MBaseline_IsThumb, |
| 424 | GIFBS_HasFPARMv8_HasFullFP16_HasNEON, |
| 425 | GIFBS_HasFullFP16_HasNEON_HasV8, |
| 426 | GIFBS_HasFullFP16_HasNEON_HasV8_3a, |
| 427 | GIFBS_HasFullFP16_HasNEON_UseFPVMLx, |
| 428 | GIFBS_HasFullFP16_HasNEON_UseFusedMAC, |
| 429 | GIFBS_HasLOB_HasV8_1MMainline_IsThumb2, |
| 430 | GIFBS_HasNEON_UseFPVMLx_UseNEONForFP, |
| 431 | GIFBS_HasV5TE_IsARM_UseMulOps, |
| 432 | GIFBS_HasV6_IsARM_UseMulOps, |
| 433 | GIFBS_HasV6_IsThumb_IsThumb1Only, |
| 434 | GIFBS_HasV6T2_IsARM_UseMulOps, |
| 435 | GIFBS_HasVFP4_UseFusedMAC_UseNEONForFP, |
| 436 | GIFBS_IsARM_NoV6_UseMulOps, |
| 437 | }; |
| 438 | constexpr static PredicateBitset FeatureBitsets[] { |
| 439 | {}, // GIFBS_Invalid |
| 440 | {Feature_HasDotProdBit, }, |
| 441 | {Feature_HasFP16Bit, }, |
| 442 | {Feature_HasFPARMv8Bit, }, |
| 443 | {Feature_HasFPRegsBit, }, |
| 444 | {Feature_HasFullFP16Bit, }, |
| 445 | {Feature_HasMVEFloatBit, }, |
| 446 | {Feature_HasMVEIntBit, }, |
| 447 | {Feature_HasMatMulInt8Bit, }, |
| 448 | {Feature_HasNEONBit, }, |
| 449 | {Feature_HasVFP2Bit, }, |
| 450 | {Feature_HasVFP3Bit, }, |
| 451 | {Feature_HasVFP4Bit, }, |
| 452 | {Feature_IsARMBit, }, |
| 453 | {Feature_IsThumbBit, }, |
| 454 | {Feature_IsThumb2Bit, }, |
| 455 | {Feature_NoHonorSignDependentRoundingBit, }, |
| 456 | {Feature_DontUseNEONForFPBit, Feature_HasVFP2Bit, }, |
| 457 | {Feature_DontUseNaClTrapBit, Feature_IsARMBit, }, |
| 458 | {Feature_DontUseVMOVSRBit, Feature_HasNEONBit, }, |
| 459 | {Feature_Has8MSecExtBit, Feature_IsThumbBit, }, |
| 460 | {Feature_HasAESBit, Feature_HasV8Bit, }, |
| 461 | {Feature_HasCRCBit, Feature_IsARMBit, }, |
| 462 | {Feature_HasCRCBit, Feature_IsThumb2Bit, }, |
| 463 | {Feature_HasDBBit, Feature_IsARMBit, }, |
| 464 | {Feature_HasDBBit, Feature_IsThumbBit, }, |
| 465 | {Feature_HasDPVFPBit, Feature_HasFPARMv8Bit, }, |
| 466 | {Feature_HasDPVFPBit, Feature_HasVFP2Bit, }, |
| 467 | {Feature_HasDPVFPBit, Feature_HasVFP3Bit, }, |
| 468 | {Feature_HasDPVFPBit, Feature_HasVFP4Bit, }, |
| 469 | {Feature_HasDPVFPBit, Feature_NoHonorSignDependentRoundingBit, }, |
| 470 | {Feature_HasDSPBit, Feature_IsThumb2Bit, }, |
| 471 | {Feature_HasDivideInARMBit, Feature_IsARMBit, }, |
| 472 | {Feature_HasFP16Bit, Feature_HasNEONBit, }, |
| 473 | {Feature_HasFPARMv8Bit, Feature_HasNEONBit, }, |
| 474 | {Feature_HasFPRegsBit, Feature_HasFastVGETLNi32Bit, }, |
| 475 | {Feature_HasFPRegsBit, Feature_UseVMOVSRBit, }, |
| 476 | {Feature_HasFullFP16Bit, Feature_HasNEONBit, }, |
| 477 | {Feature_HasMVEIntBit, Feature_HasV8_1MMainlineBit, }, |
| 478 | {Feature_HasMVEIntBit, Feature_IsBEBit, }, |
| 479 | {Feature_HasMVEIntBit, Feature_IsLEBit, }, |
| 480 | {Feature_HasNEONBit, Feature_HasV8Bit, }, |
| 481 | {Feature_HasNEONBit, Feature_HasV8_1aBit, }, |
| 482 | {Feature_HasNEONBit, Feature_HasV8_3aBit, }, |
| 483 | {Feature_HasNEONBit, Feature_HasVFP4Bit, }, |
| 484 | {Feature_HasNEONBit, Feature_IsBEBit, }, |
| 485 | {Feature_HasNEONBit, Feature_IsLEBit, }, |
| 486 | {Feature_HasNEONBit, Feature_UseNEONForFPBit, }, |
| 487 | {Feature_HasSHA2Bit, Feature_HasV8Bit, }, |
| 488 | {Feature_HasV5TBit, Feature_IsARMBit, }, |
| 489 | {Feature_HasV5TBit, Feature_IsThumbBit, }, |
| 490 | {Feature_HasV5TEBit, Feature_IsARMBit, }, |
| 491 | {Feature_HasV6Bit, Feature_IsARMBit, }, |
| 492 | {Feature_HasV6KBit, Feature_IsARMBit, }, |
| 493 | {Feature_HasV6MBit, Feature_IsThumbBit, }, |
| 494 | {Feature_HasV6T2Bit, Feature_IsARMBit, }, |
| 495 | {Feature_HasV7Bit, Feature_IsARMBit, }, |
| 496 | {Feature_HasV7ClrexBit, Feature_IsThumbBit, }, |
| 497 | {Feature_HasV8MBaselineBit, Feature_IsThumbBit, }, |
| 498 | {Feature_IsARMBit, Feature_NoV5TBit, }, |
| 499 | {Feature_IsARMBit, Feature_NoV6Bit, }, |
| 500 | {Feature_IsARMBit, Feature_PreV8Bit, }, |
| 501 | {Feature_IsARMBit, Feature_UseNaClTrapBit, }, |
| 502 | {Feature_IsThumbBit, Feature_IsThumb1OnlyBit, }, |
| 503 | {Feature_IsThumbBit, Feature_IsWindowsBit, }, |
| 504 | {Feature_IsThumbBit, Feature_NoV5TBit, }, |
| 505 | {Feature_IsThumbBit, Feature_UseMovtBit, }, |
| 506 | {Feature_IsThumb2Bit, Feature_PreV8Bit, }, |
| 507 | {Feature_IsThumb2Bit, Feature_UseMulOpsBit, }, |
| 508 | {Feature_DontUseMovtBit, Feature_GenExecuteOnlyBit, Feature_IsThumb1OnlyBit, }, |
| 509 | {Feature_HasDSPBit, Feature_IsThumb2Bit, Feature_UseMulOpsBit, }, |
| 510 | {Feature_HasDivideInThumbBit, Feature_HasV8MBaselineBit, Feature_IsThumbBit, }, |
| 511 | {Feature_HasFPARMv8Bit, Feature_HasFullFP16Bit, Feature_HasNEONBit, }, |
| 512 | {Feature_HasFullFP16Bit, Feature_HasNEONBit, Feature_HasV8Bit, }, |
| 513 | {Feature_HasFullFP16Bit, Feature_HasNEONBit, Feature_HasV8_3aBit, }, |
| 514 | {Feature_HasFullFP16Bit, Feature_HasNEONBit, Feature_UseFPVMLxBit, }, |
| 515 | {Feature_HasFullFP16Bit, Feature_HasNEONBit, Feature_UseFusedMACBit, }, |
| 516 | {Feature_HasLOBBit, Feature_HasV8_1MMainlineBit, Feature_IsThumb2Bit, }, |
| 517 | {Feature_HasNEONBit, Feature_UseFPVMLxBit, Feature_UseNEONForFPBit, }, |
| 518 | {Feature_HasV5TEBit, Feature_IsARMBit, Feature_UseMulOpsBit, }, |
| 519 | {Feature_HasV6Bit, Feature_IsARMBit, Feature_UseMulOpsBit, }, |
| 520 | {Feature_HasV6Bit, Feature_IsThumbBit, Feature_IsThumb1OnlyBit, }, |
| 521 | {Feature_HasV6T2Bit, Feature_IsARMBit, Feature_UseMulOpsBit, }, |
| 522 | {Feature_HasVFP4Bit, Feature_UseFusedMACBit, Feature_UseNEONForFPBit, }, |
| 523 | {Feature_IsARMBit, Feature_NoV6Bit, Feature_UseMulOpsBit, }, |
| 524 | }; |
| 525 | |
| 526 | // ComplexPattern predicates. |
| 527 | enum { |
| 528 | GICP_Invalid, |
| 529 | }; |
| 530 | // See constructor for table contents |
| 531 | |
| 532 | ARMInstructionSelector::ComplexMatcherMemFn |
| 533 | ARMInstructionSelector::ComplexPredicateFns[] = { |
| 534 | nullptr, // GICP_Invalid |
| 535 | }; |
| 536 | |
| 537 | // PatFrag predicates. |
| 538 | enum { |
| 539 | GICXXPred_MI_Predicate_bf_inv_mask_imm = GICXXPred_Invalid + 1, |
| 540 | GICXXPred_MI_Predicate_vfp_f32imm, |
| 541 | GICXXPred_MI_Predicate_vfp_f64imm, |
| 542 | }; |
| 543 | bool ARMInstructionSelector::testMIPredicate_MI(unsigned PredicateID, const MachineInstr & MI, const MatcherState &State) const { |
| 544 | const MachineFunction &MF = *MI.getParent()->getParent(); |
| 545 | const MachineRegisterInfo &MRI = MF.getRegInfo(); |
| 546 | const auto &Operands = State.RecordedOperands; |
| 547 | (void)Operands; |
| 548 | (void)MRI; |
| 549 | switch (PredicateID) { |
| 550 | case GICXXPred_MI_Predicate_bf_inv_mask_imm: { |
| 551 | |
| 552 | // There's better methods of implementing this check. IntImmLeaf<> would be |
| 553 | // equivalent and have less boilerplate but we need a test for C++ |
| 554 | // predicates and this one causes new rules to be imported into GlobalISel |
| 555 | // without requiring additional features first. |
| 556 | const auto &MO = MI.getOperand(1); |
| 557 | if (!MO.isCImm()) |
| 558 | return false; |
| 559 | return ARM::isBitFieldInvertedMask(MO.getCImm()->getZExtValue()); |
| 560 | |
| 561 | llvm_unreachable("bf_inv_mask_imm should have returned"); |
| 562 | } |
| 563 | case GICXXPred_MI_Predicate_vfp_f32imm: { |
| 564 | |
| 565 | const auto &MO = MI.getOperand(1); |
| 566 | if (!MO.isFPImm()) |
| 567 | return false; |
| 568 | return ARM_AM::getFP32Imm(MO.getFPImm()->getValueAPF()) != -1; |
| 569 | |
| 570 | llvm_unreachable("vfp_f32imm should have returned"); |
| 571 | } |
| 572 | case GICXXPred_MI_Predicate_vfp_f64imm: { |
| 573 | |
| 574 | const auto &MO = MI.getOperand(1); |
| 575 | if (!MO.isFPImm()) |
| 576 | return false; |
| 577 | return ARM_AM::getFP64Imm(MO.getFPImm()->getValueAPF()) != -1; |
| 578 | |
| 579 | llvm_unreachable("vfp_f64imm should have returned"); |
| 580 | } |
| 581 | } |
| 582 | llvm_unreachable("Unknown predicate"); |
| 583 | return false; |
| 584 | } |
| 585 | // PatFrag predicates. |
| 586 | bool ARMInstructionSelector::testMOPredicate_MO(unsigned PredicateID, const MachineOperand & MO, const MatcherState &State) const { |
| 587 | const auto &Operands = State.RecordedOperands; |
| 588 | Register Reg = MO.getReg(); |
| 589 | (void)Operands; |
| 590 | (void)Reg; |
| 591 | llvm_unreachable("Unknown predicate"); |
| 592 | return false; |
| 593 | } |
| 594 | // PatFrag predicates. |
| 595 | enum { |
| 596 | GICXXPred_I64_Predicate_VectorIndex8 = GICXXPred_Invalid + 1, |
| 597 | GICXXPred_I64_Predicate_VectorIndex16, |
| 598 | GICXXPred_I64_Predicate_VectorIndex32, |
| 599 | GICXXPred_I64_Predicate_VectorIndex64, |
| 600 | GICXXPred_I64_Predicate_asr_imm, |
| 601 | GICXXPred_I64_Predicate_imm0_7, |
| 602 | GICXXPred_I64_Predicate_imm0_15, |
| 603 | GICXXPred_I64_Predicate_imm0_31, |
| 604 | GICXXPred_I64_Predicate_imm0_32, |
| 605 | GICXXPred_I64_Predicate_imm0_63, |
| 606 | GICXXPred_I64_Predicate_imm0_239, |
| 607 | GICXXPred_I64_Predicate_imm0_255, |
| 608 | GICXXPred_I64_Predicate_imm0_255_expr, |
| 609 | GICXXPred_I64_Predicate_imm0_4095, |
| 610 | GICXXPred_I64_Predicate_imm0_65535, |
| 611 | GICXXPred_I64_Predicate_imm0_65535_expr, |
| 612 | GICXXPred_I64_Predicate_imm0_65535_neg, |
| 613 | GICXXPred_I64_Predicate_imm1_7, |
| 614 | GICXXPred_I64_Predicate_imm1_15, |
| 615 | GICXXPred_I64_Predicate_imm1_16, |
| 616 | GICXXPred_I64_Predicate_imm1_31, |
| 617 | GICXXPred_I64_Predicate_imm8, |
| 618 | GICXXPred_I64_Predicate_imm8_255, |
| 619 | GICXXPred_I64_Predicate_imm8_or_16, |
| 620 | GICXXPred_I64_Predicate_imm16, |
| 621 | GICXXPred_I64_Predicate_imm16_31, |
| 622 | GICXXPred_I64_Predicate_imm24b, |
| 623 | GICXXPred_I64_Predicate_imm32, |
| 624 | GICXXPred_I64_Predicate_imm256_510, |
| 625 | GICXXPred_I64_Predicate_imm_3b, |
| 626 | GICXXPred_I64_Predicate_imm_4b, |
| 627 | GICXXPred_I64_Predicate_imm_6b, |
| 628 | GICXXPred_I64_Predicate_imm_7b, |
| 629 | GICXXPred_I64_Predicate_imm_9b, |
| 630 | GICXXPred_I64_Predicate_imm_11b, |
| 631 | GICXXPred_I64_Predicate_imm_12b, |
| 632 | GICXXPred_I64_Predicate_imm_13b, |
| 633 | GICXXPred_I64_Predicate_imm_even, |
| 634 | GICXXPred_I64_Predicate_imm_odd, |
| 635 | GICXXPred_I64_Predicate_imm_sr, |
| 636 | GICXXPred_I64_Predicate_long_shift, |
| 637 | GICXXPred_I64_Predicate_mod_imm, |
| 638 | GICXXPred_I64_Predicate_mod_imm_not, |
| 639 | GICXXPred_I64_Predicate_pkh_asr_amt, |
| 640 | GICXXPred_I64_Predicate_pkh_lsl_amt, |
| 641 | GICXXPred_I64_Predicate_shr_imm8, |
| 642 | GICXXPred_I64_Predicate_shr_imm16, |
| 643 | GICXXPred_I64_Predicate_shr_imm32, |
| 644 | GICXXPred_I64_Predicate_shr_imm64, |
| 645 | GICXXPred_I64_Predicate_t2_so_imm, |
| 646 | GICXXPred_I64_Predicate_t2_so_imm_neg, |
| 647 | }; |
| 648 | bool ARMInstructionSelector::testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const { |
| 649 | switch (PredicateID) { |
| 650 | case GICXXPred_I64_Predicate_VectorIndex8: { |
| 651 | |
| 652 | return ((uint64_t)Imm) < 8; |
| 653 | |
| 654 | } |
| 655 | case GICXXPred_I64_Predicate_VectorIndex16: { |
| 656 | |
| 657 | return ((uint64_t)Imm) < 4; |
| 658 | |
| 659 | } |
| 660 | case GICXXPred_I64_Predicate_VectorIndex32: { |
| 661 | |
| 662 | return ((uint64_t)Imm) < 2; |
| 663 | |
| 664 | } |
| 665 | case GICXXPred_I64_Predicate_VectorIndex64: { |
| 666 | |
| 667 | return ((uint64_t)Imm) < 1; |
| 668 | |
| 669 | } |
| 670 | case GICXXPred_I64_Predicate_asr_imm: { |
| 671 | return Imm > 0 && Imm <= 32; |
| 672 | } |
| 673 | case GICXXPred_I64_Predicate_imm0_7: { |
| 674 | |
| 675 | return Imm >= 0 && Imm < 8; |
| 676 | |
| 677 | } |
| 678 | case GICXXPred_I64_Predicate_imm0_15: { |
| 679 | |
| 680 | return Imm >= 0 && Imm < 16; |
| 681 | |
| 682 | } |
| 683 | case GICXXPred_I64_Predicate_imm0_31: { |
| 684 | |
| 685 | return Imm >= 0 && Imm < 32; |
| 686 | |
| 687 | } |
| 688 | case GICXXPred_I64_Predicate_imm0_32: { |
| 689 | |
| 690 | return Imm >= 0 && Imm < 33; |
| 691 | |
| 692 | } |
| 693 | case GICXXPred_I64_Predicate_imm0_63: { |
| 694 | |
| 695 | return Imm >= 0 && Imm < 64; |
| 696 | |
| 697 | } |
| 698 | case GICXXPred_I64_Predicate_imm0_239: { |
| 699 | return Imm >= 0 && Imm < 240; |
| 700 | } |
| 701 | case GICXXPred_I64_Predicate_imm0_255: { |
| 702 | return Imm >= 0 && Imm < 256; |
| 703 | } |
| 704 | case GICXXPred_I64_Predicate_imm0_255_expr: { |
| 705 | return Imm >= 0 && Imm < 256; |
| 706 | } |
| 707 | case GICXXPred_I64_Predicate_imm0_4095: { |
| 708 | |
| 709 | return Imm >= 0 && Imm < 4096; |
| 710 | |
| 711 | } |
| 712 | case GICXXPred_I64_Predicate_imm0_65535: { |
| 713 | |
| 714 | return Imm >= 0 && Imm < 65536; |
| 715 | |
| 716 | } |
| 717 | case GICXXPred_I64_Predicate_imm0_65535_expr: { |
| 718 | |
| 719 | return Imm >= 0 && Imm < 65536; |
| 720 | |
| 721 | } |
| 722 | case GICXXPred_I64_Predicate_imm0_65535_neg: { |
| 723 | |
| 724 | return -Imm >= 0 && -Imm < 65536; |
| 725 | |
| 726 | } |
| 727 | case GICXXPred_I64_Predicate_imm1_7: { |
| 728 | return Imm > 0 && Imm < 8; |
| 729 | } |
| 730 | case GICXXPred_I64_Predicate_imm1_15: { |
| 731 | return Imm > 0 && Imm < 16; |
| 732 | } |
| 733 | case GICXXPred_I64_Predicate_imm1_16: { |
| 734 | |
| 735 | return Imm > 0 && Imm <= 16; |
| 736 | |
| 737 | } |
| 738 | case GICXXPred_I64_Predicate_imm1_31: { |
| 739 | return Imm > 0 && Imm < 32; |
| 740 | } |
| 741 | case GICXXPred_I64_Predicate_imm8: { |
| 742 | return Imm == 8; |
| 743 | } |
| 744 | case GICXXPred_I64_Predicate_imm8_255: { |
| 745 | |
| 746 | return Imm >= 8 && Imm < 256; |
| 747 | |
| 748 | } |
| 749 | case GICXXPred_I64_Predicate_imm8_or_16: { |
| 750 | return Imm == 8 || Imm == 16; |
| 751 | } |
| 752 | case GICXXPred_I64_Predicate_imm16: { |
| 753 | return Imm == 16; |
| 754 | } |
| 755 | case GICXXPred_I64_Predicate_imm16_31: { |
| 756 | |
| 757 | return (int32_t)Imm >= 16 && (int32_t)Imm < 32; |
| 758 | |
| 759 | } |
| 760 | case GICXXPred_I64_Predicate_imm24b: { |
| 761 | |
| 762 | return Imm >= 0 && Imm <= 0xffffff; |
| 763 | |
| 764 | } |
| 765 | case GICXXPred_I64_Predicate_imm32: { |
| 766 | return Imm == 32; |
| 767 | } |
| 768 | case GICXXPred_I64_Predicate_imm256_510: { |
| 769 | |
| 770 | return Imm >= 256 && Imm < 511; |
| 771 | |
| 772 | } |
| 773 | case GICXXPred_I64_Predicate_imm_3b: { |
| 774 | { return Imm >= 0 && Imm < (1 << 3); } |
| 775 | llvm_unreachable("imm_3b should have returned"); |
| 776 | } |
| 777 | case GICXXPred_I64_Predicate_imm_4b: { |
| 778 | { return Imm >= 0 && Imm < (1 << 4); } |
| 779 | llvm_unreachable("imm_4b should have returned"); |
| 780 | } |
| 781 | case GICXXPred_I64_Predicate_imm_6b: { |
| 782 | { return Imm >= 0 && Imm < (1 << 6); } |
| 783 | llvm_unreachable("imm_6b should have returned"); |
| 784 | } |
| 785 | case GICXXPred_I64_Predicate_imm_7b: { |
| 786 | { return Imm >= 0 && Imm < (1 << 7); } |
| 787 | llvm_unreachable("imm_7b should have returned"); |
| 788 | } |
| 789 | case GICXXPred_I64_Predicate_imm_9b: { |
| 790 | { return Imm >= 0 && Imm < (1 << 9); } |
| 791 | llvm_unreachable("imm_9b should have returned"); |
| 792 | } |
| 793 | case GICXXPred_I64_Predicate_imm_11b: { |
| 794 | { return Imm >= 0 && Imm < (1 << 11); } |
| 795 | llvm_unreachable("imm_11b should have returned"); |
| 796 | } |
| 797 | case GICXXPred_I64_Predicate_imm_12b: { |
| 798 | { return Imm >= 0 && Imm < (1 << 12); } |
| 799 | llvm_unreachable("imm_12b should have returned"); |
| 800 | } |
| 801 | case GICXXPred_I64_Predicate_imm_13b: { |
| 802 | { return Imm >= 0 && Imm < (1 << 13); } |
| 803 | llvm_unreachable("imm_13b should have returned"); |
| 804 | } |
| 805 | case GICXXPred_I64_Predicate_imm_even: { |
| 806 | return (Imm & 1) == 0; |
| 807 | } |
| 808 | case GICXXPred_I64_Predicate_imm_odd: { |
| 809 | return (Imm & 1) == 1; |
| 810 | } |
| 811 | case GICXXPred_I64_Predicate_imm_sr: { |
| 812 | |
| 813 | return Imm > 0 && Imm <= 32; |
| 814 | |
| 815 | } |
| 816 | case GICXXPred_I64_Predicate_long_shift: { |
| 817 | return Imm > 0 && Imm <= 32; |
| 818 | } |
| 819 | case GICXXPred_I64_Predicate_mod_imm: { |
| 820 | |
| 821 | return ARM_AM::getSOImmVal(Imm) != -1; |
| 822 | |
| 823 | } |
| 824 | case GICXXPred_I64_Predicate_mod_imm_not: { |
| 825 | |
| 826 | return ARM_AM::getSOImmVal(~(uint32_t)Imm) != -1; |
| 827 | |
| 828 | } |
| 829 | case GICXXPred_I64_Predicate_pkh_asr_amt: { |
| 830 | return Imm > 0 && Imm <= 32; |
| 831 | } |
| 832 | case GICXXPred_I64_Predicate_pkh_lsl_amt: { |
| 833 | return Imm >= 0 && Imm < 32; |
| 834 | } |
| 835 | case GICXXPred_I64_Predicate_shr_imm8: { |
| 836 | return Imm > 0 && Imm <= 8; |
| 837 | } |
| 838 | case GICXXPred_I64_Predicate_shr_imm16: { |
| 839 | return Imm > 0 && Imm <= 16; |
| 840 | } |
| 841 | case GICXXPred_I64_Predicate_shr_imm32: { |
| 842 | return Imm > 0 && Imm <= 32; |
| 843 | } |
| 844 | case GICXXPred_I64_Predicate_shr_imm64: { |
| 845 | return Imm > 0 && Imm <= 64; |
| 846 | } |
| 847 | case GICXXPred_I64_Predicate_t2_so_imm: { |
| 848 | |
| 849 | return ARM_AM::getT2SOImmVal(Imm) != -1; |
| 850 | |
| 851 | } |
| 852 | case GICXXPred_I64_Predicate_t2_so_imm_neg: { |
| 853 | |
| 854 | return Imm && ARM_AM::getT2SOImmVal(-(uint32_t)Imm) != -1; |
| 855 | |
| 856 | } |
| 857 | } |
| 858 | llvm_unreachable("Unknown predicate"); |
| 859 | return false; |
| 860 | } |
| 861 | // PatFrag predicates. |
| 862 | bool ARMInstructionSelector::testImmPredicate_APFloat(unsigned PredicateID, const APFloat & Imm) const { |
| 863 | llvm_unreachable("Unknown predicate"); |
| 864 | return false; |
| 865 | } |
| 866 | // PatFrag predicates. |
| 867 | enum { |
| 868 | GICXXPred_APInt_Predicate_arm_i32imm = GICXXPred_Invalid + 1, |
| 869 | }; |
| 870 | bool ARMInstructionSelector::testImmPredicate_APInt(unsigned PredicateID, const APInt & Imm) const { |
| 871 | switch (PredicateID) { |
| 872 | case GICXXPred_APInt_Predicate_arm_i32imm: { |
| 873 | |
| 874 | if (Subtarget->useMovt()) |
| 875 | return true; |
| 876 | if (ARM_AM::isSOImmTwoPartVal(Imm.getZExtValue())) |
| 877 | return true; |
| 878 | return ARM_AM::isSOImmTwoPartValNeg(Imm.getZExtValue()); |
| 879 | |
| 880 | llvm_unreachable("arm_i32imm should have returned"); |
| 881 | } |
| 882 | } |
| 883 | llvm_unreachable("Unknown predicate"); |
| 884 | return false; |
| 885 | } |
| 886 | bool ARMInstructionSelector::testSimplePredicate(unsigned) const { |
| 887 | llvm_unreachable("ARMInstructionSelector does not support simple predicates!"); |
| 888 | return false; |
| 889 | } |
| 890 | // Custom renderers. |
| 891 | enum { |
| 892 | GICR_Invalid, |
| 893 | GICR_renderInvertedImm, |
| 894 | GICR_renderVFPF32Imm, |
| 895 | GICR_renderVFPF64Imm, |
| 896 | }; |
| 897 | ARMInstructionSelector::CustomRendererFn |
| 898 | ARMInstructionSelector::CustomRenderers[] = { |
| 899 | nullptr, // GICR_Invalid |
| 900 | &ARMInstructionSelector::renderInvertedImm, |
| 901 | &ARMInstructionSelector::renderVFPF32Imm, |
| 902 | &ARMInstructionSelector::renderVFPF64Imm, |
| 903 | }; |
| 904 | |
| 905 | bool ARMInstructionSelector::selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const { |
| 906 | const PredicateBitset AvailableFeatures = getAvailableFeatures(); |
| 907 | MachineIRBuilder B(I); |
| 908 | State.MIs.clear(); |
| 909 | State.MIs.push_back(&I); |
| 910 | |
| 911 | if (executeMatchTable(*this, State, ExecInfo, B, getMatchTable(), TII, MF->getRegInfo(), TRI, RBI, AvailableFeatures, &CoverageInfo)) { |
| 912 | return true; |
| 913 | } |
| 914 | |
| 915 | return false; |
| 916 | } |
| 917 | |
| 918 | bool ARMInstructionSelector::runCustomAction(unsigned, const MatcherState&, NewMIVector &) const { |
| 919 | llvm_unreachable("ARMInstructionSelector does not support custom C++ actions!"); |
| 920 | } |
| 921 | #if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ |
| 922 | #define GIMT_Encode2(Val) uint8_t(Val), uint8_t((uint16_t)Val >> 8) |
| 923 | #define GIMT_Encode4(Val) uint8_t(Val), uint8_t((uint32_t)Val >> 8), uint8_t((uint32_t)Val >> 16), uint8_t((uint32_t)Val >> 24) |
| 924 | #define GIMT_Encode8(Val) uint8_t(Val), uint8_t((uint64_t)Val >> 8), uint8_t((uint64_t)Val >> 16), uint8_t((uint64_t)Val >> 24), uint8_t((uint64_t)Val >> 32), uint8_t((uint64_t)Val >> 40), uint8_t((uint64_t)Val >> 48), uint8_t((uint64_t)Val >> 56) |
| 925 | #else |
| 926 | #define GIMT_Encode2(Val) uint8_t((uint16_t)Val >> 8), uint8_t(Val) |
| 927 | #define GIMT_Encode4(Val) uint8_t((uint32_t)Val >> 24), uint8_t((uint32_t)Val >> 16), uint8_t((uint32_t)Val >> 8), uint8_t(Val) |
| 928 | #define GIMT_Encode8(Val) uint8_t((uint64_t)Val >> 56), uint8_t((uint64_t)Val >> 48), uint8_t((uint64_t)Val >> 40), uint8_t((uint64_t)Val >> 32), uint8_t((uint64_t)Val >> 24), uint8_t((uint64_t)Val >> 16), uint8_t((uint64_t)Val >> 8), uint8_t(Val) |
| 929 | #endif |
| 930 | const uint8_t *ARMInstructionSelector::getMatchTable() const { |
| 931 | constexpr static uint8_t MatchTable0[] = { |
| 932 | /* 0 */ GIM_SwitchOpcode, /*MI*/0, /*[*/GIMT_Encode2(53), GIMT_Encode2(308), /*)*//*default:*//*Label 79*/ GIMT_Encode4(130893), |
| 933 | /* 10 */ /*TargetOpcode::G_ADD*//*Label 0*/ GIMT_Encode4(1030), |
| 934 | /* 14 */ /*TargetOpcode::G_SUB*//*Label 1*/ GIMT_Encode4(10357), |
| 935 | /* 18 */ /*TargetOpcode::G_MUL*//*Label 2*/ GIMT_Encode4(13601), |
| 936 | /* 22 */ /*TargetOpcode::G_SDIV*//*Label 3*/ GIMT_Encode4(15305), |
| 937 | /* 26 */ /*TargetOpcode::G_UDIV*//*Label 4*/ GIMT_Encode4(15401), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 938 | /* 46 */ /*TargetOpcode::G_AND*//*Label 5*/ GIMT_Encode4(15497), |
| 939 | /* 50 */ /*TargetOpcode::G_OR*//*Label 6*/ GIMT_Encode4(18677), |
| 940 | /* 54 */ /*TargetOpcode::G_XOR*//*Label 7*/ GIMT_Encode4(24486), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 941 | /* 114 */ /*TargetOpcode::G_CONCAT_VECTORS*//*Label 8*/ GIMT_Encode4(26181), GIMT_Encode4(0), GIMT_Encode4(0), |
| 942 | /* 126 */ /*TargetOpcode::G_BITCAST*//*Label 9*/ GIMT_Encode4(26568), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 943 | /* 142 */ /*TargetOpcode::G_INTRINSIC_TRUNC*//*Label 10*/ GIMT_Encode4(35580), |
| 944 | /* 146 */ /*TargetOpcode::G_INTRINSIC_ROUND*//*Label 11*/ GIMT_Encode4(35988), GIMT_Encode4(0), GIMT_Encode4(0), |
| 945 | /* 158 */ /*TargetOpcode::G_INTRINSIC_ROUNDEVEN*//*Label 12*/ GIMT_Encode4(36363), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 946 | /* 174 */ /*TargetOpcode::G_SEXTLOAD*//*Label 13*/ GIMT_Encode4(36626), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 947 | /* 294 */ /*TargetOpcode::G_FENCE*//*Label 14*/ GIMT_Encode4(36789), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 948 | /* 314 */ /*TargetOpcode::G_INTRINSIC*//*Label 15*/ GIMT_Encode4(36810), |
| 949 | /* 318 */ /*TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS*//*Label 16*/ GIMT_Encode4(91130), GIMT_Encode4(0), GIMT_Encode4(0), |
| 950 | /* 330 */ /*TargetOpcode::G_ANYEXT*//*Label 17*/ GIMT_Encode4(98792), |
| 951 | /* 334 */ /*TargetOpcode::G_TRUNC*//*Label 18*/ GIMT_Encode4(98950), |
| 952 | /* 338 */ /*TargetOpcode::G_CONSTANT*//*Label 19*/ GIMT_Encode4(99108), |
| 953 | /* 342 */ /*TargetOpcode::G_FCONSTANT*//*Label 20*/ GIMT_Encode4(99429), GIMT_Encode4(0), GIMT_Encode4(0), |
| 954 | /* 354 */ /*TargetOpcode::G_SEXT*//*Label 21*/ GIMT_Encode4(99525), |
| 955 | /* 358 */ /*TargetOpcode::G_SEXT_INREG*//*Label 22*/ GIMT_Encode4(99683), |
| 956 | /* 362 */ /*TargetOpcode::G_ZEXT*//*Label 23*/ GIMT_Encode4(100288), |
| 957 | /* 366 */ /*TargetOpcode::G_SHL*//*Label 24*/ GIMT_Encode4(100446), |
| 958 | /* 370 */ /*TargetOpcode::G_LSHR*//*Label 25*/ GIMT_Encode4(100662), |
| 959 | /* 374 */ /*TargetOpcode::G_ASHR*//*Label 26*/ GIMT_Encode4(100770), GIMT_Encode4(0), GIMT_Encode4(0), |
| 960 | /* 386 */ /*TargetOpcode::G_ROTR*//*Label 27*/ GIMT_Encode4(101043), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 961 | /* 454 */ /*TargetOpcode::G_UMULH*//*Label 28*/ GIMT_Encode4(101375), |
| 962 | /* 458 */ /*TargetOpcode::G_SMULH*//*Label 29*/ GIMT_Encode4(101623), |
| 963 | /* 462 */ /*TargetOpcode::G_UADDSAT*//*Label 30*/ GIMT_Encode4(101992), |
| 964 | /* 466 */ /*TargetOpcode::G_SADDSAT*//*Label 31*/ GIMT_Encode4(102637), |
| 965 | /* 470 */ /*TargetOpcode::G_USUBSAT*//*Label 32*/ GIMT_Encode4(103937), |
| 966 | /* 474 */ /*TargetOpcode::G_SSUBSAT*//*Label 33*/ GIMT_Encode4(104582), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 967 | /* 518 */ /*TargetOpcode::G_FADD*//*Label 34*/ GIMT_Encode4(105602), |
| 968 | /* 522 */ /*TargetOpcode::G_FSUB*//*Label 35*/ GIMT_Encode4(107955), |
| 969 | /* 526 */ /*TargetOpcode::G_FMUL*//*Label 36*/ GIMT_Encode4(109632), |
| 970 | /* 530 */ /*TargetOpcode::G_FMA*//*Label 37*/ GIMT_Encode4(110613), GIMT_Encode4(0), |
| 971 | /* 538 */ /*TargetOpcode::G_FDIV*//*Label 38*/ GIMT_Encode4(112704), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 972 | /* 586 */ /*TargetOpcode::G_FNEG*//*Label 39*/ GIMT_Encode4(112869), |
| 973 | /* 590 */ /*TargetOpcode::G_FPEXT*//*Label 40*/ GIMT_Encode4(114400), |
| 974 | /* 594 */ /*TargetOpcode::G_FPTRUNC*//*Label 41*/ GIMT_Encode4(114636), |
| 975 | /* 598 */ /*TargetOpcode::G_FPTOSI*//*Label 42*/ GIMT_Encode4(114908), |
| 976 | /* 602 */ /*TargetOpcode::G_FPTOUI*//*Label 43*/ GIMT_Encode4(116242), |
| 977 | /* 606 */ /*TargetOpcode::G_SITOFP*//*Label 44*/ GIMT_Encode4(117576), |
| 978 | /* 610 */ /*TargetOpcode::G_UITOFP*//*Label 45*/ GIMT_Encode4(118228), GIMT_Encode4(0), GIMT_Encode4(0), |
| 979 | /* 622 */ /*TargetOpcode::G_FABS*//*Label 46*/ GIMT_Encode4(118880), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 980 | /* 638 */ /*TargetOpcode::G_FMINNUM*//*Label 47*/ GIMT_Encode4(119656), |
| 981 | /* 642 */ /*TargetOpcode::G_FMAXNUM*//*Label 48*/ GIMT_Encode4(120248), GIMT_Encode4(0), GIMT_Encode4(0), |
| 982 | /* 654 */ /*TargetOpcode::G_FMINIMUM*//*Label 49*/ GIMT_Encode4(120840), |
| 983 | /* 658 */ /*TargetOpcode::G_FMAXIMUM*//*Label 50*/ GIMT_Encode4(121574), GIMT_Encode4(0), GIMT_Encode4(0), |
| 984 | /* 670 */ /*TargetOpcode::G_GET_FPENV*//*Label 51*/ GIMT_Encode4(122308), |
| 985 | /* 674 */ /*TargetOpcode::G_SET_FPENV*//*Label 52*/ GIMT_Encode4(122341), |
| 986 | /* 678 */ /*TargetOpcode::G_RESET_FPENV*//*Label 53*/ GIMT_Encode4(122377), |
| 987 | /* 682 */ /*TargetOpcode::G_GET_FPMODE*//*Label 54*/ GIMT_Encode4(122506), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 988 | /* 702 */ /*TargetOpcode::G_SMIN*//*Label 55*/ GIMT_Encode4(122539), |
| 989 | /* 706 */ /*TargetOpcode::G_SMAX*//*Label 56*/ GIMT_Encode4(123082), |
| 990 | /* 710 */ /*TargetOpcode::G_UMIN*//*Label 57*/ GIMT_Encode4(123625), |
| 991 | /* 714 */ /*TargetOpcode::G_UMAX*//*Label 58*/ GIMT_Encode4(124546), |
| 992 | /* 718 */ /*TargetOpcode::G_ABS*//*Label 59*/ GIMT_Encode4(125467), GIMT_Encode4(0), GIMT_Encode4(0), |
| 993 | /* 730 */ /*TargetOpcode::G_BR*//*Label 60*/ GIMT_Encode4(125938), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 994 | /* 750 */ /*TargetOpcode::G_INSERT_VECTOR_ELT*//*Label 61*/ GIMT_Encode4(126011), |
| 995 | /* 754 */ /*TargetOpcode::G_EXTRACT_VECTOR_ELT*//*Label 62*/ GIMT_Encode4(126311), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 996 | /* 782 */ /*TargetOpcode::G_CTLZ*//*Label 63*/ GIMT_Encode4(126368), GIMT_Encode4(0), |
| 997 | /* 790 */ /*TargetOpcode::G_CTPOP*//*Label 64*/ GIMT_Encode4(126929), |
| 998 | /* 794 */ /*TargetOpcode::G_BSWAP*//*Label 65*/ GIMT_Encode4(127037), |
| 999 | /* 798 */ /*TargetOpcode::G_BITREVERSE*//*Label 66*/ GIMT_Encode4(127327), |
| 1000 | /* 802 */ /*TargetOpcode::G_FCEIL*//*Label 67*/ GIMT_Encode4(127759), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 1001 | /* 850 */ /*TargetOpcode::G_FSQRT*//*Label 68*/ GIMT_Encode4(128134), |
| 1002 | /* 854 */ /*TargetOpcode::G_FFLOOR*//*Label 69*/ GIMT_Encode4(128272), |
| 1003 | /* 858 */ /*TargetOpcode::G_FRINT*//*Label 70*/ GIMT_Encode4(128647), |
| 1004 | /* 862 */ /*TargetOpcode::G_FNEARBYINT*//*Label 71*/ GIMT_Encode4(129055), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 1005 | /* 950 */ /*TargetOpcode::G_TRAP*//*Label 72*/ GIMT_Encode4(129193), |
| 1006 | /* 954 */ /*TargetOpcode::G_DEBUGTRAP*//*Label 73*/ GIMT_Encode4(129239), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 1007 | /* 994 */ /*TargetOpcode::G_VECREDUCE_ADD*//*Label 74*/ GIMT_Encode4(129326), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 1008 | /* 1014 */ /*TargetOpcode::G_VECREDUCE_SMAX*//*Label 75*/ GIMT_Encode4(129747), |
| 1009 | /* 1018 */ /*TargetOpcode::G_VECREDUCE_SMIN*//*Label 76*/ GIMT_Encode4(130027), |
| 1010 | /* 1022 */ /*TargetOpcode::G_VECREDUCE_UMAX*//*Label 77*/ GIMT_Encode4(130316), |
| 1011 | /* 1026 */ /*TargetOpcode::G_VECREDUCE_UMIN*//*Label 78*/ GIMT_Encode4(130597), |
| 1012 | /* 1030 */ // Label 0: @1030 |
| 1013 | /* 1030 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(16), /*)*//*default:*//*Label 89*/ GIMT_Encode4(10356), |
| 1014 | /* 1041 */ /*GILLT_s32*//*Label 80*/ GIMT_Encode4(1101), |
| 1015 | /* 1045 */ /*GILLT_s64*//*Label 81*/ GIMT_Encode4(6877), GIMT_Encode4(0), |
| 1016 | /* 1053 */ /*GILLT_v2s32*//*Label 82*/ GIMT_Encode4(6924), |
| 1017 | /* 1057 */ /*GILLT_v2s64*//*Label 83*/ GIMT_Encode4(7109), GIMT_Encode4(0), |
| 1018 | /* 1065 */ /*GILLT_v4s16*//*Label 84*/ GIMT_Encode4(7820), |
| 1019 | /* 1069 */ /*GILLT_v4s32*//*Label 85*/ GIMT_Encode4(8005), GIMT_Encode4(0), GIMT_Encode4(0), |
| 1020 | /* 1081 */ /*GILLT_v8s8*//*Label 86*/ GIMT_Encode4(8961), |
| 1021 | /* 1085 */ /*GILLT_v8s16*//*Label 87*/ GIMT_Encode4(9146), GIMT_Encode4(0), GIMT_Encode4(0), |
| 1022 | /* 1097 */ /*GILLT_v16s8*//*Label 88*/ GIMT_Encode4(10102), |
| 1023 | /* 1101 */ // Label 80: @1101 |
| 1024 | /* 1101 */ GIM_Try, /*On fail goto*//*Label 90*/ GIMT_Encode4(6876), |
| 1025 | /* 1106 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 1026 | /* 1109 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 1027 | /* 1112 */ GIM_Try, /*On fail goto*//*Label 91*/ GIMT_Encode4(1187), // Rule ID 5670 // |
| 1028 | /* 1117 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 1029 | /* 1120 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1030 | /* 1124 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1031 | /* 1128 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 1032 | /* 1132 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1033 | /* 1136 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1034 | /* 1140 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 1035 | /* 1145 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(255), |
| 1036 | /* 1156 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 1037 | /* 1160 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 1038 | /* 1162 */ // (add:{ *:[i32] } (and:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 255:{ *:[i32] }), GPR:{ *:[i32] }:$Rn) => (UXTAB:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, 0:{ *:[i32] }) |
| 1039 | /* 1162 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UXTAB), |
| 1040 | /* 1165 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1041 | /* 1167 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 1042 | /* 1169 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 1043 | /* 1173 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 1044 | /* 1176 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1045 | /* 1179 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1046 | /* 1185 */ GIR_RootConstrainSelectedInstOperands, |
| 1047 | /* 1186 */ // GIR_Coverage, 5670, |
| 1048 | /* 1186 */ GIR_EraseRootFromParent_Done, |
| 1049 | /* 1187 */ // Label 91: @1187 |
| 1050 | /* 1187 */ GIM_Try, /*On fail goto*//*Label 92*/ GIMT_Encode4(1262), // Rule ID 5671 // |
| 1051 | /* 1192 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 1052 | /* 1195 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1053 | /* 1199 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1054 | /* 1203 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 1055 | /* 1207 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1056 | /* 1211 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1057 | /* 1215 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 1058 | /* 1220 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535), |
| 1059 | /* 1231 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 1060 | /* 1235 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 1061 | /* 1237 */ // (add:{ *:[i32] } (and:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] }), GPR:{ *:[i32] }:$Rn) => (UXTAH:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, 0:{ *:[i32] }) |
| 1062 | /* 1237 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UXTAH), |
| 1063 | /* 1240 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1064 | /* 1242 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 1065 | /* 1244 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 1066 | /* 1248 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 1067 | /* 1251 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1068 | /* 1254 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1069 | /* 1260 */ GIR_RootConstrainSelectedInstOperands, |
| 1070 | /* 1261 */ // GIR_Coverage, 5671, |
| 1071 | /* 1261 */ GIR_EraseRootFromParent_Done, |
| 1072 | /* 1262 */ // Label 92: @1262 |
| 1073 | /* 1262 */ GIM_Try, /*On fail goto*//*Label 93*/ GIMT_Encode4(1337), // Rule ID 5705 // |
| 1074 | /* 1267 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 1075 | /* 1270 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1076 | /* 1274 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1077 | /* 1278 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 1078 | /* 1282 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1079 | /* 1286 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1080 | /* 1290 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1081 | /* 1295 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(255), |
| 1082 | /* 1306 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1083 | /* 1310 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 1084 | /* 1312 */ // (add:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 255:{ *:[i32] }), rGPR:{ *:[i32] }:$Rn) => (t2UXTAB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] }) |
| 1085 | /* 1312 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UXTAB), |
| 1086 | /* 1315 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1087 | /* 1317 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 1088 | /* 1319 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 1089 | /* 1323 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 1090 | /* 1326 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1091 | /* 1329 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1092 | /* 1335 */ GIR_RootConstrainSelectedInstOperands, |
| 1093 | /* 1336 */ // GIR_Coverage, 5705, |
| 1094 | /* 1336 */ GIR_EraseRootFromParent_Done, |
| 1095 | /* 1337 */ // Label 93: @1337 |
| 1096 | /* 1337 */ GIM_Try, /*On fail goto*//*Label 94*/ GIMT_Encode4(1412), // Rule ID 5706 // |
| 1097 | /* 1342 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 1098 | /* 1345 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1099 | /* 1349 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1100 | /* 1353 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 1101 | /* 1357 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1102 | /* 1361 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1103 | /* 1365 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1104 | /* 1370 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535), |
| 1105 | /* 1381 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1106 | /* 1385 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 1107 | /* 1387 */ // (add:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] }), rGPR:{ *:[i32] }:$Rn) => (t2UXTAH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] }) |
| 1108 | /* 1387 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UXTAH), |
| 1109 | /* 1390 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1110 | /* 1392 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 1111 | /* 1394 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 1112 | /* 1398 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 1113 | /* 1401 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1114 | /* 1404 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1115 | /* 1410 */ GIR_RootConstrainSelectedInstOperands, |
| 1116 | /* 1411 */ // GIR_Coverage, 5706, |
| 1117 | /* 1411 */ GIR_EraseRootFromParent_Done, |
| 1118 | /* 1412 */ // Label 94: @1412 |
| 1119 | /* 1412 */ GIM_Try, /*On fail goto*//*Label 95*/ GIMT_Encode4(1487), // Rule ID 2000 // |
| 1120 | /* 1417 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 1121 | /* 1420 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1122 | /* 1424 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 1123 | /* 1428 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 1124 | /* 1432 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 1125 | /* 1436 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1126 | /* 1440 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1127 | /* 1444 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 1128 | /* 1449 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(255), |
| 1129 | /* 1460 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 1130 | /* 1462 */ // (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (and:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 255:{ *:[i32] })) => (UXTAB:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, 0:{ *:[i32] }) |
| 1131 | /* 1462 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UXTAB), |
| 1132 | /* 1465 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1133 | /* 1467 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 1134 | /* 1469 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 1135 | /* 1473 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 1136 | /* 1476 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1137 | /* 1479 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1138 | /* 1485 */ GIR_RootConstrainSelectedInstOperands, |
| 1139 | /* 1486 */ // GIR_Coverage, 2000, |
| 1140 | /* 1486 */ GIR_EraseRootFromParent_Done, |
| 1141 | /* 1487 */ // Label 95: @1487 |
| 1142 | /* 1487 */ GIM_Try, /*On fail goto*//*Label 96*/ GIMT_Encode4(1562), // Rule ID 2001 // |
| 1143 | /* 1492 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 1144 | /* 1495 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1145 | /* 1499 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 1146 | /* 1503 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 1147 | /* 1507 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 1148 | /* 1511 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1149 | /* 1515 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1150 | /* 1519 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 1151 | /* 1524 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535), |
| 1152 | /* 1535 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 1153 | /* 1537 */ // (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (and:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] })) => (UXTAH:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, 0:{ *:[i32] }) |
| 1154 | /* 1537 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UXTAH), |
| 1155 | /* 1540 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1156 | /* 1542 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 1157 | /* 1544 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 1158 | /* 1548 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 1159 | /* 1551 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1160 | /* 1554 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1161 | /* 1560 */ GIR_RootConstrainSelectedInstOperands, |
| 1162 | /* 1561 */ // GIR_Coverage, 2001, |
| 1163 | /* 1561 */ GIR_EraseRootFromParent_Done, |
| 1164 | /* 1562 */ // Label 96: @1562 |
| 1165 | /* 1562 */ GIM_Try, /*On fail goto*//*Label 97*/ GIMT_Encode4(1637), // Rule ID 2239 // |
| 1166 | /* 1567 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 1167 | /* 1570 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1168 | /* 1574 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1169 | /* 1578 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 1170 | /* 1582 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 1171 | /* 1586 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1172 | /* 1590 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1173 | /* 1594 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1174 | /* 1599 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(255), |
| 1175 | /* 1610 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 1176 | /* 1612 */ // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 255:{ *:[i32] })) => (t2UXTAB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] }) |
| 1177 | /* 1612 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UXTAB), |
| 1178 | /* 1615 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1179 | /* 1617 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 1180 | /* 1619 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 1181 | /* 1623 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 1182 | /* 1626 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1183 | /* 1629 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1184 | /* 1635 */ GIR_RootConstrainSelectedInstOperands, |
| 1185 | /* 1636 */ // GIR_Coverage, 2239, |
| 1186 | /* 1636 */ GIR_EraseRootFromParent_Done, |
| 1187 | /* 1637 */ // Label 97: @1637 |
| 1188 | /* 1637 */ GIM_Try, /*On fail goto*//*Label 98*/ GIMT_Encode4(1712), // Rule ID 2240 // |
| 1189 | /* 1642 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 1190 | /* 1645 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1191 | /* 1649 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1192 | /* 1653 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 1193 | /* 1657 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 1194 | /* 1661 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1195 | /* 1665 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1196 | /* 1669 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1197 | /* 1674 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535), |
| 1198 | /* 1685 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 1199 | /* 1687 */ // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] })) => (t2UXTAH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] }) |
| 1200 | /* 1687 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UXTAH), |
| 1201 | /* 1690 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1202 | /* 1692 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 1203 | /* 1694 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 1204 | /* 1698 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 1205 | /* 1701 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1206 | /* 1704 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1207 | /* 1710 */ GIR_RootConstrainSelectedInstOperands, |
| 1208 | /* 1711 */ // GIR_Coverage, 2240, |
| 1209 | /* 1711 */ GIR_EraseRootFromParent_Done, |
| 1210 | /* 1712 */ // Label 98: @1712 |
| 1211 | /* 1712 */ GIM_Try, /*On fail goto*//*Label 99*/ GIMT_Encode4(1840), // Rule ID 5681 // |
| 1212 | /* 1717 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 1213 | /* 1720 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1214 | /* 1724 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1215 | /* 1728 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 1216 | /* 1732 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1217 | /* 1736 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 1218 | /* 1740 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR), |
| 1219 | /* 1744 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 1220 | /* 1748 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 1221 | /* 1752 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 1222 | /* 1756 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 1223 | /* 1760 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 1224 | /* 1764 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 1225 | /* 1768 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1226 | /* 1773 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 24, |
| 1227 | /* 1777 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4] |
| 1228 | /* 1781 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_SHL), |
| 1229 | /* 1785 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32, |
| 1230 | /* 1789 */ // MIs[4] Rm |
| 1231 | /* 1789 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1, |
| 1232 | /* 1794 */ GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 8, |
| 1233 | /* 1798 */ // MIs[1] Operand 2 |
| 1234 | /* 1798 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16), |
| 1235 | /* 1809 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1236 | /* 1813 */ GIM_CheckIsSafeToFold, /*NumInsns*/4, |
| 1237 | /* 1815 */ // (add:{ *:[i32] } (sext_inreg:{ *:[i32] } (or:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 24:{ *:[i32] }), (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 8:{ *:[i32] })), i16:{ *:[Other] }), rGPR:{ *:[i32] }:$Rn) => (t2SXTAH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 3:{ *:[i32] }) |
| 1238 | /* 1815 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SXTAH), |
| 1239 | /* 1818 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1240 | /* 1820 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 1241 | /* 1822 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm |
| 1242 | /* 1826 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 1243 | /* 1829 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1244 | /* 1832 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1245 | /* 1838 */ GIR_RootConstrainSelectedInstOperands, |
| 1246 | /* 1839 */ // GIR_Coverage, 5681, |
| 1247 | /* 1839 */ GIR_EraseRootFromParent_Done, |
| 1248 | /* 1840 */ // Label 99: @1840 |
| 1249 | /* 1840 */ GIM_Try, /*On fail goto*//*Label 100*/ GIMT_Encode4(1968), // Rule ID 5682 // |
| 1250 | /* 1845 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 1251 | /* 1848 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1252 | /* 1852 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1253 | /* 1856 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 1254 | /* 1860 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1255 | /* 1864 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 1256 | /* 1868 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR), |
| 1257 | /* 1872 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 1258 | /* 1876 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 1259 | /* 1880 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 1260 | /* 1884 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL), |
| 1261 | /* 1888 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 1262 | /* 1892 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 1263 | /* 1896 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1264 | /* 1901 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 8, |
| 1265 | /* 1905 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4] |
| 1266 | /* 1909 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 1267 | /* 1913 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32, |
| 1268 | /* 1917 */ // MIs[4] Rm |
| 1269 | /* 1917 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1, |
| 1270 | /* 1922 */ GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 24, |
| 1271 | /* 1926 */ // MIs[1] Operand 2 |
| 1272 | /* 1926 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16), |
| 1273 | /* 1937 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1274 | /* 1941 */ GIM_CheckIsSafeToFold, /*NumInsns*/4, |
| 1275 | /* 1943 */ // (add:{ *:[i32] } (sext_inreg:{ *:[i32] } (or:{ *:[i32] } (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 8:{ *:[i32] }), (srl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 24:{ *:[i32] })), i16:{ *:[Other] }), rGPR:{ *:[i32] }:$Rn) => (t2SXTAH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 3:{ *:[i32] }) |
| 1276 | /* 1943 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SXTAH), |
| 1277 | /* 1946 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1278 | /* 1948 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 1279 | /* 1950 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm |
| 1280 | /* 1954 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 1281 | /* 1957 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1282 | /* 1960 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1283 | /* 1966 */ GIR_RootConstrainSelectedInstOperands, |
| 1284 | /* 1967 */ // GIR_Coverage, 5682, |
| 1285 | /* 1967 */ GIR_EraseRootFromParent_Done, |
| 1286 | /* 1968 */ // Label 100: @1968 |
| 1287 | /* 1968 */ GIM_Try, /*On fail goto*//*Label 101*/ GIMT_Encode4(2096), // Rule ID 2106 // |
| 1288 | /* 1973 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 1289 | /* 1976 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1290 | /* 1980 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1291 | /* 1984 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 1292 | /* 1988 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 1293 | /* 1992 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1294 | /* 1996 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 1295 | /* 2000 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR), |
| 1296 | /* 2004 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 1297 | /* 2008 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 1298 | /* 2012 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 1299 | /* 2016 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 1300 | /* 2020 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 1301 | /* 2024 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 1302 | /* 2028 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1303 | /* 2033 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 24, |
| 1304 | /* 2037 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4] |
| 1305 | /* 2041 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_SHL), |
| 1306 | /* 2045 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32, |
| 1307 | /* 2049 */ // MIs[4] Rm |
| 1308 | /* 2049 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1, |
| 1309 | /* 2054 */ GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 8, |
| 1310 | /* 2058 */ // MIs[1] Operand 2 |
| 1311 | /* 2058 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16), |
| 1312 | /* 2069 */ GIM_CheckIsSafeToFold, /*NumInsns*/4, |
| 1313 | /* 2071 */ // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (sext_inreg:{ *:[i32] } (or:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 24:{ *:[i32] }), (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 8:{ *:[i32] })), i16:{ *:[Other] })) => (t2SXTAH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 3:{ *:[i32] }) |
| 1314 | /* 2071 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SXTAH), |
| 1315 | /* 2074 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1316 | /* 2076 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 1317 | /* 2078 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm |
| 1318 | /* 2082 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 1319 | /* 2085 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1320 | /* 2088 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1321 | /* 2094 */ GIR_RootConstrainSelectedInstOperands, |
| 1322 | /* 2095 */ // GIR_Coverage, 2106, |
| 1323 | /* 2095 */ GIR_EraseRootFromParent_Done, |
| 1324 | /* 2096 */ // Label 101: @2096 |
| 1325 | /* 2096 */ GIM_Try, /*On fail goto*//*Label 102*/ GIMT_Encode4(2224), // Rule ID 5680 // |
| 1326 | /* 2101 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 1327 | /* 2104 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1328 | /* 2108 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1329 | /* 2112 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 1330 | /* 2116 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 1331 | /* 2120 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1332 | /* 2124 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 1333 | /* 2128 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR), |
| 1334 | /* 2132 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 1335 | /* 2136 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 1336 | /* 2140 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 1337 | /* 2144 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL), |
| 1338 | /* 2148 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 1339 | /* 2152 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 1340 | /* 2156 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1341 | /* 2161 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 8, |
| 1342 | /* 2165 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4] |
| 1343 | /* 2169 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 1344 | /* 2173 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32, |
| 1345 | /* 2177 */ // MIs[4] Rm |
| 1346 | /* 2177 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1, |
| 1347 | /* 2182 */ GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 24, |
| 1348 | /* 2186 */ // MIs[1] Operand 2 |
| 1349 | /* 2186 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16), |
| 1350 | /* 2197 */ GIM_CheckIsSafeToFold, /*NumInsns*/4, |
| 1351 | /* 2199 */ // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (sext_inreg:{ *:[i32] } (or:{ *:[i32] } (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 8:{ *:[i32] }), (srl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 24:{ *:[i32] })), i16:{ *:[Other] })) => (t2SXTAH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 3:{ *:[i32] }) |
| 1352 | /* 2199 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SXTAH), |
| 1353 | /* 2202 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1354 | /* 2204 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 1355 | /* 2206 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm |
| 1356 | /* 2210 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 1357 | /* 2213 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1358 | /* 2216 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1359 | /* 2222 */ GIR_RootConstrainSelectedInstOperands, |
| 1360 | /* 2223 */ // GIR_Coverage, 5680, |
| 1361 | /* 2223 */ GIR_EraseRootFromParent_Done, |
| 1362 | /* 2224 */ // Label 102: @2224 |
| 1363 | /* 2224 */ GIM_Try, /*On fail goto*//*Label 103*/ GIMT_Encode4(2334), // Rule ID 5449 // |
| 1364 | /* 2229 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM_UseMulOps), |
| 1365 | /* 2232 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1366 | /* 2236 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1367 | /* 2240 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 1368 | /* 2244 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1369 | /* 2248 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1370 | /* 2252 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 1371 | /* 2256 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 1372 | /* 2260 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 1373 | /* 2264 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 1374 | /* 2268 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1375 | /* 2273 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16, |
| 1376 | /* 2277 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] |
| 1377 | /* 2281 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 1378 | /* 2285 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 1379 | /* 2289 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 1380 | /* 2293 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1381 | /* 2298 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16, |
| 1382 | /* 2302 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 1383 | /* 2306 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 1384 | /* 2308 */ // (add:{ *:[i32] } (mul:{ *:[i32] } (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, 16:{ *:[i32] })), GPR:{ *:[i32] }:$Ra) => (SMLATT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) |
| 1385 | /* 2308 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLATT), |
| 1386 | /* 2311 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1387 | /* 2313 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn |
| 1388 | /* 2317 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm |
| 1389 | /* 2321 */ GIR_RootToRootCopy, /*OpIdx*/2, // Ra |
| 1390 | /* 2323 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1391 | /* 2326 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1392 | /* 2332 */ GIR_RootConstrainSelectedInstOperands, |
| 1393 | /* 2333 */ // GIR_Coverage, 5449, |
| 1394 | /* 2333 */ GIR_EraseRootFromParent_Done, |
| 1395 | /* 2334 */ // Label 103: @2334 |
| 1396 | /* 2334 */ GIM_Try, /*On fail goto*//*Label 104*/ GIMT_Encode4(2444), // Rule ID 5486 // |
| 1397 | /* 2339 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2_UseMulOps), |
| 1398 | /* 2342 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1399 | /* 2346 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1400 | /* 2350 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 1401 | /* 2354 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1402 | /* 2358 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1403 | /* 2362 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 1404 | /* 2366 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 1405 | /* 2370 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 1406 | /* 2374 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 1407 | /* 2378 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1408 | /* 2383 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16, |
| 1409 | /* 2387 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] |
| 1410 | /* 2391 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 1411 | /* 2395 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 1412 | /* 2399 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 1413 | /* 2403 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1414 | /* 2408 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16, |
| 1415 | /* 2412 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1416 | /* 2416 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 1417 | /* 2418 */ // (add:{ *:[i32] } (mul:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 16:{ *:[i32] })), rGPR:{ *:[i32] }:$Ra) => (t2SMLATT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) |
| 1418 | /* 2418 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLATT), |
| 1419 | /* 2421 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1420 | /* 2423 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn |
| 1421 | /* 2427 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm |
| 1422 | /* 2431 */ GIR_RootToRootCopy, /*OpIdx*/2, // Ra |
| 1423 | /* 2433 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1424 | /* 2436 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1425 | /* 2442 */ GIR_RootConstrainSelectedInstOperands, |
| 1426 | /* 2443 */ // GIR_Coverage, 5486, |
| 1427 | /* 2443 */ GIR_EraseRootFromParent_Done, |
| 1428 | /* 2444 */ // Label 104: @2444 |
| 1429 | /* 2444 */ GIM_Try, /*On fail goto*//*Label 105*/ GIMT_Encode4(2554), // Rule ID 192 // |
| 1430 | /* 2449 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM_UseMulOps), |
| 1431 | /* 2452 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1432 | /* 2456 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 1433 | /* 2460 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 1434 | /* 2464 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 1435 | /* 2468 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1436 | /* 2472 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1437 | /* 2476 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 1438 | /* 2480 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 1439 | /* 2484 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 1440 | /* 2488 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 1441 | /* 2492 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1442 | /* 2497 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16, |
| 1443 | /* 2501 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] |
| 1444 | /* 2505 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 1445 | /* 2509 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 1446 | /* 2513 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 1447 | /* 2517 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1448 | /* 2522 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16, |
| 1449 | /* 2526 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 1450 | /* 2528 */ // (add:{ *:[i32] } GPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, 16:{ *:[i32] }))) => (SMLATT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) |
| 1451 | /* 2528 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLATT), |
| 1452 | /* 2531 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1453 | /* 2533 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn |
| 1454 | /* 2537 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm |
| 1455 | /* 2541 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra |
| 1456 | /* 2543 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1457 | /* 2546 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1458 | /* 2552 */ GIR_RootConstrainSelectedInstOperands, |
| 1459 | /* 2553 */ // GIR_Coverage, 192, |
| 1460 | /* 2553 */ GIR_EraseRootFromParent_Done, |
| 1461 | /* 2554 */ // Label 105: @2554 |
| 1462 | /* 2554 */ GIM_Try, /*On fail goto*//*Label 106*/ GIMT_Encode4(2664), // Rule ID 521 // |
| 1463 | /* 2559 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2_UseMulOps), |
| 1464 | /* 2562 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1465 | /* 2566 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1466 | /* 2570 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 1467 | /* 2574 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 1468 | /* 2578 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1469 | /* 2582 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1470 | /* 2586 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 1471 | /* 2590 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 1472 | /* 2594 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 1473 | /* 2598 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 1474 | /* 2602 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1475 | /* 2607 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16, |
| 1476 | /* 2611 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] |
| 1477 | /* 2615 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 1478 | /* 2619 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 1479 | /* 2623 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 1480 | /* 2627 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1481 | /* 2632 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16, |
| 1482 | /* 2636 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 1483 | /* 2638 */ // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 16:{ *:[i32] }))) => (t2SMLATT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) |
| 1484 | /* 2638 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLATT), |
| 1485 | /* 2641 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1486 | /* 2643 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn |
| 1487 | /* 2647 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm |
| 1488 | /* 2651 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra |
| 1489 | /* 2653 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1490 | /* 2656 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1491 | /* 2662 */ GIR_RootConstrainSelectedInstOperands, |
| 1492 | /* 2663 */ // GIR_Coverage, 521, |
| 1493 | /* 2663 */ GIR_EraseRootFromParent_Done, |
| 1494 | /* 2664 */ // Label 106: @2664 |
| 1495 | /* 2664 */ GIM_Try, /*On fail goto*//*Label 107*/ GIMT_Encode4(2777), // Rule ID 5448 // |
| 1496 | /* 2669 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM_UseMulOps), |
| 1497 | /* 2672 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1498 | /* 2676 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1499 | /* 2680 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 1500 | /* 2684 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1501 | /* 2688 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1502 | /* 2692 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 1503 | /* 2696 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 1504 | /* 2700 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 1505 | /* 2704 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 1506 | /* 2708 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1507 | /* 2713 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16, |
| 1508 | /* 2717 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] |
| 1509 | /* 2721 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 1510 | /* 2725 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 1511 | /* 2729 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1512 | /* 2734 */ // MIs[3] Operand 2 |
| 1513 | /* 2734 */ GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(16), |
| 1514 | /* 2745 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 1515 | /* 2749 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 1516 | /* 2751 */ // (add:{ *:[i32] } (mul:{ *:[i32] } (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, 16:{ *:[i32] }), (sext_inreg:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, i16:{ *:[Other] })), GPR:{ *:[i32] }:$Ra) => (SMLABT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) |
| 1517 | /* 2751 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLABT), |
| 1518 | /* 2754 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1519 | /* 2756 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn |
| 1520 | /* 2760 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 1521 | /* 2764 */ GIR_RootToRootCopy, /*OpIdx*/2, // Ra |
| 1522 | /* 2766 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1523 | /* 2769 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1524 | /* 2775 */ GIR_RootConstrainSelectedInstOperands, |
| 1525 | /* 2776 */ // GIR_Coverage, 5448, |
| 1526 | /* 2776 */ GIR_EraseRootFromParent_Done, |
| 1527 | /* 2777 */ // Label 107: @2777 |
| 1528 | /* 2777 */ GIM_Try, /*On fail goto*//*Label 108*/ GIMT_Encode4(2890), // Rule ID 5485 // |
| 1529 | /* 2782 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2_UseMulOps), |
| 1530 | /* 2785 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1531 | /* 2789 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1532 | /* 2793 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 1533 | /* 2797 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1534 | /* 2801 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1535 | /* 2805 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 1536 | /* 2809 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 1537 | /* 2813 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 1538 | /* 2817 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 1539 | /* 2821 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1540 | /* 2826 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16, |
| 1541 | /* 2830 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] |
| 1542 | /* 2834 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 1543 | /* 2838 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 1544 | /* 2842 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1545 | /* 2847 */ // MIs[3] Operand 2 |
| 1546 | /* 2847 */ GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(16), |
| 1547 | /* 2858 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1548 | /* 2862 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 1549 | /* 2864 */ // (add:{ *:[i32] } (mul:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 16:{ *:[i32] }), (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, i16:{ *:[Other] })), rGPR:{ *:[i32] }:$Ra) => (t2SMLABT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) |
| 1550 | /* 2864 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLABT), |
| 1551 | /* 2867 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1552 | /* 2869 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn |
| 1553 | /* 2873 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 1554 | /* 2877 */ GIR_RootToRootCopy, /*OpIdx*/2, // Ra |
| 1555 | /* 2879 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1556 | /* 2882 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1557 | /* 2888 */ GIR_RootConstrainSelectedInstOperands, |
| 1558 | /* 2889 */ // GIR_Coverage, 5485, |
| 1559 | /* 2889 */ GIR_EraseRootFromParent_Done, |
| 1560 | /* 2890 */ // Label 108: @2890 |
| 1561 | /* 2890 */ GIM_Try, /*On fail goto*//*Label 109*/ GIMT_Encode4(3003), // Rule ID 5447 // |
| 1562 | /* 2895 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM_UseMulOps), |
| 1563 | /* 2898 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1564 | /* 2902 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1565 | /* 2906 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 1566 | /* 2910 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1567 | /* 2914 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1568 | /* 2918 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 1569 | /* 2922 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 1570 | /* 2926 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 1571 | /* 2930 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1572 | /* 2935 */ // MIs[2] Operand 2 |
| 1573 | /* 2935 */ GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16), |
| 1574 | /* 2946 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] |
| 1575 | /* 2950 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 1576 | /* 2954 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 1577 | /* 2958 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 1578 | /* 2962 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1579 | /* 2967 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16, |
| 1580 | /* 2971 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 1581 | /* 2975 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 1582 | /* 2977 */ // (add:{ *:[i32] } (mul:{ *:[i32] } (sext_inreg:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, i16:{ *:[Other] }), (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, 16:{ *:[i32] })), GPR:{ *:[i32] }:$Ra) => (SMLABT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) |
| 1583 | /* 2977 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLABT), |
| 1584 | /* 2980 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1585 | /* 2982 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn |
| 1586 | /* 2986 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm |
| 1587 | /* 2990 */ GIR_RootToRootCopy, /*OpIdx*/2, // Ra |
| 1588 | /* 2992 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1589 | /* 2995 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1590 | /* 3001 */ GIR_RootConstrainSelectedInstOperands, |
| 1591 | /* 3002 */ // GIR_Coverage, 5447, |
| 1592 | /* 3002 */ GIR_EraseRootFromParent_Done, |
| 1593 | /* 3003 */ // Label 109: @3003 |
| 1594 | /* 3003 */ GIM_Try, /*On fail goto*//*Label 110*/ GIMT_Encode4(3116), // Rule ID 5484 // |
| 1595 | /* 3008 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2_UseMulOps), |
| 1596 | /* 3011 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1597 | /* 3015 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1598 | /* 3019 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 1599 | /* 3023 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1600 | /* 3027 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1601 | /* 3031 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 1602 | /* 3035 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 1603 | /* 3039 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 1604 | /* 3043 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1605 | /* 3048 */ // MIs[2] Operand 2 |
| 1606 | /* 3048 */ GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16), |
| 1607 | /* 3059 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] |
| 1608 | /* 3063 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 1609 | /* 3067 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 1610 | /* 3071 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 1611 | /* 3075 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1612 | /* 3080 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16, |
| 1613 | /* 3084 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1614 | /* 3088 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 1615 | /* 3090 */ // (add:{ *:[i32] } (mul:{ *:[i32] } (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, i16:{ *:[Other] }), (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 16:{ *:[i32] })), rGPR:{ *:[i32] }:$Ra) => (t2SMLABT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) |
| 1616 | /* 3090 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLABT), |
| 1617 | /* 3093 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1618 | /* 3095 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn |
| 1619 | /* 3099 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm |
| 1620 | /* 3103 */ GIR_RootToRootCopy, /*OpIdx*/2, // Ra |
| 1621 | /* 3105 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1622 | /* 3108 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1623 | /* 3114 */ GIR_RootConstrainSelectedInstOperands, |
| 1624 | /* 3115 */ // GIR_Coverage, 5484, |
| 1625 | /* 3115 */ GIR_EraseRootFromParent_Done, |
| 1626 | /* 3116 */ // Label 110: @3116 |
| 1627 | /* 3116 */ GIM_Try, /*On fail goto*//*Label 111*/ GIMT_Encode4(3229), // Rule ID 191 // |
| 1628 | /* 3121 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM_UseMulOps), |
| 1629 | /* 3124 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1630 | /* 3128 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 1631 | /* 3132 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 1632 | /* 3136 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 1633 | /* 3140 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1634 | /* 3144 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1635 | /* 3148 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 1636 | /* 3152 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 1637 | /* 3156 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 1638 | /* 3160 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 1639 | /* 3164 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1640 | /* 3169 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16, |
| 1641 | /* 3173 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] |
| 1642 | /* 3177 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 1643 | /* 3181 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 1644 | /* 3185 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1645 | /* 3190 */ // MIs[3] Operand 2 |
| 1646 | /* 3190 */ GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(16), |
| 1647 | /* 3201 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 1648 | /* 3203 */ // (add:{ *:[i32] } GPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sext_inreg:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, i16:{ *:[Other] }))) => (SMLATB:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) |
| 1649 | /* 3203 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLATB), |
| 1650 | /* 3206 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1651 | /* 3208 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn |
| 1652 | /* 3212 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm |
| 1653 | /* 3216 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra |
| 1654 | /* 3218 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1655 | /* 3221 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1656 | /* 3227 */ GIR_RootConstrainSelectedInstOperands, |
| 1657 | /* 3228 */ // GIR_Coverage, 191, |
| 1658 | /* 3228 */ GIR_EraseRootFromParent_Done, |
| 1659 | /* 3229 */ // Label 111: @3229 |
| 1660 | /* 3229 */ GIM_Try, /*On fail goto*//*Label 112*/ GIMT_Encode4(3342), // Rule ID 520 // |
| 1661 | /* 3234 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2_UseMulOps), |
| 1662 | /* 3237 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1663 | /* 3241 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1664 | /* 3245 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 1665 | /* 3249 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 1666 | /* 3253 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1667 | /* 3257 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1668 | /* 3261 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 1669 | /* 3265 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 1670 | /* 3269 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 1671 | /* 3273 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 1672 | /* 3277 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1673 | /* 3282 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16, |
| 1674 | /* 3286 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] |
| 1675 | /* 3290 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 1676 | /* 3294 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 1677 | /* 3298 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1678 | /* 3303 */ // MIs[3] Operand 2 |
| 1679 | /* 3303 */ GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(16), |
| 1680 | /* 3314 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 1681 | /* 3316 */ // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, i16:{ *:[Other] }))) => (t2SMLATB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) |
| 1682 | /* 3316 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLATB), |
| 1683 | /* 3319 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1684 | /* 3321 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn |
| 1685 | /* 3325 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm |
| 1686 | /* 3329 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra |
| 1687 | /* 3331 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1688 | /* 3334 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1689 | /* 3340 */ GIR_RootConstrainSelectedInstOperands, |
| 1690 | /* 3341 */ // GIR_Coverage, 520, |
| 1691 | /* 3341 */ GIR_EraseRootFromParent_Done, |
| 1692 | /* 3342 */ // Label 112: @3342 |
| 1693 | /* 3342 */ GIM_Try, /*On fail goto*//*Label 113*/ GIMT_Encode4(3455), // Rule ID 190 // |
| 1694 | /* 3347 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM_UseMulOps), |
| 1695 | /* 3350 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1696 | /* 3354 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 1697 | /* 3358 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 1698 | /* 3362 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 1699 | /* 3366 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1700 | /* 3370 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1701 | /* 3374 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 1702 | /* 3378 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 1703 | /* 3382 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 1704 | /* 3386 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1705 | /* 3391 */ // MIs[2] Operand 2 |
| 1706 | /* 3391 */ GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16), |
| 1707 | /* 3402 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] |
| 1708 | /* 3406 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 1709 | /* 3410 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 1710 | /* 3414 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 1711 | /* 3418 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1712 | /* 3423 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16, |
| 1713 | /* 3427 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 1714 | /* 3429 */ // (add:{ *:[i32] } GPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } (sext_inreg:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, i16:{ *:[Other] }), (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, 16:{ *:[i32] }))) => (SMLABT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) |
| 1715 | /* 3429 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLABT), |
| 1716 | /* 3432 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1717 | /* 3434 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn |
| 1718 | /* 3438 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm |
| 1719 | /* 3442 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra |
| 1720 | /* 3444 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1721 | /* 3447 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1722 | /* 3453 */ GIR_RootConstrainSelectedInstOperands, |
| 1723 | /* 3454 */ // GIR_Coverage, 190, |
| 1724 | /* 3454 */ GIR_EraseRootFromParent_Done, |
| 1725 | /* 3455 */ // Label 113: @3455 |
| 1726 | /* 3455 */ GIM_Try, /*On fail goto*//*Label 114*/ GIMT_Encode4(3568), // Rule ID 519 // |
| 1727 | /* 3460 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2_UseMulOps), |
| 1728 | /* 3463 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1729 | /* 3467 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1730 | /* 3471 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 1731 | /* 3475 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 1732 | /* 3479 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1733 | /* 3483 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1734 | /* 3487 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 1735 | /* 3491 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 1736 | /* 3495 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 1737 | /* 3499 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1738 | /* 3504 */ // MIs[2] Operand 2 |
| 1739 | /* 3504 */ GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16), |
| 1740 | /* 3515 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] |
| 1741 | /* 3519 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 1742 | /* 3523 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 1743 | /* 3527 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 1744 | /* 3531 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1745 | /* 3536 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16, |
| 1746 | /* 3540 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 1747 | /* 3542 */ // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, i16:{ *:[Other] }), (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 16:{ *:[i32] }))) => (t2SMLABT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) |
| 1748 | /* 3542 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLABT), |
| 1749 | /* 3545 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1750 | /* 3547 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn |
| 1751 | /* 3551 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm |
| 1752 | /* 3555 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra |
| 1753 | /* 3557 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1754 | /* 3560 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1755 | /* 3566 */ GIR_RootConstrainSelectedInstOperands, |
| 1756 | /* 3567 */ // GIR_Coverage, 519, |
| 1757 | /* 3567 */ GIR_EraseRootFromParent_Done, |
| 1758 | /* 3568 */ // Label 114: @3568 |
| 1759 | /* 3568 */ GIM_Try, /*On fail goto*//*Label 115*/ GIMT_Encode4(3659), // Rule ID 5679 // |
| 1760 | /* 3573 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 1761 | /* 3576 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1762 | /* 3580 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1763 | /* 3584 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 1764 | /* 3588 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1765 | /* 3592 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 1766 | /* 3596 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ROTR), |
| 1767 | /* 3600 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 1768 | /* 3604 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 1769 | /* 3608 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1770 | /* 3613 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 24, |
| 1771 | /* 3617 */ // MIs[1] Operand 2 |
| 1772 | /* 3617 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16), |
| 1773 | /* 3628 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1774 | /* 3632 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 1775 | /* 3634 */ // (add:{ *:[i32] } (sext_inreg:{ *:[i32] } (rotr:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 24:{ *:[i32] }), i16:{ *:[Other] }), rGPR:{ *:[i32] }:$Rn) => (t2SXTAH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 3:{ *:[i32] }) |
| 1776 | /* 3634 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SXTAH), |
| 1777 | /* 3637 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1778 | /* 3639 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 1779 | /* 3641 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 1780 | /* 3645 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 1781 | /* 3648 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1782 | /* 3651 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1783 | /* 3657 */ GIR_RootConstrainSelectedInstOperands, |
| 1784 | /* 3658 */ // GIR_Coverage, 5679, |
| 1785 | /* 3658 */ GIR_EraseRootFromParent_Done, |
| 1786 | /* 3659 */ // Label 115: @3659 |
| 1787 | /* 3659 */ GIM_Try, /*On fail goto*//*Label 116*/ GIMT_Encode4(3750), // Rule ID 2105 // |
| 1788 | /* 3664 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 1789 | /* 3667 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1790 | /* 3671 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1791 | /* 3675 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 1792 | /* 3679 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 1793 | /* 3683 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1794 | /* 3687 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 1795 | /* 3691 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ROTR), |
| 1796 | /* 3695 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 1797 | /* 3699 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 1798 | /* 3703 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1799 | /* 3708 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 24, |
| 1800 | /* 3712 */ // MIs[1] Operand 2 |
| 1801 | /* 3712 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16), |
| 1802 | /* 3723 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 1803 | /* 3725 */ // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (sext_inreg:{ *:[i32] } (rotr:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 24:{ *:[i32] }), i16:{ *:[Other] })) => (t2SXTAH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 3:{ *:[i32] }) |
| 1804 | /* 3725 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SXTAH), |
| 1805 | /* 3728 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1806 | /* 3730 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 1807 | /* 3732 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 1808 | /* 3736 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 1809 | /* 3739 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1810 | /* 3742 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1811 | /* 3748 */ GIR_RootConstrainSelectedInstOperands, |
| 1812 | /* 3749 */ // GIR_Coverage, 2105, |
| 1813 | /* 3749 */ GIR_EraseRootFromParent_Done, |
| 1814 | /* 3750 */ // Label 116: @3750 |
| 1815 | /* 3750 */ GIM_Try, /*On fail goto*//*Label 117*/ GIMT_Encode4(3866), // Rule ID 5446 // |
| 1816 | /* 3755 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM_UseMulOps), |
| 1817 | /* 3758 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1818 | /* 3762 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1819 | /* 3766 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 1820 | /* 3770 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1821 | /* 3774 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1822 | /* 3778 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 1823 | /* 3782 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 1824 | /* 3786 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 1825 | /* 3790 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1826 | /* 3795 */ // MIs[2] Operand 2 |
| 1827 | /* 3795 */ GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16), |
| 1828 | /* 3806 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] |
| 1829 | /* 3810 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 1830 | /* 3814 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 1831 | /* 3818 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1832 | /* 3823 */ // MIs[3] Operand 2 |
| 1833 | /* 3823 */ GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(16), |
| 1834 | /* 3834 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 1835 | /* 3838 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 1836 | /* 3840 */ // (add:{ *:[i32] } (mul:{ *:[i32] } (sext_inreg:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, i16:{ *:[Other] }), (sext_inreg:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, i16:{ *:[Other] })), GPR:{ *:[i32] }:$Ra) => (SMLABB:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) |
| 1837 | /* 3840 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLABB), |
| 1838 | /* 3843 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1839 | /* 3845 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn |
| 1840 | /* 3849 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm |
| 1841 | /* 3853 */ GIR_RootToRootCopy, /*OpIdx*/2, // Ra |
| 1842 | /* 3855 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1843 | /* 3858 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1844 | /* 3864 */ GIR_RootConstrainSelectedInstOperands, |
| 1845 | /* 3865 */ // GIR_Coverage, 5446, |
| 1846 | /* 3865 */ GIR_EraseRootFromParent_Done, |
| 1847 | /* 3866 */ // Label 117: @3866 |
| 1848 | /* 3866 */ GIM_Try, /*On fail goto*//*Label 118*/ GIMT_Encode4(3982), // Rule ID 5483 // |
| 1849 | /* 3871 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2_UseMulOps), |
| 1850 | /* 3874 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1851 | /* 3878 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1852 | /* 3882 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 1853 | /* 3886 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1854 | /* 3890 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1855 | /* 3894 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 1856 | /* 3898 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 1857 | /* 3902 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 1858 | /* 3906 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1859 | /* 3911 */ // MIs[2] Operand 2 |
| 1860 | /* 3911 */ GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16), |
| 1861 | /* 3922 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] |
| 1862 | /* 3926 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 1863 | /* 3930 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 1864 | /* 3934 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1865 | /* 3939 */ // MIs[3] Operand 2 |
| 1866 | /* 3939 */ GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(16), |
| 1867 | /* 3950 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1868 | /* 3954 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 1869 | /* 3956 */ // (add:{ *:[i32] } (mul:{ *:[i32] } (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, i16:{ *:[Other] }), (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, i16:{ *:[Other] })), rGPR:{ *:[i32] }:$Ra) => (t2SMLABB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) |
| 1870 | /* 3956 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLABB), |
| 1871 | /* 3959 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1872 | /* 3961 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn |
| 1873 | /* 3965 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm |
| 1874 | /* 3969 */ GIR_RootToRootCopy, /*OpIdx*/2, // Ra |
| 1875 | /* 3971 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1876 | /* 3974 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1877 | /* 3980 */ GIR_RootConstrainSelectedInstOperands, |
| 1878 | /* 3981 */ // GIR_Coverage, 5483, |
| 1879 | /* 3981 */ GIR_EraseRootFromParent_Done, |
| 1880 | /* 3982 */ // Label 118: @3982 |
| 1881 | /* 3982 */ GIM_Try, /*On fail goto*//*Label 119*/ GIMT_Encode4(4098), // Rule ID 189 // |
| 1882 | /* 3987 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM_UseMulOps), |
| 1883 | /* 3990 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1884 | /* 3994 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 1885 | /* 3998 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 1886 | /* 4002 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 1887 | /* 4006 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1888 | /* 4010 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1889 | /* 4014 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 1890 | /* 4018 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 1891 | /* 4022 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 1892 | /* 4026 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1893 | /* 4031 */ // MIs[2] Operand 2 |
| 1894 | /* 4031 */ GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16), |
| 1895 | /* 4042 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] |
| 1896 | /* 4046 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 1897 | /* 4050 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 1898 | /* 4054 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1899 | /* 4059 */ // MIs[3] Operand 2 |
| 1900 | /* 4059 */ GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(16), |
| 1901 | /* 4070 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 1902 | /* 4072 */ // (add:{ *:[i32] } GPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } (sext_inreg:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, i16:{ *:[Other] }), (sext_inreg:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, i16:{ *:[Other] }))) => (SMLABB:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) |
| 1903 | /* 4072 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLABB), |
| 1904 | /* 4075 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1905 | /* 4077 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn |
| 1906 | /* 4081 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm |
| 1907 | /* 4085 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra |
| 1908 | /* 4087 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1909 | /* 4090 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1910 | /* 4096 */ GIR_RootConstrainSelectedInstOperands, |
| 1911 | /* 4097 */ // GIR_Coverage, 189, |
| 1912 | /* 4097 */ GIR_EraseRootFromParent_Done, |
| 1913 | /* 4098 */ // Label 119: @4098 |
| 1914 | /* 4098 */ GIM_Try, /*On fail goto*//*Label 120*/ GIMT_Encode4(4214), // Rule ID 518 // |
| 1915 | /* 4103 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2_UseMulOps), |
| 1916 | /* 4106 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1917 | /* 4110 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1918 | /* 4114 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 1919 | /* 4118 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 1920 | /* 4122 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1921 | /* 4126 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1922 | /* 4130 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 1923 | /* 4134 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 1924 | /* 4138 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 1925 | /* 4142 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1926 | /* 4147 */ // MIs[2] Operand 2 |
| 1927 | /* 4147 */ GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16), |
| 1928 | /* 4158 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] |
| 1929 | /* 4162 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 1930 | /* 4166 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 1931 | /* 4170 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1932 | /* 4175 */ // MIs[3] Operand 2 |
| 1933 | /* 4175 */ GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(16), |
| 1934 | /* 4186 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 1935 | /* 4188 */ // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, i16:{ *:[Other] }), (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, i16:{ *:[Other] }))) => (t2SMLABB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) |
| 1936 | /* 4188 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLABB), |
| 1937 | /* 4191 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1938 | /* 4193 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn |
| 1939 | /* 4197 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm |
| 1940 | /* 4201 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra |
| 1941 | /* 4203 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1942 | /* 4206 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1943 | /* 4212 */ GIR_RootConstrainSelectedInstOperands, |
| 1944 | /* 4213 */ // GIR_Coverage, 518, |
| 1945 | /* 4213 */ GIR_EraseRootFromParent_Done, |
| 1946 | /* 4214 */ // Label 120: @4214 |
| 1947 | /* 4214 */ GIM_Try, /*On fail goto*//*Label 121*/ GIMT_Encode4(4302), // Rule ID 3248 // |
| 1948 | /* 4219 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 1949 | /* 4222 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 1950 | /* 4226 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1951 | /* 4230 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_VECREDUCE_ADD), |
| 1952 | /* 4234 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 1953 | /* 4238 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 1954 | /* 4242 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_MUL), |
| 1955 | /* 4246 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, |
| 1956 | /* 4250 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32, |
| 1957 | /* 4254 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 1958 | /* 4259 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 1959 | /* 4264 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 1960 | /* 4268 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 1961 | /* 4270 */ // (add:{ *:[i32] } (vecreduce_add:{ *:[i32] } (mul:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src1, MQPR:{ *:[v4i32] }:$src2)), tGPREven:{ *:[i32] }:$src3) => (MVE_VMLADAVau32:{ *:[i32] } ?:{ *:[i32] }:$src3, ?:{ *:[v4i32] }:$src1, ?:{ *:[v4i32] }:$src2) |
| 1962 | /* 4270 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVau32), |
| 1963 | /* 4273 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 1964 | /* 4275 */ GIR_RootToRootCopy, /*OpIdx*/2, // src3 |
| 1965 | /* 4277 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1 |
| 1966 | /* 4281 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2 |
| 1967 | /* 4285 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 1968 | /* 4288 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1969 | /* 4294 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1970 | /* 4300 */ GIR_RootConstrainSelectedInstOperands, |
| 1971 | /* 4301 */ // GIR_Coverage, 3248, |
| 1972 | /* 4301 */ GIR_EraseRootFromParent_Done, |
| 1973 | /* 4302 */ // Label 121: @4302 |
| 1974 | /* 4302 */ GIM_Try, /*On fail goto*//*Label 122*/ GIMT_Encode4(4390), // Rule ID 3249 // |
| 1975 | /* 4307 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 1976 | /* 4310 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 1977 | /* 4314 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1978 | /* 4318 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_VECREDUCE_ADD), |
| 1979 | /* 4322 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 1980 | /* 4326 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 1981 | /* 4330 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_MUL), |
| 1982 | /* 4334 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, |
| 1983 | /* 4338 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s16, |
| 1984 | /* 4342 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 1985 | /* 4347 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 1986 | /* 4352 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 1987 | /* 4356 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 1988 | /* 4358 */ // (add:{ *:[i32] } (vecreduce_add:{ *:[i32] } (mul:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src1, MQPR:{ *:[v8i16] }:$src2)), tGPREven:{ *:[i32] }:$src3) => (MVE_VMLADAVau16:{ *:[i32] } ?:{ *:[i32] }:$src3, ?:{ *:[v8i16] }:$src1, ?:{ *:[v8i16] }:$src2) |
| 1989 | /* 4358 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVau16), |
| 1990 | /* 4361 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 1991 | /* 4363 */ GIR_RootToRootCopy, /*OpIdx*/2, // src3 |
| 1992 | /* 4365 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1 |
| 1993 | /* 4369 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2 |
| 1994 | /* 4373 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 1995 | /* 4376 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1996 | /* 4382 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1997 | /* 4388 */ GIR_RootConstrainSelectedInstOperands, |
| 1998 | /* 4389 */ // GIR_Coverage, 3249, |
| 1999 | /* 4389 */ GIR_EraseRootFromParent_Done, |
| 2000 | /* 4390 */ // Label 122: @4390 |
| 2001 | /* 4390 */ GIM_Try, /*On fail goto*//*Label 123*/ GIMT_Encode4(4478), // Rule ID 3252 // |
| 2002 | /* 4395 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 2003 | /* 4398 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 2004 | /* 4402 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2005 | /* 4406 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_VECREDUCE_ADD), |
| 2006 | /* 4410 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, |
| 2007 | /* 4414 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 2008 | /* 4418 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_MUL), |
| 2009 | /* 4422 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v16s8, |
| 2010 | /* 4426 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v16s8, |
| 2011 | /* 4430 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 2012 | /* 4435 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 2013 | /* 4440 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 2014 | /* 4444 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 2015 | /* 4446 */ // (add:{ *:[i32] } (vecreduce_add:{ *:[i32] } (mul:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$src1, MQPR:{ *:[v16i8] }:$src2)), tGPREven:{ *:[i32] }:$src3) => (MVE_VMLADAVau8:{ *:[i32] } ?:{ *:[i32] }:$src3, ?:{ *:[v16i8] }:$src1, ?:{ *:[v16i8] }:$src2) |
| 2016 | /* 4446 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVau8), |
| 2017 | /* 4449 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 2018 | /* 4451 */ GIR_RootToRootCopy, /*OpIdx*/2, // src3 |
| 2019 | /* 4453 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1 |
| 2020 | /* 4457 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2 |
| 2021 | /* 4461 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 2022 | /* 4464 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2023 | /* 4470 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2024 | /* 4476 */ GIR_RootConstrainSelectedInstOperands, |
| 2025 | /* 4477 */ // GIR_Coverage, 3252, |
| 2026 | /* 4477 */ GIR_EraseRootFromParent_Done, |
| 2027 | /* 4478 */ // Label 123: @4478 |
| 2028 | /* 4478 */ GIM_Try, /*On fail goto*//*Label 124*/ GIMT_Encode4(4566), // Rule ID 5950 // |
| 2029 | /* 4483 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 2030 | /* 4486 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 2031 | /* 4490 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 2032 | /* 4494 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2033 | /* 4498 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_VECREDUCE_ADD), |
| 2034 | /* 4502 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 2035 | /* 4506 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 2036 | /* 4510 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_MUL), |
| 2037 | /* 4514 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, |
| 2038 | /* 4518 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32, |
| 2039 | /* 4522 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 2040 | /* 4527 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 2041 | /* 4532 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 2042 | /* 4534 */ // (add:{ *:[i32] } tGPREven:{ *:[i32] }:$src3, (vecreduce_add:{ *:[i32] } (mul:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src1, MQPR:{ *:[v4i32] }:$src2))) => (MVE_VMLADAVau32:{ *:[i32] } ?:{ *:[i32] }:$src3, ?:{ *:[v4i32] }:$src1, ?:{ *:[v4i32] }:$src2) |
| 2043 | /* 4534 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVau32), |
| 2044 | /* 4537 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 2045 | /* 4539 */ GIR_RootToRootCopy, /*OpIdx*/1, // src3 |
| 2046 | /* 4541 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1 |
| 2047 | /* 4545 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2 |
| 2048 | /* 4549 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 2049 | /* 4552 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2050 | /* 4558 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2051 | /* 4564 */ GIR_RootConstrainSelectedInstOperands, |
| 2052 | /* 4565 */ // GIR_Coverage, 5950, |
| 2053 | /* 4565 */ GIR_EraseRootFromParent_Done, |
| 2054 | /* 4566 */ // Label 124: @4566 |
| 2055 | /* 4566 */ GIM_Try, /*On fail goto*//*Label 125*/ GIMT_Encode4(4654), // Rule ID 5951 // |
| 2056 | /* 4571 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 2057 | /* 4574 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 2058 | /* 4578 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 2059 | /* 4582 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2060 | /* 4586 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_VECREDUCE_ADD), |
| 2061 | /* 4590 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 2062 | /* 4594 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 2063 | /* 4598 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_MUL), |
| 2064 | /* 4602 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, |
| 2065 | /* 4606 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s16, |
| 2066 | /* 4610 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 2067 | /* 4615 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 2068 | /* 4620 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 2069 | /* 4622 */ // (add:{ *:[i32] } tGPREven:{ *:[i32] }:$src3, (vecreduce_add:{ *:[i32] } (mul:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src1, MQPR:{ *:[v8i16] }:$src2))) => (MVE_VMLADAVau16:{ *:[i32] } ?:{ *:[i32] }:$src3, ?:{ *:[v8i16] }:$src1, ?:{ *:[v8i16] }:$src2) |
| 2070 | /* 4622 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVau16), |
| 2071 | /* 4625 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 2072 | /* 4627 */ GIR_RootToRootCopy, /*OpIdx*/1, // src3 |
| 2073 | /* 4629 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1 |
| 2074 | /* 4633 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2 |
| 2075 | /* 4637 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 2076 | /* 4640 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2077 | /* 4646 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2078 | /* 4652 */ GIR_RootConstrainSelectedInstOperands, |
| 2079 | /* 4653 */ // GIR_Coverage, 5951, |
| 2080 | /* 4653 */ GIR_EraseRootFromParent_Done, |
| 2081 | /* 4654 */ // Label 125: @4654 |
| 2082 | /* 4654 */ GIM_Try, /*On fail goto*//*Label 126*/ GIMT_Encode4(4742), // Rule ID 5954 // |
| 2083 | /* 4659 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 2084 | /* 4662 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 2085 | /* 4666 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 2086 | /* 4670 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2087 | /* 4674 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_VECREDUCE_ADD), |
| 2088 | /* 4678 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, |
| 2089 | /* 4682 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 2090 | /* 4686 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_MUL), |
| 2091 | /* 4690 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v16s8, |
| 2092 | /* 4694 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v16s8, |
| 2093 | /* 4698 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 2094 | /* 4703 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 2095 | /* 4708 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 2096 | /* 4710 */ // (add:{ *:[i32] } tGPREven:{ *:[i32] }:$src3, (vecreduce_add:{ *:[i32] } (mul:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$src1, MQPR:{ *:[v16i8] }:$src2))) => (MVE_VMLADAVau8:{ *:[i32] } ?:{ *:[i32] }:$src3, ?:{ *:[v16i8] }:$src1, ?:{ *:[v16i8] }:$src2) |
| 2097 | /* 4710 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVau8), |
| 2098 | /* 4713 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 2099 | /* 4715 */ GIR_RootToRootCopy, /*OpIdx*/1, // src3 |
| 2100 | /* 4717 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1 |
| 2101 | /* 4721 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2 |
| 2102 | /* 4725 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 2103 | /* 4728 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2104 | /* 4734 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2105 | /* 4740 */ GIR_RootConstrainSelectedInstOperands, |
| 2106 | /* 4741 */ // GIR_Coverage, 5954, |
| 2107 | /* 4741 */ GIR_EraseRootFromParent_Done, |
| 2108 | /* 4742 */ // Label 126: @4742 |
| 2109 | /* 4742 */ GIM_Try, /*On fail goto*//*Label 127*/ GIMT_Encode4(4799), // Rule ID 72 // |
| 2110 | /* 4747 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 2111 | /* 4750 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 2112 | /* 4754 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 2113 | /* 4758 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2114 | /* 4762 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 2115 | /* 4766 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm), |
| 2116 | /* 4770 */ // MIs[1] Operand 1 |
| 2117 | /* 4770 */ // No operand predicates |
| 2118 | /* 4770 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2119 | /* 4772 */ // (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm) => (ADDri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 2120 | /* 4772 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::ADDri), |
| 2121 | /* 4775 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 2122 | /* 4777 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 2123 | /* 4779 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 2124 | /* 4782 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2125 | /* 4785 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2126 | /* 4791 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2127 | /* 4797 */ GIR_RootConstrainSelectedInstOperands, |
| 2128 | /* 4798 */ // GIR_Coverage, 72, |
| 2129 | /* 4798 */ GIR_EraseRootFromParent_Done, |
| 2130 | /* 4799 */ // Label 127: @4799 |
| 2131 | /* 4799 */ GIM_Try, /*On fail goto*//*Label 128*/ GIMT_Encode4(4856), // Rule ID 303 // |
| 2132 | /* 4804 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), |
| 2133 | /* 4807 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 2134 | /* 4811 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 2135 | /* 4815 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2136 | /* 4819 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 2137 | /* 4823 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_7), |
| 2138 | /* 4827 */ // MIs[1] Operand 1 |
| 2139 | /* 4827 */ // No operand predicates |
| 2140 | /* 4827 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2141 | /* 4829 */ // (add:{ *:[i32] } tGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_imm0_7>>:$imm3) => (tADDi3:{ *:[i32] } tGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$imm3) |
| 2142 | /* 4829 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tADDi3), |
| 2143 | /* 4832 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 2144 | /* 4834 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define | RegState::Dead), |
| 2145 | /* 4840 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 2146 | /* 4842 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm3 |
| 2147 | /* 4845 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2148 | /* 4848 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2149 | /* 4854 */ GIR_RootConstrainSelectedInstOperands, |
| 2150 | /* 4855 */ // GIR_Coverage, 303, |
| 2151 | /* 4855 */ GIR_EraseRootFromParent_Done, |
| 2152 | /* 4856 */ // Label 128: @4856 |
| 2153 | /* 4856 */ GIM_Try, /*On fail goto*//*Label 129*/ GIMT_Encode4(4913), // Rule ID 304 // |
| 2154 | /* 4861 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), |
| 2155 | /* 4864 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 2156 | /* 4868 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 2157 | /* 4872 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2158 | /* 4876 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 2159 | /* 4880 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_255_expr), |
| 2160 | /* 4884 */ // MIs[1] Operand 1 |
| 2161 | /* 4884 */ // No operand predicates |
| 2162 | /* 4884 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2163 | /* 4886 */ // (add:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_imm0_255_expr>>:$imm8) => (tADDi8:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm8) |
| 2164 | /* 4886 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tADDi8), |
| 2165 | /* 4889 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn] |
| 2166 | /* 4891 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define | RegState::Dead), |
| 2167 | /* 4897 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 2168 | /* 4899 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm8 |
| 2169 | /* 4902 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2170 | /* 4905 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2171 | /* 4911 */ GIR_RootConstrainSelectedInstOperands, |
| 2172 | /* 4912 */ // GIR_Coverage, 304, |
| 2173 | /* 4912 */ GIR_EraseRootFromParent_Done, |
| 2174 | /* 4913 */ // Label 129: @4913 |
| 2175 | /* 4913 */ GIM_Try, /*On fail goto*//*Label 130*/ GIMT_Encode4(4970), // Rule ID 407 // |
| 2176 | /* 4918 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 2177 | /* 4921 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2178 | /* 4925 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 2179 | /* 4929 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2180 | /* 4933 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 2181 | /* 4937 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm), |
| 2182 | /* 4941 */ // MIs[1] Operand 1 |
| 2183 | /* 4941 */ // No operand predicates |
| 2184 | /* 4941 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2185 | /* 4943 */ // (add:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm) => (t2ADDri:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 2186 | /* 4943 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ADDri), |
| 2187 | /* 4946 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 2188 | /* 4948 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 2189 | /* 4950 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 2190 | /* 4953 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2191 | /* 4956 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2192 | /* 4962 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2193 | /* 4968 */ GIR_RootConstrainSelectedInstOperands, |
| 2194 | /* 4969 */ // GIR_Coverage, 407, |
| 2195 | /* 4969 */ GIR_EraseRootFromParent_Done, |
| 2196 | /* 4970 */ // Label 130: @4970 |
| 2197 | /* 4970 */ GIM_Try, /*On fail goto*//*Label 131*/ GIMT_Encode4(5021), // Rule ID 408 // |
| 2198 | /* 4975 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 2199 | /* 4978 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2200 | /* 4982 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 2201 | /* 4986 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2202 | /* 4990 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 2203 | /* 4994 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_4095), |
| 2204 | /* 4998 */ // MIs[1] Operand 1 |
| 2205 | /* 4998 */ // No operand predicates |
| 2206 | /* 4998 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2207 | /* 5000 */ // (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_imm0_4095>>:$imm) => (t2ADDri12:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 2208 | /* 5000 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ADDri12), |
| 2209 | /* 5003 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 2210 | /* 5005 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 2211 | /* 5007 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 2212 | /* 5010 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2213 | /* 5013 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2214 | /* 5019 */ GIR_RootConstrainSelectedInstOperands, |
| 2215 | /* 5020 */ // GIR_Coverage, 408, |
| 2216 | /* 5020 */ GIR_EraseRootFromParent_Done, |
| 2217 | /* 5021 */ // Label 131: @5021 |
| 2218 | /* 5021 */ GIM_Try, /*On fail goto*//*Label 132*/ GIMT_Encode4(5097), // Rule ID 171 // |
| 2219 | /* 5026 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM_UseMulOps), |
| 2220 | /* 5029 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 2221 | /* 5033 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2222 | /* 5037 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 2223 | /* 5041 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 2224 | /* 5045 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 2225 | /* 5049 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 2226 | /* 5054 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 2227 | /* 5059 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 2228 | /* 5063 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2229 | /* 5065 */ // (add:{ *:[i32] } (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm), GPRnopc:{ *:[i32] }:$Ra) => (MLA:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra) |
| 2230 | /* 5065 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MLA), |
| 2231 | /* 5068 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 2232 | /* 5070 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 2233 | /* 5074 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm |
| 2234 | /* 5078 */ GIR_RootToRootCopy, /*OpIdx*/2, // Ra |
| 2235 | /* 5080 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2236 | /* 5083 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2237 | /* 5089 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2238 | /* 5095 */ GIR_RootConstrainSelectedInstOperands, |
| 2239 | /* 5096 */ // GIR_Coverage, 171, |
| 2240 | /* 5096 */ GIR_EraseRootFromParent_Done, |
| 2241 | /* 5097 */ // Label 132: @5097 |
| 2242 | /* 5097 */ GIM_Try, /*On fail goto*//*Label 133*/ GIMT_Encode4(5173), // Rule ID 172 // |
| 2243 | /* 5102 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM_NoV6), |
| 2244 | /* 5105 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 2245 | /* 5109 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2246 | /* 5113 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 2247 | /* 5117 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 2248 | /* 5121 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 2249 | /* 5125 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 2250 | /* 5130 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 2251 | /* 5135 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 2252 | /* 5139 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2253 | /* 5141 */ // (add:{ *:[i32] } (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm), GPRnopc:{ *:[i32] }:$Ra) => (MLAv5:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra) |
| 2254 | /* 5141 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MLAv5), |
| 2255 | /* 5144 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 2256 | /* 5146 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 2257 | /* 5150 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm |
| 2258 | /* 5154 */ GIR_RootToRootCopy, /*OpIdx*/2, // Ra |
| 2259 | /* 5156 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2260 | /* 5159 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2261 | /* 5165 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2262 | /* 5171 */ GIR_RootConstrainSelectedInstOperands, |
| 2263 | /* 5172 */ // GIR_Coverage, 172, |
| 2264 | /* 5172 */ GIR_EraseRootFromParent_Done, |
| 2265 | /* 5173 */ // Label 133: @5173 |
| 2266 | /* 5173 */ GIM_Try, /*On fail goto*//*Label 134*/ GIMT_Encode4(5243), // Rule ID 503 // |
| 2267 | /* 5178 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2_UseMulOps), |
| 2268 | /* 5181 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2269 | /* 5185 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2270 | /* 5189 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 2271 | /* 5193 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 2272 | /* 5197 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 2273 | /* 5201 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2274 | /* 5206 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2275 | /* 5211 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2276 | /* 5215 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2277 | /* 5217 */ // (add:{ *:[i32] } (mul:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm), rGPR:{ *:[i32] }:$Ra) => (t2MLA:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) |
| 2278 | /* 5217 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MLA), |
| 2279 | /* 5220 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 2280 | /* 5222 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 2281 | /* 5226 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm |
| 2282 | /* 5230 */ GIR_RootToRootCopy, /*OpIdx*/2, // Ra |
| 2283 | /* 5232 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2284 | /* 5235 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2285 | /* 5241 */ GIR_RootConstrainSelectedInstOperands, |
| 2286 | /* 5242 */ // GIR_Coverage, 503, |
| 2287 | /* 5242 */ GIR_EraseRootFromParent_Done, |
| 2288 | /* 5243 */ // Label 134: @5243 |
| 2289 | /* 5243 */ GIM_Try, /*On fail goto*//*Label 135*/ GIMT_Encode4(5314), // Rule ID 5672 // |
| 2290 | /* 5248 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 2291 | /* 5251 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 2292 | /* 5255 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2293 | /* 5259 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 2294 | /* 5263 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 2295 | /* 5267 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 2296 | /* 5272 */ // MIs[1] Operand 2 |
| 2297 | /* 5272 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(8), |
| 2298 | /* 5283 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 2299 | /* 5287 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2300 | /* 5289 */ // (add:{ *:[i32] } (sext_inreg:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, i8:{ *:[Other] }), GPR:{ *:[i32] }:$Rn) => (SXTAB:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, 0:{ *:[i32] }) |
| 2301 | /* 5289 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SXTAB), |
| 2302 | /* 5292 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 2303 | /* 5294 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 2304 | /* 5296 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 2305 | /* 5300 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 2306 | /* 5303 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2307 | /* 5306 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2308 | /* 5312 */ GIR_RootConstrainSelectedInstOperands, |
| 2309 | /* 5313 */ // GIR_Coverage, 5672, |
| 2310 | /* 5313 */ GIR_EraseRootFromParent_Done, |
| 2311 | /* 5314 */ // Label 135: @5314 |
| 2312 | /* 5314 */ GIM_Try, /*On fail goto*//*Label 136*/ GIMT_Encode4(5385), // Rule ID 5673 // |
| 2313 | /* 5319 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 2314 | /* 5322 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 2315 | /* 5326 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2316 | /* 5330 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 2317 | /* 5334 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 2318 | /* 5338 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 2319 | /* 5343 */ // MIs[1] Operand 2 |
| 2320 | /* 5343 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16), |
| 2321 | /* 5354 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 2322 | /* 5358 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2323 | /* 5360 */ // (add:{ *:[i32] } (sext_inreg:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, i16:{ *:[Other] }), GPR:{ *:[i32] }:$Rn) => (SXTAH:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, 0:{ *:[i32] }) |
| 2324 | /* 5360 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SXTAH), |
| 2325 | /* 5363 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 2326 | /* 5365 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 2327 | /* 5367 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 2328 | /* 5371 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 2329 | /* 5374 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2330 | /* 5377 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2331 | /* 5383 */ GIR_RootConstrainSelectedInstOperands, |
| 2332 | /* 5384 */ // GIR_Coverage, 5673, |
| 2333 | /* 5384 */ GIR_EraseRootFromParent_Done, |
| 2334 | /* 5385 */ // Label 136: @5385 |
| 2335 | /* 5385 */ GIM_Try, /*On fail goto*//*Label 137*/ GIMT_Encode4(5456), // Rule ID 5707 // |
| 2336 | /* 5390 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 2337 | /* 5393 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2338 | /* 5397 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2339 | /* 5401 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 2340 | /* 5405 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 2341 | /* 5409 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2342 | /* 5414 */ // MIs[1] Operand 2 |
| 2343 | /* 5414 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(8), |
| 2344 | /* 5425 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2345 | /* 5429 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2346 | /* 5431 */ // (add:{ *:[i32] } (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, i8:{ *:[Other] }), rGPR:{ *:[i32] }:$Rn) => (t2SXTAB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] }) |
| 2347 | /* 5431 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SXTAB), |
| 2348 | /* 5434 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 2349 | /* 5436 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 2350 | /* 5438 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 2351 | /* 5442 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 2352 | /* 5445 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2353 | /* 5448 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2354 | /* 5454 */ GIR_RootConstrainSelectedInstOperands, |
| 2355 | /* 5455 */ // GIR_Coverage, 5707, |
| 2356 | /* 5455 */ GIR_EraseRootFromParent_Done, |
| 2357 | /* 5456 */ // Label 137: @5456 |
| 2358 | /* 5456 */ GIM_Try, /*On fail goto*//*Label 138*/ GIMT_Encode4(5527), // Rule ID 5708 // |
| 2359 | /* 5461 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 2360 | /* 5464 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2361 | /* 5468 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2362 | /* 5472 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 2363 | /* 5476 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 2364 | /* 5480 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2365 | /* 5485 */ // MIs[1] Operand 2 |
| 2366 | /* 5485 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16), |
| 2367 | /* 5496 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2368 | /* 5500 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2369 | /* 5502 */ // (add:{ *:[i32] } (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, i16:{ *:[Other] }), rGPR:{ *:[i32] }:$Rn) => (t2SXTAH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] }) |
| 2370 | /* 5502 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SXTAH), |
| 2371 | /* 5505 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 2372 | /* 5507 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 2373 | /* 5509 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 2374 | /* 5513 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 2375 | /* 5516 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2376 | /* 5519 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2377 | /* 5525 */ GIR_RootConstrainSelectedInstOperands, |
| 2378 | /* 5526 */ // GIR_Coverage, 5708, |
| 2379 | /* 5526 */ GIR_EraseRootFromParent_Done, |
| 2380 | /* 5527 */ // Label 138: @5527 |
| 2381 | /* 5527 */ GIM_Try, /*On fail goto*//*Label 139*/ GIMT_Encode4(5597), // Rule ID 180 // |
| 2382 | /* 5532 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM_UseMulOps), |
| 2383 | /* 5535 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 2384 | /* 5539 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2385 | /* 5543 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMULH), |
| 2386 | /* 5547 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 2387 | /* 5551 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 2388 | /* 5555 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 2389 | /* 5560 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 2390 | /* 5565 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 2391 | /* 5569 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2392 | /* 5571 */ // (add:{ *:[i32] } (mulhs:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm), GPR:{ *:[i32] }:$Ra) => (SMMLA:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) |
| 2393 | /* 5571 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMMLA), |
| 2394 | /* 5574 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 2395 | /* 5576 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 2396 | /* 5580 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm |
| 2397 | /* 5584 */ GIR_RootToRootCopy, /*OpIdx*/2, // Ra |
| 2398 | /* 5586 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2399 | /* 5589 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2400 | /* 5595 */ GIR_RootConstrainSelectedInstOperands, |
| 2401 | /* 5596 */ // GIR_Coverage, 180, |
| 2402 | /* 5596 */ GIR_EraseRootFromParent_Done, |
| 2403 | /* 5597 */ // Label 139: @5597 |
| 2404 | /* 5597 */ GIM_Try, /*On fail goto*//*Label 140*/ GIMT_Encode4(5667), // Rule ID 509 // |
| 2405 | /* 5602 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2_UseMulOps), |
| 2406 | /* 5605 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2407 | /* 5609 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2408 | /* 5613 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMULH), |
| 2409 | /* 5617 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 2410 | /* 5621 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 2411 | /* 5625 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2412 | /* 5630 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2413 | /* 5635 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2414 | /* 5639 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2415 | /* 5641 */ // (add:{ *:[i32] } (mulhs:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn), rGPR:{ *:[i32] }:$Ra) => (t2SMMLA:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) |
| 2416 | /* 5641 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMMLA), |
| 2417 | /* 5644 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 2418 | /* 5646 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 2419 | /* 5650 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 2420 | /* 5654 */ GIR_RootToRootCopy, /*OpIdx*/2, // Ra |
| 2421 | /* 5656 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2422 | /* 5659 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2423 | /* 5665 */ GIR_RootConstrainSelectedInstOperands, |
| 2424 | /* 5666 */ // GIR_Coverage, 509, |
| 2425 | /* 5666 */ GIR_EraseRootFromParent_Done, |
| 2426 | /* 5667 */ // Label 140: @5667 |
| 2427 | /* 5667 */ GIM_Try, /*On fail goto*//*Label 141*/ GIMT_Encode4(5730), // Rule ID 3053 // |
| 2428 | /* 5672 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 2429 | /* 5675 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 2430 | /* 5679 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2431 | /* 5683 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_VECREDUCE_ADD), |
| 2432 | /* 5687 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, |
| 2433 | /* 5691 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 2434 | /* 5696 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 2435 | /* 5700 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2436 | /* 5702 */ // (add:{ *:[i32] } (vecreduce_add:{ *:[i32] } MQPR:{ *:[v16i8] }:$vec), tGPREven:{ *:[i32] }:$acc) => (MVE_VADDVu8acc:{ *:[i32] } ?:{ *:[i32] }:$acc, ?:{ *:[v16i8] }:$vec) |
| 2437 | /* 5702 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDVu8acc), |
| 2438 | /* 5705 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda] |
| 2439 | /* 5707 */ GIR_RootToRootCopy, /*OpIdx*/2, // acc |
| 2440 | /* 5709 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vec |
| 2441 | /* 5713 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 2442 | /* 5716 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2443 | /* 5722 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2444 | /* 5728 */ GIR_RootConstrainSelectedInstOperands, |
| 2445 | /* 5729 */ // GIR_Coverage, 3053, |
| 2446 | /* 5729 */ GIR_EraseRootFromParent_Done, |
| 2447 | /* 5730 */ // Label 141: @5730 |
| 2448 | /* 5730 */ GIM_Try, /*On fail goto*//*Label 142*/ GIMT_Encode4(5793), // Rule ID 3081 // |
| 2449 | /* 5735 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 2450 | /* 5738 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 2451 | /* 5742 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2452 | /* 5746 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_VECREDUCE_ADD), |
| 2453 | /* 5750 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 2454 | /* 5754 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 2455 | /* 5759 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 2456 | /* 5763 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2457 | /* 5765 */ // (add:{ *:[i32] } (vecreduce_add:{ *:[i32] } MQPR:{ *:[v8i16] }:$vec), tGPREven:{ *:[i32] }:$acc) => (MVE_VADDVu16acc:{ *:[i32] } ?:{ *:[i32] }:$acc, ?:{ *:[v8i16] }:$vec) |
| 2458 | /* 5765 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDVu16acc), |
| 2459 | /* 5768 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda] |
| 2460 | /* 5770 */ GIR_RootToRootCopy, /*OpIdx*/2, // acc |
| 2461 | /* 5772 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vec |
| 2462 | /* 5776 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 2463 | /* 5779 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2464 | /* 5785 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2465 | /* 5791 */ GIR_RootConstrainSelectedInstOperands, |
| 2466 | /* 5792 */ // GIR_Coverage, 3081, |
| 2467 | /* 5792 */ GIR_EraseRootFromParent_Done, |
| 2468 | /* 5793 */ // Label 142: @5793 |
| 2469 | /* 5793 */ GIM_Try, /*On fail goto*//*Label 143*/ GIMT_Encode4(5856), // Rule ID 3091 // |
| 2470 | /* 5798 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 2471 | /* 5801 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 2472 | /* 5805 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2473 | /* 5809 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_VECREDUCE_ADD), |
| 2474 | /* 5813 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 2475 | /* 5817 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 2476 | /* 5822 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 2477 | /* 5826 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2478 | /* 5828 */ // (add:{ *:[i32] } (vecreduce_add:{ *:[i32] } MQPR:{ *:[v4i32] }:$vec), tGPREven:{ *:[i32] }:$acc) => (MVE_VADDVu32acc:{ *:[i32] } ?:{ *:[i32] }:$acc, ?:{ *:[v4i32] }:$vec) |
| 2479 | /* 5828 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDVu32acc), |
| 2480 | /* 5831 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda] |
| 2481 | /* 5833 */ GIR_RootToRootCopy, /*OpIdx*/2, // acc |
| 2482 | /* 5835 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vec |
| 2483 | /* 5839 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 2484 | /* 5842 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2485 | /* 5848 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2486 | /* 5854 */ GIR_RootConstrainSelectedInstOperands, |
| 2487 | /* 5855 */ // GIR_Coverage, 3091, |
| 2488 | /* 5855 */ GIR_EraseRootFromParent_Done, |
| 2489 | /* 5856 */ // Label 143: @5856 |
| 2490 | /* 5856 */ GIM_Try, /*On fail goto*//*Label 144*/ GIMT_Encode4(5932), // Rule ID 5443 // |
| 2491 | /* 5861 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM_UseMulOps), |
| 2492 | /* 5864 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 2493 | /* 5868 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 2494 | /* 5872 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2495 | /* 5876 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 2496 | /* 5880 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 2497 | /* 5884 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 2498 | /* 5888 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 2499 | /* 5893 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 2500 | /* 5898 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2501 | /* 5900 */ // (add:{ *:[i32] } GPRnopc:{ *:[i32] }:$Ra, (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)) => (MLA:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra) |
| 2502 | /* 5900 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MLA), |
| 2503 | /* 5903 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 2504 | /* 5905 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 2505 | /* 5909 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm |
| 2506 | /* 5913 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra |
| 2507 | /* 5915 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2508 | /* 5918 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2509 | /* 5924 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2510 | /* 5930 */ GIR_RootConstrainSelectedInstOperands, |
| 2511 | /* 5931 */ // GIR_Coverage, 5443, |
| 2512 | /* 5931 */ GIR_EraseRootFromParent_Done, |
| 2513 | /* 5932 */ // Label 144: @5932 |
| 2514 | /* 5932 */ GIM_Try, /*On fail goto*//*Label 145*/ GIMT_Encode4(6008), // Rule ID 5444 // |
| 2515 | /* 5937 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM_NoV6), |
| 2516 | /* 5940 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 2517 | /* 5944 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 2518 | /* 5948 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2519 | /* 5952 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 2520 | /* 5956 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 2521 | /* 5960 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 2522 | /* 5964 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 2523 | /* 5969 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 2524 | /* 5974 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2525 | /* 5976 */ // (add:{ *:[i32] } GPRnopc:{ *:[i32] }:$Ra, (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)) => (MLAv5:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra) |
| 2526 | /* 5976 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MLAv5), |
| 2527 | /* 5979 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 2528 | /* 5981 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 2529 | /* 5985 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm |
| 2530 | /* 5989 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra |
| 2531 | /* 5991 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2532 | /* 5994 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2533 | /* 6000 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2534 | /* 6006 */ GIR_RootConstrainSelectedInstOperands, |
| 2535 | /* 6007 */ // GIR_Coverage, 5444, |
| 2536 | /* 6007 */ GIR_EraseRootFromParent_Done, |
| 2537 | /* 6008 */ // Label 145: @6008 |
| 2538 | /* 6008 */ GIM_Try, /*On fail goto*//*Label 146*/ GIMT_Encode4(6078), // Rule ID 5481 // |
| 2539 | /* 6013 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2_UseMulOps), |
| 2540 | /* 6016 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2541 | /* 6020 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2542 | /* 6024 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2543 | /* 6028 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 2544 | /* 6032 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 2545 | /* 6036 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 2546 | /* 6040 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2547 | /* 6045 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2548 | /* 6050 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2549 | /* 6052 */ // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)) => (t2MLA:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) |
| 2550 | /* 6052 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MLA), |
| 2551 | /* 6055 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 2552 | /* 6057 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 2553 | /* 6061 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm |
| 2554 | /* 6065 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra |
| 2555 | /* 6067 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2556 | /* 6070 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2557 | /* 6076 */ GIR_RootConstrainSelectedInstOperands, |
| 2558 | /* 6077 */ // GIR_Coverage, 5481, |
| 2559 | /* 6077 */ GIR_EraseRootFromParent_Done, |
| 2560 | /* 6078 */ // Label 146: @6078 |
| 2561 | /* 6078 */ GIM_Try, /*On fail goto*//*Label 147*/ GIMT_Encode4(6149), // Rule ID 2004 // |
| 2562 | /* 6083 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 2563 | /* 6086 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 2564 | /* 6090 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 2565 | /* 6094 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2566 | /* 6098 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 2567 | /* 6102 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 2568 | /* 6106 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 2569 | /* 6111 */ // MIs[1] Operand 2 |
| 2570 | /* 6111 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(8), |
| 2571 | /* 6122 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2572 | /* 6124 */ // (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (sext_inreg:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, i8:{ *:[Other] })) => (SXTAB:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, 0:{ *:[i32] }) |
| 2573 | /* 6124 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SXTAB), |
| 2574 | /* 6127 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 2575 | /* 6129 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 2576 | /* 6131 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 2577 | /* 6135 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 2578 | /* 6138 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2579 | /* 6141 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2580 | /* 6147 */ GIR_RootConstrainSelectedInstOperands, |
| 2581 | /* 6148 */ // GIR_Coverage, 2004, |
| 2582 | /* 6148 */ GIR_EraseRootFromParent_Done, |
| 2583 | /* 6149 */ // Label 147: @6149 |
| 2584 | /* 6149 */ GIM_Try, /*On fail goto*//*Label 148*/ GIMT_Encode4(6220), // Rule ID 2005 // |
| 2585 | /* 6154 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 2586 | /* 6157 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 2587 | /* 6161 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 2588 | /* 6165 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2589 | /* 6169 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 2590 | /* 6173 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 2591 | /* 6177 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 2592 | /* 6182 */ // MIs[1] Operand 2 |
| 2593 | /* 6182 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16), |
| 2594 | /* 6193 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2595 | /* 6195 */ // (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (sext_inreg:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, i16:{ *:[Other] })) => (SXTAH:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, 0:{ *:[i32] }) |
| 2596 | /* 6195 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SXTAH), |
| 2597 | /* 6198 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 2598 | /* 6200 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 2599 | /* 6202 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 2600 | /* 6206 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 2601 | /* 6209 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2602 | /* 6212 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2603 | /* 6218 */ GIR_RootConstrainSelectedInstOperands, |
| 2604 | /* 6219 */ // GIR_Coverage, 2005, |
| 2605 | /* 6219 */ GIR_EraseRootFromParent_Done, |
| 2606 | /* 6220 */ // Label 148: @6220 |
| 2607 | /* 6220 */ GIM_Try, /*On fail goto*//*Label 149*/ GIMT_Encode4(6291), // Rule ID 2243 // |
| 2608 | /* 6225 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 2609 | /* 6228 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2610 | /* 6232 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2611 | /* 6236 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2612 | /* 6240 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 2613 | /* 6244 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 2614 | /* 6248 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2615 | /* 6253 */ // MIs[1] Operand 2 |
| 2616 | /* 6253 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(8), |
| 2617 | /* 6264 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2618 | /* 6266 */ // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, i8:{ *:[Other] })) => (t2SXTAB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] }) |
| 2619 | /* 6266 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SXTAB), |
| 2620 | /* 6269 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 2621 | /* 6271 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 2622 | /* 6273 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 2623 | /* 6277 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 2624 | /* 6280 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2625 | /* 6283 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2626 | /* 6289 */ GIR_RootConstrainSelectedInstOperands, |
| 2627 | /* 6290 */ // GIR_Coverage, 2243, |
| 2628 | /* 6290 */ GIR_EraseRootFromParent_Done, |
| 2629 | /* 6291 */ // Label 149: @6291 |
| 2630 | /* 6291 */ GIM_Try, /*On fail goto*//*Label 150*/ GIMT_Encode4(6362), // Rule ID 2244 // |
| 2631 | /* 6296 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 2632 | /* 6299 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2633 | /* 6303 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2634 | /* 6307 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2635 | /* 6311 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 2636 | /* 6315 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 2637 | /* 6319 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2638 | /* 6324 */ // MIs[1] Operand 2 |
| 2639 | /* 6324 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16), |
| 2640 | /* 6335 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2641 | /* 6337 */ // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, i16:{ *:[Other] })) => (t2SXTAH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] }) |
| 2642 | /* 6337 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SXTAH), |
| 2643 | /* 6340 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 2644 | /* 6342 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 2645 | /* 6344 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 2646 | /* 6348 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 2647 | /* 6351 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2648 | /* 6354 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2649 | /* 6360 */ GIR_RootConstrainSelectedInstOperands, |
| 2650 | /* 6361 */ // GIR_Coverage, 2244, |
| 2651 | /* 6361 */ GIR_EraseRootFromParent_Done, |
| 2652 | /* 6362 */ // Label 150: @6362 |
| 2653 | /* 6362 */ GIM_Try, /*On fail goto*//*Label 151*/ GIMT_Encode4(6432), // Rule ID 5445 // |
| 2654 | /* 6367 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM_UseMulOps), |
| 2655 | /* 6370 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 2656 | /* 6374 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 2657 | /* 6378 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2658 | /* 6382 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMULH), |
| 2659 | /* 6386 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 2660 | /* 6390 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 2661 | /* 6394 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 2662 | /* 6399 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 2663 | /* 6404 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2664 | /* 6406 */ // (add:{ *:[i32] } GPR:{ *:[i32] }:$Ra, (mulhs:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)) => (SMMLA:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) |
| 2665 | /* 6406 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMMLA), |
| 2666 | /* 6409 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 2667 | /* 6411 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 2668 | /* 6415 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm |
| 2669 | /* 6419 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra |
| 2670 | /* 6421 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2671 | /* 6424 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2672 | /* 6430 */ GIR_RootConstrainSelectedInstOperands, |
| 2673 | /* 6431 */ // GIR_Coverage, 5445, |
| 2674 | /* 6431 */ GIR_EraseRootFromParent_Done, |
| 2675 | /* 6432 */ // Label 151: @6432 |
| 2676 | /* 6432 */ GIM_Try, /*On fail goto*//*Label 152*/ GIMT_Encode4(6502), // Rule ID 5482 // |
| 2677 | /* 6437 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2_UseMulOps), |
| 2678 | /* 6440 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2679 | /* 6444 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2680 | /* 6448 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2681 | /* 6452 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMULH), |
| 2682 | /* 6456 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 2683 | /* 6460 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 2684 | /* 6464 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2685 | /* 6469 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2686 | /* 6474 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2687 | /* 6476 */ // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Ra, (mulhs:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)) => (t2SMMLA:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) |
| 2688 | /* 6476 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMMLA), |
| 2689 | /* 6479 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 2690 | /* 6481 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 2691 | /* 6485 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 2692 | /* 6489 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra |
| 2693 | /* 6491 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2694 | /* 6494 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2695 | /* 6500 */ GIR_RootConstrainSelectedInstOperands, |
| 2696 | /* 6501 */ // GIR_Coverage, 5482, |
| 2697 | /* 6501 */ GIR_EraseRootFromParent_Done, |
| 2698 | /* 6502 */ // Label 152: @6502 |
| 2699 | /* 6502 */ GIM_Try, /*On fail goto*//*Label 153*/ GIMT_Encode4(6565), // Rule ID 5926 // |
| 2700 | /* 6507 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 2701 | /* 6510 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 2702 | /* 6514 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 2703 | /* 6518 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2704 | /* 6522 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_VECREDUCE_ADD), |
| 2705 | /* 6526 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, |
| 2706 | /* 6530 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 2707 | /* 6535 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2708 | /* 6537 */ // (add:{ *:[i32] } tGPREven:{ *:[i32] }:$acc, (vecreduce_add:{ *:[i32] } MQPR:{ *:[v16i8] }:$vec)) => (MVE_VADDVu8acc:{ *:[i32] } ?:{ *:[i32] }:$acc, ?:{ *:[v16i8] }:$vec) |
| 2709 | /* 6537 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDVu8acc), |
| 2710 | /* 6540 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda] |
| 2711 | /* 6542 */ GIR_RootToRootCopy, /*OpIdx*/1, // acc |
| 2712 | /* 6544 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vec |
| 2713 | /* 6548 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 2714 | /* 6551 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2715 | /* 6557 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2716 | /* 6563 */ GIR_RootConstrainSelectedInstOperands, |
| 2717 | /* 6564 */ // GIR_Coverage, 5926, |
| 2718 | /* 6564 */ GIR_EraseRootFromParent_Done, |
| 2719 | /* 6565 */ // Label 153: @6565 |
| 2720 | /* 6565 */ GIM_Try, /*On fail goto*//*Label 154*/ GIMT_Encode4(6628), // Rule ID 5940 // |
| 2721 | /* 6570 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 2722 | /* 6573 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 2723 | /* 6577 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 2724 | /* 6581 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2725 | /* 6585 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_VECREDUCE_ADD), |
| 2726 | /* 6589 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 2727 | /* 6593 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 2728 | /* 6598 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2729 | /* 6600 */ // (add:{ *:[i32] } tGPREven:{ *:[i32] }:$acc, (vecreduce_add:{ *:[i32] } MQPR:{ *:[v8i16] }:$vec)) => (MVE_VADDVu16acc:{ *:[i32] } ?:{ *:[i32] }:$acc, ?:{ *:[v8i16] }:$vec) |
| 2730 | /* 6600 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDVu16acc), |
| 2731 | /* 6603 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda] |
| 2732 | /* 6605 */ GIR_RootToRootCopy, /*OpIdx*/1, // acc |
| 2733 | /* 6607 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vec |
| 2734 | /* 6611 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 2735 | /* 6614 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2736 | /* 6620 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2737 | /* 6626 */ GIR_RootConstrainSelectedInstOperands, |
| 2738 | /* 6627 */ // GIR_Coverage, 5940, |
| 2739 | /* 6627 */ GIR_EraseRootFromParent_Done, |
| 2740 | /* 6628 */ // Label 154: @6628 |
| 2741 | /* 6628 */ GIM_Try, /*On fail goto*//*Label 155*/ GIMT_Encode4(6691), // Rule ID 5945 // |
| 2742 | /* 6633 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 2743 | /* 6636 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 2744 | /* 6640 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 2745 | /* 6644 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2746 | /* 6648 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_VECREDUCE_ADD), |
| 2747 | /* 6652 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 2748 | /* 6656 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 2749 | /* 6661 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2750 | /* 6663 */ // (add:{ *:[i32] } tGPREven:{ *:[i32] }:$acc, (vecreduce_add:{ *:[i32] } MQPR:{ *:[v4i32] }:$vec)) => (MVE_VADDVu32acc:{ *:[i32] } ?:{ *:[i32] }:$acc, ?:{ *:[v4i32] }:$vec) |
| 2751 | /* 6663 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDVu32acc), |
| 2752 | /* 6666 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda] |
| 2753 | /* 6668 */ GIR_RootToRootCopy, /*OpIdx*/1, // acc |
| 2754 | /* 6670 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vec |
| 2755 | /* 6674 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 2756 | /* 6677 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2757 | /* 6683 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2758 | /* 6689 */ GIR_RootConstrainSelectedInstOperands, |
| 2759 | /* 6690 */ // GIR_Coverage, 5945, |
| 2760 | /* 6690 */ GIR_EraseRootFromParent_Done, |
| 2761 | /* 6691 */ // Label 155: @6691 |
| 2762 | /* 6691 */ GIM_Try, /*On fail goto*//*Label 156*/ GIMT_Encode4(6737), // Rule ID 73 // |
| 2763 | /* 6696 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 2764 | /* 6699 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 2765 | /* 6703 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 2766 | /* 6707 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 2767 | /* 6711 */ // (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (ADDrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) |
| 2768 | /* 6711 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::ADDrr), |
| 2769 | /* 6714 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 2770 | /* 6716 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 2771 | /* 6718 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 2772 | /* 6720 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2773 | /* 6723 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2774 | /* 6729 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2775 | /* 6735 */ GIR_RootConstrainSelectedInstOperands, |
| 2776 | /* 6736 */ // GIR_Coverage, 73, |
| 2777 | /* 6736 */ GIR_EraseRootFromParent_Done, |
| 2778 | /* 6737 */ // Label 156: @6737 |
| 2779 | /* 6737 */ GIM_Try, /*On fail goto*//*Label 157*/ GIMT_Encode4(6783), // Rule ID 305 // |
| 2780 | /* 6742 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), |
| 2781 | /* 6745 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 2782 | /* 6749 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 2783 | /* 6753 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 2784 | /* 6757 */ // (add:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) => (tADDrr:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) |
| 2785 | /* 6757 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tADDrr), |
| 2786 | /* 6760 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 2787 | /* 6762 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define | RegState::Dead), |
| 2788 | /* 6768 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 2789 | /* 6770 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 2790 | /* 6772 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2791 | /* 6775 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2792 | /* 6781 */ GIR_RootConstrainSelectedInstOperands, |
| 2793 | /* 6782 */ // GIR_Coverage, 305, |
| 2794 | /* 6782 */ GIR_EraseRootFromParent_Done, |
| 2795 | /* 6783 */ // Label 157: @6783 |
| 2796 | /* 6783 */ GIM_Try, /*On fail goto*//*Label 158*/ GIMT_Encode4(6829), // Rule ID 409 // |
| 2797 | /* 6788 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 2798 | /* 6791 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 2799 | /* 6795 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 2800 | /* 6799 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2801 | /* 6803 */ // (add:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2ADDrr:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 2802 | /* 6803 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ADDrr), |
| 2803 | /* 6806 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 2804 | /* 6808 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 2805 | /* 6810 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 2806 | /* 6812 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2807 | /* 6815 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2808 | /* 6821 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2809 | /* 6827 */ GIR_RootConstrainSelectedInstOperands, |
| 2810 | /* 6828 */ // GIR_Coverage, 409, |
| 2811 | /* 6828 */ GIR_EraseRootFromParent_Done, |
| 2812 | /* 6829 */ // Label 158: @6829 |
| 2813 | /* 6829 */ GIM_Try, /*On fail goto*//*Label 159*/ GIMT_Encode4(6875), // Rule ID 5463 // |
| 2814 | /* 6834 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 2815 | /* 6837 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 2816 | /* 6841 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2817 | /* 6845 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 2818 | /* 6849 */ // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn) => (t2ADDrr:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 2819 | /* 6849 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ADDrr), |
| 2820 | /* 6852 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 2821 | /* 6854 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 2822 | /* 6856 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 2823 | /* 6858 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2824 | /* 6861 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2825 | /* 6867 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2826 | /* 6873 */ GIR_RootConstrainSelectedInstOperands, |
| 2827 | /* 6874 */ // GIR_Coverage, 5463, |
| 2828 | /* 6874 */ GIR_EraseRootFromParent_Done, |
| 2829 | /* 6875 */ // Label 159: @6875 |
| 2830 | /* 6875 */ GIM_Reject, |
| 2831 | /* 6876 */ // Label 90: @6876 |
| 2832 | /* 6876 */ GIM_Reject, |
| 2833 | /* 6877 */ // Label 81: @6877 |
| 2834 | /* 6877 */ GIM_Try, /*On fail goto*//*Label 160*/ GIMT_Encode4(6923), // Rule ID 762 // |
| 2835 | /* 6882 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 2836 | /* 6885 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 2837 | /* 6888 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 2838 | /* 6891 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2839 | /* 6895 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2840 | /* 6899 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2841 | /* 6903 */ // (add:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) => (VADDv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) |
| 2842 | /* 6903 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDv1i64), |
| 2843 | /* 6906 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 2844 | /* 6908 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 2845 | /* 6910 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 2846 | /* 6912 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2847 | /* 6915 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2848 | /* 6921 */ GIR_RootConstrainSelectedInstOperands, |
| 2849 | /* 6922 */ // GIR_Coverage, 762, |
| 2850 | /* 6922 */ GIR_EraseRootFromParent_Done, |
| 2851 | /* 6923 */ // Label 160: @6923 |
| 2852 | /* 6923 */ GIM_Reject, |
| 2853 | /* 6924 */ // Label 82: @6924 |
| 2854 | /* 6924 */ GIM_Try, /*On fail goto*//*Label 161*/ GIMT_Encode4(7108), |
| 2855 | /* 6929 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 2856 | /* 6932 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 2857 | /* 6935 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2858 | /* 6939 */ GIM_Try, /*On fail goto*//*Label 162*/ GIMT_Encode4(7005), // Rule ID 5532 // |
| 2859 | /* 6944 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 2860 | /* 6947 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2861 | /* 6951 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 2862 | /* 6955 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 2863 | /* 6959 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, |
| 2864 | /* 6963 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2865 | /* 6968 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2866 | /* 6973 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2867 | /* 6977 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2868 | /* 6979 */ // (add:{ *:[v2i32] } (mul:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm), DPR:{ *:[v2i32] }:$src1) => (VMLAv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 2869 | /* 6979 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv2i32), |
| 2870 | /* 6982 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 2871 | /* 6984 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 2872 | /* 6986 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 2873 | /* 6990 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 2874 | /* 6994 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2875 | /* 6997 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2876 | /* 7003 */ GIR_RootConstrainSelectedInstOperands, |
| 2877 | /* 7004 */ // GIR_Coverage, 5532, |
| 2878 | /* 7004 */ GIR_EraseRootFromParent_Done, |
| 2879 | /* 7005 */ // Label 162: @7005 |
| 2880 | /* 7005 */ GIM_Try, /*On fail goto*//*Label 163*/ GIMT_Encode4(7071), // Rule ID 889 // |
| 2881 | /* 7010 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 2882 | /* 7013 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2883 | /* 7017 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2884 | /* 7021 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 2885 | /* 7025 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 2886 | /* 7029 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, |
| 2887 | /* 7033 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2888 | /* 7038 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2889 | /* 7043 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2890 | /* 7045 */ // (add:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, (mul:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)) => (VMLAv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 2891 | /* 7045 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv2i32), |
| 2892 | /* 7048 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 2893 | /* 7050 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 2894 | /* 7052 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 2895 | /* 7056 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 2896 | /* 7060 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2897 | /* 7063 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2898 | /* 7069 */ GIR_RootConstrainSelectedInstOperands, |
| 2899 | /* 7070 */ // GIR_Coverage, 889, |
| 2900 | /* 7070 */ GIR_EraseRootFromParent_Done, |
| 2901 | /* 7071 */ // Label 163: @7071 |
| 2902 | /* 7071 */ GIM_Try, /*On fail goto*//*Label 164*/ GIMT_Encode4(7107), // Rule ID 758 // |
| 2903 | /* 7076 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 2904 | /* 7079 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2905 | /* 7083 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2906 | /* 7087 */ // (add:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VADDv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 2907 | /* 7087 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDv2i32), |
| 2908 | /* 7090 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 2909 | /* 7092 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 2910 | /* 7094 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 2911 | /* 7096 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2912 | /* 7099 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2913 | /* 7105 */ GIR_RootConstrainSelectedInstOperands, |
| 2914 | /* 7106 */ // GIR_Coverage, 758, |
| 2915 | /* 7106 */ GIR_EraseRootFromParent_Done, |
| 2916 | /* 7107 */ // Label 164: @7107 |
| 2917 | /* 7107 */ GIM_Reject, |
| 2918 | /* 7108 */ // Label 161: @7108 |
| 2919 | /* 7108 */ GIM_Reject, |
| 2920 | /* 7109 */ // Label 83: @7109 |
| 2921 | /* 7109 */ GIM_Try, /*On fail goto*//*Label 165*/ GIMT_Encode4(7819), |
| 2922 | /* 7114 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 2923 | /* 7117 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 2924 | /* 7120 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 2925 | /* 7124 */ GIM_Try, /*On fail goto*//*Label 166*/ GIMT_Encode4(7192), // Rule ID 782 // |
| 2926 | /* 7129 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 2927 | /* 7132 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2928 | /* 7136 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 2929 | /* 7140 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 2930 | /* 7144 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2931 | /* 7149 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 2932 | /* 7153 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 2933 | /* 7157 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, |
| 2934 | /* 7161 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2935 | /* 7166 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 2936 | /* 7168 */ // (add:{ *:[v2i64] } (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VADDLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 2937 | /* 7168 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv2i64), |
| 2938 | /* 7171 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 2939 | /* 7173 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 2940 | /* 7177 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 2941 | /* 7181 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2942 | /* 7184 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2943 | /* 7190 */ GIR_RootConstrainSelectedInstOperands, |
| 2944 | /* 7191 */ // GIR_Coverage, 782, |
| 2945 | /* 7191 */ GIR_EraseRootFromParent_Done, |
| 2946 | /* 7192 */ // Label 166: @7192 |
| 2947 | /* 7192 */ GIM_Try, /*On fail goto*//*Label 167*/ GIMT_Encode4(7260), // Rule ID 781 // |
| 2948 | /* 7197 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 2949 | /* 7200 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2950 | /* 7204 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 2951 | /* 7208 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 2952 | /* 7212 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2953 | /* 7217 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 2954 | /* 7221 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 2955 | /* 7225 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, |
| 2956 | /* 7229 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2957 | /* 7234 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 2958 | /* 7236 */ // (add:{ *:[v2i64] } (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VADDLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 2959 | /* 7236 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv2i64), |
| 2960 | /* 7239 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 2961 | /* 7241 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 2962 | /* 7245 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 2963 | /* 7249 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2964 | /* 7252 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2965 | /* 7258 */ GIR_RootConstrainSelectedInstOperands, |
| 2966 | /* 7259 */ // GIR_Coverage, 781, |
| 2967 | /* 7259 */ GIR_EraseRootFromParent_Done, |
| 2968 | /* 7260 */ // Label 167: @7260 |
| 2969 | /* 7260 */ GIM_Try, /*On fail goto*//*Label 168*/ GIMT_Encode4(7328), // Rule ID 770 // |
| 2970 | /* 7265 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 2971 | /* 7268 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2972 | /* 7272 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT), |
| 2973 | /* 7276 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 2974 | /* 7280 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2975 | /* 7285 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 2976 | /* 7289 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT), |
| 2977 | /* 7293 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, |
| 2978 | /* 7297 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2979 | /* 7302 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 2980 | /* 7304 */ // (add:{ *:[v2i64] } (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VADDLsv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 2981 | /* 7304 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLsv2i64), |
| 2982 | /* 7307 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 2983 | /* 7309 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 2984 | /* 7313 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 2985 | /* 7317 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2986 | /* 7320 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2987 | /* 7326 */ GIR_RootConstrainSelectedInstOperands, |
| 2988 | /* 7327 */ // GIR_Coverage, 770, |
| 2989 | /* 7327 */ GIR_EraseRootFromParent_Done, |
| 2990 | /* 7328 */ // Label 168: @7328 |
| 2991 | /* 7328 */ GIM_Try, /*On fail goto*//*Label 169*/ GIMT_Encode4(7396), // Rule ID 780 // |
| 2992 | /* 7333 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 2993 | /* 7336 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2994 | /* 7340 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 2995 | /* 7344 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 2996 | /* 7348 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2997 | /* 7353 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 2998 | /* 7357 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 2999 | /* 7361 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, |
| 3000 | /* 7365 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3001 | /* 7370 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 3002 | /* 7372 */ // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VADDLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 3003 | /* 7372 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv2i64), |
| 3004 | /* 7375 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3005 | /* 7377 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3006 | /* 7381 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 3007 | /* 7385 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3008 | /* 7388 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3009 | /* 7394 */ GIR_RootConstrainSelectedInstOperands, |
| 3010 | /* 7395 */ // GIR_Coverage, 780, |
| 3011 | /* 7395 */ GIR_EraseRootFromParent_Done, |
| 3012 | /* 7396 */ // Label 169: @7396 |
| 3013 | /* 7396 */ GIM_Try, /*On fail goto*//*Label 170*/ GIMT_Encode4(7464), // Rule ID 779 // |
| 3014 | /* 7401 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3015 | /* 7404 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3016 | /* 7408 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 3017 | /* 7412 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 3018 | /* 7416 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3019 | /* 7421 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 3020 | /* 7425 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 3021 | /* 7429 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, |
| 3022 | /* 7433 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3023 | /* 7438 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 3024 | /* 7440 */ // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VADDLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 3025 | /* 7440 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv2i64), |
| 3026 | /* 7443 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3027 | /* 7445 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3028 | /* 7449 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 3029 | /* 7453 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3030 | /* 7456 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3031 | /* 7462 */ GIR_RootConstrainSelectedInstOperands, |
| 3032 | /* 7463 */ // GIR_Coverage, 779, |
| 3033 | /* 7463 */ GIR_EraseRootFromParent_Done, |
| 3034 | /* 7464 */ // Label 170: @7464 |
| 3035 | /* 7464 */ GIM_Try, /*On fail goto*//*Label 171*/ GIMT_Encode4(7517), // Rule ID 5511 // |
| 3036 | /* 7469 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3037 | /* 7472 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3038 | /* 7476 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 3039 | /* 7480 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 3040 | /* 7484 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3041 | /* 7489 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3042 | /* 7493 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3043 | /* 7495 */ // (add:{ *:[v2i64] } (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm), QPR:{ *:[v2i64] }:$Vn) => (VADDWuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 3044 | /* 7495 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv2i64), |
| 3045 | /* 7498 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3046 | /* 7500 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 3047 | /* 7502 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 3048 | /* 7506 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3049 | /* 7509 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3050 | /* 7515 */ GIR_RootConstrainSelectedInstOperands, |
| 3051 | /* 7516 */ // GIR_Coverage, 5511, |
| 3052 | /* 7516 */ GIR_EraseRootFromParent_Done, |
| 3053 | /* 7517 */ // Label 171: @7517 |
| 3054 | /* 7517 */ GIM_Try, /*On fail goto*//*Label 172*/ GIMT_Encode4(7570), // Rule ID 5505 // |
| 3055 | /* 7522 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3056 | /* 7525 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3057 | /* 7529 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT), |
| 3058 | /* 7533 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 3059 | /* 7537 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3060 | /* 7542 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3061 | /* 7546 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3062 | /* 7548 */ // (add:{ *:[v2i64] } (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm), QPR:{ *:[v2i64] }:$Vn) => (VADDWsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 3063 | /* 7548 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWsv2i64), |
| 3064 | /* 7551 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3065 | /* 7553 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 3066 | /* 7555 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 3067 | /* 7559 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3068 | /* 7562 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3069 | /* 7568 */ GIR_RootConstrainSelectedInstOperands, |
| 3070 | /* 7569 */ // GIR_Coverage, 5505, |
| 3071 | /* 7569 */ GIR_EraseRootFromParent_Done, |
| 3072 | /* 7570 */ // Label 172: @7570 |
| 3073 | /* 7570 */ GIM_Try, /*On fail goto*//*Label 173*/ GIMT_Encode4(7623), // Rule ID 5510 // |
| 3074 | /* 7575 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3075 | /* 7578 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3076 | /* 7582 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 3077 | /* 7586 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 3078 | /* 7590 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3079 | /* 7595 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3080 | /* 7599 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3081 | /* 7601 */ // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm), QPR:{ *:[v2i64] }:$Vn) => (VADDWuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 3082 | /* 7601 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv2i64), |
| 3083 | /* 7604 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3084 | /* 7606 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 3085 | /* 7608 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 3086 | /* 7612 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3087 | /* 7615 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3088 | /* 7621 */ GIR_RootConstrainSelectedInstOperands, |
| 3089 | /* 7622 */ // GIR_Coverage, 5510, |
| 3090 | /* 7622 */ GIR_EraseRootFromParent_Done, |
| 3091 | /* 7623 */ // Label 173: @7623 |
| 3092 | /* 7623 */ GIM_Try, /*On fail goto*//*Label 174*/ GIMT_Encode4(7676), // Rule ID 791 // |
| 3093 | /* 7628 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3094 | /* 7631 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3095 | /* 7635 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3096 | /* 7639 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 3097 | /* 7643 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 3098 | /* 7647 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3099 | /* 7652 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3100 | /* 7654 */ // (add:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VADDWuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 3101 | /* 7654 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv2i64), |
| 3102 | /* 7657 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3103 | /* 7659 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 3104 | /* 7661 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 3105 | /* 7665 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3106 | /* 7668 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3107 | /* 7674 */ GIR_RootConstrainSelectedInstOperands, |
| 3108 | /* 7675 */ // GIR_Coverage, 791, |
| 3109 | /* 7675 */ GIR_EraseRootFromParent_Done, |
| 3110 | /* 7676 */ // Label 174: @7676 |
| 3111 | /* 7676 */ GIM_Try, /*On fail goto*//*Label 175*/ GIMT_Encode4(7729), // Rule ID 785 // |
| 3112 | /* 7681 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3113 | /* 7684 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3114 | /* 7688 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3115 | /* 7692 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT), |
| 3116 | /* 7696 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 3117 | /* 7700 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3118 | /* 7705 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3119 | /* 7707 */ // (add:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VADDWsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 3120 | /* 7707 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWsv2i64), |
| 3121 | /* 7710 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3122 | /* 7712 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 3123 | /* 7714 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 3124 | /* 7718 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3125 | /* 7721 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3126 | /* 7727 */ GIR_RootConstrainSelectedInstOperands, |
| 3127 | /* 7728 */ // GIR_Coverage, 785, |
| 3128 | /* 7728 */ GIR_EraseRootFromParent_Done, |
| 3129 | /* 7729 */ // Label 175: @7729 |
| 3130 | /* 7729 */ GIM_Try, /*On fail goto*//*Label 176*/ GIMT_Encode4(7782), // Rule ID 790 // |
| 3131 | /* 7734 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3132 | /* 7737 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3133 | /* 7741 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3134 | /* 7745 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 3135 | /* 7749 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 3136 | /* 7753 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3137 | /* 7758 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3138 | /* 7760 */ // (add:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VADDWuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 3139 | /* 7760 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv2i64), |
| 3140 | /* 7763 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3141 | /* 7765 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 3142 | /* 7767 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 3143 | /* 7771 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3144 | /* 7774 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3145 | /* 7780 */ GIR_RootConstrainSelectedInstOperands, |
| 3146 | /* 7781 */ // GIR_Coverage, 790, |
| 3147 | /* 7781 */ GIR_EraseRootFromParent_Done, |
| 3148 | /* 7782 */ // Label 176: @7782 |
| 3149 | /* 7782 */ GIM_Try, /*On fail goto*//*Label 177*/ GIMT_Encode4(7818), // Rule ID 763 // |
| 3150 | /* 7787 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3151 | /* 7790 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3152 | /* 7794 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3153 | /* 7798 */ // (add:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) => (VADDv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) |
| 3154 | /* 7798 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDv2i64), |
| 3155 | /* 7801 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3156 | /* 7803 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 3157 | /* 7805 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 3158 | /* 7807 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3159 | /* 7810 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3160 | /* 7816 */ GIR_RootConstrainSelectedInstOperands, |
| 3161 | /* 7817 */ // GIR_Coverage, 763, |
| 3162 | /* 7817 */ GIR_EraseRootFromParent_Done, |
| 3163 | /* 7818 */ // Label 177: @7818 |
| 3164 | /* 7818 */ GIM_Reject, |
| 3165 | /* 7819 */ // Label 165: @7819 |
| 3166 | /* 7819 */ GIM_Reject, |
| 3167 | /* 7820 */ // Label 84: @7820 |
| 3168 | /* 7820 */ GIM_Try, /*On fail goto*//*Label 178*/ GIMT_Encode4(8004), |
| 3169 | /* 7825 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 3170 | /* 7828 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 3171 | /* 7831 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3172 | /* 7835 */ GIM_Try, /*On fail goto*//*Label 179*/ GIMT_Encode4(7901), // Rule ID 5531 // |
| 3173 | /* 7840 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3174 | /* 7843 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3175 | /* 7847 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 3176 | /* 7851 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 3177 | /* 7855 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 3178 | /* 7859 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3179 | /* 7864 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3180 | /* 7869 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3181 | /* 7873 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3182 | /* 7875 */ // (add:{ *:[v4i16] } (mul:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm), DPR:{ *:[v4i16] }:$src1) => (VMLAv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 3183 | /* 7875 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv4i16), |
| 3184 | /* 7878 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3185 | /* 7880 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 3186 | /* 7882 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3187 | /* 7886 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 3188 | /* 7890 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3189 | /* 7893 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3190 | /* 7899 */ GIR_RootConstrainSelectedInstOperands, |
| 3191 | /* 7900 */ // GIR_Coverage, 5531, |
| 3192 | /* 7900 */ GIR_EraseRootFromParent_Done, |
| 3193 | /* 7901 */ // Label 179: @7901 |
| 3194 | /* 7901 */ GIM_Try, /*On fail goto*//*Label 180*/ GIMT_Encode4(7967), // Rule ID 888 // |
| 3195 | /* 7906 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3196 | /* 7909 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3197 | /* 7913 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3198 | /* 7917 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 3199 | /* 7921 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 3200 | /* 7925 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 3201 | /* 7929 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3202 | /* 7934 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3203 | /* 7939 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3204 | /* 7941 */ // (add:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, (mul:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)) => (VMLAv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 3205 | /* 7941 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv4i16), |
| 3206 | /* 7944 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3207 | /* 7946 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 3208 | /* 7948 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3209 | /* 7952 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 3210 | /* 7956 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3211 | /* 7959 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3212 | /* 7965 */ GIR_RootConstrainSelectedInstOperands, |
| 3213 | /* 7966 */ // GIR_Coverage, 888, |
| 3214 | /* 7966 */ GIR_EraseRootFromParent_Done, |
| 3215 | /* 7967 */ // Label 180: @7967 |
| 3216 | /* 7967 */ GIM_Try, /*On fail goto*//*Label 181*/ GIMT_Encode4(8003), // Rule ID 757 // |
| 3217 | /* 7972 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3218 | /* 7975 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3219 | /* 7979 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3220 | /* 7983 */ // (add:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VADDv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 3221 | /* 7983 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDv4i16), |
| 3222 | /* 7986 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3223 | /* 7988 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 3224 | /* 7990 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 3225 | /* 7992 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3226 | /* 7995 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3227 | /* 8001 */ GIR_RootConstrainSelectedInstOperands, |
| 3228 | /* 8002 */ // GIR_Coverage, 757, |
| 3229 | /* 8002 */ GIR_EraseRootFromParent_Done, |
| 3230 | /* 8003 */ // Label 181: @8003 |
| 3231 | /* 8003 */ GIM_Reject, |
| 3232 | /* 8004 */ // Label 178: @8004 |
| 3233 | /* 8004 */ GIM_Reject, |
| 3234 | /* 8005 */ // Label 85: @8005 |
| 3235 | /* 8005 */ GIM_Try, /*On fail goto*//*Label 182*/ GIMT_Encode4(8960), |
| 3236 | /* 8010 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 3237 | /* 8013 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 3238 | /* 8016 */ GIM_Try, /*On fail goto*//*Label 183*/ GIMT_Encode4(8088), // Rule ID 778 // |
| 3239 | /* 8021 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3240 | /* 8024 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3241 | /* 8028 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3242 | /* 8032 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 3243 | /* 8036 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 3244 | /* 8040 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3245 | /* 8045 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 3246 | /* 8049 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 3247 | /* 8053 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, |
| 3248 | /* 8057 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3249 | /* 8062 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 3250 | /* 8064 */ // (add:{ *:[v4i32] } (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VADDLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 3251 | /* 8064 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv4i32), |
| 3252 | /* 8067 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3253 | /* 8069 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3254 | /* 8073 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 3255 | /* 8077 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3256 | /* 8080 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3257 | /* 8086 */ GIR_RootConstrainSelectedInstOperands, |
| 3258 | /* 8087 */ // GIR_Coverage, 778, |
| 3259 | /* 8087 */ GIR_EraseRootFromParent_Done, |
| 3260 | /* 8088 */ // Label 183: @8088 |
| 3261 | /* 8088 */ GIM_Try, /*On fail goto*//*Label 184*/ GIMT_Encode4(8160), // Rule ID 777 // |
| 3262 | /* 8093 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3263 | /* 8096 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3264 | /* 8100 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3265 | /* 8104 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 3266 | /* 8108 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 3267 | /* 8112 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3268 | /* 8117 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 3269 | /* 8121 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 3270 | /* 8125 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, |
| 3271 | /* 8129 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3272 | /* 8134 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 3273 | /* 8136 */ // (add:{ *:[v4i32] } (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VADDLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 3274 | /* 8136 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv4i32), |
| 3275 | /* 8139 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3276 | /* 8141 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3277 | /* 8145 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 3278 | /* 8149 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3279 | /* 8152 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3280 | /* 8158 */ GIR_RootConstrainSelectedInstOperands, |
| 3281 | /* 8159 */ // GIR_Coverage, 777, |
| 3282 | /* 8159 */ GIR_EraseRootFromParent_Done, |
| 3283 | /* 8160 */ // Label 184: @8160 |
| 3284 | /* 8160 */ GIM_Try, /*On fail goto*//*Label 185*/ GIMT_Encode4(8232), // Rule ID 769 // |
| 3285 | /* 8165 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3286 | /* 8168 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3287 | /* 8172 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3288 | /* 8176 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT), |
| 3289 | /* 8180 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 3290 | /* 8184 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3291 | /* 8189 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 3292 | /* 8193 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT), |
| 3293 | /* 8197 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, |
| 3294 | /* 8201 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3295 | /* 8206 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 3296 | /* 8208 */ // (add:{ *:[v4i32] } (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VADDLsv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 3297 | /* 8208 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLsv4i32), |
| 3298 | /* 8211 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3299 | /* 8213 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3300 | /* 8217 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 3301 | /* 8221 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3302 | /* 8224 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3303 | /* 8230 */ GIR_RootConstrainSelectedInstOperands, |
| 3304 | /* 8231 */ // GIR_Coverage, 769, |
| 3305 | /* 8231 */ GIR_EraseRootFromParent_Done, |
| 3306 | /* 8232 */ // Label 185: @8232 |
| 3307 | /* 8232 */ GIM_Try, /*On fail goto*//*Label 186*/ GIMT_Encode4(8304), // Rule ID 776 // |
| 3308 | /* 8237 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3309 | /* 8240 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3310 | /* 8244 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3311 | /* 8248 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 3312 | /* 8252 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 3313 | /* 8256 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3314 | /* 8261 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 3315 | /* 8265 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 3316 | /* 8269 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, |
| 3317 | /* 8273 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3318 | /* 8278 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 3319 | /* 8280 */ // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VADDLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 3320 | /* 8280 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv4i32), |
| 3321 | /* 8283 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3322 | /* 8285 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3323 | /* 8289 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 3324 | /* 8293 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3325 | /* 8296 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3326 | /* 8302 */ GIR_RootConstrainSelectedInstOperands, |
| 3327 | /* 8303 */ // GIR_Coverage, 776, |
| 3328 | /* 8303 */ GIR_EraseRootFromParent_Done, |
| 3329 | /* 8304 */ // Label 186: @8304 |
| 3330 | /* 8304 */ GIM_Try, /*On fail goto*//*Label 187*/ GIMT_Encode4(8376), // Rule ID 775 // |
| 3331 | /* 8309 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3332 | /* 8312 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3333 | /* 8316 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3334 | /* 8320 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 3335 | /* 8324 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 3336 | /* 8328 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3337 | /* 8333 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 3338 | /* 8337 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 3339 | /* 8341 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, |
| 3340 | /* 8345 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3341 | /* 8350 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 3342 | /* 8352 */ // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VADDLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 3343 | /* 8352 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv4i32), |
| 3344 | /* 8355 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3345 | /* 8357 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3346 | /* 8361 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 3347 | /* 8365 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3348 | /* 8368 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3349 | /* 8374 */ GIR_RootConstrainSelectedInstOperands, |
| 3350 | /* 8375 */ // GIR_Coverage, 775, |
| 3351 | /* 8375 */ GIR_EraseRootFromParent_Done, |
| 3352 | /* 8376 */ // Label 187: @8376 |
| 3353 | /* 8376 */ GIM_Try, /*On fail goto*//*Label 188*/ GIMT_Encode4(8446), // Rule ID 5535 // |
| 3354 | /* 8381 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3355 | /* 8384 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3356 | /* 8388 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3357 | /* 8392 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 3358 | /* 8396 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 3359 | /* 8400 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 3360 | /* 8404 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3361 | /* 8409 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3362 | /* 8414 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3363 | /* 8418 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3364 | /* 8420 */ // (add:{ *:[v4i32] } (mul:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm), QPR:{ *:[v4i32] }:$src1) => (VMLAv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 3365 | /* 8420 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv4i32), |
| 3366 | /* 8423 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3367 | /* 8425 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 3368 | /* 8427 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3369 | /* 8431 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 3370 | /* 8435 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3371 | /* 8438 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3372 | /* 8444 */ GIR_RootConstrainSelectedInstOperands, |
| 3373 | /* 8445 */ // GIR_Coverage, 5535, |
| 3374 | /* 8445 */ GIR_EraseRootFromParent_Done, |
| 3375 | /* 8446 */ // Label 188: @8446 |
| 3376 | /* 8446 */ GIM_Try, /*On fail goto*//*Label 189*/ GIMT_Encode4(8503), // Rule ID 5509 // |
| 3377 | /* 8451 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3378 | /* 8454 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3379 | /* 8458 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3380 | /* 8462 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 3381 | /* 8466 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 3382 | /* 8470 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3383 | /* 8475 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3384 | /* 8479 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3385 | /* 8481 */ // (add:{ *:[v4i32] } (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm), QPR:{ *:[v4i32] }:$Vn) => (VADDWuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 3386 | /* 8481 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv4i32), |
| 3387 | /* 8484 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3388 | /* 8486 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 3389 | /* 8488 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 3390 | /* 8492 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3391 | /* 8495 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3392 | /* 8501 */ GIR_RootConstrainSelectedInstOperands, |
| 3393 | /* 8502 */ // GIR_Coverage, 5509, |
| 3394 | /* 8502 */ GIR_EraseRootFromParent_Done, |
| 3395 | /* 8503 */ // Label 189: @8503 |
| 3396 | /* 8503 */ GIM_Try, /*On fail goto*//*Label 190*/ GIMT_Encode4(8560), // Rule ID 5504 // |
| 3397 | /* 8508 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3398 | /* 8511 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3399 | /* 8515 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3400 | /* 8519 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT), |
| 3401 | /* 8523 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 3402 | /* 8527 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3403 | /* 8532 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3404 | /* 8536 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3405 | /* 8538 */ // (add:{ *:[v4i32] } (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm), QPR:{ *:[v4i32] }:$Vn) => (VADDWsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 3406 | /* 8538 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWsv4i32), |
| 3407 | /* 8541 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3408 | /* 8543 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 3409 | /* 8545 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 3410 | /* 8549 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3411 | /* 8552 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3412 | /* 8558 */ GIR_RootConstrainSelectedInstOperands, |
| 3413 | /* 8559 */ // GIR_Coverage, 5504, |
| 3414 | /* 8559 */ GIR_EraseRootFromParent_Done, |
| 3415 | /* 8560 */ // Label 190: @8560 |
| 3416 | /* 8560 */ GIM_Try, /*On fail goto*//*Label 191*/ GIMT_Encode4(8617), // Rule ID 5508 // |
| 3417 | /* 8565 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3418 | /* 8568 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3419 | /* 8572 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3420 | /* 8576 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 3421 | /* 8580 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 3422 | /* 8584 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3423 | /* 8589 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3424 | /* 8593 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3425 | /* 8595 */ // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm), QPR:{ *:[v4i32] }:$Vn) => (VADDWuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 3426 | /* 8595 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv4i32), |
| 3427 | /* 8598 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3428 | /* 8600 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 3429 | /* 8602 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 3430 | /* 8606 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3431 | /* 8609 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3432 | /* 8615 */ GIR_RootConstrainSelectedInstOperands, |
| 3433 | /* 8616 */ // GIR_Coverage, 5508, |
| 3434 | /* 8616 */ GIR_EraseRootFromParent_Done, |
| 3435 | /* 8617 */ // Label 191: @8617 |
| 3436 | /* 8617 */ GIM_Try, /*On fail goto*//*Label 192*/ GIMT_Encode4(8687), // Rule ID 892 // |
| 3437 | /* 8622 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3438 | /* 8625 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3439 | /* 8629 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3440 | /* 8633 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3441 | /* 8637 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 3442 | /* 8641 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 3443 | /* 8645 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 3444 | /* 8649 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3445 | /* 8654 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3446 | /* 8659 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3447 | /* 8661 */ // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (mul:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)) => (VMLAv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 3448 | /* 8661 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv4i32), |
| 3449 | /* 8664 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3450 | /* 8666 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 3451 | /* 8668 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3452 | /* 8672 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 3453 | /* 8676 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3454 | /* 8679 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3455 | /* 8685 */ GIR_RootConstrainSelectedInstOperands, |
| 3456 | /* 8686 */ // GIR_Coverage, 892, |
| 3457 | /* 8686 */ GIR_EraseRootFromParent_Done, |
| 3458 | /* 8687 */ // Label 192: @8687 |
| 3459 | /* 8687 */ GIM_Try, /*On fail goto*//*Label 193*/ GIMT_Encode4(8744), // Rule ID 789 // |
| 3460 | /* 8692 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3461 | /* 8695 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3462 | /* 8699 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3463 | /* 8703 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3464 | /* 8707 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 3465 | /* 8711 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 3466 | /* 8715 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3467 | /* 8720 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3468 | /* 8722 */ // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VADDWuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 3469 | /* 8722 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv4i32), |
| 3470 | /* 8725 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3471 | /* 8727 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 3472 | /* 8729 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 3473 | /* 8733 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3474 | /* 8736 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3475 | /* 8742 */ GIR_RootConstrainSelectedInstOperands, |
| 3476 | /* 8743 */ // GIR_Coverage, 789, |
| 3477 | /* 8743 */ GIR_EraseRootFromParent_Done, |
| 3478 | /* 8744 */ // Label 193: @8744 |
| 3479 | /* 8744 */ GIM_Try, /*On fail goto*//*Label 194*/ GIMT_Encode4(8801), // Rule ID 784 // |
| 3480 | /* 8749 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3481 | /* 8752 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3482 | /* 8756 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3483 | /* 8760 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3484 | /* 8764 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT), |
| 3485 | /* 8768 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 3486 | /* 8772 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3487 | /* 8777 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3488 | /* 8779 */ // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VADDWsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 3489 | /* 8779 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWsv4i32), |
| 3490 | /* 8782 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3491 | /* 8784 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 3492 | /* 8786 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 3493 | /* 8790 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3494 | /* 8793 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3495 | /* 8799 */ GIR_RootConstrainSelectedInstOperands, |
| 3496 | /* 8800 */ // GIR_Coverage, 784, |
| 3497 | /* 8800 */ GIR_EraseRootFromParent_Done, |
| 3498 | /* 8801 */ // Label 194: @8801 |
| 3499 | /* 8801 */ GIM_Try, /*On fail goto*//*Label 195*/ GIMT_Encode4(8858), // Rule ID 788 // |
| 3500 | /* 8806 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3501 | /* 8809 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3502 | /* 8813 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3503 | /* 8817 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3504 | /* 8821 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 3505 | /* 8825 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 3506 | /* 8829 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3507 | /* 8834 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3508 | /* 8836 */ // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VADDWuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 3509 | /* 8836 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv4i32), |
| 3510 | /* 8839 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3511 | /* 8841 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 3512 | /* 8843 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 3513 | /* 8847 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3514 | /* 8850 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3515 | /* 8856 */ GIR_RootConstrainSelectedInstOperands, |
| 3516 | /* 8857 */ // GIR_Coverage, 788, |
| 3517 | /* 8857 */ GIR_EraseRootFromParent_Done, |
| 3518 | /* 8858 */ // Label 195: @8858 |
| 3519 | /* 8858 */ GIM_Try, /*On fail goto*//*Label 196*/ GIMT_Encode4(8898), // Rule ID 761 // |
| 3520 | /* 8863 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3521 | /* 8866 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3522 | /* 8870 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3523 | /* 8874 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3524 | /* 8878 */ // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VADDv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 3525 | /* 8878 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDv4i32), |
| 3526 | /* 8881 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3527 | /* 8883 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 3528 | /* 8885 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 3529 | /* 8887 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3530 | /* 8890 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3531 | /* 8896 */ GIR_RootConstrainSelectedInstOperands, |
| 3532 | /* 8897 */ // GIR_Coverage, 761, |
| 3533 | /* 8897 */ GIR_EraseRootFromParent_Done, |
| 3534 | /* 8898 */ // Label 196: @8898 |
| 3535 | /* 8898 */ GIM_Try, /*On fail goto*//*Label 197*/ GIMT_Encode4(8959), // Rule ID 3496 // |
| 3536 | /* 8903 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 3537 | /* 8906 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 3538 | /* 8910 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 3539 | /* 8914 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 3540 | /* 8918 */ // (add:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VADDi32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 3541 | /* 8918 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 3542 | /* 8921 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 3543 | /* 8925 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 3544 | /* 8930 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDi32), |
| 3545 | /* 8933 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 3546 | /* 8935 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 3547 | /* 8937 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 3548 | /* 8939 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 3549 | /* 8942 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3550 | /* 8948 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3551 | /* 8954 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 3552 | /* 8957 */ GIR_RootConstrainSelectedInstOperands, |
| 3553 | /* 8958 */ // GIR_Coverage, 3496, |
| 3554 | /* 8958 */ GIR_EraseRootFromParent_Done, |
| 3555 | /* 8959 */ // Label 197: @8959 |
| 3556 | /* 8959 */ GIM_Reject, |
| 3557 | /* 8960 */ // Label 182: @8960 |
| 3558 | /* 8960 */ GIM_Reject, |
| 3559 | /* 8961 */ // Label 86: @8961 |
| 3560 | /* 8961 */ GIM_Try, /*On fail goto*//*Label 198*/ GIMT_Encode4(9145), |
| 3561 | /* 8966 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 3562 | /* 8969 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 3563 | /* 8972 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3564 | /* 8976 */ GIM_Try, /*On fail goto*//*Label 199*/ GIMT_Encode4(9042), // Rule ID 5530 // |
| 3565 | /* 8981 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3566 | /* 8984 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3567 | /* 8988 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 3568 | /* 8992 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 3569 | /* 8996 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, |
| 3570 | /* 9000 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3571 | /* 9005 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3572 | /* 9010 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3573 | /* 9014 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3574 | /* 9016 */ // (add:{ *:[v8i8] } (mul:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm), DPR:{ *:[v8i8] }:$src1) => (VMLAv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 3575 | /* 9016 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv8i8), |
| 3576 | /* 9019 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3577 | /* 9021 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 3578 | /* 9023 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3579 | /* 9027 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 3580 | /* 9031 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3581 | /* 9034 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3582 | /* 9040 */ GIR_RootConstrainSelectedInstOperands, |
| 3583 | /* 9041 */ // GIR_Coverage, 5530, |
| 3584 | /* 9041 */ GIR_EraseRootFromParent_Done, |
| 3585 | /* 9042 */ // Label 199: @9042 |
| 3586 | /* 9042 */ GIM_Try, /*On fail goto*//*Label 200*/ GIMT_Encode4(9108), // Rule ID 887 // |
| 3587 | /* 9047 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3588 | /* 9050 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3589 | /* 9054 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3590 | /* 9058 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 3591 | /* 9062 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 3592 | /* 9066 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, |
| 3593 | /* 9070 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3594 | /* 9075 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3595 | /* 9080 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3596 | /* 9082 */ // (add:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, (mul:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)) => (VMLAv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 3597 | /* 9082 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv8i8), |
| 3598 | /* 9085 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3599 | /* 9087 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 3600 | /* 9089 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3601 | /* 9093 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 3602 | /* 9097 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3603 | /* 9100 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3604 | /* 9106 */ GIR_RootConstrainSelectedInstOperands, |
| 3605 | /* 9107 */ // GIR_Coverage, 887, |
| 3606 | /* 9107 */ GIR_EraseRootFromParent_Done, |
| 3607 | /* 9108 */ // Label 200: @9108 |
| 3608 | /* 9108 */ GIM_Try, /*On fail goto*//*Label 201*/ GIMT_Encode4(9144), // Rule ID 756 // |
| 3609 | /* 9113 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3610 | /* 9116 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3611 | /* 9120 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3612 | /* 9124 */ // (add:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VADDv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 3613 | /* 9124 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDv8i8), |
| 3614 | /* 9127 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3615 | /* 9129 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 3616 | /* 9131 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 3617 | /* 9133 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3618 | /* 9136 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3619 | /* 9142 */ GIR_RootConstrainSelectedInstOperands, |
| 3620 | /* 9143 */ // GIR_Coverage, 756, |
| 3621 | /* 9143 */ GIR_EraseRootFromParent_Done, |
| 3622 | /* 9144 */ // Label 201: @9144 |
| 3623 | /* 9144 */ GIM_Reject, |
| 3624 | /* 9145 */ // Label 198: @9145 |
| 3625 | /* 9145 */ GIM_Reject, |
| 3626 | /* 9146 */ // Label 87: @9146 |
| 3627 | /* 9146 */ GIM_Try, /*On fail goto*//*Label 202*/ GIMT_Encode4(10101), |
| 3628 | /* 9151 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 3629 | /* 9154 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 3630 | /* 9157 */ GIM_Try, /*On fail goto*//*Label 203*/ GIMT_Encode4(9229), // Rule ID 774 // |
| 3631 | /* 9162 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3632 | /* 9165 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3633 | /* 9169 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3634 | /* 9173 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 3635 | /* 9177 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 3636 | /* 9181 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3637 | /* 9186 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 3638 | /* 9190 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 3639 | /* 9194 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, |
| 3640 | /* 9198 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3641 | /* 9203 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 3642 | /* 9205 */ // (add:{ *:[v8i16] } (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VADDLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 3643 | /* 9205 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv8i16), |
| 3644 | /* 9208 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3645 | /* 9210 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3646 | /* 9214 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 3647 | /* 9218 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3648 | /* 9221 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3649 | /* 9227 */ GIR_RootConstrainSelectedInstOperands, |
| 3650 | /* 9228 */ // GIR_Coverage, 774, |
| 3651 | /* 9228 */ GIR_EraseRootFromParent_Done, |
| 3652 | /* 9229 */ // Label 203: @9229 |
| 3653 | /* 9229 */ GIM_Try, /*On fail goto*//*Label 204*/ GIMT_Encode4(9301), // Rule ID 773 // |
| 3654 | /* 9234 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3655 | /* 9237 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3656 | /* 9241 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3657 | /* 9245 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 3658 | /* 9249 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 3659 | /* 9253 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3660 | /* 9258 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 3661 | /* 9262 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 3662 | /* 9266 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, |
| 3663 | /* 9270 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3664 | /* 9275 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 3665 | /* 9277 */ // (add:{ *:[v8i16] } (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VADDLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 3666 | /* 9277 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv8i16), |
| 3667 | /* 9280 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3668 | /* 9282 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3669 | /* 9286 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 3670 | /* 9290 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3671 | /* 9293 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3672 | /* 9299 */ GIR_RootConstrainSelectedInstOperands, |
| 3673 | /* 9300 */ // GIR_Coverage, 773, |
| 3674 | /* 9300 */ GIR_EraseRootFromParent_Done, |
| 3675 | /* 9301 */ // Label 204: @9301 |
| 3676 | /* 9301 */ GIM_Try, /*On fail goto*//*Label 205*/ GIMT_Encode4(9373), // Rule ID 768 // |
| 3677 | /* 9306 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3678 | /* 9309 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3679 | /* 9313 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3680 | /* 9317 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT), |
| 3681 | /* 9321 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 3682 | /* 9325 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3683 | /* 9330 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 3684 | /* 9334 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT), |
| 3685 | /* 9338 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, |
| 3686 | /* 9342 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3687 | /* 9347 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 3688 | /* 9349 */ // (add:{ *:[v8i16] } (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VADDLsv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 3689 | /* 9349 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLsv8i16), |
| 3690 | /* 9352 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3691 | /* 9354 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3692 | /* 9358 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 3693 | /* 9362 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3694 | /* 9365 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3695 | /* 9371 */ GIR_RootConstrainSelectedInstOperands, |
| 3696 | /* 9372 */ // GIR_Coverage, 768, |
| 3697 | /* 9372 */ GIR_EraseRootFromParent_Done, |
| 3698 | /* 9373 */ // Label 205: @9373 |
| 3699 | /* 9373 */ GIM_Try, /*On fail goto*//*Label 206*/ GIMT_Encode4(9445), // Rule ID 772 // |
| 3700 | /* 9378 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3701 | /* 9381 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3702 | /* 9385 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3703 | /* 9389 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 3704 | /* 9393 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 3705 | /* 9397 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3706 | /* 9402 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 3707 | /* 9406 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 3708 | /* 9410 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, |
| 3709 | /* 9414 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3710 | /* 9419 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 3711 | /* 9421 */ // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VADDLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 3712 | /* 9421 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv8i16), |
| 3713 | /* 9424 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3714 | /* 9426 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3715 | /* 9430 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 3716 | /* 9434 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3717 | /* 9437 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3718 | /* 9443 */ GIR_RootConstrainSelectedInstOperands, |
| 3719 | /* 9444 */ // GIR_Coverage, 772, |
| 3720 | /* 9444 */ GIR_EraseRootFromParent_Done, |
| 3721 | /* 9445 */ // Label 206: @9445 |
| 3722 | /* 9445 */ GIM_Try, /*On fail goto*//*Label 207*/ GIMT_Encode4(9517), // Rule ID 771 // |
| 3723 | /* 9450 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3724 | /* 9453 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3725 | /* 9457 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3726 | /* 9461 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 3727 | /* 9465 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 3728 | /* 9469 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3729 | /* 9474 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 3730 | /* 9478 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 3731 | /* 9482 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, |
| 3732 | /* 9486 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3733 | /* 9491 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 3734 | /* 9493 */ // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VADDLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 3735 | /* 9493 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv8i16), |
| 3736 | /* 9496 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3737 | /* 9498 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3738 | /* 9502 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 3739 | /* 9506 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3740 | /* 9509 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3741 | /* 9515 */ GIR_RootConstrainSelectedInstOperands, |
| 3742 | /* 9516 */ // GIR_Coverage, 771, |
| 3743 | /* 9516 */ GIR_EraseRootFromParent_Done, |
| 3744 | /* 9517 */ // Label 207: @9517 |
| 3745 | /* 9517 */ GIM_Try, /*On fail goto*//*Label 208*/ GIMT_Encode4(9587), // Rule ID 5534 // |
| 3746 | /* 9522 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3747 | /* 9525 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3748 | /* 9529 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3749 | /* 9533 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 3750 | /* 9537 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 3751 | /* 9541 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 3752 | /* 9545 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3753 | /* 9550 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3754 | /* 9555 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3755 | /* 9559 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3756 | /* 9561 */ // (add:{ *:[v8i16] } (mul:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm), QPR:{ *:[v8i16] }:$src1) => (VMLAv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 3757 | /* 9561 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv8i16), |
| 3758 | /* 9564 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3759 | /* 9566 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 3760 | /* 9568 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3761 | /* 9572 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 3762 | /* 9576 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3763 | /* 9579 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3764 | /* 9585 */ GIR_RootConstrainSelectedInstOperands, |
| 3765 | /* 9586 */ // GIR_Coverage, 5534, |
| 3766 | /* 9586 */ GIR_EraseRootFromParent_Done, |
| 3767 | /* 9587 */ // Label 208: @9587 |
| 3768 | /* 9587 */ GIM_Try, /*On fail goto*//*Label 209*/ GIMT_Encode4(9644), // Rule ID 5507 // |
| 3769 | /* 9592 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3770 | /* 9595 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3771 | /* 9599 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3772 | /* 9603 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 3773 | /* 9607 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 3774 | /* 9611 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3775 | /* 9616 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3776 | /* 9620 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3777 | /* 9622 */ // (add:{ *:[v8i16] } (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm), QPR:{ *:[v8i16] }:$Vn) => (VADDWuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 3778 | /* 9622 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv8i16), |
| 3779 | /* 9625 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3780 | /* 9627 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 3781 | /* 9629 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 3782 | /* 9633 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3783 | /* 9636 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3784 | /* 9642 */ GIR_RootConstrainSelectedInstOperands, |
| 3785 | /* 9643 */ // GIR_Coverage, 5507, |
| 3786 | /* 9643 */ GIR_EraseRootFromParent_Done, |
| 3787 | /* 9644 */ // Label 209: @9644 |
| 3788 | /* 9644 */ GIM_Try, /*On fail goto*//*Label 210*/ GIMT_Encode4(9701), // Rule ID 5503 // |
| 3789 | /* 9649 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3790 | /* 9652 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3791 | /* 9656 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3792 | /* 9660 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT), |
| 3793 | /* 9664 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 3794 | /* 9668 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3795 | /* 9673 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3796 | /* 9677 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3797 | /* 9679 */ // (add:{ *:[v8i16] } (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm), QPR:{ *:[v8i16] }:$Vn) => (VADDWsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 3798 | /* 9679 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWsv8i16), |
| 3799 | /* 9682 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3800 | /* 9684 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 3801 | /* 9686 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 3802 | /* 9690 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3803 | /* 9693 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3804 | /* 9699 */ GIR_RootConstrainSelectedInstOperands, |
| 3805 | /* 9700 */ // GIR_Coverage, 5503, |
| 3806 | /* 9700 */ GIR_EraseRootFromParent_Done, |
| 3807 | /* 9701 */ // Label 210: @9701 |
| 3808 | /* 9701 */ GIM_Try, /*On fail goto*//*Label 211*/ GIMT_Encode4(9758), // Rule ID 5506 // |
| 3809 | /* 9706 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3810 | /* 9709 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3811 | /* 9713 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3812 | /* 9717 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 3813 | /* 9721 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 3814 | /* 9725 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3815 | /* 9730 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3816 | /* 9734 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3817 | /* 9736 */ // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm), QPR:{ *:[v8i16] }:$Vn) => (VADDWuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 3818 | /* 9736 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv8i16), |
| 3819 | /* 9739 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3820 | /* 9741 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 3821 | /* 9743 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 3822 | /* 9747 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3823 | /* 9750 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3824 | /* 9756 */ GIR_RootConstrainSelectedInstOperands, |
| 3825 | /* 9757 */ // GIR_Coverage, 5506, |
| 3826 | /* 9757 */ GIR_EraseRootFromParent_Done, |
| 3827 | /* 9758 */ // Label 211: @9758 |
| 3828 | /* 9758 */ GIM_Try, /*On fail goto*//*Label 212*/ GIMT_Encode4(9828), // Rule ID 891 // |
| 3829 | /* 9763 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3830 | /* 9766 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3831 | /* 9770 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3832 | /* 9774 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3833 | /* 9778 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 3834 | /* 9782 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 3835 | /* 9786 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 3836 | /* 9790 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3837 | /* 9795 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3838 | /* 9800 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3839 | /* 9802 */ // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, (mul:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)) => (VMLAv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 3840 | /* 9802 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv8i16), |
| 3841 | /* 9805 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3842 | /* 9807 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 3843 | /* 9809 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3844 | /* 9813 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 3845 | /* 9817 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3846 | /* 9820 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3847 | /* 9826 */ GIR_RootConstrainSelectedInstOperands, |
| 3848 | /* 9827 */ // GIR_Coverage, 891, |
| 3849 | /* 9827 */ GIR_EraseRootFromParent_Done, |
| 3850 | /* 9828 */ // Label 212: @9828 |
| 3851 | /* 9828 */ GIM_Try, /*On fail goto*//*Label 213*/ GIMT_Encode4(9885), // Rule ID 787 // |
| 3852 | /* 9833 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3853 | /* 9836 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3854 | /* 9840 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3855 | /* 9844 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3856 | /* 9848 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 3857 | /* 9852 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 3858 | /* 9856 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3859 | /* 9861 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3860 | /* 9863 */ // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VADDWuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 3861 | /* 9863 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv8i16), |
| 3862 | /* 9866 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3863 | /* 9868 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 3864 | /* 9870 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 3865 | /* 9874 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3866 | /* 9877 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3867 | /* 9883 */ GIR_RootConstrainSelectedInstOperands, |
| 3868 | /* 9884 */ // GIR_Coverage, 787, |
| 3869 | /* 9884 */ GIR_EraseRootFromParent_Done, |
| 3870 | /* 9885 */ // Label 213: @9885 |
| 3871 | /* 9885 */ GIM_Try, /*On fail goto*//*Label 214*/ GIMT_Encode4(9942), // Rule ID 783 // |
| 3872 | /* 9890 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3873 | /* 9893 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3874 | /* 9897 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3875 | /* 9901 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3876 | /* 9905 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT), |
| 3877 | /* 9909 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 3878 | /* 9913 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3879 | /* 9918 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3880 | /* 9920 */ // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VADDWsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 3881 | /* 9920 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWsv8i16), |
| 3882 | /* 9923 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3883 | /* 9925 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 3884 | /* 9927 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 3885 | /* 9931 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3886 | /* 9934 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3887 | /* 9940 */ GIR_RootConstrainSelectedInstOperands, |
| 3888 | /* 9941 */ // GIR_Coverage, 783, |
| 3889 | /* 9941 */ GIR_EraseRootFromParent_Done, |
| 3890 | /* 9942 */ // Label 214: @9942 |
| 3891 | /* 9942 */ GIM_Try, /*On fail goto*//*Label 215*/ GIMT_Encode4(9999), // Rule ID 786 // |
| 3892 | /* 9947 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3893 | /* 9950 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3894 | /* 9954 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3895 | /* 9958 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3896 | /* 9962 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 3897 | /* 9966 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 3898 | /* 9970 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3899 | /* 9975 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3900 | /* 9977 */ // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VADDWuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 3901 | /* 9977 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv8i16), |
| 3902 | /* 9980 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3903 | /* 9982 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 3904 | /* 9984 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 3905 | /* 9988 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3906 | /* 9991 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3907 | /* 9997 */ GIR_RootConstrainSelectedInstOperands, |
| 3908 | /* 9998 */ // GIR_Coverage, 786, |
| 3909 | /* 9998 */ GIR_EraseRootFromParent_Done, |
| 3910 | /* 9999 */ // Label 215: @9999 |
| 3911 | /* 9999 */ GIM_Try, /*On fail goto*//*Label 216*/ GIMT_Encode4(10039), // Rule ID 760 // |
| 3912 | /* 10004 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3913 | /* 10007 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3914 | /* 10011 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3915 | /* 10015 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3916 | /* 10019 */ // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VADDv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 3917 | /* 10019 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDv8i16), |
| 3918 | /* 10022 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3919 | /* 10024 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 3920 | /* 10026 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 3921 | /* 10028 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3922 | /* 10031 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3923 | /* 10037 */ GIR_RootConstrainSelectedInstOperands, |
| 3924 | /* 10038 */ // GIR_Coverage, 760, |
| 3925 | /* 10038 */ GIR_EraseRootFromParent_Done, |
| 3926 | /* 10039 */ // Label 216: @10039 |
| 3927 | /* 10039 */ GIM_Try, /*On fail goto*//*Label 217*/ GIMT_Encode4(10100), // Rule ID 3492 // |
| 3928 | /* 10044 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 3929 | /* 10047 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 3930 | /* 10051 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 3931 | /* 10055 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 3932 | /* 10059 */ // (add:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VADDi16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 3933 | /* 10059 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 3934 | /* 10062 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 3935 | /* 10066 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 3936 | /* 10071 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDi16), |
| 3937 | /* 10074 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 3938 | /* 10076 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 3939 | /* 10078 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 3940 | /* 10080 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 3941 | /* 10083 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3942 | /* 10089 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3943 | /* 10095 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 3944 | /* 10098 */ GIR_RootConstrainSelectedInstOperands, |
| 3945 | /* 10099 */ // GIR_Coverage, 3492, |
| 3946 | /* 10099 */ GIR_EraseRootFromParent_Done, |
| 3947 | /* 10100 */ // Label 217: @10100 |
| 3948 | /* 10100 */ GIM_Reject, |
| 3949 | /* 10101 */ // Label 202: @10101 |
| 3950 | /* 10101 */ GIM_Reject, |
| 3951 | /* 10102 */ // Label 88: @10102 |
| 3952 | /* 10102 */ GIM_Try, /*On fail goto*//*Label 218*/ GIMT_Encode4(10355), |
| 3953 | /* 10107 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 3954 | /* 10110 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 3955 | /* 10113 */ GIM_Try, /*On fail goto*//*Label 219*/ GIMT_Encode4(10183), // Rule ID 5533 // |
| 3956 | /* 10118 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3957 | /* 10121 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3958 | /* 10125 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3959 | /* 10129 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 3960 | /* 10133 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, |
| 3961 | /* 10137 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, |
| 3962 | /* 10141 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3963 | /* 10146 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3964 | /* 10151 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3965 | /* 10155 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3966 | /* 10157 */ // (add:{ *:[v16i8] } (mul:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm), QPR:{ *:[v16i8] }:$src1) => (VMLAv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 3967 | /* 10157 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv16i8), |
| 3968 | /* 10160 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3969 | /* 10162 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 3970 | /* 10164 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3971 | /* 10168 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 3972 | /* 10172 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3973 | /* 10175 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3974 | /* 10181 */ GIR_RootConstrainSelectedInstOperands, |
| 3975 | /* 10182 */ // GIR_Coverage, 5533, |
| 3976 | /* 10182 */ GIR_EraseRootFromParent_Done, |
| 3977 | /* 10183 */ // Label 219: @10183 |
| 3978 | /* 10183 */ GIM_Try, /*On fail goto*//*Label 220*/ GIMT_Encode4(10253), // Rule ID 890 // |
| 3979 | /* 10188 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 3980 | /* 10191 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3981 | /* 10195 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3982 | /* 10199 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3983 | /* 10203 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 3984 | /* 10207 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, |
| 3985 | /* 10211 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, |
| 3986 | /* 10215 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3987 | /* 10220 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3988 | /* 10225 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3989 | /* 10227 */ // (add:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, (mul:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)) => (VMLAv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 3990 | /* 10227 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv16i8), |
| 3991 | /* 10230 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3992 | /* 10232 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 3993 | /* 10234 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3994 | /* 10238 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 3995 | /* 10242 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3996 | /* 10245 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3997 | /* 10251 */ GIR_RootConstrainSelectedInstOperands, |
| 3998 | /* 10252 */ // GIR_Coverage, 890, |
| 3999 | /* 10252 */ GIR_EraseRootFromParent_Done, |
| 4000 | /* 10253 */ // Label 220: @10253 |
| 4001 | /* 10253 */ GIM_Try, /*On fail goto*//*Label 221*/ GIMT_Encode4(10293), // Rule ID 759 // |
| 4002 | /* 10258 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 4003 | /* 10261 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4004 | /* 10265 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4005 | /* 10269 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4006 | /* 10273 */ // (add:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VADDv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 4007 | /* 10273 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDv16i8), |
| 4008 | /* 10276 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4009 | /* 10278 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 4010 | /* 10280 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 4011 | /* 10282 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4012 | /* 10285 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4013 | /* 10291 */ GIR_RootConstrainSelectedInstOperands, |
| 4014 | /* 10292 */ // GIR_Coverage, 759, |
| 4015 | /* 10292 */ GIR_EraseRootFromParent_Done, |
| 4016 | /* 10293 */ // Label 221: @10293 |
| 4017 | /* 10293 */ GIM_Try, /*On fail goto*//*Label 222*/ GIMT_Encode4(10354), // Rule ID 3488 // |
| 4018 | /* 10298 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 4019 | /* 10301 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 4020 | /* 10305 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 4021 | /* 10309 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 4022 | /* 10313 */ // (add:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VADDi8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 4023 | /* 10313 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 4024 | /* 10316 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 4025 | /* 10320 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 4026 | /* 10325 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDi8), |
| 4027 | /* 10328 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 4028 | /* 10330 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 4029 | /* 10332 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 4030 | /* 10334 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 4031 | /* 10337 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4032 | /* 10343 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4033 | /* 10349 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 4034 | /* 10352 */ GIR_RootConstrainSelectedInstOperands, |
| 4035 | /* 10353 */ // GIR_Coverage, 3488, |
| 4036 | /* 10353 */ GIR_EraseRootFromParent_Done, |
| 4037 | /* 10354 */ // Label 222: @10354 |
| 4038 | /* 10354 */ GIM_Reject, |
| 4039 | /* 10355 */ // Label 218: @10355 |
| 4040 | /* 10355 */ GIM_Reject, |
| 4041 | /* 10356 */ // Label 89: @10356 |
| 4042 | /* 10356 */ GIM_Reject, |
| 4043 | /* 10357 */ // Label 1: @10357 |
| 4044 | /* 10357 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(16), /*)*//*default:*//*Label 232*/ GIMT_Encode4(13600), |
| 4045 | /* 10368 */ /*GILLT_s32*//*Label 223*/ GIMT_Encode4(10428), |
| 4046 | /* 10372 */ /*GILLT_s64*//*Label 224*/ GIMT_Encode4(11042), GIMT_Encode4(0), |
| 4047 | /* 10380 */ /*GILLT_v2s32*//*Label 225*/ GIMT_Encode4(11089), |
| 4048 | /* 10384 */ /*GILLT_v2s64*//*Label 226*/ GIMT_Encode4(11204), GIMT_Encode4(0), |
| 4049 | /* 10392 */ /*GILLT_v4s16*//*Label 227*/ GIMT_Encode4(11756), |
| 4050 | /* 10396 */ /*GILLT_v4s32*//*Label 228*/ GIMT_Encode4(11871), GIMT_Encode4(0), GIMT_Encode4(0), |
| 4051 | /* 10408 */ /*GILLT_v8s8*//*Label 229*/ GIMT_Encode4(12586), |
| 4052 | /* 10412 */ /*GILLT_v8s16*//*Label 230*/ GIMT_Encode4(12701), GIMT_Encode4(0), GIMT_Encode4(0), |
| 4053 | /* 10424 */ /*GILLT_v16s8*//*Label 231*/ GIMT_Encode4(13416), |
| 4054 | /* 10428 */ // Label 223: @10428 |
| 4055 | /* 10428 */ GIM_Try, /*On fail goto*//*Label 233*/ GIMT_Encode4(11041), |
| 4056 | /* 10433 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 4057 | /* 10436 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 4058 | /* 10439 */ GIM_Try, /*On fail goto*//*Label 234*/ GIMT_Encode4(10483), // Rule ID 330 // |
| 4059 | /* 10444 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), |
| 4060 | /* 10447 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 4061 | /* 10451 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/1, 0, |
| 4062 | /* 10455 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 4063 | /* 10459 */ // (sub:{ *:[i32] } 0:{ *:[i32] }, tGPR:{ *:[i32] }:$Rn) => (tRSB:{ *:[i32] } tGPR:{ *:[i32] }:$Rn) |
| 4064 | /* 10459 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tRSB), |
| 4065 | /* 10462 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 4066 | /* 10464 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define | RegState::Dead), |
| 4067 | /* 10470 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 4068 | /* 10472 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4069 | /* 10475 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4070 | /* 10481 */ GIR_RootConstrainSelectedInstOperands, |
| 4071 | /* 10482 */ // GIR_Coverage, 330, |
| 4072 | /* 10482 */ GIR_EraseRootFromParent_Done, |
| 4073 | /* 10483 */ // Label 234: @10483 |
| 4074 | /* 10483 */ GIM_Try, /*On fail goto*//*Label 235*/ GIMT_Encode4(10540), // Rule ID 96 // |
| 4075 | /* 10488 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 4076 | /* 10491 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 4077 | /* 10495 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4078 | /* 10499 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 4079 | /* 10503 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm), |
| 4080 | /* 10507 */ // MIs[1] Operand 1 |
| 4081 | /* 10507 */ // No operand predicates |
| 4082 | /* 10507 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 4083 | /* 10511 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4084 | /* 10513 */ // (sub:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm, GPR:{ *:[i32] }:$Rn) => (RSBri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 4085 | /* 10513 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::RSBri), |
| 4086 | /* 10516 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 4087 | /* 10518 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 4088 | /* 10520 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 4089 | /* 10523 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4090 | /* 10526 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4091 | /* 10532 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4092 | /* 10538 */ GIR_RootConstrainSelectedInstOperands, |
| 4093 | /* 10539 */ // GIR_Coverage, 96, |
| 4094 | /* 10539 */ GIR_EraseRootFromParent_Done, |
| 4095 | /* 10540 */ // Label 235: @10540 |
| 4096 | /* 10540 */ GIM_Try, /*On fail goto*//*Label 236*/ GIMT_Encode4(10597), // Rule ID 427 // |
| 4097 | /* 10545 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 4098 | /* 10548 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 4099 | /* 10552 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4100 | /* 10556 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 4101 | /* 10560 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm), |
| 4102 | /* 10564 */ // MIs[1] Operand 1 |
| 4103 | /* 10564 */ // No operand predicates |
| 4104 | /* 10564 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 4105 | /* 10568 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4106 | /* 10570 */ // (sub:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm, rGPR:{ *:[i32] }:$Rn) => (t2RSBri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 4107 | /* 10570 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2RSBri), |
| 4108 | /* 10573 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 4109 | /* 10575 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 4110 | /* 10577 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 4111 | /* 10580 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4112 | /* 10583 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4113 | /* 10589 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4114 | /* 10595 */ GIR_RootConstrainSelectedInstOperands, |
| 4115 | /* 10596 */ // GIR_Coverage, 427, |
| 4116 | /* 10596 */ GIR_EraseRootFromParent_Done, |
| 4117 | /* 10597 */ // Label 236: @10597 |
| 4118 | /* 10597 */ GIM_Try, /*On fail goto*//*Label 237*/ GIMT_Encode4(10654), // Rule ID 76 // |
| 4119 | /* 10602 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 4120 | /* 10605 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 4121 | /* 10609 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 4122 | /* 10613 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4123 | /* 10617 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 4124 | /* 10621 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm), |
| 4125 | /* 10625 */ // MIs[1] Operand 1 |
| 4126 | /* 10625 */ // No operand predicates |
| 4127 | /* 10625 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4128 | /* 10627 */ // (sub:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm) => (SUBri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 4129 | /* 10627 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SUBri), |
| 4130 | /* 10630 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 4131 | /* 10632 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 4132 | /* 10634 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 4133 | /* 10637 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4134 | /* 10640 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4135 | /* 10646 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4136 | /* 10652 */ GIR_RootConstrainSelectedInstOperands, |
| 4137 | /* 10653 */ // GIR_Coverage, 76, |
| 4138 | /* 10653 */ GIR_EraseRootFromParent_Done, |
| 4139 | /* 10654 */ // Label 237: @10654 |
| 4140 | /* 10654 */ GIM_Try, /*On fail goto*//*Label 238*/ GIMT_Encode4(10711), // Rule ID 411 // |
| 4141 | /* 10659 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 4142 | /* 10662 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 4143 | /* 10666 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 4144 | /* 10670 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4145 | /* 10674 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 4146 | /* 10678 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm), |
| 4147 | /* 10682 */ // MIs[1] Operand 1 |
| 4148 | /* 10682 */ // No operand predicates |
| 4149 | /* 10682 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4150 | /* 10684 */ // (sub:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm) => (t2SUBri:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 4151 | /* 10684 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SUBri), |
| 4152 | /* 10687 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 4153 | /* 10689 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 4154 | /* 10691 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 4155 | /* 10694 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4156 | /* 10697 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4157 | /* 10703 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4158 | /* 10709 */ GIR_RootConstrainSelectedInstOperands, |
| 4159 | /* 10710 */ // GIR_Coverage, 411, |
| 4160 | /* 10710 */ GIR_EraseRootFromParent_Done, |
| 4161 | /* 10711 */ // Label 238: @10711 |
| 4162 | /* 10711 */ GIM_Try, /*On fail goto*//*Label 239*/ GIMT_Encode4(10762), // Rule ID 412 // |
| 4163 | /* 10716 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 4164 | /* 10719 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 4165 | /* 10723 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 4166 | /* 10727 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4167 | /* 10731 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 4168 | /* 10735 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_4095), |
| 4169 | /* 10739 */ // MIs[1] Operand 1 |
| 4170 | /* 10739 */ // No operand predicates |
| 4171 | /* 10739 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4172 | /* 10741 */ // (sub:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_imm0_4095>>:$imm) => (t2SUBri12:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 4173 | /* 10741 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SUBri12), |
| 4174 | /* 10744 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 4175 | /* 10746 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 4176 | /* 10748 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 4177 | /* 10751 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4178 | /* 10754 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4179 | /* 10760 */ GIR_RootConstrainSelectedInstOperands, |
| 4180 | /* 10761 */ // GIR_Coverage, 412, |
| 4181 | /* 10761 */ GIR_EraseRootFromParent_Done, |
| 4182 | /* 10762 */ // Label 239: @10762 |
| 4183 | /* 10762 */ GIM_Try, /*On fail goto*//*Label 240*/ GIMT_Encode4(10832), // Rule ID 173 // |
| 4184 | /* 10767 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6T2_IsARM_UseMulOps), |
| 4185 | /* 10770 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 4186 | /* 10774 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 4187 | /* 10778 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4188 | /* 10782 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 4189 | /* 10786 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 4190 | /* 10790 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 4191 | /* 10794 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 4192 | /* 10799 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 4193 | /* 10804 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4194 | /* 10806 */ // (sub:{ *:[i32] } GPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)) => (MLS:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) |
| 4195 | /* 10806 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MLS), |
| 4196 | /* 10809 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 4197 | /* 10811 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 4198 | /* 10815 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm |
| 4199 | /* 10819 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra |
| 4200 | /* 10821 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4201 | /* 10824 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4202 | /* 10830 */ GIR_RootConstrainSelectedInstOperands, |
| 4203 | /* 10831 */ // GIR_Coverage, 173, |
| 4204 | /* 10831 */ GIR_EraseRootFromParent_Done, |
| 4205 | /* 10832 */ // Label 240: @10832 |
| 4206 | /* 10832 */ GIM_Try, /*On fail goto*//*Label 241*/ GIMT_Encode4(10902), // Rule ID 504 // |
| 4207 | /* 10837 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2_UseMulOps), |
| 4208 | /* 10840 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 4209 | /* 10844 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 4210 | /* 10848 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4211 | /* 10852 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 4212 | /* 10856 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 4213 | /* 10860 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 4214 | /* 10864 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 4215 | /* 10869 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 4216 | /* 10874 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4217 | /* 10876 */ // (sub:{ *:[i32] } rGPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)) => (t2MLS:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) |
| 4218 | /* 10876 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MLS), |
| 4219 | /* 10879 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 4220 | /* 10881 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 4221 | /* 10885 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm |
| 4222 | /* 10889 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra |
| 4223 | /* 10891 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4224 | /* 10894 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4225 | /* 10900 */ GIR_RootConstrainSelectedInstOperands, |
| 4226 | /* 10901 */ // GIR_Coverage, 504, |
| 4227 | /* 10901 */ GIR_EraseRootFromParent_Done, |
| 4228 | /* 10902 */ // Label 241: @10902 |
| 4229 | /* 10902 */ GIM_Try, /*On fail goto*//*Label 242*/ GIMT_Encode4(10948), // Rule ID 77 // |
| 4230 | /* 10907 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 4231 | /* 10910 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 4232 | /* 10914 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 4233 | /* 10918 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 4234 | /* 10922 */ // (sub:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (SUBrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) |
| 4235 | /* 10922 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SUBrr), |
| 4236 | /* 10925 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 4237 | /* 10927 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 4238 | /* 10929 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 4239 | /* 10931 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4240 | /* 10934 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4241 | /* 10940 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4242 | /* 10946 */ GIR_RootConstrainSelectedInstOperands, |
| 4243 | /* 10947 */ // GIR_Coverage, 77, |
| 4244 | /* 10947 */ GIR_EraseRootFromParent_Done, |
| 4245 | /* 10948 */ // Label 242: @10948 |
| 4246 | /* 10948 */ GIM_Try, /*On fail goto*//*Label 243*/ GIMT_Encode4(10994), // Rule ID 333 // |
| 4247 | /* 10953 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), |
| 4248 | /* 10956 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 4249 | /* 10960 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 4250 | /* 10964 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 4251 | /* 10968 */ // (sub:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) => (tSUBrr:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) |
| 4252 | /* 10968 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tSUBrr), |
| 4253 | /* 10971 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 4254 | /* 10973 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define | RegState::Dead), |
| 4255 | /* 10979 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 4256 | /* 10981 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 4257 | /* 10983 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4258 | /* 10986 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4259 | /* 10992 */ GIR_RootConstrainSelectedInstOperands, |
| 4260 | /* 10993 */ // GIR_Coverage, 333, |
| 4261 | /* 10993 */ GIR_EraseRootFromParent_Done, |
| 4262 | /* 10994 */ // Label 243: @10994 |
| 4263 | /* 10994 */ GIM_Try, /*On fail goto*//*Label 244*/ GIMT_Encode4(11040), // Rule ID 413 // |
| 4264 | /* 10999 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 4265 | /* 11002 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 4266 | /* 11006 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 4267 | /* 11010 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 4268 | /* 11014 */ // (sub:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SUBrr:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 4269 | /* 11014 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SUBrr), |
| 4270 | /* 11017 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 4271 | /* 11019 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 4272 | /* 11021 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 4273 | /* 11023 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4274 | /* 11026 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4275 | /* 11032 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4276 | /* 11038 */ GIR_RootConstrainSelectedInstOperands, |
| 4277 | /* 11039 */ // GIR_Coverage, 413, |
| 4278 | /* 11039 */ GIR_EraseRootFromParent_Done, |
| 4279 | /* 11040 */ // Label 244: @11040 |
| 4280 | /* 11040 */ GIM_Reject, |
| 4281 | /* 11041 */ // Label 233: @11041 |
| 4282 | /* 11041 */ GIM_Reject, |
| 4283 | /* 11042 */ // Label 224: @11042 |
| 4284 | /* 11042 */ GIM_Try, /*On fail goto*//*Label 245*/ GIMT_Encode4(11088), // Rule ID 966 // |
| 4285 | /* 11047 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 4286 | /* 11050 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 4287 | /* 11053 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 4288 | /* 11056 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4289 | /* 11060 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4290 | /* 11064 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4291 | /* 11068 */ // (sub:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) => (VSUBv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) |
| 4292 | /* 11068 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBv1i64), |
| 4293 | /* 11071 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4294 | /* 11073 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 4295 | /* 11075 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 4296 | /* 11077 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4297 | /* 11080 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4298 | /* 11086 */ GIR_RootConstrainSelectedInstOperands, |
| 4299 | /* 11087 */ // GIR_Coverage, 966, |
| 4300 | /* 11087 */ GIR_EraseRootFromParent_Done, |
| 4301 | /* 11088 */ // Label 245: @11088 |
| 4302 | /* 11088 */ GIM_Reject, |
| 4303 | /* 11089 */ // Label 225: @11089 |
| 4304 | /* 11089 */ GIM_Try, /*On fail goto*//*Label 246*/ GIMT_Encode4(11203), |
| 4305 | /* 11094 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 4306 | /* 11097 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 4307 | /* 11100 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4308 | /* 11104 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4309 | /* 11108 */ GIM_Try, /*On fail goto*//*Label 247*/ GIMT_Encode4(11170), // Rule ID 917 // |
| 4310 | /* 11113 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 4311 | /* 11116 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4312 | /* 11120 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 4313 | /* 11124 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 4314 | /* 11128 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, |
| 4315 | /* 11132 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4316 | /* 11137 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4317 | /* 11142 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4318 | /* 11144 */ // (sub:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, (mul:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)) => (VMLSv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 4319 | /* 11144 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLSv2i32), |
| 4320 | /* 11147 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4321 | /* 11149 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 4322 | /* 11151 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 4323 | /* 11155 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 4324 | /* 11159 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4325 | /* 11162 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4326 | /* 11168 */ GIR_RootConstrainSelectedInstOperands, |
| 4327 | /* 11169 */ // GIR_Coverage, 917, |
| 4328 | /* 11169 */ GIR_EraseRootFromParent_Done, |
| 4329 | /* 11170 */ // Label 247: @11170 |
| 4330 | /* 11170 */ GIM_Try, /*On fail goto*//*Label 248*/ GIMT_Encode4(11202), // Rule ID 962 // |
| 4331 | /* 11175 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 4332 | /* 11178 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4333 | /* 11182 */ // (sub:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VSUBv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 4334 | /* 11182 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBv2i32), |
| 4335 | /* 11185 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4336 | /* 11187 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 4337 | /* 11189 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 4338 | /* 11191 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4339 | /* 11194 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4340 | /* 11200 */ GIR_RootConstrainSelectedInstOperands, |
| 4341 | /* 11201 */ // GIR_Coverage, 962, |
| 4342 | /* 11201 */ GIR_EraseRootFromParent_Done, |
| 4343 | /* 11202 */ // Label 248: @11202 |
| 4344 | /* 11202 */ GIM_Reject, |
| 4345 | /* 11203 */ // Label 246: @11203 |
| 4346 | /* 11203 */ GIM_Reject, |
| 4347 | /* 11204 */ // Label 226: @11204 |
| 4348 | /* 11204 */ GIM_Try, /*On fail goto*//*Label 249*/ GIMT_Encode4(11755), |
| 4349 | /* 11209 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 4350 | /* 11212 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 4351 | /* 11215 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4352 | /* 11219 */ GIM_Try, /*On fail goto*//*Label 250*/ GIMT_Encode4(11287), // Rule ID 986 // |
| 4353 | /* 11224 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 4354 | /* 11227 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4355 | /* 11231 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 4356 | /* 11235 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 4357 | /* 11239 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4358 | /* 11244 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 4359 | /* 11248 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 4360 | /* 11252 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, |
| 4361 | /* 11256 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4362 | /* 11261 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 4363 | /* 11263 */ // (sub:{ *:[v2i64] } (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VSUBLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 4364 | /* 11263 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv2i64), |
| 4365 | /* 11266 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4366 | /* 11268 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 4367 | /* 11272 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 4368 | /* 11276 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4369 | /* 11279 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4370 | /* 11285 */ GIR_RootConstrainSelectedInstOperands, |
| 4371 | /* 11286 */ // GIR_Coverage, 986, |
| 4372 | /* 11286 */ GIR_EraseRootFromParent_Done, |
| 4373 | /* 11287 */ // Label 250: @11287 |
| 4374 | /* 11287 */ GIM_Try, /*On fail goto*//*Label 251*/ GIMT_Encode4(11355), // Rule ID 985 // |
| 4375 | /* 11292 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 4376 | /* 11295 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4377 | /* 11299 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 4378 | /* 11303 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 4379 | /* 11307 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4380 | /* 11312 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 4381 | /* 11316 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 4382 | /* 11320 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, |
| 4383 | /* 11324 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4384 | /* 11329 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 4385 | /* 11331 */ // (sub:{ *:[v2i64] } (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VSUBLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 4386 | /* 11331 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv2i64), |
| 4387 | /* 11334 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4388 | /* 11336 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 4389 | /* 11340 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 4390 | /* 11344 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4391 | /* 11347 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4392 | /* 11353 */ GIR_RootConstrainSelectedInstOperands, |
| 4393 | /* 11354 */ // GIR_Coverage, 985, |
| 4394 | /* 11354 */ GIR_EraseRootFromParent_Done, |
| 4395 | /* 11355 */ // Label 251: @11355 |
| 4396 | /* 11355 */ GIM_Try, /*On fail goto*//*Label 252*/ GIMT_Encode4(11423), // Rule ID 974 // |
| 4397 | /* 11360 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 4398 | /* 11363 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4399 | /* 11367 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT), |
| 4400 | /* 11371 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 4401 | /* 11375 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4402 | /* 11380 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 4403 | /* 11384 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT), |
| 4404 | /* 11388 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, |
| 4405 | /* 11392 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4406 | /* 11397 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 4407 | /* 11399 */ // (sub:{ *:[v2i64] } (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VSUBLsv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 4408 | /* 11399 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLsv2i64), |
| 4409 | /* 11402 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4410 | /* 11404 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 4411 | /* 11408 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 4412 | /* 11412 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4413 | /* 11415 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4414 | /* 11421 */ GIR_RootConstrainSelectedInstOperands, |
| 4415 | /* 11422 */ // GIR_Coverage, 974, |
| 4416 | /* 11422 */ GIR_EraseRootFromParent_Done, |
| 4417 | /* 11423 */ // Label 252: @11423 |
| 4418 | /* 11423 */ GIM_Try, /*On fail goto*//*Label 253*/ GIMT_Encode4(11491), // Rule ID 984 // |
| 4419 | /* 11428 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 4420 | /* 11431 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4421 | /* 11435 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 4422 | /* 11439 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 4423 | /* 11443 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4424 | /* 11448 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 4425 | /* 11452 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 4426 | /* 11456 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, |
| 4427 | /* 11460 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4428 | /* 11465 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 4429 | /* 11467 */ // (sub:{ *:[v2i64] } (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VSUBLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 4430 | /* 11467 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv2i64), |
| 4431 | /* 11470 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4432 | /* 11472 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 4433 | /* 11476 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 4434 | /* 11480 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4435 | /* 11483 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4436 | /* 11489 */ GIR_RootConstrainSelectedInstOperands, |
| 4437 | /* 11490 */ // GIR_Coverage, 984, |
| 4438 | /* 11490 */ GIR_EraseRootFromParent_Done, |
| 4439 | /* 11491 */ // Label 253: @11491 |
| 4440 | /* 11491 */ GIM_Try, /*On fail goto*//*Label 254*/ GIMT_Encode4(11559), // Rule ID 983 // |
| 4441 | /* 11496 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 4442 | /* 11499 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4443 | /* 11503 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 4444 | /* 11507 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 4445 | /* 11511 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4446 | /* 11516 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 4447 | /* 11520 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 4448 | /* 11524 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, |
| 4449 | /* 11528 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4450 | /* 11533 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 4451 | /* 11535 */ // (sub:{ *:[v2i64] } (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VSUBLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 4452 | /* 11535 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv2i64), |
| 4453 | /* 11538 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4454 | /* 11540 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 4455 | /* 11544 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 4456 | /* 11548 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4457 | /* 11551 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4458 | /* 11557 */ GIR_RootConstrainSelectedInstOperands, |
| 4459 | /* 11558 */ // GIR_Coverage, 983, |
| 4460 | /* 11558 */ GIR_EraseRootFromParent_Done, |
| 4461 | /* 11559 */ // Label 254: @11559 |
| 4462 | /* 11559 */ GIM_Try, /*On fail goto*//*Label 255*/ GIMT_Encode4(11612), // Rule ID 995 // |
| 4463 | /* 11564 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 4464 | /* 11567 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4465 | /* 11571 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4466 | /* 11575 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 4467 | /* 11579 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 4468 | /* 11583 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4469 | /* 11588 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4470 | /* 11590 */ // (sub:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VSUBWuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 4471 | /* 11590 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBWuv2i64), |
| 4472 | /* 11593 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4473 | /* 11595 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 4474 | /* 11597 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 4475 | /* 11601 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4476 | /* 11604 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4477 | /* 11610 */ GIR_RootConstrainSelectedInstOperands, |
| 4478 | /* 11611 */ // GIR_Coverage, 995, |
| 4479 | /* 11611 */ GIR_EraseRootFromParent_Done, |
| 4480 | /* 11612 */ // Label 255: @11612 |
| 4481 | /* 11612 */ GIM_Try, /*On fail goto*//*Label 256*/ GIMT_Encode4(11665), // Rule ID 989 // |
| 4482 | /* 11617 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 4483 | /* 11620 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4484 | /* 11624 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4485 | /* 11628 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT), |
| 4486 | /* 11632 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 4487 | /* 11636 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4488 | /* 11641 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4489 | /* 11643 */ // (sub:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VSUBWsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 4490 | /* 11643 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBWsv2i64), |
| 4491 | /* 11646 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4492 | /* 11648 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 4493 | /* 11650 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 4494 | /* 11654 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4495 | /* 11657 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4496 | /* 11663 */ GIR_RootConstrainSelectedInstOperands, |
| 4497 | /* 11664 */ // GIR_Coverage, 989, |
| 4498 | /* 11664 */ GIR_EraseRootFromParent_Done, |
| 4499 | /* 11665 */ // Label 256: @11665 |
| 4500 | /* 11665 */ GIM_Try, /*On fail goto*//*Label 257*/ GIMT_Encode4(11718), // Rule ID 994 // |
| 4501 | /* 11670 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 4502 | /* 11673 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4503 | /* 11677 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4504 | /* 11681 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 4505 | /* 11685 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 4506 | /* 11689 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4507 | /* 11694 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4508 | /* 11696 */ // (sub:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VSUBWuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 4509 | /* 11696 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBWuv2i64), |
| 4510 | /* 11699 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4511 | /* 11701 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 4512 | /* 11703 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 4513 | /* 11707 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4514 | /* 11710 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4515 | /* 11716 */ GIR_RootConstrainSelectedInstOperands, |
| 4516 | /* 11717 */ // GIR_Coverage, 994, |
| 4517 | /* 11717 */ GIR_EraseRootFromParent_Done, |
| 4518 | /* 11718 */ // Label 257: @11718 |
| 4519 | /* 11718 */ GIM_Try, /*On fail goto*//*Label 258*/ GIMT_Encode4(11754), // Rule ID 967 // |
| 4520 | /* 11723 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 4521 | /* 11726 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4522 | /* 11730 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4523 | /* 11734 */ // (sub:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) => (VSUBv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) |
| 4524 | /* 11734 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBv2i64), |
| 4525 | /* 11737 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4526 | /* 11739 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 4527 | /* 11741 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 4528 | /* 11743 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4529 | /* 11746 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4530 | /* 11752 */ GIR_RootConstrainSelectedInstOperands, |
| 4531 | /* 11753 */ // GIR_Coverage, 967, |
| 4532 | /* 11753 */ GIR_EraseRootFromParent_Done, |
| 4533 | /* 11754 */ // Label 258: @11754 |
| 4534 | /* 11754 */ GIM_Reject, |
| 4535 | /* 11755 */ // Label 249: @11755 |
| 4536 | /* 11755 */ GIM_Reject, |
| 4537 | /* 11756 */ // Label 227: @11756 |
| 4538 | /* 11756 */ GIM_Try, /*On fail goto*//*Label 259*/ GIMT_Encode4(11870), |
| 4539 | /* 11761 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 4540 | /* 11764 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 4541 | /* 11767 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4542 | /* 11771 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4543 | /* 11775 */ GIM_Try, /*On fail goto*//*Label 260*/ GIMT_Encode4(11837), // Rule ID 916 // |
| 4544 | /* 11780 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 4545 | /* 11783 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4546 | /* 11787 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 4547 | /* 11791 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 4548 | /* 11795 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 4549 | /* 11799 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4550 | /* 11804 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4551 | /* 11809 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4552 | /* 11811 */ // (sub:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, (mul:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)) => (VMLSv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 4553 | /* 11811 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLSv4i16), |
| 4554 | /* 11814 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4555 | /* 11816 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 4556 | /* 11818 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 4557 | /* 11822 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 4558 | /* 11826 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4559 | /* 11829 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4560 | /* 11835 */ GIR_RootConstrainSelectedInstOperands, |
| 4561 | /* 11836 */ // GIR_Coverage, 916, |
| 4562 | /* 11836 */ GIR_EraseRootFromParent_Done, |
| 4563 | /* 11837 */ // Label 260: @11837 |
| 4564 | /* 11837 */ GIM_Try, /*On fail goto*//*Label 261*/ GIMT_Encode4(11869), // Rule ID 961 // |
| 4565 | /* 11842 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 4566 | /* 11845 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4567 | /* 11849 */ // (sub:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VSUBv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 4568 | /* 11849 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBv4i16), |
| 4569 | /* 11852 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4570 | /* 11854 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 4571 | /* 11856 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 4572 | /* 11858 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4573 | /* 11861 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4574 | /* 11867 */ GIR_RootConstrainSelectedInstOperands, |
| 4575 | /* 11868 */ // GIR_Coverage, 961, |
| 4576 | /* 11868 */ GIR_EraseRootFromParent_Done, |
| 4577 | /* 11869 */ // Label 261: @11869 |
| 4578 | /* 11869 */ GIM_Reject, |
| 4579 | /* 11870 */ // Label 259: @11870 |
| 4580 | /* 11870 */ GIM_Reject, |
| 4581 | /* 11871 */ // Label 228: @11871 |
| 4582 | /* 11871 */ GIM_Try, /*On fail goto*//*Label 262*/ GIMT_Encode4(12585), |
| 4583 | /* 11876 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 4584 | /* 11879 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 4585 | /* 11882 */ GIM_Try, /*On fail goto*//*Label 263*/ GIMT_Encode4(11954), // Rule ID 982 // |
| 4586 | /* 11887 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 4587 | /* 11890 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4588 | /* 11894 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4589 | /* 11898 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 4590 | /* 11902 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 4591 | /* 11906 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4592 | /* 11911 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 4593 | /* 11915 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 4594 | /* 11919 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, |
| 4595 | /* 11923 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4596 | /* 11928 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 4597 | /* 11930 */ // (sub:{ *:[v4i32] } (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VSUBLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 4598 | /* 11930 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv4i32), |
| 4599 | /* 11933 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4600 | /* 11935 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 4601 | /* 11939 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 4602 | /* 11943 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4603 | /* 11946 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4604 | /* 11952 */ GIR_RootConstrainSelectedInstOperands, |
| 4605 | /* 11953 */ // GIR_Coverage, 982, |
| 4606 | /* 11953 */ GIR_EraseRootFromParent_Done, |
| 4607 | /* 11954 */ // Label 263: @11954 |
| 4608 | /* 11954 */ GIM_Try, /*On fail goto*//*Label 264*/ GIMT_Encode4(12026), // Rule ID 981 // |
| 4609 | /* 11959 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 4610 | /* 11962 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4611 | /* 11966 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4612 | /* 11970 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 4613 | /* 11974 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 4614 | /* 11978 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4615 | /* 11983 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 4616 | /* 11987 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 4617 | /* 11991 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, |
| 4618 | /* 11995 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4619 | /* 12000 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 4620 | /* 12002 */ // (sub:{ *:[v4i32] } (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VSUBLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 4621 | /* 12002 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv4i32), |
| 4622 | /* 12005 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4623 | /* 12007 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 4624 | /* 12011 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 4625 | /* 12015 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4626 | /* 12018 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4627 | /* 12024 */ GIR_RootConstrainSelectedInstOperands, |
| 4628 | /* 12025 */ // GIR_Coverage, 981, |
| 4629 | /* 12025 */ GIR_EraseRootFromParent_Done, |
| 4630 | /* 12026 */ // Label 264: @12026 |
| 4631 | /* 12026 */ GIM_Try, /*On fail goto*//*Label 265*/ GIMT_Encode4(12098), // Rule ID 973 // |
| 4632 | /* 12031 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 4633 | /* 12034 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4634 | /* 12038 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4635 | /* 12042 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT), |
| 4636 | /* 12046 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 4637 | /* 12050 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4638 | /* 12055 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 4639 | /* 12059 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT), |
| 4640 | /* 12063 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, |
| 4641 | /* 12067 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4642 | /* 12072 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 4643 | /* 12074 */ // (sub:{ *:[v4i32] } (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VSUBLsv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 4644 | /* 12074 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLsv4i32), |
| 4645 | /* 12077 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4646 | /* 12079 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 4647 | /* 12083 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 4648 | /* 12087 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4649 | /* 12090 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4650 | /* 12096 */ GIR_RootConstrainSelectedInstOperands, |
| 4651 | /* 12097 */ // GIR_Coverage, 973, |
| 4652 | /* 12097 */ GIR_EraseRootFromParent_Done, |
| 4653 | /* 12098 */ // Label 265: @12098 |
| 4654 | /* 12098 */ GIM_Try, /*On fail goto*//*Label 266*/ GIMT_Encode4(12170), // Rule ID 980 // |
| 4655 | /* 12103 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 4656 | /* 12106 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4657 | /* 12110 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4658 | /* 12114 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 4659 | /* 12118 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 4660 | /* 12122 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4661 | /* 12127 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 4662 | /* 12131 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 4663 | /* 12135 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, |
| 4664 | /* 12139 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4665 | /* 12144 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 4666 | /* 12146 */ // (sub:{ *:[v4i32] } (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VSUBLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 4667 | /* 12146 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv4i32), |
| 4668 | /* 12149 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4669 | /* 12151 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 4670 | /* 12155 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 4671 | /* 12159 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4672 | /* 12162 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4673 | /* 12168 */ GIR_RootConstrainSelectedInstOperands, |
| 4674 | /* 12169 */ // GIR_Coverage, 980, |
| 4675 | /* 12169 */ GIR_EraseRootFromParent_Done, |
| 4676 | /* 12170 */ // Label 266: @12170 |
| 4677 | /* 12170 */ GIM_Try, /*On fail goto*//*Label 267*/ GIMT_Encode4(12242), // Rule ID 979 // |
| 4678 | /* 12175 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 4679 | /* 12178 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4680 | /* 12182 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4681 | /* 12186 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 4682 | /* 12190 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 4683 | /* 12194 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4684 | /* 12199 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 4685 | /* 12203 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 4686 | /* 12207 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, |
| 4687 | /* 12211 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4688 | /* 12216 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 4689 | /* 12218 */ // (sub:{ *:[v4i32] } (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VSUBLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 4690 | /* 12218 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv4i32), |
| 4691 | /* 12221 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4692 | /* 12223 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 4693 | /* 12227 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 4694 | /* 12231 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4695 | /* 12234 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4696 | /* 12240 */ GIR_RootConstrainSelectedInstOperands, |
| 4697 | /* 12241 */ // GIR_Coverage, 979, |
| 4698 | /* 12241 */ GIR_EraseRootFromParent_Done, |
| 4699 | /* 12242 */ // Label 267: @12242 |
| 4700 | /* 12242 */ GIM_Try, /*On fail goto*//*Label 268*/ GIMT_Encode4(12312), // Rule ID 920 // |
| 4701 | /* 12247 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 4702 | /* 12250 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4703 | /* 12254 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4704 | /* 12258 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4705 | /* 12262 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 4706 | /* 12266 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 4707 | /* 12270 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 4708 | /* 12274 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4709 | /* 12279 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4710 | /* 12284 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4711 | /* 12286 */ // (sub:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (mul:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)) => (VMLSv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 4712 | /* 12286 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLSv4i32), |
| 4713 | /* 12289 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4714 | /* 12291 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 4715 | /* 12293 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 4716 | /* 12297 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 4717 | /* 12301 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4718 | /* 12304 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4719 | /* 12310 */ GIR_RootConstrainSelectedInstOperands, |
| 4720 | /* 12311 */ // GIR_Coverage, 920, |
| 4721 | /* 12311 */ GIR_EraseRootFromParent_Done, |
| 4722 | /* 12312 */ // Label 268: @12312 |
| 4723 | /* 12312 */ GIM_Try, /*On fail goto*//*Label 269*/ GIMT_Encode4(12369), // Rule ID 993 // |
| 4724 | /* 12317 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 4725 | /* 12320 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4726 | /* 12324 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4727 | /* 12328 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4728 | /* 12332 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 4729 | /* 12336 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 4730 | /* 12340 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4731 | /* 12345 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4732 | /* 12347 */ // (sub:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VSUBWuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 4733 | /* 12347 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBWuv4i32), |
| 4734 | /* 12350 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4735 | /* 12352 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 4736 | /* 12354 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 4737 | /* 12358 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4738 | /* 12361 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4739 | /* 12367 */ GIR_RootConstrainSelectedInstOperands, |
| 4740 | /* 12368 */ // GIR_Coverage, 993, |
| 4741 | /* 12368 */ GIR_EraseRootFromParent_Done, |
| 4742 | /* 12369 */ // Label 269: @12369 |
| 4743 | /* 12369 */ GIM_Try, /*On fail goto*//*Label 270*/ GIMT_Encode4(12426), // Rule ID 988 // |
| 4744 | /* 12374 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 4745 | /* 12377 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4746 | /* 12381 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4747 | /* 12385 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4748 | /* 12389 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT), |
| 4749 | /* 12393 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 4750 | /* 12397 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4751 | /* 12402 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4752 | /* 12404 */ // (sub:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VSUBWsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 4753 | /* 12404 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBWsv4i32), |
| 4754 | /* 12407 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4755 | /* 12409 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 4756 | /* 12411 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 4757 | /* 12415 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4758 | /* 12418 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4759 | /* 12424 */ GIR_RootConstrainSelectedInstOperands, |
| 4760 | /* 12425 */ // GIR_Coverage, 988, |
| 4761 | /* 12425 */ GIR_EraseRootFromParent_Done, |
| 4762 | /* 12426 */ // Label 270: @12426 |
| 4763 | /* 12426 */ GIM_Try, /*On fail goto*//*Label 271*/ GIMT_Encode4(12483), // Rule ID 992 // |
| 4764 | /* 12431 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 4765 | /* 12434 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4766 | /* 12438 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4767 | /* 12442 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4768 | /* 12446 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 4769 | /* 12450 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 4770 | /* 12454 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4771 | /* 12459 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4772 | /* 12461 */ // (sub:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VSUBWuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 4773 | /* 12461 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBWuv4i32), |
| 4774 | /* 12464 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4775 | /* 12466 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 4776 | /* 12468 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 4777 | /* 12472 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4778 | /* 12475 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4779 | /* 12481 */ GIR_RootConstrainSelectedInstOperands, |
| 4780 | /* 12482 */ // GIR_Coverage, 992, |
| 4781 | /* 12482 */ GIR_EraseRootFromParent_Done, |
| 4782 | /* 12483 */ // Label 271: @12483 |
| 4783 | /* 12483 */ GIM_Try, /*On fail goto*//*Label 272*/ GIMT_Encode4(12523), // Rule ID 965 // |
| 4784 | /* 12488 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 4785 | /* 12491 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4786 | /* 12495 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4787 | /* 12499 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4788 | /* 12503 */ // (sub:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VSUBv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 4789 | /* 12503 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBv4i32), |
| 4790 | /* 12506 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4791 | /* 12508 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 4792 | /* 12510 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 4793 | /* 12512 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4794 | /* 12515 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4795 | /* 12521 */ GIR_RootConstrainSelectedInstOperands, |
| 4796 | /* 12522 */ // GIR_Coverage, 965, |
| 4797 | /* 12522 */ GIR_EraseRootFromParent_Done, |
| 4798 | /* 12523 */ // Label 272: @12523 |
| 4799 | /* 12523 */ GIM_Try, /*On fail goto*//*Label 273*/ GIMT_Encode4(12584), // Rule ID 3508 // |
| 4800 | /* 12528 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 4801 | /* 12531 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 4802 | /* 12535 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 4803 | /* 12539 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 4804 | /* 12543 */ // (sub:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VSUBi32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 4805 | /* 12543 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 4806 | /* 12546 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 4807 | /* 12550 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 4808 | /* 12555 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSUBi32), |
| 4809 | /* 12558 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 4810 | /* 12560 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 4811 | /* 12562 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 4812 | /* 12564 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 4813 | /* 12567 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4814 | /* 12573 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4815 | /* 12579 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 4816 | /* 12582 */ GIR_RootConstrainSelectedInstOperands, |
| 4817 | /* 12583 */ // GIR_Coverage, 3508, |
| 4818 | /* 12583 */ GIR_EraseRootFromParent_Done, |
| 4819 | /* 12584 */ // Label 273: @12584 |
| 4820 | /* 12584 */ GIM_Reject, |
| 4821 | /* 12585 */ // Label 262: @12585 |
| 4822 | /* 12585 */ GIM_Reject, |
| 4823 | /* 12586 */ // Label 229: @12586 |
| 4824 | /* 12586 */ GIM_Try, /*On fail goto*//*Label 274*/ GIMT_Encode4(12700), |
| 4825 | /* 12591 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 4826 | /* 12594 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 4827 | /* 12597 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4828 | /* 12601 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4829 | /* 12605 */ GIM_Try, /*On fail goto*//*Label 275*/ GIMT_Encode4(12667), // Rule ID 915 // |
| 4830 | /* 12610 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 4831 | /* 12613 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4832 | /* 12617 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 4833 | /* 12621 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 4834 | /* 12625 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, |
| 4835 | /* 12629 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4836 | /* 12634 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4837 | /* 12639 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4838 | /* 12641 */ // (sub:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, (mul:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)) => (VMLSv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 4839 | /* 12641 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLSv8i8), |
| 4840 | /* 12644 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4841 | /* 12646 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 4842 | /* 12648 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 4843 | /* 12652 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 4844 | /* 12656 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4845 | /* 12659 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4846 | /* 12665 */ GIR_RootConstrainSelectedInstOperands, |
| 4847 | /* 12666 */ // GIR_Coverage, 915, |
| 4848 | /* 12666 */ GIR_EraseRootFromParent_Done, |
| 4849 | /* 12667 */ // Label 275: @12667 |
| 4850 | /* 12667 */ GIM_Try, /*On fail goto*//*Label 276*/ GIMT_Encode4(12699), // Rule ID 960 // |
| 4851 | /* 12672 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 4852 | /* 12675 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4853 | /* 12679 */ // (sub:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VSUBv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 4854 | /* 12679 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBv8i8), |
| 4855 | /* 12682 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4856 | /* 12684 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 4857 | /* 12686 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 4858 | /* 12688 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4859 | /* 12691 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4860 | /* 12697 */ GIR_RootConstrainSelectedInstOperands, |
| 4861 | /* 12698 */ // GIR_Coverage, 960, |
| 4862 | /* 12698 */ GIR_EraseRootFromParent_Done, |
| 4863 | /* 12699 */ // Label 276: @12699 |
| 4864 | /* 12699 */ GIM_Reject, |
| 4865 | /* 12700 */ // Label 274: @12700 |
| 4866 | /* 12700 */ GIM_Reject, |
| 4867 | /* 12701 */ // Label 230: @12701 |
| 4868 | /* 12701 */ GIM_Try, /*On fail goto*//*Label 277*/ GIMT_Encode4(13415), |
| 4869 | /* 12706 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 4870 | /* 12709 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 4871 | /* 12712 */ GIM_Try, /*On fail goto*//*Label 278*/ GIMT_Encode4(12784), // Rule ID 978 // |
| 4872 | /* 12717 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 4873 | /* 12720 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4874 | /* 12724 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4875 | /* 12728 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 4876 | /* 12732 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 4877 | /* 12736 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4878 | /* 12741 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 4879 | /* 12745 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 4880 | /* 12749 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, |
| 4881 | /* 12753 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4882 | /* 12758 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 4883 | /* 12760 */ // (sub:{ *:[v8i16] } (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VSUBLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 4884 | /* 12760 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv8i16), |
| 4885 | /* 12763 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4886 | /* 12765 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 4887 | /* 12769 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 4888 | /* 12773 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4889 | /* 12776 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4890 | /* 12782 */ GIR_RootConstrainSelectedInstOperands, |
| 4891 | /* 12783 */ // GIR_Coverage, 978, |
| 4892 | /* 12783 */ GIR_EraseRootFromParent_Done, |
| 4893 | /* 12784 */ // Label 278: @12784 |
| 4894 | /* 12784 */ GIM_Try, /*On fail goto*//*Label 279*/ GIMT_Encode4(12856), // Rule ID 977 // |
| 4895 | /* 12789 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 4896 | /* 12792 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4897 | /* 12796 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4898 | /* 12800 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 4899 | /* 12804 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 4900 | /* 12808 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4901 | /* 12813 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 4902 | /* 12817 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 4903 | /* 12821 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, |
| 4904 | /* 12825 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4905 | /* 12830 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 4906 | /* 12832 */ // (sub:{ *:[v8i16] } (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VSUBLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 4907 | /* 12832 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv8i16), |
| 4908 | /* 12835 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4909 | /* 12837 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 4910 | /* 12841 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 4911 | /* 12845 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4912 | /* 12848 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4913 | /* 12854 */ GIR_RootConstrainSelectedInstOperands, |
| 4914 | /* 12855 */ // GIR_Coverage, 977, |
| 4915 | /* 12855 */ GIR_EraseRootFromParent_Done, |
| 4916 | /* 12856 */ // Label 279: @12856 |
| 4917 | /* 12856 */ GIM_Try, /*On fail goto*//*Label 280*/ GIMT_Encode4(12928), // Rule ID 972 // |
| 4918 | /* 12861 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 4919 | /* 12864 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4920 | /* 12868 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4921 | /* 12872 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT), |
| 4922 | /* 12876 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 4923 | /* 12880 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4924 | /* 12885 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 4925 | /* 12889 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT), |
| 4926 | /* 12893 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, |
| 4927 | /* 12897 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4928 | /* 12902 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 4929 | /* 12904 */ // (sub:{ *:[v8i16] } (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VSUBLsv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 4930 | /* 12904 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLsv8i16), |
| 4931 | /* 12907 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4932 | /* 12909 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 4933 | /* 12913 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 4934 | /* 12917 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4935 | /* 12920 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4936 | /* 12926 */ GIR_RootConstrainSelectedInstOperands, |
| 4937 | /* 12927 */ // GIR_Coverage, 972, |
| 4938 | /* 12927 */ GIR_EraseRootFromParent_Done, |
| 4939 | /* 12928 */ // Label 280: @12928 |
| 4940 | /* 12928 */ GIM_Try, /*On fail goto*//*Label 281*/ GIMT_Encode4(13000), // Rule ID 976 // |
| 4941 | /* 12933 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 4942 | /* 12936 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4943 | /* 12940 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4944 | /* 12944 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 4945 | /* 12948 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 4946 | /* 12952 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4947 | /* 12957 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 4948 | /* 12961 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 4949 | /* 12965 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, |
| 4950 | /* 12969 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4951 | /* 12974 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 4952 | /* 12976 */ // (sub:{ *:[v8i16] } (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VSUBLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 4953 | /* 12976 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv8i16), |
| 4954 | /* 12979 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4955 | /* 12981 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 4956 | /* 12985 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 4957 | /* 12989 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4958 | /* 12992 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4959 | /* 12998 */ GIR_RootConstrainSelectedInstOperands, |
| 4960 | /* 12999 */ // GIR_Coverage, 976, |
| 4961 | /* 12999 */ GIR_EraseRootFromParent_Done, |
| 4962 | /* 13000 */ // Label 281: @13000 |
| 4963 | /* 13000 */ GIM_Try, /*On fail goto*//*Label 282*/ GIMT_Encode4(13072), // Rule ID 975 // |
| 4964 | /* 13005 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 4965 | /* 13008 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4966 | /* 13012 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4967 | /* 13016 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 4968 | /* 13020 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 4969 | /* 13024 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4970 | /* 13029 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 4971 | /* 13033 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 4972 | /* 13037 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, |
| 4973 | /* 13041 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4974 | /* 13046 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 4975 | /* 13048 */ // (sub:{ *:[v8i16] } (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VSUBLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 4976 | /* 13048 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv8i16), |
| 4977 | /* 13051 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4978 | /* 13053 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 4979 | /* 13057 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 4980 | /* 13061 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4981 | /* 13064 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4982 | /* 13070 */ GIR_RootConstrainSelectedInstOperands, |
| 4983 | /* 13071 */ // GIR_Coverage, 975, |
| 4984 | /* 13071 */ GIR_EraseRootFromParent_Done, |
| 4985 | /* 13072 */ // Label 282: @13072 |
| 4986 | /* 13072 */ GIM_Try, /*On fail goto*//*Label 283*/ GIMT_Encode4(13142), // Rule ID 919 // |
| 4987 | /* 13077 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 4988 | /* 13080 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4989 | /* 13084 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4990 | /* 13088 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4991 | /* 13092 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 4992 | /* 13096 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 4993 | /* 13100 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 4994 | /* 13104 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4995 | /* 13109 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4996 | /* 13114 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4997 | /* 13116 */ // (sub:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, (mul:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)) => (VMLSv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 4998 | /* 13116 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLSv8i16), |
| 4999 | /* 13119 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5000 | /* 13121 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 5001 | /* 13123 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 5002 | /* 13127 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 5003 | /* 13131 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5004 | /* 13134 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5005 | /* 13140 */ GIR_RootConstrainSelectedInstOperands, |
| 5006 | /* 13141 */ // GIR_Coverage, 919, |
| 5007 | /* 13141 */ GIR_EraseRootFromParent_Done, |
| 5008 | /* 13142 */ // Label 283: @13142 |
| 5009 | /* 13142 */ GIM_Try, /*On fail goto*//*Label 284*/ GIMT_Encode4(13199), // Rule ID 991 // |
| 5010 | /* 13147 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 5011 | /* 13150 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5012 | /* 13154 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5013 | /* 13158 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 5014 | /* 13162 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 5015 | /* 13166 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 5016 | /* 13170 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5017 | /* 13175 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 5018 | /* 13177 */ // (sub:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VSUBWuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 5019 | /* 13177 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBWuv8i16), |
| 5020 | /* 13180 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5021 | /* 13182 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 5022 | /* 13184 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 5023 | /* 13188 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5024 | /* 13191 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5025 | /* 13197 */ GIR_RootConstrainSelectedInstOperands, |
| 5026 | /* 13198 */ // GIR_Coverage, 991, |
| 5027 | /* 13198 */ GIR_EraseRootFromParent_Done, |
| 5028 | /* 13199 */ // Label 284: @13199 |
| 5029 | /* 13199 */ GIM_Try, /*On fail goto*//*Label 285*/ GIMT_Encode4(13256), // Rule ID 987 // |
| 5030 | /* 13204 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 5031 | /* 13207 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5032 | /* 13211 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5033 | /* 13215 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 5034 | /* 13219 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT), |
| 5035 | /* 13223 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 5036 | /* 13227 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5037 | /* 13232 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 5038 | /* 13234 */ // (sub:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VSUBWsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 5039 | /* 13234 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBWsv8i16), |
| 5040 | /* 13237 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5041 | /* 13239 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 5042 | /* 13241 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 5043 | /* 13245 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5044 | /* 13248 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5045 | /* 13254 */ GIR_RootConstrainSelectedInstOperands, |
| 5046 | /* 13255 */ // GIR_Coverage, 987, |
| 5047 | /* 13255 */ GIR_EraseRootFromParent_Done, |
| 5048 | /* 13256 */ // Label 285: @13256 |
| 5049 | /* 13256 */ GIM_Try, /*On fail goto*//*Label 286*/ GIMT_Encode4(13313), // Rule ID 990 // |
| 5050 | /* 13261 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 5051 | /* 13264 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5052 | /* 13268 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5053 | /* 13272 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 5054 | /* 13276 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 5055 | /* 13280 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 5056 | /* 13284 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5057 | /* 13289 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 5058 | /* 13291 */ // (sub:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VSUBWuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 5059 | /* 13291 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBWuv8i16), |
| 5060 | /* 13294 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5061 | /* 13296 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 5062 | /* 13298 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 5063 | /* 13302 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5064 | /* 13305 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5065 | /* 13311 */ GIR_RootConstrainSelectedInstOperands, |
| 5066 | /* 13312 */ // GIR_Coverage, 990, |
| 5067 | /* 13312 */ GIR_EraseRootFromParent_Done, |
| 5068 | /* 13313 */ // Label 286: @13313 |
| 5069 | /* 13313 */ GIM_Try, /*On fail goto*//*Label 287*/ GIMT_Encode4(13353), // Rule ID 964 // |
| 5070 | /* 13318 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 5071 | /* 13321 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5072 | /* 13325 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5073 | /* 13329 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5074 | /* 13333 */ // (sub:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VSUBv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 5075 | /* 13333 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBv8i16), |
| 5076 | /* 13336 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5077 | /* 13338 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 5078 | /* 13340 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 5079 | /* 13342 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5080 | /* 13345 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5081 | /* 13351 */ GIR_RootConstrainSelectedInstOperands, |
| 5082 | /* 13352 */ // GIR_Coverage, 964, |
| 5083 | /* 13352 */ GIR_EraseRootFromParent_Done, |
| 5084 | /* 13353 */ // Label 287: @13353 |
| 5085 | /* 13353 */ GIM_Try, /*On fail goto*//*Label 288*/ GIMT_Encode4(13414), // Rule ID 3504 // |
| 5086 | /* 13358 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 5087 | /* 13361 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 5088 | /* 13365 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 5089 | /* 13369 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 5090 | /* 13373 */ // (sub:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VSUBi16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 5091 | /* 13373 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 5092 | /* 13376 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 5093 | /* 13380 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5094 | /* 13385 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSUBi16), |
| 5095 | /* 13388 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 5096 | /* 13390 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 5097 | /* 13392 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 5098 | /* 13394 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 5099 | /* 13397 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5100 | /* 13403 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5101 | /* 13409 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 5102 | /* 13412 */ GIR_RootConstrainSelectedInstOperands, |
| 5103 | /* 13413 */ // GIR_Coverage, 3504, |
| 5104 | /* 13413 */ GIR_EraseRootFromParent_Done, |
| 5105 | /* 13414 */ // Label 288: @13414 |
| 5106 | /* 13414 */ GIM_Reject, |
| 5107 | /* 13415 */ // Label 277: @13415 |
| 5108 | /* 13415 */ GIM_Reject, |
| 5109 | /* 13416 */ // Label 231: @13416 |
| 5110 | /* 13416 */ GIM_Try, /*On fail goto*//*Label 289*/ GIMT_Encode4(13599), |
| 5111 | /* 13421 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 5112 | /* 13424 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 5113 | /* 13427 */ GIM_Try, /*On fail goto*//*Label 290*/ GIMT_Encode4(13497), // Rule ID 918 // |
| 5114 | /* 13432 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 5115 | /* 13435 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5116 | /* 13439 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5117 | /* 13443 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 5118 | /* 13447 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 5119 | /* 13451 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, |
| 5120 | /* 13455 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, |
| 5121 | /* 13459 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5122 | /* 13464 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5123 | /* 13469 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 5124 | /* 13471 */ // (sub:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, (mul:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)) => (VMLSv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 5125 | /* 13471 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLSv16i8), |
| 5126 | /* 13474 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5127 | /* 13476 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 5128 | /* 13478 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 5129 | /* 13482 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 5130 | /* 13486 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5131 | /* 13489 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5132 | /* 13495 */ GIR_RootConstrainSelectedInstOperands, |
| 5133 | /* 13496 */ // GIR_Coverage, 918, |
| 5134 | /* 13496 */ GIR_EraseRootFromParent_Done, |
| 5135 | /* 13497 */ // Label 290: @13497 |
| 5136 | /* 13497 */ GIM_Try, /*On fail goto*//*Label 291*/ GIMT_Encode4(13537), // Rule ID 963 // |
| 5137 | /* 13502 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 5138 | /* 13505 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5139 | /* 13509 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5140 | /* 13513 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5141 | /* 13517 */ // (sub:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VSUBv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 5142 | /* 13517 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBv16i8), |
| 5143 | /* 13520 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5144 | /* 13522 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 5145 | /* 13524 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 5146 | /* 13526 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5147 | /* 13529 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5148 | /* 13535 */ GIR_RootConstrainSelectedInstOperands, |
| 5149 | /* 13536 */ // GIR_Coverage, 963, |
| 5150 | /* 13536 */ GIR_EraseRootFromParent_Done, |
| 5151 | /* 13537 */ // Label 291: @13537 |
| 5152 | /* 13537 */ GIM_Try, /*On fail goto*//*Label 292*/ GIMT_Encode4(13598), // Rule ID 3500 // |
| 5153 | /* 13542 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 5154 | /* 13545 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 5155 | /* 13549 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 5156 | /* 13553 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 5157 | /* 13557 */ // (sub:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VSUBi8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 5158 | /* 13557 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 5159 | /* 13560 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 5160 | /* 13564 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5161 | /* 13569 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSUBi8), |
| 5162 | /* 13572 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 5163 | /* 13574 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 5164 | /* 13576 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 5165 | /* 13578 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 5166 | /* 13581 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5167 | /* 13587 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5168 | /* 13593 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 5169 | /* 13596 */ GIR_RootConstrainSelectedInstOperands, |
| 5170 | /* 13597 */ // GIR_Coverage, 3500, |
| 5171 | /* 13597 */ GIR_EraseRootFromParent_Done, |
| 5172 | /* 13598 */ // Label 292: @13598 |
| 5173 | /* 13598 */ GIM_Reject, |
| 5174 | /* 13599 */ // Label 289: @13599 |
| 5175 | /* 13599 */ GIM_Reject, |
| 5176 | /* 13600 */ // Label 232: @13600 |
| 5177 | /* 13600 */ GIM_Reject, |
| 5178 | /* 13601 */ // Label 2: @13601 |
| 5179 | /* 13601 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(16), /*)*//*default:*//*Label 300*/ GIMT_Encode4(15304), |
| 5180 | /* 13612 */ /*GILLT_s32*//*Label 293*/ GIMT_Encode4(13672), GIMT_Encode4(0), GIMT_Encode4(0), |
| 5181 | /* 13624 */ /*GILLT_v2s32*//*Label 294*/ GIMT_Encode4(14591), GIMT_Encode4(0), GIMT_Encode4(0), |
| 5182 | /* 13636 */ /*GILLT_v4s16*//*Label 295*/ GIMT_Encode4(14638), |
| 5183 | /* 13640 */ /*GILLT_v4s32*//*Label 296*/ GIMT_Encode4(14685), GIMT_Encode4(0), GIMT_Encode4(0), |
| 5184 | /* 13652 */ /*GILLT_v8s8*//*Label 297*/ GIMT_Encode4(14914), |
| 5185 | /* 13656 */ /*GILLT_v8s16*//*Label 298*/ GIMT_Encode4(14961), GIMT_Encode4(0), GIMT_Encode4(0), |
| 5186 | /* 13668 */ /*GILLT_v16s8*//*Label 299*/ GIMT_Encode4(15190), |
| 5187 | /* 13672 */ // Label 293: @13672 |
| 5188 | /* 13672 */ GIM_Try, /*On fail goto*//*Label 301*/ GIMT_Encode4(14590), |
| 5189 | /* 13677 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 5190 | /* 13680 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 5191 | /* 13683 */ GIM_Try, /*On fail goto*//*Label 302*/ GIMT_Encode4(13771), // Rule ID 186 // |
| 5192 | /* 13688 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM), |
| 5193 | /* 13691 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 5194 | /* 13695 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5195 | /* 13699 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 5196 | /* 13703 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 5197 | /* 13707 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 5198 | /* 13711 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 5199 | /* 13716 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16, |
| 5200 | /* 13720 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 5201 | /* 13724 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 5202 | /* 13728 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 5203 | /* 13732 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 5204 | /* 13736 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 5205 | /* 13741 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16, |
| 5206 | /* 13745 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 5207 | /* 13747 */ // (mul:{ *:[i32] } (sra:{ *:[i32] } GPR:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 16:{ *:[i32] })) => (SMULTT:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) |
| 5208 | /* 13747 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMULTT), |
| 5209 | /* 13750 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 5210 | /* 13752 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 5211 | /* 13756 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 5212 | /* 13760 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5213 | /* 13763 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5214 | /* 13769 */ GIR_RootConstrainSelectedInstOperands, |
| 5215 | /* 13770 */ // GIR_Coverage, 186, |
| 5216 | /* 13770 */ GIR_EraseRootFromParent_Done, |
| 5217 | /* 13771 */ // Label 302: @13771 |
| 5218 | /* 13771 */ GIM_Try, /*On fail goto*//*Label 303*/ GIMT_Encode4(13859), // Rule ID 515 // |
| 5219 | /* 13776 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 5220 | /* 13779 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 5221 | /* 13783 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5222 | /* 13787 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 5223 | /* 13791 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 5224 | /* 13795 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 5225 | /* 13799 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 5226 | /* 13804 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16, |
| 5227 | /* 13808 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 5228 | /* 13812 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 5229 | /* 13816 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 5230 | /* 13820 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 5231 | /* 13824 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 5232 | /* 13829 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16, |
| 5233 | /* 13833 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 5234 | /* 13835 */ // (mul:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 16:{ *:[i32] })) => (t2SMULTT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 5235 | /* 13835 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMULTT), |
| 5236 | /* 13838 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 5237 | /* 13840 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 5238 | /* 13844 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 5239 | /* 13848 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5240 | /* 13851 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5241 | /* 13857 */ GIR_RootConstrainSelectedInstOperands, |
| 5242 | /* 13858 */ // GIR_Coverage, 515, |
| 5243 | /* 13858 */ GIR_EraseRootFromParent_Done, |
| 5244 | /* 13859 */ // Label 303: @13859 |
| 5245 | /* 13859 */ GIM_Try, /*On fail goto*//*Label 304*/ GIMT_Encode4(13950), // Rule ID 185 // |
| 5246 | /* 13864 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM), |
| 5247 | /* 13867 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 5248 | /* 13871 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5249 | /* 13875 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 5250 | /* 13879 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 5251 | /* 13883 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 5252 | /* 13887 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 5253 | /* 13892 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16, |
| 5254 | /* 13896 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 5255 | /* 13900 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 5256 | /* 13904 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 5257 | /* 13908 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 5258 | /* 13913 */ // MIs[2] Operand 2 |
| 5259 | /* 13913 */ GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16), |
| 5260 | /* 13924 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 5261 | /* 13926 */ // (mul:{ *:[i32] } (sra:{ *:[i32] } GPR:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sext_inreg:{ *:[i32] } GPR:{ *:[i32] }:$Rm, i16:{ *:[Other] })) => (SMULTB:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) |
| 5262 | /* 13926 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMULTB), |
| 5263 | /* 13929 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 5264 | /* 13931 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 5265 | /* 13935 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 5266 | /* 13939 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5267 | /* 13942 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5268 | /* 13948 */ GIR_RootConstrainSelectedInstOperands, |
| 5269 | /* 13949 */ // GIR_Coverage, 185, |
| 5270 | /* 13949 */ GIR_EraseRootFromParent_Done, |
| 5271 | /* 13950 */ // Label 304: @13950 |
| 5272 | /* 13950 */ GIM_Try, /*On fail goto*//*Label 305*/ GIMT_Encode4(14041), // Rule ID 514 // |
| 5273 | /* 13955 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 5274 | /* 13958 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 5275 | /* 13962 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5276 | /* 13966 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 5277 | /* 13970 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 5278 | /* 13974 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 5279 | /* 13978 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 5280 | /* 13983 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16, |
| 5281 | /* 13987 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 5282 | /* 13991 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 5283 | /* 13995 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 5284 | /* 13999 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 5285 | /* 14004 */ // MIs[2] Operand 2 |
| 5286 | /* 14004 */ GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16), |
| 5287 | /* 14015 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 5288 | /* 14017 */ // (mul:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, i16:{ *:[Other] })) => (t2SMULTB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 5289 | /* 14017 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMULTB), |
| 5290 | /* 14020 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 5291 | /* 14022 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 5292 | /* 14026 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 5293 | /* 14030 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5294 | /* 14033 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5295 | /* 14039 */ GIR_RootConstrainSelectedInstOperands, |
| 5296 | /* 14040 */ // GIR_Coverage, 514, |
| 5297 | /* 14040 */ GIR_EraseRootFromParent_Done, |
| 5298 | /* 14041 */ // Label 305: @14041 |
| 5299 | /* 14041 */ GIM_Try, /*On fail goto*//*Label 306*/ GIMT_Encode4(14132), // Rule ID 184 // |
| 5300 | /* 14046 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM), |
| 5301 | /* 14049 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 5302 | /* 14053 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5303 | /* 14057 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 5304 | /* 14061 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 5305 | /* 14065 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 5306 | /* 14070 */ // MIs[1] Operand 2 |
| 5307 | /* 14070 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16), |
| 5308 | /* 14081 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 5309 | /* 14085 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 5310 | /* 14089 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 5311 | /* 14093 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 5312 | /* 14097 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 5313 | /* 14102 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16, |
| 5314 | /* 14106 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 5315 | /* 14108 */ // (mul:{ *:[i32] } (sext_inreg:{ *:[i32] } GPR:{ *:[i32] }:$Rn, i16:{ *:[Other] }), (sra:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 16:{ *:[i32] })) => (SMULBT:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) |
| 5316 | /* 14108 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMULBT), |
| 5317 | /* 14111 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 5318 | /* 14113 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 5319 | /* 14117 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 5320 | /* 14121 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5321 | /* 14124 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5322 | /* 14130 */ GIR_RootConstrainSelectedInstOperands, |
| 5323 | /* 14131 */ // GIR_Coverage, 184, |
| 5324 | /* 14131 */ GIR_EraseRootFromParent_Done, |
| 5325 | /* 14132 */ // Label 306: @14132 |
| 5326 | /* 14132 */ GIM_Try, /*On fail goto*//*Label 307*/ GIMT_Encode4(14223), // Rule ID 513 // |
| 5327 | /* 14137 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 5328 | /* 14140 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 5329 | /* 14144 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5330 | /* 14148 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 5331 | /* 14152 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 5332 | /* 14156 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 5333 | /* 14161 */ // MIs[1] Operand 2 |
| 5334 | /* 14161 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16), |
| 5335 | /* 14172 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 5336 | /* 14176 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 5337 | /* 14180 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 5338 | /* 14184 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 5339 | /* 14188 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 5340 | /* 14193 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16, |
| 5341 | /* 14197 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 5342 | /* 14199 */ // (mul:{ *:[i32] } (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, i16:{ *:[Other] }), (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 16:{ *:[i32] })) => (t2SMULBT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 5343 | /* 14199 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMULBT), |
| 5344 | /* 14202 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 5345 | /* 14204 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 5346 | /* 14208 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 5347 | /* 14212 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5348 | /* 14215 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5349 | /* 14221 */ GIR_RootConstrainSelectedInstOperands, |
| 5350 | /* 14222 */ // GIR_Coverage, 513, |
| 5351 | /* 14222 */ GIR_EraseRootFromParent_Done, |
| 5352 | /* 14223 */ // Label 307: @14223 |
| 5353 | /* 14223 */ GIM_Try, /*On fail goto*//*Label 308*/ GIMT_Encode4(14317), // Rule ID 183 // |
| 5354 | /* 14228 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM), |
| 5355 | /* 14231 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 5356 | /* 14235 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5357 | /* 14239 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 5358 | /* 14243 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 5359 | /* 14247 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 5360 | /* 14252 */ // MIs[1] Operand 2 |
| 5361 | /* 14252 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16), |
| 5362 | /* 14263 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 5363 | /* 14267 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 5364 | /* 14271 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 5365 | /* 14275 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 5366 | /* 14280 */ // MIs[2] Operand 2 |
| 5367 | /* 14280 */ GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16), |
| 5368 | /* 14291 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 5369 | /* 14293 */ // (mul:{ *:[i32] } (sext_inreg:{ *:[i32] } GPR:{ *:[i32] }:$Rn, i16:{ *:[Other] }), (sext_inreg:{ *:[i32] } GPR:{ *:[i32] }:$Rm, i16:{ *:[Other] })) => (SMULBB:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) |
| 5370 | /* 14293 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMULBB), |
| 5371 | /* 14296 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 5372 | /* 14298 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 5373 | /* 14302 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 5374 | /* 14306 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5375 | /* 14309 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5376 | /* 14315 */ GIR_RootConstrainSelectedInstOperands, |
| 5377 | /* 14316 */ // GIR_Coverage, 183, |
| 5378 | /* 14316 */ GIR_EraseRootFromParent_Done, |
| 5379 | /* 14317 */ // Label 308: @14317 |
| 5380 | /* 14317 */ GIM_Try, /*On fail goto*//*Label 309*/ GIMT_Encode4(14411), // Rule ID 512 // |
| 5381 | /* 14322 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 5382 | /* 14325 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 5383 | /* 14329 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5384 | /* 14333 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 5385 | /* 14337 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 5386 | /* 14341 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 5387 | /* 14346 */ // MIs[1] Operand 2 |
| 5388 | /* 14346 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16), |
| 5389 | /* 14357 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 5390 | /* 14361 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 5391 | /* 14365 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 5392 | /* 14369 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 5393 | /* 14374 */ // MIs[2] Operand 2 |
| 5394 | /* 14374 */ GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16), |
| 5395 | /* 14385 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 5396 | /* 14387 */ // (mul:{ *:[i32] } (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, i16:{ *:[Other] }), (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, i16:{ *:[Other] })) => (t2SMULBB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 5397 | /* 14387 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMULBB), |
| 5398 | /* 14390 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 5399 | /* 14392 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 5400 | /* 14396 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 5401 | /* 14400 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5402 | /* 14403 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5403 | /* 14409 */ GIR_RootConstrainSelectedInstOperands, |
| 5404 | /* 14410 */ // GIR_Coverage, 512, |
| 5405 | /* 14410 */ GIR_EraseRootFromParent_Done, |
| 5406 | /* 14411 */ // Label 309: @14411 |
| 5407 | /* 14411 */ GIM_Try, /*On fail goto*//*Label 310*/ GIMT_Encode4(14457), // Rule ID 169 // |
| 5408 | /* 14416 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 5409 | /* 14419 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 5410 | /* 14423 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 5411 | /* 14427 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 5412 | /* 14431 */ // (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (MUL:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 5413 | /* 14431 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MUL), |
| 5414 | /* 14434 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 5415 | /* 14436 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 5416 | /* 14438 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 5417 | /* 14440 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5418 | /* 14443 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5419 | /* 14449 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5420 | /* 14455 */ GIR_RootConstrainSelectedInstOperands, |
| 5421 | /* 14456 */ // GIR_Coverage, 169, |
| 5422 | /* 14456 */ GIR_EraseRootFromParent_Done, |
| 5423 | /* 14457 */ // Label 310: @14457 |
| 5424 | /* 14457 */ GIM_Try, /*On fail goto*//*Label 311*/ GIMT_Encode4(14503), // Rule ID 170 // |
| 5425 | /* 14462 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM_NoV6_UseMulOps), |
| 5426 | /* 14465 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 5427 | /* 14469 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 5428 | /* 14473 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 5429 | /* 14477 */ // (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (MULv5:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 5430 | /* 14477 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MULv5), |
| 5431 | /* 14480 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 5432 | /* 14482 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 5433 | /* 14484 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 5434 | /* 14486 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5435 | /* 14489 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5436 | /* 14495 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5437 | /* 14501 */ GIR_RootConstrainSelectedInstOperands, |
| 5438 | /* 14502 */ // GIR_Coverage, 170, |
| 5439 | /* 14502 */ GIR_EraseRootFromParent_Done, |
| 5440 | /* 14503 */ // Label 311: @14503 |
| 5441 | /* 14503 */ GIM_Try, /*On fail goto*//*Label 312*/ GIMT_Encode4(14549), // Rule ID 323 // |
| 5442 | /* 14508 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), |
| 5443 | /* 14511 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 5444 | /* 14515 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 5445 | /* 14519 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 5446 | /* 14523 */ // (mul:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) => (tMUL:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) |
| 5447 | /* 14523 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tMUL), |
| 5448 | /* 14526 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 5449 | /* 14528 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define | RegState::Dead), |
| 5450 | /* 14534 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 5451 | /* 14536 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 5452 | /* 14538 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5453 | /* 14541 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5454 | /* 14547 */ GIR_RootConstrainSelectedInstOperands, |
| 5455 | /* 14548 */ // GIR_Coverage, 323, |
| 5456 | /* 14548 */ GIR_EraseRootFromParent_Done, |
| 5457 | /* 14549 */ // Label 312: @14549 |
| 5458 | /* 14549 */ GIM_Try, /*On fail goto*//*Label 313*/ GIMT_Encode4(14589), // Rule ID 502 // |
| 5459 | /* 14554 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 5460 | /* 14557 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 5461 | /* 14561 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 5462 | /* 14565 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 5463 | /* 14569 */ // (mul:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2MUL:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 5464 | /* 14569 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MUL), |
| 5465 | /* 14572 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 5466 | /* 14574 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 5467 | /* 14576 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 5468 | /* 14578 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5469 | /* 14581 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5470 | /* 14587 */ GIR_RootConstrainSelectedInstOperands, |
| 5471 | /* 14588 */ // GIR_Coverage, 502, |
| 5472 | /* 14588 */ GIR_EraseRootFromParent_Done, |
| 5473 | /* 14589 */ // Label 313: @14589 |
| 5474 | /* 14589 */ GIM_Reject, |
| 5475 | /* 14590 */ // Label 301: @14590 |
| 5476 | /* 14590 */ GIM_Reject, |
| 5477 | /* 14591 */ // Label 294: @14591 |
| 5478 | /* 14591 */ GIM_Try, /*On fail goto*//*Label 314*/ GIMT_Encode4(14637), // Rule ID 837 // |
| 5479 | /* 14596 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 5480 | /* 14599 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 5481 | /* 14602 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 5482 | /* 14605 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5483 | /* 14609 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5484 | /* 14613 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5485 | /* 14617 */ // (mul:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VMULv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 5486 | /* 14617 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULv2i32), |
| 5487 | /* 14620 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5488 | /* 14622 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 5489 | /* 14624 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 5490 | /* 14626 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5491 | /* 14629 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5492 | /* 14635 */ GIR_RootConstrainSelectedInstOperands, |
| 5493 | /* 14636 */ // GIR_Coverage, 837, |
| 5494 | /* 14636 */ GIR_EraseRootFromParent_Done, |
| 5495 | /* 14637 */ // Label 314: @14637 |
| 5496 | /* 14637 */ GIM_Reject, |
| 5497 | /* 14638 */ // Label 295: @14638 |
| 5498 | /* 14638 */ GIM_Try, /*On fail goto*//*Label 315*/ GIMT_Encode4(14684), // Rule ID 836 // |
| 5499 | /* 14643 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 5500 | /* 14646 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 5501 | /* 14649 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 5502 | /* 14652 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5503 | /* 14656 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5504 | /* 14660 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5505 | /* 14664 */ // (mul:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VMULv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 5506 | /* 14664 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULv4i16), |
| 5507 | /* 14667 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5508 | /* 14669 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 5509 | /* 14671 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 5510 | /* 14673 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5511 | /* 14676 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5512 | /* 14682 */ GIR_RootConstrainSelectedInstOperands, |
| 5513 | /* 14683 */ // GIR_Coverage, 836, |
| 5514 | /* 14683 */ GIR_EraseRootFromParent_Done, |
| 5515 | /* 14684 */ // Label 315: @14684 |
| 5516 | /* 14684 */ GIM_Reject, |
| 5517 | /* 14685 */ // Label 296: @14685 |
| 5518 | /* 14685 */ GIM_Try, /*On fail goto*//*Label 316*/ GIMT_Encode4(14913), |
| 5519 | /* 14690 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 5520 | /* 14693 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 5521 | /* 14696 */ GIM_Try, /*On fail goto*//*Label 317*/ GIMT_Encode4(14811), // Rule ID 4421 // |
| 5522 | /* 14701 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 5523 | /* 14704 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 5524 | /* 14708 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5525 | /* 14712 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 5526 | /* 14716 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 5527 | /* 14720 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 5528 | /* 14725 */ // MIs[1] Operand 2 |
| 5529 | /* 14725 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16), |
| 5530 | /* 14736 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 5531 | /* 14740 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 5532 | /* 14744 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, |
| 5533 | /* 14748 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 5534 | /* 14753 */ // MIs[2] Operand 2 |
| 5535 | /* 14753 */ GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16), |
| 5536 | /* 14764 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 5537 | /* 14766 */ // (mul:{ *:[v4i32] } (sext_inreg:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src1, v4i16:{ *:[Other] }), (sext_inreg:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src2, v4i16:{ *:[Other] })) => (MVE_VMULLBs16:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src1, MQPR:{ *:[v4i32] }:$src2) |
| 5538 | /* 14766 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 5539 | /* 14769 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 5540 | /* 14773 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5541 | /* 14778 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLBs16), |
| 5542 | /* 14781 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 5543 | /* 14783 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 5544 | /* 14787 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2 |
| 5545 | /* 14791 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 5546 | /* 14794 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5547 | /* 14800 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5548 | /* 14806 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 5549 | /* 14809 */ GIR_RootConstrainSelectedInstOperands, |
| 5550 | /* 14810 */ // GIR_Coverage, 4421, |
| 5551 | /* 14810 */ GIR_EraseRootFromParent_Done, |
| 5552 | /* 14811 */ // Label 317: @14811 |
| 5553 | /* 14811 */ GIM_Try, /*On fail goto*//*Label 318*/ GIMT_Encode4(14851), // Rule ID 840 // |
| 5554 | /* 14816 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 5555 | /* 14819 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5556 | /* 14823 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5557 | /* 14827 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5558 | /* 14831 */ // (mul:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VMULv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 5559 | /* 14831 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULv4i32), |
| 5560 | /* 14834 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5561 | /* 14836 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 5562 | /* 14838 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 5563 | /* 14840 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5564 | /* 14843 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5565 | /* 14849 */ GIR_RootConstrainSelectedInstOperands, |
| 5566 | /* 14850 */ // GIR_Coverage, 840, |
| 5567 | /* 14850 */ GIR_EraseRootFromParent_Done, |
| 5568 | /* 14851 */ // Label 318: @14851 |
| 5569 | /* 14851 */ GIM_Try, /*On fail goto*//*Label 319*/ GIMT_Encode4(14912), // Rule ID 3466 // |
| 5570 | /* 14856 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 5571 | /* 14859 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 5572 | /* 14863 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 5573 | /* 14867 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 5574 | /* 14871 */ // (mul:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VMULi32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 5575 | /* 14871 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 5576 | /* 14874 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 5577 | /* 14878 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5578 | /* 14883 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULi32), |
| 5579 | /* 14886 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 5580 | /* 14888 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 5581 | /* 14890 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 5582 | /* 14892 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 5583 | /* 14895 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5584 | /* 14901 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5585 | /* 14907 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 5586 | /* 14910 */ GIR_RootConstrainSelectedInstOperands, |
| 5587 | /* 14911 */ // GIR_Coverage, 3466, |
| 5588 | /* 14911 */ GIR_EraseRootFromParent_Done, |
| 5589 | /* 14912 */ // Label 319: @14912 |
| 5590 | /* 14912 */ GIM_Reject, |
| 5591 | /* 14913 */ // Label 316: @14913 |
| 5592 | /* 14913 */ GIM_Reject, |
| 5593 | /* 14914 */ // Label 297: @14914 |
| 5594 | /* 14914 */ GIM_Try, /*On fail goto*//*Label 320*/ GIMT_Encode4(14960), // Rule ID 835 // |
| 5595 | /* 14919 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 5596 | /* 14922 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 5597 | /* 14925 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 5598 | /* 14928 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5599 | /* 14932 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5600 | /* 14936 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5601 | /* 14940 */ // (mul:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VMULv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 5602 | /* 14940 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULv8i8), |
| 5603 | /* 14943 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5604 | /* 14945 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 5605 | /* 14947 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 5606 | /* 14949 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5607 | /* 14952 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5608 | /* 14958 */ GIR_RootConstrainSelectedInstOperands, |
| 5609 | /* 14959 */ // GIR_Coverage, 835, |
| 5610 | /* 14959 */ GIR_EraseRootFromParent_Done, |
| 5611 | /* 14960 */ // Label 320: @14960 |
| 5612 | /* 14960 */ GIM_Reject, |
| 5613 | /* 14961 */ // Label 298: @14961 |
| 5614 | /* 14961 */ GIM_Try, /*On fail goto*//*Label 321*/ GIMT_Encode4(15189), |
| 5615 | /* 14966 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 5616 | /* 14969 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 5617 | /* 14972 */ GIM_Try, /*On fail goto*//*Label 322*/ GIMT_Encode4(15087), // Rule ID 4426 // |
| 5618 | /* 14977 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 5619 | /* 14980 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 5620 | /* 14984 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5621 | /* 14988 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 5622 | /* 14992 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 5623 | /* 14996 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 5624 | /* 15001 */ // MIs[1] Operand 2 |
| 5625 | /* 15001 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(8), |
| 5626 | /* 15012 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 5627 | /* 15016 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 5628 | /* 15020 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, |
| 5629 | /* 15024 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 5630 | /* 15029 */ // MIs[2] Operand 2 |
| 5631 | /* 15029 */ GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(8), |
| 5632 | /* 15040 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 5633 | /* 15042 */ // (mul:{ *:[v8i16] } (sext_inreg:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src1, v8i8:{ *:[Other] }), (sext_inreg:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src2, v8i8:{ *:[Other] })) => (MVE_VMULLBs8:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src1, MQPR:{ *:[v8i16] }:$src2) |
| 5634 | /* 15042 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 5635 | /* 15045 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 5636 | /* 15049 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5637 | /* 15054 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLBs8), |
| 5638 | /* 15057 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 5639 | /* 15059 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 5640 | /* 15063 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2 |
| 5641 | /* 15067 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 5642 | /* 15070 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5643 | /* 15076 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5644 | /* 15082 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 5645 | /* 15085 */ GIR_RootConstrainSelectedInstOperands, |
| 5646 | /* 15086 */ // GIR_Coverage, 4426, |
| 5647 | /* 15086 */ GIR_EraseRootFromParent_Done, |
| 5648 | /* 15087 */ // Label 322: @15087 |
| 5649 | /* 15087 */ GIM_Try, /*On fail goto*//*Label 323*/ GIMT_Encode4(15127), // Rule ID 839 // |
| 5650 | /* 15092 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 5651 | /* 15095 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5652 | /* 15099 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5653 | /* 15103 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5654 | /* 15107 */ // (mul:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VMULv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 5655 | /* 15107 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULv8i16), |
| 5656 | /* 15110 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5657 | /* 15112 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 5658 | /* 15114 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 5659 | /* 15116 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5660 | /* 15119 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5661 | /* 15125 */ GIR_RootConstrainSelectedInstOperands, |
| 5662 | /* 15126 */ // GIR_Coverage, 839, |
| 5663 | /* 15126 */ GIR_EraseRootFromParent_Done, |
| 5664 | /* 15127 */ // Label 323: @15127 |
| 5665 | /* 15127 */ GIM_Try, /*On fail goto*//*Label 324*/ GIMT_Encode4(15188), // Rule ID 3462 // |
| 5666 | /* 15132 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 5667 | /* 15135 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 5668 | /* 15139 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 5669 | /* 15143 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 5670 | /* 15147 */ // (mul:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VMULi16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 5671 | /* 15147 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 5672 | /* 15150 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 5673 | /* 15154 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5674 | /* 15159 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULi16), |
| 5675 | /* 15162 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 5676 | /* 15164 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 5677 | /* 15166 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 5678 | /* 15168 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 5679 | /* 15171 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5680 | /* 15177 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5681 | /* 15183 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 5682 | /* 15186 */ GIR_RootConstrainSelectedInstOperands, |
| 5683 | /* 15187 */ // GIR_Coverage, 3462, |
| 5684 | /* 15187 */ GIR_EraseRootFromParent_Done, |
| 5685 | /* 15188 */ // Label 324: @15188 |
| 5686 | /* 15188 */ GIM_Reject, |
| 5687 | /* 15189 */ // Label 321: @15189 |
| 5688 | /* 15189 */ GIM_Reject, |
| 5689 | /* 15190 */ // Label 299: @15190 |
| 5690 | /* 15190 */ GIM_Try, /*On fail goto*//*Label 325*/ GIMT_Encode4(15303), |
| 5691 | /* 15195 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 5692 | /* 15198 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 5693 | /* 15201 */ GIM_Try, /*On fail goto*//*Label 326*/ GIMT_Encode4(15241), // Rule ID 838 // |
| 5694 | /* 15206 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 5695 | /* 15209 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5696 | /* 15213 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5697 | /* 15217 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5698 | /* 15221 */ // (mul:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VMULv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 5699 | /* 15221 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULv16i8), |
| 5700 | /* 15224 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5701 | /* 15226 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 5702 | /* 15228 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 5703 | /* 15230 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5704 | /* 15233 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5705 | /* 15239 */ GIR_RootConstrainSelectedInstOperands, |
| 5706 | /* 15240 */ // GIR_Coverage, 838, |
| 5707 | /* 15240 */ GIR_EraseRootFromParent_Done, |
| 5708 | /* 15241 */ // Label 326: @15241 |
| 5709 | /* 15241 */ GIM_Try, /*On fail goto*//*Label 327*/ GIMT_Encode4(15302), // Rule ID 3458 // |
| 5710 | /* 15246 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 5711 | /* 15249 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 5712 | /* 15253 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 5713 | /* 15257 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 5714 | /* 15261 */ // (mul:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VMULi8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 5715 | /* 15261 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 5716 | /* 15264 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 5717 | /* 15268 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5718 | /* 15273 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULi8), |
| 5719 | /* 15276 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 5720 | /* 15278 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 5721 | /* 15280 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 5722 | /* 15282 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 5723 | /* 15285 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5724 | /* 15291 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5725 | /* 15297 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 5726 | /* 15300 */ GIR_RootConstrainSelectedInstOperands, |
| 5727 | /* 15301 */ // GIR_Coverage, 3458, |
| 5728 | /* 15301 */ GIR_EraseRootFromParent_Done, |
| 5729 | /* 15302 */ // Label 327: @15302 |
| 5730 | /* 15302 */ GIM_Reject, |
| 5731 | /* 15303 */ // Label 325: @15303 |
| 5732 | /* 15303 */ GIM_Reject, |
| 5733 | /* 15304 */ // Label 300: @15304 |
| 5734 | /* 15304 */ GIM_Reject, |
| 5735 | /* 15305 */ // Label 3: @15305 |
| 5736 | /* 15305 */ GIM_Try, /*On fail goto*//*Label 328*/ GIMT_Encode4(15400), |
| 5737 | /* 15310 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 5738 | /* 15313 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 5739 | /* 15316 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 5740 | /* 15319 */ GIM_Try, /*On fail goto*//*Label 329*/ GIMT_Encode4(15359), // Rule ID 195 // |
| 5741 | /* 15324 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDivideInARM_IsARM), |
| 5742 | /* 15327 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 5743 | /* 15331 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 5744 | /* 15335 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 5745 | /* 15339 */ // (sdiv:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (SDIV:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) |
| 5746 | /* 15339 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SDIV), |
| 5747 | /* 15342 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 5748 | /* 15344 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 5749 | /* 15346 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 5750 | /* 15348 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5751 | /* 15351 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5752 | /* 15357 */ GIR_RootConstrainSelectedInstOperands, |
| 5753 | /* 15358 */ // GIR_Coverage, 195, |
| 5754 | /* 15358 */ GIR_EraseRootFromParent_Done, |
| 5755 | /* 15359 */ // Label 329: @15359 |
| 5756 | /* 15359 */ GIM_Try, /*On fail goto*//*Label 330*/ GIMT_Encode4(15399), // Rule ID 532 // |
| 5757 | /* 15364 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDivideInThumb_HasV8MBaseline_IsThumb), |
| 5758 | /* 15367 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 5759 | /* 15371 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 5760 | /* 15375 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 5761 | /* 15379 */ // (sdiv:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SDIV:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 5762 | /* 15379 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SDIV), |
| 5763 | /* 15382 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 5764 | /* 15384 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 5765 | /* 15386 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 5766 | /* 15388 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5767 | /* 15391 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5768 | /* 15397 */ GIR_RootConstrainSelectedInstOperands, |
| 5769 | /* 15398 */ // GIR_Coverage, 532, |
| 5770 | /* 15398 */ GIR_EraseRootFromParent_Done, |
| 5771 | /* 15399 */ // Label 330: @15399 |
| 5772 | /* 15399 */ GIM_Reject, |
| 5773 | /* 15400 */ // Label 328: @15400 |
| 5774 | /* 15400 */ GIM_Reject, |
| 5775 | /* 15401 */ // Label 4: @15401 |
| 5776 | /* 15401 */ GIM_Try, /*On fail goto*//*Label 331*/ GIMT_Encode4(15496), |
| 5777 | /* 15406 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 5778 | /* 15409 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 5779 | /* 15412 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 5780 | /* 15415 */ GIM_Try, /*On fail goto*//*Label 332*/ GIMT_Encode4(15455), // Rule ID 196 // |
| 5781 | /* 15420 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDivideInARM_IsARM), |
| 5782 | /* 15423 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 5783 | /* 15427 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 5784 | /* 15431 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 5785 | /* 15435 */ // (udiv:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (UDIV:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) |
| 5786 | /* 15435 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UDIV), |
| 5787 | /* 15438 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 5788 | /* 15440 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 5789 | /* 15442 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 5790 | /* 15444 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5791 | /* 15447 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5792 | /* 15453 */ GIR_RootConstrainSelectedInstOperands, |
| 5793 | /* 15454 */ // GIR_Coverage, 196, |
| 5794 | /* 15454 */ GIR_EraseRootFromParent_Done, |
| 5795 | /* 15455 */ // Label 332: @15455 |
| 5796 | /* 15455 */ GIM_Try, /*On fail goto*//*Label 333*/ GIMT_Encode4(15495), // Rule ID 533 // |
| 5797 | /* 15460 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDivideInThumb_HasV8MBaseline_IsThumb), |
| 5798 | /* 15463 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 5799 | /* 15467 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 5800 | /* 15471 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 5801 | /* 15475 */ // (udiv:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UDIV:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 5802 | /* 15475 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UDIV), |
| 5803 | /* 15478 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 5804 | /* 15480 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 5805 | /* 15482 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 5806 | /* 15484 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5807 | /* 15487 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5808 | /* 15493 */ GIR_RootConstrainSelectedInstOperands, |
| 5809 | /* 15494 */ // GIR_Coverage, 533, |
| 5810 | /* 15494 */ GIR_EraseRootFromParent_Done, |
| 5811 | /* 15495 */ // Label 333: @15495 |
| 5812 | /* 15495 */ GIM_Reject, |
| 5813 | /* 15496 */ // Label 331: @15496 |
| 5814 | /* 15496 */ GIM_Reject, |
| 5815 | /* 15497 */ // Label 5: @15497 |
| 5816 | /* 15497 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(16), /*)*//*default:*//*Label 347*/ GIMT_Encode4(18676), |
| 5817 | /* 15508 */ /*GILLT_s32*//*Label 334*/ GIMT_Encode4(15568), |
| 5818 | /* 15512 */ /*GILLT_s64*//*Label 335*/ GIMT_Encode4(17560), |
| 5819 | /* 15516 */ /*GILLT_v2s1*//*Label 336*/ GIMT_Encode4(17607), |
| 5820 | /* 15520 */ /*GILLT_v2s32*//*Label 337*/ GIMT_Encode4(17725), |
| 5821 | /* 15524 */ /*GILLT_v2s64*//*Label 338*/ GIMT_Encode4(17772), |
| 5822 | /* 15528 */ /*GILLT_v4s1*//*Label 339*/ GIMT_Encode4(17886), |
| 5823 | /* 15532 */ /*GILLT_v4s16*//*Label 340*/ GIMT_Encode4(18004), |
| 5824 | /* 15536 */ /*GILLT_v4s32*//*Label 341*/ GIMT_Encode4(18051), GIMT_Encode4(0), |
| 5825 | /* 15544 */ /*GILLT_v8s1*//*Label 342*/ GIMT_Encode4(18165), |
| 5826 | /* 15548 */ /*GILLT_v8s8*//*Label 343*/ GIMT_Encode4(18283), |
| 5827 | /* 15552 */ /*GILLT_v8s16*//*Label 344*/ GIMT_Encode4(18330), GIMT_Encode4(0), |
| 5828 | /* 15560 */ /*GILLT_v16s1*//*Label 345*/ GIMT_Encode4(18444), |
| 5829 | /* 15564 */ /*GILLT_v16s8*//*Label 346*/ GIMT_Encode4(18562), |
| 5830 | /* 15568 */ // Label 334: @15568 |
| 5831 | /* 15568 */ GIM_Try, /*On fail goto*//*Label 348*/ GIMT_Encode4(17559), |
| 5832 | /* 15573 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 5833 | /* 15576 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 5834 | /* 15579 */ GIM_Try, /*On fail goto*//*Label 349*/ GIMT_Encode4(15652), // Rule ID 1855 // |
| 5835 | /* 15584 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 5836 | /* 15587 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 5837 | /* 15591 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5838 | /* 15595 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 5839 | /* 15599 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 5840 | /* 15603 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 5841 | /* 15607 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 5842 | /* 15612 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 8, |
| 5843 | /* 15616 */ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16711935), |
| 5844 | /* 15627 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 5845 | /* 15629 */ // (and:{ *:[i32] } (srl:{ *:[i32] } GPR:{ *:[i32] }:$Src, 8:{ *:[i32] }), 16711935:{ *:[i32] }) => (UXTB16:{ *:[i32] } GPR:{ *:[i32] }:$Src, 1:{ *:[i32] }) |
| 5846 | /* 15629 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UXTB16), |
| 5847 | /* 15632 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 5848 | /* 15634 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Src |
| 5849 | /* 15638 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 5850 | /* 15641 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5851 | /* 15644 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5852 | /* 15650 */ GIR_RootConstrainSelectedInstOperands, |
| 5853 | /* 15651 */ // GIR_Coverage, 1855, |
| 5854 | /* 15651 */ GIR_EraseRootFromParent_Done, |
| 5855 | /* 15652 */ // Label 349: @15652 |
| 5856 | /* 15652 */ GIM_Try, /*On fail goto*//*Label 350*/ GIMT_Encode4(15725), // Rule ID 2112 // |
| 5857 | /* 15657 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 5858 | /* 15660 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 5859 | /* 15664 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5860 | /* 15668 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 5861 | /* 15672 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 5862 | /* 15676 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 5863 | /* 15680 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 5864 | /* 15685 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 8, |
| 5865 | /* 15689 */ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16711935), |
| 5866 | /* 15700 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 5867 | /* 15702 */ // (and:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$Src, 8:{ *:[i32] }), 16711935:{ *:[i32] }) => (t2UXTB16:{ *:[i32] } rGPR:{ *:[i32] }:$Src, 1:{ *:[i32] }) |
| 5868 | /* 15702 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UXTB16), |
| 5869 | /* 15705 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 5870 | /* 15707 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Src |
| 5871 | /* 15711 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 5872 | /* 15714 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5873 | /* 15717 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5874 | /* 15723 */ GIR_RootConstrainSelectedInstOperands, |
| 5875 | /* 15724 */ // GIR_Coverage, 2112, |
| 5876 | /* 15724 */ GIR_EraseRootFromParent_Done, |
| 5877 | /* 15725 */ // Label 350: @15725 |
| 5878 | /* 15725 */ GIM_Try, /*On fail goto*//*Label 351*/ GIMT_Encode4(15773), // Rule ID 1997 // |
| 5879 | /* 15730 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 5880 | /* 15733 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 5881 | /* 15737 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 5882 | /* 15741 */ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(255), |
| 5883 | /* 15752 */ // (and:{ *:[i32] } GPR:{ *:[i32] }:$Src, 255:{ *:[i32] }) => (UXTB:{ *:[i32] } GPR:{ *:[i32] }:$Src, 0:{ *:[i32] }) |
| 5884 | /* 15752 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UXTB), |
| 5885 | /* 15755 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 5886 | /* 15757 */ GIR_RootToRootCopy, /*OpIdx*/1, // Src |
| 5887 | /* 15759 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 5888 | /* 15762 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5889 | /* 15765 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5890 | /* 15771 */ GIR_RootConstrainSelectedInstOperands, |
| 5891 | /* 15772 */ // GIR_Coverage, 1997, |
| 5892 | /* 15772 */ GIR_EraseRootFromParent_Done, |
| 5893 | /* 15773 */ // Label 351: @15773 |
| 5894 | /* 15773 */ GIM_Try, /*On fail goto*//*Label 352*/ GIMT_Encode4(15821), // Rule ID 1998 // |
| 5895 | /* 15778 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 5896 | /* 15781 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 5897 | /* 15785 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 5898 | /* 15789 */ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(65535), |
| 5899 | /* 15800 */ // (and:{ *:[i32] } GPR:{ *:[i32] }:$Src, 65535:{ *:[i32] }) => (UXTH:{ *:[i32] } GPR:{ *:[i32] }:$Src, 0:{ *:[i32] }) |
| 5900 | /* 15800 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UXTH), |
| 5901 | /* 15803 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 5902 | /* 15805 */ GIR_RootToRootCopy, /*OpIdx*/1, // Src |
| 5903 | /* 15807 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 5904 | /* 15810 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5905 | /* 15813 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5906 | /* 15819 */ GIR_RootConstrainSelectedInstOperands, |
| 5907 | /* 15820 */ // GIR_Coverage, 1998, |
| 5908 | /* 15820 */ GIR_EraseRootFromParent_Done, |
| 5909 | /* 15821 */ // Label 352: @15821 |
| 5910 | /* 15821 */ GIM_Try, /*On fail goto*//*Label 353*/ GIMT_Encode4(15869), // Rule ID 1999 // |
| 5911 | /* 15826 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 5912 | /* 15829 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 5913 | /* 15833 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 5914 | /* 15837 */ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16711935), |
| 5915 | /* 15848 */ // (and:{ *:[i32] } GPR:{ *:[i32] }:$Src, 16711935:{ *:[i32] }) => (UXTB16:{ *:[i32] } GPR:{ *:[i32] }:$Src, 0:{ *:[i32] }) |
| 5916 | /* 15848 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UXTB16), |
| 5917 | /* 15851 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 5918 | /* 15853 */ GIR_RootToRootCopy, /*OpIdx*/1, // Src |
| 5919 | /* 15855 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 5920 | /* 15858 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5921 | /* 15861 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5922 | /* 15867 */ GIR_RootConstrainSelectedInstOperands, |
| 5923 | /* 15868 */ // GIR_Coverage, 1999, |
| 5924 | /* 15868 */ GIR_EraseRootFromParent_Done, |
| 5925 | /* 15869 */ // Label 353: @15869 |
| 5926 | /* 15869 */ GIM_Try, /*On fail goto*//*Label 354*/ GIMT_Encode4(15917), // Rule ID 2236 // |
| 5927 | /* 15874 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 5928 | /* 15877 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 5929 | /* 15881 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 5930 | /* 15885 */ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(255), |
| 5931 | /* 15896 */ // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 255:{ *:[i32] }) => (t2UXTB:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] }) |
| 5932 | /* 15896 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UXTB), |
| 5933 | /* 15899 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 5934 | /* 15901 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 5935 | /* 15903 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 5936 | /* 15906 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5937 | /* 15909 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5938 | /* 15915 */ GIR_RootConstrainSelectedInstOperands, |
| 5939 | /* 15916 */ // GIR_Coverage, 2236, |
| 5940 | /* 15916 */ GIR_EraseRootFromParent_Done, |
| 5941 | /* 15917 */ // Label 354: @15917 |
| 5942 | /* 15917 */ GIM_Try, /*On fail goto*//*Label 355*/ GIMT_Encode4(15965), // Rule ID 2237 // |
| 5943 | /* 15922 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 5944 | /* 15925 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 5945 | /* 15929 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 5946 | /* 15933 */ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(65535), |
| 5947 | /* 15944 */ // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] }) => (t2UXTH:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] }) |
| 5948 | /* 15944 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UXTH), |
| 5949 | /* 15947 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 5950 | /* 15949 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 5951 | /* 15951 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 5952 | /* 15954 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5953 | /* 15957 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5954 | /* 15963 */ GIR_RootConstrainSelectedInstOperands, |
| 5955 | /* 15964 */ // GIR_Coverage, 2237, |
| 5956 | /* 15964 */ GIR_EraseRootFromParent_Done, |
| 5957 | /* 15965 */ // Label 355: @15965 |
| 5958 | /* 15965 */ GIM_Try, /*On fail goto*//*Label 356*/ GIMT_Encode4(16013), // Rule ID 2238 // |
| 5959 | /* 15970 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 5960 | /* 15973 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 5961 | /* 15977 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 5962 | /* 15981 */ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16711935), |
| 5963 | /* 15992 */ // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 16711935:{ *:[i32] }) => (t2UXTB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] }) |
| 5964 | /* 15992 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UXTB16), |
| 5965 | /* 15995 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 5966 | /* 15997 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 5967 | /* 15999 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 5968 | /* 16002 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5969 | /* 16005 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5970 | /* 16011 */ GIR_RootConstrainSelectedInstOperands, |
| 5971 | /* 16012 */ // GIR_Coverage, 2238, |
| 5972 | /* 16012 */ GIR_EraseRootFromParent_Done, |
| 5973 | /* 16013 */ // Label 356: @16013 |
| 5974 | /* 16013 */ GIM_Try, /*On fail goto*//*Label 357*/ GIMT_Encode4(16090), // Rule ID 5439 // |
| 5975 | /* 16018 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 5976 | /* 16021 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 5977 | /* 16025 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5978 | /* 16029 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 5979 | /* 16033 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 5980 | /* 16037 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 5981 | /* 16041 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, uint8_t(-1), |
| 5982 | /* 16045 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 5983 | /* 16049 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 5984 | /* 16053 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm), |
| 5985 | /* 16057 */ // MIs[2] Operand 1 |
| 5986 | /* 16057 */ // No operand predicates |
| 5987 | /* 16057 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 5988 | /* 16061 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 5989 | /* 16063 */ // (and:{ *:[i32] } (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm), GPR:{ *:[i32] }:$Rn) => (BICri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 5990 | /* 16063 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::BICri), |
| 5991 | /* 16066 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 5992 | /* 16068 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 5993 | /* 16070 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 5994 | /* 16073 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5995 | /* 16076 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5996 | /* 16082 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5997 | /* 16088 */ GIR_RootConstrainSelectedInstOperands, |
| 5998 | /* 16089 */ // GIR_Coverage, 5439, |
| 5999 | /* 16089 */ GIR_EraseRootFromParent_Done, |
| 6000 | /* 16090 */ // Label 357: @16090 |
| 6001 | /* 16090 */ GIM_Try, /*On fail goto*//*Label 358*/ GIMT_Encode4(16167), // Rule ID 5472 // |
| 6002 | /* 16095 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 6003 | /* 16098 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6004 | /* 16102 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 6005 | /* 16106 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 6006 | /* 16110 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 6007 | /* 16114 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 6008 | /* 16118 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, uint8_t(-1), |
| 6009 | /* 16122 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 6010 | /* 16126 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 6011 | /* 16130 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm), |
| 6012 | /* 16134 */ // MIs[2] Operand 1 |
| 6013 | /* 16134 */ // No operand predicates |
| 6014 | /* 16134 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6015 | /* 16138 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 6016 | /* 16140 */ // (and:{ *:[i32] } (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm), rGPR:{ *:[i32] }:$Rn) => (t2BICri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 6017 | /* 16140 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2BICri), |
| 6018 | /* 16143 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6019 | /* 16145 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 6020 | /* 16147 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 6021 | /* 16150 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6022 | /* 16153 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6023 | /* 16159 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6024 | /* 16165 */ GIR_RootConstrainSelectedInstOperands, |
| 6025 | /* 16166 */ // GIR_Coverage, 5472, |
| 6026 | /* 16166 */ GIR_EraseRootFromParent_Done, |
| 6027 | /* 16167 */ // Label 358: @16167 |
| 6028 | /* 16167 */ GIM_Try, /*On fail goto*//*Label 359*/ GIMT_Encode4(16244), // Rule ID 5438 // |
| 6029 | /* 16172 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 6030 | /* 16175 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 6031 | /* 16179 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 6032 | /* 16183 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 6033 | /* 16187 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 6034 | /* 16191 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 6035 | /* 16195 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 6036 | /* 16199 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 6037 | /* 16203 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm), |
| 6038 | /* 16207 */ // MIs[2] Operand 1 |
| 6039 | /* 16207 */ // No operand predicates |
| 6040 | /* 16207 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), |
| 6041 | /* 16211 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 6042 | /* 16215 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 6043 | /* 16217 */ // (and:{ *:[i32] } (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm, -1:{ *:[i32] }), GPR:{ *:[i32] }:$Rn) => (BICri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 6044 | /* 16217 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::BICri), |
| 6045 | /* 16220 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6046 | /* 16222 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 6047 | /* 16224 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 6048 | /* 16227 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6049 | /* 16230 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6050 | /* 16236 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6051 | /* 16242 */ GIR_RootConstrainSelectedInstOperands, |
| 6052 | /* 16243 */ // GIR_Coverage, 5438, |
| 6053 | /* 16243 */ GIR_EraseRootFromParent_Done, |
| 6054 | /* 16244 */ // Label 359: @16244 |
| 6055 | /* 16244 */ GIM_Try, /*On fail goto*//*Label 360*/ GIMT_Encode4(16321), // Rule ID 5471 // |
| 6056 | /* 16249 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 6057 | /* 16252 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6058 | /* 16256 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 6059 | /* 16260 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 6060 | /* 16264 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 6061 | /* 16268 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 6062 | /* 16272 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 6063 | /* 16276 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 6064 | /* 16280 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm), |
| 6065 | /* 16284 */ // MIs[2] Operand 1 |
| 6066 | /* 16284 */ // No operand predicates |
| 6067 | /* 16284 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), |
| 6068 | /* 16288 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6069 | /* 16292 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 6070 | /* 16294 */ // (and:{ *:[i32] } (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm, -1:{ *:[i32] }), rGPR:{ *:[i32] }:$Rn) => (t2BICri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 6071 | /* 16294 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2BICri), |
| 6072 | /* 16297 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6073 | /* 16299 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 6074 | /* 16301 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 6075 | /* 16304 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6076 | /* 16307 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6077 | /* 16313 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6078 | /* 16319 */ GIR_RootConstrainSelectedInstOperands, |
| 6079 | /* 16320 */ // GIR_Coverage, 5471, |
| 6080 | /* 16320 */ GIR_EraseRootFromParent_Done, |
| 6081 | /* 16321 */ // Label 360: @16321 |
| 6082 | /* 16321 */ GIM_Try, /*On fail goto*//*Label 361*/ GIMT_Encode4(16398), // Rule ID 5437 // |
| 6083 | /* 16326 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 6084 | /* 16329 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 6085 | /* 16333 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 6086 | /* 16337 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 6087 | /* 16341 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 6088 | /* 16345 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 6089 | /* 16349 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 6090 | /* 16353 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, uint8_t(-1), |
| 6091 | /* 16357 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 6092 | /* 16361 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 6093 | /* 16365 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm), |
| 6094 | /* 16369 */ // MIs[2] Operand 1 |
| 6095 | /* 16369 */ // No operand predicates |
| 6096 | /* 16369 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 6097 | /* 16371 */ // (and:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm)) => (BICri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 6098 | /* 16371 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::BICri), |
| 6099 | /* 16374 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6100 | /* 16376 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 6101 | /* 16378 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 6102 | /* 16381 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6103 | /* 16384 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6104 | /* 16390 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6105 | /* 16396 */ GIR_RootConstrainSelectedInstOperands, |
| 6106 | /* 16397 */ // GIR_Coverage, 5437, |
| 6107 | /* 16397 */ GIR_EraseRootFromParent_Done, |
| 6108 | /* 16398 */ // Label 361: @16398 |
| 6109 | /* 16398 */ GIM_Try, /*On fail goto*//*Label 362*/ GIMT_Encode4(16475), // Rule ID 5470 // |
| 6110 | /* 16403 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 6111 | /* 16406 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6112 | /* 16410 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6113 | /* 16414 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 6114 | /* 16418 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 6115 | /* 16422 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 6116 | /* 16426 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 6117 | /* 16430 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, uint8_t(-1), |
| 6118 | /* 16434 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 6119 | /* 16438 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 6120 | /* 16442 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm), |
| 6121 | /* 16446 */ // MIs[2] Operand 1 |
| 6122 | /* 16446 */ // No operand predicates |
| 6123 | /* 16446 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 6124 | /* 16448 */ // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm)) => (t2BICri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 6125 | /* 16448 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2BICri), |
| 6126 | /* 16451 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6127 | /* 16453 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 6128 | /* 16455 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 6129 | /* 16458 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6130 | /* 16461 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6131 | /* 16467 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6132 | /* 16473 */ GIR_RootConstrainSelectedInstOperands, |
| 6133 | /* 16474 */ // GIR_Coverage, 5470, |
| 6134 | /* 16474 */ GIR_EraseRootFromParent_Done, |
| 6135 | /* 16475 */ // Label 362: @16475 |
| 6136 | /* 16475 */ GIM_Try, /*On fail goto*//*Label 363*/ GIMT_Encode4(16552), // Rule ID 159 // |
| 6137 | /* 16480 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 6138 | /* 16483 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 6139 | /* 16487 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 6140 | /* 16491 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 6141 | /* 16495 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 6142 | /* 16499 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 6143 | /* 16503 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 6144 | /* 16507 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 6145 | /* 16511 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 6146 | /* 16515 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm), |
| 6147 | /* 16519 */ // MIs[2] Operand 1 |
| 6148 | /* 16519 */ // No operand predicates |
| 6149 | /* 16519 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), |
| 6150 | /* 16523 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 6151 | /* 16525 */ // (and:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm, -1:{ *:[i32] })) => (BICri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 6152 | /* 16525 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::BICri), |
| 6153 | /* 16528 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6154 | /* 16530 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 6155 | /* 16532 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 6156 | /* 16535 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6157 | /* 16538 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6158 | /* 16544 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6159 | /* 16550 */ GIR_RootConstrainSelectedInstOperands, |
| 6160 | /* 16551 */ // GIR_Coverage, 159, |
| 6161 | /* 16551 */ GIR_EraseRootFromParent_Done, |
| 6162 | /* 16552 */ // Label 363: @16552 |
| 6163 | /* 16552 */ GIM_Try, /*On fail goto*//*Label 364*/ GIMT_Encode4(16629), // Rule ID 490 // |
| 6164 | /* 16557 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 6165 | /* 16560 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6166 | /* 16564 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6167 | /* 16568 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 6168 | /* 16572 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 6169 | /* 16576 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 6170 | /* 16580 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 6171 | /* 16584 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 6172 | /* 16588 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 6173 | /* 16592 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm), |
| 6174 | /* 16596 */ // MIs[2] Operand 1 |
| 6175 | /* 16596 */ // No operand predicates |
| 6176 | /* 16596 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), |
| 6177 | /* 16600 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 6178 | /* 16602 */ // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm, -1:{ *:[i32] })) => (t2BICri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 6179 | /* 16602 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2BICri), |
| 6180 | /* 16605 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6181 | /* 16607 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 6182 | /* 16609 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 6183 | /* 16612 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6184 | /* 16615 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6185 | /* 16621 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6186 | /* 16627 */ GIR_RootConstrainSelectedInstOperands, |
| 6187 | /* 16628 */ // GIR_Coverage, 490, |
| 6188 | /* 16628 */ GIR_EraseRootFromParent_Done, |
| 6189 | /* 16629 */ // Label 364: @16629 |
| 6190 | /* 16629 */ GIM_Try, /*On fail goto*//*Label 365*/ GIMT_Encode4(16700), // Rule ID 5440 // |
| 6191 | /* 16634 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 6192 | /* 16637 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 6193 | /* 16641 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 6194 | /* 16645 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 6195 | /* 16649 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 6196 | /* 16653 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 6197 | /* 16657 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 6198 | /* 16662 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), |
| 6199 | /* 16666 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 6200 | /* 16670 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 6201 | /* 16672 */ // (and:{ *:[i32] } (xor:{ *:[i32] } GPR:{ *:[i32] }:$Rm, -1:{ *:[i32] }), GPR:{ *:[i32] }:$Rn) => (BICrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) |
| 6202 | /* 16672 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::BICrr), |
| 6203 | /* 16675 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6204 | /* 16677 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 6205 | /* 16679 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 6206 | /* 16683 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6207 | /* 16686 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6208 | /* 16692 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6209 | /* 16698 */ GIR_RootConstrainSelectedInstOperands, |
| 6210 | /* 16699 */ // GIR_Coverage, 5440, |
| 6211 | /* 16699 */ GIR_EraseRootFromParent_Done, |
| 6212 | /* 16700 */ // Label 365: @16700 |
| 6213 | /* 16700 */ GIM_Try, /*On fail goto*//*Label 366*/ GIMT_Encode4(16771), // Rule ID 5461 // |
| 6214 | /* 16705 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), |
| 6215 | /* 16708 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 6216 | /* 16712 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 6217 | /* 16716 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 6218 | /* 16720 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 6219 | /* 16724 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 6220 | /* 16728 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 6221 | /* 16733 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), |
| 6222 | /* 16737 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 6223 | /* 16741 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 6224 | /* 16743 */ // (and:{ *:[i32] } (xor:{ *:[i32] } tGPR:{ *:[i32] }:$Rm, -1:{ *:[i32] }), tGPR:{ *:[i32] }:$Rn) => (tBIC:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) |
| 6225 | /* 16743 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tBIC), |
| 6226 | /* 16746 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn] |
| 6227 | /* 16748 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define | RegState::Dead), |
| 6228 | /* 16754 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 6229 | /* 16756 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 6230 | /* 16760 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6231 | /* 16763 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6232 | /* 16769 */ GIR_RootConstrainSelectedInstOperands, |
| 6233 | /* 16770 */ // GIR_Coverage, 5461, |
| 6234 | /* 16770 */ GIR_EraseRootFromParent_Done, |
| 6235 | /* 16771 */ // Label 366: @16771 |
| 6236 | /* 16771 */ GIM_Try, /*On fail goto*//*Label 367*/ GIMT_Encode4(16842), // Rule ID 5473 // |
| 6237 | /* 16776 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 6238 | /* 16779 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6239 | /* 16783 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 6240 | /* 16787 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 6241 | /* 16791 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 6242 | /* 16795 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 6243 | /* 16799 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6244 | /* 16804 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), |
| 6245 | /* 16808 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6246 | /* 16812 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 6247 | /* 16814 */ // (and:{ *:[i32] } (xor:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, -1:{ *:[i32] }), rGPR:{ *:[i32] }:$Rn) => (t2BICrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 6248 | /* 16814 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2BICrr), |
| 6249 | /* 16817 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6250 | /* 16819 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 6251 | /* 16821 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 6252 | /* 16825 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6253 | /* 16828 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6254 | /* 16834 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6255 | /* 16840 */ GIR_RootConstrainSelectedInstOperands, |
| 6256 | /* 16841 */ // GIR_Coverage, 5473, |
| 6257 | /* 16841 */ GIR_EraseRootFromParent_Done, |
| 6258 | /* 16842 */ // Label 367: @16842 |
| 6259 | /* 16842 */ GIM_Try, /*On fail goto*//*Label 368*/ GIMT_Encode4(16913), // Rule ID 160 // |
| 6260 | /* 16847 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 6261 | /* 16850 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 6262 | /* 16854 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 6263 | /* 16858 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 6264 | /* 16862 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 6265 | /* 16866 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 6266 | /* 16870 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 6267 | /* 16874 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 6268 | /* 16879 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), |
| 6269 | /* 16883 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 6270 | /* 16885 */ // (and:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } GPR:{ *:[i32] }:$Rm, -1:{ *:[i32] })) => (BICrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) |
| 6271 | /* 16885 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::BICrr), |
| 6272 | /* 16888 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6273 | /* 16890 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 6274 | /* 16892 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 6275 | /* 16896 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6276 | /* 16899 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6277 | /* 16905 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6278 | /* 16911 */ GIR_RootConstrainSelectedInstOperands, |
| 6279 | /* 16912 */ // GIR_Coverage, 160, |
| 6280 | /* 16912 */ GIR_EraseRootFromParent_Done, |
| 6281 | /* 16913 */ // Label 368: @16913 |
| 6282 | /* 16913 */ GIM_Try, /*On fail goto*//*Label 369*/ GIMT_Encode4(16984), // Rule ID 313 // |
| 6283 | /* 16918 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), |
| 6284 | /* 16921 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 6285 | /* 16925 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 6286 | /* 16929 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 6287 | /* 16933 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 6288 | /* 16937 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 6289 | /* 16941 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 6290 | /* 16945 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 6291 | /* 16950 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), |
| 6292 | /* 16954 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 6293 | /* 16956 */ // (and:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } tGPR:{ *:[i32] }:$Rm, -1:{ *:[i32] })) => (tBIC:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) |
| 6294 | /* 16956 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tBIC), |
| 6295 | /* 16959 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn] |
| 6296 | /* 16961 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define | RegState::Dead), |
| 6297 | /* 16967 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 6298 | /* 16969 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 6299 | /* 16973 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6300 | /* 16976 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6301 | /* 16982 */ GIR_RootConstrainSelectedInstOperands, |
| 6302 | /* 16983 */ // GIR_Coverage, 313, |
| 6303 | /* 16983 */ GIR_EraseRootFromParent_Done, |
| 6304 | /* 16984 */ // Label 369: @16984 |
| 6305 | /* 16984 */ GIM_Try, /*On fail goto*//*Label 370*/ GIMT_Encode4(17055), // Rule ID 491 // |
| 6306 | /* 16989 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 6307 | /* 16992 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6308 | /* 16996 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6309 | /* 17000 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 6310 | /* 17004 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 6311 | /* 17008 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 6312 | /* 17012 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 6313 | /* 17016 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6314 | /* 17021 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), |
| 6315 | /* 17025 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 6316 | /* 17027 */ // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, -1:{ *:[i32] })) => (t2BICrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 6317 | /* 17027 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2BICrr), |
| 6318 | /* 17030 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6319 | /* 17032 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 6320 | /* 17034 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 6321 | /* 17038 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6322 | /* 17041 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6323 | /* 17047 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6324 | /* 17053 */ GIR_RootConstrainSelectedInstOperands, |
| 6325 | /* 17054 */ // GIR_Coverage, 491, |
| 6326 | /* 17054 */ GIR_EraseRootFromParent_Done, |
| 6327 | /* 17055 */ // Label 370: @17055 |
| 6328 | /* 17055 */ GIM_Try, /*On fail goto*//*Label 371*/ GIMT_Encode4(17100), // Rule ID 345 // |
| 6329 | /* 17060 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsThumb_IsThumb1Only), |
| 6330 | /* 17063 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 6331 | /* 17067 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 6332 | /* 17071 */ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(255), |
| 6333 | /* 17082 */ // (and:{ *:[i32] } tGPR:{ *:[i32] }:$Rm, 255:{ *:[i32] }) => (tUXTB:{ *:[i32] } tGPR:{ *:[i32] }:$Rm) |
| 6334 | /* 17082 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tUXTB), |
| 6335 | /* 17085 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6336 | /* 17087 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 6337 | /* 17089 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6338 | /* 17092 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6339 | /* 17098 */ GIR_RootConstrainSelectedInstOperands, |
| 6340 | /* 17099 */ // GIR_Coverage, 345, |
| 6341 | /* 17099 */ GIR_EraseRootFromParent_Done, |
| 6342 | /* 17100 */ // Label 371: @17100 |
| 6343 | /* 17100 */ GIM_Try, /*On fail goto*//*Label 372*/ GIMT_Encode4(17145), // Rule ID 346 // |
| 6344 | /* 17105 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsThumb_IsThumb1Only), |
| 6345 | /* 17108 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 6346 | /* 17112 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 6347 | /* 17116 */ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(65535), |
| 6348 | /* 17127 */ // (and:{ *:[i32] } tGPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] }) => (tUXTH:{ *:[i32] } tGPR:{ *:[i32] }:$Rm) |
| 6349 | /* 17127 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tUXTH), |
| 6350 | /* 17130 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6351 | /* 17132 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 6352 | /* 17134 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6353 | /* 17137 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6354 | /* 17143 */ GIR_RootConstrainSelectedInstOperands, |
| 6355 | /* 17144 */ // GIR_Coverage, 346, |
| 6356 | /* 17144 */ GIR_EraseRootFromParent_Done, |
| 6357 | /* 17145 */ // Label 372: @17145 |
| 6358 | /* 17145 */ GIM_Try, /*On fail goto*//*Label 373*/ GIMT_Encode4(17204), // Rule ID 1894 // |
| 6359 | /* 17150 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 6360 | /* 17153 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 6361 | /* 17157 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 6362 | /* 17161 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 6363 | /* 17165 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 6364 | /* 17169 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm_not), |
| 6365 | /* 17173 */ // MIs[1] Operand 1 |
| 6366 | /* 17173 */ // No operand predicates |
| 6367 | /* 17173 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 6368 | /* 17175 */ // (and:{ *:[i32] } GPR:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_mod_imm_not>><<X:imm_not_XFORM>>:$imm) => (BICri:{ *:[i32] } GPR:{ *:[i32] }:$src, (imm_not_XFORM:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_mod_imm_not>>:$imm)) |
| 6369 | /* 17175 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::BICri), |
| 6370 | /* 17178 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6371 | /* 17180 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 6372 | /* 17182 */ GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderInvertedImm), // imm |
| 6373 | /* 17187 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6374 | /* 17190 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6375 | /* 17196 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6376 | /* 17202 */ GIR_RootConstrainSelectedInstOperands, |
| 6377 | /* 17203 */ // GIR_Coverage, 1894, |
| 6378 | /* 17203 */ GIR_EraseRootFromParent_Done, |
| 6379 | /* 17204 */ // Label 373: @17204 |
| 6380 | /* 17204 */ GIM_Try, /*On fail goto*//*Label 374*/ GIMT_Encode4(17261), // Rule ID 147 // |
| 6381 | /* 17209 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 6382 | /* 17212 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 6383 | /* 17216 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 6384 | /* 17220 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 6385 | /* 17224 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 6386 | /* 17228 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm), |
| 6387 | /* 17232 */ // MIs[1] Operand 1 |
| 6388 | /* 17232 */ // No operand predicates |
| 6389 | /* 17232 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 6390 | /* 17234 */ // (and:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm) => (ANDri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 6391 | /* 17234 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::ANDri), |
| 6392 | /* 17237 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6393 | /* 17239 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 6394 | /* 17241 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 6395 | /* 17244 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6396 | /* 17247 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6397 | /* 17253 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6398 | /* 17259 */ GIR_RootConstrainSelectedInstOperands, |
| 6399 | /* 17260 */ // GIR_Coverage, 147, |
| 6400 | /* 17260 */ GIR_EraseRootFromParent_Done, |
| 6401 | /* 17261 */ // Label 374: @17261 |
| 6402 | /* 17261 */ GIM_Try, /*On fail goto*//*Label 375*/ GIMT_Encode4(17318), // Rule ID 481 // |
| 6403 | /* 17266 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 6404 | /* 17269 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6405 | /* 17273 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6406 | /* 17277 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 6407 | /* 17281 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 6408 | /* 17285 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm), |
| 6409 | /* 17289 */ // MIs[1] Operand 1 |
| 6410 | /* 17289 */ // No operand predicates |
| 6411 | /* 17289 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 6412 | /* 17291 */ // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm) => (t2ANDri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 6413 | /* 17291 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ANDri), |
| 6414 | /* 17294 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6415 | /* 17296 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 6416 | /* 17298 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 6417 | /* 17301 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6418 | /* 17304 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6419 | /* 17310 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6420 | /* 17316 */ GIR_RootConstrainSelectedInstOperands, |
| 6421 | /* 17317 */ // GIR_Coverage, 481, |
| 6422 | /* 17317 */ GIR_EraseRootFromParent_Done, |
| 6423 | /* 17318 */ // Label 375: @17318 |
| 6424 | /* 17318 */ GIM_Try, /*On fail goto*//*Label 376*/ GIMT_Encode4(17369), // Rule ID 163 // |
| 6425 | /* 17323 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6T2_IsARM), |
| 6426 | /* 17326 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 6427 | /* 17330 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 6428 | /* 17334 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 6429 | /* 17338 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 6430 | /* 17342 */ // MIs[1] Operand 1 |
| 6431 | /* 17342 */ // No operand predicates |
| 6432 | /* 17342 */ GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_bf_inv_mask_imm), |
| 6433 | /* 17346 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 6434 | /* 17348 */ // (and:{ *:[i32] } GPR:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_bf_inv_mask_imm>>:$imm) => (BFC:{ *:[i32] } GPR:{ *:[i32] }:$src, (imm:{ *:[i32] }):$imm) |
| 6435 | /* 17348 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::BFC), |
| 6436 | /* 17351 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6437 | /* 17353 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 6438 | /* 17355 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 6439 | /* 17358 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6440 | /* 17361 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6441 | /* 17367 */ GIR_RootConstrainSelectedInstOperands, |
| 6442 | /* 17368 */ // GIR_Coverage, 163, |
| 6443 | /* 17368 */ GIR_EraseRootFromParent_Done, |
| 6444 | /* 17369 */ // Label 376: @17369 |
| 6445 | /* 17369 */ GIM_Try, /*On fail goto*//*Label 377*/ GIMT_Encode4(17420), // Rule ID 493 // |
| 6446 | /* 17374 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 6447 | /* 17377 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6448 | /* 17381 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6449 | /* 17385 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 6450 | /* 17389 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 6451 | /* 17393 */ // MIs[1] Operand 1 |
| 6452 | /* 17393 */ // No operand predicates |
| 6453 | /* 17393 */ GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_bf_inv_mask_imm), |
| 6454 | /* 17397 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 6455 | /* 17399 */ // (and:{ *:[i32] } rGPR:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_bf_inv_mask_imm>>:$imm) => (t2BFC:{ *:[i32] } rGPR:{ *:[i32] }:$src, (imm:{ *:[i32] }):$imm) |
| 6456 | /* 17399 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2BFC), |
| 6457 | /* 17402 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6458 | /* 17404 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 6459 | /* 17406 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 6460 | /* 17409 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6461 | /* 17412 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6462 | /* 17418 */ GIR_RootConstrainSelectedInstOperands, |
| 6463 | /* 17419 */ // GIR_Coverage, 493, |
| 6464 | /* 17419 */ GIR_EraseRootFromParent_Done, |
| 6465 | /* 17420 */ // Label 377: @17420 |
| 6466 | /* 17420 */ GIM_Try, /*On fail goto*//*Label 378*/ GIMT_Encode4(17466), // Rule ID 148 // |
| 6467 | /* 17425 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 6468 | /* 17428 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 6469 | /* 17432 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 6470 | /* 17436 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 6471 | /* 17440 */ // (and:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (ANDrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) |
| 6472 | /* 17440 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::ANDrr), |
| 6473 | /* 17443 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6474 | /* 17445 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 6475 | /* 17447 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 6476 | /* 17449 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6477 | /* 17452 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6478 | /* 17458 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6479 | /* 17464 */ GIR_RootConstrainSelectedInstOperands, |
| 6480 | /* 17465 */ // GIR_Coverage, 148, |
| 6481 | /* 17465 */ GIR_EraseRootFromParent_Done, |
| 6482 | /* 17466 */ // Label 378: @17466 |
| 6483 | /* 17466 */ GIM_Try, /*On fail goto*//*Label 379*/ GIMT_Encode4(17512), // Rule ID 310 // |
| 6484 | /* 17471 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), |
| 6485 | /* 17474 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 6486 | /* 17478 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 6487 | /* 17482 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 6488 | /* 17486 */ // (and:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) => (tAND:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) |
| 6489 | /* 17486 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tAND), |
| 6490 | /* 17489 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn] |
| 6491 | /* 17491 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define | RegState::Dead), |
| 6492 | /* 17497 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 6493 | /* 17499 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 6494 | /* 17501 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6495 | /* 17504 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6496 | /* 17510 */ GIR_RootConstrainSelectedInstOperands, |
| 6497 | /* 17511 */ // GIR_Coverage, 310, |
| 6498 | /* 17511 */ GIR_EraseRootFromParent_Done, |
| 6499 | /* 17512 */ // Label 379: @17512 |
| 6500 | /* 17512 */ GIM_Try, /*On fail goto*//*Label 380*/ GIMT_Encode4(17558), // Rule ID 482 // |
| 6501 | /* 17517 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 6502 | /* 17520 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6503 | /* 17524 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6504 | /* 17528 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6505 | /* 17532 */ // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2ANDrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 6506 | /* 17532 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ANDrr), |
| 6507 | /* 17535 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6508 | /* 17537 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 6509 | /* 17539 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 6510 | /* 17541 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6511 | /* 17544 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6512 | /* 17550 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6513 | /* 17556 */ GIR_RootConstrainSelectedInstOperands, |
| 6514 | /* 17557 */ // GIR_Coverage, 482, |
| 6515 | /* 17557 */ GIR_EraseRootFromParent_Done, |
| 6516 | /* 17558 */ // Label 380: @17558 |
| 6517 | /* 17558 */ GIM_Reject, |
| 6518 | /* 17559 */ // Label 348: @17559 |
| 6519 | /* 17559 */ GIM_Reject, |
| 6520 | /* 17560 */ // Label 335: @17560 |
| 6521 | /* 17560 */ GIM_Try, /*On fail goto*//*Label 381*/ GIMT_Encode4(17606), // Rule ID 2526 // |
| 6522 | /* 17565 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 6523 | /* 17568 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 6524 | /* 17571 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 6525 | /* 17574 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 6526 | /* 17578 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 6527 | /* 17582 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 6528 | /* 17586 */ // (and:{ *:[v1i64] } DPR:{ *:[v1i64] }:$LHS, DPR:{ *:[v1i64] }:$RHS) => (VANDd:{ *:[v1i64] } DPR:{ *:[v1i64] }:$LHS, DPR:{ *:[v1i64] }:$RHS) |
| 6529 | /* 17586 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VANDd), |
| 6530 | /* 17589 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 6531 | /* 17591 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS |
| 6532 | /* 17593 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS |
| 6533 | /* 17595 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6534 | /* 17598 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6535 | /* 17604 */ GIR_RootConstrainSelectedInstOperands, |
| 6536 | /* 17605 */ // GIR_Coverage, 2526, |
| 6537 | /* 17605 */ GIR_EraseRootFromParent_Done, |
| 6538 | /* 17606 */ // Label 381: @17606 |
| 6539 | /* 17606 */ GIM_Reject, |
| 6540 | /* 17607 */ // Label 336: @17607 |
| 6541 | /* 17607 */ GIM_Try, /*On fail goto*//*Label 382*/ GIMT_Encode4(17724), // Rule ID 1826 // |
| 6542 | /* 17612 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 6543 | /* 17615 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s1, |
| 6544 | /* 17618 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s1, |
| 6545 | /* 17621 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 6546 | /* 17625 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 6547 | /* 17629 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 6548 | /* 17633 */ // (and:{ *:[v2i1] } VCCR:{ *:[v2i1] }:$p1, VCCR:{ *:[v2i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v2i1] } (t2ANDrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v2i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v2i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] }) |
| 6549 | /* 17633 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, |
| 6550 | /* 17636 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 6551 | /* 17640 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6552 | /* 17645 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2 |
| 6553 | /* 17649 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 6554 | /* 17654 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 6555 | /* 17657 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 6556 | /* 17661 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6557 | /* 17666 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1 |
| 6558 | /* 17670 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 6559 | /* 17675 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 6560 | /* 17678 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2ANDrr), |
| 6561 | /* 17682 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6562 | /* 17687 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 6563 | /* 17690 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 6564 | /* 17693 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 6565 | /* 17696 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6566 | /* 17702 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6567 | /* 17708 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 6568 | /* 17710 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 6569 | /* 17713 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 6570 | /* 17715 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 6571 | /* 17718 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID), |
| 6572 | /* 17723 */ // GIR_Coverage, 1826, |
| 6573 | /* 17723 */ GIR_EraseRootFromParent_Done, |
| 6574 | /* 17724 */ // Label 382: @17724 |
| 6575 | /* 17724 */ GIM_Reject, |
| 6576 | /* 17725 */ // Label 337: @17725 |
| 6577 | /* 17725 */ GIM_Try, /*On fail goto*//*Label 383*/ GIMT_Encode4(17771), // Rule ID 1133 // |
| 6578 | /* 17730 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 6579 | /* 17733 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 6580 | /* 17736 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 6581 | /* 17739 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 6582 | /* 17743 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 6583 | /* 17747 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 6584 | /* 17751 */ // (and:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VANDd:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 6585 | /* 17751 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VANDd), |
| 6586 | /* 17754 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 6587 | /* 17756 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 6588 | /* 17758 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 6589 | /* 17760 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6590 | /* 17763 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6591 | /* 17769 */ GIR_RootConstrainSelectedInstOperands, |
| 6592 | /* 17770 */ // GIR_Coverage, 1133, |
| 6593 | /* 17770 */ GIR_EraseRootFromParent_Done, |
| 6594 | /* 17771 */ // Label 383: @17771 |
| 6595 | /* 17771 */ GIM_Reject, |
| 6596 | /* 17772 */ // Label 338: @17772 |
| 6597 | /* 17772 */ GIM_Try, /*On fail goto*//*Label 384*/ GIMT_Encode4(17885), |
| 6598 | /* 17777 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 6599 | /* 17780 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 6600 | /* 17783 */ GIM_Try, /*On fail goto*//*Label 385*/ GIMT_Encode4(17823), // Rule ID 2529 // |
| 6601 | /* 17788 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 6602 | /* 17791 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 6603 | /* 17795 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 6604 | /* 17799 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 6605 | /* 17803 */ // (and:{ *:[v2i64] } QPR:{ *:[v2i64] }:$LHS, QPR:{ *:[v2i64] }:$RHS) => (VANDq:{ *:[v2i64] } QPR:{ *:[v2i64] }:$LHS, QPR:{ *:[v2i64] }:$RHS) |
| 6606 | /* 17803 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VANDq), |
| 6607 | /* 17806 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 6608 | /* 17808 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS |
| 6609 | /* 17810 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS |
| 6610 | /* 17812 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6611 | /* 17815 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6612 | /* 17821 */ GIR_RootConstrainSelectedInstOperands, |
| 6613 | /* 17822 */ // GIR_Coverage, 2529, |
| 6614 | /* 17822 */ GIR_EraseRootFromParent_Done, |
| 6615 | /* 17823 */ // Label 385: @17823 |
| 6616 | /* 17823 */ GIM_Try, /*On fail goto*//*Label 386*/ GIMT_Encode4(17884), // Rule ID 3370 // |
| 6617 | /* 17828 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 6618 | /* 17831 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 6619 | /* 17835 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 6620 | /* 17839 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 6621 | /* 17843 */ // (and:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$Qm, MQPR:{ *:[v2i64] }:$Qn) => (MVE_VAND:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$Qm, MQPR:{ *:[v2i64] }:$Qn) |
| 6622 | /* 17843 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 6623 | /* 17846 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 6624 | /* 17850 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6625 | /* 17855 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VAND), |
| 6626 | /* 17858 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 6627 | /* 17860 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 6628 | /* 17862 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 6629 | /* 17864 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 6630 | /* 17867 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6631 | /* 17873 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6632 | /* 17879 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 6633 | /* 17882 */ GIR_RootConstrainSelectedInstOperands, |
| 6634 | /* 17883 */ // GIR_Coverage, 3370, |
| 6635 | /* 17883 */ GIR_EraseRootFromParent_Done, |
| 6636 | /* 17884 */ // Label 386: @17884 |
| 6637 | /* 17884 */ GIM_Reject, |
| 6638 | /* 17885 */ // Label 384: @17885 |
| 6639 | /* 17885 */ GIM_Reject, |
| 6640 | /* 17886 */ // Label 339: @17886 |
| 6641 | /* 17886 */ GIM_Try, /*On fail goto*//*Label 387*/ GIMT_Encode4(18003), // Rule ID 1827 // |
| 6642 | /* 17891 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 6643 | /* 17894 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s1, |
| 6644 | /* 17897 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s1, |
| 6645 | /* 17900 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 6646 | /* 17904 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 6647 | /* 17908 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 6648 | /* 17912 */ // (and:{ *:[v4i1] } VCCR:{ *:[v4i1] }:$p1, VCCR:{ *:[v4i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v4i1] } (t2ANDrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v4i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v4i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] }) |
| 6649 | /* 17912 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, |
| 6650 | /* 17915 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 6651 | /* 17919 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6652 | /* 17924 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2 |
| 6653 | /* 17928 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 6654 | /* 17933 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 6655 | /* 17936 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 6656 | /* 17940 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6657 | /* 17945 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1 |
| 6658 | /* 17949 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 6659 | /* 17954 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 6660 | /* 17957 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2ANDrr), |
| 6661 | /* 17961 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6662 | /* 17966 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 6663 | /* 17969 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 6664 | /* 17972 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 6665 | /* 17975 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6666 | /* 17981 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6667 | /* 17987 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 6668 | /* 17989 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 6669 | /* 17992 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 6670 | /* 17994 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 6671 | /* 17997 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID), |
| 6672 | /* 18002 */ // GIR_Coverage, 1827, |
| 6673 | /* 18002 */ GIR_EraseRootFromParent_Done, |
| 6674 | /* 18003 */ // Label 387: @18003 |
| 6675 | /* 18003 */ GIM_Reject, |
| 6676 | /* 18004 */ // Label 340: @18004 |
| 6677 | /* 18004 */ GIM_Try, /*On fail goto*//*Label 388*/ GIMT_Encode4(18050), // Rule ID 2525 // |
| 6678 | /* 18009 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 6679 | /* 18012 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 6680 | /* 18015 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 6681 | /* 18018 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 6682 | /* 18022 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 6683 | /* 18026 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 6684 | /* 18030 */ // (and:{ *:[v4i16] } DPR:{ *:[v4i16] }:$LHS, DPR:{ *:[v4i16] }:$RHS) => (VANDd:{ *:[v4i16] } DPR:{ *:[v4i16] }:$LHS, DPR:{ *:[v4i16] }:$RHS) |
| 6685 | /* 18030 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VANDd), |
| 6686 | /* 18033 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 6687 | /* 18035 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS |
| 6688 | /* 18037 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS |
| 6689 | /* 18039 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6690 | /* 18042 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6691 | /* 18048 */ GIR_RootConstrainSelectedInstOperands, |
| 6692 | /* 18049 */ // GIR_Coverage, 2525, |
| 6693 | /* 18049 */ GIR_EraseRootFromParent_Done, |
| 6694 | /* 18050 */ // Label 388: @18050 |
| 6695 | /* 18050 */ GIM_Reject, |
| 6696 | /* 18051 */ // Label 341: @18051 |
| 6697 | /* 18051 */ GIM_Try, /*On fail goto*//*Label 389*/ GIMT_Encode4(18164), |
| 6698 | /* 18056 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 6699 | /* 18059 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 6700 | /* 18062 */ GIM_Try, /*On fail goto*//*Label 390*/ GIMT_Encode4(18102), // Rule ID 1134 // |
| 6701 | /* 18067 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 6702 | /* 18070 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 6703 | /* 18074 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 6704 | /* 18078 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 6705 | /* 18082 */ // (and:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VANDq:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 6706 | /* 18082 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VANDq), |
| 6707 | /* 18085 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 6708 | /* 18087 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 6709 | /* 18089 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 6710 | /* 18091 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6711 | /* 18094 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6712 | /* 18100 */ GIR_RootConstrainSelectedInstOperands, |
| 6713 | /* 18101 */ // GIR_Coverage, 1134, |
| 6714 | /* 18101 */ GIR_EraseRootFromParent_Done, |
| 6715 | /* 18102 */ // Label 390: @18102 |
| 6716 | /* 18102 */ GIM_Try, /*On fail goto*//*Label 391*/ GIMT_Encode4(18163), // Rule ID 3366 // |
| 6717 | /* 18107 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 6718 | /* 18110 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 6719 | /* 18114 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 6720 | /* 18118 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 6721 | /* 18122 */ // (and:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VAND:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 6722 | /* 18122 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 6723 | /* 18125 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 6724 | /* 18129 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6725 | /* 18134 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VAND), |
| 6726 | /* 18137 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 6727 | /* 18139 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 6728 | /* 18141 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 6729 | /* 18143 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 6730 | /* 18146 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6731 | /* 18152 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6732 | /* 18158 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 6733 | /* 18161 */ GIR_RootConstrainSelectedInstOperands, |
| 6734 | /* 18162 */ // GIR_Coverage, 3366, |
| 6735 | /* 18162 */ GIR_EraseRootFromParent_Done, |
| 6736 | /* 18163 */ // Label 391: @18163 |
| 6737 | /* 18163 */ GIM_Reject, |
| 6738 | /* 18164 */ // Label 389: @18164 |
| 6739 | /* 18164 */ GIM_Reject, |
| 6740 | /* 18165 */ // Label 342: @18165 |
| 6741 | /* 18165 */ GIM_Try, /*On fail goto*//*Label 392*/ GIMT_Encode4(18282), // Rule ID 1828 // |
| 6742 | /* 18170 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 6743 | /* 18173 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s1, |
| 6744 | /* 18176 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s1, |
| 6745 | /* 18179 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 6746 | /* 18183 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 6747 | /* 18187 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 6748 | /* 18191 */ // (and:{ *:[v8i1] } VCCR:{ *:[v8i1] }:$p1, VCCR:{ *:[v8i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v8i1] } (t2ANDrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v8i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v8i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] }) |
| 6749 | /* 18191 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, |
| 6750 | /* 18194 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 6751 | /* 18198 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6752 | /* 18203 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2 |
| 6753 | /* 18207 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 6754 | /* 18212 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 6755 | /* 18215 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 6756 | /* 18219 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6757 | /* 18224 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1 |
| 6758 | /* 18228 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 6759 | /* 18233 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 6760 | /* 18236 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2ANDrr), |
| 6761 | /* 18240 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6762 | /* 18245 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 6763 | /* 18248 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 6764 | /* 18251 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 6765 | /* 18254 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6766 | /* 18260 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6767 | /* 18266 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 6768 | /* 18268 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 6769 | /* 18271 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 6770 | /* 18273 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 6771 | /* 18276 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID), |
| 6772 | /* 18281 */ // GIR_Coverage, 1828, |
| 6773 | /* 18281 */ GIR_EraseRootFromParent_Done, |
| 6774 | /* 18282 */ // Label 392: @18282 |
| 6775 | /* 18282 */ GIM_Reject, |
| 6776 | /* 18283 */ // Label 343: @18283 |
| 6777 | /* 18283 */ GIM_Try, /*On fail goto*//*Label 393*/ GIMT_Encode4(18329), // Rule ID 2524 // |
| 6778 | /* 18288 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 6779 | /* 18291 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 6780 | /* 18294 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 6781 | /* 18297 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 6782 | /* 18301 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 6783 | /* 18305 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 6784 | /* 18309 */ // (and:{ *:[v8i8] } DPR:{ *:[v8i8] }:$LHS, DPR:{ *:[v8i8] }:$RHS) => (VANDd:{ *:[v8i8] } DPR:{ *:[v8i8] }:$LHS, DPR:{ *:[v8i8] }:$RHS) |
| 6785 | /* 18309 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VANDd), |
| 6786 | /* 18312 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 6787 | /* 18314 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS |
| 6788 | /* 18316 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS |
| 6789 | /* 18318 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6790 | /* 18321 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6791 | /* 18327 */ GIR_RootConstrainSelectedInstOperands, |
| 6792 | /* 18328 */ // GIR_Coverage, 2524, |
| 6793 | /* 18328 */ GIR_EraseRootFromParent_Done, |
| 6794 | /* 18329 */ // Label 393: @18329 |
| 6795 | /* 18329 */ GIM_Reject, |
| 6796 | /* 18330 */ // Label 344: @18330 |
| 6797 | /* 18330 */ GIM_Try, /*On fail goto*//*Label 394*/ GIMT_Encode4(18443), |
| 6798 | /* 18335 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 6799 | /* 18338 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 6800 | /* 18341 */ GIM_Try, /*On fail goto*//*Label 395*/ GIMT_Encode4(18381), // Rule ID 2528 // |
| 6801 | /* 18346 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 6802 | /* 18349 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 6803 | /* 18353 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 6804 | /* 18357 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 6805 | /* 18361 */ // (and:{ *:[v8i16] } QPR:{ *:[v8i16] }:$LHS, QPR:{ *:[v8i16] }:$RHS) => (VANDq:{ *:[v8i16] } QPR:{ *:[v8i16] }:$LHS, QPR:{ *:[v8i16] }:$RHS) |
| 6806 | /* 18361 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VANDq), |
| 6807 | /* 18364 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 6808 | /* 18366 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS |
| 6809 | /* 18368 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS |
| 6810 | /* 18370 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6811 | /* 18373 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6812 | /* 18379 */ GIR_RootConstrainSelectedInstOperands, |
| 6813 | /* 18380 */ // GIR_Coverage, 2528, |
| 6814 | /* 18380 */ GIR_EraseRootFromParent_Done, |
| 6815 | /* 18381 */ // Label 395: @18381 |
| 6816 | /* 18381 */ GIM_Try, /*On fail goto*//*Label 396*/ GIMT_Encode4(18442), // Rule ID 3362 // |
| 6817 | /* 18386 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 6818 | /* 18389 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 6819 | /* 18393 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 6820 | /* 18397 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 6821 | /* 18401 */ // (and:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VAND:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 6822 | /* 18401 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 6823 | /* 18404 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 6824 | /* 18408 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6825 | /* 18413 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VAND), |
| 6826 | /* 18416 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 6827 | /* 18418 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 6828 | /* 18420 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 6829 | /* 18422 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 6830 | /* 18425 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6831 | /* 18431 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6832 | /* 18437 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 6833 | /* 18440 */ GIR_RootConstrainSelectedInstOperands, |
| 6834 | /* 18441 */ // GIR_Coverage, 3362, |
| 6835 | /* 18441 */ GIR_EraseRootFromParent_Done, |
| 6836 | /* 18442 */ // Label 396: @18442 |
| 6837 | /* 18442 */ GIM_Reject, |
| 6838 | /* 18443 */ // Label 394: @18443 |
| 6839 | /* 18443 */ GIM_Reject, |
| 6840 | /* 18444 */ // Label 345: @18444 |
| 6841 | /* 18444 */ GIM_Try, /*On fail goto*//*Label 397*/ GIMT_Encode4(18561), // Rule ID 1829 // |
| 6842 | /* 18449 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 6843 | /* 18452 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s1, |
| 6844 | /* 18455 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s1, |
| 6845 | /* 18458 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 6846 | /* 18462 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 6847 | /* 18466 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 6848 | /* 18470 */ // (and:{ *:[v16i1] } VCCR:{ *:[v16i1] }:$p1, VCCR:{ *:[v16i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v16i1] } (t2ANDrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v16i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v16i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] }) |
| 6849 | /* 18470 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, |
| 6850 | /* 18473 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 6851 | /* 18477 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6852 | /* 18482 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2 |
| 6853 | /* 18486 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 6854 | /* 18491 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 6855 | /* 18494 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 6856 | /* 18498 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6857 | /* 18503 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1 |
| 6858 | /* 18507 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 6859 | /* 18512 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 6860 | /* 18515 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2ANDrr), |
| 6861 | /* 18519 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6862 | /* 18524 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 6863 | /* 18527 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 6864 | /* 18530 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 6865 | /* 18533 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6866 | /* 18539 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6867 | /* 18545 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 6868 | /* 18547 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 6869 | /* 18550 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 6870 | /* 18552 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 6871 | /* 18555 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID), |
| 6872 | /* 18560 */ // GIR_Coverage, 1829, |
| 6873 | /* 18560 */ GIR_EraseRootFromParent_Done, |
| 6874 | /* 18561 */ // Label 397: @18561 |
| 6875 | /* 18561 */ GIM_Reject, |
| 6876 | /* 18562 */ // Label 346: @18562 |
| 6877 | /* 18562 */ GIM_Try, /*On fail goto*//*Label 398*/ GIMT_Encode4(18675), |
| 6878 | /* 18567 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 6879 | /* 18570 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 6880 | /* 18573 */ GIM_Try, /*On fail goto*//*Label 399*/ GIMT_Encode4(18613), // Rule ID 2527 // |
| 6881 | /* 18578 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 6882 | /* 18581 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 6883 | /* 18585 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 6884 | /* 18589 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 6885 | /* 18593 */ // (and:{ *:[v16i8] } QPR:{ *:[v16i8] }:$LHS, QPR:{ *:[v16i8] }:$RHS) => (VANDq:{ *:[v16i8] } QPR:{ *:[v16i8] }:$LHS, QPR:{ *:[v16i8] }:$RHS) |
| 6886 | /* 18593 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VANDq), |
| 6887 | /* 18596 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 6888 | /* 18598 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS |
| 6889 | /* 18600 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS |
| 6890 | /* 18602 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6891 | /* 18605 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6892 | /* 18611 */ GIR_RootConstrainSelectedInstOperands, |
| 6893 | /* 18612 */ // GIR_Coverage, 2527, |
| 6894 | /* 18612 */ GIR_EraseRootFromParent_Done, |
| 6895 | /* 18613 */ // Label 399: @18613 |
| 6896 | /* 18613 */ GIM_Try, /*On fail goto*//*Label 400*/ GIMT_Encode4(18674), // Rule ID 3358 // |
| 6897 | /* 18618 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 6898 | /* 18621 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 6899 | /* 18625 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 6900 | /* 18629 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 6901 | /* 18633 */ // (and:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VAND:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 6902 | /* 18633 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 6903 | /* 18636 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 6904 | /* 18640 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6905 | /* 18645 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VAND), |
| 6906 | /* 18648 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 6907 | /* 18650 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 6908 | /* 18652 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 6909 | /* 18654 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 6910 | /* 18657 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6911 | /* 18663 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6912 | /* 18669 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 6913 | /* 18672 */ GIR_RootConstrainSelectedInstOperands, |
| 6914 | /* 18673 */ // GIR_Coverage, 3358, |
| 6915 | /* 18673 */ GIR_EraseRootFromParent_Done, |
| 6916 | /* 18674 */ // Label 400: @18674 |
| 6917 | /* 18674 */ GIM_Reject, |
| 6918 | /* 18675 */ // Label 398: @18675 |
| 6919 | /* 18675 */ GIM_Reject, |
| 6920 | /* 18676 */ // Label 347: @18676 |
| 6921 | /* 18676 */ GIM_Reject, |
| 6922 | /* 18677 */ // Label 6: @18677 |
| 6923 | /* 18677 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(16), /*)*//*default:*//*Label 414*/ GIMT_Encode4(24485), |
| 6924 | /* 18688 */ /*GILLT_s32*//*Label 401*/ GIMT_Encode4(18748), |
| 6925 | /* 18692 */ /*GILLT_s64*//*Label 402*/ GIMT_Encode4(23369), |
| 6926 | /* 18696 */ /*GILLT_v2s1*//*Label 403*/ GIMT_Encode4(23416), |
| 6927 | /* 18700 */ /*GILLT_v2s32*//*Label 404*/ GIMT_Encode4(23534), |
| 6928 | /* 18704 */ /*GILLT_v2s64*//*Label 405*/ GIMT_Encode4(23581), |
| 6929 | /* 18708 */ /*GILLT_v4s1*//*Label 406*/ GIMT_Encode4(23695), |
| 6930 | /* 18712 */ /*GILLT_v4s16*//*Label 407*/ GIMT_Encode4(23813), |
| 6931 | /* 18716 */ /*GILLT_v4s32*//*Label 408*/ GIMT_Encode4(23860), GIMT_Encode4(0), |
| 6932 | /* 18724 */ /*GILLT_v8s1*//*Label 409*/ GIMT_Encode4(23974), |
| 6933 | /* 18728 */ /*GILLT_v8s8*//*Label 410*/ GIMT_Encode4(24092), |
| 6934 | /* 18732 */ /*GILLT_v8s16*//*Label 411*/ GIMT_Encode4(24139), GIMT_Encode4(0), |
| 6935 | /* 18740 */ /*GILLT_v16s1*//*Label 412*/ GIMT_Encode4(24253), |
| 6936 | /* 18744 */ /*GILLT_v16s8*//*Label 413*/ GIMT_Encode4(24371), |
| 6937 | /* 18748 */ // Label 401: @18748 |
| 6938 | /* 18748 */ GIM_Try, /*On fail goto*//*Label 415*/ GIMT_Encode4(23368), |
| 6939 | /* 18753 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 6940 | /* 18756 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 6941 | /* 18759 */ GIM_Try, /*On fail goto*//*Label 416*/ GIMT_Encode4(18886), // Rule ID 5655 // |
| 6942 | /* 18764 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 6943 | /* 18767 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 6944 | /* 18771 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 6945 | /* 18775 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 6946 | /* 18779 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 6947 | /* 18783 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 6948 | /* 18787 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 6949 | /* 18791 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 6950 | /* 18795 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 6951 | /* 18799 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 6952 | /* 18803 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 6953 | /* 18808 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 8, |
| 6954 | /* 18812 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(255), |
| 6955 | /* 18823 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 6956 | /* 18827 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 6957 | /* 18831 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 6958 | /* 18835 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 6959 | /* 18839 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4] |
| 6960 | /* 18843 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_SHL), |
| 6961 | /* 18847 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32, |
| 6962 | /* 18851 */ // MIs[4] Rm |
| 6963 | /* 18851 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 6964 | /* 18856 */ GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 24, |
| 6965 | /* 18860 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16, |
| 6966 | /* 18864 */ GIM_CheckIsSafeToFold, /*NumInsns*/4, |
| 6967 | /* 18866 */ // (or:{ *:[i32] } (and:{ *:[i32] } (srl:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 8:{ *:[i32] }), 255:{ *:[i32] }), (sra:{ *:[i32] } (shl:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 24:{ *:[i32] }), 16:{ *:[i32] })) => (REVSH:{ *:[i32] } GPR:{ *:[i32] }:$Rm) |
| 6968 | /* 18866 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::REVSH), |
| 6969 | /* 18869 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6970 | /* 18871 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 6971 | /* 18875 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6972 | /* 18878 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6973 | /* 18884 */ GIR_RootConstrainSelectedInstOperands, |
| 6974 | /* 18885 */ // GIR_Coverage, 5655, |
| 6975 | /* 18885 */ GIR_EraseRootFromParent_Done, |
| 6976 | /* 18886 */ // Label 416: @18886 |
| 6977 | /* 18886 */ GIM_Try, /*On fail goto*//*Label 417*/ GIMT_Encode4(19013), // Rule ID 5697 // |
| 6978 | /* 18891 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 6979 | /* 18894 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6980 | /* 18898 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 6981 | /* 18902 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 6982 | /* 18906 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 6983 | /* 18910 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 6984 | /* 18914 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 6985 | /* 18918 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 6986 | /* 18922 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 6987 | /* 18926 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 6988 | /* 18930 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6989 | /* 18935 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 8, |
| 6990 | /* 18939 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(255), |
| 6991 | /* 18950 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 6992 | /* 18954 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 6993 | /* 18958 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 6994 | /* 18962 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 6995 | /* 18966 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4] |
| 6996 | /* 18970 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_SHL), |
| 6997 | /* 18974 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32, |
| 6998 | /* 18978 */ // MIs[4] Rm |
| 6999 | /* 18978 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 7000 | /* 18983 */ GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 24, |
| 7001 | /* 18987 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16, |
| 7002 | /* 18991 */ GIM_CheckIsSafeToFold, /*NumInsns*/4, |
| 7003 | /* 18993 */ // (or:{ *:[i32] } (and:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 8:{ *:[i32] }), 255:{ *:[i32] }), (sra:{ *:[i32] } (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 24:{ *:[i32] }), 16:{ *:[i32] })) => (t2REVSH:{ *:[i32] } rGPR:{ *:[i32] }:$Rm) |
| 7004 | /* 18993 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2REVSH), |
| 7005 | /* 18996 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 7006 | /* 18998 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 7007 | /* 19002 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7008 | /* 19005 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7009 | /* 19011 */ GIR_RootConstrainSelectedInstOperands, |
| 7010 | /* 19012 */ // GIR_Coverage, 5697, |
| 7011 | /* 19012 */ GIR_EraseRootFromParent_Done, |
| 7012 | /* 19013 */ // Label 417: @19013 |
| 7013 | /* 19013 */ GIM_Try, /*On fail goto*//*Label 418*/ GIMT_Encode4(19140), // Rule ID 1914 // |
| 7014 | /* 19018 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 7015 | /* 19021 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 7016 | /* 19025 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 7017 | /* 19029 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 7018 | /* 19033 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 7019 | /* 19037 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 7020 | /* 19041 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 7021 | /* 19045 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SHL), |
| 7022 | /* 19049 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 7023 | /* 19053 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 7024 | /* 19057 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 7025 | /* 19062 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 24, |
| 7026 | /* 19066 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16, |
| 7027 | /* 19070 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 7028 | /* 19074 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND), |
| 7029 | /* 19078 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 7030 | /* 19082 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 7031 | /* 19086 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4] |
| 7032 | /* 19090 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 7033 | /* 19094 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32, |
| 7034 | /* 19098 */ // MIs[4] Rm |
| 7035 | /* 19098 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 7036 | /* 19103 */ GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 8, |
| 7037 | /* 19107 */ GIM_CheckConstantInt, /*MI*/3, /*Op*/2, GIMT_Encode8(255), |
| 7038 | /* 19118 */ GIM_CheckIsSafeToFold, /*NumInsns*/4, |
| 7039 | /* 19120 */ // (or:{ *:[i32] } (sra:{ *:[i32] } (shl:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 24:{ *:[i32] }), 16:{ *:[i32] }), (and:{ *:[i32] } (srl:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 8:{ *:[i32] }), 255:{ *:[i32] })) => (REVSH:{ *:[i32] } GPR:{ *:[i32] }:$Rm) |
| 7040 | /* 19120 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::REVSH), |
| 7041 | /* 19123 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 7042 | /* 19125 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 7043 | /* 19129 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7044 | /* 19132 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7045 | /* 19138 */ GIR_RootConstrainSelectedInstOperands, |
| 7046 | /* 19139 */ // GIR_Coverage, 1914, |
| 7047 | /* 19139 */ GIR_EraseRootFromParent_Done, |
| 7048 | /* 19140 */ // Label 418: @19140 |
| 7049 | /* 19140 */ GIM_Try, /*On fail goto*//*Label 419*/ GIMT_Encode4(19267), // Rule ID 2196 // |
| 7050 | /* 19145 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 7051 | /* 19148 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7052 | /* 19152 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 7053 | /* 19156 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 7054 | /* 19160 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 7055 | /* 19164 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 7056 | /* 19168 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 7057 | /* 19172 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SHL), |
| 7058 | /* 19176 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 7059 | /* 19180 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 7060 | /* 19184 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7061 | /* 19189 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 24, |
| 7062 | /* 19193 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16, |
| 7063 | /* 19197 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 7064 | /* 19201 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND), |
| 7065 | /* 19205 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 7066 | /* 19209 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 7067 | /* 19213 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4] |
| 7068 | /* 19217 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 7069 | /* 19221 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32, |
| 7070 | /* 19225 */ // MIs[4] Rm |
| 7071 | /* 19225 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 7072 | /* 19230 */ GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 8, |
| 7073 | /* 19234 */ GIM_CheckConstantInt, /*MI*/3, /*Op*/2, GIMT_Encode8(255), |
| 7074 | /* 19245 */ GIM_CheckIsSafeToFold, /*NumInsns*/4, |
| 7075 | /* 19247 */ // (or:{ *:[i32] } (sra:{ *:[i32] } (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 24:{ *:[i32] }), 16:{ *:[i32] }), (and:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 8:{ *:[i32] }), 255:{ *:[i32] })) => (t2REVSH:{ *:[i32] } rGPR:{ *:[i32] }:$Rm) |
| 7076 | /* 19247 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2REVSH), |
| 7077 | /* 19250 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 7078 | /* 19252 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 7079 | /* 19256 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7080 | /* 19259 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7081 | /* 19265 */ GIR_RootConstrainSelectedInstOperands, |
| 7082 | /* 19266 */ // GIR_Coverage, 2196, |
| 7083 | /* 19266 */ GIR_EraseRootFromParent_Done, |
| 7084 | /* 19267 */ // Label 419: @19267 |
| 7085 | /* 19267 */ GIM_Try, /*On fail goto*//*Label 420*/ GIMT_Encode4(19400), // Rule ID 5453 // |
| 7086 | /* 19272 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 7087 | /* 19275 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 7088 | /* 19279 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 7089 | /* 19283 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 7090 | /* 19287 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 7091 | /* 19291 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 7092 | /* 19295 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 7093 | /* 19299 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 7094 | /* 19303 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 7095 | /* 19307 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 7096 | /* 19311 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 7097 | /* 19316 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 7098 | /* 19320 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 7099 | /* 19324 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_pkh_asr_amt), |
| 7100 | /* 19328 */ // MIs[3] Operand 1 |
| 7101 | /* 19328 */ // No operand predicates |
| 7102 | /* 19328 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535), |
| 7103 | /* 19339 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] |
| 7104 | /* 19343 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND), |
| 7105 | /* 19347 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32, |
| 7106 | /* 19351 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32, |
| 7107 | /* 19355 */ GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 7108 | /* 19360 */ GIM_CheckConstantInt, /*MI*/4, /*Op*/2, GIMT_Encode8(4294901760), |
| 7109 | /* 19371 */ GIM_CheckIsSafeToFold, /*NumInsns*/4, |
| 7110 | /* 19373 */ // (or:{ *:[i32] } (and:{ *:[i32] } (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_asr_amt>>:$sh), 65535:{ *:[i32] }), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 4294901760:{ *:[i32] })) => (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh) |
| 7111 | /* 19373 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHTB), |
| 7112 | /* 19376 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 7113 | /* 19378 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Rn |
| 7114 | /* 19382 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 7115 | /* 19386 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh |
| 7116 | /* 19389 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7117 | /* 19392 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7118 | /* 19398 */ GIR_RootConstrainSelectedInstOperands, |
| 7119 | /* 19399 */ // GIR_Coverage, 5453, |
| 7120 | /* 19399 */ GIR_EraseRootFromParent_Done, |
| 7121 | /* 19400 */ // Label 420: @19400 |
| 7122 | /* 19400 */ GIM_Try, /*On fail goto*//*Label 421*/ GIMT_Encode4(19533), // Rule ID 5490 // |
| 7123 | /* 19405 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 7124 | /* 19408 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7125 | /* 19412 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 7126 | /* 19416 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 7127 | /* 19420 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 7128 | /* 19424 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 7129 | /* 19428 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 7130 | /* 19432 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 7131 | /* 19436 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 7132 | /* 19440 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 7133 | /* 19444 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7134 | /* 19449 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 7135 | /* 19453 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 7136 | /* 19457 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_pkh_asr_amt), |
| 7137 | /* 19461 */ // MIs[3] Operand 1 |
| 7138 | /* 19461 */ // No operand predicates |
| 7139 | /* 19461 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535), |
| 7140 | /* 19472 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] |
| 7141 | /* 19476 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND), |
| 7142 | /* 19480 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32, |
| 7143 | /* 19484 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32, |
| 7144 | /* 19488 */ GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7145 | /* 19493 */ GIM_CheckConstantInt, /*MI*/4, /*Op*/2, GIMT_Encode8(4294901760), |
| 7146 | /* 19504 */ GIM_CheckIsSafeToFold, /*NumInsns*/4, |
| 7147 | /* 19506 */ // (or:{ *:[i32] } (and:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_asr_amt>>:$sh), 65535:{ *:[i32] }), (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 4294901760:{ *:[i32] })) => (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh) |
| 7148 | /* 19506 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHTB), |
| 7149 | /* 19509 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 7150 | /* 19511 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Rn |
| 7151 | /* 19515 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 7152 | /* 19519 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh |
| 7153 | /* 19522 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7154 | /* 19525 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7155 | /* 19531 */ GIR_RootConstrainSelectedInstOperands, |
| 7156 | /* 19532 */ // GIR_Coverage, 5490, |
| 7157 | /* 19532 */ GIR_EraseRootFromParent_Done, |
| 7158 | /* 19533 */ // Label 421: @19533 |
| 7159 | /* 19533 */ GIM_Try, /*On fail goto*//*Label 422*/ GIMT_Encode4(19666), // Rule ID 5660 // |
| 7160 | /* 19538 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 7161 | /* 19541 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 7162 | /* 19545 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 7163 | /* 19549 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 7164 | /* 19553 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 7165 | /* 19557 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 7166 | /* 19561 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 7167 | /* 19565 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 7168 | /* 19569 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 7169 | /* 19573 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 7170 | /* 19577 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 7171 | /* 19582 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 7172 | /* 19586 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 7173 | /* 19590 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm1_15), |
| 7174 | /* 19594 */ // MIs[3] Operand 1 |
| 7175 | /* 19594 */ // No operand predicates |
| 7176 | /* 19594 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535), |
| 7177 | /* 19605 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] |
| 7178 | /* 19609 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND), |
| 7179 | /* 19613 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32, |
| 7180 | /* 19617 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32, |
| 7181 | /* 19621 */ GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 7182 | /* 19626 */ GIM_CheckConstantInt, /*MI*/4, /*Op*/2, GIMT_Encode8(4294901760), |
| 7183 | /* 19637 */ GIM_CheckIsSafeToFold, /*NumInsns*/4, |
| 7184 | /* 19639 */ // (or:{ *:[i32] } (and:{ *:[i32] } (srl:{ *:[i32] } GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh), 65535:{ *:[i32] }), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, 4294901760:{ *:[i32] })) => (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh) |
| 7185 | /* 19639 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHTB), |
| 7186 | /* 19642 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 7187 | /* 19644 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // src1 |
| 7188 | /* 19648 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2 |
| 7189 | /* 19652 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh |
| 7190 | /* 19655 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7191 | /* 19658 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7192 | /* 19664 */ GIR_RootConstrainSelectedInstOperands, |
| 7193 | /* 19665 */ // GIR_Coverage, 5660, |
| 7194 | /* 19665 */ GIR_EraseRootFromParent_Done, |
| 7195 | /* 19666 */ // Label 422: @19666 |
| 7196 | /* 19666 */ GIM_Try, /*On fail goto*//*Label 423*/ GIMT_Encode4(19799), // Rule ID 5702 // |
| 7197 | /* 19671 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 7198 | /* 19674 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7199 | /* 19678 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 7200 | /* 19682 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 7201 | /* 19686 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 7202 | /* 19690 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 7203 | /* 19694 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 7204 | /* 19698 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 7205 | /* 19702 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 7206 | /* 19706 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 7207 | /* 19710 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7208 | /* 19715 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 7209 | /* 19719 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 7210 | /* 19723 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm1_15), |
| 7211 | /* 19727 */ // MIs[3] Operand 1 |
| 7212 | /* 19727 */ // No operand predicates |
| 7213 | /* 19727 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535), |
| 7214 | /* 19738 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] |
| 7215 | /* 19742 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND), |
| 7216 | /* 19746 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32, |
| 7217 | /* 19750 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32, |
| 7218 | /* 19754 */ GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7219 | /* 19759 */ GIM_CheckConstantInt, /*MI*/4, /*Op*/2, GIMT_Encode8(4294901760), |
| 7220 | /* 19770 */ GIM_CheckIsSafeToFold, /*NumInsns*/4, |
| 7221 | /* 19772 */ // (or:{ *:[i32] } (and:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh), 65535:{ *:[i32] }), (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 4294901760:{ *:[i32] })) => (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh) |
| 7222 | /* 19772 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHTB), |
| 7223 | /* 19775 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 7224 | /* 19777 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // src1 |
| 7225 | /* 19781 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2 |
| 7226 | /* 19785 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh |
| 7227 | /* 19788 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7228 | /* 19791 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7229 | /* 19797 */ GIR_RootConstrainSelectedInstOperands, |
| 7230 | /* 19798 */ // GIR_Coverage, 5702, |
| 7231 | /* 19798 */ GIR_EraseRootFromParent_Done, |
| 7232 | /* 19799 */ // Label 423: @19799 |
| 7233 | /* 19799 */ GIM_Try, /*On fail goto*//*Label 424*/ GIMT_Encode4(19932), // Rule ID 5452 // |
| 7234 | /* 19804 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 7235 | /* 19807 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 7236 | /* 19811 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 7237 | /* 19815 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 7238 | /* 19819 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 7239 | /* 19823 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 7240 | /* 19827 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 7241 | /* 19831 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SHL), |
| 7242 | /* 19835 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 7243 | /* 19839 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 7244 | /* 19843 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 7245 | /* 19848 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 7246 | /* 19852 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 7247 | /* 19856 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_pkh_lsl_amt), |
| 7248 | /* 19860 */ // MIs[3] Operand 1 |
| 7249 | /* 19860 */ // No operand predicates |
| 7250 | /* 19860 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760), |
| 7251 | /* 19871 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] |
| 7252 | /* 19875 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND), |
| 7253 | /* 19879 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32, |
| 7254 | /* 19883 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32, |
| 7255 | /* 19887 */ GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 7256 | /* 19892 */ GIM_CheckConstantInt, /*MI*/4, /*Op*/2, GIMT_Encode8(65535), |
| 7257 | /* 19903 */ GIM_CheckIsSafeToFold, /*NumInsns*/4, |
| 7258 | /* 19905 */ // (or:{ *:[i32] } (and:{ *:[i32] } (shl:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_lsl_amt>>:$sh), 4294901760:{ *:[i32] }), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 65535:{ *:[i32] })) => (PKHBT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh) |
| 7259 | /* 19905 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHBT), |
| 7260 | /* 19908 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 7261 | /* 19910 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Rn |
| 7262 | /* 19914 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 7263 | /* 19918 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh |
| 7264 | /* 19921 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7265 | /* 19924 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7266 | /* 19930 */ GIR_RootConstrainSelectedInstOperands, |
| 7267 | /* 19931 */ // GIR_Coverage, 5452, |
| 7268 | /* 19931 */ GIR_EraseRootFromParent_Done, |
| 7269 | /* 19932 */ // Label 424: @19932 |
| 7270 | /* 19932 */ GIM_Try, /*On fail goto*//*Label 425*/ GIMT_Encode4(20065), // Rule ID 5489 // |
| 7271 | /* 19937 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 7272 | /* 19940 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7273 | /* 19944 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 7274 | /* 19948 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 7275 | /* 19952 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 7276 | /* 19956 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 7277 | /* 19960 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 7278 | /* 19964 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SHL), |
| 7279 | /* 19968 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 7280 | /* 19972 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 7281 | /* 19976 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7282 | /* 19981 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 7283 | /* 19985 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 7284 | /* 19989 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_pkh_lsl_amt), |
| 7285 | /* 19993 */ // MIs[3] Operand 1 |
| 7286 | /* 19993 */ // No operand predicates |
| 7287 | /* 19993 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760), |
| 7288 | /* 20004 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] |
| 7289 | /* 20008 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND), |
| 7290 | /* 20012 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32, |
| 7291 | /* 20016 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32, |
| 7292 | /* 20020 */ GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7293 | /* 20025 */ GIM_CheckConstantInt, /*MI*/4, /*Op*/2, GIMT_Encode8(65535), |
| 7294 | /* 20036 */ GIM_CheckIsSafeToFold, /*NumInsns*/4, |
| 7295 | /* 20038 */ // (or:{ *:[i32] } (and:{ *:[i32] } (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_lsl_amt>>:$sh), 4294901760:{ *:[i32] }), (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 65535:{ *:[i32] })) => (t2PKHBT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh) |
| 7296 | /* 20038 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHBT), |
| 7297 | /* 20041 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 7298 | /* 20043 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Rn |
| 7299 | /* 20047 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 7300 | /* 20051 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh |
| 7301 | /* 20054 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7302 | /* 20057 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7303 | /* 20063 */ GIR_RootConstrainSelectedInstOperands, |
| 7304 | /* 20064 */ // GIR_Coverage, 5489, |
| 7305 | /* 20064 */ GIR_EraseRootFromParent_Done, |
| 7306 | /* 20065 */ // Label 425: @20065 |
| 7307 | /* 20065 */ GIM_Try, /*On fail goto*//*Label 426*/ GIMT_Encode4(20198), // Rule ID 203 // |
| 7308 | /* 20070 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 7309 | /* 20073 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 7310 | /* 20077 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 7311 | /* 20081 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 7312 | /* 20085 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 7313 | /* 20089 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 7314 | /* 20093 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 7315 | /* 20098 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760), |
| 7316 | /* 20109 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 7317 | /* 20113 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), |
| 7318 | /* 20117 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 7319 | /* 20121 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 7320 | /* 20125 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 7321 | /* 20129 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 7322 | /* 20133 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 7323 | /* 20137 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 7324 | /* 20141 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 7325 | /* 20146 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] |
| 7326 | /* 20150 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 7327 | /* 20154 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_pkh_asr_amt), |
| 7328 | /* 20158 */ // MIs[4] Operand 1 |
| 7329 | /* 20158 */ // No operand predicates |
| 7330 | /* 20158 */ GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(65535), |
| 7331 | /* 20169 */ GIM_CheckIsSafeToFold, /*NumInsns*/4, |
| 7332 | /* 20171 */ // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 4294901760:{ *:[i32] }), (and:{ *:[i32] } (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_asr_amt>>:$sh), 65535:{ *:[i32] })) => (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh) |
| 7333 | /* 20171 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHTB), |
| 7334 | /* 20174 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 7335 | /* 20176 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 7336 | /* 20180 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm |
| 7337 | /* 20184 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // sh |
| 7338 | /* 20187 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7339 | /* 20190 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7340 | /* 20196 */ GIR_RootConstrainSelectedInstOperands, |
| 7341 | /* 20197 */ // GIR_Coverage, 203, |
| 7342 | /* 20197 */ GIR_EraseRootFromParent_Done, |
| 7343 | /* 20198 */ // Label 426: @20198 |
| 7344 | /* 20198 */ GIM_Try, /*On fail goto*//*Label 427*/ GIMT_Encode4(20331), // Rule ID 540 // |
| 7345 | /* 20203 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 7346 | /* 20206 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7347 | /* 20210 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 7348 | /* 20214 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 7349 | /* 20218 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 7350 | /* 20222 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 7351 | /* 20226 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7352 | /* 20231 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760), |
| 7353 | /* 20242 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 7354 | /* 20246 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), |
| 7355 | /* 20250 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 7356 | /* 20254 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 7357 | /* 20258 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 7358 | /* 20262 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 7359 | /* 20266 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 7360 | /* 20270 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 7361 | /* 20274 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7362 | /* 20279 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] |
| 7363 | /* 20283 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 7364 | /* 20287 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_pkh_asr_amt), |
| 7365 | /* 20291 */ // MIs[4] Operand 1 |
| 7366 | /* 20291 */ // No operand predicates |
| 7367 | /* 20291 */ GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(65535), |
| 7368 | /* 20302 */ GIM_CheckIsSafeToFold, /*NumInsns*/4, |
| 7369 | /* 20304 */ // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 4294901760:{ *:[i32] }), (and:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_asr_amt>>:$sh), 65535:{ *:[i32] })) => (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh) |
| 7370 | /* 20304 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHTB), |
| 7371 | /* 20307 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 7372 | /* 20309 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 7373 | /* 20313 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm |
| 7374 | /* 20317 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // sh |
| 7375 | /* 20320 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7376 | /* 20323 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7377 | /* 20329 */ GIR_RootConstrainSelectedInstOperands, |
| 7378 | /* 20330 */ // GIR_Coverage, 540, |
| 7379 | /* 20330 */ GIR_EraseRootFromParent_Done, |
| 7380 | /* 20331 */ // Label 427: @20331 |
| 7381 | /* 20331 */ GIM_Try, /*On fail goto*//*Label 428*/ GIMT_Encode4(20464), // Rule ID 1919 // |
| 7382 | /* 20336 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 7383 | /* 20339 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 7384 | /* 20343 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 7385 | /* 20347 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 7386 | /* 20351 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 7387 | /* 20355 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 7388 | /* 20359 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 7389 | /* 20364 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760), |
| 7390 | /* 20375 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 7391 | /* 20379 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), |
| 7392 | /* 20383 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 7393 | /* 20387 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 7394 | /* 20391 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 7395 | /* 20395 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 7396 | /* 20399 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 7397 | /* 20403 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 7398 | /* 20407 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 7399 | /* 20412 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] |
| 7400 | /* 20416 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 7401 | /* 20420 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm1_15), |
| 7402 | /* 20424 */ // MIs[4] Operand 1 |
| 7403 | /* 20424 */ // No operand predicates |
| 7404 | /* 20424 */ GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(65535), |
| 7405 | /* 20435 */ GIM_CheckIsSafeToFold, /*NumInsns*/4, |
| 7406 | /* 20437 */ // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }), (and:{ *:[i32] } (srl:{ *:[i32] } GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh), 65535:{ *:[i32] })) => (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh) |
| 7407 | /* 20437 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHTB), |
| 7408 | /* 20440 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 7409 | /* 20442 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 7410 | /* 20446 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src2 |
| 7411 | /* 20450 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // sh |
| 7412 | /* 20453 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7413 | /* 20456 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7414 | /* 20462 */ GIR_RootConstrainSelectedInstOperands, |
| 7415 | /* 20463 */ // GIR_Coverage, 1919, |
| 7416 | /* 20463 */ GIR_EraseRootFromParent_Done, |
| 7417 | /* 20464 */ // Label 428: @20464 |
| 7418 | /* 20464 */ GIM_Try, /*On fail goto*//*Label 429*/ GIMT_Encode4(20597), // Rule ID 2201 // |
| 7419 | /* 20469 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 7420 | /* 20472 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7421 | /* 20476 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 7422 | /* 20480 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 7423 | /* 20484 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 7424 | /* 20488 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 7425 | /* 20492 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7426 | /* 20497 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760), |
| 7427 | /* 20508 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 7428 | /* 20512 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), |
| 7429 | /* 20516 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 7430 | /* 20520 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 7431 | /* 20524 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 7432 | /* 20528 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 7433 | /* 20532 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 7434 | /* 20536 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 7435 | /* 20540 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7436 | /* 20545 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] |
| 7437 | /* 20549 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 7438 | /* 20553 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm1_15), |
| 7439 | /* 20557 */ // MIs[4] Operand 1 |
| 7440 | /* 20557 */ // No operand predicates |
| 7441 | /* 20557 */ GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(65535), |
| 7442 | /* 20568 */ GIM_CheckIsSafeToFold, /*NumInsns*/4, |
| 7443 | /* 20570 */ // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }), (and:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh), 65535:{ *:[i32] })) => (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh) |
| 7444 | /* 20570 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHTB), |
| 7445 | /* 20573 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 7446 | /* 20575 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 7447 | /* 20579 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src2 |
| 7448 | /* 20583 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // sh |
| 7449 | /* 20586 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7450 | /* 20589 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7451 | /* 20595 */ GIR_RootConstrainSelectedInstOperands, |
| 7452 | /* 20596 */ // GIR_Coverage, 2201, |
| 7453 | /* 20596 */ GIR_EraseRootFromParent_Done, |
| 7454 | /* 20597 */ // Label 429: @20597 |
| 7455 | /* 20597 */ GIM_Try, /*On fail goto*//*Label 430*/ GIMT_Encode4(20730), // Rule ID 202 // |
| 7456 | /* 20602 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 7457 | /* 20605 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 7458 | /* 20609 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 7459 | /* 20613 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 7460 | /* 20617 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 7461 | /* 20621 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 7462 | /* 20625 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 7463 | /* 20630 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535), |
| 7464 | /* 20641 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 7465 | /* 20645 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), |
| 7466 | /* 20649 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 7467 | /* 20653 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 7468 | /* 20657 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 7469 | /* 20661 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL), |
| 7470 | /* 20665 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 7471 | /* 20669 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 7472 | /* 20673 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 7473 | /* 20678 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] |
| 7474 | /* 20682 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 7475 | /* 20686 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_pkh_lsl_amt), |
| 7476 | /* 20690 */ // MIs[4] Operand 1 |
| 7477 | /* 20690 */ // No operand predicates |
| 7478 | /* 20690 */ GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(4294901760), |
| 7479 | /* 20701 */ GIM_CheckIsSafeToFold, /*NumInsns*/4, |
| 7480 | /* 20703 */ // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 65535:{ *:[i32] }), (and:{ *:[i32] } (shl:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_lsl_amt>>:$sh), 4294901760:{ *:[i32] })) => (PKHBT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh) |
| 7481 | /* 20703 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHBT), |
| 7482 | /* 20706 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 7483 | /* 20708 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 7484 | /* 20712 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm |
| 7485 | /* 20716 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // sh |
| 7486 | /* 20719 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7487 | /* 20722 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7488 | /* 20728 */ GIR_RootConstrainSelectedInstOperands, |
| 7489 | /* 20729 */ // GIR_Coverage, 202, |
| 7490 | /* 20729 */ GIR_EraseRootFromParent_Done, |
| 7491 | /* 20730 */ // Label 430: @20730 |
| 7492 | /* 20730 */ GIM_Try, /*On fail goto*//*Label 431*/ GIMT_Encode4(20863), // Rule ID 539 // |
| 7493 | /* 20735 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 7494 | /* 20738 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7495 | /* 20742 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 7496 | /* 20746 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 7497 | /* 20750 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 7498 | /* 20754 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 7499 | /* 20758 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7500 | /* 20763 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535), |
| 7501 | /* 20774 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 7502 | /* 20778 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), |
| 7503 | /* 20782 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 7504 | /* 20786 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 7505 | /* 20790 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 7506 | /* 20794 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL), |
| 7507 | /* 20798 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 7508 | /* 20802 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 7509 | /* 20806 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7510 | /* 20811 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] |
| 7511 | /* 20815 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 7512 | /* 20819 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_pkh_lsl_amt), |
| 7513 | /* 20823 */ // MIs[4] Operand 1 |
| 7514 | /* 20823 */ // No operand predicates |
| 7515 | /* 20823 */ GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(4294901760), |
| 7516 | /* 20834 */ GIM_CheckIsSafeToFold, /*NumInsns*/4, |
| 7517 | /* 20836 */ // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 65535:{ *:[i32] }), (and:{ *:[i32] } (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_lsl_amt>>:$sh), 4294901760:{ *:[i32] })) => (t2PKHBT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh) |
| 7518 | /* 20836 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHBT), |
| 7519 | /* 20839 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 7520 | /* 20841 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 7521 | /* 20845 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm |
| 7522 | /* 20849 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // sh |
| 7523 | /* 20852 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7524 | /* 20855 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7525 | /* 20861 */ GIR_RootConstrainSelectedInstOperands, |
| 7526 | /* 20862 */ // GIR_Coverage, 539, |
| 7527 | /* 20862 */ GIR_EraseRootFromParent_Done, |
| 7528 | /* 20863 */ // Label 431: @20863 |
| 7529 | /* 20863 */ GIM_Try, /*On fail goto*//*Label 432*/ GIMT_Encode4(20968), // Rule ID 1915 // |
| 7530 | /* 20868 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 7531 | /* 20871 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 7532 | /* 20875 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 7533 | /* 20879 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 7534 | /* 20883 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 7535 | /* 20887 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 7536 | /* 20891 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 7537 | /* 20896 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535), |
| 7538 | /* 20907 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 7539 | /* 20911 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), |
| 7540 | /* 20915 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 7541 | /* 20919 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 7542 | /* 20923 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 7543 | /* 20928 */ GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(4294901760), |
| 7544 | /* 20939 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 7545 | /* 20941 */ // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 65535:{ *:[i32] }), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, 4294901760:{ *:[i32] })) => (PKHBT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, 0:{ *:[i32] }) |
| 7546 | /* 20941 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHBT), |
| 7547 | /* 20944 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 7548 | /* 20946 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 7549 | /* 20950 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 7550 | /* 20954 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 7551 | /* 20957 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7552 | /* 20960 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7553 | /* 20966 */ GIR_RootConstrainSelectedInstOperands, |
| 7554 | /* 20967 */ // GIR_Coverage, 1915, |
| 7555 | /* 20967 */ GIR_EraseRootFromParent_Done, |
| 7556 | /* 20968 */ // Label 432: @20968 |
| 7557 | /* 20968 */ GIM_Try, /*On fail goto*//*Label 433*/ GIMT_Encode4(21073), // Rule ID 2197 // |
| 7558 | /* 20973 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 7559 | /* 20976 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7560 | /* 20980 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 7561 | /* 20984 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 7562 | /* 20988 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 7563 | /* 20992 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 7564 | /* 20996 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7565 | /* 21001 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535), |
| 7566 | /* 21012 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 7567 | /* 21016 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), |
| 7568 | /* 21020 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 7569 | /* 21024 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 7570 | /* 21028 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7571 | /* 21033 */ GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(4294901760), |
| 7572 | /* 21044 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 7573 | /* 21046 */ // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 65535:{ *:[i32] }), (and:{ *:[i32] } rGPR:{ *:[i32] }:$src2, 4294901760:{ *:[i32] })) => (t2PKHBT:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, 0:{ *:[i32] }) |
| 7574 | /* 21046 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHBT), |
| 7575 | /* 21049 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 7576 | /* 21051 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 7577 | /* 21055 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2 |
| 7578 | /* 21059 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 7579 | /* 21062 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7580 | /* 21065 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7581 | /* 21071 */ GIR_RootConstrainSelectedInstOperands, |
| 7582 | /* 21072 */ // GIR_Coverage, 2197, |
| 7583 | /* 21072 */ GIR_EraseRootFromParent_Done, |
| 7584 | /* 21073 */ // Label 433: @21073 |
| 7585 | /* 21073 */ GIM_Try, /*On fail goto*//*Label 434*/ GIMT_Encode4(21178), // Rule ID 5656 // |
| 7586 | /* 21078 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 7587 | /* 21081 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 7588 | /* 21085 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 7589 | /* 21089 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 7590 | /* 21093 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 7591 | /* 21097 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 7592 | /* 21101 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 7593 | /* 21106 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760), |
| 7594 | /* 21117 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 7595 | /* 21121 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), |
| 7596 | /* 21125 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 7597 | /* 21129 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 7598 | /* 21133 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 7599 | /* 21138 */ GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(65535), |
| 7600 | /* 21149 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 7601 | /* 21151 */ // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, 4294901760:{ *:[i32] }), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 65535:{ *:[i32] })) => (PKHBT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, 0:{ *:[i32] }) |
| 7602 | /* 21151 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHBT), |
| 7603 | /* 21154 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 7604 | /* 21156 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn |
| 7605 | /* 21160 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 7606 | /* 21164 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 7607 | /* 21167 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7608 | /* 21170 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7609 | /* 21176 */ GIR_RootConstrainSelectedInstOperands, |
| 7610 | /* 21177 */ // GIR_Coverage, 5656, |
| 7611 | /* 21177 */ GIR_EraseRootFromParent_Done, |
| 7612 | /* 21178 */ // Label 434: @21178 |
| 7613 | /* 21178 */ GIM_Try, /*On fail goto*//*Label 435*/ GIMT_Encode4(21283), // Rule ID 5698 // |
| 7614 | /* 21183 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 7615 | /* 21186 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7616 | /* 21190 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 7617 | /* 21194 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 7618 | /* 21198 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 7619 | /* 21202 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 7620 | /* 21206 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7621 | /* 21211 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760), |
| 7622 | /* 21222 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 7623 | /* 21226 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), |
| 7624 | /* 21230 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 7625 | /* 21234 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 7626 | /* 21238 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7627 | /* 21243 */ GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(65535), |
| 7628 | /* 21254 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 7629 | /* 21256 */ // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$src2, 4294901760:{ *:[i32] }), (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 65535:{ *:[i32] })) => (t2PKHBT:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, 0:{ *:[i32] }) |
| 7630 | /* 21256 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHBT), |
| 7631 | /* 21259 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 7632 | /* 21261 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1 |
| 7633 | /* 21265 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2 |
| 7634 | /* 21269 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 7635 | /* 21272 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7636 | /* 21275 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7637 | /* 21281 */ GIR_RootConstrainSelectedInstOperands, |
| 7638 | /* 21282 */ // GIR_Coverage, 5698, |
| 7639 | /* 21282 */ GIR_EraseRootFromParent_Done, |
| 7640 | /* 21283 */ // Label 435: @21283 |
| 7641 | /* 21283 */ GIM_Try, /*On fail goto*//*Label 436*/ GIMT_Encode4(21389), // Rule ID 1918 // |
| 7642 | /* 21288 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 7643 | /* 21291 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 7644 | /* 21295 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 7645 | /* 21299 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 7646 | /* 21303 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 7647 | /* 21307 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 7648 | /* 21311 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 7649 | /* 21316 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760), |
| 7650 | /* 21327 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 7651 | /* 21331 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 7652 | /* 21335 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 7653 | /* 21339 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 7654 | /* 21343 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 7655 | /* 21348 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 7656 | /* 21352 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 7657 | /* 21356 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16_31), |
| 7658 | /* 21360 */ // MIs[3] Operand 1 |
| 7659 | /* 21360 */ // No operand predicates |
| 7660 | /* 21360 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 7661 | /* 21362 */ // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }), (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)) => (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh) |
| 7662 | /* 21362 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHTB), |
| 7663 | /* 21365 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 7664 | /* 21367 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 7665 | /* 21371 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2 |
| 7666 | /* 21375 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh |
| 7667 | /* 21378 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7668 | /* 21381 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7669 | /* 21387 */ GIR_RootConstrainSelectedInstOperands, |
| 7670 | /* 21388 */ // GIR_Coverage, 1918, |
| 7671 | /* 21388 */ GIR_EraseRootFromParent_Done, |
| 7672 | /* 21389 */ // Label 436: @21389 |
| 7673 | /* 21389 */ GIM_Try, /*On fail goto*//*Label 437*/ GIMT_Encode4(21495), // Rule ID 2200 // |
| 7674 | /* 21394 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 7675 | /* 21397 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7676 | /* 21401 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 7677 | /* 21405 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 7678 | /* 21409 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 7679 | /* 21413 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 7680 | /* 21417 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7681 | /* 21422 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760), |
| 7682 | /* 21433 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 7683 | /* 21437 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 7684 | /* 21441 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 7685 | /* 21445 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 7686 | /* 21449 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7687 | /* 21454 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 7688 | /* 21458 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 7689 | /* 21462 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16_31), |
| 7690 | /* 21466 */ // MIs[3] Operand 1 |
| 7691 | /* 21466 */ // No operand predicates |
| 7692 | /* 21466 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 7693 | /* 21468 */ // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }), (sra:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)) => (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh) |
| 7694 | /* 21468 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHTB), |
| 7695 | /* 21471 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 7696 | /* 21473 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 7697 | /* 21477 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2 |
| 7698 | /* 21481 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh |
| 7699 | /* 21484 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7700 | /* 21487 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7701 | /* 21493 */ GIR_RootConstrainSelectedInstOperands, |
| 7702 | /* 21494 */ // GIR_Coverage, 2200, |
| 7703 | /* 21494 */ GIR_EraseRootFromParent_Done, |
| 7704 | /* 21495 */ // Label 437: @21495 |
| 7705 | /* 21495 */ GIM_Try, /*On fail goto*//*Label 438*/ GIMT_Encode4(21601), // Rule ID 1917 // |
| 7706 | /* 21500 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 7707 | /* 21503 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 7708 | /* 21507 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 7709 | /* 21511 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 7710 | /* 21515 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 7711 | /* 21519 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 7712 | /* 21523 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 7713 | /* 21528 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760), |
| 7714 | /* 21539 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 7715 | /* 21543 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 7716 | /* 21547 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 7717 | /* 21551 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 7718 | /* 21555 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 7719 | /* 21560 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 7720 | /* 21564 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 7721 | /* 21568 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16), |
| 7722 | /* 21572 */ // MIs[3] Operand 1 |
| 7723 | /* 21572 */ // No operand predicates |
| 7724 | /* 21572 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 7725 | /* 21574 */ // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }), (srl:{ *:[i32] } GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh)) => (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh) |
| 7726 | /* 21574 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHTB), |
| 7727 | /* 21577 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 7728 | /* 21579 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 7729 | /* 21583 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2 |
| 7730 | /* 21587 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh |
| 7731 | /* 21590 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7732 | /* 21593 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7733 | /* 21599 */ GIR_RootConstrainSelectedInstOperands, |
| 7734 | /* 21600 */ // GIR_Coverage, 1917, |
| 7735 | /* 21600 */ GIR_EraseRootFromParent_Done, |
| 7736 | /* 21601 */ // Label 438: @21601 |
| 7737 | /* 21601 */ GIM_Try, /*On fail goto*//*Label 439*/ GIMT_Encode4(21707), // Rule ID 2199 // |
| 7738 | /* 21606 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 7739 | /* 21609 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7740 | /* 21613 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 7741 | /* 21617 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 7742 | /* 21621 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 7743 | /* 21625 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 7744 | /* 21629 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7745 | /* 21634 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760), |
| 7746 | /* 21645 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 7747 | /* 21649 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 7748 | /* 21653 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 7749 | /* 21657 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 7750 | /* 21661 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7751 | /* 21666 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 7752 | /* 21670 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 7753 | /* 21674 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16), |
| 7754 | /* 21678 */ // MIs[3] Operand 1 |
| 7755 | /* 21678 */ // No operand predicates |
| 7756 | /* 21678 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 7757 | /* 21680 */ // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }), (srl:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh)) => (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh) |
| 7758 | /* 21680 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHTB), |
| 7759 | /* 21683 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 7760 | /* 21685 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 7761 | /* 21689 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2 |
| 7762 | /* 21693 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh |
| 7763 | /* 21696 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7764 | /* 21699 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7765 | /* 21705 */ GIR_RootConstrainSelectedInstOperands, |
| 7766 | /* 21706 */ // GIR_Coverage, 2199, |
| 7767 | /* 21706 */ GIR_EraseRootFromParent_Done, |
| 7768 | /* 21707 */ // Label 439: @21707 |
| 7769 | /* 21707 */ GIM_Try, /*On fail goto*//*Label 440*/ GIMT_Encode4(21813), // Rule ID 1916 // |
| 7770 | /* 21712 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 7771 | /* 21715 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 7772 | /* 21719 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 7773 | /* 21723 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 7774 | /* 21727 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 7775 | /* 21731 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 7776 | /* 21735 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 7777 | /* 21740 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535), |
| 7778 | /* 21751 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 7779 | /* 21755 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SHL), |
| 7780 | /* 21759 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 7781 | /* 21763 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 7782 | /* 21767 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 7783 | /* 21772 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 7784 | /* 21776 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 7785 | /* 21780 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16_31), |
| 7786 | /* 21784 */ // MIs[3] Operand 1 |
| 7787 | /* 21784 */ // No operand predicates |
| 7788 | /* 21784 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 7789 | /* 21786 */ // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 65535:{ *:[i32] }), (shl:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)) => (PKHBT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh) |
| 7790 | /* 21786 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHBT), |
| 7791 | /* 21789 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 7792 | /* 21791 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 7793 | /* 21795 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 7794 | /* 21799 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh |
| 7795 | /* 21802 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7796 | /* 21805 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7797 | /* 21811 */ GIR_RootConstrainSelectedInstOperands, |
| 7798 | /* 21812 */ // GIR_Coverage, 1916, |
| 7799 | /* 21812 */ GIR_EraseRootFromParent_Done, |
| 7800 | /* 21813 */ // Label 440: @21813 |
| 7801 | /* 21813 */ GIM_Try, /*On fail goto*//*Label 441*/ GIMT_Encode4(21919), // Rule ID 2198 // |
| 7802 | /* 21818 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 7803 | /* 21821 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7804 | /* 21825 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 7805 | /* 21829 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 7806 | /* 21833 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 7807 | /* 21837 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 7808 | /* 21841 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7809 | /* 21846 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535), |
| 7810 | /* 21857 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 7811 | /* 21861 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SHL), |
| 7812 | /* 21865 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 7813 | /* 21869 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 7814 | /* 21873 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7815 | /* 21878 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 7816 | /* 21882 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 7817 | /* 21886 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16_31), |
| 7818 | /* 21890 */ // MIs[3] Operand 1 |
| 7819 | /* 21890 */ // No operand predicates |
| 7820 | /* 21890 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 7821 | /* 21892 */ // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 65535:{ *:[i32] }), (shl:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)) => (t2PKHBT:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh) |
| 7822 | /* 21892 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHBT), |
| 7823 | /* 21895 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 7824 | /* 21897 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 7825 | /* 21901 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2 |
| 7826 | /* 21905 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh |
| 7827 | /* 21908 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7828 | /* 21911 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7829 | /* 21917 */ GIR_RootConstrainSelectedInstOperands, |
| 7830 | /* 21918 */ // GIR_Coverage, 2198, |
| 7831 | /* 21918 */ GIR_EraseRootFromParent_Done, |
| 7832 | /* 21919 */ // Label 441: @21919 |
| 7833 | /* 21919 */ GIM_Try, /*On fail goto*//*Label 442*/ GIMT_Encode4(22025), // Rule ID 5659 // |
| 7834 | /* 21924 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 7835 | /* 21927 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 7836 | /* 21931 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 7837 | /* 21935 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 7838 | /* 21939 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 7839 | /* 21943 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 7840 | /* 21947 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 7841 | /* 21952 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 7842 | /* 21956 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 7843 | /* 21960 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16_31), |
| 7844 | /* 21964 */ // MIs[2] Operand 1 |
| 7845 | /* 21964 */ // No operand predicates |
| 7846 | /* 21964 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 7847 | /* 21968 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND), |
| 7848 | /* 21972 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 7849 | /* 21976 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 7850 | /* 21980 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 7851 | /* 21985 */ GIM_CheckConstantInt, /*MI*/3, /*Op*/2, GIMT_Encode8(4294901760), |
| 7852 | /* 21996 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 7853 | /* 21998 */ // (or:{ *:[i32] } (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, 4294901760:{ *:[i32] })) => (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh) |
| 7854 | /* 21998 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHTB), |
| 7855 | /* 22001 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 7856 | /* 22003 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src1 |
| 7857 | /* 22007 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2 |
| 7858 | /* 22011 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sh |
| 7859 | /* 22014 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7860 | /* 22017 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7861 | /* 22023 */ GIR_RootConstrainSelectedInstOperands, |
| 7862 | /* 22024 */ // GIR_Coverage, 5659, |
| 7863 | /* 22024 */ GIR_EraseRootFromParent_Done, |
| 7864 | /* 22025 */ // Label 442: @22025 |
| 7865 | /* 22025 */ GIM_Try, /*On fail goto*//*Label 443*/ GIMT_Encode4(22131), // Rule ID 5701 // |
| 7866 | /* 22030 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 7867 | /* 22033 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7868 | /* 22037 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 7869 | /* 22041 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 7870 | /* 22045 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 7871 | /* 22049 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 7872 | /* 22053 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7873 | /* 22058 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 7874 | /* 22062 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 7875 | /* 22066 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16_31), |
| 7876 | /* 22070 */ // MIs[2] Operand 1 |
| 7877 | /* 22070 */ // No operand predicates |
| 7878 | /* 22070 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 7879 | /* 22074 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND), |
| 7880 | /* 22078 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 7881 | /* 22082 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 7882 | /* 22086 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7883 | /* 22091 */ GIM_CheckConstantInt, /*MI*/3, /*Op*/2, GIMT_Encode8(4294901760), |
| 7884 | /* 22102 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 7885 | /* 22104 */ // (or:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh), (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 4294901760:{ *:[i32] })) => (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh) |
| 7886 | /* 22104 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHTB), |
| 7887 | /* 22107 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 7888 | /* 22109 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src1 |
| 7889 | /* 22113 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2 |
| 7890 | /* 22117 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sh |
| 7891 | /* 22120 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7892 | /* 22123 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7893 | /* 22129 */ GIR_RootConstrainSelectedInstOperands, |
| 7894 | /* 22130 */ // GIR_Coverage, 5701, |
| 7895 | /* 22130 */ GIR_EraseRootFromParent_Done, |
| 7896 | /* 22131 */ // Label 443: @22131 |
| 7897 | /* 22131 */ GIM_Try, /*On fail goto*//*Label 444*/ GIMT_Encode4(22237), // Rule ID 5658 // |
| 7898 | /* 22136 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 7899 | /* 22139 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 7900 | /* 22143 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 7901 | /* 22147 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 7902 | /* 22151 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 7903 | /* 22155 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 7904 | /* 22159 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 7905 | /* 22164 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 7906 | /* 22168 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 7907 | /* 22172 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16), |
| 7908 | /* 22176 */ // MIs[2] Operand 1 |
| 7909 | /* 22176 */ // No operand predicates |
| 7910 | /* 22176 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 7911 | /* 22180 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND), |
| 7912 | /* 22184 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 7913 | /* 22188 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 7914 | /* 22192 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 7915 | /* 22197 */ GIM_CheckConstantInt, /*MI*/3, /*Op*/2, GIMT_Encode8(4294901760), |
| 7916 | /* 22208 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 7917 | /* 22210 */ // (or:{ *:[i32] } (srl:{ *:[i32] } GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, 4294901760:{ *:[i32] })) => (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh) |
| 7918 | /* 22210 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHTB), |
| 7919 | /* 22213 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 7920 | /* 22215 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src1 |
| 7921 | /* 22219 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2 |
| 7922 | /* 22223 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sh |
| 7923 | /* 22226 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7924 | /* 22229 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7925 | /* 22235 */ GIR_RootConstrainSelectedInstOperands, |
| 7926 | /* 22236 */ // GIR_Coverage, 5658, |
| 7927 | /* 22236 */ GIR_EraseRootFromParent_Done, |
| 7928 | /* 22237 */ // Label 444: @22237 |
| 7929 | /* 22237 */ GIM_Try, /*On fail goto*//*Label 445*/ GIMT_Encode4(22343), // Rule ID 5700 // |
| 7930 | /* 22242 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 7931 | /* 22245 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7932 | /* 22249 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 7933 | /* 22253 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 7934 | /* 22257 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 7935 | /* 22261 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 7936 | /* 22265 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7937 | /* 22270 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 7938 | /* 22274 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 7939 | /* 22278 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16), |
| 7940 | /* 22282 */ // MIs[2] Operand 1 |
| 7941 | /* 22282 */ // No operand predicates |
| 7942 | /* 22282 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 7943 | /* 22286 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND), |
| 7944 | /* 22290 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 7945 | /* 22294 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 7946 | /* 22298 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7947 | /* 22303 */ GIM_CheckConstantInt, /*MI*/3, /*Op*/2, GIMT_Encode8(4294901760), |
| 7948 | /* 22314 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 7949 | /* 22316 */ // (or:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh), (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 4294901760:{ *:[i32] })) => (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh) |
| 7950 | /* 22316 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHTB), |
| 7951 | /* 22319 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 7952 | /* 22321 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src1 |
| 7953 | /* 22325 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2 |
| 7954 | /* 22329 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sh |
| 7955 | /* 22332 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7956 | /* 22335 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7957 | /* 22341 */ GIR_RootConstrainSelectedInstOperands, |
| 7958 | /* 22342 */ // GIR_Coverage, 5700, |
| 7959 | /* 22342 */ GIR_EraseRootFromParent_Done, |
| 7960 | /* 22343 */ // Label 445: @22343 |
| 7961 | /* 22343 */ GIM_Try, /*On fail goto*//*Label 446*/ GIMT_Encode4(22449), // Rule ID 5657 // |
| 7962 | /* 22348 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 7963 | /* 22351 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 7964 | /* 22355 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 7965 | /* 22359 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), |
| 7966 | /* 22363 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 7967 | /* 22367 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 7968 | /* 22371 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 7969 | /* 22376 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 7970 | /* 22380 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 7971 | /* 22384 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16_31), |
| 7972 | /* 22388 */ // MIs[2] Operand 1 |
| 7973 | /* 22388 */ // No operand predicates |
| 7974 | /* 22388 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 7975 | /* 22392 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND), |
| 7976 | /* 22396 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 7977 | /* 22400 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 7978 | /* 22404 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 7979 | /* 22409 */ GIM_CheckConstantInt, /*MI*/3, /*Op*/2, GIMT_Encode8(65535), |
| 7980 | /* 22420 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 7981 | /* 22422 */ // (or:{ *:[i32] } (shl:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 65535:{ *:[i32] })) => (PKHBT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh) |
| 7982 | /* 22422 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHBT), |
| 7983 | /* 22425 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 7984 | /* 22427 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn |
| 7985 | /* 22431 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 7986 | /* 22435 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sh |
| 7987 | /* 22438 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7988 | /* 22441 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7989 | /* 22447 */ GIR_RootConstrainSelectedInstOperands, |
| 7990 | /* 22448 */ // GIR_Coverage, 5657, |
| 7991 | /* 22448 */ GIR_EraseRootFromParent_Done, |
| 7992 | /* 22449 */ // Label 446: @22449 |
| 7993 | /* 22449 */ GIM_Try, /*On fail goto*//*Label 447*/ GIMT_Encode4(22555), // Rule ID 5699 // |
| 7994 | /* 22454 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 7995 | /* 22457 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7996 | /* 22461 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 7997 | /* 22465 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), |
| 7998 | /* 22469 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 7999 | /* 22473 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 8000 | /* 22477 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8001 | /* 22482 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 8002 | /* 22486 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 8003 | /* 22490 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16_31), |
| 8004 | /* 22494 */ // MIs[2] Operand 1 |
| 8005 | /* 22494 */ // No operand predicates |
| 8006 | /* 22494 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 8007 | /* 22498 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND), |
| 8008 | /* 22502 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 8009 | /* 22506 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 8010 | /* 22510 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8011 | /* 22515 */ GIM_CheckConstantInt, /*MI*/3, /*Op*/2, GIMT_Encode8(65535), |
| 8012 | /* 22526 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 8013 | /* 22528 */ // (or:{ *:[i32] } (shl:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh), (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 65535:{ *:[i32] })) => (t2PKHBT:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh) |
| 8014 | /* 22528 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHBT), |
| 8015 | /* 22531 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 8016 | /* 22533 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src1 |
| 8017 | /* 22537 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2 |
| 8018 | /* 22541 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sh |
| 8019 | /* 22544 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8020 | /* 22547 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8021 | /* 22553 */ GIR_RootConstrainSelectedInstOperands, |
| 8022 | /* 22554 */ // GIR_Coverage, 5699, |
| 8023 | /* 22554 */ GIR_EraseRootFromParent_Done, |
| 8024 | /* 22555 */ // Label 447: @22555 |
| 8025 | /* 22555 */ GIM_Try, /*On fail goto*//*Label 448*/ GIMT_Encode4(22632), // Rule ID 5477 // |
| 8026 | /* 22560 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 8027 | /* 22563 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8028 | /* 22567 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 8029 | /* 22571 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 8030 | /* 22575 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 8031 | /* 22579 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 8032 | /* 22583 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, uint8_t(-1), |
| 8033 | /* 22587 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 8034 | /* 22591 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 8035 | /* 22595 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm), |
| 8036 | /* 22599 */ // MIs[2] Operand 1 |
| 8037 | /* 22599 */ // No operand predicates |
| 8038 | /* 22599 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8039 | /* 22603 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 8040 | /* 22605 */ // (or:{ *:[i32] } (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm), rGPR:{ *:[i32] }:$Rn) => (t2ORNri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 8041 | /* 22605 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ORNri), |
| 8042 | /* 22608 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 8043 | /* 22610 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 8044 | /* 22612 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 8045 | /* 22615 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8046 | /* 22618 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8047 | /* 22624 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8048 | /* 22630 */ GIR_RootConstrainSelectedInstOperands, |
| 8049 | /* 22631 */ // GIR_Coverage, 5477, |
| 8050 | /* 22631 */ GIR_EraseRootFromParent_Done, |
| 8051 | /* 22632 */ // Label 448: @22632 |
| 8052 | /* 22632 */ GIM_Try, /*On fail goto*//*Label 449*/ GIMT_Encode4(22709), // Rule ID 5476 // |
| 8053 | /* 22637 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 8054 | /* 22640 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8055 | /* 22644 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 8056 | /* 22648 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 8057 | /* 22652 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 8058 | /* 22656 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 8059 | /* 22660 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 8060 | /* 22664 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 8061 | /* 22668 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm), |
| 8062 | /* 22672 */ // MIs[2] Operand 1 |
| 8063 | /* 22672 */ // No operand predicates |
| 8064 | /* 22672 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), |
| 8065 | /* 22676 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8066 | /* 22680 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 8067 | /* 22682 */ // (or:{ *:[i32] } (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm, -1:{ *:[i32] }), rGPR:{ *:[i32] }:$Rn) => (t2ORNri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 8068 | /* 22682 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ORNri), |
| 8069 | /* 22685 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 8070 | /* 22687 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 8071 | /* 22689 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 8072 | /* 22692 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8073 | /* 22695 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8074 | /* 22701 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8075 | /* 22707 */ GIR_RootConstrainSelectedInstOperands, |
| 8076 | /* 22708 */ // GIR_Coverage, 5476, |
| 8077 | /* 22708 */ GIR_EraseRootFromParent_Done, |
| 8078 | /* 22709 */ // Label 449: @22709 |
| 8079 | /* 22709 */ GIM_Try, /*On fail goto*//*Label 450*/ GIMT_Encode4(22786), // Rule ID 5475 // |
| 8080 | /* 22714 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 8081 | /* 22717 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8082 | /* 22721 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8083 | /* 22725 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 8084 | /* 22729 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 8085 | /* 22733 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 8086 | /* 22737 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 8087 | /* 22741 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, uint8_t(-1), |
| 8088 | /* 22745 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 8089 | /* 22749 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 8090 | /* 22753 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm), |
| 8091 | /* 22757 */ // MIs[2] Operand 1 |
| 8092 | /* 22757 */ // No operand predicates |
| 8093 | /* 22757 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 8094 | /* 22759 */ // (or:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm)) => (t2ORNri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 8095 | /* 22759 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ORNri), |
| 8096 | /* 22762 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 8097 | /* 22764 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 8098 | /* 22766 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 8099 | /* 22769 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8100 | /* 22772 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8101 | /* 22778 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8102 | /* 22784 */ GIR_RootConstrainSelectedInstOperands, |
| 8103 | /* 22785 */ // GIR_Coverage, 5475, |
| 8104 | /* 22785 */ GIR_EraseRootFromParent_Done, |
| 8105 | /* 22786 */ // Label 450: @22786 |
| 8106 | /* 22786 */ GIM_Try, /*On fail goto*//*Label 451*/ GIMT_Encode4(22863), // Rule ID 496 // |
| 8107 | /* 22791 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 8108 | /* 22794 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8109 | /* 22798 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8110 | /* 22802 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 8111 | /* 22806 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 8112 | /* 22810 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 8113 | /* 22814 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 8114 | /* 22818 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 8115 | /* 22822 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 8116 | /* 22826 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm), |
| 8117 | /* 22830 */ // MIs[2] Operand 1 |
| 8118 | /* 22830 */ // No operand predicates |
| 8119 | /* 22830 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), |
| 8120 | /* 22834 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 8121 | /* 22836 */ // (or:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm, -1:{ *:[i32] })) => (t2ORNri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 8122 | /* 22836 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ORNri), |
| 8123 | /* 22839 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 8124 | /* 22841 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 8125 | /* 22843 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 8126 | /* 22846 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8127 | /* 22849 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8128 | /* 22855 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8129 | /* 22861 */ GIR_RootConstrainSelectedInstOperands, |
| 8130 | /* 22862 */ // GIR_Coverage, 496, |
| 8131 | /* 22862 */ GIR_EraseRootFromParent_Done, |
| 8132 | /* 22863 */ // Label 451: @22863 |
| 8133 | /* 22863 */ GIM_Try, /*On fail goto*//*Label 452*/ GIMT_Encode4(22934), // Rule ID 5478 // |
| 8134 | /* 22868 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 8135 | /* 22871 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8136 | /* 22875 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 8137 | /* 22879 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 8138 | /* 22883 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 8139 | /* 22887 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 8140 | /* 22891 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8141 | /* 22896 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), |
| 8142 | /* 22900 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8143 | /* 22904 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 8144 | /* 22906 */ // (or:{ *:[i32] } (xor:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, -1:{ *:[i32] }), rGPR:{ *:[i32] }:$Rn) => (t2ORNrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 8145 | /* 22906 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ORNrr), |
| 8146 | /* 22909 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 8147 | /* 22911 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 8148 | /* 22913 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 8149 | /* 22917 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8150 | /* 22920 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8151 | /* 22926 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8152 | /* 22932 */ GIR_RootConstrainSelectedInstOperands, |
| 8153 | /* 22933 */ // GIR_Coverage, 5478, |
| 8154 | /* 22933 */ GIR_EraseRootFromParent_Done, |
| 8155 | /* 22934 */ // Label 452: @22934 |
| 8156 | /* 22934 */ GIM_Try, /*On fail goto*//*Label 453*/ GIMT_Encode4(23005), // Rule ID 497 // |
| 8157 | /* 22939 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 8158 | /* 22942 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8159 | /* 22946 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8160 | /* 22950 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 8161 | /* 22954 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 8162 | /* 22958 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 8163 | /* 22962 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 8164 | /* 22966 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8165 | /* 22971 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), |
| 8166 | /* 22975 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 8167 | /* 22977 */ // (or:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, -1:{ *:[i32] })) => (t2ORNrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 8168 | /* 22977 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ORNrr), |
| 8169 | /* 22980 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 8170 | /* 22982 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 8171 | /* 22984 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 8172 | /* 22988 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8173 | /* 22991 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8174 | /* 22997 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8175 | /* 23003 */ GIR_RootConstrainSelectedInstOperands, |
| 8176 | /* 23004 */ // GIR_Coverage, 497, |
| 8177 | /* 23004 */ GIR_EraseRootFromParent_Done, |
| 8178 | /* 23005 */ // Label 453: @23005 |
| 8179 | /* 23005 */ GIM_Try, /*On fail goto*//*Label 454*/ GIMT_Encode4(23060), // Rule ID 1848 // |
| 8180 | /* 23010 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6T2_IsARM), |
| 8181 | /* 23013 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 8182 | /* 23017 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 8183 | /* 23021 */ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(4294901760), |
| 8184 | /* 23032 */ // (or:{ *:[i32] } GPR:{ *:[i32] }:$src, 4294901760:{ *:[i32] }) => (MOVTi16:{ *:[i32] } GPR:{ *:[i32] }:$src, 65535:{ *:[i32] }) |
| 8185 | /* 23032 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MOVTi16), |
| 8186 | /* 23035 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 8187 | /* 23037 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 8188 | /* 23039 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(65535), |
| 8189 | /* 23049 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8190 | /* 23052 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8191 | /* 23058 */ GIR_RootConstrainSelectedInstOperands, |
| 8192 | /* 23059 */ // GIR_Coverage, 1848, |
| 8193 | /* 23059 */ GIR_EraseRootFromParent_Done, |
| 8194 | /* 23060 */ // Label 454: @23060 |
| 8195 | /* 23060 */ GIM_Try, /*On fail goto*//*Label 455*/ GIMT_Encode4(23115), // Rule ID 2094 // |
| 8196 | /* 23065 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 8197 | /* 23068 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8198 | /* 23072 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8199 | /* 23076 */ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(4294901760), |
| 8200 | /* 23087 */ // (or:{ *:[i32] } rGPR:{ *:[i32] }:$src, 4294901760:{ *:[i32] }) => (t2MOVTi16:{ *:[i32] } rGPR:{ *:[i32] }:$src, 65535:{ *:[i32] }) |
| 8201 | /* 23087 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MOVTi16), |
| 8202 | /* 23090 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 8203 | /* 23092 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 8204 | /* 23094 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(65535), |
| 8205 | /* 23104 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8206 | /* 23107 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8207 | /* 23113 */ GIR_RootConstrainSelectedInstOperands, |
| 8208 | /* 23114 */ // GIR_Coverage, 2094, |
| 8209 | /* 23114 */ GIR_EraseRootFromParent_Done, |
| 8210 | /* 23115 */ // Label 455: @23115 |
| 8211 | /* 23115 */ GIM_Try, /*On fail goto*//*Label 456*/ GIMT_Encode4(23172), // Rule ID 151 // |
| 8212 | /* 23120 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 8213 | /* 23123 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 8214 | /* 23127 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 8215 | /* 23131 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 8216 | /* 23135 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 8217 | /* 23139 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm), |
| 8218 | /* 23143 */ // MIs[1] Operand 1 |
| 8219 | /* 23143 */ // No operand predicates |
| 8220 | /* 23143 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 8221 | /* 23145 */ // (or:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm) => (ORRri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 8222 | /* 23145 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::ORRri), |
| 8223 | /* 23148 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 8224 | /* 23150 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 8225 | /* 23152 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 8226 | /* 23155 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8227 | /* 23158 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8228 | /* 23164 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8229 | /* 23170 */ GIR_RootConstrainSelectedInstOperands, |
| 8230 | /* 23171 */ // GIR_Coverage, 151, |
| 8231 | /* 23171 */ GIR_EraseRootFromParent_Done, |
| 8232 | /* 23172 */ // Label 456: @23172 |
| 8233 | /* 23172 */ GIM_Try, /*On fail goto*//*Label 457*/ GIMT_Encode4(23229), // Rule ID 484 // |
| 8234 | /* 23177 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 8235 | /* 23180 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8236 | /* 23184 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8237 | /* 23188 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 8238 | /* 23192 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 8239 | /* 23196 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm), |
| 8240 | /* 23200 */ // MIs[1] Operand 1 |
| 8241 | /* 23200 */ // No operand predicates |
| 8242 | /* 23200 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 8243 | /* 23202 */ // (or:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm) => (t2ORRri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 8244 | /* 23202 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ORRri), |
| 8245 | /* 23205 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 8246 | /* 23207 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 8247 | /* 23209 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 8248 | /* 23212 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8249 | /* 23215 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8250 | /* 23221 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8251 | /* 23227 */ GIR_RootConstrainSelectedInstOperands, |
| 8252 | /* 23228 */ // GIR_Coverage, 484, |
| 8253 | /* 23228 */ GIR_EraseRootFromParent_Done, |
| 8254 | /* 23229 */ // Label 457: @23229 |
| 8255 | /* 23229 */ GIM_Try, /*On fail goto*//*Label 458*/ GIMT_Encode4(23275), // Rule ID 152 // |
| 8256 | /* 23234 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 8257 | /* 23237 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 8258 | /* 23241 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 8259 | /* 23245 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 8260 | /* 23249 */ // (or:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (ORRrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) |
| 8261 | /* 23249 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::ORRrr), |
| 8262 | /* 23252 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 8263 | /* 23254 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 8264 | /* 23256 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 8265 | /* 23258 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8266 | /* 23261 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8267 | /* 23267 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8268 | /* 23273 */ GIR_RootConstrainSelectedInstOperands, |
| 8269 | /* 23274 */ // GIR_Coverage, 152, |
| 8270 | /* 23274 */ GIR_EraseRootFromParent_Done, |
| 8271 | /* 23275 */ // Label 458: @23275 |
| 8272 | /* 23275 */ GIM_Try, /*On fail goto*//*Label 459*/ GIMT_Encode4(23321), // Rule ID 325 // |
| 8273 | /* 23280 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), |
| 8274 | /* 23283 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 8275 | /* 23287 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 8276 | /* 23291 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 8277 | /* 23295 */ // (or:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) => (tORR:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) |
| 8278 | /* 23295 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tORR), |
| 8279 | /* 23298 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn] |
| 8280 | /* 23300 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define | RegState::Dead), |
| 8281 | /* 23306 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 8282 | /* 23308 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 8283 | /* 23310 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8284 | /* 23313 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8285 | /* 23319 */ GIR_RootConstrainSelectedInstOperands, |
| 8286 | /* 23320 */ // GIR_Coverage, 325, |
| 8287 | /* 23320 */ GIR_EraseRootFromParent_Done, |
| 8288 | /* 23321 */ // Label 459: @23321 |
| 8289 | /* 23321 */ GIM_Try, /*On fail goto*//*Label 460*/ GIMT_Encode4(23367), // Rule ID 485 // |
| 8290 | /* 23326 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 8291 | /* 23329 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8292 | /* 23333 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8293 | /* 23337 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8294 | /* 23341 */ // (or:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2ORRrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 8295 | /* 23341 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ORRrr), |
| 8296 | /* 23344 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 8297 | /* 23346 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 8298 | /* 23348 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 8299 | /* 23350 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8300 | /* 23353 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8301 | /* 23359 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8302 | /* 23365 */ GIR_RootConstrainSelectedInstOperands, |
| 8303 | /* 23366 */ // GIR_Coverage, 485, |
| 8304 | /* 23366 */ GIR_EraseRootFromParent_Done, |
| 8305 | /* 23367 */ // Label 460: @23367 |
| 8306 | /* 23367 */ GIM_Reject, |
| 8307 | /* 23368 */ // Label 415: @23368 |
| 8308 | /* 23368 */ GIM_Reject, |
| 8309 | /* 23369 */ // Label 402: @23369 |
| 8310 | /* 23369 */ GIM_Try, /*On fail goto*//*Label 461*/ GIMT_Encode4(23415), // Rule ID 2532 // |
| 8311 | /* 23374 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 8312 | /* 23377 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 8313 | /* 23380 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 8314 | /* 23383 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8315 | /* 23387 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8316 | /* 23391 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8317 | /* 23395 */ // (or:{ *:[v1i64] } DPR:{ *:[v1i64] }:$LHS, DPR:{ *:[v1i64] }:$RHS) => (VORRd:{ *:[v1i64] } DPR:{ *:[v1i64] }:$LHS, DPR:{ *:[v1i64] }:$RHS) |
| 8318 | /* 23395 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VORRd), |
| 8319 | /* 23398 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 8320 | /* 23400 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS |
| 8321 | /* 23402 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS |
| 8322 | /* 23404 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8323 | /* 23407 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8324 | /* 23413 */ GIR_RootConstrainSelectedInstOperands, |
| 8325 | /* 23414 */ // GIR_Coverage, 2532, |
| 8326 | /* 23414 */ GIR_EraseRootFromParent_Done, |
| 8327 | /* 23415 */ // Label 461: @23415 |
| 8328 | /* 23415 */ GIM_Reject, |
| 8329 | /* 23416 */ // Label 403: @23416 |
| 8330 | /* 23416 */ GIM_Try, /*On fail goto*//*Label 462*/ GIMT_Encode4(23533), // Rule ID 1834 // |
| 8331 | /* 23421 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 8332 | /* 23424 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s1, |
| 8333 | /* 23427 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s1, |
| 8334 | /* 23430 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 8335 | /* 23434 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 8336 | /* 23438 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 8337 | /* 23442 */ // (or:{ *:[v2i1] } VCCR:{ *:[v2i1] }:$p1, VCCR:{ *:[v2i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v2i1] } (t2ORRrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v2i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v2i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] }) |
| 8338 | /* 23442 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, |
| 8339 | /* 23445 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8340 | /* 23449 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8341 | /* 23454 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2 |
| 8342 | /* 23458 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 8343 | /* 23463 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 8344 | /* 23466 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8345 | /* 23470 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8346 | /* 23475 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1 |
| 8347 | /* 23479 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 8348 | /* 23484 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 8349 | /* 23487 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2ORRrr), |
| 8350 | /* 23491 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8351 | /* 23496 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 8352 | /* 23499 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 8353 | /* 23502 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 8354 | /* 23505 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8355 | /* 23511 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8356 | /* 23517 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 8357 | /* 23519 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8358 | /* 23522 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 8359 | /* 23524 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 8360 | /* 23527 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID), |
| 8361 | /* 23532 */ // GIR_Coverage, 1834, |
| 8362 | /* 23532 */ GIR_EraseRootFromParent_Done, |
| 8363 | /* 23533 */ // Label 462: @23533 |
| 8364 | /* 23533 */ GIM_Reject, |
| 8365 | /* 23534 */ // Label 404: @23534 |
| 8366 | /* 23534 */ GIM_Try, /*On fail goto*//*Label 463*/ GIMT_Encode4(23580), // Rule ID 1137 // |
| 8367 | /* 23539 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 8368 | /* 23542 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 8369 | /* 23545 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 8370 | /* 23548 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8371 | /* 23552 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8372 | /* 23556 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8373 | /* 23560 */ // (or:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VORRd:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 8374 | /* 23560 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VORRd), |
| 8375 | /* 23563 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 8376 | /* 23565 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 8377 | /* 23567 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 8378 | /* 23569 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8379 | /* 23572 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8380 | /* 23578 */ GIR_RootConstrainSelectedInstOperands, |
| 8381 | /* 23579 */ // GIR_Coverage, 1137, |
| 8382 | /* 23579 */ GIR_EraseRootFromParent_Done, |
| 8383 | /* 23580 */ // Label 463: @23580 |
| 8384 | /* 23580 */ GIM_Reject, |
| 8385 | /* 23581 */ // Label 405: @23581 |
| 8386 | /* 23581 */ GIM_Try, /*On fail goto*//*Label 464*/ GIMT_Encode4(23694), |
| 8387 | /* 23586 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 8388 | /* 23589 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 8389 | /* 23592 */ GIM_Try, /*On fail goto*//*Label 465*/ GIMT_Encode4(23632), // Rule ID 2535 // |
| 8390 | /* 23597 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 8391 | /* 23600 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 8392 | /* 23604 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 8393 | /* 23608 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 8394 | /* 23612 */ // (or:{ *:[v2i64] } QPR:{ *:[v2i64] }:$LHS, QPR:{ *:[v2i64] }:$RHS) => (VORRq:{ *:[v2i64] } QPR:{ *:[v2i64] }:$LHS, QPR:{ *:[v2i64] }:$RHS) |
| 8395 | /* 23612 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VORRq), |
| 8396 | /* 23615 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 8397 | /* 23617 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS |
| 8398 | /* 23619 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS |
| 8399 | /* 23621 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8400 | /* 23624 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8401 | /* 23630 */ GIR_RootConstrainSelectedInstOperands, |
| 8402 | /* 23631 */ // GIR_Coverage, 2535, |
| 8403 | /* 23631 */ GIR_EraseRootFromParent_Done, |
| 8404 | /* 23632 */ // Label 465: @23632 |
| 8405 | /* 23632 */ GIM_Try, /*On fail goto*//*Label 466*/ GIMT_Encode4(23693), // Rule ID 3384 // |
| 8406 | /* 23637 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 8407 | /* 23640 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 8408 | /* 23644 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 8409 | /* 23648 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 8410 | /* 23652 */ // (or:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$Qm, MQPR:{ *:[v2i64] }:$Qn) => (MVE_VORR:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$Qm, MQPR:{ *:[v2i64] }:$Qn) |
| 8411 | /* 23652 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 8412 | /* 23655 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 8413 | /* 23659 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8414 | /* 23664 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VORR), |
| 8415 | /* 23667 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 8416 | /* 23669 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 8417 | /* 23671 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 8418 | /* 23673 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 8419 | /* 23676 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8420 | /* 23682 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8421 | /* 23688 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 8422 | /* 23691 */ GIR_RootConstrainSelectedInstOperands, |
| 8423 | /* 23692 */ // GIR_Coverage, 3384, |
| 8424 | /* 23692 */ GIR_EraseRootFromParent_Done, |
| 8425 | /* 23693 */ // Label 466: @23693 |
| 8426 | /* 23693 */ GIM_Reject, |
| 8427 | /* 23694 */ // Label 464: @23694 |
| 8428 | /* 23694 */ GIM_Reject, |
| 8429 | /* 23695 */ // Label 406: @23695 |
| 8430 | /* 23695 */ GIM_Try, /*On fail goto*//*Label 467*/ GIMT_Encode4(23812), // Rule ID 1835 // |
| 8431 | /* 23700 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 8432 | /* 23703 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s1, |
| 8433 | /* 23706 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s1, |
| 8434 | /* 23709 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 8435 | /* 23713 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 8436 | /* 23717 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 8437 | /* 23721 */ // (or:{ *:[v4i1] } VCCR:{ *:[v4i1] }:$p1, VCCR:{ *:[v4i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v4i1] } (t2ORRrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v4i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v4i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] }) |
| 8438 | /* 23721 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, |
| 8439 | /* 23724 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8440 | /* 23728 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8441 | /* 23733 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2 |
| 8442 | /* 23737 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 8443 | /* 23742 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 8444 | /* 23745 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8445 | /* 23749 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8446 | /* 23754 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1 |
| 8447 | /* 23758 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 8448 | /* 23763 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 8449 | /* 23766 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2ORRrr), |
| 8450 | /* 23770 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8451 | /* 23775 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 8452 | /* 23778 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 8453 | /* 23781 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 8454 | /* 23784 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8455 | /* 23790 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8456 | /* 23796 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 8457 | /* 23798 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8458 | /* 23801 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 8459 | /* 23803 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 8460 | /* 23806 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID), |
| 8461 | /* 23811 */ // GIR_Coverage, 1835, |
| 8462 | /* 23811 */ GIR_EraseRootFromParent_Done, |
| 8463 | /* 23812 */ // Label 467: @23812 |
| 8464 | /* 23812 */ GIM_Reject, |
| 8465 | /* 23813 */ // Label 407: @23813 |
| 8466 | /* 23813 */ GIM_Try, /*On fail goto*//*Label 468*/ GIMT_Encode4(23859), // Rule ID 2531 // |
| 8467 | /* 23818 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 8468 | /* 23821 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 8469 | /* 23824 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 8470 | /* 23827 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8471 | /* 23831 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8472 | /* 23835 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8473 | /* 23839 */ // (or:{ *:[v4i16] } DPR:{ *:[v4i16] }:$LHS, DPR:{ *:[v4i16] }:$RHS) => (VORRd:{ *:[v4i16] } DPR:{ *:[v4i16] }:$LHS, DPR:{ *:[v4i16] }:$RHS) |
| 8474 | /* 23839 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VORRd), |
| 8475 | /* 23842 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 8476 | /* 23844 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS |
| 8477 | /* 23846 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS |
| 8478 | /* 23848 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8479 | /* 23851 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8480 | /* 23857 */ GIR_RootConstrainSelectedInstOperands, |
| 8481 | /* 23858 */ // GIR_Coverage, 2531, |
| 8482 | /* 23858 */ GIR_EraseRootFromParent_Done, |
| 8483 | /* 23859 */ // Label 468: @23859 |
| 8484 | /* 23859 */ GIM_Reject, |
| 8485 | /* 23860 */ // Label 408: @23860 |
| 8486 | /* 23860 */ GIM_Try, /*On fail goto*//*Label 469*/ GIMT_Encode4(23973), |
| 8487 | /* 23865 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 8488 | /* 23868 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 8489 | /* 23871 */ GIM_Try, /*On fail goto*//*Label 470*/ GIMT_Encode4(23911), // Rule ID 1138 // |
| 8490 | /* 23876 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 8491 | /* 23879 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 8492 | /* 23883 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 8493 | /* 23887 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 8494 | /* 23891 */ // (or:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VORRq:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 8495 | /* 23891 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VORRq), |
| 8496 | /* 23894 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 8497 | /* 23896 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 8498 | /* 23898 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 8499 | /* 23900 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8500 | /* 23903 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8501 | /* 23909 */ GIR_RootConstrainSelectedInstOperands, |
| 8502 | /* 23910 */ // GIR_Coverage, 1138, |
| 8503 | /* 23910 */ GIR_EraseRootFromParent_Done, |
| 8504 | /* 23911 */ // Label 470: @23911 |
| 8505 | /* 23911 */ GIM_Try, /*On fail goto*//*Label 471*/ GIMT_Encode4(23972), // Rule ID 3380 // |
| 8506 | /* 23916 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 8507 | /* 23919 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 8508 | /* 23923 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 8509 | /* 23927 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 8510 | /* 23931 */ // (or:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VORR:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 8511 | /* 23931 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 8512 | /* 23934 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 8513 | /* 23938 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8514 | /* 23943 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VORR), |
| 8515 | /* 23946 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 8516 | /* 23948 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 8517 | /* 23950 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 8518 | /* 23952 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 8519 | /* 23955 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8520 | /* 23961 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8521 | /* 23967 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 8522 | /* 23970 */ GIR_RootConstrainSelectedInstOperands, |
| 8523 | /* 23971 */ // GIR_Coverage, 3380, |
| 8524 | /* 23971 */ GIR_EraseRootFromParent_Done, |
| 8525 | /* 23972 */ // Label 471: @23972 |
| 8526 | /* 23972 */ GIM_Reject, |
| 8527 | /* 23973 */ // Label 469: @23973 |
| 8528 | /* 23973 */ GIM_Reject, |
| 8529 | /* 23974 */ // Label 409: @23974 |
| 8530 | /* 23974 */ GIM_Try, /*On fail goto*//*Label 472*/ GIMT_Encode4(24091), // Rule ID 1836 // |
| 8531 | /* 23979 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 8532 | /* 23982 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s1, |
| 8533 | /* 23985 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s1, |
| 8534 | /* 23988 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 8535 | /* 23992 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 8536 | /* 23996 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 8537 | /* 24000 */ // (or:{ *:[v8i1] } VCCR:{ *:[v8i1] }:$p1, VCCR:{ *:[v8i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v8i1] } (t2ORRrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v8i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v8i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] }) |
| 8538 | /* 24000 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, |
| 8539 | /* 24003 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8540 | /* 24007 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8541 | /* 24012 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2 |
| 8542 | /* 24016 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 8543 | /* 24021 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 8544 | /* 24024 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8545 | /* 24028 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8546 | /* 24033 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1 |
| 8547 | /* 24037 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 8548 | /* 24042 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 8549 | /* 24045 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2ORRrr), |
| 8550 | /* 24049 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8551 | /* 24054 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 8552 | /* 24057 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 8553 | /* 24060 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 8554 | /* 24063 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8555 | /* 24069 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8556 | /* 24075 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 8557 | /* 24077 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8558 | /* 24080 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 8559 | /* 24082 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 8560 | /* 24085 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID), |
| 8561 | /* 24090 */ // GIR_Coverage, 1836, |
| 8562 | /* 24090 */ GIR_EraseRootFromParent_Done, |
| 8563 | /* 24091 */ // Label 472: @24091 |
| 8564 | /* 24091 */ GIM_Reject, |
| 8565 | /* 24092 */ // Label 410: @24092 |
| 8566 | /* 24092 */ GIM_Try, /*On fail goto*//*Label 473*/ GIMT_Encode4(24138), // Rule ID 2530 // |
| 8567 | /* 24097 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 8568 | /* 24100 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 8569 | /* 24103 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 8570 | /* 24106 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8571 | /* 24110 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8572 | /* 24114 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8573 | /* 24118 */ // (or:{ *:[v8i8] } DPR:{ *:[v8i8] }:$LHS, DPR:{ *:[v8i8] }:$RHS) => (VORRd:{ *:[v8i8] } DPR:{ *:[v8i8] }:$LHS, DPR:{ *:[v8i8] }:$RHS) |
| 8574 | /* 24118 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VORRd), |
| 8575 | /* 24121 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 8576 | /* 24123 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS |
| 8577 | /* 24125 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS |
| 8578 | /* 24127 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8579 | /* 24130 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8580 | /* 24136 */ GIR_RootConstrainSelectedInstOperands, |
| 8581 | /* 24137 */ // GIR_Coverage, 2530, |
| 8582 | /* 24137 */ GIR_EraseRootFromParent_Done, |
| 8583 | /* 24138 */ // Label 473: @24138 |
| 8584 | /* 24138 */ GIM_Reject, |
| 8585 | /* 24139 */ // Label 411: @24139 |
| 8586 | /* 24139 */ GIM_Try, /*On fail goto*//*Label 474*/ GIMT_Encode4(24252), |
| 8587 | /* 24144 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 8588 | /* 24147 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 8589 | /* 24150 */ GIM_Try, /*On fail goto*//*Label 475*/ GIMT_Encode4(24190), // Rule ID 2534 // |
| 8590 | /* 24155 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 8591 | /* 24158 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 8592 | /* 24162 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 8593 | /* 24166 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 8594 | /* 24170 */ // (or:{ *:[v8i16] } QPR:{ *:[v8i16] }:$LHS, QPR:{ *:[v8i16] }:$RHS) => (VORRq:{ *:[v8i16] } QPR:{ *:[v8i16] }:$LHS, QPR:{ *:[v8i16] }:$RHS) |
| 8595 | /* 24170 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VORRq), |
| 8596 | /* 24173 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 8597 | /* 24175 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS |
| 8598 | /* 24177 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS |
| 8599 | /* 24179 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8600 | /* 24182 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8601 | /* 24188 */ GIR_RootConstrainSelectedInstOperands, |
| 8602 | /* 24189 */ // GIR_Coverage, 2534, |
| 8603 | /* 24189 */ GIR_EraseRootFromParent_Done, |
| 8604 | /* 24190 */ // Label 475: @24190 |
| 8605 | /* 24190 */ GIM_Try, /*On fail goto*//*Label 476*/ GIMT_Encode4(24251), // Rule ID 3376 // |
| 8606 | /* 24195 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 8607 | /* 24198 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 8608 | /* 24202 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 8609 | /* 24206 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 8610 | /* 24210 */ // (or:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VORR:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 8611 | /* 24210 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 8612 | /* 24213 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 8613 | /* 24217 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8614 | /* 24222 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VORR), |
| 8615 | /* 24225 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 8616 | /* 24227 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 8617 | /* 24229 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 8618 | /* 24231 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 8619 | /* 24234 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8620 | /* 24240 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8621 | /* 24246 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 8622 | /* 24249 */ GIR_RootConstrainSelectedInstOperands, |
| 8623 | /* 24250 */ // GIR_Coverage, 3376, |
| 8624 | /* 24250 */ GIR_EraseRootFromParent_Done, |
| 8625 | /* 24251 */ // Label 476: @24251 |
| 8626 | /* 24251 */ GIM_Reject, |
| 8627 | /* 24252 */ // Label 474: @24252 |
| 8628 | /* 24252 */ GIM_Reject, |
| 8629 | /* 24253 */ // Label 412: @24253 |
| 8630 | /* 24253 */ GIM_Try, /*On fail goto*//*Label 477*/ GIMT_Encode4(24370), // Rule ID 1837 // |
| 8631 | /* 24258 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 8632 | /* 24261 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s1, |
| 8633 | /* 24264 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s1, |
| 8634 | /* 24267 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 8635 | /* 24271 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 8636 | /* 24275 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 8637 | /* 24279 */ // (or:{ *:[v16i1] } VCCR:{ *:[v16i1] }:$p1, VCCR:{ *:[v16i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v16i1] } (t2ORRrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v16i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v16i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] }) |
| 8638 | /* 24279 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, |
| 8639 | /* 24282 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8640 | /* 24286 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8641 | /* 24291 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2 |
| 8642 | /* 24295 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 8643 | /* 24300 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 8644 | /* 24303 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8645 | /* 24307 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8646 | /* 24312 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1 |
| 8647 | /* 24316 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 8648 | /* 24321 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 8649 | /* 24324 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2ORRrr), |
| 8650 | /* 24328 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8651 | /* 24333 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 8652 | /* 24336 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 8653 | /* 24339 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 8654 | /* 24342 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8655 | /* 24348 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8656 | /* 24354 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 8657 | /* 24356 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8658 | /* 24359 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 8659 | /* 24361 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 8660 | /* 24364 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID), |
| 8661 | /* 24369 */ // GIR_Coverage, 1837, |
| 8662 | /* 24369 */ GIR_EraseRootFromParent_Done, |
| 8663 | /* 24370 */ // Label 477: @24370 |
| 8664 | /* 24370 */ GIM_Reject, |
| 8665 | /* 24371 */ // Label 413: @24371 |
| 8666 | /* 24371 */ GIM_Try, /*On fail goto*//*Label 478*/ GIMT_Encode4(24484), |
| 8667 | /* 24376 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 8668 | /* 24379 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 8669 | /* 24382 */ GIM_Try, /*On fail goto*//*Label 479*/ GIMT_Encode4(24422), // Rule ID 2533 // |
| 8670 | /* 24387 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 8671 | /* 24390 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 8672 | /* 24394 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 8673 | /* 24398 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 8674 | /* 24402 */ // (or:{ *:[v16i8] } QPR:{ *:[v16i8] }:$LHS, QPR:{ *:[v16i8] }:$RHS) => (VORRq:{ *:[v16i8] } QPR:{ *:[v16i8] }:$LHS, QPR:{ *:[v16i8] }:$RHS) |
| 8675 | /* 24402 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VORRq), |
| 8676 | /* 24405 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 8677 | /* 24407 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS |
| 8678 | /* 24409 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS |
| 8679 | /* 24411 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8680 | /* 24414 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8681 | /* 24420 */ GIR_RootConstrainSelectedInstOperands, |
| 8682 | /* 24421 */ // GIR_Coverage, 2533, |
| 8683 | /* 24421 */ GIR_EraseRootFromParent_Done, |
| 8684 | /* 24422 */ // Label 479: @24422 |
| 8685 | /* 24422 */ GIM_Try, /*On fail goto*//*Label 480*/ GIMT_Encode4(24483), // Rule ID 3372 // |
| 8686 | /* 24427 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 8687 | /* 24430 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 8688 | /* 24434 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 8689 | /* 24438 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 8690 | /* 24442 */ // (or:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VORR:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 8691 | /* 24442 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 8692 | /* 24445 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 8693 | /* 24449 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8694 | /* 24454 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VORR), |
| 8695 | /* 24457 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 8696 | /* 24459 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 8697 | /* 24461 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 8698 | /* 24463 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 8699 | /* 24466 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8700 | /* 24472 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8701 | /* 24478 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 8702 | /* 24481 */ GIR_RootConstrainSelectedInstOperands, |
| 8703 | /* 24482 */ // GIR_Coverage, 3372, |
| 8704 | /* 24482 */ GIR_EraseRootFromParent_Done, |
| 8705 | /* 24483 */ // Label 480: @24483 |
| 8706 | /* 24483 */ GIM_Reject, |
| 8707 | /* 24484 */ // Label 478: @24484 |
| 8708 | /* 24484 */ GIM_Reject, |
| 8709 | /* 24485 */ // Label 414: @24485 |
| 8710 | /* 24485 */ GIM_Reject, |
| 8711 | /* 24486 */ // Label 7: @24486 |
| 8712 | /* 24486 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(16), /*)*//*default:*//*Label 494*/ GIMT_Encode4(26180), |
| 8713 | /* 24497 */ /*GILLT_s32*//*Label 481*/ GIMT_Encode4(24557), |
| 8714 | /* 24501 */ /*GILLT_s64*//*Label 482*/ GIMT_Encode4(25064), |
| 8715 | /* 24505 */ /*GILLT_v2s1*//*Label 483*/ GIMT_Encode4(25111), |
| 8716 | /* 24509 */ /*GILLT_v2s32*//*Label 484*/ GIMT_Encode4(25229), |
| 8717 | /* 24513 */ /*GILLT_v2s64*//*Label 485*/ GIMT_Encode4(25276), |
| 8718 | /* 24517 */ /*GILLT_v4s1*//*Label 486*/ GIMT_Encode4(25390), |
| 8719 | /* 24521 */ /*GILLT_v4s16*//*Label 487*/ GIMT_Encode4(25508), |
| 8720 | /* 24525 */ /*GILLT_v4s32*//*Label 488*/ GIMT_Encode4(25555), GIMT_Encode4(0), |
| 8721 | /* 24533 */ /*GILLT_v8s1*//*Label 489*/ GIMT_Encode4(25669), |
| 8722 | /* 24537 */ /*GILLT_v8s8*//*Label 490*/ GIMT_Encode4(25787), |
| 8723 | /* 24541 */ /*GILLT_v8s16*//*Label 491*/ GIMT_Encode4(25834), GIMT_Encode4(0), |
| 8724 | /* 24549 */ /*GILLT_v16s1*//*Label 492*/ GIMT_Encode4(25948), |
| 8725 | /* 24553 */ /*GILLT_v16s8*//*Label 493*/ GIMT_Encode4(26066), |
| 8726 | /* 24557 */ // Label 481: @24557 |
| 8727 | /* 24557 */ GIM_Try, /*On fail goto*//*Label 495*/ GIMT_Encode4(25063), |
| 8728 | /* 24562 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 8729 | /* 24565 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 8730 | /* 24568 */ GIM_Try, /*On fail goto*//*Label 496*/ GIMT_Encode4(24623), // Rule ID 5480 // |
| 8731 | /* 24573 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 8732 | /* 24576 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8733 | /* 24580 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/1, uint8_t(-1), |
| 8734 | /* 24584 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 8735 | /* 24588 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 8736 | /* 24592 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm), |
| 8737 | /* 24596 */ // MIs[1] Operand 1 |
| 8738 | /* 24596 */ // No operand predicates |
| 8739 | /* 24596 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 8740 | /* 24598 */ // (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm) => (t2MVNi:{ *:[i32] } (imm:{ *:[i32] }):$imm) |
| 8741 | /* 24598 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MVNi), |
| 8742 | /* 24601 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 8743 | /* 24603 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 8744 | /* 24606 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8745 | /* 24609 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8746 | /* 24615 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8747 | /* 24621 */ GIR_RootConstrainSelectedInstOperands, |
| 8748 | /* 24622 */ // GIR_Coverage, 5480, |
| 8749 | /* 24622 */ GIR_EraseRootFromParent_Done, |
| 8750 | /* 24623 */ // Label 496: @24623 |
| 8751 | /* 24623 */ GIM_Try, /*On fail goto*//*Label 497*/ GIMT_Encode4(24678), // Rule ID 499 // |
| 8752 | /* 24628 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 8753 | /* 24631 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8754 | /* 24635 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 8755 | /* 24639 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 8756 | /* 24643 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm), |
| 8757 | /* 24647 */ // MIs[1] Operand 1 |
| 8758 | /* 24647 */ // No operand predicates |
| 8759 | /* 24647 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1), |
| 8760 | /* 24651 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 8761 | /* 24653 */ // (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm, -1:{ *:[i32] }) => (t2MVNi:{ *:[i32] } (imm:{ *:[i32] }):$imm) |
| 8762 | /* 24653 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MVNi), |
| 8763 | /* 24656 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 8764 | /* 24658 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 8765 | /* 24661 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8766 | /* 24664 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8767 | /* 24670 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8768 | /* 24676 */ GIR_RootConstrainSelectedInstOperands, |
| 8769 | /* 24677 */ // GIR_Coverage, 499, |
| 8770 | /* 24677 */ GIR_EraseRootFromParent_Done, |
| 8771 | /* 24678 */ // Label 497: @24678 |
| 8772 | /* 24678 */ GIM_Try, /*On fail goto*//*Label 498*/ GIMT_Encode4(24722), // Rule ID 500 // |
| 8773 | /* 24683 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 8774 | /* 24686 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8775 | /* 24690 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8776 | /* 24694 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1), |
| 8777 | /* 24698 */ // (xor:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, -1:{ *:[i32] }) => (t2MVNr:{ *:[i32] } rGPR:{ *:[i32] }:$Rm) |
| 8778 | /* 24698 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MVNr), |
| 8779 | /* 24701 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 8780 | /* 24703 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 8781 | /* 24705 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8782 | /* 24708 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8783 | /* 24714 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8784 | /* 24720 */ GIR_RootConstrainSelectedInstOperands, |
| 8785 | /* 24721 */ // GIR_Coverage, 500, |
| 8786 | /* 24721 */ GIR_EraseRootFromParent_Done, |
| 8787 | /* 24722 */ // Label 498: @24722 |
| 8788 | /* 24722 */ GIM_Try, /*On fail goto*//*Label 499*/ GIMT_Encode4(24766), // Rule ID 165 // |
| 8789 | /* 24727 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 8790 | /* 24730 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 8791 | /* 24734 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 8792 | /* 24738 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1), |
| 8793 | /* 24742 */ // (xor:{ *:[i32] } GPR:{ *:[i32] }:$Rm, -1:{ *:[i32] }) => (MVNr:{ *:[i32] } GPR:{ *:[i32] }:$Rm) |
| 8794 | /* 24742 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVNr), |
| 8795 | /* 24745 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 8796 | /* 24747 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 8797 | /* 24749 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8798 | /* 24752 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8799 | /* 24758 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8800 | /* 24764 */ GIR_RootConstrainSelectedInstOperands, |
| 8801 | /* 24765 */ // GIR_Coverage, 165, |
| 8802 | /* 24765 */ GIR_EraseRootFromParent_Done, |
| 8803 | /* 24766 */ // Label 499: @24766 |
| 8804 | /* 24766 */ GIM_Try, /*On fail goto*//*Label 500*/ GIMT_Encode4(24810), // Rule ID 324 // |
| 8805 | /* 24771 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), |
| 8806 | /* 24774 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 8807 | /* 24778 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 8808 | /* 24782 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1), |
| 8809 | /* 24786 */ // (xor:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, -1:{ *:[i32] }) => (tMVN:{ *:[i32] } tGPR:{ *:[i32] }:$Rn) |
| 8810 | /* 24786 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tMVN), |
| 8811 | /* 24789 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 8812 | /* 24791 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define | RegState::Dead), |
| 8813 | /* 24797 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 8814 | /* 24799 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8815 | /* 24802 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8816 | /* 24808 */ GIR_RootConstrainSelectedInstOperands, |
| 8817 | /* 24809 */ // GIR_Coverage, 324, |
| 8818 | /* 24809 */ GIR_EraseRootFromParent_Done, |
| 8819 | /* 24810 */ // Label 500: @24810 |
| 8820 | /* 24810 */ GIM_Try, /*On fail goto*//*Label 501*/ GIMT_Encode4(24867), // Rule ID 155 // |
| 8821 | /* 24815 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 8822 | /* 24818 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 8823 | /* 24822 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 8824 | /* 24826 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 8825 | /* 24830 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 8826 | /* 24834 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm), |
| 8827 | /* 24838 */ // MIs[1] Operand 1 |
| 8828 | /* 24838 */ // No operand predicates |
| 8829 | /* 24838 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 8830 | /* 24840 */ // (xor:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm) => (EORri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 8831 | /* 24840 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::EORri), |
| 8832 | /* 24843 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 8833 | /* 24845 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 8834 | /* 24847 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 8835 | /* 24850 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8836 | /* 24853 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8837 | /* 24859 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8838 | /* 24865 */ GIR_RootConstrainSelectedInstOperands, |
| 8839 | /* 24866 */ // GIR_Coverage, 155, |
| 8840 | /* 24866 */ GIR_EraseRootFromParent_Done, |
| 8841 | /* 24867 */ // Label 501: @24867 |
| 8842 | /* 24867 */ GIM_Try, /*On fail goto*//*Label 502*/ GIMT_Encode4(24924), // Rule ID 487 // |
| 8843 | /* 24872 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 8844 | /* 24875 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8845 | /* 24879 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8846 | /* 24883 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 8847 | /* 24887 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 8848 | /* 24891 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm), |
| 8849 | /* 24895 */ // MIs[1] Operand 1 |
| 8850 | /* 24895 */ // No operand predicates |
| 8851 | /* 24895 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 8852 | /* 24897 */ // (xor:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm) => (t2EORri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 8853 | /* 24897 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2EORri), |
| 8854 | /* 24900 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 8855 | /* 24902 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 8856 | /* 24904 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 8857 | /* 24907 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8858 | /* 24910 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8859 | /* 24916 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8860 | /* 24922 */ GIR_RootConstrainSelectedInstOperands, |
| 8861 | /* 24923 */ // GIR_Coverage, 487, |
| 8862 | /* 24923 */ GIR_EraseRootFromParent_Done, |
| 8863 | /* 24924 */ // Label 502: @24924 |
| 8864 | /* 24924 */ GIM_Try, /*On fail goto*//*Label 503*/ GIMT_Encode4(24970), // Rule ID 156 // |
| 8865 | /* 24929 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 8866 | /* 24932 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 8867 | /* 24936 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 8868 | /* 24940 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 8869 | /* 24944 */ // (xor:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (EORrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) |
| 8870 | /* 24944 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::EORrr), |
| 8871 | /* 24947 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 8872 | /* 24949 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 8873 | /* 24951 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 8874 | /* 24953 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8875 | /* 24956 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8876 | /* 24962 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8877 | /* 24968 */ GIR_RootConstrainSelectedInstOperands, |
| 8878 | /* 24969 */ // GIR_Coverage, 156, |
| 8879 | /* 24969 */ GIR_EraseRootFromParent_Done, |
| 8880 | /* 24970 */ // Label 503: @24970 |
| 8881 | /* 24970 */ GIM_Try, /*On fail goto*//*Label 504*/ GIMT_Encode4(25016), // Rule ID 317 // |
| 8882 | /* 24975 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), |
| 8883 | /* 24978 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 8884 | /* 24982 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 8885 | /* 24986 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 8886 | /* 24990 */ // (xor:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) => (tEOR:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) |
| 8887 | /* 24990 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tEOR), |
| 8888 | /* 24993 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn] |
| 8889 | /* 24995 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define | RegState::Dead), |
| 8890 | /* 25001 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 8891 | /* 25003 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 8892 | /* 25005 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8893 | /* 25008 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8894 | /* 25014 */ GIR_RootConstrainSelectedInstOperands, |
| 8895 | /* 25015 */ // GIR_Coverage, 317, |
| 8896 | /* 25015 */ GIR_EraseRootFromParent_Done, |
| 8897 | /* 25016 */ // Label 504: @25016 |
| 8898 | /* 25016 */ GIM_Try, /*On fail goto*//*Label 505*/ GIMT_Encode4(25062), // Rule ID 488 // |
| 8899 | /* 25021 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 8900 | /* 25024 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8901 | /* 25028 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8902 | /* 25032 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8903 | /* 25036 */ // (xor:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2EORrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 8904 | /* 25036 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2EORrr), |
| 8905 | /* 25039 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 8906 | /* 25041 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 8907 | /* 25043 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 8908 | /* 25045 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8909 | /* 25048 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8910 | /* 25054 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8911 | /* 25060 */ GIR_RootConstrainSelectedInstOperands, |
| 8912 | /* 25061 */ // GIR_Coverage, 488, |
| 8913 | /* 25061 */ GIR_EraseRootFromParent_Done, |
| 8914 | /* 25062 */ // Label 505: @25062 |
| 8915 | /* 25062 */ GIM_Reject, |
| 8916 | /* 25063 */ // Label 495: @25063 |
| 8917 | /* 25063 */ GIM_Reject, |
| 8918 | /* 25064 */ // Label 482: @25064 |
| 8919 | /* 25064 */ GIM_Try, /*On fail goto*//*Label 506*/ GIMT_Encode4(25110), // Rule ID 2538 // |
| 8920 | /* 25069 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 8921 | /* 25072 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 8922 | /* 25075 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 8923 | /* 25078 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8924 | /* 25082 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8925 | /* 25086 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8926 | /* 25090 */ // (xor:{ *:[v1i64] } DPR:{ *:[v1i64] }:$LHS, DPR:{ *:[v1i64] }:$RHS) => (VEORd:{ *:[v1i64] } DPR:{ *:[v1i64] }:$LHS, DPR:{ *:[v1i64] }:$RHS) |
| 8927 | /* 25090 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VEORd), |
| 8928 | /* 25093 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 8929 | /* 25095 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS |
| 8930 | /* 25097 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS |
| 8931 | /* 25099 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8932 | /* 25102 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8933 | /* 25108 */ GIR_RootConstrainSelectedInstOperands, |
| 8934 | /* 25109 */ // GIR_Coverage, 2538, |
| 8935 | /* 25109 */ GIR_EraseRootFromParent_Done, |
| 8936 | /* 25110 */ // Label 506: @25110 |
| 8937 | /* 25110 */ GIM_Reject, |
| 8938 | /* 25111 */ // Label 483: @25111 |
| 8939 | /* 25111 */ GIM_Try, /*On fail goto*//*Label 507*/ GIMT_Encode4(25228), // Rule ID 1830 // |
| 8940 | /* 25116 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 8941 | /* 25119 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s1, |
| 8942 | /* 25122 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s1, |
| 8943 | /* 25125 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 8944 | /* 25129 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 8945 | /* 25133 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 8946 | /* 25137 */ // (xor:{ *:[v2i1] } VCCR:{ *:[v2i1] }:$p1, VCCR:{ *:[v2i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v2i1] } (t2EORrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v2i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v2i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] }) |
| 8947 | /* 25137 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, |
| 8948 | /* 25140 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8949 | /* 25144 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8950 | /* 25149 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2 |
| 8951 | /* 25153 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 8952 | /* 25158 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 8953 | /* 25161 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8954 | /* 25165 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8955 | /* 25170 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1 |
| 8956 | /* 25174 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 8957 | /* 25179 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 8958 | /* 25182 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2EORrr), |
| 8959 | /* 25186 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8960 | /* 25191 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 8961 | /* 25194 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 8962 | /* 25197 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 8963 | /* 25200 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8964 | /* 25206 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8965 | /* 25212 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 8966 | /* 25214 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8967 | /* 25217 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 8968 | /* 25219 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 8969 | /* 25222 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID), |
| 8970 | /* 25227 */ // GIR_Coverage, 1830, |
| 8971 | /* 25227 */ GIR_EraseRootFromParent_Done, |
| 8972 | /* 25228 */ // Label 507: @25228 |
| 8973 | /* 25228 */ GIM_Reject, |
| 8974 | /* 25229 */ // Label 484: @25229 |
| 8975 | /* 25229 */ GIM_Try, /*On fail goto*//*Label 508*/ GIMT_Encode4(25275), // Rule ID 1135 // |
| 8976 | /* 25234 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 8977 | /* 25237 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 8978 | /* 25240 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 8979 | /* 25243 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8980 | /* 25247 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8981 | /* 25251 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8982 | /* 25255 */ // (xor:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VEORd:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 8983 | /* 25255 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VEORd), |
| 8984 | /* 25258 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 8985 | /* 25260 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 8986 | /* 25262 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 8987 | /* 25264 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8988 | /* 25267 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8989 | /* 25273 */ GIR_RootConstrainSelectedInstOperands, |
| 8990 | /* 25274 */ // GIR_Coverage, 1135, |
| 8991 | /* 25274 */ GIR_EraseRootFromParent_Done, |
| 8992 | /* 25275 */ // Label 508: @25275 |
| 8993 | /* 25275 */ GIM_Reject, |
| 8994 | /* 25276 */ // Label 485: @25276 |
| 8995 | /* 25276 */ GIM_Try, /*On fail goto*//*Label 509*/ GIMT_Encode4(25389), |
| 8996 | /* 25281 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 8997 | /* 25284 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 8998 | /* 25287 */ GIM_Try, /*On fail goto*//*Label 510*/ GIMT_Encode4(25327), // Rule ID 2541 // |
| 8999 | /* 25292 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 9000 | /* 25295 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9001 | /* 25299 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9002 | /* 25303 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9003 | /* 25307 */ // (xor:{ *:[v2i64] } QPR:{ *:[v2i64] }:$LHS, QPR:{ *:[v2i64] }:$RHS) => (VEORq:{ *:[v2i64] } QPR:{ *:[v2i64] }:$LHS, QPR:{ *:[v2i64] }:$RHS) |
| 9004 | /* 25307 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VEORq), |
| 9005 | /* 25310 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 9006 | /* 25312 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS |
| 9007 | /* 25314 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS |
| 9008 | /* 25316 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9009 | /* 25319 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9010 | /* 25325 */ GIR_RootConstrainSelectedInstOperands, |
| 9011 | /* 25326 */ // GIR_Coverage, 2541, |
| 9012 | /* 25326 */ GIR_EraseRootFromParent_Done, |
| 9013 | /* 25327 */ // Label 510: @25327 |
| 9014 | /* 25327 */ GIM_Try, /*On fail goto*//*Label 511*/ GIMT_Encode4(25388), // Rule ID 3398 // |
| 9015 | /* 25332 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 9016 | /* 25335 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9017 | /* 25339 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9018 | /* 25343 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9019 | /* 25347 */ // (xor:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$Qm, MQPR:{ *:[v2i64] }:$Qn) => (MVE_VEOR:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$Qm, MQPR:{ *:[v2i64] }:$Qn) |
| 9020 | /* 25347 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 9021 | /* 25350 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 9022 | /* 25354 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9023 | /* 25359 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VEOR), |
| 9024 | /* 25362 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 9025 | /* 25364 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 9026 | /* 25366 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 9027 | /* 25368 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 9028 | /* 25371 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9029 | /* 25377 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9030 | /* 25383 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 9031 | /* 25386 */ GIR_RootConstrainSelectedInstOperands, |
| 9032 | /* 25387 */ // GIR_Coverage, 3398, |
| 9033 | /* 25387 */ GIR_EraseRootFromParent_Done, |
| 9034 | /* 25388 */ // Label 511: @25388 |
| 9035 | /* 25388 */ GIM_Reject, |
| 9036 | /* 25389 */ // Label 509: @25389 |
| 9037 | /* 25389 */ GIM_Reject, |
| 9038 | /* 25390 */ // Label 486: @25390 |
| 9039 | /* 25390 */ GIM_Try, /*On fail goto*//*Label 512*/ GIMT_Encode4(25507), // Rule ID 1831 // |
| 9040 | /* 25395 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 9041 | /* 25398 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s1, |
| 9042 | /* 25401 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s1, |
| 9043 | /* 25404 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 9044 | /* 25408 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 9045 | /* 25412 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 9046 | /* 25416 */ // (xor:{ *:[v4i1] } VCCR:{ *:[v4i1] }:$p1, VCCR:{ *:[v4i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v4i1] } (t2EORrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v4i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v4i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] }) |
| 9047 | /* 25416 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, |
| 9048 | /* 25419 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9049 | /* 25423 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9050 | /* 25428 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2 |
| 9051 | /* 25432 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 9052 | /* 25437 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 9053 | /* 25440 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9054 | /* 25444 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9055 | /* 25449 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1 |
| 9056 | /* 25453 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 9057 | /* 25458 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 9058 | /* 25461 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2EORrr), |
| 9059 | /* 25465 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9060 | /* 25470 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 9061 | /* 25473 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 9062 | /* 25476 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 9063 | /* 25479 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9064 | /* 25485 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9065 | /* 25491 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 9066 | /* 25493 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9067 | /* 25496 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 9068 | /* 25498 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 9069 | /* 25501 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID), |
| 9070 | /* 25506 */ // GIR_Coverage, 1831, |
| 9071 | /* 25506 */ GIR_EraseRootFromParent_Done, |
| 9072 | /* 25507 */ // Label 512: @25507 |
| 9073 | /* 25507 */ GIM_Reject, |
| 9074 | /* 25508 */ // Label 487: @25508 |
| 9075 | /* 25508 */ GIM_Try, /*On fail goto*//*Label 513*/ GIMT_Encode4(25554), // Rule ID 2537 // |
| 9076 | /* 25513 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 9077 | /* 25516 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 9078 | /* 25519 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 9079 | /* 25522 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9080 | /* 25526 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9081 | /* 25530 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9082 | /* 25534 */ // (xor:{ *:[v4i16] } DPR:{ *:[v4i16] }:$LHS, DPR:{ *:[v4i16] }:$RHS) => (VEORd:{ *:[v4i16] } DPR:{ *:[v4i16] }:$LHS, DPR:{ *:[v4i16] }:$RHS) |
| 9083 | /* 25534 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VEORd), |
| 9084 | /* 25537 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 9085 | /* 25539 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS |
| 9086 | /* 25541 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS |
| 9087 | /* 25543 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9088 | /* 25546 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9089 | /* 25552 */ GIR_RootConstrainSelectedInstOperands, |
| 9090 | /* 25553 */ // GIR_Coverage, 2537, |
| 9091 | /* 25553 */ GIR_EraseRootFromParent_Done, |
| 9092 | /* 25554 */ // Label 513: @25554 |
| 9093 | /* 25554 */ GIM_Reject, |
| 9094 | /* 25555 */ // Label 488: @25555 |
| 9095 | /* 25555 */ GIM_Try, /*On fail goto*//*Label 514*/ GIMT_Encode4(25668), |
| 9096 | /* 25560 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 9097 | /* 25563 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 9098 | /* 25566 */ GIM_Try, /*On fail goto*//*Label 515*/ GIMT_Encode4(25606), // Rule ID 1136 // |
| 9099 | /* 25571 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 9100 | /* 25574 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9101 | /* 25578 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9102 | /* 25582 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9103 | /* 25586 */ // (xor:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VEORq:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 9104 | /* 25586 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VEORq), |
| 9105 | /* 25589 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 9106 | /* 25591 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 9107 | /* 25593 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 9108 | /* 25595 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9109 | /* 25598 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9110 | /* 25604 */ GIR_RootConstrainSelectedInstOperands, |
| 9111 | /* 25605 */ // GIR_Coverage, 1136, |
| 9112 | /* 25605 */ GIR_EraseRootFromParent_Done, |
| 9113 | /* 25606 */ // Label 515: @25606 |
| 9114 | /* 25606 */ GIM_Try, /*On fail goto*//*Label 516*/ GIMT_Encode4(25667), // Rule ID 3394 // |
| 9115 | /* 25611 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 9116 | /* 25614 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9117 | /* 25618 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9118 | /* 25622 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9119 | /* 25626 */ // (xor:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VEOR:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 9120 | /* 25626 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 9121 | /* 25629 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 9122 | /* 25633 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9123 | /* 25638 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VEOR), |
| 9124 | /* 25641 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 9125 | /* 25643 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 9126 | /* 25645 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 9127 | /* 25647 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 9128 | /* 25650 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9129 | /* 25656 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9130 | /* 25662 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 9131 | /* 25665 */ GIR_RootConstrainSelectedInstOperands, |
| 9132 | /* 25666 */ // GIR_Coverage, 3394, |
| 9133 | /* 25666 */ GIR_EraseRootFromParent_Done, |
| 9134 | /* 25667 */ // Label 516: @25667 |
| 9135 | /* 25667 */ GIM_Reject, |
| 9136 | /* 25668 */ // Label 514: @25668 |
| 9137 | /* 25668 */ GIM_Reject, |
| 9138 | /* 25669 */ // Label 489: @25669 |
| 9139 | /* 25669 */ GIM_Try, /*On fail goto*//*Label 517*/ GIMT_Encode4(25786), // Rule ID 1832 // |
| 9140 | /* 25674 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 9141 | /* 25677 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s1, |
| 9142 | /* 25680 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s1, |
| 9143 | /* 25683 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 9144 | /* 25687 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 9145 | /* 25691 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 9146 | /* 25695 */ // (xor:{ *:[v8i1] } VCCR:{ *:[v8i1] }:$p1, VCCR:{ *:[v8i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v8i1] } (t2EORrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v8i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v8i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] }) |
| 9147 | /* 25695 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, |
| 9148 | /* 25698 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9149 | /* 25702 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9150 | /* 25707 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2 |
| 9151 | /* 25711 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 9152 | /* 25716 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 9153 | /* 25719 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9154 | /* 25723 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9155 | /* 25728 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1 |
| 9156 | /* 25732 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 9157 | /* 25737 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 9158 | /* 25740 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2EORrr), |
| 9159 | /* 25744 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9160 | /* 25749 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 9161 | /* 25752 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 9162 | /* 25755 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 9163 | /* 25758 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9164 | /* 25764 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9165 | /* 25770 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 9166 | /* 25772 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9167 | /* 25775 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 9168 | /* 25777 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 9169 | /* 25780 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID), |
| 9170 | /* 25785 */ // GIR_Coverage, 1832, |
| 9171 | /* 25785 */ GIR_EraseRootFromParent_Done, |
| 9172 | /* 25786 */ // Label 517: @25786 |
| 9173 | /* 25786 */ GIM_Reject, |
| 9174 | /* 25787 */ // Label 490: @25787 |
| 9175 | /* 25787 */ GIM_Try, /*On fail goto*//*Label 518*/ GIMT_Encode4(25833), // Rule ID 2536 // |
| 9176 | /* 25792 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 9177 | /* 25795 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 9178 | /* 25798 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 9179 | /* 25801 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9180 | /* 25805 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9181 | /* 25809 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9182 | /* 25813 */ // (xor:{ *:[v8i8] } DPR:{ *:[v8i8] }:$LHS, DPR:{ *:[v8i8] }:$RHS) => (VEORd:{ *:[v8i8] } DPR:{ *:[v8i8] }:$LHS, DPR:{ *:[v8i8] }:$RHS) |
| 9183 | /* 25813 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VEORd), |
| 9184 | /* 25816 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 9185 | /* 25818 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS |
| 9186 | /* 25820 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS |
| 9187 | /* 25822 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9188 | /* 25825 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9189 | /* 25831 */ GIR_RootConstrainSelectedInstOperands, |
| 9190 | /* 25832 */ // GIR_Coverage, 2536, |
| 9191 | /* 25832 */ GIR_EraseRootFromParent_Done, |
| 9192 | /* 25833 */ // Label 518: @25833 |
| 9193 | /* 25833 */ GIM_Reject, |
| 9194 | /* 25834 */ // Label 491: @25834 |
| 9195 | /* 25834 */ GIM_Try, /*On fail goto*//*Label 519*/ GIMT_Encode4(25947), |
| 9196 | /* 25839 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 9197 | /* 25842 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 9198 | /* 25845 */ GIM_Try, /*On fail goto*//*Label 520*/ GIMT_Encode4(25885), // Rule ID 2540 // |
| 9199 | /* 25850 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 9200 | /* 25853 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9201 | /* 25857 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9202 | /* 25861 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9203 | /* 25865 */ // (xor:{ *:[v8i16] } QPR:{ *:[v8i16] }:$LHS, QPR:{ *:[v8i16] }:$RHS) => (VEORq:{ *:[v8i16] } QPR:{ *:[v8i16] }:$LHS, QPR:{ *:[v8i16] }:$RHS) |
| 9204 | /* 25865 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VEORq), |
| 9205 | /* 25868 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 9206 | /* 25870 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS |
| 9207 | /* 25872 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS |
| 9208 | /* 25874 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9209 | /* 25877 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9210 | /* 25883 */ GIR_RootConstrainSelectedInstOperands, |
| 9211 | /* 25884 */ // GIR_Coverage, 2540, |
| 9212 | /* 25884 */ GIR_EraseRootFromParent_Done, |
| 9213 | /* 25885 */ // Label 520: @25885 |
| 9214 | /* 25885 */ GIM_Try, /*On fail goto*//*Label 521*/ GIMT_Encode4(25946), // Rule ID 3390 // |
| 9215 | /* 25890 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 9216 | /* 25893 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9217 | /* 25897 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9218 | /* 25901 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9219 | /* 25905 */ // (xor:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VEOR:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 9220 | /* 25905 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 9221 | /* 25908 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 9222 | /* 25912 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9223 | /* 25917 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VEOR), |
| 9224 | /* 25920 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 9225 | /* 25922 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 9226 | /* 25924 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 9227 | /* 25926 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 9228 | /* 25929 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9229 | /* 25935 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9230 | /* 25941 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 9231 | /* 25944 */ GIR_RootConstrainSelectedInstOperands, |
| 9232 | /* 25945 */ // GIR_Coverage, 3390, |
| 9233 | /* 25945 */ GIR_EraseRootFromParent_Done, |
| 9234 | /* 25946 */ // Label 521: @25946 |
| 9235 | /* 25946 */ GIM_Reject, |
| 9236 | /* 25947 */ // Label 519: @25947 |
| 9237 | /* 25947 */ GIM_Reject, |
| 9238 | /* 25948 */ // Label 492: @25948 |
| 9239 | /* 25948 */ GIM_Try, /*On fail goto*//*Label 522*/ GIMT_Encode4(26065), // Rule ID 1833 // |
| 9240 | /* 25953 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 9241 | /* 25956 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s1, |
| 9242 | /* 25959 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s1, |
| 9243 | /* 25962 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 9244 | /* 25966 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 9245 | /* 25970 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 9246 | /* 25974 */ // (xor:{ *:[v16i1] } VCCR:{ *:[v16i1] }:$p1, VCCR:{ *:[v16i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v16i1] } (t2EORrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v16i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v16i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] }) |
| 9247 | /* 25974 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, |
| 9248 | /* 25977 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9249 | /* 25981 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9250 | /* 25986 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2 |
| 9251 | /* 25990 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 9252 | /* 25995 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 9253 | /* 25998 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9254 | /* 26002 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9255 | /* 26007 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1 |
| 9256 | /* 26011 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 9257 | /* 26016 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 9258 | /* 26019 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2EORrr), |
| 9259 | /* 26023 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9260 | /* 26028 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 9261 | /* 26031 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 9262 | /* 26034 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 9263 | /* 26037 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9264 | /* 26043 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9265 | /* 26049 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 9266 | /* 26051 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9267 | /* 26054 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 9268 | /* 26056 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 9269 | /* 26059 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID), |
| 9270 | /* 26064 */ // GIR_Coverage, 1833, |
| 9271 | /* 26064 */ GIR_EraseRootFromParent_Done, |
| 9272 | /* 26065 */ // Label 522: @26065 |
| 9273 | /* 26065 */ GIM_Reject, |
| 9274 | /* 26066 */ // Label 493: @26066 |
| 9275 | /* 26066 */ GIM_Try, /*On fail goto*//*Label 523*/ GIMT_Encode4(26179), |
| 9276 | /* 26071 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 9277 | /* 26074 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 9278 | /* 26077 */ GIM_Try, /*On fail goto*//*Label 524*/ GIMT_Encode4(26117), // Rule ID 2539 // |
| 9279 | /* 26082 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 9280 | /* 26085 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9281 | /* 26089 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9282 | /* 26093 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9283 | /* 26097 */ // (xor:{ *:[v16i8] } QPR:{ *:[v16i8] }:$LHS, QPR:{ *:[v16i8] }:$RHS) => (VEORq:{ *:[v16i8] } QPR:{ *:[v16i8] }:$LHS, QPR:{ *:[v16i8] }:$RHS) |
| 9284 | /* 26097 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VEORq), |
| 9285 | /* 26100 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 9286 | /* 26102 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS |
| 9287 | /* 26104 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS |
| 9288 | /* 26106 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9289 | /* 26109 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9290 | /* 26115 */ GIR_RootConstrainSelectedInstOperands, |
| 9291 | /* 26116 */ // GIR_Coverage, 2539, |
| 9292 | /* 26116 */ GIR_EraseRootFromParent_Done, |
| 9293 | /* 26117 */ // Label 524: @26117 |
| 9294 | /* 26117 */ GIM_Try, /*On fail goto*//*Label 525*/ GIMT_Encode4(26178), // Rule ID 3386 // |
| 9295 | /* 26122 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 9296 | /* 26125 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9297 | /* 26129 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9298 | /* 26133 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9299 | /* 26137 */ // (xor:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VEOR:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 9300 | /* 26137 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 9301 | /* 26140 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 9302 | /* 26144 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9303 | /* 26149 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VEOR), |
| 9304 | /* 26152 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 9305 | /* 26154 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 9306 | /* 26156 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 9307 | /* 26158 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 9308 | /* 26161 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9309 | /* 26167 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9310 | /* 26173 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 9311 | /* 26176 */ GIR_RootConstrainSelectedInstOperands, |
| 9312 | /* 26177 */ // GIR_Coverage, 3386, |
| 9313 | /* 26177 */ GIR_EraseRootFromParent_Done, |
| 9314 | /* 26178 */ // Label 525: @26178 |
| 9315 | /* 26178 */ GIM_Reject, |
| 9316 | /* 26179 */ // Label 523: @26179 |
| 9317 | /* 26179 */ GIM_Reject, |
| 9318 | /* 26180 */ // Label 494: @26180 |
| 9319 | /* 26180 */ GIM_Reject, |
| 9320 | /* 26181 */ // Label 8: @26181 |
| 9321 | /* 26181 */ GIM_Try, /*On fail goto*//*Label 526*/ GIMT_Encode4(26567), |
| 9322 | /* 26186 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, |
| 9323 | /* 26189 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(5), GIMT_Encode2(16), /*)*//*default:*//*Label 531*/ GIMT_Encode4(26566), |
| 9324 | /* 26200 */ /*GILLT_v2s64*//*Label 527*/ GIMT_Encode4(26244), GIMT_Encode4(0), GIMT_Encode4(0), |
| 9325 | /* 26212 */ /*GILLT_v4s32*//*Label 528*/ GIMT_Encode4(26302), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 9326 | /* 26228 */ /*GILLT_v8s16*//*Label 529*/ GIMT_Encode4(26405), GIMT_Encode4(0), GIMT_Encode4(0), |
| 9327 | /* 26240 */ /*GILLT_v16s8*//*Label 530*/ GIMT_Encode4(26508), |
| 9328 | /* 26244 */ // Label 527: @26244 |
| 9329 | /* 26244 */ GIM_Try, /*On fail goto*//*Label 532*/ GIMT_Encode4(26301), // Rule ID 3024 // |
| 9330 | /* 26249 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 9331 | /* 26252 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 9332 | /* 26255 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 9333 | /* 26258 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9334 | /* 26262 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9335 | /* 26266 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9336 | /* 26270 */ // (concat_vectors:{ *:[v2i64] } DPR:{ *:[v1i64] }:$Dn, DPR:{ *:[v1i64] }:$Dm) => (REG_SEQUENCE:{ *:[v2i64] } QPR:{ *:[i32] }, DPR:{ *:[v1i64] }:$Dn, dsub_0:{ *:[i32] }, DPR:{ *:[v1i64] }:$Dm, dsub_1:{ *:[i32] }) |
| 9337 | /* 26270 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 9338 | /* 26273 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 9339 | /* 26275 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dn |
| 9340 | /* 26277 */ GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/1, |
| 9341 | /* 26280 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm |
| 9342 | /* 26282 */ GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/2, |
| 9343 | /* 26285 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 9344 | /* 26290 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPRRegClassID), |
| 9345 | /* 26295 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(ARM::DPRRegClassID), |
| 9346 | /* 26300 */ // GIR_Coverage, 3024, |
| 9347 | /* 26300 */ GIR_EraseRootFromParent_Done, |
| 9348 | /* 26301 */ // Label 532: @26301 |
| 9349 | /* 26301 */ GIM_Reject, |
| 9350 | /* 26302 */ // Label 528: @26302 |
| 9351 | /* 26302 */ GIM_Try, /*On fail goto*//*Label 533*/ GIMT_Encode4(26404), |
| 9352 | /* 26307 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 9353 | /* 26310 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 9354 | /* 26313 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9355 | /* 26317 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9356 | /* 26321 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9357 | /* 26325 */ GIM_Try, /*On fail goto*//*Label 534*/ GIMT_Encode4(26364), // Rule ID 3025 // |
| 9358 | /* 26330 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 9359 | /* 26333 */ // (concat_vectors:{ *:[v4i32] } DPR:{ *:[v2i32] }:$Dn, DPR:{ *:[v2i32] }:$Dm) => (REG_SEQUENCE:{ *:[v4i32] } QPR:{ *:[i32] }, DPR:{ *:[v2i32] }:$Dn, dsub_0:{ *:[i32] }, DPR:{ *:[v2i32] }:$Dm, dsub_1:{ *:[i32] }) |
| 9360 | /* 26333 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 9361 | /* 26336 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 9362 | /* 26338 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dn |
| 9363 | /* 26340 */ GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/1, |
| 9364 | /* 26343 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm |
| 9365 | /* 26345 */ GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/2, |
| 9366 | /* 26348 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 9367 | /* 26353 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPRRegClassID), |
| 9368 | /* 26358 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(ARM::DPRRegClassID), |
| 9369 | /* 26363 */ // GIR_Coverage, 3025, |
| 9370 | /* 26363 */ GIR_EraseRootFromParent_Done, |
| 9371 | /* 26364 */ // Label 534: @26364 |
| 9372 | /* 26364 */ GIM_Try, /*On fail goto*//*Label 535*/ GIMT_Encode4(26403), // Rule ID 3028 // |
| 9373 | /* 26369 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 9374 | /* 26372 */ // (concat_vectors:{ *:[v4f32] } DPR:{ *:[v2f32] }:$Dn, DPR:{ *:[v2f32] }:$Dm) => (REG_SEQUENCE:{ *:[v4f32] } QPR:{ *:[i32] }, DPR:{ *:[v2f32] }:$Dn, dsub_0:{ *:[i32] }, DPR:{ *:[v2f32] }:$Dm, dsub_1:{ *:[i32] }) |
| 9375 | /* 26372 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 9376 | /* 26375 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 9377 | /* 26377 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dn |
| 9378 | /* 26379 */ GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/1, |
| 9379 | /* 26382 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm |
| 9380 | /* 26384 */ GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/2, |
| 9381 | /* 26387 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 9382 | /* 26392 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPRRegClassID), |
| 9383 | /* 26397 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(ARM::DPRRegClassID), |
| 9384 | /* 26402 */ // GIR_Coverage, 3028, |
| 9385 | /* 26402 */ GIR_EraseRootFromParent_Done, |
| 9386 | /* 26403 */ // Label 535: @26403 |
| 9387 | /* 26403 */ GIM_Reject, |
| 9388 | /* 26404 */ // Label 533: @26404 |
| 9389 | /* 26404 */ GIM_Reject, |
| 9390 | /* 26405 */ // Label 529: @26405 |
| 9391 | /* 26405 */ GIM_Try, /*On fail goto*//*Label 536*/ GIMT_Encode4(26507), |
| 9392 | /* 26410 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 9393 | /* 26413 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 9394 | /* 26416 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9395 | /* 26420 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9396 | /* 26424 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9397 | /* 26428 */ GIM_Try, /*On fail goto*//*Label 537*/ GIMT_Encode4(26467), // Rule ID 3026 // |
| 9398 | /* 26433 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 9399 | /* 26436 */ // (concat_vectors:{ *:[v8i16] } DPR:{ *:[v4i16] }:$Dn, DPR:{ *:[v4i16] }:$Dm) => (REG_SEQUENCE:{ *:[v8i16] } QPR:{ *:[i32] }, DPR:{ *:[v4i16] }:$Dn, dsub_0:{ *:[i32] }, DPR:{ *:[v4i16] }:$Dm, dsub_1:{ *:[i32] }) |
| 9400 | /* 26436 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 9401 | /* 26439 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 9402 | /* 26441 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dn |
| 9403 | /* 26443 */ GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/1, |
| 9404 | /* 26446 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm |
| 9405 | /* 26448 */ GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/2, |
| 9406 | /* 26451 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 9407 | /* 26456 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPRRegClassID), |
| 9408 | /* 26461 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(ARM::DPRRegClassID), |
| 9409 | /* 26466 */ // GIR_Coverage, 3026, |
| 9410 | /* 26466 */ GIR_EraseRootFromParent_Done, |
| 9411 | /* 26467 */ // Label 537: @26467 |
| 9412 | /* 26467 */ GIM_Try, /*On fail goto*//*Label 538*/ GIMT_Encode4(26506), // Rule ID 3029 // |
| 9413 | /* 26472 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 9414 | /* 26475 */ // (concat_vectors:{ *:[v8f16] } DPR:{ *:[v4f16] }:$Dn, DPR:{ *:[v4f16] }:$Dm) => (REG_SEQUENCE:{ *:[v8f16] } QPR:{ *:[i32] }, DPR:{ *:[v4f16] }:$Dn, dsub_0:{ *:[i32] }, DPR:{ *:[v4f16] }:$Dm, dsub_1:{ *:[i32] }) |
| 9415 | /* 26475 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 9416 | /* 26478 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 9417 | /* 26480 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dn |
| 9418 | /* 26482 */ GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/1, |
| 9419 | /* 26485 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm |
| 9420 | /* 26487 */ GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/2, |
| 9421 | /* 26490 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 9422 | /* 26495 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPRRegClassID), |
| 9423 | /* 26500 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(ARM::DPRRegClassID), |
| 9424 | /* 26505 */ // GIR_Coverage, 3029, |
| 9425 | /* 26505 */ GIR_EraseRootFromParent_Done, |
| 9426 | /* 26506 */ // Label 538: @26506 |
| 9427 | /* 26506 */ GIM_Reject, |
| 9428 | /* 26507 */ // Label 536: @26507 |
| 9429 | /* 26507 */ GIM_Reject, |
| 9430 | /* 26508 */ // Label 530: @26508 |
| 9431 | /* 26508 */ GIM_Try, /*On fail goto*//*Label 539*/ GIMT_Encode4(26565), // Rule ID 3027 // |
| 9432 | /* 26513 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 9433 | /* 26516 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 9434 | /* 26519 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 9435 | /* 26522 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9436 | /* 26526 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9437 | /* 26530 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9438 | /* 26534 */ // (concat_vectors:{ *:[v16i8] } DPR:{ *:[v8i8] }:$Dn, DPR:{ *:[v8i8] }:$Dm) => (REG_SEQUENCE:{ *:[v16i8] } QPR:{ *:[i32] }, DPR:{ *:[v8i8] }:$Dn, dsub_0:{ *:[i32] }, DPR:{ *:[v8i8] }:$Dm, dsub_1:{ *:[i32] }) |
| 9439 | /* 26534 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 9440 | /* 26537 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 9441 | /* 26539 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dn |
| 9442 | /* 26541 */ GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/1, |
| 9443 | /* 26544 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm |
| 9444 | /* 26546 */ GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/2, |
| 9445 | /* 26549 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 9446 | /* 26554 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPRRegClassID), |
| 9447 | /* 26559 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(ARM::DPRRegClassID), |
| 9448 | /* 26564 */ // GIR_Coverage, 3027, |
| 9449 | /* 26564 */ GIR_EraseRootFromParent_Done, |
| 9450 | /* 26565 */ // Label 539: @26565 |
| 9451 | /* 26565 */ GIM_Reject, |
| 9452 | /* 26566 */ // Label 531: @26566 |
| 9453 | /* 26566 */ GIM_Reject, |
| 9454 | /* 26567 */ // Label 526: @26567 |
| 9455 | /* 26567 */ GIM_Reject, |
| 9456 | /* 26568 */ // Label 9: @26568 |
| 9457 | /* 26568 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(16), /*)*//*default:*//*Label 549*/ GIMT_Encode4(35579), |
| 9458 | /* 26579 */ /*GILLT_s32*//*Label 540*/ GIMT_Encode4(26639), |
| 9459 | /* 26583 */ /*GILLT_s64*//*Label 541*/ GIMT_Encode4(26787), GIMT_Encode4(0), |
| 9460 | /* 26591 */ /*GILLT_v2s32*//*Label 542*/ GIMT_Encode4(27542), |
| 9461 | /* 26595 */ /*GILLT_v2s64*//*Label 543*/ GIMT_Encode4(28297), GIMT_Encode4(0), |
| 9462 | /* 26603 */ /*GILLT_v4s16*//*Label 544*/ GIMT_Encode4(30016), |
| 9463 | /* 26607 */ /*GILLT_v4s32*//*Label 545*/ GIMT_Encode4(30771), GIMT_Encode4(0), GIMT_Encode4(0), |
| 9464 | /* 26619 */ /*GILLT_v8s8*//*Label 546*/ GIMT_Encode4(32490), |
| 9465 | /* 26623 */ /*GILLT_v8s16*//*Label 547*/ GIMT_Encode4(32905), GIMT_Encode4(0), GIMT_Encode4(0), |
| 9466 | /* 26635 */ /*GILLT_v16s8*//*Label 548*/ GIMT_Encode4(34624), |
| 9467 | /* 26639 */ // Label 540: @26639 |
| 9468 | /* 26639 */ GIM_Try, /*On fail goto*//*Label 550*/ GIMT_Encode4(26786), |
| 9469 | /* 26644 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 9470 | /* 26647 */ GIM_Try, /*On fail goto*//*Label 551*/ GIMT_Encode4(26681), // Rule ID 692 // |
| 9471 | /* 26652 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRegs), |
| 9472 | /* 26655 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 9473 | /* 26659 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 9474 | /* 26663 */ // (bitconvert:{ *:[i32] } SPR:{ *:[f32] }:$Sn) => (VMOVRS:{ *:[i32] } SPR:{ *:[f32] }:$Sn) |
| 9475 | /* 26663 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVRS), |
| 9476 | /* 26666 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt] |
| 9477 | /* 26668 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn |
| 9478 | /* 26670 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9479 | /* 26673 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9480 | /* 26679 */ GIR_RootConstrainSelectedInstOperands, |
| 9481 | /* 26680 */ // GIR_Coverage, 692, |
| 9482 | /* 26680 */ GIR_EraseRootFromParent_Done, |
| 9483 | /* 26681 */ // Label 551: @26681 |
| 9484 | /* 26681 */ GIM_Try, /*On fail goto*//*Label 552*/ GIMT_Encode4(26715), // Rule ID 693 // |
| 9485 | /* 26686 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRegs_UseVMOVSR), |
| 9486 | /* 26689 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 9487 | /* 26693 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 9488 | /* 26697 */ // (bitconvert:{ *:[f32] } GPR:{ *:[i32] }:$Rt) => (VMOVSR:{ *:[f32] } GPR:{ *:[i32] }:$Rt) |
| 9489 | /* 26697 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVSR), |
| 9490 | /* 26700 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sn] |
| 9491 | /* 26702 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rt |
| 9492 | /* 26704 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9493 | /* 26707 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9494 | /* 26713 */ GIR_RootConstrainSelectedInstOperands, |
| 9495 | /* 26714 */ // GIR_Coverage, 693, |
| 9496 | /* 26714 */ GIR_EraseRootFromParent_Done, |
| 9497 | /* 26715 */ // Label 552: @26715 |
| 9498 | /* 26715 */ GIM_Try, /*On fail goto*//*Label 553*/ GIMT_Encode4(26785), // Rule ID 2718 // |
| 9499 | /* 26720 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseVMOVSR_HasNEON), |
| 9500 | /* 26723 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 9501 | /* 26727 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 9502 | /* 26731 */ // (bitconvert:{ *:[f32] } GPR:{ *:[i32] }:$a) => (EXTRACT_SUBREG:{ *:[f32] } (VMOVDRR:{ *:[f64] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$a), ssub_0:{ *:[i32] }) |
| 9503 | /* 26731 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 9504 | /* 26734 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VMOVDRR), |
| 9505 | /* 26738 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9506 | /* 26743 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 9507 | /* 26747 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 9508 | /* 26751 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 9509 | /* 26754 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9510 | /* 26760 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 9511 | /* 26762 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9512 | /* 26765 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 9513 | /* 26767 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0), |
| 9514 | /* 26774 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 9515 | /* 26779 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 9516 | /* 26784 */ // GIR_Coverage, 2718, |
| 9517 | /* 26784 */ GIR_EraseRootFromParent_Done, |
| 9518 | /* 26785 */ // Label 553: @26785 |
| 9519 | /* 26785 */ GIM_Reject, |
| 9520 | /* 26786 */ // Label 550: @26786 |
| 9521 | /* 26786 */ GIM_Reject, |
| 9522 | /* 26787 */ // Label 541: @26787 |
| 9523 | /* 26787 */ GIM_Try, /*On fail goto*//*Label 554*/ GIMT_Encode4(26819), // Rule ID 2720 // |
| 9524 | /* 26792 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 9525 | /* 26795 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 9526 | /* 26798 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9527 | /* 26802 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9528 | /* 26806 */ // (bitconvert:{ *:[f64] } DPR:{ *:[v1i64] }:$src) => DPR:{ *:[f64] }:$src |
| 9529 | /* 26806 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9530 | /* 26809 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 9531 | /* 26811 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 9532 | /* 26813 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 9533 | /* 26818 */ // GIR_Coverage, 2720, |
| 9534 | /* 26818 */ GIR_EraseRootFromParent_Done, |
| 9535 | /* 26819 */ // Label 554: @26819 |
| 9536 | /* 26819 */ GIM_Try, /*On fail goto*//*Label 555*/ GIMT_Encode4(26851), // Rule ID 2721 // |
| 9537 | /* 26824 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 9538 | /* 26827 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 9539 | /* 26830 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9540 | /* 26834 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9541 | /* 26838 */ // (bitconvert:{ *:[v1i64] } DPR:{ *:[f64] }:$src) => DPR:{ *:[v1i64] }:$src |
| 9542 | /* 26838 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9543 | /* 26841 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 9544 | /* 26843 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 9545 | /* 26845 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 9546 | /* 26850 */ // GIR_Coverage, 2721, |
| 9547 | /* 26850 */ GIR_EraseRootFromParent_Done, |
| 9548 | /* 26851 */ // Label 555: @26851 |
| 9549 | /* 26851 */ GIM_Try, /*On fail goto*//*Label 556*/ GIMT_Encode4(26883), // Rule ID 2732 // |
| 9550 | /* 26856 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 9551 | /* 26859 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 9552 | /* 26862 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9553 | /* 26866 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9554 | /* 26870 */ // (bitconvert:{ *:[f64] } DPR:{ *:[v2f32] }:$src) => DPR:{ *:[f64] }:$src |
| 9555 | /* 26870 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9556 | /* 26873 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 9557 | /* 26875 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 9558 | /* 26877 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 9559 | /* 26882 */ // GIR_Coverage, 2732, |
| 9560 | /* 26882 */ GIR_EraseRootFromParent_Done, |
| 9561 | /* 26883 */ // Label 556: @26883 |
| 9562 | /* 26883 */ GIM_Try, /*On fail goto*//*Label 557*/ GIMT_Encode4(26915), // Rule ID 2733 // |
| 9563 | /* 26888 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 9564 | /* 26891 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 9565 | /* 26894 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9566 | /* 26898 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9567 | /* 26902 */ // (bitconvert:{ *:[f64] } DPR:{ *:[v2i32] }:$src) => DPR:{ *:[f64] }:$src |
| 9568 | /* 26902 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9569 | /* 26905 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 9570 | /* 26907 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 9571 | /* 26909 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 9572 | /* 26914 */ // GIR_Coverage, 2733, |
| 9573 | /* 26914 */ GIR_EraseRootFromParent_Done, |
| 9574 | /* 26915 */ // Label 557: @26915 |
| 9575 | /* 26915 */ GIM_Try, /*On fail goto*//*Label 558*/ GIMT_Encode4(26947), // Rule ID 2734 // |
| 9576 | /* 26920 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 9577 | /* 26923 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 9578 | /* 26926 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9579 | /* 26930 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9580 | /* 26934 */ // (bitconvert:{ *:[f64] } DPR:{ *:[v4f16] }:$src) => DPR:{ *:[f64] }:$src |
| 9581 | /* 26934 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9582 | /* 26937 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 9583 | /* 26939 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 9584 | /* 26941 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 9585 | /* 26946 */ // GIR_Coverage, 2734, |
| 9586 | /* 26946 */ GIR_EraseRootFromParent_Done, |
| 9587 | /* 26947 */ // Label 558: @26947 |
| 9588 | /* 26947 */ GIM_Try, /*On fail goto*//*Label 559*/ GIMT_Encode4(26979), // Rule ID 2735 // |
| 9589 | /* 26952 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 9590 | /* 26955 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 9591 | /* 26958 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9592 | /* 26962 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9593 | /* 26966 */ // (bitconvert:{ *:[f64] } DPR:{ *:[v4i16] }:$src) => DPR:{ *:[f64] }:$src |
| 9594 | /* 26966 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9595 | /* 26969 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 9596 | /* 26971 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 9597 | /* 26973 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 9598 | /* 26978 */ // GIR_Coverage, 2735, |
| 9599 | /* 26978 */ GIR_EraseRootFromParent_Done, |
| 9600 | /* 26979 */ // Label 559: @26979 |
| 9601 | /* 26979 */ GIM_Try, /*On fail goto*//*Label 560*/ GIMT_Encode4(27011), // Rule ID 2736 // |
| 9602 | /* 26984 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 9603 | /* 26987 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 9604 | /* 26990 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9605 | /* 26994 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9606 | /* 26998 */ // (bitconvert:{ *:[f64] } DPR:{ *:[v8i8] }:$src) => DPR:{ *:[f64] }:$src |
| 9607 | /* 26998 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9608 | /* 27001 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 9609 | /* 27003 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 9610 | /* 27005 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 9611 | /* 27010 */ // GIR_Coverage, 2736, |
| 9612 | /* 27010 */ GIR_EraseRootFromParent_Done, |
| 9613 | /* 27011 */ // Label 560: @27011 |
| 9614 | /* 27011 */ GIM_Try, /*On fail goto*//*Label 561*/ GIMT_Encode4(27043), // Rule ID 2737 // |
| 9615 | /* 27016 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 9616 | /* 27019 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 9617 | /* 27022 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9618 | /* 27026 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9619 | /* 27030 */ // (bitconvert:{ *:[v1i64] } DPR:{ *:[v2f32] }:$src) => DPR:{ *:[v1i64] }:$src |
| 9620 | /* 27030 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9621 | /* 27033 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 9622 | /* 27035 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 9623 | /* 27037 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 9624 | /* 27042 */ // GIR_Coverage, 2737, |
| 9625 | /* 27042 */ GIR_EraseRootFromParent_Done, |
| 9626 | /* 27043 */ // Label 561: @27043 |
| 9627 | /* 27043 */ GIM_Try, /*On fail goto*//*Label 562*/ GIMT_Encode4(27075), // Rule ID 2738 // |
| 9628 | /* 27048 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 9629 | /* 27051 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 9630 | /* 27054 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9631 | /* 27058 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9632 | /* 27062 */ // (bitconvert:{ *:[v1i64] } DPR:{ *:[v2i32] }:$src) => DPR:{ *:[v1i64] }:$src |
| 9633 | /* 27062 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9634 | /* 27065 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 9635 | /* 27067 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 9636 | /* 27069 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 9637 | /* 27074 */ // GIR_Coverage, 2738, |
| 9638 | /* 27074 */ GIR_EraseRootFromParent_Done, |
| 9639 | /* 27075 */ // Label 562: @27075 |
| 9640 | /* 27075 */ GIM_Try, /*On fail goto*//*Label 563*/ GIMT_Encode4(27107), // Rule ID 2739 // |
| 9641 | /* 27080 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 9642 | /* 27083 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 9643 | /* 27086 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9644 | /* 27090 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9645 | /* 27094 */ // (bitconvert:{ *:[v1i64] } DPR:{ *:[v4f16] }:$src) => DPR:{ *:[v1i64] }:$src |
| 9646 | /* 27094 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9647 | /* 27097 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 9648 | /* 27099 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 9649 | /* 27101 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 9650 | /* 27106 */ // GIR_Coverage, 2739, |
| 9651 | /* 27106 */ GIR_EraseRootFromParent_Done, |
| 9652 | /* 27107 */ // Label 563: @27107 |
| 9653 | /* 27107 */ GIM_Try, /*On fail goto*//*Label 564*/ GIMT_Encode4(27139), // Rule ID 2740 // |
| 9654 | /* 27112 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 9655 | /* 27115 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 9656 | /* 27118 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9657 | /* 27122 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9658 | /* 27126 */ // (bitconvert:{ *:[v1i64] } DPR:{ *:[v4i16] }:$src) => DPR:{ *:[v1i64] }:$src |
| 9659 | /* 27126 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9660 | /* 27129 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 9661 | /* 27131 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 9662 | /* 27133 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 9663 | /* 27138 */ // GIR_Coverage, 2740, |
| 9664 | /* 27138 */ GIR_EraseRootFromParent_Done, |
| 9665 | /* 27139 */ // Label 564: @27139 |
| 9666 | /* 27139 */ GIM_Try, /*On fail goto*//*Label 565*/ GIMT_Encode4(27171), // Rule ID 2741 // |
| 9667 | /* 27144 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 9668 | /* 27147 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 9669 | /* 27150 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9670 | /* 27154 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9671 | /* 27158 */ // (bitconvert:{ *:[v1i64] } DPR:{ *:[v8i8] }:$src) => DPR:{ *:[v1i64] }:$src |
| 9672 | /* 27158 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9673 | /* 27161 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 9674 | /* 27163 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 9675 | /* 27165 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 9676 | /* 27170 */ // GIR_Coverage, 2741, |
| 9677 | /* 27170 */ GIR_EraseRootFromParent_Done, |
| 9678 | /* 27171 */ // Label 565: @27171 |
| 9679 | /* 27171 */ GIM_Try, /*On fail goto*//*Label 566*/ GIMT_Encode4(27208), // Rule ID 2804 // |
| 9680 | /* 27176 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 9681 | /* 27179 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 9682 | /* 27182 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9683 | /* 27186 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9684 | /* 27190 */ // (bitconvert:{ *:[f64] } DPR:{ *:[v2f32] }:$src) => (VREV64d32:{ *:[f64] } DPR:{ *:[v2f32] }:$src) |
| 9685 | /* 27190 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d32), |
| 9686 | /* 27193 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 9687 | /* 27195 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 9688 | /* 27197 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9689 | /* 27200 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9690 | /* 27206 */ GIR_RootConstrainSelectedInstOperands, |
| 9691 | /* 27207 */ // GIR_Coverage, 2804, |
| 9692 | /* 27207 */ GIR_EraseRootFromParent_Done, |
| 9693 | /* 27208 */ // Label 566: @27208 |
| 9694 | /* 27208 */ GIM_Try, /*On fail goto*//*Label 567*/ GIMT_Encode4(27245), // Rule ID 2805 // |
| 9695 | /* 27213 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 9696 | /* 27216 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 9697 | /* 27219 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9698 | /* 27223 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9699 | /* 27227 */ // (bitconvert:{ *:[f64] } DPR:{ *:[v2i32] }:$src) => (VREV64d32:{ *:[f64] } DPR:{ *:[v2i32] }:$src) |
| 9700 | /* 27227 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d32), |
| 9701 | /* 27230 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 9702 | /* 27232 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 9703 | /* 27234 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9704 | /* 27237 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9705 | /* 27243 */ GIR_RootConstrainSelectedInstOperands, |
| 9706 | /* 27244 */ // GIR_Coverage, 2805, |
| 9707 | /* 27244 */ GIR_EraseRootFromParent_Done, |
| 9708 | /* 27245 */ // Label 567: @27245 |
| 9709 | /* 27245 */ GIM_Try, /*On fail goto*//*Label 568*/ GIMT_Encode4(27282), // Rule ID 2806 // |
| 9710 | /* 27250 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 9711 | /* 27253 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 9712 | /* 27256 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9713 | /* 27260 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9714 | /* 27264 */ // (bitconvert:{ *:[f64] } DPR:{ *:[v4f16] }:$src) => (VREV64d16:{ *:[f64] } DPR:{ *:[v4f16] }:$src) |
| 9715 | /* 27264 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d16), |
| 9716 | /* 27267 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 9717 | /* 27269 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 9718 | /* 27271 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9719 | /* 27274 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9720 | /* 27280 */ GIR_RootConstrainSelectedInstOperands, |
| 9721 | /* 27281 */ // GIR_Coverage, 2806, |
| 9722 | /* 27281 */ GIR_EraseRootFromParent_Done, |
| 9723 | /* 27282 */ // Label 568: @27282 |
| 9724 | /* 27282 */ GIM_Try, /*On fail goto*//*Label 569*/ GIMT_Encode4(27319), // Rule ID 2807 // |
| 9725 | /* 27287 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 9726 | /* 27290 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 9727 | /* 27293 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9728 | /* 27297 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9729 | /* 27301 */ // (bitconvert:{ *:[f64] } DPR:{ *:[v4i16] }:$src) => (VREV64d16:{ *:[f64] } DPR:{ *:[v4i16] }:$src) |
| 9730 | /* 27301 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d16), |
| 9731 | /* 27304 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 9732 | /* 27306 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 9733 | /* 27308 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9734 | /* 27311 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9735 | /* 27317 */ GIR_RootConstrainSelectedInstOperands, |
| 9736 | /* 27318 */ // GIR_Coverage, 2807, |
| 9737 | /* 27318 */ GIR_EraseRootFromParent_Done, |
| 9738 | /* 27319 */ // Label 569: @27319 |
| 9739 | /* 27319 */ GIM_Try, /*On fail goto*//*Label 570*/ GIMT_Encode4(27356), // Rule ID 2808 // |
| 9740 | /* 27324 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 9741 | /* 27327 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 9742 | /* 27330 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9743 | /* 27334 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9744 | /* 27338 */ // (bitconvert:{ *:[f64] } DPR:{ *:[v8i8] }:$src) => (VREV64d8:{ *:[f64] } DPR:{ *:[v8i8] }:$src) |
| 9745 | /* 27338 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d8), |
| 9746 | /* 27341 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 9747 | /* 27343 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 9748 | /* 27345 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9749 | /* 27348 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9750 | /* 27354 */ GIR_RootConstrainSelectedInstOperands, |
| 9751 | /* 27355 */ // GIR_Coverage, 2808, |
| 9752 | /* 27355 */ GIR_EraseRootFromParent_Done, |
| 9753 | /* 27356 */ // Label 570: @27356 |
| 9754 | /* 27356 */ GIM_Try, /*On fail goto*//*Label 571*/ GIMT_Encode4(27393), // Rule ID 2809 // |
| 9755 | /* 27361 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 9756 | /* 27364 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 9757 | /* 27367 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9758 | /* 27371 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9759 | /* 27375 */ // (bitconvert:{ *:[v1i64] } DPR:{ *:[v2f32] }:$src) => (VREV64d32:{ *:[v1i64] } DPR:{ *:[v2f32] }:$src) |
| 9760 | /* 27375 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d32), |
| 9761 | /* 27378 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 9762 | /* 27380 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 9763 | /* 27382 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9764 | /* 27385 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9765 | /* 27391 */ GIR_RootConstrainSelectedInstOperands, |
| 9766 | /* 27392 */ // GIR_Coverage, 2809, |
| 9767 | /* 27392 */ GIR_EraseRootFromParent_Done, |
| 9768 | /* 27393 */ // Label 571: @27393 |
| 9769 | /* 27393 */ GIM_Try, /*On fail goto*//*Label 572*/ GIMT_Encode4(27430), // Rule ID 2810 // |
| 9770 | /* 27398 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 9771 | /* 27401 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 9772 | /* 27404 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9773 | /* 27408 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9774 | /* 27412 */ // (bitconvert:{ *:[v1i64] } DPR:{ *:[v2i32] }:$src) => (VREV64d32:{ *:[v1i64] } DPR:{ *:[v2i32] }:$src) |
| 9775 | /* 27412 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d32), |
| 9776 | /* 27415 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 9777 | /* 27417 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 9778 | /* 27419 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9779 | /* 27422 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9780 | /* 27428 */ GIR_RootConstrainSelectedInstOperands, |
| 9781 | /* 27429 */ // GIR_Coverage, 2810, |
| 9782 | /* 27429 */ GIR_EraseRootFromParent_Done, |
| 9783 | /* 27430 */ // Label 572: @27430 |
| 9784 | /* 27430 */ GIM_Try, /*On fail goto*//*Label 573*/ GIMT_Encode4(27467), // Rule ID 2811 // |
| 9785 | /* 27435 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 9786 | /* 27438 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 9787 | /* 27441 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9788 | /* 27445 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9789 | /* 27449 */ // (bitconvert:{ *:[v1i64] } DPR:{ *:[v4f16] }:$src) => (VREV64d16:{ *:[v1i64] } DPR:{ *:[v4f16] }:$src) |
| 9790 | /* 27449 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d16), |
| 9791 | /* 27452 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 9792 | /* 27454 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 9793 | /* 27456 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9794 | /* 27459 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9795 | /* 27465 */ GIR_RootConstrainSelectedInstOperands, |
| 9796 | /* 27466 */ // GIR_Coverage, 2811, |
| 9797 | /* 27466 */ GIR_EraseRootFromParent_Done, |
| 9798 | /* 27467 */ // Label 573: @27467 |
| 9799 | /* 27467 */ GIM_Try, /*On fail goto*//*Label 574*/ GIMT_Encode4(27504), // Rule ID 2812 // |
| 9800 | /* 27472 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 9801 | /* 27475 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 9802 | /* 27478 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9803 | /* 27482 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9804 | /* 27486 */ // (bitconvert:{ *:[v1i64] } DPR:{ *:[v4i16] }:$src) => (VREV64d16:{ *:[v1i64] } DPR:{ *:[v4i16] }:$src) |
| 9805 | /* 27486 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d16), |
| 9806 | /* 27489 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 9807 | /* 27491 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 9808 | /* 27493 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9809 | /* 27496 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9810 | /* 27502 */ GIR_RootConstrainSelectedInstOperands, |
| 9811 | /* 27503 */ // GIR_Coverage, 2812, |
| 9812 | /* 27503 */ GIR_EraseRootFromParent_Done, |
| 9813 | /* 27504 */ // Label 574: @27504 |
| 9814 | /* 27504 */ GIM_Try, /*On fail goto*//*Label 575*/ GIMT_Encode4(27541), // Rule ID 2813 // |
| 9815 | /* 27509 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 9816 | /* 27512 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 9817 | /* 27515 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9818 | /* 27519 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9819 | /* 27523 */ // (bitconvert:{ *:[v1i64] } DPR:{ *:[v8i8] }:$src) => (VREV64d8:{ *:[v1i64] } DPR:{ *:[v8i8] }:$src) |
| 9820 | /* 27523 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d8), |
| 9821 | /* 27526 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 9822 | /* 27528 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 9823 | /* 27530 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9824 | /* 27533 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9825 | /* 27539 */ GIR_RootConstrainSelectedInstOperands, |
| 9826 | /* 27540 */ // GIR_Coverage, 2813, |
| 9827 | /* 27540 */ GIR_EraseRootFromParent_Done, |
| 9828 | /* 27541 */ // Label 575: @27541 |
| 9829 | /* 27541 */ GIM_Reject, |
| 9830 | /* 27542 */ // Label 542: @27542 |
| 9831 | /* 27542 */ GIM_Try, /*On fail goto*//*Label 576*/ GIMT_Encode4(27574), // Rule ID 2722 // |
| 9832 | /* 27547 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 9833 | /* 27550 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 9834 | /* 27553 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9835 | /* 27557 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9836 | /* 27561 */ // (bitconvert:{ *:[v2f32] } DPR:{ *:[v2i32] }:$src) => DPR:{ *:[v2f32] }:$src |
| 9837 | /* 27561 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9838 | /* 27564 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 9839 | /* 27566 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 9840 | /* 27568 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 9841 | /* 27573 */ // GIR_Coverage, 2722, |
| 9842 | /* 27573 */ GIR_EraseRootFromParent_Done, |
| 9843 | /* 27574 */ // Label 576: @27574 |
| 9844 | /* 27574 */ GIM_Try, /*On fail goto*//*Label 577*/ GIMT_Encode4(27606), // Rule ID 2723 // |
| 9845 | /* 27579 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 9846 | /* 27582 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 9847 | /* 27585 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9848 | /* 27589 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9849 | /* 27593 */ // (bitconvert:{ *:[v2i32] } DPR:{ *:[v2f32] }:$src) => DPR:{ *:[v2i32] }:$src |
| 9850 | /* 27593 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9851 | /* 27596 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 9852 | /* 27598 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 9853 | /* 27600 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 9854 | /* 27605 */ // GIR_Coverage, 2723, |
| 9855 | /* 27605 */ GIR_EraseRootFromParent_Done, |
| 9856 | /* 27606 */ // Label 577: @27606 |
| 9857 | /* 27606 */ GIM_Try, /*On fail goto*//*Label 578*/ GIMT_Encode4(27638), // Rule ID 2742 // |
| 9858 | /* 27611 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 9859 | /* 27614 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 9860 | /* 27617 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9861 | /* 27621 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9862 | /* 27625 */ // (bitconvert:{ *:[v2f32] } DPR:{ *:[f64] }:$src) => DPR:{ *:[v2f32] }:$src |
| 9863 | /* 27625 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9864 | /* 27628 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 9865 | /* 27630 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 9866 | /* 27632 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 9867 | /* 27637 */ // GIR_Coverage, 2742, |
| 9868 | /* 27637 */ GIR_EraseRootFromParent_Done, |
| 9869 | /* 27638 */ // Label 578: @27638 |
| 9870 | /* 27638 */ GIM_Try, /*On fail goto*//*Label 579*/ GIMT_Encode4(27670), // Rule ID 2743 // |
| 9871 | /* 27643 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 9872 | /* 27646 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 9873 | /* 27649 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9874 | /* 27653 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9875 | /* 27657 */ // (bitconvert:{ *:[v2f32] } DPR:{ *:[v1i64] }:$src) => DPR:{ *:[v2f32] }:$src |
| 9876 | /* 27657 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9877 | /* 27660 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 9878 | /* 27662 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 9879 | /* 27664 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 9880 | /* 27669 */ // GIR_Coverage, 2743, |
| 9881 | /* 27669 */ GIR_EraseRootFromParent_Done, |
| 9882 | /* 27670 */ // Label 579: @27670 |
| 9883 | /* 27670 */ GIM_Try, /*On fail goto*//*Label 580*/ GIMT_Encode4(27702), // Rule ID 2744 // |
| 9884 | /* 27675 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 9885 | /* 27678 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 9886 | /* 27681 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9887 | /* 27685 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9888 | /* 27689 */ // (bitconvert:{ *:[v2f32] } DPR:{ *:[v4f16] }:$src) => DPR:{ *:[v2f32] }:$src |
| 9889 | /* 27689 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9890 | /* 27692 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 9891 | /* 27694 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 9892 | /* 27696 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 9893 | /* 27701 */ // GIR_Coverage, 2744, |
| 9894 | /* 27701 */ GIR_EraseRootFromParent_Done, |
| 9895 | /* 27702 */ // Label 580: @27702 |
| 9896 | /* 27702 */ GIM_Try, /*On fail goto*//*Label 581*/ GIMT_Encode4(27734), // Rule ID 2745 // |
| 9897 | /* 27707 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 9898 | /* 27710 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 9899 | /* 27713 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9900 | /* 27717 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9901 | /* 27721 */ // (bitconvert:{ *:[v2f32] } DPR:{ *:[v4i16] }:$src) => DPR:{ *:[v2f32] }:$src |
| 9902 | /* 27721 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9903 | /* 27724 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 9904 | /* 27726 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 9905 | /* 27728 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 9906 | /* 27733 */ // GIR_Coverage, 2745, |
| 9907 | /* 27733 */ GIR_EraseRootFromParent_Done, |
| 9908 | /* 27734 */ // Label 581: @27734 |
| 9909 | /* 27734 */ GIM_Try, /*On fail goto*//*Label 582*/ GIMT_Encode4(27766), // Rule ID 2746 // |
| 9910 | /* 27739 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 9911 | /* 27742 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 9912 | /* 27745 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9913 | /* 27749 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9914 | /* 27753 */ // (bitconvert:{ *:[v2f32] } DPR:{ *:[v8i8] }:$src) => DPR:{ *:[v2f32] }:$src |
| 9915 | /* 27753 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9916 | /* 27756 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 9917 | /* 27758 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 9918 | /* 27760 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 9919 | /* 27765 */ // GIR_Coverage, 2746, |
| 9920 | /* 27765 */ GIR_EraseRootFromParent_Done, |
| 9921 | /* 27766 */ // Label 582: @27766 |
| 9922 | /* 27766 */ GIM_Try, /*On fail goto*//*Label 583*/ GIMT_Encode4(27798), // Rule ID 2747 // |
| 9923 | /* 27771 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 9924 | /* 27774 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 9925 | /* 27777 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9926 | /* 27781 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9927 | /* 27785 */ // (bitconvert:{ *:[v2i32] } DPR:{ *:[f64] }:$src) => DPR:{ *:[v2i32] }:$src |
| 9928 | /* 27785 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9929 | /* 27788 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 9930 | /* 27790 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 9931 | /* 27792 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 9932 | /* 27797 */ // GIR_Coverage, 2747, |
| 9933 | /* 27797 */ GIR_EraseRootFromParent_Done, |
| 9934 | /* 27798 */ // Label 583: @27798 |
| 9935 | /* 27798 */ GIM_Try, /*On fail goto*//*Label 584*/ GIMT_Encode4(27830), // Rule ID 2748 // |
| 9936 | /* 27803 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 9937 | /* 27806 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 9938 | /* 27809 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9939 | /* 27813 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9940 | /* 27817 */ // (bitconvert:{ *:[v2i32] } DPR:{ *:[v1i64] }:$src) => DPR:{ *:[v2i32] }:$src |
| 9941 | /* 27817 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9942 | /* 27820 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 9943 | /* 27822 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 9944 | /* 27824 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 9945 | /* 27829 */ // GIR_Coverage, 2748, |
| 9946 | /* 27829 */ GIR_EraseRootFromParent_Done, |
| 9947 | /* 27830 */ // Label 584: @27830 |
| 9948 | /* 27830 */ GIM_Try, /*On fail goto*//*Label 585*/ GIMT_Encode4(27862), // Rule ID 2749 // |
| 9949 | /* 27835 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 9950 | /* 27838 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 9951 | /* 27841 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9952 | /* 27845 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9953 | /* 27849 */ // (bitconvert:{ *:[v2i32] } DPR:{ *:[v4f16] }:$src) => DPR:{ *:[v2i32] }:$src |
| 9954 | /* 27849 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9955 | /* 27852 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 9956 | /* 27854 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 9957 | /* 27856 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 9958 | /* 27861 */ // GIR_Coverage, 2749, |
| 9959 | /* 27861 */ GIR_EraseRootFromParent_Done, |
| 9960 | /* 27862 */ // Label 585: @27862 |
| 9961 | /* 27862 */ GIM_Try, /*On fail goto*//*Label 586*/ GIMT_Encode4(27894), // Rule ID 2750 // |
| 9962 | /* 27867 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 9963 | /* 27870 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 9964 | /* 27873 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9965 | /* 27877 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9966 | /* 27881 */ // (bitconvert:{ *:[v2i32] } DPR:{ *:[v4i16] }:$src) => DPR:{ *:[v2i32] }:$src |
| 9967 | /* 27881 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9968 | /* 27884 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 9969 | /* 27886 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 9970 | /* 27888 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 9971 | /* 27893 */ // GIR_Coverage, 2750, |
| 9972 | /* 27893 */ GIR_EraseRootFromParent_Done, |
| 9973 | /* 27894 */ // Label 586: @27894 |
| 9974 | /* 27894 */ GIM_Try, /*On fail goto*//*Label 587*/ GIMT_Encode4(27926), // Rule ID 2751 // |
| 9975 | /* 27899 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 9976 | /* 27902 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 9977 | /* 27905 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9978 | /* 27909 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9979 | /* 27913 */ // (bitconvert:{ *:[v2i32] } DPR:{ *:[v8i8] }:$src) => DPR:{ *:[v2i32] }:$src |
| 9980 | /* 27913 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9981 | /* 27916 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 9982 | /* 27918 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 9983 | /* 27920 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 9984 | /* 27925 */ // GIR_Coverage, 2751, |
| 9985 | /* 27925 */ GIR_EraseRootFromParent_Done, |
| 9986 | /* 27926 */ // Label 587: @27926 |
| 9987 | /* 27926 */ GIM_Try, /*On fail goto*//*Label 588*/ GIMT_Encode4(27963), // Rule ID 2814 // |
| 9988 | /* 27931 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 9989 | /* 27934 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 9990 | /* 27937 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9991 | /* 27941 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9992 | /* 27945 */ // (bitconvert:{ *:[v2f32] } DPR:{ *:[f64] }:$src) => (VREV64d32:{ *:[v2f32] } DPR:{ *:[f64] }:$src) |
| 9993 | /* 27945 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d32), |
| 9994 | /* 27948 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 9995 | /* 27950 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 9996 | /* 27952 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9997 | /* 27955 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9998 | /* 27961 */ GIR_RootConstrainSelectedInstOperands, |
| 9999 | /* 27962 */ // GIR_Coverage, 2814, |
| 10000 | /* 27962 */ GIR_EraseRootFromParent_Done, |
| 10001 | /* 27963 */ // Label 588: @27963 |
| 10002 | /* 27963 */ GIM_Try, /*On fail goto*//*Label 589*/ GIMT_Encode4(28000), // Rule ID 2815 // |
| 10003 | /* 27968 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 10004 | /* 27971 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 10005 | /* 27974 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10006 | /* 27978 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10007 | /* 27982 */ // (bitconvert:{ *:[v2f32] } DPR:{ *:[v1i64] }:$src) => (VREV64d32:{ *:[v2f32] } DPR:{ *:[v1i64] }:$src) |
| 10008 | /* 27982 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d32), |
| 10009 | /* 27985 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 10010 | /* 27987 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10011 | /* 27989 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 10012 | /* 27992 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10013 | /* 27998 */ GIR_RootConstrainSelectedInstOperands, |
| 10014 | /* 27999 */ // GIR_Coverage, 2815, |
| 10015 | /* 27999 */ GIR_EraseRootFromParent_Done, |
| 10016 | /* 28000 */ // Label 589: @28000 |
| 10017 | /* 28000 */ GIM_Try, /*On fail goto*//*Label 590*/ GIMT_Encode4(28037), // Rule ID 2816 // |
| 10018 | /* 28005 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 10019 | /* 28008 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 10020 | /* 28011 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10021 | /* 28015 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10022 | /* 28019 */ // (bitconvert:{ *:[v2f32] } DPR:{ *:[v4f16] }:$src) => (VREV32d16:{ *:[v2f32] } DPR:{ *:[v4f16] }:$src) |
| 10023 | /* 28019 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d16), |
| 10024 | /* 28022 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 10025 | /* 28024 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10026 | /* 28026 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 10027 | /* 28029 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10028 | /* 28035 */ GIR_RootConstrainSelectedInstOperands, |
| 10029 | /* 28036 */ // GIR_Coverage, 2816, |
| 10030 | /* 28036 */ GIR_EraseRootFromParent_Done, |
| 10031 | /* 28037 */ // Label 590: @28037 |
| 10032 | /* 28037 */ GIM_Try, /*On fail goto*//*Label 591*/ GIMT_Encode4(28074), // Rule ID 2817 // |
| 10033 | /* 28042 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 10034 | /* 28045 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 10035 | /* 28048 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10036 | /* 28052 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10037 | /* 28056 */ // (bitconvert:{ *:[v2f32] } DPR:{ *:[v4i16] }:$src) => (VREV32d16:{ *:[v2f32] } DPR:{ *:[v4i16] }:$src) |
| 10038 | /* 28056 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d16), |
| 10039 | /* 28059 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 10040 | /* 28061 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10041 | /* 28063 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 10042 | /* 28066 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10043 | /* 28072 */ GIR_RootConstrainSelectedInstOperands, |
| 10044 | /* 28073 */ // GIR_Coverage, 2817, |
| 10045 | /* 28073 */ GIR_EraseRootFromParent_Done, |
| 10046 | /* 28074 */ // Label 591: @28074 |
| 10047 | /* 28074 */ GIM_Try, /*On fail goto*//*Label 592*/ GIMT_Encode4(28111), // Rule ID 2818 // |
| 10048 | /* 28079 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 10049 | /* 28082 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 10050 | /* 28085 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10051 | /* 28089 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10052 | /* 28093 */ // (bitconvert:{ *:[v2f32] } DPR:{ *:[v8i8] }:$src) => (VREV32d8:{ *:[v2f32] } DPR:{ *:[v8i8] }:$src) |
| 10053 | /* 28093 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d8), |
| 10054 | /* 28096 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 10055 | /* 28098 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10056 | /* 28100 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 10057 | /* 28103 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10058 | /* 28109 */ GIR_RootConstrainSelectedInstOperands, |
| 10059 | /* 28110 */ // GIR_Coverage, 2818, |
| 10060 | /* 28110 */ GIR_EraseRootFromParent_Done, |
| 10061 | /* 28111 */ // Label 592: @28111 |
| 10062 | /* 28111 */ GIM_Try, /*On fail goto*//*Label 593*/ GIMT_Encode4(28148), // Rule ID 2819 // |
| 10063 | /* 28116 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 10064 | /* 28119 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 10065 | /* 28122 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10066 | /* 28126 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10067 | /* 28130 */ // (bitconvert:{ *:[v2i32] } DPR:{ *:[f64] }:$src) => (VREV64d32:{ *:[v2i32] } DPR:{ *:[f64] }:$src) |
| 10068 | /* 28130 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d32), |
| 10069 | /* 28133 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 10070 | /* 28135 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10071 | /* 28137 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 10072 | /* 28140 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10073 | /* 28146 */ GIR_RootConstrainSelectedInstOperands, |
| 10074 | /* 28147 */ // GIR_Coverage, 2819, |
| 10075 | /* 28147 */ GIR_EraseRootFromParent_Done, |
| 10076 | /* 28148 */ // Label 593: @28148 |
| 10077 | /* 28148 */ GIM_Try, /*On fail goto*//*Label 594*/ GIMT_Encode4(28185), // Rule ID 2820 // |
| 10078 | /* 28153 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 10079 | /* 28156 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 10080 | /* 28159 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10081 | /* 28163 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10082 | /* 28167 */ // (bitconvert:{ *:[v2i32] } DPR:{ *:[v1i64] }:$src) => (VREV64d32:{ *:[v2i32] } DPR:{ *:[v1i64] }:$src) |
| 10083 | /* 28167 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d32), |
| 10084 | /* 28170 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 10085 | /* 28172 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10086 | /* 28174 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 10087 | /* 28177 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10088 | /* 28183 */ GIR_RootConstrainSelectedInstOperands, |
| 10089 | /* 28184 */ // GIR_Coverage, 2820, |
| 10090 | /* 28184 */ GIR_EraseRootFromParent_Done, |
| 10091 | /* 28185 */ // Label 594: @28185 |
| 10092 | /* 28185 */ GIM_Try, /*On fail goto*//*Label 595*/ GIMT_Encode4(28222), // Rule ID 2821 // |
| 10093 | /* 28190 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 10094 | /* 28193 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 10095 | /* 28196 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10096 | /* 28200 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10097 | /* 28204 */ // (bitconvert:{ *:[v2i32] } DPR:{ *:[v4f16] }:$src) => (VREV32d16:{ *:[v2i32] } DPR:{ *:[v4f16] }:$src) |
| 10098 | /* 28204 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d16), |
| 10099 | /* 28207 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 10100 | /* 28209 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10101 | /* 28211 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 10102 | /* 28214 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10103 | /* 28220 */ GIR_RootConstrainSelectedInstOperands, |
| 10104 | /* 28221 */ // GIR_Coverage, 2821, |
| 10105 | /* 28221 */ GIR_EraseRootFromParent_Done, |
| 10106 | /* 28222 */ // Label 595: @28222 |
| 10107 | /* 28222 */ GIM_Try, /*On fail goto*//*Label 596*/ GIMT_Encode4(28259), // Rule ID 2822 // |
| 10108 | /* 28227 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 10109 | /* 28230 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 10110 | /* 28233 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10111 | /* 28237 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10112 | /* 28241 */ // (bitconvert:{ *:[v2i32] } DPR:{ *:[v4i16] }:$src) => (VREV32d16:{ *:[v2i32] } DPR:{ *:[v4i16] }:$src) |
| 10113 | /* 28241 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d16), |
| 10114 | /* 28244 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 10115 | /* 28246 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10116 | /* 28248 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 10117 | /* 28251 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10118 | /* 28257 */ GIR_RootConstrainSelectedInstOperands, |
| 10119 | /* 28258 */ // GIR_Coverage, 2822, |
| 10120 | /* 28258 */ GIR_EraseRootFromParent_Done, |
| 10121 | /* 28259 */ // Label 596: @28259 |
| 10122 | /* 28259 */ GIM_Try, /*On fail goto*//*Label 597*/ GIMT_Encode4(28296), // Rule ID 2823 // |
| 10123 | /* 28264 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 10124 | /* 28267 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 10125 | /* 28270 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10126 | /* 28274 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10127 | /* 28278 */ // (bitconvert:{ *:[v2i32] } DPR:{ *:[v8i8] }:$src) => (VREV32d8:{ *:[v2i32] } DPR:{ *:[v8i8] }:$src) |
| 10128 | /* 28278 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d8), |
| 10129 | /* 28281 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 10130 | /* 28283 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10131 | /* 28285 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 10132 | /* 28288 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10133 | /* 28294 */ GIR_RootConstrainSelectedInstOperands, |
| 10134 | /* 28295 */ // GIR_Coverage, 2823, |
| 10135 | /* 28295 */ GIR_EraseRootFromParent_Done, |
| 10136 | /* 28296 */ // Label 597: @28296 |
| 10137 | /* 28296 */ GIM_Reject, |
| 10138 | /* 28297 */ // Label 543: @28297 |
| 10139 | /* 28297 */ GIM_Try, /*On fail goto*//*Label 598*/ GIMT_Encode4(28329), // Rule ID 2726 // |
| 10140 | /* 28302 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 10141 | /* 28305 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 10142 | /* 28308 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10143 | /* 28312 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10144 | /* 28316 */ // (bitconvert:{ *:[v2f64] } QPR:{ *:[v2i64] }:$src) => QPR:{ *:[v2f64] }:$src |
| 10145 | /* 28316 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10146 | /* 28319 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 10147 | /* 28321 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10148 | /* 28323 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 10149 | /* 28328 */ // GIR_Coverage, 2726, |
| 10150 | /* 28328 */ GIR_EraseRootFromParent_Done, |
| 10151 | /* 28329 */ // Label 598: @28329 |
| 10152 | /* 28329 */ GIM_Try, /*On fail goto*//*Label 599*/ GIMT_Encode4(28361), // Rule ID 2727 // |
| 10153 | /* 28334 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 10154 | /* 28337 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 10155 | /* 28340 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10156 | /* 28344 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10157 | /* 28348 */ // (bitconvert:{ *:[v2i64] } QPR:{ *:[v2f64] }:$src) => QPR:{ *:[v2i64] }:$src |
| 10158 | /* 28348 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10159 | /* 28351 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 10160 | /* 28353 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10161 | /* 28355 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 10162 | /* 28360 */ // GIR_Coverage, 2727, |
| 10163 | /* 28360 */ GIR_EraseRootFromParent_Done, |
| 10164 | /* 28361 */ // Label 599: @28361 |
| 10165 | /* 28361 */ GIM_Try, /*On fail goto*//*Label 600*/ GIMT_Encode4(28393), // Rule ID 2768 // |
| 10166 | /* 28366 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 10167 | /* 28369 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 10168 | /* 28372 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10169 | /* 28376 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10170 | /* 28380 */ // (bitconvert:{ *:[v2f64] } QPR:{ *:[v4f32] }:$src) => QPR:{ *:[v2f64] }:$src |
| 10171 | /* 28380 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10172 | /* 28383 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 10173 | /* 28385 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10174 | /* 28387 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 10175 | /* 28392 */ // GIR_Coverage, 2768, |
| 10176 | /* 28392 */ GIR_EraseRootFromParent_Done, |
| 10177 | /* 28393 */ // Label 600: @28393 |
| 10178 | /* 28393 */ GIM_Try, /*On fail goto*//*Label 601*/ GIMT_Encode4(28425), // Rule ID 2769 // |
| 10179 | /* 28398 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 10180 | /* 28401 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 10181 | /* 28404 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10182 | /* 28408 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10183 | /* 28412 */ // (bitconvert:{ *:[v2f64] } QPR:{ *:[v4i32] }:$src) => QPR:{ *:[v2f64] }:$src |
| 10184 | /* 28412 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10185 | /* 28415 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 10186 | /* 28417 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10187 | /* 28419 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 10188 | /* 28424 */ // GIR_Coverage, 2769, |
| 10189 | /* 28424 */ GIR_EraseRootFromParent_Done, |
| 10190 | /* 28425 */ // Label 601: @28425 |
| 10191 | /* 28425 */ GIM_Try, /*On fail goto*//*Label 602*/ GIMT_Encode4(28457), // Rule ID 2770 // |
| 10192 | /* 28430 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 10193 | /* 28433 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 10194 | /* 28436 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10195 | /* 28440 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10196 | /* 28444 */ // (bitconvert:{ *:[v2f64] } QPR:{ *:[v8f16] }:$src) => QPR:{ *:[v2f64] }:$src |
| 10197 | /* 28444 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10198 | /* 28447 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 10199 | /* 28449 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10200 | /* 28451 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 10201 | /* 28456 */ // GIR_Coverage, 2770, |
| 10202 | /* 28456 */ GIR_EraseRootFromParent_Done, |
| 10203 | /* 28457 */ // Label 602: @28457 |
| 10204 | /* 28457 */ GIM_Try, /*On fail goto*//*Label 603*/ GIMT_Encode4(28489), // Rule ID 2771 // |
| 10205 | /* 28462 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 10206 | /* 28465 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 10207 | /* 28468 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10208 | /* 28472 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10209 | /* 28476 */ // (bitconvert:{ *:[v2f64] } QPR:{ *:[v8i16] }:$src) => QPR:{ *:[v2f64] }:$src |
| 10210 | /* 28476 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10211 | /* 28479 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 10212 | /* 28481 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10213 | /* 28483 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 10214 | /* 28488 */ // GIR_Coverage, 2771, |
| 10215 | /* 28488 */ GIR_EraseRootFromParent_Done, |
| 10216 | /* 28489 */ // Label 603: @28489 |
| 10217 | /* 28489 */ GIM_Try, /*On fail goto*//*Label 604*/ GIMT_Encode4(28521), // Rule ID 2772 // |
| 10218 | /* 28494 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 10219 | /* 28497 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 10220 | /* 28500 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10221 | /* 28504 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10222 | /* 28508 */ // (bitconvert:{ *:[v2f64] } QPR:{ *:[v16i8] }:$src) => QPR:{ *:[v2f64] }:$src |
| 10223 | /* 28508 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10224 | /* 28511 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 10225 | /* 28513 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10226 | /* 28515 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 10227 | /* 28520 */ // GIR_Coverage, 2772, |
| 10228 | /* 28520 */ GIR_EraseRootFromParent_Done, |
| 10229 | /* 28521 */ // Label 604: @28521 |
| 10230 | /* 28521 */ GIM_Try, /*On fail goto*//*Label 605*/ GIMT_Encode4(28553), // Rule ID 2773 // |
| 10231 | /* 28526 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 10232 | /* 28529 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 10233 | /* 28532 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10234 | /* 28536 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10235 | /* 28540 */ // (bitconvert:{ *:[v2i64] } QPR:{ *:[v4f32] }:$src) => QPR:{ *:[v2i64] }:$src |
| 10236 | /* 28540 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10237 | /* 28543 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 10238 | /* 28545 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10239 | /* 28547 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 10240 | /* 28552 */ // GIR_Coverage, 2773, |
| 10241 | /* 28552 */ GIR_EraseRootFromParent_Done, |
| 10242 | /* 28553 */ // Label 605: @28553 |
| 10243 | /* 28553 */ GIM_Try, /*On fail goto*//*Label 606*/ GIMT_Encode4(28585), // Rule ID 2774 // |
| 10244 | /* 28558 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 10245 | /* 28561 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 10246 | /* 28564 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10247 | /* 28568 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10248 | /* 28572 */ // (bitconvert:{ *:[v2i64] } QPR:{ *:[v4i32] }:$src) => QPR:{ *:[v2i64] }:$src |
| 10249 | /* 28572 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10250 | /* 28575 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 10251 | /* 28577 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10252 | /* 28579 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 10253 | /* 28584 */ // GIR_Coverage, 2774, |
| 10254 | /* 28584 */ GIR_EraseRootFromParent_Done, |
| 10255 | /* 28585 */ // Label 606: @28585 |
| 10256 | /* 28585 */ GIM_Try, /*On fail goto*//*Label 607*/ GIMT_Encode4(28617), // Rule ID 2775 // |
| 10257 | /* 28590 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 10258 | /* 28593 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 10259 | /* 28596 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10260 | /* 28600 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10261 | /* 28604 */ // (bitconvert:{ *:[v2i64] } QPR:{ *:[v8f16] }:$src) => QPR:{ *:[v2i64] }:$src |
| 10262 | /* 28604 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10263 | /* 28607 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 10264 | /* 28609 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10265 | /* 28611 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 10266 | /* 28616 */ // GIR_Coverage, 2775, |
| 10267 | /* 28616 */ GIR_EraseRootFromParent_Done, |
| 10268 | /* 28617 */ // Label 607: @28617 |
| 10269 | /* 28617 */ GIM_Try, /*On fail goto*//*Label 608*/ GIMT_Encode4(28649), // Rule ID 2776 // |
| 10270 | /* 28622 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 10271 | /* 28625 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 10272 | /* 28628 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10273 | /* 28632 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10274 | /* 28636 */ // (bitconvert:{ *:[v2i64] } QPR:{ *:[v8i16] }:$src) => QPR:{ *:[v2i64] }:$src |
| 10275 | /* 28636 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10276 | /* 28639 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 10277 | /* 28641 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10278 | /* 28643 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 10279 | /* 28648 */ // GIR_Coverage, 2776, |
| 10280 | /* 28648 */ GIR_EraseRootFromParent_Done, |
| 10281 | /* 28649 */ // Label 608: @28649 |
| 10282 | /* 28649 */ GIM_Try, /*On fail goto*//*Label 609*/ GIMT_Encode4(28681), // Rule ID 2777 // |
| 10283 | /* 28654 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 10284 | /* 28657 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 10285 | /* 28660 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10286 | /* 28664 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10287 | /* 28668 */ // (bitconvert:{ *:[v2i64] } QPR:{ *:[v16i8] }:$src) => QPR:{ *:[v2i64] }:$src |
| 10288 | /* 28668 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10289 | /* 28671 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 10290 | /* 28673 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10291 | /* 28675 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 10292 | /* 28680 */ // GIR_Coverage, 2777, |
| 10293 | /* 28680 */ GIR_EraseRootFromParent_Done, |
| 10294 | /* 28681 */ // Label 609: @28681 |
| 10295 | /* 28681 */ GIM_Try, /*On fail goto*//*Label 610*/ GIMT_Encode4(28718), // Rule ID 2840 // |
| 10296 | /* 28686 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 10297 | /* 28689 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 10298 | /* 28692 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10299 | /* 28696 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10300 | /* 28700 */ // (bitconvert:{ *:[v2f64] } QPR:{ *:[v4f32] }:$src) => (VREV64q32:{ *:[v2f64] } QPR:{ *:[v4f32] }:$src) |
| 10301 | /* 28700 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q32), |
| 10302 | /* 28703 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 10303 | /* 28705 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10304 | /* 28707 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 10305 | /* 28710 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10306 | /* 28716 */ GIR_RootConstrainSelectedInstOperands, |
| 10307 | /* 28717 */ // GIR_Coverage, 2840, |
| 10308 | /* 28717 */ GIR_EraseRootFromParent_Done, |
| 10309 | /* 28718 */ // Label 610: @28718 |
| 10310 | /* 28718 */ GIM_Try, /*On fail goto*//*Label 611*/ GIMT_Encode4(28755), // Rule ID 2841 // |
| 10311 | /* 28723 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 10312 | /* 28726 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 10313 | /* 28729 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10314 | /* 28733 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10315 | /* 28737 */ // (bitconvert:{ *:[v2f64] } QPR:{ *:[v4i32] }:$src) => (VREV64q32:{ *:[v2f64] } QPR:{ *:[v4i32] }:$src) |
| 10316 | /* 28737 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q32), |
| 10317 | /* 28740 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 10318 | /* 28742 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10319 | /* 28744 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 10320 | /* 28747 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10321 | /* 28753 */ GIR_RootConstrainSelectedInstOperands, |
| 10322 | /* 28754 */ // GIR_Coverage, 2841, |
| 10323 | /* 28754 */ GIR_EraseRootFromParent_Done, |
| 10324 | /* 28755 */ // Label 611: @28755 |
| 10325 | /* 28755 */ GIM_Try, /*On fail goto*//*Label 612*/ GIMT_Encode4(28792), // Rule ID 2842 // |
| 10326 | /* 28760 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 10327 | /* 28763 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 10328 | /* 28766 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10329 | /* 28770 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10330 | /* 28774 */ // (bitconvert:{ *:[v2f64] } QPR:{ *:[v8f16] }:$src) => (VREV64q16:{ *:[v2f64] } QPR:{ *:[v8f16] }:$src) |
| 10331 | /* 28774 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q16), |
| 10332 | /* 28777 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 10333 | /* 28779 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10334 | /* 28781 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 10335 | /* 28784 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10336 | /* 28790 */ GIR_RootConstrainSelectedInstOperands, |
| 10337 | /* 28791 */ // GIR_Coverage, 2842, |
| 10338 | /* 28791 */ GIR_EraseRootFromParent_Done, |
| 10339 | /* 28792 */ // Label 612: @28792 |
| 10340 | /* 28792 */ GIM_Try, /*On fail goto*//*Label 613*/ GIMT_Encode4(28829), // Rule ID 2843 // |
| 10341 | /* 28797 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 10342 | /* 28800 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 10343 | /* 28803 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10344 | /* 28807 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10345 | /* 28811 */ // (bitconvert:{ *:[v2f64] } QPR:{ *:[v8i16] }:$src) => (VREV64q16:{ *:[v2f64] } QPR:{ *:[v8i16] }:$src) |
| 10346 | /* 28811 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q16), |
| 10347 | /* 28814 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 10348 | /* 28816 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10349 | /* 28818 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 10350 | /* 28821 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10351 | /* 28827 */ GIR_RootConstrainSelectedInstOperands, |
| 10352 | /* 28828 */ // GIR_Coverage, 2843, |
| 10353 | /* 28828 */ GIR_EraseRootFromParent_Done, |
| 10354 | /* 28829 */ // Label 613: @28829 |
| 10355 | /* 28829 */ GIM_Try, /*On fail goto*//*Label 614*/ GIMT_Encode4(28866), // Rule ID 2844 // |
| 10356 | /* 28834 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 10357 | /* 28837 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 10358 | /* 28840 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10359 | /* 28844 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10360 | /* 28848 */ // (bitconvert:{ *:[v2f64] } QPR:{ *:[v16i8] }:$src) => (VREV64q8:{ *:[v2f64] } QPR:{ *:[v16i8] }:$src) |
| 10361 | /* 28848 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q8), |
| 10362 | /* 28851 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 10363 | /* 28853 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10364 | /* 28855 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 10365 | /* 28858 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10366 | /* 28864 */ GIR_RootConstrainSelectedInstOperands, |
| 10367 | /* 28865 */ // GIR_Coverage, 2844, |
| 10368 | /* 28865 */ GIR_EraseRootFromParent_Done, |
| 10369 | /* 28866 */ // Label 614: @28866 |
| 10370 | /* 28866 */ GIM_Try, /*On fail goto*//*Label 615*/ GIMT_Encode4(28903), // Rule ID 2845 // |
| 10371 | /* 28871 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 10372 | /* 28874 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 10373 | /* 28877 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10374 | /* 28881 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10375 | /* 28885 */ // (bitconvert:{ *:[v2i64] } QPR:{ *:[v4f32] }:$src) => (VREV64q32:{ *:[v2i64] } QPR:{ *:[v4f32] }:$src) |
| 10376 | /* 28885 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q32), |
| 10377 | /* 28888 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 10378 | /* 28890 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10379 | /* 28892 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 10380 | /* 28895 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10381 | /* 28901 */ GIR_RootConstrainSelectedInstOperands, |
| 10382 | /* 28902 */ // GIR_Coverage, 2845, |
| 10383 | /* 28902 */ GIR_EraseRootFromParent_Done, |
| 10384 | /* 28903 */ // Label 615: @28903 |
| 10385 | /* 28903 */ GIM_Try, /*On fail goto*//*Label 616*/ GIMT_Encode4(28940), // Rule ID 2846 // |
| 10386 | /* 28908 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 10387 | /* 28911 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 10388 | /* 28914 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10389 | /* 28918 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10390 | /* 28922 */ // (bitconvert:{ *:[v2i64] } QPR:{ *:[v4i32] }:$src) => (VREV64q32:{ *:[v2i64] } QPR:{ *:[v4i32] }:$src) |
| 10391 | /* 28922 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q32), |
| 10392 | /* 28925 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 10393 | /* 28927 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10394 | /* 28929 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 10395 | /* 28932 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10396 | /* 28938 */ GIR_RootConstrainSelectedInstOperands, |
| 10397 | /* 28939 */ // GIR_Coverage, 2846, |
| 10398 | /* 28939 */ GIR_EraseRootFromParent_Done, |
| 10399 | /* 28940 */ // Label 616: @28940 |
| 10400 | /* 28940 */ GIM_Try, /*On fail goto*//*Label 617*/ GIMT_Encode4(28977), // Rule ID 2847 // |
| 10401 | /* 28945 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 10402 | /* 28948 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 10403 | /* 28951 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10404 | /* 28955 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10405 | /* 28959 */ // (bitconvert:{ *:[v2i64] } QPR:{ *:[v8f16] }:$src) => (VREV64q16:{ *:[v2i64] } QPR:{ *:[v8f16] }:$src) |
| 10406 | /* 28959 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q16), |
| 10407 | /* 28962 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 10408 | /* 28964 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10409 | /* 28966 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 10410 | /* 28969 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10411 | /* 28975 */ GIR_RootConstrainSelectedInstOperands, |
| 10412 | /* 28976 */ // GIR_Coverage, 2847, |
| 10413 | /* 28976 */ GIR_EraseRootFromParent_Done, |
| 10414 | /* 28977 */ // Label 617: @28977 |
| 10415 | /* 28977 */ GIM_Try, /*On fail goto*//*Label 618*/ GIMT_Encode4(29014), // Rule ID 2848 // |
| 10416 | /* 28982 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 10417 | /* 28985 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 10418 | /* 28988 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10419 | /* 28992 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10420 | /* 28996 */ // (bitconvert:{ *:[v2i64] } QPR:{ *:[v8i16] }:$src) => (VREV64q16:{ *:[v2i64] } QPR:{ *:[v8i16] }:$src) |
| 10421 | /* 28996 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q16), |
| 10422 | /* 28999 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 10423 | /* 29001 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10424 | /* 29003 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 10425 | /* 29006 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10426 | /* 29012 */ GIR_RootConstrainSelectedInstOperands, |
| 10427 | /* 29013 */ // GIR_Coverage, 2848, |
| 10428 | /* 29013 */ GIR_EraseRootFromParent_Done, |
| 10429 | /* 29014 */ // Label 618: @29014 |
| 10430 | /* 29014 */ GIM_Try, /*On fail goto*//*Label 619*/ GIMT_Encode4(29051), // Rule ID 2849 // |
| 10431 | /* 29019 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 10432 | /* 29022 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 10433 | /* 29025 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10434 | /* 29029 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10435 | /* 29033 */ // (bitconvert:{ *:[v2i64] } QPR:{ *:[v16i8] }:$src) => (VREV64q8:{ *:[v2i64] } QPR:{ *:[v16i8] }:$src) |
| 10436 | /* 29033 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q8), |
| 10437 | /* 29036 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 10438 | /* 29038 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10439 | /* 29040 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 10440 | /* 29043 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10441 | /* 29049 */ GIR_RootConstrainSelectedInstOperands, |
| 10442 | /* 29050 */ // GIR_Coverage, 2849, |
| 10443 | /* 29050 */ GIR_EraseRootFromParent_Done, |
| 10444 | /* 29051 */ // Label 619: @29051 |
| 10445 | /* 29051 */ GIM_Try, /*On fail goto*//*Label 620*/ GIMT_Encode4(29083), // Rule ID 5283 // |
| 10446 | /* 29056 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 10447 | /* 29059 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 10448 | /* 29062 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10449 | /* 29066 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10450 | /* 29070 */ // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v2i64] }:$src) => MQPR:{ *:[v2f64] }:$src |
| 10451 | /* 29070 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10452 | /* 29073 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 10453 | /* 29075 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10454 | /* 29077 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 10455 | /* 29082 */ // GIR_Coverage, 5283, |
| 10456 | /* 29082 */ GIR_EraseRootFromParent_Done, |
| 10457 | /* 29083 */ // Label 620: @29083 |
| 10458 | /* 29083 */ GIM_Try, /*On fail goto*//*Label 621*/ GIMT_Encode4(29115), // Rule ID 5284 // |
| 10459 | /* 29088 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 10460 | /* 29091 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 10461 | /* 29094 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10462 | /* 29098 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10463 | /* 29102 */ // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v2f64] }:$src) => MQPR:{ *:[v2i64] }:$src |
| 10464 | /* 29102 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10465 | /* 29105 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 10466 | /* 29107 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10467 | /* 29109 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 10468 | /* 29114 */ // GIR_Coverage, 5284, |
| 10469 | /* 29114 */ GIR_EraseRootFromParent_Done, |
| 10470 | /* 29115 */ // Label 621: @29115 |
| 10471 | /* 29115 */ GIM_Try, /*On fail goto*//*Label 622*/ GIMT_Encode4(29147), // Rule ID 5289 // |
| 10472 | /* 29120 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), |
| 10473 | /* 29123 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 10474 | /* 29126 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10475 | /* 29130 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10476 | /* 29134 */ // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v4f32] }:$src) => MQPR:{ *:[v2f64] }:$src |
| 10477 | /* 29134 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10478 | /* 29137 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 10479 | /* 29139 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10480 | /* 29141 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 10481 | /* 29146 */ // GIR_Coverage, 5289, |
| 10482 | /* 29146 */ GIR_EraseRootFromParent_Done, |
| 10483 | /* 29147 */ // Label 622: @29147 |
| 10484 | /* 29147 */ GIM_Try, /*On fail goto*//*Label 623*/ GIMT_Encode4(29179), // Rule ID 5290 // |
| 10485 | /* 29152 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), |
| 10486 | /* 29155 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 10487 | /* 29158 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10488 | /* 29162 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10489 | /* 29166 */ // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v4i32] }:$src) => MQPR:{ *:[v2f64] }:$src |
| 10490 | /* 29166 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10491 | /* 29169 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 10492 | /* 29171 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10493 | /* 29173 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 10494 | /* 29178 */ // GIR_Coverage, 5290, |
| 10495 | /* 29178 */ GIR_EraseRootFromParent_Done, |
| 10496 | /* 29179 */ // Label 623: @29179 |
| 10497 | /* 29179 */ GIM_Try, /*On fail goto*//*Label 624*/ GIMT_Encode4(29211), // Rule ID 5291 // |
| 10498 | /* 29184 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), |
| 10499 | /* 29187 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 10500 | /* 29190 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10501 | /* 29194 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10502 | /* 29198 */ // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v8f16] }:$src) => MQPR:{ *:[v2f64] }:$src |
| 10503 | /* 29198 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10504 | /* 29201 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 10505 | /* 29203 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10506 | /* 29205 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 10507 | /* 29210 */ // GIR_Coverage, 5291, |
| 10508 | /* 29210 */ GIR_EraseRootFromParent_Done, |
| 10509 | /* 29211 */ // Label 624: @29211 |
| 10510 | /* 29211 */ GIM_Try, /*On fail goto*//*Label 625*/ GIMT_Encode4(29243), // Rule ID 5292 // |
| 10511 | /* 29216 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), |
| 10512 | /* 29219 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 10513 | /* 29222 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10514 | /* 29226 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10515 | /* 29230 */ // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v8i16] }:$src) => MQPR:{ *:[v2f64] }:$src |
| 10516 | /* 29230 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10517 | /* 29233 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 10518 | /* 29235 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10519 | /* 29237 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 10520 | /* 29242 */ // GIR_Coverage, 5292, |
| 10521 | /* 29242 */ GIR_EraseRootFromParent_Done, |
| 10522 | /* 29243 */ // Label 625: @29243 |
| 10523 | /* 29243 */ GIM_Try, /*On fail goto*//*Label 626*/ GIMT_Encode4(29275), // Rule ID 5293 // |
| 10524 | /* 29248 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), |
| 10525 | /* 29251 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 10526 | /* 29254 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10527 | /* 29258 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10528 | /* 29262 */ // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v16i8] }:$src) => MQPR:{ *:[v2f64] }:$src |
| 10529 | /* 29262 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10530 | /* 29265 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 10531 | /* 29267 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10532 | /* 29269 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 10533 | /* 29274 */ // GIR_Coverage, 5293, |
| 10534 | /* 29274 */ GIR_EraseRootFromParent_Done, |
| 10535 | /* 29275 */ // Label 626: @29275 |
| 10536 | /* 29275 */ GIM_Try, /*On fail goto*//*Label 627*/ GIMT_Encode4(29307), // Rule ID 5294 // |
| 10537 | /* 29280 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), |
| 10538 | /* 29283 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 10539 | /* 29286 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10540 | /* 29290 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10541 | /* 29294 */ // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v4f32] }:$src) => MQPR:{ *:[v2i64] }:$src |
| 10542 | /* 29294 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10543 | /* 29297 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 10544 | /* 29299 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10545 | /* 29301 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 10546 | /* 29306 */ // GIR_Coverage, 5294, |
| 10547 | /* 29306 */ GIR_EraseRootFromParent_Done, |
| 10548 | /* 29307 */ // Label 627: @29307 |
| 10549 | /* 29307 */ GIM_Try, /*On fail goto*//*Label 628*/ GIMT_Encode4(29339), // Rule ID 5295 // |
| 10550 | /* 29312 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), |
| 10551 | /* 29315 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 10552 | /* 29318 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10553 | /* 29322 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10554 | /* 29326 */ // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$src) => MQPR:{ *:[v2i64] }:$src |
| 10555 | /* 29326 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10556 | /* 29329 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 10557 | /* 29331 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10558 | /* 29333 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 10559 | /* 29338 */ // GIR_Coverage, 5295, |
| 10560 | /* 29338 */ GIR_EraseRootFromParent_Done, |
| 10561 | /* 29339 */ // Label 628: @29339 |
| 10562 | /* 29339 */ GIM_Try, /*On fail goto*//*Label 629*/ GIMT_Encode4(29371), // Rule ID 5296 // |
| 10563 | /* 29344 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), |
| 10564 | /* 29347 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 10565 | /* 29350 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10566 | /* 29354 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10567 | /* 29358 */ // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v8f16] }:$src) => MQPR:{ *:[v2i64] }:$src |
| 10568 | /* 29358 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10569 | /* 29361 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 10570 | /* 29363 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10571 | /* 29365 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 10572 | /* 29370 */ // GIR_Coverage, 5296, |
| 10573 | /* 29370 */ GIR_EraseRootFromParent_Done, |
| 10574 | /* 29371 */ // Label 629: @29371 |
| 10575 | /* 29371 */ GIM_Try, /*On fail goto*//*Label 630*/ GIMT_Encode4(29403), // Rule ID 5297 // |
| 10576 | /* 29376 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), |
| 10577 | /* 29379 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 10578 | /* 29382 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10579 | /* 29386 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10580 | /* 29390 */ // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v8i16] }:$src) => MQPR:{ *:[v2i64] }:$src |
| 10581 | /* 29390 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10582 | /* 29393 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 10583 | /* 29395 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10584 | /* 29397 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 10585 | /* 29402 */ // GIR_Coverage, 5297, |
| 10586 | /* 29402 */ GIR_EraseRootFromParent_Done, |
| 10587 | /* 29403 */ // Label 630: @29403 |
| 10588 | /* 29403 */ GIM_Try, /*On fail goto*//*Label 631*/ GIMT_Encode4(29435), // Rule ID 5298 // |
| 10589 | /* 29408 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), |
| 10590 | /* 29411 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 10591 | /* 29414 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10592 | /* 29418 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10593 | /* 29422 */ // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v16i8] }:$src) => MQPR:{ *:[v2i64] }:$src |
| 10594 | /* 29422 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10595 | /* 29425 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 10596 | /* 29427 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10597 | /* 29429 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 10598 | /* 29434 */ // GIR_Coverage, 5298, |
| 10599 | /* 29434 */ GIR_EraseRootFromParent_Done, |
| 10600 | /* 29435 */ // Label 631: @29435 |
| 10601 | /* 29435 */ GIM_Try, /*On fail goto*//*Label 632*/ GIMT_Encode4(29493), // Rule ID 5325 // |
| 10602 | /* 29440 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), |
| 10603 | /* 29443 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 10604 | /* 29446 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10605 | /* 29450 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10606 | /* 29454 */ // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v4f32] }:$src) => (MVE_VREV64_32:{ *:[v2f64] } MQPR:{ *:[v4f32] }:$src) |
| 10607 | /* 29454 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 10608 | /* 29457 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10609 | /* 29461 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10610 | /* 29466 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_32), |
| 10611 | /* 29469 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 10612 | /* 29471 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10613 | /* 29473 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 10614 | /* 29476 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10615 | /* 29482 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10616 | /* 29488 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10617 | /* 29491 */ GIR_RootConstrainSelectedInstOperands, |
| 10618 | /* 29492 */ // GIR_Coverage, 5325, |
| 10619 | /* 29492 */ GIR_EraseRootFromParent_Done, |
| 10620 | /* 29493 */ // Label 632: @29493 |
| 10621 | /* 29493 */ GIM_Try, /*On fail goto*//*Label 633*/ GIMT_Encode4(29551), // Rule ID 5326 // |
| 10622 | /* 29498 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), |
| 10623 | /* 29501 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 10624 | /* 29504 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10625 | /* 29508 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10626 | /* 29512 */ // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v4i32] }:$src) => (MVE_VREV64_32:{ *:[v2f64] } MQPR:{ *:[v4i32] }:$src) |
| 10627 | /* 29512 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 10628 | /* 29515 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10629 | /* 29519 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10630 | /* 29524 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_32), |
| 10631 | /* 29527 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 10632 | /* 29529 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10633 | /* 29531 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 10634 | /* 29534 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10635 | /* 29540 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10636 | /* 29546 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10637 | /* 29549 */ GIR_RootConstrainSelectedInstOperands, |
| 10638 | /* 29550 */ // GIR_Coverage, 5326, |
| 10639 | /* 29550 */ GIR_EraseRootFromParent_Done, |
| 10640 | /* 29551 */ // Label 633: @29551 |
| 10641 | /* 29551 */ GIM_Try, /*On fail goto*//*Label 634*/ GIMT_Encode4(29609), // Rule ID 5327 // |
| 10642 | /* 29556 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), |
| 10643 | /* 29559 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 10644 | /* 29562 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10645 | /* 29566 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10646 | /* 29570 */ // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v8f16] }:$src) => (MVE_VREV64_16:{ *:[v2f64] } MQPR:{ *:[v8f16] }:$src) |
| 10647 | /* 29570 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 10648 | /* 29573 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10649 | /* 29577 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10650 | /* 29582 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_16), |
| 10651 | /* 29585 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 10652 | /* 29587 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10653 | /* 29589 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 10654 | /* 29592 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10655 | /* 29598 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10656 | /* 29604 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10657 | /* 29607 */ GIR_RootConstrainSelectedInstOperands, |
| 10658 | /* 29608 */ // GIR_Coverage, 5327, |
| 10659 | /* 29608 */ GIR_EraseRootFromParent_Done, |
| 10660 | /* 29609 */ // Label 634: @29609 |
| 10661 | /* 29609 */ GIM_Try, /*On fail goto*//*Label 635*/ GIMT_Encode4(29667), // Rule ID 5328 // |
| 10662 | /* 29614 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), |
| 10663 | /* 29617 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 10664 | /* 29620 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10665 | /* 29624 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10666 | /* 29628 */ // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v8i16] }:$src) => (MVE_VREV64_16:{ *:[v2f64] } MQPR:{ *:[v8i16] }:$src) |
| 10667 | /* 29628 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 10668 | /* 29631 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10669 | /* 29635 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10670 | /* 29640 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_16), |
| 10671 | /* 29643 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 10672 | /* 29645 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10673 | /* 29647 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 10674 | /* 29650 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10675 | /* 29656 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10676 | /* 29662 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10677 | /* 29665 */ GIR_RootConstrainSelectedInstOperands, |
| 10678 | /* 29666 */ // GIR_Coverage, 5328, |
| 10679 | /* 29666 */ GIR_EraseRootFromParent_Done, |
| 10680 | /* 29667 */ // Label 635: @29667 |
| 10681 | /* 29667 */ GIM_Try, /*On fail goto*//*Label 636*/ GIMT_Encode4(29725), // Rule ID 5329 // |
| 10682 | /* 29672 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), |
| 10683 | /* 29675 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 10684 | /* 29678 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10685 | /* 29682 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10686 | /* 29686 */ // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v16i8] }:$src) => (MVE_VREV64_8:{ *:[v2f64] } MQPR:{ *:[v16i8] }:$src) |
| 10687 | /* 29686 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 10688 | /* 29689 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10689 | /* 29693 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10690 | /* 29698 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_8), |
| 10691 | /* 29701 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 10692 | /* 29703 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10693 | /* 29705 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 10694 | /* 29708 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10695 | /* 29714 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10696 | /* 29720 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10697 | /* 29723 */ GIR_RootConstrainSelectedInstOperands, |
| 10698 | /* 29724 */ // GIR_Coverage, 5329, |
| 10699 | /* 29724 */ GIR_EraseRootFromParent_Done, |
| 10700 | /* 29725 */ // Label 636: @29725 |
| 10701 | /* 29725 */ GIM_Try, /*On fail goto*//*Label 637*/ GIMT_Encode4(29783), // Rule ID 5330 // |
| 10702 | /* 29730 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), |
| 10703 | /* 29733 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 10704 | /* 29736 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10705 | /* 29740 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10706 | /* 29744 */ // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v4f32] }:$src) => (MVE_VREV64_32:{ *:[v2i64] } MQPR:{ *:[v4f32] }:$src) |
| 10707 | /* 29744 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 10708 | /* 29747 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10709 | /* 29751 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10710 | /* 29756 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_32), |
| 10711 | /* 29759 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 10712 | /* 29761 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10713 | /* 29763 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 10714 | /* 29766 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10715 | /* 29772 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10716 | /* 29778 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10717 | /* 29781 */ GIR_RootConstrainSelectedInstOperands, |
| 10718 | /* 29782 */ // GIR_Coverage, 5330, |
| 10719 | /* 29782 */ GIR_EraseRootFromParent_Done, |
| 10720 | /* 29783 */ // Label 637: @29783 |
| 10721 | /* 29783 */ GIM_Try, /*On fail goto*//*Label 638*/ GIMT_Encode4(29841), // Rule ID 5331 // |
| 10722 | /* 29788 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), |
| 10723 | /* 29791 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 10724 | /* 29794 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10725 | /* 29798 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10726 | /* 29802 */ // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$src) => (MVE_VREV64_32:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$src) |
| 10727 | /* 29802 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 10728 | /* 29805 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10729 | /* 29809 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10730 | /* 29814 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_32), |
| 10731 | /* 29817 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 10732 | /* 29819 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10733 | /* 29821 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 10734 | /* 29824 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10735 | /* 29830 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10736 | /* 29836 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10737 | /* 29839 */ GIR_RootConstrainSelectedInstOperands, |
| 10738 | /* 29840 */ // GIR_Coverage, 5331, |
| 10739 | /* 29840 */ GIR_EraseRootFromParent_Done, |
| 10740 | /* 29841 */ // Label 638: @29841 |
| 10741 | /* 29841 */ GIM_Try, /*On fail goto*//*Label 639*/ GIMT_Encode4(29899), // Rule ID 5332 // |
| 10742 | /* 29846 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), |
| 10743 | /* 29849 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 10744 | /* 29852 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10745 | /* 29856 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10746 | /* 29860 */ // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v8f16] }:$src) => (MVE_VREV64_16:{ *:[v2i64] } MQPR:{ *:[v8f16] }:$src) |
| 10747 | /* 29860 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 10748 | /* 29863 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10749 | /* 29867 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10750 | /* 29872 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_16), |
| 10751 | /* 29875 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 10752 | /* 29877 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10753 | /* 29879 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 10754 | /* 29882 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10755 | /* 29888 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10756 | /* 29894 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10757 | /* 29897 */ GIR_RootConstrainSelectedInstOperands, |
| 10758 | /* 29898 */ // GIR_Coverage, 5332, |
| 10759 | /* 29898 */ GIR_EraseRootFromParent_Done, |
| 10760 | /* 29899 */ // Label 639: @29899 |
| 10761 | /* 29899 */ GIM_Try, /*On fail goto*//*Label 640*/ GIMT_Encode4(29957), // Rule ID 5333 // |
| 10762 | /* 29904 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), |
| 10763 | /* 29907 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 10764 | /* 29910 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10765 | /* 29914 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10766 | /* 29918 */ // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v8i16] }:$src) => (MVE_VREV64_16:{ *:[v2i64] } MQPR:{ *:[v8i16] }:$src) |
| 10767 | /* 29918 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 10768 | /* 29921 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10769 | /* 29925 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10770 | /* 29930 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_16), |
| 10771 | /* 29933 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 10772 | /* 29935 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10773 | /* 29937 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 10774 | /* 29940 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10775 | /* 29946 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10776 | /* 29952 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10777 | /* 29955 */ GIR_RootConstrainSelectedInstOperands, |
| 10778 | /* 29956 */ // GIR_Coverage, 5333, |
| 10779 | /* 29956 */ GIR_EraseRootFromParent_Done, |
| 10780 | /* 29957 */ // Label 640: @29957 |
| 10781 | /* 29957 */ GIM_Try, /*On fail goto*//*Label 641*/ GIMT_Encode4(30015), // Rule ID 5334 // |
| 10782 | /* 29962 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), |
| 10783 | /* 29965 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 10784 | /* 29968 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10785 | /* 29972 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10786 | /* 29976 */ // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v16i8] }:$src) => (MVE_VREV64_8:{ *:[v2i64] } MQPR:{ *:[v16i8] }:$src) |
| 10787 | /* 29976 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 10788 | /* 29979 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10789 | /* 29983 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10790 | /* 29988 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_8), |
| 10791 | /* 29991 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 10792 | /* 29993 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10793 | /* 29995 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 10794 | /* 29998 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10795 | /* 30004 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10796 | /* 30010 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10797 | /* 30013 */ GIR_RootConstrainSelectedInstOperands, |
| 10798 | /* 30014 */ // GIR_Coverage, 5334, |
| 10799 | /* 30014 */ GIR_EraseRootFromParent_Done, |
| 10800 | /* 30015 */ // Label 641: @30015 |
| 10801 | /* 30015 */ GIM_Reject, |
| 10802 | /* 30016 */ // Label 544: @30016 |
| 10803 | /* 30016 */ GIM_Try, /*On fail goto*//*Label 642*/ GIMT_Encode4(30048), // Rule ID 2724 // |
| 10804 | /* 30021 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 10805 | /* 30024 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 10806 | /* 30027 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10807 | /* 30031 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10808 | /* 30035 */ // (bitconvert:{ *:[v4i16] } DPR:{ *:[v4f16] }:$src) => DPR:{ *:[v4i16] }:$src |
| 10809 | /* 30035 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10810 | /* 30038 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 10811 | /* 30040 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10812 | /* 30042 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 10813 | /* 30047 */ // GIR_Coverage, 2724, |
| 10814 | /* 30047 */ GIR_EraseRootFromParent_Done, |
| 10815 | /* 30048 */ // Label 642: @30048 |
| 10816 | /* 30048 */ GIM_Try, /*On fail goto*//*Label 643*/ GIMT_Encode4(30080), // Rule ID 2725 // |
| 10817 | /* 30053 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 10818 | /* 30056 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 10819 | /* 30059 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10820 | /* 30063 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10821 | /* 30067 */ // (bitconvert:{ *:[v4f16] } DPR:{ *:[v4i16] }:$src) => DPR:{ *:[v4f16] }:$src |
| 10822 | /* 30067 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10823 | /* 30070 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 10824 | /* 30072 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10825 | /* 30074 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 10826 | /* 30079 */ // GIR_Coverage, 2725, |
| 10827 | /* 30079 */ GIR_EraseRootFromParent_Done, |
| 10828 | /* 30080 */ // Label 643: @30080 |
| 10829 | /* 30080 */ GIM_Try, /*On fail goto*//*Label 644*/ GIMT_Encode4(30112), // Rule ID 2752 // |
| 10830 | /* 30085 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 10831 | /* 30088 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 10832 | /* 30091 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10833 | /* 30095 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10834 | /* 30099 */ // (bitconvert:{ *:[v4f16] } DPR:{ *:[f64] }:$src) => DPR:{ *:[v4f16] }:$src |
| 10835 | /* 30099 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10836 | /* 30102 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 10837 | /* 30104 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10838 | /* 30106 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 10839 | /* 30111 */ // GIR_Coverage, 2752, |
| 10840 | /* 30111 */ GIR_EraseRootFromParent_Done, |
| 10841 | /* 30112 */ // Label 644: @30112 |
| 10842 | /* 30112 */ GIM_Try, /*On fail goto*//*Label 645*/ GIMT_Encode4(30144), // Rule ID 2753 // |
| 10843 | /* 30117 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 10844 | /* 30120 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 10845 | /* 30123 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10846 | /* 30127 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10847 | /* 30131 */ // (bitconvert:{ *:[v4f16] } DPR:{ *:[v1i64] }:$src) => DPR:{ *:[v4f16] }:$src |
| 10848 | /* 30131 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10849 | /* 30134 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 10850 | /* 30136 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10851 | /* 30138 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 10852 | /* 30143 */ // GIR_Coverage, 2753, |
| 10853 | /* 30143 */ GIR_EraseRootFromParent_Done, |
| 10854 | /* 30144 */ // Label 645: @30144 |
| 10855 | /* 30144 */ GIM_Try, /*On fail goto*//*Label 646*/ GIMT_Encode4(30176), // Rule ID 2754 // |
| 10856 | /* 30149 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 10857 | /* 30152 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 10858 | /* 30155 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10859 | /* 30159 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10860 | /* 30163 */ // (bitconvert:{ *:[v4f16] } DPR:{ *:[v2f32] }:$src) => DPR:{ *:[v4f16] }:$src |
| 10861 | /* 30163 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10862 | /* 30166 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 10863 | /* 30168 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10864 | /* 30170 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 10865 | /* 30175 */ // GIR_Coverage, 2754, |
| 10866 | /* 30175 */ GIR_EraseRootFromParent_Done, |
| 10867 | /* 30176 */ // Label 646: @30176 |
| 10868 | /* 30176 */ GIM_Try, /*On fail goto*//*Label 647*/ GIMT_Encode4(30208), // Rule ID 2755 // |
| 10869 | /* 30181 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 10870 | /* 30184 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 10871 | /* 30187 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10872 | /* 30191 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10873 | /* 30195 */ // (bitconvert:{ *:[v4f16] } DPR:{ *:[v2i32] }:$src) => DPR:{ *:[v4f16] }:$src |
| 10874 | /* 30195 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10875 | /* 30198 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 10876 | /* 30200 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10877 | /* 30202 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 10878 | /* 30207 */ // GIR_Coverage, 2755, |
| 10879 | /* 30207 */ GIR_EraseRootFromParent_Done, |
| 10880 | /* 30208 */ // Label 647: @30208 |
| 10881 | /* 30208 */ GIM_Try, /*On fail goto*//*Label 648*/ GIMT_Encode4(30240), // Rule ID 2756 // |
| 10882 | /* 30213 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 10883 | /* 30216 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 10884 | /* 30219 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10885 | /* 30223 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10886 | /* 30227 */ // (bitconvert:{ *:[v4f16] } DPR:{ *:[v8i8] }:$src) => DPR:{ *:[v4f16] }:$src |
| 10887 | /* 30227 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10888 | /* 30230 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 10889 | /* 30232 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10890 | /* 30234 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 10891 | /* 30239 */ // GIR_Coverage, 2756, |
| 10892 | /* 30239 */ GIR_EraseRootFromParent_Done, |
| 10893 | /* 30240 */ // Label 648: @30240 |
| 10894 | /* 30240 */ GIM_Try, /*On fail goto*//*Label 649*/ GIMT_Encode4(30272), // Rule ID 2757 // |
| 10895 | /* 30245 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 10896 | /* 30248 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 10897 | /* 30251 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10898 | /* 30255 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10899 | /* 30259 */ // (bitconvert:{ *:[v4i16] } DPR:{ *:[f64] }:$src) => DPR:{ *:[v4i16] }:$src |
| 10900 | /* 30259 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10901 | /* 30262 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 10902 | /* 30264 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10903 | /* 30266 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 10904 | /* 30271 */ // GIR_Coverage, 2757, |
| 10905 | /* 30271 */ GIR_EraseRootFromParent_Done, |
| 10906 | /* 30272 */ // Label 649: @30272 |
| 10907 | /* 30272 */ GIM_Try, /*On fail goto*//*Label 650*/ GIMT_Encode4(30304), // Rule ID 2758 // |
| 10908 | /* 30277 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 10909 | /* 30280 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 10910 | /* 30283 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10911 | /* 30287 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10912 | /* 30291 */ // (bitconvert:{ *:[v4i16] } DPR:{ *:[v1i64] }:$src) => DPR:{ *:[v4i16] }:$src |
| 10913 | /* 30291 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10914 | /* 30294 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 10915 | /* 30296 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10916 | /* 30298 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 10917 | /* 30303 */ // GIR_Coverage, 2758, |
| 10918 | /* 30303 */ GIR_EraseRootFromParent_Done, |
| 10919 | /* 30304 */ // Label 650: @30304 |
| 10920 | /* 30304 */ GIM_Try, /*On fail goto*//*Label 651*/ GIMT_Encode4(30336), // Rule ID 2759 // |
| 10921 | /* 30309 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 10922 | /* 30312 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 10923 | /* 30315 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10924 | /* 30319 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10925 | /* 30323 */ // (bitconvert:{ *:[v4i16] } DPR:{ *:[v2f32] }:$src) => DPR:{ *:[v4i16] }:$src |
| 10926 | /* 30323 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10927 | /* 30326 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 10928 | /* 30328 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10929 | /* 30330 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 10930 | /* 30335 */ // GIR_Coverage, 2759, |
| 10931 | /* 30335 */ GIR_EraseRootFromParent_Done, |
| 10932 | /* 30336 */ // Label 651: @30336 |
| 10933 | /* 30336 */ GIM_Try, /*On fail goto*//*Label 652*/ GIMT_Encode4(30368), // Rule ID 2760 // |
| 10934 | /* 30341 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 10935 | /* 30344 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 10936 | /* 30347 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10937 | /* 30351 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10938 | /* 30355 */ // (bitconvert:{ *:[v4i16] } DPR:{ *:[v2i32] }:$src) => DPR:{ *:[v4i16] }:$src |
| 10939 | /* 30355 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10940 | /* 30358 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 10941 | /* 30360 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10942 | /* 30362 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 10943 | /* 30367 */ // GIR_Coverage, 2760, |
| 10944 | /* 30367 */ GIR_EraseRootFromParent_Done, |
| 10945 | /* 30368 */ // Label 652: @30368 |
| 10946 | /* 30368 */ GIM_Try, /*On fail goto*//*Label 653*/ GIMT_Encode4(30400), // Rule ID 2761 // |
| 10947 | /* 30373 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 10948 | /* 30376 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 10949 | /* 30379 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10950 | /* 30383 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10951 | /* 30387 */ // (bitconvert:{ *:[v4i16] } DPR:{ *:[v8i8] }:$src) => DPR:{ *:[v4i16] }:$src |
| 10952 | /* 30387 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10953 | /* 30390 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 10954 | /* 30392 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10955 | /* 30394 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 10956 | /* 30399 */ // GIR_Coverage, 2761, |
| 10957 | /* 30399 */ GIR_EraseRootFromParent_Done, |
| 10958 | /* 30400 */ // Label 653: @30400 |
| 10959 | /* 30400 */ GIM_Try, /*On fail goto*//*Label 654*/ GIMT_Encode4(30437), // Rule ID 2824 // |
| 10960 | /* 30405 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 10961 | /* 30408 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 10962 | /* 30411 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10963 | /* 30415 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10964 | /* 30419 */ // (bitconvert:{ *:[v4f16] } DPR:{ *:[f64] }:$src) => (VREV64d16:{ *:[v4f16] } DPR:{ *:[f64] }:$src) |
| 10965 | /* 30419 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d16), |
| 10966 | /* 30422 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 10967 | /* 30424 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10968 | /* 30426 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 10969 | /* 30429 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10970 | /* 30435 */ GIR_RootConstrainSelectedInstOperands, |
| 10971 | /* 30436 */ // GIR_Coverage, 2824, |
| 10972 | /* 30436 */ GIR_EraseRootFromParent_Done, |
| 10973 | /* 30437 */ // Label 654: @30437 |
| 10974 | /* 30437 */ GIM_Try, /*On fail goto*//*Label 655*/ GIMT_Encode4(30474), // Rule ID 2825 // |
| 10975 | /* 30442 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 10976 | /* 30445 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 10977 | /* 30448 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10978 | /* 30452 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10979 | /* 30456 */ // (bitconvert:{ *:[v4f16] } DPR:{ *:[v1i64] }:$src) => (VREV64d16:{ *:[v4f16] } DPR:{ *:[v1i64] }:$src) |
| 10980 | /* 30456 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d16), |
| 10981 | /* 30459 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 10982 | /* 30461 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10983 | /* 30463 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 10984 | /* 30466 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10985 | /* 30472 */ GIR_RootConstrainSelectedInstOperands, |
| 10986 | /* 30473 */ // GIR_Coverage, 2825, |
| 10987 | /* 30473 */ GIR_EraseRootFromParent_Done, |
| 10988 | /* 30474 */ // Label 655: @30474 |
| 10989 | /* 30474 */ GIM_Try, /*On fail goto*//*Label 656*/ GIMT_Encode4(30511), // Rule ID 2826 // |
| 10990 | /* 30479 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 10991 | /* 30482 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 10992 | /* 30485 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10993 | /* 30489 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10994 | /* 30493 */ // (bitconvert:{ *:[v4f16] } DPR:{ *:[v2f32] }:$src) => (VREV32d16:{ *:[v4f16] } DPR:{ *:[v2f32] }:$src) |
| 10995 | /* 30493 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d16), |
| 10996 | /* 30496 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 10997 | /* 30498 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10998 | /* 30500 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 10999 | /* 30503 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11000 | /* 30509 */ GIR_RootConstrainSelectedInstOperands, |
| 11001 | /* 30510 */ // GIR_Coverage, 2826, |
| 11002 | /* 30510 */ GIR_EraseRootFromParent_Done, |
| 11003 | /* 30511 */ // Label 656: @30511 |
| 11004 | /* 30511 */ GIM_Try, /*On fail goto*//*Label 657*/ GIMT_Encode4(30548), // Rule ID 2827 // |
| 11005 | /* 30516 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 11006 | /* 30519 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 11007 | /* 30522 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11008 | /* 30526 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11009 | /* 30530 */ // (bitconvert:{ *:[v4f16] } DPR:{ *:[v2i32] }:$src) => (VREV32d16:{ *:[v4f16] } DPR:{ *:[v2i32] }:$src) |
| 11010 | /* 30530 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d16), |
| 11011 | /* 30533 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11012 | /* 30535 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11013 | /* 30537 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11014 | /* 30540 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11015 | /* 30546 */ GIR_RootConstrainSelectedInstOperands, |
| 11016 | /* 30547 */ // GIR_Coverage, 2827, |
| 11017 | /* 30547 */ GIR_EraseRootFromParent_Done, |
| 11018 | /* 30548 */ // Label 657: @30548 |
| 11019 | /* 30548 */ GIM_Try, /*On fail goto*//*Label 658*/ GIMT_Encode4(30585), // Rule ID 2828 // |
| 11020 | /* 30553 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 11021 | /* 30556 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 11022 | /* 30559 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11023 | /* 30563 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11024 | /* 30567 */ // (bitconvert:{ *:[v4f16] } DPR:{ *:[v8i8] }:$src) => (VREV16d8:{ *:[v4f16] } DPR:{ *:[v8i8] }:$src) |
| 11025 | /* 30567 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV16d8), |
| 11026 | /* 30570 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11027 | /* 30572 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11028 | /* 30574 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11029 | /* 30577 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11030 | /* 30583 */ GIR_RootConstrainSelectedInstOperands, |
| 11031 | /* 30584 */ // GIR_Coverage, 2828, |
| 11032 | /* 30584 */ GIR_EraseRootFromParent_Done, |
| 11033 | /* 30585 */ // Label 658: @30585 |
| 11034 | /* 30585 */ GIM_Try, /*On fail goto*//*Label 659*/ GIMT_Encode4(30622), // Rule ID 2829 // |
| 11035 | /* 30590 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 11036 | /* 30593 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 11037 | /* 30596 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11038 | /* 30600 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11039 | /* 30604 */ // (bitconvert:{ *:[v4i16] } DPR:{ *:[f64] }:$src) => (VREV64d16:{ *:[v4i16] } DPR:{ *:[f64] }:$src) |
| 11040 | /* 30604 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d16), |
| 11041 | /* 30607 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11042 | /* 30609 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11043 | /* 30611 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11044 | /* 30614 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11045 | /* 30620 */ GIR_RootConstrainSelectedInstOperands, |
| 11046 | /* 30621 */ // GIR_Coverage, 2829, |
| 11047 | /* 30621 */ GIR_EraseRootFromParent_Done, |
| 11048 | /* 30622 */ // Label 659: @30622 |
| 11049 | /* 30622 */ GIM_Try, /*On fail goto*//*Label 660*/ GIMT_Encode4(30659), // Rule ID 2830 // |
| 11050 | /* 30627 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 11051 | /* 30630 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 11052 | /* 30633 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11053 | /* 30637 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11054 | /* 30641 */ // (bitconvert:{ *:[v4i16] } DPR:{ *:[v1i64] }:$src) => (VREV64d16:{ *:[v4i16] } DPR:{ *:[v1i64] }:$src) |
| 11055 | /* 30641 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d16), |
| 11056 | /* 30644 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11057 | /* 30646 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11058 | /* 30648 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11059 | /* 30651 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11060 | /* 30657 */ GIR_RootConstrainSelectedInstOperands, |
| 11061 | /* 30658 */ // GIR_Coverage, 2830, |
| 11062 | /* 30658 */ GIR_EraseRootFromParent_Done, |
| 11063 | /* 30659 */ // Label 660: @30659 |
| 11064 | /* 30659 */ GIM_Try, /*On fail goto*//*Label 661*/ GIMT_Encode4(30696), // Rule ID 2831 // |
| 11065 | /* 30664 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 11066 | /* 30667 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 11067 | /* 30670 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11068 | /* 30674 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11069 | /* 30678 */ // (bitconvert:{ *:[v4i16] } DPR:{ *:[v2f32] }:$src) => (VREV32d16:{ *:[v4i16] } DPR:{ *:[v2f32] }:$src) |
| 11070 | /* 30678 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d16), |
| 11071 | /* 30681 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11072 | /* 30683 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11073 | /* 30685 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11074 | /* 30688 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11075 | /* 30694 */ GIR_RootConstrainSelectedInstOperands, |
| 11076 | /* 30695 */ // GIR_Coverage, 2831, |
| 11077 | /* 30695 */ GIR_EraseRootFromParent_Done, |
| 11078 | /* 30696 */ // Label 661: @30696 |
| 11079 | /* 30696 */ GIM_Try, /*On fail goto*//*Label 662*/ GIMT_Encode4(30733), // Rule ID 2832 // |
| 11080 | /* 30701 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 11081 | /* 30704 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 11082 | /* 30707 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11083 | /* 30711 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11084 | /* 30715 */ // (bitconvert:{ *:[v4i16] } DPR:{ *:[v2i32] }:$src) => (VREV32d16:{ *:[v4i16] } DPR:{ *:[v2i32] }:$src) |
| 11085 | /* 30715 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d16), |
| 11086 | /* 30718 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11087 | /* 30720 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11088 | /* 30722 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11089 | /* 30725 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11090 | /* 30731 */ GIR_RootConstrainSelectedInstOperands, |
| 11091 | /* 30732 */ // GIR_Coverage, 2832, |
| 11092 | /* 30732 */ GIR_EraseRootFromParent_Done, |
| 11093 | /* 30733 */ // Label 662: @30733 |
| 11094 | /* 30733 */ GIM_Try, /*On fail goto*//*Label 663*/ GIMT_Encode4(30770), // Rule ID 2833 // |
| 11095 | /* 30738 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 11096 | /* 30741 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 11097 | /* 30744 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11098 | /* 30748 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11099 | /* 30752 */ // (bitconvert:{ *:[v4i16] } DPR:{ *:[v8i8] }:$src) => (VREV16d8:{ *:[v4i16] } DPR:{ *:[v8i8] }:$src) |
| 11100 | /* 30752 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV16d8), |
| 11101 | /* 30755 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11102 | /* 30757 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11103 | /* 30759 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11104 | /* 30762 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11105 | /* 30768 */ GIR_RootConstrainSelectedInstOperands, |
| 11106 | /* 30769 */ // GIR_Coverage, 2833, |
| 11107 | /* 30769 */ GIR_EraseRootFromParent_Done, |
| 11108 | /* 30770 */ // Label 663: @30770 |
| 11109 | /* 30770 */ GIM_Reject, |
| 11110 | /* 30771 */ // Label 545: @30771 |
| 11111 | /* 30771 */ GIM_Try, /*On fail goto*//*Label 664*/ GIMT_Encode4(30803), // Rule ID 2728 // |
| 11112 | /* 30776 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 11113 | /* 30779 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 11114 | /* 30782 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11115 | /* 30786 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11116 | /* 30790 */ // (bitconvert:{ *:[v4i32] } QPR:{ *:[v4f32] }:$src) => QPR:{ *:[v4i32] }:$src |
| 11117 | /* 30790 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11118 | /* 30793 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11119 | /* 30795 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11120 | /* 30797 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 11121 | /* 30802 */ // GIR_Coverage, 2728, |
| 11122 | /* 30802 */ GIR_EraseRootFromParent_Done, |
| 11123 | /* 30803 */ // Label 664: @30803 |
| 11124 | /* 30803 */ GIM_Try, /*On fail goto*//*Label 665*/ GIMT_Encode4(30835), // Rule ID 2729 // |
| 11125 | /* 30808 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 11126 | /* 30811 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 11127 | /* 30814 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11128 | /* 30818 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11129 | /* 30822 */ // (bitconvert:{ *:[v4f32] } QPR:{ *:[v4i32] }:$src) => QPR:{ *:[v4f32] }:$src |
| 11130 | /* 30822 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11131 | /* 30825 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11132 | /* 30827 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11133 | /* 30829 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 11134 | /* 30834 */ // GIR_Coverage, 2729, |
| 11135 | /* 30834 */ GIR_EraseRootFromParent_Done, |
| 11136 | /* 30835 */ // Label 665: @30835 |
| 11137 | /* 30835 */ GIM_Try, /*On fail goto*//*Label 666*/ GIMT_Encode4(30867), // Rule ID 2778 // |
| 11138 | /* 30840 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 11139 | /* 30843 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 11140 | /* 30846 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11141 | /* 30850 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11142 | /* 30854 */ // (bitconvert:{ *:[v4f32] } QPR:{ *:[v2f64] }:$src) => QPR:{ *:[v4f32] }:$src |
| 11143 | /* 30854 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11144 | /* 30857 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11145 | /* 30859 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11146 | /* 30861 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 11147 | /* 30866 */ // GIR_Coverage, 2778, |
| 11148 | /* 30866 */ GIR_EraseRootFromParent_Done, |
| 11149 | /* 30867 */ // Label 666: @30867 |
| 11150 | /* 30867 */ GIM_Try, /*On fail goto*//*Label 667*/ GIMT_Encode4(30899), // Rule ID 2779 // |
| 11151 | /* 30872 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 11152 | /* 30875 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 11153 | /* 30878 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11154 | /* 30882 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11155 | /* 30886 */ // (bitconvert:{ *:[v4f32] } QPR:{ *:[v2i64] }:$src) => QPR:{ *:[v4f32] }:$src |
| 11156 | /* 30886 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11157 | /* 30889 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11158 | /* 30891 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11159 | /* 30893 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 11160 | /* 30898 */ // GIR_Coverage, 2779, |
| 11161 | /* 30898 */ GIR_EraseRootFromParent_Done, |
| 11162 | /* 30899 */ // Label 667: @30899 |
| 11163 | /* 30899 */ GIM_Try, /*On fail goto*//*Label 668*/ GIMT_Encode4(30931), // Rule ID 2780 // |
| 11164 | /* 30904 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 11165 | /* 30907 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 11166 | /* 30910 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11167 | /* 30914 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11168 | /* 30918 */ // (bitconvert:{ *:[v4f32] } QPR:{ *:[v8f16] }:$src) => QPR:{ *:[v4f32] }:$src |
| 11169 | /* 30918 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11170 | /* 30921 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11171 | /* 30923 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11172 | /* 30925 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 11173 | /* 30930 */ // GIR_Coverage, 2780, |
| 11174 | /* 30930 */ GIR_EraseRootFromParent_Done, |
| 11175 | /* 30931 */ // Label 668: @30931 |
| 11176 | /* 30931 */ GIM_Try, /*On fail goto*//*Label 669*/ GIMT_Encode4(30963), // Rule ID 2781 // |
| 11177 | /* 30936 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 11178 | /* 30939 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 11179 | /* 30942 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11180 | /* 30946 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11181 | /* 30950 */ // (bitconvert:{ *:[v4f32] } QPR:{ *:[v8i16] }:$src) => QPR:{ *:[v4f32] }:$src |
| 11182 | /* 30950 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11183 | /* 30953 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11184 | /* 30955 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11185 | /* 30957 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 11186 | /* 30962 */ // GIR_Coverage, 2781, |
| 11187 | /* 30962 */ GIR_EraseRootFromParent_Done, |
| 11188 | /* 30963 */ // Label 669: @30963 |
| 11189 | /* 30963 */ GIM_Try, /*On fail goto*//*Label 670*/ GIMT_Encode4(30995), // Rule ID 2782 // |
| 11190 | /* 30968 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 11191 | /* 30971 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 11192 | /* 30974 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11193 | /* 30978 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11194 | /* 30982 */ // (bitconvert:{ *:[v4f32] } QPR:{ *:[v16i8] }:$src) => QPR:{ *:[v4f32] }:$src |
| 11195 | /* 30982 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11196 | /* 30985 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11197 | /* 30987 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11198 | /* 30989 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 11199 | /* 30994 */ // GIR_Coverage, 2782, |
| 11200 | /* 30994 */ GIR_EraseRootFromParent_Done, |
| 11201 | /* 30995 */ // Label 670: @30995 |
| 11202 | /* 30995 */ GIM_Try, /*On fail goto*//*Label 671*/ GIMT_Encode4(31027), // Rule ID 2783 // |
| 11203 | /* 31000 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 11204 | /* 31003 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 11205 | /* 31006 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11206 | /* 31010 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11207 | /* 31014 */ // (bitconvert:{ *:[v4i32] } QPR:{ *:[v2f64] }:$src) => QPR:{ *:[v4i32] }:$src |
| 11208 | /* 31014 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11209 | /* 31017 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11210 | /* 31019 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11211 | /* 31021 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 11212 | /* 31026 */ // GIR_Coverage, 2783, |
| 11213 | /* 31026 */ GIR_EraseRootFromParent_Done, |
| 11214 | /* 31027 */ // Label 671: @31027 |
| 11215 | /* 31027 */ GIM_Try, /*On fail goto*//*Label 672*/ GIMT_Encode4(31059), // Rule ID 2784 // |
| 11216 | /* 31032 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 11217 | /* 31035 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 11218 | /* 31038 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11219 | /* 31042 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11220 | /* 31046 */ // (bitconvert:{ *:[v4i32] } QPR:{ *:[v2i64] }:$src) => QPR:{ *:[v4i32] }:$src |
| 11221 | /* 31046 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11222 | /* 31049 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11223 | /* 31051 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11224 | /* 31053 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 11225 | /* 31058 */ // GIR_Coverage, 2784, |
| 11226 | /* 31058 */ GIR_EraseRootFromParent_Done, |
| 11227 | /* 31059 */ // Label 672: @31059 |
| 11228 | /* 31059 */ GIM_Try, /*On fail goto*//*Label 673*/ GIMT_Encode4(31091), // Rule ID 2785 // |
| 11229 | /* 31064 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 11230 | /* 31067 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 11231 | /* 31070 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11232 | /* 31074 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11233 | /* 31078 */ // (bitconvert:{ *:[v4i32] } QPR:{ *:[v8f16] }:$src) => QPR:{ *:[v4i32] }:$src |
| 11234 | /* 31078 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11235 | /* 31081 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11236 | /* 31083 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11237 | /* 31085 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 11238 | /* 31090 */ // GIR_Coverage, 2785, |
| 11239 | /* 31090 */ GIR_EraseRootFromParent_Done, |
| 11240 | /* 31091 */ // Label 673: @31091 |
| 11241 | /* 31091 */ GIM_Try, /*On fail goto*//*Label 674*/ GIMT_Encode4(31123), // Rule ID 2786 // |
| 11242 | /* 31096 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 11243 | /* 31099 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 11244 | /* 31102 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11245 | /* 31106 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11246 | /* 31110 */ // (bitconvert:{ *:[v4i32] } QPR:{ *:[v8i16] }:$src) => QPR:{ *:[v4i32] }:$src |
| 11247 | /* 31110 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11248 | /* 31113 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11249 | /* 31115 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11250 | /* 31117 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 11251 | /* 31122 */ // GIR_Coverage, 2786, |
| 11252 | /* 31122 */ GIR_EraseRootFromParent_Done, |
| 11253 | /* 31123 */ // Label 674: @31123 |
| 11254 | /* 31123 */ GIM_Try, /*On fail goto*//*Label 675*/ GIMT_Encode4(31155), // Rule ID 2787 // |
| 11255 | /* 31128 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 11256 | /* 31131 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 11257 | /* 31134 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11258 | /* 31138 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11259 | /* 31142 */ // (bitconvert:{ *:[v4i32] } QPR:{ *:[v16i8] }:$src) => QPR:{ *:[v4i32] }:$src |
| 11260 | /* 31142 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11261 | /* 31145 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11262 | /* 31147 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11263 | /* 31149 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 11264 | /* 31154 */ // GIR_Coverage, 2787, |
| 11265 | /* 31154 */ GIR_EraseRootFromParent_Done, |
| 11266 | /* 31155 */ // Label 675: @31155 |
| 11267 | /* 31155 */ GIM_Try, /*On fail goto*//*Label 676*/ GIMT_Encode4(31192), // Rule ID 2850 // |
| 11268 | /* 31160 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 11269 | /* 31163 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 11270 | /* 31166 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11271 | /* 31170 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11272 | /* 31174 */ // (bitconvert:{ *:[v4f32] } QPR:{ *:[v2f64] }:$src) => (VREV64q32:{ *:[v4f32] } QPR:{ *:[v2f64] }:$src) |
| 11273 | /* 31174 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q32), |
| 11274 | /* 31177 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11275 | /* 31179 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11276 | /* 31181 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11277 | /* 31184 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11278 | /* 31190 */ GIR_RootConstrainSelectedInstOperands, |
| 11279 | /* 31191 */ // GIR_Coverage, 2850, |
| 11280 | /* 31191 */ GIR_EraseRootFromParent_Done, |
| 11281 | /* 31192 */ // Label 676: @31192 |
| 11282 | /* 31192 */ GIM_Try, /*On fail goto*//*Label 677*/ GIMT_Encode4(31229), // Rule ID 2851 // |
| 11283 | /* 31197 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 11284 | /* 31200 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 11285 | /* 31203 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11286 | /* 31207 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11287 | /* 31211 */ // (bitconvert:{ *:[v4f32] } QPR:{ *:[v2i64] }:$src) => (VREV64q32:{ *:[v4f32] } QPR:{ *:[v2i64] }:$src) |
| 11288 | /* 31211 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q32), |
| 11289 | /* 31214 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11290 | /* 31216 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11291 | /* 31218 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11292 | /* 31221 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11293 | /* 31227 */ GIR_RootConstrainSelectedInstOperands, |
| 11294 | /* 31228 */ // GIR_Coverage, 2851, |
| 11295 | /* 31228 */ GIR_EraseRootFromParent_Done, |
| 11296 | /* 31229 */ // Label 677: @31229 |
| 11297 | /* 31229 */ GIM_Try, /*On fail goto*//*Label 678*/ GIMT_Encode4(31266), // Rule ID 2852 // |
| 11298 | /* 31234 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 11299 | /* 31237 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 11300 | /* 31240 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11301 | /* 31244 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11302 | /* 31248 */ // (bitconvert:{ *:[v4f32] } QPR:{ *:[v8f16] }:$src) => (VREV32q16:{ *:[v4f32] } QPR:{ *:[v8f16] }:$src) |
| 11303 | /* 31248 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q16), |
| 11304 | /* 31251 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11305 | /* 31253 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11306 | /* 31255 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11307 | /* 31258 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11308 | /* 31264 */ GIR_RootConstrainSelectedInstOperands, |
| 11309 | /* 31265 */ // GIR_Coverage, 2852, |
| 11310 | /* 31265 */ GIR_EraseRootFromParent_Done, |
| 11311 | /* 31266 */ // Label 678: @31266 |
| 11312 | /* 31266 */ GIM_Try, /*On fail goto*//*Label 679*/ GIMT_Encode4(31303), // Rule ID 2853 // |
| 11313 | /* 31271 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 11314 | /* 31274 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 11315 | /* 31277 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11316 | /* 31281 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11317 | /* 31285 */ // (bitconvert:{ *:[v4f32] } QPR:{ *:[v8i16] }:$src) => (VREV32q16:{ *:[v4f32] } QPR:{ *:[v8i16] }:$src) |
| 11318 | /* 31285 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q16), |
| 11319 | /* 31288 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11320 | /* 31290 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11321 | /* 31292 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11322 | /* 31295 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11323 | /* 31301 */ GIR_RootConstrainSelectedInstOperands, |
| 11324 | /* 31302 */ // GIR_Coverage, 2853, |
| 11325 | /* 31302 */ GIR_EraseRootFromParent_Done, |
| 11326 | /* 31303 */ // Label 679: @31303 |
| 11327 | /* 31303 */ GIM_Try, /*On fail goto*//*Label 680*/ GIMT_Encode4(31340), // Rule ID 2854 // |
| 11328 | /* 31308 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 11329 | /* 31311 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 11330 | /* 31314 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11331 | /* 31318 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11332 | /* 31322 */ // (bitconvert:{ *:[v4f32] } QPR:{ *:[v16i8] }:$src) => (VREV32q8:{ *:[v4f32] } QPR:{ *:[v16i8] }:$src) |
| 11333 | /* 31322 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q8), |
| 11334 | /* 31325 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11335 | /* 31327 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11336 | /* 31329 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11337 | /* 31332 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11338 | /* 31338 */ GIR_RootConstrainSelectedInstOperands, |
| 11339 | /* 31339 */ // GIR_Coverage, 2854, |
| 11340 | /* 31339 */ GIR_EraseRootFromParent_Done, |
| 11341 | /* 31340 */ // Label 680: @31340 |
| 11342 | /* 31340 */ GIM_Try, /*On fail goto*//*Label 681*/ GIMT_Encode4(31377), // Rule ID 2855 // |
| 11343 | /* 31345 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 11344 | /* 31348 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 11345 | /* 31351 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11346 | /* 31355 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11347 | /* 31359 */ // (bitconvert:{ *:[v4i32] } QPR:{ *:[v2f64] }:$src) => (VREV64q32:{ *:[v4i32] } QPR:{ *:[v2f64] }:$src) |
| 11348 | /* 31359 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q32), |
| 11349 | /* 31362 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11350 | /* 31364 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11351 | /* 31366 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11352 | /* 31369 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11353 | /* 31375 */ GIR_RootConstrainSelectedInstOperands, |
| 11354 | /* 31376 */ // GIR_Coverage, 2855, |
| 11355 | /* 31376 */ GIR_EraseRootFromParent_Done, |
| 11356 | /* 31377 */ // Label 681: @31377 |
| 11357 | /* 31377 */ GIM_Try, /*On fail goto*//*Label 682*/ GIMT_Encode4(31414), // Rule ID 2856 // |
| 11358 | /* 31382 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 11359 | /* 31385 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 11360 | /* 31388 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11361 | /* 31392 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11362 | /* 31396 */ // (bitconvert:{ *:[v4i32] } QPR:{ *:[v2i64] }:$src) => (VREV64q32:{ *:[v4i32] } QPR:{ *:[v2i64] }:$src) |
| 11363 | /* 31396 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q32), |
| 11364 | /* 31399 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11365 | /* 31401 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11366 | /* 31403 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11367 | /* 31406 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11368 | /* 31412 */ GIR_RootConstrainSelectedInstOperands, |
| 11369 | /* 31413 */ // GIR_Coverage, 2856, |
| 11370 | /* 31413 */ GIR_EraseRootFromParent_Done, |
| 11371 | /* 31414 */ // Label 682: @31414 |
| 11372 | /* 31414 */ GIM_Try, /*On fail goto*//*Label 683*/ GIMT_Encode4(31451), // Rule ID 2857 // |
| 11373 | /* 31419 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 11374 | /* 31422 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 11375 | /* 31425 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11376 | /* 31429 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11377 | /* 31433 */ // (bitconvert:{ *:[v4i32] } QPR:{ *:[v8f16] }:$src) => (VREV32q16:{ *:[v4i32] } QPR:{ *:[v8f16] }:$src) |
| 11378 | /* 31433 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q16), |
| 11379 | /* 31436 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11380 | /* 31438 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11381 | /* 31440 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11382 | /* 31443 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11383 | /* 31449 */ GIR_RootConstrainSelectedInstOperands, |
| 11384 | /* 31450 */ // GIR_Coverage, 2857, |
| 11385 | /* 31450 */ GIR_EraseRootFromParent_Done, |
| 11386 | /* 31451 */ // Label 683: @31451 |
| 11387 | /* 31451 */ GIM_Try, /*On fail goto*//*Label 684*/ GIMT_Encode4(31488), // Rule ID 2858 // |
| 11388 | /* 31456 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 11389 | /* 31459 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 11390 | /* 31462 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11391 | /* 31466 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11392 | /* 31470 */ // (bitconvert:{ *:[v4i32] } QPR:{ *:[v8i16] }:$src) => (VREV32q16:{ *:[v4i32] } QPR:{ *:[v8i16] }:$src) |
| 11393 | /* 31470 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q16), |
| 11394 | /* 31473 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11395 | /* 31475 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11396 | /* 31477 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11397 | /* 31480 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11398 | /* 31486 */ GIR_RootConstrainSelectedInstOperands, |
| 11399 | /* 31487 */ // GIR_Coverage, 2858, |
| 11400 | /* 31487 */ GIR_EraseRootFromParent_Done, |
| 11401 | /* 31488 */ // Label 684: @31488 |
| 11402 | /* 31488 */ GIM_Try, /*On fail goto*//*Label 685*/ GIMT_Encode4(31525), // Rule ID 2859 // |
| 11403 | /* 31493 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 11404 | /* 31496 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 11405 | /* 31499 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11406 | /* 31503 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11407 | /* 31507 */ // (bitconvert:{ *:[v4i32] } QPR:{ *:[v16i8] }:$src) => (VREV32q8:{ *:[v4i32] } QPR:{ *:[v16i8] }:$src) |
| 11408 | /* 31507 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q8), |
| 11409 | /* 31510 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11410 | /* 31512 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11411 | /* 31514 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11412 | /* 31517 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11413 | /* 31523 */ GIR_RootConstrainSelectedInstOperands, |
| 11414 | /* 31524 */ // GIR_Coverage, 2859, |
| 11415 | /* 31524 */ GIR_EraseRootFromParent_Done, |
| 11416 | /* 31525 */ // Label 685: @31525 |
| 11417 | /* 31525 */ GIM_Try, /*On fail goto*//*Label 686*/ GIMT_Encode4(31557), // Rule ID 5285 // |
| 11418 | /* 31530 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 11419 | /* 31533 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 11420 | /* 31536 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11421 | /* 31540 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11422 | /* 31544 */ // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$src) => MQPR:{ *:[v4i32] }:$src |
| 11423 | /* 31544 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11424 | /* 31547 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11425 | /* 31549 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11426 | /* 31551 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 11427 | /* 31556 */ // GIR_Coverage, 5285, |
| 11428 | /* 31556 */ GIR_EraseRootFromParent_Done, |
| 11429 | /* 31557 */ // Label 686: @31557 |
| 11430 | /* 31557 */ GIM_Try, /*On fail goto*//*Label 687*/ GIMT_Encode4(31589), // Rule ID 5286 // |
| 11431 | /* 31562 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 11432 | /* 31565 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 11433 | /* 31568 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11434 | /* 31572 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11435 | /* 31576 */ // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$src) => MQPR:{ *:[v4f32] }:$src |
| 11436 | /* 31576 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11437 | /* 31579 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11438 | /* 31581 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11439 | /* 31583 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 11440 | /* 31588 */ // GIR_Coverage, 5286, |
| 11441 | /* 31588 */ GIR_EraseRootFromParent_Done, |
| 11442 | /* 31589 */ // Label 687: @31589 |
| 11443 | /* 31589 */ GIM_Try, /*On fail goto*//*Label 688*/ GIMT_Encode4(31621), // Rule ID 5299 // |
| 11444 | /* 31594 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), |
| 11445 | /* 31597 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 11446 | /* 31600 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11447 | /* 31604 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11448 | /* 31608 */ // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v2f64] }:$src) => MQPR:{ *:[v4f32] }:$src |
| 11449 | /* 31608 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11450 | /* 31611 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11451 | /* 31613 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11452 | /* 31615 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 11453 | /* 31620 */ // GIR_Coverage, 5299, |
| 11454 | /* 31620 */ GIR_EraseRootFromParent_Done, |
| 11455 | /* 31621 */ // Label 688: @31621 |
| 11456 | /* 31621 */ GIM_Try, /*On fail goto*//*Label 689*/ GIMT_Encode4(31653), // Rule ID 5300 // |
| 11457 | /* 31626 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), |
| 11458 | /* 31629 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 11459 | /* 31632 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11460 | /* 31636 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11461 | /* 31640 */ // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v2i64] }:$src) => MQPR:{ *:[v4f32] }:$src |
| 11462 | /* 31640 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11463 | /* 31643 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11464 | /* 31645 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11465 | /* 31647 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 11466 | /* 31652 */ // GIR_Coverage, 5300, |
| 11467 | /* 31652 */ GIR_EraseRootFromParent_Done, |
| 11468 | /* 31653 */ // Label 689: @31653 |
| 11469 | /* 31653 */ GIM_Try, /*On fail goto*//*Label 690*/ GIMT_Encode4(31685), // Rule ID 5301 // |
| 11470 | /* 31658 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), |
| 11471 | /* 31661 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 11472 | /* 31664 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11473 | /* 31668 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11474 | /* 31672 */ // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v8f16] }:$src) => MQPR:{ *:[v4f32] }:$src |
| 11475 | /* 31672 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11476 | /* 31675 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11477 | /* 31677 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11478 | /* 31679 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 11479 | /* 31684 */ // GIR_Coverage, 5301, |
| 11480 | /* 31684 */ GIR_EraseRootFromParent_Done, |
| 11481 | /* 31685 */ // Label 690: @31685 |
| 11482 | /* 31685 */ GIM_Try, /*On fail goto*//*Label 691*/ GIMT_Encode4(31717), // Rule ID 5302 // |
| 11483 | /* 31690 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), |
| 11484 | /* 31693 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 11485 | /* 31696 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11486 | /* 31700 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11487 | /* 31704 */ // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v8i16] }:$src) => MQPR:{ *:[v4f32] }:$src |
| 11488 | /* 31704 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11489 | /* 31707 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11490 | /* 31709 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11491 | /* 31711 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 11492 | /* 31716 */ // GIR_Coverage, 5302, |
| 11493 | /* 31716 */ GIR_EraseRootFromParent_Done, |
| 11494 | /* 31717 */ // Label 691: @31717 |
| 11495 | /* 31717 */ GIM_Try, /*On fail goto*//*Label 692*/ GIMT_Encode4(31749), // Rule ID 5303 // |
| 11496 | /* 31722 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), |
| 11497 | /* 31725 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 11498 | /* 31728 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11499 | /* 31732 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11500 | /* 31736 */ // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v16i8] }:$src) => MQPR:{ *:[v4f32] }:$src |
| 11501 | /* 31736 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11502 | /* 31739 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11503 | /* 31741 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11504 | /* 31743 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 11505 | /* 31748 */ // GIR_Coverage, 5303, |
| 11506 | /* 31748 */ GIR_EraseRootFromParent_Done, |
| 11507 | /* 31749 */ // Label 692: @31749 |
| 11508 | /* 31749 */ GIM_Try, /*On fail goto*//*Label 693*/ GIMT_Encode4(31781), // Rule ID 5304 // |
| 11509 | /* 31754 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), |
| 11510 | /* 31757 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 11511 | /* 31760 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11512 | /* 31764 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11513 | /* 31768 */ // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v2f64] }:$src) => MQPR:{ *:[v4i32] }:$src |
| 11514 | /* 31768 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11515 | /* 31771 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11516 | /* 31773 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11517 | /* 31775 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 11518 | /* 31780 */ // GIR_Coverage, 5304, |
| 11519 | /* 31780 */ GIR_EraseRootFromParent_Done, |
| 11520 | /* 31781 */ // Label 693: @31781 |
| 11521 | /* 31781 */ GIM_Try, /*On fail goto*//*Label 694*/ GIMT_Encode4(31813), // Rule ID 5305 // |
| 11522 | /* 31786 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), |
| 11523 | /* 31789 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 11524 | /* 31792 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11525 | /* 31796 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11526 | /* 31800 */ // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v2i64] }:$src) => MQPR:{ *:[v4i32] }:$src |
| 11527 | /* 31800 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11528 | /* 31803 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11529 | /* 31805 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11530 | /* 31807 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 11531 | /* 31812 */ // GIR_Coverage, 5305, |
| 11532 | /* 31812 */ GIR_EraseRootFromParent_Done, |
| 11533 | /* 31813 */ // Label 694: @31813 |
| 11534 | /* 31813 */ GIM_Try, /*On fail goto*//*Label 695*/ GIMT_Encode4(31845), // Rule ID 5306 // |
| 11535 | /* 31818 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), |
| 11536 | /* 31821 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 11537 | /* 31824 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11538 | /* 31828 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11539 | /* 31832 */ // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v8f16] }:$src) => MQPR:{ *:[v4i32] }:$src |
| 11540 | /* 31832 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11541 | /* 31835 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11542 | /* 31837 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11543 | /* 31839 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 11544 | /* 31844 */ // GIR_Coverage, 5306, |
| 11545 | /* 31844 */ GIR_EraseRootFromParent_Done, |
| 11546 | /* 31845 */ // Label 695: @31845 |
| 11547 | /* 31845 */ GIM_Try, /*On fail goto*//*Label 696*/ GIMT_Encode4(31877), // Rule ID 5307 // |
| 11548 | /* 31850 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), |
| 11549 | /* 31853 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 11550 | /* 31856 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11551 | /* 31860 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11552 | /* 31864 */ // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$src) => MQPR:{ *:[v4i32] }:$src |
| 11553 | /* 31864 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11554 | /* 31867 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11555 | /* 31869 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11556 | /* 31871 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 11557 | /* 31876 */ // GIR_Coverage, 5307, |
| 11558 | /* 31876 */ GIR_EraseRootFromParent_Done, |
| 11559 | /* 31877 */ // Label 696: @31877 |
| 11560 | /* 31877 */ GIM_Try, /*On fail goto*//*Label 697*/ GIMT_Encode4(31909), // Rule ID 5308 // |
| 11561 | /* 31882 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), |
| 11562 | /* 31885 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 11563 | /* 31888 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11564 | /* 31892 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11565 | /* 31896 */ // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v16i8] }:$src) => MQPR:{ *:[v4i32] }:$src |
| 11566 | /* 31896 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11567 | /* 31899 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11568 | /* 31901 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11569 | /* 31903 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 11570 | /* 31908 */ // GIR_Coverage, 5308, |
| 11571 | /* 31908 */ GIR_EraseRootFromParent_Done, |
| 11572 | /* 31909 */ // Label 697: @31909 |
| 11573 | /* 31909 */ GIM_Try, /*On fail goto*//*Label 698*/ GIMT_Encode4(31967), // Rule ID 5335 // |
| 11574 | /* 31914 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), |
| 11575 | /* 31917 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 11576 | /* 31920 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11577 | /* 31924 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11578 | /* 31928 */ // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v2f64] }:$src) => (MVE_VREV64_32:{ *:[v4f32] } MQPR:{ *:[v2f64] }:$src) |
| 11579 | /* 31928 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 11580 | /* 31931 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 11581 | /* 31935 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 11582 | /* 31940 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_32), |
| 11583 | /* 31943 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 11584 | /* 31945 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11585 | /* 31947 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 11586 | /* 31950 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11587 | /* 31956 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11588 | /* 31962 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 11589 | /* 31965 */ GIR_RootConstrainSelectedInstOperands, |
| 11590 | /* 31966 */ // GIR_Coverage, 5335, |
| 11591 | /* 31966 */ GIR_EraseRootFromParent_Done, |
| 11592 | /* 31967 */ // Label 698: @31967 |
| 11593 | /* 31967 */ GIM_Try, /*On fail goto*//*Label 699*/ GIMT_Encode4(32025), // Rule ID 5336 // |
| 11594 | /* 31972 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), |
| 11595 | /* 31975 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 11596 | /* 31978 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11597 | /* 31982 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11598 | /* 31986 */ // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v2i64] }:$src) => (MVE_VREV64_32:{ *:[v4f32] } MQPR:{ *:[v2i64] }:$src) |
| 11599 | /* 31986 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 11600 | /* 31989 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 11601 | /* 31993 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 11602 | /* 31998 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_32), |
| 11603 | /* 32001 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 11604 | /* 32003 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11605 | /* 32005 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 11606 | /* 32008 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11607 | /* 32014 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11608 | /* 32020 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 11609 | /* 32023 */ GIR_RootConstrainSelectedInstOperands, |
| 11610 | /* 32024 */ // GIR_Coverage, 5336, |
| 11611 | /* 32024 */ GIR_EraseRootFromParent_Done, |
| 11612 | /* 32025 */ // Label 699: @32025 |
| 11613 | /* 32025 */ GIM_Try, /*On fail goto*//*Label 700*/ GIMT_Encode4(32083), // Rule ID 5337 // |
| 11614 | /* 32030 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), |
| 11615 | /* 32033 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 11616 | /* 32036 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11617 | /* 32040 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11618 | /* 32044 */ // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v8f16] }:$src) => (MVE_VREV32_16:{ *:[v4f32] } MQPR:{ *:[v8f16] }:$src) |
| 11619 | /* 32044 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 11620 | /* 32047 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 11621 | /* 32051 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 11622 | /* 32056 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_16), |
| 11623 | /* 32059 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 11624 | /* 32061 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11625 | /* 32063 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 11626 | /* 32066 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11627 | /* 32072 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11628 | /* 32078 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 11629 | /* 32081 */ GIR_RootConstrainSelectedInstOperands, |
| 11630 | /* 32082 */ // GIR_Coverage, 5337, |
| 11631 | /* 32082 */ GIR_EraseRootFromParent_Done, |
| 11632 | /* 32083 */ // Label 700: @32083 |
| 11633 | /* 32083 */ GIM_Try, /*On fail goto*//*Label 701*/ GIMT_Encode4(32141), // Rule ID 5338 // |
| 11634 | /* 32088 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), |
| 11635 | /* 32091 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 11636 | /* 32094 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11637 | /* 32098 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11638 | /* 32102 */ // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v8i16] }:$src) => (MVE_VREV32_16:{ *:[v4f32] } MQPR:{ *:[v8i16] }:$src) |
| 11639 | /* 32102 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 11640 | /* 32105 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 11641 | /* 32109 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 11642 | /* 32114 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_16), |
| 11643 | /* 32117 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 11644 | /* 32119 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11645 | /* 32121 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 11646 | /* 32124 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11647 | /* 32130 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11648 | /* 32136 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 11649 | /* 32139 */ GIR_RootConstrainSelectedInstOperands, |
| 11650 | /* 32140 */ // GIR_Coverage, 5338, |
| 11651 | /* 32140 */ GIR_EraseRootFromParent_Done, |
| 11652 | /* 32141 */ // Label 701: @32141 |
| 11653 | /* 32141 */ GIM_Try, /*On fail goto*//*Label 702*/ GIMT_Encode4(32199), // Rule ID 5339 // |
| 11654 | /* 32146 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), |
| 11655 | /* 32149 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 11656 | /* 32152 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11657 | /* 32156 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11658 | /* 32160 */ // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v16i8] }:$src) => (MVE_VREV32_8:{ *:[v4f32] } MQPR:{ *:[v16i8] }:$src) |
| 11659 | /* 32160 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 11660 | /* 32163 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 11661 | /* 32167 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 11662 | /* 32172 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_8), |
| 11663 | /* 32175 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 11664 | /* 32177 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11665 | /* 32179 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 11666 | /* 32182 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11667 | /* 32188 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11668 | /* 32194 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 11669 | /* 32197 */ GIR_RootConstrainSelectedInstOperands, |
| 11670 | /* 32198 */ // GIR_Coverage, 5339, |
| 11671 | /* 32198 */ GIR_EraseRootFromParent_Done, |
| 11672 | /* 32199 */ // Label 702: @32199 |
| 11673 | /* 32199 */ GIM_Try, /*On fail goto*//*Label 703*/ GIMT_Encode4(32257), // Rule ID 5340 // |
| 11674 | /* 32204 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), |
| 11675 | /* 32207 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 11676 | /* 32210 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11677 | /* 32214 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11678 | /* 32218 */ // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v2f64] }:$src) => (MVE_VREV64_32:{ *:[v4i32] } MQPR:{ *:[v2f64] }:$src) |
| 11679 | /* 32218 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 11680 | /* 32221 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 11681 | /* 32225 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 11682 | /* 32230 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_32), |
| 11683 | /* 32233 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 11684 | /* 32235 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11685 | /* 32237 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 11686 | /* 32240 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11687 | /* 32246 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11688 | /* 32252 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 11689 | /* 32255 */ GIR_RootConstrainSelectedInstOperands, |
| 11690 | /* 32256 */ // GIR_Coverage, 5340, |
| 11691 | /* 32256 */ GIR_EraseRootFromParent_Done, |
| 11692 | /* 32257 */ // Label 703: @32257 |
| 11693 | /* 32257 */ GIM_Try, /*On fail goto*//*Label 704*/ GIMT_Encode4(32315), // Rule ID 5341 // |
| 11694 | /* 32262 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), |
| 11695 | /* 32265 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 11696 | /* 32268 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11697 | /* 32272 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11698 | /* 32276 */ // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v2i64] }:$src) => (MVE_VREV64_32:{ *:[v4i32] } MQPR:{ *:[v2i64] }:$src) |
| 11699 | /* 32276 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 11700 | /* 32279 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 11701 | /* 32283 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 11702 | /* 32288 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_32), |
| 11703 | /* 32291 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 11704 | /* 32293 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11705 | /* 32295 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 11706 | /* 32298 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11707 | /* 32304 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11708 | /* 32310 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 11709 | /* 32313 */ GIR_RootConstrainSelectedInstOperands, |
| 11710 | /* 32314 */ // GIR_Coverage, 5341, |
| 11711 | /* 32314 */ GIR_EraseRootFromParent_Done, |
| 11712 | /* 32315 */ // Label 704: @32315 |
| 11713 | /* 32315 */ GIM_Try, /*On fail goto*//*Label 705*/ GIMT_Encode4(32373), // Rule ID 5342 // |
| 11714 | /* 32320 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), |
| 11715 | /* 32323 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 11716 | /* 32326 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11717 | /* 32330 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11718 | /* 32334 */ // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v8f16] }:$src) => (MVE_VREV32_16:{ *:[v4i32] } MQPR:{ *:[v8f16] }:$src) |
| 11719 | /* 32334 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 11720 | /* 32337 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 11721 | /* 32341 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 11722 | /* 32346 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_16), |
| 11723 | /* 32349 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 11724 | /* 32351 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11725 | /* 32353 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 11726 | /* 32356 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11727 | /* 32362 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11728 | /* 32368 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 11729 | /* 32371 */ GIR_RootConstrainSelectedInstOperands, |
| 11730 | /* 32372 */ // GIR_Coverage, 5342, |
| 11731 | /* 32372 */ GIR_EraseRootFromParent_Done, |
| 11732 | /* 32373 */ // Label 705: @32373 |
| 11733 | /* 32373 */ GIM_Try, /*On fail goto*//*Label 706*/ GIMT_Encode4(32431), // Rule ID 5343 // |
| 11734 | /* 32378 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), |
| 11735 | /* 32381 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 11736 | /* 32384 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11737 | /* 32388 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11738 | /* 32392 */ // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$src) => (MVE_VREV32_16:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$src) |
| 11739 | /* 32392 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 11740 | /* 32395 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 11741 | /* 32399 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 11742 | /* 32404 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_16), |
| 11743 | /* 32407 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 11744 | /* 32409 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11745 | /* 32411 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 11746 | /* 32414 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11747 | /* 32420 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11748 | /* 32426 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 11749 | /* 32429 */ GIR_RootConstrainSelectedInstOperands, |
| 11750 | /* 32430 */ // GIR_Coverage, 5343, |
| 11751 | /* 32430 */ GIR_EraseRootFromParent_Done, |
| 11752 | /* 32431 */ // Label 706: @32431 |
| 11753 | /* 32431 */ GIM_Try, /*On fail goto*//*Label 707*/ GIMT_Encode4(32489), // Rule ID 5344 // |
| 11754 | /* 32436 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), |
| 11755 | /* 32439 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 11756 | /* 32442 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11757 | /* 32446 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11758 | /* 32450 */ // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v16i8] }:$src) => (MVE_VREV32_8:{ *:[v4i32] } MQPR:{ *:[v16i8] }:$src) |
| 11759 | /* 32450 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 11760 | /* 32453 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 11761 | /* 32457 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 11762 | /* 32462 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_8), |
| 11763 | /* 32465 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 11764 | /* 32467 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11765 | /* 32469 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 11766 | /* 32472 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11767 | /* 32478 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11768 | /* 32484 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 11769 | /* 32487 */ GIR_RootConstrainSelectedInstOperands, |
| 11770 | /* 32488 */ // GIR_Coverage, 5344, |
| 11771 | /* 32488 */ GIR_EraseRootFromParent_Done, |
| 11772 | /* 32489 */ // Label 707: @32489 |
| 11773 | /* 32489 */ GIM_Reject, |
| 11774 | /* 32490 */ // Label 546: @32490 |
| 11775 | /* 32490 */ GIM_Try, /*On fail goto*//*Label 708*/ GIMT_Encode4(32522), // Rule ID 2762 // |
| 11776 | /* 32495 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 11777 | /* 32498 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 11778 | /* 32501 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11779 | /* 32505 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11780 | /* 32509 */ // (bitconvert:{ *:[v8i8] } DPR:{ *:[f64] }:$src) => DPR:{ *:[v8i8] }:$src |
| 11781 | /* 32509 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11782 | /* 32512 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11783 | /* 32514 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11784 | /* 32516 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 11785 | /* 32521 */ // GIR_Coverage, 2762, |
| 11786 | /* 32521 */ GIR_EraseRootFromParent_Done, |
| 11787 | /* 32522 */ // Label 708: @32522 |
| 11788 | /* 32522 */ GIM_Try, /*On fail goto*//*Label 709*/ GIMT_Encode4(32554), // Rule ID 2763 // |
| 11789 | /* 32527 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 11790 | /* 32530 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 11791 | /* 32533 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11792 | /* 32537 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11793 | /* 32541 */ // (bitconvert:{ *:[v8i8] } DPR:{ *:[v1i64] }:$src) => DPR:{ *:[v8i8] }:$src |
| 11794 | /* 32541 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11795 | /* 32544 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11796 | /* 32546 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11797 | /* 32548 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 11798 | /* 32553 */ // GIR_Coverage, 2763, |
| 11799 | /* 32553 */ GIR_EraseRootFromParent_Done, |
| 11800 | /* 32554 */ // Label 709: @32554 |
| 11801 | /* 32554 */ GIM_Try, /*On fail goto*//*Label 710*/ GIMT_Encode4(32586), // Rule ID 2764 // |
| 11802 | /* 32559 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 11803 | /* 32562 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 11804 | /* 32565 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11805 | /* 32569 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11806 | /* 32573 */ // (bitconvert:{ *:[v8i8] } DPR:{ *:[v2f32] }:$src) => DPR:{ *:[v8i8] }:$src |
| 11807 | /* 32573 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11808 | /* 32576 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11809 | /* 32578 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11810 | /* 32580 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 11811 | /* 32585 */ // GIR_Coverage, 2764, |
| 11812 | /* 32585 */ GIR_EraseRootFromParent_Done, |
| 11813 | /* 32586 */ // Label 710: @32586 |
| 11814 | /* 32586 */ GIM_Try, /*On fail goto*//*Label 711*/ GIMT_Encode4(32618), // Rule ID 2765 // |
| 11815 | /* 32591 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 11816 | /* 32594 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 11817 | /* 32597 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11818 | /* 32601 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11819 | /* 32605 */ // (bitconvert:{ *:[v8i8] } DPR:{ *:[v2i32] }:$src) => DPR:{ *:[v8i8] }:$src |
| 11820 | /* 32605 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11821 | /* 32608 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11822 | /* 32610 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11823 | /* 32612 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 11824 | /* 32617 */ // GIR_Coverage, 2765, |
| 11825 | /* 32617 */ GIR_EraseRootFromParent_Done, |
| 11826 | /* 32618 */ // Label 711: @32618 |
| 11827 | /* 32618 */ GIM_Try, /*On fail goto*//*Label 712*/ GIMT_Encode4(32650), // Rule ID 2766 // |
| 11828 | /* 32623 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 11829 | /* 32626 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 11830 | /* 32629 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11831 | /* 32633 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11832 | /* 32637 */ // (bitconvert:{ *:[v8i8] } DPR:{ *:[v4f16] }:$src) => DPR:{ *:[v8i8] }:$src |
| 11833 | /* 32637 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11834 | /* 32640 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11835 | /* 32642 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11836 | /* 32644 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 11837 | /* 32649 */ // GIR_Coverage, 2766, |
| 11838 | /* 32649 */ GIR_EraseRootFromParent_Done, |
| 11839 | /* 32650 */ // Label 712: @32650 |
| 11840 | /* 32650 */ GIM_Try, /*On fail goto*//*Label 713*/ GIMT_Encode4(32682), // Rule ID 2767 // |
| 11841 | /* 32655 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 11842 | /* 32658 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 11843 | /* 32661 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11844 | /* 32665 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11845 | /* 32669 */ // (bitconvert:{ *:[v8i8] } DPR:{ *:[v4i16] }:$src) => DPR:{ *:[v8i8] }:$src |
| 11846 | /* 32669 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11847 | /* 32672 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11848 | /* 32674 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11849 | /* 32676 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 11850 | /* 32681 */ // GIR_Coverage, 2767, |
| 11851 | /* 32681 */ GIR_EraseRootFromParent_Done, |
| 11852 | /* 32682 */ // Label 713: @32682 |
| 11853 | /* 32682 */ GIM_Try, /*On fail goto*//*Label 714*/ GIMT_Encode4(32719), // Rule ID 2834 // |
| 11854 | /* 32687 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 11855 | /* 32690 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 11856 | /* 32693 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11857 | /* 32697 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11858 | /* 32701 */ // (bitconvert:{ *:[v8i8] } DPR:{ *:[f64] }:$src) => (VREV64d8:{ *:[v8i8] } DPR:{ *:[f64] }:$src) |
| 11859 | /* 32701 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d8), |
| 11860 | /* 32704 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11861 | /* 32706 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11862 | /* 32708 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11863 | /* 32711 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11864 | /* 32717 */ GIR_RootConstrainSelectedInstOperands, |
| 11865 | /* 32718 */ // GIR_Coverage, 2834, |
| 11866 | /* 32718 */ GIR_EraseRootFromParent_Done, |
| 11867 | /* 32719 */ // Label 714: @32719 |
| 11868 | /* 32719 */ GIM_Try, /*On fail goto*//*Label 715*/ GIMT_Encode4(32756), // Rule ID 2835 // |
| 11869 | /* 32724 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 11870 | /* 32727 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 11871 | /* 32730 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11872 | /* 32734 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11873 | /* 32738 */ // (bitconvert:{ *:[v8i8] } DPR:{ *:[v1i64] }:$src) => (VREV64d8:{ *:[v8i8] } DPR:{ *:[v1i64] }:$src) |
| 11874 | /* 32738 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d8), |
| 11875 | /* 32741 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11876 | /* 32743 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11877 | /* 32745 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11878 | /* 32748 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11879 | /* 32754 */ GIR_RootConstrainSelectedInstOperands, |
| 11880 | /* 32755 */ // GIR_Coverage, 2835, |
| 11881 | /* 32755 */ GIR_EraseRootFromParent_Done, |
| 11882 | /* 32756 */ // Label 715: @32756 |
| 11883 | /* 32756 */ GIM_Try, /*On fail goto*//*Label 716*/ GIMT_Encode4(32793), // Rule ID 2836 // |
| 11884 | /* 32761 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 11885 | /* 32764 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 11886 | /* 32767 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11887 | /* 32771 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11888 | /* 32775 */ // (bitconvert:{ *:[v8i8] } DPR:{ *:[v2f32] }:$src) => (VREV32d8:{ *:[v8i8] } DPR:{ *:[v2f32] }:$src) |
| 11889 | /* 32775 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d8), |
| 11890 | /* 32778 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11891 | /* 32780 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11892 | /* 32782 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11893 | /* 32785 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11894 | /* 32791 */ GIR_RootConstrainSelectedInstOperands, |
| 11895 | /* 32792 */ // GIR_Coverage, 2836, |
| 11896 | /* 32792 */ GIR_EraseRootFromParent_Done, |
| 11897 | /* 32793 */ // Label 716: @32793 |
| 11898 | /* 32793 */ GIM_Try, /*On fail goto*//*Label 717*/ GIMT_Encode4(32830), // Rule ID 2837 // |
| 11899 | /* 32798 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 11900 | /* 32801 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 11901 | /* 32804 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11902 | /* 32808 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11903 | /* 32812 */ // (bitconvert:{ *:[v8i8] } DPR:{ *:[v2i32] }:$src) => (VREV32d8:{ *:[v8i8] } DPR:{ *:[v2i32] }:$src) |
| 11904 | /* 32812 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d8), |
| 11905 | /* 32815 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11906 | /* 32817 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11907 | /* 32819 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11908 | /* 32822 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11909 | /* 32828 */ GIR_RootConstrainSelectedInstOperands, |
| 11910 | /* 32829 */ // GIR_Coverage, 2837, |
| 11911 | /* 32829 */ GIR_EraseRootFromParent_Done, |
| 11912 | /* 32830 */ // Label 717: @32830 |
| 11913 | /* 32830 */ GIM_Try, /*On fail goto*//*Label 718*/ GIMT_Encode4(32867), // Rule ID 2838 // |
| 11914 | /* 32835 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 11915 | /* 32838 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 11916 | /* 32841 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11917 | /* 32845 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11918 | /* 32849 */ // (bitconvert:{ *:[v8i8] } DPR:{ *:[v4f16] }:$src) => (VREV16d8:{ *:[v8i8] } DPR:{ *:[v4f16] }:$src) |
| 11919 | /* 32849 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV16d8), |
| 11920 | /* 32852 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11921 | /* 32854 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11922 | /* 32856 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11923 | /* 32859 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11924 | /* 32865 */ GIR_RootConstrainSelectedInstOperands, |
| 11925 | /* 32866 */ // GIR_Coverage, 2838, |
| 11926 | /* 32866 */ GIR_EraseRootFromParent_Done, |
| 11927 | /* 32867 */ // Label 718: @32867 |
| 11928 | /* 32867 */ GIM_Try, /*On fail goto*//*Label 719*/ GIMT_Encode4(32904), // Rule ID 2839 // |
| 11929 | /* 32872 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 11930 | /* 32875 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 11931 | /* 32878 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11932 | /* 32882 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11933 | /* 32886 */ // (bitconvert:{ *:[v8i8] } DPR:{ *:[v4i16] }:$src) => (VREV16d8:{ *:[v8i8] } DPR:{ *:[v4i16] }:$src) |
| 11934 | /* 32886 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV16d8), |
| 11935 | /* 32889 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11936 | /* 32891 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11937 | /* 32893 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11938 | /* 32896 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11939 | /* 32902 */ GIR_RootConstrainSelectedInstOperands, |
| 11940 | /* 32903 */ // GIR_Coverage, 2839, |
| 11941 | /* 32903 */ GIR_EraseRootFromParent_Done, |
| 11942 | /* 32904 */ // Label 719: @32904 |
| 11943 | /* 32904 */ GIM_Reject, |
| 11944 | /* 32905 */ // Label 547: @32905 |
| 11945 | /* 32905 */ GIM_Try, /*On fail goto*//*Label 720*/ GIMT_Encode4(32937), // Rule ID 2730 // |
| 11946 | /* 32910 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 11947 | /* 32913 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 11948 | /* 32916 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11949 | /* 32920 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11950 | /* 32924 */ // (bitconvert:{ *:[v8i16] } QPR:{ *:[v8f16] }:$src) => QPR:{ *:[v8i16] }:$src |
| 11951 | /* 32924 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11952 | /* 32927 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11953 | /* 32929 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11954 | /* 32931 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 11955 | /* 32936 */ // GIR_Coverage, 2730, |
| 11956 | /* 32936 */ GIR_EraseRootFromParent_Done, |
| 11957 | /* 32937 */ // Label 720: @32937 |
| 11958 | /* 32937 */ GIM_Try, /*On fail goto*//*Label 721*/ GIMT_Encode4(32969), // Rule ID 2731 // |
| 11959 | /* 32942 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 11960 | /* 32945 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 11961 | /* 32948 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11962 | /* 32952 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11963 | /* 32956 */ // (bitconvert:{ *:[v8f16] } QPR:{ *:[v8i16] }:$src) => QPR:{ *:[v8f16] }:$src |
| 11964 | /* 32956 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11965 | /* 32959 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11966 | /* 32961 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11967 | /* 32963 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 11968 | /* 32968 */ // GIR_Coverage, 2731, |
| 11969 | /* 32968 */ GIR_EraseRootFromParent_Done, |
| 11970 | /* 32969 */ // Label 721: @32969 |
| 11971 | /* 32969 */ GIM_Try, /*On fail goto*//*Label 722*/ GIMT_Encode4(33001), // Rule ID 2788 // |
| 11972 | /* 32974 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 11973 | /* 32977 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 11974 | /* 32980 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11975 | /* 32984 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11976 | /* 32988 */ // (bitconvert:{ *:[v8f16] } QPR:{ *:[v2f64] }:$src) => QPR:{ *:[v8f16] }:$src |
| 11977 | /* 32988 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11978 | /* 32991 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11979 | /* 32993 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11980 | /* 32995 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 11981 | /* 33000 */ // GIR_Coverage, 2788, |
| 11982 | /* 33000 */ GIR_EraseRootFromParent_Done, |
| 11983 | /* 33001 */ // Label 722: @33001 |
| 11984 | /* 33001 */ GIM_Try, /*On fail goto*//*Label 723*/ GIMT_Encode4(33033), // Rule ID 2789 // |
| 11985 | /* 33006 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 11986 | /* 33009 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 11987 | /* 33012 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11988 | /* 33016 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11989 | /* 33020 */ // (bitconvert:{ *:[v8f16] } QPR:{ *:[v2i64] }:$src) => QPR:{ *:[v8f16] }:$src |
| 11990 | /* 33020 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11991 | /* 33023 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11992 | /* 33025 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11993 | /* 33027 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 11994 | /* 33032 */ // GIR_Coverage, 2789, |
| 11995 | /* 33032 */ GIR_EraseRootFromParent_Done, |
| 11996 | /* 33033 */ // Label 723: @33033 |
| 11997 | /* 33033 */ GIM_Try, /*On fail goto*//*Label 724*/ GIMT_Encode4(33065), // Rule ID 2790 // |
| 11998 | /* 33038 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 11999 | /* 33041 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 12000 | /* 33044 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12001 | /* 33048 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12002 | /* 33052 */ // (bitconvert:{ *:[v8f16] } QPR:{ *:[v4f32] }:$src) => QPR:{ *:[v8f16] }:$src |
| 12003 | /* 33052 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12004 | /* 33055 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12005 | /* 33057 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12006 | /* 33059 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 12007 | /* 33064 */ // GIR_Coverage, 2790, |
| 12008 | /* 33064 */ GIR_EraseRootFromParent_Done, |
| 12009 | /* 33065 */ // Label 724: @33065 |
| 12010 | /* 33065 */ GIM_Try, /*On fail goto*//*Label 725*/ GIMT_Encode4(33097), // Rule ID 2791 // |
| 12011 | /* 33070 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 12012 | /* 33073 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 12013 | /* 33076 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12014 | /* 33080 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12015 | /* 33084 */ // (bitconvert:{ *:[v8f16] } QPR:{ *:[v4i32] }:$src) => QPR:{ *:[v8f16] }:$src |
| 12016 | /* 33084 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12017 | /* 33087 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12018 | /* 33089 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12019 | /* 33091 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 12020 | /* 33096 */ // GIR_Coverage, 2791, |
| 12021 | /* 33096 */ GIR_EraseRootFromParent_Done, |
| 12022 | /* 33097 */ // Label 725: @33097 |
| 12023 | /* 33097 */ GIM_Try, /*On fail goto*//*Label 726*/ GIMT_Encode4(33129), // Rule ID 2792 // |
| 12024 | /* 33102 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 12025 | /* 33105 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 12026 | /* 33108 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12027 | /* 33112 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12028 | /* 33116 */ // (bitconvert:{ *:[v8f16] } QPR:{ *:[v16i8] }:$src) => QPR:{ *:[v8f16] }:$src |
| 12029 | /* 33116 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12030 | /* 33119 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12031 | /* 33121 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12032 | /* 33123 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 12033 | /* 33128 */ // GIR_Coverage, 2792, |
| 12034 | /* 33128 */ GIR_EraseRootFromParent_Done, |
| 12035 | /* 33129 */ // Label 726: @33129 |
| 12036 | /* 33129 */ GIM_Try, /*On fail goto*//*Label 727*/ GIMT_Encode4(33161), // Rule ID 2793 // |
| 12037 | /* 33134 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 12038 | /* 33137 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 12039 | /* 33140 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12040 | /* 33144 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12041 | /* 33148 */ // (bitconvert:{ *:[v8i16] } QPR:{ *:[v2f64] }:$src) => QPR:{ *:[v8i16] }:$src |
| 12042 | /* 33148 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12043 | /* 33151 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12044 | /* 33153 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12045 | /* 33155 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 12046 | /* 33160 */ // GIR_Coverage, 2793, |
| 12047 | /* 33160 */ GIR_EraseRootFromParent_Done, |
| 12048 | /* 33161 */ // Label 727: @33161 |
| 12049 | /* 33161 */ GIM_Try, /*On fail goto*//*Label 728*/ GIMT_Encode4(33193), // Rule ID 2794 // |
| 12050 | /* 33166 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 12051 | /* 33169 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 12052 | /* 33172 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12053 | /* 33176 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12054 | /* 33180 */ // (bitconvert:{ *:[v8i16] } QPR:{ *:[v2i64] }:$src) => QPR:{ *:[v8i16] }:$src |
| 12055 | /* 33180 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12056 | /* 33183 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12057 | /* 33185 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12058 | /* 33187 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 12059 | /* 33192 */ // GIR_Coverage, 2794, |
| 12060 | /* 33192 */ GIR_EraseRootFromParent_Done, |
| 12061 | /* 33193 */ // Label 728: @33193 |
| 12062 | /* 33193 */ GIM_Try, /*On fail goto*//*Label 729*/ GIMT_Encode4(33225), // Rule ID 2795 // |
| 12063 | /* 33198 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 12064 | /* 33201 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 12065 | /* 33204 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12066 | /* 33208 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12067 | /* 33212 */ // (bitconvert:{ *:[v8i16] } QPR:{ *:[v4f32] }:$src) => QPR:{ *:[v8i16] }:$src |
| 12068 | /* 33212 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12069 | /* 33215 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12070 | /* 33217 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12071 | /* 33219 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 12072 | /* 33224 */ // GIR_Coverage, 2795, |
| 12073 | /* 33224 */ GIR_EraseRootFromParent_Done, |
| 12074 | /* 33225 */ // Label 729: @33225 |
| 12075 | /* 33225 */ GIM_Try, /*On fail goto*//*Label 730*/ GIMT_Encode4(33257), // Rule ID 2796 // |
| 12076 | /* 33230 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 12077 | /* 33233 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 12078 | /* 33236 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12079 | /* 33240 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12080 | /* 33244 */ // (bitconvert:{ *:[v8i16] } QPR:{ *:[v4i32] }:$src) => QPR:{ *:[v8i16] }:$src |
| 12081 | /* 33244 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12082 | /* 33247 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12083 | /* 33249 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12084 | /* 33251 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 12085 | /* 33256 */ // GIR_Coverage, 2796, |
| 12086 | /* 33256 */ GIR_EraseRootFromParent_Done, |
| 12087 | /* 33257 */ // Label 730: @33257 |
| 12088 | /* 33257 */ GIM_Try, /*On fail goto*//*Label 731*/ GIMT_Encode4(33289), // Rule ID 2797 // |
| 12089 | /* 33262 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 12090 | /* 33265 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 12091 | /* 33268 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12092 | /* 33272 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12093 | /* 33276 */ // (bitconvert:{ *:[v8i16] } QPR:{ *:[v16i8] }:$src) => QPR:{ *:[v8i16] }:$src |
| 12094 | /* 33276 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12095 | /* 33279 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12096 | /* 33281 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12097 | /* 33283 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 12098 | /* 33288 */ // GIR_Coverage, 2797, |
| 12099 | /* 33288 */ GIR_EraseRootFromParent_Done, |
| 12100 | /* 33289 */ // Label 731: @33289 |
| 12101 | /* 33289 */ GIM_Try, /*On fail goto*//*Label 732*/ GIMT_Encode4(33326), // Rule ID 2860 // |
| 12102 | /* 33294 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 12103 | /* 33297 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 12104 | /* 33300 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12105 | /* 33304 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12106 | /* 33308 */ // (bitconvert:{ *:[v8f16] } QPR:{ *:[v2f64] }:$src) => (VREV64q16:{ *:[v8f16] } QPR:{ *:[v2f64] }:$src) |
| 12107 | /* 33308 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q16), |
| 12108 | /* 33311 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12109 | /* 33313 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12110 | /* 33315 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12111 | /* 33318 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12112 | /* 33324 */ GIR_RootConstrainSelectedInstOperands, |
| 12113 | /* 33325 */ // GIR_Coverage, 2860, |
| 12114 | /* 33325 */ GIR_EraseRootFromParent_Done, |
| 12115 | /* 33326 */ // Label 732: @33326 |
| 12116 | /* 33326 */ GIM_Try, /*On fail goto*//*Label 733*/ GIMT_Encode4(33363), // Rule ID 2861 // |
| 12117 | /* 33331 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 12118 | /* 33334 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 12119 | /* 33337 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12120 | /* 33341 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12121 | /* 33345 */ // (bitconvert:{ *:[v8f16] } QPR:{ *:[v2i64] }:$src) => (VREV64q16:{ *:[v8f16] } QPR:{ *:[v2i64] }:$src) |
| 12122 | /* 33345 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q16), |
| 12123 | /* 33348 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12124 | /* 33350 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12125 | /* 33352 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12126 | /* 33355 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12127 | /* 33361 */ GIR_RootConstrainSelectedInstOperands, |
| 12128 | /* 33362 */ // GIR_Coverage, 2861, |
| 12129 | /* 33362 */ GIR_EraseRootFromParent_Done, |
| 12130 | /* 33363 */ // Label 733: @33363 |
| 12131 | /* 33363 */ GIM_Try, /*On fail goto*//*Label 734*/ GIMT_Encode4(33400), // Rule ID 2862 // |
| 12132 | /* 33368 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 12133 | /* 33371 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 12134 | /* 33374 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12135 | /* 33378 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12136 | /* 33382 */ // (bitconvert:{ *:[v8f16] } QPR:{ *:[v4f32] }:$src) => (VREV32q16:{ *:[v8f16] } QPR:{ *:[v4f32] }:$src) |
| 12137 | /* 33382 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q16), |
| 12138 | /* 33385 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12139 | /* 33387 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12140 | /* 33389 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12141 | /* 33392 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12142 | /* 33398 */ GIR_RootConstrainSelectedInstOperands, |
| 12143 | /* 33399 */ // GIR_Coverage, 2862, |
| 12144 | /* 33399 */ GIR_EraseRootFromParent_Done, |
| 12145 | /* 33400 */ // Label 734: @33400 |
| 12146 | /* 33400 */ GIM_Try, /*On fail goto*//*Label 735*/ GIMT_Encode4(33437), // Rule ID 2863 // |
| 12147 | /* 33405 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 12148 | /* 33408 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 12149 | /* 33411 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12150 | /* 33415 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12151 | /* 33419 */ // (bitconvert:{ *:[v8f16] } QPR:{ *:[v4i32] }:$src) => (VREV32q16:{ *:[v8f16] } QPR:{ *:[v4i32] }:$src) |
| 12152 | /* 33419 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q16), |
| 12153 | /* 33422 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12154 | /* 33424 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12155 | /* 33426 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12156 | /* 33429 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12157 | /* 33435 */ GIR_RootConstrainSelectedInstOperands, |
| 12158 | /* 33436 */ // GIR_Coverage, 2863, |
| 12159 | /* 33436 */ GIR_EraseRootFromParent_Done, |
| 12160 | /* 33437 */ // Label 735: @33437 |
| 12161 | /* 33437 */ GIM_Try, /*On fail goto*//*Label 736*/ GIMT_Encode4(33474), // Rule ID 2864 // |
| 12162 | /* 33442 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 12163 | /* 33445 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 12164 | /* 33448 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12165 | /* 33452 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12166 | /* 33456 */ // (bitconvert:{ *:[v8f16] } QPR:{ *:[v16i8] }:$src) => (VREV16q8:{ *:[v8f16] } QPR:{ *:[v16i8] }:$src) |
| 12167 | /* 33456 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV16q8), |
| 12168 | /* 33459 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12169 | /* 33461 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12170 | /* 33463 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12171 | /* 33466 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12172 | /* 33472 */ GIR_RootConstrainSelectedInstOperands, |
| 12173 | /* 33473 */ // GIR_Coverage, 2864, |
| 12174 | /* 33473 */ GIR_EraseRootFromParent_Done, |
| 12175 | /* 33474 */ // Label 736: @33474 |
| 12176 | /* 33474 */ GIM_Try, /*On fail goto*//*Label 737*/ GIMT_Encode4(33511), // Rule ID 2865 // |
| 12177 | /* 33479 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 12178 | /* 33482 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 12179 | /* 33485 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12180 | /* 33489 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12181 | /* 33493 */ // (bitconvert:{ *:[v8i16] } QPR:{ *:[v2f64] }:$src) => (VREV64q16:{ *:[v8i16] } QPR:{ *:[v2f64] }:$src) |
| 12182 | /* 33493 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q16), |
| 12183 | /* 33496 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12184 | /* 33498 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12185 | /* 33500 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12186 | /* 33503 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12187 | /* 33509 */ GIR_RootConstrainSelectedInstOperands, |
| 12188 | /* 33510 */ // GIR_Coverage, 2865, |
| 12189 | /* 33510 */ GIR_EraseRootFromParent_Done, |
| 12190 | /* 33511 */ // Label 737: @33511 |
| 12191 | /* 33511 */ GIM_Try, /*On fail goto*//*Label 738*/ GIMT_Encode4(33548), // Rule ID 2866 // |
| 12192 | /* 33516 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 12193 | /* 33519 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 12194 | /* 33522 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12195 | /* 33526 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12196 | /* 33530 */ // (bitconvert:{ *:[v8i16] } QPR:{ *:[v2i64] }:$src) => (VREV64q16:{ *:[v8i16] } QPR:{ *:[v2i64] }:$src) |
| 12197 | /* 33530 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q16), |
| 12198 | /* 33533 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12199 | /* 33535 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12200 | /* 33537 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12201 | /* 33540 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12202 | /* 33546 */ GIR_RootConstrainSelectedInstOperands, |
| 12203 | /* 33547 */ // GIR_Coverage, 2866, |
| 12204 | /* 33547 */ GIR_EraseRootFromParent_Done, |
| 12205 | /* 33548 */ // Label 738: @33548 |
| 12206 | /* 33548 */ GIM_Try, /*On fail goto*//*Label 739*/ GIMT_Encode4(33585), // Rule ID 2867 // |
| 12207 | /* 33553 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 12208 | /* 33556 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 12209 | /* 33559 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12210 | /* 33563 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12211 | /* 33567 */ // (bitconvert:{ *:[v8i16] } QPR:{ *:[v4f32] }:$src) => (VREV32q16:{ *:[v8i16] } QPR:{ *:[v4f32] }:$src) |
| 12212 | /* 33567 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q16), |
| 12213 | /* 33570 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12214 | /* 33572 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12215 | /* 33574 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12216 | /* 33577 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12217 | /* 33583 */ GIR_RootConstrainSelectedInstOperands, |
| 12218 | /* 33584 */ // GIR_Coverage, 2867, |
| 12219 | /* 33584 */ GIR_EraseRootFromParent_Done, |
| 12220 | /* 33585 */ // Label 739: @33585 |
| 12221 | /* 33585 */ GIM_Try, /*On fail goto*//*Label 740*/ GIMT_Encode4(33622), // Rule ID 2868 // |
| 12222 | /* 33590 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 12223 | /* 33593 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 12224 | /* 33596 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12225 | /* 33600 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12226 | /* 33604 */ // (bitconvert:{ *:[v8i16] } QPR:{ *:[v4i32] }:$src) => (VREV32q16:{ *:[v8i16] } QPR:{ *:[v4i32] }:$src) |
| 12227 | /* 33604 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q16), |
| 12228 | /* 33607 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12229 | /* 33609 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12230 | /* 33611 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12231 | /* 33614 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12232 | /* 33620 */ GIR_RootConstrainSelectedInstOperands, |
| 12233 | /* 33621 */ // GIR_Coverage, 2868, |
| 12234 | /* 33621 */ GIR_EraseRootFromParent_Done, |
| 12235 | /* 33622 */ // Label 740: @33622 |
| 12236 | /* 33622 */ GIM_Try, /*On fail goto*//*Label 741*/ GIMT_Encode4(33659), // Rule ID 2869 // |
| 12237 | /* 33627 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 12238 | /* 33630 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 12239 | /* 33633 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12240 | /* 33637 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12241 | /* 33641 */ // (bitconvert:{ *:[v8i16] } QPR:{ *:[v16i8] }:$src) => (VREV16q8:{ *:[v8i16] } QPR:{ *:[v16i8] }:$src) |
| 12242 | /* 33641 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV16q8), |
| 12243 | /* 33644 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12244 | /* 33646 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12245 | /* 33648 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12246 | /* 33651 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12247 | /* 33657 */ GIR_RootConstrainSelectedInstOperands, |
| 12248 | /* 33658 */ // GIR_Coverage, 2869, |
| 12249 | /* 33658 */ GIR_EraseRootFromParent_Done, |
| 12250 | /* 33659 */ // Label 741: @33659 |
| 12251 | /* 33659 */ GIM_Try, /*On fail goto*//*Label 742*/ GIMT_Encode4(33691), // Rule ID 5287 // |
| 12252 | /* 33664 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 12253 | /* 33667 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 12254 | /* 33670 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12255 | /* 33674 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12256 | /* 33678 */ // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$src) => MQPR:{ *:[v8i16] }:$src |
| 12257 | /* 33678 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12258 | /* 33681 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12259 | /* 33683 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12260 | /* 33685 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 12261 | /* 33690 */ // GIR_Coverage, 5287, |
| 12262 | /* 33690 */ GIR_EraseRootFromParent_Done, |
| 12263 | /* 33691 */ // Label 742: @33691 |
| 12264 | /* 33691 */ GIM_Try, /*On fail goto*//*Label 743*/ GIMT_Encode4(33723), // Rule ID 5288 // |
| 12265 | /* 33696 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 12266 | /* 33699 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 12267 | /* 33702 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12268 | /* 33706 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12269 | /* 33710 */ // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v8i16] }:$src) => MQPR:{ *:[v8f16] }:$src |
| 12270 | /* 33710 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12271 | /* 33713 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12272 | /* 33715 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12273 | /* 33717 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 12274 | /* 33722 */ // GIR_Coverage, 5288, |
| 12275 | /* 33722 */ GIR_EraseRootFromParent_Done, |
| 12276 | /* 33723 */ // Label 743: @33723 |
| 12277 | /* 33723 */ GIM_Try, /*On fail goto*//*Label 744*/ GIMT_Encode4(33755), // Rule ID 5309 // |
| 12278 | /* 33728 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), |
| 12279 | /* 33731 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 12280 | /* 33734 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12281 | /* 33738 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12282 | /* 33742 */ // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v2f64] }:$src) => MQPR:{ *:[v8f16] }:$src |
| 12283 | /* 33742 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12284 | /* 33745 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12285 | /* 33747 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12286 | /* 33749 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 12287 | /* 33754 */ // GIR_Coverage, 5309, |
| 12288 | /* 33754 */ GIR_EraseRootFromParent_Done, |
| 12289 | /* 33755 */ // Label 744: @33755 |
| 12290 | /* 33755 */ GIM_Try, /*On fail goto*//*Label 745*/ GIMT_Encode4(33787), // Rule ID 5310 // |
| 12291 | /* 33760 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), |
| 12292 | /* 33763 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 12293 | /* 33766 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12294 | /* 33770 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12295 | /* 33774 */ // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v2i64] }:$src) => MQPR:{ *:[v8f16] }:$src |
| 12296 | /* 33774 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12297 | /* 33777 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12298 | /* 33779 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12299 | /* 33781 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 12300 | /* 33786 */ // GIR_Coverage, 5310, |
| 12301 | /* 33786 */ GIR_EraseRootFromParent_Done, |
| 12302 | /* 33787 */ // Label 745: @33787 |
| 12303 | /* 33787 */ GIM_Try, /*On fail goto*//*Label 746*/ GIMT_Encode4(33819), // Rule ID 5311 // |
| 12304 | /* 33792 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), |
| 12305 | /* 33795 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 12306 | /* 33798 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12307 | /* 33802 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12308 | /* 33806 */ // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v4f32] }:$src) => MQPR:{ *:[v8f16] }:$src |
| 12309 | /* 33806 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12310 | /* 33809 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12311 | /* 33811 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12312 | /* 33813 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 12313 | /* 33818 */ // GIR_Coverage, 5311, |
| 12314 | /* 33818 */ GIR_EraseRootFromParent_Done, |
| 12315 | /* 33819 */ // Label 746: @33819 |
| 12316 | /* 33819 */ GIM_Try, /*On fail goto*//*Label 747*/ GIMT_Encode4(33851), // Rule ID 5312 // |
| 12317 | /* 33824 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), |
| 12318 | /* 33827 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 12319 | /* 33830 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12320 | /* 33834 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12321 | /* 33838 */ // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v4i32] }:$src) => MQPR:{ *:[v8f16] }:$src |
| 12322 | /* 33838 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12323 | /* 33841 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12324 | /* 33843 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12325 | /* 33845 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 12326 | /* 33850 */ // GIR_Coverage, 5312, |
| 12327 | /* 33850 */ GIR_EraseRootFromParent_Done, |
| 12328 | /* 33851 */ // Label 747: @33851 |
| 12329 | /* 33851 */ GIM_Try, /*On fail goto*//*Label 748*/ GIMT_Encode4(33883), // Rule ID 5313 // |
| 12330 | /* 33856 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), |
| 12331 | /* 33859 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 12332 | /* 33862 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12333 | /* 33866 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12334 | /* 33870 */ // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v16i8] }:$src) => MQPR:{ *:[v8f16] }:$src |
| 12335 | /* 33870 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12336 | /* 33873 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12337 | /* 33875 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12338 | /* 33877 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 12339 | /* 33882 */ // GIR_Coverage, 5313, |
| 12340 | /* 33882 */ GIR_EraseRootFromParent_Done, |
| 12341 | /* 33883 */ // Label 748: @33883 |
| 12342 | /* 33883 */ GIM_Try, /*On fail goto*//*Label 749*/ GIMT_Encode4(33915), // Rule ID 5314 // |
| 12343 | /* 33888 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), |
| 12344 | /* 33891 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 12345 | /* 33894 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12346 | /* 33898 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12347 | /* 33902 */ // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v2f64] }:$src) => MQPR:{ *:[v8i16] }:$src |
| 12348 | /* 33902 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12349 | /* 33905 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12350 | /* 33907 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12351 | /* 33909 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 12352 | /* 33914 */ // GIR_Coverage, 5314, |
| 12353 | /* 33914 */ GIR_EraseRootFromParent_Done, |
| 12354 | /* 33915 */ // Label 749: @33915 |
| 12355 | /* 33915 */ GIM_Try, /*On fail goto*//*Label 750*/ GIMT_Encode4(33947), // Rule ID 5315 // |
| 12356 | /* 33920 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), |
| 12357 | /* 33923 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 12358 | /* 33926 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12359 | /* 33930 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12360 | /* 33934 */ // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v2i64] }:$src) => MQPR:{ *:[v8i16] }:$src |
| 12361 | /* 33934 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12362 | /* 33937 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12363 | /* 33939 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12364 | /* 33941 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 12365 | /* 33946 */ // GIR_Coverage, 5315, |
| 12366 | /* 33946 */ GIR_EraseRootFromParent_Done, |
| 12367 | /* 33947 */ // Label 750: @33947 |
| 12368 | /* 33947 */ GIM_Try, /*On fail goto*//*Label 751*/ GIMT_Encode4(33979), // Rule ID 5316 // |
| 12369 | /* 33952 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), |
| 12370 | /* 33955 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 12371 | /* 33958 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12372 | /* 33962 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12373 | /* 33966 */ // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v4f32] }:$src) => MQPR:{ *:[v8i16] }:$src |
| 12374 | /* 33966 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12375 | /* 33969 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12376 | /* 33971 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12377 | /* 33973 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 12378 | /* 33978 */ // GIR_Coverage, 5316, |
| 12379 | /* 33978 */ GIR_EraseRootFromParent_Done, |
| 12380 | /* 33979 */ // Label 751: @33979 |
| 12381 | /* 33979 */ GIM_Try, /*On fail goto*//*Label 752*/ GIMT_Encode4(34011), // Rule ID 5317 // |
| 12382 | /* 33984 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), |
| 12383 | /* 33987 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 12384 | /* 33990 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12385 | /* 33994 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12386 | /* 33998 */ // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v4i32] }:$src) => MQPR:{ *:[v8i16] }:$src |
| 12387 | /* 33998 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12388 | /* 34001 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12389 | /* 34003 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12390 | /* 34005 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 12391 | /* 34010 */ // GIR_Coverage, 5317, |
| 12392 | /* 34010 */ GIR_EraseRootFromParent_Done, |
| 12393 | /* 34011 */ // Label 752: @34011 |
| 12394 | /* 34011 */ GIM_Try, /*On fail goto*//*Label 753*/ GIMT_Encode4(34043), // Rule ID 5318 // |
| 12395 | /* 34016 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), |
| 12396 | /* 34019 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 12397 | /* 34022 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12398 | /* 34026 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12399 | /* 34030 */ // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$src) => MQPR:{ *:[v8i16] }:$src |
| 12400 | /* 34030 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12401 | /* 34033 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12402 | /* 34035 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12403 | /* 34037 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 12404 | /* 34042 */ // GIR_Coverage, 5318, |
| 12405 | /* 34042 */ GIR_EraseRootFromParent_Done, |
| 12406 | /* 34043 */ // Label 753: @34043 |
| 12407 | /* 34043 */ GIM_Try, /*On fail goto*//*Label 754*/ GIMT_Encode4(34101), // Rule ID 5345 // |
| 12408 | /* 34048 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), |
| 12409 | /* 34051 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 12410 | /* 34054 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12411 | /* 34058 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12412 | /* 34062 */ // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v2f64] }:$src) => (MVE_VREV64_16:{ *:[v8f16] } MQPR:{ *:[v2f64] }:$src) |
| 12413 | /* 34062 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 12414 | /* 34065 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 12415 | /* 34069 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 12416 | /* 34074 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_16), |
| 12417 | /* 34077 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 12418 | /* 34079 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12419 | /* 34081 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 12420 | /* 34084 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12421 | /* 34090 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12422 | /* 34096 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 12423 | /* 34099 */ GIR_RootConstrainSelectedInstOperands, |
| 12424 | /* 34100 */ // GIR_Coverage, 5345, |
| 12425 | /* 34100 */ GIR_EraseRootFromParent_Done, |
| 12426 | /* 34101 */ // Label 754: @34101 |
| 12427 | /* 34101 */ GIM_Try, /*On fail goto*//*Label 755*/ GIMT_Encode4(34159), // Rule ID 5346 // |
| 12428 | /* 34106 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), |
| 12429 | /* 34109 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 12430 | /* 34112 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12431 | /* 34116 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12432 | /* 34120 */ // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v2i64] }:$src) => (MVE_VREV64_16:{ *:[v8f16] } MQPR:{ *:[v2i64] }:$src) |
| 12433 | /* 34120 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 12434 | /* 34123 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 12435 | /* 34127 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 12436 | /* 34132 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_16), |
| 12437 | /* 34135 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 12438 | /* 34137 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12439 | /* 34139 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 12440 | /* 34142 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12441 | /* 34148 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12442 | /* 34154 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 12443 | /* 34157 */ GIR_RootConstrainSelectedInstOperands, |
| 12444 | /* 34158 */ // GIR_Coverage, 5346, |
| 12445 | /* 34158 */ GIR_EraseRootFromParent_Done, |
| 12446 | /* 34159 */ // Label 755: @34159 |
| 12447 | /* 34159 */ GIM_Try, /*On fail goto*//*Label 756*/ GIMT_Encode4(34217), // Rule ID 5347 // |
| 12448 | /* 34164 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), |
| 12449 | /* 34167 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 12450 | /* 34170 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12451 | /* 34174 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12452 | /* 34178 */ // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v4f32] }:$src) => (MVE_VREV32_16:{ *:[v8f16] } MQPR:{ *:[v4f32] }:$src) |
| 12453 | /* 34178 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 12454 | /* 34181 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 12455 | /* 34185 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 12456 | /* 34190 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_16), |
| 12457 | /* 34193 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 12458 | /* 34195 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12459 | /* 34197 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 12460 | /* 34200 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12461 | /* 34206 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12462 | /* 34212 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 12463 | /* 34215 */ GIR_RootConstrainSelectedInstOperands, |
| 12464 | /* 34216 */ // GIR_Coverage, 5347, |
| 12465 | /* 34216 */ GIR_EraseRootFromParent_Done, |
| 12466 | /* 34217 */ // Label 756: @34217 |
| 12467 | /* 34217 */ GIM_Try, /*On fail goto*//*Label 757*/ GIMT_Encode4(34275), // Rule ID 5348 // |
| 12468 | /* 34222 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), |
| 12469 | /* 34225 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 12470 | /* 34228 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12471 | /* 34232 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12472 | /* 34236 */ // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v4i32] }:$src) => (MVE_VREV32_16:{ *:[v8f16] } MQPR:{ *:[v4i32] }:$src) |
| 12473 | /* 34236 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 12474 | /* 34239 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 12475 | /* 34243 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 12476 | /* 34248 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_16), |
| 12477 | /* 34251 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 12478 | /* 34253 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12479 | /* 34255 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 12480 | /* 34258 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12481 | /* 34264 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12482 | /* 34270 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 12483 | /* 34273 */ GIR_RootConstrainSelectedInstOperands, |
| 12484 | /* 34274 */ // GIR_Coverage, 5348, |
| 12485 | /* 34274 */ GIR_EraseRootFromParent_Done, |
| 12486 | /* 34275 */ // Label 757: @34275 |
| 12487 | /* 34275 */ GIM_Try, /*On fail goto*//*Label 758*/ GIMT_Encode4(34333), // Rule ID 5349 // |
| 12488 | /* 34280 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), |
| 12489 | /* 34283 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 12490 | /* 34286 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12491 | /* 34290 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12492 | /* 34294 */ // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v16i8] }:$src) => (MVE_VREV16_8:{ *:[v8f16] } MQPR:{ *:[v16i8] }:$src) |
| 12493 | /* 34294 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 12494 | /* 34297 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 12495 | /* 34301 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 12496 | /* 34306 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV16_8), |
| 12497 | /* 34309 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 12498 | /* 34311 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12499 | /* 34313 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 12500 | /* 34316 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12501 | /* 34322 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12502 | /* 34328 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 12503 | /* 34331 */ GIR_RootConstrainSelectedInstOperands, |
| 12504 | /* 34332 */ // GIR_Coverage, 5349, |
| 12505 | /* 34332 */ GIR_EraseRootFromParent_Done, |
| 12506 | /* 34333 */ // Label 758: @34333 |
| 12507 | /* 34333 */ GIM_Try, /*On fail goto*//*Label 759*/ GIMT_Encode4(34391), // Rule ID 5350 // |
| 12508 | /* 34338 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), |
| 12509 | /* 34341 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 12510 | /* 34344 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12511 | /* 34348 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12512 | /* 34352 */ // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v2f64] }:$src) => (MVE_VREV64_16:{ *:[v8i16] } MQPR:{ *:[v2f64] }:$src) |
| 12513 | /* 34352 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 12514 | /* 34355 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 12515 | /* 34359 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 12516 | /* 34364 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_16), |
| 12517 | /* 34367 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 12518 | /* 34369 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12519 | /* 34371 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 12520 | /* 34374 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12521 | /* 34380 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12522 | /* 34386 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 12523 | /* 34389 */ GIR_RootConstrainSelectedInstOperands, |
| 12524 | /* 34390 */ // GIR_Coverage, 5350, |
| 12525 | /* 34390 */ GIR_EraseRootFromParent_Done, |
| 12526 | /* 34391 */ // Label 759: @34391 |
| 12527 | /* 34391 */ GIM_Try, /*On fail goto*//*Label 760*/ GIMT_Encode4(34449), // Rule ID 5351 // |
| 12528 | /* 34396 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), |
| 12529 | /* 34399 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 12530 | /* 34402 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12531 | /* 34406 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12532 | /* 34410 */ // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v2i64] }:$src) => (MVE_VREV64_16:{ *:[v8i16] } MQPR:{ *:[v2i64] }:$src) |
| 12533 | /* 34410 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 12534 | /* 34413 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 12535 | /* 34417 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 12536 | /* 34422 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_16), |
| 12537 | /* 34425 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 12538 | /* 34427 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12539 | /* 34429 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 12540 | /* 34432 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12541 | /* 34438 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12542 | /* 34444 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 12543 | /* 34447 */ GIR_RootConstrainSelectedInstOperands, |
| 12544 | /* 34448 */ // GIR_Coverage, 5351, |
| 12545 | /* 34448 */ GIR_EraseRootFromParent_Done, |
| 12546 | /* 34449 */ // Label 760: @34449 |
| 12547 | /* 34449 */ GIM_Try, /*On fail goto*//*Label 761*/ GIMT_Encode4(34507), // Rule ID 5352 // |
| 12548 | /* 34454 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), |
| 12549 | /* 34457 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 12550 | /* 34460 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12551 | /* 34464 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12552 | /* 34468 */ // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v4f32] }:$src) => (MVE_VREV32_16:{ *:[v8i16] } MQPR:{ *:[v4f32] }:$src) |
| 12553 | /* 34468 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 12554 | /* 34471 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 12555 | /* 34475 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 12556 | /* 34480 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_16), |
| 12557 | /* 34483 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 12558 | /* 34485 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12559 | /* 34487 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 12560 | /* 34490 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12561 | /* 34496 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12562 | /* 34502 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 12563 | /* 34505 */ GIR_RootConstrainSelectedInstOperands, |
| 12564 | /* 34506 */ // GIR_Coverage, 5352, |
| 12565 | /* 34506 */ GIR_EraseRootFromParent_Done, |
| 12566 | /* 34507 */ // Label 761: @34507 |
| 12567 | /* 34507 */ GIM_Try, /*On fail goto*//*Label 762*/ GIMT_Encode4(34565), // Rule ID 5353 // |
| 12568 | /* 34512 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), |
| 12569 | /* 34515 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 12570 | /* 34518 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12571 | /* 34522 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12572 | /* 34526 */ // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v4i32] }:$src) => (MVE_VREV32_16:{ *:[v8i16] } MQPR:{ *:[v4i32] }:$src) |
| 12573 | /* 34526 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 12574 | /* 34529 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 12575 | /* 34533 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 12576 | /* 34538 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_16), |
| 12577 | /* 34541 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 12578 | /* 34543 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12579 | /* 34545 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 12580 | /* 34548 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12581 | /* 34554 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12582 | /* 34560 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 12583 | /* 34563 */ GIR_RootConstrainSelectedInstOperands, |
| 12584 | /* 34564 */ // GIR_Coverage, 5353, |
| 12585 | /* 34564 */ GIR_EraseRootFromParent_Done, |
| 12586 | /* 34565 */ // Label 762: @34565 |
| 12587 | /* 34565 */ GIM_Try, /*On fail goto*//*Label 763*/ GIMT_Encode4(34623), // Rule ID 5354 // |
| 12588 | /* 34570 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), |
| 12589 | /* 34573 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 12590 | /* 34576 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12591 | /* 34580 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12592 | /* 34584 */ // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$src) => (MVE_VREV16_8:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$src) |
| 12593 | /* 34584 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 12594 | /* 34587 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 12595 | /* 34591 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 12596 | /* 34596 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV16_8), |
| 12597 | /* 34599 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 12598 | /* 34601 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12599 | /* 34603 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 12600 | /* 34606 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12601 | /* 34612 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12602 | /* 34618 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 12603 | /* 34621 */ GIR_RootConstrainSelectedInstOperands, |
| 12604 | /* 34622 */ // GIR_Coverage, 5354, |
| 12605 | /* 34622 */ GIR_EraseRootFromParent_Done, |
| 12606 | /* 34623 */ // Label 763: @34623 |
| 12607 | /* 34623 */ GIM_Reject, |
| 12608 | /* 34624 */ // Label 548: @34624 |
| 12609 | /* 34624 */ GIM_Try, /*On fail goto*//*Label 764*/ GIMT_Encode4(34656), // Rule ID 2798 // |
| 12610 | /* 34629 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 12611 | /* 34632 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 12612 | /* 34635 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12613 | /* 34639 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12614 | /* 34643 */ // (bitconvert:{ *:[v16i8] } QPR:{ *:[v2f64] }:$src) => QPR:{ *:[v16i8] }:$src |
| 12615 | /* 34643 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12616 | /* 34646 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12617 | /* 34648 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12618 | /* 34650 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 12619 | /* 34655 */ // GIR_Coverage, 2798, |
| 12620 | /* 34655 */ GIR_EraseRootFromParent_Done, |
| 12621 | /* 34656 */ // Label 764: @34656 |
| 12622 | /* 34656 */ GIM_Try, /*On fail goto*//*Label 765*/ GIMT_Encode4(34688), // Rule ID 2799 // |
| 12623 | /* 34661 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 12624 | /* 34664 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 12625 | /* 34667 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12626 | /* 34671 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12627 | /* 34675 */ // (bitconvert:{ *:[v16i8] } QPR:{ *:[v2i64] }:$src) => QPR:{ *:[v16i8] }:$src |
| 12628 | /* 34675 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12629 | /* 34678 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12630 | /* 34680 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12631 | /* 34682 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 12632 | /* 34687 */ // GIR_Coverage, 2799, |
| 12633 | /* 34687 */ GIR_EraseRootFromParent_Done, |
| 12634 | /* 34688 */ // Label 765: @34688 |
| 12635 | /* 34688 */ GIM_Try, /*On fail goto*//*Label 766*/ GIMT_Encode4(34720), // Rule ID 2800 // |
| 12636 | /* 34693 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 12637 | /* 34696 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 12638 | /* 34699 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12639 | /* 34703 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12640 | /* 34707 */ // (bitconvert:{ *:[v16i8] } QPR:{ *:[v4f32] }:$src) => QPR:{ *:[v16i8] }:$src |
| 12641 | /* 34707 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12642 | /* 34710 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12643 | /* 34712 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12644 | /* 34714 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 12645 | /* 34719 */ // GIR_Coverage, 2800, |
| 12646 | /* 34719 */ GIR_EraseRootFromParent_Done, |
| 12647 | /* 34720 */ // Label 766: @34720 |
| 12648 | /* 34720 */ GIM_Try, /*On fail goto*//*Label 767*/ GIMT_Encode4(34752), // Rule ID 2801 // |
| 12649 | /* 34725 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 12650 | /* 34728 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 12651 | /* 34731 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12652 | /* 34735 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12653 | /* 34739 */ // (bitconvert:{ *:[v16i8] } QPR:{ *:[v4i32] }:$src) => QPR:{ *:[v16i8] }:$src |
| 12654 | /* 34739 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12655 | /* 34742 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12656 | /* 34744 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12657 | /* 34746 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 12658 | /* 34751 */ // GIR_Coverage, 2801, |
| 12659 | /* 34751 */ GIR_EraseRootFromParent_Done, |
| 12660 | /* 34752 */ // Label 767: @34752 |
| 12661 | /* 34752 */ GIM_Try, /*On fail goto*//*Label 768*/ GIMT_Encode4(34784), // Rule ID 2802 // |
| 12662 | /* 34757 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 12663 | /* 34760 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 12664 | /* 34763 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12665 | /* 34767 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12666 | /* 34771 */ // (bitconvert:{ *:[v16i8] } QPR:{ *:[v8f16] }:$src) => QPR:{ *:[v16i8] }:$src |
| 12667 | /* 34771 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12668 | /* 34774 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12669 | /* 34776 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12670 | /* 34778 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 12671 | /* 34783 */ // GIR_Coverage, 2802, |
| 12672 | /* 34783 */ GIR_EraseRootFromParent_Done, |
| 12673 | /* 34784 */ // Label 768: @34784 |
| 12674 | /* 34784 */ GIM_Try, /*On fail goto*//*Label 769*/ GIMT_Encode4(34816), // Rule ID 2803 // |
| 12675 | /* 34789 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE), |
| 12676 | /* 34792 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 12677 | /* 34795 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12678 | /* 34799 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12679 | /* 34803 */ // (bitconvert:{ *:[v16i8] } QPR:{ *:[v8i16] }:$src) => QPR:{ *:[v16i8] }:$src |
| 12680 | /* 34803 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12681 | /* 34806 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12682 | /* 34808 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12683 | /* 34810 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 12684 | /* 34815 */ // GIR_Coverage, 2803, |
| 12685 | /* 34815 */ GIR_EraseRootFromParent_Done, |
| 12686 | /* 34816 */ // Label 769: @34816 |
| 12687 | /* 34816 */ GIM_Try, /*On fail goto*//*Label 770*/ GIMT_Encode4(34853), // Rule ID 2870 // |
| 12688 | /* 34821 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 12689 | /* 34824 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 12690 | /* 34827 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12691 | /* 34831 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12692 | /* 34835 */ // (bitconvert:{ *:[v16i8] } QPR:{ *:[v2f64] }:$src) => (VREV64q8:{ *:[v16i8] } QPR:{ *:[v2f64] }:$src) |
| 12693 | /* 34835 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q8), |
| 12694 | /* 34838 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12695 | /* 34840 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12696 | /* 34842 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12697 | /* 34845 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12698 | /* 34851 */ GIR_RootConstrainSelectedInstOperands, |
| 12699 | /* 34852 */ // GIR_Coverage, 2870, |
| 12700 | /* 34852 */ GIR_EraseRootFromParent_Done, |
| 12701 | /* 34853 */ // Label 770: @34853 |
| 12702 | /* 34853 */ GIM_Try, /*On fail goto*//*Label 771*/ GIMT_Encode4(34890), // Rule ID 2871 // |
| 12703 | /* 34858 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 12704 | /* 34861 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 12705 | /* 34864 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12706 | /* 34868 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12707 | /* 34872 */ // (bitconvert:{ *:[v16i8] } QPR:{ *:[v2i64] }:$src) => (VREV64q8:{ *:[v16i8] } QPR:{ *:[v2i64] }:$src) |
| 12708 | /* 34872 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q8), |
| 12709 | /* 34875 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12710 | /* 34877 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12711 | /* 34879 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12712 | /* 34882 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12713 | /* 34888 */ GIR_RootConstrainSelectedInstOperands, |
| 12714 | /* 34889 */ // GIR_Coverage, 2871, |
| 12715 | /* 34889 */ GIR_EraseRootFromParent_Done, |
| 12716 | /* 34890 */ // Label 771: @34890 |
| 12717 | /* 34890 */ GIM_Try, /*On fail goto*//*Label 772*/ GIMT_Encode4(34927), // Rule ID 2872 // |
| 12718 | /* 34895 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 12719 | /* 34898 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 12720 | /* 34901 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12721 | /* 34905 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12722 | /* 34909 */ // (bitconvert:{ *:[v16i8] } QPR:{ *:[v4f32] }:$src) => (VREV32q8:{ *:[v16i8] } QPR:{ *:[v4f32] }:$src) |
| 12723 | /* 34909 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q8), |
| 12724 | /* 34912 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12725 | /* 34914 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12726 | /* 34916 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12727 | /* 34919 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12728 | /* 34925 */ GIR_RootConstrainSelectedInstOperands, |
| 12729 | /* 34926 */ // GIR_Coverage, 2872, |
| 12730 | /* 34926 */ GIR_EraseRootFromParent_Done, |
| 12731 | /* 34927 */ // Label 772: @34927 |
| 12732 | /* 34927 */ GIM_Try, /*On fail goto*//*Label 773*/ GIMT_Encode4(34964), // Rule ID 2873 // |
| 12733 | /* 34932 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 12734 | /* 34935 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 12735 | /* 34938 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12736 | /* 34942 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12737 | /* 34946 */ // (bitconvert:{ *:[v16i8] } QPR:{ *:[v4i32] }:$src) => (VREV32q8:{ *:[v16i8] } QPR:{ *:[v4i32] }:$src) |
| 12738 | /* 34946 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q8), |
| 12739 | /* 34949 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12740 | /* 34951 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12741 | /* 34953 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12742 | /* 34956 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12743 | /* 34962 */ GIR_RootConstrainSelectedInstOperands, |
| 12744 | /* 34963 */ // GIR_Coverage, 2873, |
| 12745 | /* 34963 */ GIR_EraseRootFromParent_Done, |
| 12746 | /* 34964 */ // Label 773: @34964 |
| 12747 | /* 34964 */ GIM_Try, /*On fail goto*//*Label 774*/ GIMT_Encode4(35001), // Rule ID 2874 // |
| 12748 | /* 34969 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 12749 | /* 34972 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 12750 | /* 34975 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12751 | /* 34979 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12752 | /* 34983 */ // (bitconvert:{ *:[v16i8] } QPR:{ *:[v8f16] }:$src) => (VREV16q8:{ *:[v16i8] } QPR:{ *:[v8f16] }:$src) |
| 12753 | /* 34983 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV16q8), |
| 12754 | /* 34986 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12755 | /* 34988 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12756 | /* 34990 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12757 | /* 34993 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12758 | /* 34999 */ GIR_RootConstrainSelectedInstOperands, |
| 12759 | /* 35000 */ // GIR_Coverage, 2874, |
| 12760 | /* 35000 */ GIR_EraseRootFromParent_Done, |
| 12761 | /* 35001 */ // Label 774: @35001 |
| 12762 | /* 35001 */ GIM_Try, /*On fail goto*//*Label 775*/ GIMT_Encode4(35038), // Rule ID 2875 // |
| 12763 | /* 35006 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE), |
| 12764 | /* 35009 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 12765 | /* 35012 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12766 | /* 35016 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12767 | /* 35020 */ // (bitconvert:{ *:[v16i8] } QPR:{ *:[v8i16] }:$src) => (VREV16q8:{ *:[v16i8] } QPR:{ *:[v8i16] }:$src) |
| 12768 | /* 35020 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV16q8), |
| 12769 | /* 35023 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12770 | /* 35025 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12771 | /* 35027 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12772 | /* 35030 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12773 | /* 35036 */ GIR_RootConstrainSelectedInstOperands, |
| 12774 | /* 35037 */ // GIR_Coverage, 2875, |
| 12775 | /* 35037 */ GIR_EraseRootFromParent_Done, |
| 12776 | /* 35038 */ // Label 775: @35038 |
| 12777 | /* 35038 */ GIM_Try, /*On fail goto*//*Label 776*/ GIMT_Encode4(35070), // Rule ID 5319 // |
| 12778 | /* 35043 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), |
| 12779 | /* 35046 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 12780 | /* 35049 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12781 | /* 35053 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12782 | /* 35057 */ // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v2f64] }:$src) => MQPR:{ *:[v16i8] }:$src |
| 12783 | /* 35057 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12784 | /* 35060 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12785 | /* 35062 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12786 | /* 35064 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 12787 | /* 35069 */ // GIR_Coverage, 5319, |
| 12788 | /* 35069 */ GIR_EraseRootFromParent_Done, |
| 12789 | /* 35070 */ // Label 776: @35070 |
| 12790 | /* 35070 */ GIM_Try, /*On fail goto*//*Label 777*/ GIMT_Encode4(35102), // Rule ID 5320 // |
| 12791 | /* 35075 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), |
| 12792 | /* 35078 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 12793 | /* 35081 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12794 | /* 35085 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12795 | /* 35089 */ // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v2i64] }:$src) => MQPR:{ *:[v16i8] }:$src |
| 12796 | /* 35089 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12797 | /* 35092 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12798 | /* 35094 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12799 | /* 35096 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 12800 | /* 35101 */ // GIR_Coverage, 5320, |
| 12801 | /* 35101 */ GIR_EraseRootFromParent_Done, |
| 12802 | /* 35102 */ // Label 777: @35102 |
| 12803 | /* 35102 */ GIM_Try, /*On fail goto*//*Label 778*/ GIMT_Encode4(35134), // Rule ID 5321 // |
| 12804 | /* 35107 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), |
| 12805 | /* 35110 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 12806 | /* 35113 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12807 | /* 35117 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12808 | /* 35121 */ // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v4f32] }:$src) => MQPR:{ *:[v16i8] }:$src |
| 12809 | /* 35121 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12810 | /* 35124 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12811 | /* 35126 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12812 | /* 35128 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 12813 | /* 35133 */ // GIR_Coverage, 5321, |
| 12814 | /* 35133 */ GIR_EraseRootFromParent_Done, |
| 12815 | /* 35134 */ // Label 778: @35134 |
| 12816 | /* 35134 */ GIM_Try, /*On fail goto*//*Label 779*/ GIMT_Encode4(35166), // Rule ID 5322 // |
| 12817 | /* 35139 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), |
| 12818 | /* 35142 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 12819 | /* 35145 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12820 | /* 35149 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12821 | /* 35153 */ // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v4i32] }:$src) => MQPR:{ *:[v16i8] }:$src |
| 12822 | /* 35153 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12823 | /* 35156 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12824 | /* 35158 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12825 | /* 35160 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 12826 | /* 35165 */ // GIR_Coverage, 5322, |
| 12827 | /* 35165 */ GIR_EraseRootFromParent_Done, |
| 12828 | /* 35166 */ // Label 779: @35166 |
| 12829 | /* 35166 */ GIM_Try, /*On fail goto*//*Label 780*/ GIMT_Encode4(35198), // Rule ID 5323 // |
| 12830 | /* 35171 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), |
| 12831 | /* 35174 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 12832 | /* 35177 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12833 | /* 35181 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12834 | /* 35185 */ // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v8f16] }:$src) => MQPR:{ *:[v16i8] }:$src |
| 12835 | /* 35185 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12836 | /* 35188 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12837 | /* 35190 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12838 | /* 35192 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 12839 | /* 35197 */ // GIR_Coverage, 5323, |
| 12840 | /* 35197 */ GIR_EraseRootFromParent_Done, |
| 12841 | /* 35198 */ // Label 780: @35198 |
| 12842 | /* 35198 */ GIM_Try, /*On fail goto*//*Label 781*/ GIMT_Encode4(35230), // Rule ID 5324 // |
| 12843 | /* 35203 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE), |
| 12844 | /* 35206 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 12845 | /* 35209 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12846 | /* 35213 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12847 | /* 35217 */ // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v8i16] }:$src) => MQPR:{ *:[v16i8] }:$src |
| 12848 | /* 35217 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12849 | /* 35220 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12850 | /* 35222 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12851 | /* 35224 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 12852 | /* 35229 */ // GIR_Coverage, 5324, |
| 12853 | /* 35229 */ GIR_EraseRootFromParent_Done, |
| 12854 | /* 35230 */ // Label 781: @35230 |
| 12855 | /* 35230 */ GIM_Try, /*On fail goto*//*Label 782*/ GIMT_Encode4(35288), // Rule ID 5355 // |
| 12856 | /* 35235 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), |
| 12857 | /* 35238 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 12858 | /* 35241 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12859 | /* 35245 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12860 | /* 35249 */ // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v2f64] }:$src) => (MVE_VREV64_8:{ *:[v16i8] } MQPR:{ *:[v2f64] }:$src) |
| 12861 | /* 35249 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 12862 | /* 35252 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 12863 | /* 35256 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 12864 | /* 35261 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_8), |
| 12865 | /* 35264 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 12866 | /* 35266 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12867 | /* 35268 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 12868 | /* 35271 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12869 | /* 35277 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12870 | /* 35283 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 12871 | /* 35286 */ GIR_RootConstrainSelectedInstOperands, |
| 12872 | /* 35287 */ // GIR_Coverage, 5355, |
| 12873 | /* 35287 */ GIR_EraseRootFromParent_Done, |
| 12874 | /* 35288 */ // Label 782: @35288 |
| 12875 | /* 35288 */ GIM_Try, /*On fail goto*//*Label 783*/ GIMT_Encode4(35346), // Rule ID 5356 // |
| 12876 | /* 35293 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), |
| 12877 | /* 35296 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 12878 | /* 35299 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12879 | /* 35303 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12880 | /* 35307 */ // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v2i64] }:$src) => (MVE_VREV64_8:{ *:[v16i8] } MQPR:{ *:[v2i64] }:$src) |
| 12881 | /* 35307 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 12882 | /* 35310 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 12883 | /* 35314 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 12884 | /* 35319 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_8), |
| 12885 | /* 35322 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 12886 | /* 35324 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12887 | /* 35326 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 12888 | /* 35329 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12889 | /* 35335 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12890 | /* 35341 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 12891 | /* 35344 */ GIR_RootConstrainSelectedInstOperands, |
| 12892 | /* 35345 */ // GIR_Coverage, 5356, |
| 12893 | /* 35345 */ GIR_EraseRootFromParent_Done, |
| 12894 | /* 35346 */ // Label 783: @35346 |
| 12895 | /* 35346 */ GIM_Try, /*On fail goto*//*Label 784*/ GIMT_Encode4(35404), // Rule ID 5357 // |
| 12896 | /* 35351 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), |
| 12897 | /* 35354 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 12898 | /* 35357 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12899 | /* 35361 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12900 | /* 35365 */ // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v4f32] }:$src) => (MVE_VREV32_8:{ *:[v16i8] } MQPR:{ *:[v4f32] }:$src) |
| 12901 | /* 35365 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 12902 | /* 35368 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 12903 | /* 35372 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 12904 | /* 35377 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_8), |
| 12905 | /* 35380 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 12906 | /* 35382 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12907 | /* 35384 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 12908 | /* 35387 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12909 | /* 35393 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12910 | /* 35399 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 12911 | /* 35402 */ GIR_RootConstrainSelectedInstOperands, |
| 12912 | /* 35403 */ // GIR_Coverage, 5357, |
| 12913 | /* 35403 */ GIR_EraseRootFromParent_Done, |
| 12914 | /* 35404 */ // Label 784: @35404 |
| 12915 | /* 35404 */ GIM_Try, /*On fail goto*//*Label 785*/ GIMT_Encode4(35462), // Rule ID 5358 // |
| 12916 | /* 35409 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), |
| 12917 | /* 35412 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 12918 | /* 35415 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12919 | /* 35419 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12920 | /* 35423 */ // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v4i32] }:$src) => (MVE_VREV32_8:{ *:[v16i8] } MQPR:{ *:[v4i32] }:$src) |
| 12921 | /* 35423 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 12922 | /* 35426 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 12923 | /* 35430 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 12924 | /* 35435 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_8), |
| 12925 | /* 35438 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 12926 | /* 35440 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12927 | /* 35442 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 12928 | /* 35445 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12929 | /* 35451 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12930 | /* 35457 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 12931 | /* 35460 */ GIR_RootConstrainSelectedInstOperands, |
| 12932 | /* 35461 */ // GIR_Coverage, 5358, |
| 12933 | /* 35461 */ GIR_EraseRootFromParent_Done, |
| 12934 | /* 35462 */ // Label 785: @35462 |
| 12935 | /* 35462 */ GIM_Try, /*On fail goto*//*Label 786*/ GIMT_Encode4(35520), // Rule ID 5359 // |
| 12936 | /* 35467 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), |
| 12937 | /* 35470 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 12938 | /* 35473 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12939 | /* 35477 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12940 | /* 35481 */ // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v8f16] }:$src) => (MVE_VREV16_8:{ *:[v16i8] } MQPR:{ *:[v8f16] }:$src) |
| 12941 | /* 35481 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 12942 | /* 35484 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 12943 | /* 35488 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 12944 | /* 35493 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV16_8), |
| 12945 | /* 35496 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 12946 | /* 35498 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12947 | /* 35500 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 12948 | /* 35503 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12949 | /* 35509 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12950 | /* 35515 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 12951 | /* 35518 */ GIR_RootConstrainSelectedInstOperands, |
| 12952 | /* 35519 */ // GIR_Coverage, 5359, |
| 12953 | /* 35519 */ GIR_EraseRootFromParent_Done, |
| 12954 | /* 35520 */ // Label 786: @35520 |
| 12955 | /* 35520 */ GIM_Try, /*On fail goto*//*Label 787*/ GIMT_Encode4(35578), // Rule ID 5360 // |
| 12956 | /* 35525 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE), |
| 12957 | /* 35528 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 12958 | /* 35531 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12959 | /* 35535 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12960 | /* 35539 */ // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v8i16] }:$src) => (MVE_VREV16_8:{ *:[v16i8] } MQPR:{ *:[v8i16] }:$src) |
| 12961 | /* 35539 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 12962 | /* 35542 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 12963 | /* 35546 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 12964 | /* 35551 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV16_8), |
| 12965 | /* 35554 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 12966 | /* 35556 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12967 | /* 35558 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 12968 | /* 35561 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12969 | /* 35567 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12970 | /* 35573 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 12971 | /* 35576 */ GIR_RootConstrainSelectedInstOperands, |
| 12972 | /* 35577 */ // GIR_Coverage, 5360, |
| 12973 | /* 35577 */ GIR_EraseRootFromParent_Done, |
| 12974 | /* 35578 */ // Label 787: @35578 |
| 12975 | /* 35578 */ GIM_Reject, |
| 12976 | /* 35579 */ // Label 549: @35579 |
| 12977 | /* 35579 */ GIM_Reject, |
| 12978 | /* 35580 */ // Label 10: @35580 |
| 12979 | /* 35580 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 795*/ GIMT_Encode4(35987), |
| 12980 | /* 35591 */ /*GILLT_s16*//*Label 788*/ GIMT_Encode4(35643), |
| 12981 | /* 35595 */ /*GILLT_s32*//*Label 789*/ GIMT_Encode4(35681), |
| 12982 | /* 35599 */ /*GILLT_s64*//*Label 790*/ GIMT_Encode4(35719), GIMT_Encode4(0), |
| 12983 | /* 35607 */ /*GILLT_v2s32*//*Label 791*/ GIMT_Encode4(35757), GIMT_Encode4(0), GIMT_Encode4(0), |
| 12984 | /* 35619 */ /*GILLT_v4s16*//*Label 792*/ GIMT_Encode4(35784), |
| 12985 | /* 35623 */ /*GILLT_v4s32*//*Label 793*/ GIMT_Encode4(35811), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 12986 | /* 35639 */ /*GILLT_v8s16*//*Label 794*/ GIMT_Encode4(35899), |
| 12987 | /* 35643 */ // Label 788: @35643 |
| 12988 | /* 35643 */ GIM_Try, /*On fail goto*//*Label 796*/ GIMT_Encode4(35680), // Rule ID 665 // |
| 12989 | /* 35648 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 12990 | /* 35651 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 12991 | /* 35654 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 12992 | /* 35658 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 12993 | /* 35662 */ // (ftrunc:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VRINTZH:{ *:[f16] } HPR:{ *:[f16] }:$Sm) |
| 12994 | /* 35662 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTZH), |
| 12995 | /* 35665 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 12996 | /* 35667 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm |
| 12997 | /* 35669 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12998 | /* 35672 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12999 | /* 35678 */ GIR_RootConstrainSelectedInstOperands, |
| 13000 | /* 35679 */ // GIR_Coverage, 665, |
| 13001 | /* 35679 */ GIR_EraseRootFromParent_Done, |
| 13002 | /* 35680 */ // Label 796: @35680 |
| 13003 | /* 35680 */ GIM_Reject, |
| 13004 | /* 35681 */ // Label 789: @35681 |
| 13005 | /* 35681 */ GIM_Try, /*On fail goto*//*Label 797*/ GIMT_Encode4(35718), // Rule ID 666 // |
| 13006 | /* 35686 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8), |
| 13007 | /* 35689 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 13008 | /* 35692 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 13009 | /* 35696 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 13010 | /* 35700 */ // (ftrunc:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VRINTZS:{ *:[f32] } SPR:{ *:[f32] }:$Sm) |
| 13011 | /* 35700 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTZS), |
| 13012 | /* 35703 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 13013 | /* 35705 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm |
| 13014 | /* 35707 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 13015 | /* 35710 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13016 | /* 35716 */ GIR_RootConstrainSelectedInstOperands, |
| 13017 | /* 35717 */ // GIR_Coverage, 666, |
| 13018 | /* 35717 */ GIR_EraseRootFromParent_Done, |
| 13019 | /* 35718 */ // Label 797: @35718 |
| 13020 | /* 35718 */ GIM_Reject, |
| 13021 | /* 35719 */ // Label 790: @35719 |
| 13022 | /* 35719 */ GIM_Try, /*On fail goto*//*Label 798*/ GIMT_Encode4(35756), // Rule ID 667 // |
| 13023 | /* 35724 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), |
| 13024 | /* 35727 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 13025 | /* 35730 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13026 | /* 35734 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13027 | /* 35738 */ // (ftrunc:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VRINTZD:{ *:[f64] } DPR:{ *:[f64] }:$Dm) |
| 13028 | /* 35738 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTZD), |
| 13029 | /* 35741 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 13030 | /* 35743 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dm |
| 13031 | /* 35745 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 13032 | /* 35748 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13033 | /* 35754 */ GIR_RootConstrainSelectedInstOperands, |
| 13034 | /* 35755 */ // GIR_Coverage, 667, |
| 13035 | /* 35755 */ GIR_EraseRootFromParent_Done, |
| 13036 | /* 35756 */ // Label 798: @35756 |
| 13037 | /* 35756 */ GIM_Reject, |
| 13038 | /* 35757 */ // Label 791: @35757 |
| 13039 | /* 35757 */ GIM_Try, /*On fail goto*//*Label 799*/ GIMT_Encode4(35783), // Rule ID 1703 // |
| 13040 | /* 35762 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8), |
| 13041 | /* 35765 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 13042 | /* 35768 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13043 | /* 35772 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13044 | /* 35776 */ // (ftrunc:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) => (VRINTZNDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) |
| 13045 | /* 35776 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTZNDf), |
| 13046 | /* 35781 */ GIR_RootConstrainSelectedInstOperands, |
| 13047 | /* 35782 */ // GIR_Coverage, 1703, |
| 13048 | /* 35782 */ GIR_Done, |
| 13049 | /* 35783 */ // Label 799: @35783 |
| 13050 | /* 35783 */ GIM_Reject, |
| 13051 | /* 35784 */ // Label 792: @35784 |
| 13052 | /* 35784 */ GIM_Try, /*On fail goto*//*Label 800*/ GIMT_Encode4(35810), // Rule ID 1705 // |
| 13053 | /* 35789 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), |
| 13054 | /* 35792 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 13055 | /* 35795 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13056 | /* 35799 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13057 | /* 35803 */ // (ftrunc:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) => (VRINTZNDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) |
| 13058 | /* 35803 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTZNDh), |
| 13059 | /* 35808 */ GIR_RootConstrainSelectedInstOperands, |
| 13060 | /* 35809 */ // GIR_Coverage, 1705, |
| 13061 | /* 35809 */ GIR_Done, |
| 13062 | /* 35810 */ // Label 800: @35810 |
| 13063 | /* 35810 */ GIM_Reject, |
| 13064 | /* 35811 */ // Label 793: @35811 |
| 13065 | /* 35811 */ GIM_Try, /*On fail goto*//*Label 801*/ GIMT_Encode4(35898), |
| 13066 | /* 35816 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 13067 | /* 35819 */ GIM_Try, /*On fail goto*//*Label 802*/ GIMT_Encode4(35842), // Rule ID 1704 // |
| 13068 | /* 35824 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8), |
| 13069 | /* 35827 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13070 | /* 35831 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13071 | /* 35835 */ // (ftrunc:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) => (VRINTZNQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) |
| 13072 | /* 35835 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTZNQf), |
| 13073 | /* 35840 */ GIR_RootConstrainSelectedInstOperands, |
| 13074 | /* 35841 */ // GIR_Coverage, 1704, |
| 13075 | /* 35841 */ GIR_Done, |
| 13076 | /* 35842 */ // Label 802: @35842 |
| 13077 | /* 35842 */ GIM_Try, /*On fail goto*//*Label 803*/ GIMT_Encode4(35897), // Rule ID 3982 // |
| 13078 | /* 35847 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 13079 | /* 35850 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13080 | /* 35854 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13081 | /* 35858 */ // (ftrunc:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val) => (MVE_VRINTf32Z:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val) |
| 13082 | /* 35858 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 13083 | /* 35861 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 13084 | /* 35865 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 13085 | /* 35870 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf32Z), |
| 13086 | /* 35873 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 13087 | /* 35875 */ GIR_RootToRootCopy, /*OpIdx*/1, // val |
| 13088 | /* 35877 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 13089 | /* 35880 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13090 | /* 35886 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13091 | /* 35892 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 13092 | /* 35895 */ GIR_RootConstrainSelectedInstOperands, |
| 13093 | /* 35896 */ // GIR_Coverage, 3982, |
| 13094 | /* 35896 */ GIR_EraseRootFromParent_Done, |
| 13095 | /* 35897 */ // Label 803: @35897 |
| 13096 | /* 35897 */ GIM_Reject, |
| 13097 | /* 35898 */ // Label 801: @35898 |
| 13098 | /* 35898 */ GIM_Reject, |
| 13099 | /* 35899 */ // Label 794: @35899 |
| 13100 | /* 35899 */ GIM_Try, /*On fail goto*//*Label 804*/ GIMT_Encode4(35986), |
| 13101 | /* 35904 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 13102 | /* 35907 */ GIM_Try, /*On fail goto*//*Label 805*/ GIMT_Encode4(35930), // Rule ID 1706 // |
| 13103 | /* 35912 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), |
| 13104 | /* 35915 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13105 | /* 35919 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13106 | /* 35923 */ // (ftrunc:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) => (VRINTZNQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) |
| 13107 | /* 35923 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTZNQh), |
| 13108 | /* 35928 */ GIR_RootConstrainSelectedInstOperands, |
| 13109 | /* 35929 */ // GIR_Coverage, 1706, |
| 13110 | /* 35929 */ GIR_Done, |
| 13111 | /* 35930 */ // Label 805: @35930 |
| 13112 | /* 35930 */ GIM_Try, /*On fail goto*//*Label 806*/ GIMT_Encode4(35985), // Rule ID 3970 // |
| 13113 | /* 35935 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 13114 | /* 35938 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13115 | /* 35942 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13116 | /* 35946 */ // (ftrunc:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val) => (MVE_VRINTf16Z:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val) |
| 13117 | /* 35946 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 13118 | /* 35949 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 13119 | /* 35953 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 13120 | /* 35958 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf16Z), |
| 13121 | /* 35961 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 13122 | /* 35963 */ GIR_RootToRootCopy, /*OpIdx*/1, // val |
| 13123 | /* 35965 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 13124 | /* 35968 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13125 | /* 35974 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13126 | /* 35980 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 13127 | /* 35983 */ GIR_RootConstrainSelectedInstOperands, |
| 13128 | /* 35984 */ // GIR_Coverage, 3970, |
| 13129 | /* 35984 */ GIR_EraseRootFromParent_Done, |
| 13130 | /* 35985 */ // Label 806: @35985 |
| 13131 | /* 35985 */ GIM_Reject, |
| 13132 | /* 35986 */ // Label 804: @35986 |
| 13133 | /* 35986 */ GIM_Reject, |
| 13134 | /* 35987 */ // Label 795: @35987 |
| 13135 | /* 35987 */ GIM_Reject, |
| 13136 | /* 35988 */ // Label 11: @35988 |
| 13137 | /* 35988 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 814*/ GIMT_Encode4(36362), |
| 13138 | /* 35999 */ /*GILLT_s16*//*Label 807*/ GIMT_Encode4(36051), |
| 13139 | /* 36003 */ /*GILLT_s32*//*Label 808*/ GIMT_Encode4(36078), |
| 13140 | /* 36007 */ /*GILLT_s64*//*Label 809*/ GIMT_Encode4(36105), GIMT_Encode4(0), |
| 13141 | /* 36015 */ /*GILLT_v2s32*//*Label 810*/ GIMT_Encode4(36132), GIMT_Encode4(0), GIMT_Encode4(0), |
| 13142 | /* 36027 */ /*GILLT_v4s16*//*Label 811*/ GIMT_Encode4(36159), |
| 13143 | /* 36031 */ /*GILLT_v4s32*//*Label 812*/ GIMT_Encode4(36186), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 13144 | /* 36047 */ /*GILLT_v8s16*//*Label 813*/ GIMT_Encode4(36274), |
| 13145 | /* 36051 */ // Label 807: @36051 |
| 13146 | /* 36051 */ GIM_Try, /*On fail goto*//*Label 815*/ GIMT_Encode4(36077), // Rule ID 674 // |
| 13147 | /* 36056 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 13148 | /* 36059 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 13149 | /* 36062 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 13150 | /* 36066 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 13151 | /* 36070 */ // (fround:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VRINTAH:{ *:[f16] } HPR:{ *:[f16] }:$Sm) |
| 13152 | /* 36070 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTAH), |
| 13153 | /* 36075 */ GIR_RootConstrainSelectedInstOperands, |
| 13154 | /* 36076 */ // GIR_Coverage, 674, |
| 13155 | /* 36076 */ GIR_Done, |
| 13156 | /* 36077 */ // Label 815: @36077 |
| 13157 | /* 36077 */ GIM_Reject, |
| 13158 | /* 36078 */ // Label 808: @36078 |
| 13159 | /* 36078 */ GIM_Try, /*On fail goto*//*Label 816*/ GIMT_Encode4(36104), // Rule ID 675 // |
| 13160 | /* 36083 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8), |
| 13161 | /* 36086 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 13162 | /* 36089 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 13163 | /* 36093 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 13164 | /* 36097 */ // (fround:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VRINTAS:{ *:[f32] } SPR:{ *:[f32] }:$Sm) |
| 13165 | /* 36097 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTAS), |
| 13166 | /* 36102 */ GIR_RootConstrainSelectedInstOperands, |
| 13167 | /* 36103 */ // GIR_Coverage, 675, |
| 13168 | /* 36103 */ GIR_Done, |
| 13169 | /* 36104 */ // Label 816: @36104 |
| 13170 | /* 36104 */ GIM_Reject, |
| 13171 | /* 36105 */ // Label 809: @36105 |
| 13172 | /* 36105 */ GIM_Try, /*On fail goto*//*Label 817*/ GIMT_Encode4(36131), // Rule ID 676 // |
| 13173 | /* 36110 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), |
| 13174 | /* 36113 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 13175 | /* 36116 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13176 | /* 36120 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13177 | /* 36124 */ // (fround:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VRINTAD:{ *:[f64] } DPR:{ *:[f64] }:$Dm) |
| 13178 | /* 36124 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTAD), |
| 13179 | /* 36129 */ GIR_RootConstrainSelectedInstOperands, |
| 13180 | /* 36130 */ // GIR_Coverage, 676, |
| 13181 | /* 36130 */ GIR_Done, |
| 13182 | /* 36131 */ // Label 817: @36131 |
| 13183 | /* 36131 */ GIM_Reject, |
| 13184 | /* 36132 */ // Label 810: @36132 |
| 13185 | /* 36132 */ GIM_Try, /*On fail goto*//*Label 818*/ GIMT_Encode4(36158), // Rule ID 1699 // |
| 13186 | /* 36137 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8), |
| 13187 | /* 36140 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 13188 | /* 36143 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13189 | /* 36147 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13190 | /* 36151 */ // (fround:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) => (VRINTANDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) |
| 13191 | /* 36151 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTANDf), |
| 13192 | /* 36156 */ GIR_RootConstrainSelectedInstOperands, |
| 13193 | /* 36157 */ // GIR_Coverage, 1699, |
| 13194 | /* 36157 */ GIR_Done, |
| 13195 | /* 36158 */ // Label 818: @36158 |
| 13196 | /* 36158 */ GIM_Reject, |
| 13197 | /* 36159 */ // Label 811: @36159 |
| 13198 | /* 36159 */ GIM_Try, /*On fail goto*//*Label 819*/ GIMT_Encode4(36185), // Rule ID 1701 // |
| 13199 | /* 36164 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), |
| 13200 | /* 36167 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 13201 | /* 36170 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13202 | /* 36174 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13203 | /* 36178 */ // (fround:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) => (VRINTANDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) |
| 13204 | /* 36178 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTANDh), |
| 13205 | /* 36183 */ GIR_RootConstrainSelectedInstOperands, |
| 13206 | /* 36184 */ // GIR_Coverage, 1701, |
| 13207 | /* 36184 */ GIR_Done, |
| 13208 | /* 36185 */ // Label 819: @36185 |
| 13209 | /* 36185 */ GIM_Reject, |
| 13210 | /* 36186 */ // Label 812: @36186 |
| 13211 | /* 36186 */ GIM_Try, /*On fail goto*//*Label 820*/ GIMT_Encode4(36273), |
| 13212 | /* 36191 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 13213 | /* 36194 */ GIM_Try, /*On fail goto*//*Label 821*/ GIMT_Encode4(36217), // Rule ID 1700 // |
| 13214 | /* 36199 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8), |
| 13215 | /* 36202 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13216 | /* 36206 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13217 | /* 36210 */ // (fround:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) => (VRINTANQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) |
| 13218 | /* 36210 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTANQf), |
| 13219 | /* 36215 */ GIR_RootConstrainSelectedInstOperands, |
| 13220 | /* 36216 */ // GIR_Coverage, 1700, |
| 13221 | /* 36216 */ GIR_Done, |
| 13222 | /* 36217 */ // Label 821: @36217 |
| 13223 | /* 36217 */ GIM_Try, /*On fail goto*//*Label 822*/ GIMT_Encode4(36272), // Rule ID 3980 // |
| 13224 | /* 36222 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 13225 | /* 36225 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13226 | /* 36229 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13227 | /* 36233 */ // (fround:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val) => (MVE_VRINTf32A:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val) |
| 13228 | /* 36233 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 13229 | /* 36236 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 13230 | /* 36240 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 13231 | /* 36245 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf32A), |
| 13232 | /* 36248 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 13233 | /* 36250 */ GIR_RootToRootCopy, /*OpIdx*/1, // val |
| 13234 | /* 36252 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 13235 | /* 36255 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13236 | /* 36261 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13237 | /* 36267 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 13238 | /* 36270 */ GIR_RootConstrainSelectedInstOperands, |
| 13239 | /* 36271 */ // GIR_Coverage, 3980, |
| 13240 | /* 36271 */ GIR_EraseRootFromParent_Done, |
| 13241 | /* 36272 */ // Label 822: @36272 |
| 13242 | /* 36272 */ GIM_Reject, |
| 13243 | /* 36273 */ // Label 820: @36273 |
| 13244 | /* 36273 */ GIM_Reject, |
| 13245 | /* 36274 */ // Label 813: @36274 |
| 13246 | /* 36274 */ GIM_Try, /*On fail goto*//*Label 823*/ GIMT_Encode4(36361), |
| 13247 | /* 36279 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 13248 | /* 36282 */ GIM_Try, /*On fail goto*//*Label 824*/ GIMT_Encode4(36305), // Rule ID 1702 // |
| 13249 | /* 36287 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), |
| 13250 | /* 36290 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13251 | /* 36294 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13252 | /* 36298 */ // (fround:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) => (VRINTANQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) |
| 13253 | /* 36298 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTANQh), |
| 13254 | /* 36303 */ GIR_RootConstrainSelectedInstOperands, |
| 13255 | /* 36304 */ // GIR_Coverage, 1702, |
| 13256 | /* 36304 */ GIR_Done, |
| 13257 | /* 36305 */ // Label 824: @36305 |
| 13258 | /* 36305 */ GIM_Try, /*On fail goto*//*Label 825*/ GIMT_Encode4(36360), // Rule ID 3968 // |
| 13259 | /* 36310 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 13260 | /* 36313 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13261 | /* 36317 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13262 | /* 36321 */ // (fround:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val) => (MVE_VRINTf16A:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val) |
| 13263 | /* 36321 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 13264 | /* 36324 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 13265 | /* 36328 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 13266 | /* 36333 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf16A), |
| 13267 | /* 36336 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 13268 | /* 36338 */ GIR_RootToRootCopy, /*OpIdx*/1, // val |
| 13269 | /* 36340 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 13270 | /* 36343 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13271 | /* 36349 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13272 | /* 36355 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 13273 | /* 36358 */ GIR_RootConstrainSelectedInstOperands, |
| 13274 | /* 36359 */ // GIR_Coverage, 3968, |
| 13275 | /* 36359 */ GIR_EraseRootFromParent_Done, |
| 13276 | /* 36360 */ // Label 825: @36360 |
| 13277 | /* 36360 */ GIM_Reject, |
| 13278 | /* 36361 */ // Label 823: @36361 |
| 13279 | /* 36361 */ GIM_Reject, |
| 13280 | /* 36362 */ // Label 814: @36362 |
| 13281 | /* 36362 */ GIM_Reject, |
| 13282 | /* 36363 */ // Label 12: @36363 |
| 13283 | /* 36363 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 831*/ GIMT_Encode4(36625), |
| 13284 | /* 36374 */ /*GILLT_s16*//*Label 826*/ GIMT_Encode4(36426), |
| 13285 | /* 36378 */ /*GILLT_s32*//*Label 827*/ GIMT_Encode4(36453), |
| 13286 | /* 36382 */ /*GILLT_s64*//*Label 828*/ GIMT_Encode4(36480), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 13287 | /* 36406 */ /*GILLT_v4s32*//*Label 829*/ GIMT_Encode4(36507), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 13288 | /* 36422 */ /*GILLT_v8s16*//*Label 830*/ GIMT_Encode4(36566), |
| 13289 | /* 36426 */ // Label 826: @36426 |
| 13290 | /* 36426 */ GIM_Try, /*On fail goto*//*Label 832*/ GIMT_Encode4(36452), // Rule ID 678 // |
| 13291 | /* 36431 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 13292 | /* 36434 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 13293 | /* 36437 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 13294 | /* 36441 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 13295 | /* 36445 */ // (froundeven:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VRINTNH:{ *:[f16] } HPR:{ *:[f16] }:$Sm) |
| 13296 | /* 36445 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTNH), |
| 13297 | /* 36450 */ GIR_RootConstrainSelectedInstOperands, |
| 13298 | /* 36451 */ // GIR_Coverage, 678, |
| 13299 | /* 36451 */ GIR_Done, |
| 13300 | /* 36452 */ // Label 832: @36452 |
| 13301 | /* 36452 */ GIM_Reject, |
| 13302 | /* 36453 */ // Label 827: @36453 |
| 13303 | /* 36453 */ GIM_Try, /*On fail goto*//*Label 833*/ GIMT_Encode4(36479), // Rule ID 680 // |
| 13304 | /* 36458 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8), |
| 13305 | /* 36461 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 13306 | /* 36464 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 13307 | /* 36468 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 13308 | /* 36472 */ // (froundeven:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VRINTNS:{ *:[f32] } SPR:{ *:[f32] }:$Sm) |
| 13309 | /* 36472 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTNS), |
| 13310 | /* 36477 */ GIR_RootConstrainSelectedInstOperands, |
| 13311 | /* 36478 */ // GIR_Coverage, 680, |
| 13312 | /* 36478 */ GIR_Done, |
| 13313 | /* 36479 */ // Label 833: @36479 |
| 13314 | /* 36479 */ GIM_Reject, |
| 13315 | /* 36480 */ // Label 828: @36480 |
| 13316 | /* 36480 */ GIM_Try, /*On fail goto*//*Label 834*/ GIMT_Encode4(36506), // Rule ID 682 // |
| 13317 | /* 36485 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), |
| 13318 | /* 36488 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 13319 | /* 36491 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13320 | /* 36495 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13321 | /* 36499 */ // (froundeven:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VRINTND:{ *:[f64] } DPR:{ *:[f64] }:$Dm) |
| 13322 | /* 36499 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTND), |
| 13323 | /* 36504 */ GIR_RootConstrainSelectedInstOperands, |
| 13324 | /* 36505 */ // GIR_Coverage, 682, |
| 13325 | /* 36505 */ GIR_Done, |
| 13326 | /* 36506 */ // Label 834: @36506 |
| 13327 | /* 36506 */ GIM_Reject, |
| 13328 | /* 36507 */ // Label 829: @36507 |
| 13329 | /* 36507 */ GIM_Try, /*On fail goto*//*Label 835*/ GIMT_Encode4(36565), // Rule ID 3976 // |
| 13330 | /* 36512 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 13331 | /* 36515 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 13332 | /* 36518 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13333 | /* 36522 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13334 | /* 36526 */ // (froundeven:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val) => (MVE_VRINTf32N:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val) |
| 13335 | /* 36526 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 13336 | /* 36529 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 13337 | /* 36533 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 13338 | /* 36538 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf32N), |
| 13339 | /* 36541 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 13340 | /* 36543 */ GIR_RootToRootCopy, /*OpIdx*/1, // val |
| 13341 | /* 36545 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 13342 | /* 36548 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13343 | /* 36554 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13344 | /* 36560 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 13345 | /* 36563 */ GIR_RootConstrainSelectedInstOperands, |
| 13346 | /* 36564 */ // GIR_Coverage, 3976, |
| 13347 | /* 36564 */ GIR_EraseRootFromParent_Done, |
| 13348 | /* 36565 */ // Label 835: @36565 |
| 13349 | /* 36565 */ GIM_Reject, |
| 13350 | /* 36566 */ // Label 830: @36566 |
| 13351 | /* 36566 */ GIM_Try, /*On fail goto*//*Label 836*/ GIMT_Encode4(36624), // Rule ID 3964 // |
| 13352 | /* 36571 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 13353 | /* 36574 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 13354 | /* 36577 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13355 | /* 36581 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13356 | /* 36585 */ // (froundeven:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val) => (MVE_VRINTf16N:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val) |
| 13357 | /* 36585 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 13358 | /* 36588 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 13359 | /* 36592 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 13360 | /* 36597 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf16N), |
| 13361 | /* 36600 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 13362 | /* 36602 */ GIR_RootToRootCopy, /*OpIdx*/1, // val |
| 13363 | /* 36604 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 13364 | /* 36607 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13365 | /* 36613 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13366 | /* 36619 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 13367 | /* 36622 */ GIR_RootConstrainSelectedInstOperands, |
| 13368 | /* 36623 */ // GIR_Coverage, 3964, |
| 13369 | /* 36623 */ GIR_EraseRootFromParent_Done, |
| 13370 | /* 36624 */ // Label 836: @36624 |
| 13371 | /* 36624 */ GIM_Reject, |
| 13372 | /* 36625 */ // Label 831: @36625 |
| 13373 | /* 36625 */ GIM_Reject, |
| 13374 | /* 36626 */ // Label 13: @36626 |
| 13375 | /* 36626 */ GIM_Try, /*On fail goto*//*Label 837*/ GIMT_Encode4(36788), |
| 13376 | /* 36631 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 13377 | /* 36634 */ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 13378 | /* 36637 */ GIM_Try, /*On fail goto*//*Label 838*/ GIMT_Encode4(36712), // Rule ID 2053 // |
| 13379 | /* 36642 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsThumb_IsThumb1Only), |
| 13380 | /* 36645 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 13381 | /* 36652 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 13382 | /* 36656 */ // MIs[0] Rn |
| 13383 | /* 36656 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 13384 | /* 36660 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 13385 | /* 36664 */ // (ld:{ *:[i32] } tGPR:{ *:[i32] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>> => (tLDRSB:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, (tMOVi8:{ *:[i32] } 0:{ *:[i32] })) |
| 13386 | /* 36664 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 13387 | /* 36667 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::tMOVi8), |
| 13388 | /* 36671 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 13389 | /* 36676 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define | RegState::Dead), |
| 13390 | /* 36682 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 13391 | /* 36685 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 13392 | /* 36688 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13393 | /* 36694 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 13394 | /* 36696 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tLDRSB), |
| 13395 | /* 36699 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt] |
| 13396 | /* 36701 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 13397 | /* 36703 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 13398 | /* 36706 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 13399 | /* 36710 */ GIR_RootConstrainSelectedInstOperands, |
| 13400 | /* 36711 */ // GIR_Coverage, 2053, |
| 13401 | /* 36711 */ GIR_EraseRootFromParent_Done, |
| 13402 | /* 36712 */ // Label 838: @36712 |
| 13403 | /* 36712 */ GIM_Try, /*On fail goto*//*Label 839*/ GIMT_Encode4(36787), // Rule ID 2054 // |
| 13404 | /* 36717 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsThumb_IsThumb1Only), |
| 13405 | /* 36720 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 13406 | /* 36727 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 13407 | /* 36731 */ // MIs[0] Rn |
| 13408 | /* 36731 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 13409 | /* 36735 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 13410 | /* 36739 */ // (ld:{ *:[i32] } tGPR:{ *:[i32] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>> => (tLDRSH:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, (tMOVi8:{ *:[i32] } 0:{ *:[i32] })) |
| 13411 | /* 36739 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 13412 | /* 36742 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::tMOVi8), |
| 13413 | /* 36746 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 13414 | /* 36751 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define | RegState::Dead), |
| 13415 | /* 36757 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 13416 | /* 36760 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 13417 | /* 36763 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13418 | /* 36769 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 13419 | /* 36771 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tLDRSH), |
| 13420 | /* 36774 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt] |
| 13421 | /* 36776 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 13422 | /* 36778 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 13423 | /* 36781 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 13424 | /* 36785 */ GIR_RootConstrainSelectedInstOperands, |
| 13425 | /* 36786 */ // GIR_Coverage, 2054, |
| 13426 | /* 36786 */ GIR_EraseRootFromParent_Done, |
| 13427 | /* 36787 */ // Label 839: @36787 |
| 13428 | /* 36787 */ GIM_Reject, |
| 13429 | /* 36788 */ // Label 837: @36788 |
| 13430 | /* 36788 */ GIM_Reject, |
| 13431 | /* 36789 */ // Label 14: @36789 |
| 13432 | /* 36789 */ GIM_Try, /*On fail goto*//*Label 840*/ GIMT_Encode4(36809), // Rule ID 5421 // |
| 13433 | /* 36794 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 13434 | /* 36797 */ // MIs[0] Operand 0 |
| 13435 | /* 36797 */ GIM_CheckIsImm, /*MI*/0, /*Op*/0, |
| 13436 | /* 36800 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/1, 0, |
| 13437 | /* 36804 */ // (atomic_fence (timm:{ *:[i32] }), 0:{ *:[i32] }) => (MEMBARRIER) |
| 13438 | /* 36804 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::MEMBARRIER), |
| 13439 | /* 36807 */ GIR_RootConstrainSelectedInstOperands, |
| 13440 | /* 36808 */ // GIR_Coverage, 5421, |
| 13441 | /* 36808 */ GIR_EraseRootFromParent_Done, |
| 13442 | /* 36809 */ // Label 840: @36809 |
| 13443 | /* 36809 */ GIM_Reject, |
| 13444 | /* 36810 */ // Label 15: @36810 |
| 13445 | /* 36810 */ GIM_Try, /*On fail goto*//*Label 841*/ GIMT_Encode4(41773), |
| 13446 | /* 36815 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, |
| 13447 | /* 36818 */ GIM_Try, /*On fail goto*//*Label 842*/ GIMT_Encode4(36866), // Rule ID 1856 // |
| 13448 | /* 36823 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 13449 | /* 36826 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uxtb16), |
| 13450 | /* 36831 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 13451 | /* 36834 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 13452 | /* 36837 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 13453 | /* 36841 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 13454 | /* 36845 */ // (intrinsic_wo_chain:{ *:[i32] } 3948:{ *:[iPTR] }, GPR:{ *:[i32] }:$Src) => (UXTB16:{ *:[i32] } GPR:{ *:[i32] }:$Src, 0:{ *:[i32] }) |
| 13455 | /* 36845 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UXTB16), |
| 13456 | /* 36848 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 13457 | /* 36850 */ GIR_RootToRootCopy, /*OpIdx*/2, // Src |
| 13458 | /* 36852 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 13459 | /* 36855 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 13460 | /* 36858 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13461 | /* 36864 */ GIR_RootConstrainSelectedInstOperands, |
| 13462 | /* 36865 */ // GIR_Coverage, 1856, |
| 13463 | /* 36865 */ GIR_EraseRootFromParent_Done, |
| 13464 | /* 36866 */ // Label 842: @36866 |
| 13465 | /* 36866 */ GIM_Try, /*On fail goto*//*Label 843*/ GIMT_Encode4(36914), // Rule ID 2110 // |
| 13466 | /* 36871 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 13467 | /* 36874 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uxtb16), |
| 13468 | /* 36879 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 13469 | /* 36882 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 13470 | /* 36885 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 13471 | /* 36889 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 13472 | /* 36893 */ // (intrinsic_wo_chain:{ *:[i32] } 3948:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rm) => (t2UXTB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] }) |
| 13473 | /* 36893 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UXTB16), |
| 13474 | /* 36896 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 13475 | /* 36898 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 13476 | /* 36900 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 13477 | /* 36903 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 13478 | /* 36906 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13479 | /* 36912 */ GIR_RootConstrainSelectedInstOperands, |
| 13480 | /* 36913 */ // GIR_Coverage, 2110, |
| 13481 | /* 36913 */ GIR_EraseRootFromParent_Done, |
| 13482 | /* 36914 */ // Label 843: @36914 |
| 13483 | /* 36914 */ GIM_Try, /*On fail goto*//*Label 844*/ GIMT_Encode4(36950), // Rule ID 677 // |
| 13484 | /* 36919 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 13485 | /* 36922 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrintn), |
| 13486 | /* 36927 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16, |
| 13487 | /* 36930 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 13488 | /* 36933 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 13489 | /* 36937 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 13490 | /* 36941 */ // (intrinsic_wo_chain:{ *:[f16] } 3837:{ *:[iPTR] }, HPR:{ *:[f16] }:$Sm) => (VRINTNH:{ *:[f16] } HPR:{ *:[f16] }:$Sm) |
| 13491 | /* 36941 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTNH), |
| 13492 | /* 36944 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 13493 | /* 36946 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 13494 | /* 36948 */ GIR_RootConstrainSelectedInstOperands, |
| 13495 | /* 36949 */ // GIR_Coverage, 677, |
| 13496 | /* 36949 */ GIR_EraseRootFromParent_Done, |
| 13497 | /* 36950 */ // Label 844: @36950 |
| 13498 | /* 36950 */ GIM_Try, /*On fail goto*//*Label 845*/ GIMT_Encode4(36986), // Rule ID 679 // |
| 13499 | /* 36955 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8), |
| 13500 | /* 36958 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrintn), |
| 13501 | /* 36963 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 13502 | /* 36966 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 13503 | /* 36969 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 13504 | /* 36973 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 13505 | /* 36977 */ // (intrinsic_wo_chain:{ *:[f32] } 3837:{ *:[iPTR] }, SPR:{ *:[f32] }:$Sm) => (VRINTNS:{ *:[f32] } SPR:{ *:[f32] }:$Sm) |
| 13506 | /* 36977 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTNS), |
| 13507 | /* 36980 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 13508 | /* 36982 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 13509 | /* 36984 */ GIR_RootConstrainSelectedInstOperands, |
| 13510 | /* 36985 */ // GIR_Coverage, 679, |
| 13511 | /* 36985 */ GIR_EraseRootFromParent_Done, |
| 13512 | /* 36986 */ // Label 845: @36986 |
| 13513 | /* 36986 */ GIM_Try, /*On fail goto*//*Label 846*/ GIMT_Encode4(37022), // Rule ID 681 // |
| 13514 | /* 36991 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), |
| 13515 | /* 36994 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrintn), |
| 13516 | /* 36999 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 13517 | /* 37002 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 13518 | /* 37005 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13519 | /* 37009 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13520 | /* 37013 */ // (intrinsic_wo_chain:{ *:[f64] } 3837:{ *:[iPTR] }, DPR:{ *:[f64] }:$Dm) => (VRINTND:{ *:[f64] } DPR:{ *:[f64] }:$Dm) |
| 13521 | /* 37013 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTND), |
| 13522 | /* 37016 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 13523 | /* 37018 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm |
| 13524 | /* 37020 */ GIR_RootConstrainSelectedInstOperands, |
| 13525 | /* 37021 */ // GIR_Coverage, 681, |
| 13526 | /* 37021 */ GIR_EraseRootFromParent_Done, |
| 13527 | /* 37022 */ // Label 846: @37022 |
| 13528 | /* 37022 */ GIM_Try, /*On fail goto*//*Label 847*/ GIMT_Encode4(37067), // Rule ID 696 // |
| 13529 | /* 37027 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), |
| 13530 | /* 37030 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_vcvtr), |
| 13531 | /* 37035 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 13532 | /* 37038 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 13533 | /* 37041 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 13534 | /* 37045 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13535 | /* 37049 */ // (intrinsic_wo_chain:{ *:[f32] } 3949:{ *:[iPTR] }, DPR:{ *:[f64] }:$Dm) => (VTOSIRD:{ *:[f32] } DPR:{ *:[f64] }:$Dm) |
| 13536 | /* 37049 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VTOSIRD), |
| 13537 | /* 37052 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 13538 | /* 37054 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm |
| 13539 | /* 37056 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 13540 | /* 37059 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13541 | /* 37065 */ GIR_RootConstrainSelectedInstOperands, |
| 13542 | /* 37066 */ // GIR_Coverage, 696, |
| 13543 | /* 37066 */ GIR_EraseRootFromParent_Done, |
| 13544 | /* 37067 */ // Label 847: @37067 |
| 13545 | /* 37067 */ GIM_Try, /*On fail goto*//*Label 848*/ GIMT_Encode4(37112), // Rule ID 697 // |
| 13546 | /* 37072 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), |
| 13547 | /* 37075 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_vcvtr), |
| 13548 | /* 37080 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 13549 | /* 37083 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 13550 | /* 37086 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 13551 | /* 37090 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 13552 | /* 37094 */ // (intrinsic_wo_chain:{ *:[f32] } 3949:{ *:[iPTR] }, SPR:{ *:[f32] }:$Sm) => (VTOSIRS:{ *:[f32] } SPR:{ *:[f32] }:$Sm) |
| 13553 | /* 37094 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VTOSIRS), |
| 13554 | /* 37097 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 13555 | /* 37099 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 13556 | /* 37101 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 13557 | /* 37104 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13558 | /* 37110 */ GIR_RootConstrainSelectedInstOperands, |
| 13559 | /* 37111 */ // GIR_Coverage, 697, |
| 13560 | /* 37111 */ GIR_EraseRootFromParent_Done, |
| 13561 | /* 37112 */ // Label 848: @37112 |
| 13562 | /* 37112 */ GIM_Try, /*On fail goto*//*Label 849*/ GIMT_Encode4(37157), // Rule ID 698 // |
| 13563 | /* 37117 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), |
| 13564 | /* 37120 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_vcvtru), |
| 13565 | /* 37125 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 13566 | /* 37128 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 13567 | /* 37131 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 13568 | /* 37135 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13569 | /* 37139 */ // (intrinsic_wo_chain:{ *:[f32] } 3950:{ *:[iPTR] }, DPR:{ *:[f64] }:$Dm) => (VTOUIRD:{ *:[f32] } DPR:{ *:[f64] }:$Dm) |
| 13570 | /* 37139 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VTOUIRD), |
| 13571 | /* 37142 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 13572 | /* 37144 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm |
| 13573 | /* 37146 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 13574 | /* 37149 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13575 | /* 37155 */ GIR_RootConstrainSelectedInstOperands, |
| 13576 | /* 37156 */ // GIR_Coverage, 698, |
| 13577 | /* 37156 */ GIR_EraseRootFromParent_Done, |
| 13578 | /* 37157 */ // Label 849: @37157 |
| 13579 | /* 37157 */ GIM_Try, /*On fail goto*//*Label 850*/ GIMT_Encode4(37202), // Rule ID 699 // |
| 13580 | /* 37162 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), |
| 13581 | /* 37165 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_vcvtru), |
| 13582 | /* 37170 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 13583 | /* 37173 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 13584 | /* 37176 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 13585 | /* 37180 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 13586 | /* 37184 */ // (intrinsic_wo_chain:{ *:[f32] } 3950:{ *:[iPTR] }, SPR:{ *:[f32] }:$Sm) => (VTOUIRS:{ *:[f32] } SPR:{ *:[f32] }:$Sm) |
| 13587 | /* 37184 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VTOUIRS), |
| 13588 | /* 37187 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 13589 | /* 37189 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 13590 | /* 37191 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 13591 | /* 37194 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13592 | /* 37200 */ GIR_RootConstrainSelectedInstOperands, |
| 13593 | /* 37201 */ // GIR_Coverage, 699, |
| 13594 | /* 37201 */ GIR_EraseRootFromParent_Done, |
| 13595 | /* 37202 */ // Label 850: @37202 |
| 13596 | /* 37202 */ GIM_Try, /*On fail goto*//*Label 851*/ GIMT_Encode4(37247), // Rule ID 1242 // |
| 13597 | /* 37207 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 13598 | /* 37210 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpaddls), |
| 13599 | /* 37215 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 13600 | /* 37218 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 13601 | /* 37221 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13602 | /* 37225 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13603 | /* 37229 */ // (intrinsic_wo_chain:{ *:[v4i16] } 3805:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm) => (VPADDLsv8i8:{ *:[v4i16] } DPR:{ *:[v8i8] }:$Vm) |
| 13604 | /* 37229 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLsv8i8), |
| 13605 | /* 37232 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13606 | /* 37234 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 13607 | /* 37236 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 13608 | /* 37239 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13609 | /* 37245 */ GIR_RootConstrainSelectedInstOperands, |
| 13610 | /* 37246 */ // GIR_Coverage, 1242, |
| 13611 | /* 37246 */ GIR_EraseRootFromParent_Done, |
| 13612 | /* 37247 */ // Label 851: @37247 |
| 13613 | /* 37247 */ GIM_Try, /*On fail goto*//*Label 852*/ GIMT_Encode4(37292), // Rule ID 1243 // |
| 13614 | /* 37252 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 13615 | /* 37255 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpaddls), |
| 13616 | /* 37260 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 13617 | /* 37263 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 13618 | /* 37266 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13619 | /* 37270 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13620 | /* 37274 */ // (intrinsic_wo_chain:{ *:[v2i32] } 3805:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm) => (VPADDLsv4i16:{ *:[v2i32] } DPR:{ *:[v4i16] }:$Vm) |
| 13621 | /* 37274 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLsv4i16), |
| 13622 | /* 37277 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13623 | /* 37279 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 13624 | /* 37281 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 13625 | /* 37284 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13626 | /* 37290 */ GIR_RootConstrainSelectedInstOperands, |
| 13627 | /* 37291 */ // GIR_Coverage, 1243, |
| 13628 | /* 37291 */ GIR_EraseRootFromParent_Done, |
| 13629 | /* 37292 */ // Label 852: @37292 |
| 13630 | /* 37292 */ GIM_Try, /*On fail goto*//*Label 853*/ GIMT_Encode4(37337), // Rule ID 1244 // |
| 13631 | /* 37297 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 13632 | /* 37300 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpaddls), |
| 13633 | /* 37305 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 13634 | /* 37308 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 13635 | /* 37311 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13636 | /* 37315 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13637 | /* 37319 */ // (intrinsic_wo_chain:{ *:[v1i64] } 3805:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm) => (VPADDLsv2i32:{ *:[v1i64] } DPR:{ *:[v2i32] }:$Vm) |
| 13638 | /* 37319 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLsv2i32), |
| 13639 | /* 37322 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13640 | /* 37324 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 13641 | /* 37326 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 13642 | /* 37329 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13643 | /* 37335 */ GIR_RootConstrainSelectedInstOperands, |
| 13644 | /* 37336 */ // GIR_Coverage, 1244, |
| 13645 | /* 37336 */ GIR_EraseRootFromParent_Done, |
| 13646 | /* 37337 */ // Label 853: @37337 |
| 13647 | /* 37337 */ GIM_Try, /*On fail goto*//*Label 854*/ GIMT_Encode4(37382), // Rule ID 1245 // |
| 13648 | /* 37342 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 13649 | /* 37345 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpaddls), |
| 13650 | /* 37350 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 13651 | /* 37353 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 13652 | /* 37356 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13653 | /* 37360 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13654 | /* 37364 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3805:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm) => (VPADDLsv16i8:{ *:[v8i16] } QPR:{ *:[v16i8] }:$Vm) |
| 13655 | /* 37364 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLsv16i8), |
| 13656 | /* 37367 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13657 | /* 37369 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 13658 | /* 37371 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 13659 | /* 37374 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13660 | /* 37380 */ GIR_RootConstrainSelectedInstOperands, |
| 13661 | /* 37381 */ // GIR_Coverage, 1245, |
| 13662 | /* 37381 */ GIR_EraseRootFromParent_Done, |
| 13663 | /* 37382 */ // Label 854: @37382 |
| 13664 | /* 37382 */ GIM_Try, /*On fail goto*//*Label 855*/ GIMT_Encode4(37427), // Rule ID 1246 // |
| 13665 | /* 37387 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 13666 | /* 37390 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpaddls), |
| 13667 | /* 37395 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 13668 | /* 37398 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 13669 | /* 37401 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13670 | /* 37405 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13671 | /* 37409 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3805:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm) => (VPADDLsv8i16:{ *:[v4i32] } QPR:{ *:[v8i16] }:$Vm) |
| 13672 | /* 37409 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLsv8i16), |
| 13673 | /* 37412 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13674 | /* 37414 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 13675 | /* 37416 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 13676 | /* 37419 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13677 | /* 37425 */ GIR_RootConstrainSelectedInstOperands, |
| 13678 | /* 37426 */ // GIR_Coverage, 1246, |
| 13679 | /* 37426 */ GIR_EraseRootFromParent_Done, |
| 13680 | /* 37427 */ // Label 855: @37427 |
| 13681 | /* 37427 */ GIM_Try, /*On fail goto*//*Label 856*/ GIMT_Encode4(37472), // Rule ID 1247 // |
| 13682 | /* 37432 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 13683 | /* 37435 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpaddls), |
| 13684 | /* 37440 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 13685 | /* 37443 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 13686 | /* 37446 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13687 | /* 37450 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13688 | /* 37454 */ // (intrinsic_wo_chain:{ *:[v2i64] } 3805:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm) => (VPADDLsv4i32:{ *:[v2i64] } QPR:{ *:[v4i32] }:$Vm) |
| 13689 | /* 37454 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLsv4i32), |
| 13690 | /* 37457 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13691 | /* 37459 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 13692 | /* 37461 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 13693 | /* 37464 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13694 | /* 37470 */ GIR_RootConstrainSelectedInstOperands, |
| 13695 | /* 37471 */ // GIR_Coverage, 1247, |
| 13696 | /* 37471 */ GIR_EraseRootFromParent_Done, |
| 13697 | /* 37472 */ // Label 856: @37472 |
| 13698 | /* 37472 */ GIM_Try, /*On fail goto*//*Label 857*/ GIMT_Encode4(37517), // Rule ID 1248 // |
| 13699 | /* 37477 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 13700 | /* 37480 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpaddlu), |
| 13701 | /* 37485 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 13702 | /* 37488 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 13703 | /* 37491 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13704 | /* 37495 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13705 | /* 37499 */ // (intrinsic_wo_chain:{ *:[v4i16] } 3806:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm) => (VPADDLuv8i8:{ *:[v4i16] } DPR:{ *:[v8i8] }:$Vm) |
| 13706 | /* 37499 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLuv8i8), |
| 13707 | /* 37502 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13708 | /* 37504 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 13709 | /* 37506 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 13710 | /* 37509 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13711 | /* 37515 */ GIR_RootConstrainSelectedInstOperands, |
| 13712 | /* 37516 */ // GIR_Coverage, 1248, |
| 13713 | /* 37516 */ GIR_EraseRootFromParent_Done, |
| 13714 | /* 37517 */ // Label 857: @37517 |
| 13715 | /* 37517 */ GIM_Try, /*On fail goto*//*Label 858*/ GIMT_Encode4(37562), // Rule ID 1249 // |
| 13716 | /* 37522 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 13717 | /* 37525 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpaddlu), |
| 13718 | /* 37530 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 13719 | /* 37533 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 13720 | /* 37536 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13721 | /* 37540 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13722 | /* 37544 */ // (intrinsic_wo_chain:{ *:[v2i32] } 3806:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm) => (VPADDLuv4i16:{ *:[v2i32] } DPR:{ *:[v4i16] }:$Vm) |
| 13723 | /* 37544 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLuv4i16), |
| 13724 | /* 37547 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13725 | /* 37549 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 13726 | /* 37551 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 13727 | /* 37554 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13728 | /* 37560 */ GIR_RootConstrainSelectedInstOperands, |
| 13729 | /* 37561 */ // GIR_Coverage, 1249, |
| 13730 | /* 37561 */ GIR_EraseRootFromParent_Done, |
| 13731 | /* 37562 */ // Label 858: @37562 |
| 13732 | /* 37562 */ GIM_Try, /*On fail goto*//*Label 859*/ GIMT_Encode4(37607), // Rule ID 1250 // |
| 13733 | /* 37567 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 13734 | /* 37570 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpaddlu), |
| 13735 | /* 37575 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 13736 | /* 37578 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 13737 | /* 37581 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13738 | /* 37585 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13739 | /* 37589 */ // (intrinsic_wo_chain:{ *:[v1i64] } 3806:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm) => (VPADDLuv2i32:{ *:[v1i64] } DPR:{ *:[v2i32] }:$Vm) |
| 13740 | /* 37589 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLuv2i32), |
| 13741 | /* 37592 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13742 | /* 37594 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 13743 | /* 37596 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 13744 | /* 37599 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13745 | /* 37605 */ GIR_RootConstrainSelectedInstOperands, |
| 13746 | /* 37606 */ // GIR_Coverage, 1250, |
| 13747 | /* 37606 */ GIR_EraseRootFromParent_Done, |
| 13748 | /* 37607 */ // Label 859: @37607 |
| 13749 | /* 37607 */ GIM_Try, /*On fail goto*//*Label 860*/ GIMT_Encode4(37652), // Rule ID 1251 // |
| 13750 | /* 37612 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 13751 | /* 37615 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpaddlu), |
| 13752 | /* 37620 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 13753 | /* 37623 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 13754 | /* 37626 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13755 | /* 37630 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13756 | /* 37634 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3806:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm) => (VPADDLuv16i8:{ *:[v8i16] } QPR:{ *:[v16i8] }:$Vm) |
| 13757 | /* 37634 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLuv16i8), |
| 13758 | /* 37637 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13759 | /* 37639 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 13760 | /* 37641 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 13761 | /* 37644 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13762 | /* 37650 */ GIR_RootConstrainSelectedInstOperands, |
| 13763 | /* 37651 */ // GIR_Coverage, 1251, |
| 13764 | /* 37651 */ GIR_EraseRootFromParent_Done, |
| 13765 | /* 37652 */ // Label 860: @37652 |
| 13766 | /* 37652 */ GIM_Try, /*On fail goto*//*Label 861*/ GIMT_Encode4(37697), // Rule ID 1252 // |
| 13767 | /* 37657 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 13768 | /* 37660 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpaddlu), |
| 13769 | /* 37665 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 13770 | /* 37668 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 13771 | /* 37671 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13772 | /* 37675 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13773 | /* 37679 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3806:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm) => (VPADDLuv8i16:{ *:[v4i32] } QPR:{ *:[v8i16] }:$Vm) |
| 13774 | /* 37679 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLuv8i16), |
| 13775 | /* 37682 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13776 | /* 37684 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 13777 | /* 37686 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 13778 | /* 37689 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13779 | /* 37695 */ GIR_RootConstrainSelectedInstOperands, |
| 13780 | /* 37696 */ // GIR_Coverage, 1252, |
| 13781 | /* 37696 */ GIR_EraseRootFromParent_Done, |
| 13782 | /* 37697 */ // Label 861: @37697 |
| 13783 | /* 37697 */ GIM_Try, /*On fail goto*//*Label 862*/ GIMT_Encode4(37742), // Rule ID 1253 // |
| 13784 | /* 37702 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 13785 | /* 37705 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpaddlu), |
| 13786 | /* 37710 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 13787 | /* 37713 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 13788 | /* 37716 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13789 | /* 37720 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13790 | /* 37724 */ // (intrinsic_wo_chain:{ *:[v2i64] } 3806:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm) => (VPADDLuv4i32:{ *:[v2i64] } QPR:{ *:[v4i32] }:$Vm) |
| 13791 | /* 37724 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLuv4i32), |
| 13792 | /* 37727 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13793 | /* 37729 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 13794 | /* 37731 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 13795 | /* 37734 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13796 | /* 37740 */ GIR_RootConstrainSelectedInstOperands, |
| 13797 | /* 37741 */ // GIR_Coverage, 1253, |
| 13798 | /* 37741 */ GIR_EraseRootFromParent_Done, |
| 13799 | /* 37742 */ // Label 862: @37742 |
| 13800 | /* 37742 */ GIM_Try, /*On fail goto*//*Label 863*/ GIMT_Encode4(37787), // Rule ID 1282 // |
| 13801 | /* 37747 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 13802 | /* 37750 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrecpe), |
| 13803 | /* 37755 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 13804 | /* 37758 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 13805 | /* 37761 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13806 | /* 37765 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13807 | /* 37769 */ // (intrinsic_wo_chain:{ *:[v2i32] } 3833:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm) => (VRECPEd:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm) |
| 13808 | /* 37769 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRECPEd), |
| 13809 | /* 37772 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13810 | /* 37774 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 13811 | /* 37776 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 13812 | /* 37779 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13813 | /* 37785 */ GIR_RootConstrainSelectedInstOperands, |
| 13814 | /* 37786 */ // GIR_Coverage, 1282, |
| 13815 | /* 37786 */ GIR_EraseRootFromParent_Done, |
| 13816 | /* 37787 */ // Label 863: @37787 |
| 13817 | /* 37787 */ GIM_Try, /*On fail goto*//*Label 864*/ GIMT_Encode4(37832), // Rule ID 1283 // |
| 13818 | /* 37792 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 13819 | /* 37795 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrecpe), |
| 13820 | /* 37800 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 13821 | /* 37803 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 13822 | /* 37806 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13823 | /* 37810 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13824 | /* 37814 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3833:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm) => (VRECPEq:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm) |
| 13825 | /* 37814 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRECPEq), |
| 13826 | /* 37817 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13827 | /* 37819 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 13828 | /* 37821 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 13829 | /* 37824 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13830 | /* 37830 */ GIR_RootConstrainSelectedInstOperands, |
| 13831 | /* 37831 */ // GIR_Coverage, 1283, |
| 13832 | /* 37831 */ GIR_EraseRootFromParent_Done, |
| 13833 | /* 37832 */ // Label 864: @37832 |
| 13834 | /* 37832 */ GIM_Try, /*On fail goto*//*Label 865*/ GIMT_Encode4(37877), // Rule ID 1284 // |
| 13835 | /* 37837 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 13836 | /* 37840 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrecpe), |
| 13837 | /* 37845 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 13838 | /* 37848 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 13839 | /* 37851 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13840 | /* 37855 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13841 | /* 37859 */ // (intrinsic_wo_chain:{ *:[v2f32] } 3833:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VRECPEfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) |
| 13842 | /* 37859 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRECPEfd), |
| 13843 | /* 37862 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13844 | /* 37864 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 13845 | /* 37866 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 13846 | /* 37869 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13847 | /* 37875 */ GIR_RootConstrainSelectedInstOperands, |
| 13848 | /* 37876 */ // GIR_Coverage, 1284, |
| 13849 | /* 37876 */ GIR_EraseRootFromParent_Done, |
| 13850 | /* 37877 */ // Label 865: @37877 |
| 13851 | /* 37877 */ GIM_Try, /*On fail goto*//*Label 866*/ GIMT_Encode4(37922), // Rule ID 1285 // |
| 13852 | /* 37882 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 13853 | /* 37885 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrecpe), |
| 13854 | /* 37890 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 13855 | /* 37893 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 13856 | /* 37896 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13857 | /* 37900 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13858 | /* 37904 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3833:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VRECPEfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) |
| 13859 | /* 37904 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRECPEfq), |
| 13860 | /* 37907 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13861 | /* 37909 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 13862 | /* 37911 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 13863 | /* 37914 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13864 | /* 37920 */ GIR_RootConstrainSelectedInstOperands, |
| 13865 | /* 37921 */ // GIR_Coverage, 1285, |
| 13866 | /* 37921 */ GIR_EraseRootFromParent_Done, |
| 13867 | /* 37922 */ // Label 866: @37922 |
| 13868 | /* 37922 */ GIM_Try, /*On fail goto*//*Label 867*/ GIMT_Encode4(37967), // Rule ID 1286 // |
| 13869 | /* 37927 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 13870 | /* 37930 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrecpe), |
| 13871 | /* 37935 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 13872 | /* 37938 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 13873 | /* 37941 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13874 | /* 37945 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13875 | /* 37949 */ // (intrinsic_wo_chain:{ *:[v4f16] } 3833:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VRECPEhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) |
| 13876 | /* 37949 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRECPEhd), |
| 13877 | /* 37952 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13878 | /* 37954 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 13879 | /* 37956 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 13880 | /* 37959 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13881 | /* 37965 */ GIR_RootConstrainSelectedInstOperands, |
| 13882 | /* 37966 */ // GIR_Coverage, 1286, |
| 13883 | /* 37966 */ GIR_EraseRootFromParent_Done, |
| 13884 | /* 37967 */ // Label 867: @37967 |
| 13885 | /* 37967 */ GIM_Try, /*On fail goto*//*Label 868*/ GIMT_Encode4(38012), // Rule ID 1287 // |
| 13886 | /* 37972 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 13887 | /* 37975 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrecpe), |
| 13888 | /* 37980 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 13889 | /* 37983 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 13890 | /* 37986 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13891 | /* 37990 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13892 | /* 37994 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3833:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VRECPEhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) |
| 13893 | /* 37994 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRECPEhq), |
| 13894 | /* 37997 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13895 | /* 37999 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 13896 | /* 38001 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 13897 | /* 38004 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13898 | /* 38010 */ GIR_RootConstrainSelectedInstOperands, |
| 13899 | /* 38011 */ // GIR_Coverage, 1287, |
| 13900 | /* 38011 */ GIR_EraseRootFromParent_Done, |
| 13901 | /* 38012 */ // Label 868: @38012 |
| 13902 | /* 38012 */ GIM_Try, /*On fail goto*//*Label 869*/ GIMT_Encode4(38057), // Rule ID 1292 // |
| 13903 | /* 38017 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 13904 | /* 38020 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrsqrte), |
| 13905 | /* 38025 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 13906 | /* 38028 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 13907 | /* 38031 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13908 | /* 38035 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13909 | /* 38039 */ // (intrinsic_wo_chain:{ *:[v2i32] } 3841:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm) => (VRSQRTEd:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm) |
| 13910 | /* 38039 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSQRTEd), |
| 13911 | /* 38042 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13912 | /* 38044 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 13913 | /* 38046 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 13914 | /* 38049 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13915 | /* 38055 */ GIR_RootConstrainSelectedInstOperands, |
| 13916 | /* 38056 */ // GIR_Coverage, 1292, |
| 13917 | /* 38056 */ GIR_EraseRootFromParent_Done, |
| 13918 | /* 38057 */ // Label 869: @38057 |
| 13919 | /* 38057 */ GIM_Try, /*On fail goto*//*Label 870*/ GIMT_Encode4(38102), // Rule ID 1293 // |
| 13920 | /* 38062 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 13921 | /* 38065 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrsqrte), |
| 13922 | /* 38070 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 13923 | /* 38073 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 13924 | /* 38076 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13925 | /* 38080 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13926 | /* 38084 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3841:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm) => (VRSQRTEq:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm) |
| 13927 | /* 38084 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSQRTEq), |
| 13928 | /* 38087 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13929 | /* 38089 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 13930 | /* 38091 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 13931 | /* 38094 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13932 | /* 38100 */ GIR_RootConstrainSelectedInstOperands, |
| 13933 | /* 38101 */ // GIR_Coverage, 1293, |
| 13934 | /* 38101 */ GIR_EraseRootFromParent_Done, |
| 13935 | /* 38102 */ // Label 870: @38102 |
| 13936 | /* 38102 */ GIM_Try, /*On fail goto*//*Label 871*/ GIMT_Encode4(38147), // Rule ID 1294 // |
| 13937 | /* 38107 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 13938 | /* 38110 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrsqrte), |
| 13939 | /* 38115 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 13940 | /* 38118 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 13941 | /* 38121 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13942 | /* 38125 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13943 | /* 38129 */ // (intrinsic_wo_chain:{ *:[v2f32] } 3841:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VRSQRTEfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) |
| 13944 | /* 38129 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSQRTEfd), |
| 13945 | /* 38132 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13946 | /* 38134 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 13947 | /* 38136 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 13948 | /* 38139 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13949 | /* 38145 */ GIR_RootConstrainSelectedInstOperands, |
| 13950 | /* 38146 */ // GIR_Coverage, 1294, |
| 13951 | /* 38146 */ GIR_EraseRootFromParent_Done, |
| 13952 | /* 38147 */ // Label 871: @38147 |
| 13953 | /* 38147 */ GIM_Try, /*On fail goto*//*Label 872*/ GIMT_Encode4(38192), // Rule ID 1295 // |
| 13954 | /* 38152 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 13955 | /* 38155 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrsqrte), |
| 13956 | /* 38160 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 13957 | /* 38163 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 13958 | /* 38166 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13959 | /* 38170 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13960 | /* 38174 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3841:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VRSQRTEfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) |
| 13961 | /* 38174 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSQRTEfq), |
| 13962 | /* 38177 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13963 | /* 38179 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 13964 | /* 38181 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 13965 | /* 38184 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13966 | /* 38190 */ GIR_RootConstrainSelectedInstOperands, |
| 13967 | /* 38191 */ // GIR_Coverage, 1295, |
| 13968 | /* 38191 */ GIR_EraseRootFromParent_Done, |
| 13969 | /* 38192 */ // Label 872: @38192 |
| 13970 | /* 38192 */ GIM_Try, /*On fail goto*//*Label 873*/ GIMT_Encode4(38237), // Rule ID 1296 // |
| 13971 | /* 38197 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 13972 | /* 38200 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrsqrte), |
| 13973 | /* 38205 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 13974 | /* 38208 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 13975 | /* 38211 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13976 | /* 38215 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13977 | /* 38219 */ // (intrinsic_wo_chain:{ *:[v4f16] } 3841:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VRSQRTEhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) |
| 13978 | /* 38219 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSQRTEhd), |
| 13979 | /* 38222 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13980 | /* 38224 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 13981 | /* 38226 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 13982 | /* 38229 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13983 | /* 38235 */ GIR_RootConstrainSelectedInstOperands, |
| 13984 | /* 38236 */ // GIR_Coverage, 1296, |
| 13985 | /* 38236 */ GIR_EraseRootFromParent_Done, |
| 13986 | /* 38237 */ // Label 873: @38237 |
| 13987 | /* 38237 */ GIM_Try, /*On fail goto*//*Label 874*/ GIMT_Encode4(38282), // Rule ID 1297 // |
| 13988 | /* 38242 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 13989 | /* 38245 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrsqrte), |
| 13990 | /* 38250 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 13991 | /* 38253 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 13992 | /* 38256 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13993 | /* 38260 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13994 | /* 38264 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3841:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VRSQRTEhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) |
| 13995 | /* 38264 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSQRTEhq), |
| 13996 | /* 38267 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13997 | /* 38269 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 13998 | /* 38271 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 13999 | /* 38274 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14000 | /* 38280 */ GIR_RootConstrainSelectedInstOperands, |
| 14001 | /* 38281 */ // GIR_Coverage, 1297, |
| 14002 | /* 38281 */ GIR_EraseRootFromParent_Done, |
| 14003 | /* 38282 */ // Label 874: @38282 |
| 14004 | /* 38282 */ GIM_Try, /*On fail goto*//*Label 875*/ GIMT_Encode4(38327), // Rule ID 1518 // |
| 14005 | /* 38287 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 14006 | /* 38290 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqabs), |
| 14007 | /* 38295 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, |
| 14008 | /* 38298 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 14009 | /* 38301 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14010 | /* 38305 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14011 | /* 38309 */ // (intrinsic_wo_chain:{ *:[v8i8] } 3811:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm) => (VQABSv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm) |
| 14012 | /* 38309 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQABSv8i8), |
| 14013 | /* 38312 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14014 | /* 38314 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14015 | /* 38316 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14016 | /* 38319 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14017 | /* 38325 */ GIR_RootConstrainSelectedInstOperands, |
| 14018 | /* 38326 */ // GIR_Coverage, 1518, |
| 14019 | /* 38326 */ GIR_EraseRootFromParent_Done, |
| 14020 | /* 38327 */ // Label 875: @38327 |
| 14021 | /* 38327 */ GIM_Try, /*On fail goto*//*Label 876*/ GIMT_Encode4(38372), // Rule ID 1519 // |
| 14022 | /* 38332 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 14023 | /* 38335 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqabs), |
| 14024 | /* 38340 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 14025 | /* 38343 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 14026 | /* 38346 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14027 | /* 38350 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14028 | /* 38354 */ // (intrinsic_wo_chain:{ *:[v4i16] } 3811:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm) => (VQABSv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm) |
| 14029 | /* 38354 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQABSv4i16), |
| 14030 | /* 38357 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14031 | /* 38359 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14032 | /* 38361 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14033 | /* 38364 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14034 | /* 38370 */ GIR_RootConstrainSelectedInstOperands, |
| 14035 | /* 38371 */ // GIR_Coverage, 1519, |
| 14036 | /* 38371 */ GIR_EraseRootFromParent_Done, |
| 14037 | /* 38372 */ // Label 876: @38372 |
| 14038 | /* 38372 */ GIM_Try, /*On fail goto*//*Label 877*/ GIMT_Encode4(38417), // Rule ID 1520 // |
| 14039 | /* 38377 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 14040 | /* 38380 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqabs), |
| 14041 | /* 38385 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 14042 | /* 38388 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 14043 | /* 38391 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14044 | /* 38395 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14045 | /* 38399 */ // (intrinsic_wo_chain:{ *:[v2i32] } 3811:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm) => (VQABSv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm) |
| 14046 | /* 38399 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQABSv2i32), |
| 14047 | /* 38402 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14048 | /* 38404 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14049 | /* 38406 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14050 | /* 38409 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14051 | /* 38415 */ GIR_RootConstrainSelectedInstOperands, |
| 14052 | /* 38416 */ // GIR_Coverage, 1520, |
| 14053 | /* 38416 */ GIR_EraseRootFromParent_Done, |
| 14054 | /* 38417 */ // Label 877: @38417 |
| 14055 | /* 38417 */ GIM_Try, /*On fail goto*//*Label 878*/ GIMT_Encode4(38462), // Rule ID 1521 // |
| 14056 | /* 38422 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 14057 | /* 38425 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqabs), |
| 14058 | /* 38430 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 14059 | /* 38433 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 14060 | /* 38436 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14061 | /* 38440 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14062 | /* 38444 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3811:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm) => (VQABSv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm) |
| 14063 | /* 38444 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQABSv16i8), |
| 14064 | /* 38447 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14065 | /* 38449 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14066 | /* 38451 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14067 | /* 38454 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14068 | /* 38460 */ GIR_RootConstrainSelectedInstOperands, |
| 14069 | /* 38461 */ // GIR_Coverage, 1521, |
| 14070 | /* 38461 */ GIR_EraseRootFromParent_Done, |
| 14071 | /* 38462 */ // Label 878: @38462 |
| 14072 | /* 38462 */ GIM_Try, /*On fail goto*//*Label 879*/ GIMT_Encode4(38507), // Rule ID 1522 // |
| 14073 | /* 38467 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 14074 | /* 38470 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqabs), |
| 14075 | /* 38475 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 14076 | /* 38478 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 14077 | /* 38481 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14078 | /* 38485 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14079 | /* 38489 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3811:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm) => (VQABSv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm) |
| 14080 | /* 38489 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQABSv8i16), |
| 14081 | /* 38492 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14082 | /* 38494 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14083 | /* 38496 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14084 | /* 38499 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14085 | /* 38505 */ GIR_RootConstrainSelectedInstOperands, |
| 14086 | /* 38506 */ // GIR_Coverage, 1522, |
| 14087 | /* 38506 */ GIR_EraseRootFromParent_Done, |
| 14088 | /* 38507 */ // Label 879: @38507 |
| 14089 | /* 38507 */ GIM_Try, /*On fail goto*//*Label 880*/ GIMT_Encode4(38552), // Rule ID 1523 // |
| 14090 | /* 38512 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 14091 | /* 38515 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqabs), |
| 14092 | /* 38520 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 14093 | /* 38523 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 14094 | /* 38526 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14095 | /* 38530 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14096 | /* 38534 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3811:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm) => (VQABSv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm) |
| 14097 | /* 38534 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQABSv4i32), |
| 14098 | /* 38537 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14099 | /* 38539 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14100 | /* 38541 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14101 | /* 38544 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14102 | /* 38550 */ GIR_RootConstrainSelectedInstOperands, |
| 14103 | /* 38551 */ // GIR_Coverage, 1523, |
| 14104 | /* 38551 */ GIR_EraseRootFromParent_Done, |
| 14105 | /* 38552 */ // Label 880: @38552 |
| 14106 | /* 38552 */ GIM_Try, /*On fail goto*//*Label 881*/ GIMT_Encode4(38597), // Rule ID 1534 // |
| 14107 | /* 38557 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 14108 | /* 38560 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqneg), |
| 14109 | /* 38565 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, |
| 14110 | /* 38568 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 14111 | /* 38571 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14112 | /* 38575 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14113 | /* 38579 */ // (intrinsic_wo_chain:{ *:[v8i8] } 3817:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm) => (VQNEGv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm) |
| 14114 | /* 38579 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQNEGv8i8), |
| 14115 | /* 38582 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14116 | /* 38584 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14117 | /* 38586 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14118 | /* 38589 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14119 | /* 38595 */ GIR_RootConstrainSelectedInstOperands, |
| 14120 | /* 38596 */ // GIR_Coverage, 1534, |
| 14121 | /* 38596 */ GIR_EraseRootFromParent_Done, |
| 14122 | /* 38597 */ // Label 881: @38597 |
| 14123 | /* 38597 */ GIM_Try, /*On fail goto*//*Label 882*/ GIMT_Encode4(38642), // Rule ID 1535 // |
| 14124 | /* 38602 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 14125 | /* 38605 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqneg), |
| 14126 | /* 38610 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 14127 | /* 38613 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 14128 | /* 38616 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14129 | /* 38620 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14130 | /* 38624 */ // (intrinsic_wo_chain:{ *:[v4i16] } 3817:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm) => (VQNEGv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm) |
| 14131 | /* 38624 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQNEGv4i16), |
| 14132 | /* 38627 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14133 | /* 38629 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14134 | /* 38631 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14135 | /* 38634 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14136 | /* 38640 */ GIR_RootConstrainSelectedInstOperands, |
| 14137 | /* 38641 */ // GIR_Coverage, 1535, |
| 14138 | /* 38641 */ GIR_EraseRootFromParent_Done, |
| 14139 | /* 38642 */ // Label 882: @38642 |
| 14140 | /* 38642 */ GIM_Try, /*On fail goto*//*Label 883*/ GIMT_Encode4(38687), // Rule ID 1536 // |
| 14141 | /* 38647 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 14142 | /* 38650 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqneg), |
| 14143 | /* 38655 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 14144 | /* 38658 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 14145 | /* 38661 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14146 | /* 38665 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14147 | /* 38669 */ // (intrinsic_wo_chain:{ *:[v2i32] } 3817:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm) => (VQNEGv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm) |
| 14148 | /* 38669 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQNEGv2i32), |
| 14149 | /* 38672 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14150 | /* 38674 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14151 | /* 38676 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14152 | /* 38679 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14153 | /* 38685 */ GIR_RootConstrainSelectedInstOperands, |
| 14154 | /* 38686 */ // GIR_Coverage, 1536, |
| 14155 | /* 38686 */ GIR_EraseRootFromParent_Done, |
| 14156 | /* 38687 */ // Label 883: @38687 |
| 14157 | /* 38687 */ GIM_Try, /*On fail goto*//*Label 884*/ GIMT_Encode4(38732), // Rule ID 1537 // |
| 14158 | /* 38692 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 14159 | /* 38695 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqneg), |
| 14160 | /* 38700 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 14161 | /* 38703 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 14162 | /* 38706 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14163 | /* 38710 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14164 | /* 38714 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3817:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm) => (VQNEGv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm) |
| 14165 | /* 38714 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQNEGv16i8), |
| 14166 | /* 38717 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14167 | /* 38719 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14168 | /* 38721 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14169 | /* 38724 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14170 | /* 38730 */ GIR_RootConstrainSelectedInstOperands, |
| 14171 | /* 38731 */ // GIR_Coverage, 1537, |
| 14172 | /* 38731 */ GIR_EraseRootFromParent_Done, |
| 14173 | /* 38732 */ // Label 884: @38732 |
| 14174 | /* 38732 */ GIM_Try, /*On fail goto*//*Label 885*/ GIMT_Encode4(38777), // Rule ID 1538 // |
| 14175 | /* 38737 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 14176 | /* 38740 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqneg), |
| 14177 | /* 38745 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 14178 | /* 38748 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 14179 | /* 38751 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14180 | /* 38755 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14181 | /* 38759 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3817:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm) => (VQNEGv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm) |
| 14182 | /* 38759 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQNEGv8i16), |
| 14183 | /* 38762 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14184 | /* 38764 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14185 | /* 38766 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14186 | /* 38769 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14187 | /* 38775 */ GIR_RootConstrainSelectedInstOperands, |
| 14188 | /* 38776 */ // GIR_Coverage, 1538, |
| 14189 | /* 38776 */ GIR_EraseRootFromParent_Done, |
| 14190 | /* 38777 */ // Label 885: @38777 |
| 14191 | /* 38777 */ GIM_Try, /*On fail goto*//*Label 886*/ GIMT_Encode4(38822), // Rule ID 1539 // |
| 14192 | /* 38782 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 14193 | /* 38785 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqneg), |
| 14194 | /* 38790 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 14195 | /* 38793 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 14196 | /* 38796 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14197 | /* 38800 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14198 | /* 38804 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3817:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm) => (VQNEGv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm) |
| 14199 | /* 38804 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQNEGv4i32), |
| 14200 | /* 38807 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14201 | /* 38809 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14202 | /* 38811 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14203 | /* 38814 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14204 | /* 38820 */ GIR_RootConstrainSelectedInstOperands, |
| 14205 | /* 38821 */ // GIR_Coverage, 1539, |
| 14206 | /* 38821 */ GIR_EraseRootFromParent_Done, |
| 14207 | /* 38822 */ // Label 886: @38822 |
| 14208 | /* 38822 */ GIM_Try, /*On fail goto*//*Label 887*/ GIMT_Encode4(38867), // Rule ID 1540 // |
| 14209 | /* 38827 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 14210 | /* 38830 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcls), |
| 14211 | /* 38835 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, |
| 14212 | /* 38838 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 14213 | /* 38841 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14214 | /* 38845 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14215 | /* 38849 */ // (intrinsic_wo_chain:{ *:[v8i8] } 3758:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm) => (VCLSv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm) |
| 14216 | /* 38849 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCLSv8i8), |
| 14217 | /* 38852 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14218 | /* 38854 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14219 | /* 38856 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14220 | /* 38859 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14221 | /* 38865 */ GIR_RootConstrainSelectedInstOperands, |
| 14222 | /* 38866 */ // GIR_Coverage, 1540, |
| 14223 | /* 38866 */ GIR_EraseRootFromParent_Done, |
| 14224 | /* 38867 */ // Label 887: @38867 |
| 14225 | /* 38867 */ GIM_Try, /*On fail goto*//*Label 888*/ GIMT_Encode4(38912), // Rule ID 1541 // |
| 14226 | /* 38872 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 14227 | /* 38875 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcls), |
| 14228 | /* 38880 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 14229 | /* 38883 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 14230 | /* 38886 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14231 | /* 38890 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14232 | /* 38894 */ // (intrinsic_wo_chain:{ *:[v4i16] } 3758:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm) => (VCLSv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm) |
| 14233 | /* 38894 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCLSv4i16), |
| 14234 | /* 38897 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14235 | /* 38899 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14236 | /* 38901 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14237 | /* 38904 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14238 | /* 38910 */ GIR_RootConstrainSelectedInstOperands, |
| 14239 | /* 38911 */ // GIR_Coverage, 1541, |
| 14240 | /* 38911 */ GIR_EraseRootFromParent_Done, |
| 14241 | /* 38912 */ // Label 888: @38912 |
| 14242 | /* 38912 */ GIM_Try, /*On fail goto*//*Label 889*/ GIMT_Encode4(38957), // Rule ID 1542 // |
| 14243 | /* 38917 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 14244 | /* 38920 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcls), |
| 14245 | /* 38925 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 14246 | /* 38928 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 14247 | /* 38931 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14248 | /* 38935 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14249 | /* 38939 */ // (intrinsic_wo_chain:{ *:[v2i32] } 3758:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm) => (VCLSv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm) |
| 14250 | /* 38939 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCLSv2i32), |
| 14251 | /* 38942 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14252 | /* 38944 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14253 | /* 38946 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14254 | /* 38949 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14255 | /* 38955 */ GIR_RootConstrainSelectedInstOperands, |
| 14256 | /* 38956 */ // GIR_Coverage, 1542, |
| 14257 | /* 38956 */ GIR_EraseRootFromParent_Done, |
| 14258 | /* 38957 */ // Label 889: @38957 |
| 14259 | /* 38957 */ GIM_Try, /*On fail goto*//*Label 890*/ GIMT_Encode4(39002), // Rule ID 1543 // |
| 14260 | /* 38962 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 14261 | /* 38965 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcls), |
| 14262 | /* 38970 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 14263 | /* 38973 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 14264 | /* 38976 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14265 | /* 38980 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14266 | /* 38984 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3758:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm) => (VCLSv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm) |
| 14267 | /* 38984 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCLSv16i8), |
| 14268 | /* 38987 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14269 | /* 38989 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14270 | /* 38991 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14271 | /* 38994 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14272 | /* 39000 */ GIR_RootConstrainSelectedInstOperands, |
| 14273 | /* 39001 */ // GIR_Coverage, 1543, |
| 14274 | /* 39001 */ GIR_EraseRootFromParent_Done, |
| 14275 | /* 39002 */ // Label 890: @39002 |
| 14276 | /* 39002 */ GIM_Try, /*On fail goto*//*Label 891*/ GIMT_Encode4(39047), // Rule ID 1544 // |
| 14277 | /* 39007 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 14278 | /* 39010 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcls), |
| 14279 | /* 39015 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 14280 | /* 39018 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 14281 | /* 39021 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14282 | /* 39025 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14283 | /* 39029 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3758:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm) => (VCLSv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm) |
| 14284 | /* 39029 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCLSv8i16), |
| 14285 | /* 39032 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14286 | /* 39034 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14287 | /* 39036 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14288 | /* 39039 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14289 | /* 39045 */ GIR_RootConstrainSelectedInstOperands, |
| 14290 | /* 39046 */ // GIR_Coverage, 1544, |
| 14291 | /* 39046 */ GIR_EraseRootFromParent_Done, |
| 14292 | /* 39047 */ // Label 891: @39047 |
| 14293 | /* 39047 */ GIM_Try, /*On fail goto*//*Label 892*/ GIMT_Encode4(39092), // Rule ID 1545 // |
| 14294 | /* 39052 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 14295 | /* 39055 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcls), |
| 14296 | /* 39060 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 14297 | /* 39063 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 14298 | /* 39066 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14299 | /* 39070 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14300 | /* 39074 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3758:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm) => (VCLSv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm) |
| 14301 | /* 39074 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCLSv4i32), |
| 14302 | /* 39077 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14303 | /* 39079 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14304 | /* 39081 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14305 | /* 39084 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14306 | /* 39090 */ GIR_RootConstrainSelectedInstOperands, |
| 14307 | /* 39091 */ // GIR_Coverage, 1545, |
| 14308 | /* 39091 */ GIR_EraseRootFromParent_Done, |
| 14309 | /* 39092 */ // Label 892: @39092 |
| 14310 | /* 39092 */ GIM_Try, /*On fail goto*//*Label 893*/ GIMT_Encode4(39137), // Rule ID 1589 // |
| 14311 | /* 39097 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 14312 | /* 39100 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqmovns), |
| 14313 | /* 39105 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, |
| 14314 | /* 39108 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 14315 | /* 39111 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14316 | /* 39115 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14317 | /* 39119 */ // (intrinsic_wo_chain:{ *:[v8i8] } 3814:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm) => (VQMOVNsv8i8:{ *:[v8i8] } QPR:{ *:[v8i16] }:$Vm) |
| 14318 | /* 39119 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQMOVNsv8i8), |
| 14319 | /* 39122 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14320 | /* 39124 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14321 | /* 39126 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14322 | /* 39129 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14323 | /* 39135 */ GIR_RootConstrainSelectedInstOperands, |
| 14324 | /* 39136 */ // GIR_Coverage, 1589, |
| 14325 | /* 39136 */ GIR_EraseRootFromParent_Done, |
| 14326 | /* 39137 */ // Label 893: @39137 |
| 14327 | /* 39137 */ GIM_Try, /*On fail goto*//*Label 894*/ GIMT_Encode4(39182), // Rule ID 1590 // |
| 14328 | /* 39142 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 14329 | /* 39145 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqmovns), |
| 14330 | /* 39150 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 14331 | /* 39153 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 14332 | /* 39156 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14333 | /* 39160 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14334 | /* 39164 */ // (intrinsic_wo_chain:{ *:[v4i16] } 3814:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm) => (VQMOVNsv4i16:{ *:[v4i16] } QPR:{ *:[v4i32] }:$Vm) |
| 14335 | /* 39164 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQMOVNsv4i16), |
| 14336 | /* 39167 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14337 | /* 39169 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14338 | /* 39171 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14339 | /* 39174 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14340 | /* 39180 */ GIR_RootConstrainSelectedInstOperands, |
| 14341 | /* 39181 */ // GIR_Coverage, 1590, |
| 14342 | /* 39181 */ GIR_EraseRootFromParent_Done, |
| 14343 | /* 39182 */ // Label 894: @39182 |
| 14344 | /* 39182 */ GIM_Try, /*On fail goto*//*Label 895*/ GIMT_Encode4(39227), // Rule ID 1591 // |
| 14345 | /* 39187 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 14346 | /* 39190 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqmovns), |
| 14347 | /* 39195 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 14348 | /* 39198 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 14349 | /* 39201 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14350 | /* 39205 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14351 | /* 39209 */ // (intrinsic_wo_chain:{ *:[v2i32] } 3814:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm) => (VQMOVNsv2i32:{ *:[v2i32] } QPR:{ *:[v2i64] }:$Vm) |
| 14352 | /* 39209 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQMOVNsv2i32), |
| 14353 | /* 39212 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14354 | /* 39214 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14355 | /* 39216 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14356 | /* 39219 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14357 | /* 39225 */ GIR_RootConstrainSelectedInstOperands, |
| 14358 | /* 39226 */ // GIR_Coverage, 1591, |
| 14359 | /* 39226 */ GIR_EraseRootFromParent_Done, |
| 14360 | /* 39227 */ // Label 895: @39227 |
| 14361 | /* 39227 */ GIM_Try, /*On fail goto*//*Label 896*/ GIMT_Encode4(39272), // Rule ID 1592 // |
| 14362 | /* 39232 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 14363 | /* 39235 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqmovnu), |
| 14364 | /* 39240 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, |
| 14365 | /* 39243 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 14366 | /* 39246 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14367 | /* 39250 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14368 | /* 39254 */ // (intrinsic_wo_chain:{ *:[v8i8] } 3816:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm) => (VQMOVNuv8i8:{ *:[v8i8] } QPR:{ *:[v8i16] }:$Vm) |
| 14369 | /* 39254 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQMOVNuv8i8), |
| 14370 | /* 39257 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14371 | /* 39259 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14372 | /* 39261 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14373 | /* 39264 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14374 | /* 39270 */ GIR_RootConstrainSelectedInstOperands, |
| 14375 | /* 39271 */ // GIR_Coverage, 1592, |
| 14376 | /* 39271 */ GIR_EraseRootFromParent_Done, |
| 14377 | /* 39272 */ // Label 896: @39272 |
| 14378 | /* 39272 */ GIM_Try, /*On fail goto*//*Label 897*/ GIMT_Encode4(39317), // Rule ID 1593 // |
| 14379 | /* 39277 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 14380 | /* 39280 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqmovnu), |
| 14381 | /* 39285 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 14382 | /* 39288 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 14383 | /* 39291 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14384 | /* 39295 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14385 | /* 39299 */ // (intrinsic_wo_chain:{ *:[v4i16] } 3816:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm) => (VQMOVNuv4i16:{ *:[v4i16] } QPR:{ *:[v4i32] }:$Vm) |
| 14386 | /* 39299 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQMOVNuv4i16), |
| 14387 | /* 39302 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14388 | /* 39304 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14389 | /* 39306 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14390 | /* 39309 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14391 | /* 39315 */ GIR_RootConstrainSelectedInstOperands, |
| 14392 | /* 39316 */ // GIR_Coverage, 1593, |
| 14393 | /* 39316 */ GIR_EraseRootFromParent_Done, |
| 14394 | /* 39317 */ // Label 897: @39317 |
| 14395 | /* 39317 */ GIM_Try, /*On fail goto*//*Label 898*/ GIMT_Encode4(39362), // Rule ID 1594 // |
| 14396 | /* 39322 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 14397 | /* 39325 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqmovnu), |
| 14398 | /* 39330 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 14399 | /* 39333 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 14400 | /* 39336 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14401 | /* 39340 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14402 | /* 39344 */ // (intrinsic_wo_chain:{ *:[v2i32] } 3816:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm) => (VQMOVNuv2i32:{ *:[v2i32] } QPR:{ *:[v2i64] }:$Vm) |
| 14403 | /* 39344 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQMOVNuv2i32), |
| 14404 | /* 39347 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14405 | /* 39349 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14406 | /* 39351 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14407 | /* 39354 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14408 | /* 39360 */ GIR_RootConstrainSelectedInstOperands, |
| 14409 | /* 39361 */ // GIR_Coverage, 1594, |
| 14410 | /* 39361 */ GIR_EraseRootFromParent_Done, |
| 14411 | /* 39362 */ // Label 898: @39362 |
| 14412 | /* 39362 */ GIM_Try, /*On fail goto*//*Label 899*/ GIMT_Encode4(39407), // Rule ID 1595 // |
| 14413 | /* 39367 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 14414 | /* 39370 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqmovnsu), |
| 14415 | /* 39375 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, |
| 14416 | /* 39378 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 14417 | /* 39381 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14418 | /* 39385 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14419 | /* 39389 */ // (intrinsic_wo_chain:{ *:[v8i8] } 3815:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm) => (VQMOVNsuv8i8:{ *:[v8i8] } QPR:{ *:[v8i16] }:$Vm) |
| 14420 | /* 39389 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQMOVNsuv8i8), |
| 14421 | /* 39392 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14422 | /* 39394 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14423 | /* 39396 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14424 | /* 39399 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14425 | /* 39405 */ GIR_RootConstrainSelectedInstOperands, |
| 14426 | /* 39406 */ // GIR_Coverage, 1595, |
| 14427 | /* 39406 */ GIR_EraseRootFromParent_Done, |
| 14428 | /* 39407 */ // Label 899: @39407 |
| 14429 | /* 39407 */ GIM_Try, /*On fail goto*//*Label 900*/ GIMT_Encode4(39452), // Rule ID 1596 // |
| 14430 | /* 39412 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 14431 | /* 39415 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqmovnsu), |
| 14432 | /* 39420 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 14433 | /* 39423 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 14434 | /* 39426 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14435 | /* 39430 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14436 | /* 39434 */ // (intrinsic_wo_chain:{ *:[v4i16] } 3815:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm) => (VQMOVNsuv4i16:{ *:[v4i16] } QPR:{ *:[v4i32] }:$Vm) |
| 14437 | /* 39434 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQMOVNsuv4i16), |
| 14438 | /* 39437 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14439 | /* 39439 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14440 | /* 39441 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14441 | /* 39444 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14442 | /* 39450 */ GIR_RootConstrainSelectedInstOperands, |
| 14443 | /* 39451 */ // GIR_Coverage, 1596, |
| 14444 | /* 39451 */ GIR_EraseRootFromParent_Done, |
| 14445 | /* 39452 */ // Label 900: @39452 |
| 14446 | /* 39452 */ GIM_Try, /*On fail goto*//*Label 901*/ GIMT_Encode4(39497), // Rule ID 1597 // |
| 14447 | /* 39457 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 14448 | /* 39460 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqmovnsu), |
| 14449 | /* 39465 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 14450 | /* 39468 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 14451 | /* 39471 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14452 | /* 39475 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14453 | /* 39479 */ // (intrinsic_wo_chain:{ *:[v2i32] } 3815:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm) => (VQMOVNsuv2i32:{ *:[v2i32] } QPR:{ *:[v2i64] }:$Vm) |
| 14454 | /* 39479 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQMOVNsuv2i32), |
| 14455 | /* 39482 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14456 | /* 39484 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14457 | /* 39486 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14458 | /* 39489 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14459 | /* 39495 */ GIR_RootConstrainSelectedInstOperands, |
| 14460 | /* 39496 */ // GIR_Coverage, 1597, |
| 14461 | /* 39496 */ GIR_EraseRootFromParent_Done, |
| 14462 | /* 39497 */ // Label 901: @39497 |
| 14463 | /* 39497 */ GIM_Try, /*On fail goto*//*Label 902*/ GIMT_Encode4(39533), // Rule ID 1620 // |
| 14464 | /* 39502 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8), |
| 14465 | /* 39505 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtas), |
| 14466 | /* 39510 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 14467 | /* 39513 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 14468 | /* 39516 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14469 | /* 39520 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14470 | /* 39524 */ // (intrinsic_wo_chain:{ *:[v2i32] } 3759:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VCVTANSDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm) |
| 14471 | /* 39524 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTANSDf), |
| 14472 | /* 39527 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14473 | /* 39529 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14474 | /* 39531 */ GIR_RootConstrainSelectedInstOperands, |
| 14475 | /* 39532 */ // GIR_Coverage, 1620, |
| 14476 | /* 39532 */ GIR_EraseRootFromParent_Done, |
| 14477 | /* 39533 */ // Label 902: @39533 |
| 14478 | /* 39533 */ GIM_Try, /*On fail goto*//*Label 903*/ GIMT_Encode4(39569), // Rule ID 1621 // |
| 14479 | /* 39538 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8), |
| 14480 | /* 39541 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtas), |
| 14481 | /* 39546 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 14482 | /* 39549 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 14483 | /* 39552 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14484 | /* 39556 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14485 | /* 39560 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3759:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VCVTANSQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm) |
| 14486 | /* 39560 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTANSQf), |
| 14487 | /* 39563 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14488 | /* 39565 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14489 | /* 39567 */ GIR_RootConstrainSelectedInstOperands, |
| 14490 | /* 39568 */ // GIR_Coverage, 1621, |
| 14491 | /* 39568 */ GIR_EraseRootFromParent_Done, |
| 14492 | /* 39569 */ // Label 903: @39569 |
| 14493 | /* 39569 */ GIM_Try, /*On fail goto*//*Label 904*/ GIMT_Encode4(39605), // Rule ID 1622 // |
| 14494 | /* 39574 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8), |
| 14495 | /* 39577 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtau), |
| 14496 | /* 39582 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 14497 | /* 39585 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 14498 | /* 39588 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14499 | /* 39592 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14500 | /* 39596 */ // (intrinsic_wo_chain:{ *:[v2i32] } 3760:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VCVTANUDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm) |
| 14501 | /* 39596 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTANUDf), |
| 14502 | /* 39599 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14503 | /* 39601 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14504 | /* 39603 */ GIR_RootConstrainSelectedInstOperands, |
| 14505 | /* 39604 */ // GIR_Coverage, 1622, |
| 14506 | /* 39604 */ GIR_EraseRootFromParent_Done, |
| 14507 | /* 39605 */ // Label 904: @39605 |
| 14508 | /* 39605 */ GIM_Try, /*On fail goto*//*Label 905*/ GIMT_Encode4(39641), // Rule ID 1623 // |
| 14509 | /* 39610 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8), |
| 14510 | /* 39613 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtau), |
| 14511 | /* 39618 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 14512 | /* 39621 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 14513 | /* 39624 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14514 | /* 39628 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14515 | /* 39632 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3760:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VCVTANUQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm) |
| 14516 | /* 39632 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTANUQf), |
| 14517 | /* 39635 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14518 | /* 39637 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14519 | /* 39639 */ GIR_RootConstrainSelectedInstOperands, |
| 14520 | /* 39640 */ // GIR_Coverage, 1623, |
| 14521 | /* 39640 */ GIR_EraseRootFromParent_Done, |
| 14522 | /* 39641 */ // Label 905: @39641 |
| 14523 | /* 39641 */ GIM_Try, /*On fail goto*//*Label 906*/ GIMT_Encode4(39677), // Rule ID 1624 // |
| 14524 | /* 39646 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), |
| 14525 | /* 39649 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtas), |
| 14526 | /* 39654 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 14527 | /* 39657 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 14528 | /* 39660 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14529 | /* 39664 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14530 | /* 39668 */ // (intrinsic_wo_chain:{ *:[v4i16] } 3759:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VCVTANSDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm) |
| 14531 | /* 39668 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTANSDh), |
| 14532 | /* 39671 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14533 | /* 39673 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14534 | /* 39675 */ GIR_RootConstrainSelectedInstOperands, |
| 14535 | /* 39676 */ // GIR_Coverage, 1624, |
| 14536 | /* 39676 */ GIR_EraseRootFromParent_Done, |
| 14537 | /* 39677 */ // Label 906: @39677 |
| 14538 | /* 39677 */ GIM_Try, /*On fail goto*//*Label 907*/ GIMT_Encode4(39713), // Rule ID 1625 // |
| 14539 | /* 39682 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), |
| 14540 | /* 39685 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtas), |
| 14541 | /* 39690 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 14542 | /* 39693 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 14543 | /* 39696 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14544 | /* 39700 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14545 | /* 39704 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3759:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VCVTANSQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm) |
| 14546 | /* 39704 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTANSQh), |
| 14547 | /* 39707 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14548 | /* 39709 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14549 | /* 39711 */ GIR_RootConstrainSelectedInstOperands, |
| 14550 | /* 39712 */ // GIR_Coverage, 1625, |
| 14551 | /* 39712 */ GIR_EraseRootFromParent_Done, |
| 14552 | /* 39713 */ // Label 907: @39713 |
| 14553 | /* 39713 */ GIM_Try, /*On fail goto*//*Label 908*/ GIMT_Encode4(39749), // Rule ID 1626 // |
| 14554 | /* 39718 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), |
| 14555 | /* 39721 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtau), |
| 14556 | /* 39726 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 14557 | /* 39729 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 14558 | /* 39732 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14559 | /* 39736 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14560 | /* 39740 */ // (intrinsic_wo_chain:{ *:[v4i16] } 3760:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VCVTANUDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm) |
| 14561 | /* 39740 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTANUDh), |
| 14562 | /* 39743 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14563 | /* 39745 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14564 | /* 39747 */ GIR_RootConstrainSelectedInstOperands, |
| 14565 | /* 39748 */ // GIR_Coverage, 1626, |
| 14566 | /* 39748 */ GIR_EraseRootFromParent_Done, |
| 14567 | /* 39749 */ // Label 908: @39749 |
| 14568 | /* 39749 */ GIM_Try, /*On fail goto*//*Label 909*/ GIMT_Encode4(39785), // Rule ID 1627 // |
| 14569 | /* 39754 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), |
| 14570 | /* 39757 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtau), |
| 14571 | /* 39762 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 14572 | /* 39765 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 14573 | /* 39768 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14574 | /* 39772 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14575 | /* 39776 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3760:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VCVTANUQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm) |
| 14576 | /* 39776 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTANUQh), |
| 14577 | /* 39779 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14578 | /* 39781 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14579 | /* 39783 */ GIR_RootConstrainSelectedInstOperands, |
| 14580 | /* 39784 */ // GIR_Coverage, 1627, |
| 14581 | /* 39784 */ GIR_EraseRootFromParent_Done, |
| 14582 | /* 39785 */ // Label 909: @39785 |
| 14583 | /* 39785 */ GIM_Try, /*On fail goto*//*Label 910*/ GIMT_Encode4(39821), // Rule ID 1628 // |
| 14584 | /* 39790 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8), |
| 14585 | /* 39793 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtns), |
| 14586 | /* 39798 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 14587 | /* 39801 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 14588 | /* 39804 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14589 | /* 39808 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14590 | /* 39812 */ // (intrinsic_wo_chain:{ *:[v2i32] } 3771:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VCVTNNSDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm) |
| 14591 | /* 39812 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTNNSDf), |
| 14592 | /* 39815 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14593 | /* 39817 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14594 | /* 39819 */ GIR_RootConstrainSelectedInstOperands, |
| 14595 | /* 39820 */ // GIR_Coverage, 1628, |
| 14596 | /* 39820 */ GIR_EraseRootFromParent_Done, |
| 14597 | /* 39821 */ // Label 910: @39821 |
| 14598 | /* 39821 */ GIM_Try, /*On fail goto*//*Label 911*/ GIMT_Encode4(39857), // Rule ID 1629 // |
| 14599 | /* 39826 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8), |
| 14600 | /* 39829 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtns), |
| 14601 | /* 39834 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 14602 | /* 39837 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 14603 | /* 39840 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14604 | /* 39844 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14605 | /* 39848 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3771:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VCVTNNSQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm) |
| 14606 | /* 39848 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTNNSQf), |
| 14607 | /* 39851 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14608 | /* 39853 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14609 | /* 39855 */ GIR_RootConstrainSelectedInstOperands, |
| 14610 | /* 39856 */ // GIR_Coverage, 1629, |
| 14611 | /* 39856 */ GIR_EraseRootFromParent_Done, |
| 14612 | /* 39857 */ // Label 911: @39857 |
| 14613 | /* 39857 */ GIM_Try, /*On fail goto*//*Label 912*/ GIMT_Encode4(39893), // Rule ID 1630 // |
| 14614 | /* 39862 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8), |
| 14615 | /* 39865 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtnu), |
| 14616 | /* 39870 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 14617 | /* 39873 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 14618 | /* 39876 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14619 | /* 39880 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14620 | /* 39884 */ // (intrinsic_wo_chain:{ *:[v2i32] } 3772:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VCVTNNUDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm) |
| 14621 | /* 39884 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTNNUDf), |
| 14622 | /* 39887 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14623 | /* 39889 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14624 | /* 39891 */ GIR_RootConstrainSelectedInstOperands, |
| 14625 | /* 39892 */ // GIR_Coverage, 1630, |
| 14626 | /* 39892 */ GIR_EraseRootFromParent_Done, |
| 14627 | /* 39893 */ // Label 912: @39893 |
| 14628 | /* 39893 */ GIM_Try, /*On fail goto*//*Label 913*/ GIMT_Encode4(39929), // Rule ID 1631 // |
| 14629 | /* 39898 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8), |
| 14630 | /* 39901 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtnu), |
| 14631 | /* 39906 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 14632 | /* 39909 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 14633 | /* 39912 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14634 | /* 39916 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14635 | /* 39920 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3772:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VCVTNNUQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm) |
| 14636 | /* 39920 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTNNUQf), |
| 14637 | /* 39923 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14638 | /* 39925 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14639 | /* 39927 */ GIR_RootConstrainSelectedInstOperands, |
| 14640 | /* 39928 */ // GIR_Coverage, 1631, |
| 14641 | /* 39928 */ GIR_EraseRootFromParent_Done, |
| 14642 | /* 39929 */ // Label 913: @39929 |
| 14643 | /* 39929 */ GIM_Try, /*On fail goto*//*Label 914*/ GIMT_Encode4(39965), // Rule ID 1632 // |
| 14644 | /* 39934 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), |
| 14645 | /* 39937 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtns), |
| 14646 | /* 39942 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 14647 | /* 39945 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 14648 | /* 39948 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14649 | /* 39952 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14650 | /* 39956 */ // (intrinsic_wo_chain:{ *:[v4i16] } 3771:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VCVTNNSDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm) |
| 14651 | /* 39956 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTNNSDh), |
| 14652 | /* 39959 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14653 | /* 39961 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14654 | /* 39963 */ GIR_RootConstrainSelectedInstOperands, |
| 14655 | /* 39964 */ // GIR_Coverage, 1632, |
| 14656 | /* 39964 */ GIR_EraseRootFromParent_Done, |
| 14657 | /* 39965 */ // Label 914: @39965 |
| 14658 | /* 39965 */ GIM_Try, /*On fail goto*//*Label 915*/ GIMT_Encode4(40001), // Rule ID 1633 // |
| 14659 | /* 39970 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), |
| 14660 | /* 39973 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtns), |
| 14661 | /* 39978 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 14662 | /* 39981 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 14663 | /* 39984 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14664 | /* 39988 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14665 | /* 39992 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3771:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VCVTNNSQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm) |
| 14666 | /* 39992 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTNNSQh), |
| 14667 | /* 39995 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14668 | /* 39997 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14669 | /* 39999 */ GIR_RootConstrainSelectedInstOperands, |
| 14670 | /* 40000 */ // GIR_Coverage, 1633, |
| 14671 | /* 40000 */ GIR_EraseRootFromParent_Done, |
| 14672 | /* 40001 */ // Label 915: @40001 |
| 14673 | /* 40001 */ GIM_Try, /*On fail goto*//*Label 916*/ GIMT_Encode4(40037), // Rule ID 1634 // |
| 14674 | /* 40006 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), |
| 14675 | /* 40009 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtnu), |
| 14676 | /* 40014 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 14677 | /* 40017 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 14678 | /* 40020 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14679 | /* 40024 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14680 | /* 40028 */ // (intrinsic_wo_chain:{ *:[v4i16] } 3772:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VCVTNNUDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm) |
| 14681 | /* 40028 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTNNUDh), |
| 14682 | /* 40031 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14683 | /* 40033 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14684 | /* 40035 */ GIR_RootConstrainSelectedInstOperands, |
| 14685 | /* 40036 */ // GIR_Coverage, 1634, |
| 14686 | /* 40036 */ GIR_EraseRootFromParent_Done, |
| 14687 | /* 40037 */ // Label 916: @40037 |
| 14688 | /* 40037 */ GIM_Try, /*On fail goto*//*Label 917*/ GIMT_Encode4(40073), // Rule ID 1635 // |
| 14689 | /* 40042 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), |
| 14690 | /* 40045 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtnu), |
| 14691 | /* 40050 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 14692 | /* 40053 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 14693 | /* 40056 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14694 | /* 40060 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14695 | /* 40064 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3772:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VCVTNNUQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm) |
| 14696 | /* 40064 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTNNUQh), |
| 14697 | /* 40067 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14698 | /* 40069 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14699 | /* 40071 */ GIR_RootConstrainSelectedInstOperands, |
| 14700 | /* 40072 */ // GIR_Coverage, 1635, |
| 14701 | /* 40072 */ GIR_EraseRootFromParent_Done, |
| 14702 | /* 40073 */ // Label 917: @40073 |
| 14703 | /* 40073 */ GIM_Try, /*On fail goto*//*Label 918*/ GIMT_Encode4(40109), // Rule ID 1636 // |
| 14704 | /* 40078 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8), |
| 14705 | /* 40081 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtps), |
| 14706 | /* 40086 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 14707 | /* 40089 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 14708 | /* 40092 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14709 | /* 40096 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14710 | /* 40100 */ // (intrinsic_wo_chain:{ *:[v2i32] } 3773:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VCVTPNSDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm) |
| 14711 | /* 40100 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTPNSDf), |
| 14712 | /* 40103 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14713 | /* 40105 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14714 | /* 40107 */ GIR_RootConstrainSelectedInstOperands, |
| 14715 | /* 40108 */ // GIR_Coverage, 1636, |
| 14716 | /* 40108 */ GIR_EraseRootFromParent_Done, |
| 14717 | /* 40109 */ // Label 918: @40109 |
| 14718 | /* 40109 */ GIM_Try, /*On fail goto*//*Label 919*/ GIMT_Encode4(40145), // Rule ID 1637 // |
| 14719 | /* 40114 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8), |
| 14720 | /* 40117 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtps), |
| 14721 | /* 40122 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 14722 | /* 40125 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 14723 | /* 40128 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14724 | /* 40132 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14725 | /* 40136 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3773:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VCVTPNSQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm) |
| 14726 | /* 40136 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTPNSQf), |
| 14727 | /* 40139 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14728 | /* 40141 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14729 | /* 40143 */ GIR_RootConstrainSelectedInstOperands, |
| 14730 | /* 40144 */ // GIR_Coverage, 1637, |
| 14731 | /* 40144 */ GIR_EraseRootFromParent_Done, |
| 14732 | /* 40145 */ // Label 919: @40145 |
| 14733 | /* 40145 */ GIM_Try, /*On fail goto*//*Label 920*/ GIMT_Encode4(40181), // Rule ID 1638 // |
| 14734 | /* 40150 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8), |
| 14735 | /* 40153 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtpu), |
| 14736 | /* 40158 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 14737 | /* 40161 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 14738 | /* 40164 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14739 | /* 40168 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14740 | /* 40172 */ // (intrinsic_wo_chain:{ *:[v2i32] } 3774:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VCVTPNUDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm) |
| 14741 | /* 40172 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTPNUDf), |
| 14742 | /* 40175 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14743 | /* 40177 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14744 | /* 40179 */ GIR_RootConstrainSelectedInstOperands, |
| 14745 | /* 40180 */ // GIR_Coverage, 1638, |
| 14746 | /* 40180 */ GIR_EraseRootFromParent_Done, |
| 14747 | /* 40181 */ // Label 920: @40181 |
| 14748 | /* 40181 */ GIM_Try, /*On fail goto*//*Label 921*/ GIMT_Encode4(40217), // Rule ID 1639 // |
| 14749 | /* 40186 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8), |
| 14750 | /* 40189 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtpu), |
| 14751 | /* 40194 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 14752 | /* 40197 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 14753 | /* 40200 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14754 | /* 40204 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14755 | /* 40208 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3774:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VCVTPNUQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm) |
| 14756 | /* 40208 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTPNUQf), |
| 14757 | /* 40211 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14758 | /* 40213 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14759 | /* 40215 */ GIR_RootConstrainSelectedInstOperands, |
| 14760 | /* 40216 */ // GIR_Coverage, 1639, |
| 14761 | /* 40216 */ GIR_EraseRootFromParent_Done, |
| 14762 | /* 40217 */ // Label 921: @40217 |
| 14763 | /* 40217 */ GIM_Try, /*On fail goto*//*Label 922*/ GIMT_Encode4(40253), // Rule ID 1640 // |
| 14764 | /* 40222 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), |
| 14765 | /* 40225 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtps), |
| 14766 | /* 40230 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 14767 | /* 40233 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 14768 | /* 40236 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14769 | /* 40240 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14770 | /* 40244 */ // (intrinsic_wo_chain:{ *:[v4i16] } 3773:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VCVTPNSDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm) |
| 14771 | /* 40244 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTPNSDh), |
| 14772 | /* 40247 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14773 | /* 40249 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14774 | /* 40251 */ GIR_RootConstrainSelectedInstOperands, |
| 14775 | /* 40252 */ // GIR_Coverage, 1640, |
| 14776 | /* 40252 */ GIR_EraseRootFromParent_Done, |
| 14777 | /* 40253 */ // Label 922: @40253 |
| 14778 | /* 40253 */ GIM_Try, /*On fail goto*//*Label 923*/ GIMT_Encode4(40289), // Rule ID 1641 // |
| 14779 | /* 40258 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), |
| 14780 | /* 40261 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtps), |
| 14781 | /* 40266 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 14782 | /* 40269 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 14783 | /* 40272 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14784 | /* 40276 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14785 | /* 40280 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3773:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VCVTPNSQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm) |
| 14786 | /* 40280 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTPNSQh), |
| 14787 | /* 40283 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14788 | /* 40285 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14789 | /* 40287 */ GIR_RootConstrainSelectedInstOperands, |
| 14790 | /* 40288 */ // GIR_Coverage, 1641, |
| 14791 | /* 40288 */ GIR_EraseRootFromParent_Done, |
| 14792 | /* 40289 */ // Label 923: @40289 |
| 14793 | /* 40289 */ GIM_Try, /*On fail goto*//*Label 924*/ GIMT_Encode4(40325), // Rule ID 1642 // |
| 14794 | /* 40294 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), |
| 14795 | /* 40297 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtpu), |
| 14796 | /* 40302 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 14797 | /* 40305 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 14798 | /* 40308 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14799 | /* 40312 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14800 | /* 40316 */ // (intrinsic_wo_chain:{ *:[v4i16] } 3774:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VCVTPNUDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm) |
| 14801 | /* 40316 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTPNUDh), |
| 14802 | /* 40319 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14803 | /* 40321 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14804 | /* 40323 */ GIR_RootConstrainSelectedInstOperands, |
| 14805 | /* 40324 */ // GIR_Coverage, 1642, |
| 14806 | /* 40324 */ GIR_EraseRootFromParent_Done, |
| 14807 | /* 40325 */ // Label 924: @40325 |
| 14808 | /* 40325 */ GIM_Try, /*On fail goto*//*Label 925*/ GIMT_Encode4(40361), // Rule ID 1643 // |
| 14809 | /* 40330 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), |
| 14810 | /* 40333 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtpu), |
| 14811 | /* 40338 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 14812 | /* 40341 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 14813 | /* 40344 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14814 | /* 40348 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14815 | /* 40352 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3774:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VCVTPNUQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm) |
| 14816 | /* 40352 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTPNUQh), |
| 14817 | /* 40355 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14818 | /* 40357 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14819 | /* 40359 */ GIR_RootConstrainSelectedInstOperands, |
| 14820 | /* 40360 */ // GIR_Coverage, 1643, |
| 14821 | /* 40360 */ GIR_EraseRootFromParent_Done, |
| 14822 | /* 40361 */ // Label 925: @40361 |
| 14823 | /* 40361 */ GIM_Try, /*On fail goto*//*Label 926*/ GIMT_Encode4(40397), // Rule ID 1644 // |
| 14824 | /* 40366 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8), |
| 14825 | /* 40369 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtms), |
| 14826 | /* 40374 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 14827 | /* 40377 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 14828 | /* 40380 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14829 | /* 40384 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14830 | /* 40388 */ // (intrinsic_wo_chain:{ *:[v2i32] } 3769:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VCVTMNSDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm) |
| 14831 | /* 40388 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTMNSDf), |
| 14832 | /* 40391 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14833 | /* 40393 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14834 | /* 40395 */ GIR_RootConstrainSelectedInstOperands, |
| 14835 | /* 40396 */ // GIR_Coverage, 1644, |
| 14836 | /* 40396 */ GIR_EraseRootFromParent_Done, |
| 14837 | /* 40397 */ // Label 926: @40397 |
| 14838 | /* 40397 */ GIM_Try, /*On fail goto*//*Label 927*/ GIMT_Encode4(40433), // Rule ID 1645 // |
| 14839 | /* 40402 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8), |
| 14840 | /* 40405 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtms), |
| 14841 | /* 40410 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 14842 | /* 40413 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 14843 | /* 40416 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14844 | /* 40420 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14845 | /* 40424 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3769:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VCVTMNSQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm) |
| 14846 | /* 40424 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTMNSQf), |
| 14847 | /* 40427 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14848 | /* 40429 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14849 | /* 40431 */ GIR_RootConstrainSelectedInstOperands, |
| 14850 | /* 40432 */ // GIR_Coverage, 1645, |
| 14851 | /* 40432 */ GIR_EraseRootFromParent_Done, |
| 14852 | /* 40433 */ // Label 927: @40433 |
| 14853 | /* 40433 */ GIM_Try, /*On fail goto*//*Label 928*/ GIMT_Encode4(40469), // Rule ID 1646 // |
| 14854 | /* 40438 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8), |
| 14855 | /* 40441 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtmu), |
| 14856 | /* 40446 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 14857 | /* 40449 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 14858 | /* 40452 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14859 | /* 40456 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14860 | /* 40460 */ // (intrinsic_wo_chain:{ *:[v2i32] } 3770:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VCVTMNUDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm) |
| 14861 | /* 40460 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTMNUDf), |
| 14862 | /* 40463 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14863 | /* 40465 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14864 | /* 40467 */ GIR_RootConstrainSelectedInstOperands, |
| 14865 | /* 40468 */ // GIR_Coverage, 1646, |
| 14866 | /* 40468 */ GIR_EraseRootFromParent_Done, |
| 14867 | /* 40469 */ // Label 928: @40469 |
| 14868 | /* 40469 */ GIM_Try, /*On fail goto*//*Label 929*/ GIMT_Encode4(40505), // Rule ID 1647 // |
| 14869 | /* 40474 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8), |
| 14870 | /* 40477 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtmu), |
| 14871 | /* 40482 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 14872 | /* 40485 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 14873 | /* 40488 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14874 | /* 40492 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14875 | /* 40496 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3770:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VCVTMNUQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm) |
| 14876 | /* 40496 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTMNUQf), |
| 14877 | /* 40499 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14878 | /* 40501 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14879 | /* 40503 */ GIR_RootConstrainSelectedInstOperands, |
| 14880 | /* 40504 */ // GIR_Coverage, 1647, |
| 14881 | /* 40504 */ GIR_EraseRootFromParent_Done, |
| 14882 | /* 40505 */ // Label 929: @40505 |
| 14883 | /* 40505 */ GIM_Try, /*On fail goto*//*Label 930*/ GIMT_Encode4(40541), // Rule ID 1648 // |
| 14884 | /* 40510 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), |
| 14885 | /* 40513 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtms), |
| 14886 | /* 40518 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 14887 | /* 40521 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 14888 | /* 40524 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14889 | /* 40528 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14890 | /* 40532 */ // (intrinsic_wo_chain:{ *:[v4i16] } 3769:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VCVTMNSDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm) |
| 14891 | /* 40532 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTMNSDh), |
| 14892 | /* 40535 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14893 | /* 40537 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14894 | /* 40539 */ GIR_RootConstrainSelectedInstOperands, |
| 14895 | /* 40540 */ // GIR_Coverage, 1648, |
| 14896 | /* 40540 */ GIR_EraseRootFromParent_Done, |
| 14897 | /* 40541 */ // Label 930: @40541 |
| 14898 | /* 40541 */ GIM_Try, /*On fail goto*//*Label 931*/ GIMT_Encode4(40577), // Rule ID 1649 // |
| 14899 | /* 40546 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), |
| 14900 | /* 40549 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtms), |
| 14901 | /* 40554 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 14902 | /* 40557 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 14903 | /* 40560 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14904 | /* 40564 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14905 | /* 40568 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3769:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VCVTMNSQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm) |
| 14906 | /* 40568 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTMNSQh), |
| 14907 | /* 40571 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14908 | /* 40573 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14909 | /* 40575 */ GIR_RootConstrainSelectedInstOperands, |
| 14910 | /* 40576 */ // GIR_Coverage, 1649, |
| 14911 | /* 40576 */ GIR_EraseRootFromParent_Done, |
| 14912 | /* 40577 */ // Label 931: @40577 |
| 14913 | /* 40577 */ GIM_Try, /*On fail goto*//*Label 932*/ GIMT_Encode4(40613), // Rule ID 1650 // |
| 14914 | /* 40582 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), |
| 14915 | /* 40585 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtmu), |
| 14916 | /* 40590 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 14917 | /* 40593 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 14918 | /* 40596 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14919 | /* 40600 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14920 | /* 40604 */ // (intrinsic_wo_chain:{ *:[v4i16] } 3770:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VCVTMNUDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm) |
| 14921 | /* 40604 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTMNUDh), |
| 14922 | /* 40607 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14923 | /* 40609 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14924 | /* 40611 */ GIR_RootConstrainSelectedInstOperands, |
| 14925 | /* 40612 */ // GIR_Coverage, 1650, |
| 14926 | /* 40612 */ GIR_EraseRootFromParent_Done, |
| 14927 | /* 40613 */ // Label 932: @40613 |
| 14928 | /* 40613 */ GIM_Try, /*On fail goto*//*Label 933*/ GIMT_Encode4(40649), // Rule ID 1651 // |
| 14929 | /* 40618 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), |
| 14930 | /* 40621 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtmu), |
| 14931 | /* 40626 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 14932 | /* 40629 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 14933 | /* 40632 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14934 | /* 40636 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14935 | /* 40640 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3770:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VCVTMNUQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm) |
| 14936 | /* 40640 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTMNUQh), |
| 14937 | /* 40643 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14938 | /* 40645 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14939 | /* 40647 */ GIR_RootConstrainSelectedInstOperands, |
| 14940 | /* 40648 */ // GIR_Coverage, 1651, |
| 14941 | /* 40648 */ GIR_EraseRootFromParent_Done, |
| 14942 | /* 40649 */ // Label 933: @40649 |
| 14943 | /* 40649 */ GIM_Try, /*On fail goto*//*Label 934*/ GIMT_Encode4(40694), // Rule ID 1668 // |
| 14944 | /* 40654 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP16_HasNEON), |
| 14945 | /* 40657 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfp2hf), |
| 14946 | /* 40662 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 14947 | /* 40665 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 14948 | /* 40668 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14949 | /* 40672 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14950 | /* 40676 */ // (intrinsic_wo_chain:{ *:[v4i16] } 3765:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VCVTf2h:{ *:[v4i16] } QPR:{ *:[v4f32] }:$Vm) |
| 14951 | /* 40676 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTf2h), |
| 14952 | /* 40679 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14953 | /* 40681 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14954 | /* 40683 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14955 | /* 40686 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14956 | /* 40692 */ GIR_RootConstrainSelectedInstOperands, |
| 14957 | /* 40693 */ // GIR_Coverage, 1668, |
| 14958 | /* 40693 */ GIR_EraseRootFromParent_Done, |
| 14959 | /* 40694 */ // Label 934: @40694 |
| 14960 | /* 40694 */ GIM_Try, /*On fail goto*//*Label 935*/ GIMT_Encode4(40739), // Rule ID 1669 // |
| 14961 | /* 40699 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP16_HasNEON), |
| 14962 | /* 40702 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvthf2fp), |
| 14963 | /* 40707 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 14964 | /* 40710 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 14965 | /* 40713 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14966 | /* 40717 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14967 | /* 40721 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3768:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm) => (VCVTh2f:{ *:[v4f32] } DPR:{ *:[v4i16] }:$Vm) |
| 14968 | /* 40721 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTh2f), |
| 14969 | /* 40724 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14970 | /* 40726 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14971 | /* 40728 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14972 | /* 40731 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14973 | /* 40737 */ GIR_RootConstrainSelectedInstOperands, |
| 14974 | /* 40738 */ // GIR_Coverage, 1669, |
| 14975 | /* 40738 */ GIR_EraseRootFromParent_Done, |
| 14976 | /* 40739 */ // Label 935: @40739 |
| 14977 | /* 40739 */ GIM_Try, /*On fail goto*//*Label 936*/ GIMT_Encode4(40775), // Rule ID 1691 // |
| 14978 | /* 40744 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8), |
| 14979 | /* 40747 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrintn), |
| 14980 | /* 40752 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 14981 | /* 40755 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 14982 | /* 40758 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14983 | /* 40762 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14984 | /* 40766 */ // (intrinsic_wo_chain:{ *:[v2f32] } 3837:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VRINTNNDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) |
| 14985 | /* 40766 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTNNDf), |
| 14986 | /* 40769 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14987 | /* 40771 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14988 | /* 40773 */ GIR_RootConstrainSelectedInstOperands, |
| 14989 | /* 40774 */ // GIR_Coverage, 1691, |
| 14990 | /* 40774 */ GIR_EraseRootFromParent_Done, |
| 14991 | /* 40775 */ // Label 936: @40775 |
| 14992 | /* 40775 */ GIM_Try, /*On fail goto*//*Label 937*/ GIMT_Encode4(40811), // Rule ID 1692 // |
| 14993 | /* 40780 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8), |
| 14994 | /* 40783 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrintn), |
| 14995 | /* 40788 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 14996 | /* 40791 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 14997 | /* 40794 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14998 | /* 40798 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14999 | /* 40802 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3837:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VRINTNNQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) |
| 15000 | /* 40802 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTNNQf), |
| 15001 | /* 40805 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15002 | /* 40807 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15003 | /* 40809 */ GIR_RootConstrainSelectedInstOperands, |
| 15004 | /* 40810 */ // GIR_Coverage, 1692, |
| 15005 | /* 40810 */ GIR_EraseRootFromParent_Done, |
| 15006 | /* 40811 */ // Label 937: @40811 |
| 15007 | /* 40811 */ GIM_Try, /*On fail goto*//*Label 938*/ GIMT_Encode4(40847), // Rule ID 1693 // |
| 15008 | /* 40816 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), |
| 15009 | /* 40819 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrintn), |
| 15010 | /* 40824 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 15011 | /* 40827 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 15012 | /* 40830 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15013 | /* 40834 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15014 | /* 40838 */ // (intrinsic_wo_chain:{ *:[v4f16] } 3837:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VRINTNNDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) |
| 15015 | /* 40838 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTNNDh), |
| 15016 | /* 40841 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15017 | /* 40843 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15018 | /* 40845 */ GIR_RootConstrainSelectedInstOperands, |
| 15019 | /* 40846 */ // GIR_Coverage, 1693, |
| 15020 | /* 40846 */ GIR_EraseRootFromParent_Done, |
| 15021 | /* 40847 */ // Label 938: @40847 |
| 15022 | /* 40847 */ GIM_Try, /*On fail goto*//*Label 939*/ GIMT_Encode4(40883), // Rule ID 1694 // |
| 15023 | /* 40852 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), |
| 15024 | /* 40855 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrintn), |
| 15025 | /* 40860 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 15026 | /* 40863 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 15027 | /* 40866 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15028 | /* 40870 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15029 | /* 40874 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3837:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VRINTNNQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) |
| 15030 | /* 40874 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTNNQh), |
| 15031 | /* 40877 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15032 | /* 40879 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15033 | /* 40881 */ GIR_RootConstrainSelectedInstOperands, |
| 15034 | /* 40882 */ // GIR_Coverage, 1694, |
| 15035 | /* 40882 */ GIR_EraseRootFromParent_Done, |
| 15036 | /* 40883 */ // Label 939: @40883 |
| 15037 | /* 40883 */ GIM_Try, /*On fail goto*//*Label 940*/ GIMT_Encode4(40919), // Rule ID 1717 // |
| 15038 | /* 40888 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAES_HasV8), |
| 15039 | /* 40891 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_aesimc), |
| 15040 | /* 40896 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 15041 | /* 40899 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 15042 | /* 40902 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15043 | /* 40906 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15044 | /* 40910 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3728:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm) => (AESIMC:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm) |
| 15045 | /* 40910 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::AESIMC), |
| 15046 | /* 40913 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15047 | /* 40915 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15048 | /* 40917 */ GIR_RootConstrainSelectedInstOperands, |
| 15049 | /* 40918 */ // GIR_Coverage, 1717, |
| 15050 | /* 40918 */ GIR_EraseRootFromParent_Done, |
| 15051 | /* 40919 */ // Label 940: @40919 |
| 15052 | /* 40919 */ GIM_Try, /*On fail goto*//*Label 941*/ GIMT_Encode4(40955), // Rule ID 1718 // |
| 15053 | /* 40924 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAES_HasV8), |
| 15054 | /* 40927 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_aesmc), |
| 15055 | /* 40932 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 15056 | /* 40935 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 15057 | /* 40938 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15058 | /* 40942 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15059 | /* 40946 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3729:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm) => (AESMC:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm) |
| 15060 | /* 40946 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::AESMC), |
| 15061 | /* 40949 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15062 | /* 40951 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15063 | /* 40953 */ GIR_RootConstrainSelectedInstOperands, |
| 15064 | /* 40954 */ // GIR_Coverage, 1718, |
| 15065 | /* 40954 */ GIR_EraseRootFromParent_Done, |
| 15066 | /* 40955 */ // Label 941: @40955 |
| 15067 | /* 40955 */ GIM_Try, /*On fail goto*//*Label 942*/ GIMT_Encode4(41003), // Rule ID 1851 // |
| 15068 | /* 40960 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 15069 | /* 40963 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sxtb16), |
| 15070 | /* 40968 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 15071 | /* 40971 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 15072 | /* 40974 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 15073 | /* 40978 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 15074 | /* 40982 */ // (intrinsic_wo_chain:{ *:[i32] } 3923:{ *:[iPTR] }, GPR:{ *:[i32] }:$Src) => (SXTB16:{ *:[i32] } GPR:{ *:[i32] }:$Src, 0:{ *:[i32] }) |
| 15075 | /* 40982 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SXTB16), |
| 15076 | /* 40985 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 15077 | /* 40987 */ GIR_RootToRootCopy, /*OpIdx*/2, // Src |
| 15078 | /* 40989 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15079 | /* 40992 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 15080 | /* 40995 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15081 | /* 41001 */ GIR_RootConstrainSelectedInstOperands, |
| 15082 | /* 41002 */ // GIR_Coverage, 1851, |
| 15083 | /* 41002 */ GIR_EraseRootFromParent_Done, |
| 15084 | /* 41003 */ // Label 942: @41003 |
| 15085 | /* 41003 */ GIM_Try, /*On fail goto*//*Label 943*/ GIMT_Encode4(41051), // Rule ID 2099 // |
| 15086 | /* 41008 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 15087 | /* 41011 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sxtb16), |
| 15088 | /* 41016 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 15089 | /* 41019 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 15090 | /* 41022 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 15091 | /* 41026 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 15092 | /* 41030 */ // (intrinsic_wo_chain:{ *:[i32] } 3923:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn) => (t2SXTB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 0:{ *:[i32] }) |
| 15093 | /* 41030 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SXTB16), |
| 15094 | /* 41033 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 15095 | /* 41035 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 15096 | /* 41037 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15097 | /* 41040 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 15098 | /* 41043 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15099 | /* 41049 */ GIR_RootConstrainSelectedInstOperands, |
| 15100 | /* 41050 */ // GIR_Coverage, 2099, |
| 15101 | /* 41050 */ GIR_EraseRootFromParent_Done, |
| 15102 | /* 41051 */ // Label 943: @41051 |
| 15103 | /* 41051 */ GIM_Try, /*On fail goto*//*Label 944*/ GIMT_Encode4(41117), // Rule ID 3648 // |
| 15104 | /* 41056 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 15105 | /* 41059 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcls), |
| 15106 | /* 41064 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 15107 | /* 41067 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 15108 | /* 41070 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 15109 | /* 41074 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 15110 | /* 41078 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3611:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$val) => (MVE_VCLSs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$val) |
| 15111 | /* 41078 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 15112 | /* 41081 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 15113 | /* 41085 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 15114 | /* 41090 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCLSs8), |
| 15115 | /* 41093 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 15116 | /* 41095 */ GIR_RootToRootCopy, /*OpIdx*/2, // val |
| 15117 | /* 41097 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15118 | /* 41100 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15119 | /* 41106 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15120 | /* 41112 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 15121 | /* 41115 */ GIR_RootConstrainSelectedInstOperands, |
| 15122 | /* 41116 */ // GIR_Coverage, 3648, |
| 15123 | /* 41116 */ GIR_EraseRootFromParent_Done, |
| 15124 | /* 41117 */ // Label 944: @41117 |
| 15125 | /* 41117 */ GIM_Try, /*On fail goto*//*Label 945*/ GIMT_Encode4(41183), // Rule ID 3650 // |
| 15126 | /* 41122 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 15127 | /* 41125 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcls), |
| 15128 | /* 41130 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 15129 | /* 41133 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 15130 | /* 41136 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 15131 | /* 41140 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 15132 | /* 41144 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3611:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$val) => (MVE_VCLSs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$val) |
| 15133 | /* 41144 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 15134 | /* 41147 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 15135 | /* 41151 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 15136 | /* 41156 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCLSs16), |
| 15137 | /* 41159 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 15138 | /* 41161 */ GIR_RootToRootCopy, /*OpIdx*/2, // val |
| 15139 | /* 41163 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15140 | /* 41166 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15141 | /* 41172 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15142 | /* 41178 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 15143 | /* 41181 */ GIR_RootConstrainSelectedInstOperands, |
| 15144 | /* 41182 */ // GIR_Coverage, 3650, |
| 15145 | /* 41182 */ GIR_EraseRootFromParent_Done, |
| 15146 | /* 41183 */ // Label 945: @41183 |
| 15147 | /* 41183 */ GIM_Try, /*On fail goto*//*Label 946*/ GIMT_Encode4(41249), // Rule ID 3652 // |
| 15148 | /* 41188 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 15149 | /* 41191 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcls), |
| 15150 | /* 41196 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 15151 | /* 41199 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 15152 | /* 41202 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 15153 | /* 41206 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 15154 | /* 41210 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3611:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$val) => (MVE_VCLSs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$val) |
| 15155 | /* 41210 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 15156 | /* 41213 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 15157 | /* 41217 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 15158 | /* 41222 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCLSs32), |
| 15159 | /* 41225 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 15160 | /* 41227 */ GIR_RootToRootCopy, /*OpIdx*/2, // val |
| 15161 | /* 41229 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15162 | /* 41232 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15163 | /* 41238 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15164 | /* 41244 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 15165 | /* 41247 */ GIR_RootConstrainSelectedInstOperands, |
| 15166 | /* 41248 */ // GIR_Coverage, 3652, |
| 15167 | /* 41248 */ GIR_EraseRootFromParent_Done, |
| 15168 | /* 41249 */ // Label 946: @41249 |
| 15169 | /* 41249 */ GIM_Try, /*On fail goto*//*Label 947*/ GIMT_Encode4(41300), // Rule ID 4864 // |
| 15170 | /* 41254 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 15171 | /* 41257 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vctp8), |
| 15172 | /* 41262 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s1, |
| 15173 | /* 41265 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 15174 | /* 41268 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 15175 | /* 41272 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 15176 | /* 41276 */ // (intrinsic_wo_chain:{ *:[v16i1] } 3619:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn) => (MVE_VCTP8:{ *:[v16i1] } rGPR:{ *:[i32] }:$Rn) |
| 15177 | /* 41276 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCTP8), |
| 15178 | /* 41279 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0] |
| 15179 | /* 41281 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 15180 | /* 41283 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15181 | /* 41286 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15182 | /* 41292 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15183 | /* 41298 */ GIR_RootConstrainSelectedInstOperands, |
| 15184 | /* 41299 */ // GIR_Coverage, 4864, |
| 15185 | /* 41299 */ GIR_EraseRootFromParent_Done, |
| 15186 | /* 41300 */ // Label 947: @41300 |
| 15187 | /* 41300 */ GIM_Try, /*On fail goto*//*Label 948*/ GIMT_Encode4(41351), // Rule ID 4866 // |
| 15188 | /* 41305 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 15189 | /* 41308 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vctp16), |
| 15190 | /* 41313 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s1, |
| 15191 | /* 41316 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 15192 | /* 41319 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 15193 | /* 41323 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 15194 | /* 41327 */ // (intrinsic_wo_chain:{ *:[v8i1] } 3616:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn) => (MVE_VCTP16:{ *:[v8i1] } rGPR:{ *:[i32] }:$Rn) |
| 15195 | /* 41327 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCTP16), |
| 15196 | /* 41330 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0] |
| 15197 | /* 41332 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 15198 | /* 41334 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15199 | /* 41337 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15200 | /* 41343 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15201 | /* 41349 */ GIR_RootConstrainSelectedInstOperands, |
| 15202 | /* 41350 */ // GIR_Coverage, 4866, |
| 15203 | /* 41350 */ GIR_EraseRootFromParent_Done, |
| 15204 | /* 41351 */ // Label 948: @41351 |
| 15205 | /* 41351 */ GIM_Try, /*On fail goto*//*Label 949*/ GIMT_Encode4(41402), // Rule ID 4868 // |
| 15206 | /* 41356 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 15207 | /* 41359 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vctp32), |
| 15208 | /* 41364 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s1, |
| 15209 | /* 41367 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 15210 | /* 41370 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 15211 | /* 41374 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 15212 | /* 41378 */ // (intrinsic_wo_chain:{ *:[v4i1] } 3617:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn) => (MVE_VCTP32:{ *:[v4i1] } rGPR:{ *:[i32] }:$Rn) |
| 15213 | /* 41378 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCTP32), |
| 15214 | /* 41381 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0] |
| 15215 | /* 41383 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 15216 | /* 41385 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15217 | /* 41388 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15218 | /* 41394 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15219 | /* 41400 */ GIR_RootConstrainSelectedInstOperands, |
| 15220 | /* 41401 */ // GIR_Coverage, 4868, |
| 15221 | /* 41401 */ GIR_EraseRootFromParent_Done, |
| 15222 | /* 41402 */ // Label 949: @41402 |
| 15223 | /* 41402 */ GIM_Try, /*On fail goto*//*Label 950*/ GIMT_Encode4(41453), // Rule ID 4870 // |
| 15224 | /* 41407 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 15225 | /* 41410 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vctp64), |
| 15226 | /* 41415 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s1, |
| 15227 | /* 41418 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 15228 | /* 41421 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 15229 | /* 41425 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 15230 | /* 41429 */ // (intrinsic_wo_chain:{ *:[v2i1] } 3618:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn) => (MVE_VCTP64:{ *:[v2i1] } rGPR:{ *:[i32] }:$Rn) |
| 15231 | /* 41429 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCTP64), |
| 15232 | /* 41432 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0] |
| 15233 | /* 41434 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 15234 | /* 41436 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15235 | /* 41439 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15236 | /* 41445 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15237 | /* 41451 */ GIR_RootConstrainSelectedInstOperands, |
| 15238 | /* 41452 */ // GIR_Coverage, 4870, |
| 15239 | /* 41452 */ GIR_EraseRootFromParent_Done, |
| 15240 | /* 41453 */ // Label 950: @41453 |
| 15241 | /* 41453 */ GIM_Try, /*On fail goto*//*Label 951*/ GIMT_Encode4(41499), // Rule ID 600 // |
| 15242 | /* 41458 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has8MSecExt_IsThumb), |
| 15243 | /* 41461 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_cmse_tt), |
| 15244 | /* 41466 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 15245 | /* 41469 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 15246 | /* 41473 */ // MIs[0] Rn |
| 15247 | /* 41473 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 15248 | /* 41477 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 15249 | /* 41481 */ // (intrinsic_wo_chain:{ *:[i32] } 3501:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn) => (t2TT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn) |
| 15250 | /* 41481 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2TT), |
| 15251 | /* 41484 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt] |
| 15252 | /* 41486 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 15253 | /* 41488 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 15254 | /* 41491 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15255 | /* 41497 */ GIR_RootConstrainSelectedInstOperands, |
| 15256 | /* 41498 */ // GIR_Coverage, 600, |
| 15257 | /* 41498 */ GIR_EraseRootFromParent_Done, |
| 15258 | /* 41499 */ // Label 951: @41499 |
| 15259 | /* 41499 */ GIM_Try, /*On fail goto*//*Label 952*/ GIMT_Encode4(41545), // Rule ID 601 // |
| 15260 | /* 41504 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has8MSecExt_IsThumb), |
| 15261 | /* 41507 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_cmse_ttt), |
| 15262 | /* 41512 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 15263 | /* 41515 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 15264 | /* 41519 */ // MIs[0] Rn |
| 15265 | /* 41519 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 15266 | /* 41523 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 15267 | /* 41527 */ // (intrinsic_wo_chain:{ *:[i32] } 3504:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn) => (t2TTT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn) |
| 15268 | /* 41527 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2TTT), |
| 15269 | /* 41530 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt] |
| 15270 | /* 41532 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 15271 | /* 41534 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 15272 | /* 41537 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15273 | /* 41543 */ GIR_RootConstrainSelectedInstOperands, |
| 15274 | /* 41544 */ // GIR_Coverage, 601, |
| 15275 | /* 41544 */ GIR_EraseRootFromParent_Done, |
| 15276 | /* 41545 */ // Label 952: @41545 |
| 15277 | /* 41545 */ GIM_Try, /*On fail goto*//*Label 953*/ GIMT_Encode4(41591), // Rule ID 602 // |
| 15278 | /* 41550 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has8MSecExt_IsThumb), |
| 15279 | /* 41553 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_cmse_tta), |
| 15280 | /* 41558 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 15281 | /* 41561 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 15282 | /* 41565 */ // MIs[0] Rn |
| 15283 | /* 41565 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 15284 | /* 41569 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 15285 | /* 41573 */ // (intrinsic_wo_chain:{ *:[i32] } 3502:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn) => (t2TTA:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn) |
| 15286 | /* 41573 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2TTA), |
| 15287 | /* 41576 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt] |
| 15288 | /* 41578 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 15289 | /* 41580 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 15290 | /* 41583 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15291 | /* 41589 */ GIR_RootConstrainSelectedInstOperands, |
| 15292 | /* 41590 */ // GIR_Coverage, 602, |
| 15293 | /* 41590 */ GIR_EraseRootFromParent_Done, |
| 15294 | /* 41591 */ // Label 953: @41591 |
| 15295 | /* 41591 */ GIM_Try, /*On fail goto*//*Label 954*/ GIMT_Encode4(41637), // Rule ID 603 // |
| 15296 | /* 41596 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has8MSecExt_IsThumb), |
| 15297 | /* 41599 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_cmse_ttat), |
| 15298 | /* 41604 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 15299 | /* 41607 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 15300 | /* 41611 */ // MIs[0] Rn |
| 15301 | /* 41611 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 15302 | /* 41615 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 15303 | /* 41619 */ // (intrinsic_wo_chain:{ *:[i32] } 3503:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn) => (t2TTAT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn) |
| 15304 | /* 41619 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2TTAT), |
| 15305 | /* 41622 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt] |
| 15306 | /* 41624 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 15307 | /* 41626 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 15308 | /* 41629 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15309 | /* 41635 */ GIR_RootConstrainSelectedInstOperands, |
| 15310 | /* 41636 */ // GIR_Coverage, 603, |
| 15311 | /* 41636 */ GIR_EraseRootFromParent_Done, |
| 15312 | /* 41637 */ // Label 954: @41637 |
| 15313 | /* 41637 */ GIM_Try, /*On fail goto*//*Label 955*/ GIMT_Encode4(41772), // Rule ID 2693 // |
| 15314 | /* 41642 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 15315 | /* 41645 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sha1h), |
| 15316 | /* 41650 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 15317 | /* 41653 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 15318 | /* 41656 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 15319 | /* 41660 */ // (intrinsic_wo_chain:{ *:[i32] } 3736:{ *:[iPTR] }, i32:{ *:[i32] }:$Rn) => (COPY_TO_REGCLASS:{ *:[i32] } (EXTRACT_SUBREG:{ *:[f32] } (SHA1H:{ *:[v16i8] } (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i64] }, (COPY_TO_REGCLASS:{ *:[f32] } i32:{ *:[i32] }:$Rn, SPR:{ *:[i32] }), ssub_0:{ *:[i32] })), ssub_0:{ *:[i32] }), GPR:{ *:[i32] }) |
| 15320 | /* 41660 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32, |
| 15321 | /* 41663 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 15322 | /* 41667 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 15323 | /* 41672 */ GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 15324 | /* 41676 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 15325 | /* 41681 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8, |
| 15326 | /* 41684 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG), |
| 15327 | /* 41688 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 15328 | /* 41693 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0, |
| 15329 | /* 41696 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3, |
| 15330 | /* 41699 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17, |
| 15331 | /* 41702 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPair_with_ssub_0RegClassID), |
| 15332 | /* 41707 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 15333 | /* 41712 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8, |
| 15334 | /* 41715 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::SHA1H), |
| 15335 | /* 41719 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 15336 | /* 41724 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 15337 | /* 41727 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 15338 | /* 41729 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 15339 | /* 41732 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 15340 | /* 41736 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 15341 | /* 41741 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0), |
| 15342 | /* 41748 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 15343 | /* 41753 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(ARM::MQPRRegClassID), |
| 15344 | /* 41758 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 15345 | /* 41761 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 15346 | /* 41763 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 15347 | /* 41766 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 15348 | /* 41771 */ // GIR_Coverage, 2693, |
| 15349 | /* 41771 */ GIR_EraseRootFromParent_Done, |
| 15350 | /* 41772 */ // Label 955: @41772 |
| 15351 | /* 41772 */ GIM_Reject, |
| 15352 | /* 41773 */ // Label 841: @41773 |
| 15353 | /* 41773 */ GIM_Try, /*On fail goto*//*Label 956*/ GIMT_Encode4(62327), |
| 15354 | /* 41778 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/4, |
| 15355 | /* 41781 */ GIM_Try, /*On fail goto*//*Label 957*/ GIMT_Encode4(41838), // Rule ID 2117 // |
| 15356 | /* 41786 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 15357 | /* 41789 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uxtab16), |
| 15358 | /* 41794 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 15359 | /* 41797 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 15360 | /* 41800 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 15361 | /* 41803 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 15362 | /* 41807 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 15363 | /* 41811 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 15364 | /* 41815 */ // (intrinsic_wo_chain:{ *:[i32] } 3947:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UXTAB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] }) |
| 15365 | /* 41815 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UXTAB16), |
| 15366 | /* 41818 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 15367 | /* 41820 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 15368 | /* 41822 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 15369 | /* 41824 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15370 | /* 41827 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 15371 | /* 41830 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15372 | /* 41836 */ GIR_RootConstrainSelectedInstOperands, |
| 15373 | /* 41837 */ // GIR_Coverage, 2117, |
| 15374 | /* 41837 */ GIR_EraseRootFromParent_Done, |
| 15375 | /* 41838 */ // Label 957: @41838 |
| 15376 | /* 41838 */ GIM_Try, /*On fail goto*//*Label 958*/ GIMT_Encode4(41937), // Rule ID 1888 // |
| 15377 | /* 41843 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 15378 | /* 41846 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usat), |
| 15379 | /* 41851 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 15380 | /* 41854 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 15381 | /* 41857 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 15382 | /* 41860 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 15383 | /* 41864 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 15384 | /* 41868 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), |
| 15385 | /* 41872 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 15386 | /* 41876 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 15387 | /* 41880 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 15388 | /* 41885 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 15389 | /* 41889 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 15390 | /* 41893 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31), |
| 15391 | /* 41897 */ // MIs[2] Operand 1 |
| 15392 | /* 41897 */ // No operand predicates |
| 15393 | /* 41897 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3] |
| 15394 | /* 41901 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 15395 | /* 41905 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31), |
| 15396 | /* 41909 */ // MIs[3] Operand 1 |
| 15397 | /* 41909 */ // No operand predicates |
| 15398 | /* 41909 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 15399 | /* 41911 */ // (intrinsic_wo_chain:{ *:[i32] } 3942:{ *:[iPTR] }, (shl:{ *:[i32] } GPRnopc:{ *:[i32] }:$a, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$shft), (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$pos) => (USAT:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$pos, GPRnopc:{ *:[i32] }:$a, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$shft) |
| 15400 | /* 41911 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::USAT), |
| 15401 | /* 41914 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 15402 | /* 41916 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // pos |
| 15403 | /* 41919 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 15404 | /* 41923 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // shft |
| 15405 | /* 41926 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 15406 | /* 41929 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15407 | /* 41935 */ GIR_RootConstrainSelectedInstOperands, |
| 15408 | /* 41936 */ // GIR_Coverage, 1888, |
| 15409 | /* 41936 */ GIR_EraseRootFromParent_Done, |
| 15410 | /* 41937 */ // Label 958: @41937 |
| 15411 | /* 41937 */ GIM_Try, /*On fail goto*//*Label 959*/ GIMT_Encode4(42036), // Rule ID 2154 // |
| 15412 | /* 41942 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 15413 | /* 41945 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usat), |
| 15414 | /* 41950 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 15415 | /* 41953 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 15416 | /* 41956 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 15417 | /* 41959 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 15418 | /* 41963 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 15419 | /* 41967 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), |
| 15420 | /* 41971 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 15421 | /* 41975 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 15422 | /* 41979 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 15423 | /* 41984 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 15424 | /* 41988 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 15425 | /* 41992 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31), |
| 15426 | /* 41996 */ // MIs[2] Operand 1 |
| 15427 | /* 41996 */ // No operand predicates |
| 15428 | /* 41996 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3] |
| 15429 | /* 42000 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 15430 | /* 42004 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31), |
| 15431 | /* 42008 */ // MIs[3] Operand 1 |
| 15432 | /* 42008 */ // No operand predicates |
| 15433 | /* 42008 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 15434 | /* 42010 */ // (intrinsic_wo_chain:{ *:[i32] } 3942:{ *:[iPTR] }, (shl:{ *:[i32] } GPRnopc:{ *:[i32] }:$a, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$shft), (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$pos) => (t2USAT:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$pos, GPRnopc:{ *:[i32] }:$a, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$shft) |
| 15435 | /* 42010 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2USAT), |
| 15436 | /* 42013 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 15437 | /* 42015 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // pos |
| 15438 | /* 42018 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 15439 | /* 42022 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // shft |
| 15440 | /* 42025 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 15441 | /* 42028 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15442 | /* 42034 */ GIR_RootConstrainSelectedInstOperands, |
| 15443 | /* 42035 */ // GIR_Coverage, 2154, |
| 15444 | /* 42035 */ GIR_EraseRootFromParent_Done, |
| 15445 | /* 42036 */ // Label 959: @42036 |
| 15446 | /* 42036 */ GIM_Try, /*On fail goto*//*Label 960*/ GIMT_Encode4(42120), // Rule ID 5430 // |
| 15447 | /* 42041 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 15448 | /* 42044 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd), |
| 15449 | /* 42049 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 15450 | /* 42052 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 15451 | /* 42055 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 15452 | /* 42058 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 15453 | /* 42062 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 15454 | /* 42066 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC), |
| 15455 | /* 42070 */ GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 15456 | /* 42073 */ GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd), |
| 15457 | /* 42078 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 15458 | /* 42082 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 15459 | /* 42087 */ // MIs[1] Rn |
| 15460 | /* 42087 */ GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 15461 | /* 42092 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 15462 | /* 42096 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 15463 | /* 42098 */ // (intrinsic_wo_chain:{ *:[i32] } 3865:{ *:[iPTR] }, (intrinsic_wo_chain:{ *:[i32] } 3865:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rn), GPRnopc:{ *:[i32] }:$Rm) => (QDADD:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn) |
| 15464 | /* 42098 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QDADD), |
| 15465 | /* 42101 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 15466 | /* 42103 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 15467 | /* 42105 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 15468 | /* 42109 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 15469 | /* 42112 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15470 | /* 42118 */ GIR_RootConstrainSelectedInstOperands, |
| 15471 | /* 42119 */ // GIR_Coverage, 5430, |
| 15472 | /* 42119 */ GIR_EraseRootFromParent_Done, |
| 15473 | /* 42120 */ // Label 960: @42120 |
| 15474 | /* 42120 */ GIM_Try, /*On fail goto*//*Label 961*/ GIMT_Encode4(42204), // Rule ID 5687 // |
| 15475 | /* 42125 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 15476 | /* 42128 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd), |
| 15477 | /* 42133 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 15478 | /* 42136 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 15479 | /* 42139 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 15480 | /* 42142 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 15481 | /* 42146 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 15482 | /* 42150 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC), |
| 15483 | /* 42154 */ GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 15484 | /* 42157 */ GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd), |
| 15485 | /* 42162 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 15486 | /* 42166 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 15487 | /* 42171 */ // MIs[1] Rn |
| 15488 | /* 42171 */ GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 15489 | /* 42176 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 15490 | /* 42180 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 15491 | /* 42182 */ // (intrinsic_wo_chain:{ *:[i32] } 3865:{ *:[iPTR] }, (intrinsic_wo_chain:{ *:[i32] } 3865:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rn), rGPR:{ *:[i32] }:$Rm) => (t2QDADD:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn) |
| 15492 | /* 42182 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QDADD), |
| 15493 | /* 42185 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 15494 | /* 42187 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 15495 | /* 42189 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 15496 | /* 42193 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 15497 | /* 42196 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15498 | /* 42202 */ GIR_RootConstrainSelectedInstOperands, |
| 15499 | /* 42203 */ // GIR_Coverage, 5687, |
| 15500 | /* 42203 */ GIR_EraseRootFromParent_Done, |
| 15501 | /* 42204 */ // Label 961: @42204 |
| 15502 | /* 42204 */ GIM_Try, /*On fail goto*//*Label 962*/ GIMT_Encode4(42288), // Rule ID 109 // |
| 15503 | /* 42209 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 15504 | /* 42212 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd), |
| 15505 | /* 42217 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 15506 | /* 42220 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 15507 | /* 42223 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 15508 | /* 42226 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 15509 | /* 42230 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 15510 | /* 42234 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 15511 | /* 42238 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC), |
| 15512 | /* 42242 */ GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 15513 | /* 42245 */ GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd), |
| 15514 | /* 42250 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 15515 | /* 42254 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 15516 | /* 42259 */ // MIs[1] Rn |
| 15517 | /* 42259 */ GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 15518 | /* 42264 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 15519 | /* 42266 */ // (intrinsic_wo_chain:{ *:[i32] } 3865:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rm, (intrinsic_wo_chain:{ *:[i32] } 3865:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rn)) => (QDADD:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn) |
| 15520 | /* 42266 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QDADD), |
| 15521 | /* 42269 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 15522 | /* 42271 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 15523 | /* 42273 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 15524 | /* 42277 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 15525 | /* 42280 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15526 | /* 42286 */ GIR_RootConstrainSelectedInstOperands, |
| 15527 | /* 42287 */ // GIR_Coverage, 109, |
| 15528 | /* 42287 */ GIR_EraseRootFromParent_Done, |
| 15529 | /* 42288 */ // Label 962: @42288 |
| 15530 | /* 42288 */ GIM_Try, /*On fail goto*//*Label 963*/ GIMT_Encode4(42372), // Rule ID 110 // |
| 15531 | /* 42293 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 15532 | /* 42296 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qsub), |
| 15533 | /* 42301 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 15534 | /* 42304 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 15535 | /* 42307 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 15536 | /* 42310 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 15537 | /* 42314 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 15538 | /* 42318 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 15539 | /* 42322 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC), |
| 15540 | /* 42326 */ GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 15541 | /* 42329 */ GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd), |
| 15542 | /* 42334 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 15543 | /* 42338 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 15544 | /* 42343 */ // MIs[1] Rn |
| 15545 | /* 42343 */ GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 15546 | /* 42348 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 15547 | /* 42350 */ // (intrinsic_wo_chain:{ *:[i32] } 3870:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rm, (intrinsic_wo_chain:{ *:[i32] } 3865:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rn)) => (QDSUB:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn) |
| 15548 | /* 42350 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QDSUB), |
| 15549 | /* 42353 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 15550 | /* 42355 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 15551 | /* 42357 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 15552 | /* 42361 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 15553 | /* 42364 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15554 | /* 42370 */ GIR_RootConstrainSelectedInstOperands, |
| 15555 | /* 42371 */ // GIR_Coverage, 110, |
| 15556 | /* 42371 */ GIR_EraseRootFromParent_Done, |
| 15557 | /* 42372 */ // Label 963: @42372 |
| 15558 | /* 42372 */ GIM_Try, /*On fail goto*//*Label 964*/ GIMT_Encode4(42456), // Rule ID 2132 // |
| 15559 | /* 42377 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 15560 | /* 42380 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd), |
| 15561 | /* 42385 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 15562 | /* 42388 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 15563 | /* 42391 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 15564 | /* 42394 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 15565 | /* 42398 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 15566 | /* 42402 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 15567 | /* 42406 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC), |
| 15568 | /* 42410 */ GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 15569 | /* 42413 */ GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd), |
| 15570 | /* 42418 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 15571 | /* 42422 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 15572 | /* 42427 */ // MIs[1] Rn |
| 15573 | /* 42427 */ GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 15574 | /* 42432 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 15575 | /* 42434 */ // (intrinsic_wo_chain:{ *:[i32] } 3865:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rm, (intrinsic_wo_chain:{ *:[i32] } 3865:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rn)) => (t2QDADD:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn) |
| 15576 | /* 42434 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QDADD), |
| 15577 | /* 42437 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 15578 | /* 42439 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 15579 | /* 42441 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 15580 | /* 42445 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 15581 | /* 42448 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15582 | /* 42454 */ GIR_RootConstrainSelectedInstOperands, |
| 15583 | /* 42455 */ // GIR_Coverage, 2132, |
| 15584 | /* 42455 */ GIR_EraseRootFromParent_Done, |
| 15585 | /* 42456 */ // Label 964: @42456 |
| 15586 | /* 42456 */ GIM_Try, /*On fail goto*//*Label 965*/ GIMT_Encode4(42540), // Rule ID 2133 // |
| 15587 | /* 42461 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 15588 | /* 42464 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qsub), |
| 15589 | /* 42469 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 15590 | /* 42472 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 15591 | /* 42475 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 15592 | /* 42478 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 15593 | /* 42482 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 15594 | /* 42486 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 15595 | /* 42490 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC), |
| 15596 | /* 42494 */ GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 15597 | /* 42497 */ GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd), |
| 15598 | /* 42502 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 15599 | /* 42506 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 15600 | /* 42511 */ // MIs[1] Rn |
| 15601 | /* 42511 */ GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 15602 | /* 42516 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 15603 | /* 42518 */ // (intrinsic_wo_chain:{ *:[i32] } 3870:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rm, (intrinsic_wo_chain:{ *:[i32] } 3865:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rn)) => (t2QDSUB:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn) |
| 15604 | /* 42518 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QDSUB), |
| 15605 | /* 42521 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 15606 | /* 42523 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 15607 | /* 42525 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 15608 | /* 42529 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 15609 | /* 42532 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15610 | /* 42538 */ GIR_RootConstrainSelectedInstOperands, |
| 15611 | /* 42539 */ // GIR_Coverage, 2133, |
| 15612 | /* 42539 */ GIR_EraseRootFromParent_Done, |
| 15613 | /* 42540 */ // Label 965: @42540 |
| 15614 | /* 42540 */ GIM_Try, /*On fail goto*//*Label 966*/ GIMT_Encode4(42613), // Rule ID 4058 // |
| 15615 | /* 42545 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 15616 | /* 42548 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvta), |
| 15617 | /* 42553 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 15618 | /* 42556 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 15619 | /* 42559 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 15620 | /* 42562 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 15621 | /* 42566 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 15622 | /* 42570 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 15623 | /* 42574 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3627:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v8f16] }:$in) => (MVE_VCVTs16f16a:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$in) |
| 15624 | /* 42574 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 15625 | /* 42577 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 15626 | /* 42581 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 15627 | /* 42586 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs16f16a), |
| 15628 | /* 42589 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 15629 | /* 42591 */ GIR_RootToRootCopy, /*OpIdx*/3, // in |
| 15630 | /* 42593 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15631 | /* 42596 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15632 | /* 42602 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15633 | /* 42608 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 15634 | /* 42611 */ GIR_RootConstrainSelectedInstOperands, |
| 15635 | /* 42612 */ // GIR_Coverage, 4058, |
| 15636 | /* 42612 */ GIR_EraseRootFromParent_Done, |
| 15637 | /* 42613 */ // Label 966: @42613 |
| 15638 | /* 42613 */ GIM_Try, /*On fail goto*//*Label 967*/ GIMT_Encode4(42686), // Rule ID 4060 // |
| 15639 | /* 42618 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 15640 | /* 42621 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtn), |
| 15641 | /* 42626 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 15642 | /* 42629 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 15643 | /* 42632 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 15644 | /* 42635 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 15645 | /* 42639 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 15646 | /* 42643 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 15647 | /* 42647 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3631:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v8f16] }:$in) => (MVE_VCVTs16f16n:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$in) |
| 15648 | /* 42647 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 15649 | /* 42650 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 15650 | /* 42654 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 15651 | /* 42659 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs16f16n), |
| 15652 | /* 42662 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 15653 | /* 42664 */ GIR_RootToRootCopy, /*OpIdx*/3, // in |
| 15654 | /* 42666 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15655 | /* 42669 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15656 | /* 42675 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15657 | /* 42681 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 15658 | /* 42684 */ GIR_RootConstrainSelectedInstOperands, |
| 15659 | /* 42685 */ // GIR_Coverage, 4060, |
| 15660 | /* 42685 */ GIR_EraseRootFromParent_Done, |
| 15661 | /* 42686 */ // Label 967: @42686 |
| 15662 | /* 42686 */ GIM_Try, /*On fail goto*//*Label 968*/ GIMT_Encode4(42759), // Rule ID 4062 // |
| 15663 | /* 42691 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 15664 | /* 42694 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtp), |
| 15665 | /* 42699 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 15666 | /* 42702 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 15667 | /* 42705 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 15668 | /* 42708 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 15669 | /* 42712 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 15670 | /* 42716 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 15671 | /* 42720 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3633:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v8f16] }:$in) => (MVE_VCVTs16f16p:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$in) |
| 15672 | /* 42720 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 15673 | /* 42723 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 15674 | /* 42727 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 15675 | /* 42732 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs16f16p), |
| 15676 | /* 42735 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 15677 | /* 42737 */ GIR_RootToRootCopy, /*OpIdx*/3, // in |
| 15678 | /* 42739 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15679 | /* 42742 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15680 | /* 42748 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15681 | /* 42754 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 15682 | /* 42757 */ GIR_RootConstrainSelectedInstOperands, |
| 15683 | /* 42758 */ // GIR_Coverage, 4062, |
| 15684 | /* 42758 */ GIR_EraseRootFromParent_Done, |
| 15685 | /* 42759 */ // Label 968: @42759 |
| 15686 | /* 42759 */ GIM_Try, /*On fail goto*//*Label 969*/ GIMT_Encode4(42832), // Rule ID 4064 // |
| 15687 | /* 42764 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 15688 | /* 42767 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtm), |
| 15689 | /* 42772 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 15690 | /* 42775 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 15691 | /* 42778 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 15692 | /* 42781 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 15693 | /* 42785 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 15694 | /* 42789 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 15695 | /* 42793 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3629:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v8f16] }:$in) => (MVE_VCVTs16f16m:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$in) |
| 15696 | /* 42793 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 15697 | /* 42796 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 15698 | /* 42800 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 15699 | /* 42805 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs16f16m), |
| 15700 | /* 42808 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 15701 | /* 42810 */ GIR_RootToRootCopy, /*OpIdx*/3, // in |
| 15702 | /* 42812 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15703 | /* 42815 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15704 | /* 42821 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15705 | /* 42827 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 15706 | /* 42830 */ GIR_RootConstrainSelectedInstOperands, |
| 15707 | /* 42831 */ // GIR_Coverage, 4064, |
| 15708 | /* 42831 */ GIR_EraseRootFromParent_Done, |
| 15709 | /* 42832 */ // Label 969: @42832 |
| 15710 | /* 42832 */ GIM_Try, /*On fail goto*//*Label 970*/ GIMT_Encode4(42905), // Rule ID 4066 // |
| 15711 | /* 42837 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 15712 | /* 42840 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvta), |
| 15713 | /* 42845 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 15714 | /* 42848 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 15715 | /* 42851 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 15716 | /* 42854 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 15717 | /* 42858 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 15718 | /* 42862 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 15719 | /* 42866 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3627:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v8f16] }:$in) => (MVE_VCVTu16f16a:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$in) |
| 15720 | /* 42866 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 15721 | /* 42869 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 15722 | /* 42873 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 15723 | /* 42878 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu16f16a), |
| 15724 | /* 42881 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 15725 | /* 42883 */ GIR_RootToRootCopy, /*OpIdx*/3, // in |
| 15726 | /* 42885 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15727 | /* 42888 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15728 | /* 42894 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15729 | /* 42900 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 15730 | /* 42903 */ GIR_RootConstrainSelectedInstOperands, |
| 15731 | /* 42904 */ // GIR_Coverage, 4066, |
| 15732 | /* 42904 */ GIR_EraseRootFromParent_Done, |
| 15733 | /* 42905 */ // Label 970: @42905 |
| 15734 | /* 42905 */ GIM_Try, /*On fail goto*//*Label 971*/ GIMT_Encode4(42978), // Rule ID 4068 // |
| 15735 | /* 42910 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 15736 | /* 42913 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtn), |
| 15737 | /* 42918 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 15738 | /* 42921 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 15739 | /* 42924 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 15740 | /* 42927 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 15741 | /* 42931 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 15742 | /* 42935 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 15743 | /* 42939 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3631:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v8f16] }:$in) => (MVE_VCVTu16f16n:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$in) |
| 15744 | /* 42939 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 15745 | /* 42942 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 15746 | /* 42946 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 15747 | /* 42951 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu16f16n), |
| 15748 | /* 42954 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 15749 | /* 42956 */ GIR_RootToRootCopy, /*OpIdx*/3, // in |
| 15750 | /* 42958 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15751 | /* 42961 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15752 | /* 42967 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15753 | /* 42973 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 15754 | /* 42976 */ GIR_RootConstrainSelectedInstOperands, |
| 15755 | /* 42977 */ // GIR_Coverage, 4068, |
| 15756 | /* 42977 */ GIR_EraseRootFromParent_Done, |
| 15757 | /* 42978 */ // Label 971: @42978 |
| 15758 | /* 42978 */ GIM_Try, /*On fail goto*//*Label 972*/ GIMT_Encode4(43051), // Rule ID 4070 // |
| 15759 | /* 42983 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 15760 | /* 42986 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtp), |
| 15761 | /* 42991 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 15762 | /* 42994 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 15763 | /* 42997 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 15764 | /* 43000 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 15765 | /* 43004 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 15766 | /* 43008 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 15767 | /* 43012 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3633:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v8f16] }:$in) => (MVE_VCVTu16f16p:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$in) |
| 15768 | /* 43012 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 15769 | /* 43015 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 15770 | /* 43019 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 15771 | /* 43024 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu16f16p), |
| 15772 | /* 43027 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 15773 | /* 43029 */ GIR_RootToRootCopy, /*OpIdx*/3, // in |
| 15774 | /* 43031 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15775 | /* 43034 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15776 | /* 43040 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15777 | /* 43046 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 15778 | /* 43049 */ GIR_RootConstrainSelectedInstOperands, |
| 15779 | /* 43050 */ // GIR_Coverage, 4070, |
| 15780 | /* 43050 */ GIR_EraseRootFromParent_Done, |
| 15781 | /* 43051 */ // Label 972: @43051 |
| 15782 | /* 43051 */ GIM_Try, /*On fail goto*//*Label 973*/ GIMT_Encode4(43124), // Rule ID 4072 // |
| 15783 | /* 43056 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 15784 | /* 43059 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtm), |
| 15785 | /* 43064 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 15786 | /* 43067 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 15787 | /* 43070 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 15788 | /* 43073 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 15789 | /* 43077 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 15790 | /* 43081 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 15791 | /* 43085 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3629:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v8f16] }:$in) => (MVE_VCVTu16f16m:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$in) |
| 15792 | /* 43085 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 15793 | /* 43088 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 15794 | /* 43092 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 15795 | /* 43097 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu16f16m), |
| 15796 | /* 43100 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 15797 | /* 43102 */ GIR_RootToRootCopy, /*OpIdx*/3, // in |
| 15798 | /* 43104 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15799 | /* 43107 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15800 | /* 43113 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15801 | /* 43119 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 15802 | /* 43122 */ GIR_RootConstrainSelectedInstOperands, |
| 15803 | /* 43123 */ // GIR_Coverage, 4072, |
| 15804 | /* 43123 */ GIR_EraseRootFromParent_Done, |
| 15805 | /* 43124 */ // Label 973: @43124 |
| 15806 | /* 43124 */ GIM_Try, /*On fail goto*//*Label 974*/ GIMT_Encode4(43197), // Rule ID 4074 // |
| 15807 | /* 43129 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 15808 | /* 43132 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvta), |
| 15809 | /* 43137 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 15810 | /* 43140 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 15811 | /* 43143 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 15812 | /* 43146 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 15813 | /* 43150 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 15814 | /* 43154 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 15815 | /* 43158 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3627:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v4f32] }:$in) => (MVE_VCVTs32f32a:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$in) |
| 15816 | /* 43158 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 15817 | /* 43161 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 15818 | /* 43165 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 15819 | /* 43170 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs32f32a), |
| 15820 | /* 43173 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 15821 | /* 43175 */ GIR_RootToRootCopy, /*OpIdx*/3, // in |
| 15822 | /* 43177 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15823 | /* 43180 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15824 | /* 43186 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15825 | /* 43192 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 15826 | /* 43195 */ GIR_RootConstrainSelectedInstOperands, |
| 15827 | /* 43196 */ // GIR_Coverage, 4074, |
| 15828 | /* 43196 */ GIR_EraseRootFromParent_Done, |
| 15829 | /* 43197 */ // Label 974: @43197 |
| 15830 | /* 43197 */ GIM_Try, /*On fail goto*//*Label 975*/ GIMT_Encode4(43270), // Rule ID 4076 // |
| 15831 | /* 43202 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 15832 | /* 43205 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtn), |
| 15833 | /* 43210 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 15834 | /* 43213 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 15835 | /* 43216 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 15836 | /* 43219 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 15837 | /* 43223 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 15838 | /* 43227 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 15839 | /* 43231 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3631:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v4f32] }:$in) => (MVE_VCVTs32f32n:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$in) |
| 15840 | /* 43231 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 15841 | /* 43234 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 15842 | /* 43238 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 15843 | /* 43243 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs32f32n), |
| 15844 | /* 43246 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 15845 | /* 43248 */ GIR_RootToRootCopy, /*OpIdx*/3, // in |
| 15846 | /* 43250 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15847 | /* 43253 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15848 | /* 43259 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15849 | /* 43265 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 15850 | /* 43268 */ GIR_RootConstrainSelectedInstOperands, |
| 15851 | /* 43269 */ // GIR_Coverage, 4076, |
| 15852 | /* 43269 */ GIR_EraseRootFromParent_Done, |
| 15853 | /* 43270 */ // Label 975: @43270 |
| 15854 | /* 43270 */ GIM_Try, /*On fail goto*//*Label 976*/ GIMT_Encode4(43343), // Rule ID 4078 // |
| 15855 | /* 43275 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 15856 | /* 43278 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtp), |
| 15857 | /* 43283 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 15858 | /* 43286 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 15859 | /* 43289 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 15860 | /* 43292 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 15861 | /* 43296 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 15862 | /* 43300 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 15863 | /* 43304 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3633:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v4f32] }:$in) => (MVE_VCVTs32f32p:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$in) |
| 15864 | /* 43304 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 15865 | /* 43307 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 15866 | /* 43311 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 15867 | /* 43316 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs32f32p), |
| 15868 | /* 43319 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 15869 | /* 43321 */ GIR_RootToRootCopy, /*OpIdx*/3, // in |
| 15870 | /* 43323 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15871 | /* 43326 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15872 | /* 43332 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15873 | /* 43338 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 15874 | /* 43341 */ GIR_RootConstrainSelectedInstOperands, |
| 15875 | /* 43342 */ // GIR_Coverage, 4078, |
| 15876 | /* 43342 */ GIR_EraseRootFromParent_Done, |
| 15877 | /* 43343 */ // Label 976: @43343 |
| 15878 | /* 43343 */ GIM_Try, /*On fail goto*//*Label 977*/ GIMT_Encode4(43416), // Rule ID 4080 // |
| 15879 | /* 43348 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 15880 | /* 43351 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtm), |
| 15881 | /* 43356 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 15882 | /* 43359 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 15883 | /* 43362 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 15884 | /* 43365 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 15885 | /* 43369 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 15886 | /* 43373 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 15887 | /* 43377 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3629:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v4f32] }:$in) => (MVE_VCVTs32f32m:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$in) |
| 15888 | /* 43377 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 15889 | /* 43380 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 15890 | /* 43384 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 15891 | /* 43389 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs32f32m), |
| 15892 | /* 43392 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 15893 | /* 43394 */ GIR_RootToRootCopy, /*OpIdx*/3, // in |
| 15894 | /* 43396 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15895 | /* 43399 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15896 | /* 43405 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15897 | /* 43411 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 15898 | /* 43414 */ GIR_RootConstrainSelectedInstOperands, |
| 15899 | /* 43415 */ // GIR_Coverage, 4080, |
| 15900 | /* 43415 */ GIR_EraseRootFromParent_Done, |
| 15901 | /* 43416 */ // Label 977: @43416 |
| 15902 | /* 43416 */ GIM_Try, /*On fail goto*//*Label 978*/ GIMT_Encode4(43489), // Rule ID 4082 // |
| 15903 | /* 43421 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 15904 | /* 43424 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvta), |
| 15905 | /* 43429 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 15906 | /* 43432 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 15907 | /* 43435 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 15908 | /* 43438 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 15909 | /* 43442 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 15910 | /* 43446 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 15911 | /* 43450 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3627:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v4f32] }:$in) => (MVE_VCVTu32f32a:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$in) |
| 15912 | /* 43450 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 15913 | /* 43453 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 15914 | /* 43457 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 15915 | /* 43462 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu32f32a), |
| 15916 | /* 43465 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 15917 | /* 43467 */ GIR_RootToRootCopy, /*OpIdx*/3, // in |
| 15918 | /* 43469 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15919 | /* 43472 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15920 | /* 43478 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15921 | /* 43484 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 15922 | /* 43487 */ GIR_RootConstrainSelectedInstOperands, |
| 15923 | /* 43488 */ // GIR_Coverage, 4082, |
| 15924 | /* 43488 */ GIR_EraseRootFromParent_Done, |
| 15925 | /* 43489 */ // Label 978: @43489 |
| 15926 | /* 43489 */ GIM_Try, /*On fail goto*//*Label 979*/ GIMT_Encode4(43562), // Rule ID 4084 // |
| 15927 | /* 43494 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 15928 | /* 43497 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtn), |
| 15929 | /* 43502 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 15930 | /* 43505 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 15931 | /* 43508 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 15932 | /* 43511 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 15933 | /* 43515 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 15934 | /* 43519 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 15935 | /* 43523 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3631:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v4f32] }:$in) => (MVE_VCVTu32f32n:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$in) |
| 15936 | /* 43523 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 15937 | /* 43526 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 15938 | /* 43530 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 15939 | /* 43535 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu32f32n), |
| 15940 | /* 43538 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 15941 | /* 43540 */ GIR_RootToRootCopy, /*OpIdx*/3, // in |
| 15942 | /* 43542 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15943 | /* 43545 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15944 | /* 43551 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15945 | /* 43557 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 15946 | /* 43560 */ GIR_RootConstrainSelectedInstOperands, |
| 15947 | /* 43561 */ // GIR_Coverage, 4084, |
| 15948 | /* 43561 */ GIR_EraseRootFromParent_Done, |
| 15949 | /* 43562 */ // Label 979: @43562 |
| 15950 | /* 43562 */ GIM_Try, /*On fail goto*//*Label 980*/ GIMT_Encode4(43635), // Rule ID 4086 // |
| 15951 | /* 43567 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 15952 | /* 43570 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtp), |
| 15953 | /* 43575 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 15954 | /* 43578 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 15955 | /* 43581 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 15956 | /* 43584 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 15957 | /* 43588 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 15958 | /* 43592 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 15959 | /* 43596 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3633:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v4f32] }:$in) => (MVE_VCVTu32f32p:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$in) |
| 15960 | /* 43596 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 15961 | /* 43599 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 15962 | /* 43603 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 15963 | /* 43608 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu32f32p), |
| 15964 | /* 43611 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 15965 | /* 43613 */ GIR_RootToRootCopy, /*OpIdx*/3, // in |
| 15966 | /* 43615 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15967 | /* 43618 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15968 | /* 43624 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15969 | /* 43630 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 15970 | /* 43633 */ GIR_RootConstrainSelectedInstOperands, |
| 15971 | /* 43634 */ // GIR_Coverage, 4086, |
| 15972 | /* 43634 */ GIR_EraseRootFromParent_Done, |
| 15973 | /* 43635 */ // Label 980: @43635 |
| 15974 | /* 43635 */ GIM_Try, /*On fail goto*//*Label 981*/ GIMT_Encode4(43708), // Rule ID 4088 // |
| 15975 | /* 43640 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 15976 | /* 43643 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtm), |
| 15977 | /* 43648 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 15978 | /* 43651 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 15979 | /* 43654 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 15980 | /* 43657 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 15981 | /* 43661 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 15982 | /* 43665 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 15983 | /* 43669 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3629:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v4f32] }:$in) => (MVE_VCVTu32f32m:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$in) |
| 15984 | /* 43669 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 15985 | /* 43672 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 15986 | /* 43676 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 15987 | /* 43681 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu32f32m), |
| 15988 | /* 43684 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 15989 | /* 43686 */ GIR_RootToRootCopy, /*OpIdx*/3, // in |
| 15990 | /* 43688 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15991 | /* 43691 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15992 | /* 43697 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15993 | /* 43703 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 15994 | /* 43706 */ GIR_RootConstrainSelectedInstOperands, |
| 15995 | /* 43707 */ // GIR_Coverage, 4088, |
| 15996 | /* 43707 */ GIR_EraseRootFromParent_Done, |
| 15997 | /* 43708 */ // Label 981: @43708 |
| 15998 | /* 43708 */ GIM_Try, /*On fail goto*//*Label 982*/ GIMT_Encode4(43781), // Rule ID 4532 // |
| 15999 | /* 43713 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 16000 | /* 43716 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_widen), |
| 16001 | /* 43721 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 16002 | /* 43724 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 16003 | /* 43727 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 16004 | /* 43730 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16005 | /* 43734 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16006 | /* 43738 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 16007 | /* 43742 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3625:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$Qm, 0:{ *:[i32] }) => (MVE_VCVTf32f16bh:{ *:[v4f32] } MQPR:{ *:[v8f16] }:$Qm) |
| 16008 | /* 43742 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 16009 | /* 43745 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 16010 | /* 43749 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 16011 | /* 43754 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf32f16bh), |
| 16012 | /* 43757 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 16013 | /* 43759 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 16014 | /* 43761 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16015 | /* 43764 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16016 | /* 43770 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16017 | /* 43776 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 16018 | /* 43779 */ GIR_RootConstrainSelectedInstOperands, |
| 16019 | /* 43780 */ // GIR_Coverage, 4532, |
| 16020 | /* 43780 */ GIR_EraseRootFromParent_Done, |
| 16021 | /* 43781 */ // Label 982: @43781 |
| 16022 | /* 43781 */ GIM_Try, /*On fail goto*//*Label 983*/ GIMT_Encode4(43854), // Rule ID 4538 // |
| 16023 | /* 43786 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 16024 | /* 43789 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_widen), |
| 16025 | /* 43794 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 16026 | /* 43797 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 16027 | /* 43800 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 16028 | /* 43803 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16029 | /* 43807 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16030 | /* 43811 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1, |
| 16031 | /* 43815 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3625:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$Qm, 1:{ *:[i32] }) => (MVE_VCVTf32f16th:{ *:[v4f32] } MQPR:{ *:[v8f16] }:$Qm) |
| 16032 | /* 43815 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 16033 | /* 43818 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 16034 | /* 43822 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 16035 | /* 43827 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf32f16th), |
| 16036 | /* 43830 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 16037 | /* 43832 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 16038 | /* 43834 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16039 | /* 43837 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16040 | /* 43843 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16041 | /* 43849 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 16042 | /* 43852 */ GIR_RootConstrainSelectedInstOperands, |
| 16043 | /* 43853 */ // GIR_Coverage, 4538, |
| 16044 | /* 43853 */ GIR_EraseRootFromParent_Done, |
| 16045 | /* 43854 */ // Label 983: @43854 |
| 16046 | /* 43854 */ GIM_Try, /*On fail goto*//*Label 984*/ GIMT_Encode4(43922), // Rule ID 1881 // |
| 16047 | /* 43859 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 16048 | /* 43862 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usat), |
| 16049 | /* 43867 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 16050 | /* 43870 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16051 | /* 43873 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 16052 | /* 43876 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16053 | /* 43880 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16054 | /* 43884 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 16055 | /* 43888 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 16056 | /* 43892 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31), |
| 16057 | /* 43896 */ // MIs[1] Operand 1 |
| 16058 | /* 43896 */ // No operand predicates |
| 16059 | /* 43896 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 16060 | /* 43898 */ // (intrinsic_wo_chain:{ *:[i32] } 3942:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$a, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$pos) => (USAT:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$pos, GPRnopc:{ *:[i32] }:$a, 0:{ *:[i32] }) |
| 16061 | /* 43898 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::USAT), |
| 16062 | /* 43901 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 16063 | /* 43903 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // pos |
| 16064 | /* 43906 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 16065 | /* 43908 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16066 | /* 43911 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16067 | /* 43914 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16068 | /* 43920 */ GIR_RootConstrainSelectedInstOperands, |
| 16069 | /* 43921 */ // GIR_Coverage, 1881, |
| 16070 | /* 43921 */ GIR_EraseRootFromParent_Done, |
| 16071 | /* 43922 */ // Label 984: @43922 |
| 16072 | /* 43922 */ GIM_Try, /*On fail goto*//*Label 985*/ GIMT_Encode4(43987), // Rule ID 1885 // |
| 16073 | /* 43927 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 16074 | /* 43930 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usat16), |
| 16075 | /* 43935 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 16076 | /* 43938 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16077 | /* 43941 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 16078 | /* 43944 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16079 | /* 43948 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16080 | /* 43952 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 16081 | /* 43956 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 16082 | /* 43960 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15), |
| 16083 | /* 43964 */ // MIs[1] Operand 1 |
| 16084 | /* 43964 */ // No operand predicates |
| 16085 | /* 43964 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 16086 | /* 43966 */ // (intrinsic_wo_chain:{ *:[i32] } 3943:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$a, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$pos) => (USAT16:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$pos, GPRnopc:{ *:[i32] }:$a) |
| 16087 | /* 43966 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::USAT16), |
| 16088 | /* 43969 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 16089 | /* 43971 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // pos |
| 16090 | /* 43974 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 16091 | /* 43976 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16092 | /* 43979 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16093 | /* 43985 */ GIR_RootConstrainSelectedInstOperands, |
| 16094 | /* 43986 */ // GIR_Coverage, 1885, |
| 16095 | /* 43986 */ GIR_EraseRootFromParent_Done, |
| 16096 | /* 43987 */ // Label 985: @43987 |
| 16097 | /* 43987 */ GIM_Try, /*On fail goto*//*Label 986*/ GIMT_Encode4(44055), // Rule ID 2149 // |
| 16098 | /* 43992 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 16099 | /* 43995 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usat), |
| 16100 | /* 44000 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 16101 | /* 44003 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16102 | /* 44006 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 16103 | /* 44009 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16104 | /* 44013 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 16105 | /* 44017 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 16106 | /* 44021 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 16107 | /* 44025 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31), |
| 16108 | /* 44029 */ // MIs[1] Operand 1 |
| 16109 | /* 44029 */ // No operand predicates |
| 16110 | /* 44029 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 16111 | /* 44031 */ // (intrinsic_wo_chain:{ *:[i32] } 3942:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$pos) => (t2USAT:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$pos, GPR:{ *:[i32] }:$a, 0:{ *:[i32] }) |
| 16112 | /* 44031 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2USAT), |
| 16113 | /* 44034 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 16114 | /* 44036 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // pos |
| 16115 | /* 44039 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 16116 | /* 44041 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16117 | /* 44044 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16118 | /* 44047 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16119 | /* 44053 */ GIR_RootConstrainSelectedInstOperands, |
| 16120 | /* 44054 */ // GIR_Coverage, 2149, |
| 16121 | /* 44054 */ GIR_EraseRootFromParent_Done, |
| 16122 | /* 44055 */ // Label 986: @44055 |
| 16123 | /* 44055 */ GIM_Try, /*On fail goto*//*Label 987*/ GIMT_Encode4(44120), // Rule ID 2151 // |
| 16124 | /* 44060 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 16125 | /* 44063 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usat16), |
| 16126 | /* 44068 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 16127 | /* 44071 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16128 | /* 44074 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 16129 | /* 44077 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16130 | /* 44081 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 16131 | /* 44085 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 16132 | /* 44089 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 16133 | /* 44093 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15), |
| 16134 | /* 44097 */ // MIs[1] Operand 1 |
| 16135 | /* 44097 */ // No operand predicates |
| 16136 | /* 44097 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 16137 | /* 44099 */ // (intrinsic_wo_chain:{ *:[i32] } 3943:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$pos) => (t2USAT16:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$pos, GPR:{ *:[i32] }:$a) |
| 16138 | /* 44099 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2USAT16), |
| 16139 | /* 44102 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 16140 | /* 44104 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // pos |
| 16141 | /* 44107 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 16142 | /* 44109 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16143 | /* 44112 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16144 | /* 44118 */ GIR_RootConstrainSelectedInstOperands, |
| 16145 | /* 44119 */ // GIR_Coverage, 2151, |
| 16146 | /* 44119 */ GIR_EraseRootFromParent_Done, |
| 16147 | /* 44120 */ // Label 987: @44120 |
| 16148 | /* 44120 */ GIM_Try, /*On fail goto*//*Label 988*/ GIMT_Encode4(44203), // Rule ID 3928 // |
| 16149 | /* 44125 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqshlu_imm), |
| 16150 | /* 44130 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 16151 | /* 44133 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 16152 | /* 44136 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 16153 | /* 44139 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16154 | /* 44143 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16155 | /* 44147 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 16156 | /* 44151 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 16157 | /* 44155 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_7), |
| 16158 | /* 44159 */ // MIs[1] Operand 1 |
| 16159 | /* 44159 */ // No operand predicates |
| 16160 | /* 44159 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 16161 | /* 44161 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3686:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_7>>:$imm) => (MVE_VQSHLU_imms8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_7>>:$imm) |
| 16162 | /* 44161 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 16163 | /* 44164 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 16164 | /* 44168 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 16165 | /* 44173 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHLU_imms8), |
| 16166 | /* 44176 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 16167 | /* 44178 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 16168 | /* 44180 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 16169 | /* 44183 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16170 | /* 44186 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16171 | /* 44192 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16172 | /* 44198 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 16173 | /* 44201 */ GIR_RootConstrainSelectedInstOperands, |
| 16174 | /* 44202 */ // GIR_Coverage, 3928, |
| 16175 | /* 44202 */ GIR_EraseRootFromParent_Done, |
| 16176 | /* 44203 */ // Label 988: @44203 |
| 16177 | /* 44203 */ GIM_Try, /*On fail goto*//*Label 989*/ GIMT_Encode4(44286), // Rule ID 3930 // |
| 16178 | /* 44208 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqshlu_imm), |
| 16179 | /* 44213 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 16180 | /* 44216 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 16181 | /* 44219 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 16182 | /* 44222 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16183 | /* 44226 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16184 | /* 44230 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 16185 | /* 44234 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 16186 | /* 44238 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15), |
| 16187 | /* 44242 */ // MIs[1] Operand 1 |
| 16188 | /* 44242 */ // No operand predicates |
| 16189 | /* 44242 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 16190 | /* 44244 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3686:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$imm) => (MVE_VQSHLU_imms16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$imm) |
| 16191 | /* 44244 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 16192 | /* 44247 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 16193 | /* 44251 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 16194 | /* 44256 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHLU_imms16), |
| 16195 | /* 44259 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 16196 | /* 44261 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 16197 | /* 44263 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 16198 | /* 44266 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16199 | /* 44269 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16200 | /* 44275 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16201 | /* 44281 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 16202 | /* 44284 */ GIR_RootConstrainSelectedInstOperands, |
| 16203 | /* 44285 */ // GIR_Coverage, 3930, |
| 16204 | /* 44285 */ GIR_EraseRootFromParent_Done, |
| 16205 | /* 44286 */ // Label 989: @44286 |
| 16206 | /* 44286 */ GIM_Try, /*On fail goto*//*Label 990*/ GIMT_Encode4(44369), // Rule ID 3932 // |
| 16207 | /* 44291 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqshlu_imm), |
| 16208 | /* 44296 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 16209 | /* 44299 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 16210 | /* 44302 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 16211 | /* 44305 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16212 | /* 44309 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16213 | /* 44313 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 16214 | /* 44317 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 16215 | /* 44321 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31), |
| 16216 | /* 44325 */ // MIs[1] Operand 1 |
| 16217 | /* 44325 */ // No operand predicates |
| 16218 | /* 44325 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 16219 | /* 44327 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3686:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$imm) => (MVE_VQSHLU_imms32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$imm) |
| 16220 | /* 44327 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 16221 | /* 44330 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 16222 | /* 44334 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 16223 | /* 44339 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHLU_imms32), |
| 16224 | /* 44342 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 16225 | /* 44344 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 16226 | /* 44346 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 16227 | /* 44349 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16228 | /* 44352 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16229 | /* 44358 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16230 | /* 44364 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 16231 | /* 44367 */ GIR_RootConstrainSelectedInstOperands, |
| 16232 | /* 44368 */ // GIR_Coverage, 3932, |
| 16233 | /* 44368 */ GIR_EraseRootFromParent_Done, |
| 16234 | /* 44369 */ // Label 990: @44369 |
| 16235 | /* 44369 */ GIM_Try, /*On fail goto*//*Label 991*/ GIMT_Encode4(44430), // Rule ID 1652 // |
| 16236 | /* 44374 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 16237 | /* 44377 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfp2fxs), |
| 16238 | /* 44382 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 16239 | /* 44385 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 16240 | /* 44388 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 16241 | /* 44391 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 16242 | /* 44395 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 16243 | /* 44399 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 16244 | /* 44403 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 16245 | /* 44407 */ // MIs[1] Operand 1 |
| 16246 | /* 44407 */ // No operand predicates |
| 16247 | /* 44407 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 16248 | /* 44409 */ // (intrinsic_wo_chain:{ *:[v2i32] } 3763:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTf2xsd:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm, (imm:{ *:[i32] }):$SIMM) |
| 16249 | /* 44409 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTf2xsd), |
| 16250 | /* 44412 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 16251 | /* 44414 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 16252 | /* 44416 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM |
| 16253 | /* 44419 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16254 | /* 44422 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16255 | /* 44428 */ GIR_RootConstrainSelectedInstOperands, |
| 16256 | /* 44429 */ // GIR_Coverage, 1652, |
| 16257 | /* 44429 */ GIR_EraseRootFromParent_Done, |
| 16258 | /* 44430 */ // Label 991: @44430 |
| 16259 | /* 44430 */ GIM_Try, /*On fail goto*//*Label 992*/ GIMT_Encode4(44491), // Rule ID 1653 // |
| 16260 | /* 44435 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 16261 | /* 44438 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfp2fxu), |
| 16262 | /* 44443 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 16263 | /* 44446 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 16264 | /* 44449 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 16265 | /* 44452 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 16266 | /* 44456 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 16267 | /* 44460 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 16268 | /* 44464 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 16269 | /* 44468 */ // MIs[1] Operand 1 |
| 16270 | /* 44468 */ // No operand predicates |
| 16271 | /* 44468 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 16272 | /* 44470 */ // (intrinsic_wo_chain:{ *:[v2i32] } 3764:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTf2xud:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm, (imm:{ *:[i32] }):$SIMM) |
| 16273 | /* 44470 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTf2xud), |
| 16274 | /* 44473 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 16275 | /* 44475 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 16276 | /* 44477 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM |
| 16277 | /* 44480 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16278 | /* 44483 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16279 | /* 44489 */ GIR_RootConstrainSelectedInstOperands, |
| 16280 | /* 44490 */ // GIR_Coverage, 1653, |
| 16281 | /* 44490 */ GIR_EraseRootFromParent_Done, |
| 16282 | /* 44491 */ // Label 992: @44491 |
| 16283 | /* 44491 */ GIM_Try, /*On fail goto*//*Label 993*/ GIMT_Encode4(44552), // Rule ID 1654 // |
| 16284 | /* 44496 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 16285 | /* 44499 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfxs2fp), |
| 16286 | /* 44504 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 16287 | /* 44507 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 16288 | /* 44510 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 16289 | /* 44513 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 16290 | /* 44517 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 16291 | /* 44521 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 16292 | /* 44525 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 16293 | /* 44529 */ // MIs[1] Operand 1 |
| 16294 | /* 44529 */ // No operand predicates |
| 16295 | /* 44529 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 16296 | /* 44531 */ // (intrinsic_wo_chain:{ *:[v2f32] } 3766:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTxs2fd:{ *:[v2f32] } DPR:{ *:[v2i32] }:$Vm, (imm:{ *:[i32] }):$SIMM) |
| 16297 | /* 44531 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTxs2fd), |
| 16298 | /* 44534 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 16299 | /* 44536 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 16300 | /* 44538 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM |
| 16301 | /* 44541 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16302 | /* 44544 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16303 | /* 44550 */ GIR_RootConstrainSelectedInstOperands, |
| 16304 | /* 44551 */ // GIR_Coverage, 1654, |
| 16305 | /* 44551 */ GIR_EraseRootFromParent_Done, |
| 16306 | /* 44552 */ // Label 993: @44552 |
| 16307 | /* 44552 */ GIM_Try, /*On fail goto*//*Label 994*/ GIMT_Encode4(44613), // Rule ID 1655 // |
| 16308 | /* 44557 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 16309 | /* 44560 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfxu2fp), |
| 16310 | /* 44565 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 16311 | /* 44568 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 16312 | /* 44571 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 16313 | /* 44574 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 16314 | /* 44578 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 16315 | /* 44582 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 16316 | /* 44586 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 16317 | /* 44590 */ // MIs[1] Operand 1 |
| 16318 | /* 44590 */ // No operand predicates |
| 16319 | /* 44590 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 16320 | /* 44592 */ // (intrinsic_wo_chain:{ *:[v2f32] } 3767:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTxu2fd:{ *:[v2f32] } DPR:{ *:[v2i32] }:$Vm, (imm:{ *:[i32] }):$SIMM) |
| 16321 | /* 44592 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTxu2fd), |
| 16322 | /* 44595 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 16323 | /* 44597 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 16324 | /* 44599 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM |
| 16325 | /* 44602 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16326 | /* 44605 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16327 | /* 44611 */ GIR_RootConstrainSelectedInstOperands, |
| 16328 | /* 44612 */ // GIR_Coverage, 1655, |
| 16329 | /* 44612 */ GIR_EraseRootFromParent_Done, |
| 16330 | /* 44613 */ // Label 994: @44613 |
| 16331 | /* 44613 */ GIM_Try, /*On fail goto*//*Label 995*/ GIMT_Encode4(44674), // Rule ID 1656 // |
| 16332 | /* 44618 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 16333 | /* 44621 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfp2fxs), |
| 16334 | /* 44626 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 16335 | /* 44629 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 16336 | /* 44632 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 16337 | /* 44635 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 16338 | /* 44639 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 16339 | /* 44643 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 16340 | /* 44647 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 16341 | /* 44651 */ // MIs[1] Operand 1 |
| 16342 | /* 44651 */ // No operand predicates |
| 16343 | /* 44651 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 16344 | /* 44653 */ // (intrinsic_wo_chain:{ *:[v4i16] } 3763:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTh2xsd:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm, (imm:{ *:[i32] }):$SIMM) |
| 16345 | /* 44653 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTh2xsd), |
| 16346 | /* 44656 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 16347 | /* 44658 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 16348 | /* 44660 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM |
| 16349 | /* 44663 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16350 | /* 44666 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16351 | /* 44672 */ GIR_RootConstrainSelectedInstOperands, |
| 16352 | /* 44673 */ // GIR_Coverage, 1656, |
| 16353 | /* 44673 */ GIR_EraseRootFromParent_Done, |
| 16354 | /* 44674 */ // Label 995: @44674 |
| 16355 | /* 44674 */ GIM_Try, /*On fail goto*//*Label 996*/ GIMT_Encode4(44735), // Rule ID 1657 // |
| 16356 | /* 44679 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 16357 | /* 44682 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfp2fxu), |
| 16358 | /* 44687 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 16359 | /* 44690 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 16360 | /* 44693 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 16361 | /* 44696 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 16362 | /* 44700 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 16363 | /* 44704 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 16364 | /* 44708 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 16365 | /* 44712 */ // MIs[1] Operand 1 |
| 16366 | /* 44712 */ // No operand predicates |
| 16367 | /* 44712 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 16368 | /* 44714 */ // (intrinsic_wo_chain:{ *:[v4i16] } 3764:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTh2xud:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm, (imm:{ *:[i32] }):$SIMM) |
| 16369 | /* 44714 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTh2xud), |
| 16370 | /* 44717 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 16371 | /* 44719 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 16372 | /* 44721 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM |
| 16373 | /* 44724 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16374 | /* 44727 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16375 | /* 44733 */ GIR_RootConstrainSelectedInstOperands, |
| 16376 | /* 44734 */ // GIR_Coverage, 1657, |
| 16377 | /* 44734 */ GIR_EraseRootFromParent_Done, |
| 16378 | /* 44735 */ // Label 996: @44735 |
| 16379 | /* 44735 */ GIM_Try, /*On fail goto*//*Label 997*/ GIMT_Encode4(44796), // Rule ID 1658 // |
| 16380 | /* 44740 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 16381 | /* 44743 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfxs2fp), |
| 16382 | /* 44748 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 16383 | /* 44751 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 16384 | /* 44754 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 16385 | /* 44757 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 16386 | /* 44761 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 16387 | /* 44765 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 16388 | /* 44769 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 16389 | /* 44773 */ // MIs[1] Operand 1 |
| 16390 | /* 44773 */ // No operand predicates |
| 16391 | /* 44773 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 16392 | /* 44775 */ // (intrinsic_wo_chain:{ *:[v4f16] } 3766:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTxs2hd:{ *:[v4f16] } DPR:{ *:[v4i16] }:$Vm, (imm:{ *:[i32] }):$SIMM) |
| 16393 | /* 44775 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTxs2hd), |
| 16394 | /* 44778 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 16395 | /* 44780 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 16396 | /* 44782 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM |
| 16397 | /* 44785 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16398 | /* 44788 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16399 | /* 44794 */ GIR_RootConstrainSelectedInstOperands, |
| 16400 | /* 44795 */ // GIR_Coverage, 1658, |
| 16401 | /* 44795 */ GIR_EraseRootFromParent_Done, |
| 16402 | /* 44796 */ // Label 997: @44796 |
| 16403 | /* 44796 */ GIM_Try, /*On fail goto*//*Label 998*/ GIMT_Encode4(44857), // Rule ID 1659 // |
| 16404 | /* 44801 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 16405 | /* 44804 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfxu2fp), |
| 16406 | /* 44809 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 16407 | /* 44812 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 16408 | /* 44815 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 16409 | /* 44818 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 16410 | /* 44822 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 16411 | /* 44826 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 16412 | /* 44830 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 16413 | /* 44834 */ // MIs[1] Operand 1 |
| 16414 | /* 44834 */ // No operand predicates |
| 16415 | /* 44834 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 16416 | /* 44836 */ // (intrinsic_wo_chain:{ *:[v4f16] } 3767:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTxu2hd:{ *:[v4f16] } DPR:{ *:[v4i16] }:$Vm, (imm:{ *:[i32] }):$SIMM) |
| 16417 | /* 44836 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTxu2hd), |
| 16418 | /* 44839 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 16419 | /* 44841 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 16420 | /* 44843 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM |
| 16421 | /* 44846 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16422 | /* 44849 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16423 | /* 44855 */ GIR_RootConstrainSelectedInstOperands, |
| 16424 | /* 44856 */ // GIR_Coverage, 1659, |
| 16425 | /* 44856 */ GIR_EraseRootFromParent_Done, |
| 16426 | /* 44857 */ // Label 998: @44857 |
| 16427 | /* 44857 */ GIM_Try, /*On fail goto*//*Label 999*/ GIMT_Encode4(44918), // Rule ID 1660 // |
| 16428 | /* 44862 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 16429 | /* 44865 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfp2fxs), |
| 16430 | /* 44870 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 16431 | /* 44873 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 16432 | /* 44876 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 16433 | /* 44879 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 16434 | /* 44883 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 16435 | /* 44887 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 16436 | /* 44891 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 16437 | /* 44895 */ // MIs[1] Operand 1 |
| 16438 | /* 44895 */ // No operand predicates |
| 16439 | /* 44895 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 16440 | /* 44897 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3763:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTf2xsq:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm, (imm:{ *:[i32] }):$SIMM) |
| 16441 | /* 44897 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTf2xsq), |
| 16442 | /* 44900 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 16443 | /* 44902 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 16444 | /* 44904 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM |
| 16445 | /* 44907 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16446 | /* 44910 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16447 | /* 44916 */ GIR_RootConstrainSelectedInstOperands, |
| 16448 | /* 44917 */ // GIR_Coverage, 1660, |
| 16449 | /* 44917 */ GIR_EraseRootFromParent_Done, |
| 16450 | /* 44918 */ // Label 999: @44918 |
| 16451 | /* 44918 */ GIM_Try, /*On fail goto*//*Label 1000*/ GIMT_Encode4(44979), // Rule ID 1661 // |
| 16452 | /* 44923 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 16453 | /* 44926 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfp2fxu), |
| 16454 | /* 44931 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 16455 | /* 44934 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 16456 | /* 44937 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 16457 | /* 44940 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 16458 | /* 44944 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 16459 | /* 44948 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 16460 | /* 44952 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 16461 | /* 44956 */ // MIs[1] Operand 1 |
| 16462 | /* 44956 */ // No operand predicates |
| 16463 | /* 44956 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 16464 | /* 44958 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3764:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTf2xuq:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm, (imm:{ *:[i32] }):$SIMM) |
| 16465 | /* 44958 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTf2xuq), |
| 16466 | /* 44961 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 16467 | /* 44963 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 16468 | /* 44965 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM |
| 16469 | /* 44968 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16470 | /* 44971 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16471 | /* 44977 */ GIR_RootConstrainSelectedInstOperands, |
| 16472 | /* 44978 */ // GIR_Coverage, 1661, |
| 16473 | /* 44978 */ GIR_EraseRootFromParent_Done, |
| 16474 | /* 44979 */ // Label 1000: @44979 |
| 16475 | /* 44979 */ GIM_Try, /*On fail goto*//*Label 1001*/ GIMT_Encode4(45040), // Rule ID 1662 // |
| 16476 | /* 44984 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 16477 | /* 44987 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfxs2fp), |
| 16478 | /* 44992 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 16479 | /* 44995 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 16480 | /* 44998 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 16481 | /* 45001 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 16482 | /* 45005 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 16483 | /* 45009 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 16484 | /* 45013 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 16485 | /* 45017 */ // MIs[1] Operand 1 |
| 16486 | /* 45017 */ // No operand predicates |
| 16487 | /* 45017 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 16488 | /* 45019 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3766:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTxs2fq:{ *:[v4f32] } QPR:{ *:[v4i32] }:$Vm, (imm:{ *:[i32] }):$SIMM) |
| 16489 | /* 45019 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTxs2fq), |
| 16490 | /* 45022 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 16491 | /* 45024 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 16492 | /* 45026 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM |
| 16493 | /* 45029 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16494 | /* 45032 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16495 | /* 45038 */ GIR_RootConstrainSelectedInstOperands, |
| 16496 | /* 45039 */ // GIR_Coverage, 1662, |
| 16497 | /* 45039 */ GIR_EraseRootFromParent_Done, |
| 16498 | /* 45040 */ // Label 1001: @45040 |
| 16499 | /* 45040 */ GIM_Try, /*On fail goto*//*Label 1002*/ GIMT_Encode4(45101), // Rule ID 1663 // |
| 16500 | /* 45045 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 16501 | /* 45048 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfxu2fp), |
| 16502 | /* 45053 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 16503 | /* 45056 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 16504 | /* 45059 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 16505 | /* 45062 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 16506 | /* 45066 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 16507 | /* 45070 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 16508 | /* 45074 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 16509 | /* 45078 */ // MIs[1] Operand 1 |
| 16510 | /* 45078 */ // No operand predicates |
| 16511 | /* 45078 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 16512 | /* 45080 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3767:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTxu2fq:{ *:[v4f32] } QPR:{ *:[v4i32] }:$Vm, (imm:{ *:[i32] }):$SIMM) |
| 16513 | /* 45080 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTxu2fq), |
| 16514 | /* 45083 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 16515 | /* 45085 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 16516 | /* 45087 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM |
| 16517 | /* 45090 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16518 | /* 45093 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16519 | /* 45099 */ GIR_RootConstrainSelectedInstOperands, |
| 16520 | /* 45100 */ // GIR_Coverage, 1663, |
| 16521 | /* 45100 */ GIR_EraseRootFromParent_Done, |
| 16522 | /* 45101 */ // Label 1002: @45101 |
| 16523 | /* 45101 */ GIM_Try, /*On fail goto*//*Label 1003*/ GIMT_Encode4(45162), // Rule ID 1664 // |
| 16524 | /* 45106 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 16525 | /* 45109 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfp2fxs), |
| 16526 | /* 45114 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 16527 | /* 45117 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 16528 | /* 45120 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 16529 | /* 45123 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 16530 | /* 45127 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 16531 | /* 45131 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 16532 | /* 45135 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 16533 | /* 45139 */ // MIs[1] Operand 1 |
| 16534 | /* 45139 */ // No operand predicates |
| 16535 | /* 45139 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 16536 | /* 45141 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3763:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTh2xsq:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm, (imm:{ *:[i32] }):$SIMM) |
| 16537 | /* 45141 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTh2xsq), |
| 16538 | /* 45144 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 16539 | /* 45146 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 16540 | /* 45148 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM |
| 16541 | /* 45151 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16542 | /* 45154 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16543 | /* 45160 */ GIR_RootConstrainSelectedInstOperands, |
| 16544 | /* 45161 */ // GIR_Coverage, 1664, |
| 16545 | /* 45161 */ GIR_EraseRootFromParent_Done, |
| 16546 | /* 45162 */ // Label 1003: @45162 |
| 16547 | /* 45162 */ GIM_Try, /*On fail goto*//*Label 1004*/ GIMT_Encode4(45223), // Rule ID 1665 // |
| 16548 | /* 45167 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 16549 | /* 45170 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfp2fxu), |
| 16550 | /* 45175 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 16551 | /* 45178 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 16552 | /* 45181 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 16553 | /* 45184 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 16554 | /* 45188 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 16555 | /* 45192 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 16556 | /* 45196 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 16557 | /* 45200 */ // MIs[1] Operand 1 |
| 16558 | /* 45200 */ // No operand predicates |
| 16559 | /* 45200 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 16560 | /* 45202 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3764:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTh2xuq:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm, (imm:{ *:[i32] }):$SIMM) |
| 16561 | /* 45202 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTh2xuq), |
| 16562 | /* 45205 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 16563 | /* 45207 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 16564 | /* 45209 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM |
| 16565 | /* 45212 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16566 | /* 45215 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16567 | /* 45221 */ GIR_RootConstrainSelectedInstOperands, |
| 16568 | /* 45222 */ // GIR_Coverage, 1665, |
| 16569 | /* 45222 */ GIR_EraseRootFromParent_Done, |
| 16570 | /* 45223 */ // Label 1004: @45223 |
| 16571 | /* 45223 */ GIM_Try, /*On fail goto*//*Label 1005*/ GIMT_Encode4(45284), // Rule ID 1666 // |
| 16572 | /* 45228 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 16573 | /* 45231 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfxs2fp), |
| 16574 | /* 45236 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 16575 | /* 45239 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 16576 | /* 45242 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 16577 | /* 45245 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 16578 | /* 45249 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 16579 | /* 45253 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 16580 | /* 45257 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 16581 | /* 45261 */ // MIs[1] Operand 1 |
| 16582 | /* 45261 */ // No operand predicates |
| 16583 | /* 45261 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 16584 | /* 45263 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3766:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTxs2hq:{ *:[v8f16] } QPR:{ *:[v8i16] }:$Vm, (imm:{ *:[i32] }):$SIMM) |
| 16585 | /* 45263 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTxs2hq), |
| 16586 | /* 45266 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 16587 | /* 45268 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 16588 | /* 45270 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM |
| 16589 | /* 45273 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16590 | /* 45276 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16591 | /* 45282 */ GIR_RootConstrainSelectedInstOperands, |
| 16592 | /* 45283 */ // GIR_Coverage, 1666, |
| 16593 | /* 45283 */ GIR_EraseRootFromParent_Done, |
| 16594 | /* 45284 */ // Label 1005: @45284 |
| 16595 | /* 45284 */ GIM_Try, /*On fail goto*//*Label 1006*/ GIMT_Encode4(45345), // Rule ID 1667 // |
| 16596 | /* 45289 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 16597 | /* 45292 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfxu2fp), |
| 16598 | /* 45297 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 16599 | /* 45300 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 16600 | /* 45303 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 16601 | /* 45306 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 16602 | /* 45310 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 16603 | /* 45314 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 16604 | /* 45318 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 16605 | /* 45322 */ // MIs[1] Operand 1 |
| 16606 | /* 45322 */ // No operand predicates |
| 16607 | /* 45322 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 16608 | /* 45324 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3767:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTxu2hq:{ *:[v8f16] } QPR:{ *:[v8i16] }:$Vm, (imm:{ *:[i32] }):$SIMM) |
| 16609 | /* 45324 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTxu2hq), |
| 16610 | /* 45327 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 16611 | /* 45329 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 16612 | /* 45331 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM |
| 16613 | /* 45334 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16614 | /* 45337 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16615 | /* 45343 */ GIR_RootConstrainSelectedInstOperands, |
| 16616 | /* 45344 */ // GIR_Coverage, 1667, |
| 16617 | /* 45344 */ GIR_EraseRootFromParent_Done, |
| 16618 | /* 45345 */ // Label 1006: @45345 |
| 16619 | /* 45345 */ GIM_Try, /*On fail goto*//*Label 1007*/ GIMT_Encode4(45406), // Rule ID 1725 // |
| 16620 | /* 45350 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_HasV8_1MMainline), |
| 16621 | /* 45353 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_sqshl), |
| 16622 | /* 45358 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 16623 | /* 45361 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16624 | /* 45364 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 16625 | /* 45367 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16626 | /* 45371 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16627 | /* 45375 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 16628 | /* 45379 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 16629 | /* 45383 */ // MIs[1] Operand 1 |
| 16630 | /* 45383 */ // No operand predicates |
| 16631 | /* 45383 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 16632 | /* 45385 */ // (intrinsic_wo_chain:{ *:[i32] } 3591:{ *:[iPTR] }, rGPR:{ *:[i32] }:$RdaSrc, (imm:{ *:[i32] }):$imm) => (MVE_SQSHL:{ *:[i32] } rGPR:{ *:[i32] }:$RdaSrc, (imm:{ *:[i32] }):$imm) |
| 16633 | /* 45385 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_SQSHL), |
| 16634 | /* 45388 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 16635 | /* 45390 */ GIR_RootToRootCopy, /*OpIdx*/2, // RdaSrc |
| 16636 | /* 45392 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 16637 | /* 45395 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16638 | /* 45398 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16639 | /* 45404 */ GIR_RootConstrainSelectedInstOperands, |
| 16640 | /* 45405 */ // GIR_Coverage, 1725, |
| 16641 | /* 45405 */ GIR_EraseRootFromParent_Done, |
| 16642 | /* 45406 */ // Label 1007: @45406 |
| 16643 | /* 45406 */ GIM_Try, /*On fail goto*//*Label 1008*/ GIMT_Encode4(45467), // Rule ID 1726 // |
| 16644 | /* 45411 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_HasV8_1MMainline), |
| 16645 | /* 45414 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_srshr), |
| 16646 | /* 45419 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 16647 | /* 45422 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16648 | /* 45425 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 16649 | /* 45428 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16650 | /* 45432 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16651 | /* 45436 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 16652 | /* 45440 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 16653 | /* 45444 */ // MIs[1] Operand 1 |
| 16654 | /* 45444 */ // No operand predicates |
| 16655 | /* 45444 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 16656 | /* 45446 */ // (intrinsic_wo_chain:{ *:[i32] } 3593:{ *:[iPTR] }, rGPR:{ *:[i32] }:$RdaSrc, (imm:{ *:[i32] }):$imm) => (MVE_SRSHR:{ *:[i32] } rGPR:{ *:[i32] }:$RdaSrc, (imm:{ *:[i32] }):$imm) |
| 16657 | /* 45446 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_SRSHR), |
| 16658 | /* 45449 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 16659 | /* 45451 */ GIR_RootToRootCopy, /*OpIdx*/2, // RdaSrc |
| 16660 | /* 45453 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 16661 | /* 45456 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16662 | /* 45459 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16663 | /* 45465 */ GIR_RootConstrainSelectedInstOperands, |
| 16664 | /* 45466 */ // GIR_Coverage, 1726, |
| 16665 | /* 45466 */ GIR_EraseRootFromParent_Done, |
| 16666 | /* 45467 */ // Label 1008: @45467 |
| 16667 | /* 45467 */ GIM_Try, /*On fail goto*//*Label 1009*/ GIMT_Encode4(45528), // Rule ID 1727 // |
| 16668 | /* 45472 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_HasV8_1MMainline), |
| 16669 | /* 45475 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_uqshl), |
| 16670 | /* 45480 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 16671 | /* 45483 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16672 | /* 45486 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 16673 | /* 45489 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16674 | /* 45493 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16675 | /* 45497 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 16676 | /* 45501 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 16677 | /* 45505 */ // MIs[1] Operand 1 |
| 16678 | /* 45505 */ // No operand predicates |
| 16679 | /* 45505 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 16680 | /* 45507 */ // (intrinsic_wo_chain:{ *:[i32] } 3598:{ *:[iPTR] }, rGPR:{ *:[i32] }:$RdaSrc, (imm:{ *:[i32] }):$imm) => (MVE_UQSHL:{ *:[i32] } rGPR:{ *:[i32] }:$RdaSrc, (imm:{ *:[i32] }):$imm) |
| 16681 | /* 45507 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_UQSHL), |
| 16682 | /* 45510 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 16683 | /* 45512 */ GIR_RootToRootCopy, /*OpIdx*/2, // RdaSrc |
| 16684 | /* 45514 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 16685 | /* 45517 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16686 | /* 45520 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16687 | /* 45526 */ GIR_RootConstrainSelectedInstOperands, |
| 16688 | /* 45527 */ // GIR_Coverage, 1727, |
| 16689 | /* 45527 */ GIR_EraseRootFromParent_Done, |
| 16690 | /* 45528 */ // Label 1009: @45528 |
| 16691 | /* 45528 */ GIM_Try, /*On fail goto*//*Label 1010*/ GIMT_Encode4(45589), // Rule ID 1728 // |
| 16692 | /* 45533 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_HasV8_1MMainline), |
| 16693 | /* 45536 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_urshr), |
| 16694 | /* 45541 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 16695 | /* 45544 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16696 | /* 45547 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 16697 | /* 45550 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16698 | /* 45554 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16699 | /* 45558 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 16700 | /* 45562 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 16701 | /* 45566 */ // MIs[1] Operand 1 |
| 16702 | /* 45566 */ // No operand predicates |
| 16703 | /* 45566 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 16704 | /* 45568 */ // (intrinsic_wo_chain:{ *:[i32] } 3600:{ *:[iPTR] }, rGPR:{ *:[i32] }:$RdaSrc, (imm:{ *:[i32] }):$imm) => (MVE_URSHR:{ *:[i32] } rGPR:{ *:[i32] }:$RdaSrc, (imm:{ *:[i32] }):$imm) |
| 16705 | /* 45568 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_URSHR), |
| 16706 | /* 45571 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 16707 | /* 45573 */ GIR_RootToRootCopy, /*OpIdx*/2, // RdaSrc |
| 16708 | /* 45575 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 16709 | /* 45578 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16710 | /* 45581 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16711 | /* 45587 */ GIR_RootConstrainSelectedInstOperands, |
| 16712 | /* 45588 */ // GIR_Coverage, 1728, |
| 16713 | /* 45588 */ GIR_EraseRootFromParent_Done, |
| 16714 | /* 45589 */ // Label 1010: @45589 |
| 16715 | /* 45589 */ GIM_Try, /*On fail goto*//*Label 1011*/ GIMT_Encode4(45643), // Rule ID 105 // |
| 16716 | /* 45594 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 16717 | /* 45597 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd8), |
| 16718 | /* 45602 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 16719 | /* 45605 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16720 | /* 45608 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 16721 | /* 45611 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16722 | /* 45615 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16723 | /* 45619 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16724 | /* 45623 */ // (intrinsic_wo_chain:{ *:[i32] } 3867:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (QADD8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 16725 | /* 45623 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QADD8), |
| 16726 | /* 45626 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 16727 | /* 45628 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 16728 | /* 45630 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 16729 | /* 45632 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16730 | /* 45635 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16731 | /* 45641 */ GIR_RootConstrainSelectedInstOperands, |
| 16732 | /* 45642 */ // GIR_Coverage, 105, |
| 16733 | /* 45642 */ GIR_EraseRootFromParent_Done, |
| 16734 | /* 45643 */ // Label 1011: @45643 |
| 16735 | /* 45643 */ GIM_Try, /*On fail goto*//*Label 1012*/ GIMT_Encode4(45697), // Rule ID 106 // |
| 16736 | /* 45648 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 16737 | /* 45651 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd16), |
| 16738 | /* 45656 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 16739 | /* 45659 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16740 | /* 45662 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 16741 | /* 45665 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16742 | /* 45669 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16743 | /* 45673 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16744 | /* 45677 */ // (intrinsic_wo_chain:{ *:[i32] } 3866:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (QADD16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 16745 | /* 45677 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QADD16), |
| 16746 | /* 45680 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 16747 | /* 45682 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 16748 | /* 45684 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 16749 | /* 45686 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16750 | /* 45689 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16751 | /* 45695 */ GIR_RootConstrainSelectedInstOperands, |
| 16752 | /* 45696 */ // GIR_Coverage, 106, |
| 16753 | /* 45696 */ GIR_EraseRootFromParent_Done, |
| 16754 | /* 45697 */ // Label 1012: @45697 |
| 16755 | /* 45697 */ GIM_Try, /*On fail goto*//*Label 1013*/ GIMT_Encode4(45751), // Rule ID 107 // |
| 16756 | /* 45702 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 16757 | /* 45705 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qsub16), |
| 16758 | /* 45710 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 16759 | /* 45713 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16760 | /* 45716 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 16761 | /* 45719 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16762 | /* 45723 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16763 | /* 45727 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16764 | /* 45731 */ // (intrinsic_wo_chain:{ *:[i32] } 3871:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (QSUB16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 16765 | /* 45731 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QSUB16), |
| 16766 | /* 45734 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 16767 | /* 45736 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 16768 | /* 45738 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 16769 | /* 45740 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16770 | /* 45743 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16771 | /* 45749 */ GIR_RootConstrainSelectedInstOperands, |
| 16772 | /* 45750 */ // GIR_Coverage, 107, |
| 16773 | /* 45750 */ GIR_EraseRootFromParent_Done, |
| 16774 | /* 45751 */ // Label 1013: @45751 |
| 16775 | /* 45751 */ GIM_Try, /*On fail goto*//*Label 1014*/ GIMT_Encode4(45805), // Rule ID 108 // |
| 16776 | /* 45756 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 16777 | /* 45759 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qsub8), |
| 16778 | /* 45764 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 16779 | /* 45767 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16780 | /* 45770 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 16781 | /* 45773 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16782 | /* 45777 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16783 | /* 45781 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16784 | /* 45785 */ // (intrinsic_wo_chain:{ *:[i32] } 3872:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (QSUB8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 16785 | /* 45785 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QSUB8), |
| 16786 | /* 45788 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 16787 | /* 45790 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 16788 | /* 45792 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 16789 | /* 45794 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16790 | /* 45797 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16791 | /* 45803 */ GIR_RootConstrainSelectedInstOperands, |
| 16792 | /* 45804 */ // GIR_Coverage, 108, |
| 16793 | /* 45804 */ GIR_EraseRootFromParent_Done, |
| 16794 | /* 45805 */ // Label 1014: @45805 |
| 16795 | /* 45805 */ GIM_Try, /*On fail goto*//*Label 1015*/ GIMT_Encode4(45859), // Rule ID 111 // |
| 16796 | /* 45810 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 16797 | /* 45813 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qsub), |
| 16798 | /* 45818 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 16799 | /* 45821 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16800 | /* 45824 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 16801 | /* 45827 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16802 | /* 45831 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16803 | /* 45835 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16804 | /* 45839 */ // (intrinsic_wo_chain:{ *:[i32] } 3870:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn) => (QSUB:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn) |
| 16805 | /* 45839 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QSUB), |
| 16806 | /* 45842 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 16807 | /* 45844 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 16808 | /* 45846 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rn |
| 16809 | /* 45848 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16810 | /* 45851 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16811 | /* 45857 */ GIR_RootConstrainSelectedInstOperands, |
| 16812 | /* 45858 */ // GIR_Coverage, 111, |
| 16813 | /* 45858 */ GIR_EraseRootFromParent_Done, |
| 16814 | /* 45859 */ // Label 1015: @45859 |
| 16815 | /* 45859 */ GIM_Try, /*On fail goto*//*Label 1016*/ GIMT_Encode4(45913), // Rule ID 112 // |
| 16816 | /* 45864 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 16817 | /* 45867 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd), |
| 16818 | /* 45872 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 16819 | /* 45875 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16820 | /* 45878 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 16821 | /* 45881 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16822 | /* 45885 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16823 | /* 45889 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16824 | /* 45893 */ // (intrinsic_wo_chain:{ *:[i32] } 3865:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn) => (QADD:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn) |
| 16825 | /* 45893 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QADD), |
| 16826 | /* 45896 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 16827 | /* 45898 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 16828 | /* 45900 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rn |
| 16829 | /* 45902 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16830 | /* 45905 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16831 | /* 45911 */ GIR_RootConstrainSelectedInstOperands, |
| 16832 | /* 45912 */ // GIR_Coverage, 112, |
| 16833 | /* 45912 */ GIR_EraseRootFromParent_Done, |
| 16834 | /* 45913 */ // Label 1016: @45913 |
| 16835 | /* 45913 */ GIM_Try, /*On fail goto*//*Label 1017*/ GIMT_Encode4(45967), // Rule ID 113 // |
| 16836 | /* 45918 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 16837 | /* 45921 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqadd16), |
| 16838 | /* 45926 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 16839 | /* 45929 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16840 | /* 45932 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 16841 | /* 45935 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16842 | /* 45939 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16843 | /* 45943 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16844 | /* 45947 */ // (intrinsic_wo_chain:{ *:[i32] } 3934:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UQADD16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 16845 | /* 45947 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UQADD16), |
| 16846 | /* 45950 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 16847 | /* 45952 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 16848 | /* 45954 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 16849 | /* 45956 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16850 | /* 45959 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16851 | /* 45965 */ GIR_RootConstrainSelectedInstOperands, |
| 16852 | /* 45966 */ // GIR_Coverage, 113, |
| 16853 | /* 45966 */ GIR_EraseRootFromParent_Done, |
| 16854 | /* 45967 */ // Label 1017: @45967 |
| 16855 | /* 45967 */ GIM_Try, /*On fail goto*//*Label 1018*/ GIMT_Encode4(46021), // Rule ID 114 // |
| 16856 | /* 45972 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 16857 | /* 45975 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqadd8), |
| 16858 | /* 45980 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 16859 | /* 45983 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16860 | /* 45986 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 16861 | /* 45989 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16862 | /* 45993 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16863 | /* 45997 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16864 | /* 46001 */ // (intrinsic_wo_chain:{ *:[i32] } 3935:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UQADD8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 16865 | /* 46001 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UQADD8), |
| 16866 | /* 46004 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 16867 | /* 46006 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 16868 | /* 46008 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 16869 | /* 46010 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16870 | /* 46013 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16871 | /* 46019 */ GIR_RootConstrainSelectedInstOperands, |
| 16872 | /* 46020 */ // GIR_Coverage, 114, |
| 16873 | /* 46020 */ GIR_EraseRootFromParent_Done, |
| 16874 | /* 46021 */ // Label 1018: @46021 |
| 16875 | /* 46021 */ GIM_Try, /*On fail goto*//*Label 1019*/ GIMT_Encode4(46075), // Rule ID 115 // |
| 16876 | /* 46026 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 16877 | /* 46029 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqsub16), |
| 16878 | /* 46034 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 16879 | /* 46037 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16880 | /* 46040 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 16881 | /* 46043 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16882 | /* 46047 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16883 | /* 46051 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16884 | /* 46055 */ // (intrinsic_wo_chain:{ *:[i32] } 3938:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UQSUB16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 16885 | /* 46055 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UQSUB16), |
| 16886 | /* 46058 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 16887 | /* 46060 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 16888 | /* 46062 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 16889 | /* 46064 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16890 | /* 46067 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16891 | /* 46073 */ GIR_RootConstrainSelectedInstOperands, |
| 16892 | /* 46074 */ // GIR_Coverage, 115, |
| 16893 | /* 46074 */ GIR_EraseRootFromParent_Done, |
| 16894 | /* 46075 */ // Label 1019: @46075 |
| 16895 | /* 46075 */ GIM_Try, /*On fail goto*//*Label 1020*/ GIMT_Encode4(46129), // Rule ID 116 // |
| 16896 | /* 46080 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 16897 | /* 46083 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqsub8), |
| 16898 | /* 46088 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 16899 | /* 46091 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16900 | /* 46094 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 16901 | /* 46097 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16902 | /* 46101 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16903 | /* 46105 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16904 | /* 46109 */ // (intrinsic_wo_chain:{ *:[i32] } 3939:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UQSUB8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 16905 | /* 46109 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UQSUB8), |
| 16906 | /* 46112 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 16907 | /* 46114 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 16908 | /* 46116 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 16909 | /* 46118 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16910 | /* 46121 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16911 | /* 46127 */ GIR_RootConstrainSelectedInstOperands, |
| 16912 | /* 46128 */ // GIR_Coverage, 116, |
| 16913 | /* 46128 */ GIR_EraseRootFromParent_Done, |
| 16914 | /* 46129 */ // Label 1020: @46129 |
| 16915 | /* 46129 */ GIM_Try, /*On fail goto*//*Label 1021*/ GIMT_Encode4(46183), // Rule ID 117 // |
| 16916 | /* 46134 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 16917 | /* 46137 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qasx), |
| 16918 | /* 46142 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 16919 | /* 46145 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16920 | /* 46148 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 16921 | /* 46151 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16922 | /* 46155 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16923 | /* 46159 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16924 | /* 46163 */ // (intrinsic_wo_chain:{ *:[i32] } 3868:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (QASX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 16925 | /* 46163 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QASX), |
| 16926 | /* 46166 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 16927 | /* 46168 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 16928 | /* 46170 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 16929 | /* 46172 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16930 | /* 46175 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16931 | /* 46181 */ GIR_RootConstrainSelectedInstOperands, |
| 16932 | /* 46182 */ // GIR_Coverage, 117, |
| 16933 | /* 46182 */ GIR_EraseRootFromParent_Done, |
| 16934 | /* 46183 */ // Label 1021: @46183 |
| 16935 | /* 46183 */ GIM_Try, /*On fail goto*//*Label 1022*/ GIMT_Encode4(46237), // Rule ID 118 // |
| 16936 | /* 46188 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 16937 | /* 46191 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qsax), |
| 16938 | /* 46196 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 16939 | /* 46199 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16940 | /* 46202 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 16941 | /* 46205 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16942 | /* 46209 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16943 | /* 46213 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16944 | /* 46217 */ // (intrinsic_wo_chain:{ *:[i32] } 3869:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (QSAX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 16945 | /* 46217 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QSAX), |
| 16946 | /* 46220 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 16947 | /* 46222 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 16948 | /* 46224 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 16949 | /* 46226 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16950 | /* 46229 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16951 | /* 46235 */ GIR_RootConstrainSelectedInstOperands, |
| 16952 | /* 46236 */ // GIR_Coverage, 118, |
| 16953 | /* 46236 */ GIR_EraseRootFromParent_Done, |
| 16954 | /* 46237 */ // Label 1022: @46237 |
| 16955 | /* 46237 */ GIM_Try, /*On fail goto*//*Label 1023*/ GIMT_Encode4(46291), // Rule ID 119 // |
| 16956 | /* 46242 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 16957 | /* 46245 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqasx), |
| 16958 | /* 46250 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 16959 | /* 46253 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16960 | /* 46256 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 16961 | /* 46259 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16962 | /* 46263 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16963 | /* 46267 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16964 | /* 46271 */ // (intrinsic_wo_chain:{ *:[i32] } 3936:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UQASX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 16965 | /* 46271 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UQASX), |
| 16966 | /* 46274 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 16967 | /* 46276 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 16968 | /* 46278 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 16969 | /* 46280 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16970 | /* 46283 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16971 | /* 46289 */ GIR_RootConstrainSelectedInstOperands, |
| 16972 | /* 46290 */ // GIR_Coverage, 119, |
| 16973 | /* 46290 */ GIR_EraseRootFromParent_Done, |
| 16974 | /* 46291 */ // Label 1023: @46291 |
| 16975 | /* 46291 */ GIM_Try, /*On fail goto*//*Label 1024*/ GIMT_Encode4(46345), // Rule ID 120 // |
| 16976 | /* 46296 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 16977 | /* 46299 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqsax), |
| 16978 | /* 46304 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 16979 | /* 46307 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16980 | /* 46310 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 16981 | /* 46313 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16982 | /* 46317 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16983 | /* 46321 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16984 | /* 46325 */ // (intrinsic_wo_chain:{ *:[i32] } 3937:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UQSAX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 16985 | /* 46325 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UQSAX), |
| 16986 | /* 46328 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 16987 | /* 46330 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 16988 | /* 46332 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 16989 | /* 46334 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16990 | /* 46337 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16991 | /* 46343 */ GIR_RootConstrainSelectedInstOperands, |
| 16992 | /* 46344 */ // GIR_Coverage, 120, |
| 16993 | /* 46344 */ GIR_EraseRootFromParent_Done, |
| 16994 | /* 46345 */ // Label 1024: @46345 |
| 16995 | /* 46345 */ GIM_Try, /*On fail goto*//*Label 1025*/ GIMT_Encode4(46399), // Rule ID 133 // |
| 16996 | /* 46350 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 16997 | /* 46353 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shasx), |
| 16998 | /* 46358 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 16999 | /* 46361 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17000 | /* 46364 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17001 | /* 46367 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17002 | /* 46371 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17003 | /* 46375 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17004 | /* 46379 */ // (intrinsic_wo_chain:{ *:[i32] } 3880:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SHASX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 17005 | /* 46379 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHASX), |
| 17006 | /* 46382 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 17007 | /* 46384 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 17008 | /* 46386 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 17009 | /* 46388 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17010 | /* 46391 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17011 | /* 46397 */ GIR_RootConstrainSelectedInstOperands, |
| 17012 | /* 46398 */ // GIR_Coverage, 133, |
| 17013 | /* 46398 */ GIR_EraseRootFromParent_Done, |
| 17014 | /* 46399 */ // Label 1025: @46399 |
| 17015 | /* 46399 */ GIM_Try, /*On fail goto*//*Label 1026*/ GIMT_Encode4(46453), // Rule ID 134 // |
| 17016 | /* 46404 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 17017 | /* 46407 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shadd16), |
| 17018 | /* 46412 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 17019 | /* 46415 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17020 | /* 46418 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17021 | /* 46421 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17022 | /* 46425 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17023 | /* 46429 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17024 | /* 46433 */ // (intrinsic_wo_chain:{ *:[i32] } 3878:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SHADD16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 17025 | /* 46433 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHADD16), |
| 17026 | /* 46436 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 17027 | /* 46438 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 17028 | /* 46440 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 17029 | /* 46442 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17030 | /* 46445 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17031 | /* 46451 */ GIR_RootConstrainSelectedInstOperands, |
| 17032 | /* 46452 */ // GIR_Coverage, 134, |
| 17033 | /* 46452 */ GIR_EraseRootFromParent_Done, |
| 17034 | /* 46453 */ // Label 1026: @46453 |
| 17035 | /* 46453 */ GIM_Try, /*On fail goto*//*Label 1027*/ GIMT_Encode4(46507), // Rule ID 135 // |
| 17036 | /* 46458 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 17037 | /* 46461 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shadd8), |
| 17038 | /* 46466 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 17039 | /* 46469 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17040 | /* 46472 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17041 | /* 46475 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17042 | /* 46479 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17043 | /* 46483 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17044 | /* 46487 */ // (intrinsic_wo_chain:{ *:[i32] } 3879:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SHADD8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 17045 | /* 46487 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHADD8), |
| 17046 | /* 46490 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 17047 | /* 46492 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 17048 | /* 46494 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 17049 | /* 46496 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17050 | /* 46499 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17051 | /* 46505 */ GIR_RootConstrainSelectedInstOperands, |
| 17052 | /* 46506 */ // GIR_Coverage, 135, |
| 17053 | /* 46506 */ GIR_EraseRootFromParent_Done, |
| 17054 | /* 46507 */ // Label 1027: @46507 |
| 17055 | /* 46507 */ GIM_Try, /*On fail goto*//*Label 1028*/ GIMT_Encode4(46561), // Rule ID 136 // |
| 17056 | /* 46512 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 17057 | /* 46515 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shsax), |
| 17058 | /* 46520 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 17059 | /* 46523 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17060 | /* 46526 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17061 | /* 46529 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17062 | /* 46533 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17063 | /* 46537 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17064 | /* 46541 */ // (intrinsic_wo_chain:{ *:[i32] } 3881:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SHSAX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 17065 | /* 46541 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHSAX), |
| 17066 | /* 46544 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 17067 | /* 46546 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 17068 | /* 46548 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 17069 | /* 46550 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17070 | /* 46553 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17071 | /* 46559 */ GIR_RootConstrainSelectedInstOperands, |
| 17072 | /* 46560 */ // GIR_Coverage, 136, |
| 17073 | /* 46560 */ GIR_EraseRootFromParent_Done, |
| 17074 | /* 46561 */ // Label 1028: @46561 |
| 17075 | /* 46561 */ GIM_Try, /*On fail goto*//*Label 1029*/ GIMT_Encode4(46615), // Rule ID 137 // |
| 17076 | /* 46566 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 17077 | /* 46569 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shsub16), |
| 17078 | /* 46574 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 17079 | /* 46577 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17080 | /* 46580 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17081 | /* 46583 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17082 | /* 46587 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17083 | /* 46591 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17084 | /* 46595 */ // (intrinsic_wo_chain:{ *:[i32] } 3882:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SHSUB16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 17085 | /* 46595 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHSUB16), |
| 17086 | /* 46598 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 17087 | /* 46600 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 17088 | /* 46602 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 17089 | /* 46604 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17090 | /* 46607 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17091 | /* 46613 */ GIR_RootConstrainSelectedInstOperands, |
| 17092 | /* 46614 */ // GIR_Coverage, 137, |
| 17093 | /* 46614 */ GIR_EraseRootFromParent_Done, |
| 17094 | /* 46615 */ // Label 1029: @46615 |
| 17095 | /* 46615 */ GIM_Try, /*On fail goto*//*Label 1030*/ GIMT_Encode4(46669), // Rule ID 138 // |
| 17096 | /* 46620 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 17097 | /* 46623 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shsub8), |
| 17098 | /* 46628 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 17099 | /* 46631 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17100 | /* 46634 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17101 | /* 46637 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17102 | /* 46641 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17103 | /* 46645 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17104 | /* 46649 */ // (intrinsic_wo_chain:{ *:[i32] } 3883:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SHSUB8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 17105 | /* 46649 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHSUB8), |
| 17106 | /* 46652 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 17107 | /* 46654 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 17108 | /* 46656 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 17109 | /* 46658 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17110 | /* 46661 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17111 | /* 46667 */ GIR_RootConstrainSelectedInstOperands, |
| 17112 | /* 46668 */ // GIR_Coverage, 138, |
| 17113 | /* 46668 */ GIR_EraseRootFromParent_Done, |
| 17114 | /* 46669 */ // Label 1030: @46669 |
| 17115 | /* 46669 */ GIM_Try, /*On fail goto*//*Label 1031*/ GIMT_Encode4(46723), // Rule ID 139 // |
| 17116 | /* 46674 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 17117 | /* 46677 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhasx), |
| 17118 | /* 46682 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 17119 | /* 46685 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17120 | /* 46688 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17121 | /* 46691 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17122 | /* 46695 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17123 | /* 46699 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17124 | /* 46703 */ // (intrinsic_wo_chain:{ *:[i32] } 3929:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UHASX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 17125 | /* 46703 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UHASX), |
| 17126 | /* 46706 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 17127 | /* 46708 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 17128 | /* 46710 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 17129 | /* 46712 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17130 | /* 46715 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17131 | /* 46721 */ GIR_RootConstrainSelectedInstOperands, |
| 17132 | /* 46722 */ // GIR_Coverage, 139, |
| 17133 | /* 46722 */ GIR_EraseRootFromParent_Done, |
| 17134 | /* 46723 */ // Label 1031: @46723 |
| 17135 | /* 46723 */ GIM_Try, /*On fail goto*//*Label 1032*/ GIMT_Encode4(46777), // Rule ID 140 // |
| 17136 | /* 46728 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 17137 | /* 46731 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhadd16), |
| 17138 | /* 46736 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 17139 | /* 46739 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17140 | /* 46742 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17141 | /* 46745 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17142 | /* 46749 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17143 | /* 46753 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17144 | /* 46757 */ // (intrinsic_wo_chain:{ *:[i32] } 3927:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UHADD16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 17145 | /* 46757 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UHADD16), |
| 17146 | /* 46760 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 17147 | /* 46762 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 17148 | /* 46764 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 17149 | /* 46766 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17150 | /* 46769 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17151 | /* 46775 */ GIR_RootConstrainSelectedInstOperands, |
| 17152 | /* 46776 */ // GIR_Coverage, 140, |
| 17153 | /* 46776 */ GIR_EraseRootFromParent_Done, |
| 17154 | /* 46777 */ // Label 1032: @46777 |
| 17155 | /* 46777 */ GIM_Try, /*On fail goto*//*Label 1033*/ GIMT_Encode4(46831), // Rule ID 141 // |
| 17156 | /* 46782 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 17157 | /* 46785 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhadd8), |
| 17158 | /* 46790 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 17159 | /* 46793 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17160 | /* 46796 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17161 | /* 46799 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17162 | /* 46803 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17163 | /* 46807 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17164 | /* 46811 */ // (intrinsic_wo_chain:{ *:[i32] } 3928:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UHADD8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 17165 | /* 46811 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UHADD8), |
| 17166 | /* 46814 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 17167 | /* 46816 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 17168 | /* 46818 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 17169 | /* 46820 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17170 | /* 46823 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17171 | /* 46829 */ GIR_RootConstrainSelectedInstOperands, |
| 17172 | /* 46830 */ // GIR_Coverage, 141, |
| 17173 | /* 46830 */ GIR_EraseRootFromParent_Done, |
| 17174 | /* 46831 */ // Label 1033: @46831 |
| 17175 | /* 46831 */ GIM_Try, /*On fail goto*//*Label 1034*/ GIMT_Encode4(46885), // Rule ID 142 // |
| 17176 | /* 46836 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 17177 | /* 46839 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhsax), |
| 17178 | /* 46844 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 17179 | /* 46847 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17180 | /* 46850 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17181 | /* 46853 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17182 | /* 46857 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17183 | /* 46861 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17184 | /* 46865 */ // (intrinsic_wo_chain:{ *:[i32] } 3930:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UHSAX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 17185 | /* 46865 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UHSAX), |
| 17186 | /* 46868 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 17187 | /* 46870 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 17188 | /* 46872 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 17189 | /* 46874 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17190 | /* 46877 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17191 | /* 46883 */ GIR_RootConstrainSelectedInstOperands, |
| 17192 | /* 46884 */ // GIR_Coverage, 142, |
| 17193 | /* 46884 */ GIR_EraseRootFromParent_Done, |
| 17194 | /* 46885 */ // Label 1034: @46885 |
| 17195 | /* 46885 */ GIM_Try, /*On fail goto*//*Label 1035*/ GIMT_Encode4(46939), // Rule ID 143 // |
| 17196 | /* 46890 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 17197 | /* 46893 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhsub16), |
| 17198 | /* 46898 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 17199 | /* 46901 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17200 | /* 46904 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17201 | /* 46907 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17202 | /* 46911 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17203 | /* 46915 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17204 | /* 46919 */ // (intrinsic_wo_chain:{ *:[i32] } 3931:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UHSUB16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 17205 | /* 46919 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UHSUB16), |
| 17206 | /* 46922 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 17207 | /* 46924 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 17208 | /* 46926 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 17209 | /* 46928 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17210 | /* 46931 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17211 | /* 46937 */ GIR_RootConstrainSelectedInstOperands, |
| 17212 | /* 46938 */ // GIR_Coverage, 143, |
| 17213 | /* 46938 */ GIR_EraseRootFromParent_Done, |
| 17214 | /* 46939 */ // Label 1035: @46939 |
| 17215 | /* 46939 */ GIM_Try, /*On fail goto*//*Label 1036*/ GIMT_Encode4(46993), // Rule ID 144 // |
| 17216 | /* 46944 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 17217 | /* 46947 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhsub8), |
| 17218 | /* 46952 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 17219 | /* 46955 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17220 | /* 46958 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17221 | /* 46961 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17222 | /* 46965 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17223 | /* 46969 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17224 | /* 46973 */ // (intrinsic_wo_chain:{ *:[i32] } 3932:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UHSUB8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 17225 | /* 46973 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UHSUB8), |
| 17226 | /* 46976 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 17227 | /* 46978 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 17228 | /* 46980 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 17229 | /* 46982 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17230 | /* 46985 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17231 | /* 46991 */ GIR_RootConstrainSelectedInstOperands, |
| 17232 | /* 46992 */ // GIR_Coverage, 144, |
| 17233 | /* 46992 */ GIR_EraseRootFromParent_Done, |
| 17234 | /* 46993 */ // Label 1036: @46993 |
| 17235 | /* 46993 */ GIM_Try, /*On fail goto*//*Label 1037*/ GIMT_Encode4(47047), // Rule ID 145 // |
| 17236 | /* 46998 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 17237 | /* 47001 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usad8), |
| 17238 | /* 47006 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 17239 | /* 47009 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17240 | /* 47012 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17241 | /* 47015 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 17242 | /* 47019 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 17243 | /* 47023 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 17244 | /* 47027 */ // (intrinsic_wo_chain:{ *:[i32] } 3940:{ *:[iPTR] }, GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (USAD8:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) |
| 17245 | /* 47027 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::USAD8), |
| 17246 | /* 47030 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 17247 | /* 47032 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 17248 | /* 47034 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 17249 | /* 47036 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17250 | /* 47039 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17251 | /* 47045 */ GIR_RootConstrainSelectedInstOperands, |
| 17252 | /* 47046 */ // GIR_Coverage, 145, |
| 17253 | /* 47046 */ GIR_EraseRootFromParent_Done, |
| 17254 | /* 47047 */ // Label 1037: @47047 |
| 17255 | /* 47047 */ GIM_Try, /*On fail goto*//*Label 1038*/ GIMT_Encode4(47092), // Rule ID 204 // |
| 17256 | /* 47052 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCRC_IsARM), |
| 17257 | /* 47055 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32b), |
| 17258 | /* 47060 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 17259 | /* 47063 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17260 | /* 47066 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17261 | /* 47069 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17262 | /* 47073 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17263 | /* 47077 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17264 | /* 47081 */ // (intrinsic_wo_chain:{ *:[i32] } 3505:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (CRC32B:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 17265 | /* 47081 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::CRC32B), |
| 17266 | /* 47084 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 17267 | /* 47086 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 17268 | /* 47088 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 17269 | /* 47090 */ GIR_RootConstrainSelectedInstOperands, |
| 17270 | /* 47091 */ // GIR_Coverage, 204, |
| 17271 | /* 47091 */ GIR_EraseRootFromParent_Done, |
| 17272 | /* 47092 */ // Label 1038: @47092 |
| 17273 | /* 47092 */ GIM_Try, /*On fail goto*//*Label 1039*/ GIMT_Encode4(47137), // Rule ID 205 // |
| 17274 | /* 47097 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCRC_IsARM), |
| 17275 | /* 47100 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32cb), |
| 17276 | /* 47105 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 17277 | /* 47108 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17278 | /* 47111 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17279 | /* 47114 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17280 | /* 47118 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17281 | /* 47122 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17282 | /* 47126 */ // (intrinsic_wo_chain:{ *:[i32] } 3506:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (CRC32CB:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 17283 | /* 47126 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::CRC32CB), |
| 17284 | /* 47129 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 17285 | /* 47131 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 17286 | /* 47133 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 17287 | /* 47135 */ GIR_RootConstrainSelectedInstOperands, |
| 17288 | /* 47136 */ // GIR_Coverage, 205, |
| 17289 | /* 47136 */ GIR_EraseRootFromParent_Done, |
| 17290 | /* 47137 */ // Label 1039: @47137 |
| 17291 | /* 47137 */ GIM_Try, /*On fail goto*//*Label 1040*/ GIMT_Encode4(47182), // Rule ID 206 // |
| 17292 | /* 47142 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCRC_IsARM), |
| 17293 | /* 47145 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32h), |
| 17294 | /* 47150 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 17295 | /* 47153 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17296 | /* 47156 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17297 | /* 47159 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17298 | /* 47163 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17299 | /* 47167 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17300 | /* 47171 */ // (intrinsic_wo_chain:{ *:[i32] } 3509:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (CRC32H:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 17301 | /* 47171 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::CRC32H), |
| 17302 | /* 47174 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 17303 | /* 47176 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 17304 | /* 47178 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 17305 | /* 47180 */ GIR_RootConstrainSelectedInstOperands, |
| 17306 | /* 47181 */ // GIR_Coverage, 206, |
| 17307 | /* 47181 */ GIR_EraseRootFromParent_Done, |
| 17308 | /* 47182 */ // Label 1040: @47182 |
| 17309 | /* 47182 */ GIM_Try, /*On fail goto*//*Label 1041*/ GIMT_Encode4(47227), // Rule ID 207 // |
| 17310 | /* 47187 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCRC_IsARM), |
| 17311 | /* 47190 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32ch), |
| 17312 | /* 47195 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 17313 | /* 47198 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17314 | /* 47201 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17315 | /* 47204 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17316 | /* 47208 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17317 | /* 47212 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17318 | /* 47216 */ // (intrinsic_wo_chain:{ *:[i32] } 3507:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (CRC32CH:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 17319 | /* 47216 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::CRC32CH), |
| 17320 | /* 47219 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 17321 | /* 47221 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 17322 | /* 47223 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 17323 | /* 47225 */ GIR_RootConstrainSelectedInstOperands, |
| 17324 | /* 47226 */ // GIR_Coverage, 207, |
| 17325 | /* 47226 */ GIR_EraseRootFromParent_Done, |
| 17326 | /* 47227 */ // Label 1041: @47227 |
| 17327 | /* 47227 */ GIM_Try, /*On fail goto*//*Label 1042*/ GIMT_Encode4(47272), // Rule ID 208 // |
| 17328 | /* 47232 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCRC_IsARM), |
| 17329 | /* 47235 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32w), |
| 17330 | /* 47240 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 17331 | /* 47243 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17332 | /* 47246 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17333 | /* 47249 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17334 | /* 47253 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17335 | /* 47257 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17336 | /* 47261 */ // (intrinsic_wo_chain:{ *:[i32] } 3510:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (CRC32W:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 17337 | /* 47261 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::CRC32W), |
| 17338 | /* 47264 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 17339 | /* 47266 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 17340 | /* 47268 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 17341 | /* 47270 */ GIR_RootConstrainSelectedInstOperands, |
| 17342 | /* 47271 */ // GIR_Coverage, 208, |
| 17343 | /* 47271 */ GIR_EraseRootFromParent_Done, |
| 17344 | /* 47272 */ // Label 1042: @47272 |
| 17345 | /* 47272 */ GIM_Try, /*On fail goto*//*Label 1043*/ GIMT_Encode4(47317), // Rule ID 209 // |
| 17346 | /* 47277 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCRC_IsARM), |
| 17347 | /* 47280 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32cw), |
| 17348 | /* 47285 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 17349 | /* 47288 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17350 | /* 47291 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17351 | /* 47294 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17352 | /* 47298 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17353 | /* 47302 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17354 | /* 47306 */ // (intrinsic_wo_chain:{ *:[i32] } 3508:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (CRC32CW:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 17355 | /* 47306 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::CRC32CW), |
| 17356 | /* 47309 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 17357 | /* 47311 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 17358 | /* 47313 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 17359 | /* 47315 */ GIR_RootConstrainSelectedInstOperands, |
| 17360 | /* 47316 */ // GIR_Coverage, 209, |
| 17361 | /* 47316 */ GIR_EraseRootFromParent_Done, |
| 17362 | /* 47317 */ // Label 1043: @47317 |
| 17363 | /* 47317 */ GIM_Try, /*On fail goto*//*Label 1044*/ GIMT_Encode4(47371), // Rule ID 432 // |
| 17364 | /* 47322 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 17365 | /* 47325 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd16), |
| 17366 | /* 47330 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 17367 | /* 47333 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17368 | /* 47336 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17369 | /* 47339 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17370 | /* 47343 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17371 | /* 47347 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17372 | /* 47351 */ // (intrinsic_wo_chain:{ *:[i32] } 3866:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2QADD16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 17373 | /* 47351 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QADD16), |
| 17374 | /* 47354 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 17375 | /* 47356 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 17376 | /* 47358 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 17377 | /* 47360 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17378 | /* 47363 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17379 | /* 47369 */ GIR_RootConstrainSelectedInstOperands, |
| 17380 | /* 47370 */ // GIR_Coverage, 432, |
| 17381 | /* 47370 */ GIR_EraseRootFromParent_Done, |
| 17382 | /* 47371 */ // Label 1044: @47371 |
| 17383 | /* 47371 */ GIM_Try, /*On fail goto*//*Label 1045*/ GIMT_Encode4(47425), // Rule ID 433 // |
| 17384 | /* 47376 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 17385 | /* 47379 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd8), |
| 17386 | /* 47384 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 17387 | /* 47387 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17388 | /* 47390 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17389 | /* 47393 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17390 | /* 47397 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17391 | /* 47401 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17392 | /* 47405 */ // (intrinsic_wo_chain:{ *:[i32] } 3867:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2QADD8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 17393 | /* 47405 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QADD8), |
| 17394 | /* 47408 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 17395 | /* 47410 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 17396 | /* 47412 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 17397 | /* 47414 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17398 | /* 47417 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17399 | /* 47423 */ GIR_RootConstrainSelectedInstOperands, |
| 17400 | /* 47424 */ // GIR_Coverage, 433, |
| 17401 | /* 47424 */ GIR_EraseRootFromParent_Done, |
| 17402 | /* 47425 */ // Label 1045: @47425 |
| 17403 | /* 47425 */ GIM_Try, /*On fail goto*//*Label 1046*/ GIMT_Encode4(47479), // Rule ID 434 // |
| 17404 | /* 47430 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 17405 | /* 47433 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qasx), |
| 17406 | /* 47438 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 17407 | /* 47441 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17408 | /* 47444 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17409 | /* 47447 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17410 | /* 47451 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17411 | /* 47455 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17412 | /* 47459 */ // (intrinsic_wo_chain:{ *:[i32] } 3868:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2QASX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 17413 | /* 47459 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QASX), |
| 17414 | /* 47462 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 17415 | /* 47464 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 17416 | /* 47466 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 17417 | /* 47468 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17418 | /* 47471 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17419 | /* 47477 */ GIR_RootConstrainSelectedInstOperands, |
| 17420 | /* 47478 */ // GIR_Coverage, 434, |
| 17421 | /* 47478 */ GIR_EraseRootFromParent_Done, |
| 17422 | /* 47479 */ // Label 1046: @47479 |
| 17423 | /* 47479 */ GIM_Try, /*On fail goto*//*Label 1047*/ GIMT_Encode4(47533), // Rule ID 435 // |
| 17424 | /* 47484 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 17425 | /* 47487 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqsub8), |
| 17426 | /* 47492 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 17427 | /* 47495 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17428 | /* 47498 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17429 | /* 47501 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17430 | /* 47505 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17431 | /* 47509 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17432 | /* 47513 */ // (intrinsic_wo_chain:{ *:[i32] } 3939:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UQSUB8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 17433 | /* 47513 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UQSUB8), |
| 17434 | /* 47516 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 17435 | /* 47518 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 17436 | /* 47520 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 17437 | /* 47522 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17438 | /* 47525 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17439 | /* 47531 */ GIR_RootConstrainSelectedInstOperands, |
| 17440 | /* 47532 */ // GIR_Coverage, 435, |
| 17441 | /* 47532 */ GIR_EraseRootFromParent_Done, |
| 17442 | /* 47533 */ // Label 1047: @47533 |
| 17443 | /* 47533 */ GIM_Try, /*On fail goto*//*Label 1048*/ GIMT_Encode4(47587), // Rule ID 436 // |
| 17444 | /* 47538 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 17445 | /* 47541 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qsax), |
| 17446 | /* 47546 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 17447 | /* 47549 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17448 | /* 47552 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17449 | /* 47555 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17450 | /* 47559 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17451 | /* 47563 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17452 | /* 47567 */ // (intrinsic_wo_chain:{ *:[i32] } 3869:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2QSAX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 17453 | /* 47567 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QSAX), |
| 17454 | /* 47570 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 17455 | /* 47572 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 17456 | /* 47574 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 17457 | /* 47576 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17458 | /* 47579 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17459 | /* 47585 */ GIR_RootConstrainSelectedInstOperands, |
| 17460 | /* 47586 */ // GIR_Coverage, 436, |
| 17461 | /* 47586 */ GIR_EraseRootFromParent_Done, |
| 17462 | /* 47587 */ // Label 1048: @47587 |
| 17463 | /* 47587 */ GIM_Try, /*On fail goto*//*Label 1049*/ GIMT_Encode4(47641), // Rule ID 437 // |
| 17464 | /* 47592 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 17465 | /* 47595 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qsub16), |
| 17466 | /* 47600 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 17467 | /* 47603 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17468 | /* 47606 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17469 | /* 47609 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17470 | /* 47613 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17471 | /* 47617 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17472 | /* 47621 */ // (intrinsic_wo_chain:{ *:[i32] } 3871:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2QSUB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 17473 | /* 47621 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QSUB16), |
| 17474 | /* 47624 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 17475 | /* 47626 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 17476 | /* 47628 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 17477 | /* 47630 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17478 | /* 47633 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17479 | /* 47639 */ GIR_RootConstrainSelectedInstOperands, |
| 17480 | /* 47640 */ // GIR_Coverage, 437, |
| 17481 | /* 47640 */ GIR_EraseRootFromParent_Done, |
| 17482 | /* 47641 */ // Label 1049: @47641 |
| 17483 | /* 47641 */ GIM_Try, /*On fail goto*//*Label 1050*/ GIMT_Encode4(47695), // Rule ID 438 // |
| 17484 | /* 47646 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 17485 | /* 47649 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qsub8), |
| 17486 | /* 47654 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 17487 | /* 47657 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17488 | /* 47660 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17489 | /* 47663 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17490 | /* 47667 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17491 | /* 47671 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17492 | /* 47675 */ // (intrinsic_wo_chain:{ *:[i32] } 3872:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2QSUB8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 17493 | /* 47675 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QSUB8), |
| 17494 | /* 47678 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 17495 | /* 47680 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 17496 | /* 47682 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 17497 | /* 47684 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17498 | /* 47687 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17499 | /* 47693 */ GIR_RootConstrainSelectedInstOperands, |
| 17500 | /* 47694 */ // GIR_Coverage, 438, |
| 17501 | /* 47694 */ GIR_EraseRootFromParent_Done, |
| 17502 | /* 47695 */ // Label 1050: @47695 |
| 17503 | /* 47695 */ GIM_Try, /*On fail goto*//*Label 1051*/ GIMT_Encode4(47749), // Rule ID 439 // |
| 17504 | /* 47700 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 17505 | /* 47703 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqadd16), |
| 17506 | /* 47708 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 17507 | /* 47711 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17508 | /* 47714 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17509 | /* 47717 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17510 | /* 47721 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17511 | /* 47725 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17512 | /* 47729 */ // (intrinsic_wo_chain:{ *:[i32] } 3934:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UQADD16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 17513 | /* 47729 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UQADD16), |
| 17514 | /* 47732 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 17515 | /* 47734 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 17516 | /* 47736 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 17517 | /* 47738 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17518 | /* 47741 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17519 | /* 47747 */ GIR_RootConstrainSelectedInstOperands, |
| 17520 | /* 47748 */ // GIR_Coverage, 439, |
| 17521 | /* 47748 */ GIR_EraseRootFromParent_Done, |
| 17522 | /* 47749 */ // Label 1051: @47749 |
| 17523 | /* 47749 */ GIM_Try, /*On fail goto*//*Label 1052*/ GIMT_Encode4(47803), // Rule ID 440 // |
| 17524 | /* 47754 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 17525 | /* 47757 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqadd8), |
| 17526 | /* 47762 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 17527 | /* 47765 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17528 | /* 47768 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17529 | /* 47771 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17530 | /* 47775 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17531 | /* 47779 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17532 | /* 47783 */ // (intrinsic_wo_chain:{ *:[i32] } 3935:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UQADD8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 17533 | /* 47783 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UQADD8), |
| 17534 | /* 47786 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 17535 | /* 47788 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 17536 | /* 47790 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 17537 | /* 47792 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17538 | /* 47795 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17539 | /* 47801 */ GIR_RootConstrainSelectedInstOperands, |
| 17540 | /* 47802 */ // GIR_Coverage, 440, |
| 17541 | /* 47802 */ GIR_EraseRootFromParent_Done, |
| 17542 | /* 47803 */ // Label 1052: @47803 |
| 17543 | /* 47803 */ GIM_Try, /*On fail goto*//*Label 1053*/ GIMT_Encode4(47857), // Rule ID 441 // |
| 17544 | /* 47808 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 17545 | /* 47811 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqasx), |
| 17546 | /* 47816 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 17547 | /* 47819 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17548 | /* 47822 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17549 | /* 47825 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17550 | /* 47829 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17551 | /* 47833 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17552 | /* 47837 */ // (intrinsic_wo_chain:{ *:[i32] } 3936:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UQASX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 17553 | /* 47837 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UQASX), |
| 17554 | /* 47840 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 17555 | /* 47842 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 17556 | /* 47844 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 17557 | /* 47846 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17558 | /* 47849 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17559 | /* 47855 */ GIR_RootConstrainSelectedInstOperands, |
| 17560 | /* 47856 */ // GIR_Coverage, 441, |
| 17561 | /* 47856 */ GIR_EraseRootFromParent_Done, |
| 17562 | /* 47857 */ // Label 1053: @47857 |
| 17563 | /* 47857 */ GIM_Try, /*On fail goto*//*Label 1054*/ GIMT_Encode4(47911), // Rule ID 442 // |
| 17564 | /* 47862 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 17565 | /* 47865 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqsax), |
| 17566 | /* 47870 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 17567 | /* 47873 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17568 | /* 47876 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17569 | /* 47879 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17570 | /* 47883 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17571 | /* 47887 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17572 | /* 47891 */ // (intrinsic_wo_chain:{ *:[i32] } 3937:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UQSAX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 17573 | /* 47891 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UQSAX), |
| 17574 | /* 47894 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 17575 | /* 47896 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 17576 | /* 47898 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 17577 | /* 47900 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17578 | /* 47903 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17579 | /* 47909 */ GIR_RootConstrainSelectedInstOperands, |
| 17580 | /* 47910 */ // GIR_Coverage, 442, |
| 17581 | /* 47910 */ GIR_EraseRootFromParent_Done, |
| 17582 | /* 47911 */ // Label 1054: @47911 |
| 17583 | /* 47911 */ GIM_Try, /*On fail goto*//*Label 1055*/ GIMT_Encode4(47965), // Rule ID 443 // |
| 17584 | /* 47916 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 17585 | /* 47919 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqsub16), |
| 17586 | /* 47924 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 17587 | /* 47927 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17588 | /* 47930 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17589 | /* 47933 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17590 | /* 47937 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17591 | /* 47941 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17592 | /* 47945 */ // (intrinsic_wo_chain:{ *:[i32] } 3938:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UQSUB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 17593 | /* 47945 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UQSUB16), |
| 17594 | /* 47948 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 17595 | /* 47950 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 17596 | /* 47952 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 17597 | /* 47954 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17598 | /* 47957 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17599 | /* 47963 */ GIR_RootConstrainSelectedInstOperands, |
| 17600 | /* 47964 */ // GIR_Coverage, 443, |
| 17601 | /* 47964 */ GIR_EraseRootFromParent_Done, |
| 17602 | /* 47965 */ // Label 1055: @47965 |
| 17603 | /* 47965 */ GIM_Try, /*On fail goto*//*Label 1056*/ GIMT_Encode4(48019), // Rule ID 456 // |
| 17604 | /* 47970 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 17605 | /* 47973 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shasx), |
| 17606 | /* 47978 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 17607 | /* 47981 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17608 | /* 47984 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17609 | /* 47987 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17610 | /* 47991 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17611 | /* 47995 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17612 | /* 47999 */ // (intrinsic_wo_chain:{ *:[i32] } 3880:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SHASX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 17613 | /* 47999 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SHASX), |
| 17614 | /* 48002 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 17615 | /* 48004 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 17616 | /* 48006 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 17617 | /* 48008 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17618 | /* 48011 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17619 | /* 48017 */ GIR_RootConstrainSelectedInstOperands, |
| 17620 | /* 48018 */ // GIR_Coverage, 456, |
| 17621 | /* 48018 */ GIR_EraseRootFromParent_Done, |
| 17622 | /* 48019 */ // Label 1056: @48019 |
| 17623 | /* 48019 */ GIM_Try, /*On fail goto*//*Label 1057*/ GIMT_Encode4(48073), // Rule ID 457 // |
| 17624 | /* 48024 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 17625 | /* 48027 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shadd16), |
| 17626 | /* 48032 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 17627 | /* 48035 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17628 | /* 48038 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17629 | /* 48041 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17630 | /* 48045 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17631 | /* 48049 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17632 | /* 48053 */ // (intrinsic_wo_chain:{ *:[i32] } 3878:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SHADD16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 17633 | /* 48053 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SHADD16), |
| 17634 | /* 48056 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 17635 | /* 48058 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 17636 | /* 48060 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 17637 | /* 48062 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17638 | /* 48065 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17639 | /* 48071 */ GIR_RootConstrainSelectedInstOperands, |
| 17640 | /* 48072 */ // GIR_Coverage, 457, |
| 17641 | /* 48072 */ GIR_EraseRootFromParent_Done, |
| 17642 | /* 48073 */ // Label 1057: @48073 |
| 17643 | /* 48073 */ GIM_Try, /*On fail goto*//*Label 1058*/ GIMT_Encode4(48127), // Rule ID 458 // |
| 17644 | /* 48078 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 17645 | /* 48081 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shadd8), |
| 17646 | /* 48086 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 17647 | /* 48089 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17648 | /* 48092 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17649 | /* 48095 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17650 | /* 48099 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17651 | /* 48103 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17652 | /* 48107 */ // (intrinsic_wo_chain:{ *:[i32] } 3879:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SHADD8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 17653 | /* 48107 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SHADD8), |
| 17654 | /* 48110 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 17655 | /* 48112 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 17656 | /* 48114 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 17657 | /* 48116 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17658 | /* 48119 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17659 | /* 48125 */ GIR_RootConstrainSelectedInstOperands, |
| 17660 | /* 48126 */ // GIR_Coverage, 458, |
| 17661 | /* 48126 */ GIR_EraseRootFromParent_Done, |
| 17662 | /* 48127 */ // Label 1058: @48127 |
| 17663 | /* 48127 */ GIM_Try, /*On fail goto*//*Label 1059*/ GIMT_Encode4(48181), // Rule ID 459 // |
| 17664 | /* 48132 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 17665 | /* 48135 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shsax), |
| 17666 | /* 48140 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 17667 | /* 48143 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17668 | /* 48146 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17669 | /* 48149 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17670 | /* 48153 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17671 | /* 48157 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17672 | /* 48161 */ // (intrinsic_wo_chain:{ *:[i32] } 3881:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SHSAX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 17673 | /* 48161 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SHSAX), |
| 17674 | /* 48164 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 17675 | /* 48166 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 17676 | /* 48168 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 17677 | /* 48170 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17678 | /* 48173 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17679 | /* 48179 */ GIR_RootConstrainSelectedInstOperands, |
| 17680 | /* 48180 */ // GIR_Coverage, 459, |
| 17681 | /* 48180 */ GIR_EraseRootFromParent_Done, |
| 17682 | /* 48181 */ // Label 1059: @48181 |
| 17683 | /* 48181 */ GIM_Try, /*On fail goto*//*Label 1060*/ GIMT_Encode4(48235), // Rule ID 460 // |
| 17684 | /* 48186 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 17685 | /* 48189 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shsub16), |
| 17686 | /* 48194 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 17687 | /* 48197 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17688 | /* 48200 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17689 | /* 48203 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17690 | /* 48207 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17691 | /* 48211 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17692 | /* 48215 */ // (intrinsic_wo_chain:{ *:[i32] } 3882:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SHSUB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 17693 | /* 48215 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SHSUB16), |
| 17694 | /* 48218 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 17695 | /* 48220 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 17696 | /* 48222 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 17697 | /* 48224 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17698 | /* 48227 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17699 | /* 48233 */ GIR_RootConstrainSelectedInstOperands, |
| 17700 | /* 48234 */ // GIR_Coverage, 460, |
| 17701 | /* 48234 */ GIR_EraseRootFromParent_Done, |
| 17702 | /* 48235 */ // Label 1060: @48235 |
| 17703 | /* 48235 */ GIM_Try, /*On fail goto*//*Label 1061*/ GIMT_Encode4(48289), // Rule ID 461 // |
| 17704 | /* 48240 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 17705 | /* 48243 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shsub8), |
| 17706 | /* 48248 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 17707 | /* 48251 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17708 | /* 48254 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17709 | /* 48257 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17710 | /* 48261 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17711 | /* 48265 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17712 | /* 48269 */ // (intrinsic_wo_chain:{ *:[i32] } 3883:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SHSUB8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 17713 | /* 48269 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SHSUB8), |
| 17714 | /* 48272 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 17715 | /* 48274 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 17716 | /* 48276 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 17717 | /* 48278 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17718 | /* 48281 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17719 | /* 48287 */ GIR_RootConstrainSelectedInstOperands, |
| 17720 | /* 48288 */ // GIR_Coverage, 461, |
| 17721 | /* 48288 */ GIR_EraseRootFromParent_Done, |
| 17722 | /* 48289 */ // Label 1061: @48289 |
| 17723 | /* 48289 */ GIM_Try, /*On fail goto*//*Label 1062*/ GIMT_Encode4(48343), // Rule ID 462 // |
| 17724 | /* 48294 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 17725 | /* 48297 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhasx), |
| 17726 | /* 48302 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 17727 | /* 48305 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17728 | /* 48308 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17729 | /* 48311 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17730 | /* 48315 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17731 | /* 48319 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17732 | /* 48323 */ // (intrinsic_wo_chain:{ *:[i32] } 3929:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UHASX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 17733 | /* 48323 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UHASX), |
| 17734 | /* 48326 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 17735 | /* 48328 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 17736 | /* 48330 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 17737 | /* 48332 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17738 | /* 48335 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17739 | /* 48341 */ GIR_RootConstrainSelectedInstOperands, |
| 17740 | /* 48342 */ // GIR_Coverage, 462, |
| 17741 | /* 48342 */ GIR_EraseRootFromParent_Done, |
| 17742 | /* 48343 */ // Label 1062: @48343 |
| 17743 | /* 48343 */ GIM_Try, /*On fail goto*//*Label 1063*/ GIMT_Encode4(48397), // Rule ID 463 // |
| 17744 | /* 48348 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 17745 | /* 48351 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhadd16), |
| 17746 | /* 48356 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 17747 | /* 48359 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17748 | /* 48362 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17749 | /* 48365 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17750 | /* 48369 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17751 | /* 48373 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17752 | /* 48377 */ // (intrinsic_wo_chain:{ *:[i32] } 3927:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UHADD16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 17753 | /* 48377 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UHADD16), |
| 17754 | /* 48380 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 17755 | /* 48382 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 17756 | /* 48384 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 17757 | /* 48386 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17758 | /* 48389 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17759 | /* 48395 */ GIR_RootConstrainSelectedInstOperands, |
| 17760 | /* 48396 */ // GIR_Coverage, 463, |
| 17761 | /* 48396 */ GIR_EraseRootFromParent_Done, |
| 17762 | /* 48397 */ // Label 1063: @48397 |
| 17763 | /* 48397 */ GIM_Try, /*On fail goto*//*Label 1064*/ GIMT_Encode4(48451), // Rule ID 464 // |
| 17764 | /* 48402 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 17765 | /* 48405 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhadd8), |
| 17766 | /* 48410 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 17767 | /* 48413 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17768 | /* 48416 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17769 | /* 48419 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17770 | /* 48423 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17771 | /* 48427 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17772 | /* 48431 */ // (intrinsic_wo_chain:{ *:[i32] } 3928:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UHADD8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 17773 | /* 48431 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UHADD8), |
| 17774 | /* 48434 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 17775 | /* 48436 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 17776 | /* 48438 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 17777 | /* 48440 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17778 | /* 48443 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17779 | /* 48449 */ GIR_RootConstrainSelectedInstOperands, |
| 17780 | /* 48450 */ // GIR_Coverage, 464, |
| 17781 | /* 48450 */ GIR_EraseRootFromParent_Done, |
| 17782 | /* 48451 */ // Label 1064: @48451 |
| 17783 | /* 48451 */ GIM_Try, /*On fail goto*//*Label 1065*/ GIMT_Encode4(48505), // Rule ID 465 // |
| 17784 | /* 48456 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 17785 | /* 48459 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhsax), |
| 17786 | /* 48464 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 17787 | /* 48467 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17788 | /* 48470 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17789 | /* 48473 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17790 | /* 48477 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17791 | /* 48481 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17792 | /* 48485 */ // (intrinsic_wo_chain:{ *:[i32] } 3930:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UHSAX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 17793 | /* 48485 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UHSAX), |
| 17794 | /* 48488 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 17795 | /* 48490 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 17796 | /* 48492 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 17797 | /* 48494 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17798 | /* 48497 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17799 | /* 48503 */ GIR_RootConstrainSelectedInstOperands, |
| 17800 | /* 48504 */ // GIR_Coverage, 465, |
| 17801 | /* 48504 */ GIR_EraseRootFromParent_Done, |
| 17802 | /* 48505 */ // Label 1065: @48505 |
| 17803 | /* 48505 */ GIM_Try, /*On fail goto*//*Label 1066*/ GIMT_Encode4(48559), // Rule ID 466 // |
| 17804 | /* 48510 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 17805 | /* 48513 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhsub16), |
| 17806 | /* 48518 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 17807 | /* 48521 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17808 | /* 48524 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17809 | /* 48527 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17810 | /* 48531 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17811 | /* 48535 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17812 | /* 48539 */ // (intrinsic_wo_chain:{ *:[i32] } 3931:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UHSUB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 17813 | /* 48539 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UHSUB16), |
| 17814 | /* 48542 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 17815 | /* 48544 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 17816 | /* 48546 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 17817 | /* 48548 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17818 | /* 48551 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17819 | /* 48557 */ GIR_RootConstrainSelectedInstOperands, |
| 17820 | /* 48558 */ // GIR_Coverage, 466, |
| 17821 | /* 48558 */ GIR_EraseRootFromParent_Done, |
| 17822 | /* 48559 */ // Label 1066: @48559 |
| 17823 | /* 48559 */ GIM_Try, /*On fail goto*//*Label 1067*/ GIMT_Encode4(48613), // Rule ID 467 // |
| 17824 | /* 48564 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 17825 | /* 48567 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhsub8), |
| 17826 | /* 48572 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 17827 | /* 48575 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17828 | /* 48578 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17829 | /* 48581 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17830 | /* 48585 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17831 | /* 48589 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17832 | /* 48593 */ // (intrinsic_wo_chain:{ *:[i32] } 3932:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UHSUB8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 17833 | /* 48593 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UHSUB8), |
| 17834 | /* 48596 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 17835 | /* 48598 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 17836 | /* 48600 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 17837 | /* 48602 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17838 | /* 48605 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17839 | /* 48611 */ GIR_RootConstrainSelectedInstOperands, |
| 17840 | /* 48612 */ // GIR_Coverage, 467, |
| 17841 | /* 48612 */ GIR_EraseRootFromParent_Done, |
| 17842 | /* 48613 */ // Label 1067: @48613 |
| 17843 | /* 48613 */ GIM_Try, /*On fail goto*//*Label 1068*/ GIMT_Encode4(48667), // Rule ID 468 // |
| 17844 | /* 48618 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 17845 | /* 48621 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usad8), |
| 17846 | /* 48626 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 17847 | /* 48629 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17848 | /* 48632 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17849 | /* 48635 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17850 | /* 48639 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17851 | /* 48643 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17852 | /* 48647 */ // (intrinsic_wo_chain:{ *:[i32] } 3940:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2USAD8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 17853 | /* 48647 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2USAD8), |
| 17854 | /* 48650 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 17855 | /* 48652 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 17856 | /* 48654 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 17857 | /* 48656 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17858 | /* 48659 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17859 | /* 48665 */ GIR_RootConstrainSelectedInstOperands, |
| 17860 | /* 48666 */ // GIR_Coverage, 468, |
| 17861 | /* 48666 */ GIR_EraseRootFromParent_Done, |
| 17862 | /* 48667 */ // Label 1068: @48667 |
| 17863 | /* 48667 */ GIM_Try, /*On fail goto*//*Label 1069*/ GIMT_Encode4(48721), // Rule ID 524 // |
| 17864 | /* 48672 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 17865 | /* 48675 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smuad), |
| 17866 | /* 48680 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 17867 | /* 48683 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17868 | /* 48686 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17869 | /* 48689 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17870 | /* 48693 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17871 | /* 48697 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17872 | /* 48701 */ // (intrinsic_wo_chain:{ *:[i32] } 3898:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMUAD:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 17873 | /* 48701 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMUAD), |
| 17874 | /* 48704 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 17875 | /* 48706 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 17876 | /* 48708 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 17877 | /* 48710 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17878 | /* 48713 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17879 | /* 48719 */ GIR_RootConstrainSelectedInstOperands, |
| 17880 | /* 48720 */ // GIR_Coverage, 524, |
| 17881 | /* 48720 */ GIR_EraseRootFromParent_Done, |
| 17882 | /* 48721 */ // Label 1069: @48721 |
| 17883 | /* 48721 */ GIM_Try, /*On fail goto*//*Label 1070*/ GIMT_Encode4(48775), // Rule ID 525 // |
| 17884 | /* 48726 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 17885 | /* 48729 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smuadx), |
| 17886 | /* 48734 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 17887 | /* 48737 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17888 | /* 48740 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17889 | /* 48743 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17890 | /* 48747 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17891 | /* 48751 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17892 | /* 48755 */ // (intrinsic_wo_chain:{ *:[i32] } 3899:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMUADX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 17893 | /* 48755 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMUADX), |
| 17894 | /* 48758 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 17895 | /* 48760 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 17896 | /* 48762 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 17897 | /* 48764 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17898 | /* 48767 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17899 | /* 48773 */ GIR_RootConstrainSelectedInstOperands, |
| 17900 | /* 48774 */ // GIR_Coverage, 525, |
| 17901 | /* 48774 */ GIR_EraseRootFromParent_Done, |
| 17902 | /* 48775 */ // Label 1070: @48775 |
| 17903 | /* 48775 */ GIM_Try, /*On fail goto*//*Label 1071*/ GIMT_Encode4(48829), // Rule ID 526 // |
| 17904 | /* 48780 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 17905 | /* 48783 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smusd), |
| 17906 | /* 48788 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 17907 | /* 48791 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17908 | /* 48794 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17909 | /* 48797 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17910 | /* 48801 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17911 | /* 48805 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17912 | /* 48809 */ // (intrinsic_wo_chain:{ *:[i32] } 3906:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMUSD:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 17913 | /* 48809 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMUSD), |
| 17914 | /* 48812 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 17915 | /* 48814 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 17916 | /* 48816 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 17917 | /* 48818 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17918 | /* 48821 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17919 | /* 48827 */ GIR_RootConstrainSelectedInstOperands, |
| 17920 | /* 48828 */ // GIR_Coverage, 526, |
| 17921 | /* 48828 */ GIR_EraseRootFromParent_Done, |
| 17922 | /* 48829 */ // Label 1071: @48829 |
| 17923 | /* 48829 */ GIM_Try, /*On fail goto*//*Label 1072*/ GIMT_Encode4(48883), // Rule ID 527 // |
| 17924 | /* 48834 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 17925 | /* 48837 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smusdx), |
| 17926 | /* 48842 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 17927 | /* 48845 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17928 | /* 48848 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17929 | /* 48851 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17930 | /* 48855 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17931 | /* 48859 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17932 | /* 48863 */ // (intrinsic_wo_chain:{ *:[i32] } 3907:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMUSDX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 17933 | /* 48863 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMUSDX), |
| 17934 | /* 48866 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 17935 | /* 48868 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 17936 | /* 48870 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 17937 | /* 48872 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17938 | /* 48875 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17939 | /* 48881 */ GIR_RootConstrainSelectedInstOperands, |
| 17940 | /* 48882 */ // GIR_Coverage, 527, |
| 17941 | /* 48882 */ GIR_EraseRootFromParent_Done, |
| 17942 | /* 48883 */ // Label 1072: @48883 |
| 17943 | /* 48883 */ GIM_Try, /*On fail goto*//*Label 1073*/ GIMT_Encode4(48928), // Rule ID 541 // |
| 17944 | /* 48888 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCRC_IsThumb2), |
| 17945 | /* 48891 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32b), |
| 17946 | /* 48896 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 17947 | /* 48899 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17948 | /* 48902 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17949 | /* 48905 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17950 | /* 48909 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17951 | /* 48913 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17952 | /* 48917 */ // (intrinsic_wo_chain:{ *:[i32] } 3505:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2CRC32B:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 17953 | /* 48917 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2CRC32B), |
| 17954 | /* 48920 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 17955 | /* 48922 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 17956 | /* 48924 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 17957 | /* 48926 */ GIR_RootConstrainSelectedInstOperands, |
| 17958 | /* 48927 */ // GIR_Coverage, 541, |
| 17959 | /* 48927 */ GIR_EraseRootFromParent_Done, |
| 17960 | /* 48928 */ // Label 1073: @48928 |
| 17961 | /* 48928 */ GIM_Try, /*On fail goto*//*Label 1074*/ GIMT_Encode4(48973), // Rule ID 542 // |
| 17962 | /* 48933 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCRC_IsThumb2), |
| 17963 | /* 48936 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32cb), |
| 17964 | /* 48941 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 17965 | /* 48944 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17966 | /* 48947 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17967 | /* 48950 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17968 | /* 48954 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17969 | /* 48958 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17970 | /* 48962 */ // (intrinsic_wo_chain:{ *:[i32] } 3506:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2CRC32CB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 17971 | /* 48962 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2CRC32CB), |
| 17972 | /* 48965 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 17973 | /* 48967 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 17974 | /* 48969 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 17975 | /* 48971 */ GIR_RootConstrainSelectedInstOperands, |
| 17976 | /* 48972 */ // GIR_Coverage, 542, |
| 17977 | /* 48972 */ GIR_EraseRootFromParent_Done, |
| 17978 | /* 48973 */ // Label 1074: @48973 |
| 17979 | /* 48973 */ GIM_Try, /*On fail goto*//*Label 1075*/ GIMT_Encode4(49018), // Rule ID 543 // |
| 17980 | /* 48978 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCRC_IsThumb2), |
| 17981 | /* 48981 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32h), |
| 17982 | /* 48986 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 17983 | /* 48989 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17984 | /* 48992 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17985 | /* 48995 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17986 | /* 48999 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17987 | /* 49003 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17988 | /* 49007 */ // (intrinsic_wo_chain:{ *:[i32] } 3509:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2CRC32H:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 17989 | /* 49007 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2CRC32H), |
| 17990 | /* 49010 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 17991 | /* 49012 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 17992 | /* 49014 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 17993 | /* 49016 */ GIR_RootConstrainSelectedInstOperands, |
| 17994 | /* 49017 */ // GIR_Coverage, 543, |
| 17995 | /* 49017 */ GIR_EraseRootFromParent_Done, |
| 17996 | /* 49018 */ // Label 1075: @49018 |
| 17997 | /* 49018 */ GIM_Try, /*On fail goto*//*Label 1076*/ GIMT_Encode4(49063), // Rule ID 544 // |
| 17998 | /* 49023 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCRC_IsThumb2), |
| 17999 | /* 49026 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32ch), |
| 18000 | /* 49031 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18001 | /* 49034 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18002 | /* 49037 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18003 | /* 49040 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18004 | /* 49044 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18005 | /* 49048 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18006 | /* 49052 */ // (intrinsic_wo_chain:{ *:[i32] } 3507:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2CRC32CH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 18007 | /* 49052 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2CRC32CH), |
| 18008 | /* 49055 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18009 | /* 49057 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18010 | /* 49059 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18011 | /* 49061 */ GIR_RootConstrainSelectedInstOperands, |
| 18012 | /* 49062 */ // GIR_Coverage, 544, |
| 18013 | /* 49062 */ GIR_EraseRootFromParent_Done, |
| 18014 | /* 49063 */ // Label 1076: @49063 |
| 18015 | /* 49063 */ GIM_Try, /*On fail goto*//*Label 1077*/ GIMT_Encode4(49108), // Rule ID 545 // |
| 18016 | /* 49068 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCRC_IsThumb2), |
| 18017 | /* 49071 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32w), |
| 18018 | /* 49076 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18019 | /* 49079 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18020 | /* 49082 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18021 | /* 49085 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18022 | /* 49089 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18023 | /* 49093 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18024 | /* 49097 */ // (intrinsic_wo_chain:{ *:[i32] } 3510:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2CRC32W:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 18025 | /* 49097 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2CRC32W), |
| 18026 | /* 49100 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18027 | /* 49102 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18028 | /* 49104 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18029 | /* 49106 */ GIR_RootConstrainSelectedInstOperands, |
| 18030 | /* 49107 */ // GIR_Coverage, 545, |
| 18031 | /* 49107 */ GIR_EraseRootFromParent_Done, |
| 18032 | /* 49108 */ // Label 1077: @49108 |
| 18033 | /* 49108 */ GIM_Try, /*On fail goto*//*Label 1078*/ GIMT_Encode4(49153), // Rule ID 546 // |
| 18034 | /* 49113 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCRC_IsThumb2), |
| 18035 | /* 49116 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32cw), |
| 18036 | /* 49121 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18037 | /* 49124 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18038 | /* 49127 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18039 | /* 49130 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18040 | /* 49134 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18041 | /* 49138 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18042 | /* 49142 */ // (intrinsic_wo_chain:{ *:[i32] } 3508:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2CRC32CW:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 18043 | /* 49142 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2CRC32CW), |
| 18044 | /* 49145 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18045 | /* 49147 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18046 | /* 49149 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18047 | /* 49151 */ GIR_RootConstrainSelectedInstOperands, |
| 18048 | /* 49152 */ // GIR_Coverage, 546, |
| 18049 | /* 49152 */ GIR_EraseRootFromParent_Done, |
| 18050 | /* 49153 */ // Label 1078: @49153 |
| 18051 | /* 49153 */ GIM_Try, /*On fail goto*//*Label 1079*/ GIMT_Encode4(49207), // Rule ID 792 // |
| 18052 | /* 49158 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 18053 | /* 49161 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhadds), |
| 18054 | /* 49166 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 18055 | /* 49169 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 18056 | /* 49172 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 18057 | /* 49175 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18058 | /* 49179 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18059 | /* 49183 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18060 | /* 49187 */ // (intrinsic_wo_chain:{ *:[v4i16] } 3775:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VHADDsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 18061 | /* 49187 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHADDsv4i16), |
| 18062 | /* 49190 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 18063 | /* 49192 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 18064 | /* 49194 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 18065 | /* 49196 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18066 | /* 49199 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18067 | /* 49205 */ GIR_RootConstrainSelectedInstOperands, |
| 18068 | /* 49206 */ // GIR_Coverage, 792, |
| 18069 | /* 49206 */ GIR_EraseRootFromParent_Done, |
| 18070 | /* 49207 */ // Label 1079: @49207 |
| 18071 | /* 49207 */ GIM_Try, /*On fail goto*//*Label 1080*/ GIMT_Encode4(49261), // Rule ID 793 // |
| 18072 | /* 49212 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 18073 | /* 49215 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhadds), |
| 18074 | /* 49220 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 18075 | /* 49223 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 18076 | /* 49226 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 18077 | /* 49229 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18078 | /* 49233 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18079 | /* 49237 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18080 | /* 49241 */ // (intrinsic_wo_chain:{ *:[v2i32] } 3775:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VHADDsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 18081 | /* 49241 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHADDsv2i32), |
| 18082 | /* 49244 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 18083 | /* 49246 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 18084 | /* 49248 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 18085 | /* 49250 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18086 | /* 49253 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18087 | /* 49259 */ GIR_RootConstrainSelectedInstOperands, |
| 18088 | /* 49260 */ // GIR_Coverage, 793, |
| 18089 | /* 49260 */ GIR_EraseRootFromParent_Done, |
| 18090 | /* 49261 */ // Label 1080: @49261 |
| 18091 | /* 49261 */ GIM_Try, /*On fail goto*//*Label 1081*/ GIMT_Encode4(49315), // Rule ID 794 // |
| 18092 | /* 49266 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 18093 | /* 49269 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhadds), |
| 18094 | /* 49274 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 18095 | /* 49277 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 18096 | /* 49280 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 18097 | /* 49283 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18098 | /* 49287 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18099 | /* 49291 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18100 | /* 49295 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3775:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VHADDsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 18101 | /* 49295 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHADDsv8i16), |
| 18102 | /* 49298 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 18103 | /* 49300 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 18104 | /* 49302 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 18105 | /* 49304 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18106 | /* 49307 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18107 | /* 49313 */ GIR_RootConstrainSelectedInstOperands, |
| 18108 | /* 49314 */ // GIR_Coverage, 794, |
| 18109 | /* 49314 */ GIR_EraseRootFromParent_Done, |
| 18110 | /* 49315 */ // Label 1081: @49315 |
| 18111 | /* 49315 */ GIM_Try, /*On fail goto*//*Label 1082*/ GIMT_Encode4(49369), // Rule ID 795 // |
| 18112 | /* 49320 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 18113 | /* 49323 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhadds), |
| 18114 | /* 49328 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 18115 | /* 49331 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 18116 | /* 49334 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 18117 | /* 49337 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18118 | /* 49341 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18119 | /* 49345 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18120 | /* 49349 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3775:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VHADDsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 18121 | /* 49349 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHADDsv4i32), |
| 18122 | /* 49352 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 18123 | /* 49354 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 18124 | /* 49356 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 18125 | /* 49358 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18126 | /* 49361 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18127 | /* 49367 */ GIR_RootConstrainSelectedInstOperands, |
| 18128 | /* 49368 */ // GIR_Coverage, 795, |
| 18129 | /* 49368 */ GIR_EraseRootFromParent_Done, |
| 18130 | /* 49369 */ // Label 1082: @49369 |
| 18131 | /* 49369 */ GIM_Try, /*On fail goto*//*Label 1083*/ GIMT_Encode4(49423), // Rule ID 796 // |
| 18132 | /* 49374 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 18133 | /* 49377 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhadds), |
| 18134 | /* 49382 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, |
| 18135 | /* 49385 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 18136 | /* 49388 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 18137 | /* 49391 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18138 | /* 49395 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18139 | /* 49399 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18140 | /* 49403 */ // (intrinsic_wo_chain:{ *:[v8i8] } 3775:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VHADDsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 18141 | /* 49403 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHADDsv8i8), |
| 18142 | /* 49406 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 18143 | /* 49408 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 18144 | /* 49410 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 18145 | /* 49412 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18146 | /* 49415 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18147 | /* 49421 */ GIR_RootConstrainSelectedInstOperands, |
| 18148 | /* 49422 */ // GIR_Coverage, 796, |
| 18149 | /* 49422 */ GIR_EraseRootFromParent_Done, |
| 18150 | /* 49423 */ // Label 1083: @49423 |
| 18151 | /* 49423 */ GIM_Try, /*On fail goto*//*Label 1084*/ GIMT_Encode4(49477), // Rule ID 797 // |
| 18152 | /* 49428 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 18153 | /* 49431 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhadds), |
| 18154 | /* 49436 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 18155 | /* 49439 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 18156 | /* 49442 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 18157 | /* 49445 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18158 | /* 49449 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18159 | /* 49453 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18160 | /* 49457 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3775:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VHADDsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 18161 | /* 49457 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHADDsv16i8), |
| 18162 | /* 49460 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 18163 | /* 49462 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 18164 | /* 49464 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 18165 | /* 49466 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18166 | /* 49469 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18167 | /* 49475 */ GIR_RootConstrainSelectedInstOperands, |
| 18168 | /* 49476 */ // GIR_Coverage, 797, |
| 18169 | /* 49476 */ GIR_EraseRootFromParent_Done, |
| 18170 | /* 49477 */ // Label 1084: @49477 |
| 18171 | /* 49477 */ GIM_Try, /*On fail goto*//*Label 1085*/ GIMT_Encode4(49531), // Rule ID 798 // |
| 18172 | /* 49482 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 18173 | /* 49485 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhaddu), |
| 18174 | /* 49490 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 18175 | /* 49493 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 18176 | /* 49496 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 18177 | /* 49499 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18178 | /* 49503 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18179 | /* 49507 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18180 | /* 49511 */ // (intrinsic_wo_chain:{ *:[v4i16] } 3776:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VHADDuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 18181 | /* 49511 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHADDuv4i16), |
| 18182 | /* 49514 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 18183 | /* 49516 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 18184 | /* 49518 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 18185 | /* 49520 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18186 | /* 49523 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18187 | /* 49529 */ GIR_RootConstrainSelectedInstOperands, |
| 18188 | /* 49530 */ // GIR_Coverage, 798, |
| 18189 | /* 49530 */ GIR_EraseRootFromParent_Done, |
| 18190 | /* 49531 */ // Label 1085: @49531 |
| 18191 | /* 49531 */ GIM_Try, /*On fail goto*//*Label 1086*/ GIMT_Encode4(49585), // Rule ID 799 // |
| 18192 | /* 49536 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 18193 | /* 49539 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhaddu), |
| 18194 | /* 49544 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 18195 | /* 49547 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 18196 | /* 49550 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 18197 | /* 49553 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18198 | /* 49557 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18199 | /* 49561 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18200 | /* 49565 */ // (intrinsic_wo_chain:{ *:[v2i32] } 3776:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VHADDuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 18201 | /* 49565 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHADDuv2i32), |
| 18202 | /* 49568 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 18203 | /* 49570 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 18204 | /* 49572 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 18205 | /* 49574 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18206 | /* 49577 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18207 | /* 49583 */ GIR_RootConstrainSelectedInstOperands, |
| 18208 | /* 49584 */ // GIR_Coverage, 799, |
| 18209 | /* 49584 */ GIR_EraseRootFromParent_Done, |
| 18210 | /* 49585 */ // Label 1086: @49585 |
| 18211 | /* 49585 */ GIM_Try, /*On fail goto*//*Label 1087*/ GIMT_Encode4(49639), // Rule ID 800 // |
| 18212 | /* 49590 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 18213 | /* 49593 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhaddu), |
| 18214 | /* 49598 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 18215 | /* 49601 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 18216 | /* 49604 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 18217 | /* 49607 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18218 | /* 49611 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18219 | /* 49615 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18220 | /* 49619 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3776:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VHADDuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 18221 | /* 49619 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHADDuv8i16), |
| 18222 | /* 49622 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 18223 | /* 49624 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 18224 | /* 49626 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 18225 | /* 49628 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18226 | /* 49631 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18227 | /* 49637 */ GIR_RootConstrainSelectedInstOperands, |
| 18228 | /* 49638 */ // GIR_Coverage, 800, |
| 18229 | /* 49638 */ GIR_EraseRootFromParent_Done, |
| 18230 | /* 49639 */ // Label 1087: @49639 |
| 18231 | /* 49639 */ GIM_Try, /*On fail goto*//*Label 1088*/ GIMT_Encode4(49693), // Rule ID 801 // |
| 18232 | /* 49644 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 18233 | /* 49647 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhaddu), |
| 18234 | /* 49652 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 18235 | /* 49655 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 18236 | /* 49658 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 18237 | /* 49661 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18238 | /* 49665 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18239 | /* 49669 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18240 | /* 49673 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3776:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VHADDuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 18241 | /* 49673 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHADDuv4i32), |
| 18242 | /* 49676 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 18243 | /* 49678 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 18244 | /* 49680 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 18245 | /* 49682 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18246 | /* 49685 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18247 | /* 49691 */ GIR_RootConstrainSelectedInstOperands, |
| 18248 | /* 49692 */ // GIR_Coverage, 801, |
| 18249 | /* 49692 */ GIR_EraseRootFromParent_Done, |
| 18250 | /* 49693 */ // Label 1088: @49693 |
| 18251 | /* 49693 */ GIM_Try, /*On fail goto*//*Label 1089*/ GIMT_Encode4(49747), // Rule ID 802 // |
| 18252 | /* 49698 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 18253 | /* 49701 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhaddu), |
| 18254 | /* 49706 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, |
| 18255 | /* 49709 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 18256 | /* 49712 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 18257 | /* 49715 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18258 | /* 49719 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18259 | /* 49723 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18260 | /* 49727 */ // (intrinsic_wo_chain:{ *:[v8i8] } 3776:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VHADDuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 18261 | /* 49727 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHADDuv8i8), |
| 18262 | /* 49730 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 18263 | /* 49732 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 18264 | /* 49734 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 18265 | /* 49736 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18266 | /* 49739 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18267 | /* 49745 */ GIR_RootConstrainSelectedInstOperands, |
| 18268 | /* 49746 */ // GIR_Coverage, 802, |
| 18269 | /* 49746 */ GIR_EraseRootFromParent_Done, |
| 18270 | /* 49747 */ // Label 1089: @49747 |
| 18271 | /* 49747 */ GIM_Try, /*On fail goto*//*Label 1090*/ GIMT_Encode4(49801), // Rule ID 803 // |
| 18272 | /* 49752 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 18273 | /* 49755 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhaddu), |
| 18274 | /* 49760 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 18275 | /* 49763 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 18276 | /* 49766 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 18277 | /* 49769 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18278 | /* 49773 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18279 | /* 49777 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18280 | /* 49781 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3776:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VHADDuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 18281 | /* 49781 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHADDuv16i8), |
| 18282 | /* 49784 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 18283 | /* 49786 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 18284 | /* 49788 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 18285 | /* 49790 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18286 | /* 49793 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18287 | /* 49799 */ GIR_RootConstrainSelectedInstOperands, |
| 18288 | /* 49800 */ // GIR_Coverage, 803, |
| 18289 | /* 49800 */ GIR_EraseRootFromParent_Done, |
| 18290 | /* 49801 */ // Label 1090: @49801 |
| 18291 | /* 49801 */ GIM_Try, /*On fail goto*//*Label 1091*/ GIMT_Encode4(49855), // Rule ID 804 // |
| 18292 | /* 49806 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 18293 | /* 49809 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrhadds), |
| 18294 | /* 49814 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 18295 | /* 49817 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 18296 | /* 49820 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 18297 | /* 49823 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18298 | /* 49827 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18299 | /* 49831 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18300 | /* 49835 */ // (intrinsic_wo_chain:{ *:[v4i16] } 3835:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VRHADDsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 18301 | /* 49835 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRHADDsv4i16), |
| 18302 | /* 49838 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 18303 | /* 49840 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 18304 | /* 49842 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 18305 | /* 49844 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18306 | /* 49847 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18307 | /* 49853 */ GIR_RootConstrainSelectedInstOperands, |
| 18308 | /* 49854 */ // GIR_Coverage, 804, |
| 18309 | /* 49854 */ GIR_EraseRootFromParent_Done, |
| 18310 | /* 49855 */ // Label 1091: @49855 |
| 18311 | /* 49855 */ GIM_Try, /*On fail goto*//*Label 1092*/ GIMT_Encode4(49909), // Rule ID 805 // |
| 18312 | /* 49860 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 18313 | /* 49863 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrhadds), |
| 18314 | /* 49868 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 18315 | /* 49871 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 18316 | /* 49874 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 18317 | /* 49877 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18318 | /* 49881 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18319 | /* 49885 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18320 | /* 49889 */ // (intrinsic_wo_chain:{ *:[v2i32] } 3835:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VRHADDsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 18321 | /* 49889 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRHADDsv2i32), |
| 18322 | /* 49892 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 18323 | /* 49894 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 18324 | /* 49896 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 18325 | /* 49898 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18326 | /* 49901 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18327 | /* 49907 */ GIR_RootConstrainSelectedInstOperands, |
| 18328 | /* 49908 */ // GIR_Coverage, 805, |
| 18329 | /* 49908 */ GIR_EraseRootFromParent_Done, |
| 18330 | /* 49909 */ // Label 1092: @49909 |
| 18331 | /* 49909 */ GIM_Try, /*On fail goto*//*Label 1093*/ GIMT_Encode4(49963), // Rule ID 806 // |
| 18332 | /* 49914 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 18333 | /* 49917 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrhadds), |
| 18334 | /* 49922 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 18335 | /* 49925 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 18336 | /* 49928 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 18337 | /* 49931 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18338 | /* 49935 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18339 | /* 49939 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18340 | /* 49943 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3835:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VRHADDsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 18341 | /* 49943 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRHADDsv8i16), |
| 18342 | /* 49946 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 18343 | /* 49948 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 18344 | /* 49950 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 18345 | /* 49952 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18346 | /* 49955 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18347 | /* 49961 */ GIR_RootConstrainSelectedInstOperands, |
| 18348 | /* 49962 */ // GIR_Coverage, 806, |
| 18349 | /* 49962 */ GIR_EraseRootFromParent_Done, |
| 18350 | /* 49963 */ // Label 1093: @49963 |
| 18351 | /* 49963 */ GIM_Try, /*On fail goto*//*Label 1094*/ GIMT_Encode4(50017), // Rule ID 807 // |
| 18352 | /* 49968 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 18353 | /* 49971 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrhadds), |
| 18354 | /* 49976 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 18355 | /* 49979 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 18356 | /* 49982 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 18357 | /* 49985 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18358 | /* 49989 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18359 | /* 49993 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18360 | /* 49997 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3835:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VRHADDsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 18361 | /* 49997 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRHADDsv4i32), |
| 18362 | /* 50000 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 18363 | /* 50002 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 18364 | /* 50004 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 18365 | /* 50006 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18366 | /* 50009 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18367 | /* 50015 */ GIR_RootConstrainSelectedInstOperands, |
| 18368 | /* 50016 */ // GIR_Coverage, 807, |
| 18369 | /* 50016 */ GIR_EraseRootFromParent_Done, |
| 18370 | /* 50017 */ // Label 1094: @50017 |
| 18371 | /* 50017 */ GIM_Try, /*On fail goto*//*Label 1095*/ GIMT_Encode4(50071), // Rule ID 808 // |
| 18372 | /* 50022 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 18373 | /* 50025 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrhadds), |
| 18374 | /* 50030 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, |
| 18375 | /* 50033 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 18376 | /* 50036 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 18377 | /* 50039 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18378 | /* 50043 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18379 | /* 50047 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18380 | /* 50051 */ // (intrinsic_wo_chain:{ *:[v8i8] } 3835:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VRHADDsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 18381 | /* 50051 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRHADDsv8i8), |
| 18382 | /* 50054 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 18383 | /* 50056 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 18384 | /* 50058 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 18385 | /* 50060 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18386 | /* 50063 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18387 | /* 50069 */ GIR_RootConstrainSelectedInstOperands, |
| 18388 | /* 50070 */ // GIR_Coverage, 808, |
| 18389 | /* 50070 */ GIR_EraseRootFromParent_Done, |
| 18390 | /* 50071 */ // Label 1095: @50071 |
| 18391 | /* 50071 */ GIM_Try, /*On fail goto*//*Label 1096*/ GIMT_Encode4(50125), // Rule ID 809 // |
| 18392 | /* 50076 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 18393 | /* 50079 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrhadds), |
| 18394 | /* 50084 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 18395 | /* 50087 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 18396 | /* 50090 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 18397 | /* 50093 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18398 | /* 50097 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18399 | /* 50101 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18400 | /* 50105 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3835:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VRHADDsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 18401 | /* 50105 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRHADDsv16i8), |
| 18402 | /* 50108 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 18403 | /* 50110 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 18404 | /* 50112 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 18405 | /* 50114 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18406 | /* 50117 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18407 | /* 50123 */ GIR_RootConstrainSelectedInstOperands, |
| 18408 | /* 50124 */ // GIR_Coverage, 809, |
| 18409 | /* 50124 */ GIR_EraseRootFromParent_Done, |
| 18410 | /* 50125 */ // Label 1096: @50125 |
| 18411 | /* 50125 */ GIM_Try, /*On fail goto*//*Label 1097*/ GIMT_Encode4(50179), // Rule ID 810 // |
| 18412 | /* 50130 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 18413 | /* 50133 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrhaddu), |
| 18414 | /* 50138 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 18415 | /* 50141 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 18416 | /* 50144 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 18417 | /* 50147 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18418 | /* 50151 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18419 | /* 50155 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18420 | /* 50159 */ // (intrinsic_wo_chain:{ *:[v4i16] } 3836:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VRHADDuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 18421 | /* 50159 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRHADDuv4i16), |
| 18422 | /* 50162 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 18423 | /* 50164 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 18424 | /* 50166 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 18425 | /* 50168 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18426 | /* 50171 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18427 | /* 50177 */ GIR_RootConstrainSelectedInstOperands, |
| 18428 | /* 50178 */ // GIR_Coverage, 810, |
| 18429 | /* 50178 */ GIR_EraseRootFromParent_Done, |
| 18430 | /* 50179 */ // Label 1097: @50179 |
| 18431 | /* 50179 */ GIM_Try, /*On fail goto*//*Label 1098*/ GIMT_Encode4(50233), // Rule ID 811 // |
| 18432 | /* 50184 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 18433 | /* 50187 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrhaddu), |
| 18434 | /* 50192 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 18435 | /* 50195 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 18436 | /* 50198 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 18437 | /* 50201 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18438 | /* 50205 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18439 | /* 50209 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18440 | /* 50213 */ // (intrinsic_wo_chain:{ *:[v2i32] } 3836:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VRHADDuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 18441 | /* 50213 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRHADDuv2i32), |
| 18442 | /* 50216 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 18443 | /* 50218 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 18444 | /* 50220 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 18445 | /* 50222 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18446 | /* 50225 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18447 | /* 50231 */ GIR_RootConstrainSelectedInstOperands, |
| 18448 | /* 50232 */ // GIR_Coverage, 811, |
| 18449 | /* 50232 */ GIR_EraseRootFromParent_Done, |
| 18450 | /* 50233 */ // Label 1098: @50233 |
| 18451 | /* 50233 */ GIM_Try, /*On fail goto*//*Label 1099*/ GIMT_Encode4(50287), // Rule ID 812 // |
| 18452 | /* 50238 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 18453 | /* 50241 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrhaddu), |
| 18454 | /* 50246 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 18455 | /* 50249 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 18456 | /* 50252 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 18457 | /* 50255 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18458 | /* 50259 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18459 | /* 50263 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18460 | /* 50267 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3836:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VRHADDuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 18461 | /* 50267 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRHADDuv8i16), |
| 18462 | /* 50270 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 18463 | /* 50272 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 18464 | /* 50274 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 18465 | /* 50276 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18466 | /* 50279 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18467 | /* 50285 */ GIR_RootConstrainSelectedInstOperands, |
| 18468 | /* 50286 */ // GIR_Coverage, 812, |
| 18469 | /* 50286 */ GIR_EraseRootFromParent_Done, |
| 18470 | /* 50287 */ // Label 1099: @50287 |
| 18471 | /* 50287 */ GIM_Try, /*On fail goto*//*Label 1100*/ GIMT_Encode4(50341), // Rule ID 813 // |
| 18472 | /* 50292 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 18473 | /* 50295 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrhaddu), |
| 18474 | /* 50300 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 18475 | /* 50303 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 18476 | /* 50306 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 18477 | /* 50309 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18478 | /* 50313 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18479 | /* 50317 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18480 | /* 50321 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3836:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VRHADDuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 18481 | /* 50321 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRHADDuv4i32), |
| 18482 | /* 50324 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 18483 | /* 50326 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 18484 | /* 50328 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 18485 | /* 50330 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18486 | /* 50333 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18487 | /* 50339 */ GIR_RootConstrainSelectedInstOperands, |
| 18488 | /* 50340 */ // GIR_Coverage, 813, |
| 18489 | /* 50340 */ GIR_EraseRootFromParent_Done, |
| 18490 | /* 50341 */ // Label 1100: @50341 |
| 18491 | /* 50341 */ GIM_Try, /*On fail goto*//*Label 1101*/ GIMT_Encode4(50395), // Rule ID 814 // |
| 18492 | /* 50346 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 18493 | /* 50349 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrhaddu), |
| 18494 | /* 50354 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, |
| 18495 | /* 50357 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 18496 | /* 50360 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 18497 | /* 50363 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18498 | /* 50367 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18499 | /* 50371 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18500 | /* 50375 */ // (intrinsic_wo_chain:{ *:[v8i8] } 3836:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VRHADDuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 18501 | /* 50375 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRHADDuv8i8), |
| 18502 | /* 50378 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 18503 | /* 50380 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 18504 | /* 50382 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 18505 | /* 50384 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18506 | /* 50387 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18507 | /* 50393 */ GIR_RootConstrainSelectedInstOperands, |
| 18508 | /* 50394 */ // GIR_Coverage, 814, |
| 18509 | /* 50394 */ GIR_EraseRootFromParent_Done, |
| 18510 | /* 50395 */ // Label 1101: @50395 |
| 18511 | /* 50395 */ GIM_Try, /*On fail goto*//*Label 1102*/ GIMT_Encode4(50449), // Rule ID 815 // |
| 18512 | /* 50400 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 18513 | /* 50403 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrhaddu), |
| 18514 | /* 50408 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 18515 | /* 50411 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 18516 | /* 50414 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 18517 | /* 50417 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18518 | /* 50421 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18519 | /* 50425 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18520 | /* 50429 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3836:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VRHADDuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 18521 | /* 50429 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRHADDuv16i8), |
| 18522 | /* 50432 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 18523 | /* 50434 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 18524 | /* 50436 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 18525 | /* 50438 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18526 | /* 50441 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18527 | /* 50447 */ GIR_RootConstrainSelectedInstOperands, |
| 18528 | /* 50448 */ // GIR_Coverage, 815, |
| 18529 | /* 50448 */ GIR_EraseRootFromParent_Done, |
| 18530 | /* 50449 */ // Label 1102: @50449 |
| 18531 | /* 50449 */ GIM_Try, /*On fail goto*//*Label 1103*/ GIMT_Encode4(50503), // Rule ID 832 // |
| 18532 | /* 50454 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 18533 | /* 50457 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vraddhn), |
| 18534 | /* 50462 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, |
| 18535 | /* 50465 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 18536 | /* 50468 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 18537 | /* 50471 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18538 | /* 50475 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18539 | /* 50479 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18540 | /* 50483 */ // (intrinsic_wo_chain:{ *:[v8i8] } 3832:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VRADDHNv8i8:{ *:[v8i8] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 18541 | /* 50483 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRADDHNv8i8), |
| 18542 | /* 50486 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 18543 | /* 50488 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 18544 | /* 50490 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 18545 | /* 50492 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18546 | /* 50495 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18547 | /* 50501 */ GIR_RootConstrainSelectedInstOperands, |
| 18548 | /* 50502 */ // GIR_Coverage, 832, |
| 18549 | /* 50502 */ GIR_EraseRootFromParent_Done, |
| 18550 | /* 50503 */ // Label 1103: @50503 |
| 18551 | /* 50503 */ GIM_Try, /*On fail goto*//*Label 1104*/ GIMT_Encode4(50557), // Rule ID 833 // |
| 18552 | /* 50508 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 18553 | /* 50511 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vraddhn), |
| 18554 | /* 50516 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 18555 | /* 50519 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 18556 | /* 50522 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 18557 | /* 50525 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18558 | /* 50529 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18559 | /* 50533 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18560 | /* 50537 */ // (intrinsic_wo_chain:{ *:[v4i16] } 3832:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VRADDHNv4i16:{ *:[v4i16] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 18561 | /* 50537 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRADDHNv4i16), |
| 18562 | /* 50540 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 18563 | /* 50542 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 18564 | /* 50544 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 18565 | /* 50546 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18566 | /* 50549 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18567 | /* 50555 */ GIR_RootConstrainSelectedInstOperands, |
| 18568 | /* 50556 */ // GIR_Coverage, 833, |
| 18569 | /* 50556 */ GIR_EraseRootFromParent_Done, |
| 18570 | /* 50557 */ // Label 1104: @50557 |
| 18571 | /* 50557 */ GIM_Try, /*On fail goto*//*Label 1105*/ GIMT_Encode4(50611), // Rule ID 834 // |
| 18572 | /* 50562 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 18573 | /* 50565 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vraddhn), |
| 18574 | /* 50570 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 18575 | /* 50573 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 18576 | /* 50576 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 18577 | /* 50579 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18578 | /* 50583 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18579 | /* 50587 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18580 | /* 50591 */ // (intrinsic_wo_chain:{ *:[v2i32] } 3832:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) => (VRADDHNv2i32:{ *:[v2i32] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) |
| 18581 | /* 50591 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRADDHNv2i32), |
| 18582 | /* 50594 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 18583 | /* 50596 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 18584 | /* 50598 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 18585 | /* 50600 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18586 | /* 50603 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18587 | /* 50609 */ GIR_RootConstrainSelectedInstOperands, |
| 18588 | /* 50610 */ // GIR_Coverage, 834, |
| 18589 | /* 50610 */ GIR_EraseRootFromParent_Done, |
| 18590 | /* 50611 */ // Label 1105: @50611 |
| 18591 | /* 50611 */ GIM_Try, /*On fail goto*//*Label 1106*/ GIMT_Encode4(50665), // Rule ID 841 // |
| 18592 | /* 50616 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 18593 | /* 50619 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vmulp), |
| 18594 | /* 50624 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, |
| 18595 | /* 50627 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 18596 | /* 50630 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 18597 | /* 50633 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18598 | /* 50637 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18599 | /* 50641 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18600 | /* 50645 */ // (intrinsic_wo_chain:{ *:[v8i8] } 3801:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VMULpd:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 18601 | /* 50645 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULpd), |
| 18602 | /* 50648 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 18603 | /* 50650 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 18604 | /* 50652 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 18605 | /* 50654 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18606 | /* 50657 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18607 | /* 50663 */ GIR_RootConstrainSelectedInstOperands, |
| 18608 | /* 50664 */ // GIR_Coverage, 841, |
| 18609 | /* 50664 */ GIR_EraseRootFromParent_Done, |
| 18610 | /* 50665 */ // Label 1106: @50665 |
| 18611 | /* 50665 */ GIM_Try, /*On fail goto*//*Label 1107*/ GIMT_Encode4(50719), // Rule ID 842 // |
| 18612 | /* 50670 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 18613 | /* 50673 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vmulp), |
| 18614 | /* 50678 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 18615 | /* 50681 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 18616 | /* 50684 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 18617 | /* 50687 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18618 | /* 50691 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18619 | /* 50695 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18620 | /* 50699 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3801:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VMULpq:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 18621 | /* 50699 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULpq), |
| 18622 | /* 50702 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 18623 | /* 50704 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 18624 | /* 50706 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 18625 | /* 50708 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18626 | /* 50711 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18627 | /* 50717 */ GIR_RootConstrainSelectedInstOperands, |
| 18628 | /* 50718 */ // GIR_Coverage, 842, |
| 18629 | /* 50718 */ GIR_EraseRootFromParent_Done, |
| 18630 | /* 50719 */ // Label 1107: @50719 |
| 18631 | /* 50719 */ GIM_Try, /*On fail goto*//*Label 1108*/ GIMT_Encode4(50773), // Rule ID 855 // |
| 18632 | /* 50724 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 18633 | /* 50727 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqdmulh), |
| 18634 | /* 50732 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 18635 | /* 50735 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 18636 | /* 50738 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 18637 | /* 50741 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18638 | /* 50745 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18639 | /* 50749 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18640 | /* 50753 */ // (intrinsic_wo_chain:{ *:[v4i16] } 3812:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VQDMULHv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 18641 | /* 50753 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQDMULHv4i16), |
| 18642 | /* 50756 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 18643 | /* 50758 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 18644 | /* 50760 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 18645 | /* 50762 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18646 | /* 50765 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18647 | /* 50771 */ GIR_RootConstrainSelectedInstOperands, |
| 18648 | /* 50772 */ // GIR_Coverage, 855, |
| 18649 | /* 50772 */ GIR_EraseRootFromParent_Done, |
| 18650 | /* 50773 */ // Label 1108: @50773 |
| 18651 | /* 50773 */ GIM_Try, /*On fail goto*//*Label 1109*/ GIMT_Encode4(50827), // Rule ID 856 // |
| 18652 | /* 50778 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 18653 | /* 50781 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqdmulh), |
| 18654 | /* 50786 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 18655 | /* 50789 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 18656 | /* 50792 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 18657 | /* 50795 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18658 | /* 50799 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18659 | /* 50803 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18660 | /* 50807 */ // (intrinsic_wo_chain:{ *:[v2i32] } 3812:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VQDMULHv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 18661 | /* 50807 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQDMULHv2i32), |
| 18662 | /* 50810 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 18663 | /* 50812 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 18664 | /* 50814 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 18665 | /* 50816 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18666 | /* 50819 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18667 | /* 50825 */ GIR_RootConstrainSelectedInstOperands, |
| 18668 | /* 50826 */ // GIR_Coverage, 856, |
| 18669 | /* 50826 */ GIR_EraseRootFromParent_Done, |
| 18670 | /* 50827 */ // Label 1109: @50827 |
| 18671 | /* 50827 */ GIM_Try, /*On fail goto*//*Label 1110*/ GIMT_Encode4(50881), // Rule ID 857 // |
| 18672 | /* 50832 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 18673 | /* 50835 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqdmulh), |
| 18674 | /* 50840 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 18675 | /* 50843 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 18676 | /* 50846 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 18677 | /* 50849 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18678 | /* 50853 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18679 | /* 50857 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18680 | /* 50861 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3812:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VQDMULHv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 18681 | /* 50861 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQDMULHv8i16), |
| 18682 | /* 50864 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 18683 | /* 50866 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 18684 | /* 50868 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 18685 | /* 50870 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18686 | /* 50873 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18687 | /* 50879 */ GIR_RootConstrainSelectedInstOperands, |
| 18688 | /* 50880 */ // GIR_Coverage, 857, |
| 18689 | /* 50880 */ GIR_EraseRootFromParent_Done, |
| 18690 | /* 50881 */ // Label 1110: @50881 |
| 18691 | /* 50881 */ GIM_Try, /*On fail goto*//*Label 1111*/ GIMT_Encode4(50935), // Rule ID 858 // |
| 18692 | /* 50886 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 18693 | /* 50889 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqdmulh), |
| 18694 | /* 50894 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 18695 | /* 50897 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 18696 | /* 50900 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 18697 | /* 50903 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18698 | /* 50907 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18699 | /* 50911 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18700 | /* 50915 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3812:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VQDMULHv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 18701 | /* 50915 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQDMULHv4i32), |
| 18702 | /* 50918 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 18703 | /* 50920 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 18704 | /* 50922 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 18705 | /* 50924 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18706 | /* 50927 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18707 | /* 50933 */ GIR_RootConstrainSelectedInstOperands, |
| 18708 | /* 50934 */ // GIR_Coverage, 858, |
| 18709 | /* 50934 */ GIR_EraseRootFromParent_Done, |
| 18710 | /* 50935 */ // Label 1111: @50935 |
| 18711 | /* 50935 */ GIM_Try, /*On fail goto*//*Label 1112*/ GIMT_Encode4(50989), // Rule ID 863 // |
| 18712 | /* 50940 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 18713 | /* 50943 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrdmulh), |
| 18714 | /* 50948 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 18715 | /* 50951 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 18716 | /* 50954 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 18717 | /* 50957 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18718 | /* 50961 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18719 | /* 50965 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18720 | /* 50969 */ // (intrinsic_wo_chain:{ *:[v4i16] } 3820:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VQRDMULHv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 18721 | /* 50969 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRDMULHv4i16), |
| 18722 | /* 50972 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 18723 | /* 50974 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 18724 | /* 50976 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 18725 | /* 50978 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18726 | /* 50981 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18727 | /* 50987 */ GIR_RootConstrainSelectedInstOperands, |
| 18728 | /* 50988 */ // GIR_Coverage, 863, |
| 18729 | /* 50988 */ GIR_EraseRootFromParent_Done, |
| 18730 | /* 50989 */ // Label 1112: @50989 |
| 18731 | /* 50989 */ GIM_Try, /*On fail goto*//*Label 1113*/ GIMT_Encode4(51043), // Rule ID 864 // |
| 18732 | /* 50994 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 18733 | /* 50997 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrdmulh), |
| 18734 | /* 51002 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 18735 | /* 51005 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 18736 | /* 51008 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 18737 | /* 51011 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18738 | /* 51015 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18739 | /* 51019 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18740 | /* 51023 */ // (intrinsic_wo_chain:{ *:[v2i32] } 3820:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VQRDMULHv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 18741 | /* 51023 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRDMULHv2i32), |
| 18742 | /* 51026 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 18743 | /* 51028 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 18744 | /* 51030 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 18745 | /* 51032 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18746 | /* 51035 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18747 | /* 51041 */ GIR_RootConstrainSelectedInstOperands, |
| 18748 | /* 51042 */ // GIR_Coverage, 864, |
| 18749 | /* 51042 */ GIR_EraseRootFromParent_Done, |
| 18750 | /* 51043 */ // Label 1113: @51043 |
| 18751 | /* 51043 */ GIM_Try, /*On fail goto*//*Label 1114*/ GIMT_Encode4(51097), // Rule ID 865 // |
| 18752 | /* 51048 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 18753 | /* 51051 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrdmulh), |
| 18754 | /* 51056 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 18755 | /* 51059 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 18756 | /* 51062 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 18757 | /* 51065 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18758 | /* 51069 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18759 | /* 51073 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18760 | /* 51077 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3820:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VQRDMULHv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 18761 | /* 51077 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRDMULHv8i16), |
| 18762 | /* 51080 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 18763 | /* 51082 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 18764 | /* 51084 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 18765 | /* 51086 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18766 | /* 51089 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18767 | /* 51095 */ GIR_RootConstrainSelectedInstOperands, |
| 18768 | /* 51096 */ // GIR_Coverage, 865, |
| 18769 | /* 51096 */ GIR_EraseRootFromParent_Done, |
| 18770 | /* 51097 */ // Label 1114: @51097 |
| 18771 | /* 51097 */ GIM_Try, /*On fail goto*//*Label 1115*/ GIMT_Encode4(51151), // Rule ID 866 // |
| 18772 | /* 51102 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 18773 | /* 51105 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrdmulh), |
| 18774 | /* 51110 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 18775 | /* 51113 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 18776 | /* 51116 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 18777 | /* 51119 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18778 | /* 51123 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18779 | /* 51127 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18780 | /* 51131 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3820:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VQRDMULHv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 18781 | /* 51131 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRDMULHv4i32), |
| 18782 | /* 51134 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 18783 | /* 51136 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 18784 | /* 51138 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 18785 | /* 51140 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18786 | /* 51143 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18787 | /* 51149 */ GIR_RootConstrainSelectedInstOperands, |
| 18788 | /* 51150 */ // GIR_Coverage, 866, |
| 18789 | /* 51150 */ GIR_EraseRootFromParent_Done, |
| 18790 | /* 51151 */ // Label 1115: @51151 |
| 18791 | /* 51151 */ GIM_Try, /*On fail goto*//*Label 1116*/ GIMT_Encode4(51205), // Rule ID 877 // |
| 18792 | /* 51156 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 18793 | /* 51159 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vmullp), |
| 18794 | /* 51164 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 18795 | /* 51167 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 18796 | /* 51170 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 18797 | /* 51173 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18798 | /* 51177 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18799 | /* 51181 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18800 | /* 51185 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3798:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VMULLp8:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 18801 | /* 51185 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULLp8), |
| 18802 | /* 51188 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 18803 | /* 51190 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 18804 | /* 51192 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 18805 | /* 51194 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18806 | /* 51197 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18807 | /* 51203 */ GIR_RootConstrainSelectedInstOperands, |
| 18808 | /* 51204 */ // GIR_Coverage, 877, |
| 18809 | /* 51204 */ GIR_EraseRootFromParent_Done, |
| 18810 | /* 51205 */ // Label 1116: @51205 |
| 18811 | /* 51205 */ GIM_Try, /*On fail goto*//*Label 1117*/ GIMT_Encode4(51250), // Rule ID 878 // |
| 18812 | /* 51210 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAES_HasV8), |
| 18813 | /* 51213 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vmullp), |
| 18814 | /* 51218 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 18815 | /* 51221 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 18816 | /* 51224 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 18817 | /* 51227 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18818 | /* 51231 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18819 | /* 51235 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18820 | /* 51239 */ // (intrinsic_wo_chain:{ *:[v2i64] } 3798:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) => (VMULLp64:{ *:[v2i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) |
| 18821 | /* 51239 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULLp64), |
| 18822 | /* 51242 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 18823 | /* 51244 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 18824 | /* 51246 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 18825 | /* 51248 */ GIR_RootConstrainSelectedInstOperands, |
| 18826 | /* 51249 */ // GIR_Coverage, 878, |
| 18827 | /* 51249 */ GIR_EraseRootFromParent_Done, |
| 18828 | /* 51250 */ // Label 1117: @51250 |
| 18829 | /* 51250 */ GIM_Try, /*On fail goto*//*Label 1118*/ GIMT_Encode4(51304), // Rule ID 883 // |
| 18830 | /* 51255 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 18831 | /* 51258 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqdmull), |
| 18832 | /* 51263 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 18833 | /* 51266 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 18834 | /* 51269 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 18835 | /* 51272 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18836 | /* 51276 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18837 | /* 51280 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18838 | /* 51284 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3813:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VQDMULLv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 18839 | /* 51284 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQDMULLv4i32), |
| 18840 | /* 51287 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 18841 | /* 51289 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 18842 | /* 51291 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 18843 | /* 51293 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18844 | /* 51296 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18845 | /* 51302 */ GIR_RootConstrainSelectedInstOperands, |
| 18846 | /* 51303 */ // GIR_Coverage, 883, |
| 18847 | /* 51303 */ GIR_EraseRootFromParent_Done, |
| 18848 | /* 51304 */ // Label 1118: @51304 |
| 18849 | /* 51304 */ GIM_Try, /*On fail goto*//*Label 1119*/ GIMT_Encode4(51358), // Rule ID 884 // |
| 18850 | /* 51309 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 18851 | /* 51312 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqdmull), |
| 18852 | /* 51317 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 18853 | /* 51320 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 18854 | /* 51323 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 18855 | /* 51326 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18856 | /* 51330 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18857 | /* 51334 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18858 | /* 51338 */ // (intrinsic_wo_chain:{ *:[v2i64] } 3813:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VQDMULLv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 18859 | /* 51338 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQDMULLv2i64), |
| 18860 | /* 51341 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 18861 | /* 51343 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 18862 | /* 51345 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 18863 | /* 51347 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18864 | /* 51350 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18865 | /* 51356 */ GIR_RootConstrainSelectedInstOperands, |
| 18866 | /* 51357 */ // GIR_Coverage, 884, |
| 18867 | /* 51357 */ GIR_EraseRootFromParent_Done, |
| 18868 | /* 51358 */ // Label 1119: @51358 |
| 18869 | /* 51358 */ GIM_Try, /*On fail goto*//*Label 1120*/ GIMT_Encode4(51412), // Rule ID 996 // |
| 18870 | /* 51363 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 18871 | /* 51366 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhsubs), |
| 18872 | /* 51371 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 18873 | /* 51374 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 18874 | /* 51377 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 18875 | /* 51380 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18876 | /* 51384 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18877 | /* 51388 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18878 | /* 51392 */ // (intrinsic_wo_chain:{ *:[v4i16] } 3777:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VHSUBsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 18879 | /* 51392 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHSUBsv4i16), |
| 18880 | /* 51395 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 18881 | /* 51397 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 18882 | /* 51399 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 18883 | /* 51401 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18884 | /* 51404 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18885 | /* 51410 */ GIR_RootConstrainSelectedInstOperands, |
| 18886 | /* 51411 */ // GIR_Coverage, 996, |
| 18887 | /* 51411 */ GIR_EraseRootFromParent_Done, |
| 18888 | /* 51412 */ // Label 1120: @51412 |
| 18889 | /* 51412 */ GIM_Try, /*On fail goto*//*Label 1121*/ GIMT_Encode4(51466), // Rule ID 997 // |
| 18890 | /* 51417 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 18891 | /* 51420 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhsubs), |
| 18892 | /* 51425 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 18893 | /* 51428 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 18894 | /* 51431 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 18895 | /* 51434 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18896 | /* 51438 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18897 | /* 51442 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18898 | /* 51446 */ // (intrinsic_wo_chain:{ *:[v2i32] } 3777:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VHSUBsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 18899 | /* 51446 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHSUBsv2i32), |
| 18900 | /* 51449 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 18901 | /* 51451 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 18902 | /* 51453 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 18903 | /* 51455 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18904 | /* 51458 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18905 | /* 51464 */ GIR_RootConstrainSelectedInstOperands, |
| 18906 | /* 51465 */ // GIR_Coverage, 997, |
| 18907 | /* 51465 */ GIR_EraseRootFromParent_Done, |
| 18908 | /* 51466 */ // Label 1121: @51466 |
| 18909 | /* 51466 */ GIM_Try, /*On fail goto*//*Label 1122*/ GIMT_Encode4(51520), // Rule ID 998 // |
| 18910 | /* 51471 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 18911 | /* 51474 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhsubs), |
| 18912 | /* 51479 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 18913 | /* 51482 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 18914 | /* 51485 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 18915 | /* 51488 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18916 | /* 51492 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18917 | /* 51496 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18918 | /* 51500 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3777:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VHSUBsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 18919 | /* 51500 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHSUBsv8i16), |
| 18920 | /* 51503 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 18921 | /* 51505 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 18922 | /* 51507 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 18923 | /* 51509 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18924 | /* 51512 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18925 | /* 51518 */ GIR_RootConstrainSelectedInstOperands, |
| 18926 | /* 51519 */ // GIR_Coverage, 998, |
| 18927 | /* 51519 */ GIR_EraseRootFromParent_Done, |
| 18928 | /* 51520 */ // Label 1122: @51520 |
| 18929 | /* 51520 */ GIM_Try, /*On fail goto*//*Label 1123*/ GIMT_Encode4(51574), // Rule ID 999 // |
| 18930 | /* 51525 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 18931 | /* 51528 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhsubs), |
| 18932 | /* 51533 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 18933 | /* 51536 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 18934 | /* 51539 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 18935 | /* 51542 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18936 | /* 51546 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18937 | /* 51550 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18938 | /* 51554 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3777:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VHSUBsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 18939 | /* 51554 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHSUBsv4i32), |
| 18940 | /* 51557 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 18941 | /* 51559 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 18942 | /* 51561 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 18943 | /* 51563 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18944 | /* 51566 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18945 | /* 51572 */ GIR_RootConstrainSelectedInstOperands, |
| 18946 | /* 51573 */ // GIR_Coverage, 999, |
| 18947 | /* 51573 */ GIR_EraseRootFromParent_Done, |
| 18948 | /* 51574 */ // Label 1123: @51574 |
| 18949 | /* 51574 */ GIM_Try, /*On fail goto*//*Label 1124*/ GIMT_Encode4(51628), // Rule ID 1000 // |
| 18950 | /* 51579 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 18951 | /* 51582 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhsubs), |
| 18952 | /* 51587 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, |
| 18953 | /* 51590 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 18954 | /* 51593 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 18955 | /* 51596 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18956 | /* 51600 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18957 | /* 51604 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18958 | /* 51608 */ // (intrinsic_wo_chain:{ *:[v8i8] } 3777:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VHSUBsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 18959 | /* 51608 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHSUBsv8i8), |
| 18960 | /* 51611 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 18961 | /* 51613 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 18962 | /* 51615 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 18963 | /* 51617 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18964 | /* 51620 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18965 | /* 51626 */ GIR_RootConstrainSelectedInstOperands, |
| 18966 | /* 51627 */ // GIR_Coverage, 1000, |
| 18967 | /* 51627 */ GIR_EraseRootFromParent_Done, |
| 18968 | /* 51628 */ // Label 1124: @51628 |
| 18969 | /* 51628 */ GIM_Try, /*On fail goto*//*Label 1125*/ GIMT_Encode4(51682), // Rule ID 1001 // |
| 18970 | /* 51633 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 18971 | /* 51636 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhsubs), |
| 18972 | /* 51641 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 18973 | /* 51644 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 18974 | /* 51647 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 18975 | /* 51650 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18976 | /* 51654 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18977 | /* 51658 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 18978 | /* 51662 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3777:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VHSUBsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 18979 | /* 51662 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHSUBsv16i8), |
| 18980 | /* 51665 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 18981 | /* 51667 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 18982 | /* 51669 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 18983 | /* 51671 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18984 | /* 51674 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18985 | /* 51680 */ GIR_RootConstrainSelectedInstOperands, |
| 18986 | /* 51681 */ // GIR_Coverage, 1001, |
| 18987 | /* 51681 */ GIR_EraseRootFromParent_Done, |
| 18988 | /* 51682 */ // Label 1125: @51682 |
| 18989 | /* 51682 */ GIM_Try, /*On fail goto*//*Label 1126*/ GIMT_Encode4(51736), // Rule ID 1002 // |
| 18990 | /* 51687 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 18991 | /* 51690 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhsubu), |
| 18992 | /* 51695 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 18993 | /* 51698 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 18994 | /* 51701 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 18995 | /* 51704 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18996 | /* 51708 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18997 | /* 51712 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 18998 | /* 51716 */ // (intrinsic_wo_chain:{ *:[v4i16] } 3778:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VHSUBuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 18999 | /* 51716 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHSUBuv4i16), |
| 19000 | /* 51719 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19001 | /* 51721 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19002 | /* 51723 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19003 | /* 51725 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19004 | /* 51728 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19005 | /* 51734 */ GIR_RootConstrainSelectedInstOperands, |
| 19006 | /* 51735 */ // GIR_Coverage, 1002, |
| 19007 | /* 51735 */ GIR_EraseRootFromParent_Done, |
| 19008 | /* 51736 */ // Label 1126: @51736 |
| 19009 | /* 51736 */ GIM_Try, /*On fail goto*//*Label 1127*/ GIMT_Encode4(51790), // Rule ID 1003 // |
| 19010 | /* 51741 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 19011 | /* 51744 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhsubu), |
| 19012 | /* 51749 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 19013 | /* 51752 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 19014 | /* 51755 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 19015 | /* 51758 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19016 | /* 51762 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19017 | /* 51766 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19018 | /* 51770 */ // (intrinsic_wo_chain:{ *:[v2i32] } 3778:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VHSUBuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 19019 | /* 51770 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHSUBuv2i32), |
| 19020 | /* 51773 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19021 | /* 51775 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19022 | /* 51777 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19023 | /* 51779 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19024 | /* 51782 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19025 | /* 51788 */ GIR_RootConstrainSelectedInstOperands, |
| 19026 | /* 51789 */ // GIR_Coverage, 1003, |
| 19027 | /* 51789 */ GIR_EraseRootFromParent_Done, |
| 19028 | /* 51790 */ // Label 1127: @51790 |
| 19029 | /* 51790 */ GIM_Try, /*On fail goto*//*Label 1128*/ GIMT_Encode4(51844), // Rule ID 1004 // |
| 19030 | /* 51795 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 19031 | /* 51798 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhsubu), |
| 19032 | /* 51803 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 19033 | /* 51806 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 19034 | /* 51809 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 19035 | /* 51812 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19036 | /* 51816 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19037 | /* 51820 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19038 | /* 51824 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3778:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VHSUBuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 19039 | /* 51824 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHSUBuv8i16), |
| 19040 | /* 51827 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19041 | /* 51829 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19042 | /* 51831 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19043 | /* 51833 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19044 | /* 51836 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19045 | /* 51842 */ GIR_RootConstrainSelectedInstOperands, |
| 19046 | /* 51843 */ // GIR_Coverage, 1004, |
| 19047 | /* 51843 */ GIR_EraseRootFromParent_Done, |
| 19048 | /* 51844 */ // Label 1128: @51844 |
| 19049 | /* 51844 */ GIM_Try, /*On fail goto*//*Label 1129*/ GIMT_Encode4(51898), // Rule ID 1005 // |
| 19050 | /* 51849 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 19051 | /* 51852 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhsubu), |
| 19052 | /* 51857 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 19053 | /* 51860 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 19054 | /* 51863 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 19055 | /* 51866 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19056 | /* 51870 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19057 | /* 51874 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19058 | /* 51878 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3778:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VHSUBuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 19059 | /* 51878 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHSUBuv4i32), |
| 19060 | /* 51881 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19061 | /* 51883 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19062 | /* 51885 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19063 | /* 51887 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19064 | /* 51890 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19065 | /* 51896 */ GIR_RootConstrainSelectedInstOperands, |
| 19066 | /* 51897 */ // GIR_Coverage, 1005, |
| 19067 | /* 51897 */ GIR_EraseRootFromParent_Done, |
| 19068 | /* 51898 */ // Label 1129: @51898 |
| 19069 | /* 51898 */ GIM_Try, /*On fail goto*//*Label 1130*/ GIMT_Encode4(51952), // Rule ID 1006 // |
| 19070 | /* 51903 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 19071 | /* 51906 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhsubu), |
| 19072 | /* 51911 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, |
| 19073 | /* 51914 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 19074 | /* 51917 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 19075 | /* 51920 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19076 | /* 51924 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19077 | /* 51928 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19078 | /* 51932 */ // (intrinsic_wo_chain:{ *:[v8i8] } 3778:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VHSUBuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 19079 | /* 51932 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHSUBuv8i8), |
| 19080 | /* 51935 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19081 | /* 51937 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19082 | /* 51939 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19083 | /* 51941 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19084 | /* 51944 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19085 | /* 51950 */ GIR_RootConstrainSelectedInstOperands, |
| 19086 | /* 51951 */ // GIR_Coverage, 1006, |
| 19087 | /* 51951 */ GIR_EraseRootFromParent_Done, |
| 19088 | /* 51952 */ // Label 1130: @51952 |
| 19089 | /* 51952 */ GIM_Try, /*On fail goto*//*Label 1131*/ GIMT_Encode4(52006), // Rule ID 1007 // |
| 19090 | /* 51957 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 19091 | /* 51960 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhsubu), |
| 19092 | /* 51965 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 19093 | /* 51968 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 19094 | /* 51971 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 19095 | /* 51974 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19096 | /* 51978 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19097 | /* 51982 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19098 | /* 51986 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3778:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VHSUBuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 19099 | /* 51986 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHSUBuv16i8), |
| 19100 | /* 51989 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19101 | /* 51991 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19102 | /* 51993 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19103 | /* 51995 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19104 | /* 51998 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19105 | /* 52004 */ GIR_RootConstrainSelectedInstOperands, |
| 19106 | /* 52005 */ // GIR_Coverage, 1007, |
| 19107 | /* 52005 */ GIR_EraseRootFromParent_Done, |
| 19108 | /* 52006 */ // Label 1131: @52006 |
| 19109 | /* 52006 */ GIM_Try, /*On fail goto*//*Label 1132*/ GIMT_Encode4(52060), // Rule ID 1024 // |
| 19110 | /* 52011 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 19111 | /* 52014 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrsubhn), |
| 19112 | /* 52019 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, |
| 19113 | /* 52022 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 19114 | /* 52025 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 19115 | /* 52028 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19116 | /* 52032 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19117 | /* 52036 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19118 | /* 52040 */ // (intrinsic_wo_chain:{ *:[v8i8] } 3843:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VRSUBHNv8i8:{ *:[v8i8] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 19119 | /* 52040 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSUBHNv8i8), |
| 19120 | /* 52043 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19121 | /* 52045 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19122 | /* 52047 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19123 | /* 52049 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19124 | /* 52052 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19125 | /* 52058 */ GIR_RootConstrainSelectedInstOperands, |
| 19126 | /* 52059 */ // GIR_Coverage, 1024, |
| 19127 | /* 52059 */ GIR_EraseRootFromParent_Done, |
| 19128 | /* 52060 */ // Label 1132: @52060 |
| 19129 | /* 52060 */ GIM_Try, /*On fail goto*//*Label 1133*/ GIMT_Encode4(52114), // Rule ID 1025 // |
| 19130 | /* 52065 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 19131 | /* 52068 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrsubhn), |
| 19132 | /* 52073 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 19133 | /* 52076 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 19134 | /* 52079 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 19135 | /* 52082 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19136 | /* 52086 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19137 | /* 52090 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19138 | /* 52094 */ // (intrinsic_wo_chain:{ *:[v4i16] } 3843:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VRSUBHNv4i16:{ *:[v4i16] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 19139 | /* 52094 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSUBHNv4i16), |
| 19140 | /* 52097 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19141 | /* 52099 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19142 | /* 52101 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19143 | /* 52103 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19144 | /* 52106 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19145 | /* 52112 */ GIR_RootConstrainSelectedInstOperands, |
| 19146 | /* 52113 */ // GIR_Coverage, 1025, |
| 19147 | /* 52113 */ GIR_EraseRootFromParent_Done, |
| 19148 | /* 52114 */ // Label 1133: @52114 |
| 19149 | /* 52114 */ GIM_Try, /*On fail goto*//*Label 1134*/ GIMT_Encode4(52168), // Rule ID 1026 // |
| 19150 | /* 52119 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 19151 | /* 52122 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrsubhn), |
| 19152 | /* 52127 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 19153 | /* 52130 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 19154 | /* 52133 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 19155 | /* 52136 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19156 | /* 52140 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19157 | /* 52144 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19158 | /* 52148 */ // (intrinsic_wo_chain:{ *:[v2i32] } 3843:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) => (VRSUBHNv2i32:{ *:[v2i32] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) |
| 19159 | /* 52148 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSUBHNv2i32), |
| 19160 | /* 52151 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19161 | /* 52153 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19162 | /* 52155 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19163 | /* 52157 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19164 | /* 52160 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19165 | /* 52166 */ GIR_RootConstrainSelectedInstOperands, |
| 19166 | /* 52167 */ // GIR_Coverage, 1026, |
| 19167 | /* 52167 */ GIR_EraseRootFromParent_Done, |
| 19168 | /* 52168 */ // Label 1134: @52168 |
| 19169 | /* 52168 */ GIM_Try, /*On fail goto*//*Label 1135*/ GIMT_Encode4(52222), // Rule ID 1119 // |
| 19170 | /* 52173 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 19171 | /* 52176 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vacge), |
| 19172 | /* 52181 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 19173 | /* 52184 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 19174 | /* 52187 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 19175 | /* 52190 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19176 | /* 52194 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19177 | /* 52198 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19178 | /* 52202 */ // (intrinsic_wo_chain:{ *:[v2i32] } 3753:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VACGEfd:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) |
| 19179 | /* 52202 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VACGEfd), |
| 19180 | /* 52205 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19181 | /* 52207 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19182 | /* 52209 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19183 | /* 52211 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19184 | /* 52214 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19185 | /* 52220 */ GIR_RootConstrainSelectedInstOperands, |
| 19186 | /* 52221 */ // GIR_Coverage, 1119, |
| 19187 | /* 52221 */ GIR_EraseRootFromParent_Done, |
| 19188 | /* 52222 */ // Label 1135: @52222 |
| 19189 | /* 52222 */ GIM_Try, /*On fail goto*//*Label 1136*/ GIMT_Encode4(52276), // Rule ID 1120 // |
| 19190 | /* 52227 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 19191 | /* 52230 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vacge), |
| 19192 | /* 52235 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 19193 | /* 52238 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 19194 | /* 52241 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 19195 | /* 52244 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19196 | /* 52248 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19197 | /* 52252 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19198 | /* 52256 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3753:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (VACGEfq:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) |
| 19199 | /* 52256 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VACGEfq), |
| 19200 | /* 52259 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19201 | /* 52261 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19202 | /* 52263 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19203 | /* 52265 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19204 | /* 52268 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19205 | /* 52274 */ GIR_RootConstrainSelectedInstOperands, |
| 19206 | /* 52275 */ // GIR_Coverage, 1120, |
| 19207 | /* 52275 */ GIR_EraseRootFromParent_Done, |
| 19208 | /* 52276 */ // Label 1136: @52276 |
| 19209 | /* 52276 */ GIM_Try, /*On fail goto*//*Label 1137*/ GIMT_Encode4(52330), // Rule ID 1121 // |
| 19210 | /* 52281 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 19211 | /* 52284 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vacge), |
| 19212 | /* 52289 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 19213 | /* 52292 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 19214 | /* 52295 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 19215 | /* 52298 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19216 | /* 52302 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19217 | /* 52306 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19218 | /* 52310 */ // (intrinsic_wo_chain:{ *:[v4i16] } 3753:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VACGEhd:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) |
| 19219 | /* 52310 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VACGEhd), |
| 19220 | /* 52313 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19221 | /* 52315 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19222 | /* 52317 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19223 | /* 52319 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19224 | /* 52322 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19225 | /* 52328 */ GIR_RootConstrainSelectedInstOperands, |
| 19226 | /* 52329 */ // GIR_Coverage, 1121, |
| 19227 | /* 52329 */ GIR_EraseRootFromParent_Done, |
| 19228 | /* 52330 */ // Label 1137: @52330 |
| 19229 | /* 52330 */ GIM_Try, /*On fail goto*//*Label 1138*/ GIMT_Encode4(52384), // Rule ID 1122 // |
| 19230 | /* 52335 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 19231 | /* 52338 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vacge), |
| 19232 | /* 52343 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 19233 | /* 52346 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 19234 | /* 52349 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 19235 | /* 52352 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19236 | /* 52356 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19237 | /* 52360 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19238 | /* 52364 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3753:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (VACGEhq:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) |
| 19239 | /* 52364 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VACGEhq), |
| 19240 | /* 52367 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19241 | /* 52369 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19242 | /* 52371 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19243 | /* 52373 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19244 | /* 52376 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19245 | /* 52382 */ GIR_RootConstrainSelectedInstOperands, |
| 19246 | /* 52383 */ // GIR_Coverage, 1122, |
| 19247 | /* 52383 */ GIR_EraseRootFromParent_Done, |
| 19248 | /* 52384 */ // Label 1138: @52384 |
| 19249 | /* 52384 */ GIM_Try, /*On fail goto*//*Label 1139*/ GIMT_Encode4(52438), // Rule ID 1123 // |
| 19250 | /* 52389 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 19251 | /* 52392 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vacgt), |
| 19252 | /* 52397 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 19253 | /* 52400 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 19254 | /* 52403 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 19255 | /* 52406 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19256 | /* 52410 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19257 | /* 52414 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19258 | /* 52418 */ // (intrinsic_wo_chain:{ *:[v2i32] } 3754:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VACGTfd:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) |
| 19259 | /* 52418 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VACGTfd), |
| 19260 | /* 52421 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19261 | /* 52423 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19262 | /* 52425 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19263 | /* 52427 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19264 | /* 52430 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19265 | /* 52436 */ GIR_RootConstrainSelectedInstOperands, |
| 19266 | /* 52437 */ // GIR_Coverage, 1123, |
| 19267 | /* 52437 */ GIR_EraseRootFromParent_Done, |
| 19268 | /* 52438 */ // Label 1139: @52438 |
| 19269 | /* 52438 */ GIM_Try, /*On fail goto*//*Label 1140*/ GIMT_Encode4(52492), // Rule ID 1124 // |
| 19270 | /* 52443 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 19271 | /* 52446 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vacgt), |
| 19272 | /* 52451 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 19273 | /* 52454 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 19274 | /* 52457 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 19275 | /* 52460 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19276 | /* 52464 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19277 | /* 52468 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19278 | /* 52472 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3754:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (VACGTfq:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) |
| 19279 | /* 52472 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VACGTfq), |
| 19280 | /* 52475 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19281 | /* 52477 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19282 | /* 52479 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19283 | /* 52481 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19284 | /* 52484 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19285 | /* 52490 */ GIR_RootConstrainSelectedInstOperands, |
| 19286 | /* 52491 */ // GIR_Coverage, 1124, |
| 19287 | /* 52491 */ GIR_EraseRootFromParent_Done, |
| 19288 | /* 52492 */ // Label 1140: @52492 |
| 19289 | /* 52492 */ GIM_Try, /*On fail goto*//*Label 1141*/ GIMT_Encode4(52546), // Rule ID 1125 // |
| 19290 | /* 52497 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 19291 | /* 52500 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vacgt), |
| 19292 | /* 52505 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 19293 | /* 52508 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 19294 | /* 52511 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 19295 | /* 52514 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19296 | /* 52518 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19297 | /* 52522 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19298 | /* 52526 */ // (intrinsic_wo_chain:{ *:[v4i16] } 3754:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VACGThd:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) |
| 19299 | /* 52526 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VACGThd), |
| 19300 | /* 52529 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19301 | /* 52531 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19302 | /* 52533 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19303 | /* 52535 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19304 | /* 52538 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19305 | /* 52544 */ GIR_RootConstrainSelectedInstOperands, |
| 19306 | /* 52545 */ // GIR_Coverage, 1125, |
| 19307 | /* 52545 */ GIR_EraseRootFromParent_Done, |
| 19308 | /* 52546 */ // Label 1141: @52546 |
| 19309 | /* 52546 */ GIM_Try, /*On fail goto*//*Label 1142*/ GIMT_Encode4(52600), // Rule ID 1126 // |
| 19310 | /* 52551 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 19311 | /* 52554 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vacgt), |
| 19312 | /* 52559 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 19313 | /* 52562 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 19314 | /* 52565 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 19315 | /* 52568 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19316 | /* 52572 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19317 | /* 52576 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19318 | /* 52580 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3754:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (VACGThq:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) |
| 19319 | /* 52580 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VACGThq), |
| 19320 | /* 52583 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19321 | /* 52585 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19322 | /* 52587 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19323 | /* 52589 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19324 | /* 52592 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19325 | /* 52598 */ GIR_RootConstrainSelectedInstOperands, |
| 19326 | /* 52599 */ // GIR_Coverage, 1126, |
| 19327 | /* 52599 */ GIR_EraseRootFromParent_Done, |
| 19328 | /* 52600 */ // Label 1142: @52600 |
| 19329 | /* 52600 */ GIM_Try, /*On fail goto*//*Label 1143*/ GIMT_Encode4(52654), // Rule ID 1169 // |
| 19330 | /* 52605 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 19331 | /* 52608 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vabds), |
| 19332 | /* 52613 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 19333 | /* 52616 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 19334 | /* 52619 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 19335 | /* 52622 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19336 | /* 52626 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19337 | /* 52630 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19338 | /* 52634 */ // (intrinsic_wo_chain:{ *:[v2f32] } 3750:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VABDfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) |
| 19339 | /* 52634 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDfd), |
| 19340 | /* 52637 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19341 | /* 52639 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19342 | /* 52641 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19343 | /* 52643 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19344 | /* 52646 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19345 | /* 52652 */ GIR_RootConstrainSelectedInstOperands, |
| 19346 | /* 52653 */ // GIR_Coverage, 1169, |
| 19347 | /* 52653 */ GIR_EraseRootFromParent_Done, |
| 19348 | /* 52654 */ // Label 1143: @52654 |
| 19349 | /* 52654 */ GIM_Try, /*On fail goto*//*Label 1144*/ GIMT_Encode4(52708), // Rule ID 1170 // |
| 19350 | /* 52659 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 19351 | /* 52662 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vabds), |
| 19352 | /* 52667 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 19353 | /* 52670 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 19354 | /* 52673 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 19355 | /* 52676 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19356 | /* 52680 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19357 | /* 52684 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19358 | /* 52688 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3750:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (VABDfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) |
| 19359 | /* 52688 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDfq), |
| 19360 | /* 52691 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19361 | /* 52693 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19362 | /* 52695 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19363 | /* 52697 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19364 | /* 52700 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19365 | /* 52706 */ GIR_RootConstrainSelectedInstOperands, |
| 19366 | /* 52707 */ // GIR_Coverage, 1170, |
| 19367 | /* 52707 */ GIR_EraseRootFromParent_Done, |
| 19368 | /* 52708 */ // Label 1144: @52708 |
| 19369 | /* 52708 */ GIM_Try, /*On fail goto*//*Label 1145*/ GIMT_Encode4(52762), // Rule ID 1171 // |
| 19370 | /* 52713 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 19371 | /* 52716 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vabds), |
| 19372 | /* 52721 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 19373 | /* 52724 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 19374 | /* 52727 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 19375 | /* 52730 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19376 | /* 52734 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19377 | /* 52738 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19378 | /* 52742 */ // (intrinsic_wo_chain:{ *:[v4f16] } 3750:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VABDhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) |
| 19379 | /* 52742 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDhd), |
| 19380 | /* 52745 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19381 | /* 52747 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19382 | /* 52749 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19383 | /* 52751 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19384 | /* 52754 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19385 | /* 52760 */ GIR_RootConstrainSelectedInstOperands, |
| 19386 | /* 52761 */ // GIR_Coverage, 1171, |
| 19387 | /* 52761 */ GIR_EraseRootFromParent_Done, |
| 19388 | /* 52762 */ // Label 1145: @52762 |
| 19389 | /* 52762 */ GIM_Try, /*On fail goto*//*Label 1146*/ GIMT_Encode4(52816), // Rule ID 1172 // |
| 19390 | /* 52767 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 19391 | /* 52770 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vabds), |
| 19392 | /* 52775 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 19393 | /* 52778 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 19394 | /* 52781 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 19395 | /* 52784 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19396 | /* 52788 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19397 | /* 52792 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19398 | /* 52796 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3750:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (VABDhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) |
| 19399 | /* 52796 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDhq), |
| 19400 | /* 52799 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19401 | /* 52801 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19402 | /* 52803 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19403 | /* 52805 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19404 | /* 52808 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19405 | /* 52814 */ GIR_RootConstrainSelectedInstOperands, |
| 19406 | /* 52815 */ // GIR_Coverage, 1172, |
| 19407 | /* 52815 */ GIR_EraseRootFromParent_Done, |
| 19408 | /* 52816 */ // Label 1146: @52816 |
| 19409 | /* 52816 */ GIM_Try, /*On fail goto*//*Label 1147*/ GIMT_Encode4(52870), // Rule ID 1237 // |
| 19410 | /* 52821 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 19411 | /* 52824 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpadd), |
| 19412 | /* 52829 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, |
| 19413 | /* 52832 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 19414 | /* 52835 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 19415 | /* 52838 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19416 | /* 52842 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19417 | /* 52846 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19418 | /* 52850 */ // (intrinsic_wo_chain:{ *:[v8i8] } 3804:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VPADDi8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 19419 | /* 52850 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDi8), |
| 19420 | /* 52853 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19421 | /* 52855 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19422 | /* 52857 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19423 | /* 52859 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19424 | /* 52862 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19425 | /* 52868 */ GIR_RootConstrainSelectedInstOperands, |
| 19426 | /* 52869 */ // GIR_Coverage, 1237, |
| 19427 | /* 52869 */ GIR_EraseRootFromParent_Done, |
| 19428 | /* 52870 */ // Label 1147: @52870 |
| 19429 | /* 52870 */ GIM_Try, /*On fail goto*//*Label 1148*/ GIMT_Encode4(52924), // Rule ID 1238 // |
| 19430 | /* 52875 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 19431 | /* 52878 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpadd), |
| 19432 | /* 52883 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 19433 | /* 52886 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 19434 | /* 52889 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 19435 | /* 52892 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19436 | /* 52896 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19437 | /* 52900 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19438 | /* 52904 */ // (intrinsic_wo_chain:{ *:[v4i16] } 3804:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VPADDi16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 19439 | /* 52904 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDi16), |
| 19440 | /* 52907 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19441 | /* 52909 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19442 | /* 52911 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19443 | /* 52913 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19444 | /* 52916 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19445 | /* 52922 */ GIR_RootConstrainSelectedInstOperands, |
| 19446 | /* 52923 */ // GIR_Coverage, 1238, |
| 19447 | /* 52923 */ GIR_EraseRootFromParent_Done, |
| 19448 | /* 52924 */ // Label 1148: @52924 |
| 19449 | /* 52924 */ GIM_Try, /*On fail goto*//*Label 1149*/ GIMT_Encode4(52978), // Rule ID 1239 // |
| 19450 | /* 52929 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 19451 | /* 52932 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpadd), |
| 19452 | /* 52937 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 19453 | /* 52940 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 19454 | /* 52943 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 19455 | /* 52946 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19456 | /* 52950 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19457 | /* 52954 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19458 | /* 52958 */ // (intrinsic_wo_chain:{ *:[v2i32] } 3804:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VPADDi32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 19459 | /* 52958 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDi32), |
| 19460 | /* 52961 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19461 | /* 52963 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19462 | /* 52965 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19463 | /* 52967 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19464 | /* 52970 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19465 | /* 52976 */ GIR_RootConstrainSelectedInstOperands, |
| 19466 | /* 52977 */ // GIR_Coverage, 1239, |
| 19467 | /* 52977 */ GIR_EraseRootFromParent_Done, |
| 19468 | /* 52978 */ // Label 1149: @52978 |
| 19469 | /* 52978 */ GIM_Try, /*On fail goto*//*Label 1150*/ GIMT_Encode4(53032), // Rule ID 1240 // |
| 19470 | /* 52983 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 19471 | /* 52986 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpadd), |
| 19472 | /* 52991 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 19473 | /* 52994 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 19474 | /* 52997 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 19475 | /* 53000 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19476 | /* 53004 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19477 | /* 53008 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19478 | /* 53012 */ // (intrinsic_wo_chain:{ *:[v2f32] } 3804:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VPADDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) |
| 19479 | /* 53012 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDf), |
| 19480 | /* 53015 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19481 | /* 53017 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19482 | /* 53019 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19483 | /* 53021 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19484 | /* 53024 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19485 | /* 53030 */ GIR_RootConstrainSelectedInstOperands, |
| 19486 | /* 53031 */ // GIR_Coverage, 1240, |
| 19487 | /* 53031 */ GIR_EraseRootFromParent_Done, |
| 19488 | /* 53032 */ // Label 1150: @53032 |
| 19489 | /* 53032 */ GIM_Try, /*On fail goto*//*Label 1151*/ GIMT_Encode4(53086), // Rule ID 1241 // |
| 19490 | /* 53037 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 19491 | /* 53040 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpadd), |
| 19492 | /* 53045 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 19493 | /* 53048 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 19494 | /* 53051 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 19495 | /* 53054 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19496 | /* 53058 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19497 | /* 53062 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19498 | /* 53066 */ // (intrinsic_wo_chain:{ *:[v4f16] } 3804:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VPADDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) |
| 19499 | /* 53066 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDh), |
| 19500 | /* 53069 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19501 | /* 53071 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19502 | /* 53073 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19503 | /* 53075 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19504 | /* 53078 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19505 | /* 53084 */ GIR_RootConstrainSelectedInstOperands, |
| 19506 | /* 53085 */ // GIR_Coverage, 1241, |
| 19507 | /* 53085 */ GIR_EraseRootFromParent_Done, |
| 19508 | /* 53086 */ // Label 1151: @53086 |
| 19509 | /* 53086 */ GIM_Try, /*On fail goto*//*Label 1152*/ GIMT_Encode4(53140), // Rule ID 1254 // |
| 19510 | /* 53091 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 19511 | /* 53094 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpadals), |
| 19512 | /* 53099 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 19513 | /* 53102 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 19514 | /* 53105 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 19515 | /* 53108 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19516 | /* 53112 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19517 | /* 53116 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19518 | /* 53120 */ // (intrinsic_wo_chain:{ *:[v4i16] } 3802:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v8i8] }:$Vm) => (VPADALsv8i8:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v8i8] }:$Vm) |
| 19519 | /* 53120 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADALsv8i8), |
| 19520 | /* 53123 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19521 | /* 53125 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 19522 | /* 53127 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19523 | /* 53129 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19524 | /* 53132 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19525 | /* 53138 */ GIR_RootConstrainSelectedInstOperands, |
| 19526 | /* 53139 */ // GIR_Coverage, 1254, |
| 19527 | /* 53139 */ GIR_EraseRootFromParent_Done, |
| 19528 | /* 53140 */ // Label 1152: @53140 |
| 19529 | /* 53140 */ GIM_Try, /*On fail goto*//*Label 1153*/ GIMT_Encode4(53194), // Rule ID 1255 // |
| 19530 | /* 53145 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 19531 | /* 53148 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpadals), |
| 19532 | /* 53153 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 19533 | /* 53156 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 19534 | /* 53159 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 19535 | /* 53162 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19536 | /* 53166 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19537 | /* 53170 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19538 | /* 53174 */ // (intrinsic_wo_chain:{ *:[v2i32] } 3802:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v4i16] }:$Vm) => (VPADALsv4i16:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v4i16] }:$Vm) |
| 19539 | /* 53174 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADALsv4i16), |
| 19540 | /* 53177 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19541 | /* 53179 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 19542 | /* 53181 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19543 | /* 53183 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19544 | /* 53186 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19545 | /* 53192 */ GIR_RootConstrainSelectedInstOperands, |
| 19546 | /* 53193 */ // GIR_Coverage, 1255, |
| 19547 | /* 53193 */ GIR_EraseRootFromParent_Done, |
| 19548 | /* 53194 */ // Label 1153: @53194 |
| 19549 | /* 53194 */ GIM_Try, /*On fail goto*//*Label 1154*/ GIMT_Encode4(53248), // Rule ID 1256 // |
| 19550 | /* 53199 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 19551 | /* 53202 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpadals), |
| 19552 | /* 53207 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 19553 | /* 53210 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 19554 | /* 53213 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 19555 | /* 53216 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19556 | /* 53220 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19557 | /* 53224 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19558 | /* 53228 */ // (intrinsic_wo_chain:{ *:[v1i64] } 3802:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$src1, DPR:{ *:[v2i32] }:$Vm) => (VPADALsv2i32:{ *:[v1i64] } DPR:{ *:[v1i64] }:$src1, DPR:{ *:[v2i32] }:$Vm) |
| 19559 | /* 53228 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADALsv2i32), |
| 19560 | /* 53231 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19561 | /* 53233 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 19562 | /* 53235 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19563 | /* 53237 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19564 | /* 53240 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19565 | /* 53246 */ GIR_RootConstrainSelectedInstOperands, |
| 19566 | /* 53247 */ // GIR_Coverage, 1256, |
| 19567 | /* 53247 */ GIR_EraseRootFromParent_Done, |
| 19568 | /* 53248 */ // Label 1154: @53248 |
| 19569 | /* 53248 */ GIM_Try, /*On fail goto*//*Label 1155*/ GIMT_Encode4(53302), // Rule ID 1257 // |
| 19570 | /* 53253 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 19571 | /* 53256 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpadals), |
| 19572 | /* 53261 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 19573 | /* 53264 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 19574 | /* 53267 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 19575 | /* 53270 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19576 | /* 53274 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19577 | /* 53278 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19578 | /* 53282 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3802:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v16i8] }:$Vm) => (VPADALsv16i8:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v16i8] }:$Vm) |
| 19579 | /* 53282 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADALsv16i8), |
| 19580 | /* 53285 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19581 | /* 53287 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 19582 | /* 53289 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19583 | /* 53291 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19584 | /* 53294 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19585 | /* 53300 */ GIR_RootConstrainSelectedInstOperands, |
| 19586 | /* 53301 */ // GIR_Coverage, 1257, |
| 19587 | /* 53301 */ GIR_EraseRootFromParent_Done, |
| 19588 | /* 53302 */ // Label 1155: @53302 |
| 19589 | /* 53302 */ GIM_Try, /*On fail goto*//*Label 1156*/ GIMT_Encode4(53356), // Rule ID 1258 // |
| 19590 | /* 53307 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 19591 | /* 53310 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpadals), |
| 19592 | /* 53315 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 19593 | /* 53318 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 19594 | /* 53321 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 19595 | /* 53324 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19596 | /* 53328 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19597 | /* 53332 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19598 | /* 53336 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3802:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v8i16] }:$Vm) => (VPADALsv8i16:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v8i16] }:$Vm) |
| 19599 | /* 53336 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADALsv8i16), |
| 19600 | /* 53339 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19601 | /* 53341 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 19602 | /* 53343 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19603 | /* 53345 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19604 | /* 53348 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19605 | /* 53354 */ GIR_RootConstrainSelectedInstOperands, |
| 19606 | /* 53355 */ // GIR_Coverage, 1258, |
| 19607 | /* 53355 */ GIR_EraseRootFromParent_Done, |
| 19608 | /* 53356 */ // Label 1156: @53356 |
| 19609 | /* 53356 */ GIM_Try, /*On fail goto*//*Label 1157*/ GIMT_Encode4(53410), // Rule ID 1259 // |
| 19610 | /* 53361 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 19611 | /* 53364 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpadals), |
| 19612 | /* 53369 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 19613 | /* 53372 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 19614 | /* 53375 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 19615 | /* 53378 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19616 | /* 53382 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19617 | /* 53386 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19618 | /* 53390 */ // (intrinsic_wo_chain:{ *:[v2i64] } 3802:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$src1, QPR:{ *:[v4i32] }:$Vm) => (VPADALsv4i32:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, QPR:{ *:[v4i32] }:$Vm) |
| 19619 | /* 53390 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADALsv4i32), |
| 19620 | /* 53393 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19621 | /* 53395 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 19622 | /* 53397 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19623 | /* 53399 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19624 | /* 53402 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19625 | /* 53408 */ GIR_RootConstrainSelectedInstOperands, |
| 19626 | /* 53409 */ // GIR_Coverage, 1259, |
| 19627 | /* 53409 */ GIR_EraseRootFromParent_Done, |
| 19628 | /* 53410 */ // Label 1157: @53410 |
| 19629 | /* 53410 */ GIM_Try, /*On fail goto*//*Label 1158*/ GIMT_Encode4(53464), // Rule ID 1260 // |
| 19630 | /* 53415 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 19631 | /* 53418 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpadalu), |
| 19632 | /* 53423 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 19633 | /* 53426 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 19634 | /* 53429 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 19635 | /* 53432 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19636 | /* 53436 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19637 | /* 53440 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19638 | /* 53444 */ // (intrinsic_wo_chain:{ *:[v4i16] } 3803:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v8i8] }:$Vm) => (VPADALuv8i8:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v8i8] }:$Vm) |
| 19639 | /* 53444 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADALuv8i8), |
| 19640 | /* 53447 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19641 | /* 53449 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 19642 | /* 53451 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19643 | /* 53453 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19644 | /* 53456 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19645 | /* 53462 */ GIR_RootConstrainSelectedInstOperands, |
| 19646 | /* 53463 */ // GIR_Coverage, 1260, |
| 19647 | /* 53463 */ GIR_EraseRootFromParent_Done, |
| 19648 | /* 53464 */ // Label 1158: @53464 |
| 19649 | /* 53464 */ GIM_Try, /*On fail goto*//*Label 1159*/ GIMT_Encode4(53518), // Rule ID 1261 // |
| 19650 | /* 53469 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 19651 | /* 53472 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpadalu), |
| 19652 | /* 53477 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 19653 | /* 53480 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 19654 | /* 53483 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 19655 | /* 53486 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19656 | /* 53490 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19657 | /* 53494 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19658 | /* 53498 */ // (intrinsic_wo_chain:{ *:[v2i32] } 3803:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v4i16] }:$Vm) => (VPADALuv4i16:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v4i16] }:$Vm) |
| 19659 | /* 53498 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADALuv4i16), |
| 19660 | /* 53501 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19661 | /* 53503 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 19662 | /* 53505 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19663 | /* 53507 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19664 | /* 53510 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19665 | /* 53516 */ GIR_RootConstrainSelectedInstOperands, |
| 19666 | /* 53517 */ // GIR_Coverage, 1261, |
| 19667 | /* 53517 */ GIR_EraseRootFromParent_Done, |
| 19668 | /* 53518 */ // Label 1159: @53518 |
| 19669 | /* 53518 */ GIM_Try, /*On fail goto*//*Label 1160*/ GIMT_Encode4(53572), // Rule ID 1262 // |
| 19670 | /* 53523 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 19671 | /* 53526 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpadalu), |
| 19672 | /* 53531 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 19673 | /* 53534 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 19674 | /* 53537 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 19675 | /* 53540 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19676 | /* 53544 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19677 | /* 53548 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19678 | /* 53552 */ // (intrinsic_wo_chain:{ *:[v1i64] } 3803:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$src1, DPR:{ *:[v2i32] }:$Vm) => (VPADALuv2i32:{ *:[v1i64] } DPR:{ *:[v1i64] }:$src1, DPR:{ *:[v2i32] }:$Vm) |
| 19679 | /* 53552 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADALuv2i32), |
| 19680 | /* 53555 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19681 | /* 53557 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 19682 | /* 53559 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19683 | /* 53561 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19684 | /* 53564 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19685 | /* 53570 */ GIR_RootConstrainSelectedInstOperands, |
| 19686 | /* 53571 */ // GIR_Coverage, 1262, |
| 19687 | /* 53571 */ GIR_EraseRootFromParent_Done, |
| 19688 | /* 53572 */ // Label 1160: @53572 |
| 19689 | /* 53572 */ GIM_Try, /*On fail goto*//*Label 1161*/ GIMT_Encode4(53626), // Rule ID 1263 // |
| 19690 | /* 53577 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 19691 | /* 53580 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpadalu), |
| 19692 | /* 53585 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 19693 | /* 53588 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 19694 | /* 53591 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 19695 | /* 53594 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19696 | /* 53598 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19697 | /* 53602 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19698 | /* 53606 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3803:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v16i8] }:$Vm) => (VPADALuv16i8:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v16i8] }:$Vm) |
| 19699 | /* 53606 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADALuv16i8), |
| 19700 | /* 53609 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19701 | /* 53611 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 19702 | /* 53613 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19703 | /* 53615 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19704 | /* 53618 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19705 | /* 53624 */ GIR_RootConstrainSelectedInstOperands, |
| 19706 | /* 53625 */ // GIR_Coverage, 1263, |
| 19707 | /* 53625 */ GIR_EraseRootFromParent_Done, |
| 19708 | /* 53626 */ // Label 1161: @53626 |
| 19709 | /* 53626 */ GIM_Try, /*On fail goto*//*Label 1162*/ GIMT_Encode4(53680), // Rule ID 1264 // |
| 19710 | /* 53631 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 19711 | /* 53634 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpadalu), |
| 19712 | /* 53639 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 19713 | /* 53642 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 19714 | /* 53645 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 19715 | /* 53648 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19716 | /* 53652 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19717 | /* 53656 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19718 | /* 53660 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3803:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v8i16] }:$Vm) => (VPADALuv8i16:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v8i16] }:$Vm) |
| 19719 | /* 53660 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADALuv8i16), |
| 19720 | /* 53663 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19721 | /* 53665 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 19722 | /* 53667 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19723 | /* 53669 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19724 | /* 53672 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19725 | /* 53678 */ GIR_RootConstrainSelectedInstOperands, |
| 19726 | /* 53679 */ // GIR_Coverage, 1264, |
| 19727 | /* 53679 */ GIR_EraseRootFromParent_Done, |
| 19728 | /* 53680 */ // Label 1162: @53680 |
| 19729 | /* 53680 */ GIM_Try, /*On fail goto*//*Label 1163*/ GIMT_Encode4(53734), // Rule ID 1265 // |
| 19730 | /* 53685 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 19731 | /* 53688 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpadalu), |
| 19732 | /* 53693 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 19733 | /* 53696 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 19734 | /* 53699 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 19735 | /* 53702 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19736 | /* 53706 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19737 | /* 53710 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19738 | /* 53714 */ // (intrinsic_wo_chain:{ *:[v2i64] } 3803:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$src1, QPR:{ *:[v4i32] }:$Vm) => (VPADALuv4i32:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, QPR:{ *:[v4i32] }:$Vm) |
| 19739 | /* 53714 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADALuv4i32), |
| 19740 | /* 53717 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19741 | /* 53719 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 19742 | /* 53721 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19743 | /* 53723 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19744 | /* 53726 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19745 | /* 53732 */ GIR_RootConstrainSelectedInstOperands, |
| 19746 | /* 53733 */ // GIR_Coverage, 1265, |
| 19747 | /* 53733 */ GIR_EraseRootFromParent_Done, |
| 19748 | /* 53734 */ // Label 1163: @53734 |
| 19749 | /* 53734 */ GIM_Try, /*On fail goto*//*Label 1164*/ GIMT_Encode4(53788), // Rule ID 1266 // |
| 19750 | /* 53739 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 19751 | /* 53742 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpmaxs), |
| 19752 | /* 53747 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, |
| 19753 | /* 53750 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 19754 | /* 53753 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 19755 | /* 53756 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19756 | /* 53760 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19757 | /* 53764 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19758 | /* 53768 */ // (intrinsic_wo_chain:{ *:[v8i8] } 3807:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VPMAXs8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 19759 | /* 53768 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMAXs8), |
| 19760 | /* 53771 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19761 | /* 53773 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19762 | /* 53775 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19763 | /* 53777 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19764 | /* 53780 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19765 | /* 53786 */ GIR_RootConstrainSelectedInstOperands, |
| 19766 | /* 53787 */ // GIR_Coverage, 1266, |
| 19767 | /* 53787 */ GIR_EraseRootFromParent_Done, |
| 19768 | /* 53788 */ // Label 1164: @53788 |
| 19769 | /* 53788 */ GIM_Try, /*On fail goto*//*Label 1165*/ GIMT_Encode4(53842), // Rule ID 1267 // |
| 19770 | /* 53793 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 19771 | /* 53796 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpmaxs), |
| 19772 | /* 53801 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 19773 | /* 53804 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 19774 | /* 53807 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 19775 | /* 53810 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19776 | /* 53814 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19777 | /* 53818 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19778 | /* 53822 */ // (intrinsic_wo_chain:{ *:[v4i16] } 3807:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VPMAXs16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 19779 | /* 53822 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMAXs16), |
| 19780 | /* 53825 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19781 | /* 53827 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19782 | /* 53829 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19783 | /* 53831 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19784 | /* 53834 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19785 | /* 53840 */ GIR_RootConstrainSelectedInstOperands, |
| 19786 | /* 53841 */ // GIR_Coverage, 1267, |
| 19787 | /* 53841 */ GIR_EraseRootFromParent_Done, |
| 19788 | /* 53842 */ // Label 1165: @53842 |
| 19789 | /* 53842 */ GIM_Try, /*On fail goto*//*Label 1166*/ GIMT_Encode4(53896), // Rule ID 1268 // |
| 19790 | /* 53847 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 19791 | /* 53850 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpmaxs), |
| 19792 | /* 53855 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 19793 | /* 53858 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 19794 | /* 53861 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 19795 | /* 53864 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19796 | /* 53868 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19797 | /* 53872 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19798 | /* 53876 */ // (intrinsic_wo_chain:{ *:[v2i32] } 3807:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VPMAXs32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 19799 | /* 53876 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMAXs32), |
| 19800 | /* 53879 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19801 | /* 53881 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19802 | /* 53883 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19803 | /* 53885 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19804 | /* 53888 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19805 | /* 53894 */ GIR_RootConstrainSelectedInstOperands, |
| 19806 | /* 53895 */ // GIR_Coverage, 1268, |
| 19807 | /* 53895 */ GIR_EraseRootFromParent_Done, |
| 19808 | /* 53896 */ // Label 1166: @53896 |
| 19809 | /* 53896 */ GIM_Try, /*On fail goto*//*Label 1167*/ GIMT_Encode4(53950), // Rule ID 1269 // |
| 19810 | /* 53901 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 19811 | /* 53904 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpmaxu), |
| 19812 | /* 53909 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, |
| 19813 | /* 53912 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 19814 | /* 53915 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 19815 | /* 53918 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19816 | /* 53922 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19817 | /* 53926 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19818 | /* 53930 */ // (intrinsic_wo_chain:{ *:[v8i8] } 3808:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VPMAXu8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 19819 | /* 53930 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMAXu8), |
| 19820 | /* 53933 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19821 | /* 53935 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19822 | /* 53937 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19823 | /* 53939 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19824 | /* 53942 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19825 | /* 53948 */ GIR_RootConstrainSelectedInstOperands, |
| 19826 | /* 53949 */ // GIR_Coverage, 1269, |
| 19827 | /* 53949 */ GIR_EraseRootFromParent_Done, |
| 19828 | /* 53950 */ // Label 1167: @53950 |
| 19829 | /* 53950 */ GIM_Try, /*On fail goto*//*Label 1168*/ GIMT_Encode4(54004), // Rule ID 1270 // |
| 19830 | /* 53955 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 19831 | /* 53958 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpmaxu), |
| 19832 | /* 53963 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 19833 | /* 53966 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 19834 | /* 53969 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 19835 | /* 53972 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19836 | /* 53976 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19837 | /* 53980 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19838 | /* 53984 */ // (intrinsic_wo_chain:{ *:[v4i16] } 3808:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VPMAXu16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 19839 | /* 53984 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMAXu16), |
| 19840 | /* 53987 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19841 | /* 53989 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19842 | /* 53991 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19843 | /* 53993 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19844 | /* 53996 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19845 | /* 54002 */ GIR_RootConstrainSelectedInstOperands, |
| 19846 | /* 54003 */ // GIR_Coverage, 1270, |
| 19847 | /* 54003 */ GIR_EraseRootFromParent_Done, |
| 19848 | /* 54004 */ // Label 1168: @54004 |
| 19849 | /* 54004 */ GIM_Try, /*On fail goto*//*Label 1169*/ GIMT_Encode4(54058), // Rule ID 1271 // |
| 19850 | /* 54009 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 19851 | /* 54012 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpmaxu), |
| 19852 | /* 54017 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 19853 | /* 54020 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 19854 | /* 54023 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 19855 | /* 54026 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19856 | /* 54030 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19857 | /* 54034 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19858 | /* 54038 */ // (intrinsic_wo_chain:{ *:[v2i32] } 3808:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VPMAXu32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 19859 | /* 54038 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMAXu32), |
| 19860 | /* 54041 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19861 | /* 54043 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19862 | /* 54045 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19863 | /* 54047 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19864 | /* 54050 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19865 | /* 54056 */ GIR_RootConstrainSelectedInstOperands, |
| 19866 | /* 54057 */ // GIR_Coverage, 1271, |
| 19867 | /* 54057 */ GIR_EraseRootFromParent_Done, |
| 19868 | /* 54058 */ // Label 1169: @54058 |
| 19869 | /* 54058 */ GIM_Try, /*On fail goto*//*Label 1170*/ GIMT_Encode4(54112), // Rule ID 1272 // |
| 19870 | /* 54063 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 19871 | /* 54066 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpmaxs), |
| 19872 | /* 54071 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 19873 | /* 54074 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 19874 | /* 54077 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 19875 | /* 54080 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19876 | /* 54084 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19877 | /* 54088 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19878 | /* 54092 */ // (intrinsic_wo_chain:{ *:[v2f32] } 3807:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VPMAXf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) |
| 19879 | /* 54092 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMAXf), |
| 19880 | /* 54095 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19881 | /* 54097 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19882 | /* 54099 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19883 | /* 54101 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19884 | /* 54104 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19885 | /* 54110 */ GIR_RootConstrainSelectedInstOperands, |
| 19886 | /* 54111 */ // GIR_Coverage, 1272, |
| 19887 | /* 54111 */ GIR_EraseRootFromParent_Done, |
| 19888 | /* 54112 */ // Label 1170: @54112 |
| 19889 | /* 54112 */ GIM_Try, /*On fail goto*//*Label 1171*/ GIMT_Encode4(54166), // Rule ID 1273 // |
| 19890 | /* 54117 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 19891 | /* 54120 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpmaxs), |
| 19892 | /* 54125 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 19893 | /* 54128 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 19894 | /* 54131 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 19895 | /* 54134 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19896 | /* 54138 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19897 | /* 54142 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19898 | /* 54146 */ // (intrinsic_wo_chain:{ *:[v4f16] } 3807:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VPMAXh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) |
| 19899 | /* 54146 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMAXh), |
| 19900 | /* 54149 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19901 | /* 54151 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19902 | /* 54153 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19903 | /* 54155 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19904 | /* 54158 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19905 | /* 54164 */ GIR_RootConstrainSelectedInstOperands, |
| 19906 | /* 54165 */ // GIR_Coverage, 1273, |
| 19907 | /* 54165 */ GIR_EraseRootFromParent_Done, |
| 19908 | /* 54166 */ // Label 1171: @54166 |
| 19909 | /* 54166 */ GIM_Try, /*On fail goto*//*Label 1172*/ GIMT_Encode4(54220), // Rule ID 1274 // |
| 19910 | /* 54171 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 19911 | /* 54174 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpmins), |
| 19912 | /* 54179 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, |
| 19913 | /* 54182 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 19914 | /* 54185 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 19915 | /* 54188 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19916 | /* 54192 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19917 | /* 54196 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19918 | /* 54200 */ // (intrinsic_wo_chain:{ *:[v8i8] } 3809:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VPMINs8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 19919 | /* 54200 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMINs8), |
| 19920 | /* 54203 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19921 | /* 54205 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19922 | /* 54207 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19923 | /* 54209 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19924 | /* 54212 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19925 | /* 54218 */ GIR_RootConstrainSelectedInstOperands, |
| 19926 | /* 54219 */ // GIR_Coverage, 1274, |
| 19927 | /* 54219 */ GIR_EraseRootFromParent_Done, |
| 19928 | /* 54220 */ // Label 1172: @54220 |
| 19929 | /* 54220 */ GIM_Try, /*On fail goto*//*Label 1173*/ GIMT_Encode4(54274), // Rule ID 1275 // |
| 19930 | /* 54225 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 19931 | /* 54228 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpmins), |
| 19932 | /* 54233 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 19933 | /* 54236 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 19934 | /* 54239 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 19935 | /* 54242 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19936 | /* 54246 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19937 | /* 54250 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19938 | /* 54254 */ // (intrinsic_wo_chain:{ *:[v4i16] } 3809:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VPMINs16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 19939 | /* 54254 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMINs16), |
| 19940 | /* 54257 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19941 | /* 54259 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19942 | /* 54261 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19943 | /* 54263 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19944 | /* 54266 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19945 | /* 54272 */ GIR_RootConstrainSelectedInstOperands, |
| 19946 | /* 54273 */ // GIR_Coverage, 1275, |
| 19947 | /* 54273 */ GIR_EraseRootFromParent_Done, |
| 19948 | /* 54274 */ // Label 1173: @54274 |
| 19949 | /* 54274 */ GIM_Try, /*On fail goto*//*Label 1174*/ GIMT_Encode4(54328), // Rule ID 1276 // |
| 19950 | /* 54279 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 19951 | /* 54282 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpmins), |
| 19952 | /* 54287 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 19953 | /* 54290 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 19954 | /* 54293 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 19955 | /* 54296 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19956 | /* 54300 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19957 | /* 54304 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19958 | /* 54308 */ // (intrinsic_wo_chain:{ *:[v2i32] } 3809:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VPMINs32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 19959 | /* 54308 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMINs32), |
| 19960 | /* 54311 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19961 | /* 54313 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19962 | /* 54315 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19963 | /* 54317 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19964 | /* 54320 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19965 | /* 54326 */ GIR_RootConstrainSelectedInstOperands, |
| 19966 | /* 54327 */ // GIR_Coverage, 1276, |
| 19967 | /* 54327 */ GIR_EraseRootFromParent_Done, |
| 19968 | /* 54328 */ // Label 1174: @54328 |
| 19969 | /* 54328 */ GIM_Try, /*On fail goto*//*Label 1175*/ GIMT_Encode4(54382), // Rule ID 1277 // |
| 19970 | /* 54333 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 19971 | /* 54336 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpminu), |
| 19972 | /* 54341 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, |
| 19973 | /* 54344 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 19974 | /* 54347 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 19975 | /* 54350 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19976 | /* 54354 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19977 | /* 54358 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19978 | /* 54362 */ // (intrinsic_wo_chain:{ *:[v8i8] } 3810:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VPMINu8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 19979 | /* 54362 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMINu8), |
| 19980 | /* 54365 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19981 | /* 54367 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19982 | /* 54369 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19983 | /* 54371 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19984 | /* 54374 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19985 | /* 54380 */ GIR_RootConstrainSelectedInstOperands, |
| 19986 | /* 54381 */ // GIR_Coverage, 1277, |
| 19987 | /* 54381 */ GIR_EraseRootFromParent_Done, |
| 19988 | /* 54382 */ // Label 1175: @54382 |
| 19989 | /* 54382 */ GIM_Try, /*On fail goto*//*Label 1176*/ GIMT_Encode4(54436), // Rule ID 1278 // |
| 19990 | /* 54387 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 19991 | /* 54390 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpminu), |
| 19992 | /* 54395 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 19993 | /* 54398 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 19994 | /* 54401 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 19995 | /* 54404 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19996 | /* 54408 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19997 | /* 54412 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19998 | /* 54416 */ // (intrinsic_wo_chain:{ *:[v4i16] } 3810:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VPMINu16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 19999 | /* 54416 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMINu16), |
| 20000 | /* 54419 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20001 | /* 54421 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20002 | /* 54423 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20003 | /* 54425 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20004 | /* 54428 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20005 | /* 54434 */ GIR_RootConstrainSelectedInstOperands, |
| 20006 | /* 54435 */ // GIR_Coverage, 1278, |
| 20007 | /* 54435 */ GIR_EraseRootFromParent_Done, |
| 20008 | /* 54436 */ // Label 1176: @54436 |
| 20009 | /* 54436 */ GIM_Try, /*On fail goto*//*Label 1177*/ GIMT_Encode4(54490), // Rule ID 1279 // |
| 20010 | /* 54441 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20011 | /* 54444 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpminu), |
| 20012 | /* 54449 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 20013 | /* 54452 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 20014 | /* 54455 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 20015 | /* 54458 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20016 | /* 54462 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20017 | /* 54466 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20018 | /* 54470 */ // (intrinsic_wo_chain:{ *:[v2i32] } 3810:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VPMINu32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 20019 | /* 54470 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMINu32), |
| 20020 | /* 54473 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20021 | /* 54475 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20022 | /* 54477 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20023 | /* 54479 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20024 | /* 54482 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20025 | /* 54488 */ GIR_RootConstrainSelectedInstOperands, |
| 20026 | /* 54489 */ // GIR_Coverage, 1279, |
| 20027 | /* 54489 */ GIR_EraseRootFromParent_Done, |
| 20028 | /* 54490 */ // Label 1177: @54490 |
| 20029 | /* 54490 */ GIM_Try, /*On fail goto*//*Label 1178*/ GIMT_Encode4(54544), // Rule ID 1280 // |
| 20030 | /* 54495 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20031 | /* 54498 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpmins), |
| 20032 | /* 54503 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 20033 | /* 54506 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 20034 | /* 54509 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 20035 | /* 54512 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20036 | /* 54516 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20037 | /* 54520 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20038 | /* 54524 */ // (intrinsic_wo_chain:{ *:[v2f32] } 3809:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VPMINf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) |
| 20039 | /* 54524 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMINf), |
| 20040 | /* 54527 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20041 | /* 54529 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20042 | /* 54531 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20043 | /* 54533 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20044 | /* 54536 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20045 | /* 54542 */ GIR_RootConstrainSelectedInstOperands, |
| 20046 | /* 54543 */ // GIR_Coverage, 1280, |
| 20047 | /* 54543 */ GIR_EraseRootFromParent_Done, |
| 20048 | /* 54544 */ // Label 1178: @54544 |
| 20049 | /* 54544 */ GIM_Try, /*On fail goto*//*Label 1179*/ GIMT_Encode4(54598), // Rule ID 1281 // |
| 20050 | /* 54549 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 20051 | /* 54552 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpmins), |
| 20052 | /* 54557 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 20053 | /* 54560 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 20054 | /* 54563 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 20055 | /* 54566 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20056 | /* 54570 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20057 | /* 54574 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20058 | /* 54578 */ // (intrinsic_wo_chain:{ *:[v4f16] } 3809:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VPMINh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) |
| 20059 | /* 54578 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMINh), |
| 20060 | /* 54581 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20061 | /* 54583 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20062 | /* 54585 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20063 | /* 54587 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20064 | /* 54590 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20065 | /* 54596 */ GIR_RootConstrainSelectedInstOperands, |
| 20066 | /* 54597 */ // GIR_Coverage, 1281, |
| 20067 | /* 54597 */ GIR_EraseRootFromParent_Done, |
| 20068 | /* 54598 */ // Label 1179: @54598 |
| 20069 | /* 54598 */ GIM_Try, /*On fail goto*//*Label 1180*/ GIMT_Encode4(54652), // Rule ID 1288 // |
| 20070 | /* 54603 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20071 | /* 54606 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrecps), |
| 20072 | /* 54611 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 20073 | /* 54614 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 20074 | /* 54617 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 20075 | /* 54620 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20076 | /* 54624 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20077 | /* 54628 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20078 | /* 54632 */ // (intrinsic_wo_chain:{ *:[v2f32] } 3834:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VRECPSfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) |
| 20079 | /* 54632 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRECPSfd), |
| 20080 | /* 54635 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20081 | /* 54637 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20082 | /* 54639 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20083 | /* 54641 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20084 | /* 54644 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20085 | /* 54650 */ GIR_RootConstrainSelectedInstOperands, |
| 20086 | /* 54651 */ // GIR_Coverage, 1288, |
| 20087 | /* 54651 */ GIR_EraseRootFromParent_Done, |
| 20088 | /* 54652 */ // Label 1180: @54652 |
| 20089 | /* 54652 */ GIM_Try, /*On fail goto*//*Label 1181*/ GIMT_Encode4(54706), // Rule ID 1289 // |
| 20090 | /* 54657 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20091 | /* 54660 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrecps), |
| 20092 | /* 54665 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 20093 | /* 54668 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 20094 | /* 54671 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 20095 | /* 54674 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20096 | /* 54678 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20097 | /* 54682 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20098 | /* 54686 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3834:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (VRECPSfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) |
| 20099 | /* 54686 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRECPSfq), |
| 20100 | /* 54689 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20101 | /* 54691 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20102 | /* 54693 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20103 | /* 54695 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20104 | /* 54698 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20105 | /* 54704 */ GIR_RootConstrainSelectedInstOperands, |
| 20106 | /* 54705 */ // GIR_Coverage, 1289, |
| 20107 | /* 54705 */ GIR_EraseRootFromParent_Done, |
| 20108 | /* 54706 */ // Label 1181: @54706 |
| 20109 | /* 54706 */ GIM_Try, /*On fail goto*//*Label 1182*/ GIMT_Encode4(54760), // Rule ID 1290 // |
| 20110 | /* 54711 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 20111 | /* 54714 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrecps), |
| 20112 | /* 54719 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 20113 | /* 54722 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 20114 | /* 54725 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 20115 | /* 54728 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20116 | /* 54732 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20117 | /* 54736 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20118 | /* 54740 */ // (intrinsic_wo_chain:{ *:[v4f16] } 3834:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VRECPShd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) |
| 20119 | /* 54740 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRECPShd), |
| 20120 | /* 54743 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20121 | /* 54745 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20122 | /* 54747 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20123 | /* 54749 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20124 | /* 54752 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20125 | /* 54758 */ GIR_RootConstrainSelectedInstOperands, |
| 20126 | /* 54759 */ // GIR_Coverage, 1290, |
| 20127 | /* 54759 */ GIR_EraseRootFromParent_Done, |
| 20128 | /* 54760 */ // Label 1182: @54760 |
| 20129 | /* 54760 */ GIM_Try, /*On fail goto*//*Label 1183*/ GIMT_Encode4(54814), // Rule ID 1291 // |
| 20130 | /* 54765 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 20131 | /* 54768 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrecps), |
| 20132 | /* 54773 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 20133 | /* 54776 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 20134 | /* 54779 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 20135 | /* 54782 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20136 | /* 54786 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20137 | /* 54790 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20138 | /* 54794 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3834:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (VRECPShq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) |
| 20139 | /* 54794 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRECPShq), |
| 20140 | /* 54797 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20141 | /* 54799 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20142 | /* 54801 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20143 | /* 54803 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20144 | /* 54806 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20145 | /* 54812 */ GIR_RootConstrainSelectedInstOperands, |
| 20146 | /* 54813 */ // GIR_Coverage, 1291, |
| 20147 | /* 54813 */ GIR_EraseRootFromParent_Done, |
| 20148 | /* 54814 */ // Label 1183: @54814 |
| 20149 | /* 54814 */ GIM_Try, /*On fail goto*//*Label 1184*/ GIMT_Encode4(54868), // Rule ID 1298 // |
| 20150 | /* 54819 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20151 | /* 54822 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrsqrts), |
| 20152 | /* 54827 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 20153 | /* 54830 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 20154 | /* 54833 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 20155 | /* 54836 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20156 | /* 54840 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20157 | /* 54844 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20158 | /* 54848 */ // (intrinsic_wo_chain:{ *:[v2f32] } 3842:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VRSQRTSfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) |
| 20159 | /* 54848 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSQRTSfd), |
| 20160 | /* 54851 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20161 | /* 54853 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20162 | /* 54855 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20163 | /* 54857 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20164 | /* 54860 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20165 | /* 54866 */ GIR_RootConstrainSelectedInstOperands, |
| 20166 | /* 54867 */ // GIR_Coverage, 1298, |
| 20167 | /* 54867 */ GIR_EraseRootFromParent_Done, |
| 20168 | /* 54868 */ // Label 1184: @54868 |
| 20169 | /* 54868 */ GIM_Try, /*On fail goto*//*Label 1185*/ GIMT_Encode4(54922), // Rule ID 1299 // |
| 20170 | /* 54873 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20171 | /* 54876 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrsqrts), |
| 20172 | /* 54881 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 20173 | /* 54884 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 20174 | /* 54887 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 20175 | /* 54890 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20176 | /* 54894 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20177 | /* 54898 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20178 | /* 54902 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3842:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (VRSQRTSfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) |
| 20179 | /* 54902 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSQRTSfq), |
| 20180 | /* 54905 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20181 | /* 54907 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20182 | /* 54909 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20183 | /* 54911 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20184 | /* 54914 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20185 | /* 54920 */ GIR_RootConstrainSelectedInstOperands, |
| 20186 | /* 54921 */ // GIR_Coverage, 1299, |
| 20187 | /* 54921 */ GIR_EraseRootFromParent_Done, |
| 20188 | /* 54922 */ // Label 1185: @54922 |
| 20189 | /* 54922 */ GIM_Try, /*On fail goto*//*Label 1186*/ GIMT_Encode4(54976), // Rule ID 1300 // |
| 20190 | /* 54927 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 20191 | /* 54930 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrsqrts), |
| 20192 | /* 54935 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 20193 | /* 54938 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 20194 | /* 54941 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 20195 | /* 54944 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20196 | /* 54948 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20197 | /* 54952 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20198 | /* 54956 */ // (intrinsic_wo_chain:{ *:[v4f16] } 3842:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VRSQRTShd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) |
| 20199 | /* 54956 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSQRTShd), |
| 20200 | /* 54959 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20201 | /* 54961 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20202 | /* 54963 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20203 | /* 54965 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20204 | /* 54968 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20205 | /* 54974 */ GIR_RootConstrainSelectedInstOperands, |
| 20206 | /* 54975 */ // GIR_Coverage, 1300, |
| 20207 | /* 54975 */ GIR_EraseRootFromParent_Done, |
| 20208 | /* 54976 */ // Label 1186: @54976 |
| 20209 | /* 54976 */ GIM_Try, /*On fail goto*//*Label 1187*/ GIMT_Encode4(55030), // Rule ID 1301 // |
| 20210 | /* 54981 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 20211 | /* 54984 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrsqrts), |
| 20212 | /* 54989 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 20213 | /* 54992 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 20214 | /* 54995 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 20215 | /* 54998 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20216 | /* 55002 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20217 | /* 55006 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20218 | /* 55010 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3842:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (VRSQRTShq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) |
| 20219 | /* 55010 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSQRTShq), |
| 20220 | /* 55013 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20221 | /* 55015 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20222 | /* 55017 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20223 | /* 55019 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20224 | /* 55022 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20225 | /* 55028 */ GIR_RootConstrainSelectedInstOperands, |
| 20226 | /* 55029 */ // GIR_Coverage, 1301, |
| 20227 | /* 55029 */ GIR_EraseRootFromParent_Done, |
| 20228 | /* 55030 */ // Label 1187: @55030 |
| 20229 | /* 55030 */ GIM_Try, /*On fail goto*//*Label 1188*/ GIMT_Encode4(55084), // Rule ID 1302 // |
| 20230 | /* 55035 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20231 | /* 55038 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vshifts), |
| 20232 | /* 55043 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 20233 | /* 55046 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 20234 | /* 55049 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 20235 | /* 55052 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20236 | /* 55056 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20237 | /* 55060 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20238 | /* 55064 */ // (intrinsic_wo_chain:{ *:[v4i16] } 3845:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) => (VSHLsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) |
| 20239 | /* 55064 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLsv4i16), |
| 20240 | /* 55067 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20241 | /* 55069 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 20242 | /* 55071 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 20243 | /* 55073 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20244 | /* 55076 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20245 | /* 55082 */ GIR_RootConstrainSelectedInstOperands, |
| 20246 | /* 55083 */ // GIR_Coverage, 1302, |
| 20247 | /* 55083 */ GIR_EraseRootFromParent_Done, |
| 20248 | /* 55084 */ // Label 1188: @55084 |
| 20249 | /* 55084 */ GIM_Try, /*On fail goto*//*Label 1189*/ GIMT_Encode4(55138), // Rule ID 1303 // |
| 20250 | /* 55089 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20251 | /* 55092 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vshifts), |
| 20252 | /* 55097 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 20253 | /* 55100 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 20254 | /* 55103 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 20255 | /* 55106 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20256 | /* 55110 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20257 | /* 55114 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20258 | /* 55118 */ // (intrinsic_wo_chain:{ *:[v2i32] } 3845:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) => (VSHLsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) |
| 20259 | /* 55118 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLsv2i32), |
| 20260 | /* 55121 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20261 | /* 55123 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 20262 | /* 55125 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 20263 | /* 55127 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20264 | /* 55130 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20265 | /* 55136 */ GIR_RootConstrainSelectedInstOperands, |
| 20266 | /* 55137 */ // GIR_Coverage, 1303, |
| 20267 | /* 55137 */ GIR_EraseRootFromParent_Done, |
| 20268 | /* 55138 */ // Label 1189: @55138 |
| 20269 | /* 55138 */ GIM_Try, /*On fail goto*//*Label 1190*/ GIMT_Encode4(55192), // Rule ID 1304 // |
| 20270 | /* 55143 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20271 | /* 55146 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vshifts), |
| 20272 | /* 55151 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 20273 | /* 55154 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 20274 | /* 55157 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 20275 | /* 55160 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20276 | /* 55164 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20277 | /* 55168 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20278 | /* 55172 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3845:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) => (VSHLsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) |
| 20279 | /* 55172 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLsv8i16), |
| 20280 | /* 55175 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20281 | /* 55177 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 20282 | /* 55179 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 20283 | /* 55181 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20284 | /* 55184 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20285 | /* 55190 */ GIR_RootConstrainSelectedInstOperands, |
| 20286 | /* 55191 */ // GIR_Coverage, 1304, |
| 20287 | /* 55191 */ GIR_EraseRootFromParent_Done, |
| 20288 | /* 55192 */ // Label 1190: @55192 |
| 20289 | /* 55192 */ GIM_Try, /*On fail goto*//*Label 1191*/ GIMT_Encode4(55246), // Rule ID 1305 // |
| 20290 | /* 55197 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20291 | /* 55200 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vshifts), |
| 20292 | /* 55205 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 20293 | /* 55208 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 20294 | /* 55211 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 20295 | /* 55214 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20296 | /* 55218 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20297 | /* 55222 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20298 | /* 55226 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3845:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) => (VSHLsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) |
| 20299 | /* 55226 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLsv4i32), |
| 20300 | /* 55229 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20301 | /* 55231 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 20302 | /* 55233 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 20303 | /* 55235 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20304 | /* 55238 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20305 | /* 55244 */ GIR_RootConstrainSelectedInstOperands, |
| 20306 | /* 55245 */ // GIR_Coverage, 1305, |
| 20307 | /* 55245 */ GIR_EraseRootFromParent_Done, |
| 20308 | /* 55246 */ // Label 1191: @55246 |
| 20309 | /* 55246 */ GIM_Try, /*On fail goto*//*Label 1192*/ GIMT_Encode4(55300), // Rule ID 1306 // |
| 20310 | /* 55251 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20311 | /* 55254 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vshifts), |
| 20312 | /* 55259 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, |
| 20313 | /* 55262 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 20314 | /* 55265 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 20315 | /* 55268 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20316 | /* 55272 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20317 | /* 55276 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20318 | /* 55280 */ // (intrinsic_wo_chain:{ *:[v8i8] } 3845:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) => (VSHLsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) |
| 20319 | /* 55280 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLsv8i8), |
| 20320 | /* 55283 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20321 | /* 55285 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 20322 | /* 55287 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 20323 | /* 55289 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20324 | /* 55292 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20325 | /* 55298 */ GIR_RootConstrainSelectedInstOperands, |
| 20326 | /* 55299 */ // GIR_Coverage, 1306, |
| 20327 | /* 55299 */ GIR_EraseRootFromParent_Done, |
| 20328 | /* 55300 */ // Label 1192: @55300 |
| 20329 | /* 55300 */ GIM_Try, /*On fail goto*//*Label 1193*/ GIMT_Encode4(55354), // Rule ID 1307 // |
| 20330 | /* 55305 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20331 | /* 55308 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vshifts), |
| 20332 | /* 55313 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 20333 | /* 55316 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 20334 | /* 55319 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 20335 | /* 55322 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20336 | /* 55326 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20337 | /* 55330 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20338 | /* 55334 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3845:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) => (VSHLsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) |
| 20339 | /* 55334 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLsv16i8), |
| 20340 | /* 55337 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20341 | /* 55339 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 20342 | /* 55341 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 20343 | /* 55343 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20344 | /* 55346 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20345 | /* 55352 */ GIR_RootConstrainSelectedInstOperands, |
| 20346 | /* 55353 */ // GIR_Coverage, 1307, |
| 20347 | /* 55353 */ GIR_EraseRootFromParent_Done, |
| 20348 | /* 55354 */ // Label 1193: @55354 |
| 20349 | /* 55354 */ GIM_Try, /*On fail goto*//*Label 1194*/ GIMT_Encode4(55408), // Rule ID 1308 // |
| 20350 | /* 55359 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20351 | /* 55362 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vshifts), |
| 20352 | /* 55367 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 20353 | /* 55370 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 20354 | /* 55373 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 20355 | /* 55376 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20356 | /* 55380 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20357 | /* 55384 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20358 | /* 55388 */ // (intrinsic_wo_chain:{ *:[v1i64] } 3845:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) => (VSHLsv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) |
| 20359 | /* 55388 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLsv1i64), |
| 20360 | /* 55391 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20361 | /* 55393 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 20362 | /* 55395 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 20363 | /* 55397 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20364 | /* 55400 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20365 | /* 55406 */ GIR_RootConstrainSelectedInstOperands, |
| 20366 | /* 55407 */ // GIR_Coverage, 1308, |
| 20367 | /* 55407 */ GIR_EraseRootFromParent_Done, |
| 20368 | /* 55408 */ // Label 1194: @55408 |
| 20369 | /* 55408 */ GIM_Try, /*On fail goto*//*Label 1195*/ GIMT_Encode4(55462), // Rule ID 1309 // |
| 20370 | /* 55413 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20371 | /* 55416 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vshifts), |
| 20372 | /* 55421 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 20373 | /* 55424 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 20374 | /* 55427 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 20375 | /* 55430 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20376 | /* 55434 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20377 | /* 55438 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20378 | /* 55442 */ // (intrinsic_wo_chain:{ *:[v2i64] } 3845:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) => (VSHLsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) |
| 20379 | /* 55442 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLsv2i64), |
| 20380 | /* 55445 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20381 | /* 55447 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 20382 | /* 55449 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 20383 | /* 55451 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20384 | /* 55454 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20385 | /* 55460 */ GIR_RootConstrainSelectedInstOperands, |
| 20386 | /* 55461 */ // GIR_Coverage, 1309, |
| 20387 | /* 55461 */ GIR_EraseRootFromParent_Done, |
| 20388 | /* 55462 */ // Label 1195: @55462 |
| 20389 | /* 55462 */ GIM_Try, /*On fail goto*//*Label 1196*/ GIMT_Encode4(55516), // Rule ID 1310 // |
| 20390 | /* 55467 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20391 | /* 55470 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vshiftu), |
| 20392 | /* 55475 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 20393 | /* 55478 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 20394 | /* 55481 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 20395 | /* 55484 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20396 | /* 55488 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20397 | /* 55492 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20398 | /* 55496 */ // (intrinsic_wo_chain:{ *:[v4i16] } 3846:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) => (VSHLuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) |
| 20399 | /* 55496 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLuv4i16), |
| 20400 | /* 55499 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20401 | /* 55501 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 20402 | /* 55503 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 20403 | /* 55505 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20404 | /* 55508 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20405 | /* 55514 */ GIR_RootConstrainSelectedInstOperands, |
| 20406 | /* 55515 */ // GIR_Coverage, 1310, |
| 20407 | /* 55515 */ GIR_EraseRootFromParent_Done, |
| 20408 | /* 55516 */ // Label 1196: @55516 |
| 20409 | /* 55516 */ GIM_Try, /*On fail goto*//*Label 1197*/ GIMT_Encode4(55570), // Rule ID 1311 // |
| 20410 | /* 55521 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20411 | /* 55524 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vshiftu), |
| 20412 | /* 55529 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 20413 | /* 55532 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 20414 | /* 55535 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 20415 | /* 55538 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20416 | /* 55542 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20417 | /* 55546 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20418 | /* 55550 */ // (intrinsic_wo_chain:{ *:[v2i32] } 3846:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) => (VSHLuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) |
| 20419 | /* 55550 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLuv2i32), |
| 20420 | /* 55553 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20421 | /* 55555 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 20422 | /* 55557 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 20423 | /* 55559 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20424 | /* 55562 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20425 | /* 55568 */ GIR_RootConstrainSelectedInstOperands, |
| 20426 | /* 55569 */ // GIR_Coverage, 1311, |
| 20427 | /* 55569 */ GIR_EraseRootFromParent_Done, |
| 20428 | /* 55570 */ // Label 1197: @55570 |
| 20429 | /* 55570 */ GIM_Try, /*On fail goto*//*Label 1198*/ GIMT_Encode4(55624), // Rule ID 1312 // |
| 20430 | /* 55575 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20431 | /* 55578 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vshiftu), |
| 20432 | /* 55583 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 20433 | /* 55586 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 20434 | /* 55589 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 20435 | /* 55592 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20436 | /* 55596 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20437 | /* 55600 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20438 | /* 55604 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3846:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) => (VSHLuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) |
| 20439 | /* 55604 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLuv8i16), |
| 20440 | /* 55607 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20441 | /* 55609 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 20442 | /* 55611 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 20443 | /* 55613 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20444 | /* 55616 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20445 | /* 55622 */ GIR_RootConstrainSelectedInstOperands, |
| 20446 | /* 55623 */ // GIR_Coverage, 1312, |
| 20447 | /* 55623 */ GIR_EraseRootFromParent_Done, |
| 20448 | /* 55624 */ // Label 1198: @55624 |
| 20449 | /* 55624 */ GIM_Try, /*On fail goto*//*Label 1199*/ GIMT_Encode4(55678), // Rule ID 1313 // |
| 20450 | /* 55629 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20451 | /* 55632 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vshiftu), |
| 20452 | /* 55637 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 20453 | /* 55640 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 20454 | /* 55643 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 20455 | /* 55646 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20456 | /* 55650 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20457 | /* 55654 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20458 | /* 55658 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3846:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) => (VSHLuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) |
| 20459 | /* 55658 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLuv4i32), |
| 20460 | /* 55661 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20461 | /* 55663 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 20462 | /* 55665 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 20463 | /* 55667 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20464 | /* 55670 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20465 | /* 55676 */ GIR_RootConstrainSelectedInstOperands, |
| 20466 | /* 55677 */ // GIR_Coverage, 1313, |
| 20467 | /* 55677 */ GIR_EraseRootFromParent_Done, |
| 20468 | /* 55678 */ // Label 1199: @55678 |
| 20469 | /* 55678 */ GIM_Try, /*On fail goto*//*Label 1200*/ GIMT_Encode4(55732), // Rule ID 1314 // |
| 20470 | /* 55683 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20471 | /* 55686 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vshiftu), |
| 20472 | /* 55691 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, |
| 20473 | /* 55694 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 20474 | /* 55697 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 20475 | /* 55700 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20476 | /* 55704 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20477 | /* 55708 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20478 | /* 55712 */ // (intrinsic_wo_chain:{ *:[v8i8] } 3846:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) => (VSHLuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) |
| 20479 | /* 55712 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLuv8i8), |
| 20480 | /* 55715 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20481 | /* 55717 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 20482 | /* 55719 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 20483 | /* 55721 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20484 | /* 55724 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20485 | /* 55730 */ GIR_RootConstrainSelectedInstOperands, |
| 20486 | /* 55731 */ // GIR_Coverage, 1314, |
| 20487 | /* 55731 */ GIR_EraseRootFromParent_Done, |
| 20488 | /* 55732 */ // Label 1200: @55732 |
| 20489 | /* 55732 */ GIM_Try, /*On fail goto*//*Label 1201*/ GIMT_Encode4(55786), // Rule ID 1315 // |
| 20490 | /* 55737 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20491 | /* 55740 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vshiftu), |
| 20492 | /* 55745 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 20493 | /* 55748 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 20494 | /* 55751 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 20495 | /* 55754 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20496 | /* 55758 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20497 | /* 55762 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20498 | /* 55766 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3846:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) => (VSHLuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) |
| 20499 | /* 55766 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLuv16i8), |
| 20500 | /* 55769 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20501 | /* 55771 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 20502 | /* 55773 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 20503 | /* 55775 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20504 | /* 55778 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20505 | /* 55784 */ GIR_RootConstrainSelectedInstOperands, |
| 20506 | /* 55785 */ // GIR_Coverage, 1315, |
| 20507 | /* 55785 */ GIR_EraseRootFromParent_Done, |
| 20508 | /* 55786 */ // Label 1201: @55786 |
| 20509 | /* 55786 */ GIM_Try, /*On fail goto*//*Label 1202*/ GIMT_Encode4(55840), // Rule ID 1316 // |
| 20510 | /* 55791 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20511 | /* 55794 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vshiftu), |
| 20512 | /* 55799 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 20513 | /* 55802 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 20514 | /* 55805 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 20515 | /* 55808 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20516 | /* 55812 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20517 | /* 55816 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20518 | /* 55820 */ // (intrinsic_wo_chain:{ *:[v1i64] } 3846:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) => (VSHLuv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) |
| 20519 | /* 55820 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLuv1i64), |
| 20520 | /* 55823 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20521 | /* 55825 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 20522 | /* 55827 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 20523 | /* 55829 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20524 | /* 55832 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20525 | /* 55838 */ GIR_RootConstrainSelectedInstOperands, |
| 20526 | /* 55839 */ // GIR_Coverage, 1316, |
| 20527 | /* 55839 */ GIR_EraseRootFromParent_Done, |
| 20528 | /* 55840 */ // Label 1202: @55840 |
| 20529 | /* 55840 */ GIM_Try, /*On fail goto*//*Label 1203*/ GIMT_Encode4(55894), // Rule ID 1317 // |
| 20530 | /* 55845 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20531 | /* 55848 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vshiftu), |
| 20532 | /* 55853 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 20533 | /* 55856 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 20534 | /* 55859 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 20535 | /* 55862 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20536 | /* 55866 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20537 | /* 55870 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20538 | /* 55874 */ // (intrinsic_wo_chain:{ *:[v2i64] } 3846:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) => (VSHLuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) |
| 20539 | /* 55874 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLuv2i64), |
| 20540 | /* 55877 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20541 | /* 55879 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 20542 | /* 55881 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 20543 | /* 55883 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20544 | /* 55886 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20545 | /* 55892 */ GIR_RootConstrainSelectedInstOperands, |
| 20546 | /* 55893 */ // GIR_Coverage, 1317, |
| 20547 | /* 55893 */ GIR_EraseRootFromParent_Done, |
| 20548 | /* 55894 */ // Label 1203: @55894 |
| 20549 | /* 55894 */ GIM_Try, /*On fail goto*//*Label 1204*/ GIMT_Encode4(55948), // Rule ID 1351 // |
| 20550 | /* 55899 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20551 | /* 55902 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrshifts), |
| 20552 | /* 55907 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 20553 | /* 55910 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 20554 | /* 55913 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 20555 | /* 55916 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20556 | /* 55920 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20557 | /* 55924 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20558 | /* 55928 */ // (intrinsic_wo_chain:{ *:[v4i16] } 3839:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) => (VRSHLsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) |
| 20559 | /* 55928 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLsv4i16), |
| 20560 | /* 55931 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20561 | /* 55933 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 20562 | /* 55935 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 20563 | /* 55937 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20564 | /* 55940 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20565 | /* 55946 */ GIR_RootConstrainSelectedInstOperands, |
| 20566 | /* 55947 */ // GIR_Coverage, 1351, |
| 20567 | /* 55947 */ GIR_EraseRootFromParent_Done, |
| 20568 | /* 55948 */ // Label 1204: @55948 |
| 20569 | /* 55948 */ GIM_Try, /*On fail goto*//*Label 1205*/ GIMT_Encode4(56002), // Rule ID 1352 // |
| 20570 | /* 55953 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20571 | /* 55956 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrshifts), |
| 20572 | /* 55961 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 20573 | /* 55964 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 20574 | /* 55967 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 20575 | /* 55970 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20576 | /* 55974 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20577 | /* 55978 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20578 | /* 55982 */ // (intrinsic_wo_chain:{ *:[v2i32] } 3839:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) => (VRSHLsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) |
| 20579 | /* 55982 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLsv2i32), |
| 20580 | /* 55985 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20581 | /* 55987 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 20582 | /* 55989 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 20583 | /* 55991 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20584 | /* 55994 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20585 | /* 56000 */ GIR_RootConstrainSelectedInstOperands, |
| 20586 | /* 56001 */ // GIR_Coverage, 1352, |
| 20587 | /* 56001 */ GIR_EraseRootFromParent_Done, |
| 20588 | /* 56002 */ // Label 1205: @56002 |
| 20589 | /* 56002 */ GIM_Try, /*On fail goto*//*Label 1206*/ GIMT_Encode4(56056), // Rule ID 1353 // |
| 20590 | /* 56007 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20591 | /* 56010 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrshifts), |
| 20592 | /* 56015 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 20593 | /* 56018 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 20594 | /* 56021 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 20595 | /* 56024 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20596 | /* 56028 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20597 | /* 56032 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20598 | /* 56036 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3839:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) => (VRSHLsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) |
| 20599 | /* 56036 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLsv8i16), |
| 20600 | /* 56039 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20601 | /* 56041 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 20602 | /* 56043 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 20603 | /* 56045 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20604 | /* 56048 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20605 | /* 56054 */ GIR_RootConstrainSelectedInstOperands, |
| 20606 | /* 56055 */ // GIR_Coverage, 1353, |
| 20607 | /* 56055 */ GIR_EraseRootFromParent_Done, |
| 20608 | /* 56056 */ // Label 1206: @56056 |
| 20609 | /* 56056 */ GIM_Try, /*On fail goto*//*Label 1207*/ GIMT_Encode4(56110), // Rule ID 1354 // |
| 20610 | /* 56061 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20611 | /* 56064 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrshifts), |
| 20612 | /* 56069 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 20613 | /* 56072 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 20614 | /* 56075 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 20615 | /* 56078 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20616 | /* 56082 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20617 | /* 56086 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20618 | /* 56090 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3839:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) => (VRSHLsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) |
| 20619 | /* 56090 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLsv4i32), |
| 20620 | /* 56093 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20621 | /* 56095 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 20622 | /* 56097 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 20623 | /* 56099 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20624 | /* 56102 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20625 | /* 56108 */ GIR_RootConstrainSelectedInstOperands, |
| 20626 | /* 56109 */ // GIR_Coverage, 1354, |
| 20627 | /* 56109 */ GIR_EraseRootFromParent_Done, |
| 20628 | /* 56110 */ // Label 1207: @56110 |
| 20629 | /* 56110 */ GIM_Try, /*On fail goto*//*Label 1208*/ GIMT_Encode4(56164), // Rule ID 1355 // |
| 20630 | /* 56115 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20631 | /* 56118 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrshifts), |
| 20632 | /* 56123 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, |
| 20633 | /* 56126 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 20634 | /* 56129 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 20635 | /* 56132 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20636 | /* 56136 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20637 | /* 56140 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20638 | /* 56144 */ // (intrinsic_wo_chain:{ *:[v8i8] } 3839:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) => (VRSHLsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) |
| 20639 | /* 56144 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLsv8i8), |
| 20640 | /* 56147 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20641 | /* 56149 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 20642 | /* 56151 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 20643 | /* 56153 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20644 | /* 56156 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20645 | /* 56162 */ GIR_RootConstrainSelectedInstOperands, |
| 20646 | /* 56163 */ // GIR_Coverage, 1355, |
| 20647 | /* 56163 */ GIR_EraseRootFromParent_Done, |
| 20648 | /* 56164 */ // Label 1208: @56164 |
| 20649 | /* 56164 */ GIM_Try, /*On fail goto*//*Label 1209*/ GIMT_Encode4(56218), // Rule ID 1356 // |
| 20650 | /* 56169 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20651 | /* 56172 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrshifts), |
| 20652 | /* 56177 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 20653 | /* 56180 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 20654 | /* 56183 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 20655 | /* 56186 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20656 | /* 56190 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20657 | /* 56194 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20658 | /* 56198 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3839:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) => (VRSHLsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) |
| 20659 | /* 56198 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLsv16i8), |
| 20660 | /* 56201 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20661 | /* 56203 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 20662 | /* 56205 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 20663 | /* 56207 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20664 | /* 56210 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20665 | /* 56216 */ GIR_RootConstrainSelectedInstOperands, |
| 20666 | /* 56217 */ // GIR_Coverage, 1356, |
| 20667 | /* 56217 */ GIR_EraseRootFromParent_Done, |
| 20668 | /* 56218 */ // Label 1209: @56218 |
| 20669 | /* 56218 */ GIM_Try, /*On fail goto*//*Label 1210*/ GIMT_Encode4(56272), // Rule ID 1357 // |
| 20670 | /* 56223 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20671 | /* 56226 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrshifts), |
| 20672 | /* 56231 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 20673 | /* 56234 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 20674 | /* 56237 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 20675 | /* 56240 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20676 | /* 56244 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20677 | /* 56248 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20678 | /* 56252 */ // (intrinsic_wo_chain:{ *:[v1i64] } 3839:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) => (VRSHLsv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) |
| 20679 | /* 56252 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLsv1i64), |
| 20680 | /* 56255 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20681 | /* 56257 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 20682 | /* 56259 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 20683 | /* 56261 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20684 | /* 56264 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20685 | /* 56270 */ GIR_RootConstrainSelectedInstOperands, |
| 20686 | /* 56271 */ // GIR_Coverage, 1357, |
| 20687 | /* 56271 */ GIR_EraseRootFromParent_Done, |
| 20688 | /* 56272 */ // Label 1210: @56272 |
| 20689 | /* 56272 */ GIM_Try, /*On fail goto*//*Label 1211*/ GIMT_Encode4(56326), // Rule ID 1358 // |
| 20690 | /* 56277 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20691 | /* 56280 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrshifts), |
| 20692 | /* 56285 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 20693 | /* 56288 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 20694 | /* 56291 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 20695 | /* 56294 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20696 | /* 56298 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20697 | /* 56302 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20698 | /* 56306 */ // (intrinsic_wo_chain:{ *:[v2i64] } 3839:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) => (VRSHLsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) |
| 20699 | /* 56306 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLsv2i64), |
| 20700 | /* 56309 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20701 | /* 56311 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 20702 | /* 56313 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 20703 | /* 56315 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20704 | /* 56318 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20705 | /* 56324 */ GIR_RootConstrainSelectedInstOperands, |
| 20706 | /* 56325 */ // GIR_Coverage, 1358, |
| 20707 | /* 56325 */ GIR_EraseRootFromParent_Done, |
| 20708 | /* 56326 */ // Label 1211: @56326 |
| 20709 | /* 56326 */ GIM_Try, /*On fail goto*//*Label 1212*/ GIMT_Encode4(56380), // Rule ID 1359 // |
| 20710 | /* 56331 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20711 | /* 56334 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrshiftu), |
| 20712 | /* 56339 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 20713 | /* 56342 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 20714 | /* 56345 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 20715 | /* 56348 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20716 | /* 56352 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20717 | /* 56356 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20718 | /* 56360 */ // (intrinsic_wo_chain:{ *:[v4i16] } 3840:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) => (VRSHLuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) |
| 20719 | /* 56360 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLuv4i16), |
| 20720 | /* 56363 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20721 | /* 56365 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 20722 | /* 56367 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 20723 | /* 56369 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20724 | /* 56372 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20725 | /* 56378 */ GIR_RootConstrainSelectedInstOperands, |
| 20726 | /* 56379 */ // GIR_Coverage, 1359, |
| 20727 | /* 56379 */ GIR_EraseRootFromParent_Done, |
| 20728 | /* 56380 */ // Label 1212: @56380 |
| 20729 | /* 56380 */ GIM_Try, /*On fail goto*//*Label 1213*/ GIMT_Encode4(56434), // Rule ID 1360 // |
| 20730 | /* 56385 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20731 | /* 56388 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrshiftu), |
| 20732 | /* 56393 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 20733 | /* 56396 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 20734 | /* 56399 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 20735 | /* 56402 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20736 | /* 56406 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20737 | /* 56410 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20738 | /* 56414 */ // (intrinsic_wo_chain:{ *:[v2i32] } 3840:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) => (VRSHLuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) |
| 20739 | /* 56414 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLuv2i32), |
| 20740 | /* 56417 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20741 | /* 56419 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 20742 | /* 56421 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 20743 | /* 56423 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20744 | /* 56426 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20745 | /* 56432 */ GIR_RootConstrainSelectedInstOperands, |
| 20746 | /* 56433 */ // GIR_Coverage, 1360, |
| 20747 | /* 56433 */ GIR_EraseRootFromParent_Done, |
| 20748 | /* 56434 */ // Label 1213: @56434 |
| 20749 | /* 56434 */ GIM_Try, /*On fail goto*//*Label 1214*/ GIMT_Encode4(56488), // Rule ID 1361 // |
| 20750 | /* 56439 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20751 | /* 56442 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrshiftu), |
| 20752 | /* 56447 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 20753 | /* 56450 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 20754 | /* 56453 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 20755 | /* 56456 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20756 | /* 56460 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20757 | /* 56464 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20758 | /* 56468 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3840:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) => (VRSHLuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) |
| 20759 | /* 56468 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLuv8i16), |
| 20760 | /* 56471 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20761 | /* 56473 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 20762 | /* 56475 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 20763 | /* 56477 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20764 | /* 56480 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20765 | /* 56486 */ GIR_RootConstrainSelectedInstOperands, |
| 20766 | /* 56487 */ // GIR_Coverage, 1361, |
| 20767 | /* 56487 */ GIR_EraseRootFromParent_Done, |
| 20768 | /* 56488 */ // Label 1214: @56488 |
| 20769 | /* 56488 */ GIM_Try, /*On fail goto*//*Label 1215*/ GIMT_Encode4(56542), // Rule ID 1362 // |
| 20770 | /* 56493 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20771 | /* 56496 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrshiftu), |
| 20772 | /* 56501 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 20773 | /* 56504 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 20774 | /* 56507 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 20775 | /* 56510 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20776 | /* 56514 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20777 | /* 56518 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20778 | /* 56522 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3840:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) => (VRSHLuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) |
| 20779 | /* 56522 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLuv4i32), |
| 20780 | /* 56525 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20781 | /* 56527 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 20782 | /* 56529 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 20783 | /* 56531 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20784 | /* 56534 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20785 | /* 56540 */ GIR_RootConstrainSelectedInstOperands, |
| 20786 | /* 56541 */ // GIR_Coverage, 1362, |
| 20787 | /* 56541 */ GIR_EraseRootFromParent_Done, |
| 20788 | /* 56542 */ // Label 1215: @56542 |
| 20789 | /* 56542 */ GIM_Try, /*On fail goto*//*Label 1216*/ GIMT_Encode4(56596), // Rule ID 1363 // |
| 20790 | /* 56547 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20791 | /* 56550 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrshiftu), |
| 20792 | /* 56555 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, |
| 20793 | /* 56558 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 20794 | /* 56561 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 20795 | /* 56564 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20796 | /* 56568 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20797 | /* 56572 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20798 | /* 56576 */ // (intrinsic_wo_chain:{ *:[v8i8] } 3840:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) => (VRSHLuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) |
| 20799 | /* 56576 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLuv8i8), |
| 20800 | /* 56579 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20801 | /* 56581 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 20802 | /* 56583 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 20803 | /* 56585 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20804 | /* 56588 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20805 | /* 56594 */ GIR_RootConstrainSelectedInstOperands, |
| 20806 | /* 56595 */ // GIR_Coverage, 1363, |
| 20807 | /* 56595 */ GIR_EraseRootFromParent_Done, |
| 20808 | /* 56596 */ // Label 1216: @56596 |
| 20809 | /* 56596 */ GIM_Try, /*On fail goto*//*Label 1217*/ GIMT_Encode4(56650), // Rule ID 1364 // |
| 20810 | /* 56601 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20811 | /* 56604 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrshiftu), |
| 20812 | /* 56609 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 20813 | /* 56612 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 20814 | /* 56615 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 20815 | /* 56618 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20816 | /* 56622 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20817 | /* 56626 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20818 | /* 56630 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3840:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) => (VRSHLuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) |
| 20819 | /* 56630 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLuv16i8), |
| 20820 | /* 56633 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20821 | /* 56635 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 20822 | /* 56637 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 20823 | /* 56639 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20824 | /* 56642 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20825 | /* 56648 */ GIR_RootConstrainSelectedInstOperands, |
| 20826 | /* 56649 */ // GIR_Coverage, 1364, |
| 20827 | /* 56649 */ GIR_EraseRootFromParent_Done, |
| 20828 | /* 56650 */ // Label 1217: @56650 |
| 20829 | /* 56650 */ GIM_Try, /*On fail goto*//*Label 1218*/ GIMT_Encode4(56704), // Rule ID 1365 // |
| 20830 | /* 56655 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20831 | /* 56658 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrshiftu), |
| 20832 | /* 56663 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 20833 | /* 56666 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 20834 | /* 56669 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 20835 | /* 56672 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20836 | /* 56676 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20837 | /* 56680 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20838 | /* 56684 */ // (intrinsic_wo_chain:{ *:[v1i64] } 3840:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) => (VRSHLuv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) |
| 20839 | /* 56684 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLuv1i64), |
| 20840 | /* 56687 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20841 | /* 56689 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 20842 | /* 56691 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 20843 | /* 56693 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20844 | /* 56696 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20845 | /* 56702 */ GIR_RootConstrainSelectedInstOperands, |
| 20846 | /* 56703 */ // GIR_Coverage, 1365, |
| 20847 | /* 56703 */ GIR_EraseRootFromParent_Done, |
| 20848 | /* 56704 */ // Label 1218: @56704 |
| 20849 | /* 56704 */ GIM_Try, /*On fail goto*//*Label 1219*/ GIMT_Encode4(56758), // Rule ID 1366 // |
| 20850 | /* 56709 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20851 | /* 56712 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrshiftu), |
| 20852 | /* 56717 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 20853 | /* 56720 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 20854 | /* 56723 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 20855 | /* 56726 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20856 | /* 56730 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20857 | /* 56734 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20858 | /* 56738 */ // (intrinsic_wo_chain:{ *:[v2i64] } 3840:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) => (VRSHLuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) |
| 20859 | /* 56738 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLuv2i64), |
| 20860 | /* 56741 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20861 | /* 56743 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 20862 | /* 56745 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 20863 | /* 56747 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20864 | /* 56750 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20865 | /* 56756 */ GIR_RootConstrainSelectedInstOperands, |
| 20866 | /* 56757 */ // GIR_Coverage, 1366, |
| 20867 | /* 56757 */ GIR_EraseRootFromParent_Done, |
| 20868 | /* 56758 */ // Label 1219: @56758 |
| 20869 | /* 56758 */ GIM_Try, /*On fail goto*//*Label 1220*/ GIMT_Encode4(56812), // Rule ID 1386 // |
| 20870 | /* 56763 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20871 | /* 56766 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqshifts), |
| 20872 | /* 56771 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 20873 | /* 56774 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 20874 | /* 56777 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 20875 | /* 56780 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20876 | /* 56784 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20877 | /* 56788 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20878 | /* 56792 */ // (intrinsic_wo_chain:{ *:[v4i16] } 3829:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) => (VQSHLsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) |
| 20879 | /* 56792 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLsv4i16), |
| 20880 | /* 56795 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20881 | /* 56797 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 20882 | /* 56799 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 20883 | /* 56801 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20884 | /* 56804 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20885 | /* 56810 */ GIR_RootConstrainSelectedInstOperands, |
| 20886 | /* 56811 */ // GIR_Coverage, 1386, |
| 20887 | /* 56811 */ GIR_EraseRootFromParent_Done, |
| 20888 | /* 56812 */ // Label 1220: @56812 |
| 20889 | /* 56812 */ GIM_Try, /*On fail goto*//*Label 1221*/ GIMT_Encode4(56866), // Rule ID 1387 // |
| 20890 | /* 56817 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20891 | /* 56820 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqshifts), |
| 20892 | /* 56825 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 20893 | /* 56828 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 20894 | /* 56831 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 20895 | /* 56834 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20896 | /* 56838 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20897 | /* 56842 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20898 | /* 56846 */ // (intrinsic_wo_chain:{ *:[v2i32] } 3829:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) => (VQSHLsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) |
| 20899 | /* 56846 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLsv2i32), |
| 20900 | /* 56849 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20901 | /* 56851 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 20902 | /* 56853 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 20903 | /* 56855 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20904 | /* 56858 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20905 | /* 56864 */ GIR_RootConstrainSelectedInstOperands, |
| 20906 | /* 56865 */ // GIR_Coverage, 1387, |
| 20907 | /* 56865 */ GIR_EraseRootFromParent_Done, |
| 20908 | /* 56866 */ // Label 1221: @56866 |
| 20909 | /* 56866 */ GIM_Try, /*On fail goto*//*Label 1222*/ GIMT_Encode4(56920), // Rule ID 1388 // |
| 20910 | /* 56871 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20911 | /* 56874 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqshifts), |
| 20912 | /* 56879 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 20913 | /* 56882 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 20914 | /* 56885 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 20915 | /* 56888 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20916 | /* 56892 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20917 | /* 56896 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20918 | /* 56900 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3829:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) => (VQSHLsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) |
| 20919 | /* 56900 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLsv8i16), |
| 20920 | /* 56903 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20921 | /* 56905 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 20922 | /* 56907 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 20923 | /* 56909 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20924 | /* 56912 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20925 | /* 56918 */ GIR_RootConstrainSelectedInstOperands, |
| 20926 | /* 56919 */ // GIR_Coverage, 1388, |
| 20927 | /* 56919 */ GIR_EraseRootFromParent_Done, |
| 20928 | /* 56920 */ // Label 1222: @56920 |
| 20929 | /* 56920 */ GIM_Try, /*On fail goto*//*Label 1223*/ GIMT_Encode4(56974), // Rule ID 1389 // |
| 20930 | /* 56925 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20931 | /* 56928 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqshifts), |
| 20932 | /* 56933 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 20933 | /* 56936 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 20934 | /* 56939 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 20935 | /* 56942 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20936 | /* 56946 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20937 | /* 56950 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20938 | /* 56954 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3829:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) => (VQSHLsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) |
| 20939 | /* 56954 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLsv4i32), |
| 20940 | /* 56957 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20941 | /* 56959 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 20942 | /* 56961 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 20943 | /* 56963 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20944 | /* 56966 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20945 | /* 56972 */ GIR_RootConstrainSelectedInstOperands, |
| 20946 | /* 56973 */ // GIR_Coverage, 1389, |
| 20947 | /* 56973 */ GIR_EraseRootFromParent_Done, |
| 20948 | /* 56974 */ // Label 1223: @56974 |
| 20949 | /* 56974 */ GIM_Try, /*On fail goto*//*Label 1224*/ GIMT_Encode4(57028), // Rule ID 1390 // |
| 20950 | /* 56979 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20951 | /* 56982 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqshifts), |
| 20952 | /* 56987 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, |
| 20953 | /* 56990 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 20954 | /* 56993 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 20955 | /* 56996 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20956 | /* 57000 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20957 | /* 57004 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20958 | /* 57008 */ // (intrinsic_wo_chain:{ *:[v8i8] } 3829:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) => (VQSHLsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) |
| 20959 | /* 57008 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLsv8i8), |
| 20960 | /* 57011 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20961 | /* 57013 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 20962 | /* 57015 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 20963 | /* 57017 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20964 | /* 57020 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20965 | /* 57026 */ GIR_RootConstrainSelectedInstOperands, |
| 20966 | /* 57027 */ // GIR_Coverage, 1390, |
| 20967 | /* 57027 */ GIR_EraseRootFromParent_Done, |
| 20968 | /* 57028 */ // Label 1224: @57028 |
| 20969 | /* 57028 */ GIM_Try, /*On fail goto*//*Label 1225*/ GIMT_Encode4(57082), // Rule ID 1391 // |
| 20970 | /* 57033 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20971 | /* 57036 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqshifts), |
| 20972 | /* 57041 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 20973 | /* 57044 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 20974 | /* 57047 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 20975 | /* 57050 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20976 | /* 57054 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20977 | /* 57058 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20978 | /* 57062 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3829:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) => (VQSHLsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) |
| 20979 | /* 57062 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLsv16i8), |
| 20980 | /* 57065 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20981 | /* 57067 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 20982 | /* 57069 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 20983 | /* 57071 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20984 | /* 57074 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20985 | /* 57080 */ GIR_RootConstrainSelectedInstOperands, |
| 20986 | /* 57081 */ // GIR_Coverage, 1391, |
| 20987 | /* 57081 */ GIR_EraseRootFromParent_Done, |
| 20988 | /* 57082 */ // Label 1225: @57082 |
| 20989 | /* 57082 */ GIM_Try, /*On fail goto*//*Label 1226*/ GIMT_Encode4(57136), // Rule ID 1392 // |
| 20990 | /* 57087 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 20991 | /* 57090 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqshifts), |
| 20992 | /* 57095 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 20993 | /* 57098 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 20994 | /* 57101 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 20995 | /* 57104 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20996 | /* 57108 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20997 | /* 57112 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20998 | /* 57116 */ // (intrinsic_wo_chain:{ *:[v1i64] } 3829:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) => (VQSHLsv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) |
| 20999 | /* 57116 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLsv1i64), |
| 21000 | /* 57119 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21001 | /* 57121 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 21002 | /* 57123 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 21003 | /* 57125 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21004 | /* 57128 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21005 | /* 57134 */ GIR_RootConstrainSelectedInstOperands, |
| 21006 | /* 57135 */ // GIR_Coverage, 1392, |
| 21007 | /* 57135 */ GIR_EraseRootFromParent_Done, |
| 21008 | /* 57136 */ // Label 1226: @57136 |
| 21009 | /* 57136 */ GIM_Try, /*On fail goto*//*Label 1227*/ GIMT_Encode4(57190), // Rule ID 1393 // |
| 21010 | /* 57141 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 21011 | /* 57144 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqshifts), |
| 21012 | /* 57149 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 21013 | /* 57152 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 21014 | /* 57155 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 21015 | /* 57158 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21016 | /* 57162 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21017 | /* 57166 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21018 | /* 57170 */ // (intrinsic_wo_chain:{ *:[v2i64] } 3829:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) => (VQSHLsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) |
| 21019 | /* 57170 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLsv2i64), |
| 21020 | /* 57173 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21021 | /* 57175 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 21022 | /* 57177 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 21023 | /* 57179 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21024 | /* 57182 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21025 | /* 57188 */ GIR_RootConstrainSelectedInstOperands, |
| 21026 | /* 57189 */ // GIR_Coverage, 1393, |
| 21027 | /* 57189 */ GIR_EraseRootFromParent_Done, |
| 21028 | /* 57190 */ // Label 1227: @57190 |
| 21029 | /* 57190 */ GIM_Try, /*On fail goto*//*Label 1228*/ GIMT_Encode4(57244), // Rule ID 1394 // |
| 21030 | /* 57195 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 21031 | /* 57198 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqshiftu), |
| 21032 | /* 57203 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 21033 | /* 57206 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 21034 | /* 57209 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 21035 | /* 57212 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21036 | /* 57216 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21037 | /* 57220 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21038 | /* 57224 */ // (intrinsic_wo_chain:{ *:[v4i16] } 3831:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) => (VQSHLuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) |
| 21039 | /* 57224 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLuv4i16), |
| 21040 | /* 57227 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21041 | /* 57229 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 21042 | /* 57231 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 21043 | /* 57233 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21044 | /* 57236 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21045 | /* 57242 */ GIR_RootConstrainSelectedInstOperands, |
| 21046 | /* 57243 */ // GIR_Coverage, 1394, |
| 21047 | /* 57243 */ GIR_EraseRootFromParent_Done, |
| 21048 | /* 57244 */ // Label 1228: @57244 |
| 21049 | /* 57244 */ GIM_Try, /*On fail goto*//*Label 1229*/ GIMT_Encode4(57298), // Rule ID 1395 // |
| 21050 | /* 57249 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 21051 | /* 57252 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqshiftu), |
| 21052 | /* 57257 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 21053 | /* 57260 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 21054 | /* 57263 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 21055 | /* 57266 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21056 | /* 57270 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21057 | /* 57274 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21058 | /* 57278 */ // (intrinsic_wo_chain:{ *:[v2i32] } 3831:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) => (VQSHLuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) |
| 21059 | /* 57278 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLuv2i32), |
| 21060 | /* 57281 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21061 | /* 57283 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 21062 | /* 57285 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 21063 | /* 57287 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21064 | /* 57290 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21065 | /* 57296 */ GIR_RootConstrainSelectedInstOperands, |
| 21066 | /* 57297 */ // GIR_Coverage, 1395, |
| 21067 | /* 57297 */ GIR_EraseRootFromParent_Done, |
| 21068 | /* 57298 */ // Label 1229: @57298 |
| 21069 | /* 57298 */ GIM_Try, /*On fail goto*//*Label 1230*/ GIMT_Encode4(57352), // Rule ID 1396 // |
| 21070 | /* 57303 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 21071 | /* 57306 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqshiftu), |
| 21072 | /* 57311 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 21073 | /* 57314 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 21074 | /* 57317 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 21075 | /* 57320 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21076 | /* 57324 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21077 | /* 57328 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21078 | /* 57332 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3831:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) => (VQSHLuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) |
| 21079 | /* 57332 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLuv8i16), |
| 21080 | /* 57335 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21081 | /* 57337 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 21082 | /* 57339 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 21083 | /* 57341 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21084 | /* 57344 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21085 | /* 57350 */ GIR_RootConstrainSelectedInstOperands, |
| 21086 | /* 57351 */ // GIR_Coverage, 1396, |
| 21087 | /* 57351 */ GIR_EraseRootFromParent_Done, |
| 21088 | /* 57352 */ // Label 1230: @57352 |
| 21089 | /* 57352 */ GIM_Try, /*On fail goto*//*Label 1231*/ GIMT_Encode4(57406), // Rule ID 1397 // |
| 21090 | /* 57357 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 21091 | /* 57360 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqshiftu), |
| 21092 | /* 57365 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 21093 | /* 57368 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 21094 | /* 57371 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 21095 | /* 57374 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21096 | /* 57378 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21097 | /* 57382 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21098 | /* 57386 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3831:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) => (VQSHLuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) |
| 21099 | /* 57386 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLuv4i32), |
| 21100 | /* 57389 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21101 | /* 57391 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 21102 | /* 57393 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 21103 | /* 57395 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21104 | /* 57398 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21105 | /* 57404 */ GIR_RootConstrainSelectedInstOperands, |
| 21106 | /* 57405 */ // GIR_Coverage, 1397, |
| 21107 | /* 57405 */ GIR_EraseRootFromParent_Done, |
| 21108 | /* 57406 */ // Label 1231: @57406 |
| 21109 | /* 57406 */ GIM_Try, /*On fail goto*//*Label 1232*/ GIMT_Encode4(57460), // Rule ID 1398 // |
| 21110 | /* 57411 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 21111 | /* 57414 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqshiftu), |
| 21112 | /* 57419 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, |
| 21113 | /* 57422 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 21114 | /* 57425 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 21115 | /* 57428 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21116 | /* 57432 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21117 | /* 57436 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21118 | /* 57440 */ // (intrinsic_wo_chain:{ *:[v8i8] } 3831:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) => (VQSHLuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) |
| 21119 | /* 57440 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLuv8i8), |
| 21120 | /* 57443 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21121 | /* 57445 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 21122 | /* 57447 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 21123 | /* 57449 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21124 | /* 57452 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21125 | /* 57458 */ GIR_RootConstrainSelectedInstOperands, |
| 21126 | /* 57459 */ // GIR_Coverage, 1398, |
| 21127 | /* 57459 */ GIR_EraseRootFromParent_Done, |
| 21128 | /* 57460 */ // Label 1232: @57460 |
| 21129 | /* 57460 */ GIM_Try, /*On fail goto*//*Label 1233*/ GIMT_Encode4(57514), // Rule ID 1399 // |
| 21130 | /* 57465 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 21131 | /* 57468 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqshiftu), |
| 21132 | /* 57473 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 21133 | /* 57476 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 21134 | /* 57479 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 21135 | /* 57482 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21136 | /* 57486 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21137 | /* 57490 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21138 | /* 57494 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3831:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) => (VQSHLuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) |
| 21139 | /* 57494 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLuv16i8), |
| 21140 | /* 57497 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21141 | /* 57499 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 21142 | /* 57501 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 21143 | /* 57503 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21144 | /* 57506 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21145 | /* 57512 */ GIR_RootConstrainSelectedInstOperands, |
| 21146 | /* 57513 */ // GIR_Coverage, 1399, |
| 21147 | /* 57513 */ GIR_EraseRootFromParent_Done, |
| 21148 | /* 57514 */ // Label 1233: @57514 |
| 21149 | /* 57514 */ GIM_Try, /*On fail goto*//*Label 1234*/ GIMT_Encode4(57568), // Rule ID 1400 // |
| 21150 | /* 57519 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 21151 | /* 57522 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqshiftu), |
| 21152 | /* 57527 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 21153 | /* 57530 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 21154 | /* 57533 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 21155 | /* 57536 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21156 | /* 57540 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21157 | /* 57544 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21158 | /* 57548 */ // (intrinsic_wo_chain:{ *:[v1i64] } 3831:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) => (VQSHLuv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) |
| 21159 | /* 57548 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLuv1i64), |
| 21160 | /* 57551 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21161 | /* 57553 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 21162 | /* 57555 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 21163 | /* 57557 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21164 | /* 57560 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21165 | /* 57566 */ GIR_RootConstrainSelectedInstOperands, |
| 21166 | /* 57567 */ // GIR_Coverage, 1400, |
| 21167 | /* 57567 */ GIR_EraseRootFromParent_Done, |
| 21168 | /* 57568 */ // Label 1234: @57568 |
| 21169 | /* 57568 */ GIM_Try, /*On fail goto*//*Label 1235*/ GIMT_Encode4(57622), // Rule ID 1401 // |
| 21170 | /* 57573 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 21171 | /* 57576 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqshiftu), |
| 21172 | /* 57581 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 21173 | /* 57584 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 21174 | /* 57587 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 21175 | /* 57590 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21176 | /* 57594 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21177 | /* 57598 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21178 | /* 57602 */ // (intrinsic_wo_chain:{ *:[v2i64] } 3831:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) => (VQSHLuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) |
| 21179 | /* 57602 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLuv2i64), |
| 21180 | /* 57605 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21181 | /* 57607 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 21182 | /* 57609 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 21183 | /* 57611 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21184 | /* 57614 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21185 | /* 57620 */ GIR_RootConstrainSelectedInstOperands, |
| 21186 | /* 57621 */ // GIR_Coverage, 1401, |
| 21187 | /* 57621 */ GIR_EraseRootFromParent_Done, |
| 21188 | /* 57622 */ // Label 1235: @57622 |
| 21189 | /* 57622 */ GIM_Try, /*On fail goto*//*Label 1236*/ GIMT_Encode4(57676), // Rule ID 1435 // |
| 21190 | /* 57627 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 21191 | /* 57630 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrshifts), |
| 21192 | /* 57635 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 21193 | /* 57638 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 21194 | /* 57641 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 21195 | /* 57644 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21196 | /* 57648 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21197 | /* 57652 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21198 | /* 57656 */ // (intrinsic_wo_chain:{ *:[v4i16] } 3824:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) => (VQRSHLsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) |
| 21199 | /* 57656 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLsv4i16), |
| 21200 | /* 57659 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21201 | /* 57661 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 21202 | /* 57663 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 21203 | /* 57665 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21204 | /* 57668 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21205 | /* 57674 */ GIR_RootConstrainSelectedInstOperands, |
| 21206 | /* 57675 */ // GIR_Coverage, 1435, |
| 21207 | /* 57675 */ GIR_EraseRootFromParent_Done, |
| 21208 | /* 57676 */ // Label 1236: @57676 |
| 21209 | /* 57676 */ GIM_Try, /*On fail goto*//*Label 1237*/ GIMT_Encode4(57730), // Rule ID 1436 // |
| 21210 | /* 57681 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 21211 | /* 57684 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrshifts), |
| 21212 | /* 57689 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 21213 | /* 57692 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 21214 | /* 57695 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 21215 | /* 57698 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21216 | /* 57702 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21217 | /* 57706 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21218 | /* 57710 */ // (intrinsic_wo_chain:{ *:[v2i32] } 3824:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) => (VQRSHLsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) |
| 21219 | /* 57710 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLsv2i32), |
| 21220 | /* 57713 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21221 | /* 57715 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 21222 | /* 57717 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 21223 | /* 57719 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21224 | /* 57722 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21225 | /* 57728 */ GIR_RootConstrainSelectedInstOperands, |
| 21226 | /* 57729 */ // GIR_Coverage, 1436, |
| 21227 | /* 57729 */ GIR_EraseRootFromParent_Done, |
| 21228 | /* 57730 */ // Label 1237: @57730 |
| 21229 | /* 57730 */ GIM_Try, /*On fail goto*//*Label 1238*/ GIMT_Encode4(57784), // Rule ID 1437 // |
| 21230 | /* 57735 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 21231 | /* 57738 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrshifts), |
| 21232 | /* 57743 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 21233 | /* 57746 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 21234 | /* 57749 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 21235 | /* 57752 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21236 | /* 57756 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21237 | /* 57760 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21238 | /* 57764 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3824:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) => (VQRSHLsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) |
| 21239 | /* 57764 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLsv8i16), |
| 21240 | /* 57767 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21241 | /* 57769 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 21242 | /* 57771 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 21243 | /* 57773 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21244 | /* 57776 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21245 | /* 57782 */ GIR_RootConstrainSelectedInstOperands, |
| 21246 | /* 57783 */ // GIR_Coverage, 1437, |
| 21247 | /* 57783 */ GIR_EraseRootFromParent_Done, |
| 21248 | /* 57784 */ // Label 1238: @57784 |
| 21249 | /* 57784 */ GIM_Try, /*On fail goto*//*Label 1239*/ GIMT_Encode4(57838), // Rule ID 1438 // |
| 21250 | /* 57789 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 21251 | /* 57792 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrshifts), |
| 21252 | /* 57797 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 21253 | /* 57800 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 21254 | /* 57803 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 21255 | /* 57806 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21256 | /* 57810 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21257 | /* 57814 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21258 | /* 57818 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3824:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) => (VQRSHLsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) |
| 21259 | /* 57818 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLsv4i32), |
| 21260 | /* 57821 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21261 | /* 57823 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 21262 | /* 57825 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 21263 | /* 57827 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21264 | /* 57830 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21265 | /* 57836 */ GIR_RootConstrainSelectedInstOperands, |
| 21266 | /* 57837 */ // GIR_Coverage, 1438, |
| 21267 | /* 57837 */ GIR_EraseRootFromParent_Done, |
| 21268 | /* 57838 */ // Label 1239: @57838 |
| 21269 | /* 57838 */ GIM_Try, /*On fail goto*//*Label 1240*/ GIMT_Encode4(57892), // Rule ID 1439 // |
| 21270 | /* 57843 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 21271 | /* 57846 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrshifts), |
| 21272 | /* 57851 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, |
| 21273 | /* 57854 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 21274 | /* 57857 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 21275 | /* 57860 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21276 | /* 57864 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21277 | /* 57868 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21278 | /* 57872 */ // (intrinsic_wo_chain:{ *:[v8i8] } 3824:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) => (VQRSHLsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) |
| 21279 | /* 57872 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLsv8i8), |
| 21280 | /* 57875 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21281 | /* 57877 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 21282 | /* 57879 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 21283 | /* 57881 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21284 | /* 57884 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21285 | /* 57890 */ GIR_RootConstrainSelectedInstOperands, |
| 21286 | /* 57891 */ // GIR_Coverage, 1439, |
| 21287 | /* 57891 */ GIR_EraseRootFromParent_Done, |
| 21288 | /* 57892 */ // Label 1240: @57892 |
| 21289 | /* 57892 */ GIM_Try, /*On fail goto*//*Label 1241*/ GIMT_Encode4(57946), // Rule ID 1440 // |
| 21290 | /* 57897 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 21291 | /* 57900 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrshifts), |
| 21292 | /* 57905 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 21293 | /* 57908 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 21294 | /* 57911 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 21295 | /* 57914 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21296 | /* 57918 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21297 | /* 57922 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21298 | /* 57926 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3824:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) => (VQRSHLsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) |
| 21299 | /* 57926 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLsv16i8), |
| 21300 | /* 57929 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21301 | /* 57931 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 21302 | /* 57933 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 21303 | /* 57935 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21304 | /* 57938 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21305 | /* 57944 */ GIR_RootConstrainSelectedInstOperands, |
| 21306 | /* 57945 */ // GIR_Coverage, 1440, |
| 21307 | /* 57945 */ GIR_EraseRootFromParent_Done, |
| 21308 | /* 57946 */ // Label 1241: @57946 |
| 21309 | /* 57946 */ GIM_Try, /*On fail goto*//*Label 1242*/ GIMT_Encode4(58000), // Rule ID 1441 // |
| 21310 | /* 57951 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 21311 | /* 57954 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrshifts), |
| 21312 | /* 57959 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 21313 | /* 57962 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 21314 | /* 57965 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 21315 | /* 57968 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21316 | /* 57972 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21317 | /* 57976 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21318 | /* 57980 */ // (intrinsic_wo_chain:{ *:[v1i64] } 3824:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) => (VQRSHLsv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) |
| 21319 | /* 57980 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLsv1i64), |
| 21320 | /* 57983 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21321 | /* 57985 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 21322 | /* 57987 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 21323 | /* 57989 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21324 | /* 57992 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21325 | /* 57998 */ GIR_RootConstrainSelectedInstOperands, |
| 21326 | /* 57999 */ // GIR_Coverage, 1441, |
| 21327 | /* 57999 */ GIR_EraseRootFromParent_Done, |
| 21328 | /* 58000 */ // Label 1242: @58000 |
| 21329 | /* 58000 */ GIM_Try, /*On fail goto*//*Label 1243*/ GIMT_Encode4(58054), // Rule ID 1442 // |
| 21330 | /* 58005 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 21331 | /* 58008 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrshifts), |
| 21332 | /* 58013 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 21333 | /* 58016 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 21334 | /* 58019 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 21335 | /* 58022 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21336 | /* 58026 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21337 | /* 58030 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21338 | /* 58034 */ // (intrinsic_wo_chain:{ *:[v2i64] } 3824:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) => (VQRSHLsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) |
| 21339 | /* 58034 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLsv2i64), |
| 21340 | /* 58037 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21341 | /* 58039 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 21342 | /* 58041 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 21343 | /* 58043 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21344 | /* 58046 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21345 | /* 58052 */ GIR_RootConstrainSelectedInstOperands, |
| 21346 | /* 58053 */ // GIR_Coverage, 1442, |
| 21347 | /* 58053 */ GIR_EraseRootFromParent_Done, |
| 21348 | /* 58054 */ // Label 1243: @58054 |
| 21349 | /* 58054 */ GIM_Try, /*On fail goto*//*Label 1244*/ GIMT_Encode4(58108), // Rule ID 1443 // |
| 21350 | /* 58059 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 21351 | /* 58062 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrshiftu), |
| 21352 | /* 58067 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 21353 | /* 58070 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 21354 | /* 58073 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 21355 | /* 58076 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21356 | /* 58080 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21357 | /* 58084 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21358 | /* 58088 */ // (intrinsic_wo_chain:{ *:[v4i16] } 3825:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) => (VQRSHLuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) |
| 21359 | /* 58088 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLuv4i16), |
| 21360 | /* 58091 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21361 | /* 58093 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 21362 | /* 58095 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 21363 | /* 58097 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21364 | /* 58100 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21365 | /* 58106 */ GIR_RootConstrainSelectedInstOperands, |
| 21366 | /* 58107 */ // GIR_Coverage, 1443, |
| 21367 | /* 58107 */ GIR_EraseRootFromParent_Done, |
| 21368 | /* 58108 */ // Label 1244: @58108 |
| 21369 | /* 58108 */ GIM_Try, /*On fail goto*//*Label 1245*/ GIMT_Encode4(58162), // Rule ID 1444 // |
| 21370 | /* 58113 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 21371 | /* 58116 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrshiftu), |
| 21372 | /* 58121 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 21373 | /* 58124 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 21374 | /* 58127 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 21375 | /* 58130 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21376 | /* 58134 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21377 | /* 58138 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21378 | /* 58142 */ // (intrinsic_wo_chain:{ *:[v2i32] } 3825:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) => (VQRSHLuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) |
| 21379 | /* 58142 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLuv2i32), |
| 21380 | /* 58145 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21381 | /* 58147 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 21382 | /* 58149 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 21383 | /* 58151 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21384 | /* 58154 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21385 | /* 58160 */ GIR_RootConstrainSelectedInstOperands, |
| 21386 | /* 58161 */ // GIR_Coverage, 1444, |
| 21387 | /* 58161 */ GIR_EraseRootFromParent_Done, |
| 21388 | /* 58162 */ // Label 1245: @58162 |
| 21389 | /* 58162 */ GIM_Try, /*On fail goto*//*Label 1246*/ GIMT_Encode4(58216), // Rule ID 1445 // |
| 21390 | /* 58167 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 21391 | /* 58170 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrshiftu), |
| 21392 | /* 58175 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 21393 | /* 58178 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 21394 | /* 58181 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 21395 | /* 58184 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21396 | /* 58188 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21397 | /* 58192 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21398 | /* 58196 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3825:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) => (VQRSHLuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) |
| 21399 | /* 58196 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLuv8i16), |
| 21400 | /* 58199 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21401 | /* 58201 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 21402 | /* 58203 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 21403 | /* 58205 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21404 | /* 58208 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21405 | /* 58214 */ GIR_RootConstrainSelectedInstOperands, |
| 21406 | /* 58215 */ // GIR_Coverage, 1445, |
| 21407 | /* 58215 */ GIR_EraseRootFromParent_Done, |
| 21408 | /* 58216 */ // Label 1246: @58216 |
| 21409 | /* 58216 */ GIM_Try, /*On fail goto*//*Label 1247*/ GIMT_Encode4(58270), // Rule ID 1446 // |
| 21410 | /* 58221 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 21411 | /* 58224 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrshiftu), |
| 21412 | /* 58229 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 21413 | /* 58232 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 21414 | /* 58235 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 21415 | /* 58238 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21416 | /* 58242 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21417 | /* 58246 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21418 | /* 58250 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3825:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) => (VQRSHLuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) |
| 21419 | /* 58250 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLuv4i32), |
| 21420 | /* 58253 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21421 | /* 58255 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 21422 | /* 58257 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 21423 | /* 58259 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21424 | /* 58262 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21425 | /* 58268 */ GIR_RootConstrainSelectedInstOperands, |
| 21426 | /* 58269 */ // GIR_Coverage, 1446, |
| 21427 | /* 58269 */ GIR_EraseRootFromParent_Done, |
| 21428 | /* 58270 */ // Label 1247: @58270 |
| 21429 | /* 58270 */ GIM_Try, /*On fail goto*//*Label 1248*/ GIMT_Encode4(58324), // Rule ID 1447 // |
| 21430 | /* 58275 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 21431 | /* 58278 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrshiftu), |
| 21432 | /* 58283 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, |
| 21433 | /* 58286 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 21434 | /* 58289 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 21435 | /* 58292 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21436 | /* 58296 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21437 | /* 58300 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21438 | /* 58304 */ // (intrinsic_wo_chain:{ *:[v8i8] } 3825:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) => (VQRSHLuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) |
| 21439 | /* 58304 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLuv8i8), |
| 21440 | /* 58307 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21441 | /* 58309 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 21442 | /* 58311 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 21443 | /* 58313 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21444 | /* 58316 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21445 | /* 58322 */ GIR_RootConstrainSelectedInstOperands, |
| 21446 | /* 58323 */ // GIR_Coverage, 1447, |
| 21447 | /* 58323 */ GIR_EraseRootFromParent_Done, |
| 21448 | /* 58324 */ // Label 1248: @58324 |
| 21449 | /* 58324 */ GIM_Try, /*On fail goto*//*Label 1249*/ GIMT_Encode4(58378), // Rule ID 1448 // |
| 21450 | /* 58329 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 21451 | /* 58332 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrshiftu), |
| 21452 | /* 58337 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 21453 | /* 58340 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 21454 | /* 58343 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 21455 | /* 58346 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21456 | /* 58350 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21457 | /* 58354 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21458 | /* 58358 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3825:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) => (VQRSHLuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) |
| 21459 | /* 58358 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLuv16i8), |
| 21460 | /* 58361 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21461 | /* 58363 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 21462 | /* 58365 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 21463 | /* 58367 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21464 | /* 58370 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21465 | /* 58376 */ GIR_RootConstrainSelectedInstOperands, |
| 21466 | /* 58377 */ // GIR_Coverage, 1448, |
| 21467 | /* 58377 */ GIR_EraseRootFromParent_Done, |
| 21468 | /* 58378 */ // Label 1249: @58378 |
| 21469 | /* 58378 */ GIM_Try, /*On fail goto*//*Label 1250*/ GIMT_Encode4(58432), // Rule ID 1449 // |
| 21470 | /* 58383 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 21471 | /* 58386 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrshiftu), |
| 21472 | /* 58391 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 21473 | /* 58394 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 21474 | /* 58397 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 21475 | /* 58400 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21476 | /* 58404 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21477 | /* 58408 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21478 | /* 58412 */ // (intrinsic_wo_chain:{ *:[v1i64] } 3825:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) => (VQRSHLuv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) |
| 21479 | /* 58412 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLuv1i64), |
| 21480 | /* 58415 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21481 | /* 58417 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 21482 | /* 58419 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 21483 | /* 58421 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21484 | /* 58424 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21485 | /* 58430 */ GIR_RootConstrainSelectedInstOperands, |
| 21486 | /* 58431 */ // GIR_Coverage, 1449, |
| 21487 | /* 58431 */ GIR_EraseRootFromParent_Done, |
| 21488 | /* 58432 */ // Label 1250: @58432 |
| 21489 | /* 58432 */ GIM_Try, /*On fail goto*//*Label 1251*/ GIMT_Encode4(58486), // Rule ID 1450 // |
| 21490 | /* 58437 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 21491 | /* 58440 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrshiftu), |
| 21492 | /* 58445 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 21493 | /* 58448 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 21494 | /* 58451 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 21495 | /* 58454 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21496 | /* 58458 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21497 | /* 58462 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21498 | /* 58466 */ // (intrinsic_wo_chain:{ *:[v2i64] } 3825:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) => (VQRSHLuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) |
| 21499 | /* 58466 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLuv2i64), |
| 21500 | /* 58469 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21501 | /* 58471 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 21502 | /* 58473 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 21503 | /* 58475 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21504 | /* 58478 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21505 | /* 58484 */ GIR_RootConstrainSelectedInstOperands, |
| 21506 | /* 58485 */ // GIR_Coverage, 1450, |
| 21507 | /* 58485 */ GIR_EraseRootFromParent_Done, |
| 21508 | /* 58486 */ // Label 1251: @58486 |
| 21509 | /* 58486 */ GIM_Try, /*On fail goto*//*Label 1252*/ GIMT_Encode4(58531), // Rule ID 1715 // |
| 21510 | /* 58491 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAES_HasV8), |
| 21511 | /* 58494 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_aesd), |
| 21512 | /* 58499 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 21513 | /* 58502 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 21514 | /* 58505 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 21515 | /* 58508 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21516 | /* 58512 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21517 | /* 58516 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21518 | /* 58520 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3726:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$src, QPR:{ *:[v16i8] }:$Vm) => (AESD:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src, QPR:{ *:[v16i8] }:$Vm) |
| 21519 | /* 58520 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::AESD), |
| 21520 | /* 58523 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21521 | /* 58525 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 21522 | /* 58527 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 21523 | /* 58529 */ GIR_RootConstrainSelectedInstOperands, |
| 21524 | /* 58530 */ // GIR_Coverage, 1715, |
| 21525 | /* 58530 */ GIR_EraseRootFromParent_Done, |
| 21526 | /* 58531 */ // Label 1252: @58531 |
| 21527 | /* 58531 */ GIM_Try, /*On fail goto*//*Label 1253*/ GIMT_Encode4(58576), // Rule ID 1716 // |
| 21528 | /* 58536 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAES_HasV8), |
| 21529 | /* 58539 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_aese), |
| 21530 | /* 58544 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 21531 | /* 58547 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 21532 | /* 58550 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 21533 | /* 58553 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21534 | /* 58557 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21535 | /* 58561 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21536 | /* 58565 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3727:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$src, QPR:{ *:[v16i8] }:$Vm) => (AESE:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src, QPR:{ *:[v16i8] }:$Vm) |
| 21537 | /* 58565 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::AESE), |
| 21538 | /* 58568 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21539 | /* 58570 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 21540 | /* 58572 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 21541 | /* 58574 */ GIR_RootConstrainSelectedInstOperands, |
| 21542 | /* 58575 */ // GIR_Coverage, 1716, |
| 21543 | /* 58575 */ GIR_EraseRootFromParent_Done, |
| 21544 | /* 58576 */ // Label 1253: @58576 |
| 21545 | /* 58576 */ GIM_Try, /*On fail goto*//*Label 1254*/ GIMT_Encode4(58621), // Rule ID 1719 // |
| 21546 | /* 58581 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA2_HasV8), |
| 21547 | /* 58584 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sha1su1), |
| 21548 | /* 58589 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 21549 | /* 58592 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 21550 | /* 58595 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 21551 | /* 58598 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21552 | /* 58602 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21553 | /* 58606 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21554 | /* 58610 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3740:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vm) => (SHA1SU1:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vm) |
| 21555 | /* 58610 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHA1SU1), |
| 21556 | /* 58613 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21557 | /* 58615 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 21558 | /* 58617 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 21559 | /* 58619 */ GIR_RootConstrainSelectedInstOperands, |
| 21560 | /* 58620 */ // GIR_Coverage, 1719, |
| 21561 | /* 58620 */ GIR_EraseRootFromParent_Done, |
| 21562 | /* 58621 */ // Label 1254: @58621 |
| 21563 | /* 58621 */ GIM_Try, /*On fail goto*//*Label 1255*/ GIMT_Encode4(58666), // Rule ID 1720 // |
| 21564 | /* 58626 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA2_HasV8), |
| 21565 | /* 58629 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sha256su0), |
| 21566 | /* 58634 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 21567 | /* 58637 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 21568 | /* 58640 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 21569 | /* 58643 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21570 | /* 58647 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21571 | /* 58651 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21572 | /* 58655 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3743:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vm) => (SHA256SU0:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vm) |
| 21573 | /* 58655 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHA256SU0), |
| 21574 | /* 58658 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21575 | /* 58660 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 21576 | /* 58662 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 21577 | /* 58664 */ GIR_RootConstrainSelectedInstOperands, |
| 21578 | /* 58665 */ // GIR_Coverage, 1720, |
| 21579 | /* 58665 */ GIR_EraseRootFromParent_Done, |
| 21580 | /* 58666 */ // Label 1255: @58666 |
| 21581 | /* 58666 */ GIM_Try, /*On fail goto*//*Label 1256*/ GIMT_Encode4(58720), // Rule ID 1729 // |
| 21582 | /* 58671 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_HasV8_1MMainline), |
| 21583 | /* 58674 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_sqrshr), |
| 21584 | /* 58679 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 21585 | /* 58682 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 21586 | /* 58685 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 21587 | /* 58688 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 21588 | /* 58692 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 21589 | /* 58696 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 21590 | /* 58700 */ // (intrinsic_wo_chain:{ *:[i32] } 3589:{ *:[iPTR] }, rGPR:{ *:[i32] }:$RdaSrc, rGPR:{ *:[i32] }:$Rm) => (MVE_SQRSHR:{ *:[i32] } rGPR:{ *:[i32] }:$RdaSrc, rGPR:{ *:[i32] }:$Rm) |
| 21591 | /* 58700 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_SQRSHR), |
| 21592 | /* 58703 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 21593 | /* 58705 */ GIR_RootToRootCopy, /*OpIdx*/2, // RdaSrc |
| 21594 | /* 58707 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 21595 | /* 58709 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21596 | /* 58712 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21597 | /* 58718 */ GIR_RootConstrainSelectedInstOperands, |
| 21598 | /* 58719 */ // GIR_Coverage, 1729, |
| 21599 | /* 58719 */ GIR_EraseRootFromParent_Done, |
| 21600 | /* 58720 */ // Label 1256: @58720 |
| 21601 | /* 58720 */ GIM_Try, /*On fail goto*//*Label 1257*/ GIMT_Encode4(58774), // Rule ID 1730 // |
| 21602 | /* 58725 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_HasV8_1MMainline), |
| 21603 | /* 58728 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_uqrshl), |
| 21604 | /* 58733 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 21605 | /* 58736 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 21606 | /* 58739 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 21607 | /* 58742 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 21608 | /* 58746 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 21609 | /* 58750 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 21610 | /* 58754 */ // (intrinsic_wo_chain:{ *:[i32] } 3596:{ *:[iPTR] }, rGPR:{ *:[i32] }:$RdaSrc, rGPR:{ *:[i32] }:$Rm) => (MVE_UQRSHL:{ *:[i32] } rGPR:{ *:[i32] }:$RdaSrc, rGPR:{ *:[i32] }:$Rm) |
| 21611 | /* 58754 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_UQRSHL), |
| 21612 | /* 58757 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 21613 | /* 58759 */ GIR_RootToRootCopy, /*OpIdx*/2, // RdaSrc |
| 21614 | /* 58761 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 21615 | /* 58763 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21616 | /* 58766 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21617 | /* 58772 */ GIR_RootConstrainSelectedInstOperands, |
| 21618 | /* 58773 */ // GIR_Coverage, 1730, |
| 21619 | /* 58773 */ GIR_EraseRootFromParent_Done, |
| 21620 | /* 58774 */ // Label 1257: @58774 |
| 21621 | /* 58774 */ GIM_Try, /*On fail goto*//*Label 1258*/ GIMT_Encode4(58831), // Rule ID 1853 // |
| 21622 | /* 58779 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 21623 | /* 58782 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sxtab16), |
| 21624 | /* 58787 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 21625 | /* 58790 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 21626 | /* 58793 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 21627 | /* 58796 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 21628 | /* 58800 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 21629 | /* 58804 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 21630 | /* 58808 */ // (intrinsic_wo_chain:{ *:[i32] } 3922:{ *:[iPTR] }, GPR:{ *:[i32] }:$LHS, GPR:{ *:[i32] }:$RHS) => (SXTAB16:{ *:[i32] } GPR:{ *:[i32] }:$LHS, GPR:{ *:[i32] }:$RHS, 0:{ *:[i32] }) |
| 21631 | /* 58808 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SXTAB16), |
| 21632 | /* 58811 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 21633 | /* 58813 */ GIR_RootToRootCopy, /*OpIdx*/2, // LHS |
| 21634 | /* 58815 */ GIR_RootToRootCopy, /*OpIdx*/3, // RHS |
| 21635 | /* 58817 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21636 | /* 58820 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21637 | /* 58823 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21638 | /* 58829 */ GIR_RootConstrainSelectedInstOperands, |
| 21639 | /* 58830 */ // GIR_Coverage, 1853, |
| 21640 | /* 58830 */ GIR_EraseRootFromParent_Done, |
| 21641 | /* 58831 */ // Label 1258: @58831 |
| 21642 | /* 58831 */ GIM_Try, /*On fail goto*//*Label 1259*/ GIMT_Encode4(58888), // Rule ID 1860 // |
| 21643 | /* 58836 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 21644 | /* 58839 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uxtab16), |
| 21645 | /* 58844 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 21646 | /* 58847 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 21647 | /* 58850 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 21648 | /* 58853 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 21649 | /* 58857 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 21650 | /* 58861 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 21651 | /* 58865 */ // (intrinsic_wo_chain:{ *:[i32] } 3947:{ *:[iPTR] }, GPR:{ *:[i32] }:$LHS, GPR:{ *:[i32] }:$RHS) => (UXTAB16:{ *:[i32] } GPR:{ *:[i32] }:$LHS, GPR:{ *:[i32] }:$RHS, 0:{ *:[i32] }) |
| 21652 | /* 58865 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UXTAB16), |
| 21653 | /* 58868 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 21654 | /* 58870 */ GIR_RootToRootCopy, /*OpIdx*/2, // LHS |
| 21655 | /* 58872 */ GIR_RootToRootCopy, /*OpIdx*/3, // RHS |
| 21656 | /* 58874 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21657 | /* 58877 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21658 | /* 58880 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21659 | /* 58886 */ GIR_RootConstrainSelectedInstOperands, |
| 21660 | /* 58887 */ // GIR_Coverage, 1860, |
| 21661 | /* 58887 */ GIR_EraseRootFromParent_Done, |
| 21662 | /* 58888 */ // Label 1259: @58888 |
| 21663 | /* 58888 */ GIM_Try, /*On fail goto*//*Label 1260*/ GIMT_Encode4(58942), // Rule ID 1907 // |
| 21664 | /* 58893 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 21665 | /* 58896 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smuad), |
| 21666 | /* 58901 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 21667 | /* 58904 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 21668 | /* 58907 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 21669 | /* 58910 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 21670 | /* 58914 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 21671 | /* 58918 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 21672 | /* 58922 */ // (intrinsic_wo_chain:{ *:[i32] } 3898:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SMUAD:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 21673 | /* 58922 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMUAD), |
| 21674 | /* 58925 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 21675 | /* 58927 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 21676 | /* 58929 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 21677 | /* 58931 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21678 | /* 58934 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21679 | /* 58940 */ GIR_RootConstrainSelectedInstOperands, |
| 21680 | /* 58941 */ // GIR_Coverage, 1907, |
| 21681 | /* 58941 */ GIR_EraseRootFromParent_Done, |
| 21682 | /* 58942 */ // Label 1260: @58942 |
| 21683 | /* 58942 */ GIM_Try, /*On fail goto*//*Label 1261*/ GIMT_Encode4(58996), // Rule ID 1908 // |
| 21684 | /* 58947 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 21685 | /* 58950 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smuadx), |
| 21686 | /* 58955 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 21687 | /* 58958 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 21688 | /* 58961 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 21689 | /* 58964 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 21690 | /* 58968 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 21691 | /* 58972 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 21692 | /* 58976 */ // (intrinsic_wo_chain:{ *:[i32] } 3899:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SMUADX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 21693 | /* 58976 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMUADX), |
| 21694 | /* 58979 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 21695 | /* 58981 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 21696 | /* 58983 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 21697 | /* 58985 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21698 | /* 58988 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21699 | /* 58994 */ GIR_RootConstrainSelectedInstOperands, |
| 21700 | /* 58995 */ // GIR_Coverage, 1908, |
| 21701 | /* 58995 */ GIR_EraseRootFromParent_Done, |
| 21702 | /* 58996 */ // Label 1261: @58996 |
| 21703 | /* 58996 */ GIM_Try, /*On fail goto*//*Label 1262*/ GIMT_Encode4(59050), // Rule ID 1909 // |
| 21704 | /* 59001 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 21705 | /* 59004 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smusd), |
| 21706 | /* 59009 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 21707 | /* 59012 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 21708 | /* 59015 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 21709 | /* 59018 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 21710 | /* 59022 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 21711 | /* 59026 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 21712 | /* 59030 */ // (intrinsic_wo_chain:{ *:[i32] } 3906:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SMUSD:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 21713 | /* 59030 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMUSD), |
| 21714 | /* 59033 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 21715 | /* 59035 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 21716 | /* 59037 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 21717 | /* 59039 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21718 | /* 59042 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21719 | /* 59048 */ GIR_RootConstrainSelectedInstOperands, |
| 21720 | /* 59049 */ // GIR_Coverage, 1909, |
| 21721 | /* 59049 */ GIR_EraseRootFromParent_Done, |
| 21722 | /* 59050 */ // Label 1262: @59050 |
| 21723 | /* 59050 */ GIM_Try, /*On fail goto*//*Label 1263*/ GIMT_Encode4(59104), // Rule ID 1910 // |
| 21724 | /* 59055 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 21725 | /* 59058 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smusdx), |
| 21726 | /* 59063 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 21727 | /* 59066 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 21728 | /* 59069 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 21729 | /* 59072 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 21730 | /* 59076 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 21731 | /* 59080 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 21732 | /* 59084 */ // (intrinsic_wo_chain:{ *:[i32] } 3907:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SMUSDX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 21733 | /* 59084 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMUSDX), |
| 21734 | /* 59087 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 21735 | /* 59089 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 21736 | /* 59091 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 21737 | /* 59093 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21738 | /* 59096 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21739 | /* 59102 */ GIR_RootConstrainSelectedInstOperands, |
| 21740 | /* 59103 */ // GIR_Coverage, 1910, |
| 21741 | /* 59103 */ GIR_EraseRootFromParent_Done, |
| 21742 | /* 59104 */ // Label 1263: @59104 |
| 21743 | /* 59104 */ GIM_Try, /*On fail goto*//*Label 1264*/ GIMT_Encode4(59158), // Rule ID 1984 // |
| 21744 | /* 59109 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM), |
| 21745 | /* 59112 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smulbb), |
| 21746 | /* 59117 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 21747 | /* 59120 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 21748 | /* 59123 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 21749 | /* 59126 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 21750 | /* 59130 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 21751 | /* 59134 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 21752 | /* 59138 */ // (intrinsic_wo_chain:{ *:[i32] } 3900:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) => (SMULBB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) |
| 21753 | /* 59138 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMULBB), |
| 21754 | /* 59141 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 21755 | /* 59143 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 21756 | /* 59145 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 21757 | /* 59147 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21758 | /* 59150 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21759 | /* 59156 */ GIR_RootConstrainSelectedInstOperands, |
| 21760 | /* 59157 */ // GIR_Coverage, 1984, |
| 21761 | /* 59157 */ GIR_EraseRootFromParent_Done, |
| 21762 | /* 59158 */ // Label 1264: @59158 |
| 21763 | /* 59158 */ GIM_Try, /*On fail goto*//*Label 1265*/ GIMT_Encode4(59212), // Rule ID 1985 // |
| 21764 | /* 59163 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM), |
| 21765 | /* 59166 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smulbt), |
| 21766 | /* 59171 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 21767 | /* 59174 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 21768 | /* 59177 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 21769 | /* 59180 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 21770 | /* 59184 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 21771 | /* 59188 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 21772 | /* 59192 */ // (intrinsic_wo_chain:{ *:[i32] } 3901:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) => (SMULBT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) |
| 21773 | /* 59192 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMULBT), |
| 21774 | /* 59195 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 21775 | /* 59197 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 21776 | /* 59199 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 21777 | /* 59201 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21778 | /* 59204 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21779 | /* 59210 */ GIR_RootConstrainSelectedInstOperands, |
| 21780 | /* 59211 */ // GIR_Coverage, 1985, |
| 21781 | /* 59211 */ GIR_EraseRootFromParent_Done, |
| 21782 | /* 59212 */ // Label 1265: @59212 |
| 21783 | /* 59212 */ GIM_Try, /*On fail goto*//*Label 1266*/ GIMT_Encode4(59266), // Rule ID 1986 // |
| 21784 | /* 59217 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM), |
| 21785 | /* 59220 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smultb), |
| 21786 | /* 59225 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 21787 | /* 59228 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 21788 | /* 59231 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 21789 | /* 59234 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 21790 | /* 59238 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 21791 | /* 59242 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 21792 | /* 59246 */ // (intrinsic_wo_chain:{ *:[i32] } 3902:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) => (SMULTB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) |
| 21793 | /* 59246 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMULTB), |
| 21794 | /* 59249 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 21795 | /* 59251 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 21796 | /* 59253 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 21797 | /* 59255 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21798 | /* 59258 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21799 | /* 59264 */ GIR_RootConstrainSelectedInstOperands, |
| 21800 | /* 59265 */ // GIR_Coverage, 1986, |
| 21801 | /* 59265 */ GIR_EraseRootFromParent_Done, |
| 21802 | /* 59266 */ // Label 1266: @59266 |
| 21803 | /* 59266 */ GIM_Try, /*On fail goto*//*Label 1267*/ GIMT_Encode4(59320), // Rule ID 1987 // |
| 21804 | /* 59271 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM), |
| 21805 | /* 59274 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smultt), |
| 21806 | /* 59279 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 21807 | /* 59282 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 21808 | /* 59285 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 21809 | /* 59288 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 21810 | /* 59292 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 21811 | /* 59296 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 21812 | /* 59300 */ // (intrinsic_wo_chain:{ *:[i32] } 3903:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) => (SMULTT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) |
| 21813 | /* 59300 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMULTT), |
| 21814 | /* 59303 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 21815 | /* 59305 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 21816 | /* 59307 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 21817 | /* 59309 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21818 | /* 59312 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21819 | /* 59318 */ GIR_RootConstrainSelectedInstOperands, |
| 21820 | /* 59319 */ // GIR_Coverage, 1987, |
| 21821 | /* 59319 */ GIR_EraseRootFromParent_Done, |
| 21822 | /* 59320 */ // Label 1267: @59320 |
| 21823 | /* 59320 */ GIM_Try, /*On fail goto*//*Label 1268*/ GIMT_Encode4(59374), // Rule ID 1988 // |
| 21824 | /* 59325 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM), |
| 21825 | /* 59328 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smulwb), |
| 21826 | /* 59333 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 21827 | /* 59336 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 21828 | /* 59339 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 21829 | /* 59342 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 21830 | /* 59346 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 21831 | /* 59350 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 21832 | /* 59354 */ // (intrinsic_wo_chain:{ *:[i32] } 3904:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) => (SMULWB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) |
| 21833 | /* 59354 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMULWB), |
| 21834 | /* 59357 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 21835 | /* 59359 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 21836 | /* 59361 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 21837 | /* 59363 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21838 | /* 59366 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21839 | /* 59372 */ GIR_RootConstrainSelectedInstOperands, |
| 21840 | /* 59373 */ // GIR_Coverage, 1988, |
| 21841 | /* 59373 */ GIR_EraseRootFromParent_Done, |
| 21842 | /* 59374 */ // Label 1268: @59374 |
| 21843 | /* 59374 */ GIM_Try, /*On fail goto*//*Label 1269*/ GIMT_Encode4(59428), // Rule ID 1989 // |
| 21844 | /* 59379 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM), |
| 21845 | /* 59382 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smulwt), |
| 21846 | /* 59387 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 21847 | /* 59390 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 21848 | /* 59393 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 21849 | /* 59396 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 21850 | /* 59400 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 21851 | /* 59404 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 21852 | /* 59408 */ // (intrinsic_wo_chain:{ *:[i32] } 3905:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) => (SMULWT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) |
| 21853 | /* 59408 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMULWT), |
| 21854 | /* 59411 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 21855 | /* 59413 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 21856 | /* 59415 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 21857 | /* 59417 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21858 | /* 59420 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21859 | /* 59426 */ GIR_RootConstrainSelectedInstOperands, |
| 21860 | /* 59427 */ // GIR_Coverage, 1989, |
| 21861 | /* 59427 */ GIR_EraseRootFromParent_Done, |
| 21862 | /* 59428 */ // Label 1269: @59428 |
| 21863 | /* 59428 */ GIM_Try, /*On fail goto*//*Label 1270*/ GIMT_Encode4(59485), // Rule ID 2100 // |
| 21864 | /* 59433 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 21865 | /* 59436 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sxtab16), |
| 21866 | /* 59441 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 21867 | /* 59444 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 21868 | /* 59447 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 21869 | /* 59450 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 21870 | /* 59454 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 21871 | /* 59458 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 21872 | /* 59462 */ // (intrinsic_wo_chain:{ *:[i32] } 3922:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SXTAB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] }) |
| 21873 | /* 59462 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SXTAB16), |
| 21874 | /* 59465 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 21875 | /* 59467 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 21876 | /* 59469 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 21877 | /* 59471 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21878 | /* 59474 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21879 | /* 59477 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21880 | /* 59483 */ GIR_RootConstrainSelectedInstOperands, |
| 21881 | /* 59484 */ // GIR_Coverage, 2100, |
| 21882 | /* 59484 */ GIR_EraseRootFromParent_Done, |
| 21883 | /* 59485 */ // Label 1270: @59485 |
| 21884 | /* 59485 */ GIM_Try, /*On fail goto*//*Label 1271*/ GIMT_Encode4(59539), // Rule ID 2130 // |
| 21885 | /* 59490 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 21886 | /* 59493 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd), |
| 21887 | /* 59498 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 21888 | /* 59501 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 21889 | /* 59504 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 21890 | /* 59507 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 21891 | /* 59511 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 21892 | /* 59515 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 21893 | /* 59519 */ // (intrinsic_wo_chain:{ *:[i32] } 3865:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn) => (t2QADD:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn) |
| 21894 | /* 59519 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QADD), |
| 21895 | /* 59522 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 21896 | /* 59524 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 21897 | /* 59526 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rn |
| 21898 | /* 59528 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21899 | /* 59531 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21900 | /* 59537 */ GIR_RootConstrainSelectedInstOperands, |
| 21901 | /* 59538 */ // GIR_Coverage, 2130, |
| 21902 | /* 59538 */ GIR_EraseRootFromParent_Done, |
| 21903 | /* 59539 */ // Label 1271: @59539 |
| 21904 | /* 59539 */ GIM_Try, /*On fail goto*//*Label 1272*/ GIMT_Encode4(59593), // Rule ID 2131 // |
| 21905 | /* 59544 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 21906 | /* 59547 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qsub), |
| 21907 | /* 59552 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 21908 | /* 59555 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 21909 | /* 59558 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 21910 | /* 59561 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 21911 | /* 59565 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 21912 | /* 59569 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 21913 | /* 59573 */ // (intrinsic_wo_chain:{ *:[i32] } 3870:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn) => (t2QSUB:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn) |
| 21914 | /* 59573 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QSUB), |
| 21915 | /* 59576 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 21916 | /* 59578 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 21917 | /* 59580 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rn |
| 21918 | /* 59582 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21919 | /* 59585 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21920 | /* 59591 */ GIR_RootConstrainSelectedInstOperands, |
| 21921 | /* 59592 */ // GIR_Coverage, 2131, |
| 21922 | /* 59592 */ GIR_EraseRootFromParent_Done, |
| 21923 | /* 59593 */ // Label 1272: @59593 |
| 21924 | /* 59593 */ GIM_Try, /*On fail goto*//*Label 1273*/ GIMT_Encode4(59647), // Rule ID 2171 // |
| 21925 | /* 59598 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 21926 | /* 59601 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smulbb), |
| 21927 | /* 59606 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 21928 | /* 59609 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 21929 | /* 59612 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 21930 | /* 59615 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 21931 | /* 59619 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 21932 | /* 59623 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 21933 | /* 59627 */ // (intrinsic_wo_chain:{ *:[i32] } 3900:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMULBB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 21934 | /* 59627 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMULBB), |
| 21935 | /* 59630 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 21936 | /* 59632 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 21937 | /* 59634 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 21938 | /* 59636 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21939 | /* 59639 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21940 | /* 59645 */ GIR_RootConstrainSelectedInstOperands, |
| 21941 | /* 59646 */ // GIR_Coverage, 2171, |
| 21942 | /* 59646 */ GIR_EraseRootFromParent_Done, |
| 21943 | /* 59647 */ // Label 1273: @59647 |
| 21944 | /* 59647 */ GIM_Try, /*On fail goto*//*Label 1274*/ GIMT_Encode4(59701), // Rule ID 2172 // |
| 21945 | /* 59652 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 21946 | /* 59655 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smulbt), |
| 21947 | /* 59660 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 21948 | /* 59663 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 21949 | /* 59666 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 21950 | /* 59669 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 21951 | /* 59673 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 21952 | /* 59677 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 21953 | /* 59681 */ // (intrinsic_wo_chain:{ *:[i32] } 3901:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMULBT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 21954 | /* 59681 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMULBT), |
| 21955 | /* 59684 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 21956 | /* 59686 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 21957 | /* 59688 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 21958 | /* 59690 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21959 | /* 59693 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21960 | /* 59699 */ GIR_RootConstrainSelectedInstOperands, |
| 21961 | /* 59700 */ // GIR_Coverage, 2172, |
| 21962 | /* 59700 */ GIR_EraseRootFromParent_Done, |
| 21963 | /* 59701 */ // Label 1274: @59701 |
| 21964 | /* 59701 */ GIM_Try, /*On fail goto*//*Label 1275*/ GIMT_Encode4(59755), // Rule ID 2173 // |
| 21965 | /* 59706 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 21966 | /* 59709 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smultb), |
| 21967 | /* 59714 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 21968 | /* 59717 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 21969 | /* 59720 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 21970 | /* 59723 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 21971 | /* 59727 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 21972 | /* 59731 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 21973 | /* 59735 */ // (intrinsic_wo_chain:{ *:[i32] } 3902:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMULTB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 21974 | /* 59735 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMULTB), |
| 21975 | /* 59738 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 21976 | /* 59740 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 21977 | /* 59742 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 21978 | /* 59744 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21979 | /* 59747 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21980 | /* 59753 */ GIR_RootConstrainSelectedInstOperands, |
| 21981 | /* 59754 */ // GIR_Coverage, 2173, |
| 21982 | /* 59754 */ GIR_EraseRootFromParent_Done, |
| 21983 | /* 59755 */ // Label 1275: @59755 |
| 21984 | /* 59755 */ GIM_Try, /*On fail goto*//*Label 1276*/ GIMT_Encode4(59809), // Rule ID 2174 // |
| 21985 | /* 59760 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 21986 | /* 59763 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smultt), |
| 21987 | /* 59768 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 21988 | /* 59771 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 21989 | /* 59774 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 21990 | /* 59777 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 21991 | /* 59781 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 21992 | /* 59785 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 21993 | /* 59789 */ // (intrinsic_wo_chain:{ *:[i32] } 3903:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMULTT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 21994 | /* 59789 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMULTT), |
| 21995 | /* 59792 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 21996 | /* 59794 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 21997 | /* 59796 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 21998 | /* 59798 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21999 | /* 59801 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22000 | /* 59807 */ GIR_RootConstrainSelectedInstOperands, |
| 22001 | /* 59808 */ // GIR_Coverage, 2174, |
| 22002 | /* 59808 */ GIR_EraseRootFromParent_Done, |
| 22003 | /* 59809 */ // Label 1276: @59809 |
| 22004 | /* 59809 */ GIM_Try, /*On fail goto*//*Label 1277*/ GIMT_Encode4(59863), // Rule ID 2175 // |
| 22005 | /* 59814 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 22006 | /* 59817 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smulwb), |
| 22007 | /* 59822 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 22008 | /* 59825 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 22009 | /* 59828 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 22010 | /* 59831 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 22011 | /* 59835 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 22012 | /* 59839 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 22013 | /* 59843 */ // (intrinsic_wo_chain:{ *:[i32] } 3904:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMULWB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 22014 | /* 59843 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMULWB), |
| 22015 | /* 59846 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 22016 | /* 59848 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 22017 | /* 59850 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 22018 | /* 59852 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22019 | /* 59855 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22020 | /* 59861 */ GIR_RootConstrainSelectedInstOperands, |
| 22021 | /* 59862 */ // GIR_Coverage, 2175, |
| 22022 | /* 59862 */ GIR_EraseRootFromParent_Done, |
| 22023 | /* 59863 */ // Label 1277: @59863 |
| 22024 | /* 59863 */ GIM_Try, /*On fail goto*//*Label 1278*/ GIMT_Encode4(59917), // Rule ID 2176 // |
| 22025 | /* 59868 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 22026 | /* 59871 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smulwt), |
| 22027 | /* 59876 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 22028 | /* 59879 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 22029 | /* 59882 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 22030 | /* 59885 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 22031 | /* 59889 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 22032 | /* 59893 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 22033 | /* 59897 */ // (intrinsic_wo_chain:{ *:[i32] } 3905:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMULWT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 22034 | /* 59897 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMULWT), |
| 22035 | /* 59900 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 22036 | /* 59902 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 22037 | /* 59904 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 22038 | /* 59906 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22039 | /* 59909 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22040 | /* 59915 */ GIR_RootConstrainSelectedInstOperands, |
| 22041 | /* 59916 */ // GIR_Coverage, 2176, |
| 22042 | /* 59916 */ GIR_EraseRootFromParent_Done, |
| 22043 | /* 59917 */ // Label 1278: @59917 |
| 22044 | /* 59917 */ GIM_Try, /*On fail goto*//*Label 1279*/ GIMT_Encode4(59965), // Rule ID 2513 // |
| 22045 | /* 59922 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8_3a), |
| 22046 | /* 59925 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcadd_rot90), |
| 22047 | /* 59930 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 22048 | /* 59933 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 22049 | /* 59936 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 22050 | /* 59939 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22051 | /* 59943 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22052 | /* 59947 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22053 | /* 59951 */ // (intrinsic_wo_chain:{ *:[v4f16] } 3757:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Rn, DPR:{ *:[v4f16] }:$Rm) => (VCADDv4f16:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Rn, DPR:{ *:[v4f16] }:$Rm, 0:{ *:[i32] }) |
| 22054 | /* 59951 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCADDv4f16), |
| 22055 | /* 59954 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22056 | /* 59956 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 22057 | /* 59958 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 22058 | /* 59960 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22059 | /* 59963 */ GIR_RootConstrainSelectedInstOperands, |
| 22060 | /* 59964 */ // GIR_Coverage, 2513, |
| 22061 | /* 59964 */ GIR_EraseRootFromParent_Done, |
| 22062 | /* 59965 */ // Label 1279: @59965 |
| 22063 | /* 59965 */ GIM_Try, /*On fail goto*//*Label 1280*/ GIMT_Encode4(60013), // Rule ID 2514 // |
| 22064 | /* 59970 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8_3a), |
| 22065 | /* 59973 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcadd_rot270), |
| 22066 | /* 59978 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 22067 | /* 59981 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 22068 | /* 59984 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 22069 | /* 59987 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22070 | /* 59991 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22071 | /* 59995 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22072 | /* 59999 */ // (intrinsic_wo_chain:{ *:[v4f16] } 3756:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Rn, DPR:{ *:[v4f16] }:$Rm) => (VCADDv4f16:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Rn, DPR:{ *:[v4f16] }:$Rm, 1:{ *:[i32] }) |
| 22073 | /* 59999 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCADDv4f16), |
| 22074 | /* 60002 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22075 | /* 60004 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 22076 | /* 60006 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 22077 | /* 60008 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 22078 | /* 60011 */ GIR_RootConstrainSelectedInstOperands, |
| 22079 | /* 60012 */ // GIR_Coverage, 2514, |
| 22080 | /* 60012 */ GIR_EraseRootFromParent_Done, |
| 22081 | /* 60013 */ // Label 1280: @60013 |
| 22082 | /* 60013 */ GIM_Try, /*On fail goto*//*Label 1281*/ GIMT_Encode4(60061), // Rule ID 2515 // |
| 22083 | /* 60018 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8_3a), |
| 22084 | /* 60021 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcadd_rot90), |
| 22085 | /* 60026 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 22086 | /* 60029 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 22087 | /* 60032 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 22088 | /* 60035 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22089 | /* 60039 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22090 | /* 60043 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22091 | /* 60047 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3757:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Rn, QPR:{ *:[v8f16] }:$Rm) => (VCADDv8f16:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Rn, QPR:{ *:[v8f16] }:$Rm, 0:{ *:[i32] }) |
| 22092 | /* 60047 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCADDv8f16), |
| 22093 | /* 60050 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22094 | /* 60052 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 22095 | /* 60054 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 22096 | /* 60056 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22097 | /* 60059 */ GIR_RootConstrainSelectedInstOperands, |
| 22098 | /* 60060 */ // GIR_Coverage, 2515, |
| 22099 | /* 60060 */ GIR_EraseRootFromParent_Done, |
| 22100 | /* 60061 */ // Label 1281: @60061 |
| 22101 | /* 60061 */ GIM_Try, /*On fail goto*//*Label 1282*/ GIMT_Encode4(60109), // Rule ID 2516 // |
| 22102 | /* 60066 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8_3a), |
| 22103 | /* 60069 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcadd_rot270), |
| 22104 | /* 60074 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 22105 | /* 60077 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 22106 | /* 60080 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 22107 | /* 60083 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22108 | /* 60087 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22109 | /* 60091 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22110 | /* 60095 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3756:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Rn, QPR:{ *:[v8f16] }:$Rm) => (VCADDv8f16:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Rn, QPR:{ *:[v8f16] }:$Rm, 1:{ *:[i32] }) |
| 22111 | /* 60095 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCADDv8f16), |
| 22112 | /* 60098 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22113 | /* 60100 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 22114 | /* 60102 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 22115 | /* 60104 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 22116 | /* 60107 */ GIR_RootConstrainSelectedInstOperands, |
| 22117 | /* 60108 */ // GIR_Coverage, 2516, |
| 22118 | /* 60108 */ GIR_EraseRootFromParent_Done, |
| 22119 | /* 60109 */ // Label 1282: @60109 |
| 22120 | /* 60109 */ GIM_Try, /*On fail goto*//*Label 1283*/ GIMT_Encode4(60157), // Rule ID 2517 // |
| 22121 | /* 60114 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8_3a), |
| 22122 | /* 60117 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcadd_rot90), |
| 22123 | /* 60122 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 22124 | /* 60125 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 22125 | /* 60128 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 22126 | /* 60131 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22127 | /* 60135 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22128 | /* 60139 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22129 | /* 60143 */ // (intrinsic_wo_chain:{ *:[v2f32] } 3757:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Rn, DPR:{ *:[v2f32] }:$Rm) => (VCADDv2f32:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Rn, DPR:{ *:[v2f32] }:$Rm, 0:{ *:[i32] }) |
| 22130 | /* 60143 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCADDv2f32), |
| 22131 | /* 60146 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22132 | /* 60148 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 22133 | /* 60150 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 22134 | /* 60152 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22135 | /* 60155 */ GIR_RootConstrainSelectedInstOperands, |
| 22136 | /* 60156 */ // GIR_Coverage, 2517, |
| 22137 | /* 60156 */ GIR_EraseRootFromParent_Done, |
| 22138 | /* 60157 */ // Label 1283: @60157 |
| 22139 | /* 60157 */ GIM_Try, /*On fail goto*//*Label 1284*/ GIMT_Encode4(60205), // Rule ID 2518 // |
| 22140 | /* 60162 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8_3a), |
| 22141 | /* 60165 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcadd_rot270), |
| 22142 | /* 60170 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 22143 | /* 60173 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 22144 | /* 60176 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 22145 | /* 60179 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22146 | /* 60183 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22147 | /* 60187 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22148 | /* 60191 */ // (intrinsic_wo_chain:{ *:[v2f32] } 3756:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Rn, DPR:{ *:[v2f32] }:$Rm) => (VCADDv2f32:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Rn, DPR:{ *:[v2f32] }:$Rm, 1:{ *:[i32] }) |
| 22149 | /* 60191 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCADDv2f32), |
| 22150 | /* 60194 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22151 | /* 60196 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 22152 | /* 60198 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 22153 | /* 60200 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 22154 | /* 60203 */ GIR_RootConstrainSelectedInstOperands, |
| 22155 | /* 60204 */ // GIR_Coverage, 2518, |
| 22156 | /* 60204 */ GIR_EraseRootFromParent_Done, |
| 22157 | /* 60205 */ // Label 1284: @60205 |
| 22158 | /* 60205 */ GIM_Try, /*On fail goto*//*Label 1285*/ GIMT_Encode4(60253), // Rule ID 2519 // |
| 22159 | /* 60210 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8_3a), |
| 22160 | /* 60213 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcadd_rot90), |
| 22161 | /* 60218 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 22162 | /* 60221 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 22163 | /* 60224 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 22164 | /* 60227 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22165 | /* 60231 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22166 | /* 60235 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22167 | /* 60239 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3757:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Rn, QPR:{ *:[v4f32] }:$Rm) => (VCADDv4f32:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Rn, QPR:{ *:[v4f32] }:$Rm, 0:{ *:[i32] }) |
| 22168 | /* 60239 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCADDv4f32), |
| 22169 | /* 60242 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22170 | /* 60244 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 22171 | /* 60246 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 22172 | /* 60248 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22173 | /* 60251 */ GIR_RootConstrainSelectedInstOperands, |
| 22174 | /* 60252 */ // GIR_Coverage, 2519, |
| 22175 | /* 60252 */ GIR_EraseRootFromParent_Done, |
| 22176 | /* 60253 */ // Label 1285: @60253 |
| 22177 | /* 60253 */ GIM_Try, /*On fail goto*//*Label 1286*/ GIMT_Encode4(60301), // Rule ID 2520 // |
| 22178 | /* 60258 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8_3a), |
| 22179 | /* 60261 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcadd_rot270), |
| 22180 | /* 60266 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 22181 | /* 60269 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 22182 | /* 60272 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 22183 | /* 60275 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22184 | /* 60279 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22185 | /* 60283 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22186 | /* 60287 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3756:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Rn, QPR:{ *:[v4f32] }:$Rm) => (VCADDv4f32:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Rn, QPR:{ *:[v4f32] }:$Rm, 1:{ *:[i32] }) |
| 22187 | /* 60287 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCADDv4f32), |
| 22188 | /* 60290 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22189 | /* 60292 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 22190 | /* 60294 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 22191 | /* 60296 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 22192 | /* 60299 */ GIR_RootConstrainSelectedInstOperands, |
| 22193 | /* 60300 */ // GIR_Coverage, 2520, |
| 22194 | /* 60300 */ GIR_EraseRootFromParent_Done, |
| 22195 | /* 60301 */ // Label 1286: @60301 |
| 22196 | /* 60301 */ GIM_Try, /*On fail goto*//*Label 1287*/ GIMT_Encode4(60406), // Rule ID 3105 // |
| 22197 | /* 60306 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 22198 | /* 60309 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_minnmv), |
| 22199 | /* 60314 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 22200 | /* 60317 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 22201 | /* 60320 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 22202 | /* 60323 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 22203 | /* 60327 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 22204 | /* 60331 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22205 | /* 60335 */ // (intrinsic_wo_chain:{ *:[f32] } 3565:{ *:[iPTR] }, SPR:{ *:[f32] }:$prev, MQPR:{ *:[v4f32] }:$vec) => (COPY_TO_REGCLASS:{ *:[f32] } (MVE_VMINNMVf32:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } SPR:{ *:[f32] }:$prev, rGPR:{ *:[i32] }), MQPR:{ *:[v4f32] }:$vec), SPR:{ *:[i32] }) |
| 22206 | /* 60335 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 22207 | /* 60338 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 22208 | /* 60342 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 22209 | /* 60347 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // prev |
| 22210 | /* 60351 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 22211 | /* 60356 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 22212 | /* 60359 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINNMVf32), |
| 22213 | /* 60363 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 22214 | /* 60368 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 22215 | /* 60371 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vec |
| 22216 | /* 60375 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 22217 | /* 60378 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22218 | /* 60384 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22219 | /* 60390 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 22220 | /* 60392 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 22221 | /* 60395 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 22222 | /* 60397 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 22223 | /* 60400 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 22224 | /* 60405 */ // GIR_Coverage, 3105, |
| 22225 | /* 60405 */ GIR_EraseRootFromParent_Done, |
| 22226 | /* 60406 */ // Label 1287: @60406 |
| 22227 | /* 60406 */ GIM_Try, /*On fail goto*//*Label 1288*/ GIMT_Encode4(60511), // Rule ID 3107 // |
| 22228 | /* 60411 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 22229 | /* 60414 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_minnmv), |
| 22230 | /* 60419 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16, |
| 22231 | /* 60422 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 22232 | /* 60425 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 22233 | /* 60428 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 22234 | /* 60432 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 22235 | /* 60436 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22236 | /* 60440 */ // (intrinsic_wo_chain:{ *:[f16] } 3565:{ *:[iPTR] }, HPR:{ *:[f16] }:$prev, MQPR:{ *:[v8f16] }:$vec) => (COPY_TO_REGCLASS:{ *:[f16] } (MVE_VMINNMVf16:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } HPR:{ *:[f16] }:$prev, rGPR:{ *:[i32] }), MQPR:{ *:[v8f16] }:$vec), HPR:{ *:[i32] }) |
| 22237 | /* 60440 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 22238 | /* 60443 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 22239 | /* 60447 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 22240 | /* 60452 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // prev |
| 22241 | /* 60456 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 22242 | /* 60461 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 22243 | /* 60464 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINNMVf16), |
| 22244 | /* 60468 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 22245 | /* 60473 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 22246 | /* 60476 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vec |
| 22247 | /* 60480 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 22248 | /* 60483 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22249 | /* 60489 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22250 | /* 60495 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 22251 | /* 60497 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 22252 | /* 60500 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 22253 | /* 60502 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 22254 | /* 60505 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::HPRRegClassID), |
| 22255 | /* 60510 */ // GIR_Coverage, 3107, |
| 22256 | /* 60510 */ GIR_EraseRootFromParent_Done, |
| 22257 | /* 60511 */ // Label 1288: @60511 |
| 22258 | /* 60511 */ GIM_Try, /*On fail goto*//*Label 1289*/ GIMT_Encode4(60616), // Rule ID 3109 // |
| 22259 | /* 60516 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 22260 | /* 60519 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_maxnmv), |
| 22261 | /* 60524 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 22262 | /* 60527 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 22263 | /* 60530 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 22264 | /* 60533 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 22265 | /* 60537 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 22266 | /* 60541 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22267 | /* 60545 */ // (intrinsic_wo_chain:{ *:[f32] } 3556:{ *:[iPTR] }, SPR:{ *:[f32] }:$prev, MQPR:{ *:[v4f32] }:$vec) => (COPY_TO_REGCLASS:{ *:[f32] } (MVE_VMAXNMVf32:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } SPR:{ *:[f32] }:$prev, rGPR:{ *:[i32] }), MQPR:{ *:[v4f32] }:$vec), SPR:{ *:[i32] }) |
| 22268 | /* 60545 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 22269 | /* 60548 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 22270 | /* 60552 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 22271 | /* 60557 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // prev |
| 22272 | /* 60561 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 22273 | /* 60566 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 22274 | /* 60569 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXNMVf32), |
| 22275 | /* 60573 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 22276 | /* 60578 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 22277 | /* 60581 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vec |
| 22278 | /* 60585 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 22279 | /* 60588 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22280 | /* 60594 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22281 | /* 60600 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 22282 | /* 60602 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 22283 | /* 60605 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 22284 | /* 60607 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 22285 | /* 60610 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 22286 | /* 60615 */ // GIR_Coverage, 3109, |
| 22287 | /* 60615 */ GIR_EraseRootFromParent_Done, |
| 22288 | /* 60616 */ // Label 1289: @60616 |
| 22289 | /* 60616 */ GIM_Try, /*On fail goto*//*Label 1290*/ GIMT_Encode4(60721), // Rule ID 3111 // |
| 22290 | /* 60621 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 22291 | /* 60624 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_maxnmv), |
| 22292 | /* 60629 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16, |
| 22293 | /* 60632 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 22294 | /* 60635 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 22295 | /* 60638 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 22296 | /* 60642 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 22297 | /* 60646 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22298 | /* 60650 */ // (intrinsic_wo_chain:{ *:[f16] } 3556:{ *:[iPTR] }, HPR:{ *:[f16] }:$prev, MQPR:{ *:[v8f16] }:$vec) => (COPY_TO_REGCLASS:{ *:[f16] } (MVE_VMAXNMVf16:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } HPR:{ *:[f16] }:$prev, rGPR:{ *:[i32] }), MQPR:{ *:[v8f16] }:$vec), HPR:{ *:[i32] }) |
| 22299 | /* 60650 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 22300 | /* 60653 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 22301 | /* 60657 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 22302 | /* 60662 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // prev |
| 22303 | /* 60666 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 22304 | /* 60671 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 22305 | /* 60674 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXNMVf16), |
| 22306 | /* 60678 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 22307 | /* 60683 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 22308 | /* 60686 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vec |
| 22309 | /* 60690 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 22310 | /* 60693 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22311 | /* 60699 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22312 | /* 60705 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 22313 | /* 60707 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 22314 | /* 60710 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 22315 | /* 60712 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 22316 | /* 60715 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::HPRRegClassID), |
| 22317 | /* 60720 */ // GIR_Coverage, 3111, |
| 22318 | /* 60720 */ GIR_EraseRootFromParent_Done, |
| 22319 | /* 60721 */ // Label 1290: @60721 |
| 22320 | /* 60721 */ GIM_Try, /*On fail goto*//*Label 1291*/ GIMT_Encode4(60826), // Rule ID 3113 // |
| 22321 | /* 60726 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 22322 | /* 60729 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_minnmav), |
| 22323 | /* 60734 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 22324 | /* 60737 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 22325 | /* 60740 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 22326 | /* 60743 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 22327 | /* 60747 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 22328 | /* 60751 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22329 | /* 60755 */ // (intrinsic_wo_chain:{ *:[f32] } 3563:{ *:[iPTR] }, SPR:{ *:[f32] }:$prev, MQPR:{ *:[v4f32] }:$vec) => (COPY_TO_REGCLASS:{ *:[f32] } (MVE_VMINNMAVf32:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } SPR:{ *:[f32] }:$prev, rGPR:{ *:[i32] }), MQPR:{ *:[v4f32] }:$vec), SPR:{ *:[i32] }) |
| 22330 | /* 60755 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 22331 | /* 60758 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 22332 | /* 60762 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 22333 | /* 60767 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // prev |
| 22334 | /* 60771 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 22335 | /* 60776 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 22336 | /* 60779 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINNMAVf32), |
| 22337 | /* 60783 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 22338 | /* 60788 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 22339 | /* 60791 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vec |
| 22340 | /* 60795 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 22341 | /* 60798 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22342 | /* 60804 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22343 | /* 60810 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 22344 | /* 60812 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 22345 | /* 60815 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 22346 | /* 60817 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 22347 | /* 60820 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 22348 | /* 60825 */ // GIR_Coverage, 3113, |
| 22349 | /* 60825 */ GIR_EraseRootFromParent_Done, |
| 22350 | /* 60826 */ // Label 1291: @60826 |
| 22351 | /* 60826 */ GIM_Try, /*On fail goto*//*Label 1292*/ GIMT_Encode4(60931), // Rule ID 3115 // |
| 22352 | /* 60831 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 22353 | /* 60834 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_minnmav), |
| 22354 | /* 60839 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16, |
| 22355 | /* 60842 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 22356 | /* 60845 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 22357 | /* 60848 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 22358 | /* 60852 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 22359 | /* 60856 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22360 | /* 60860 */ // (intrinsic_wo_chain:{ *:[f16] } 3563:{ *:[iPTR] }, HPR:{ *:[f16] }:$prev, MQPR:{ *:[v8f16] }:$vec) => (COPY_TO_REGCLASS:{ *:[f16] } (MVE_VMINNMAVf16:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } HPR:{ *:[f16] }:$prev, rGPR:{ *:[i32] }), MQPR:{ *:[v8f16] }:$vec), HPR:{ *:[i32] }) |
| 22361 | /* 60860 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 22362 | /* 60863 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 22363 | /* 60867 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 22364 | /* 60872 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // prev |
| 22365 | /* 60876 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 22366 | /* 60881 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 22367 | /* 60884 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINNMAVf16), |
| 22368 | /* 60888 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 22369 | /* 60893 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 22370 | /* 60896 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vec |
| 22371 | /* 60900 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 22372 | /* 60903 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22373 | /* 60909 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22374 | /* 60915 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 22375 | /* 60917 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 22376 | /* 60920 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 22377 | /* 60922 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 22378 | /* 60925 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::HPRRegClassID), |
| 22379 | /* 60930 */ // GIR_Coverage, 3115, |
| 22380 | /* 60930 */ GIR_EraseRootFromParent_Done, |
| 22381 | /* 60931 */ // Label 1292: @60931 |
| 22382 | /* 60931 */ GIM_Try, /*On fail goto*//*Label 1293*/ GIMT_Encode4(61036), // Rule ID 3117 // |
| 22383 | /* 60936 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 22384 | /* 60939 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_maxnmav), |
| 22385 | /* 60944 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 22386 | /* 60947 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 22387 | /* 60950 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 22388 | /* 60953 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 22389 | /* 60957 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 22390 | /* 60961 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22391 | /* 60965 */ // (intrinsic_wo_chain:{ *:[f32] } 3554:{ *:[iPTR] }, SPR:{ *:[f32] }:$prev, MQPR:{ *:[v4f32] }:$vec) => (COPY_TO_REGCLASS:{ *:[f32] } (MVE_VMAXNMAVf32:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } SPR:{ *:[f32] }:$prev, rGPR:{ *:[i32] }), MQPR:{ *:[v4f32] }:$vec), SPR:{ *:[i32] }) |
| 22392 | /* 60965 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 22393 | /* 60968 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 22394 | /* 60972 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 22395 | /* 60977 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // prev |
| 22396 | /* 60981 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 22397 | /* 60986 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 22398 | /* 60989 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXNMAVf32), |
| 22399 | /* 60993 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 22400 | /* 60998 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 22401 | /* 61001 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vec |
| 22402 | /* 61005 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 22403 | /* 61008 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22404 | /* 61014 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22405 | /* 61020 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 22406 | /* 61022 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 22407 | /* 61025 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 22408 | /* 61027 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 22409 | /* 61030 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 22410 | /* 61035 */ // GIR_Coverage, 3117, |
| 22411 | /* 61035 */ GIR_EraseRootFromParent_Done, |
| 22412 | /* 61036 */ // Label 1293: @61036 |
| 22413 | /* 61036 */ GIM_Try, /*On fail goto*//*Label 1294*/ GIMT_Encode4(61141), // Rule ID 3119 // |
| 22414 | /* 61041 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 22415 | /* 61044 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_maxnmav), |
| 22416 | /* 61049 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16, |
| 22417 | /* 61052 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 22418 | /* 61055 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 22419 | /* 61058 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 22420 | /* 61062 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 22421 | /* 61066 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22422 | /* 61070 */ // (intrinsic_wo_chain:{ *:[f16] } 3554:{ *:[iPTR] }, HPR:{ *:[f16] }:$prev, MQPR:{ *:[v8f16] }:$vec) => (COPY_TO_REGCLASS:{ *:[f16] } (MVE_VMAXNMAVf16:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } HPR:{ *:[f16] }:$prev, rGPR:{ *:[i32] }), MQPR:{ *:[v8f16] }:$vec), HPR:{ *:[i32] }) |
| 22423 | /* 61070 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 22424 | /* 61073 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 22425 | /* 61077 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 22426 | /* 61082 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // prev |
| 22427 | /* 61086 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 22428 | /* 61091 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 22429 | /* 61094 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXNMAVf16), |
| 22430 | /* 61098 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 22431 | /* 61103 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 22432 | /* 61106 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vec |
| 22433 | /* 61110 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 22434 | /* 61113 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22435 | /* 61119 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22436 | /* 61125 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 22437 | /* 61127 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 22438 | /* 61130 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 22439 | /* 61132 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 22440 | /* 61135 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::HPRRegClassID), |
| 22441 | /* 61140 */ // GIR_Coverage, 3119, |
| 22442 | /* 61140 */ GIR_EraseRootFromParent_Done, |
| 22443 | /* 61141 */ // Label 1294: @61141 |
| 22444 | /* 61141 */ GIM_Try, /*On fail goto*//*Label 1295*/ GIMT_Encode4(61201), // Rule ID 3169 // |
| 22445 | /* 61146 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 22446 | /* 61149 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_minav), |
| 22447 | /* 61154 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 22448 | /* 61157 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 22449 | /* 61160 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 22450 | /* 61163 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 22451 | /* 61167 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 22452 | /* 61171 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22453 | /* 61175 */ // (intrinsic_wo_chain:{ *:[i32] } 3561:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec) => (MVE_VMINAVs8:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec) |
| 22454 | /* 61175 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINAVs8), |
| 22455 | /* 61178 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 22456 | /* 61180 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev |
| 22457 | /* 61182 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec |
| 22458 | /* 61184 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22459 | /* 61187 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22460 | /* 61193 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22461 | /* 61199 */ GIR_RootConstrainSelectedInstOperands, |
| 22462 | /* 61200 */ // GIR_Coverage, 3169, |
| 22463 | /* 61200 */ GIR_EraseRootFromParent_Done, |
| 22464 | /* 61201 */ // Label 1295: @61201 |
| 22465 | /* 61201 */ GIM_Try, /*On fail goto*//*Label 1296*/ GIMT_Encode4(61261), // Rule ID 3171 // |
| 22466 | /* 61206 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 22467 | /* 61209 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_minav), |
| 22468 | /* 61214 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 22469 | /* 61217 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 22470 | /* 61220 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 22471 | /* 61223 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 22472 | /* 61227 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 22473 | /* 61231 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22474 | /* 61235 */ // (intrinsic_wo_chain:{ *:[i32] } 3561:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec) => (MVE_VMINAVs16:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec) |
| 22475 | /* 61235 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINAVs16), |
| 22476 | /* 61238 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 22477 | /* 61240 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev |
| 22478 | /* 61242 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec |
| 22479 | /* 61244 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22480 | /* 61247 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22481 | /* 61253 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22482 | /* 61259 */ GIR_RootConstrainSelectedInstOperands, |
| 22483 | /* 61260 */ // GIR_Coverage, 3171, |
| 22484 | /* 61260 */ GIR_EraseRootFromParent_Done, |
| 22485 | /* 61261 */ // Label 1296: @61261 |
| 22486 | /* 61261 */ GIM_Try, /*On fail goto*//*Label 1297*/ GIMT_Encode4(61321), // Rule ID 3173 // |
| 22487 | /* 61266 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 22488 | /* 61269 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_minav), |
| 22489 | /* 61274 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 22490 | /* 61277 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 22491 | /* 61280 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 22492 | /* 61283 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 22493 | /* 61287 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 22494 | /* 61291 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22495 | /* 61295 */ // (intrinsic_wo_chain:{ *:[i32] } 3561:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec) => (MVE_VMINAVs32:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec) |
| 22496 | /* 61295 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINAVs32), |
| 22497 | /* 61298 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 22498 | /* 61300 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev |
| 22499 | /* 61302 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec |
| 22500 | /* 61304 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22501 | /* 61307 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22502 | /* 61313 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22503 | /* 61319 */ GIR_RootConstrainSelectedInstOperands, |
| 22504 | /* 61320 */ // GIR_Coverage, 3173, |
| 22505 | /* 61320 */ GIR_EraseRootFromParent_Done, |
| 22506 | /* 61321 */ // Label 1297: @61321 |
| 22507 | /* 61321 */ GIM_Try, /*On fail goto*//*Label 1298*/ GIMT_Encode4(61381), // Rule ID 3175 // |
| 22508 | /* 61326 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 22509 | /* 61329 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_maxav), |
| 22510 | /* 61334 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 22511 | /* 61337 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 22512 | /* 61340 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 22513 | /* 61343 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 22514 | /* 61347 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 22515 | /* 61351 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22516 | /* 61355 */ // (intrinsic_wo_chain:{ *:[i32] } 3552:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec) => (MVE_VMAXAVs8:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec) |
| 22517 | /* 61355 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXAVs8), |
| 22518 | /* 61358 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 22519 | /* 61360 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev |
| 22520 | /* 61362 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec |
| 22521 | /* 61364 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22522 | /* 61367 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22523 | /* 61373 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22524 | /* 61379 */ GIR_RootConstrainSelectedInstOperands, |
| 22525 | /* 61380 */ // GIR_Coverage, 3175, |
| 22526 | /* 61380 */ GIR_EraseRootFromParent_Done, |
| 22527 | /* 61381 */ // Label 1298: @61381 |
| 22528 | /* 61381 */ GIM_Try, /*On fail goto*//*Label 1299*/ GIMT_Encode4(61441), // Rule ID 3177 // |
| 22529 | /* 61386 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 22530 | /* 61389 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_maxav), |
| 22531 | /* 61394 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 22532 | /* 61397 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 22533 | /* 61400 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 22534 | /* 61403 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 22535 | /* 61407 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 22536 | /* 61411 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22537 | /* 61415 */ // (intrinsic_wo_chain:{ *:[i32] } 3552:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec) => (MVE_VMAXAVs16:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec) |
| 22538 | /* 61415 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXAVs16), |
| 22539 | /* 61418 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 22540 | /* 61420 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev |
| 22541 | /* 61422 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec |
| 22542 | /* 61424 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22543 | /* 61427 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22544 | /* 61433 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22545 | /* 61439 */ GIR_RootConstrainSelectedInstOperands, |
| 22546 | /* 61440 */ // GIR_Coverage, 3177, |
| 22547 | /* 61440 */ GIR_EraseRootFromParent_Done, |
| 22548 | /* 61441 */ // Label 1299: @61441 |
| 22549 | /* 61441 */ GIM_Try, /*On fail goto*//*Label 1300*/ GIMT_Encode4(61501), // Rule ID 3179 // |
| 22550 | /* 61446 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 22551 | /* 61449 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_maxav), |
| 22552 | /* 61454 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 22553 | /* 61457 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 22554 | /* 61460 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 22555 | /* 61463 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 22556 | /* 61467 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 22557 | /* 61471 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22558 | /* 61475 */ // (intrinsic_wo_chain:{ *:[i32] } 3552:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec) => (MVE_VMAXAVs32:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec) |
| 22559 | /* 61475 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXAVs32), |
| 22560 | /* 61478 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 22561 | /* 61480 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev |
| 22562 | /* 61482 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec |
| 22563 | /* 61484 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22564 | /* 61487 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22565 | /* 61493 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22566 | /* 61499 */ GIR_RootConstrainSelectedInstOperands, |
| 22567 | /* 61500 */ // GIR_Coverage, 3179, |
| 22568 | /* 61500 */ GIR_EraseRootFromParent_Done, |
| 22569 | /* 61501 */ // Label 1300: @61501 |
| 22570 | /* 61501 */ GIM_Try, /*On fail goto*//*Label 1301*/ GIMT_Encode4(61576), // Rule ID 3470 // |
| 22571 | /* 61506 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 22572 | /* 61509 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmulh), |
| 22573 | /* 61514 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 22574 | /* 61517 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 22575 | /* 61520 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 22576 | /* 61523 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22577 | /* 61527 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22578 | /* 61531 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22579 | /* 61535 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3674:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VQDMULHi8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 22580 | /* 61535 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 22581 | /* 61538 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 22582 | /* 61542 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 22583 | /* 61547 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMULHi8), |
| 22584 | /* 61550 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 22585 | /* 61552 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 22586 | /* 61554 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 22587 | /* 61556 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22588 | /* 61559 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22589 | /* 61565 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22590 | /* 61571 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 22591 | /* 61574 */ GIR_RootConstrainSelectedInstOperands, |
| 22592 | /* 61575 */ // GIR_Coverage, 3470, |
| 22593 | /* 61575 */ GIR_EraseRootFromParent_Done, |
| 22594 | /* 61576 */ // Label 1301: @61576 |
| 22595 | /* 61576 */ GIM_Try, /*On fail goto*//*Label 1302*/ GIMT_Encode4(61651), // Rule ID 3477 // |
| 22596 | /* 61581 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 22597 | /* 61584 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmulh), |
| 22598 | /* 61589 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 22599 | /* 61592 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 22600 | /* 61595 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 22601 | /* 61598 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22602 | /* 61602 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22603 | /* 61606 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22604 | /* 61610 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3674:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VQDMULHi16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 22605 | /* 61610 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 22606 | /* 61613 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 22607 | /* 61617 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 22608 | /* 61622 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMULHi16), |
| 22609 | /* 61625 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 22610 | /* 61627 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 22611 | /* 61629 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 22612 | /* 61631 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22613 | /* 61634 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22614 | /* 61640 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22615 | /* 61646 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 22616 | /* 61649 */ GIR_RootConstrainSelectedInstOperands, |
| 22617 | /* 61650 */ // GIR_Coverage, 3477, |
| 22618 | /* 61650 */ GIR_EraseRootFromParent_Done, |
| 22619 | /* 61651 */ // Label 1302: @61651 |
| 22620 | /* 61651 */ GIM_Try, /*On fail goto*//*Label 1303*/ GIMT_Encode4(61726), // Rule ID 3481 // |
| 22621 | /* 61656 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 22622 | /* 61659 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmulh), |
| 22623 | /* 61664 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 22624 | /* 61667 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 22625 | /* 61670 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 22626 | /* 61673 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22627 | /* 61677 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22628 | /* 61681 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22629 | /* 61685 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3674:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VQDMULHi32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 22630 | /* 61685 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 22631 | /* 61688 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 22632 | /* 61692 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 22633 | /* 61697 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMULHi32), |
| 22634 | /* 61700 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 22635 | /* 61702 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 22636 | /* 61704 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 22637 | /* 61706 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22638 | /* 61709 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22639 | /* 61715 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22640 | /* 61721 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 22641 | /* 61724 */ GIR_RootConstrainSelectedInstOperands, |
| 22642 | /* 61725 */ // GIR_Coverage, 3481, |
| 22643 | /* 61725 */ GIR_EraseRootFromParent_Done, |
| 22644 | /* 61726 */ // Label 1303: @61726 |
| 22645 | /* 61726 */ GIM_Try, /*On fail goto*//*Label 1304*/ GIMT_Encode4(61801), // Rule ID 3483 // |
| 22646 | /* 61731 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 22647 | /* 61734 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqrdmulh), |
| 22648 | /* 61739 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 22649 | /* 61742 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 22650 | /* 61745 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 22651 | /* 61748 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22652 | /* 61752 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22653 | /* 61756 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22654 | /* 61760 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3683:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VQRDMULHi8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 22655 | /* 61760 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 22656 | /* 61763 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 22657 | /* 61767 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 22658 | /* 61772 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMULHi8), |
| 22659 | /* 61775 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 22660 | /* 61777 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 22661 | /* 61779 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 22662 | /* 61781 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22663 | /* 61784 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22664 | /* 61790 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22665 | /* 61796 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 22666 | /* 61799 */ GIR_RootConstrainSelectedInstOperands, |
| 22667 | /* 61800 */ // GIR_Coverage, 3483, |
| 22668 | /* 61800 */ GIR_EraseRootFromParent_Done, |
| 22669 | /* 61801 */ // Label 1304: @61801 |
| 22670 | /* 61801 */ GIM_Try, /*On fail goto*//*Label 1305*/ GIMT_Encode4(61876), // Rule ID 3485 // |
| 22671 | /* 61806 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 22672 | /* 61809 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqrdmulh), |
| 22673 | /* 61814 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 22674 | /* 61817 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 22675 | /* 61820 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 22676 | /* 61823 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22677 | /* 61827 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22678 | /* 61831 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22679 | /* 61835 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3683:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VQRDMULHi16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 22680 | /* 61835 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 22681 | /* 61838 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 22682 | /* 61842 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 22683 | /* 61847 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMULHi16), |
| 22684 | /* 61850 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 22685 | /* 61852 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 22686 | /* 61854 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 22687 | /* 61856 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22688 | /* 61859 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22689 | /* 61865 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22690 | /* 61871 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 22691 | /* 61874 */ GIR_RootConstrainSelectedInstOperands, |
| 22692 | /* 61875 */ // GIR_Coverage, 3485, |
| 22693 | /* 61875 */ GIR_EraseRootFromParent_Done, |
| 22694 | /* 61876 */ // Label 1305: @61876 |
| 22695 | /* 61876 */ GIM_Try, /*On fail goto*//*Label 1306*/ GIMT_Encode4(61951), // Rule ID 3487 // |
| 22696 | /* 61881 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 22697 | /* 61884 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqrdmulh), |
| 22698 | /* 61889 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 22699 | /* 61892 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 22700 | /* 61895 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 22701 | /* 61898 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22702 | /* 61902 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22703 | /* 61906 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22704 | /* 61910 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3683:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VQRDMULHi32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 22705 | /* 61910 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 22706 | /* 61913 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 22707 | /* 61917 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 22708 | /* 61922 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMULHi32), |
| 22709 | /* 61925 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 22710 | /* 61927 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 22711 | /* 61929 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 22712 | /* 61931 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22713 | /* 61934 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22714 | /* 61940 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22715 | /* 61946 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 22716 | /* 61949 */ GIR_RootConstrainSelectedInstOperands, |
| 22717 | /* 61950 */ // GIR_Coverage, 3487, |
| 22718 | /* 61950 */ GIR_EraseRootFromParent_Done, |
| 22719 | /* 61951 */ // Label 1306: @61951 |
| 22720 | /* 61951 */ GIM_Try, /*On fail goto*//*Label 1307*/ GIMT_Encode4(62026), // Rule ID 4755 // |
| 22721 | /* 61956 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 22722 | /* 61959 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vbrsr), |
| 22723 | /* 61964 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 22724 | /* 61967 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 22725 | /* 61970 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 22726 | /* 61973 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22727 | /* 61977 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22728 | /* 61981 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 22729 | /* 61985 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3607:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qn, rGPR:{ *:[i32] }:$Rm) => (MVE_VBRSR8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qn, rGPR:{ *:[i32] }:$Rm) |
| 22730 | /* 61985 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 22731 | /* 61988 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 22732 | /* 61992 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 22733 | /* 61997 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VBRSR8), |
| 22734 | /* 62000 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 22735 | /* 62002 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 22736 | /* 62004 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 22737 | /* 62006 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22738 | /* 62009 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22739 | /* 62015 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22740 | /* 62021 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 22741 | /* 62024 */ GIR_RootConstrainSelectedInstOperands, |
| 22742 | /* 62025 */ // GIR_Coverage, 4755, |
| 22743 | /* 62025 */ GIR_EraseRootFromParent_Done, |
| 22744 | /* 62026 */ // Label 1307: @62026 |
| 22745 | /* 62026 */ GIM_Try, /*On fail goto*//*Label 1308*/ GIMT_Encode4(62101), // Rule ID 4760 // |
| 22746 | /* 62031 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 22747 | /* 62034 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vbrsr), |
| 22748 | /* 62039 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 22749 | /* 62042 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 22750 | /* 62045 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 22751 | /* 62048 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22752 | /* 62052 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22753 | /* 62056 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 22754 | /* 62060 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3607:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qn, rGPR:{ *:[i32] }:$Rm) => (MVE_VBRSR16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qn, rGPR:{ *:[i32] }:$Rm) |
| 22755 | /* 62060 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 22756 | /* 62063 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 22757 | /* 62067 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 22758 | /* 62072 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VBRSR16), |
| 22759 | /* 62075 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 22760 | /* 62077 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 22761 | /* 62079 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 22762 | /* 62081 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22763 | /* 62084 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22764 | /* 62090 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22765 | /* 62096 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 22766 | /* 62099 */ GIR_RootConstrainSelectedInstOperands, |
| 22767 | /* 62100 */ // GIR_Coverage, 4760, |
| 22768 | /* 62100 */ GIR_EraseRootFromParent_Done, |
| 22769 | /* 62101 */ // Label 1308: @62101 |
| 22770 | /* 62101 */ GIM_Try, /*On fail goto*//*Label 1309*/ GIMT_Encode4(62176), // Rule ID 4762 // |
| 22771 | /* 62106 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 22772 | /* 62109 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vbrsr), |
| 22773 | /* 62114 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 22774 | /* 62117 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 22775 | /* 62120 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 22776 | /* 62123 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22777 | /* 62127 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22778 | /* 62131 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 22779 | /* 62135 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3607:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qn, rGPR:{ *:[i32] }:$Rm) => (MVE_VBRSR32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qn, rGPR:{ *:[i32] }:$Rm) |
| 22780 | /* 62135 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 22781 | /* 62138 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 22782 | /* 62142 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 22783 | /* 62147 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VBRSR32), |
| 22784 | /* 62150 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 22785 | /* 62152 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 22786 | /* 62154 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 22787 | /* 62156 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22788 | /* 62159 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22789 | /* 62165 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22790 | /* 62171 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 22791 | /* 62174 */ GIR_RootConstrainSelectedInstOperands, |
| 22792 | /* 62175 */ // GIR_Coverage, 4762, |
| 22793 | /* 62175 */ GIR_EraseRootFromParent_Done, |
| 22794 | /* 62176 */ // Label 1309: @62176 |
| 22795 | /* 62176 */ GIM_Try, /*On fail goto*//*Label 1310*/ GIMT_Encode4(62251), // Rule ID 4764 // |
| 22796 | /* 62181 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 22797 | /* 62184 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vbrsr), |
| 22798 | /* 62189 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 22799 | /* 62192 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 22800 | /* 62195 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 22801 | /* 62198 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22802 | /* 62202 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22803 | /* 62206 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 22804 | /* 62210 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3607:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$Qn, rGPR:{ *:[i32] }:$Rm) => (MVE_VBRSR16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qn, rGPR:{ *:[i32] }:$Rm) |
| 22805 | /* 62210 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 22806 | /* 62213 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 22807 | /* 62217 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 22808 | /* 62222 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VBRSR16), |
| 22809 | /* 62225 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 22810 | /* 62227 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 22811 | /* 62229 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 22812 | /* 62231 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22813 | /* 62234 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22814 | /* 62240 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22815 | /* 62246 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 22816 | /* 62249 */ GIR_RootConstrainSelectedInstOperands, |
| 22817 | /* 62250 */ // GIR_Coverage, 4764, |
| 22818 | /* 62250 */ GIR_EraseRootFromParent_Done, |
| 22819 | /* 62251 */ // Label 1310: @62251 |
| 22820 | /* 62251 */ GIM_Try, /*On fail goto*//*Label 1311*/ GIMT_Encode4(62326), // Rule ID 4766 // |
| 22821 | /* 62256 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 22822 | /* 62259 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vbrsr), |
| 22823 | /* 62264 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 22824 | /* 62267 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 22825 | /* 62270 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 22826 | /* 62273 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22827 | /* 62277 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22828 | /* 62281 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 22829 | /* 62285 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3607:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$Qn, rGPR:{ *:[i32] }:$Rm) => (MVE_VBRSR32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qn, rGPR:{ *:[i32] }:$Rm) |
| 22830 | /* 62285 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 22831 | /* 62288 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 22832 | /* 62292 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 22833 | /* 62297 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VBRSR32), |
| 22834 | /* 62300 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 22835 | /* 62302 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 22836 | /* 62304 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 22837 | /* 62306 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22838 | /* 62309 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22839 | /* 62315 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22840 | /* 62321 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 22841 | /* 62324 */ GIR_RootConstrainSelectedInstOperands, |
| 22842 | /* 62325 */ // GIR_Coverage, 4766, |
| 22843 | /* 62325 */ GIR_EraseRootFromParent_Done, |
| 22844 | /* 62326 */ // Label 1311: @62326 |
| 22845 | /* 62326 */ GIM_Reject, |
| 22846 | /* 62327 */ // Label 956: @62327 |
| 22847 | /* 62327 */ GIM_Try, /*On fail goto*//*Label 1312*/ GIMT_Encode4(73250), |
| 22848 | /* 62332 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/5, |
| 22849 | /* 62335 */ GIM_Try, /*On fail goto*//*Label 1313*/ GIMT_Encode4(62425), // Rule ID 3916 // |
| 22850 | /* 62340 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqshl_imm), |
| 22851 | /* 62345 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 22852 | /* 62348 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 22853 | /* 62351 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 22854 | /* 62354 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 22855 | /* 62357 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22856 | /* 62361 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22857 | /* 62365 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 22858 | /* 62369 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 22859 | /* 62373 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_7), |
| 22860 | /* 62377 */ // MIs[1] Operand 1 |
| 22861 | /* 62377 */ // No operand predicates |
| 22862 | /* 62377 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 22863 | /* 62381 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 22864 | /* 62383 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3684:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_7>>:$imm, 0:{ *:[i32] }) => (MVE_VQSHLimms8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_7>>:$imm) |
| 22865 | /* 62383 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 22866 | /* 62386 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 22867 | /* 62390 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 22868 | /* 62395 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHLimms8), |
| 22869 | /* 62398 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 22870 | /* 62400 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 22871 | /* 62402 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 22872 | /* 62405 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22873 | /* 62408 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22874 | /* 62414 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22875 | /* 62420 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 22876 | /* 62423 */ GIR_RootConstrainSelectedInstOperands, |
| 22877 | /* 62424 */ // GIR_Coverage, 3916, |
| 22878 | /* 62424 */ GIR_EraseRootFromParent_Done, |
| 22879 | /* 62425 */ // Label 1313: @62425 |
| 22880 | /* 62425 */ GIM_Try, /*On fail goto*//*Label 1314*/ GIMT_Encode4(62515), // Rule ID 3918 // |
| 22881 | /* 62430 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqshl_imm), |
| 22882 | /* 62435 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 22883 | /* 62438 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 22884 | /* 62441 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 22885 | /* 62444 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 22886 | /* 62447 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22887 | /* 62451 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22888 | /* 62455 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 22889 | /* 62459 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 22890 | /* 62463 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_7), |
| 22891 | /* 62467 */ // MIs[1] Operand 1 |
| 22892 | /* 62467 */ // No operand predicates |
| 22893 | /* 62467 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 22894 | /* 62471 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 22895 | /* 62473 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3684:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_7>>:$imm, 1:{ *:[i32] }) => (MVE_VQSHLimmu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_7>>:$imm) |
| 22896 | /* 62473 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 22897 | /* 62476 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 22898 | /* 62480 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 22899 | /* 62485 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHLimmu8), |
| 22900 | /* 62488 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 22901 | /* 62490 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 22902 | /* 62492 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 22903 | /* 62495 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22904 | /* 62498 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22905 | /* 62504 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22906 | /* 62510 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 22907 | /* 62513 */ GIR_RootConstrainSelectedInstOperands, |
| 22908 | /* 62514 */ // GIR_Coverage, 3918, |
| 22909 | /* 62514 */ GIR_EraseRootFromParent_Done, |
| 22910 | /* 62515 */ // Label 1314: @62515 |
| 22911 | /* 62515 */ GIM_Try, /*On fail goto*//*Label 1315*/ GIMT_Encode4(62605), // Rule ID 3920 // |
| 22912 | /* 62520 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqshl_imm), |
| 22913 | /* 62525 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 22914 | /* 62528 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 22915 | /* 62531 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 22916 | /* 62534 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 22917 | /* 62537 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22918 | /* 62541 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22919 | /* 62545 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 22920 | /* 62549 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 22921 | /* 62553 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15), |
| 22922 | /* 62557 */ // MIs[1] Operand 1 |
| 22923 | /* 62557 */ // No operand predicates |
| 22924 | /* 62557 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 22925 | /* 62561 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 22926 | /* 62563 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3684:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$imm, 0:{ *:[i32] }) => (MVE_VQSHLimms16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$imm) |
| 22927 | /* 62563 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 22928 | /* 62566 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 22929 | /* 62570 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 22930 | /* 62575 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHLimms16), |
| 22931 | /* 62578 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 22932 | /* 62580 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 22933 | /* 62582 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 22934 | /* 62585 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22935 | /* 62588 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22936 | /* 62594 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22937 | /* 62600 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 22938 | /* 62603 */ GIR_RootConstrainSelectedInstOperands, |
| 22939 | /* 62604 */ // GIR_Coverage, 3920, |
| 22940 | /* 62604 */ GIR_EraseRootFromParent_Done, |
| 22941 | /* 62605 */ // Label 1315: @62605 |
| 22942 | /* 62605 */ GIM_Try, /*On fail goto*//*Label 1316*/ GIMT_Encode4(62695), // Rule ID 3922 // |
| 22943 | /* 62610 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqshl_imm), |
| 22944 | /* 62615 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 22945 | /* 62618 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 22946 | /* 62621 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 22947 | /* 62624 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 22948 | /* 62627 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22949 | /* 62631 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22950 | /* 62635 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 22951 | /* 62639 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 22952 | /* 62643 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15), |
| 22953 | /* 62647 */ // MIs[1] Operand 1 |
| 22954 | /* 62647 */ // No operand predicates |
| 22955 | /* 62647 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 22956 | /* 62651 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 22957 | /* 62653 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3684:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$imm, 1:{ *:[i32] }) => (MVE_VQSHLimmu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$imm) |
| 22958 | /* 62653 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 22959 | /* 62656 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 22960 | /* 62660 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 22961 | /* 62665 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHLimmu16), |
| 22962 | /* 62668 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 22963 | /* 62670 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 22964 | /* 62672 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 22965 | /* 62675 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22966 | /* 62678 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22967 | /* 62684 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22968 | /* 62690 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 22969 | /* 62693 */ GIR_RootConstrainSelectedInstOperands, |
| 22970 | /* 62694 */ // GIR_Coverage, 3922, |
| 22971 | /* 62694 */ GIR_EraseRootFromParent_Done, |
| 22972 | /* 62695 */ // Label 1316: @62695 |
| 22973 | /* 62695 */ GIM_Try, /*On fail goto*//*Label 1317*/ GIMT_Encode4(62785), // Rule ID 3924 // |
| 22974 | /* 62700 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqshl_imm), |
| 22975 | /* 62705 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 22976 | /* 62708 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 22977 | /* 62711 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 22978 | /* 62714 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 22979 | /* 62717 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22980 | /* 62721 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 22981 | /* 62725 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 22982 | /* 62729 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 22983 | /* 62733 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31), |
| 22984 | /* 62737 */ // MIs[1] Operand 1 |
| 22985 | /* 62737 */ // No operand predicates |
| 22986 | /* 62737 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 22987 | /* 62741 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 22988 | /* 62743 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3684:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$imm, 0:{ *:[i32] }) => (MVE_VQSHLimms32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$imm) |
| 22989 | /* 62743 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 22990 | /* 62746 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 22991 | /* 62750 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 22992 | /* 62755 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHLimms32), |
| 22993 | /* 62758 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 22994 | /* 62760 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 22995 | /* 62762 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 22996 | /* 62765 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22997 | /* 62768 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22998 | /* 62774 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22999 | /* 62780 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 23000 | /* 62783 */ GIR_RootConstrainSelectedInstOperands, |
| 23001 | /* 62784 */ // GIR_Coverage, 3924, |
| 23002 | /* 62784 */ GIR_EraseRootFromParent_Done, |
| 23003 | /* 62785 */ // Label 1317: @62785 |
| 23004 | /* 62785 */ GIM_Try, /*On fail goto*//*Label 1318*/ GIMT_Encode4(62875), // Rule ID 3926 // |
| 23005 | /* 62790 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqshl_imm), |
| 23006 | /* 62795 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 23007 | /* 62798 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 23008 | /* 62801 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 23009 | /* 62804 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 23010 | /* 62807 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23011 | /* 62811 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23012 | /* 62815 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 23013 | /* 62819 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 23014 | /* 62823 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31), |
| 23015 | /* 62827 */ // MIs[1] Operand 1 |
| 23016 | /* 62827 */ // No operand predicates |
| 23017 | /* 62827 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 23018 | /* 62831 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 23019 | /* 62833 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3684:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$imm, 1:{ *:[i32] }) => (MVE_VQSHLimmu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$imm) |
| 23020 | /* 62833 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 23021 | /* 62836 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 23022 | /* 62840 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23023 | /* 62845 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHLimmu32), |
| 23024 | /* 62848 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 23025 | /* 62850 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 23026 | /* 62852 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 23027 | /* 62855 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23028 | /* 62858 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23029 | /* 62864 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23030 | /* 62870 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 23031 | /* 62873 */ GIR_RootConstrainSelectedInstOperands, |
| 23032 | /* 62874 */ // GIR_Coverage, 3926, |
| 23033 | /* 62874 */ GIR_EraseRootFromParent_Done, |
| 23034 | /* 62875 */ // Label 1318: @62875 |
| 23035 | /* 62875 */ GIM_Try, /*On fail goto*//*Label 1319*/ GIMT_Encode4(62965), // Rule ID 3934 // |
| 23036 | /* 62880 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrshr_imm), |
| 23037 | /* 62885 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 23038 | /* 62888 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 23039 | /* 62891 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 23040 | /* 62894 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 23041 | /* 62897 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23042 | /* 62901 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23043 | /* 62905 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 23044 | /* 62909 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 23045 | /* 62913 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8), |
| 23046 | /* 62917 */ // MIs[1] Operand 1 |
| 23047 | /* 62917 */ // No operand predicates |
| 23048 | /* 62917 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 23049 | /* 62921 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 23050 | /* 62923 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3700:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] }) => (MVE_VRSHR_imms8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm) |
| 23051 | /* 62923 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 23052 | /* 62926 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 23053 | /* 62930 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23054 | /* 62935 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHR_imms8), |
| 23055 | /* 62938 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 23056 | /* 62940 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 23057 | /* 62942 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 23058 | /* 62945 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23059 | /* 62948 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23060 | /* 62954 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23061 | /* 62960 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 23062 | /* 62963 */ GIR_RootConstrainSelectedInstOperands, |
| 23063 | /* 62964 */ // GIR_Coverage, 3934, |
| 23064 | /* 62964 */ GIR_EraseRootFromParent_Done, |
| 23065 | /* 62965 */ // Label 1319: @62965 |
| 23066 | /* 62965 */ GIM_Try, /*On fail goto*//*Label 1320*/ GIMT_Encode4(63055), // Rule ID 3936 // |
| 23067 | /* 62970 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrshr_imm), |
| 23068 | /* 62975 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 23069 | /* 62978 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 23070 | /* 62981 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 23071 | /* 62984 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 23072 | /* 62987 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23073 | /* 62991 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23074 | /* 62995 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 23075 | /* 62999 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 23076 | /* 63003 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8), |
| 23077 | /* 63007 */ // MIs[1] Operand 1 |
| 23078 | /* 63007 */ // No operand predicates |
| 23079 | /* 63007 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 23080 | /* 63011 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 23081 | /* 63013 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3700:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }) => (MVE_VRSHR_immu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm) |
| 23082 | /* 63013 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 23083 | /* 63016 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 23084 | /* 63020 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23085 | /* 63025 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHR_immu8), |
| 23086 | /* 63028 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 23087 | /* 63030 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 23088 | /* 63032 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 23089 | /* 63035 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23090 | /* 63038 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23091 | /* 63044 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23092 | /* 63050 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 23093 | /* 63053 */ GIR_RootConstrainSelectedInstOperands, |
| 23094 | /* 63054 */ // GIR_Coverage, 3936, |
| 23095 | /* 63054 */ GIR_EraseRootFromParent_Done, |
| 23096 | /* 63055 */ // Label 1320: @63055 |
| 23097 | /* 63055 */ GIM_Try, /*On fail goto*//*Label 1321*/ GIMT_Encode4(63145), // Rule ID 3938 // |
| 23098 | /* 63060 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrshr_imm), |
| 23099 | /* 63065 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 23100 | /* 63068 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 23101 | /* 63071 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 23102 | /* 63074 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 23103 | /* 63077 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23104 | /* 63081 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23105 | /* 63085 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 23106 | /* 63089 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 23107 | /* 63093 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16), |
| 23108 | /* 63097 */ // MIs[1] Operand 1 |
| 23109 | /* 63097 */ // No operand predicates |
| 23110 | /* 63097 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 23111 | /* 63101 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 23112 | /* 63103 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3700:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] }) => (MVE_VRSHR_imms16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm) |
| 23113 | /* 63103 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 23114 | /* 63106 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 23115 | /* 63110 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23116 | /* 63115 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHR_imms16), |
| 23117 | /* 63118 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 23118 | /* 63120 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 23119 | /* 63122 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 23120 | /* 63125 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23121 | /* 63128 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23122 | /* 63134 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23123 | /* 63140 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 23124 | /* 63143 */ GIR_RootConstrainSelectedInstOperands, |
| 23125 | /* 63144 */ // GIR_Coverage, 3938, |
| 23126 | /* 63144 */ GIR_EraseRootFromParent_Done, |
| 23127 | /* 63145 */ // Label 1321: @63145 |
| 23128 | /* 63145 */ GIM_Try, /*On fail goto*//*Label 1322*/ GIMT_Encode4(63235), // Rule ID 3940 // |
| 23129 | /* 63150 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrshr_imm), |
| 23130 | /* 63155 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 23131 | /* 63158 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 23132 | /* 63161 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 23133 | /* 63164 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 23134 | /* 63167 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23135 | /* 63171 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23136 | /* 63175 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 23137 | /* 63179 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 23138 | /* 63183 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16), |
| 23139 | /* 63187 */ // MIs[1] Operand 1 |
| 23140 | /* 63187 */ // No operand predicates |
| 23141 | /* 63187 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 23142 | /* 63191 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 23143 | /* 63193 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3700:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }) => (MVE_VRSHR_immu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm) |
| 23144 | /* 63193 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 23145 | /* 63196 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 23146 | /* 63200 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23147 | /* 63205 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHR_immu16), |
| 23148 | /* 63208 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 23149 | /* 63210 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 23150 | /* 63212 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 23151 | /* 63215 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23152 | /* 63218 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23153 | /* 63224 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23154 | /* 63230 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 23155 | /* 63233 */ GIR_RootConstrainSelectedInstOperands, |
| 23156 | /* 63234 */ // GIR_Coverage, 3940, |
| 23157 | /* 63234 */ GIR_EraseRootFromParent_Done, |
| 23158 | /* 63235 */ // Label 1322: @63235 |
| 23159 | /* 63235 */ GIM_Try, /*On fail goto*//*Label 1323*/ GIMT_Encode4(63325), // Rule ID 3942 // |
| 23160 | /* 63240 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrshr_imm), |
| 23161 | /* 63245 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 23162 | /* 63248 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 23163 | /* 63251 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 23164 | /* 63254 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 23165 | /* 63257 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23166 | /* 63261 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23167 | /* 63265 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 23168 | /* 63269 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 23169 | /* 63273 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm32), |
| 23170 | /* 63277 */ // MIs[1] Operand 1 |
| 23171 | /* 63277 */ // No operand predicates |
| 23172 | /* 63277 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 23173 | /* 63281 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 23174 | /* 63283 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3700:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm32>>:$imm, 0:{ *:[i32] }) => (MVE_VRSHR_imms32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm32>>:$imm) |
| 23175 | /* 63283 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 23176 | /* 63286 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 23177 | /* 63290 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23178 | /* 63295 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHR_imms32), |
| 23179 | /* 63298 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 23180 | /* 63300 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 23181 | /* 63302 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 23182 | /* 63305 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23183 | /* 63308 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23184 | /* 63314 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23185 | /* 63320 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 23186 | /* 63323 */ GIR_RootConstrainSelectedInstOperands, |
| 23187 | /* 63324 */ // GIR_Coverage, 3942, |
| 23188 | /* 63324 */ GIR_EraseRootFromParent_Done, |
| 23189 | /* 63325 */ // Label 1323: @63325 |
| 23190 | /* 63325 */ GIM_Try, /*On fail goto*//*Label 1324*/ GIMT_Encode4(63415), // Rule ID 3944 // |
| 23191 | /* 63330 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrshr_imm), |
| 23192 | /* 63335 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 23193 | /* 63338 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 23194 | /* 63341 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 23195 | /* 63344 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 23196 | /* 63347 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23197 | /* 63351 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23198 | /* 63355 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 23199 | /* 63359 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 23200 | /* 63363 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm32), |
| 23201 | /* 63367 */ // MIs[1] Operand 1 |
| 23202 | /* 63367 */ // No operand predicates |
| 23203 | /* 63367 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 23204 | /* 63371 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 23205 | /* 63373 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3700:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm32>>:$imm, 1:{ *:[i32] }) => (MVE_VRSHR_immu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm32>>:$imm) |
| 23206 | /* 63373 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 23207 | /* 63376 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 23208 | /* 63380 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23209 | /* 63385 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHR_immu32), |
| 23210 | /* 63388 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 23211 | /* 63390 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 23212 | /* 63392 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 23213 | /* 63395 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23214 | /* 63398 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23215 | /* 63404 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23216 | /* 63410 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 23217 | /* 63413 */ GIR_RootConstrainSelectedInstOperands, |
| 23218 | /* 63414 */ // GIR_Coverage, 3944, |
| 23219 | /* 63414 */ GIR_EraseRootFromParent_Done, |
| 23220 | /* 63415 */ // Label 1324: @63415 |
| 23221 | /* 63415 */ GIM_Try, /*On fail goto*//*Label 1325*/ GIMT_Encode4(63504), // Rule ID 4042 // |
| 23222 | /* 63420 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 23223 | /* 63423 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_fix), |
| 23224 | /* 63428 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 23225 | /* 63431 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 23226 | /* 63434 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 23227 | /* 63437 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 23228 | /* 63440 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23229 | /* 63444 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 23230 | /* 63448 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23231 | /* 63452 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 23232 | /* 63456 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 23233 | /* 63460 */ // MIs[1] Operand 1 |
| 23234 | /* 63460 */ // No operand predicates |
| 23235 | /* 63460 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 23236 | /* 63462 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3620:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$scale) => (MVE_VCVTf16s16_fix:{ *:[v8f16] } MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$scale) |
| 23237 | /* 63462 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 23238 | /* 63465 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 23239 | /* 63469 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23240 | /* 63474 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf16s16_fix), |
| 23241 | /* 63477 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 23242 | /* 63479 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 23243 | /* 63481 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // scale |
| 23244 | /* 63484 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23245 | /* 63487 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23246 | /* 63493 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23247 | /* 63499 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 23248 | /* 63502 */ GIR_RootConstrainSelectedInstOperands, |
| 23249 | /* 63503 */ // GIR_Coverage, 4042, |
| 23250 | /* 63503 */ GIR_EraseRootFromParent_Done, |
| 23251 | /* 63504 */ // Label 1325: @63504 |
| 23252 | /* 63504 */ GIM_Try, /*On fail goto*//*Label 1326*/ GIMT_Encode4(63593), // Rule ID 4044 // |
| 23253 | /* 63509 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 23254 | /* 63512 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_fix), |
| 23255 | /* 63517 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 23256 | /* 63520 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 23257 | /* 63523 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 23258 | /* 63526 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 23259 | /* 63529 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23260 | /* 63533 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 23261 | /* 63537 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23262 | /* 63541 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 23263 | /* 63545 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 23264 | /* 63549 */ // MIs[1] Operand 1 |
| 23265 | /* 63549 */ // No operand predicates |
| 23266 | /* 63549 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 23267 | /* 63551 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3620:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v8f16] }:$Qm, (imm:{ *:[i32] }):$scale) => (MVE_VCVTs16f16_fix:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$Qm, (imm:{ *:[i32] }):$scale) |
| 23268 | /* 63551 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 23269 | /* 63554 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 23270 | /* 63558 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23271 | /* 63563 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs16f16_fix), |
| 23272 | /* 63566 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 23273 | /* 63568 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 23274 | /* 63570 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // scale |
| 23275 | /* 63573 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23276 | /* 63576 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23277 | /* 63582 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23278 | /* 63588 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 23279 | /* 63591 */ GIR_RootConstrainSelectedInstOperands, |
| 23280 | /* 63592 */ // GIR_Coverage, 4044, |
| 23281 | /* 63592 */ GIR_EraseRootFromParent_Done, |
| 23282 | /* 63593 */ // Label 1326: @63593 |
| 23283 | /* 63593 */ GIM_Try, /*On fail goto*//*Label 1327*/ GIMT_Encode4(63682), // Rule ID 4046 // |
| 23284 | /* 63598 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 23285 | /* 63601 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_fix), |
| 23286 | /* 63606 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 23287 | /* 63609 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 23288 | /* 63612 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 23289 | /* 63615 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 23290 | /* 63618 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23291 | /* 63622 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 23292 | /* 63626 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23293 | /* 63630 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 23294 | /* 63634 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 23295 | /* 63638 */ // MIs[1] Operand 1 |
| 23296 | /* 63638 */ // No operand predicates |
| 23297 | /* 63638 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 23298 | /* 63640 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3620:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$scale) => (MVE_VCVTf16u16_fix:{ *:[v8f16] } MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$scale) |
| 23299 | /* 63640 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 23300 | /* 63643 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 23301 | /* 63647 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23302 | /* 63652 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf16u16_fix), |
| 23303 | /* 63655 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 23304 | /* 63657 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 23305 | /* 63659 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // scale |
| 23306 | /* 63662 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23307 | /* 63665 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23308 | /* 63671 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23309 | /* 63677 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 23310 | /* 63680 */ GIR_RootConstrainSelectedInstOperands, |
| 23311 | /* 63681 */ // GIR_Coverage, 4046, |
| 23312 | /* 63681 */ GIR_EraseRootFromParent_Done, |
| 23313 | /* 63682 */ // Label 1327: @63682 |
| 23314 | /* 63682 */ GIM_Try, /*On fail goto*//*Label 1328*/ GIMT_Encode4(63771), // Rule ID 4048 // |
| 23315 | /* 63687 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 23316 | /* 63690 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_fix), |
| 23317 | /* 63695 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 23318 | /* 63698 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 23319 | /* 63701 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 23320 | /* 63704 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 23321 | /* 63707 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23322 | /* 63711 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 23323 | /* 63715 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23324 | /* 63719 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 23325 | /* 63723 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 23326 | /* 63727 */ // MIs[1] Operand 1 |
| 23327 | /* 63727 */ // No operand predicates |
| 23328 | /* 63727 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 23329 | /* 63729 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3620:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v8f16] }:$Qm, (imm:{ *:[i32] }):$scale) => (MVE_VCVTu16f16_fix:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$Qm, (imm:{ *:[i32] }):$scale) |
| 23330 | /* 63729 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 23331 | /* 63732 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 23332 | /* 63736 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23333 | /* 63741 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu16f16_fix), |
| 23334 | /* 63744 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 23335 | /* 63746 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 23336 | /* 63748 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // scale |
| 23337 | /* 63751 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23338 | /* 63754 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23339 | /* 63760 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23340 | /* 63766 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 23341 | /* 63769 */ GIR_RootConstrainSelectedInstOperands, |
| 23342 | /* 63770 */ // GIR_Coverage, 4048, |
| 23343 | /* 63770 */ GIR_EraseRootFromParent_Done, |
| 23344 | /* 63771 */ // Label 1328: @63771 |
| 23345 | /* 63771 */ GIM_Try, /*On fail goto*//*Label 1329*/ GIMT_Encode4(63860), // Rule ID 4050 // |
| 23346 | /* 63776 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 23347 | /* 63779 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_fix), |
| 23348 | /* 63784 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 23349 | /* 63787 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 23350 | /* 63790 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 23351 | /* 63793 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 23352 | /* 63796 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23353 | /* 63800 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 23354 | /* 63804 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23355 | /* 63808 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 23356 | /* 63812 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 23357 | /* 63816 */ // MIs[1] Operand 1 |
| 23358 | /* 63816 */ // No operand predicates |
| 23359 | /* 63816 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 23360 | /* 63818 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3620:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$scale) => (MVE_VCVTf32s32_fix:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$scale) |
| 23361 | /* 63818 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 23362 | /* 63821 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 23363 | /* 63825 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23364 | /* 63830 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf32s32_fix), |
| 23365 | /* 63833 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 23366 | /* 63835 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 23367 | /* 63837 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // scale |
| 23368 | /* 63840 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23369 | /* 63843 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23370 | /* 63849 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23371 | /* 63855 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 23372 | /* 63858 */ GIR_RootConstrainSelectedInstOperands, |
| 23373 | /* 63859 */ // GIR_Coverage, 4050, |
| 23374 | /* 63859 */ GIR_EraseRootFromParent_Done, |
| 23375 | /* 63860 */ // Label 1329: @63860 |
| 23376 | /* 63860 */ GIM_Try, /*On fail goto*//*Label 1330*/ GIMT_Encode4(63949), // Rule ID 4052 // |
| 23377 | /* 63865 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 23378 | /* 63868 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_fix), |
| 23379 | /* 63873 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 23380 | /* 63876 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 23381 | /* 63879 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 23382 | /* 63882 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 23383 | /* 63885 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23384 | /* 63889 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 23385 | /* 63893 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23386 | /* 63897 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 23387 | /* 63901 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 23388 | /* 63905 */ // MIs[1] Operand 1 |
| 23389 | /* 63905 */ // No operand predicates |
| 23390 | /* 63905 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 23391 | /* 63907 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3620:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v4f32] }:$Qm, (imm:{ *:[i32] }):$scale) => (MVE_VCVTs32f32_fix:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$Qm, (imm:{ *:[i32] }):$scale) |
| 23392 | /* 63907 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 23393 | /* 63910 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 23394 | /* 63914 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23395 | /* 63919 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs32f32_fix), |
| 23396 | /* 63922 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 23397 | /* 63924 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 23398 | /* 63926 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // scale |
| 23399 | /* 63929 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23400 | /* 63932 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23401 | /* 63938 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23402 | /* 63944 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 23403 | /* 63947 */ GIR_RootConstrainSelectedInstOperands, |
| 23404 | /* 63948 */ // GIR_Coverage, 4052, |
| 23405 | /* 63948 */ GIR_EraseRootFromParent_Done, |
| 23406 | /* 63949 */ // Label 1330: @63949 |
| 23407 | /* 63949 */ GIM_Try, /*On fail goto*//*Label 1331*/ GIMT_Encode4(64038), // Rule ID 4054 // |
| 23408 | /* 63954 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 23409 | /* 63957 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_fix), |
| 23410 | /* 63962 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 23411 | /* 63965 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 23412 | /* 63968 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 23413 | /* 63971 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 23414 | /* 63974 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23415 | /* 63978 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 23416 | /* 63982 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23417 | /* 63986 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 23418 | /* 63990 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 23419 | /* 63994 */ // MIs[1] Operand 1 |
| 23420 | /* 63994 */ // No operand predicates |
| 23421 | /* 63994 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 23422 | /* 63996 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3620:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$scale) => (MVE_VCVTf32u32_fix:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$scale) |
| 23423 | /* 63996 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 23424 | /* 63999 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 23425 | /* 64003 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23426 | /* 64008 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf32u32_fix), |
| 23427 | /* 64011 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 23428 | /* 64013 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 23429 | /* 64015 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // scale |
| 23430 | /* 64018 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23431 | /* 64021 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23432 | /* 64027 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23433 | /* 64033 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 23434 | /* 64036 */ GIR_RootConstrainSelectedInstOperands, |
| 23435 | /* 64037 */ // GIR_Coverage, 4054, |
| 23436 | /* 64037 */ GIR_EraseRootFromParent_Done, |
| 23437 | /* 64038 */ // Label 1331: @64038 |
| 23438 | /* 64038 */ GIM_Try, /*On fail goto*//*Label 1332*/ GIMT_Encode4(64127), // Rule ID 4056 // |
| 23439 | /* 64043 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 23440 | /* 64046 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_fix), |
| 23441 | /* 64051 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 23442 | /* 64054 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 23443 | /* 64057 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 23444 | /* 64060 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 23445 | /* 64063 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23446 | /* 64067 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 23447 | /* 64071 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23448 | /* 64075 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 23449 | /* 64079 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 23450 | /* 64083 */ // MIs[1] Operand 1 |
| 23451 | /* 64083 */ // No operand predicates |
| 23452 | /* 64083 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 23453 | /* 64085 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3620:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v4f32] }:$Qm, (imm:{ *:[i32] }):$scale) => (MVE_VCVTu32f32_fix:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$Qm, (imm:{ *:[i32] }):$scale) |
| 23454 | /* 64085 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 23455 | /* 64088 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 23456 | /* 64092 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23457 | /* 64097 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu32f32_fix), |
| 23458 | /* 64100 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 23459 | /* 64102 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 23460 | /* 64104 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // scale |
| 23461 | /* 64107 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23462 | /* 64110 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23463 | /* 64116 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23464 | /* 64122 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 23465 | /* 64125 */ GIR_RootConstrainSelectedInstOperands, |
| 23466 | /* 64126 */ // GIR_Coverage, 4056, |
| 23467 | /* 64126 */ GIR_EraseRootFromParent_Done, |
| 23468 | /* 64127 */ // Label 1332: @64127 |
| 23469 | /* 64127 */ GIM_Try, /*On fail goto*//*Label 1333*/ GIMT_Encode4(64194), // Rule ID 3121 // |
| 23470 | /* 64132 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 23471 | /* 64135 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_minv), |
| 23472 | /* 64140 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 23473 | /* 64143 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 23474 | /* 64146 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 23475 | /* 64149 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 23476 | /* 64152 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23477 | /* 64156 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23478 | /* 64160 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23479 | /* 64164 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 23480 | /* 64168 */ // (intrinsic_wo_chain:{ *:[i32] } 3567:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec, 0:{ *:[i32] }) => (MVE_VMINVs8:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec) |
| 23481 | /* 64168 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVs8), |
| 23482 | /* 64171 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 23483 | /* 64173 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev |
| 23484 | /* 64175 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec |
| 23485 | /* 64177 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23486 | /* 64180 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23487 | /* 64186 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23488 | /* 64192 */ GIR_RootConstrainSelectedInstOperands, |
| 23489 | /* 64193 */ // GIR_Coverage, 3121, |
| 23490 | /* 64193 */ GIR_EraseRootFromParent_Done, |
| 23491 | /* 64194 */ // Label 1333: @64194 |
| 23492 | /* 64194 */ GIM_Try, /*On fail goto*//*Label 1334*/ GIMT_Encode4(64261), // Rule ID 3123 // |
| 23493 | /* 64199 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 23494 | /* 64202 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_minv), |
| 23495 | /* 64207 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 23496 | /* 64210 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 23497 | /* 64213 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 23498 | /* 64216 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 23499 | /* 64219 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23500 | /* 64223 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23501 | /* 64227 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23502 | /* 64231 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 23503 | /* 64235 */ // (intrinsic_wo_chain:{ *:[i32] } 3567:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec, 0:{ *:[i32] }) => (MVE_VMINVs16:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec) |
| 23504 | /* 64235 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVs16), |
| 23505 | /* 64238 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 23506 | /* 64240 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev |
| 23507 | /* 64242 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec |
| 23508 | /* 64244 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23509 | /* 64247 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23510 | /* 64253 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23511 | /* 64259 */ GIR_RootConstrainSelectedInstOperands, |
| 23512 | /* 64260 */ // GIR_Coverage, 3123, |
| 23513 | /* 64260 */ GIR_EraseRootFromParent_Done, |
| 23514 | /* 64261 */ // Label 1334: @64261 |
| 23515 | /* 64261 */ GIM_Try, /*On fail goto*//*Label 1335*/ GIMT_Encode4(64328), // Rule ID 3125 // |
| 23516 | /* 64266 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 23517 | /* 64269 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_minv), |
| 23518 | /* 64274 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 23519 | /* 64277 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 23520 | /* 64280 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 23521 | /* 64283 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 23522 | /* 64286 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23523 | /* 64290 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23524 | /* 64294 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23525 | /* 64298 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 23526 | /* 64302 */ // (intrinsic_wo_chain:{ *:[i32] } 3567:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec, 0:{ *:[i32] }) => (MVE_VMINVs32:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec) |
| 23527 | /* 64302 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVs32), |
| 23528 | /* 64305 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 23529 | /* 64307 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev |
| 23530 | /* 64309 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec |
| 23531 | /* 64311 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23532 | /* 64314 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23533 | /* 64320 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23534 | /* 64326 */ GIR_RootConstrainSelectedInstOperands, |
| 23535 | /* 64327 */ // GIR_Coverage, 3125, |
| 23536 | /* 64327 */ GIR_EraseRootFromParent_Done, |
| 23537 | /* 64328 */ // Label 1335: @64328 |
| 23538 | /* 64328 */ GIM_Try, /*On fail goto*//*Label 1336*/ GIMT_Encode4(64395), // Rule ID 3127 // |
| 23539 | /* 64333 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 23540 | /* 64336 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_minv), |
| 23541 | /* 64341 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 23542 | /* 64344 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 23543 | /* 64347 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 23544 | /* 64350 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 23545 | /* 64353 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23546 | /* 64357 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23547 | /* 64361 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23548 | /* 64365 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 23549 | /* 64369 */ // (intrinsic_wo_chain:{ *:[i32] } 3567:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec, 1:{ *:[i32] }) => (MVE_VMINVu8:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec) |
| 23550 | /* 64369 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVu8), |
| 23551 | /* 64372 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 23552 | /* 64374 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev |
| 23553 | /* 64376 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec |
| 23554 | /* 64378 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23555 | /* 64381 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23556 | /* 64387 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23557 | /* 64393 */ GIR_RootConstrainSelectedInstOperands, |
| 23558 | /* 64394 */ // GIR_Coverage, 3127, |
| 23559 | /* 64394 */ GIR_EraseRootFromParent_Done, |
| 23560 | /* 64395 */ // Label 1336: @64395 |
| 23561 | /* 64395 */ GIM_Try, /*On fail goto*//*Label 1337*/ GIMT_Encode4(64462), // Rule ID 3129 // |
| 23562 | /* 64400 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 23563 | /* 64403 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_minv), |
| 23564 | /* 64408 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 23565 | /* 64411 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 23566 | /* 64414 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 23567 | /* 64417 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 23568 | /* 64420 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23569 | /* 64424 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23570 | /* 64428 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23571 | /* 64432 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 23572 | /* 64436 */ // (intrinsic_wo_chain:{ *:[i32] } 3567:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec, 1:{ *:[i32] }) => (MVE_VMINVu16:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec) |
| 23573 | /* 64436 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVu16), |
| 23574 | /* 64439 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 23575 | /* 64441 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev |
| 23576 | /* 64443 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec |
| 23577 | /* 64445 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23578 | /* 64448 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23579 | /* 64454 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23580 | /* 64460 */ GIR_RootConstrainSelectedInstOperands, |
| 23581 | /* 64461 */ // GIR_Coverage, 3129, |
| 23582 | /* 64461 */ GIR_EraseRootFromParent_Done, |
| 23583 | /* 64462 */ // Label 1337: @64462 |
| 23584 | /* 64462 */ GIM_Try, /*On fail goto*//*Label 1338*/ GIMT_Encode4(64529), // Rule ID 3131 // |
| 23585 | /* 64467 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 23586 | /* 64470 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_minv), |
| 23587 | /* 64475 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 23588 | /* 64478 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 23589 | /* 64481 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 23590 | /* 64484 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 23591 | /* 64487 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23592 | /* 64491 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23593 | /* 64495 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23594 | /* 64499 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 23595 | /* 64503 */ // (intrinsic_wo_chain:{ *:[i32] } 3567:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec, 1:{ *:[i32] }) => (MVE_VMINVu32:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec) |
| 23596 | /* 64503 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVu32), |
| 23597 | /* 64506 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 23598 | /* 64508 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev |
| 23599 | /* 64510 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec |
| 23600 | /* 64512 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23601 | /* 64515 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23602 | /* 64521 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23603 | /* 64527 */ GIR_RootConstrainSelectedInstOperands, |
| 23604 | /* 64528 */ // GIR_Coverage, 3131, |
| 23605 | /* 64528 */ GIR_EraseRootFromParent_Done, |
| 23606 | /* 64529 */ // Label 1338: @64529 |
| 23607 | /* 64529 */ GIM_Try, /*On fail goto*//*Label 1339*/ GIMT_Encode4(64596), // Rule ID 3133 // |
| 23608 | /* 64534 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 23609 | /* 64537 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_maxv), |
| 23610 | /* 64542 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 23611 | /* 64545 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 23612 | /* 64548 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 23613 | /* 64551 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 23614 | /* 64554 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23615 | /* 64558 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23616 | /* 64562 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23617 | /* 64566 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 23618 | /* 64570 */ // (intrinsic_wo_chain:{ *:[i32] } 3558:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec, 0:{ *:[i32] }) => (MVE_VMAXVs8:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec) |
| 23619 | /* 64570 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVs8), |
| 23620 | /* 64573 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 23621 | /* 64575 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev |
| 23622 | /* 64577 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec |
| 23623 | /* 64579 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23624 | /* 64582 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23625 | /* 64588 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23626 | /* 64594 */ GIR_RootConstrainSelectedInstOperands, |
| 23627 | /* 64595 */ // GIR_Coverage, 3133, |
| 23628 | /* 64595 */ GIR_EraseRootFromParent_Done, |
| 23629 | /* 64596 */ // Label 1339: @64596 |
| 23630 | /* 64596 */ GIM_Try, /*On fail goto*//*Label 1340*/ GIMT_Encode4(64663), // Rule ID 3135 // |
| 23631 | /* 64601 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 23632 | /* 64604 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_maxv), |
| 23633 | /* 64609 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 23634 | /* 64612 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 23635 | /* 64615 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 23636 | /* 64618 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 23637 | /* 64621 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23638 | /* 64625 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23639 | /* 64629 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23640 | /* 64633 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 23641 | /* 64637 */ // (intrinsic_wo_chain:{ *:[i32] } 3558:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec, 0:{ *:[i32] }) => (MVE_VMAXVs16:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec) |
| 23642 | /* 64637 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVs16), |
| 23643 | /* 64640 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 23644 | /* 64642 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev |
| 23645 | /* 64644 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec |
| 23646 | /* 64646 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23647 | /* 64649 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23648 | /* 64655 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23649 | /* 64661 */ GIR_RootConstrainSelectedInstOperands, |
| 23650 | /* 64662 */ // GIR_Coverage, 3135, |
| 23651 | /* 64662 */ GIR_EraseRootFromParent_Done, |
| 23652 | /* 64663 */ // Label 1340: @64663 |
| 23653 | /* 64663 */ GIM_Try, /*On fail goto*//*Label 1341*/ GIMT_Encode4(64730), // Rule ID 3137 // |
| 23654 | /* 64668 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 23655 | /* 64671 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_maxv), |
| 23656 | /* 64676 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 23657 | /* 64679 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 23658 | /* 64682 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 23659 | /* 64685 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 23660 | /* 64688 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23661 | /* 64692 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23662 | /* 64696 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23663 | /* 64700 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 23664 | /* 64704 */ // (intrinsic_wo_chain:{ *:[i32] } 3558:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec, 0:{ *:[i32] }) => (MVE_VMAXVs32:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec) |
| 23665 | /* 64704 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVs32), |
| 23666 | /* 64707 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 23667 | /* 64709 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev |
| 23668 | /* 64711 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec |
| 23669 | /* 64713 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23670 | /* 64716 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23671 | /* 64722 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23672 | /* 64728 */ GIR_RootConstrainSelectedInstOperands, |
| 23673 | /* 64729 */ // GIR_Coverage, 3137, |
| 23674 | /* 64729 */ GIR_EraseRootFromParent_Done, |
| 23675 | /* 64730 */ // Label 1341: @64730 |
| 23676 | /* 64730 */ GIM_Try, /*On fail goto*//*Label 1342*/ GIMT_Encode4(64797), // Rule ID 3139 // |
| 23677 | /* 64735 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 23678 | /* 64738 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_maxv), |
| 23679 | /* 64743 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 23680 | /* 64746 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 23681 | /* 64749 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 23682 | /* 64752 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 23683 | /* 64755 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23684 | /* 64759 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23685 | /* 64763 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23686 | /* 64767 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 23687 | /* 64771 */ // (intrinsic_wo_chain:{ *:[i32] } 3558:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec, 1:{ *:[i32] }) => (MVE_VMAXVu8:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec) |
| 23688 | /* 64771 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVu8), |
| 23689 | /* 64774 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 23690 | /* 64776 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev |
| 23691 | /* 64778 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec |
| 23692 | /* 64780 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23693 | /* 64783 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23694 | /* 64789 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23695 | /* 64795 */ GIR_RootConstrainSelectedInstOperands, |
| 23696 | /* 64796 */ // GIR_Coverage, 3139, |
| 23697 | /* 64796 */ GIR_EraseRootFromParent_Done, |
| 23698 | /* 64797 */ // Label 1342: @64797 |
| 23699 | /* 64797 */ GIM_Try, /*On fail goto*//*Label 1343*/ GIMT_Encode4(64864), // Rule ID 3141 // |
| 23700 | /* 64802 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 23701 | /* 64805 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_maxv), |
| 23702 | /* 64810 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 23703 | /* 64813 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 23704 | /* 64816 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 23705 | /* 64819 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 23706 | /* 64822 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23707 | /* 64826 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23708 | /* 64830 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23709 | /* 64834 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 23710 | /* 64838 */ // (intrinsic_wo_chain:{ *:[i32] } 3558:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec, 1:{ *:[i32] }) => (MVE_VMAXVu16:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec) |
| 23711 | /* 64838 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVu16), |
| 23712 | /* 64841 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 23713 | /* 64843 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev |
| 23714 | /* 64845 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec |
| 23715 | /* 64847 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23716 | /* 64850 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23717 | /* 64856 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23718 | /* 64862 */ GIR_RootConstrainSelectedInstOperands, |
| 23719 | /* 64863 */ // GIR_Coverage, 3141, |
| 23720 | /* 64863 */ GIR_EraseRootFromParent_Done, |
| 23721 | /* 64864 */ // Label 1343: @64864 |
| 23722 | /* 64864 */ GIM_Try, /*On fail goto*//*Label 1344*/ GIMT_Encode4(64931), // Rule ID 3143 // |
| 23723 | /* 64869 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 23724 | /* 64872 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_maxv), |
| 23725 | /* 64877 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 23726 | /* 64880 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 23727 | /* 64883 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 23728 | /* 64886 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 23729 | /* 64889 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23730 | /* 64893 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23731 | /* 64897 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23732 | /* 64901 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 23733 | /* 64905 */ // (intrinsic_wo_chain:{ *:[i32] } 3558:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec, 1:{ *:[i32] }) => (MVE_VMAXVu32:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec) |
| 23734 | /* 64905 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVu32), |
| 23735 | /* 64908 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 23736 | /* 64910 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev |
| 23737 | /* 64912 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec |
| 23738 | /* 64914 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23739 | /* 64917 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23740 | /* 64923 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23741 | /* 64929 */ GIR_RootConstrainSelectedInstOperands, |
| 23742 | /* 64930 */ // GIR_Coverage, 3143, |
| 23743 | /* 64930 */ GIR_EraseRootFromParent_Done, |
| 23744 | /* 64931 */ // Label 1344: @64931 |
| 23745 | /* 64931 */ GIM_Try, /*On fail goto*//*Label 1345*/ GIMT_Encode4(65013), // Rule ID 3548 // |
| 23746 | /* 64936 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 23747 | /* 64939 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vabd), |
| 23748 | /* 64944 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 23749 | /* 64947 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 23750 | /* 64950 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 23751 | /* 64953 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 23752 | /* 64956 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23753 | /* 64960 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23754 | /* 64964 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23755 | /* 64968 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 23756 | /* 64972 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3604:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] }) => (MVE_VABDs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 23757 | /* 64972 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 23758 | /* 64975 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 23759 | /* 64979 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23760 | /* 64984 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDs8), |
| 23761 | /* 64987 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 23762 | /* 64989 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 23763 | /* 64991 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 23764 | /* 64993 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23765 | /* 64996 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23766 | /* 65002 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23767 | /* 65008 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 23768 | /* 65011 */ GIR_RootConstrainSelectedInstOperands, |
| 23769 | /* 65012 */ // GIR_Coverage, 3548, |
| 23770 | /* 65012 */ GIR_EraseRootFromParent_Done, |
| 23771 | /* 65013 */ // Label 1345: @65013 |
| 23772 | /* 65013 */ GIM_Try, /*On fail goto*//*Label 1346*/ GIMT_Encode4(65095), // Rule ID 3555 // |
| 23773 | /* 65018 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 23774 | /* 65021 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vabd), |
| 23775 | /* 65026 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 23776 | /* 65029 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 23777 | /* 65032 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 23778 | /* 65035 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 23779 | /* 65038 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23780 | /* 65042 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23781 | /* 65046 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23782 | /* 65050 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 23783 | /* 65054 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3604:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }) => (MVE_VABDs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 23784 | /* 65054 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 23785 | /* 65057 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 23786 | /* 65061 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23787 | /* 65066 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDs16), |
| 23788 | /* 65069 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 23789 | /* 65071 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 23790 | /* 65073 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 23791 | /* 65075 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23792 | /* 65078 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23793 | /* 65084 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23794 | /* 65090 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 23795 | /* 65093 */ GIR_RootConstrainSelectedInstOperands, |
| 23796 | /* 65094 */ // GIR_Coverage, 3555, |
| 23797 | /* 65094 */ GIR_EraseRootFromParent_Done, |
| 23798 | /* 65095 */ // Label 1346: @65095 |
| 23799 | /* 65095 */ GIM_Try, /*On fail goto*//*Label 1347*/ GIMT_Encode4(65177), // Rule ID 3559 // |
| 23800 | /* 65100 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 23801 | /* 65103 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vabd), |
| 23802 | /* 65108 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 23803 | /* 65111 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 23804 | /* 65114 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 23805 | /* 65117 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 23806 | /* 65120 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23807 | /* 65124 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23808 | /* 65128 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23809 | /* 65132 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 23810 | /* 65136 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3604:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] }) => (MVE_VABDs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 23811 | /* 65136 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 23812 | /* 65139 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 23813 | /* 65143 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23814 | /* 65148 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDs32), |
| 23815 | /* 65151 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 23816 | /* 65153 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 23817 | /* 65155 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 23818 | /* 65157 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23819 | /* 65160 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23820 | /* 65166 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23821 | /* 65172 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 23822 | /* 65175 */ GIR_RootConstrainSelectedInstOperands, |
| 23823 | /* 65176 */ // GIR_Coverage, 3559, |
| 23824 | /* 65176 */ GIR_EraseRootFromParent_Done, |
| 23825 | /* 65177 */ // Label 1347: @65177 |
| 23826 | /* 65177 */ GIM_Try, /*On fail goto*//*Label 1348*/ GIMT_Encode4(65259), // Rule ID 3563 // |
| 23827 | /* 65182 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 23828 | /* 65185 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vabd), |
| 23829 | /* 65190 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 23830 | /* 65193 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 23831 | /* 65196 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 23832 | /* 65199 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 23833 | /* 65202 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23834 | /* 65206 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23835 | /* 65210 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23836 | /* 65214 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 23837 | /* 65218 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3604:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] }) => (MVE_VABDu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 23838 | /* 65218 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 23839 | /* 65221 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 23840 | /* 65225 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23841 | /* 65230 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDu8), |
| 23842 | /* 65233 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 23843 | /* 65235 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 23844 | /* 65237 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 23845 | /* 65239 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23846 | /* 65242 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23847 | /* 65248 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23848 | /* 65254 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 23849 | /* 65257 */ GIR_RootConstrainSelectedInstOperands, |
| 23850 | /* 65258 */ // GIR_Coverage, 3563, |
| 23851 | /* 65258 */ GIR_EraseRootFromParent_Done, |
| 23852 | /* 65259 */ // Label 1348: @65259 |
| 23853 | /* 65259 */ GIM_Try, /*On fail goto*//*Label 1349*/ GIMT_Encode4(65341), // Rule ID 3567 // |
| 23854 | /* 65264 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 23855 | /* 65267 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vabd), |
| 23856 | /* 65272 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 23857 | /* 65275 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 23858 | /* 65278 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 23859 | /* 65281 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 23860 | /* 65284 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23861 | /* 65288 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23862 | /* 65292 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23863 | /* 65296 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 23864 | /* 65300 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3604:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }) => (MVE_VABDu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 23865 | /* 65300 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 23866 | /* 65303 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 23867 | /* 65307 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23868 | /* 65312 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDu16), |
| 23869 | /* 65315 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 23870 | /* 65317 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 23871 | /* 65319 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 23872 | /* 65321 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23873 | /* 65324 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23874 | /* 65330 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23875 | /* 65336 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 23876 | /* 65339 */ GIR_RootConstrainSelectedInstOperands, |
| 23877 | /* 65340 */ // GIR_Coverage, 3567, |
| 23878 | /* 65340 */ GIR_EraseRootFromParent_Done, |
| 23879 | /* 65341 */ // Label 1349: @65341 |
| 23880 | /* 65341 */ GIM_Try, /*On fail goto*//*Label 1350*/ GIMT_Encode4(65423), // Rule ID 3571 // |
| 23881 | /* 65346 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 23882 | /* 65349 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vabd), |
| 23883 | /* 65354 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 23884 | /* 65357 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 23885 | /* 65360 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 23886 | /* 65363 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 23887 | /* 65366 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23888 | /* 65370 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23889 | /* 65374 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23890 | /* 65378 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 23891 | /* 65382 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3604:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] }) => (MVE_VABDu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 23892 | /* 65382 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 23893 | /* 65385 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 23894 | /* 65389 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23895 | /* 65394 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDu32), |
| 23896 | /* 65397 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 23897 | /* 65399 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 23898 | /* 65401 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 23899 | /* 65403 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23900 | /* 65406 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23901 | /* 65412 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23902 | /* 65418 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 23903 | /* 65421 */ GIR_RootConstrainSelectedInstOperands, |
| 23904 | /* 65422 */ // GIR_Coverage, 3571, |
| 23905 | /* 65422 */ GIR_EraseRootFromParent_Done, |
| 23906 | /* 65423 */ // Label 1350: @65423 |
| 23907 | /* 65423 */ GIM_Try, /*On fail goto*//*Label 1351*/ GIMT_Encode4(65505), // Rule ID 3572 // |
| 23908 | /* 65428 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 23909 | /* 65431 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrhadd), |
| 23910 | /* 65436 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 23911 | /* 65439 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 23912 | /* 65442 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 23913 | /* 65445 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 23914 | /* 65448 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23915 | /* 65452 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23916 | /* 65456 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23917 | /* 65460 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 23918 | /* 65464 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3690:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] }) => (MVE_VRHADDs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 23919 | /* 65464 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 23920 | /* 65467 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 23921 | /* 65471 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23922 | /* 65476 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRHADDs8), |
| 23923 | /* 65479 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 23924 | /* 65481 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 23925 | /* 65483 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 23926 | /* 65485 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23927 | /* 65488 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23928 | /* 65494 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23929 | /* 65500 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 23930 | /* 65503 */ GIR_RootConstrainSelectedInstOperands, |
| 23931 | /* 65504 */ // GIR_Coverage, 3572, |
| 23932 | /* 65504 */ GIR_EraseRootFromParent_Done, |
| 23933 | /* 65505 */ // Label 1351: @65505 |
| 23934 | /* 65505 */ GIM_Try, /*On fail goto*//*Label 1352*/ GIMT_Encode4(65587), // Rule ID 3579 // |
| 23935 | /* 65510 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 23936 | /* 65513 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrhadd), |
| 23937 | /* 65518 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 23938 | /* 65521 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 23939 | /* 65524 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 23940 | /* 65527 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 23941 | /* 65530 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23942 | /* 65534 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23943 | /* 65538 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23944 | /* 65542 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 23945 | /* 65546 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3690:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }) => (MVE_VRHADDs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 23946 | /* 65546 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 23947 | /* 65549 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 23948 | /* 65553 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23949 | /* 65558 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRHADDs16), |
| 23950 | /* 65561 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 23951 | /* 65563 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 23952 | /* 65565 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 23953 | /* 65567 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23954 | /* 65570 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23955 | /* 65576 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23956 | /* 65582 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 23957 | /* 65585 */ GIR_RootConstrainSelectedInstOperands, |
| 23958 | /* 65586 */ // GIR_Coverage, 3579, |
| 23959 | /* 65586 */ GIR_EraseRootFromParent_Done, |
| 23960 | /* 65587 */ // Label 1352: @65587 |
| 23961 | /* 65587 */ GIM_Try, /*On fail goto*//*Label 1353*/ GIMT_Encode4(65669), // Rule ID 3583 // |
| 23962 | /* 65592 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 23963 | /* 65595 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrhadd), |
| 23964 | /* 65600 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 23965 | /* 65603 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 23966 | /* 65606 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 23967 | /* 65609 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 23968 | /* 65612 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23969 | /* 65616 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23970 | /* 65620 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23971 | /* 65624 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 23972 | /* 65628 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3690:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] }) => (MVE_VRHADDs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 23973 | /* 65628 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 23974 | /* 65631 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 23975 | /* 65635 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23976 | /* 65640 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRHADDs32), |
| 23977 | /* 65643 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 23978 | /* 65645 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 23979 | /* 65647 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 23980 | /* 65649 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23981 | /* 65652 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23982 | /* 65658 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23983 | /* 65664 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 23984 | /* 65667 */ GIR_RootConstrainSelectedInstOperands, |
| 23985 | /* 65668 */ // GIR_Coverage, 3583, |
| 23986 | /* 65668 */ GIR_EraseRootFromParent_Done, |
| 23987 | /* 65669 */ // Label 1353: @65669 |
| 23988 | /* 65669 */ GIM_Try, /*On fail goto*//*Label 1354*/ GIMT_Encode4(65751), // Rule ID 3587 // |
| 23989 | /* 65674 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 23990 | /* 65677 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrhadd), |
| 23991 | /* 65682 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 23992 | /* 65685 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 23993 | /* 65688 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 23994 | /* 65691 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 23995 | /* 65694 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23996 | /* 65698 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23997 | /* 65702 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23998 | /* 65706 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 23999 | /* 65710 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3690:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] }) => (MVE_VRHADDu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 24000 | /* 65710 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 24001 | /* 65713 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 24002 | /* 65717 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24003 | /* 65722 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRHADDu8), |
| 24004 | /* 65725 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24005 | /* 65727 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 24006 | /* 65729 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 24007 | /* 65731 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24008 | /* 65734 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24009 | /* 65740 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24010 | /* 65746 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24011 | /* 65749 */ GIR_RootConstrainSelectedInstOperands, |
| 24012 | /* 65750 */ // GIR_Coverage, 3587, |
| 24013 | /* 65750 */ GIR_EraseRootFromParent_Done, |
| 24014 | /* 65751 */ // Label 1354: @65751 |
| 24015 | /* 65751 */ GIM_Try, /*On fail goto*//*Label 1355*/ GIMT_Encode4(65833), // Rule ID 3591 // |
| 24016 | /* 65756 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 24017 | /* 65759 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrhadd), |
| 24018 | /* 65764 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 24019 | /* 65767 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 24020 | /* 65770 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 24021 | /* 65773 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 24022 | /* 65776 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24023 | /* 65780 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24024 | /* 65784 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24025 | /* 65788 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 24026 | /* 65792 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3690:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }) => (MVE_VRHADDu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 24027 | /* 65792 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 24028 | /* 65795 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 24029 | /* 65799 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24030 | /* 65804 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRHADDu16), |
| 24031 | /* 65807 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24032 | /* 65809 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 24033 | /* 65811 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 24034 | /* 65813 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24035 | /* 65816 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24036 | /* 65822 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24037 | /* 65828 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24038 | /* 65831 */ GIR_RootConstrainSelectedInstOperands, |
| 24039 | /* 65832 */ // GIR_Coverage, 3591, |
| 24040 | /* 65832 */ GIR_EraseRootFromParent_Done, |
| 24041 | /* 65833 */ // Label 1355: @65833 |
| 24042 | /* 65833 */ GIM_Try, /*On fail goto*//*Label 1356*/ GIMT_Encode4(65915), // Rule ID 3595 // |
| 24043 | /* 65838 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 24044 | /* 65841 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrhadd), |
| 24045 | /* 65846 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 24046 | /* 65849 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 24047 | /* 65852 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 24048 | /* 65855 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 24049 | /* 65858 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24050 | /* 65862 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24051 | /* 65866 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24052 | /* 65870 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 24053 | /* 65874 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3690:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] }) => (MVE_VRHADDu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 24054 | /* 65874 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 24055 | /* 65877 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 24056 | /* 65881 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24057 | /* 65886 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRHADDu32), |
| 24058 | /* 65889 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24059 | /* 65891 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 24060 | /* 65893 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 24061 | /* 65895 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24062 | /* 65898 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24063 | /* 65904 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24064 | /* 65910 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24065 | /* 65913 */ GIR_RootConstrainSelectedInstOperands, |
| 24066 | /* 65914 */ // GIR_Coverage, 3595, |
| 24067 | /* 65914 */ GIR_EraseRootFromParent_Done, |
| 24068 | /* 65915 */ // Label 1356: @65915 |
| 24069 | /* 65915 */ GIM_Try, /*On fail goto*//*Label 1357*/ GIMT_Encode4(65997), // Rule ID 3596 // |
| 24070 | /* 65920 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 24071 | /* 65923 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vhadd), |
| 24072 | /* 65928 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 24073 | /* 65931 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 24074 | /* 65934 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 24075 | /* 65937 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 24076 | /* 65940 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24077 | /* 65944 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24078 | /* 65948 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24079 | /* 65952 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 24080 | /* 65956 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3639:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] }) => (MVE_VHADDs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 24081 | /* 65956 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 24082 | /* 65959 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 24083 | /* 65963 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24084 | /* 65968 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHADDs8), |
| 24085 | /* 65971 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24086 | /* 65973 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 24087 | /* 65975 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 24088 | /* 65977 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24089 | /* 65980 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24090 | /* 65986 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24091 | /* 65992 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24092 | /* 65995 */ GIR_RootConstrainSelectedInstOperands, |
| 24093 | /* 65996 */ // GIR_Coverage, 3596, |
| 24094 | /* 65996 */ GIR_EraseRootFromParent_Done, |
| 24095 | /* 65997 */ // Label 1357: @65997 |
| 24096 | /* 65997 */ GIM_Try, /*On fail goto*//*Label 1358*/ GIMT_Encode4(66079), // Rule ID 3603 // |
| 24097 | /* 66002 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 24098 | /* 66005 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vhadd), |
| 24099 | /* 66010 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 24100 | /* 66013 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 24101 | /* 66016 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 24102 | /* 66019 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 24103 | /* 66022 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24104 | /* 66026 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24105 | /* 66030 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24106 | /* 66034 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 24107 | /* 66038 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3639:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }) => (MVE_VHADDs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 24108 | /* 66038 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 24109 | /* 66041 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 24110 | /* 66045 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24111 | /* 66050 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHADDs16), |
| 24112 | /* 66053 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24113 | /* 66055 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 24114 | /* 66057 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 24115 | /* 66059 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24116 | /* 66062 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24117 | /* 66068 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24118 | /* 66074 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24119 | /* 66077 */ GIR_RootConstrainSelectedInstOperands, |
| 24120 | /* 66078 */ // GIR_Coverage, 3603, |
| 24121 | /* 66078 */ GIR_EraseRootFromParent_Done, |
| 24122 | /* 66079 */ // Label 1358: @66079 |
| 24123 | /* 66079 */ GIM_Try, /*On fail goto*//*Label 1359*/ GIMT_Encode4(66161), // Rule ID 3607 // |
| 24124 | /* 66084 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 24125 | /* 66087 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vhadd), |
| 24126 | /* 66092 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 24127 | /* 66095 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 24128 | /* 66098 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 24129 | /* 66101 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 24130 | /* 66104 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24131 | /* 66108 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24132 | /* 66112 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24133 | /* 66116 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 24134 | /* 66120 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3639:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] }) => (MVE_VHADDs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 24135 | /* 66120 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 24136 | /* 66123 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 24137 | /* 66127 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24138 | /* 66132 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHADDs32), |
| 24139 | /* 66135 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24140 | /* 66137 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 24141 | /* 66139 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 24142 | /* 66141 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24143 | /* 66144 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24144 | /* 66150 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24145 | /* 66156 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24146 | /* 66159 */ GIR_RootConstrainSelectedInstOperands, |
| 24147 | /* 66160 */ // GIR_Coverage, 3607, |
| 24148 | /* 66160 */ GIR_EraseRootFromParent_Done, |
| 24149 | /* 66161 */ // Label 1359: @66161 |
| 24150 | /* 66161 */ GIM_Try, /*On fail goto*//*Label 1360*/ GIMT_Encode4(66243), // Rule ID 3611 // |
| 24151 | /* 66166 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 24152 | /* 66169 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vhadd), |
| 24153 | /* 66174 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 24154 | /* 66177 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 24155 | /* 66180 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 24156 | /* 66183 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 24157 | /* 66186 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24158 | /* 66190 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24159 | /* 66194 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24160 | /* 66198 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 24161 | /* 66202 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3639:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] }) => (MVE_VHADDu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 24162 | /* 66202 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 24163 | /* 66205 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 24164 | /* 66209 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24165 | /* 66214 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHADDu8), |
| 24166 | /* 66217 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24167 | /* 66219 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 24168 | /* 66221 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 24169 | /* 66223 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24170 | /* 66226 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24171 | /* 66232 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24172 | /* 66238 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24173 | /* 66241 */ GIR_RootConstrainSelectedInstOperands, |
| 24174 | /* 66242 */ // GIR_Coverage, 3611, |
| 24175 | /* 66242 */ GIR_EraseRootFromParent_Done, |
| 24176 | /* 66243 */ // Label 1360: @66243 |
| 24177 | /* 66243 */ GIM_Try, /*On fail goto*//*Label 1361*/ GIMT_Encode4(66325), // Rule ID 3615 // |
| 24178 | /* 66248 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 24179 | /* 66251 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vhadd), |
| 24180 | /* 66256 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 24181 | /* 66259 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 24182 | /* 66262 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 24183 | /* 66265 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 24184 | /* 66268 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24185 | /* 66272 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24186 | /* 66276 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24187 | /* 66280 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 24188 | /* 66284 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3639:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }) => (MVE_VHADDu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 24189 | /* 66284 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 24190 | /* 66287 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 24191 | /* 66291 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24192 | /* 66296 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHADDu16), |
| 24193 | /* 66299 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24194 | /* 66301 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 24195 | /* 66303 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 24196 | /* 66305 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24197 | /* 66308 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24198 | /* 66314 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24199 | /* 66320 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24200 | /* 66323 */ GIR_RootConstrainSelectedInstOperands, |
| 24201 | /* 66324 */ // GIR_Coverage, 3615, |
| 24202 | /* 66324 */ GIR_EraseRootFromParent_Done, |
| 24203 | /* 66325 */ // Label 1361: @66325 |
| 24204 | /* 66325 */ GIM_Try, /*On fail goto*//*Label 1362*/ GIMT_Encode4(66407), // Rule ID 3619 // |
| 24205 | /* 66330 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 24206 | /* 66333 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vhadd), |
| 24207 | /* 66338 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 24208 | /* 66341 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 24209 | /* 66344 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 24210 | /* 66347 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 24211 | /* 66350 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24212 | /* 66354 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24213 | /* 66358 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24214 | /* 66362 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 24215 | /* 66366 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3639:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] }) => (MVE_VHADDu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 24216 | /* 66366 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 24217 | /* 66369 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 24218 | /* 66373 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24219 | /* 66378 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHADDu32), |
| 24220 | /* 66381 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24221 | /* 66383 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 24222 | /* 66385 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 24223 | /* 66387 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24224 | /* 66390 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24225 | /* 66396 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24226 | /* 66402 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24227 | /* 66405 */ GIR_RootConstrainSelectedInstOperands, |
| 24228 | /* 66406 */ // GIR_Coverage, 3619, |
| 24229 | /* 66406 */ GIR_EraseRootFromParent_Done, |
| 24230 | /* 66407 */ // Label 1362: @66407 |
| 24231 | /* 66407 */ GIM_Try, /*On fail goto*//*Label 1363*/ GIMT_Encode4(66489), // Rule ID 3620 // |
| 24232 | /* 66412 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 24233 | /* 66415 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vhsub), |
| 24234 | /* 66420 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 24235 | /* 66423 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 24236 | /* 66426 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 24237 | /* 66429 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 24238 | /* 66432 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24239 | /* 66436 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24240 | /* 66440 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24241 | /* 66444 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 24242 | /* 66448 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3640:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] }) => (MVE_VHSUBs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 24243 | /* 66448 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 24244 | /* 66451 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 24245 | /* 66455 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24246 | /* 66460 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHSUBs8), |
| 24247 | /* 66463 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24248 | /* 66465 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 24249 | /* 66467 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 24250 | /* 66469 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24251 | /* 66472 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24252 | /* 66478 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24253 | /* 66484 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24254 | /* 66487 */ GIR_RootConstrainSelectedInstOperands, |
| 24255 | /* 66488 */ // GIR_Coverage, 3620, |
| 24256 | /* 66488 */ GIR_EraseRootFromParent_Done, |
| 24257 | /* 66489 */ // Label 1363: @66489 |
| 24258 | /* 66489 */ GIM_Try, /*On fail goto*//*Label 1364*/ GIMT_Encode4(66571), // Rule ID 3623 // |
| 24259 | /* 66494 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 24260 | /* 66497 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vhsub), |
| 24261 | /* 66502 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 24262 | /* 66505 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 24263 | /* 66508 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 24264 | /* 66511 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 24265 | /* 66514 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24266 | /* 66518 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24267 | /* 66522 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24268 | /* 66526 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 24269 | /* 66530 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3640:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }) => (MVE_VHSUBs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 24270 | /* 66530 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 24271 | /* 66533 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 24272 | /* 66537 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24273 | /* 66542 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHSUBs16), |
| 24274 | /* 66545 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24275 | /* 66547 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 24276 | /* 66549 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 24277 | /* 66551 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24278 | /* 66554 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24279 | /* 66560 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24280 | /* 66566 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24281 | /* 66569 */ GIR_RootConstrainSelectedInstOperands, |
| 24282 | /* 66570 */ // GIR_Coverage, 3623, |
| 24283 | /* 66570 */ GIR_EraseRootFromParent_Done, |
| 24284 | /* 66571 */ // Label 1364: @66571 |
| 24285 | /* 66571 */ GIM_Try, /*On fail goto*//*Label 1365*/ GIMT_Encode4(66653), // Rule ID 3626 // |
| 24286 | /* 66576 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 24287 | /* 66579 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vhsub), |
| 24288 | /* 66584 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 24289 | /* 66587 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 24290 | /* 66590 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 24291 | /* 66593 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 24292 | /* 66596 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24293 | /* 66600 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24294 | /* 66604 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24295 | /* 66608 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 24296 | /* 66612 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3640:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] }) => (MVE_VHSUBs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 24297 | /* 66612 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 24298 | /* 66615 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 24299 | /* 66619 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24300 | /* 66624 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHSUBs32), |
| 24301 | /* 66627 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24302 | /* 66629 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 24303 | /* 66631 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 24304 | /* 66633 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24305 | /* 66636 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24306 | /* 66642 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24307 | /* 66648 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24308 | /* 66651 */ GIR_RootConstrainSelectedInstOperands, |
| 24309 | /* 66652 */ // GIR_Coverage, 3626, |
| 24310 | /* 66652 */ GIR_EraseRootFromParent_Done, |
| 24311 | /* 66653 */ // Label 1365: @66653 |
| 24312 | /* 66653 */ GIM_Try, /*On fail goto*//*Label 1366*/ GIMT_Encode4(66735), // Rule ID 3629 // |
| 24313 | /* 66658 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 24314 | /* 66661 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vhsub), |
| 24315 | /* 66666 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 24316 | /* 66669 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 24317 | /* 66672 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 24318 | /* 66675 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 24319 | /* 66678 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24320 | /* 66682 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24321 | /* 66686 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24322 | /* 66690 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 24323 | /* 66694 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3640:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] }) => (MVE_VHSUBu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 24324 | /* 66694 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 24325 | /* 66697 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 24326 | /* 66701 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24327 | /* 66706 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHSUBu8), |
| 24328 | /* 66709 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24329 | /* 66711 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 24330 | /* 66713 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 24331 | /* 66715 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24332 | /* 66718 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24333 | /* 66724 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24334 | /* 66730 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24335 | /* 66733 */ GIR_RootConstrainSelectedInstOperands, |
| 24336 | /* 66734 */ // GIR_Coverage, 3629, |
| 24337 | /* 66734 */ GIR_EraseRootFromParent_Done, |
| 24338 | /* 66735 */ // Label 1366: @66735 |
| 24339 | /* 66735 */ GIM_Try, /*On fail goto*//*Label 1367*/ GIMT_Encode4(66817), // Rule ID 3632 // |
| 24340 | /* 66740 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 24341 | /* 66743 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vhsub), |
| 24342 | /* 66748 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 24343 | /* 66751 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 24344 | /* 66754 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 24345 | /* 66757 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 24346 | /* 66760 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24347 | /* 66764 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24348 | /* 66768 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24349 | /* 66772 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 24350 | /* 66776 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3640:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }) => (MVE_VHSUBu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 24351 | /* 66776 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 24352 | /* 66779 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 24353 | /* 66783 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24354 | /* 66788 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHSUBu16), |
| 24355 | /* 66791 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24356 | /* 66793 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 24357 | /* 66795 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 24358 | /* 66797 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24359 | /* 66800 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24360 | /* 66806 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24361 | /* 66812 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24362 | /* 66815 */ GIR_RootConstrainSelectedInstOperands, |
| 24363 | /* 66816 */ // GIR_Coverage, 3632, |
| 24364 | /* 66816 */ GIR_EraseRootFromParent_Done, |
| 24365 | /* 66817 */ // Label 1367: @66817 |
| 24366 | /* 66817 */ GIM_Try, /*On fail goto*//*Label 1368*/ GIMT_Encode4(66899), // Rule ID 3635 // |
| 24367 | /* 66822 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 24368 | /* 66825 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vhsub), |
| 24369 | /* 66830 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 24370 | /* 66833 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 24371 | /* 66836 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 24372 | /* 66839 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 24373 | /* 66842 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24374 | /* 66846 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24375 | /* 66850 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24376 | /* 66854 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 24377 | /* 66858 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3640:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] }) => (MVE_VHSUBu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 24378 | /* 66858 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 24379 | /* 66861 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 24380 | /* 66865 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24381 | /* 66870 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHSUBu32), |
| 24382 | /* 66873 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24383 | /* 66875 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 24384 | /* 66877 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 24385 | /* 66879 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24386 | /* 66882 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24387 | /* 66888 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24388 | /* 66894 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24389 | /* 66897 */ GIR_RootConstrainSelectedInstOperands, |
| 24390 | /* 66898 */ // GIR_Coverage, 3635, |
| 24391 | /* 66898 */ GIR_EraseRootFromParent_Done, |
| 24392 | /* 66899 */ // Label 1368: @66899 |
| 24393 | /* 66899 */ GIM_Try, /*On fail goto*//*Label 1369*/ GIMT_Encode4(66981), // Rule ID 4036 // |
| 24394 | /* 66904 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 24395 | /* 66907 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vabd), |
| 24396 | /* 66912 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 24397 | /* 66915 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 24398 | /* 66918 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 24399 | /* 66921 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 24400 | /* 66924 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24401 | /* 66928 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24402 | /* 66932 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24403 | /* 66936 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 24404 | /* 66940 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3604:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn, 0:{ *:[i32] }) => (MVE_VABDf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) |
| 24405 | /* 66940 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 24406 | /* 66943 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 24407 | /* 66947 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24408 | /* 66952 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDf32), |
| 24409 | /* 66955 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24410 | /* 66957 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 24411 | /* 66959 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 24412 | /* 66961 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24413 | /* 66964 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24414 | /* 66970 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24415 | /* 66976 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24416 | /* 66979 */ GIR_RootConstrainSelectedInstOperands, |
| 24417 | /* 66980 */ // GIR_Coverage, 4036, |
| 24418 | /* 66980 */ GIR_EraseRootFromParent_Done, |
| 24419 | /* 66981 */ // Label 1369: @66981 |
| 24420 | /* 66981 */ GIM_Try, /*On fail goto*//*Label 1370*/ GIMT_Encode4(67063), // Rule ID 4038 // |
| 24421 | /* 66986 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 24422 | /* 66989 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vabd), |
| 24423 | /* 66994 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 24424 | /* 66997 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 24425 | /* 67000 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 24426 | /* 67003 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 24427 | /* 67006 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24428 | /* 67010 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24429 | /* 67014 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24430 | /* 67018 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 24431 | /* 67022 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3604:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn, 0:{ *:[i32] }) => (MVE_VABDf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) |
| 24432 | /* 67022 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 24433 | /* 67025 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 24434 | /* 67029 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24435 | /* 67034 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDf16), |
| 24436 | /* 67037 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24437 | /* 67039 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 24438 | /* 67041 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 24439 | /* 67043 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24440 | /* 67046 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24441 | /* 67052 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24442 | /* 67058 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24443 | /* 67061 */ GIR_RootConstrainSelectedInstOperands, |
| 24444 | /* 67062 */ // GIR_Coverage, 4038, |
| 24445 | /* 67062 */ GIR_EraseRootFromParent_Done, |
| 24446 | /* 67063 */ // Label 1370: @67063 |
| 24447 | /* 67063 */ GIM_Try, /*On fail goto*//*Label 1371*/ GIMT_Encode4(67145), // Rule ID 4411 // |
| 24448 | /* 67068 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 24449 | /* 67071 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmull_poly), |
| 24450 | /* 67076 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 24451 | /* 67079 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 24452 | /* 67082 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 24453 | /* 67085 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 24454 | /* 67088 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24455 | /* 67092 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24456 | /* 67096 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24457 | /* 67100 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 24458 | /* 67104 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3667:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] }) => (MVE_VMULLBp8:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 24459 | /* 67104 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 24460 | /* 67107 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 24461 | /* 67111 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24462 | /* 67116 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLBp8), |
| 24463 | /* 67119 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24464 | /* 67121 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 24465 | /* 67123 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 24466 | /* 67125 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24467 | /* 67128 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24468 | /* 67134 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24469 | /* 67140 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24470 | /* 67143 */ GIR_RootConstrainSelectedInstOperands, |
| 24471 | /* 67144 */ // GIR_Coverage, 4411, |
| 24472 | /* 67144 */ GIR_EraseRootFromParent_Done, |
| 24473 | /* 67145 */ // Label 1371: @67145 |
| 24474 | /* 67145 */ GIM_Try, /*On fail goto*//*Label 1372*/ GIMT_Encode4(67227), // Rule ID 4413 // |
| 24475 | /* 67150 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 24476 | /* 67153 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmull_poly), |
| 24477 | /* 67158 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 24478 | /* 67161 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 24479 | /* 67164 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 24480 | /* 67167 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 24481 | /* 67170 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24482 | /* 67174 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24483 | /* 67178 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24484 | /* 67182 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 24485 | /* 67186 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3667:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] }) => (MVE_VMULLTp8:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 24486 | /* 67186 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 24487 | /* 67189 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 24488 | /* 67193 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24489 | /* 67198 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLTp8), |
| 24490 | /* 67201 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24491 | /* 67203 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 24492 | /* 67205 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 24493 | /* 67207 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24494 | /* 67210 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24495 | /* 67216 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24496 | /* 67222 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24497 | /* 67225 */ GIR_RootConstrainSelectedInstOperands, |
| 24498 | /* 67226 */ // GIR_Coverage, 4413, |
| 24499 | /* 67226 */ GIR_EraseRootFromParent_Done, |
| 24500 | /* 67227 */ // Label 1372: @67227 |
| 24501 | /* 67227 */ GIM_Try, /*On fail goto*//*Label 1373*/ GIMT_Encode4(67309), // Rule ID 4415 // |
| 24502 | /* 67232 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 24503 | /* 67235 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmull_poly), |
| 24504 | /* 67240 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 24505 | /* 67243 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 24506 | /* 67246 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 24507 | /* 67249 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 24508 | /* 67252 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24509 | /* 67256 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24510 | /* 67260 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24511 | /* 67264 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 24512 | /* 67268 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3667:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }) => (MVE_VMULLBp16:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 24513 | /* 67268 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 24514 | /* 67271 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 24515 | /* 67275 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24516 | /* 67280 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLBp16), |
| 24517 | /* 67283 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24518 | /* 67285 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 24519 | /* 67287 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 24520 | /* 67289 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24521 | /* 67292 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24522 | /* 67298 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24523 | /* 67304 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24524 | /* 67307 */ GIR_RootConstrainSelectedInstOperands, |
| 24525 | /* 67308 */ // GIR_Coverage, 4415, |
| 24526 | /* 67308 */ GIR_EraseRootFromParent_Done, |
| 24527 | /* 67309 */ // Label 1373: @67309 |
| 24528 | /* 67309 */ GIM_Try, /*On fail goto*//*Label 1374*/ GIMT_Encode4(67391), // Rule ID 4417 // |
| 24529 | /* 67314 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 24530 | /* 67317 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmull_poly), |
| 24531 | /* 67322 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 24532 | /* 67325 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 24533 | /* 67328 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 24534 | /* 67331 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 24535 | /* 67334 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24536 | /* 67338 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24537 | /* 67342 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24538 | /* 67346 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 24539 | /* 67350 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3667:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }) => (MVE_VMULLTp16:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 24540 | /* 67350 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 24541 | /* 67353 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 24542 | /* 67357 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24543 | /* 67362 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLTp16), |
| 24544 | /* 67365 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24545 | /* 67367 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 24546 | /* 67369 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 24547 | /* 67371 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24548 | /* 67374 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24549 | /* 67380 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24550 | /* 67386 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24551 | /* 67389 */ GIR_RootConstrainSelectedInstOperands, |
| 24552 | /* 67390 */ // GIR_Coverage, 4417, |
| 24553 | /* 67390 */ GIR_EraseRootFromParent_Done, |
| 24554 | /* 67391 */ // Label 1374: @67391 |
| 24555 | /* 67391 */ GIM_Try, /*On fail goto*//*Label 1375*/ GIMT_Encode4(67473), // Rule ID 4444 // |
| 24556 | /* 67396 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 24557 | /* 67399 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmulh), |
| 24558 | /* 67404 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 24559 | /* 67407 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 24560 | /* 67410 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 24561 | /* 67413 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 24562 | /* 67416 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24563 | /* 67420 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24564 | /* 67424 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24565 | /* 67428 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 24566 | /* 67432 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3665:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] }) => (MVE_VMULHs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 24567 | /* 67432 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 24568 | /* 67435 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 24569 | /* 67439 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24570 | /* 67444 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHs8), |
| 24571 | /* 67447 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24572 | /* 67449 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 24573 | /* 67451 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 24574 | /* 67453 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24575 | /* 67456 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24576 | /* 67462 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24577 | /* 67468 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24578 | /* 67471 */ GIR_RootConstrainSelectedInstOperands, |
| 24579 | /* 67472 */ // GIR_Coverage, 4444, |
| 24580 | /* 67472 */ GIR_EraseRootFromParent_Done, |
| 24581 | /* 67473 */ // Label 1375: @67473 |
| 24582 | /* 67473 */ GIM_Try, /*On fail goto*//*Label 1376*/ GIMT_Encode4(67555), // Rule ID 4451 // |
| 24583 | /* 67478 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 24584 | /* 67481 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmulh), |
| 24585 | /* 67486 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 24586 | /* 67489 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 24587 | /* 67492 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 24588 | /* 67495 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 24589 | /* 67498 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24590 | /* 67502 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24591 | /* 67506 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24592 | /* 67510 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 24593 | /* 67514 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3665:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }) => (MVE_VMULHs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 24594 | /* 67514 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 24595 | /* 67517 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 24596 | /* 67521 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24597 | /* 67526 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHs16), |
| 24598 | /* 67529 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24599 | /* 67531 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 24600 | /* 67533 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 24601 | /* 67535 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24602 | /* 67538 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24603 | /* 67544 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24604 | /* 67550 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24605 | /* 67553 */ GIR_RootConstrainSelectedInstOperands, |
| 24606 | /* 67554 */ // GIR_Coverage, 4451, |
| 24607 | /* 67554 */ GIR_EraseRootFromParent_Done, |
| 24608 | /* 67555 */ // Label 1376: @67555 |
| 24609 | /* 67555 */ GIM_Try, /*On fail goto*//*Label 1377*/ GIMT_Encode4(67637), // Rule ID 4455 // |
| 24610 | /* 67560 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 24611 | /* 67563 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmulh), |
| 24612 | /* 67568 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 24613 | /* 67571 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 24614 | /* 67574 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 24615 | /* 67577 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 24616 | /* 67580 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24617 | /* 67584 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24618 | /* 67588 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24619 | /* 67592 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 24620 | /* 67596 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3665:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] }) => (MVE_VMULHs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 24621 | /* 67596 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 24622 | /* 67599 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 24623 | /* 67603 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24624 | /* 67608 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHs32), |
| 24625 | /* 67611 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24626 | /* 67613 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 24627 | /* 67615 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 24628 | /* 67617 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24629 | /* 67620 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24630 | /* 67626 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24631 | /* 67632 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24632 | /* 67635 */ GIR_RootConstrainSelectedInstOperands, |
| 24633 | /* 67636 */ // GIR_Coverage, 4455, |
| 24634 | /* 67636 */ GIR_EraseRootFromParent_Done, |
| 24635 | /* 67637 */ // Label 1377: @67637 |
| 24636 | /* 67637 */ GIM_Try, /*On fail goto*//*Label 1378*/ GIMT_Encode4(67719), // Rule ID 4459 // |
| 24637 | /* 67642 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 24638 | /* 67645 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmulh), |
| 24639 | /* 67650 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 24640 | /* 67653 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 24641 | /* 67656 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 24642 | /* 67659 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 24643 | /* 67662 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24644 | /* 67666 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24645 | /* 67670 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24646 | /* 67674 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 24647 | /* 67678 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3665:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] }) => (MVE_VMULHu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 24648 | /* 67678 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 24649 | /* 67681 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 24650 | /* 67685 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24651 | /* 67690 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHu8), |
| 24652 | /* 67693 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24653 | /* 67695 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 24654 | /* 67697 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 24655 | /* 67699 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24656 | /* 67702 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24657 | /* 67708 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24658 | /* 67714 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24659 | /* 67717 */ GIR_RootConstrainSelectedInstOperands, |
| 24660 | /* 67718 */ // GIR_Coverage, 4459, |
| 24661 | /* 67718 */ GIR_EraseRootFromParent_Done, |
| 24662 | /* 67719 */ // Label 1378: @67719 |
| 24663 | /* 67719 */ GIM_Try, /*On fail goto*//*Label 1379*/ GIMT_Encode4(67801), // Rule ID 4463 // |
| 24664 | /* 67724 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 24665 | /* 67727 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmulh), |
| 24666 | /* 67732 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 24667 | /* 67735 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 24668 | /* 67738 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 24669 | /* 67741 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 24670 | /* 67744 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24671 | /* 67748 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24672 | /* 67752 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24673 | /* 67756 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 24674 | /* 67760 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3665:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }) => (MVE_VMULHu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 24675 | /* 67760 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 24676 | /* 67763 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 24677 | /* 67767 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24678 | /* 67772 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHu16), |
| 24679 | /* 67775 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24680 | /* 67777 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 24681 | /* 67779 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 24682 | /* 67781 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24683 | /* 67784 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24684 | /* 67790 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24685 | /* 67796 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24686 | /* 67799 */ GIR_RootConstrainSelectedInstOperands, |
| 24687 | /* 67800 */ // GIR_Coverage, 4463, |
| 24688 | /* 67800 */ GIR_EraseRootFromParent_Done, |
| 24689 | /* 67801 */ // Label 1379: @67801 |
| 24690 | /* 67801 */ GIM_Try, /*On fail goto*//*Label 1380*/ GIMT_Encode4(67883), // Rule ID 4467 // |
| 24691 | /* 67806 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 24692 | /* 67809 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmulh), |
| 24693 | /* 67814 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 24694 | /* 67817 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 24695 | /* 67820 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 24696 | /* 67823 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 24697 | /* 67826 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24698 | /* 67830 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24699 | /* 67834 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24700 | /* 67838 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 24701 | /* 67842 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3665:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] }) => (MVE_VMULHu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 24702 | /* 67842 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 24703 | /* 67845 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 24704 | /* 67849 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24705 | /* 67854 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHu32), |
| 24706 | /* 67857 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24707 | /* 67859 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 24708 | /* 67861 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 24709 | /* 67863 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24710 | /* 67866 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24711 | /* 67872 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24712 | /* 67878 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24713 | /* 67881 */ GIR_RootConstrainSelectedInstOperands, |
| 24714 | /* 67882 */ // GIR_Coverage, 4467, |
| 24715 | /* 67882 */ GIR_EraseRootFromParent_Done, |
| 24716 | /* 67883 */ // Label 1380: @67883 |
| 24717 | /* 67883 */ GIM_Try, /*On fail goto*//*Label 1381*/ GIMT_Encode4(67965), // Rule ID 4468 // |
| 24718 | /* 67888 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 24719 | /* 67891 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrmulh), |
| 24720 | /* 67896 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 24721 | /* 67899 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 24722 | /* 67902 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 24723 | /* 67905 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 24724 | /* 67908 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24725 | /* 67912 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24726 | /* 67916 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24727 | /* 67920 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 24728 | /* 67924 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3699:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] }) => (MVE_VRMULHs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 24729 | /* 67924 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 24730 | /* 67927 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 24731 | /* 67931 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24732 | /* 67936 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRMULHs8), |
| 24733 | /* 67939 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24734 | /* 67941 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 24735 | /* 67943 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 24736 | /* 67945 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24737 | /* 67948 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24738 | /* 67954 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24739 | /* 67960 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24740 | /* 67963 */ GIR_RootConstrainSelectedInstOperands, |
| 24741 | /* 67964 */ // GIR_Coverage, 4468, |
| 24742 | /* 67964 */ GIR_EraseRootFromParent_Done, |
| 24743 | /* 67965 */ // Label 1381: @67965 |
| 24744 | /* 67965 */ GIM_Try, /*On fail goto*//*Label 1382*/ GIMT_Encode4(68047), // Rule ID 4470 // |
| 24745 | /* 67970 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 24746 | /* 67973 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrmulh), |
| 24747 | /* 67978 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 24748 | /* 67981 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 24749 | /* 67984 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 24750 | /* 67987 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 24751 | /* 67990 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24752 | /* 67994 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24753 | /* 67998 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24754 | /* 68002 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 24755 | /* 68006 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3699:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }) => (MVE_VRMULHs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 24756 | /* 68006 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 24757 | /* 68009 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 24758 | /* 68013 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24759 | /* 68018 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRMULHs16), |
| 24760 | /* 68021 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24761 | /* 68023 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 24762 | /* 68025 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 24763 | /* 68027 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24764 | /* 68030 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24765 | /* 68036 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24766 | /* 68042 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24767 | /* 68045 */ GIR_RootConstrainSelectedInstOperands, |
| 24768 | /* 68046 */ // GIR_Coverage, 4470, |
| 24769 | /* 68046 */ GIR_EraseRootFromParent_Done, |
| 24770 | /* 68047 */ // Label 1382: @68047 |
| 24771 | /* 68047 */ GIM_Try, /*On fail goto*//*Label 1383*/ GIMT_Encode4(68129), // Rule ID 4472 // |
| 24772 | /* 68052 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 24773 | /* 68055 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrmulh), |
| 24774 | /* 68060 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 24775 | /* 68063 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 24776 | /* 68066 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 24777 | /* 68069 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 24778 | /* 68072 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24779 | /* 68076 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24780 | /* 68080 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24781 | /* 68084 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 24782 | /* 68088 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3699:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] }) => (MVE_VRMULHs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 24783 | /* 68088 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 24784 | /* 68091 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 24785 | /* 68095 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24786 | /* 68100 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRMULHs32), |
| 24787 | /* 68103 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24788 | /* 68105 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 24789 | /* 68107 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 24790 | /* 68109 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24791 | /* 68112 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24792 | /* 68118 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24793 | /* 68124 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24794 | /* 68127 */ GIR_RootConstrainSelectedInstOperands, |
| 24795 | /* 68128 */ // GIR_Coverage, 4472, |
| 24796 | /* 68128 */ GIR_EraseRootFromParent_Done, |
| 24797 | /* 68129 */ // Label 1383: @68129 |
| 24798 | /* 68129 */ GIM_Try, /*On fail goto*//*Label 1384*/ GIMT_Encode4(68211), // Rule ID 4474 // |
| 24799 | /* 68134 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 24800 | /* 68137 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrmulh), |
| 24801 | /* 68142 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 24802 | /* 68145 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 24803 | /* 68148 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 24804 | /* 68151 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 24805 | /* 68154 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24806 | /* 68158 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24807 | /* 68162 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24808 | /* 68166 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 24809 | /* 68170 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3699:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] }) => (MVE_VRMULHu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 24810 | /* 68170 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 24811 | /* 68173 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 24812 | /* 68177 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24813 | /* 68182 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRMULHu8), |
| 24814 | /* 68185 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24815 | /* 68187 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 24816 | /* 68189 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 24817 | /* 68191 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24818 | /* 68194 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24819 | /* 68200 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24820 | /* 68206 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24821 | /* 68209 */ GIR_RootConstrainSelectedInstOperands, |
| 24822 | /* 68210 */ // GIR_Coverage, 4474, |
| 24823 | /* 68210 */ GIR_EraseRootFromParent_Done, |
| 24824 | /* 68211 */ // Label 1384: @68211 |
| 24825 | /* 68211 */ GIM_Try, /*On fail goto*//*Label 1385*/ GIMT_Encode4(68293), // Rule ID 4476 // |
| 24826 | /* 68216 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 24827 | /* 68219 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrmulh), |
| 24828 | /* 68224 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 24829 | /* 68227 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 24830 | /* 68230 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 24831 | /* 68233 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 24832 | /* 68236 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24833 | /* 68240 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24834 | /* 68244 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24835 | /* 68248 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 24836 | /* 68252 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3699:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }) => (MVE_VRMULHu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 24837 | /* 68252 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 24838 | /* 68255 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 24839 | /* 68259 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24840 | /* 68264 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRMULHu16), |
| 24841 | /* 68267 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24842 | /* 68269 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 24843 | /* 68271 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 24844 | /* 68273 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24845 | /* 68276 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24846 | /* 68282 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24847 | /* 68288 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24848 | /* 68291 */ GIR_RootConstrainSelectedInstOperands, |
| 24849 | /* 68292 */ // GIR_Coverage, 4476, |
| 24850 | /* 68292 */ GIR_EraseRootFromParent_Done, |
| 24851 | /* 68293 */ // Label 1385: @68293 |
| 24852 | /* 68293 */ GIM_Try, /*On fail goto*//*Label 1386*/ GIMT_Encode4(68375), // Rule ID 4478 // |
| 24853 | /* 68298 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 24854 | /* 68301 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrmulh), |
| 24855 | /* 68306 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 24856 | /* 68309 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 24857 | /* 68312 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 24858 | /* 68315 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 24859 | /* 68318 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24860 | /* 68322 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24861 | /* 68326 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24862 | /* 68330 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 24863 | /* 68334 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3699:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] }) => (MVE_VRMULHu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 24864 | /* 68334 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 24865 | /* 68337 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 24866 | /* 68341 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24867 | /* 68346 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRMULHu32), |
| 24868 | /* 68349 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24869 | /* 68351 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 24870 | /* 68353 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 24871 | /* 68355 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24872 | /* 68358 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24873 | /* 68364 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24874 | /* 68370 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24875 | /* 68373 */ GIR_RootConstrainSelectedInstOperands, |
| 24876 | /* 68374 */ // GIR_Coverage, 4478, |
| 24877 | /* 68374 */ GIR_EraseRootFromParent_Done, |
| 24878 | /* 68375 */ // Label 1386: @68375 |
| 24879 | /* 68375 */ GIM_Try, /*On fail goto*//*Label 1387*/ GIMT_Encode4(68442), // Rule ID 4529 // |
| 24880 | /* 68380 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 24881 | /* 68383 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_narrow), |
| 24882 | /* 68388 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 24883 | /* 68391 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 24884 | /* 68394 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 24885 | /* 68397 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 24886 | /* 68400 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24887 | /* 68404 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24888 | /* 68408 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24889 | /* 68412 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 24890 | /* 68416 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3623:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$Qd_src, MQPR:{ *:[v4f32] }:$Qm, 0:{ *:[i32] }) => (MVE_VCVTf16f32bh:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd_src, MQPR:{ *:[v4f32] }:$Qm) |
| 24891 | /* 68416 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf16f32bh), |
| 24892 | /* 68419 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24893 | /* 68421 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src |
| 24894 | /* 68423 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 24895 | /* 68425 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24896 | /* 68428 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24897 | /* 68434 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24898 | /* 68440 */ GIR_RootConstrainSelectedInstOperands, |
| 24899 | /* 68441 */ // GIR_Coverage, 4529, |
| 24900 | /* 68441 */ GIR_EraseRootFromParent_Done, |
| 24901 | /* 68442 */ // Label 1387: @68442 |
| 24902 | /* 68442 */ GIM_Try, /*On fail goto*//*Label 1388*/ GIMT_Encode4(68509), // Rule ID 4535 // |
| 24903 | /* 68447 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 24904 | /* 68450 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_narrow), |
| 24905 | /* 68455 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 24906 | /* 68458 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 24907 | /* 68461 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 24908 | /* 68464 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 24909 | /* 68467 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24910 | /* 68471 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24911 | /* 68475 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24912 | /* 68479 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 24913 | /* 68483 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3623:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$Qd_src, MQPR:{ *:[v4f32] }:$Qm, 1:{ *:[i32] }) => (MVE_VCVTf16f32th:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd_src, MQPR:{ *:[v4f32] }:$Qm) |
| 24914 | /* 68483 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf16f32th), |
| 24915 | /* 68486 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24916 | /* 68488 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src |
| 24917 | /* 68490 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 24918 | /* 68492 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24919 | /* 68495 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24920 | /* 68501 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24921 | /* 68507 */ GIR_RootConstrainSelectedInstOperands, |
| 24922 | /* 68508 */ // GIR_Coverage, 4535, |
| 24923 | /* 68508 */ GIR_EraseRootFromParent_Done, |
| 24924 | /* 68509 */ // Label 1388: @68509 |
| 24925 | /* 68509 */ GIM_Try, /*On fail goto*//*Label 1389*/ GIMT_Encode4(68591), // Rule ID 4553 // |
| 24926 | /* 68514 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 24927 | /* 68517 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmull), |
| 24928 | /* 68522 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 24929 | /* 68525 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 24930 | /* 68528 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 24931 | /* 68531 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 24932 | /* 68534 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24933 | /* 68538 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24934 | /* 68542 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24935 | /* 68546 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 24936 | /* 68550 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3675:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }) => (MVE_VQDMULLs16bh:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 24937 | /* 68550 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 24938 | /* 68553 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 24939 | /* 68557 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24940 | /* 68562 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMULLs16bh), |
| 24941 | /* 68565 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24942 | /* 68567 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 24943 | /* 68569 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 24944 | /* 68571 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24945 | /* 68574 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24946 | /* 68580 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24947 | /* 68586 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24948 | /* 68589 */ GIR_RootConstrainSelectedInstOperands, |
| 24949 | /* 68590 */ // GIR_Coverage, 4553, |
| 24950 | /* 68590 */ GIR_EraseRootFromParent_Done, |
| 24951 | /* 68591 */ // Label 1389: @68591 |
| 24952 | /* 68591 */ GIM_Try, /*On fail goto*//*Label 1390*/ GIMT_Encode4(68673), // Rule ID 4555 // |
| 24953 | /* 68596 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 24954 | /* 68599 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmull), |
| 24955 | /* 68604 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 24956 | /* 68607 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 24957 | /* 68610 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 24958 | /* 68613 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 24959 | /* 68616 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24960 | /* 68620 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24961 | /* 68624 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24962 | /* 68628 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 24963 | /* 68632 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3675:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }) => (MVE_VQDMULLs16th:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 24964 | /* 68632 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 24965 | /* 68635 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 24966 | /* 68639 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24967 | /* 68644 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMULLs16th), |
| 24968 | /* 68647 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24969 | /* 68649 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 24970 | /* 68651 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 24971 | /* 68653 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24972 | /* 68656 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24973 | /* 68662 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24974 | /* 68668 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24975 | /* 68671 */ GIR_RootConstrainSelectedInstOperands, |
| 24976 | /* 68672 */ // GIR_Coverage, 4555, |
| 24977 | /* 68672 */ GIR_EraseRootFromParent_Done, |
| 24978 | /* 68673 */ // Label 1390: @68673 |
| 24979 | /* 68673 */ GIM_Try, /*On fail goto*//*Label 1391*/ GIMT_Encode4(68755), // Rule ID 4557 // |
| 24980 | /* 68678 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 24981 | /* 68681 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmull), |
| 24982 | /* 68686 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 24983 | /* 68689 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 24984 | /* 68692 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 24985 | /* 68695 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 24986 | /* 68698 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24987 | /* 68702 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24988 | /* 68706 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24989 | /* 68710 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 24990 | /* 68714 */ // (intrinsic_wo_chain:{ *:[v2i64] } 3675:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] }) => (MVE_VQDMULLs32bh:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 24991 | /* 68714 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 24992 | /* 68717 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 24993 | /* 68721 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24994 | /* 68726 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMULLs32bh), |
| 24995 | /* 68729 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24996 | /* 68731 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 24997 | /* 68733 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 24998 | /* 68735 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24999 | /* 68738 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25000 | /* 68744 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25001 | /* 68750 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 25002 | /* 68753 */ GIR_RootConstrainSelectedInstOperands, |
| 25003 | /* 68754 */ // GIR_Coverage, 4557, |
| 25004 | /* 68754 */ GIR_EraseRootFromParent_Done, |
| 25005 | /* 68755 */ // Label 1391: @68755 |
| 25006 | /* 68755 */ GIM_Try, /*On fail goto*//*Label 1392*/ GIMT_Encode4(68837), // Rule ID 4559 // |
| 25007 | /* 68760 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 25008 | /* 68763 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmull), |
| 25009 | /* 68768 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 25010 | /* 68771 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 25011 | /* 68774 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 25012 | /* 68777 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 25013 | /* 68780 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25014 | /* 68784 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25015 | /* 68788 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25016 | /* 68792 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 25017 | /* 68796 */ // (intrinsic_wo_chain:{ *:[v2i64] } 3675:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] }) => (MVE_VQDMULLs32th:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 25018 | /* 68796 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 25019 | /* 68799 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 25020 | /* 68803 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25021 | /* 68808 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMULLs32th), |
| 25022 | /* 68811 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 25023 | /* 68813 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 25024 | /* 68815 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 25025 | /* 68817 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25026 | /* 68820 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25027 | /* 68826 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25028 | /* 68832 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 25029 | /* 68835 */ GIR_RootConstrainSelectedInstOperands, |
| 25030 | /* 68836 */ // GIR_Coverage, 4559, |
| 25031 | /* 68836 */ GIR_EraseRootFromParent_Done, |
| 25032 | /* 68837 */ // Label 1392: @68837 |
| 25033 | /* 68837 */ GIM_Try, /*On fail goto*//*Label 1393*/ GIMT_Encode4(68914), // Rule ID 3904 // |
| 25034 | /* 68842 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vsli), |
| 25035 | /* 68847 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 25036 | /* 68850 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 25037 | /* 68853 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 25038 | /* 68856 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 25039 | /* 68859 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25040 | /* 68863 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25041 | /* 68867 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25042 | /* 68871 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 25043 | /* 68875 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 25044 | /* 68879 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_7), |
| 25045 | /* 68883 */ // MIs[1] Operand 1 |
| 25046 | /* 68883 */ // No operand predicates |
| 25047 | /* 68883 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 25048 | /* 68885 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3714:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v16i8] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_imm0_7>>:$imm) => (MVE_VSLIimm8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v16i8] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_imm0_7>>:$imm) |
| 25049 | /* 68885 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSLIimm8), |
| 25050 | /* 68888 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 25051 | /* 68890 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 25052 | /* 68892 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 25053 | /* 68894 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 25054 | /* 68897 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25055 | /* 68900 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25056 | /* 68906 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25057 | /* 68912 */ GIR_RootConstrainSelectedInstOperands, |
| 25058 | /* 68913 */ // GIR_Coverage, 3904, |
| 25059 | /* 68913 */ GIR_EraseRootFromParent_Done, |
| 25060 | /* 68914 */ // Label 1393: @68914 |
| 25061 | /* 68914 */ GIM_Try, /*On fail goto*//*Label 1394*/ GIMT_Encode4(68991), // Rule ID 3906 // |
| 25062 | /* 68919 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vsli), |
| 25063 | /* 68924 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 25064 | /* 68927 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 25065 | /* 68930 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 25066 | /* 68933 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 25067 | /* 68936 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25068 | /* 68940 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25069 | /* 68944 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25070 | /* 68948 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 25071 | /* 68952 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 25072 | /* 68956 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15), |
| 25073 | /* 68960 */ // MIs[1] Operand 1 |
| 25074 | /* 68960 */ // No operand predicates |
| 25075 | /* 68960 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 25076 | /* 68962 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3714:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$imm) => (MVE_VSLIimm16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$imm) |
| 25077 | /* 68962 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSLIimm16), |
| 25078 | /* 68965 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 25079 | /* 68967 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 25080 | /* 68969 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 25081 | /* 68971 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 25082 | /* 68974 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25083 | /* 68977 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25084 | /* 68983 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25085 | /* 68989 */ GIR_RootConstrainSelectedInstOperands, |
| 25086 | /* 68990 */ // GIR_Coverage, 3906, |
| 25087 | /* 68990 */ GIR_EraseRootFromParent_Done, |
| 25088 | /* 68991 */ // Label 1394: @68991 |
| 25089 | /* 68991 */ GIM_Try, /*On fail goto*//*Label 1395*/ GIMT_Encode4(69068), // Rule ID 3908 // |
| 25090 | /* 68996 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vsli), |
| 25091 | /* 69001 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 25092 | /* 69004 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 25093 | /* 69007 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 25094 | /* 69010 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 25095 | /* 69013 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25096 | /* 69017 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25097 | /* 69021 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25098 | /* 69025 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 25099 | /* 69029 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 25100 | /* 69033 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31), |
| 25101 | /* 69037 */ // MIs[1] Operand 1 |
| 25102 | /* 69037 */ // No operand predicates |
| 25103 | /* 69037 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 25104 | /* 69039 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3714:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$imm) => (MVE_VSLIimm32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$imm) |
| 25105 | /* 69039 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSLIimm32), |
| 25106 | /* 69042 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 25107 | /* 69044 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 25108 | /* 69046 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 25109 | /* 69048 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 25110 | /* 69051 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25111 | /* 69054 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25112 | /* 69060 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25113 | /* 69066 */ GIR_RootConstrainSelectedInstOperands, |
| 25114 | /* 69067 */ // GIR_Coverage, 3908, |
| 25115 | /* 69067 */ GIR_EraseRootFromParent_Done, |
| 25116 | /* 69068 */ // Label 1395: @69068 |
| 25117 | /* 69068 */ GIM_Try, /*On fail goto*//*Label 1396*/ GIMT_Encode4(69145), // Rule ID 3910 // |
| 25118 | /* 69073 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vsri), |
| 25119 | /* 69078 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 25120 | /* 69081 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 25121 | /* 69084 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 25122 | /* 69087 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 25123 | /* 69090 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25124 | /* 69094 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25125 | /* 69098 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25126 | /* 69102 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 25127 | /* 69106 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 25128 | /* 69110 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8), |
| 25129 | /* 69114 */ // MIs[1] Operand 1 |
| 25130 | /* 69114 */ // No operand predicates |
| 25131 | /* 69114 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 25132 | /* 69116 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3716:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v16i8] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm) => (MVE_VSRIimm8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v16i8] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm) |
| 25133 | /* 69116 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSRIimm8), |
| 25134 | /* 69119 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 25135 | /* 69121 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 25136 | /* 69123 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 25137 | /* 69125 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 25138 | /* 69128 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25139 | /* 69131 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25140 | /* 69137 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25141 | /* 69143 */ GIR_RootConstrainSelectedInstOperands, |
| 25142 | /* 69144 */ // GIR_Coverage, 3910, |
| 25143 | /* 69144 */ GIR_EraseRootFromParent_Done, |
| 25144 | /* 69145 */ // Label 1396: @69145 |
| 25145 | /* 69145 */ GIM_Try, /*On fail goto*//*Label 1397*/ GIMT_Encode4(69222), // Rule ID 3912 // |
| 25146 | /* 69150 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vsri), |
| 25147 | /* 69155 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 25148 | /* 69158 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 25149 | /* 69161 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 25150 | /* 69164 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 25151 | /* 69167 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25152 | /* 69171 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25153 | /* 69175 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25154 | /* 69179 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 25155 | /* 69183 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 25156 | /* 69187 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16), |
| 25157 | /* 69191 */ // MIs[1] Operand 1 |
| 25158 | /* 69191 */ // No operand predicates |
| 25159 | /* 69191 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 25160 | /* 69193 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3716:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm) => (MVE_VSRIimm16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm) |
| 25161 | /* 69193 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSRIimm16), |
| 25162 | /* 69196 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 25163 | /* 69198 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 25164 | /* 69200 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 25165 | /* 69202 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 25166 | /* 69205 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25167 | /* 69208 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25168 | /* 69214 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25169 | /* 69220 */ GIR_RootConstrainSelectedInstOperands, |
| 25170 | /* 69221 */ // GIR_Coverage, 3912, |
| 25171 | /* 69221 */ GIR_EraseRootFromParent_Done, |
| 25172 | /* 69222 */ // Label 1397: @69222 |
| 25173 | /* 69222 */ GIM_Try, /*On fail goto*//*Label 1398*/ GIMT_Encode4(69299), // Rule ID 3914 // |
| 25174 | /* 69227 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vsri), |
| 25175 | /* 69232 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 25176 | /* 69235 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 25177 | /* 69238 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 25178 | /* 69241 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 25179 | /* 69244 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25180 | /* 69248 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25181 | /* 69252 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25182 | /* 69256 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 25183 | /* 69260 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 25184 | /* 69264 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm32), |
| 25185 | /* 69268 */ // MIs[1] Operand 1 |
| 25186 | /* 69268 */ // No operand predicates |
| 25187 | /* 69268 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 25188 | /* 69270 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3716:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm32>>:$imm) => (MVE_VSRIimm32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm32>>:$imm) |
| 25189 | /* 69270 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSRIimm32), |
| 25190 | /* 69273 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 25191 | /* 69275 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 25192 | /* 69277 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 25193 | /* 69279 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 25194 | /* 69282 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25195 | /* 69285 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25196 | /* 69291 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25197 | /* 69297 */ GIR_RootConstrainSelectedInstOperands, |
| 25198 | /* 69298 */ // GIR_Coverage, 3914, |
| 25199 | /* 69298 */ GIR_EraseRootFromParent_Done, |
| 25200 | /* 69299 */ // Label 1398: @69299 |
| 25201 | /* 69299 */ GIM_Try, /*On fail goto*//*Label 1399*/ GIMT_Encode4(69390), // Rule ID 4383 // |
| 25202 | /* 69304 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 25203 | /* 69307 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcmulq), |
| 25204 | /* 69312 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 25205 | /* 69315 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 25206 | /* 69318 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 25207 | /* 69321 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16, |
| 25208 | /* 69324 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25209 | /* 69328 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 25210 | /* 69332 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 25211 | /* 69336 */ // MIs[1] Operand 1 |
| 25212 | /* 69336 */ // No operand predicates |
| 25213 | /* 69336 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25214 | /* 69340 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25215 | /* 69344 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 25216 | /* 69346 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3614:{ *:[iPTR] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v8f16] }:$Qn, MQPR:{ *:[v8f16] }:$Qm) => (MVE_VCMULf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qn, MQPR:{ *:[v8f16] }:$Qm, (imm:{ *:[i32] }):$rot) |
| 25217 | /* 69346 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 25218 | /* 69349 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 25219 | /* 69353 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25220 | /* 69358 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMULf16), |
| 25221 | /* 69361 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 25222 | /* 69363 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 25223 | /* 69365 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qm |
| 25224 | /* 69367 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot |
| 25225 | /* 69370 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25226 | /* 69373 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25227 | /* 69379 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25228 | /* 69385 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 25229 | /* 69388 */ GIR_RootConstrainSelectedInstOperands, |
| 25230 | /* 69389 */ // GIR_Coverage, 4383, |
| 25231 | /* 69389 */ GIR_EraseRootFromParent_Done, |
| 25232 | /* 69390 */ // Label 1399: @69390 |
| 25233 | /* 69390 */ GIM_Try, /*On fail goto*//*Label 1400*/ GIMT_Encode4(69481), // Rule ID 4385 // |
| 25234 | /* 69395 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 25235 | /* 69398 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcmulq), |
| 25236 | /* 69403 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 25237 | /* 69406 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 25238 | /* 69409 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 25239 | /* 69412 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 25240 | /* 69415 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25241 | /* 69419 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 25242 | /* 69423 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 25243 | /* 69427 */ // MIs[1] Operand 1 |
| 25244 | /* 69427 */ // No operand predicates |
| 25245 | /* 69427 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25246 | /* 69431 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25247 | /* 69435 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 25248 | /* 69437 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3614:{ *:[iPTR] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v4f32] }:$Qn, MQPR:{ *:[v4f32] }:$Qm) => (MVE_VCMULf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qn, MQPR:{ *:[v4f32] }:$Qm, (imm:{ *:[i32] }):$rot) |
| 25249 | /* 69437 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 25250 | /* 69440 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 25251 | /* 69444 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25252 | /* 69449 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMULf32), |
| 25253 | /* 69452 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 25254 | /* 69454 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 25255 | /* 69456 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qm |
| 25256 | /* 69458 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot |
| 25257 | /* 69461 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25258 | /* 69464 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25259 | /* 69470 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25260 | /* 69476 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 25261 | /* 69479 */ GIR_RootConstrainSelectedInstOperands, |
| 25262 | /* 69480 */ // GIR_Coverage, 4385, |
| 25263 | /* 69480 */ GIR_EraseRootFromParent_Done, |
| 25264 | /* 69481 */ // Label 1400: @69481 |
| 25265 | /* 69481 */ GIM_Try, /*On fail goto*//*Label 1401*/ GIMT_Encode4(69544), // Rule ID 146 // |
| 25266 | /* 69486 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 25267 | /* 69489 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usada8), |
| 25268 | /* 69494 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 25269 | /* 69497 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 25270 | /* 69500 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 25271 | /* 69503 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 25272 | /* 69506 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 25273 | /* 69510 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 25274 | /* 69514 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 25275 | /* 69518 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 25276 | /* 69522 */ // (intrinsic_wo_chain:{ *:[i32] } 3941:{ *:[iPTR] }, GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) => (USADA8:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) |
| 25277 | /* 69522 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::USADA8), |
| 25278 | /* 69525 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 25279 | /* 69527 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 25280 | /* 69529 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 25281 | /* 69531 */ GIR_RootToRootCopy, /*OpIdx*/4, // Ra |
| 25282 | /* 69533 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 25283 | /* 69536 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25284 | /* 69542 */ GIR_RootConstrainSelectedInstOperands, |
| 25285 | /* 69543 */ // GIR_Coverage, 146, |
| 25286 | /* 69543 */ GIR_EraseRootFromParent_Done, |
| 25287 | /* 69544 */ // Label 1401: @69544 |
| 25288 | /* 69544 */ GIM_Try, /*On fail goto*//*Label 1402*/ GIMT_Encode4(69607), // Rule ID 469 // |
| 25289 | /* 69549 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 25290 | /* 69552 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usada8), |
| 25291 | /* 69557 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 25292 | /* 69560 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 25293 | /* 69563 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 25294 | /* 69566 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 25295 | /* 69569 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 25296 | /* 69573 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 25297 | /* 69577 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 25298 | /* 69581 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 25299 | /* 69585 */ // (intrinsic_wo_chain:{ *:[i32] } 3941:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) => (t2USADA8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) |
| 25300 | /* 69585 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2USADA8), |
| 25301 | /* 69588 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 25302 | /* 69590 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 25303 | /* 69592 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 25304 | /* 69594 */ GIR_RootToRootCopy, /*OpIdx*/4, // Ra |
| 25305 | /* 69596 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 25306 | /* 69599 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25307 | /* 69605 */ GIR_RootConstrainSelectedInstOperands, |
| 25308 | /* 69606 */ // GIR_Coverage, 469, |
| 25309 | /* 69606 */ GIR_EraseRootFromParent_Done, |
| 25310 | /* 69607 */ // Label 1402: @69607 |
| 25311 | /* 69607 */ GIM_Try, /*On fail goto*//*Label 1403*/ GIMT_Encode4(69670), // Rule ID 528 // |
| 25312 | /* 69612 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 25313 | /* 69615 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlad), |
| 25314 | /* 69620 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 25315 | /* 69623 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 25316 | /* 69626 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 25317 | /* 69629 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 25318 | /* 69632 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 25319 | /* 69636 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 25320 | /* 69640 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 25321 | /* 69644 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 25322 | /* 69648 */ // (intrinsic_wo_chain:{ *:[i32] } 3886:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) => (t2SMLAD:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) |
| 25323 | /* 69648 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLAD), |
| 25324 | /* 69651 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 25325 | /* 69653 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 25326 | /* 69655 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 25327 | /* 69657 */ GIR_RootToRootCopy, /*OpIdx*/4, // Ra |
| 25328 | /* 69659 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 25329 | /* 69662 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25330 | /* 69668 */ GIR_RootConstrainSelectedInstOperands, |
| 25331 | /* 69669 */ // GIR_Coverage, 528, |
| 25332 | /* 69669 */ GIR_EraseRootFromParent_Done, |
| 25333 | /* 69670 */ // Label 1403: @69670 |
| 25334 | /* 69670 */ GIM_Try, /*On fail goto*//*Label 1404*/ GIMT_Encode4(69733), // Rule ID 529 // |
| 25335 | /* 69675 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 25336 | /* 69678 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smladx), |
| 25337 | /* 69683 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 25338 | /* 69686 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 25339 | /* 69689 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 25340 | /* 69692 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 25341 | /* 69695 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 25342 | /* 69699 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 25343 | /* 69703 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 25344 | /* 69707 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 25345 | /* 69711 */ // (intrinsic_wo_chain:{ *:[i32] } 3887:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) => (t2SMLADX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) |
| 25346 | /* 69711 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLADX), |
| 25347 | /* 69714 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 25348 | /* 69716 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 25349 | /* 69718 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 25350 | /* 69720 */ GIR_RootToRootCopy, /*OpIdx*/4, // Ra |
| 25351 | /* 69722 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 25352 | /* 69725 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25353 | /* 69731 */ GIR_RootConstrainSelectedInstOperands, |
| 25354 | /* 69732 */ // GIR_Coverage, 529, |
| 25355 | /* 69732 */ GIR_EraseRootFromParent_Done, |
| 25356 | /* 69733 */ // Label 1404: @69733 |
| 25357 | /* 69733 */ GIM_Try, /*On fail goto*//*Label 1405*/ GIMT_Encode4(69796), // Rule ID 530 // |
| 25358 | /* 69738 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 25359 | /* 69741 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlsd), |
| 25360 | /* 69746 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 25361 | /* 69749 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 25362 | /* 69752 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 25363 | /* 69755 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 25364 | /* 69758 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 25365 | /* 69762 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 25366 | /* 69766 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 25367 | /* 69770 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 25368 | /* 69774 */ // (intrinsic_wo_chain:{ *:[i32] } 3894:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) => (t2SMLSD:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) |
| 25369 | /* 69774 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLSD), |
| 25370 | /* 69777 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 25371 | /* 69779 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 25372 | /* 69781 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 25373 | /* 69783 */ GIR_RootToRootCopy, /*OpIdx*/4, // Ra |
| 25374 | /* 69785 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 25375 | /* 69788 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25376 | /* 69794 */ GIR_RootConstrainSelectedInstOperands, |
| 25377 | /* 69795 */ // GIR_Coverage, 530, |
| 25378 | /* 69795 */ GIR_EraseRootFromParent_Done, |
| 25379 | /* 69796 */ // Label 1405: @69796 |
| 25380 | /* 69796 */ GIM_Try, /*On fail goto*//*Label 1406*/ GIMT_Encode4(69859), // Rule ID 531 // |
| 25381 | /* 69801 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 25382 | /* 69804 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlsdx), |
| 25383 | /* 69809 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 25384 | /* 69812 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 25385 | /* 69815 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 25386 | /* 69818 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 25387 | /* 69821 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 25388 | /* 69825 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 25389 | /* 69829 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 25390 | /* 69833 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 25391 | /* 69837 */ // (intrinsic_wo_chain:{ *:[i32] } 3895:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) => (t2SMLSDX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) |
| 25392 | /* 69837 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLSDX), |
| 25393 | /* 69840 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 25394 | /* 69842 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 25395 | /* 69844 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 25396 | /* 69846 */ GIR_RootToRootCopy, /*OpIdx*/4, // Ra |
| 25397 | /* 69848 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 25398 | /* 69851 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25399 | /* 69857 */ GIR_RootConstrainSelectedInstOperands, |
| 25400 | /* 69858 */ // GIR_Coverage, 531, |
| 25401 | /* 69858 */ GIR_EraseRootFromParent_Done, |
| 25402 | /* 69859 */ // Label 1406: @69859 |
| 25403 | /* 69859 */ GIM_Try, /*On fail goto*//*Label 1407*/ GIMT_Encode4(69913), // Rule ID 951 // |
| 25404 | /* 69864 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDotProd), |
| 25405 | /* 69867 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_udot), |
| 25406 | /* 69872 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 25407 | /* 69875 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 25408 | /* 69878 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 25409 | /* 69881 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s8, |
| 25410 | /* 69884 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 25411 | /* 69888 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 25412 | /* 69892 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 25413 | /* 69896 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 25414 | /* 69900 */ // (intrinsic_wo_chain:{ *:[v2i32] } 3746:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vd, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VUDOTD:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vd, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 25415 | /* 69900 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VUDOTD), |
| 25416 | /* 69903 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 25417 | /* 69905 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vd |
| 25418 | /* 69907 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 25419 | /* 69909 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 25420 | /* 69911 */ GIR_RootConstrainSelectedInstOperands, |
| 25421 | /* 69912 */ // GIR_Coverage, 951, |
| 25422 | /* 69912 */ GIR_EraseRootFromParent_Done, |
| 25423 | /* 69913 */ // Label 1407: @69913 |
| 25424 | /* 69913 */ GIM_Try, /*On fail goto*//*Label 1408*/ GIMT_Encode4(69967), // Rule ID 952 // |
| 25425 | /* 69918 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDotProd), |
| 25426 | /* 69921 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sdot), |
| 25427 | /* 69926 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 25428 | /* 69929 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 25429 | /* 69932 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 25430 | /* 69935 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s8, |
| 25431 | /* 69938 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 25432 | /* 69942 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 25433 | /* 69946 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 25434 | /* 69950 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 25435 | /* 69954 */ // (intrinsic_wo_chain:{ *:[v2i32] } 3734:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vd, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VSDOTD:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vd, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 25436 | /* 69954 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSDOTD), |
| 25437 | /* 69957 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 25438 | /* 69959 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vd |
| 25439 | /* 69961 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 25440 | /* 69963 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 25441 | /* 69965 */ GIR_RootConstrainSelectedInstOperands, |
| 25442 | /* 69966 */ // GIR_Coverage, 952, |
| 25443 | /* 69966 */ GIR_EraseRootFromParent_Done, |
| 25444 | /* 69967 */ // Label 1408: @69967 |
| 25445 | /* 69967 */ GIM_Try, /*On fail goto*//*Label 1409*/ GIMT_Encode4(70021), // Rule ID 953 // |
| 25446 | /* 69972 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDotProd), |
| 25447 | /* 69975 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_udot), |
| 25448 | /* 69980 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 25449 | /* 69983 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 25450 | /* 69986 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 25451 | /* 69989 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 25452 | /* 69992 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 25453 | /* 69996 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 25454 | /* 70000 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 25455 | /* 70004 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 25456 | /* 70008 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3746:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VUDOTQ:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 25457 | /* 70008 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VUDOTQ), |
| 25458 | /* 70011 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 25459 | /* 70013 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vd |
| 25460 | /* 70015 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 25461 | /* 70017 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 25462 | /* 70019 */ GIR_RootConstrainSelectedInstOperands, |
| 25463 | /* 70020 */ // GIR_Coverage, 953, |
| 25464 | /* 70020 */ GIR_EraseRootFromParent_Done, |
| 25465 | /* 70021 */ // Label 1409: @70021 |
| 25466 | /* 70021 */ GIM_Try, /*On fail goto*//*Label 1410*/ GIMT_Encode4(70075), // Rule ID 954 // |
| 25467 | /* 70026 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDotProd), |
| 25468 | /* 70029 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sdot), |
| 25469 | /* 70034 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 25470 | /* 70037 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 25471 | /* 70040 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 25472 | /* 70043 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 25473 | /* 70046 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 25474 | /* 70050 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 25475 | /* 70054 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 25476 | /* 70058 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 25477 | /* 70062 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3734:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VSDOTQ:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 25478 | /* 70062 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSDOTQ), |
| 25479 | /* 70065 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 25480 | /* 70067 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vd |
| 25481 | /* 70069 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 25482 | /* 70071 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 25483 | /* 70073 */ GIR_RootConstrainSelectedInstOperands, |
| 25484 | /* 70074 */ // GIR_Coverage, 954, |
| 25485 | /* 70074 */ GIR_EraseRootFromParent_Done, |
| 25486 | /* 70075 */ // Label 1410: @70075 |
| 25487 | /* 70075 */ GIM_Try, /*On fail goto*//*Label 1411*/ GIMT_Encode4(70129), // Rule ID 955 // |
| 25488 | /* 70080 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulInt8), |
| 25489 | /* 70083 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_smmla), |
| 25490 | /* 70088 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 25491 | /* 70091 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 25492 | /* 70094 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 25493 | /* 70097 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 25494 | /* 70100 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 25495 | /* 70104 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 25496 | /* 70108 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 25497 | /* 70112 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 25498 | /* 70116 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3745:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VSMMLA:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 25499 | /* 70116 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSMMLA), |
| 25500 | /* 70119 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 25501 | /* 70121 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vd |
| 25502 | /* 70123 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 25503 | /* 70125 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 25504 | /* 70127 */ GIR_RootConstrainSelectedInstOperands, |
| 25505 | /* 70128 */ // GIR_Coverage, 955, |
| 25506 | /* 70128 */ GIR_EraseRootFromParent_Done, |
| 25507 | /* 70129 */ // Label 1411: @70129 |
| 25508 | /* 70129 */ GIM_Try, /*On fail goto*//*Label 1412*/ GIMT_Encode4(70183), // Rule ID 956 // |
| 25509 | /* 70134 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulInt8), |
| 25510 | /* 70137 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_ummla), |
| 25511 | /* 70142 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 25512 | /* 70145 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 25513 | /* 70148 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 25514 | /* 70151 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 25515 | /* 70154 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 25516 | /* 70158 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 25517 | /* 70162 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 25518 | /* 70166 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 25519 | /* 70170 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3747:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VUMMLA:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 25520 | /* 70170 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VUMMLA), |
| 25521 | /* 70173 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 25522 | /* 70175 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vd |
| 25523 | /* 70177 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 25524 | /* 70179 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 25525 | /* 70181 */ GIR_RootConstrainSelectedInstOperands, |
| 25526 | /* 70182 */ // GIR_Coverage, 956, |
| 25527 | /* 70182 */ GIR_EraseRootFromParent_Done, |
| 25528 | /* 70183 */ // Label 1412: @70183 |
| 25529 | /* 70183 */ GIM_Try, /*On fail goto*//*Label 1413*/ GIMT_Encode4(70237), // Rule ID 957 // |
| 25530 | /* 70188 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulInt8), |
| 25531 | /* 70191 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_usmmla), |
| 25532 | /* 70196 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 25533 | /* 70199 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 25534 | /* 70202 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 25535 | /* 70205 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 25536 | /* 70208 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 25537 | /* 70212 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 25538 | /* 70216 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 25539 | /* 70220 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 25540 | /* 70224 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3749:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VUSMMLA:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 25541 | /* 70224 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VUSMMLA), |
| 25542 | /* 70227 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 25543 | /* 70229 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vd |
| 25544 | /* 70231 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 25545 | /* 70233 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 25546 | /* 70235 */ GIR_RootConstrainSelectedInstOperands, |
| 25547 | /* 70236 */ // GIR_Coverage, 957, |
| 25548 | /* 70236 */ GIR_EraseRootFromParent_Done, |
| 25549 | /* 70237 */ // Label 1413: @70237 |
| 25550 | /* 70237 */ GIM_Try, /*On fail goto*//*Label 1414*/ GIMT_Encode4(70291), // Rule ID 958 // |
| 25551 | /* 70242 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulInt8), |
| 25552 | /* 70245 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_usdot), |
| 25553 | /* 70250 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 25554 | /* 70253 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 25555 | /* 70256 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 25556 | /* 70259 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s8, |
| 25557 | /* 70262 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 25558 | /* 70266 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 25559 | /* 70270 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 25560 | /* 70274 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 25561 | /* 70278 */ // (intrinsic_wo_chain:{ *:[v2i32] } 3748:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vd, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VUSDOTD:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vd, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 25562 | /* 70278 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VUSDOTD), |
| 25563 | /* 70281 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 25564 | /* 70283 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vd |
| 25565 | /* 70285 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 25566 | /* 70287 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 25567 | /* 70289 */ GIR_RootConstrainSelectedInstOperands, |
| 25568 | /* 70290 */ // GIR_Coverage, 958, |
| 25569 | /* 70290 */ GIR_EraseRootFromParent_Done, |
| 25570 | /* 70291 */ // Label 1414: @70291 |
| 25571 | /* 70291 */ GIM_Try, /*On fail goto*//*Label 1415*/ GIMT_Encode4(70345), // Rule ID 959 // |
| 25572 | /* 70296 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulInt8), |
| 25573 | /* 70299 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_usdot), |
| 25574 | /* 70304 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 25575 | /* 70307 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 25576 | /* 70310 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 25577 | /* 70313 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 25578 | /* 70316 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 25579 | /* 70320 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 25580 | /* 70324 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 25581 | /* 70328 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 25582 | /* 70332 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3748:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VUSDOTQ:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 25583 | /* 70332 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VUSDOTQ), |
| 25584 | /* 70335 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 25585 | /* 70337 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vd |
| 25586 | /* 70339 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 25587 | /* 70341 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 25588 | /* 70343 */ GIR_RootConstrainSelectedInstOperands, |
| 25589 | /* 70344 */ // GIR_Coverage, 959, |
| 25590 | /* 70344 */ GIR_EraseRootFromParent_Done, |
| 25591 | /* 70345 */ // Label 1415: @70345 |
| 25592 | /* 70345 */ GIM_Try, /*On fail goto*//*Label 1416*/ GIMT_Encode4(70408), // Rule ID 1690 // |
| 25593 | /* 70350 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 25594 | /* 70353 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vtbx1), |
| 25595 | /* 70358 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, |
| 25596 | /* 70361 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 25597 | /* 70364 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 25598 | /* 70367 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s8, |
| 25599 | /* 70370 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 25600 | /* 70374 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 25601 | /* 70378 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 25602 | /* 70382 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 25603 | /* 70386 */ // (intrinsic_wo_chain:{ *:[v8i8] } 3861:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$orig, VecListOneD:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VTBX1:{ *:[v8i8] } DPR:{ *:[v8i8] }:$orig, VecListOneD:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 25604 | /* 70386 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VTBX1), |
| 25605 | /* 70389 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 25606 | /* 70391 */ GIR_RootToRootCopy, /*OpIdx*/2, // orig |
| 25607 | /* 70393 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 25608 | /* 70395 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 25609 | /* 70397 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 25610 | /* 70400 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25611 | /* 70406 */ GIR_RootConstrainSelectedInstOperands, |
| 25612 | /* 70407 */ // GIR_Coverage, 1690, |
| 25613 | /* 70407 */ GIR_EraseRootFromParent_Done, |
| 25614 | /* 70408 */ // Label 1416: @70408 |
| 25615 | /* 70408 */ GIM_Try, /*On fail goto*//*Label 1417*/ GIMT_Encode4(70462), // Rule ID 1721 // |
| 25616 | /* 70413 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA2_HasV8), |
| 25617 | /* 70416 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sha1su0), |
| 25618 | /* 70421 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 25619 | /* 70424 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 25620 | /* 70427 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 25621 | /* 70430 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 25622 | /* 70433 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 25623 | /* 70437 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 25624 | /* 70441 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 25625 | /* 70445 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 25626 | /* 70449 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3739:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (SHA1SU0:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 25627 | /* 70449 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHA1SU0), |
| 25628 | /* 70452 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 25629 | /* 70454 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 25630 | /* 70456 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 25631 | /* 70458 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 25632 | /* 70460 */ GIR_RootConstrainSelectedInstOperands, |
| 25633 | /* 70461 */ // GIR_Coverage, 1721, |
| 25634 | /* 70461 */ GIR_EraseRootFromParent_Done, |
| 25635 | /* 70462 */ // Label 1417: @70462 |
| 25636 | /* 70462 */ GIM_Try, /*On fail goto*//*Label 1418*/ GIMT_Encode4(70516), // Rule ID 1722 // |
| 25637 | /* 70467 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA2_HasV8), |
| 25638 | /* 70470 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sha256h), |
| 25639 | /* 70475 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 25640 | /* 70478 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 25641 | /* 70481 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 25642 | /* 70484 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 25643 | /* 70487 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 25644 | /* 70491 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 25645 | /* 70495 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 25646 | /* 70499 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 25647 | /* 70503 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3741:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (SHA256H:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 25648 | /* 70503 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHA256H), |
| 25649 | /* 70506 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 25650 | /* 70508 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 25651 | /* 70510 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 25652 | /* 70512 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 25653 | /* 70514 */ GIR_RootConstrainSelectedInstOperands, |
| 25654 | /* 70515 */ // GIR_Coverage, 1722, |
| 25655 | /* 70515 */ GIR_EraseRootFromParent_Done, |
| 25656 | /* 70516 */ // Label 1418: @70516 |
| 25657 | /* 70516 */ GIM_Try, /*On fail goto*//*Label 1419*/ GIMT_Encode4(70570), // Rule ID 1723 // |
| 25658 | /* 70521 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA2_HasV8), |
| 25659 | /* 70524 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sha256h2), |
| 25660 | /* 70529 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 25661 | /* 70532 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 25662 | /* 70535 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 25663 | /* 70538 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 25664 | /* 70541 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 25665 | /* 70545 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 25666 | /* 70549 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 25667 | /* 70553 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 25668 | /* 70557 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3742:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (SHA256H2:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 25669 | /* 70557 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHA256H2), |
| 25670 | /* 70560 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 25671 | /* 70562 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 25672 | /* 70564 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 25673 | /* 70566 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 25674 | /* 70568 */ GIR_RootConstrainSelectedInstOperands, |
| 25675 | /* 70569 */ // GIR_Coverage, 1723, |
| 25676 | /* 70569 */ GIR_EraseRootFromParent_Done, |
| 25677 | /* 70570 */ // Label 1419: @70570 |
| 25678 | /* 70570 */ GIM_Try, /*On fail goto*//*Label 1420*/ GIMT_Encode4(70624), // Rule ID 1724 // |
| 25679 | /* 70575 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA2_HasV8), |
| 25680 | /* 70578 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sha256su1), |
| 25681 | /* 70583 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 25682 | /* 70586 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 25683 | /* 70589 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 25684 | /* 70592 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 25685 | /* 70595 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 25686 | /* 70599 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 25687 | /* 70603 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 25688 | /* 70607 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 25689 | /* 70611 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3744:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (SHA256SU1:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 25690 | /* 70611 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHA256SU1), |
| 25691 | /* 70614 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 25692 | /* 70616 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 25693 | /* 70618 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 25694 | /* 70620 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 25695 | /* 70622 */ GIR_RootConstrainSelectedInstOperands, |
| 25696 | /* 70623 */ // GIR_Coverage, 1724, |
| 25697 | /* 70623 */ GIR_EraseRootFromParent_Done, |
| 25698 | /* 70624 */ // Label 1420: @70624 |
| 25699 | /* 70624 */ GIM_Try, /*On fail goto*//*Label 1421*/ GIMT_Encode4(70687), // Rule ID 1899 // |
| 25700 | /* 70629 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 25701 | /* 70632 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlad), |
| 25702 | /* 70637 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 25703 | /* 70640 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 25704 | /* 70643 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 25705 | /* 70646 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 25706 | /* 70649 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 25707 | /* 70653 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 25708 | /* 70657 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 25709 | /* 70661 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 25710 | /* 70665 */ // (intrinsic_wo_chain:{ *:[i32] } 3886:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) => (SMLAD:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra) |
| 25711 | /* 70665 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLAD), |
| 25712 | /* 70668 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 25713 | /* 70670 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 25714 | /* 70672 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 25715 | /* 70674 */ GIR_RootToRootCopy, /*OpIdx*/4, // Ra |
| 25716 | /* 70676 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 25717 | /* 70679 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25718 | /* 70685 */ GIR_RootConstrainSelectedInstOperands, |
| 25719 | /* 70686 */ // GIR_Coverage, 1899, |
| 25720 | /* 70686 */ GIR_EraseRootFromParent_Done, |
| 25721 | /* 70687 */ // Label 1421: @70687 |
| 25722 | /* 70687 */ GIM_Try, /*On fail goto*//*Label 1422*/ GIMT_Encode4(70750), // Rule ID 1900 // |
| 25723 | /* 70692 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 25724 | /* 70695 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smladx), |
| 25725 | /* 70700 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 25726 | /* 70703 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 25727 | /* 70706 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 25728 | /* 70709 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 25729 | /* 70712 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 25730 | /* 70716 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 25731 | /* 70720 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 25732 | /* 70724 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 25733 | /* 70728 */ // (intrinsic_wo_chain:{ *:[i32] } 3887:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) => (SMLADX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra) |
| 25734 | /* 70728 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLADX), |
| 25735 | /* 70731 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 25736 | /* 70733 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 25737 | /* 70735 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 25738 | /* 70737 */ GIR_RootToRootCopy, /*OpIdx*/4, // Ra |
| 25739 | /* 70739 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 25740 | /* 70742 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25741 | /* 70748 */ GIR_RootConstrainSelectedInstOperands, |
| 25742 | /* 70749 */ // GIR_Coverage, 1900, |
| 25743 | /* 70749 */ GIR_EraseRootFromParent_Done, |
| 25744 | /* 70750 */ // Label 1422: @70750 |
| 25745 | /* 70750 */ GIM_Try, /*On fail goto*//*Label 1423*/ GIMT_Encode4(70813), // Rule ID 1901 // |
| 25746 | /* 70755 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 25747 | /* 70758 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlsd), |
| 25748 | /* 70763 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 25749 | /* 70766 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 25750 | /* 70769 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 25751 | /* 70772 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 25752 | /* 70775 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 25753 | /* 70779 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 25754 | /* 70783 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 25755 | /* 70787 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 25756 | /* 70791 */ // (intrinsic_wo_chain:{ *:[i32] } 3894:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) => (SMLSD:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra) |
| 25757 | /* 70791 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLSD), |
| 25758 | /* 70794 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 25759 | /* 70796 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 25760 | /* 70798 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 25761 | /* 70800 */ GIR_RootToRootCopy, /*OpIdx*/4, // Ra |
| 25762 | /* 70802 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 25763 | /* 70805 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25764 | /* 70811 */ GIR_RootConstrainSelectedInstOperands, |
| 25765 | /* 70812 */ // GIR_Coverage, 1901, |
| 25766 | /* 70812 */ GIR_EraseRootFromParent_Done, |
| 25767 | /* 70813 */ // Label 1423: @70813 |
| 25768 | /* 70813 */ GIM_Try, /*On fail goto*//*Label 1424*/ GIMT_Encode4(70876), // Rule ID 1902 // |
| 25769 | /* 70818 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 25770 | /* 70821 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlsdx), |
| 25771 | /* 70826 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 25772 | /* 70829 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 25773 | /* 70832 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 25774 | /* 70835 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 25775 | /* 70838 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 25776 | /* 70842 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 25777 | /* 70846 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 25778 | /* 70850 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 25779 | /* 70854 */ // (intrinsic_wo_chain:{ *:[i32] } 3895:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) => (SMLSDX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra) |
| 25780 | /* 70854 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLSDX), |
| 25781 | /* 70857 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 25782 | /* 70859 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 25783 | /* 70861 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 25784 | /* 70863 */ GIR_RootToRootCopy, /*OpIdx*/4, // Ra |
| 25785 | /* 70865 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 25786 | /* 70868 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25787 | /* 70874 */ GIR_RootConstrainSelectedInstOperands, |
| 25788 | /* 70875 */ // GIR_Coverage, 1902, |
| 25789 | /* 70875 */ GIR_EraseRootFromParent_Done, |
| 25790 | /* 70876 */ // Label 1424: @70876 |
| 25791 | /* 70876 */ GIM_Try, /*On fail goto*//*Label 1425*/ GIMT_Encode4(70939), // Rule ID 1990 // |
| 25792 | /* 70881 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM), |
| 25793 | /* 70884 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlabb), |
| 25794 | /* 70889 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 25795 | /* 70892 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 25796 | /* 70895 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 25797 | /* 70898 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 25798 | /* 70901 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 25799 | /* 70905 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 25800 | /* 70909 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 25801 | /* 70913 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 25802 | /* 70917 */ // (intrinsic_wo_chain:{ *:[i32] } 3884:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (SMLABB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) |
| 25803 | /* 70917 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLABB), |
| 25804 | /* 70920 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 25805 | /* 70922 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 25806 | /* 70924 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 25807 | /* 70926 */ GIR_RootToRootCopy, /*OpIdx*/4, // acc |
| 25808 | /* 70928 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 25809 | /* 70931 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25810 | /* 70937 */ GIR_RootConstrainSelectedInstOperands, |
| 25811 | /* 70938 */ // GIR_Coverage, 1990, |
| 25812 | /* 70938 */ GIR_EraseRootFromParent_Done, |
| 25813 | /* 70939 */ // Label 1425: @70939 |
| 25814 | /* 70939 */ GIM_Try, /*On fail goto*//*Label 1426*/ GIMT_Encode4(71002), // Rule ID 1991 // |
| 25815 | /* 70944 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM), |
| 25816 | /* 70947 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlabt), |
| 25817 | /* 70952 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 25818 | /* 70955 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 25819 | /* 70958 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 25820 | /* 70961 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 25821 | /* 70964 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 25822 | /* 70968 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 25823 | /* 70972 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 25824 | /* 70976 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 25825 | /* 70980 */ // (intrinsic_wo_chain:{ *:[i32] } 3885:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (SMLABT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) |
| 25826 | /* 70980 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLABT), |
| 25827 | /* 70983 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 25828 | /* 70985 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 25829 | /* 70987 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 25830 | /* 70989 */ GIR_RootToRootCopy, /*OpIdx*/4, // acc |
| 25831 | /* 70991 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 25832 | /* 70994 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25833 | /* 71000 */ GIR_RootConstrainSelectedInstOperands, |
| 25834 | /* 71001 */ // GIR_Coverage, 1991, |
| 25835 | /* 71001 */ GIR_EraseRootFromParent_Done, |
| 25836 | /* 71002 */ // Label 1426: @71002 |
| 25837 | /* 71002 */ GIM_Try, /*On fail goto*//*Label 1427*/ GIMT_Encode4(71065), // Rule ID 1992 // |
| 25838 | /* 71007 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM), |
| 25839 | /* 71010 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlatb), |
| 25840 | /* 71015 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 25841 | /* 71018 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 25842 | /* 71021 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 25843 | /* 71024 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 25844 | /* 71027 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 25845 | /* 71031 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 25846 | /* 71035 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 25847 | /* 71039 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 25848 | /* 71043 */ // (intrinsic_wo_chain:{ *:[i32] } 3890:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (SMLATB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) |
| 25849 | /* 71043 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLATB), |
| 25850 | /* 71046 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 25851 | /* 71048 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 25852 | /* 71050 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 25853 | /* 71052 */ GIR_RootToRootCopy, /*OpIdx*/4, // acc |
| 25854 | /* 71054 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 25855 | /* 71057 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25856 | /* 71063 */ GIR_RootConstrainSelectedInstOperands, |
| 25857 | /* 71064 */ // GIR_Coverage, 1992, |
| 25858 | /* 71064 */ GIR_EraseRootFromParent_Done, |
| 25859 | /* 71065 */ // Label 1427: @71065 |
| 25860 | /* 71065 */ GIM_Try, /*On fail goto*//*Label 1428*/ GIMT_Encode4(71128), // Rule ID 1993 // |
| 25861 | /* 71070 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM), |
| 25862 | /* 71073 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlatt), |
| 25863 | /* 71078 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 25864 | /* 71081 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 25865 | /* 71084 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 25866 | /* 71087 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 25867 | /* 71090 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 25868 | /* 71094 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 25869 | /* 71098 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 25870 | /* 71102 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 25871 | /* 71106 */ // (intrinsic_wo_chain:{ *:[i32] } 3891:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (SMLATT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) |
| 25872 | /* 71106 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLATT), |
| 25873 | /* 71109 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 25874 | /* 71111 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 25875 | /* 71113 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 25876 | /* 71115 */ GIR_RootToRootCopy, /*OpIdx*/4, // acc |
| 25877 | /* 71117 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 25878 | /* 71120 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25879 | /* 71126 */ GIR_RootConstrainSelectedInstOperands, |
| 25880 | /* 71127 */ // GIR_Coverage, 1993, |
| 25881 | /* 71127 */ GIR_EraseRootFromParent_Done, |
| 25882 | /* 71128 */ // Label 1428: @71128 |
| 25883 | /* 71128 */ GIM_Try, /*On fail goto*//*Label 1429*/ GIMT_Encode4(71191), // Rule ID 1994 // |
| 25884 | /* 71133 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM), |
| 25885 | /* 71136 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlawb), |
| 25886 | /* 71141 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 25887 | /* 71144 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 25888 | /* 71147 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 25889 | /* 71150 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 25890 | /* 71153 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 25891 | /* 71157 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 25892 | /* 71161 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 25893 | /* 71165 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 25894 | /* 71169 */ // (intrinsic_wo_chain:{ *:[i32] } 3892:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (SMLAWB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) |
| 25895 | /* 71169 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLAWB), |
| 25896 | /* 71172 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 25897 | /* 71174 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 25898 | /* 71176 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 25899 | /* 71178 */ GIR_RootToRootCopy, /*OpIdx*/4, // acc |
| 25900 | /* 71180 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 25901 | /* 71183 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25902 | /* 71189 */ GIR_RootConstrainSelectedInstOperands, |
| 25903 | /* 71190 */ // GIR_Coverage, 1994, |
| 25904 | /* 71190 */ GIR_EraseRootFromParent_Done, |
| 25905 | /* 71191 */ // Label 1429: @71191 |
| 25906 | /* 71191 */ GIM_Try, /*On fail goto*//*Label 1430*/ GIMT_Encode4(71254), // Rule ID 1995 // |
| 25907 | /* 71196 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM), |
| 25908 | /* 71199 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlawt), |
| 25909 | /* 71204 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 25910 | /* 71207 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 25911 | /* 71210 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 25912 | /* 71213 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 25913 | /* 71216 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 25914 | /* 71220 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 25915 | /* 71224 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 25916 | /* 71228 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 25917 | /* 71232 */ // (intrinsic_wo_chain:{ *:[i32] } 3893:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (SMLAWT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) |
| 25918 | /* 71232 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLAWT), |
| 25919 | /* 71235 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 25920 | /* 71237 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 25921 | /* 71239 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 25922 | /* 71241 */ GIR_RootToRootCopy, /*OpIdx*/4, // acc |
| 25923 | /* 71243 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 25924 | /* 71246 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25925 | /* 71252 */ GIR_RootConstrainSelectedInstOperands, |
| 25926 | /* 71253 */ // GIR_Coverage, 1995, |
| 25927 | /* 71253 */ GIR_EraseRootFromParent_Done, |
| 25928 | /* 71254 */ // Label 1430: @71254 |
| 25929 | /* 71254 */ GIM_Try, /*On fail goto*//*Label 1431*/ GIMT_Encode4(71317), // Rule ID 2181 // |
| 25930 | /* 71259 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 25931 | /* 71262 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlabb), |
| 25932 | /* 71267 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 25933 | /* 71270 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 25934 | /* 71273 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 25935 | /* 71276 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 25936 | /* 71279 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 25937 | /* 71283 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 25938 | /* 71287 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 25939 | /* 71291 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 25940 | /* 71295 */ // (intrinsic_wo_chain:{ *:[i32] } 3884:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (t2SMLABB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) |
| 25941 | /* 71295 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLABB), |
| 25942 | /* 71298 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 25943 | /* 71300 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 25944 | /* 71302 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 25945 | /* 71304 */ GIR_RootToRootCopy, /*OpIdx*/4, // acc |
| 25946 | /* 71306 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 25947 | /* 71309 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25948 | /* 71315 */ GIR_RootConstrainSelectedInstOperands, |
| 25949 | /* 71316 */ // GIR_Coverage, 2181, |
| 25950 | /* 71316 */ GIR_EraseRootFromParent_Done, |
| 25951 | /* 71317 */ // Label 1431: @71317 |
| 25952 | /* 71317 */ GIM_Try, /*On fail goto*//*Label 1432*/ GIMT_Encode4(71380), // Rule ID 2182 // |
| 25953 | /* 71322 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 25954 | /* 71325 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlabt), |
| 25955 | /* 71330 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 25956 | /* 71333 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 25957 | /* 71336 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 25958 | /* 71339 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 25959 | /* 71342 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 25960 | /* 71346 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 25961 | /* 71350 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 25962 | /* 71354 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 25963 | /* 71358 */ // (intrinsic_wo_chain:{ *:[i32] } 3885:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (t2SMLABT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) |
| 25964 | /* 71358 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLABT), |
| 25965 | /* 71361 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 25966 | /* 71363 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 25967 | /* 71365 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 25968 | /* 71367 */ GIR_RootToRootCopy, /*OpIdx*/4, // acc |
| 25969 | /* 71369 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 25970 | /* 71372 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25971 | /* 71378 */ GIR_RootConstrainSelectedInstOperands, |
| 25972 | /* 71379 */ // GIR_Coverage, 2182, |
| 25973 | /* 71379 */ GIR_EraseRootFromParent_Done, |
| 25974 | /* 71380 */ // Label 1432: @71380 |
| 25975 | /* 71380 */ GIM_Try, /*On fail goto*//*Label 1433*/ GIMT_Encode4(71443), // Rule ID 2183 // |
| 25976 | /* 71385 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 25977 | /* 71388 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlatb), |
| 25978 | /* 71393 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 25979 | /* 71396 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 25980 | /* 71399 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 25981 | /* 71402 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 25982 | /* 71405 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 25983 | /* 71409 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 25984 | /* 71413 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 25985 | /* 71417 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 25986 | /* 71421 */ // (intrinsic_wo_chain:{ *:[i32] } 3890:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (t2SMLATB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) |
| 25987 | /* 71421 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLATB), |
| 25988 | /* 71424 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 25989 | /* 71426 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 25990 | /* 71428 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 25991 | /* 71430 */ GIR_RootToRootCopy, /*OpIdx*/4, // acc |
| 25992 | /* 71432 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 25993 | /* 71435 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25994 | /* 71441 */ GIR_RootConstrainSelectedInstOperands, |
| 25995 | /* 71442 */ // GIR_Coverage, 2183, |
| 25996 | /* 71442 */ GIR_EraseRootFromParent_Done, |
| 25997 | /* 71443 */ // Label 1433: @71443 |
| 25998 | /* 71443 */ GIM_Try, /*On fail goto*//*Label 1434*/ GIMT_Encode4(71506), // Rule ID 2184 // |
| 25999 | /* 71448 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 26000 | /* 71451 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlatt), |
| 26001 | /* 71456 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 26002 | /* 71459 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 26003 | /* 71462 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 26004 | /* 71465 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26005 | /* 71468 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 26006 | /* 71472 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 26007 | /* 71476 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 26008 | /* 71480 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 26009 | /* 71484 */ // (intrinsic_wo_chain:{ *:[i32] } 3891:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (t2SMLATT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) |
| 26010 | /* 71484 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLATT), |
| 26011 | /* 71487 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 26012 | /* 71489 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 26013 | /* 71491 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 26014 | /* 71493 */ GIR_RootToRootCopy, /*OpIdx*/4, // acc |
| 26015 | /* 71495 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 26016 | /* 71498 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26017 | /* 71504 */ GIR_RootConstrainSelectedInstOperands, |
| 26018 | /* 71505 */ // GIR_Coverage, 2184, |
| 26019 | /* 71505 */ GIR_EraseRootFromParent_Done, |
| 26020 | /* 71506 */ // Label 1434: @71506 |
| 26021 | /* 71506 */ GIM_Try, /*On fail goto*//*Label 1435*/ GIMT_Encode4(71569), // Rule ID 2185 // |
| 26022 | /* 71511 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 26023 | /* 71514 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlawb), |
| 26024 | /* 71519 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 26025 | /* 71522 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 26026 | /* 71525 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 26027 | /* 71528 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26028 | /* 71531 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 26029 | /* 71535 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 26030 | /* 71539 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 26031 | /* 71543 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 26032 | /* 71547 */ // (intrinsic_wo_chain:{ *:[i32] } 3892:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (t2SMLAWB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) |
| 26033 | /* 71547 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLAWB), |
| 26034 | /* 71550 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 26035 | /* 71552 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 26036 | /* 71554 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 26037 | /* 71556 */ GIR_RootToRootCopy, /*OpIdx*/4, // acc |
| 26038 | /* 71558 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 26039 | /* 71561 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26040 | /* 71567 */ GIR_RootConstrainSelectedInstOperands, |
| 26041 | /* 71568 */ // GIR_Coverage, 2185, |
| 26042 | /* 71568 */ GIR_EraseRootFromParent_Done, |
| 26043 | /* 71569 */ // Label 1435: @71569 |
| 26044 | /* 71569 */ GIM_Try, /*On fail goto*//*Label 1436*/ GIMT_Encode4(71632), // Rule ID 2186 // |
| 26045 | /* 71574 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 26046 | /* 71577 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlawt), |
| 26047 | /* 71582 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 26048 | /* 71585 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 26049 | /* 71588 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 26050 | /* 71591 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26051 | /* 71594 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 26052 | /* 71598 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 26053 | /* 71602 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 26054 | /* 71606 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 26055 | /* 71610 */ // (intrinsic_wo_chain:{ *:[i32] } 3893:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (t2SMLAWT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) |
| 26056 | /* 71610 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLAWT), |
| 26057 | /* 71613 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 26058 | /* 71615 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 26059 | /* 71617 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 26060 | /* 71619 */ GIR_RootToRootCopy, /*OpIdx*/4, // acc |
| 26061 | /* 71621 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 26062 | /* 71624 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26063 | /* 71630 */ GIR_RootConstrainSelectedInstOperands, |
| 26064 | /* 71631 */ // GIR_Coverage, 2186, |
| 26065 | /* 71631 */ GIR_EraseRootFromParent_Done, |
| 26066 | /* 71632 */ // Label 1436: @71632 |
| 26067 | /* 71632 */ GIM_Try, /*On fail goto*//*Label 1437*/ GIMT_Encode4(71695), // Rule ID 2472 // |
| 26068 | /* 71637 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8_1a), |
| 26069 | /* 71640 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrdmlah), |
| 26070 | /* 71645 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 26071 | /* 71648 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 26072 | /* 71651 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 26073 | /* 71654 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16, |
| 26074 | /* 71657 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 26075 | /* 71661 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 26076 | /* 71665 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 26077 | /* 71669 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 26078 | /* 71673 */ // (intrinsic_wo_chain:{ *:[v4i16] } 3818:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VQRDMLAHv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 26079 | /* 71673 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRDMLAHv4i16), |
| 26080 | /* 71676 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 26081 | /* 71678 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 26082 | /* 71680 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 26083 | /* 71682 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 26084 | /* 71684 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 26085 | /* 71687 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26086 | /* 71693 */ GIR_RootConstrainSelectedInstOperands, |
| 26087 | /* 71694 */ // GIR_Coverage, 2472, |
| 26088 | /* 71694 */ GIR_EraseRootFromParent_Done, |
| 26089 | /* 71695 */ // Label 1437: @71695 |
| 26090 | /* 71695 */ GIM_Try, /*On fail goto*//*Label 1438*/ GIMT_Encode4(71758), // Rule ID 2473 // |
| 26091 | /* 71700 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8_1a), |
| 26092 | /* 71703 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrdmlah), |
| 26093 | /* 71708 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 26094 | /* 71711 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 26095 | /* 71714 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 26096 | /* 71717 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s32, |
| 26097 | /* 71720 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 26098 | /* 71724 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 26099 | /* 71728 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 26100 | /* 71732 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 26101 | /* 71736 */ // (intrinsic_wo_chain:{ *:[v2i32] } 3818:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VQRDMLAHv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 26102 | /* 71736 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRDMLAHv2i32), |
| 26103 | /* 71739 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 26104 | /* 71741 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 26105 | /* 71743 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 26106 | /* 71745 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 26107 | /* 71747 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 26108 | /* 71750 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26109 | /* 71756 */ GIR_RootConstrainSelectedInstOperands, |
| 26110 | /* 71757 */ // GIR_Coverage, 2473, |
| 26111 | /* 71757 */ GIR_EraseRootFromParent_Done, |
| 26112 | /* 71758 */ // Label 1438: @71758 |
| 26113 | /* 71758 */ GIM_Try, /*On fail goto*//*Label 1439*/ GIMT_Encode4(71821), // Rule ID 2474 // |
| 26114 | /* 71763 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8_1a), |
| 26115 | /* 71766 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrdmlah), |
| 26116 | /* 71771 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 26117 | /* 71774 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 26118 | /* 71777 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 26119 | /* 71780 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16, |
| 26120 | /* 71783 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 26121 | /* 71787 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 26122 | /* 71791 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 26123 | /* 71795 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 26124 | /* 71799 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3818:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VQRDMLAHv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 26125 | /* 71799 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRDMLAHv8i16), |
| 26126 | /* 71802 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 26127 | /* 71804 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 26128 | /* 71806 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 26129 | /* 71808 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 26130 | /* 71810 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 26131 | /* 71813 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26132 | /* 71819 */ GIR_RootConstrainSelectedInstOperands, |
| 26133 | /* 71820 */ // GIR_Coverage, 2474, |
| 26134 | /* 71820 */ GIR_EraseRootFromParent_Done, |
| 26135 | /* 71821 */ // Label 1439: @71821 |
| 26136 | /* 71821 */ GIM_Try, /*On fail goto*//*Label 1440*/ GIMT_Encode4(71884), // Rule ID 2475 // |
| 26137 | /* 71826 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8_1a), |
| 26138 | /* 71829 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrdmlah), |
| 26139 | /* 71834 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 26140 | /* 71837 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 26141 | /* 71840 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 26142 | /* 71843 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 26143 | /* 71846 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 26144 | /* 71850 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 26145 | /* 71854 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 26146 | /* 71858 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 26147 | /* 71862 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3818:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VQRDMLAHv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 26148 | /* 71862 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRDMLAHv4i32), |
| 26149 | /* 71865 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 26150 | /* 71867 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 26151 | /* 71869 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 26152 | /* 71871 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 26153 | /* 71873 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 26154 | /* 71876 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26155 | /* 71882 */ GIR_RootConstrainSelectedInstOperands, |
| 26156 | /* 71883 */ // GIR_Coverage, 2475, |
| 26157 | /* 71883 */ GIR_EraseRootFromParent_Done, |
| 26158 | /* 71884 */ // Label 1440: @71884 |
| 26159 | /* 71884 */ GIM_Try, /*On fail goto*//*Label 1441*/ GIMT_Encode4(71947), // Rule ID 2480 // |
| 26160 | /* 71889 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8_1a), |
| 26161 | /* 71892 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrdmlsh), |
| 26162 | /* 71897 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 26163 | /* 71900 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 26164 | /* 71903 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 26165 | /* 71906 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16, |
| 26166 | /* 71909 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 26167 | /* 71913 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 26168 | /* 71917 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 26169 | /* 71921 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 26170 | /* 71925 */ // (intrinsic_wo_chain:{ *:[v4i16] } 3819:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VQRDMLSHv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 26171 | /* 71925 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRDMLSHv4i16), |
| 26172 | /* 71928 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 26173 | /* 71930 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 26174 | /* 71932 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 26175 | /* 71934 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 26176 | /* 71936 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 26177 | /* 71939 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26178 | /* 71945 */ GIR_RootConstrainSelectedInstOperands, |
| 26179 | /* 71946 */ // GIR_Coverage, 2480, |
| 26180 | /* 71946 */ GIR_EraseRootFromParent_Done, |
| 26181 | /* 71947 */ // Label 1441: @71947 |
| 26182 | /* 71947 */ GIM_Try, /*On fail goto*//*Label 1442*/ GIMT_Encode4(72010), // Rule ID 2481 // |
| 26183 | /* 71952 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8_1a), |
| 26184 | /* 71955 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrdmlsh), |
| 26185 | /* 71960 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 26186 | /* 71963 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 26187 | /* 71966 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 26188 | /* 71969 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s32, |
| 26189 | /* 71972 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 26190 | /* 71976 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 26191 | /* 71980 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 26192 | /* 71984 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 26193 | /* 71988 */ // (intrinsic_wo_chain:{ *:[v2i32] } 3819:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VQRDMLSHv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 26194 | /* 71988 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRDMLSHv2i32), |
| 26195 | /* 71991 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 26196 | /* 71993 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 26197 | /* 71995 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 26198 | /* 71997 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 26199 | /* 71999 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 26200 | /* 72002 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26201 | /* 72008 */ GIR_RootConstrainSelectedInstOperands, |
| 26202 | /* 72009 */ // GIR_Coverage, 2481, |
| 26203 | /* 72009 */ GIR_EraseRootFromParent_Done, |
| 26204 | /* 72010 */ // Label 1442: @72010 |
| 26205 | /* 72010 */ GIM_Try, /*On fail goto*//*Label 1443*/ GIMT_Encode4(72073), // Rule ID 2482 // |
| 26206 | /* 72015 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8_1a), |
| 26207 | /* 72018 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrdmlsh), |
| 26208 | /* 72023 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 26209 | /* 72026 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 26210 | /* 72029 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 26211 | /* 72032 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16, |
| 26212 | /* 72035 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 26213 | /* 72039 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 26214 | /* 72043 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 26215 | /* 72047 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 26216 | /* 72051 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3819:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VQRDMLSHv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 26217 | /* 72051 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRDMLSHv8i16), |
| 26218 | /* 72054 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 26219 | /* 72056 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 26220 | /* 72058 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 26221 | /* 72060 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 26222 | /* 72062 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 26223 | /* 72065 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26224 | /* 72071 */ GIR_RootConstrainSelectedInstOperands, |
| 26225 | /* 72072 */ // GIR_Coverage, 2482, |
| 26226 | /* 72072 */ GIR_EraseRootFromParent_Done, |
| 26227 | /* 72073 */ // Label 1443: @72073 |
| 26228 | /* 72073 */ GIM_Try, /*On fail goto*//*Label 1444*/ GIMT_Encode4(72136), // Rule ID 2483 // |
| 26229 | /* 72078 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8_1a), |
| 26230 | /* 72081 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrdmlsh), |
| 26231 | /* 72086 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 26232 | /* 72089 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 26233 | /* 72092 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 26234 | /* 72095 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 26235 | /* 72098 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 26236 | /* 72102 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 26237 | /* 72106 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 26238 | /* 72110 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 26239 | /* 72114 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3819:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VQRDMLSHv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 26240 | /* 72114 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRDMLSHv4i32), |
| 26241 | /* 72117 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 26242 | /* 72119 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 26243 | /* 72121 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 26244 | /* 72123 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 26245 | /* 72125 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 26246 | /* 72128 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26247 | /* 72134 */ GIR_RootConstrainSelectedInstOperands, |
| 26248 | /* 72135 */ // GIR_Coverage, 2483, |
| 26249 | /* 72135 */ GIR_EraseRootFromParent_Done, |
| 26250 | /* 72136 */ // Label 1444: @72136 |
| 26251 | /* 72136 */ GIM_Try, /*On fail goto*//*Label 1445*/ GIMT_Encode4(72205), // Rule ID 4840 // |
| 26252 | /* 72141 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 26253 | /* 72144 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlah), |
| 26254 | /* 72149 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 26255 | /* 72152 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 26256 | /* 72155 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 26257 | /* 72158 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26258 | /* 72161 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26259 | /* 72165 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26260 | /* 72169 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26261 | /* 72173 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 26262 | /* 72177 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3670:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$v1, MQPR:{ *:[v16i8] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQDMLAH_qrs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$v1, MQPR:{ *:[v16i8] }:$v2, rGPR:{ *:[i32] }:$s) |
| 26263 | /* 72177 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLAH_qrs8), |
| 26264 | /* 72180 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26265 | /* 72182 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1 |
| 26266 | /* 72184 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2 |
| 26267 | /* 72186 */ GIR_RootToRootCopy, /*OpIdx*/4, // s |
| 26268 | /* 72188 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26269 | /* 72191 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26270 | /* 72197 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26271 | /* 72203 */ GIR_RootConstrainSelectedInstOperands, |
| 26272 | /* 72204 */ // GIR_Coverage, 4840, |
| 26273 | /* 72204 */ GIR_EraseRootFromParent_Done, |
| 26274 | /* 72205 */ // Label 1445: @72205 |
| 26275 | /* 72205 */ GIM_Try, /*On fail goto*//*Label 1446*/ GIMT_Encode4(72274), // Rule ID 4842 // |
| 26276 | /* 72210 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 26277 | /* 72213 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlah), |
| 26278 | /* 72218 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 26279 | /* 72221 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 26280 | /* 72224 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 26281 | /* 72227 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26282 | /* 72230 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26283 | /* 72234 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26284 | /* 72238 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26285 | /* 72242 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 26286 | /* 72246 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3670:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$v1, MQPR:{ *:[v8i16] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQDMLAH_qrs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$v1, MQPR:{ *:[v8i16] }:$v2, rGPR:{ *:[i32] }:$s) |
| 26287 | /* 72246 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLAH_qrs16), |
| 26288 | /* 72249 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26289 | /* 72251 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1 |
| 26290 | /* 72253 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2 |
| 26291 | /* 72255 */ GIR_RootToRootCopy, /*OpIdx*/4, // s |
| 26292 | /* 72257 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26293 | /* 72260 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26294 | /* 72266 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26295 | /* 72272 */ GIR_RootConstrainSelectedInstOperands, |
| 26296 | /* 72273 */ // GIR_Coverage, 4842, |
| 26297 | /* 72273 */ GIR_EraseRootFromParent_Done, |
| 26298 | /* 72274 */ // Label 1446: @72274 |
| 26299 | /* 72274 */ GIM_Try, /*On fail goto*//*Label 1447*/ GIMT_Encode4(72343), // Rule ID 4844 // |
| 26300 | /* 72279 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 26301 | /* 72282 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlah), |
| 26302 | /* 72287 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 26303 | /* 72290 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 26304 | /* 72293 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 26305 | /* 72296 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26306 | /* 72299 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26307 | /* 72303 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26308 | /* 72307 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26309 | /* 72311 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 26310 | /* 72315 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3670:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$v1, MQPR:{ *:[v4i32] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQDMLAH_qrs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$v1, MQPR:{ *:[v4i32] }:$v2, rGPR:{ *:[i32] }:$s) |
| 26311 | /* 72315 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLAH_qrs32), |
| 26312 | /* 72318 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26313 | /* 72320 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1 |
| 26314 | /* 72322 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2 |
| 26315 | /* 72324 */ GIR_RootToRootCopy, /*OpIdx*/4, // s |
| 26316 | /* 72326 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26317 | /* 72329 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26318 | /* 72335 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26319 | /* 72341 */ GIR_RootConstrainSelectedInstOperands, |
| 26320 | /* 72342 */ // GIR_Coverage, 4844, |
| 26321 | /* 72342 */ GIR_EraseRootFromParent_Done, |
| 26322 | /* 72343 */ // Label 1447: @72343 |
| 26323 | /* 72343 */ GIM_Try, /*On fail goto*//*Label 1448*/ GIMT_Encode4(72412), // Rule ID 4846 // |
| 26324 | /* 72348 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 26325 | /* 72351 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqrdmlah), |
| 26326 | /* 72356 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 26327 | /* 72359 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 26328 | /* 72362 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 26329 | /* 72365 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26330 | /* 72368 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26331 | /* 72372 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26332 | /* 72376 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26333 | /* 72380 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 26334 | /* 72384 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3679:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$v1, MQPR:{ *:[v16i8] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQRDMLAH_qrs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$v1, MQPR:{ *:[v16i8] }:$v2, rGPR:{ *:[i32] }:$s) |
| 26335 | /* 72384 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLAH_qrs8), |
| 26336 | /* 72387 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26337 | /* 72389 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1 |
| 26338 | /* 72391 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2 |
| 26339 | /* 72393 */ GIR_RootToRootCopy, /*OpIdx*/4, // s |
| 26340 | /* 72395 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26341 | /* 72398 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26342 | /* 72404 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26343 | /* 72410 */ GIR_RootConstrainSelectedInstOperands, |
| 26344 | /* 72411 */ // GIR_Coverage, 4846, |
| 26345 | /* 72411 */ GIR_EraseRootFromParent_Done, |
| 26346 | /* 72412 */ // Label 1448: @72412 |
| 26347 | /* 72412 */ GIM_Try, /*On fail goto*//*Label 1449*/ GIMT_Encode4(72481), // Rule ID 4848 // |
| 26348 | /* 72417 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 26349 | /* 72420 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqrdmlah), |
| 26350 | /* 72425 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 26351 | /* 72428 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 26352 | /* 72431 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 26353 | /* 72434 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26354 | /* 72437 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26355 | /* 72441 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26356 | /* 72445 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26357 | /* 72449 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 26358 | /* 72453 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3679:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$v1, MQPR:{ *:[v8i16] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQRDMLAH_qrs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$v1, MQPR:{ *:[v8i16] }:$v2, rGPR:{ *:[i32] }:$s) |
| 26359 | /* 72453 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLAH_qrs16), |
| 26360 | /* 72456 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26361 | /* 72458 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1 |
| 26362 | /* 72460 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2 |
| 26363 | /* 72462 */ GIR_RootToRootCopy, /*OpIdx*/4, // s |
| 26364 | /* 72464 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26365 | /* 72467 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26366 | /* 72473 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26367 | /* 72479 */ GIR_RootConstrainSelectedInstOperands, |
| 26368 | /* 72480 */ // GIR_Coverage, 4848, |
| 26369 | /* 72480 */ GIR_EraseRootFromParent_Done, |
| 26370 | /* 72481 */ // Label 1449: @72481 |
| 26371 | /* 72481 */ GIM_Try, /*On fail goto*//*Label 1450*/ GIMT_Encode4(72550), // Rule ID 4850 // |
| 26372 | /* 72486 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 26373 | /* 72489 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqrdmlah), |
| 26374 | /* 72494 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 26375 | /* 72497 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 26376 | /* 72500 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 26377 | /* 72503 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26378 | /* 72506 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26379 | /* 72510 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26380 | /* 72514 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26381 | /* 72518 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 26382 | /* 72522 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3679:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$v1, MQPR:{ *:[v4i32] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQRDMLAH_qrs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$v1, MQPR:{ *:[v4i32] }:$v2, rGPR:{ *:[i32] }:$s) |
| 26383 | /* 72522 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLAH_qrs32), |
| 26384 | /* 72525 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26385 | /* 72527 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1 |
| 26386 | /* 72529 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2 |
| 26387 | /* 72531 */ GIR_RootToRootCopy, /*OpIdx*/4, // s |
| 26388 | /* 72533 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26389 | /* 72536 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26390 | /* 72542 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26391 | /* 72548 */ GIR_RootConstrainSelectedInstOperands, |
| 26392 | /* 72549 */ // GIR_Coverage, 4850, |
| 26393 | /* 72549 */ GIR_EraseRootFromParent_Done, |
| 26394 | /* 72550 */ // Label 1450: @72550 |
| 26395 | /* 72550 */ GIM_Try, /*On fail goto*//*Label 1451*/ GIMT_Encode4(72619), // Rule ID 4852 // |
| 26396 | /* 72555 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 26397 | /* 72558 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlash), |
| 26398 | /* 72563 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 26399 | /* 72566 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 26400 | /* 72569 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 26401 | /* 72572 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26402 | /* 72575 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26403 | /* 72579 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26404 | /* 72583 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26405 | /* 72587 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 26406 | /* 72591 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3672:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$v1, MQPR:{ *:[v16i8] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQDMLASH_qrs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$v1, MQPR:{ *:[v16i8] }:$v2, rGPR:{ *:[i32] }:$s) |
| 26407 | /* 72591 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLASH_qrs8), |
| 26408 | /* 72594 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26409 | /* 72596 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1 |
| 26410 | /* 72598 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2 |
| 26411 | /* 72600 */ GIR_RootToRootCopy, /*OpIdx*/4, // s |
| 26412 | /* 72602 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26413 | /* 72605 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26414 | /* 72611 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26415 | /* 72617 */ GIR_RootConstrainSelectedInstOperands, |
| 26416 | /* 72618 */ // GIR_Coverage, 4852, |
| 26417 | /* 72618 */ GIR_EraseRootFromParent_Done, |
| 26418 | /* 72619 */ // Label 1451: @72619 |
| 26419 | /* 72619 */ GIM_Try, /*On fail goto*//*Label 1452*/ GIMT_Encode4(72688), // Rule ID 4854 // |
| 26420 | /* 72624 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 26421 | /* 72627 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlash), |
| 26422 | /* 72632 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 26423 | /* 72635 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 26424 | /* 72638 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 26425 | /* 72641 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26426 | /* 72644 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26427 | /* 72648 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26428 | /* 72652 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26429 | /* 72656 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 26430 | /* 72660 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3672:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$v1, MQPR:{ *:[v8i16] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQDMLASH_qrs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$v1, MQPR:{ *:[v8i16] }:$v2, rGPR:{ *:[i32] }:$s) |
| 26431 | /* 72660 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLASH_qrs16), |
| 26432 | /* 72663 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26433 | /* 72665 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1 |
| 26434 | /* 72667 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2 |
| 26435 | /* 72669 */ GIR_RootToRootCopy, /*OpIdx*/4, // s |
| 26436 | /* 72671 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26437 | /* 72674 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26438 | /* 72680 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26439 | /* 72686 */ GIR_RootConstrainSelectedInstOperands, |
| 26440 | /* 72687 */ // GIR_Coverage, 4854, |
| 26441 | /* 72687 */ GIR_EraseRootFromParent_Done, |
| 26442 | /* 72688 */ // Label 1452: @72688 |
| 26443 | /* 72688 */ GIM_Try, /*On fail goto*//*Label 1453*/ GIMT_Encode4(72757), // Rule ID 4856 // |
| 26444 | /* 72693 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 26445 | /* 72696 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlash), |
| 26446 | /* 72701 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 26447 | /* 72704 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 26448 | /* 72707 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 26449 | /* 72710 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26450 | /* 72713 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26451 | /* 72717 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26452 | /* 72721 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26453 | /* 72725 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 26454 | /* 72729 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3672:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$v1, MQPR:{ *:[v4i32] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQDMLASH_qrs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$v1, MQPR:{ *:[v4i32] }:$v2, rGPR:{ *:[i32] }:$s) |
| 26455 | /* 72729 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLASH_qrs32), |
| 26456 | /* 72732 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26457 | /* 72734 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1 |
| 26458 | /* 72736 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2 |
| 26459 | /* 72738 */ GIR_RootToRootCopy, /*OpIdx*/4, // s |
| 26460 | /* 72740 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26461 | /* 72743 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26462 | /* 72749 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26463 | /* 72755 */ GIR_RootConstrainSelectedInstOperands, |
| 26464 | /* 72756 */ // GIR_Coverage, 4856, |
| 26465 | /* 72756 */ GIR_EraseRootFromParent_Done, |
| 26466 | /* 72757 */ // Label 1453: @72757 |
| 26467 | /* 72757 */ GIM_Try, /*On fail goto*//*Label 1454*/ GIMT_Encode4(72826), // Rule ID 4858 // |
| 26468 | /* 72762 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 26469 | /* 72765 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqrdmlash), |
| 26470 | /* 72770 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 26471 | /* 72773 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 26472 | /* 72776 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 26473 | /* 72779 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26474 | /* 72782 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26475 | /* 72786 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26476 | /* 72790 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26477 | /* 72794 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 26478 | /* 72798 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3681:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$v1, MQPR:{ *:[v16i8] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQRDMLASH_qrs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$v1, MQPR:{ *:[v16i8] }:$v2, rGPR:{ *:[i32] }:$s) |
| 26479 | /* 72798 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLASH_qrs8), |
| 26480 | /* 72801 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26481 | /* 72803 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1 |
| 26482 | /* 72805 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2 |
| 26483 | /* 72807 */ GIR_RootToRootCopy, /*OpIdx*/4, // s |
| 26484 | /* 72809 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26485 | /* 72812 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26486 | /* 72818 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26487 | /* 72824 */ GIR_RootConstrainSelectedInstOperands, |
| 26488 | /* 72825 */ // GIR_Coverage, 4858, |
| 26489 | /* 72825 */ GIR_EraseRootFromParent_Done, |
| 26490 | /* 72826 */ // Label 1454: @72826 |
| 26491 | /* 72826 */ GIM_Try, /*On fail goto*//*Label 1455*/ GIMT_Encode4(72895), // Rule ID 4860 // |
| 26492 | /* 72831 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 26493 | /* 72834 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqrdmlash), |
| 26494 | /* 72839 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 26495 | /* 72842 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 26496 | /* 72845 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 26497 | /* 72848 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26498 | /* 72851 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26499 | /* 72855 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26500 | /* 72859 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26501 | /* 72863 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 26502 | /* 72867 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3681:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$v1, MQPR:{ *:[v8i16] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQRDMLASH_qrs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$v1, MQPR:{ *:[v8i16] }:$v2, rGPR:{ *:[i32] }:$s) |
| 26503 | /* 72867 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLASH_qrs16), |
| 26504 | /* 72870 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26505 | /* 72872 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1 |
| 26506 | /* 72874 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2 |
| 26507 | /* 72876 */ GIR_RootToRootCopy, /*OpIdx*/4, // s |
| 26508 | /* 72878 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26509 | /* 72881 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26510 | /* 72887 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26511 | /* 72893 */ GIR_RootConstrainSelectedInstOperands, |
| 26512 | /* 72894 */ // GIR_Coverage, 4860, |
| 26513 | /* 72894 */ GIR_EraseRootFromParent_Done, |
| 26514 | /* 72895 */ // Label 1455: @72895 |
| 26515 | /* 72895 */ GIM_Try, /*On fail goto*//*Label 1456*/ GIMT_Encode4(72964), // Rule ID 4862 // |
| 26516 | /* 72900 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 26517 | /* 72903 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqrdmlash), |
| 26518 | /* 72908 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 26519 | /* 72911 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 26520 | /* 72914 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 26521 | /* 72917 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26522 | /* 72920 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26523 | /* 72924 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26524 | /* 72928 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26525 | /* 72932 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 26526 | /* 72936 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3681:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$v1, MQPR:{ *:[v4i32] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQRDMLASH_qrs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$v1, MQPR:{ *:[v4i32] }:$v2, rGPR:{ *:[i32] }:$s) |
| 26527 | /* 72936 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLASH_qrs32), |
| 26528 | /* 72939 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26529 | /* 72941 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1 |
| 26530 | /* 72943 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2 |
| 26531 | /* 72945 */ GIR_RootToRootCopy, /*OpIdx*/4, // s |
| 26532 | /* 72947 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26533 | /* 72950 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26534 | /* 72956 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26535 | /* 72962 */ GIR_RootConstrainSelectedInstOperands, |
| 26536 | /* 72963 */ // GIR_Coverage, 4862, |
| 26537 | /* 72963 */ GIR_EraseRootFromParent_Done, |
| 26538 | /* 72964 */ // Label 1456: @72964 |
| 26539 | /* 72964 */ GIM_Try, /*On fail goto*//*Label 1457*/ GIMT_Encode4(73059), // Rule ID 2694 // |
| 26540 | /* 72969 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 26541 | /* 72972 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sha1c), |
| 26542 | /* 72977 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 26543 | /* 72980 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 26544 | /* 72983 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 26545 | /* 72986 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 26546 | /* 72989 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 26547 | /* 72993 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3735:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$hash_abcd, i32:{ *:[i32] }:$hash_e, v4i32:{ *:[v4i32] }:$wk) => (SHA1C:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$hash_abcd, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i64] }, (COPY_TO_REGCLASS:{ *:[f32] } i32:{ *:[i32] }:$hash_e, SPR:{ *:[i32] }), ssub_0:{ *:[i32] }), v4i32:{ *:[v4i32] }:$wk) |
| 26548 | /* 72993 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 26549 | /* 72996 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 26550 | /* 73000 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26551 | /* 73005 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // hash_e |
| 26552 | /* 73009 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 26553 | /* 73014 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, |
| 26554 | /* 73017 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG), |
| 26555 | /* 73021 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26556 | /* 73026 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 26557 | /* 73029 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 26558 | /* 73032 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/17, |
| 26559 | /* 73035 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPair_with_ssub_0RegClassID), |
| 26560 | /* 73040 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 26561 | /* 73045 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHA1C), |
| 26562 | /* 73048 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 26563 | /* 73050 */ GIR_RootToRootCopy, /*OpIdx*/2, // hash_abcd |
| 26564 | /* 73052 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26565 | /* 73055 */ GIR_RootToRootCopy, /*OpIdx*/4, // wk |
| 26566 | /* 73057 */ GIR_RootConstrainSelectedInstOperands, |
| 26567 | /* 73058 */ // GIR_Coverage, 2694, |
| 26568 | /* 73058 */ GIR_EraseRootFromParent_Done, |
| 26569 | /* 73059 */ // Label 1457: @73059 |
| 26570 | /* 73059 */ GIM_Try, /*On fail goto*//*Label 1458*/ GIMT_Encode4(73154), // Rule ID 2695 // |
| 26571 | /* 73064 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 26572 | /* 73067 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sha1m), |
| 26573 | /* 73072 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 26574 | /* 73075 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 26575 | /* 73078 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 26576 | /* 73081 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 26577 | /* 73084 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 26578 | /* 73088 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3737:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$hash_abcd, i32:{ *:[i32] }:$hash_e, v4i32:{ *:[v4i32] }:$wk) => (SHA1M:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$hash_abcd, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i64] }, (COPY_TO_REGCLASS:{ *:[f32] } i32:{ *:[i32] }:$hash_e, SPR:{ *:[i32] }), ssub_0:{ *:[i32] }), v4i32:{ *:[v4i32] }:$wk) |
| 26579 | /* 73088 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 26580 | /* 73091 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 26581 | /* 73095 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26582 | /* 73100 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // hash_e |
| 26583 | /* 73104 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 26584 | /* 73109 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, |
| 26585 | /* 73112 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG), |
| 26586 | /* 73116 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26587 | /* 73121 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 26588 | /* 73124 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 26589 | /* 73127 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/17, |
| 26590 | /* 73130 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPair_with_ssub_0RegClassID), |
| 26591 | /* 73135 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 26592 | /* 73140 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHA1M), |
| 26593 | /* 73143 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 26594 | /* 73145 */ GIR_RootToRootCopy, /*OpIdx*/2, // hash_abcd |
| 26595 | /* 73147 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26596 | /* 73150 */ GIR_RootToRootCopy, /*OpIdx*/4, // wk |
| 26597 | /* 73152 */ GIR_RootConstrainSelectedInstOperands, |
| 26598 | /* 73153 */ // GIR_Coverage, 2695, |
| 26599 | /* 73153 */ GIR_EraseRootFromParent_Done, |
| 26600 | /* 73154 */ // Label 1458: @73154 |
| 26601 | /* 73154 */ GIM_Try, /*On fail goto*//*Label 1459*/ GIMT_Encode4(73249), // Rule ID 2696 // |
| 26602 | /* 73159 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 26603 | /* 73162 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sha1p), |
| 26604 | /* 73167 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 26605 | /* 73170 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 26606 | /* 73173 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 26607 | /* 73176 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 26608 | /* 73179 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 26609 | /* 73183 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3738:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$hash_abcd, i32:{ *:[i32] }:$hash_e, v4i32:{ *:[v4i32] }:$wk) => (SHA1P:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$hash_abcd, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i64] }, (COPY_TO_REGCLASS:{ *:[f32] } i32:{ *:[i32] }:$hash_e, SPR:{ *:[i32] }), ssub_0:{ *:[i32] }), v4i32:{ *:[v4i32] }:$wk) |
| 26610 | /* 73183 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 26611 | /* 73186 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 26612 | /* 73190 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26613 | /* 73195 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // hash_e |
| 26614 | /* 73199 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 26615 | /* 73204 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, |
| 26616 | /* 73207 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG), |
| 26617 | /* 73211 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26618 | /* 73216 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 26619 | /* 73219 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 26620 | /* 73222 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/17, |
| 26621 | /* 73225 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPair_with_ssub_0RegClassID), |
| 26622 | /* 73230 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 26623 | /* 73235 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHA1P), |
| 26624 | /* 73238 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 26625 | /* 73240 */ GIR_RootToRootCopy, /*OpIdx*/2, // hash_abcd |
| 26626 | /* 73242 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26627 | /* 73245 */ GIR_RootToRootCopy, /*OpIdx*/4, // wk |
| 26628 | /* 73247 */ GIR_RootConstrainSelectedInstOperands, |
| 26629 | /* 73248 */ // GIR_Coverage, 2696, |
| 26630 | /* 73248 */ GIR_EraseRootFromParent_Done, |
| 26631 | /* 73249 */ // Label 1459: @73249 |
| 26632 | /* 73249 */ GIM_Reject, |
| 26633 | /* 73250 */ // Label 1312: @73250 |
| 26634 | /* 73250 */ GIM_Try, /*On fail goto*//*Label 1460*/ GIMT_Encode4(76636), |
| 26635 | /* 73255 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/6, |
| 26636 | /* 73258 */ GIM_Try, /*On fail goto*//*Label 1461*/ GIMT_Encode4(73342), // Rule ID 3727 // |
| 26637 | /* 73263 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshll_imm), |
| 26638 | /* 73268 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 26639 | /* 73271 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 26640 | /* 73274 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 26641 | /* 73277 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26642 | /* 73280 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 26643 | /* 73283 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26644 | /* 73287 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26645 | /* 73291 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 8, |
| 26646 | /* 73295 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 26647 | /* 73299 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 26648 | /* 73303 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3710:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, 8:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHLL_lws8bh:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$src) |
| 26649 | /* 73303 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26650 | /* 73306 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26651 | /* 73310 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26652 | /* 73315 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHLL_lws8bh), |
| 26653 | /* 73318 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26654 | /* 73320 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 26655 | /* 73322 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26656 | /* 73325 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26657 | /* 73331 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26658 | /* 73337 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26659 | /* 73340 */ GIR_RootConstrainSelectedInstOperands, |
| 26660 | /* 73341 */ // GIR_Coverage, 3727, |
| 26661 | /* 73341 */ GIR_EraseRootFromParent_Done, |
| 26662 | /* 73342 */ // Label 1461: @73342 |
| 26663 | /* 73342 */ GIM_Try, /*On fail goto*//*Label 1462*/ GIMT_Encode4(73426), // Rule ID 3731 // |
| 26664 | /* 73347 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshll_imm), |
| 26665 | /* 73352 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 26666 | /* 73355 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 26667 | /* 73358 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 26668 | /* 73361 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26669 | /* 73364 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 26670 | /* 73367 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26671 | /* 73371 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26672 | /* 73375 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 8, |
| 26673 | /* 73379 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 26674 | /* 73383 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 26675 | /* 73387 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3710:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, 8:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHLL_lws8th:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$src) |
| 26676 | /* 73387 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26677 | /* 73390 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26678 | /* 73394 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26679 | /* 73399 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHLL_lws8th), |
| 26680 | /* 73402 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26681 | /* 73404 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 26682 | /* 73406 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26683 | /* 73409 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26684 | /* 73415 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26685 | /* 73421 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26686 | /* 73424 */ GIR_RootConstrainSelectedInstOperands, |
| 26687 | /* 73425 */ // GIR_Coverage, 3731, |
| 26688 | /* 73425 */ GIR_EraseRootFromParent_Done, |
| 26689 | /* 73426 */ // Label 1462: @73426 |
| 26690 | /* 73426 */ GIM_Try, /*On fail goto*//*Label 1463*/ GIMT_Encode4(73510), // Rule ID 3735 // |
| 26691 | /* 73431 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshll_imm), |
| 26692 | /* 73436 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 26693 | /* 73439 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 26694 | /* 73442 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 26695 | /* 73445 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26696 | /* 73448 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 26697 | /* 73451 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26698 | /* 73455 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26699 | /* 73459 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 16, |
| 26700 | /* 73463 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 26701 | /* 73467 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 26702 | /* 73471 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3710:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, 16:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHLL_lws16bh:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$src) |
| 26703 | /* 73471 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26704 | /* 73474 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26705 | /* 73478 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26706 | /* 73483 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHLL_lws16bh), |
| 26707 | /* 73486 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26708 | /* 73488 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 26709 | /* 73490 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26710 | /* 73493 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26711 | /* 73499 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26712 | /* 73505 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26713 | /* 73508 */ GIR_RootConstrainSelectedInstOperands, |
| 26714 | /* 73509 */ // GIR_Coverage, 3735, |
| 26715 | /* 73509 */ GIR_EraseRootFromParent_Done, |
| 26716 | /* 73510 */ // Label 1463: @73510 |
| 26717 | /* 73510 */ GIM_Try, /*On fail goto*//*Label 1464*/ GIMT_Encode4(73594), // Rule ID 3739 // |
| 26718 | /* 73515 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshll_imm), |
| 26719 | /* 73520 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 26720 | /* 73523 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 26721 | /* 73526 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 26722 | /* 73529 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26723 | /* 73532 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 26724 | /* 73535 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26725 | /* 73539 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26726 | /* 73543 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 16, |
| 26727 | /* 73547 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 26728 | /* 73551 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 26729 | /* 73555 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3710:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, 16:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHLL_lws16th:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$src) |
| 26730 | /* 73555 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26731 | /* 73558 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26732 | /* 73562 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26733 | /* 73567 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHLL_lws16th), |
| 26734 | /* 73570 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26735 | /* 73572 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 26736 | /* 73574 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26737 | /* 73577 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26738 | /* 73583 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26739 | /* 73589 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26740 | /* 73592 */ GIR_RootConstrainSelectedInstOperands, |
| 26741 | /* 73593 */ // GIR_Coverage, 3739, |
| 26742 | /* 73593 */ GIR_EraseRootFromParent_Done, |
| 26743 | /* 73594 */ // Label 1464: @73594 |
| 26744 | /* 73594 */ GIM_Try, /*On fail goto*//*Label 1465*/ GIMT_Encode4(73678), // Rule ID 3743 // |
| 26745 | /* 73599 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshll_imm), |
| 26746 | /* 73604 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 26747 | /* 73607 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 26748 | /* 73610 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 26749 | /* 73613 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26750 | /* 73616 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 26751 | /* 73619 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26752 | /* 73623 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26753 | /* 73627 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 8, |
| 26754 | /* 73631 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 26755 | /* 73635 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 26756 | /* 73639 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3710:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, 8:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHLL_lwu8bh:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$src) |
| 26757 | /* 73639 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26758 | /* 73642 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26759 | /* 73646 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26760 | /* 73651 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHLL_lwu8bh), |
| 26761 | /* 73654 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26762 | /* 73656 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 26763 | /* 73658 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26764 | /* 73661 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26765 | /* 73667 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26766 | /* 73673 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26767 | /* 73676 */ GIR_RootConstrainSelectedInstOperands, |
| 26768 | /* 73677 */ // GIR_Coverage, 3743, |
| 26769 | /* 73677 */ GIR_EraseRootFromParent_Done, |
| 26770 | /* 73678 */ // Label 1465: @73678 |
| 26771 | /* 73678 */ GIM_Try, /*On fail goto*//*Label 1466*/ GIMT_Encode4(73762), // Rule ID 3747 // |
| 26772 | /* 73683 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshll_imm), |
| 26773 | /* 73688 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 26774 | /* 73691 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 26775 | /* 73694 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 26776 | /* 73697 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26777 | /* 73700 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 26778 | /* 73703 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26779 | /* 73707 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26780 | /* 73711 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 8, |
| 26781 | /* 73715 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 26782 | /* 73719 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 26783 | /* 73723 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3710:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, 8:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHLL_lwu8th:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$src) |
| 26784 | /* 73723 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26785 | /* 73726 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26786 | /* 73730 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26787 | /* 73735 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHLL_lwu8th), |
| 26788 | /* 73738 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26789 | /* 73740 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 26790 | /* 73742 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26791 | /* 73745 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26792 | /* 73751 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26793 | /* 73757 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26794 | /* 73760 */ GIR_RootConstrainSelectedInstOperands, |
| 26795 | /* 73761 */ // GIR_Coverage, 3747, |
| 26796 | /* 73761 */ GIR_EraseRootFromParent_Done, |
| 26797 | /* 73762 */ // Label 1466: @73762 |
| 26798 | /* 73762 */ GIM_Try, /*On fail goto*//*Label 1467*/ GIMT_Encode4(73846), // Rule ID 3751 // |
| 26799 | /* 73767 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshll_imm), |
| 26800 | /* 73772 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 26801 | /* 73775 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 26802 | /* 73778 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 26803 | /* 73781 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26804 | /* 73784 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 26805 | /* 73787 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26806 | /* 73791 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26807 | /* 73795 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 16, |
| 26808 | /* 73799 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 26809 | /* 73803 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 26810 | /* 73807 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3710:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, 16:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHLL_lwu16bh:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$src) |
| 26811 | /* 73807 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26812 | /* 73810 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26813 | /* 73814 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26814 | /* 73819 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHLL_lwu16bh), |
| 26815 | /* 73822 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26816 | /* 73824 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 26817 | /* 73826 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26818 | /* 73829 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26819 | /* 73835 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26820 | /* 73841 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26821 | /* 73844 */ GIR_RootConstrainSelectedInstOperands, |
| 26822 | /* 73845 */ // GIR_Coverage, 3751, |
| 26823 | /* 73845 */ GIR_EraseRootFromParent_Done, |
| 26824 | /* 73846 */ // Label 1467: @73846 |
| 26825 | /* 73846 */ GIM_Try, /*On fail goto*//*Label 1468*/ GIMT_Encode4(73930), // Rule ID 3755 // |
| 26826 | /* 73851 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshll_imm), |
| 26827 | /* 73856 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 26828 | /* 73859 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 26829 | /* 73862 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 26830 | /* 73865 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26831 | /* 73868 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 26832 | /* 73871 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26833 | /* 73875 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26834 | /* 73879 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 16, |
| 26835 | /* 73883 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 26836 | /* 73887 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 26837 | /* 73891 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3710:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, 16:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHLL_lwu16th:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$src) |
| 26838 | /* 73891 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26839 | /* 73894 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26840 | /* 73898 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26841 | /* 73903 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHLL_lwu16th), |
| 26842 | /* 73906 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26843 | /* 73908 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 26844 | /* 73910 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26845 | /* 73913 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26846 | /* 73919 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26847 | /* 73925 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26848 | /* 73928 */ GIR_RootConstrainSelectedInstOperands, |
| 26849 | /* 73929 */ // GIR_Coverage, 3755, |
| 26850 | /* 73929 */ GIR_EraseRootFromParent_Done, |
| 26851 | /* 73930 */ // Label 1468: @73930 |
| 26852 | /* 73930 */ GIM_Try, /*On fail goto*//*Label 1469*/ GIMT_Encode4(74019), // Rule ID 4387 // |
| 26853 | /* 73935 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 26854 | /* 73938 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmull), |
| 26855 | /* 73943 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 26856 | /* 73946 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 26857 | /* 73949 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 26858 | /* 73952 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26859 | /* 73955 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 26860 | /* 73958 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26861 | /* 73962 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26862 | /* 73966 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26863 | /* 73970 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 26864 | /* 73974 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 26865 | /* 73978 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3666:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VMULLBs8:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 26866 | /* 73978 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26867 | /* 73981 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26868 | /* 73985 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26869 | /* 73990 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLBs8), |
| 26870 | /* 73993 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26871 | /* 73995 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 26872 | /* 73997 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 26873 | /* 73999 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26874 | /* 74002 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26875 | /* 74008 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26876 | /* 74014 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26877 | /* 74017 */ GIR_RootConstrainSelectedInstOperands, |
| 26878 | /* 74018 */ // GIR_Coverage, 4387, |
| 26879 | /* 74018 */ GIR_EraseRootFromParent_Done, |
| 26880 | /* 74019 */ // Label 1469: @74019 |
| 26881 | /* 74019 */ GIM_Try, /*On fail goto*//*Label 1470*/ GIMT_Encode4(74108), // Rule ID 4389 // |
| 26882 | /* 74024 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 26883 | /* 74027 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmull), |
| 26884 | /* 74032 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 26885 | /* 74035 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 26886 | /* 74038 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 26887 | /* 74041 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26888 | /* 74044 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 26889 | /* 74047 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26890 | /* 74051 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26891 | /* 74055 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26892 | /* 74059 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 26893 | /* 74063 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 26894 | /* 74067 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3666:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VMULLTs8:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 26895 | /* 74067 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26896 | /* 74070 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26897 | /* 74074 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26898 | /* 74079 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLTs8), |
| 26899 | /* 74082 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26900 | /* 74084 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 26901 | /* 74086 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 26902 | /* 74088 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26903 | /* 74091 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26904 | /* 74097 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26905 | /* 74103 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26906 | /* 74106 */ GIR_RootConstrainSelectedInstOperands, |
| 26907 | /* 74107 */ // GIR_Coverage, 4389, |
| 26908 | /* 74107 */ GIR_EraseRootFromParent_Done, |
| 26909 | /* 74108 */ // Label 1470: @74108 |
| 26910 | /* 74108 */ GIM_Try, /*On fail goto*//*Label 1471*/ GIMT_Encode4(74197), // Rule ID 4391 // |
| 26911 | /* 74113 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 26912 | /* 74116 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmull), |
| 26913 | /* 74121 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 26914 | /* 74124 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 26915 | /* 74127 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 26916 | /* 74130 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26917 | /* 74133 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 26918 | /* 74136 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26919 | /* 74140 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26920 | /* 74144 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26921 | /* 74148 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 26922 | /* 74152 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 26923 | /* 74156 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3666:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VMULLBs16:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 26924 | /* 74156 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26925 | /* 74159 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26926 | /* 74163 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26927 | /* 74168 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLBs16), |
| 26928 | /* 74171 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26929 | /* 74173 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 26930 | /* 74175 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 26931 | /* 74177 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26932 | /* 74180 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26933 | /* 74186 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26934 | /* 74192 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26935 | /* 74195 */ GIR_RootConstrainSelectedInstOperands, |
| 26936 | /* 74196 */ // GIR_Coverage, 4391, |
| 26937 | /* 74196 */ GIR_EraseRootFromParent_Done, |
| 26938 | /* 74197 */ // Label 1471: @74197 |
| 26939 | /* 74197 */ GIM_Try, /*On fail goto*//*Label 1472*/ GIMT_Encode4(74286), // Rule ID 4393 // |
| 26940 | /* 74202 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 26941 | /* 74205 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmull), |
| 26942 | /* 74210 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 26943 | /* 74213 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 26944 | /* 74216 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 26945 | /* 74219 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26946 | /* 74222 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 26947 | /* 74225 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26948 | /* 74229 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26949 | /* 74233 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26950 | /* 74237 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 26951 | /* 74241 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 26952 | /* 74245 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3666:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VMULLTs16:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 26953 | /* 74245 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26954 | /* 74248 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26955 | /* 74252 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26956 | /* 74257 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLTs16), |
| 26957 | /* 74260 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26958 | /* 74262 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 26959 | /* 74264 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 26960 | /* 74266 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26961 | /* 74269 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26962 | /* 74275 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26963 | /* 74281 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26964 | /* 74284 */ GIR_RootConstrainSelectedInstOperands, |
| 26965 | /* 74285 */ // GIR_Coverage, 4393, |
| 26966 | /* 74285 */ GIR_EraseRootFromParent_Done, |
| 26967 | /* 74286 */ // Label 1472: @74286 |
| 26968 | /* 74286 */ GIM_Try, /*On fail goto*//*Label 1473*/ GIMT_Encode4(74375), // Rule ID 4395 // |
| 26969 | /* 74291 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 26970 | /* 74294 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmull), |
| 26971 | /* 74299 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 26972 | /* 74302 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 26973 | /* 74305 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 26974 | /* 74308 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26975 | /* 74311 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 26976 | /* 74314 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26977 | /* 74318 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26978 | /* 74322 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26979 | /* 74326 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 26980 | /* 74330 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 26981 | /* 74334 */ // (intrinsic_wo_chain:{ *:[v2i64] } 3666:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VMULLBs32:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 26982 | /* 74334 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26983 | /* 74337 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26984 | /* 74341 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26985 | /* 74346 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLBs32), |
| 26986 | /* 74349 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26987 | /* 74351 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 26988 | /* 74353 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 26989 | /* 74355 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26990 | /* 74358 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26991 | /* 74364 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26992 | /* 74370 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26993 | /* 74373 */ GIR_RootConstrainSelectedInstOperands, |
| 26994 | /* 74374 */ // GIR_Coverage, 4395, |
| 26995 | /* 74374 */ GIR_EraseRootFromParent_Done, |
| 26996 | /* 74375 */ // Label 1473: @74375 |
| 26997 | /* 74375 */ GIM_Try, /*On fail goto*//*Label 1474*/ GIMT_Encode4(74464), // Rule ID 4397 // |
| 26998 | /* 74380 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 26999 | /* 74383 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmull), |
| 27000 | /* 74388 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 27001 | /* 74391 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 27002 | /* 74394 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 27003 | /* 74397 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 27004 | /* 74400 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 27005 | /* 74403 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27006 | /* 74407 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27007 | /* 74411 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27008 | /* 74415 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 27009 | /* 74419 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 27010 | /* 74423 */ // (intrinsic_wo_chain:{ *:[v2i64] } 3666:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VMULLTs32:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 27011 | /* 74423 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 27012 | /* 74426 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 27013 | /* 74430 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27014 | /* 74435 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLTs32), |
| 27015 | /* 74438 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 27016 | /* 74440 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 27017 | /* 74442 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 27018 | /* 74444 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27019 | /* 74447 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27020 | /* 74453 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27021 | /* 74459 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 27022 | /* 74462 */ GIR_RootConstrainSelectedInstOperands, |
| 27023 | /* 74463 */ // GIR_Coverage, 4397, |
| 27024 | /* 74463 */ GIR_EraseRootFromParent_Done, |
| 27025 | /* 74464 */ // Label 1474: @74464 |
| 27026 | /* 74464 */ GIM_Try, /*On fail goto*//*Label 1475*/ GIMT_Encode4(74553), // Rule ID 4399 // |
| 27027 | /* 74469 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 27028 | /* 74472 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmull), |
| 27029 | /* 74477 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 27030 | /* 74480 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 27031 | /* 74483 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 27032 | /* 74486 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 27033 | /* 74489 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 27034 | /* 74492 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27035 | /* 74496 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27036 | /* 74500 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27037 | /* 74504 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 27038 | /* 74508 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 27039 | /* 74512 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3666:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VMULLBu8:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 27040 | /* 74512 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 27041 | /* 74515 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 27042 | /* 74519 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27043 | /* 74524 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLBu8), |
| 27044 | /* 74527 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 27045 | /* 74529 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 27046 | /* 74531 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 27047 | /* 74533 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27048 | /* 74536 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27049 | /* 74542 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27050 | /* 74548 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 27051 | /* 74551 */ GIR_RootConstrainSelectedInstOperands, |
| 27052 | /* 74552 */ // GIR_Coverage, 4399, |
| 27053 | /* 74552 */ GIR_EraseRootFromParent_Done, |
| 27054 | /* 74553 */ // Label 1475: @74553 |
| 27055 | /* 74553 */ GIM_Try, /*On fail goto*//*Label 1476*/ GIMT_Encode4(74642), // Rule ID 4401 // |
| 27056 | /* 74558 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 27057 | /* 74561 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmull), |
| 27058 | /* 74566 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 27059 | /* 74569 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 27060 | /* 74572 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 27061 | /* 74575 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 27062 | /* 74578 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 27063 | /* 74581 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27064 | /* 74585 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27065 | /* 74589 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27066 | /* 74593 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 27067 | /* 74597 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 27068 | /* 74601 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3666:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VMULLTu8:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 27069 | /* 74601 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 27070 | /* 74604 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 27071 | /* 74608 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27072 | /* 74613 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLTu8), |
| 27073 | /* 74616 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 27074 | /* 74618 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 27075 | /* 74620 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 27076 | /* 74622 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27077 | /* 74625 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27078 | /* 74631 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27079 | /* 74637 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 27080 | /* 74640 */ GIR_RootConstrainSelectedInstOperands, |
| 27081 | /* 74641 */ // GIR_Coverage, 4401, |
| 27082 | /* 74641 */ GIR_EraseRootFromParent_Done, |
| 27083 | /* 74642 */ // Label 1476: @74642 |
| 27084 | /* 74642 */ GIM_Try, /*On fail goto*//*Label 1477*/ GIMT_Encode4(74731), // Rule ID 4403 // |
| 27085 | /* 74647 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 27086 | /* 74650 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmull), |
| 27087 | /* 74655 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 27088 | /* 74658 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 27089 | /* 74661 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 27090 | /* 74664 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 27091 | /* 74667 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 27092 | /* 74670 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27093 | /* 74674 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27094 | /* 74678 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27095 | /* 74682 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 27096 | /* 74686 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 27097 | /* 74690 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3666:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VMULLBu16:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 27098 | /* 74690 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 27099 | /* 74693 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 27100 | /* 74697 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27101 | /* 74702 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLBu16), |
| 27102 | /* 74705 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 27103 | /* 74707 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 27104 | /* 74709 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 27105 | /* 74711 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27106 | /* 74714 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27107 | /* 74720 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27108 | /* 74726 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 27109 | /* 74729 */ GIR_RootConstrainSelectedInstOperands, |
| 27110 | /* 74730 */ // GIR_Coverage, 4403, |
| 27111 | /* 74730 */ GIR_EraseRootFromParent_Done, |
| 27112 | /* 74731 */ // Label 1477: @74731 |
| 27113 | /* 74731 */ GIM_Try, /*On fail goto*//*Label 1478*/ GIMT_Encode4(74820), // Rule ID 4405 // |
| 27114 | /* 74736 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 27115 | /* 74739 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmull), |
| 27116 | /* 74744 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 27117 | /* 74747 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 27118 | /* 74750 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 27119 | /* 74753 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 27120 | /* 74756 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 27121 | /* 74759 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27122 | /* 74763 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27123 | /* 74767 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27124 | /* 74771 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 27125 | /* 74775 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 27126 | /* 74779 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3666:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VMULLTu16:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 27127 | /* 74779 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 27128 | /* 74782 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 27129 | /* 74786 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27130 | /* 74791 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLTu16), |
| 27131 | /* 74794 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 27132 | /* 74796 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 27133 | /* 74798 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 27134 | /* 74800 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27135 | /* 74803 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27136 | /* 74809 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27137 | /* 74815 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 27138 | /* 74818 */ GIR_RootConstrainSelectedInstOperands, |
| 27139 | /* 74819 */ // GIR_Coverage, 4405, |
| 27140 | /* 74819 */ GIR_EraseRootFromParent_Done, |
| 27141 | /* 74820 */ // Label 1478: @74820 |
| 27142 | /* 74820 */ GIM_Try, /*On fail goto*//*Label 1479*/ GIMT_Encode4(74909), // Rule ID 4407 // |
| 27143 | /* 74825 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 27144 | /* 74828 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmull), |
| 27145 | /* 74833 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 27146 | /* 74836 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 27147 | /* 74839 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 27148 | /* 74842 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 27149 | /* 74845 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 27150 | /* 74848 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27151 | /* 74852 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27152 | /* 74856 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27153 | /* 74860 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 27154 | /* 74864 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 27155 | /* 74868 */ // (intrinsic_wo_chain:{ *:[v2i64] } 3666:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VMULLBu32:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 27156 | /* 74868 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 27157 | /* 74871 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 27158 | /* 74875 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27159 | /* 74880 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLBu32), |
| 27160 | /* 74883 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 27161 | /* 74885 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 27162 | /* 74887 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 27163 | /* 74889 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27164 | /* 74892 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27165 | /* 74898 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27166 | /* 74904 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 27167 | /* 74907 */ GIR_RootConstrainSelectedInstOperands, |
| 27168 | /* 74908 */ // GIR_Coverage, 4407, |
| 27169 | /* 74908 */ GIR_EraseRootFromParent_Done, |
| 27170 | /* 74909 */ // Label 1479: @74909 |
| 27171 | /* 74909 */ GIM_Try, /*On fail goto*//*Label 1480*/ GIMT_Encode4(74998), // Rule ID 4409 // |
| 27172 | /* 74914 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 27173 | /* 74917 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmull), |
| 27174 | /* 74922 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 27175 | /* 74925 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 27176 | /* 74928 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 27177 | /* 74931 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 27178 | /* 74934 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 27179 | /* 74937 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27180 | /* 74941 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27181 | /* 74945 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27182 | /* 74949 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 27183 | /* 74953 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 27184 | /* 74957 */ // (intrinsic_wo_chain:{ *:[v2i64] } 3666:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VMULLTu32:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 27185 | /* 74957 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 27186 | /* 74960 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 27187 | /* 74964 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27188 | /* 74969 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLTu32), |
| 27189 | /* 74972 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 27190 | /* 74974 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 27191 | /* 74976 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 27192 | /* 74978 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27193 | /* 74981 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27194 | /* 74987 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27195 | /* 74993 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 27196 | /* 74996 */ GIR_RootConstrainSelectedInstOperands, |
| 27197 | /* 74997 */ // GIR_Coverage, 4409, |
| 27198 | /* 74997 */ GIR_EraseRootFromParent_Done, |
| 27199 | /* 74998 */ // Label 1480: @74998 |
| 27200 | /* 74998 */ GIM_Try, /*On fail goto*//*Label 1481*/ GIMT_Encode4(75096), // Rule ID 4032 // |
| 27201 | /* 75003 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 27202 | /* 75006 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcaddq), |
| 27203 | /* 75011 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 27204 | /* 75014 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 27205 | /* 75017 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 27206 | /* 75020 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16, |
| 27207 | /* 75023 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16, |
| 27208 | /* 75026 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27209 | /* 75030 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 27210 | /* 75034 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 27211 | /* 75038 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 27212 | /* 75042 */ // MIs[1] Operand 1 |
| 27213 | /* 75042 */ // No operand predicates |
| 27214 | /* 75042 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27215 | /* 75046 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27216 | /* 75050 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 27217 | /* 75052 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3609:{ *:[iPTR] }, 1:{ *:[i32] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v8f16] }:$Qn, MQPR:{ *:[v8f16] }:$Qm) => (MVE_VCADDf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qn, MQPR:{ *:[v8f16] }:$Qm, (imm:{ *:[i32] }):$rot) |
| 27218 | /* 75052 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 27219 | /* 75055 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 27220 | /* 75059 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27221 | /* 75064 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCADDf16), |
| 27222 | /* 75067 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 27223 | /* 75069 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn |
| 27224 | /* 75071 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm |
| 27225 | /* 75073 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot |
| 27226 | /* 75076 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27227 | /* 75079 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27228 | /* 75085 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27229 | /* 75091 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 27230 | /* 75094 */ GIR_RootConstrainSelectedInstOperands, |
| 27231 | /* 75095 */ // GIR_Coverage, 4032, |
| 27232 | /* 75095 */ GIR_EraseRootFromParent_Done, |
| 27233 | /* 75096 */ // Label 1481: @75096 |
| 27234 | /* 75096 */ GIM_Try, /*On fail goto*//*Label 1482*/ GIMT_Encode4(75194), // Rule ID 4034 // |
| 27235 | /* 75101 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 27236 | /* 75104 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcaddq), |
| 27237 | /* 75109 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 27238 | /* 75112 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 27239 | /* 75115 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 27240 | /* 75118 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 27241 | /* 75121 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v4s32, |
| 27242 | /* 75124 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27243 | /* 75128 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 27244 | /* 75132 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 27245 | /* 75136 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 27246 | /* 75140 */ // MIs[1] Operand 1 |
| 27247 | /* 75140 */ // No operand predicates |
| 27248 | /* 75140 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27249 | /* 75144 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27250 | /* 75148 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 27251 | /* 75150 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3609:{ *:[iPTR] }, 1:{ *:[i32] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v4f32] }:$Qn, MQPR:{ *:[v4f32] }:$Qm) => (MVE_VCADDf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qn, MQPR:{ *:[v4f32] }:$Qm, (imm:{ *:[i32] }):$rot) |
| 27252 | /* 75150 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 27253 | /* 75153 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 27254 | /* 75157 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27255 | /* 75162 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCADDf32), |
| 27256 | /* 75165 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 27257 | /* 75167 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn |
| 27258 | /* 75169 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm |
| 27259 | /* 75171 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot |
| 27260 | /* 75174 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27261 | /* 75177 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27262 | /* 75183 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27263 | /* 75189 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 27264 | /* 75192 */ GIR_RootConstrainSelectedInstOperands, |
| 27265 | /* 75193 */ // GIR_Coverage, 4034, |
| 27266 | /* 75193 */ GIR_EraseRootFromParent_Done, |
| 27267 | /* 75194 */ // Label 1482: @75194 |
| 27268 | /* 75194 */ GIM_Try, /*On fail goto*//*Label 1483*/ GIMT_Encode4(75292), // Rule ID 4541 // |
| 27269 | /* 75199 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 27270 | /* 75202 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcaddq), |
| 27271 | /* 75207 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 27272 | /* 75210 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 27273 | /* 75213 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 27274 | /* 75216 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 27275 | /* 75219 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s8, |
| 27276 | /* 75222 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27277 | /* 75226 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 27278 | /* 75230 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 27279 | /* 75234 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 27280 | /* 75238 */ // MIs[1] Operand 1 |
| 27281 | /* 75238 */ // No operand predicates |
| 27282 | /* 75238 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27283 | /* 75242 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27284 | /* 75246 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 27285 | /* 75248 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3609:{ *:[iPTR] }, 1:{ *:[i32] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VCADDi8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm, (imm:{ *:[i32] }):$rot) |
| 27286 | /* 75248 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 27287 | /* 75251 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 27288 | /* 75255 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27289 | /* 75260 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCADDi8), |
| 27290 | /* 75263 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 27291 | /* 75265 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn |
| 27292 | /* 75267 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm |
| 27293 | /* 75269 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot |
| 27294 | /* 75272 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27295 | /* 75275 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27296 | /* 75281 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27297 | /* 75287 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 27298 | /* 75290 */ GIR_RootConstrainSelectedInstOperands, |
| 27299 | /* 75291 */ // GIR_Coverage, 4541, |
| 27300 | /* 75291 */ GIR_EraseRootFromParent_Done, |
| 27301 | /* 75292 */ // Label 1483: @75292 |
| 27302 | /* 75292 */ GIM_Try, /*On fail goto*//*Label 1484*/ GIMT_Encode4(75390), // Rule ID 4543 // |
| 27303 | /* 75297 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 27304 | /* 75300 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcaddq), |
| 27305 | /* 75305 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 27306 | /* 75308 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 27307 | /* 75311 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 27308 | /* 75314 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16, |
| 27309 | /* 75317 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16, |
| 27310 | /* 75320 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27311 | /* 75324 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 27312 | /* 75328 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 27313 | /* 75332 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 27314 | /* 75336 */ // MIs[1] Operand 1 |
| 27315 | /* 75336 */ // No operand predicates |
| 27316 | /* 75336 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27317 | /* 75340 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27318 | /* 75344 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 27319 | /* 75346 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3609:{ *:[iPTR] }, 1:{ *:[i32] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VCADDi16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$rot) |
| 27320 | /* 75346 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 27321 | /* 75349 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 27322 | /* 75353 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27323 | /* 75358 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCADDi16), |
| 27324 | /* 75361 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 27325 | /* 75363 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn |
| 27326 | /* 75365 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm |
| 27327 | /* 75367 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot |
| 27328 | /* 75370 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27329 | /* 75373 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27330 | /* 75379 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27331 | /* 75385 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 27332 | /* 75388 */ GIR_RootConstrainSelectedInstOperands, |
| 27333 | /* 75389 */ // GIR_Coverage, 4543, |
| 27334 | /* 75389 */ GIR_EraseRootFromParent_Done, |
| 27335 | /* 75390 */ // Label 1484: @75390 |
| 27336 | /* 75390 */ GIM_Try, /*On fail goto*//*Label 1485*/ GIMT_Encode4(75488), // Rule ID 4545 // |
| 27337 | /* 75395 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 27338 | /* 75398 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcaddq), |
| 27339 | /* 75403 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 27340 | /* 75406 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 27341 | /* 75409 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 27342 | /* 75412 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 27343 | /* 75415 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v4s32, |
| 27344 | /* 75418 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27345 | /* 75422 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 27346 | /* 75426 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 27347 | /* 75430 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 27348 | /* 75434 */ // MIs[1] Operand 1 |
| 27349 | /* 75434 */ // No operand predicates |
| 27350 | /* 75434 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27351 | /* 75438 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27352 | /* 75442 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 27353 | /* 75444 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3609:{ *:[iPTR] }, 1:{ *:[i32] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VCADDi32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$rot) |
| 27354 | /* 75444 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 27355 | /* 75447 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 27356 | /* 75451 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27357 | /* 75456 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCADDi32), |
| 27358 | /* 75459 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 27359 | /* 75461 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn |
| 27360 | /* 75463 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm |
| 27361 | /* 75465 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot |
| 27362 | /* 75468 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27363 | /* 75471 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27364 | /* 75477 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27365 | /* 75483 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 27366 | /* 75486 */ GIR_RootConstrainSelectedInstOperands, |
| 27367 | /* 75487 */ // GIR_Coverage, 4545, |
| 27368 | /* 75487 */ GIR_EraseRootFromParent_Done, |
| 27369 | /* 75488 */ // Label 1485: @75488 |
| 27370 | /* 75488 */ GIM_Try, /*On fail goto*//*Label 1486*/ GIMT_Encode4(75586), // Rule ID 4547 // |
| 27371 | /* 75493 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 27372 | /* 75496 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcaddq), |
| 27373 | /* 75501 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 27374 | /* 75504 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 27375 | /* 75507 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 27376 | /* 75510 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 27377 | /* 75513 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s8, |
| 27378 | /* 75516 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27379 | /* 75520 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 27380 | /* 75524 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 27381 | /* 75528 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 27382 | /* 75532 */ // MIs[1] Operand 1 |
| 27383 | /* 75532 */ // No operand predicates |
| 27384 | /* 75532 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27385 | /* 75536 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27386 | /* 75540 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 27387 | /* 75542 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3609:{ *:[iPTR] }, 0:{ *:[i32] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VHCADDs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm, (imm:{ *:[i32] }):$rot) |
| 27388 | /* 75542 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 27389 | /* 75545 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 27390 | /* 75549 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27391 | /* 75554 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHCADDs8), |
| 27392 | /* 75557 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 27393 | /* 75559 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn |
| 27394 | /* 75561 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm |
| 27395 | /* 75563 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot |
| 27396 | /* 75566 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27397 | /* 75569 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27398 | /* 75575 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27399 | /* 75581 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 27400 | /* 75584 */ GIR_RootConstrainSelectedInstOperands, |
| 27401 | /* 75585 */ // GIR_Coverage, 4547, |
| 27402 | /* 75585 */ GIR_EraseRootFromParent_Done, |
| 27403 | /* 75586 */ // Label 1486: @75586 |
| 27404 | /* 75586 */ GIM_Try, /*On fail goto*//*Label 1487*/ GIMT_Encode4(75684), // Rule ID 4549 // |
| 27405 | /* 75591 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 27406 | /* 75594 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcaddq), |
| 27407 | /* 75599 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 27408 | /* 75602 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 27409 | /* 75605 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 27410 | /* 75608 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16, |
| 27411 | /* 75611 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16, |
| 27412 | /* 75614 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27413 | /* 75618 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 27414 | /* 75622 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 27415 | /* 75626 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 27416 | /* 75630 */ // MIs[1] Operand 1 |
| 27417 | /* 75630 */ // No operand predicates |
| 27418 | /* 75630 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27419 | /* 75634 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27420 | /* 75638 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 27421 | /* 75640 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3609:{ *:[iPTR] }, 0:{ *:[i32] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VHCADDs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$rot) |
| 27422 | /* 75640 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 27423 | /* 75643 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 27424 | /* 75647 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27425 | /* 75652 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHCADDs16), |
| 27426 | /* 75655 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 27427 | /* 75657 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn |
| 27428 | /* 75659 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm |
| 27429 | /* 75661 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot |
| 27430 | /* 75664 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27431 | /* 75667 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27432 | /* 75673 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27433 | /* 75679 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 27434 | /* 75682 */ GIR_RootConstrainSelectedInstOperands, |
| 27435 | /* 75683 */ // GIR_Coverage, 4549, |
| 27436 | /* 75683 */ GIR_EraseRootFromParent_Done, |
| 27437 | /* 75684 */ // Label 1487: @75684 |
| 27438 | /* 75684 */ GIM_Try, /*On fail goto*//*Label 1488*/ GIMT_Encode4(75782), // Rule ID 4551 // |
| 27439 | /* 75689 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 27440 | /* 75692 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcaddq), |
| 27441 | /* 75697 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 27442 | /* 75700 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 27443 | /* 75703 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 27444 | /* 75706 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 27445 | /* 75709 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v4s32, |
| 27446 | /* 75712 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27447 | /* 75716 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 27448 | /* 75720 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 27449 | /* 75724 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 27450 | /* 75728 */ // MIs[1] Operand 1 |
| 27451 | /* 75728 */ // No operand predicates |
| 27452 | /* 75728 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27453 | /* 75732 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27454 | /* 75736 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 27455 | /* 75738 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3609:{ *:[iPTR] }, 0:{ *:[i32] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VHCADDs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$rot) |
| 27456 | /* 75738 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 27457 | /* 75741 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 27458 | /* 75745 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27459 | /* 75750 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHCADDs32), |
| 27460 | /* 75753 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 27461 | /* 75755 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn |
| 27462 | /* 75757 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm |
| 27463 | /* 75759 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot |
| 27464 | /* 75762 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27465 | /* 75765 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27466 | /* 75771 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27467 | /* 75777 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 27468 | /* 75780 */ GIR_RootConstrainSelectedInstOperands, |
| 27469 | /* 75781 */ // GIR_Coverage, 4551, |
| 27470 | /* 75781 */ GIR_EraseRootFromParent_Done, |
| 27471 | /* 75782 */ // Label 1488: @75782 |
| 27472 | /* 75782 */ GIM_Try, /*On fail goto*//*Label 1489*/ GIMT_Encode4(75858), // Rule ID 3037 // |
| 27473 | /* 75787 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 27474 | /* 75790 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vabav), |
| 27475 | /* 75795 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 27476 | /* 75798 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 27477 | /* 75801 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 27478 | /* 75804 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 27479 | /* 75807 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s8, |
| 27480 | /* 75810 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 27481 | /* 75814 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 27482 | /* 75818 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 27483 | /* 75822 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27484 | /* 75826 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27485 | /* 75830 */ // (intrinsic_wo_chain:{ *:[i32] } 3602:{ *:[iPTR] }, 0:{ *:[i32] }, rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VABAVs8:{ *:[i32] } rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) |
| 27486 | /* 75830 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABAVs8), |
| 27487 | /* 75833 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda] |
| 27488 | /* 75835 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rda_src |
| 27489 | /* 75837 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn |
| 27490 | /* 75839 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm |
| 27491 | /* 75841 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27492 | /* 75844 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27493 | /* 75850 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27494 | /* 75856 */ GIR_RootConstrainSelectedInstOperands, |
| 27495 | /* 75857 */ // GIR_Coverage, 3037, |
| 27496 | /* 75857 */ GIR_EraseRootFromParent_Done, |
| 27497 | /* 75858 */ // Label 1489: @75858 |
| 27498 | /* 75858 */ GIM_Try, /*On fail goto*//*Label 1490*/ GIMT_Encode4(75934), // Rule ID 3039 // |
| 27499 | /* 75863 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 27500 | /* 75866 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vabav), |
| 27501 | /* 75871 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 27502 | /* 75874 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 27503 | /* 75877 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 27504 | /* 75880 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16, |
| 27505 | /* 75883 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16, |
| 27506 | /* 75886 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 27507 | /* 75890 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 27508 | /* 75894 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 27509 | /* 75898 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27510 | /* 75902 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27511 | /* 75906 */ // (intrinsic_wo_chain:{ *:[i32] } 3602:{ *:[iPTR] }, 0:{ *:[i32] }, rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VABAVs16:{ *:[i32] } rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) |
| 27512 | /* 75906 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABAVs16), |
| 27513 | /* 75909 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda] |
| 27514 | /* 75911 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rda_src |
| 27515 | /* 75913 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn |
| 27516 | /* 75915 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm |
| 27517 | /* 75917 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27518 | /* 75920 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27519 | /* 75926 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27520 | /* 75932 */ GIR_RootConstrainSelectedInstOperands, |
| 27521 | /* 75933 */ // GIR_Coverage, 3039, |
| 27522 | /* 75933 */ GIR_EraseRootFromParent_Done, |
| 27523 | /* 75934 */ // Label 1490: @75934 |
| 27524 | /* 75934 */ GIM_Try, /*On fail goto*//*Label 1491*/ GIMT_Encode4(76010), // Rule ID 3041 // |
| 27525 | /* 75939 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 27526 | /* 75942 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vabav), |
| 27527 | /* 75947 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 27528 | /* 75950 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 27529 | /* 75953 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 27530 | /* 75956 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 27531 | /* 75959 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v4s32, |
| 27532 | /* 75962 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 27533 | /* 75966 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 27534 | /* 75970 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 27535 | /* 75974 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27536 | /* 75978 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27537 | /* 75982 */ // (intrinsic_wo_chain:{ *:[i32] } 3602:{ *:[iPTR] }, 0:{ *:[i32] }, rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VABAVs32:{ *:[i32] } rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) |
| 27538 | /* 75982 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABAVs32), |
| 27539 | /* 75985 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda] |
| 27540 | /* 75987 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rda_src |
| 27541 | /* 75989 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn |
| 27542 | /* 75991 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm |
| 27543 | /* 75993 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27544 | /* 75996 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27545 | /* 76002 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27546 | /* 76008 */ GIR_RootConstrainSelectedInstOperands, |
| 27547 | /* 76009 */ // GIR_Coverage, 3041, |
| 27548 | /* 76009 */ GIR_EraseRootFromParent_Done, |
| 27549 | /* 76010 */ // Label 1491: @76010 |
| 27550 | /* 76010 */ GIM_Try, /*On fail goto*//*Label 1492*/ GIMT_Encode4(76086), // Rule ID 3043 // |
| 27551 | /* 76015 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 27552 | /* 76018 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vabav), |
| 27553 | /* 76023 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 27554 | /* 76026 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 27555 | /* 76029 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 27556 | /* 76032 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 27557 | /* 76035 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s8, |
| 27558 | /* 76038 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 27559 | /* 76042 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 27560 | /* 76046 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 27561 | /* 76050 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27562 | /* 76054 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27563 | /* 76058 */ // (intrinsic_wo_chain:{ *:[i32] } 3602:{ *:[iPTR] }, 1:{ *:[i32] }, rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VABAVu8:{ *:[i32] } rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) |
| 27564 | /* 76058 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABAVu8), |
| 27565 | /* 76061 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda] |
| 27566 | /* 76063 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rda_src |
| 27567 | /* 76065 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn |
| 27568 | /* 76067 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm |
| 27569 | /* 76069 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27570 | /* 76072 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27571 | /* 76078 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27572 | /* 76084 */ GIR_RootConstrainSelectedInstOperands, |
| 27573 | /* 76085 */ // GIR_Coverage, 3043, |
| 27574 | /* 76085 */ GIR_EraseRootFromParent_Done, |
| 27575 | /* 76086 */ // Label 1492: @76086 |
| 27576 | /* 76086 */ GIM_Try, /*On fail goto*//*Label 1493*/ GIMT_Encode4(76162), // Rule ID 3045 // |
| 27577 | /* 76091 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 27578 | /* 76094 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vabav), |
| 27579 | /* 76099 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 27580 | /* 76102 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 27581 | /* 76105 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 27582 | /* 76108 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16, |
| 27583 | /* 76111 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16, |
| 27584 | /* 76114 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 27585 | /* 76118 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 27586 | /* 76122 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 27587 | /* 76126 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27588 | /* 76130 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27589 | /* 76134 */ // (intrinsic_wo_chain:{ *:[i32] } 3602:{ *:[iPTR] }, 1:{ *:[i32] }, rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VABAVu16:{ *:[i32] } rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) |
| 27590 | /* 76134 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABAVu16), |
| 27591 | /* 76137 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda] |
| 27592 | /* 76139 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rda_src |
| 27593 | /* 76141 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn |
| 27594 | /* 76143 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm |
| 27595 | /* 76145 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27596 | /* 76148 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27597 | /* 76154 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27598 | /* 76160 */ GIR_RootConstrainSelectedInstOperands, |
| 27599 | /* 76161 */ // GIR_Coverage, 3045, |
| 27600 | /* 76161 */ GIR_EraseRootFromParent_Done, |
| 27601 | /* 76162 */ // Label 1493: @76162 |
| 27602 | /* 76162 */ GIM_Try, /*On fail goto*//*Label 1494*/ GIMT_Encode4(76238), // Rule ID 3047 // |
| 27603 | /* 76167 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 27604 | /* 76170 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vabav), |
| 27605 | /* 76175 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 27606 | /* 76178 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 27607 | /* 76181 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 27608 | /* 76184 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 27609 | /* 76187 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v4s32, |
| 27610 | /* 76190 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 27611 | /* 76194 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 27612 | /* 76198 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 27613 | /* 76202 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27614 | /* 76206 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27615 | /* 76210 */ // (intrinsic_wo_chain:{ *:[i32] } 3602:{ *:[iPTR] }, 1:{ *:[i32] }, rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VABAVu32:{ *:[i32] } rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) |
| 27616 | /* 76210 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABAVu32), |
| 27617 | /* 76213 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda] |
| 27618 | /* 76215 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rda_src |
| 27619 | /* 76217 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn |
| 27620 | /* 76219 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm |
| 27621 | /* 76221 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27622 | /* 76224 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27623 | /* 76230 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27624 | /* 76236 */ GIR_RootConstrainSelectedInstOperands, |
| 27625 | /* 76237 */ // GIR_Coverage, 3047, |
| 27626 | /* 76237 */ GIR_EraseRootFromParent_Done, |
| 27627 | /* 76238 */ // Label 1494: @76238 |
| 27628 | /* 76238 */ GIM_Try, /*On fail goto*//*Label 1495*/ GIMT_Encode4(76323), // Rule ID 3996 // |
| 27629 | /* 76243 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 27630 | /* 76246 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcmlaq), |
| 27631 | /* 76251 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 27632 | /* 76254 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 27633 | /* 76257 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 27634 | /* 76260 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16, |
| 27635 | /* 76263 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16, |
| 27636 | /* 76266 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27637 | /* 76270 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 27638 | /* 76274 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 27639 | /* 76278 */ // MIs[1] Operand 1 |
| 27640 | /* 76278 */ // No operand predicates |
| 27641 | /* 76278 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27642 | /* 76282 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27643 | /* 76286 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27644 | /* 76290 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 27645 | /* 76292 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3612:{ *:[iPTR] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v8f16] }:$Qd_src, MQPR:{ *:[v8f16] }:$Qn, MQPR:{ *:[v8f16] }:$Qm) => (MVE_VCMLAf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd_src, MQPR:{ *:[v8f16] }:$Qn, MQPR:{ *:[v8f16] }:$Qm, (imm:{ *:[i32] }):$rot) |
| 27646 | /* 76292 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMLAf16), |
| 27647 | /* 76295 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 27648 | /* 76297 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qd_src |
| 27649 | /* 76299 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn |
| 27650 | /* 76301 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm |
| 27651 | /* 76303 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot |
| 27652 | /* 76306 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27653 | /* 76309 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27654 | /* 76315 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27655 | /* 76321 */ GIR_RootConstrainSelectedInstOperands, |
| 27656 | /* 76322 */ // GIR_Coverage, 3996, |
| 27657 | /* 76322 */ GIR_EraseRootFromParent_Done, |
| 27658 | /* 76323 */ // Label 1495: @76323 |
| 27659 | /* 76323 */ GIM_Try, /*On fail goto*//*Label 1496*/ GIMT_Encode4(76408), // Rule ID 3999 // |
| 27660 | /* 76328 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 27661 | /* 76331 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcmlaq), |
| 27662 | /* 76336 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 27663 | /* 76339 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 27664 | /* 76342 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 27665 | /* 76345 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 27666 | /* 76348 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v4s32, |
| 27667 | /* 76351 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27668 | /* 76355 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 27669 | /* 76359 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 27670 | /* 76363 */ // MIs[1] Operand 1 |
| 27671 | /* 76363 */ // No operand predicates |
| 27672 | /* 76363 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27673 | /* 76367 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27674 | /* 76371 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27675 | /* 76375 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 27676 | /* 76377 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3612:{ *:[iPTR] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v4f32] }:$Qd_src, MQPR:{ *:[v4f32] }:$Qn, MQPR:{ *:[v4f32] }:$Qm) => (MVE_VCMLAf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qd_src, MQPR:{ *:[v4f32] }:$Qn, MQPR:{ *:[v4f32] }:$Qm, (imm:{ *:[i32] }):$rot) |
| 27677 | /* 76377 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMLAf32), |
| 27678 | /* 76380 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 27679 | /* 76382 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qd_src |
| 27680 | /* 76384 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn |
| 27681 | /* 76386 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm |
| 27682 | /* 76388 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot |
| 27683 | /* 76391 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27684 | /* 76394 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27685 | /* 76400 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27686 | /* 76406 */ GIR_RootConstrainSelectedInstOperands, |
| 27687 | /* 76407 */ // GIR_Coverage, 3999, |
| 27688 | /* 76407 */ GIR_EraseRootFromParent_Done, |
| 27689 | /* 76408 */ // Label 1496: @76408 |
| 27690 | /* 76408 */ GIM_Try, /*On fail goto*//*Label 1497*/ GIMT_Encode4(76504), // Rule ID 2688 // |
| 27691 | /* 76413 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 27692 | /* 76416 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vtbx2), |
| 27693 | /* 76421 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, |
| 27694 | /* 76424 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 27695 | /* 76427 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 27696 | /* 76430 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s8, |
| 27697 | /* 76433 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s8, |
| 27698 | /* 76436 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 27699 | /* 76440 */ // (intrinsic_wo_chain:{ *:[v8i8] } 3862:{ *:[iPTR] }, v8i8:{ *:[v8i8] }:$orig, v8i8:{ *:[v8i8] }:$Vn0, v8i8:{ *:[v8i8] }:$Vn1, v8i8:{ *:[v8i8] }:$Vm) => (VTBX2:{ *:[v8i8] } v8i8:{ *:[v8i8] }:$orig, (REG_SEQUENCE:{ *:[v16i8] } DPair:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn0, dsub_0:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn1, dsub_1:{ *:[i32] }), v8i8:{ *:[v8i8] }:$Vm) |
| 27700 | /* 76440 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, |
| 27701 | /* 76443 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 27702 | /* 76447 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27703 | /* 76452 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // Vn0 |
| 27704 | /* 76456 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/1, |
| 27705 | /* 76459 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // Vn1 |
| 27706 | /* 76463 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/2, |
| 27707 | /* 76466 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPairRegClassID), |
| 27708 | /* 76471 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(ARM::DPRRegClassID), |
| 27709 | /* 76476 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(ARM::DPRRegClassID), |
| 27710 | /* 76481 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VTBX2), |
| 27711 | /* 76484 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 27712 | /* 76486 */ GIR_RootToRootCopy, /*OpIdx*/2, // orig |
| 27713 | /* 76488 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 27714 | /* 76491 */ GIR_RootToRootCopy, /*OpIdx*/5, // Vm |
| 27715 | /* 76493 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 27716 | /* 76496 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27717 | /* 76502 */ GIR_RootConstrainSelectedInstOperands, |
| 27718 | /* 76503 */ // GIR_Coverage, 2688, |
| 27719 | /* 76503 */ GIR_EraseRootFromParent_Done, |
| 27720 | /* 76504 */ // Label 1497: @76504 |
| 27721 | /* 76504 */ GIM_Try, /*On fail goto*//*Label 1498*/ GIMT_Encode4(76635), // Rule ID 2689 // |
| 27722 | /* 76509 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 27723 | /* 76512 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vtbl3), |
| 27724 | /* 76517 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, |
| 27725 | /* 76520 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 27726 | /* 76523 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 27727 | /* 76526 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s8, |
| 27728 | /* 76529 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s8, |
| 27729 | /* 76532 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 27730 | /* 76536 */ // (intrinsic_wo_chain:{ *:[v8i8] } 3859:{ *:[iPTR] }, v8i8:{ *:[v8i8] }:$Vn0, v8i8:{ *:[v8i8] }:$Vn1, v8i8:{ *:[v8i8] }:$Vn2, v8i8:{ *:[v8i8] }:$Vm) => (VTBL3Pseudo:{ *:[v8i8] } (REG_SEQUENCE:{ *:[v4i64] } QQPR:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn0, dsub_0:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn1, dsub_1:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn2, dsub_2:{ *:[i32] }, (IMPLICIT_DEF:{ *:[v8i8] }), dsub_3:{ *:[i32] }), v8i8:{ *:[v8i8] }:$Vm) |
| 27731 | /* 76536 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s8, |
| 27732 | /* 76539 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 27733 | /* 76543 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27734 | /* 76548 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 27735 | /* 76550 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s64, |
| 27736 | /* 76553 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 27737 | /* 76557 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27738 | /* 76562 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Vn0 |
| 27739 | /* 76566 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/1, |
| 27740 | /* 76569 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // Vn1 |
| 27741 | /* 76573 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/2, |
| 27742 | /* 76576 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // Vn2 |
| 27743 | /* 76580 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 27744 | /* 76583 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 27745 | /* 76586 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/4, |
| 27746 | /* 76589 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::QQPRRegClassID), |
| 27747 | /* 76594 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(ARM::DPRRegClassID), |
| 27748 | /* 76599 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(ARM::DPRRegClassID), |
| 27749 | /* 76604 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/5, GIMT_Encode2(ARM::DPRRegClassID), |
| 27750 | /* 76609 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/7, GIMT_Encode2(ARM::DPRRegClassID), |
| 27751 | /* 76614 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VTBL3Pseudo), |
| 27752 | /* 76617 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 27753 | /* 76619 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 27754 | /* 76622 */ GIR_RootToRootCopy, /*OpIdx*/5, // Vm |
| 27755 | /* 76624 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 27756 | /* 76627 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27757 | /* 76633 */ GIR_RootConstrainSelectedInstOperands, |
| 27758 | /* 76634 */ // GIR_Coverage, 2689, |
| 27759 | /* 76634 */ GIR_EraseRootFromParent_Done, |
| 27760 | /* 76635 */ // Label 1498: @76635 |
| 27761 | /* 76635 */ GIM_Reject, |
| 27762 | /* 76636 */ // Label 1460: @76636 |
| 27763 | /* 76636 */ GIM_Try, /*On fail goto*//*Label 1499*/ GIMT_Encode4(81942), |
| 27764 | /* 76641 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/7, |
| 27765 | /* 76644 */ GIM_Try, /*On fail goto*//*Label 1500*/ GIMT_Encode4(76737), // Rule ID 3838 // |
| 27766 | /* 76649 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector), |
| 27767 | /* 76654 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 27768 | /* 76657 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 27769 | /* 76660 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 27770 | /* 76663 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 27771 | /* 76666 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 27772 | /* 76669 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 27773 | /* 76672 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27774 | /* 76676 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27775 | /* 76680 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27776 | /* 76684 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 27777 | /* 76688 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 27778 | /* 76692 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 27779 | /* 76696 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3706:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHL_by_vecs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh) |
| 27780 | /* 76696 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 27781 | /* 76699 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 27782 | /* 76703 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27783 | /* 76708 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_by_vecs8), |
| 27784 | /* 76711 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 27785 | /* 76713 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 27786 | /* 76715 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 27787 | /* 76717 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27788 | /* 76720 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27789 | /* 76726 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27790 | /* 76732 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 27791 | /* 76735 */ GIR_RootConstrainSelectedInstOperands, |
| 27792 | /* 76736 */ // GIR_Coverage, 3838, |
| 27793 | /* 76736 */ GIR_EraseRootFromParent_Done, |
| 27794 | /* 76737 */ // Label 1500: @76737 |
| 27795 | /* 76737 */ GIM_Try, /*On fail goto*//*Label 1501*/ GIMT_Encode4(76830), // Rule ID 3840 // |
| 27796 | /* 76742 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector), |
| 27797 | /* 76747 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 27798 | /* 76750 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 27799 | /* 76753 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 27800 | /* 76756 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 27801 | /* 76759 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 27802 | /* 76762 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 27803 | /* 76765 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27804 | /* 76769 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27805 | /* 76773 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27806 | /* 76777 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 27807 | /* 76781 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 27808 | /* 76785 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 27809 | /* 76789 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3706:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHL_by_vecs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh) |
| 27810 | /* 76789 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 27811 | /* 76792 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 27812 | /* 76796 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27813 | /* 76801 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_by_vecs16), |
| 27814 | /* 76804 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 27815 | /* 76806 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 27816 | /* 76808 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 27817 | /* 76810 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27818 | /* 76813 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27819 | /* 76819 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27820 | /* 76825 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 27821 | /* 76828 */ GIR_RootConstrainSelectedInstOperands, |
| 27822 | /* 76829 */ // GIR_Coverage, 3840, |
| 27823 | /* 76829 */ GIR_EraseRootFromParent_Done, |
| 27824 | /* 76830 */ // Label 1501: @76830 |
| 27825 | /* 76830 */ GIM_Try, /*On fail goto*//*Label 1502*/ GIMT_Encode4(76923), // Rule ID 3842 // |
| 27826 | /* 76835 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector), |
| 27827 | /* 76840 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 27828 | /* 76843 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 27829 | /* 76846 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 27830 | /* 76849 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 27831 | /* 76852 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 27832 | /* 76855 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 27833 | /* 76858 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27834 | /* 76862 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27835 | /* 76866 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27836 | /* 76870 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 27837 | /* 76874 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 27838 | /* 76878 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 27839 | /* 76882 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3706:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHL_by_vecs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh) |
| 27840 | /* 76882 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 27841 | /* 76885 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 27842 | /* 76889 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27843 | /* 76894 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_by_vecs32), |
| 27844 | /* 76897 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 27845 | /* 76899 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 27846 | /* 76901 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 27847 | /* 76903 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27848 | /* 76906 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27849 | /* 76912 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27850 | /* 76918 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 27851 | /* 76921 */ GIR_RootConstrainSelectedInstOperands, |
| 27852 | /* 76922 */ // GIR_Coverage, 3842, |
| 27853 | /* 76922 */ GIR_EraseRootFromParent_Done, |
| 27854 | /* 76923 */ // Label 1502: @76923 |
| 27855 | /* 76923 */ GIM_Try, /*On fail goto*//*Label 1503*/ GIMT_Encode4(77016), // Rule ID 3844 // |
| 27856 | /* 76928 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector), |
| 27857 | /* 76933 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 27858 | /* 76936 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 27859 | /* 76939 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 27860 | /* 76942 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 27861 | /* 76945 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 27862 | /* 76948 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 27863 | /* 76951 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27864 | /* 76955 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27865 | /* 76959 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27866 | /* 76963 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 27867 | /* 76967 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 27868 | /* 76971 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 27869 | /* 76975 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3706:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHL_by_vecu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh) |
| 27870 | /* 76975 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 27871 | /* 76978 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 27872 | /* 76982 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27873 | /* 76987 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_by_vecu8), |
| 27874 | /* 76990 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 27875 | /* 76992 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 27876 | /* 76994 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 27877 | /* 76996 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27878 | /* 76999 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27879 | /* 77005 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27880 | /* 77011 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 27881 | /* 77014 */ GIR_RootConstrainSelectedInstOperands, |
| 27882 | /* 77015 */ // GIR_Coverage, 3844, |
| 27883 | /* 77015 */ GIR_EraseRootFromParent_Done, |
| 27884 | /* 77016 */ // Label 1503: @77016 |
| 27885 | /* 77016 */ GIM_Try, /*On fail goto*//*Label 1504*/ GIMT_Encode4(77109), // Rule ID 3846 // |
| 27886 | /* 77021 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector), |
| 27887 | /* 77026 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 27888 | /* 77029 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 27889 | /* 77032 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 27890 | /* 77035 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 27891 | /* 77038 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 27892 | /* 77041 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 27893 | /* 77044 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27894 | /* 77048 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27895 | /* 77052 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27896 | /* 77056 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 27897 | /* 77060 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 27898 | /* 77064 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 27899 | /* 77068 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3706:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHL_by_vecu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh) |
| 27900 | /* 77068 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 27901 | /* 77071 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 27902 | /* 77075 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27903 | /* 77080 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_by_vecu16), |
| 27904 | /* 77083 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 27905 | /* 77085 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 27906 | /* 77087 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 27907 | /* 77089 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27908 | /* 77092 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27909 | /* 77098 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27910 | /* 77104 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 27911 | /* 77107 */ GIR_RootConstrainSelectedInstOperands, |
| 27912 | /* 77108 */ // GIR_Coverage, 3846, |
| 27913 | /* 77108 */ GIR_EraseRootFromParent_Done, |
| 27914 | /* 77109 */ // Label 1504: @77109 |
| 27915 | /* 77109 */ GIM_Try, /*On fail goto*//*Label 1505*/ GIMT_Encode4(77202), // Rule ID 3848 // |
| 27916 | /* 77114 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector), |
| 27917 | /* 77119 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 27918 | /* 77122 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 27919 | /* 77125 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 27920 | /* 77128 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 27921 | /* 77131 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 27922 | /* 77134 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 27923 | /* 77137 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27924 | /* 77141 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27925 | /* 77145 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27926 | /* 77149 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 27927 | /* 77153 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 27928 | /* 77157 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 27929 | /* 77161 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3706:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHL_by_vecu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh) |
| 27930 | /* 77161 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 27931 | /* 77164 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 27932 | /* 77168 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27933 | /* 77173 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_by_vecu32), |
| 27934 | /* 77176 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 27935 | /* 77178 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 27936 | /* 77180 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 27937 | /* 77182 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27938 | /* 77185 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27939 | /* 77191 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27940 | /* 77197 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 27941 | /* 77200 */ GIR_RootConstrainSelectedInstOperands, |
| 27942 | /* 77201 */ // GIR_Coverage, 3848, |
| 27943 | /* 77201 */ GIR_EraseRootFromParent_Done, |
| 27944 | /* 77202 */ // Label 1505: @77202 |
| 27945 | /* 77202 */ GIM_Try, /*On fail goto*//*Label 1506*/ GIMT_Encode4(77295), // Rule ID 3850 // |
| 27946 | /* 77207 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector), |
| 27947 | /* 77212 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 27948 | /* 77215 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 27949 | /* 77218 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 27950 | /* 77221 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 27951 | /* 77224 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 27952 | /* 77227 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 27953 | /* 77230 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27954 | /* 77234 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27955 | /* 77238 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27956 | /* 77242 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 27957 | /* 77246 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 27958 | /* 77250 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 27959 | /* 77254 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3706:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHL_by_vecs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh) |
| 27960 | /* 77254 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 27961 | /* 77257 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 27962 | /* 77261 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27963 | /* 77266 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_by_vecs8), |
| 27964 | /* 77269 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 27965 | /* 77271 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 27966 | /* 77273 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 27967 | /* 77275 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27968 | /* 77278 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27969 | /* 77284 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27970 | /* 77290 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 27971 | /* 77293 */ GIR_RootConstrainSelectedInstOperands, |
| 27972 | /* 77294 */ // GIR_Coverage, 3850, |
| 27973 | /* 77294 */ GIR_EraseRootFromParent_Done, |
| 27974 | /* 77295 */ // Label 1506: @77295 |
| 27975 | /* 77295 */ GIM_Try, /*On fail goto*//*Label 1507*/ GIMT_Encode4(77388), // Rule ID 3852 // |
| 27976 | /* 77300 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector), |
| 27977 | /* 77305 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 27978 | /* 77308 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 27979 | /* 77311 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 27980 | /* 77314 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 27981 | /* 77317 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 27982 | /* 77320 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 27983 | /* 77323 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27984 | /* 77327 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27985 | /* 77331 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27986 | /* 77335 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 27987 | /* 77339 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 27988 | /* 77343 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 27989 | /* 77347 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3706:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHL_by_vecs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh) |
| 27990 | /* 77347 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 27991 | /* 77350 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 27992 | /* 77354 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27993 | /* 77359 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_by_vecs16), |
| 27994 | /* 77362 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 27995 | /* 77364 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 27996 | /* 77366 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 27997 | /* 77368 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27998 | /* 77371 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27999 | /* 77377 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28000 | /* 77383 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 28001 | /* 77386 */ GIR_RootConstrainSelectedInstOperands, |
| 28002 | /* 77387 */ // GIR_Coverage, 3852, |
| 28003 | /* 77387 */ GIR_EraseRootFromParent_Done, |
| 28004 | /* 77388 */ // Label 1507: @77388 |
| 28005 | /* 77388 */ GIM_Try, /*On fail goto*//*Label 1508*/ GIMT_Encode4(77481), // Rule ID 3854 // |
| 28006 | /* 77393 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector), |
| 28007 | /* 77398 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 28008 | /* 77401 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 28009 | /* 77404 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 28010 | /* 77407 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28011 | /* 77410 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 28012 | /* 77413 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 28013 | /* 77416 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28014 | /* 77420 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28015 | /* 77424 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28016 | /* 77428 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 28017 | /* 77432 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 28018 | /* 77436 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 28019 | /* 77440 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3706:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHL_by_vecs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh) |
| 28020 | /* 77440 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 28021 | /* 77443 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 28022 | /* 77447 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28023 | /* 77452 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_by_vecs32), |
| 28024 | /* 77455 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28025 | /* 77457 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 28026 | /* 77459 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 28027 | /* 77461 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28028 | /* 77464 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28029 | /* 77470 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28030 | /* 77476 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 28031 | /* 77479 */ GIR_RootConstrainSelectedInstOperands, |
| 28032 | /* 77480 */ // GIR_Coverage, 3854, |
| 28033 | /* 77480 */ GIR_EraseRootFromParent_Done, |
| 28034 | /* 77481 */ // Label 1508: @77481 |
| 28035 | /* 77481 */ GIM_Try, /*On fail goto*//*Label 1509*/ GIMT_Encode4(77574), // Rule ID 3856 // |
| 28036 | /* 77486 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector), |
| 28037 | /* 77491 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 28038 | /* 77494 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 28039 | /* 77497 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 28040 | /* 77500 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28041 | /* 77503 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 28042 | /* 77506 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 28043 | /* 77509 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28044 | /* 77513 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28045 | /* 77517 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28046 | /* 77521 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 28047 | /* 77525 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 28048 | /* 77529 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 28049 | /* 77533 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3706:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHL_by_vecu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh) |
| 28050 | /* 77533 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 28051 | /* 77536 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 28052 | /* 77540 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28053 | /* 77545 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_by_vecu8), |
| 28054 | /* 77548 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28055 | /* 77550 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 28056 | /* 77552 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 28057 | /* 77554 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28058 | /* 77557 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28059 | /* 77563 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28060 | /* 77569 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 28061 | /* 77572 */ GIR_RootConstrainSelectedInstOperands, |
| 28062 | /* 77573 */ // GIR_Coverage, 3856, |
| 28063 | /* 77573 */ GIR_EraseRootFromParent_Done, |
| 28064 | /* 77574 */ // Label 1509: @77574 |
| 28065 | /* 77574 */ GIM_Try, /*On fail goto*//*Label 1510*/ GIMT_Encode4(77667), // Rule ID 3858 // |
| 28066 | /* 77579 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector), |
| 28067 | /* 77584 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 28068 | /* 77587 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 28069 | /* 77590 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 28070 | /* 77593 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28071 | /* 77596 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 28072 | /* 77599 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 28073 | /* 77602 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28074 | /* 77606 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28075 | /* 77610 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28076 | /* 77614 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 28077 | /* 77618 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 28078 | /* 77622 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 28079 | /* 77626 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3706:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHL_by_vecu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh) |
| 28080 | /* 77626 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 28081 | /* 77629 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 28082 | /* 77633 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28083 | /* 77638 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_by_vecu16), |
| 28084 | /* 77641 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28085 | /* 77643 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 28086 | /* 77645 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 28087 | /* 77647 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28088 | /* 77650 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28089 | /* 77656 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28090 | /* 77662 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 28091 | /* 77665 */ GIR_RootConstrainSelectedInstOperands, |
| 28092 | /* 77666 */ // GIR_Coverage, 3858, |
| 28093 | /* 77666 */ GIR_EraseRootFromParent_Done, |
| 28094 | /* 77667 */ // Label 1510: @77667 |
| 28095 | /* 77667 */ GIM_Try, /*On fail goto*//*Label 1511*/ GIMT_Encode4(77760), // Rule ID 3860 // |
| 28096 | /* 77672 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector), |
| 28097 | /* 77677 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 28098 | /* 77680 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 28099 | /* 77683 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 28100 | /* 77686 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28101 | /* 77689 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 28102 | /* 77692 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 28103 | /* 77695 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28104 | /* 77699 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28105 | /* 77703 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28106 | /* 77707 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 28107 | /* 77711 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 28108 | /* 77715 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 28109 | /* 77719 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3706:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHL_by_vecu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh) |
| 28110 | /* 77719 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 28111 | /* 77722 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 28112 | /* 77726 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28113 | /* 77731 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_by_vecu32), |
| 28114 | /* 77734 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28115 | /* 77736 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 28116 | /* 77738 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 28117 | /* 77740 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28118 | /* 77743 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28119 | /* 77749 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28120 | /* 77755 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 28121 | /* 77758 */ GIR_RootConstrainSelectedInstOperands, |
| 28122 | /* 77759 */ // GIR_Coverage, 3860, |
| 28123 | /* 77759 */ GIR_EraseRootFromParent_Done, |
| 28124 | /* 77760 */ // Label 1511: @77760 |
| 28125 | /* 77760 */ GIM_Try, /*On fail goto*//*Label 1512*/ GIMT_Encode4(77853), // Rule ID 3862 // |
| 28126 | /* 77765 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector), |
| 28127 | /* 77770 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 28128 | /* 77773 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 28129 | /* 77776 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 28130 | /* 77779 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28131 | /* 77782 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 28132 | /* 77785 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 28133 | /* 77788 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28134 | /* 77792 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28135 | /* 77796 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28136 | /* 77800 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 28137 | /* 77804 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 28138 | /* 77808 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 28139 | /* 77812 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3706:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHL_by_vecs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh) |
| 28140 | /* 77812 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 28141 | /* 77815 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 28142 | /* 77819 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28143 | /* 77824 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_by_vecs8), |
| 28144 | /* 77827 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28145 | /* 77829 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 28146 | /* 77831 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 28147 | /* 77833 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28148 | /* 77836 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28149 | /* 77842 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28150 | /* 77848 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 28151 | /* 77851 */ GIR_RootConstrainSelectedInstOperands, |
| 28152 | /* 77852 */ // GIR_Coverage, 3862, |
| 28153 | /* 77852 */ GIR_EraseRootFromParent_Done, |
| 28154 | /* 77853 */ // Label 1512: @77853 |
| 28155 | /* 77853 */ GIM_Try, /*On fail goto*//*Label 1513*/ GIMT_Encode4(77946), // Rule ID 3864 // |
| 28156 | /* 77858 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector), |
| 28157 | /* 77863 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 28158 | /* 77866 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 28159 | /* 77869 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 28160 | /* 77872 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28161 | /* 77875 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 28162 | /* 77878 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 28163 | /* 77881 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28164 | /* 77885 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28165 | /* 77889 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28166 | /* 77893 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 28167 | /* 77897 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 28168 | /* 77901 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 28169 | /* 77905 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3706:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHL_by_vecs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh) |
| 28170 | /* 77905 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 28171 | /* 77908 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 28172 | /* 77912 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28173 | /* 77917 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_by_vecs16), |
| 28174 | /* 77920 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28175 | /* 77922 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 28176 | /* 77924 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 28177 | /* 77926 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28178 | /* 77929 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28179 | /* 77935 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28180 | /* 77941 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 28181 | /* 77944 */ GIR_RootConstrainSelectedInstOperands, |
| 28182 | /* 77945 */ // GIR_Coverage, 3864, |
| 28183 | /* 77945 */ GIR_EraseRootFromParent_Done, |
| 28184 | /* 77946 */ // Label 1513: @77946 |
| 28185 | /* 77946 */ GIM_Try, /*On fail goto*//*Label 1514*/ GIMT_Encode4(78039), // Rule ID 3866 // |
| 28186 | /* 77951 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector), |
| 28187 | /* 77956 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 28188 | /* 77959 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 28189 | /* 77962 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 28190 | /* 77965 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28191 | /* 77968 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 28192 | /* 77971 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 28193 | /* 77974 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28194 | /* 77978 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28195 | /* 77982 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28196 | /* 77986 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 28197 | /* 77990 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 28198 | /* 77994 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 28199 | /* 77998 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3706:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHL_by_vecs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh) |
| 28200 | /* 77998 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 28201 | /* 78001 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 28202 | /* 78005 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28203 | /* 78010 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_by_vecs32), |
| 28204 | /* 78013 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28205 | /* 78015 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 28206 | /* 78017 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 28207 | /* 78019 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28208 | /* 78022 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28209 | /* 78028 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28210 | /* 78034 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 28211 | /* 78037 */ GIR_RootConstrainSelectedInstOperands, |
| 28212 | /* 78038 */ // GIR_Coverage, 3866, |
| 28213 | /* 78038 */ GIR_EraseRootFromParent_Done, |
| 28214 | /* 78039 */ // Label 1514: @78039 |
| 28215 | /* 78039 */ GIM_Try, /*On fail goto*//*Label 1515*/ GIMT_Encode4(78132), // Rule ID 3868 // |
| 28216 | /* 78044 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector), |
| 28217 | /* 78049 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 28218 | /* 78052 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 28219 | /* 78055 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 28220 | /* 78058 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28221 | /* 78061 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 28222 | /* 78064 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 28223 | /* 78067 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28224 | /* 78071 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28225 | /* 78075 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28226 | /* 78079 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 28227 | /* 78083 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 28228 | /* 78087 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 28229 | /* 78091 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3706:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHL_by_vecu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh) |
| 28230 | /* 78091 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 28231 | /* 78094 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 28232 | /* 78098 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28233 | /* 78103 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_by_vecu8), |
| 28234 | /* 78106 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28235 | /* 78108 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 28236 | /* 78110 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 28237 | /* 78112 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28238 | /* 78115 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28239 | /* 78121 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28240 | /* 78127 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 28241 | /* 78130 */ GIR_RootConstrainSelectedInstOperands, |
| 28242 | /* 78131 */ // GIR_Coverage, 3868, |
| 28243 | /* 78131 */ GIR_EraseRootFromParent_Done, |
| 28244 | /* 78132 */ // Label 1515: @78132 |
| 28245 | /* 78132 */ GIM_Try, /*On fail goto*//*Label 1516*/ GIMT_Encode4(78225), // Rule ID 3870 // |
| 28246 | /* 78137 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector), |
| 28247 | /* 78142 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 28248 | /* 78145 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 28249 | /* 78148 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 28250 | /* 78151 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28251 | /* 78154 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 28252 | /* 78157 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 28253 | /* 78160 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28254 | /* 78164 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28255 | /* 78168 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28256 | /* 78172 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 28257 | /* 78176 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 28258 | /* 78180 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 28259 | /* 78184 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3706:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHL_by_vecu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh) |
| 28260 | /* 78184 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 28261 | /* 78187 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 28262 | /* 78191 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28263 | /* 78196 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_by_vecu16), |
| 28264 | /* 78199 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28265 | /* 78201 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 28266 | /* 78203 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 28267 | /* 78205 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28268 | /* 78208 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28269 | /* 78214 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28270 | /* 78220 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 28271 | /* 78223 */ GIR_RootConstrainSelectedInstOperands, |
| 28272 | /* 78224 */ // GIR_Coverage, 3870, |
| 28273 | /* 78224 */ GIR_EraseRootFromParent_Done, |
| 28274 | /* 78225 */ // Label 1516: @78225 |
| 28275 | /* 78225 */ GIM_Try, /*On fail goto*//*Label 1517*/ GIMT_Encode4(78318), // Rule ID 3872 // |
| 28276 | /* 78230 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector), |
| 28277 | /* 78235 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 28278 | /* 78238 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 28279 | /* 78241 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 28280 | /* 78244 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28281 | /* 78247 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 28282 | /* 78250 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 28283 | /* 78253 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28284 | /* 78257 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28285 | /* 78261 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28286 | /* 78265 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 28287 | /* 78269 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 28288 | /* 78273 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 28289 | /* 78277 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3706:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHL_by_vecu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh) |
| 28290 | /* 78277 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 28291 | /* 78280 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 28292 | /* 78284 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28293 | /* 78289 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_by_vecu32), |
| 28294 | /* 78292 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28295 | /* 78294 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 28296 | /* 78296 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 28297 | /* 78298 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28298 | /* 78301 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28299 | /* 78307 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28300 | /* 78313 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 28301 | /* 78316 */ GIR_RootConstrainSelectedInstOperands, |
| 28302 | /* 78317 */ // GIR_Coverage, 3872, |
| 28303 | /* 78317 */ GIR_EraseRootFromParent_Done, |
| 28304 | /* 78318 */ // Label 1517: @78318 |
| 28305 | /* 78318 */ GIM_Try, /*On fail goto*//*Label 1518*/ GIMT_Encode4(78411), // Rule ID 3874 // |
| 28306 | /* 78323 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector), |
| 28307 | /* 78328 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 28308 | /* 78331 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 28309 | /* 78334 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 28310 | /* 78337 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28311 | /* 78340 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 28312 | /* 78343 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 28313 | /* 78346 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28314 | /* 78350 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28315 | /* 78354 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28316 | /* 78358 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 28317 | /* 78362 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 28318 | /* 78366 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 28319 | /* 78370 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3706:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VRSHL_by_vecs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh) |
| 28320 | /* 78370 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 28321 | /* 78373 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 28322 | /* 78377 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28323 | /* 78382 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_by_vecs8), |
| 28324 | /* 78385 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28325 | /* 78387 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 28326 | /* 78389 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 28327 | /* 78391 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28328 | /* 78394 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28329 | /* 78400 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28330 | /* 78406 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 28331 | /* 78409 */ GIR_RootConstrainSelectedInstOperands, |
| 28332 | /* 78410 */ // GIR_Coverage, 3874, |
| 28333 | /* 78410 */ GIR_EraseRootFromParent_Done, |
| 28334 | /* 78411 */ // Label 1518: @78411 |
| 28335 | /* 78411 */ GIM_Try, /*On fail goto*//*Label 1519*/ GIMT_Encode4(78504), // Rule ID 3876 // |
| 28336 | /* 78416 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector), |
| 28337 | /* 78421 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 28338 | /* 78424 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 28339 | /* 78427 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 28340 | /* 78430 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28341 | /* 78433 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 28342 | /* 78436 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 28343 | /* 78439 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28344 | /* 78443 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28345 | /* 78447 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28346 | /* 78451 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 28347 | /* 78455 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 28348 | /* 78459 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 28349 | /* 78463 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3706:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VRSHL_by_vecs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh) |
| 28350 | /* 78463 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 28351 | /* 78466 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 28352 | /* 78470 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28353 | /* 78475 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_by_vecs16), |
| 28354 | /* 78478 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28355 | /* 78480 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 28356 | /* 78482 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 28357 | /* 78484 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28358 | /* 78487 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28359 | /* 78493 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28360 | /* 78499 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 28361 | /* 78502 */ GIR_RootConstrainSelectedInstOperands, |
| 28362 | /* 78503 */ // GIR_Coverage, 3876, |
| 28363 | /* 78503 */ GIR_EraseRootFromParent_Done, |
| 28364 | /* 78504 */ // Label 1519: @78504 |
| 28365 | /* 78504 */ GIM_Try, /*On fail goto*//*Label 1520*/ GIMT_Encode4(78597), // Rule ID 3878 // |
| 28366 | /* 78509 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector), |
| 28367 | /* 78514 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 28368 | /* 78517 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 28369 | /* 78520 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 28370 | /* 78523 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28371 | /* 78526 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 28372 | /* 78529 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 28373 | /* 78532 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28374 | /* 78536 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28375 | /* 78540 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28376 | /* 78544 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 28377 | /* 78548 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 28378 | /* 78552 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 28379 | /* 78556 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3706:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VRSHL_by_vecs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh) |
| 28380 | /* 78556 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 28381 | /* 78559 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 28382 | /* 78563 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28383 | /* 78568 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_by_vecs32), |
| 28384 | /* 78571 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28385 | /* 78573 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 28386 | /* 78575 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 28387 | /* 78577 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28388 | /* 78580 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28389 | /* 78586 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28390 | /* 78592 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 28391 | /* 78595 */ GIR_RootConstrainSelectedInstOperands, |
| 28392 | /* 78596 */ // GIR_Coverage, 3878, |
| 28393 | /* 78596 */ GIR_EraseRootFromParent_Done, |
| 28394 | /* 78597 */ // Label 1520: @78597 |
| 28395 | /* 78597 */ GIM_Try, /*On fail goto*//*Label 1521*/ GIMT_Encode4(78690), // Rule ID 3880 // |
| 28396 | /* 78602 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector), |
| 28397 | /* 78607 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 28398 | /* 78610 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 28399 | /* 78613 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 28400 | /* 78616 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28401 | /* 78619 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 28402 | /* 78622 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 28403 | /* 78625 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28404 | /* 78629 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28405 | /* 78633 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28406 | /* 78637 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 28407 | /* 78641 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 28408 | /* 78645 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 28409 | /* 78649 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3706:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VRSHL_by_vecu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh) |
| 28410 | /* 78649 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 28411 | /* 78652 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 28412 | /* 78656 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28413 | /* 78661 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_by_vecu8), |
| 28414 | /* 78664 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28415 | /* 78666 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 28416 | /* 78668 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 28417 | /* 78670 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28418 | /* 78673 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28419 | /* 78679 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28420 | /* 78685 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 28421 | /* 78688 */ GIR_RootConstrainSelectedInstOperands, |
| 28422 | /* 78689 */ // GIR_Coverage, 3880, |
| 28423 | /* 78689 */ GIR_EraseRootFromParent_Done, |
| 28424 | /* 78690 */ // Label 1521: @78690 |
| 28425 | /* 78690 */ GIM_Try, /*On fail goto*//*Label 1522*/ GIMT_Encode4(78783), // Rule ID 3882 // |
| 28426 | /* 78695 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector), |
| 28427 | /* 78700 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 28428 | /* 78703 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 28429 | /* 78706 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 28430 | /* 78709 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28431 | /* 78712 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 28432 | /* 78715 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 28433 | /* 78718 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28434 | /* 78722 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28435 | /* 78726 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28436 | /* 78730 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 28437 | /* 78734 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 28438 | /* 78738 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 28439 | /* 78742 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3706:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VRSHL_by_vecu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh) |
| 28440 | /* 78742 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 28441 | /* 78745 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 28442 | /* 78749 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28443 | /* 78754 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_by_vecu16), |
| 28444 | /* 78757 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28445 | /* 78759 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 28446 | /* 78761 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 28447 | /* 78763 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28448 | /* 78766 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28449 | /* 78772 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28450 | /* 78778 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 28451 | /* 78781 */ GIR_RootConstrainSelectedInstOperands, |
| 28452 | /* 78782 */ // GIR_Coverage, 3882, |
| 28453 | /* 78782 */ GIR_EraseRootFromParent_Done, |
| 28454 | /* 78783 */ // Label 1522: @78783 |
| 28455 | /* 78783 */ GIM_Try, /*On fail goto*//*Label 1523*/ GIMT_Encode4(78876), // Rule ID 3884 // |
| 28456 | /* 78788 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector), |
| 28457 | /* 78793 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 28458 | /* 78796 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 28459 | /* 78799 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 28460 | /* 78802 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28461 | /* 78805 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 28462 | /* 78808 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 28463 | /* 78811 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28464 | /* 78815 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28465 | /* 78819 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28466 | /* 78823 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 28467 | /* 78827 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 28468 | /* 78831 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 28469 | /* 78835 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3706:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VRSHL_by_vecu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh) |
| 28470 | /* 78835 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 28471 | /* 78838 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 28472 | /* 78842 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28473 | /* 78847 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_by_vecu32), |
| 28474 | /* 78850 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28475 | /* 78852 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 28476 | /* 78854 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 28477 | /* 78856 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28478 | /* 78859 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28479 | /* 78865 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28480 | /* 78871 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 28481 | /* 78874 */ GIR_RootConstrainSelectedInstOperands, |
| 28482 | /* 78875 */ // GIR_Coverage, 3884, |
| 28483 | /* 78875 */ GIR_EraseRootFromParent_Done, |
| 28484 | /* 78876 */ // Label 1523: @78876 |
| 28485 | /* 78876 */ GIM_Try, /*On fail goto*//*Label 1524*/ GIMT_Encode4(78954), // Rule ID 4489 // |
| 28486 | /* 78881 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqmovn), |
| 28487 | /* 78886 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 28488 | /* 78889 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 28489 | /* 78892 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 28490 | /* 78895 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28491 | /* 78898 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 28492 | /* 78901 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 28493 | /* 78904 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28494 | /* 78908 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28495 | /* 78912 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28496 | /* 78916 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 28497 | /* 78920 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 28498 | /* 78924 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 28499 | /* 78928 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3677:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQMOVNs32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm) |
| 28500 | /* 78928 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVNs32bh), |
| 28501 | /* 78931 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28502 | /* 78933 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src |
| 28503 | /* 78935 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 28504 | /* 78937 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28505 | /* 78940 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28506 | /* 78946 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28507 | /* 78952 */ GIR_RootConstrainSelectedInstOperands, |
| 28508 | /* 78953 */ // GIR_Coverage, 4489, |
| 28509 | /* 78953 */ GIR_EraseRootFromParent_Done, |
| 28510 | /* 78954 */ // Label 1524: @78954 |
| 28511 | /* 78954 */ GIM_Try, /*On fail goto*//*Label 1525*/ GIMT_Encode4(79032), // Rule ID 4491 // |
| 28512 | /* 78959 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqmovn), |
| 28513 | /* 78964 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 28514 | /* 78967 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 28515 | /* 78970 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 28516 | /* 78973 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28517 | /* 78976 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 28518 | /* 78979 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 28519 | /* 78982 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28520 | /* 78986 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28521 | /* 78990 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28522 | /* 78994 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 28523 | /* 78998 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 28524 | /* 79002 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 28525 | /* 79006 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3677:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQMOVNs32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm) |
| 28526 | /* 79006 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVNs32th), |
| 28527 | /* 79009 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28528 | /* 79011 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src |
| 28529 | /* 79013 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 28530 | /* 79015 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28531 | /* 79018 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28532 | /* 79024 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28533 | /* 79030 */ GIR_RootConstrainSelectedInstOperands, |
| 28534 | /* 79031 */ // GIR_Coverage, 4491, |
| 28535 | /* 79031 */ GIR_EraseRootFromParent_Done, |
| 28536 | /* 79032 */ // Label 1525: @79032 |
| 28537 | /* 79032 */ GIM_Try, /*On fail goto*//*Label 1526*/ GIMT_Encode4(79110), // Rule ID 4493 // |
| 28538 | /* 79037 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqmovn), |
| 28539 | /* 79042 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 28540 | /* 79045 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 28541 | /* 79048 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 28542 | /* 79051 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28543 | /* 79054 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 28544 | /* 79057 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 28545 | /* 79060 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28546 | /* 79064 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28547 | /* 79068 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28548 | /* 79072 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 28549 | /* 79076 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 28550 | /* 79080 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 28551 | /* 79084 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3677:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQMOVNs16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm) |
| 28552 | /* 79084 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVNs16bh), |
| 28553 | /* 79087 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28554 | /* 79089 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src |
| 28555 | /* 79091 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 28556 | /* 79093 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28557 | /* 79096 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28558 | /* 79102 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28559 | /* 79108 */ GIR_RootConstrainSelectedInstOperands, |
| 28560 | /* 79109 */ // GIR_Coverage, 4493, |
| 28561 | /* 79109 */ GIR_EraseRootFromParent_Done, |
| 28562 | /* 79110 */ // Label 1526: @79110 |
| 28563 | /* 79110 */ GIM_Try, /*On fail goto*//*Label 1527*/ GIMT_Encode4(79188), // Rule ID 4495 // |
| 28564 | /* 79115 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqmovn), |
| 28565 | /* 79120 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 28566 | /* 79123 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 28567 | /* 79126 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 28568 | /* 79129 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28569 | /* 79132 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 28570 | /* 79135 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 28571 | /* 79138 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28572 | /* 79142 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28573 | /* 79146 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28574 | /* 79150 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 28575 | /* 79154 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 28576 | /* 79158 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 28577 | /* 79162 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3677:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQMOVNs16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm) |
| 28578 | /* 79162 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVNs16th), |
| 28579 | /* 79165 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28580 | /* 79167 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src |
| 28581 | /* 79169 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 28582 | /* 79171 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28583 | /* 79174 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28584 | /* 79180 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28585 | /* 79186 */ GIR_RootConstrainSelectedInstOperands, |
| 28586 | /* 79187 */ // GIR_Coverage, 4495, |
| 28587 | /* 79187 */ GIR_EraseRootFromParent_Done, |
| 28588 | /* 79188 */ // Label 1527: @79188 |
| 28589 | /* 79188 */ GIM_Try, /*On fail goto*//*Label 1528*/ GIMT_Encode4(79266), // Rule ID 4497 // |
| 28590 | /* 79193 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqmovn), |
| 28591 | /* 79198 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 28592 | /* 79201 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 28593 | /* 79204 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 28594 | /* 79207 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28595 | /* 79210 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 28596 | /* 79213 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 28597 | /* 79216 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28598 | /* 79220 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28599 | /* 79224 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28600 | /* 79228 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 28601 | /* 79232 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 28602 | /* 79236 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 28603 | /* 79240 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3677:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQMOVNu32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm) |
| 28604 | /* 79240 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVNu32bh), |
| 28605 | /* 79243 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28606 | /* 79245 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src |
| 28607 | /* 79247 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 28608 | /* 79249 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28609 | /* 79252 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28610 | /* 79258 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28611 | /* 79264 */ GIR_RootConstrainSelectedInstOperands, |
| 28612 | /* 79265 */ // GIR_Coverage, 4497, |
| 28613 | /* 79265 */ GIR_EraseRootFromParent_Done, |
| 28614 | /* 79266 */ // Label 1528: @79266 |
| 28615 | /* 79266 */ GIM_Try, /*On fail goto*//*Label 1529*/ GIMT_Encode4(79344), // Rule ID 4499 // |
| 28616 | /* 79271 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqmovn), |
| 28617 | /* 79276 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 28618 | /* 79279 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 28619 | /* 79282 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 28620 | /* 79285 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28621 | /* 79288 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 28622 | /* 79291 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 28623 | /* 79294 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28624 | /* 79298 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28625 | /* 79302 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28626 | /* 79306 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 28627 | /* 79310 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 28628 | /* 79314 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 28629 | /* 79318 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3677:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQMOVNu32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm) |
| 28630 | /* 79318 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVNu32th), |
| 28631 | /* 79321 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28632 | /* 79323 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src |
| 28633 | /* 79325 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 28634 | /* 79327 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28635 | /* 79330 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28636 | /* 79336 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28637 | /* 79342 */ GIR_RootConstrainSelectedInstOperands, |
| 28638 | /* 79343 */ // GIR_Coverage, 4499, |
| 28639 | /* 79343 */ GIR_EraseRootFromParent_Done, |
| 28640 | /* 79344 */ // Label 1529: @79344 |
| 28641 | /* 79344 */ GIM_Try, /*On fail goto*//*Label 1530*/ GIMT_Encode4(79422), // Rule ID 4501 // |
| 28642 | /* 79349 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqmovn), |
| 28643 | /* 79354 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 28644 | /* 79357 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 28645 | /* 79360 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 28646 | /* 79363 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28647 | /* 79366 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 28648 | /* 79369 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 28649 | /* 79372 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28650 | /* 79376 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28651 | /* 79380 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28652 | /* 79384 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 28653 | /* 79388 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 28654 | /* 79392 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 28655 | /* 79396 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3677:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQMOVNu16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm) |
| 28656 | /* 79396 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVNu16bh), |
| 28657 | /* 79399 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28658 | /* 79401 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src |
| 28659 | /* 79403 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 28660 | /* 79405 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28661 | /* 79408 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28662 | /* 79414 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28663 | /* 79420 */ GIR_RootConstrainSelectedInstOperands, |
| 28664 | /* 79421 */ // GIR_Coverage, 4501, |
| 28665 | /* 79421 */ GIR_EraseRootFromParent_Done, |
| 28666 | /* 79422 */ // Label 1530: @79422 |
| 28667 | /* 79422 */ GIM_Try, /*On fail goto*//*Label 1531*/ GIMT_Encode4(79500), // Rule ID 4503 // |
| 28668 | /* 79427 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqmovn), |
| 28669 | /* 79432 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 28670 | /* 79435 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 28671 | /* 79438 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 28672 | /* 79441 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28673 | /* 79444 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 28674 | /* 79447 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 28675 | /* 79450 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28676 | /* 79454 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28677 | /* 79458 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28678 | /* 79462 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 28679 | /* 79466 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 28680 | /* 79470 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 28681 | /* 79474 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3677:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQMOVNu16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm) |
| 28682 | /* 79474 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVNu16th), |
| 28683 | /* 79477 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28684 | /* 79479 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src |
| 28685 | /* 79481 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 28686 | /* 79483 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28687 | /* 79486 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28688 | /* 79492 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28689 | /* 79498 */ GIR_RootConstrainSelectedInstOperands, |
| 28690 | /* 79499 */ // GIR_Coverage, 4503, |
| 28691 | /* 79499 */ GIR_EraseRootFromParent_Done, |
| 28692 | /* 79500 */ // Label 1531: @79500 |
| 28693 | /* 79500 */ GIM_Try, /*On fail goto*//*Label 1532*/ GIMT_Encode4(79578), // Rule ID 4505 // |
| 28694 | /* 79505 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqmovn), |
| 28695 | /* 79510 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 28696 | /* 79513 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 28697 | /* 79516 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 28698 | /* 79519 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28699 | /* 79522 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 28700 | /* 79525 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 28701 | /* 79528 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28702 | /* 79532 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28703 | /* 79536 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28704 | /* 79540 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 28705 | /* 79544 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 28706 | /* 79548 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 28707 | /* 79552 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3677:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQMOVUNs32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm) |
| 28708 | /* 79552 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVUNs32bh), |
| 28709 | /* 79555 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28710 | /* 79557 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src |
| 28711 | /* 79559 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 28712 | /* 79561 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28713 | /* 79564 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28714 | /* 79570 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28715 | /* 79576 */ GIR_RootConstrainSelectedInstOperands, |
| 28716 | /* 79577 */ // GIR_Coverage, 4505, |
| 28717 | /* 79577 */ GIR_EraseRootFromParent_Done, |
| 28718 | /* 79578 */ // Label 1532: @79578 |
| 28719 | /* 79578 */ GIM_Try, /*On fail goto*//*Label 1533*/ GIMT_Encode4(79656), // Rule ID 4507 // |
| 28720 | /* 79583 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqmovn), |
| 28721 | /* 79588 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 28722 | /* 79591 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 28723 | /* 79594 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 28724 | /* 79597 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28725 | /* 79600 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 28726 | /* 79603 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 28727 | /* 79606 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28728 | /* 79610 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28729 | /* 79614 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28730 | /* 79618 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 28731 | /* 79622 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 28732 | /* 79626 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 28733 | /* 79630 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3677:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQMOVUNs32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm) |
| 28734 | /* 79630 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVUNs32th), |
| 28735 | /* 79633 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28736 | /* 79635 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src |
| 28737 | /* 79637 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 28738 | /* 79639 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28739 | /* 79642 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28740 | /* 79648 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28741 | /* 79654 */ GIR_RootConstrainSelectedInstOperands, |
| 28742 | /* 79655 */ // GIR_Coverage, 4507, |
| 28743 | /* 79655 */ GIR_EraseRootFromParent_Done, |
| 28744 | /* 79656 */ // Label 1533: @79656 |
| 28745 | /* 79656 */ GIM_Try, /*On fail goto*//*Label 1534*/ GIMT_Encode4(79734), // Rule ID 4509 // |
| 28746 | /* 79661 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqmovn), |
| 28747 | /* 79666 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 28748 | /* 79669 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 28749 | /* 79672 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 28750 | /* 79675 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28751 | /* 79678 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 28752 | /* 79681 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 28753 | /* 79684 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28754 | /* 79688 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28755 | /* 79692 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28756 | /* 79696 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 28757 | /* 79700 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 28758 | /* 79704 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 28759 | /* 79708 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3677:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQMOVUNs16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm) |
| 28760 | /* 79708 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVUNs16bh), |
| 28761 | /* 79711 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28762 | /* 79713 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src |
| 28763 | /* 79715 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 28764 | /* 79717 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28765 | /* 79720 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28766 | /* 79726 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28767 | /* 79732 */ GIR_RootConstrainSelectedInstOperands, |
| 28768 | /* 79733 */ // GIR_Coverage, 4509, |
| 28769 | /* 79733 */ GIR_EraseRootFromParent_Done, |
| 28770 | /* 79734 */ // Label 1534: @79734 |
| 28771 | /* 79734 */ GIM_Try, /*On fail goto*//*Label 1535*/ GIMT_Encode4(79812), // Rule ID 4511 // |
| 28772 | /* 79739 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqmovn), |
| 28773 | /* 79744 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 28774 | /* 79747 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 28775 | /* 79750 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 28776 | /* 79753 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28777 | /* 79756 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 28778 | /* 79759 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 28779 | /* 79762 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28780 | /* 79766 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28781 | /* 79770 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28782 | /* 79774 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 28783 | /* 79778 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 28784 | /* 79782 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 28785 | /* 79786 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3677:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQMOVUNs16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm) |
| 28786 | /* 79786 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVUNs16th), |
| 28787 | /* 79789 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28788 | /* 79791 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src |
| 28789 | /* 79793 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 28790 | /* 79795 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28791 | /* 79798 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28792 | /* 79804 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28793 | /* 79810 */ GIR_RootConstrainSelectedInstOperands, |
| 28794 | /* 79811 */ // GIR_Coverage, 4511, |
| 28795 | /* 79811 */ GIR_EraseRootFromParent_Done, |
| 28796 | /* 79812 */ // Label 1535: @79812 |
| 28797 | /* 79812 */ GIM_Try, /*On fail goto*//*Label 1536*/ GIMT_Encode4(79890), // Rule ID 4701 // |
| 28798 | /* 79817 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar), |
| 28799 | /* 79822 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 28800 | /* 79825 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 28801 | /* 79828 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 28802 | /* 79831 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28803 | /* 79834 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 28804 | /* 79837 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 28805 | /* 79840 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28806 | /* 79844 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28807 | /* 79848 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 28808 | /* 79852 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 28809 | /* 79856 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 28810 | /* 79860 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 28811 | /* 79864 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3704:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHL_qrs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh) |
| 28812 | /* 79864 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_qrs8), |
| 28813 | /* 79867 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28814 | /* 79869 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 28815 | /* 79871 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 28816 | /* 79873 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28817 | /* 79876 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28818 | /* 79882 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28819 | /* 79888 */ GIR_RootConstrainSelectedInstOperands, |
| 28820 | /* 79889 */ // GIR_Coverage, 4701, |
| 28821 | /* 79889 */ GIR_EraseRootFromParent_Done, |
| 28822 | /* 79890 */ // Label 1536: @79890 |
| 28823 | /* 79890 */ GIM_Try, /*On fail goto*//*Label 1537*/ GIMT_Encode4(79968), // Rule ID 4703 // |
| 28824 | /* 79895 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar), |
| 28825 | /* 79900 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 28826 | /* 79903 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 28827 | /* 79906 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 28828 | /* 79909 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28829 | /* 79912 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 28830 | /* 79915 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 28831 | /* 79918 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28832 | /* 79922 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28833 | /* 79926 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 28834 | /* 79930 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 28835 | /* 79934 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 28836 | /* 79938 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 28837 | /* 79942 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3704:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHL_qrs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh) |
| 28838 | /* 79942 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_qrs16), |
| 28839 | /* 79945 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28840 | /* 79947 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 28841 | /* 79949 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 28842 | /* 79951 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28843 | /* 79954 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28844 | /* 79960 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28845 | /* 79966 */ GIR_RootConstrainSelectedInstOperands, |
| 28846 | /* 79967 */ // GIR_Coverage, 4703, |
| 28847 | /* 79967 */ GIR_EraseRootFromParent_Done, |
| 28848 | /* 79968 */ // Label 1537: @79968 |
| 28849 | /* 79968 */ GIM_Try, /*On fail goto*//*Label 1538*/ GIMT_Encode4(80046), // Rule ID 4705 // |
| 28850 | /* 79973 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar), |
| 28851 | /* 79978 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 28852 | /* 79981 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 28853 | /* 79984 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 28854 | /* 79987 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28855 | /* 79990 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 28856 | /* 79993 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 28857 | /* 79996 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28858 | /* 80000 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28859 | /* 80004 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 28860 | /* 80008 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 28861 | /* 80012 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 28862 | /* 80016 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 28863 | /* 80020 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3704:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHL_qrs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh) |
| 28864 | /* 80020 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_qrs32), |
| 28865 | /* 80023 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28866 | /* 80025 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 28867 | /* 80027 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 28868 | /* 80029 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28869 | /* 80032 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28870 | /* 80038 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28871 | /* 80044 */ GIR_RootConstrainSelectedInstOperands, |
| 28872 | /* 80045 */ // GIR_Coverage, 4705, |
| 28873 | /* 80045 */ GIR_EraseRootFromParent_Done, |
| 28874 | /* 80046 */ // Label 1538: @80046 |
| 28875 | /* 80046 */ GIM_Try, /*On fail goto*//*Label 1539*/ GIMT_Encode4(80124), // Rule ID 4707 // |
| 28876 | /* 80051 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar), |
| 28877 | /* 80056 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 28878 | /* 80059 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 28879 | /* 80062 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 28880 | /* 80065 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28881 | /* 80068 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 28882 | /* 80071 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 28883 | /* 80074 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28884 | /* 80078 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28885 | /* 80082 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 28886 | /* 80086 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 28887 | /* 80090 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 28888 | /* 80094 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 28889 | /* 80098 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3704:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHL_qru8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh) |
| 28890 | /* 80098 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_qru8), |
| 28891 | /* 80101 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28892 | /* 80103 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 28893 | /* 80105 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 28894 | /* 80107 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28895 | /* 80110 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28896 | /* 80116 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28897 | /* 80122 */ GIR_RootConstrainSelectedInstOperands, |
| 28898 | /* 80123 */ // GIR_Coverage, 4707, |
| 28899 | /* 80123 */ GIR_EraseRootFromParent_Done, |
| 28900 | /* 80124 */ // Label 1539: @80124 |
| 28901 | /* 80124 */ GIM_Try, /*On fail goto*//*Label 1540*/ GIMT_Encode4(80202), // Rule ID 4709 // |
| 28902 | /* 80129 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar), |
| 28903 | /* 80134 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 28904 | /* 80137 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 28905 | /* 80140 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 28906 | /* 80143 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28907 | /* 80146 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 28908 | /* 80149 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 28909 | /* 80152 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28910 | /* 80156 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28911 | /* 80160 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 28912 | /* 80164 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 28913 | /* 80168 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 28914 | /* 80172 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 28915 | /* 80176 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3704:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHL_qru16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh) |
| 28916 | /* 80176 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_qru16), |
| 28917 | /* 80179 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28918 | /* 80181 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 28919 | /* 80183 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 28920 | /* 80185 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28921 | /* 80188 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28922 | /* 80194 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28923 | /* 80200 */ GIR_RootConstrainSelectedInstOperands, |
| 28924 | /* 80201 */ // GIR_Coverage, 4709, |
| 28925 | /* 80201 */ GIR_EraseRootFromParent_Done, |
| 28926 | /* 80202 */ // Label 1540: @80202 |
| 28927 | /* 80202 */ GIM_Try, /*On fail goto*//*Label 1541*/ GIMT_Encode4(80280), // Rule ID 4711 // |
| 28928 | /* 80207 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar), |
| 28929 | /* 80212 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 28930 | /* 80215 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 28931 | /* 80218 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 28932 | /* 80221 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28933 | /* 80224 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 28934 | /* 80227 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 28935 | /* 80230 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28936 | /* 80234 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28937 | /* 80238 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 28938 | /* 80242 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 28939 | /* 80246 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 28940 | /* 80250 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 28941 | /* 80254 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3704:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHL_qru32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh) |
| 28942 | /* 80254 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_qru32), |
| 28943 | /* 80257 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28944 | /* 80259 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 28945 | /* 80261 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 28946 | /* 80263 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28947 | /* 80266 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28948 | /* 80272 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28949 | /* 80278 */ GIR_RootConstrainSelectedInstOperands, |
| 28950 | /* 80279 */ // GIR_Coverage, 4711, |
| 28951 | /* 80279 */ GIR_EraseRootFromParent_Done, |
| 28952 | /* 80280 */ // Label 1541: @80280 |
| 28953 | /* 80280 */ GIM_Try, /*On fail goto*//*Label 1542*/ GIMT_Encode4(80358), // Rule ID 4713 // |
| 28954 | /* 80285 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar), |
| 28955 | /* 80290 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 28956 | /* 80293 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 28957 | /* 80296 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 28958 | /* 80299 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28959 | /* 80302 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 28960 | /* 80305 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 28961 | /* 80308 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28962 | /* 80312 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28963 | /* 80316 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 28964 | /* 80320 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 28965 | /* 80324 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 28966 | /* 80328 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 28967 | /* 80332 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3704:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VRSHL_qrs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh) |
| 28968 | /* 80332 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_qrs8), |
| 28969 | /* 80335 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28970 | /* 80337 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 28971 | /* 80339 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 28972 | /* 80341 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28973 | /* 80344 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28974 | /* 80350 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28975 | /* 80356 */ GIR_RootConstrainSelectedInstOperands, |
| 28976 | /* 80357 */ // GIR_Coverage, 4713, |
| 28977 | /* 80357 */ GIR_EraseRootFromParent_Done, |
| 28978 | /* 80358 */ // Label 1542: @80358 |
| 28979 | /* 80358 */ GIM_Try, /*On fail goto*//*Label 1543*/ GIMT_Encode4(80436), // Rule ID 4715 // |
| 28980 | /* 80363 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar), |
| 28981 | /* 80368 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 28982 | /* 80371 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 28983 | /* 80374 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 28984 | /* 80377 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28985 | /* 80380 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 28986 | /* 80383 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 28987 | /* 80386 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28988 | /* 80390 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28989 | /* 80394 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 28990 | /* 80398 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 28991 | /* 80402 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 28992 | /* 80406 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 28993 | /* 80410 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3704:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VRSHL_qrs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh) |
| 28994 | /* 80410 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_qrs16), |
| 28995 | /* 80413 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28996 | /* 80415 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 28997 | /* 80417 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 28998 | /* 80419 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28999 | /* 80422 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29000 | /* 80428 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29001 | /* 80434 */ GIR_RootConstrainSelectedInstOperands, |
| 29002 | /* 80435 */ // GIR_Coverage, 4715, |
| 29003 | /* 80435 */ GIR_EraseRootFromParent_Done, |
| 29004 | /* 80436 */ // Label 1543: @80436 |
| 29005 | /* 80436 */ GIM_Try, /*On fail goto*//*Label 1544*/ GIMT_Encode4(80514), // Rule ID 4717 // |
| 29006 | /* 80441 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar), |
| 29007 | /* 80446 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 29008 | /* 80449 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 29009 | /* 80452 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 29010 | /* 80455 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 29011 | /* 80458 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 29012 | /* 80461 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 29013 | /* 80464 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29014 | /* 80468 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29015 | /* 80472 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 29016 | /* 80476 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 29017 | /* 80480 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 29018 | /* 80484 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 29019 | /* 80488 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3704:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VRSHL_qrs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh) |
| 29020 | /* 80488 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_qrs32), |
| 29021 | /* 80491 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29022 | /* 80493 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 29023 | /* 80495 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 29024 | /* 80497 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29025 | /* 80500 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29026 | /* 80506 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29027 | /* 80512 */ GIR_RootConstrainSelectedInstOperands, |
| 29028 | /* 80513 */ // GIR_Coverage, 4717, |
| 29029 | /* 80513 */ GIR_EraseRootFromParent_Done, |
| 29030 | /* 80514 */ // Label 1544: @80514 |
| 29031 | /* 80514 */ GIM_Try, /*On fail goto*//*Label 1545*/ GIMT_Encode4(80592), // Rule ID 4719 // |
| 29032 | /* 80519 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar), |
| 29033 | /* 80524 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 29034 | /* 80527 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 29035 | /* 80530 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 29036 | /* 80533 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 29037 | /* 80536 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 29038 | /* 80539 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 29039 | /* 80542 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29040 | /* 80546 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29041 | /* 80550 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 29042 | /* 80554 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 29043 | /* 80558 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 29044 | /* 80562 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 29045 | /* 80566 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3704:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VRSHL_qru8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh) |
| 29046 | /* 80566 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_qru8), |
| 29047 | /* 80569 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29048 | /* 80571 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 29049 | /* 80573 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 29050 | /* 80575 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29051 | /* 80578 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29052 | /* 80584 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29053 | /* 80590 */ GIR_RootConstrainSelectedInstOperands, |
| 29054 | /* 80591 */ // GIR_Coverage, 4719, |
| 29055 | /* 80591 */ GIR_EraseRootFromParent_Done, |
| 29056 | /* 80592 */ // Label 1545: @80592 |
| 29057 | /* 80592 */ GIM_Try, /*On fail goto*//*Label 1546*/ GIMT_Encode4(80670), // Rule ID 4721 // |
| 29058 | /* 80597 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar), |
| 29059 | /* 80602 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 29060 | /* 80605 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 29061 | /* 80608 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 29062 | /* 80611 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 29063 | /* 80614 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 29064 | /* 80617 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 29065 | /* 80620 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29066 | /* 80624 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29067 | /* 80628 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 29068 | /* 80632 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 29069 | /* 80636 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 29070 | /* 80640 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 29071 | /* 80644 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3704:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VRSHL_qru16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh) |
| 29072 | /* 80644 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_qru16), |
| 29073 | /* 80647 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29074 | /* 80649 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 29075 | /* 80651 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 29076 | /* 80653 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29077 | /* 80656 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29078 | /* 80662 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29079 | /* 80668 */ GIR_RootConstrainSelectedInstOperands, |
| 29080 | /* 80669 */ // GIR_Coverage, 4721, |
| 29081 | /* 80669 */ GIR_EraseRootFromParent_Done, |
| 29082 | /* 80670 */ // Label 1546: @80670 |
| 29083 | /* 80670 */ GIM_Try, /*On fail goto*//*Label 1547*/ GIMT_Encode4(80748), // Rule ID 4723 // |
| 29084 | /* 80675 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar), |
| 29085 | /* 80680 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 29086 | /* 80683 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 29087 | /* 80686 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 29088 | /* 80689 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 29089 | /* 80692 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 29090 | /* 80695 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 29091 | /* 80698 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29092 | /* 80702 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29093 | /* 80706 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 29094 | /* 80710 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 29095 | /* 80714 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 29096 | /* 80718 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 29097 | /* 80722 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3704:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VRSHL_qru32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh) |
| 29098 | /* 80722 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_qru32), |
| 29099 | /* 80725 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29100 | /* 80727 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 29101 | /* 80729 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 29102 | /* 80731 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29103 | /* 80734 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29104 | /* 80740 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29105 | /* 80746 */ GIR_RootConstrainSelectedInstOperands, |
| 29106 | /* 80747 */ // GIR_Coverage, 4723, |
| 29107 | /* 80747 */ GIR_EraseRootFromParent_Done, |
| 29108 | /* 80748 */ // Label 1547: @80748 |
| 29109 | /* 80748 */ GIM_Try, /*On fail goto*//*Label 1548*/ GIMT_Encode4(80826), // Rule ID 4725 // |
| 29110 | /* 80753 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar), |
| 29111 | /* 80758 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 29112 | /* 80761 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 29113 | /* 80764 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 29114 | /* 80767 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 29115 | /* 80770 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 29116 | /* 80773 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 29117 | /* 80776 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29118 | /* 80780 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29119 | /* 80784 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 29120 | /* 80788 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 29121 | /* 80792 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 29122 | /* 80796 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 29123 | /* 80800 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3704:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHL_qrs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh) |
| 29124 | /* 80800 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_qrs8), |
| 29125 | /* 80803 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29126 | /* 80805 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 29127 | /* 80807 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 29128 | /* 80809 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29129 | /* 80812 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29130 | /* 80818 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29131 | /* 80824 */ GIR_RootConstrainSelectedInstOperands, |
| 29132 | /* 80825 */ // GIR_Coverage, 4725, |
| 29133 | /* 80825 */ GIR_EraseRootFromParent_Done, |
| 29134 | /* 80826 */ // Label 1548: @80826 |
| 29135 | /* 80826 */ GIM_Try, /*On fail goto*//*Label 1549*/ GIMT_Encode4(80904), // Rule ID 4727 // |
| 29136 | /* 80831 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar), |
| 29137 | /* 80836 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 29138 | /* 80839 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 29139 | /* 80842 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 29140 | /* 80845 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 29141 | /* 80848 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 29142 | /* 80851 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 29143 | /* 80854 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29144 | /* 80858 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29145 | /* 80862 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 29146 | /* 80866 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 29147 | /* 80870 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 29148 | /* 80874 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 29149 | /* 80878 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3704:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHL_qrs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh) |
| 29150 | /* 80878 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_qrs16), |
| 29151 | /* 80881 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29152 | /* 80883 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 29153 | /* 80885 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 29154 | /* 80887 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29155 | /* 80890 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29156 | /* 80896 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29157 | /* 80902 */ GIR_RootConstrainSelectedInstOperands, |
| 29158 | /* 80903 */ // GIR_Coverage, 4727, |
| 29159 | /* 80903 */ GIR_EraseRootFromParent_Done, |
| 29160 | /* 80904 */ // Label 1549: @80904 |
| 29161 | /* 80904 */ GIM_Try, /*On fail goto*//*Label 1550*/ GIMT_Encode4(80982), // Rule ID 4729 // |
| 29162 | /* 80909 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar), |
| 29163 | /* 80914 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 29164 | /* 80917 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 29165 | /* 80920 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 29166 | /* 80923 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 29167 | /* 80926 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 29168 | /* 80929 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 29169 | /* 80932 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29170 | /* 80936 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29171 | /* 80940 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 29172 | /* 80944 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 29173 | /* 80948 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 29174 | /* 80952 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 29175 | /* 80956 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3704:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHL_qrs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh) |
| 29176 | /* 80956 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_qrs32), |
| 29177 | /* 80959 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29178 | /* 80961 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 29179 | /* 80963 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 29180 | /* 80965 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29181 | /* 80968 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29182 | /* 80974 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29183 | /* 80980 */ GIR_RootConstrainSelectedInstOperands, |
| 29184 | /* 80981 */ // GIR_Coverage, 4729, |
| 29185 | /* 80981 */ GIR_EraseRootFromParent_Done, |
| 29186 | /* 80982 */ // Label 1550: @80982 |
| 29187 | /* 80982 */ GIM_Try, /*On fail goto*//*Label 1551*/ GIMT_Encode4(81060), // Rule ID 4731 // |
| 29188 | /* 80987 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar), |
| 29189 | /* 80992 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 29190 | /* 80995 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 29191 | /* 80998 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 29192 | /* 81001 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 29193 | /* 81004 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 29194 | /* 81007 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 29195 | /* 81010 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29196 | /* 81014 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29197 | /* 81018 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 29198 | /* 81022 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 29199 | /* 81026 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 29200 | /* 81030 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 29201 | /* 81034 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3704:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHL_qru8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh) |
| 29202 | /* 81034 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_qru8), |
| 29203 | /* 81037 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29204 | /* 81039 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 29205 | /* 81041 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 29206 | /* 81043 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29207 | /* 81046 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29208 | /* 81052 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29209 | /* 81058 */ GIR_RootConstrainSelectedInstOperands, |
| 29210 | /* 81059 */ // GIR_Coverage, 4731, |
| 29211 | /* 81059 */ GIR_EraseRootFromParent_Done, |
| 29212 | /* 81060 */ // Label 1551: @81060 |
| 29213 | /* 81060 */ GIM_Try, /*On fail goto*//*Label 1552*/ GIMT_Encode4(81138), // Rule ID 4733 // |
| 29214 | /* 81065 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar), |
| 29215 | /* 81070 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 29216 | /* 81073 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 29217 | /* 81076 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 29218 | /* 81079 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 29219 | /* 81082 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 29220 | /* 81085 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 29221 | /* 81088 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29222 | /* 81092 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29223 | /* 81096 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 29224 | /* 81100 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 29225 | /* 81104 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 29226 | /* 81108 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 29227 | /* 81112 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3704:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHL_qru16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh) |
| 29228 | /* 81112 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_qru16), |
| 29229 | /* 81115 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29230 | /* 81117 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 29231 | /* 81119 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 29232 | /* 81121 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29233 | /* 81124 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29234 | /* 81130 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29235 | /* 81136 */ GIR_RootConstrainSelectedInstOperands, |
| 29236 | /* 81137 */ // GIR_Coverage, 4733, |
| 29237 | /* 81137 */ GIR_EraseRootFromParent_Done, |
| 29238 | /* 81138 */ // Label 1552: @81138 |
| 29239 | /* 81138 */ GIM_Try, /*On fail goto*//*Label 1553*/ GIMT_Encode4(81216), // Rule ID 4735 // |
| 29240 | /* 81143 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar), |
| 29241 | /* 81148 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 29242 | /* 81151 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 29243 | /* 81154 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 29244 | /* 81157 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 29245 | /* 81160 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 29246 | /* 81163 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 29247 | /* 81166 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29248 | /* 81170 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29249 | /* 81174 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 29250 | /* 81178 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 29251 | /* 81182 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 29252 | /* 81186 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 29253 | /* 81190 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3704:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHL_qru32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh) |
| 29254 | /* 81190 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_qru32), |
| 29255 | /* 81193 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29256 | /* 81195 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 29257 | /* 81197 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 29258 | /* 81199 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29259 | /* 81202 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29260 | /* 81208 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29261 | /* 81214 */ GIR_RootConstrainSelectedInstOperands, |
| 29262 | /* 81215 */ // GIR_Coverage, 4735, |
| 29263 | /* 81215 */ GIR_EraseRootFromParent_Done, |
| 29264 | /* 81216 */ // Label 1553: @81216 |
| 29265 | /* 81216 */ GIM_Try, /*On fail goto*//*Label 1554*/ GIMT_Encode4(81294), // Rule ID 4737 // |
| 29266 | /* 81221 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar), |
| 29267 | /* 81226 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 29268 | /* 81229 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 29269 | /* 81232 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 29270 | /* 81235 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 29271 | /* 81238 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 29272 | /* 81241 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 29273 | /* 81244 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29274 | /* 81248 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29275 | /* 81252 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 29276 | /* 81256 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 29277 | /* 81260 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 29278 | /* 81264 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 29279 | /* 81268 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3704:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHL_qrs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh) |
| 29280 | /* 81268 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_qrs8), |
| 29281 | /* 81271 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29282 | /* 81273 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 29283 | /* 81275 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 29284 | /* 81277 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29285 | /* 81280 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29286 | /* 81286 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29287 | /* 81292 */ GIR_RootConstrainSelectedInstOperands, |
| 29288 | /* 81293 */ // GIR_Coverage, 4737, |
| 29289 | /* 81293 */ GIR_EraseRootFromParent_Done, |
| 29290 | /* 81294 */ // Label 1554: @81294 |
| 29291 | /* 81294 */ GIM_Try, /*On fail goto*//*Label 1555*/ GIMT_Encode4(81372), // Rule ID 4739 // |
| 29292 | /* 81299 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar), |
| 29293 | /* 81304 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 29294 | /* 81307 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 29295 | /* 81310 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 29296 | /* 81313 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 29297 | /* 81316 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 29298 | /* 81319 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 29299 | /* 81322 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29300 | /* 81326 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29301 | /* 81330 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 29302 | /* 81334 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 29303 | /* 81338 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 29304 | /* 81342 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 29305 | /* 81346 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3704:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHL_qrs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh) |
| 29306 | /* 81346 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_qrs16), |
| 29307 | /* 81349 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29308 | /* 81351 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 29309 | /* 81353 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 29310 | /* 81355 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29311 | /* 81358 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29312 | /* 81364 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29313 | /* 81370 */ GIR_RootConstrainSelectedInstOperands, |
| 29314 | /* 81371 */ // GIR_Coverage, 4739, |
| 29315 | /* 81371 */ GIR_EraseRootFromParent_Done, |
| 29316 | /* 81372 */ // Label 1555: @81372 |
| 29317 | /* 81372 */ GIM_Try, /*On fail goto*//*Label 1556*/ GIMT_Encode4(81450), // Rule ID 4741 // |
| 29318 | /* 81377 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar), |
| 29319 | /* 81382 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 29320 | /* 81385 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 29321 | /* 81388 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 29322 | /* 81391 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 29323 | /* 81394 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 29324 | /* 81397 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 29325 | /* 81400 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29326 | /* 81404 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29327 | /* 81408 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 29328 | /* 81412 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 29329 | /* 81416 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 29330 | /* 81420 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 29331 | /* 81424 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3704:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHL_qrs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh) |
| 29332 | /* 81424 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_qrs32), |
| 29333 | /* 81427 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29334 | /* 81429 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 29335 | /* 81431 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 29336 | /* 81433 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29337 | /* 81436 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29338 | /* 81442 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29339 | /* 81448 */ GIR_RootConstrainSelectedInstOperands, |
| 29340 | /* 81449 */ // GIR_Coverage, 4741, |
| 29341 | /* 81449 */ GIR_EraseRootFromParent_Done, |
| 29342 | /* 81450 */ // Label 1556: @81450 |
| 29343 | /* 81450 */ GIM_Try, /*On fail goto*//*Label 1557*/ GIMT_Encode4(81528), // Rule ID 4743 // |
| 29344 | /* 81455 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar), |
| 29345 | /* 81460 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 29346 | /* 81463 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 29347 | /* 81466 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 29348 | /* 81469 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 29349 | /* 81472 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 29350 | /* 81475 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 29351 | /* 81478 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29352 | /* 81482 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29353 | /* 81486 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 29354 | /* 81490 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 29355 | /* 81494 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 29356 | /* 81498 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 29357 | /* 81502 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3704:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHL_qru8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh) |
| 29358 | /* 81502 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_qru8), |
| 29359 | /* 81505 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29360 | /* 81507 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 29361 | /* 81509 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 29362 | /* 81511 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29363 | /* 81514 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29364 | /* 81520 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29365 | /* 81526 */ GIR_RootConstrainSelectedInstOperands, |
| 29366 | /* 81527 */ // GIR_Coverage, 4743, |
| 29367 | /* 81527 */ GIR_EraseRootFromParent_Done, |
| 29368 | /* 81528 */ // Label 1557: @81528 |
| 29369 | /* 81528 */ GIM_Try, /*On fail goto*//*Label 1558*/ GIMT_Encode4(81606), // Rule ID 4745 // |
| 29370 | /* 81533 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar), |
| 29371 | /* 81538 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 29372 | /* 81541 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 29373 | /* 81544 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 29374 | /* 81547 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 29375 | /* 81550 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 29376 | /* 81553 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 29377 | /* 81556 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29378 | /* 81560 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29379 | /* 81564 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 29380 | /* 81568 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 29381 | /* 81572 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 29382 | /* 81576 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 29383 | /* 81580 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3704:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHL_qru16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh) |
| 29384 | /* 81580 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_qru16), |
| 29385 | /* 81583 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29386 | /* 81585 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 29387 | /* 81587 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 29388 | /* 81589 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29389 | /* 81592 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29390 | /* 81598 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29391 | /* 81604 */ GIR_RootConstrainSelectedInstOperands, |
| 29392 | /* 81605 */ // GIR_Coverage, 4745, |
| 29393 | /* 81605 */ GIR_EraseRootFromParent_Done, |
| 29394 | /* 81606 */ // Label 1558: @81606 |
| 29395 | /* 81606 */ GIM_Try, /*On fail goto*//*Label 1559*/ GIMT_Encode4(81684), // Rule ID 4747 // |
| 29396 | /* 81611 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar), |
| 29397 | /* 81616 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 29398 | /* 81619 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 29399 | /* 81622 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 29400 | /* 81625 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 29401 | /* 81628 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 29402 | /* 81631 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 29403 | /* 81634 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29404 | /* 81638 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29405 | /* 81642 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 29406 | /* 81646 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 29407 | /* 81650 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 29408 | /* 81654 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 29409 | /* 81658 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3704:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHL_qru32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh) |
| 29410 | /* 81658 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_qru32), |
| 29411 | /* 81661 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29412 | /* 81663 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 29413 | /* 81665 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 29414 | /* 81667 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29415 | /* 81670 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29416 | /* 81676 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29417 | /* 81682 */ GIR_RootConstrainSelectedInstOperands, |
| 29418 | /* 81683 */ // GIR_Coverage, 4747, |
| 29419 | /* 81683 */ GIR_EraseRootFromParent_Done, |
| 29420 | /* 81684 */ // Label 1559: @81684 |
| 29421 | /* 81684 */ GIM_Try, /*On fail goto*//*Label 1560*/ GIMT_Encode4(81820), // Rule ID 2690 // |
| 29422 | /* 81689 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 29423 | /* 81692 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vtbx3), |
| 29424 | /* 81697 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, |
| 29425 | /* 81700 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 29426 | /* 81703 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 29427 | /* 81706 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s8, |
| 29428 | /* 81709 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s8, |
| 29429 | /* 81712 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s8, |
| 29430 | /* 81715 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 29431 | /* 81719 */ // (intrinsic_wo_chain:{ *:[v8i8] } 3863:{ *:[iPTR] }, v8i8:{ *:[v8i8] }:$orig, v8i8:{ *:[v8i8] }:$Vn0, v8i8:{ *:[v8i8] }:$Vn1, v8i8:{ *:[v8i8] }:$Vn2, v8i8:{ *:[v8i8] }:$Vm) => (VTBX3Pseudo:{ *:[v8i8] } v8i8:{ *:[v8i8] }:$orig, (REG_SEQUENCE:{ *:[v4i64] } QQPR:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn0, dsub_0:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn1, dsub_1:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn2, dsub_2:{ *:[i32] }, (IMPLICIT_DEF:{ *:[v8i8] }), dsub_3:{ *:[i32] }), v8i8:{ *:[v8i8] }:$Vm) |
| 29432 | /* 81719 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s8, |
| 29433 | /* 81722 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 29434 | /* 81726 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29435 | /* 81731 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 29436 | /* 81733 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s64, |
| 29437 | /* 81736 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 29438 | /* 81740 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29439 | /* 81745 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // Vn0 |
| 29440 | /* 81749 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/1, |
| 29441 | /* 81752 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // Vn1 |
| 29442 | /* 81756 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/2, |
| 29443 | /* 81759 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/5, // Vn2 |
| 29444 | /* 81763 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 29445 | /* 81766 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 29446 | /* 81769 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/4, |
| 29447 | /* 81772 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::QQPRRegClassID), |
| 29448 | /* 81777 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(ARM::DPRRegClassID), |
| 29449 | /* 81782 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(ARM::DPRRegClassID), |
| 29450 | /* 81787 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/5, GIMT_Encode2(ARM::DPRRegClassID), |
| 29451 | /* 81792 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/7, GIMT_Encode2(ARM::DPRRegClassID), |
| 29452 | /* 81797 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VTBX3Pseudo), |
| 29453 | /* 81800 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 29454 | /* 81802 */ GIR_RootToRootCopy, /*OpIdx*/2, // orig |
| 29455 | /* 81804 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 29456 | /* 81807 */ GIR_RootToRootCopy, /*OpIdx*/6, // Vm |
| 29457 | /* 81809 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 29458 | /* 81812 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29459 | /* 81818 */ GIR_RootConstrainSelectedInstOperands, |
| 29460 | /* 81819 */ // GIR_Coverage, 2690, |
| 29461 | /* 81819 */ GIR_EraseRootFromParent_Done, |
| 29462 | /* 81820 */ // Label 1560: @81820 |
| 29463 | /* 81820 */ GIM_Try, /*On fail goto*//*Label 1561*/ GIMT_Encode4(81941), // Rule ID 2691 // |
| 29464 | /* 81825 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 29465 | /* 81828 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vtbl4), |
| 29466 | /* 81833 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, |
| 29467 | /* 81836 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 29468 | /* 81839 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 29469 | /* 81842 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s8, |
| 29470 | /* 81845 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s8, |
| 29471 | /* 81848 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s8, |
| 29472 | /* 81851 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 29473 | /* 81855 */ // (intrinsic_wo_chain:{ *:[v8i8] } 3860:{ *:[iPTR] }, v8i8:{ *:[v8i8] }:$Vn0, v8i8:{ *:[v8i8] }:$Vn1, v8i8:{ *:[v8i8] }:$Vn2, v8i8:{ *:[v8i8] }:$Vn3, v8i8:{ *:[v8i8] }:$Vm) => (VTBL4Pseudo:{ *:[v8i8] } (REG_SEQUENCE:{ *:[v4i64] } QQPR:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn0, dsub_0:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn1, dsub_1:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn2, dsub_2:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn3, dsub_3:{ *:[i32] }), v8i8:{ *:[v8i8] }:$Vm) |
| 29474 | /* 81855 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s64, |
| 29475 | /* 81858 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 29476 | /* 81862 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29477 | /* 81867 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Vn0 |
| 29478 | /* 81871 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/1, |
| 29479 | /* 81874 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // Vn1 |
| 29480 | /* 81878 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/2, |
| 29481 | /* 81881 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // Vn2 |
| 29482 | /* 81885 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 29483 | /* 81888 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/5, // Vn3 |
| 29484 | /* 81892 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/4, |
| 29485 | /* 81895 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::QQPRRegClassID), |
| 29486 | /* 81900 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(ARM::DPRRegClassID), |
| 29487 | /* 81905 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(ARM::DPRRegClassID), |
| 29488 | /* 81910 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/5, GIMT_Encode2(ARM::DPRRegClassID), |
| 29489 | /* 81915 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/7, GIMT_Encode2(ARM::DPRRegClassID), |
| 29490 | /* 81920 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VTBL4Pseudo), |
| 29491 | /* 81923 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 29492 | /* 81925 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 29493 | /* 81928 */ GIR_RootToRootCopy, /*OpIdx*/6, // Vm |
| 29494 | /* 81930 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 29495 | /* 81933 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29496 | /* 81939 */ GIR_RootConstrainSelectedInstOperands, |
| 29497 | /* 81940 */ // GIR_Coverage, 2691, |
| 29498 | /* 81940 */ GIR_EraseRootFromParent_Done, |
| 29499 | /* 81941 */ // Label 1561: @81941 |
| 29500 | /* 81941 */ GIM_Reject, |
| 29501 | /* 81942 */ // Label 1499: @81942 |
| 29502 | /* 81942 */ GIM_Try, /*On fail goto*//*Label 1562*/ GIMT_Encode4(86835), |
| 29503 | /* 81947 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/8, |
| 29504 | /* 81950 */ GIM_Try, /*On fail goto*//*Label 1563*/ GIMT_Encode4(82038), // Rule ID 3181 // |
| 29505 | /* 81955 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 29506 | /* 81958 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava), |
| 29507 | /* 81963 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 29508 | /* 81966 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 29509 | /* 81969 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 29510 | /* 81972 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 29511 | /* 81975 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 29512 | /* 81978 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v16s8, |
| 29513 | /* 81981 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v16s8, |
| 29514 | /* 81984 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 29515 | /* 81988 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 29516 | /* 81992 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 29517 | /* 81996 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 29518 | /* 82000 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 29519 | /* 82004 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29520 | /* 82008 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29521 | /* 82012 */ // (intrinsic_wo_chain:{ *:[i32] } 3659:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VMLADAVs8:{ *:[i32] } MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) |
| 29522 | /* 82012 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVs8), |
| 29523 | /* 82015 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 29524 | /* 82017 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 29525 | /* 82019 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 29526 | /* 82021 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29527 | /* 82024 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29528 | /* 82030 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29529 | /* 82036 */ GIR_RootConstrainSelectedInstOperands, |
| 29530 | /* 82037 */ // GIR_Coverage, 3181, |
| 29531 | /* 82037 */ GIR_EraseRootFromParent_Done, |
| 29532 | /* 82038 */ // Label 1563: @82038 |
| 29533 | /* 82038 */ GIM_Try, /*On fail goto*//*Label 1564*/ GIMT_Encode4(82126), // Rule ID 3185 // |
| 29534 | /* 82043 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 29535 | /* 82046 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava), |
| 29536 | /* 82051 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 29537 | /* 82054 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 29538 | /* 82057 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 29539 | /* 82060 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 29540 | /* 82063 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 29541 | /* 82066 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v16s8, |
| 29542 | /* 82069 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v16s8, |
| 29543 | /* 82072 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 29544 | /* 82076 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 29545 | /* 82080 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 29546 | /* 82084 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 29547 | /* 82088 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 29548 | /* 82092 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29549 | /* 82096 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29550 | /* 82100 */ // (intrinsic_wo_chain:{ *:[i32] } 3659:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VMLADAVxs8:{ *:[i32] } MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) |
| 29551 | /* 82100 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVxs8), |
| 29552 | /* 82103 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 29553 | /* 82105 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 29554 | /* 82107 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 29555 | /* 82109 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29556 | /* 82112 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29557 | /* 82118 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29558 | /* 82124 */ GIR_RootConstrainSelectedInstOperands, |
| 29559 | /* 82125 */ // GIR_Coverage, 3185, |
| 29560 | /* 82125 */ GIR_EraseRootFromParent_Done, |
| 29561 | /* 82126 */ // Label 1564: @82126 |
| 29562 | /* 82126 */ GIM_Try, /*On fail goto*//*Label 1565*/ GIMT_Encode4(82214), // Rule ID 3189 // |
| 29563 | /* 82131 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 29564 | /* 82134 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava), |
| 29565 | /* 82139 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 29566 | /* 82142 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 29567 | /* 82145 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 29568 | /* 82148 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 29569 | /* 82151 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 29570 | /* 82154 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v16s8, |
| 29571 | /* 82157 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v16s8, |
| 29572 | /* 82160 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 29573 | /* 82164 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 29574 | /* 82168 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 29575 | /* 82172 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 29576 | /* 82176 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 29577 | /* 82180 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29578 | /* 82184 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29579 | /* 82188 */ // (intrinsic_wo_chain:{ *:[i32] } 3659:{ *:[iPTR] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VMLADAVu8:{ *:[i32] } MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) |
| 29580 | /* 82188 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVu8), |
| 29581 | /* 82191 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 29582 | /* 82193 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 29583 | /* 82195 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 29584 | /* 82197 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29585 | /* 82200 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29586 | /* 82206 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29587 | /* 82212 */ GIR_RootConstrainSelectedInstOperands, |
| 29588 | /* 82213 */ // GIR_Coverage, 3189, |
| 29589 | /* 82213 */ GIR_EraseRootFromParent_Done, |
| 29590 | /* 82214 */ // Label 1565: @82214 |
| 29591 | /* 82214 */ GIM_Try, /*On fail goto*//*Label 1566*/ GIMT_Encode4(82302), // Rule ID 3193 // |
| 29592 | /* 82219 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 29593 | /* 82222 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava), |
| 29594 | /* 82227 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 29595 | /* 82230 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 29596 | /* 82233 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 29597 | /* 82236 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 29598 | /* 82239 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 29599 | /* 82242 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s16, |
| 29600 | /* 82245 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s16, |
| 29601 | /* 82248 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 29602 | /* 82252 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 29603 | /* 82256 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 29604 | /* 82260 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 29605 | /* 82264 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 29606 | /* 82268 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29607 | /* 82272 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29608 | /* 82276 */ // (intrinsic_wo_chain:{ *:[i32] } 3659:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VMLADAVs16:{ *:[i32] } MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) |
| 29609 | /* 82276 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVs16), |
| 29610 | /* 82279 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 29611 | /* 82281 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 29612 | /* 82283 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 29613 | /* 82285 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29614 | /* 82288 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29615 | /* 82294 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29616 | /* 82300 */ GIR_RootConstrainSelectedInstOperands, |
| 29617 | /* 82301 */ // GIR_Coverage, 3193, |
| 29618 | /* 82301 */ GIR_EraseRootFromParent_Done, |
| 29619 | /* 82302 */ // Label 1566: @82302 |
| 29620 | /* 82302 */ GIM_Try, /*On fail goto*//*Label 1567*/ GIMT_Encode4(82390), // Rule ID 3197 // |
| 29621 | /* 82307 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 29622 | /* 82310 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava), |
| 29623 | /* 82315 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 29624 | /* 82318 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 29625 | /* 82321 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 29626 | /* 82324 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 29627 | /* 82327 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 29628 | /* 82330 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s16, |
| 29629 | /* 82333 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s16, |
| 29630 | /* 82336 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 29631 | /* 82340 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 29632 | /* 82344 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 29633 | /* 82348 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 29634 | /* 82352 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 29635 | /* 82356 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29636 | /* 82360 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29637 | /* 82364 */ // (intrinsic_wo_chain:{ *:[i32] } 3659:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VMLADAVxs16:{ *:[i32] } MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) |
| 29638 | /* 82364 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVxs16), |
| 29639 | /* 82367 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 29640 | /* 82369 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 29641 | /* 82371 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 29642 | /* 82373 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29643 | /* 82376 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29644 | /* 82382 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29645 | /* 82388 */ GIR_RootConstrainSelectedInstOperands, |
| 29646 | /* 82389 */ // GIR_Coverage, 3197, |
| 29647 | /* 82389 */ GIR_EraseRootFromParent_Done, |
| 29648 | /* 82390 */ // Label 1567: @82390 |
| 29649 | /* 82390 */ GIM_Try, /*On fail goto*//*Label 1568*/ GIMT_Encode4(82478), // Rule ID 3201 // |
| 29650 | /* 82395 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 29651 | /* 82398 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava), |
| 29652 | /* 82403 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 29653 | /* 82406 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 29654 | /* 82409 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 29655 | /* 82412 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 29656 | /* 82415 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 29657 | /* 82418 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s16, |
| 29658 | /* 82421 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s16, |
| 29659 | /* 82424 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 29660 | /* 82428 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 29661 | /* 82432 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 29662 | /* 82436 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 29663 | /* 82440 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 29664 | /* 82444 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29665 | /* 82448 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29666 | /* 82452 */ // (intrinsic_wo_chain:{ *:[i32] } 3659:{ *:[iPTR] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VMLADAVu16:{ *:[i32] } MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) |
| 29667 | /* 82452 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVu16), |
| 29668 | /* 82455 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 29669 | /* 82457 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 29670 | /* 82459 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 29671 | /* 82461 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29672 | /* 82464 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29673 | /* 82470 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29674 | /* 82476 */ GIR_RootConstrainSelectedInstOperands, |
| 29675 | /* 82477 */ // GIR_Coverage, 3201, |
| 29676 | /* 82477 */ GIR_EraseRootFromParent_Done, |
| 29677 | /* 82478 */ // Label 1568: @82478 |
| 29678 | /* 82478 */ GIM_Try, /*On fail goto*//*Label 1569*/ GIMT_Encode4(82566), // Rule ID 3205 // |
| 29679 | /* 82483 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 29680 | /* 82486 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava), |
| 29681 | /* 82491 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 29682 | /* 82494 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 29683 | /* 82497 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 29684 | /* 82500 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 29685 | /* 82503 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 29686 | /* 82506 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32, |
| 29687 | /* 82509 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v4s32, |
| 29688 | /* 82512 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 29689 | /* 82516 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 29690 | /* 82520 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 29691 | /* 82524 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 29692 | /* 82528 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 29693 | /* 82532 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29694 | /* 82536 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29695 | /* 82540 */ // (intrinsic_wo_chain:{ *:[i32] } 3659:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VMLADAVs32:{ *:[i32] } MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) |
| 29696 | /* 82540 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVs32), |
| 29697 | /* 82543 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 29698 | /* 82545 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 29699 | /* 82547 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 29700 | /* 82549 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29701 | /* 82552 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29702 | /* 82558 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29703 | /* 82564 */ GIR_RootConstrainSelectedInstOperands, |
| 29704 | /* 82565 */ // GIR_Coverage, 3205, |
| 29705 | /* 82565 */ GIR_EraseRootFromParent_Done, |
| 29706 | /* 82566 */ // Label 1569: @82566 |
| 29707 | /* 82566 */ GIM_Try, /*On fail goto*//*Label 1570*/ GIMT_Encode4(82654), // Rule ID 3209 // |
| 29708 | /* 82571 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 29709 | /* 82574 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava), |
| 29710 | /* 82579 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 29711 | /* 82582 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 29712 | /* 82585 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 29713 | /* 82588 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 29714 | /* 82591 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 29715 | /* 82594 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32, |
| 29716 | /* 82597 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v4s32, |
| 29717 | /* 82600 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 29718 | /* 82604 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 29719 | /* 82608 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 29720 | /* 82612 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 29721 | /* 82616 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 29722 | /* 82620 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29723 | /* 82624 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29724 | /* 82628 */ // (intrinsic_wo_chain:{ *:[i32] } 3659:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VMLADAVxs32:{ *:[i32] } MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) |
| 29725 | /* 82628 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVxs32), |
| 29726 | /* 82631 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 29727 | /* 82633 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 29728 | /* 82635 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 29729 | /* 82637 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29730 | /* 82640 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29731 | /* 82646 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29732 | /* 82652 */ GIR_RootConstrainSelectedInstOperands, |
| 29733 | /* 82653 */ // GIR_Coverage, 3209, |
| 29734 | /* 82653 */ GIR_EraseRootFromParent_Done, |
| 29735 | /* 82654 */ // Label 1570: @82654 |
| 29736 | /* 82654 */ GIM_Try, /*On fail goto*//*Label 1571*/ GIMT_Encode4(82742), // Rule ID 3213 // |
| 29737 | /* 82659 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 29738 | /* 82662 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava), |
| 29739 | /* 82667 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 29740 | /* 82670 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 29741 | /* 82673 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 29742 | /* 82676 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 29743 | /* 82679 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 29744 | /* 82682 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32, |
| 29745 | /* 82685 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v4s32, |
| 29746 | /* 82688 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 29747 | /* 82692 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 29748 | /* 82696 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 29749 | /* 82700 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 29750 | /* 82704 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 29751 | /* 82708 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29752 | /* 82712 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29753 | /* 82716 */ // (intrinsic_wo_chain:{ *:[i32] } 3659:{ *:[iPTR] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VMLADAVu32:{ *:[i32] } MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) |
| 29754 | /* 82716 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVu32), |
| 29755 | /* 82719 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 29756 | /* 82721 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 29757 | /* 82723 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 29758 | /* 82725 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29759 | /* 82728 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29760 | /* 82734 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29761 | /* 82740 */ GIR_RootConstrainSelectedInstOperands, |
| 29762 | /* 82741 */ // GIR_Coverage, 3213, |
| 29763 | /* 82741 */ GIR_EraseRootFromParent_Done, |
| 29764 | /* 82742 */ // Label 1571: @82742 |
| 29765 | /* 82742 */ GIM_Try, /*On fail goto*//*Label 1572*/ GIMT_Encode4(82830), // Rule ID 3217 // |
| 29766 | /* 82747 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 29767 | /* 82750 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava), |
| 29768 | /* 82755 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 29769 | /* 82758 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 29770 | /* 82761 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 29771 | /* 82764 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 29772 | /* 82767 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 29773 | /* 82770 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v16s8, |
| 29774 | /* 82773 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v16s8, |
| 29775 | /* 82776 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 29776 | /* 82780 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 29777 | /* 82784 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1, |
| 29778 | /* 82788 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 29779 | /* 82792 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 29780 | /* 82796 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29781 | /* 82800 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29782 | /* 82804 */ // (intrinsic_wo_chain:{ *:[i32] } 3659:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VMLSDAVs8:{ *:[i32] } MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) |
| 29783 | /* 82804 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVs8), |
| 29784 | /* 82807 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 29785 | /* 82809 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 29786 | /* 82811 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 29787 | /* 82813 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29788 | /* 82816 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29789 | /* 82822 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29790 | /* 82828 */ GIR_RootConstrainSelectedInstOperands, |
| 29791 | /* 82829 */ // GIR_Coverage, 3217, |
| 29792 | /* 82829 */ GIR_EraseRootFromParent_Done, |
| 29793 | /* 82830 */ // Label 1572: @82830 |
| 29794 | /* 82830 */ GIM_Try, /*On fail goto*//*Label 1573*/ GIMT_Encode4(82918), // Rule ID 3221 // |
| 29795 | /* 82835 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 29796 | /* 82838 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava), |
| 29797 | /* 82843 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 29798 | /* 82846 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 29799 | /* 82849 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 29800 | /* 82852 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 29801 | /* 82855 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 29802 | /* 82858 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v16s8, |
| 29803 | /* 82861 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v16s8, |
| 29804 | /* 82864 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 29805 | /* 82868 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 29806 | /* 82872 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1, |
| 29807 | /* 82876 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 29808 | /* 82880 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 29809 | /* 82884 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29810 | /* 82888 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29811 | /* 82892 */ // (intrinsic_wo_chain:{ *:[i32] } 3659:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VMLSDAVxs8:{ *:[i32] } MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) |
| 29812 | /* 82892 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVxs8), |
| 29813 | /* 82895 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 29814 | /* 82897 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 29815 | /* 82899 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 29816 | /* 82901 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29817 | /* 82904 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29818 | /* 82910 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29819 | /* 82916 */ GIR_RootConstrainSelectedInstOperands, |
| 29820 | /* 82917 */ // GIR_Coverage, 3221, |
| 29821 | /* 82917 */ GIR_EraseRootFromParent_Done, |
| 29822 | /* 82918 */ // Label 1573: @82918 |
| 29823 | /* 82918 */ GIM_Try, /*On fail goto*//*Label 1574*/ GIMT_Encode4(83006), // Rule ID 3225 // |
| 29824 | /* 82923 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 29825 | /* 82926 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava), |
| 29826 | /* 82931 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 29827 | /* 82934 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 29828 | /* 82937 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 29829 | /* 82940 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 29830 | /* 82943 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 29831 | /* 82946 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s16, |
| 29832 | /* 82949 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s16, |
| 29833 | /* 82952 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 29834 | /* 82956 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 29835 | /* 82960 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1, |
| 29836 | /* 82964 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 29837 | /* 82968 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 29838 | /* 82972 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29839 | /* 82976 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29840 | /* 82980 */ // (intrinsic_wo_chain:{ *:[i32] } 3659:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VMLSDAVs16:{ *:[i32] } MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) |
| 29841 | /* 82980 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVs16), |
| 29842 | /* 82983 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 29843 | /* 82985 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 29844 | /* 82987 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 29845 | /* 82989 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29846 | /* 82992 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29847 | /* 82998 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29848 | /* 83004 */ GIR_RootConstrainSelectedInstOperands, |
| 29849 | /* 83005 */ // GIR_Coverage, 3225, |
| 29850 | /* 83005 */ GIR_EraseRootFromParent_Done, |
| 29851 | /* 83006 */ // Label 1574: @83006 |
| 29852 | /* 83006 */ GIM_Try, /*On fail goto*//*Label 1575*/ GIMT_Encode4(83094), // Rule ID 3229 // |
| 29853 | /* 83011 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 29854 | /* 83014 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava), |
| 29855 | /* 83019 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 29856 | /* 83022 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 29857 | /* 83025 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 29858 | /* 83028 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 29859 | /* 83031 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 29860 | /* 83034 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s16, |
| 29861 | /* 83037 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s16, |
| 29862 | /* 83040 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 29863 | /* 83044 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 29864 | /* 83048 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1, |
| 29865 | /* 83052 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 29866 | /* 83056 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 29867 | /* 83060 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29868 | /* 83064 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29869 | /* 83068 */ // (intrinsic_wo_chain:{ *:[i32] } 3659:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VMLSDAVxs16:{ *:[i32] } MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) |
| 29870 | /* 83068 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVxs16), |
| 29871 | /* 83071 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 29872 | /* 83073 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 29873 | /* 83075 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 29874 | /* 83077 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29875 | /* 83080 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29876 | /* 83086 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29877 | /* 83092 */ GIR_RootConstrainSelectedInstOperands, |
| 29878 | /* 83093 */ // GIR_Coverage, 3229, |
| 29879 | /* 83093 */ GIR_EraseRootFromParent_Done, |
| 29880 | /* 83094 */ // Label 1575: @83094 |
| 29881 | /* 83094 */ GIM_Try, /*On fail goto*//*Label 1576*/ GIMT_Encode4(83182), // Rule ID 3233 // |
| 29882 | /* 83099 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 29883 | /* 83102 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava), |
| 29884 | /* 83107 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 29885 | /* 83110 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 29886 | /* 83113 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 29887 | /* 83116 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 29888 | /* 83119 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 29889 | /* 83122 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32, |
| 29890 | /* 83125 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v4s32, |
| 29891 | /* 83128 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 29892 | /* 83132 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 29893 | /* 83136 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1, |
| 29894 | /* 83140 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 29895 | /* 83144 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 29896 | /* 83148 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29897 | /* 83152 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29898 | /* 83156 */ // (intrinsic_wo_chain:{ *:[i32] } 3659:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VMLSDAVs32:{ *:[i32] } MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) |
| 29899 | /* 83156 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVs32), |
| 29900 | /* 83159 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 29901 | /* 83161 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 29902 | /* 83163 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 29903 | /* 83165 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29904 | /* 83168 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29905 | /* 83174 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29906 | /* 83180 */ GIR_RootConstrainSelectedInstOperands, |
| 29907 | /* 83181 */ // GIR_Coverage, 3233, |
| 29908 | /* 83181 */ GIR_EraseRootFromParent_Done, |
| 29909 | /* 83182 */ // Label 1576: @83182 |
| 29910 | /* 83182 */ GIM_Try, /*On fail goto*//*Label 1577*/ GIMT_Encode4(83270), // Rule ID 3237 // |
| 29911 | /* 83187 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 29912 | /* 83190 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava), |
| 29913 | /* 83195 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 29914 | /* 83198 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 29915 | /* 83201 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 29916 | /* 83204 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 29917 | /* 83207 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 29918 | /* 83210 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32, |
| 29919 | /* 83213 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v4s32, |
| 29920 | /* 83216 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 29921 | /* 83220 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 29922 | /* 83224 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1, |
| 29923 | /* 83228 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 29924 | /* 83232 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 29925 | /* 83236 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29926 | /* 83240 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29927 | /* 83244 */ // (intrinsic_wo_chain:{ *:[i32] } 3659:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VMLSDAVxs32:{ *:[i32] } MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) |
| 29928 | /* 83244 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVxs32), |
| 29929 | /* 83247 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 29930 | /* 83249 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 29931 | /* 83251 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 29932 | /* 83253 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29933 | /* 83256 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29934 | /* 83262 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29935 | /* 83268 */ GIR_RootConstrainSelectedInstOperands, |
| 29936 | /* 83269 */ // GIR_Coverage, 3237, |
| 29937 | /* 83269 */ GIR_EraseRootFromParent_Done, |
| 29938 | /* 83270 */ // Label 1577: @83270 |
| 29939 | /* 83270 */ GIM_Try, /*On fail goto*//*Label 1578*/ GIMT_Encode4(83360), // Rule ID 3183 // |
| 29940 | /* 83275 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 29941 | /* 83278 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava), |
| 29942 | /* 83283 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 29943 | /* 83286 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 29944 | /* 83289 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 29945 | /* 83292 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 29946 | /* 83295 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 29947 | /* 83298 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v16s8, |
| 29948 | /* 83301 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v16s8, |
| 29949 | /* 83304 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 29950 | /* 83308 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 29951 | /* 83312 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 29952 | /* 83316 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 29953 | /* 83320 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 29954 | /* 83324 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29955 | /* 83328 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29956 | /* 83332 */ // (intrinsic_wo_chain:{ *:[i32] } 3659:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VMLADAVas8:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) |
| 29957 | /* 83332 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVas8), |
| 29958 | /* 83335 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 29959 | /* 83337 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc |
| 29960 | /* 83339 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 29961 | /* 83341 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 29962 | /* 83343 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29963 | /* 83346 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29964 | /* 83352 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29965 | /* 83358 */ GIR_RootConstrainSelectedInstOperands, |
| 29966 | /* 83359 */ // GIR_Coverage, 3183, |
| 29967 | /* 83359 */ GIR_EraseRootFromParent_Done, |
| 29968 | /* 83360 */ // Label 1578: @83360 |
| 29969 | /* 83360 */ GIM_Try, /*On fail goto*//*Label 1579*/ GIMT_Encode4(83450), // Rule ID 3187 // |
| 29970 | /* 83365 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 29971 | /* 83368 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava), |
| 29972 | /* 83373 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 29973 | /* 83376 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 29974 | /* 83379 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 29975 | /* 83382 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 29976 | /* 83385 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 29977 | /* 83388 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v16s8, |
| 29978 | /* 83391 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v16s8, |
| 29979 | /* 83394 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 29980 | /* 83398 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 29981 | /* 83402 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 29982 | /* 83406 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 29983 | /* 83410 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 29984 | /* 83414 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29985 | /* 83418 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29986 | /* 83422 */ // (intrinsic_wo_chain:{ *:[i32] } 3659:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VMLADAVaxs8:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) |
| 29987 | /* 83422 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVaxs8), |
| 29988 | /* 83425 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 29989 | /* 83427 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc |
| 29990 | /* 83429 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 29991 | /* 83431 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 29992 | /* 83433 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29993 | /* 83436 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29994 | /* 83442 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29995 | /* 83448 */ GIR_RootConstrainSelectedInstOperands, |
| 29996 | /* 83449 */ // GIR_Coverage, 3187, |
| 29997 | /* 83449 */ GIR_EraseRootFromParent_Done, |
| 29998 | /* 83450 */ // Label 1579: @83450 |
| 29999 | /* 83450 */ GIM_Try, /*On fail goto*//*Label 1580*/ GIMT_Encode4(83540), // Rule ID 3191 // |
| 30000 | /* 83455 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 30001 | /* 83458 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava), |
| 30002 | /* 83463 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 30003 | /* 83466 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 30004 | /* 83469 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 30005 | /* 83472 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 30006 | /* 83475 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 30007 | /* 83478 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v16s8, |
| 30008 | /* 83481 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v16s8, |
| 30009 | /* 83484 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 30010 | /* 83488 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 30011 | /* 83492 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 30012 | /* 83496 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 30013 | /* 83500 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 30014 | /* 83504 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30015 | /* 83508 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30016 | /* 83512 */ // (intrinsic_wo_chain:{ *:[i32] } 3659:{ *:[iPTR] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VMLADAVau8:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) |
| 30017 | /* 83512 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVau8), |
| 30018 | /* 83515 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 30019 | /* 83517 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc |
| 30020 | /* 83519 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 30021 | /* 83521 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 30022 | /* 83523 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30023 | /* 83526 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30024 | /* 83532 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30025 | /* 83538 */ GIR_RootConstrainSelectedInstOperands, |
| 30026 | /* 83539 */ // GIR_Coverage, 3191, |
| 30027 | /* 83539 */ GIR_EraseRootFromParent_Done, |
| 30028 | /* 83540 */ // Label 1580: @83540 |
| 30029 | /* 83540 */ GIM_Try, /*On fail goto*//*Label 1581*/ GIMT_Encode4(83630), // Rule ID 3195 // |
| 30030 | /* 83545 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 30031 | /* 83548 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava), |
| 30032 | /* 83553 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 30033 | /* 83556 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 30034 | /* 83559 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 30035 | /* 83562 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 30036 | /* 83565 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 30037 | /* 83568 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s16, |
| 30038 | /* 83571 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s16, |
| 30039 | /* 83574 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 30040 | /* 83578 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 30041 | /* 83582 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 30042 | /* 83586 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 30043 | /* 83590 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 30044 | /* 83594 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30045 | /* 83598 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30046 | /* 83602 */ // (intrinsic_wo_chain:{ *:[i32] } 3659:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VMLADAVas16:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) |
| 30047 | /* 83602 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVas16), |
| 30048 | /* 83605 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 30049 | /* 83607 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc |
| 30050 | /* 83609 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 30051 | /* 83611 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 30052 | /* 83613 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30053 | /* 83616 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30054 | /* 83622 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30055 | /* 83628 */ GIR_RootConstrainSelectedInstOperands, |
| 30056 | /* 83629 */ // GIR_Coverage, 3195, |
| 30057 | /* 83629 */ GIR_EraseRootFromParent_Done, |
| 30058 | /* 83630 */ // Label 1581: @83630 |
| 30059 | /* 83630 */ GIM_Try, /*On fail goto*//*Label 1582*/ GIMT_Encode4(83720), // Rule ID 3199 // |
| 30060 | /* 83635 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 30061 | /* 83638 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava), |
| 30062 | /* 83643 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 30063 | /* 83646 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 30064 | /* 83649 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 30065 | /* 83652 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 30066 | /* 83655 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 30067 | /* 83658 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s16, |
| 30068 | /* 83661 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s16, |
| 30069 | /* 83664 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 30070 | /* 83668 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 30071 | /* 83672 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 30072 | /* 83676 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 30073 | /* 83680 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 30074 | /* 83684 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30075 | /* 83688 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30076 | /* 83692 */ // (intrinsic_wo_chain:{ *:[i32] } 3659:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VMLADAVaxs16:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) |
| 30077 | /* 83692 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVaxs16), |
| 30078 | /* 83695 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 30079 | /* 83697 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc |
| 30080 | /* 83699 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 30081 | /* 83701 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 30082 | /* 83703 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30083 | /* 83706 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30084 | /* 83712 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30085 | /* 83718 */ GIR_RootConstrainSelectedInstOperands, |
| 30086 | /* 83719 */ // GIR_Coverage, 3199, |
| 30087 | /* 83719 */ GIR_EraseRootFromParent_Done, |
| 30088 | /* 83720 */ // Label 1582: @83720 |
| 30089 | /* 83720 */ GIM_Try, /*On fail goto*//*Label 1583*/ GIMT_Encode4(83810), // Rule ID 3203 // |
| 30090 | /* 83725 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 30091 | /* 83728 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava), |
| 30092 | /* 83733 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 30093 | /* 83736 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 30094 | /* 83739 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 30095 | /* 83742 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 30096 | /* 83745 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 30097 | /* 83748 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s16, |
| 30098 | /* 83751 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s16, |
| 30099 | /* 83754 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 30100 | /* 83758 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 30101 | /* 83762 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 30102 | /* 83766 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 30103 | /* 83770 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 30104 | /* 83774 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30105 | /* 83778 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30106 | /* 83782 */ // (intrinsic_wo_chain:{ *:[i32] } 3659:{ *:[iPTR] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VMLADAVau16:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) |
| 30107 | /* 83782 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVau16), |
| 30108 | /* 83785 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 30109 | /* 83787 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc |
| 30110 | /* 83789 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 30111 | /* 83791 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 30112 | /* 83793 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30113 | /* 83796 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30114 | /* 83802 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30115 | /* 83808 */ GIR_RootConstrainSelectedInstOperands, |
| 30116 | /* 83809 */ // GIR_Coverage, 3203, |
| 30117 | /* 83809 */ GIR_EraseRootFromParent_Done, |
| 30118 | /* 83810 */ // Label 1583: @83810 |
| 30119 | /* 83810 */ GIM_Try, /*On fail goto*//*Label 1584*/ GIMT_Encode4(83900), // Rule ID 3207 // |
| 30120 | /* 83815 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 30121 | /* 83818 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava), |
| 30122 | /* 83823 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 30123 | /* 83826 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 30124 | /* 83829 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 30125 | /* 83832 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 30126 | /* 83835 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 30127 | /* 83838 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32, |
| 30128 | /* 83841 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v4s32, |
| 30129 | /* 83844 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 30130 | /* 83848 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 30131 | /* 83852 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 30132 | /* 83856 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 30133 | /* 83860 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 30134 | /* 83864 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30135 | /* 83868 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30136 | /* 83872 */ // (intrinsic_wo_chain:{ *:[i32] } 3659:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VMLADAVas32:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) |
| 30137 | /* 83872 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVas32), |
| 30138 | /* 83875 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 30139 | /* 83877 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc |
| 30140 | /* 83879 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 30141 | /* 83881 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 30142 | /* 83883 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30143 | /* 83886 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30144 | /* 83892 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30145 | /* 83898 */ GIR_RootConstrainSelectedInstOperands, |
| 30146 | /* 83899 */ // GIR_Coverage, 3207, |
| 30147 | /* 83899 */ GIR_EraseRootFromParent_Done, |
| 30148 | /* 83900 */ // Label 1584: @83900 |
| 30149 | /* 83900 */ GIM_Try, /*On fail goto*//*Label 1585*/ GIMT_Encode4(83990), // Rule ID 3211 // |
| 30150 | /* 83905 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 30151 | /* 83908 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava), |
| 30152 | /* 83913 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 30153 | /* 83916 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 30154 | /* 83919 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 30155 | /* 83922 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 30156 | /* 83925 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 30157 | /* 83928 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32, |
| 30158 | /* 83931 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v4s32, |
| 30159 | /* 83934 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 30160 | /* 83938 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 30161 | /* 83942 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 30162 | /* 83946 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 30163 | /* 83950 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 30164 | /* 83954 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30165 | /* 83958 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30166 | /* 83962 */ // (intrinsic_wo_chain:{ *:[i32] } 3659:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VMLADAVaxs32:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) |
| 30167 | /* 83962 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVaxs32), |
| 30168 | /* 83965 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 30169 | /* 83967 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc |
| 30170 | /* 83969 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 30171 | /* 83971 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 30172 | /* 83973 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30173 | /* 83976 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30174 | /* 83982 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30175 | /* 83988 */ GIR_RootConstrainSelectedInstOperands, |
| 30176 | /* 83989 */ // GIR_Coverage, 3211, |
| 30177 | /* 83989 */ GIR_EraseRootFromParent_Done, |
| 30178 | /* 83990 */ // Label 1585: @83990 |
| 30179 | /* 83990 */ GIM_Try, /*On fail goto*//*Label 1586*/ GIMT_Encode4(84080), // Rule ID 3215 // |
| 30180 | /* 83995 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 30181 | /* 83998 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava), |
| 30182 | /* 84003 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 30183 | /* 84006 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 30184 | /* 84009 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 30185 | /* 84012 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 30186 | /* 84015 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 30187 | /* 84018 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32, |
| 30188 | /* 84021 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v4s32, |
| 30189 | /* 84024 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 30190 | /* 84028 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 30191 | /* 84032 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 30192 | /* 84036 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 30193 | /* 84040 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 30194 | /* 84044 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30195 | /* 84048 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30196 | /* 84052 */ // (intrinsic_wo_chain:{ *:[i32] } 3659:{ *:[iPTR] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VMLADAVau32:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) |
| 30197 | /* 84052 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVau32), |
| 30198 | /* 84055 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 30199 | /* 84057 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc |
| 30200 | /* 84059 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 30201 | /* 84061 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 30202 | /* 84063 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30203 | /* 84066 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30204 | /* 84072 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30205 | /* 84078 */ GIR_RootConstrainSelectedInstOperands, |
| 30206 | /* 84079 */ // GIR_Coverage, 3215, |
| 30207 | /* 84079 */ GIR_EraseRootFromParent_Done, |
| 30208 | /* 84080 */ // Label 1586: @84080 |
| 30209 | /* 84080 */ GIM_Try, /*On fail goto*//*Label 1587*/ GIMT_Encode4(84170), // Rule ID 3219 // |
| 30210 | /* 84085 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 30211 | /* 84088 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava), |
| 30212 | /* 84093 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 30213 | /* 84096 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 30214 | /* 84099 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 30215 | /* 84102 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 30216 | /* 84105 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 30217 | /* 84108 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v16s8, |
| 30218 | /* 84111 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v16s8, |
| 30219 | /* 84114 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 30220 | /* 84118 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 30221 | /* 84122 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1, |
| 30222 | /* 84126 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 30223 | /* 84130 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 30224 | /* 84134 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30225 | /* 84138 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30226 | /* 84142 */ // (intrinsic_wo_chain:{ *:[i32] } 3659:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VMLSDAVas8:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) |
| 30227 | /* 84142 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVas8), |
| 30228 | /* 84145 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 30229 | /* 84147 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc |
| 30230 | /* 84149 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 30231 | /* 84151 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 30232 | /* 84153 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30233 | /* 84156 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30234 | /* 84162 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30235 | /* 84168 */ GIR_RootConstrainSelectedInstOperands, |
| 30236 | /* 84169 */ // GIR_Coverage, 3219, |
| 30237 | /* 84169 */ GIR_EraseRootFromParent_Done, |
| 30238 | /* 84170 */ // Label 1587: @84170 |
| 30239 | /* 84170 */ GIM_Try, /*On fail goto*//*Label 1588*/ GIMT_Encode4(84260), // Rule ID 3223 // |
| 30240 | /* 84175 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 30241 | /* 84178 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava), |
| 30242 | /* 84183 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 30243 | /* 84186 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 30244 | /* 84189 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 30245 | /* 84192 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 30246 | /* 84195 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 30247 | /* 84198 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v16s8, |
| 30248 | /* 84201 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v16s8, |
| 30249 | /* 84204 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 30250 | /* 84208 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 30251 | /* 84212 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1, |
| 30252 | /* 84216 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 30253 | /* 84220 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 30254 | /* 84224 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30255 | /* 84228 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30256 | /* 84232 */ // (intrinsic_wo_chain:{ *:[i32] } 3659:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VMLSDAVaxs8:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) |
| 30257 | /* 84232 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVaxs8), |
| 30258 | /* 84235 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 30259 | /* 84237 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc |
| 30260 | /* 84239 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 30261 | /* 84241 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 30262 | /* 84243 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30263 | /* 84246 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30264 | /* 84252 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30265 | /* 84258 */ GIR_RootConstrainSelectedInstOperands, |
| 30266 | /* 84259 */ // GIR_Coverage, 3223, |
| 30267 | /* 84259 */ GIR_EraseRootFromParent_Done, |
| 30268 | /* 84260 */ // Label 1588: @84260 |
| 30269 | /* 84260 */ GIM_Try, /*On fail goto*//*Label 1589*/ GIMT_Encode4(84350), // Rule ID 3227 // |
| 30270 | /* 84265 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 30271 | /* 84268 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava), |
| 30272 | /* 84273 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 30273 | /* 84276 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 30274 | /* 84279 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 30275 | /* 84282 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 30276 | /* 84285 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 30277 | /* 84288 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s16, |
| 30278 | /* 84291 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s16, |
| 30279 | /* 84294 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 30280 | /* 84298 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 30281 | /* 84302 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1, |
| 30282 | /* 84306 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 30283 | /* 84310 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 30284 | /* 84314 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30285 | /* 84318 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30286 | /* 84322 */ // (intrinsic_wo_chain:{ *:[i32] } 3659:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VMLSDAVas16:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) |
| 30287 | /* 84322 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVas16), |
| 30288 | /* 84325 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 30289 | /* 84327 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc |
| 30290 | /* 84329 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 30291 | /* 84331 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 30292 | /* 84333 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30293 | /* 84336 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30294 | /* 84342 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30295 | /* 84348 */ GIR_RootConstrainSelectedInstOperands, |
| 30296 | /* 84349 */ // GIR_Coverage, 3227, |
| 30297 | /* 84349 */ GIR_EraseRootFromParent_Done, |
| 30298 | /* 84350 */ // Label 1589: @84350 |
| 30299 | /* 84350 */ GIM_Try, /*On fail goto*//*Label 1590*/ GIMT_Encode4(84440), // Rule ID 3231 // |
| 30300 | /* 84355 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 30301 | /* 84358 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava), |
| 30302 | /* 84363 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 30303 | /* 84366 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 30304 | /* 84369 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 30305 | /* 84372 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 30306 | /* 84375 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 30307 | /* 84378 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s16, |
| 30308 | /* 84381 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s16, |
| 30309 | /* 84384 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 30310 | /* 84388 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 30311 | /* 84392 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1, |
| 30312 | /* 84396 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 30313 | /* 84400 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 30314 | /* 84404 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30315 | /* 84408 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30316 | /* 84412 */ // (intrinsic_wo_chain:{ *:[i32] } 3659:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VMLSDAVaxs16:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) |
| 30317 | /* 84412 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVaxs16), |
| 30318 | /* 84415 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 30319 | /* 84417 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc |
| 30320 | /* 84419 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 30321 | /* 84421 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 30322 | /* 84423 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30323 | /* 84426 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30324 | /* 84432 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30325 | /* 84438 */ GIR_RootConstrainSelectedInstOperands, |
| 30326 | /* 84439 */ // GIR_Coverage, 3231, |
| 30327 | /* 84439 */ GIR_EraseRootFromParent_Done, |
| 30328 | /* 84440 */ // Label 1590: @84440 |
| 30329 | /* 84440 */ GIM_Try, /*On fail goto*//*Label 1591*/ GIMT_Encode4(84530), // Rule ID 3235 // |
| 30330 | /* 84445 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 30331 | /* 84448 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava), |
| 30332 | /* 84453 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 30333 | /* 84456 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 30334 | /* 84459 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 30335 | /* 84462 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 30336 | /* 84465 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 30337 | /* 84468 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32, |
| 30338 | /* 84471 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v4s32, |
| 30339 | /* 84474 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 30340 | /* 84478 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 30341 | /* 84482 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1, |
| 30342 | /* 84486 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 30343 | /* 84490 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 30344 | /* 84494 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30345 | /* 84498 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30346 | /* 84502 */ // (intrinsic_wo_chain:{ *:[i32] } 3659:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VMLSDAVas32:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) |
| 30347 | /* 84502 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVas32), |
| 30348 | /* 84505 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 30349 | /* 84507 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc |
| 30350 | /* 84509 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 30351 | /* 84511 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 30352 | /* 84513 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30353 | /* 84516 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30354 | /* 84522 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30355 | /* 84528 */ GIR_RootConstrainSelectedInstOperands, |
| 30356 | /* 84529 */ // GIR_Coverage, 3235, |
| 30357 | /* 84529 */ GIR_EraseRootFromParent_Done, |
| 30358 | /* 84530 */ // Label 1591: @84530 |
| 30359 | /* 84530 */ GIM_Try, /*On fail goto*//*Label 1592*/ GIMT_Encode4(84620), // Rule ID 3239 // |
| 30360 | /* 84535 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 30361 | /* 84538 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava), |
| 30362 | /* 84543 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 30363 | /* 84546 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 30364 | /* 84549 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 30365 | /* 84552 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 30366 | /* 84555 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 30367 | /* 84558 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32, |
| 30368 | /* 84561 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v4s32, |
| 30369 | /* 84564 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 30370 | /* 84568 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 30371 | /* 84572 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1, |
| 30372 | /* 84576 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 30373 | /* 84580 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 30374 | /* 84584 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30375 | /* 84588 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30376 | /* 84592 */ // (intrinsic_wo_chain:{ *:[i32] } 3659:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VMLSDAVaxs32:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) |
| 30377 | /* 84592 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVaxs32), |
| 30378 | /* 84595 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 30379 | /* 84597 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc |
| 30380 | /* 84599 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 30381 | /* 84601 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 30382 | /* 84603 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30383 | /* 84606 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30384 | /* 84612 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30385 | /* 84618 */ GIR_RootConstrainSelectedInstOperands, |
| 30386 | /* 84619 */ // GIR_Coverage, 3239, |
| 30387 | /* 84619 */ GIR_EraseRootFromParent_Done, |
| 30388 | /* 84620 */ // Label 1592: @84620 |
| 30389 | /* 84620 */ GIM_Try, /*On fail goto*//*Label 1593*/ GIMT_Encode4(84707), // Rule ID 4335 // |
| 30390 | /* 84625 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad), |
| 30391 | /* 84630 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 30392 | /* 84633 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 30393 | /* 84636 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 30394 | /* 84639 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 30395 | /* 84642 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 30396 | /* 84645 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 30397 | /* 84648 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 30398 | /* 84651 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30399 | /* 84655 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30400 | /* 84659 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30401 | /* 84663 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30402 | /* 84667 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 30403 | /* 84671 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 30404 | /* 84675 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 30405 | /* 84679 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3668:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQDMLADHs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c) |
| 30406 | /* 84679 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLADHs8), |
| 30407 | /* 84682 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30408 | /* 84684 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 30409 | /* 84686 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 30410 | /* 84688 */ GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 30411 | /* 84690 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30412 | /* 84693 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30413 | /* 84699 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30414 | /* 84705 */ GIR_RootConstrainSelectedInstOperands, |
| 30415 | /* 84706 */ // GIR_Coverage, 4335, |
| 30416 | /* 84706 */ GIR_EraseRootFromParent_Done, |
| 30417 | /* 84707 */ // Label 1593: @84707 |
| 30418 | /* 84707 */ GIM_Try, /*On fail goto*//*Label 1594*/ GIMT_Encode4(84794), // Rule ID 4337 // |
| 30419 | /* 84712 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad), |
| 30420 | /* 84717 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 30421 | /* 84720 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 30422 | /* 84723 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 30423 | /* 84726 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16, |
| 30424 | /* 84729 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 30425 | /* 84732 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 30426 | /* 84735 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 30427 | /* 84738 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30428 | /* 84742 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30429 | /* 84746 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30430 | /* 84750 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30431 | /* 84754 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 30432 | /* 84758 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 30433 | /* 84762 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 30434 | /* 84766 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3668:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQDMLADHs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c) |
| 30435 | /* 84766 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLADHs16), |
| 30436 | /* 84769 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30437 | /* 84771 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 30438 | /* 84773 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 30439 | /* 84775 */ GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 30440 | /* 84777 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30441 | /* 84780 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30442 | /* 84786 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30443 | /* 84792 */ GIR_RootConstrainSelectedInstOperands, |
| 30444 | /* 84793 */ // GIR_Coverage, 4337, |
| 30445 | /* 84793 */ GIR_EraseRootFromParent_Done, |
| 30446 | /* 84794 */ // Label 1594: @84794 |
| 30447 | /* 84794 */ GIM_Try, /*On fail goto*//*Label 1595*/ GIMT_Encode4(84881), // Rule ID 4339 // |
| 30448 | /* 84799 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad), |
| 30449 | /* 84804 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 30450 | /* 84807 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 30451 | /* 84810 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 30452 | /* 84813 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 30453 | /* 84816 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 30454 | /* 84819 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 30455 | /* 84822 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 30456 | /* 84825 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30457 | /* 84829 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30458 | /* 84833 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30459 | /* 84837 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30460 | /* 84841 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 30461 | /* 84845 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 30462 | /* 84849 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 30463 | /* 84853 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3668:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQDMLADHs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c) |
| 30464 | /* 84853 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLADHs32), |
| 30465 | /* 84856 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30466 | /* 84858 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 30467 | /* 84860 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 30468 | /* 84862 */ GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 30469 | /* 84864 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30470 | /* 84867 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30471 | /* 84873 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30472 | /* 84879 */ GIR_RootConstrainSelectedInstOperands, |
| 30473 | /* 84880 */ // GIR_Coverage, 4339, |
| 30474 | /* 84880 */ GIR_EraseRootFromParent_Done, |
| 30475 | /* 84881 */ // Label 1595: @84881 |
| 30476 | /* 84881 */ GIM_Try, /*On fail goto*//*Label 1596*/ GIMT_Encode4(84968), // Rule ID 4341 // |
| 30477 | /* 84886 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad), |
| 30478 | /* 84891 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 30479 | /* 84894 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 30480 | /* 84897 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 30481 | /* 84900 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 30482 | /* 84903 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 30483 | /* 84906 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 30484 | /* 84909 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 30485 | /* 84912 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30486 | /* 84916 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30487 | /* 84920 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30488 | /* 84924 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30489 | /* 84928 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 30490 | /* 84932 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 30491 | /* 84936 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 30492 | /* 84940 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3668:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQDMLADHXs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c) |
| 30493 | /* 84940 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLADHXs8), |
| 30494 | /* 84943 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30495 | /* 84945 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 30496 | /* 84947 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 30497 | /* 84949 */ GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 30498 | /* 84951 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30499 | /* 84954 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30500 | /* 84960 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30501 | /* 84966 */ GIR_RootConstrainSelectedInstOperands, |
| 30502 | /* 84967 */ // GIR_Coverage, 4341, |
| 30503 | /* 84967 */ GIR_EraseRootFromParent_Done, |
| 30504 | /* 84968 */ // Label 1596: @84968 |
| 30505 | /* 84968 */ GIM_Try, /*On fail goto*//*Label 1597*/ GIMT_Encode4(85055), // Rule ID 4343 // |
| 30506 | /* 84973 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad), |
| 30507 | /* 84978 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 30508 | /* 84981 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 30509 | /* 84984 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 30510 | /* 84987 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16, |
| 30511 | /* 84990 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 30512 | /* 84993 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 30513 | /* 84996 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 30514 | /* 84999 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30515 | /* 85003 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30516 | /* 85007 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30517 | /* 85011 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30518 | /* 85015 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 30519 | /* 85019 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 30520 | /* 85023 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 30521 | /* 85027 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3668:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQDMLADHXs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c) |
| 30522 | /* 85027 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLADHXs16), |
| 30523 | /* 85030 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30524 | /* 85032 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 30525 | /* 85034 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 30526 | /* 85036 */ GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 30527 | /* 85038 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30528 | /* 85041 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30529 | /* 85047 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30530 | /* 85053 */ GIR_RootConstrainSelectedInstOperands, |
| 30531 | /* 85054 */ // GIR_Coverage, 4343, |
| 30532 | /* 85054 */ GIR_EraseRootFromParent_Done, |
| 30533 | /* 85055 */ // Label 1597: @85055 |
| 30534 | /* 85055 */ GIM_Try, /*On fail goto*//*Label 1598*/ GIMT_Encode4(85142), // Rule ID 4345 // |
| 30535 | /* 85060 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad), |
| 30536 | /* 85065 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 30537 | /* 85068 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 30538 | /* 85071 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 30539 | /* 85074 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 30540 | /* 85077 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 30541 | /* 85080 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 30542 | /* 85083 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 30543 | /* 85086 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30544 | /* 85090 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30545 | /* 85094 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30546 | /* 85098 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30547 | /* 85102 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 30548 | /* 85106 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 30549 | /* 85110 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 30550 | /* 85114 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3668:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQDMLADHXs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c) |
| 30551 | /* 85114 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLADHXs32), |
| 30552 | /* 85117 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30553 | /* 85119 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 30554 | /* 85121 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 30555 | /* 85123 */ GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 30556 | /* 85125 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30557 | /* 85128 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30558 | /* 85134 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30559 | /* 85140 */ GIR_RootConstrainSelectedInstOperands, |
| 30560 | /* 85141 */ // GIR_Coverage, 4345, |
| 30561 | /* 85141 */ GIR_EraseRootFromParent_Done, |
| 30562 | /* 85142 */ // Label 1598: @85142 |
| 30563 | /* 85142 */ GIM_Try, /*On fail goto*//*Label 1599*/ GIMT_Encode4(85229), // Rule ID 4347 // |
| 30564 | /* 85147 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad), |
| 30565 | /* 85152 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 30566 | /* 85155 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 30567 | /* 85158 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 30568 | /* 85161 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 30569 | /* 85164 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 30570 | /* 85167 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 30571 | /* 85170 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 30572 | /* 85173 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30573 | /* 85177 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30574 | /* 85181 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30575 | /* 85185 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30576 | /* 85189 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 30577 | /* 85193 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 30578 | /* 85197 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 30579 | /* 85201 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3668:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRDMLADHs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c) |
| 30580 | /* 85201 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLADHs8), |
| 30581 | /* 85204 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30582 | /* 85206 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 30583 | /* 85208 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 30584 | /* 85210 */ GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 30585 | /* 85212 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30586 | /* 85215 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30587 | /* 85221 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30588 | /* 85227 */ GIR_RootConstrainSelectedInstOperands, |
| 30589 | /* 85228 */ // GIR_Coverage, 4347, |
| 30590 | /* 85228 */ GIR_EraseRootFromParent_Done, |
| 30591 | /* 85229 */ // Label 1599: @85229 |
| 30592 | /* 85229 */ GIM_Try, /*On fail goto*//*Label 1600*/ GIMT_Encode4(85316), // Rule ID 4349 // |
| 30593 | /* 85234 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad), |
| 30594 | /* 85239 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 30595 | /* 85242 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 30596 | /* 85245 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 30597 | /* 85248 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16, |
| 30598 | /* 85251 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 30599 | /* 85254 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 30600 | /* 85257 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 30601 | /* 85260 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30602 | /* 85264 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30603 | /* 85268 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30604 | /* 85272 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30605 | /* 85276 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 30606 | /* 85280 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 30607 | /* 85284 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 30608 | /* 85288 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3668:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRDMLADHs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c) |
| 30609 | /* 85288 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLADHs16), |
| 30610 | /* 85291 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30611 | /* 85293 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 30612 | /* 85295 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 30613 | /* 85297 */ GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 30614 | /* 85299 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30615 | /* 85302 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30616 | /* 85308 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30617 | /* 85314 */ GIR_RootConstrainSelectedInstOperands, |
| 30618 | /* 85315 */ // GIR_Coverage, 4349, |
| 30619 | /* 85315 */ GIR_EraseRootFromParent_Done, |
| 30620 | /* 85316 */ // Label 1600: @85316 |
| 30621 | /* 85316 */ GIM_Try, /*On fail goto*//*Label 1601*/ GIMT_Encode4(85403), // Rule ID 4351 // |
| 30622 | /* 85321 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad), |
| 30623 | /* 85326 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 30624 | /* 85329 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 30625 | /* 85332 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 30626 | /* 85335 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 30627 | /* 85338 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 30628 | /* 85341 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 30629 | /* 85344 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 30630 | /* 85347 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30631 | /* 85351 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30632 | /* 85355 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30633 | /* 85359 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30634 | /* 85363 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 30635 | /* 85367 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 30636 | /* 85371 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 30637 | /* 85375 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3668:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRDMLADHs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c) |
| 30638 | /* 85375 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLADHs32), |
| 30639 | /* 85378 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30640 | /* 85380 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 30641 | /* 85382 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 30642 | /* 85384 */ GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 30643 | /* 85386 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30644 | /* 85389 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30645 | /* 85395 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30646 | /* 85401 */ GIR_RootConstrainSelectedInstOperands, |
| 30647 | /* 85402 */ // GIR_Coverage, 4351, |
| 30648 | /* 85402 */ GIR_EraseRootFromParent_Done, |
| 30649 | /* 85403 */ // Label 1601: @85403 |
| 30650 | /* 85403 */ GIM_Try, /*On fail goto*//*Label 1602*/ GIMT_Encode4(85490), // Rule ID 4353 // |
| 30651 | /* 85408 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad), |
| 30652 | /* 85413 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 30653 | /* 85416 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 30654 | /* 85419 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 30655 | /* 85422 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 30656 | /* 85425 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 30657 | /* 85428 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 30658 | /* 85431 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 30659 | /* 85434 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30660 | /* 85438 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30661 | /* 85442 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30662 | /* 85446 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30663 | /* 85450 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 30664 | /* 85454 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 30665 | /* 85458 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 30666 | /* 85462 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3668:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRDMLADHXs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c) |
| 30667 | /* 85462 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLADHXs8), |
| 30668 | /* 85465 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30669 | /* 85467 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 30670 | /* 85469 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 30671 | /* 85471 */ GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 30672 | /* 85473 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30673 | /* 85476 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30674 | /* 85482 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30675 | /* 85488 */ GIR_RootConstrainSelectedInstOperands, |
| 30676 | /* 85489 */ // GIR_Coverage, 4353, |
| 30677 | /* 85489 */ GIR_EraseRootFromParent_Done, |
| 30678 | /* 85490 */ // Label 1602: @85490 |
| 30679 | /* 85490 */ GIM_Try, /*On fail goto*//*Label 1603*/ GIMT_Encode4(85577), // Rule ID 4355 // |
| 30680 | /* 85495 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad), |
| 30681 | /* 85500 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 30682 | /* 85503 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 30683 | /* 85506 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 30684 | /* 85509 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16, |
| 30685 | /* 85512 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 30686 | /* 85515 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 30687 | /* 85518 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 30688 | /* 85521 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30689 | /* 85525 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30690 | /* 85529 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30691 | /* 85533 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30692 | /* 85537 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 30693 | /* 85541 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 30694 | /* 85545 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 30695 | /* 85549 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3668:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRDMLADHXs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c) |
| 30696 | /* 85549 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLADHXs16), |
| 30697 | /* 85552 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30698 | /* 85554 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 30699 | /* 85556 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 30700 | /* 85558 */ GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 30701 | /* 85560 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30702 | /* 85563 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30703 | /* 85569 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30704 | /* 85575 */ GIR_RootConstrainSelectedInstOperands, |
| 30705 | /* 85576 */ // GIR_Coverage, 4355, |
| 30706 | /* 85576 */ GIR_EraseRootFromParent_Done, |
| 30707 | /* 85577 */ // Label 1603: @85577 |
| 30708 | /* 85577 */ GIM_Try, /*On fail goto*//*Label 1604*/ GIMT_Encode4(85664), // Rule ID 4357 // |
| 30709 | /* 85582 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad), |
| 30710 | /* 85587 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 30711 | /* 85590 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 30712 | /* 85593 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 30713 | /* 85596 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 30714 | /* 85599 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 30715 | /* 85602 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 30716 | /* 85605 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 30717 | /* 85608 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30718 | /* 85612 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30719 | /* 85616 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30720 | /* 85620 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30721 | /* 85624 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 30722 | /* 85628 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 30723 | /* 85632 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 30724 | /* 85636 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3668:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRDMLADHXs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c) |
| 30725 | /* 85636 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLADHXs32), |
| 30726 | /* 85639 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30727 | /* 85641 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 30728 | /* 85643 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 30729 | /* 85645 */ GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 30730 | /* 85647 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30731 | /* 85650 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30732 | /* 85656 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30733 | /* 85662 */ GIR_RootConstrainSelectedInstOperands, |
| 30734 | /* 85663 */ // GIR_Coverage, 4357, |
| 30735 | /* 85663 */ GIR_EraseRootFromParent_Done, |
| 30736 | /* 85664 */ // Label 1604: @85664 |
| 30737 | /* 85664 */ GIM_Try, /*On fail goto*//*Label 1605*/ GIMT_Encode4(85751), // Rule ID 4359 // |
| 30738 | /* 85669 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad), |
| 30739 | /* 85674 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 30740 | /* 85677 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 30741 | /* 85680 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 30742 | /* 85683 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 30743 | /* 85686 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 30744 | /* 85689 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 30745 | /* 85692 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 30746 | /* 85695 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30747 | /* 85699 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30748 | /* 85703 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30749 | /* 85707 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30750 | /* 85711 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 30751 | /* 85715 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 30752 | /* 85719 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 30753 | /* 85723 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3668:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQDMLSDHs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c) |
| 30754 | /* 85723 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLSDHs8), |
| 30755 | /* 85726 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30756 | /* 85728 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 30757 | /* 85730 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 30758 | /* 85732 */ GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 30759 | /* 85734 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30760 | /* 85737 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30761 | /* 85743 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30762 | /* 85749 */ GIR_RootConstrainSelectedInstOperands, |
| 30763 | /* 85750 */ // GIR_Coverage, 4359, |
| 30764 | /* 85750 */ GIR_EraseRootFromParent_Done, |
| 30765 | /* 85751 */ // Label 1605: @85751 |
| 30766 | /* 85751 */ GIM_Try, /*On fail goto*//*Label 1606*/ GIMT_Encode4(85838), // Rule ID 4361 // |
| 30767 | /* 85756 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad), |
| 30768 | /* 85761 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 30769 | /* 85764 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 30770 | /* 85767 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 30771 | /* 85770 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16, |
| 30772 | /* 85773 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 30773 | /* 85776 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 30774 | /* 85779 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 30775 | /* 85782 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30776 | /* 85786 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30777 | /* 85790 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30778 | /* 85794 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30779 | /* 85798 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 30780 | /* 85802 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 30781 | /* 85806 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 30782 | /* 85810 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3668:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQDMLSDHs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c) |
| 30783 | /* 85810 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLSDHs16), |
| 30784 | /* 85813 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30785 | /* 85815 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 30786 | /* 85817 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 30787 | /* 85819 */ GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 30788 | /* 85821 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30789 | /* 85824 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30790 | /* 85830 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30791 | /* 85836 */ GIR_RootConstrainSelectedInstOperands, |
| 30792 | /* 85837 */ // GIR_Coverage, 4361, |
| 30793 | /* 85837 */ GIR_EraseRootFromParent_Done, |
| 30794 | /* 85838 */ // Label 1606: @85838 |
| 30795 | /* 85838 */ GIM_Try, /*On fail goto*//*Label 1607*/ GIMT_Encode4(85925), // Rule ID 4363 // |
| 30796 | /* 85843 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad), |
| 30797 | /* 85848 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 30798 | /* 85851 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 30799 | /* 85854 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 30800 | /* 85857 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 30801 | /* 85860 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 30802 | /* 85863 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 30803 | /* 85866 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 30804 | /* 85869 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30805 | /* 85873 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30806 | /* 85877 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30807 | /* 85881 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30808 | /* 85885 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 30809 | /* 85889 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 30810 | /* 85893 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 30811 | /* 85897 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3668:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQDMLSDHs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c) |
| 30812 | /* 85897 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLSDHs32), |
| 30813 | /* 85900 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30814 | /* 85902 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 30815 | /* 85904 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 30816 | /* 85906 */ GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 30817 | /* 85908 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30818 | /* 85911 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30819 | /* 85917 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30820 | /* 85923 */ GIR_RootConstrainSelectedInstOperands, |
| 30821 | /* 85924 */ // GIR_Coverage, 4363, |
| 30822 | /* 85924 */ GIR_EraseRootFromParent_Done, |
| 30823 | /* 85925 */ // Label 1607: @85925 |
| 30824 | /* 85925 */ GIM_Try, /*On fail goto*//*Label 1608*/ GIMT_Encode4(86012), // Rule ID 4365 // |
| 30825 | /* 85930 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad), |
| 30826 | /* 85935 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 30827 | /* 85938 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 30828 | /* 85941 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 30829 | /* 85944 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 30830 | /* 85947 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 30831 | /* 85950 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 30832 | /* 85953 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 30833 | /* 85956 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30834 | /* 85960 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30835 | /* 85964 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30836 | /* 85968 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30837 | /* 85972 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 30838 | /* 85976 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 30839 | /* 85980 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 30840 | /* 85984 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3668:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQDMLSDHXs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c) |
| 30841 | /* 85984 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLSDHXs8), |
| 30842 | /* 85987 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30843 | /* 85989 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 30844 | /* 85991 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 30845 | /* 85993 */ GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 30846 | /* 85995 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30847 | /* 85998 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30848 | /* 86004 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30849 | /* 86010 */ GIR_RootConstrainSelectedInstOperands, |
| 30850 | /* 86011 */ // GIR_Coverage, 4365, |
| 30851 | /* 86011 */ GIR_EraseRootFromParent_Done, |
| 30852 | /* 86012 */ // Label 1608: @86012 |
| 30853 | /* 86012 */ GIM_Try, /*On fail goto*//*Label 1609*/ GIMT_Encode4(86099), // Rule ID 4367 // |
| 30854 | /* 86017 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad), |
| 30855 | /* 86022 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 30856 | /* 86025 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 30857 | /* 86028 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 30858 | /* 86031 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16, |
| 30859 | /* 86034 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 30860 | /* 86037 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 30861 | /* 86040 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 30862 | /* 86043 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30863 | /* 86047 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30864 | /* 86051 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30865 | /* 86055 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30866 | /* 86059 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 30867 | /* 86063 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 30868 | /* 86067 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 30869 | /* 86071 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3668:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQDMLSDHXs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c) |
| 30870 | /* 86071 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLSDHXs16), |
| 30871 | /* 86074 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30872 | /* 86076 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 30873 | /* 86078 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 30874 | /* 86080 */ GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 30875 | /* 86082 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30876 | /* 86085 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30877 | /* 86091 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30878 | /* 86097 */ GIR_RootConstrainSelectedInstOperands, |
| 30879 | /* 86098 */ // GIR_Coverage, 4367, |
| 30880 | /* 86098 */ GIR_EraseRootFromParent_Done, |
| 30881 | /* 86099 */ // Label 1609: @86099 |
| 30882 | /* 86099 */ GIM_Try, /*On fail goto*//*Label 1610*/ GIMT_Encode4(86186), // Rule ID 4369 // |
| 30883 | /* 86104 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad), |
| 30884 | /* 86109 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 30885 | /* 86112 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 30886 | /* 86115 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 30887 | /* 86118 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 30888 | /* 86121 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 30889 | /* 86124 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 30890 | /* 86127 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 30891 | /* 86130 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30892 | /* 86134 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30893 | /* 86138 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30894 | /* 86142 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30895 | /* 86146 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 30896 | /* 86150 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 30897 | /* 86154 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 30898 | /* 86158 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3668:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQDMLSDHXs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c) |
| 30899 | /* 86158 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLSDHXs32), |
| 30900 | /* 86161 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30901 | /* 86163 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 30902 | /* 86165 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 30903 | /* 86167 */ GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 30904 | /* 86169 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30905 | /* 86172 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30906 | /* 86178 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30907 | /* 86184 */ GIR_RootConstrainSelectedInstOperands, |
| 30908 | /* 86185 */ // GIR_Coverage, 4369, |
| 30909 | /* 86185 */ GIR_EraseRootFromParent_Done, |
| 30910 | /* 86186 */ // Label 1610: @86186 |
| 30911 | /* 86186 */ GIM_Try, /*On fail goto*//*Label 1611*/ GIMT_Encode4(86273), // Rule ID 4371 // |
| 30912 | /* 86191 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad), |
| 30913 | /* 86196 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 30914 | /* 86199 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 30915 | /* 86202 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 30916 | /* 86205 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 30917 | /* 86208 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 30918 | /* 86211 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 30919 | /* 86214 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 30920 | /* 86217 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30921 | /* 86221 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30922 | /* 86225 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30923 | /* 86229 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30924 | /* 86233 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 30925 | /* 86237 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 30926 | /* 86241 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 30927 | /* 86245 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3668:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRDMLSDHs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c) |
| 30928 | /* 86245 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLSDHs8), |
| 30929 | /* 86248 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30930 | /* 86250 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 30931 | /* 86252 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 30932 | /* 86254 */ GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 30933 | /* 86256 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30934 | /* 86259 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30935 | /* 86265 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30936 | /* 86271 */ GIR_RootConstrainSelectedInstOperands, |
| 30937 | /* 86272 */ // GIR_Coverage, 4371, |
| 30938 | /* 86272 */ GIR_EraseRootFromParent_Done, |
| 30939 | /* 86273 */ // Label 1611: @86273 |
| 30940 | /* 86273 */ GIM_Try, /*On fail goto*//*Label 1612*/ GIMT_Encode4(86360), // Rule ID 4373 // |
| 30941 | /* 86278 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad), |
| 30942 | /* 86283 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 30943 | /* 86286 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 30944 | /* 86289 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 30945 | /* 86292 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16, |
| 30946 | /* 86295 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 30947 | /* 86298 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 30948 | /* 86301 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 30949 | /* 86304 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30950 | /* 86308 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30951 | /* 86312 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30952 | /* 86316 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30953 | /* 86320 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 30954 | /* 86324 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 30955 | /* 86328 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 30956 | /* 86332 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3668:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRDMLSDHs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c) |
| 30957 | /* 86332 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLSDHs16), |
| 30958 | /* 86335 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30959 | /* 86337 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 30960 | /* 86339 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 30961 | /* 86341 */ GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 30962 | /* 86343 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30963 | /* 86346 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30964 | /* 86352 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30965 | /* 86358 */ GIR_RootConstrainSelectedInstOperands, |
| 30966 | /* 86359 */ // GIR_Coverage, 4373, |
| 30967 | /* 86359 */ GIR_EraseRootFromParent_Done, |
| 30968 | /* 86360 */ // Label 1612: @86360 |
| 30969 | /* 86360 */ GIM_Try, /*On fail goto*//*Label 1613*/ GIMT_Encode4(86447), // Rule ID 4375 // |
| 30970 | /* 86365 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad), |
| 30971 | /* 86370 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 30972 | /* 86373 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 30973 | /* 86376 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 30974 | /* 86379 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 30975 | /* 86382 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 30976 | /* 86385 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 30977 | /* 86388 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 30978 | /* 86391 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30979 | /* 86395 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30980 | /* 86399 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30981 | /* 86403 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30982 | /* 86407 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 30983 | /* 86411 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 30984 | /* 86415 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 30985 | /* 86419 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3668:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRDMLSDHs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c) |
| 30986 | /* 86419 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLSDHs32), |
| 30987 | /* 86422 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30988 | /* 86424 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 30989 | /* 86426 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 30990 | /* 86428 */ GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 30991 | /* 86430 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30992 | /* 86433 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30993 | /* 86439 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30994 | /* 86445 */ GIR_RootConstrainSelectedInstOperands, |
| 30995 | /* 86446 */ // GIR_Coverage, 4375, |
| 30996 | /* 86446 */ GIR_EraseRootFromParent_Done, |
| 30997 | /* 86447 */ // Label 1613: @86447 |
| 30998 | /* 86447 */ GIM_Try, /*On fail goto*//*Label 1614*/ GIMT_Encode4(86534), // Rule ID 4377 // |
| 30999 | /* 86452 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad), |
| 31000 | /* 86457 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 31001 | /* 86460 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 31002 | /* 86463 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 31003 | /* 86466 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 31004 | /* 86469 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 31005 | /* 86472 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 31006 | /* 86475 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 31007 | /* 86478 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31008 | /* 86482 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31009 | /* 86486 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31010 | /* 86490 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31011 | /* 86494 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 31012 | /* 86498 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 31013 | /* 86502 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 31014 | /* 86506 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3668:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRDMLSDHXs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c) |
| 31015 | /* 86506 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLSDHXs8), |
| 31016 | /* 86509 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31017 | /* 86511 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 31018 | /* 86513 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 31019 | /* 86515 */ GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 31020 | /* 86517 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31021 | /* 86520 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31022 | /* 86526 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31023 | /* 86532 */ GIR_RootConstrainSelectedInstOperands, |
| 31024 | /* 86533 */ // GIR_Coverage, 4377, |
| 31025 | /* 86533 */ GIR_EraseRootFromParent_Done, |
| 31026 | /* 86534 */ // Label 1614: @86534 |
| 31027 | /* 86534 */ GIM_Try, /*On fail goto*//*Label 1615*/ GIMT_Encode4(86621), // Rule ID 4379 // |
| 31028 | /* 86539 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad), |
| 31029 | /* 86544 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 31030 | /* 86547 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 31031 | /* 86550 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 31032 | /* 86553 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16, |
| 31033 | /* 86556 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 31034 | /* 86559 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 31035 | /* 86562 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 31036 | /* 86565 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31037 | /* 86569 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31038 | /* 86573 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31039 | /* 86577 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31040 | /* 86581 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 31041 | /* 86585 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 31042 | /* 86589 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 31043 | /* 86593 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3668:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRDMLSDHXs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c) |
| 31044 | /* 86593 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLSDHXs16), |
| 31045 | /* 86596 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31046 | /* 86598 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 31047 | /* 86600 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 31048 | /* 86602 */ GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 31049 | /* 86604 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31050 | /* 86607 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31051 | /* 86613 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31052 | /* 86619 */ GIR_RootConstrainSelectedInstOperands, |
| 31053 | /* 86620 */ // GIR_Coverage, 4379, |
| 31054 | /* 86620 */ GIR_EraseRootFromParent_Done, |
| 31055 | /* 86621 */ // Label 1615: @86621 |
| 31056 | /* 86621 */ GIM_Try, /*On fail goto*//*Label 1616*/ GIMT_Encode4(86708), // Rule ID 4381 // |
| 31057 | /* 86626 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad), |
| 31058 | /* 86631 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 31059 | /* 86634 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 31060 | /* 86637 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 31061 | /* 86640 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 31062 | /* 86643 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 31063 | /* 86646 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 31064 | /* 86649 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 31065 | /* 86652 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31066 | /* 86656 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31067 | /* 86660 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31068 | /* 86664 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31069 | /* 86668 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 31070 | /* 86672 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 31071 | /* 86676 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 31072 | /* 86680 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3668:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRDMLSDHXs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c) |
| 31073 | /* 86680 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLSDHXs32), |
| 31074 | /* 86683 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31075 | /* 86685 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 31076 | /* 86687 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 31077 | /* 86689 */ GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 31078 | /* 86691 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31079 | /* 86694 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31080 | /* 86700 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31081 | /* 86706 */ GIR_RootConstrainSelectedInstOperands, |
| 31082 | /* 86707 */ // GIR_Coverage, 4381, |
| 31083 | /* 86707 */ GIR_EraseRootFromParent_Done, |
| 31084 | /* 86708 */ // Label 1616: @86708 |
| 31085 | /* 86708 */ GIM_Try, /*On fail goto*//*Label 1617*/ GIMT_Encode4(86834), // Rule ID 2692 // |
| 31086 | /* 86713 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 31087 | /* 86716 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vtbx4), |
| 31088 | /* 86721 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, |
| 31089 | /* 86724 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 31090 | /* 86727 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 31091 | /* 86730 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s8, |
| 31092 | /* 86733 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s8, |
| 31093 | /* 86736 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s8, |
| 31094 | /* 86739 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s8, |
| 31095 | /* 86742 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 31096 | /* 86746 */ // (intrinsic_wo_chain:{ *:[v8i8] } 3864:{ *:[iPTR] }, v8i8:{ *:[v8i8] }:$orig, v8i8:{ *:[v8i8] }:$Vn0, v8i8:{ *:[v8i8] }:$Vn1, v8i8:{ *:[v8i8] }:$Vn2, v8i8:{ *:[v8i8] }:$Vn3, v8i8:{ *:[v8i8] }:$Vm) => (VTBX4Pseudo:{ *:[v8i8] } v8i8:{ *:[v8i8] }:$orig, (REG_SEQUENCE:{ *:[v4i64] } QQPR:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn0, dsub_0:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn1, dsub_1:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn2, dsub_2:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn3, dsub_3:{ *:[i32] }), v8i8:{ *:[v8i8] }:$Vm) |
| 31097 | /* 86746 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s64, |
| 31098 | /* 86749 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 31099 | /* 86753 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 31100 | /* 86758 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // Vn0 |
| 31101 | /* 86762 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/1, |
| 31102 | /* 86765 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // Vn1 |
| 31103 | /* 86769 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/2, |
| 31104 | /* 86772 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/5, // Vn2 |
| 31105 | /* 86776 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 31106 | /* 86779 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/6, // Vn3 |
| 31107 | /* 86783 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/4, |
| 31108 | /* 86786 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::QQPRRegClassID), |
| 31109 | /* 86791 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(ARM::DPRRegClassID), |
| 31110 | /* 86796 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(ARM::DPRRegClassID), |
| 31111 | /* 86801 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/5, GIMT_Encode2(ARM::DPRRegClassID), |
| 31112 | /* 86806 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/7, GIMT_Encode2(ARM::DPRRegClassID), |
| 31113 | /* 86811 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VTBX4Pseudo), |
| 31114 | /* 86814 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 31115 | /* 86816 */ GIR_RootToRootCopy, /*OpIdx*/2, // orig |
| 31116 | /* 86818 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 31117 | /* 86821 */ GIR_RootToRootCopy, /*OpIdx*/7, // Vm |
| 31118 | /* 86823 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 31119 | /* 86826 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31120 | /* 86832 */ GIR_RootConstrainSelectedInstOperands, |
| 31121 | /* 86833 */ // GIR_Coverage, 2692, |
| 31122 | /* 86833 */ GIR_EraseRootFromParent_Done, |
| 31123 | /* 86834 */ // Label 1617: @86834 |
| 31124 | /* 86834 */ GIM_Reject, |
| 31125 | /* 86835 */ // Label 1562: @86835 |
| 31126 | /* 86835 */ GIM_Try, /*On fail goto*//*Label 1618*/ GIMT_Encode4(91129), |
| 31127 | /* 86840 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/10, |
| 31128 | /* 86843 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshrn), |
| 31129 | /* 86848 */ GIM_Try, /*On fail goto*//*Label 1619*/ GIMT_Encode4(86955), // Rule ID 3758 // |
| 31130 | /* 86853 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 31131 | /* 86856 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 31132 | /* 86859 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 31133 | /* 86862 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 31134 | /* 86865 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 31135 | /* 86868 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 31136 | /* 86871 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 31137 | /* 86874 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 31138 | /* 86877 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 31139 | /* 86880 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31140 | /* 86884 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31141 | /* 86888 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31142 | /* 86892 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 31143 | /* 86896 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 31144 | /* 86900 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8), |
| 31145 | /* 86904 */ // MIs[1] Operand 1 |
| 31146 | /* 86904 */ // No operand predicates |
| 31147 | /* 86904 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 31148 | /* 86908 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 31149 | /* 86912 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 31150 | /* 86916 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0, |
| 31151 | /* 86920 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0, |
| 31152 | /* 86924 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 31153 | /* 86926 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3712:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHRNi16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 31154 | /* 86926 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHRNi16bh), |
| 31155 | /* 86929 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31156 | /* 86931 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 31157 | /* 86933 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 31158 | /* 86935 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 31159 | /* 86938 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31160 | /* 86941 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31161 | /* 86947 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31162 | /* 86953 */ GIR_RootConstrainSelectedInstOperands, |
| 31163 | /* 86954 */ // GIR_Coverage, 3758, |
| 31164 | /* 86954 */ GIR_EraseRootFromParent_Done, |
| 31165 | /* 86955 */ // Label 1619: @86955 |
| 31166 | /* 86955 */ GIM_Try, /*On fail goto*//*Label 1620*/ GIMT_Encode4(87062), // Rule ID 3760 // |
| 31167 | /* 86960 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 31168 | /* 86963 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 31169 | /* 86966 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 31170 | /* 86969 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 31171 | /* 86972 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 31172 | /* 86975 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 31173 | /* 86978 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 31174 | /* 86981 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 31175 | /* 86984 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 31176 | /* 86987 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31177 | /* 86991 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31178 | /* 86995 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31179 | /* 86999 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 31180 | /* 87003 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 31181 | /* 87007 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8), |
| 31182 | /* 87011 */ // MIs[1] Operand 1 |
| 31183 | /* 87011 */ // No operand predicates |
| 31184 | /* 87011 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 31185 | /* 87015 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 31186 | /* 87019 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 31187 | /* 87023 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0, |
| 31188 | /* 87027 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1, |
| 31189 | /* 87031 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 31190 | /* 87033 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3712:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHRNi16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 31191 | /* 87033 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHRNi16th), |
| 31192 | /* 87036 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31193 | /* 87038 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 31194 | /* 87040 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 31195 | /* 87042 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 31196 | /* 87045 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31197 | /* 87048 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31198 | /* 87054 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31199 | /* 87060 */ GIR_RootConstrainSelectedInstOperands, |
| 31200 | /* 87061 */ // GIR_Coverage, 3760, |
| 31201 | /* 87061 */ GIR_EraseRootFromParent_Done, |
| 31202 | /* 87062 */ // Label 1620: @87062 |
| 31203 | /* 87062 */ GIM_Try, /*On fail goto*//*Label 1621*/ GIMT_Encode4(87169), // Rule ID 3762 // |
| 31204 | /* 87067 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 31205 | /* 87070 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 31206 | /* 87073 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 31207 | /* 87076 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 31208 | /* 87079 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 31209 | /* 87082 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 31210 | /* 87085 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 31211 | /* 87088 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 31212 | /* 87091 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 31213 | /* 87094 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31214 | /* 87098 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31215 | /* 87102 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31216 | /* 87106 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 31217 | /* 87110 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 31218 | /* 87114 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16), |
| 31219 | /* 87118 */ // MIs[1] Operand 1 |
| 31220 | /* 87118 */ // No operand predicates |
| 31221 | /* 87118 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 31222 | /* 87122 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 31223 | /* 87126 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 31224 | /* 87130 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0, |
| 31225 | /* 87134 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0, |
| 31226 | /* 87138 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 31227 | /* 87140 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3712:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHRNi32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 31228 | /* 87140 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHRNi32bh), |
| 31229 | /* 87143 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31230 | /* 87145 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 31231 | /* 87147 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 31232 | /* 87149 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 31233 | /* 87152 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31234 | /* 87155 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31235 | /* 87161 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31236 | /* 87167 */ GIR_RootConstrainSelectedInstOperands, |
| 31237 | /* 87168 */ // GIR_Coverage, 3762, |
| 31238 | /* 87168 */ GIR_EraseRootFromParent_Done, |
| 31239 | /* 87169 */ // Label 1621: @87169 |
| 31240 | /* 87169 */ GIM_Try, /*On fail goto*//*Label 1622*/ GIMT_Encode4(87276), // Rule ID 3764 // |
| 31241 | /* 87174 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 31242 | /* 87177 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 31243 | /* 87180 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 31244 | /* 87183 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 31245 | /* 87186 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 31246 | /* 87189 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 31247 | /* 87192 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 31248 | /* 87195 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 31249 | /* 87198 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 31250 | /* 87201 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31251 | /* 87205 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31252 | /* 87209 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31253 | /* 87213 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 31254 | /* 87217 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 31255 | /* 87221 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16), |
| 31256 | /* 87225 */ // MIs[1] Operand 1 |
| 31257 | /* 87225 */ // No operand predicates |
| 31258 | /* 87225 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 31259 | /* 87229 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 31260 | /* 87233 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 31261 | /* 87237 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0, |
| 31262 | /* 87241 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1, |
| 31263 | /* 87245 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 31264 | /* 87247 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3712:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHRNi32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 31265 | /* 87247 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHRNi32th), |
| 31266 | /* 87250 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31267 | /* 87252 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 31268 | /* 87254 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 31269 | /* 87256 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 31270 | /* 87259 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31271 | /* 87262 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31272 | /* 87268 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31273 | /* 87274 */ GIR_RootConstrainSelectedInstOperands, |
| 31274 | /* 87275 */ // GIR_Coverage, 3764, |
| 31275 | /* 87275 */ GIR_EraseRootFromParent_Done, |
| 31276 | /* 87276 */ // Label 1622: @87276 |
| 31277 | /* 87276 */ GIM_Try, /*On fail goto*//*Label 1623*/ GIMT_Encode4(87383), // Rule ID 3766 // |
| 31278 | /* 87281 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 31279 | /* 87284 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 31280 | /* 87287 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 31281 | /* 87290 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 31282 | /* 87293 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 31283 | /* 87296 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 31284 | /* 87299 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 31285 | /* 87302 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 31286 | /* 87305 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 31287 | /* 87308 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31288 | /* 87312 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31289 | /* 87316 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31290 | /* 87320 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 31291 | /* 87324 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 31292 | /* 87328 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8), |
| 31293 | /* 87332 */ // MIs[1] Operand 1 |
| 31294 | /* 87332 */ // No operand predicates |
| 31295 | /* 87332 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 31296 | /* 87336 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 31297 | /* 87340 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 31298 | /* 87344 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1, |
| 31299 | /* 87348 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0, |
| 31300 | /* 87352 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 31301 | /* 87354 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3712:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHRNi16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 31302 | /* 87354 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHRNi16bh), |
| 31303 | /* 87357 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31304 | /* 87359 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 31305 | /* 87361 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 31306 | /* 87363 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 31307 | /* 87366 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31308 | /* 87369 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31309 | /* 87375 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31310 | /* 87381 */ GIR_RootConstrainSelectedInstOperands, |
| 31311 | /* 87382 */ // GIR_Coverage, 3766, |
| 31312 | /* 87382 */ GIR_EraseRootFromParent_Done, |
| 31313 | /* 87383 */ // Label 1623: @87383 |
| 31314 | /* 87383 */ GIM_Try, /*On fail goto*//*Label 1624*/ GIMT_Encode4(87490), // Rule ID 3768 // |
| 31315 | /* 87388 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 31316 | /* 87391 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 31317 | /* 87394 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 31318 | /* 87397 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 31319 | /* 87400 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 31320 | /* 87403 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 31321 | /* 87406 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 31322 | /* 87409 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 31323 | /* 87412 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 31324 | /* 87415 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31325 | /* 87419 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31326 | /* 87423 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31327 | /* 87427 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 31328 | /* 87431 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 31329 | /* 87435 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8), |
| 31330 | /* 87439 */ // MIs[1] Operand 1 |
| 31331 | /* 87439 */ // No operand predicates |
| 31332 | /* 87439 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 31333 | /* 87443 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 31334 | /* 87447 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 31335 | /* 87451 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1, |
| 31336 | /* 87455 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1, |
| 31337 | /* 87459 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 31338 | /* 87461 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3712:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHRNi16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 31339 | /* 87461 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHRNi16th), |
| 31340 | /* 87464 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31341 | /* 87466 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 31342 | /* 87468 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 31343 | /* 87470 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 31344 | /* 87473 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31345 | /* 87476 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31346 | /* 87482 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31347 | /* 87488 */ GIR_RootConstrainSelectedInstOperands, |
| 31348 | /* 87489 */ // GIR_Coverage, 3768, |
| 31349 | /* 87489 */ GIR_EraseRootFromParent_Done, |
| 31350 | /* 87490 */ // Label 1624: @87490 |
| 31351 | /* 87490 */ GIM_Try, /*On fail goto*//*Label 1625*/ GIMT_Encode4(87597), // Rule ID 3770 // |
| 31352 | /* 87495 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 31353 | /* 87498 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 31354 | /* 87501 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 31355 | /* 87504 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 31356 | /* 87507 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 31357 | /* 87510 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 31358 | /* 87513 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 31359 | /* 87516 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 31360 | /* 87519 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 31361 | /* 87522 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31362 | /* 87526 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31363 | /* 87530 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31364 | /* 87534 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 31365 | /* 87538 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 31366 | /* 87542 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16), |
| 31367 | /* 87546 */ // MIs[1] Operand 1 |
| 31368 | /* 87546 */ // No operand predicates |
| 31369 | /* 87546 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 31370 | /* 87550 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 31371 | /* 87554 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 31372 | /* 87558 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1, |
| 31373 | /* 87562 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0, |
| 31374 | /* 87566 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 31375 | /* 87568 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3712:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHRNi32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 31376 | /* 87568 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHRNi32bh), |
| 31377 | /* 87571 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31378 | /* 87573 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 31379 | /* 87575 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 31380 | /* 87577 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 31381 | /* 87580 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31382 | /* 87583 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31383 | /* 87589 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31384 | /* 87595 */ GIR_RootConstrainSelectedInstOperands, |
| 31385 | /* 87596 */ // GIR_Coverage, 3770, |
| 31386 | /* 87596 */ GIR_EraseRootFromParent_Done, |
| 31387 | /* 87597 */ // Label 1625: @87597 |
| 31388 | /* 87597 */ GIM_Try, /*On fail goto*//*Label 1626*/ GIMT_Encode4(87704), // Rule ID 3772 // |
| 31389 | /* 87602 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 31390 | /* 87605 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 31391 | /* 87608 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 31392 | /* 87611 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 31393 | /* 87614 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 31394 | /* 87617 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 31395 | /* 87620 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 31396 | /* 87623 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 31397 | /* 87626 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 31398 | /* 87629 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31399 | /* 87633 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31400 | /* 87637 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31401 | /* 87641 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 31402 | /* 87645 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 31403 | /* 87649 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16), |
| 31404 | /* 87653 */ // MIs[1] Operand 1 |
| 31405 | /* 87653 */ // No operand predicates |
| 31406 | /* 87653 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 31407 | /* 87657 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 31408 | /* 87661 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 31409 | /* 87665 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1, |
| 31410 | /* 87669 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1, |
| 31411 | /* 87673 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 31412 | /* 87675 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3712:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHRNi32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 31413 | /* 87675 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHRNi32th), |
| 31414 | /* 87678 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31415 | /* 87680 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 31416 | /* 87682 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 31417 | /* 87684 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 31418 | /* 87687 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31419 | /* 87690 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31420 | /* 87696 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31421 | /* 87702 */ GIR_RootConstrainSelectedInstOperands, |
| 31422 | /* 87703 */ // GIR_Coverage, 3772, |
| 31423 | /* 87703 */ GIR_EraseRootFromParent_Done, |
| 31424 | /* 87704 */ // Label 1626: @87704 |
| 31425 | /* 87704 */ GIM_Try, /*On fail goto*//*Label 1627*/ GIMT_Encode4(87811), // Rule ID 3774 // |
| 31426 | /* 87709 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 31427 | /* 87712 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 31428 | /* 87715 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 31429 | /* 87718 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 31430 | /* 87721 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 31431 | /* 87724 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 31432 | /* 87727 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 31433 | /* 87730 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 31434 | /* 87733 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 31435 | /* 87736 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31436 | /* 87740 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31437 | /* 87744 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31438 | /* 87748 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 31439 | /* 87752 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 31440 | /* 87756 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8), |
| 31441 | /* 87760 */ // MIs[1] Operand 1 |
| 31442 | /* 87760 */ // No operand predicates |
| 31443 | /* 87760 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 31444 | /* 87764 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 31445 | /* 87768 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 31446 | /* 87772 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0, |
| 31447 | /* 87776 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0, |
| 31448 | /* 87780 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 31449 | /* 87782 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3712:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VRSHRNi16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 31450 | /* 87782 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHRNi16bh), |
| 31451 | /* 87785 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31452 | /* 87787 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 31453 | /* 87789 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 31454 | /* 87791 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 31455 | /* 87794 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31456 | /* 87797 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31457 | /* 87803 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31458 | /* 87809 */ GIR_RootConstrainSelectedInstOperands, |
| 31459 | /* 87810 */ // GIR_Coverage, 3774, |
| 31460 | /* 87810 */ GIR_EraseRootFromParent_Done, |
| 31461 | /* 87811 */ // Label 1627: @87811 |
| 31462 | /* 87811 */ GIM_Try, /*On fail goto*//*Label 1628*/ GIMT_Encode4(87918), // Rule ID 3776 // |
| 31463 | /* 87816 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 31464 | /* 87819 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 31465 | /* 87822 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 31466 | /* 87825 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 31467 | /* 87828 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 31468 | /* 87831 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 31469 | /* 87834 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 31470 | /* 87837 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 31471 | /* 87840 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 31472 | /* 87843 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31473 | /* 87847 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31474 | /* 87851 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31475 | /* 87855 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 31476 | /* 87859 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 31477 | /* 87863 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8), |
| 31478 | /* 87867 */ // MIs[1] Operand 1 |
| 31479 | /* 87867 */ // No operand predicates |
| 31480 | /* 87867 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 31481 | /* 87871 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 31482 | /* 87875 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 31483 | /* 87879 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0, |
| 31484 | /* 87883 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1, |
| 31485 | /* 87887 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 31486 | /* 87889 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3712:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VRSHRNi16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 31487 | /* 87889 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHRNi16th), |
| 31488 | /* 87892 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31489 | /* 87894 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 31490 | /* 87896 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 31491 | /* 87898 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 31492 | /* 87901 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31493 | /* 87904 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31494 | /* 87910 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31495 | /* 87916 */ GIR_RootConstrainSelectedInstOperands, |
| 31496 | /* 87917 */ // GIR_Coverage, 3776, |
| 31497 | /* 87917 */ GIR_EraseRootFromParent_Done, |
| 31498 | /* 87918 */ // Label 1628: @87918 |
| 31499 | /* 87918 */ GIM_Try, /*On fail goto*//*Label 1629*/ GIMT_Encode4(88025), // Rule ID 3778 // |
| 31500 | /* 87923 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 31501 | /* 87926 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 31502 | /* 87929 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 31503 | /* 87932 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 31504 | /* 87935 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 31505 | /* 87938 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 31506 | /* 87941 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 31507 | /* 87944 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 31508 | /* 87947 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 31509 | /* 87950 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31510 | /* 87954 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31511 | /* 87958 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31512 | /* 87962 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 31513 | /* 87966 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 31514 | /* 87970 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16), |
| 31515 | /* 87974 */ // MIs[1] Operand 1 |
| 31516 | /* 87974 */ // No operand predicates |
| 31517 | /* 87974 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 31518 | /* 87978 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 31519 | /* 87982 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 31520 | /* 87986 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0, |
| 31521 | /* 87990 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0, |
| 31522 | /* 87994 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 31523 | /* 87996 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3712:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VRSHRNi32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 31524 | /* 87996 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHRNi32bh), |
| 31525 | /* 87999 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31526 | /* 88001 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 31527 | /* 88003 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 31528 | /* 88005 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 31529 | /* 88008 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31530 | /* 88011 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31531 | /* 88017 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31532 | /* 88023 */ GIR_RootConstrainSelectedInstOperands, |
| 31533 | /* 88024 */ // GIR_Coverage, 3778, |
| 31534 | /* 88024 */ GIR_EraseRootFromParent_Done, |
| 31535 | /* 88025 */ // Label 1629: @88025 |
| 31536 | /* 88025 */ GIM_Try, /*On fail goto*//*Label 1630*/ GIMT_Encode4(88132), // Rule ID 3780 // |
| 31537 | /* 88030 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 31538 | /* 88033 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 31539 | /* 88036 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 31540 | /* 88039 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 31541 | /* 88042 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 31542 | /* 88045 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 31543 | /* 88048 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 31544 | /* 88051 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 31545 | /* 88054 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 31546 | /* 88057 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31547 | /* 88061 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31548 | /* 88065 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31549 | /* 88069 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 31550 | /* 88073 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 31551 | /* 88077 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16), |
| 31552 | /* 88081 */ // MIs[1] Operand 1 |
| 31553 | /* 88081 */ // No operand predicates |
| 31554 | /* 88081 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 31555 | /* 88085 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 31556 | /* 88089 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 31557 | /* 88093 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0, |
| 31558 | /* 88097 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1, |
| 31559 | /* 88101 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 31560 | /* 88103 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3712:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VRSHRNi32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 31561 | /* 88103 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHRNi32th), |
| 31562 | /* 88106 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31563 | /* 88108 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 31564 | /* 88110 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 31565 | /* 88112 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 31566 | /* 88115 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31567 | /* 88118 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31568 | /* 88124 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31569 | /* 88130 */ GIR_RootConstrainSelectedInstOperands, |
| 31570 | /* 88131 */ // GIR_Coverage, 3780, |
| 31571 | /* 88131 */ GIR_EraseRootFromParent_Done, |
| 31572 | /* 88132 */ // Label 1630: @88132 |
| 31573 | /* 88132 */ GIM_Try, /*On fail goto*//*Label 1631*/ GIMT_Encode4(88239), // Rule ID 3782 // |
| 31574 | /* 88137 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 31575 | /* 88140 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 31576 | /* 88143 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 31577 | /* 88146 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 31578 | /* 88149 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 31579 | /* 88152 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 31580 | /* 88155 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 31581 | /* 88158 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 31582 | /* 88161 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 31583 | /* 88164 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31584 | /* 88168 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31585 | /* 88172 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31586 | /* 88176 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 31587 | /* 88180 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 31588 | /* 88184 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8), |
| 31589 | /* 88188 */ // MIs[1] Operand 1 |
| 31590 | /* 88188 */ // No operand predicates |
| 31591 | /* 88188 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 31592 | /* 88192 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 31593 | /* 88196 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 31594 | /* 88200 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1, |
| 31595 | /* 88204 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0, |
| 31596 | /* 88208 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 31597 | /* 88210 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3712:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VRSHRNi16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 31598 | /* 88210 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHRNi16bh), |
| 31599 | /* 88213 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31600 | /* 88215 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 31601 | /* 88217 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 31602 | /* 88219 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 31603 | /* 88222 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31604 | /* 88225 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31605 | /* 88231 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31606 | /* 88237 */ GIR_RootConstrainSelectedInstOperands, |
| 31607 | /* 88238 */ // GIR_Coverage, 3782, |
| 31608 | /* 88238 */ GIR_EraseRootFromParent_Done, |
| 31609 | /* 88239 */ // Label 1631: @88239 |
| 31610 | /* 88239 */ GIM_Try, /*On fail goto*//*Label 1632*/ GIMT_Encode4(88346), // Rule ID 3784 // |
| 31611 | /* 88244 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 31612 | /* 88247 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 31613 | /* 88250 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 31614 | /* 88253 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 31615 | /* 88256 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 31616 | /* 88259 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 31617 | /* 88262 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 31618 | /* 88265 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 31619 | /* 88268 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 31620 | /* 88271 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31621 | /* 88275 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31622 | /* 88279 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31623 | /* 88283 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 31624 | /* 88287 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 31625 | /* 88291 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8), |
| 31626 | /* 88295 */ // MIs[1] Operand 1 |
| 31627 | /* 88295 */ // No operand predicates |
| 31628 | /* 88295 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 31629 | /* 88299 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 31630 | /* 88303 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 31631 | /* 88307 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1, |
| 31632 | /* 88311 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1, |
| 31633 | /* 88315 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 31634 | /* 88317 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3712:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VRSHRNi16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 31635 | /* 88317 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHRNi16th), |
| 31636 | /* 88320 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31637 | /* 88322 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 31638 | /* 88324 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 31639 | /* 88326 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 31640 | /* 88329 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31641 | /* 88332 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31642 | /* 88338 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31643 | /* 88344 */ GIR_RootConstrainSelectedInstOperands, |
| 31644 | /* 88345 */ // GIR_Coverage, 3784, |
| 31645 | /* 88345 */ GIR_EraseRootFromParent_Done, |
| 31646 | /* 88346 */ // Label 1632: @88346 |
| 31647 | /* 88346 */ GIM_Try, /*On fail goto*//*Label 1633*/ GIMT_Encode4(88453), // Rule ID 3786 // |
| 31648 | /* 88351 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 31649 | /* 88354 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 31650 | /* 88357 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 31651 | /* 88360 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 31652 | /* 88363 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 31653 | /* 88366 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 31654 | /* 88369 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 31655 | /* 88372 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 31656 | /* 88375 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 31657 | /* 88378 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31658 | /* 88382 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31659 | /* 88386 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31660 | /* 88390 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 31661 | /* 88394 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 31662 | /* 88398 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16), |
| 31663 | /* 88402 */ // MIs[1] Operand 1 |
| 31664 | /* 88402 */ // No operand predicates |
| 31665 | /* 88402 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 31666 | /* 88406 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 31667 | /* 88410 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 31668 | /* 88414 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1, |
| 31669 | /* 88418 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0, |
| 31670 | /* 88422 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 31671 | /* 88424 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3712:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VRSHRNi32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 31672 | /* 88424 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHRNi32bh), |
| 31673 | /* 88427 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31674 | /* 88429 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 31675 | /* 88431 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 31676 | /* 88433 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 31677 | /* 88436 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31678 | /* 88439 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31679 | /* 88445 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31680 | /* 88451 */ GIR_RootConstrainSelectedInstOperands, |
| 31681 | /* 88452 */ // GIR_Coverage, 3786, |
| 31682 | /* 88452 */ GIR_EraseRootFromParent_Done, |
| 31683 | /* 88453 */ // Label 1633: @88453 |
| 31684 | /* 88453 */ GIM_Try, /*On fail goto*//*Label 1634*/ GIMT_Encode4(88560), // Rule ID 3788 // |
| 31685 | /* 88458 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 31686 | /* 88461 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 31687 | /* 88464 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 31688 | /* 88467 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 31689 | /* 88470 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 31690 | /* 88473 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 31691 | /* 88476 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 31692 | /* 88479 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 31693 | /* 88482 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 31694 | /* 88485 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31695 | /* 88489 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31696 | /* 88493 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31697 | /* 88497 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 31698 | /* 88501 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 31699 | /* 88505 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16), |
| 31700 | /* 88509 */ // MIs[1] Operand 1 |
| 31701 | /* 88509 */ // No operand predicates |
| 31702 | /* 88509 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 31703 | /* 88513 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 31704 | /* 88517 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 31705 | /* 88521 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1, |
| 31706 | /* 88525 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1, |
| 31707 | /* 88529 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 31708 | /* 88531 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3712:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VRSHRNi32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 31709 | /* 88531 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHRNi32th), |
| 31710 | /* 88534 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31711 | /* 88536 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 31712 | /* 88538 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 31713 | /* 88540 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 31714 | /* 88543 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31715 | /* 88546 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31716 | /* 88552 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31717 | /* 88558 */ GIR_RootConstrainSelectedInstOperands, |
| 31718 | /* 88559 */ // GIR_Coverage, 3788, |
| 31719 | /* 88559 */ GIR_EraseRootFromParent_Done, |
| 31720 | /* 88560 */ // Label 1634: @88560 |
| 31721 | /* 88560 */ GIM_Try, /*On fail goto*//*Label 1635*/ GIMT_Encode4(88667), // Rule ID 3790 // |
| 31722 | /* 88565 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 31723 | /* 88568 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 31724 | /* 88571 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 31725 | /* 88574 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 31726 | /* 88577 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 31727 | /* 88580 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 31728 | /* 88583 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 31729 | /* 88586 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 31730 | /* 88589 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 31731 | /* 88592 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31732 | /* 88596 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31733 | /* 88600 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31734 | /* 88604 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 31735 | /* 88608 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 31736 | /* 88612 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8), |
| 31737 | /* 88616 */ // MIs[1] Operand 1 |
| 31738 | /* 88616 */ // No operand predicates |
| 31739 | /* 88616 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 31740 | /* 88620 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 31741 | /* 88624 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 31742 | /* 88628 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0, |
| 31743 | /* 88632 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0, |
| 31744 | /* 88636 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 31745 | /* 88638 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3712:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHRNbhs16:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 31746 | /* 88638 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRNbhs16), |
| 31747 | /* 88641 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31748 | /* 88643 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 31749 | /* 88645 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 31750 | /* 88647 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 31751 | /* 88650 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31752 | /* 88653 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31753 | /* 88659 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31754 | /* 88665 */ GIR_RootConstrainSelectedInstOperands, |
| 31755 | /* 88666 */ // GIR_Coverage, 3790, |
| 31756 | /* 88666 */ GIR_EraseRootFromParent_Done, |
| 31757 | /* 88667 */ // Label 1635: @88667 |
| 31758 | /* 88667 */ GIM_Try, /*On fail goto*//*Label 1636*/ GIMT_Encode4(88774), // Rule ID 3792 // |
| 31759 | /* 88672 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 31760 | /* 88675 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 31761 | /* 88678 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 31762 | /* 88681 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 31763 | /* 88684 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 31764 | /* 88687 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 31765 | /* 88690 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 31766 | /* 88693 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 31767 | /* 88696 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 31768 | /* 88699 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31769 | /* 88703 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31770 | /* 88707 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31771 | /* 88711 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 31772 | /* 88715 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 31773 | /* 88719 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8), |
| 31774 | /* 88723 */ // MIs[1] Operand 1 |
| 31775 | /* 88723 */ // No operand predicates |
| 31776 | /* 88723 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 31777 | /* 88727 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 31778 | /* 88731 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 31779 | /* 88735 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0, |
| 31780 | /* 88739 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1, |
| 31781 | /* 88743 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 31782 | /* 88745 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3712:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHRNths16:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 31783 | /* 88745 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRNths16), |
| 31784 | /* 88748 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31785 | /* 88750 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 31786 | /* 88752 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 31787 | /* 88754 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 31788 | /* 88757 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31789 | /* 88760 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31790 | /* 88766 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31791 | /* 88772 */ GIR_RootConstrainSelectedInstOperands, |
| 31792 | /* 88773 */ // GIR_Coverage, 3792, |
| 31793 | /* 88773 */ GIR_EraseRootFromParent_Done, |
| 31794 | /* 88774 */ // Label 1636: @88774 |
| 31795 | /* 88774 */ GIM_Try, /*On fail goto*//*Label 1637*/ GIMT_Encode4(88881), // Rule ID 3794 // |
| 31796 | /* 88779 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 31797 | /* 88782 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 31798 | /* 88785 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 31799 | /* 88788 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 31800 | /* 88791 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 31801 | /* 88794 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 31802 | /* 88797 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 31803 | /* 88800 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 31804 | /* 88803 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 31805 | /* 88806 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31806 | /* 88810 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31807 | /* 88814 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31808 | /* 88818 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 31809 | /* 88822 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 31810 | /* 88826 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16), |
| 31811 | /* 88830 */ // MIs[1] Operand 1 |
| 31812 | /* 88830 */ // No operand predicates |
| 31813 | /* 88830 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 31814 | /* 88834 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 31815 | /* 88838 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 31816 | /* 88842 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0, |
| 31817 | /* 88846 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0, |
| 31818 | /* 88850 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 31819 | /* 88852 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3712:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHRNbhs32:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 31820 | /* 88852 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRNbhs32), |
| 31821 | /* 88855 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31822 | /* 88857 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 31823 | /* 88859 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 31824 | /* 88861 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 31825 | /* 88864 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31826 | /* 88867 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31827 | /* 88873 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31828 | /* 88879 */ GIR_RootConstrainSelectedInstOperands, |
| 31829 | /* 88880 */ // GIR_Coverage, 3794, |
| 31830 | /* 88880 */ GIR_EraseRootFromParent_Done, |
| 31831 | /* 88881 */ // Label 1637: @88881 |
| 31832 | /* 88881 */ GIM_Try, /*On fail goto*//*Label 1638*/ GIMT_Encode4(88988), // Rule ID 3796 // |
| 31833 | /* 88886 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 31834 | /* 88889 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 31835 | /* 88892 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 31836 | /* 88895 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 31837 | /* 88898 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 31838 | /* 88901 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 31839 | /* 88904 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 31840 | /* 88907 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 31841 | /* 88910 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 31842 | /* 88913 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31843 | /* 88917 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31844 | /* 88921 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31845 | /* 88925 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 31846 | /* 88929 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 31847 | /* 88933 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16), |
| 31848 | /* 88937 */ // MIs[1] Operand 1 |
| 31849 | /* 88937 */ // No operand predicates |
| 31850 | /* 88937 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 31851 | /* 88941 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 31852 | /* 88945 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 31853 | /* 88949 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0, |
| 31854 | /* 88953 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1, |
| 31855 | /* 88957 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 31856 | /* 88959 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3712:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHRNths32:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 31857 | /* 88959 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRNths32), |
| 31858 | /* 88962 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31859 | /* 88964 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 31860 | /* 88966 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 31861 | /* 88968 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 31862 | /* 88971 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31863 | /* 88974 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31864 | /* 88980 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31865 | /* 88986 */ GIR_RootConstrainSelectedInstOperands, |
| 31866 | /* 88987 */ // GIR_Coverage, 3796, |
| 31867 | /* 88987 */ GIR_EraseRootFromParent_Done, |
| 31868 | /* 88988 */ // Label 1638: @88988 |
| 31869 | /* 88988 */ GIM_Try, /*On fail goto*//*Label 1639*/ GIMT_Encode4(89095), // Rule ID 3798 // |
| 31870 | /* 88993 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 31871 | /* 88996 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 31872 | /* 88999 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 31873 | /* 89002 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 31874 | /* 89005 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 31875 | /* 89008 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 31876 | /* 89011 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 31877 | /* 89014 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 31878 | /* 89017 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 31879 | /* 89020 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31880 | /* 89024 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31881 | /* 89028 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31882 | /* 89032 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 31883 | /* 89036 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 31884 | /* 89040 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8), |
| 31885 | /* 89044 */ // MIs[1] Operand 1 |
| 31886 | /* 89044 */ // No operand predicates |
| 31887 | /* 89044 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 31888 | /* 89048 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 31889 | /* 89052 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 31890 | /* 89056 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1, |
| 31891 | /* 89060 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0, |
| 31892 | /* 89064 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 31893 | /* 89066 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3712:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHRNbhu16:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 31894 | /* 89066 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRNbhu16), |
| 31895 | /* 89069 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31896 | /* 89071 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 31897 | /* 89073 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 31898 | /* 89075 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 31899 | /* 89078 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31900 | /* 89081 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31901 | /* 89087 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31902 | /* 89093 */ GIR_RootConstrainSelectedInstOperands, |
| 31903 | /* 89094 */ // GIR_Coverage, 3798, |
| 31904 | /* 89094 */ GIR_EraseRootFromParent_Done, |
| 31905 | /* 89095 */ // Label 1639: @89095 |
| 31906 | /* 89095 */ GIM_Try, /*On fail goto*//*Label 1640*/ GIMT_Encode4(89202), // Rule ID 3800 // |
| 31907 | /* 89100 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 31908 | /* 89103 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 31909 | /* 89106 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 31910 | /* 89109 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 31911 | /* 89112 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 31912 | /* 89115 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 31913 | /* 89118 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 31914 | /* 89121 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 31915 | /* 89124 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 31916 | /* 89127 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31917 | /* 89131 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31918 | /* 89135 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31919 | /* 89139 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 31920 | /* 89143 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 31921 | /* 89147 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8), |
| 31922 | /* 89151 */ // MIs[1] Operand 1 |
| 31923 | /* 89151 */ // No operand predicates |
| 31924 | /* 89151 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 31925 | /* 89155 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 31926 | /* 89159 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 31927 | /* 89163 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1, |
| 31928 | /* 89167 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1, |
| 31929 | /* 89171 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 31930 | /* 89173 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3712:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHRNthu16:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 31931 | /* 89173 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRNthu16), |
| 31932 | /* 89176 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31933 | /* 89178 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 31934 | /* 89180 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 31935 | /* 89182 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 31936 | /* 89185 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31937 | /* 89188 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31938 | /* 89194 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31939 | /* 89200 */ GIR_RootConstrainSelectedInstOperands, |
| 31940 | /* 89201 */ // GIR_Coverage, 3800, |
| 31941 | /* 89201 */ GIR_EraseRootFromParent_Done, |
| 31942 | /* 89202 */ // Label 1640: @89202 |
| 31943 | /* 89202 */ GIM_Try, /*On fail goto*//*Label 1641*/ GIMT_Encode4(89309), // Rule ID 3802 // |
| 31944 | /* 89207 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 31945 | /* 89210 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 31946 | /* 89213 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 31947 | /* 89216 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 31948 | /* 89219 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 31949 | /* 89222 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 31950 | /* 89225 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 31951 | /* 89228 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 31952 | /* 89231 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 31953 | /* 89234 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31954 | /* 89238 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31955 | /* 89242 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31956 | /* 89246 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 31957 | /* 89250 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 31958 | /* 89254 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16), |
| 31959 | /* 89258 */ // MIs[1] Operand 1 |
| 31960 | /* 89258 */ // No operand predicates |
| 31961 | /* 89258 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 31962 | /* 89262 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 31963 | /* 89266 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 31964 | /* 89270 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1, |
| 31965 | /* 89274 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0, |
| 31966 | /* 89278 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 31967 | /* 89280 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3712:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHRNbhu32:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 31968 | /* 89280 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRNbhu32), |
| 31969 | /* 89283 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31970 | /* 89285 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 31971 | /* 89287 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 31972 | /* 89289 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 31973 | /* 89292 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31974 | /* 89295 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31975 | /* 89301 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31976 | /* 89307 */ GIR_RootConstrainSelectedInstOperands, |
| 31977 | /* 89308 */ // GIR_Coverage, 3802, |
| 31978 | /* 89308 */ GIR_EraseRootFromParent_Done, |
| 31979 | /* 89309 */ // Label 1641: @89309 |
| 31980 | /* 89309 */ GIM_Try, /*On fail goto*//*Label 1642*/ GIMT_Encode4(89416), // Rule ID 3804 // |
| 31981 | /* 89314 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 31982 | /* 89317 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 31983 | /* 89320 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 31984 | /* 89323 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 31985 | /* 89326 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 31986 | /* 89329 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 31987 | /* 89332 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 31988 | /* 89335 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 31989 | /* 89338 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 31990 | /* 89341 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31991 | /* 89345 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31992 | /* 89349 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31993 | /* 89353 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 31994 | /* 89357 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 31995 | /* 89361 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16), |
| 31996 | /* 89365 */ // MIs[1] Operand 1 |
| 31997 | /* 89365 */ // No operand predicates |
| 31998 | /* 89365 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 31999 | /* 89369 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 32000 | /* 89373 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 32001 | /* 89377 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1, |
| 32002 | /* 89381 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1, |
| 32003 | /* 89385 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32004 | /* 89387 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3712:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHRNthu32:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 32005 | /* 89387 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRNthu32), |
| 32006 | /* 89390 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 32007 | /* 89392 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 32008 | /* 89394 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 32009 | /* 89396 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 32010 | /* 89399 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32011 | /* 89402 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32012 | /* 89408 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32013 | /* 89414 */ GIR_RootConstrainSelectedInstOperands, |
| 32014 | /* 89415 */ // GIR_Coverage, 3804, |
| 32015 | /* 89415 */ GIR_EraseRootFromParent_Done, |
| 32016 | /* 89416 */ // Label 1642: @89416 |
| 32017 | /* 89416 */ GIM_Try, /*On fail goto*//*Label 1643*/ GIMT_Encode4(89523), // Rule ID 3806 // |
| 32018 | /* 89421 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 32019 | /* 89424 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 32020 | /* 89427 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 32021 | /* 89430 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 32022 | /* 89433 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 32023 | /* 89436 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 32024 | /* 89439 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 32025 | /* 89442 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 32026 | /* 89445 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 32027 | /* 89448 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32028 | /* 89452 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32029 | /* 89456 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32030 | /* 89460 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 32031 | /* 89464 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32032 | /* 89468 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8), |
| 32033 | /* 89472 */ // MIs[1] Operand 1 |
| 32034 | /* 89472 */ // No operand predicates |
| 32035 | /* 89472 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 32036 | /* 89476 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 32037 | /* 89480 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 32038 | /* 89484 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0, |
| 32039 | /* 89488 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0, |
| 32040 | /* 89492 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32041 | /* 89494 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3712:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHRNbhs16:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 32042 | /* 89494 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRNbhs16), |
| 32043 | /* 89497 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 32044 | /* 89499 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 32045 | /* 89501 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 32046 | /* 89503 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 32047 | /* 89506 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32048 | /* 89509 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32049 | /* 89515 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32050 | /* 89521 */ GIR_RootConstrainSelectedInstOperands, |
| 32051 | /* 89522 */ // GIR_Coverage, 3806, |
| 32052 | /* 89522 */ GIR_EraseRootFromParent_Done, |
| 32053 | /* 89523 */ // Label 1643: @89523 |
| 32054 | /* 89523 */ GIM_Try, /*On fail goto*//*Label 1644*/ GIMT_Encode4(89630), // Rule ID 3808 // |
| 32055 | /* 89528 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 32056 | /* 89531 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 32057 | /* 89534 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 32058 | /* 89537 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 32059 | /* 89540 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 32060 | /* 89543 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 32061 | /* 89546 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 32062 | /* 89549 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 32063 | /* 89552 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 32064 | /* 89555 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32065 | /* 89559 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32066 | /* 89563 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32067 | /* 89567 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 32068 | /* 89571 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32069 | /* 89575 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8), |
| 32070 | /* 89579 */ // MIs[1] Operand 1 |
| 32071 | /* 89579 */ // No operand predicates |
| 32072 | /* 89579 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 32073 | /* 89583 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 32074 | /* 89587 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 32075 | /* 89591 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0, |
| 32076 | /* 89595 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1, |
| 32077 | /* 89599 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32078 | /* 89601 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3712:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHRNths16:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 32079 | /* 89601 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRNths16), |
| 32080 | /* 89604 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 32081 | /* 89606 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 32082 | /* 89608 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 32083 | /* 89610 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 32084 | /* 89613 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32085 | /* 89616 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32086 | /* 89622 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32087 | /* 89628 */ GIR_RootConstrainSelectedInstOperands, |
| 32088 | /* 89629 */ // GIR_Coverage, 3808, |
| 32089 | /* 89629 */ GIR_EraseRootFromParent_Done, |
| 32090 | /* 89630 */ // Label 1644: @89630 |
| 32091 | /* 89630 */ GIM_Try, /*On fail goto*//*Label 1645*/ GIMT_Encode4(89737), // Rule ID 3810 // |
| 32092 | /* 89635 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 32093 | /* 89638 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 32094 | /* 89641 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 32095 | /* 89644 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 32096 | /* 89647 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 32097 | /* 89650 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 32098 | /* 89653 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 32099 | /* 89656 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 32100 | /* 89659 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 32101 | /* 89662 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32102 | /* 89666 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32103 | /* 89670 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32104 | /* 89674 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 32105 | /* 89678 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32106 | /* 89682 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16), |
| 32107 | /* 89686 */ // MIs[1] Operand 1 |
| 32108 | /* 89686 */ // No operand predicates |
| 32109 | /* 89686 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 32110 | /* 89690 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 32111 | /* 89694 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 32112 | /* 89698 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0, |
| 32113 | /* 89702 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0, |
| 32114 | /* 89706 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32115 | /* 89708 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3712:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHRNbhs32:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 32116 | /* 89708 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRNbhs32), |
| 32117 | /* 89711 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 32118 | /* 89713 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 32119 | /* 89715 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 32120 | /* 89717 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 32121 | /* 89720 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32122 | /* 89723 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32123 | /* 89729 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32124 | /* 89735 */ GIR_RootConstrainSelectedInstOperands, |
| 32125 | /* 89736 */ // GIR_Coverage, 3810, |
| 32126 | /* 89736 */ GIR_EraseRootFromParent_Done, |
| 32127 | /* 89737 */ // Label 1645: @89737 |
| 32128 | /* 89737 */ GIM_Try, /*On fail goto*//*Label 1646*/ GIMT_Encode4(89844), // Rule ID 3812 // |
| 32129 | /* 89742 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 32130 | /* 89745 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 32131 | /* 89748 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 32132 | /* 89751 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 32133 | /* 89754 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 32134 | /* 89757 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 32135 | /* 89760 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 32136 | /* 89763 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 32137 | /* 89766 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 32138 | /* 89769 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32139 | /* 89773 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32140 | /* 89777 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32141 | /* 89781 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 32142 | /* 89785 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32143 | /* 89789 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16), |
| 32144 | /* 89793 */ // MIs[1] Operand 1 |
| 32145 | /* 89793 */ // No operand predicates |
| 32146 | /* 89793 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 32147 | /* 89797 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 32148 | /* 89801 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 32149 | /* 89805 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0, |
| 32150 | /* 89809 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1, |
| 32151 | /* 89813 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32152 | /* 89815 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3712:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHRNths32:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 32153 | /* 89815 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRNths32), |
| 32154 | /* 89818 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 32155 | /* 89820 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 32156 | /* 89822 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 32157 | /* 89824 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 32158 | /* 89827 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32159 | /* 89830 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32160 | /* 89836 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32161 | /* 89842 */ GIR_RootConstrainSelectedInstOperands, |
| 32162 | /* 89843 */ // GIR_Coverage, 3812, |
| 32163 | /* 89843 */ GIR_EraseRootFromParent_Done, |
| 32164 | /* 89844 */ // Label 1646: @89844 |
| 32165 | /* 89844 */ GIM_Try, /*On fail goto*//*Label 1647*/ GIMT_Encode4(89951), // Rule ID 3814 // |
| 32166 | /* 89849 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 32167 | /* 89852 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 32168 | /* 89855 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 32169 | /* 89858 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 32170 | /* 89861 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 32171 | /* 89864 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 32172 | /* 89867 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 32173 | /* 89870 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 32174 | /* 89873 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 32175 | /* 89876 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32176 | /* 89880 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32177 | /* 89884 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32178 | /* 89888 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 32179 | /* 89892 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32180 | /* 89896 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8), |
| 32181 | /* 89900 */ // MIs[1] Operand 1 |
| 32182 | /* 89900 */ // No operand predicates |
| 32183 | /* 89900 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 32184 | /* 89904 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 32185 | /* 89908 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 32186 | /* 89912 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1, |
| 32187 | /* 89916 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0, |
| 32188 | /* 89920 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32189 | /* 89922 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3712:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHRNbhu16:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 32190 | /* 89922 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRNbhu16), |
| 32191 | /* 89925 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 32192 | /* 89927 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 32193 | /* 89929 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 32194 | /* 89931 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 32195 | /* 89934 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32196 | /* 89937 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32197 | /* 89943 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32198 | /* 89949 */ GIR_RootConstrainSelectedInstOperands, |
| 32199 | /* 89950 */ // GIR_Coverage, 3814, |
| 32200 | /* 89950 */ GIR_EraseRootFromParent_Done, |
| 32201 | /* 89951 */ // Label 1647: @89951 |
| 32202 | /* 89951 */ GIM_Try, /*On fail goto*//*Label 1648*/ GIMT_Encode4(90058), // Rule ID 3816 // |
| 32203 | /* 89956 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 32204 | /* 89959 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 32205 | /* 89962 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 32206 | /* 89965 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 32207 | /* 89968 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 32208 | /* 89971 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 32209 | /* 89974 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 32210 | /* 89977 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 32211 | /* 89980 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 32212 | /* 89983 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32213 | /* 89987 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32214 | /* 89991 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32215 | /* 89995 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 32216 | /* 89999 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32217 | /* 90003 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8), |
| 32218 | /* 90007 */ // MIs[1] Operand 1 |
| 32219 | /* 90007 */ // No operand predicates |
| 32220 | /* 90007 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 32221 | /* 90011 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 32222 | /* 90015 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 32223 | /* 90019 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1, |
| 32224 | /* 90023 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1, |
| 32225 | /* 90027 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32226 | /* 90029 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3712:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHRNthu16:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 32227 | /* 90029 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRNthu16), |
| 32228 | /* 90032 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 32229 | /* 90034 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 32230 | /* 90036 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 32231 | /* 90038 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 32232 | /* 90041 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32233 | /* 90044 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32234 | /* 90050 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32235 | /* 90056 */ GIR_RootConstrainSelectedInstOperands, |
| 32236 | /* 90057 */ // GIR_Coverage, 3816, |
| 32237 | /* 90057 */ GIR_EraseRootFromParent_Done, |
| 32238 | /* 90058 */ // Label 1648: @90058 |
| 32239 | /* 90058 */ GIM_Try, /*On fail goto*//*Label 1649*/ GIMT_Encode4(90165), // Rule ID 3818 // |
| 32240 | /* 90063 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 32241 | /* 90066 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 32242 | /* 90069 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 32243 | /* 90072 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 32244 | /* 90075 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 32245 | /* 90078 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 32246 | /* 90081 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 32247 | /* 90084 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 32248 | /* 90087 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 32249 | /* 90090 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32250 | /* 90094 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32251 | /* 90098 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32252 | /* 90102 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 32253 | /* 90106 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32254 | /* 90110 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16), |
| 32255 | /* 90114 */ // MIs[1] Operand 1 |
| 32256 | /* 90114 */ // No operand predicates |
| 32257 | /* 90114 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 32258 | /* 90118 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 32259 | /* 90122 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 32260 | /* 90126 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1, |
| 32261 | /* 90130 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0, |
| 32262 | /* 90134 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32263 | /* 90136 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3712:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHRNbhu32:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 32264 | /* 90136 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRNbhu32), |
| 32265 | /* 90139 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 32266 | /* 90141 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 32267 | /* 90143 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 32268 | /* 90145 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 32269 | /* 90148 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32270 | /* 90151 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32271 | /* 90157 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32272 | /* 90163 */ GIR_RootConstrainSelectedInstOperands, |
| 32273 | /* 90164 */ // GIR_Coverage, 3818, |
| 32274 | /* 90164 */ GIR_EraseRootFromParent_Done, |
| 32275 | /* 90165 */ // Label 1649: @90165 |
| 32276 | /* 90165 */ GIM_Try, /*On fail goto*//*Label 1650*/ GIMT_Encode4(90272), // Rule ID 3820 // |
| 32277 | /* 90170 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 32278 | /* 90173 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 32279 | /* 90176 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 32280 | /* 90179 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 32281 | /* 90182 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 32282 | /* 90185 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 32283 | /* 90188 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 32284 | /* 90191 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 32285 | /* 90194 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 32286 | /* 90197 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32287 | /* 90201 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32288 | /* 90205 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32289 | /* 90209 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 32290 | /* 90213 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32291 | /* 90217 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16), |
| 32292 | /* 90221 */ // MIs[1] Operand 1 |
| 32293 | /* 90221 */ // No operand predicates |
| 32294 | /* 90221 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 32295 | /* 90225 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 32296 | /* 90229 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 32297 | /* 90233 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1, |
| 32298 | /* 90237 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1, |
| 32299 | /* 90241 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32300 | /* 90243 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3712:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHRNthu32:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 32301 | /* 90243 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRNthu32), |
| 32302 | /* 90246 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 32303 | /* 90248 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 32304 | /* 90250 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 32305 | /* 90252 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 32306 | /* 90255 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32307 | /* 90258 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32308 | /* 90264 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32309 | /* 90270 */ GIR_RootConstrainSelectedInstOperands, |
| 32310 | /* 90271 */ // GIR_Coverage, 3820, |
| 32311 | /* 90271 */ GIR_EraseRootFromParent_Done, |
| 32312 | /* 90272 */ // Label 1650: @90272 |
| 32313 | /* 90272 */ GIM_Try, /*On fail goto*//*Label 1651*/ GIMT_Encode4(90379), // Rule ID 3822 // |
| 32314 | /* 90277 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 32315 | /* 90280 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 32316 | /* 90283 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 32317 | /* 90286 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 32318 | /* 90289 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 32319 | /* 90292 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 32320 | /* 90295 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 32321 | /* 90298 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 32322 | /* 90301 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 32323 | /* 90304 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32324 | /* 90308 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32325 | /* 90312 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32326 | /* 90316 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 32327 | /* 90320 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32328 | /* 90324 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8), |
| 32329 | /* 90328 */ // MIs[1] Operand 1 |
| 32330 | /* 90328 */ // No operand predicates |
| 32331 | /* 90328 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 32332 | /* 90332 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 32333 | /* 90336 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 32334 | /* 90340 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0, |
| 32335 | /* 90344 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0, |
| 32336 | /* 90348 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32337 | /* 90350 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3712:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHRUNs16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 32338 | /* 90350 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRUNs16bh), |
| 32339 | /* 90353 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 32340 | /* 90355 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 32341 | /* 90357 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 32342 | /* 90359 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 32343 | /* 90362 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32344 | /* 90365 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32345 | /* 90371 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32346 | /* 90377 */ GIR_RootConstrainSelectedInstOperands, |
| 32347 | /* 90378 */ // GIR_Coverage, 3822, |
| 32348 | /* 90378 */ GIR_EraseRootFromParent_Done, |
| 32349 | /* 90379 */ // Label 1651: @90379 |
| 32350 | /* 90379 */ GIM_Try, /*On fail goto*//*Label 1652*/ GIMT_Encode4(90486), // Rule ID 3824 // |
| 32351 | /* 90384 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 32352 | /* 90387 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 32353 | /* 90390 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 32354 | /* 90393 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 32355 | /* 90396 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 32356 | /* 90399 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 32357 | /* 90402 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 32358 | /* 90405 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 32359 | /* 90408 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 32360 | /* 90411 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32361 | /* 90415 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32362 | /* 90419 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32363 | /* 90423 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 32364 | /* 90427 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32365 | /* 90431 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8), |
| 32366 | /* 90435 */ // MIs[1] Operand 1 |
| 32367 | /* 90435 */ // No operand predicates |
| 32368 | /* 90435 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 32369 | /* 90439 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 32370 | /* 90443 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 32371 | /* 90447 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0, |
| 32372 | /* 90451 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1, |
| 32373 | /* 90455 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32374 | /* 90457 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3712:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHRUNs16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 32375 | /* 90457 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRUNs16th), |
| 32376 | /* 90460 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 32377 | /* 90462 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 32378 | /* 90464 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 32379 | /* 90466 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 32380 | /* 90469 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32381 | /* 90472 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32382 | /* 90478 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32383 | /* 90484 */ GIR_RootConstrainSelectedInstOperands, |
| 32384 | /* 90485 */ // GIR_Coverage, 3824, |
| 32385 | /* 90485 */ GIR_EraseRootFromParent_Done, |
| 32386 | /* 90486 */ // Label 1652: @90486 |
| 32387 | /* 90486 */ GIM_Try, /*On fail goto*//*Label 1653*/ GIMT_Encode4(90593), // Rule ID 3826 // |
| 32388 | /* 90491 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 32389 | /* 90494 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 32390 | /* 90497 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 32391 | /* 90500 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 32392 | /* 90503 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 32393 | /* 90506 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 32394 | /* 90509 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 32395 | /* 90512 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 32396 | /* 90515 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 32397 | /* 90518 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32398 | /* 90522 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32399 | /* 90526 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32400 | /* 90530 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 32401 | /* 90534 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32402 | /* 90538 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16), |
| 32403 | /* 90542 */ // MIs[1] Operand 1 |
| 32404 | /* 90542 */ // No operand predicates |
| 32405 | /* 90542 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 32406 | /* 90546 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 32407 | /* 90550 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 32408 | /* 90554 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0, |
| 32409 | /* 90558 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0, |
| 32410 | /* 90562 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32411 | /* 90564 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3712:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHRUNs32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 32412 | /* 90564 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRUNs32bh), |
| 32413 | /* 90567 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 32414 | /* 90569 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 32415 | /* 90571 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 32416 | /* 90573 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 32417 | /* 90576 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32418 | /* 90579 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32419 | /* 90585 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32420 | /* 90591 */ GIR_RootConstrainSelectedInstOperands, |
| 32421 | /* 90592 */ // GIR_Coverage, 3826, |
| 32422 | /* 90592 */ GIR_EraseRootFromParent_Done, |
| 32423 | /* 90593 */ // Label 1653: @90593 |
| 32424 | /* 90593 */ GIM_Try, /*On fail goto*//*Label 1654*/ GIMT_Encode4(90700), // Rule ID 3828 // |
| 32425 | /* 90598 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 32426 | /* 90601 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 32427 | /* 90604 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 32428 | /* 90607 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 32429 | /* 90610 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 32430 | /* 90613 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 32431 | /* 90616 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 32432 | /* 90619 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 32433 | /* 90622 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 32434 | /* 90625 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32435 | /* 90629 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32436 | /* 90633 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32437 | /* 90637 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 32438 | /* 90641 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32439 | /* 90645 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16), |
| 32440 | /* 90649 */ // MIs[1] Operand 1 |
| 32441 | /* 90649 */ // No operand predicates |
| 32442 | /* 90649 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 32443 | /* 90653 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 32444 | /* 90657 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 32445 | /* 90661 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0, |
| 32446 | /* 90665 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1, |
| 32447 | /* 90669 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32448 | /* 90671 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3712:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHRUNs32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 32449 | /* 90671 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRUNs32th), |
| 32450 | /* 90674 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 32451 | /* 90676 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 32452 | /* 90678 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 32453 | /* 90680 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 32454 | /* 90683 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32455 | /* 90686 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32456 | /* 90692 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32457 | /* 90698 */ GIR_RootConstrainSelectedInstOperands, |
| 32458 | /* 90699 */ // GIR_Coverage, 3828, |
| 32459 | /* 90699 */ GIR_EraseRootFromParent_Done, |
| 32460 | /* 90700 */ // Label 1654: @90700 |
| 32461 | /* 90700 */ GIM_Try, /*On fail goto*//*Label 1655*/ GIMT_Encode4(90807), // Rule ID 3830 // |
| 32462 | /* 90705 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 32463 | /* 90708 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 32464 | /* 90711 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 32465 | /* 90714 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 32466 | /* 90717 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 32467 | /* 90720 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 32468 | /* 90723 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 32469 | /* 90726 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 32470 | /* 90729 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 32471 | /* 90732 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32472 | /* 90736 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32473 | /* 90740 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32474 | /* 90744 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 32475 | /* 90748 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32476 | /* 90752 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8), |
| 32477 | /* 90756 */ // MIs[1] Operand 1 |
| 32478 | /* 90756 */ // No operand predicates |
| 32479 | /* 90756 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 32480 | /* 90760 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 32481 | /* 90764 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 32482 | /* 90768 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0, |
| 32483 | /* 90772 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0, |
| 32484 | /* 90776 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32485 | /* 90778 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3712:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHRUNs16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 32486 | /* 90778 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRUNs16bh), |
| 32487 | /* 90781 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 32488 | /* 90783 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 32489 | /* 90785 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 32490 | /* 90787 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 32491 | /* 90790 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32492 | /* 90793 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32493 | /* 90799 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32494 | /* 90805 */ GIR_RootConstrainSelectedInstOperands, |
| 32495 | /* 90806 */ // GIR_Coverage, 3830, |
| 32496 | /* 90806 */ GIR_EraseRootFromParent_Done, |
| 32497 | /* 90807 */ // Label 1655: @90807 |
| 32498 | /* 90807 */ GIM_Try, /*On fail goto*//*Label 1656*/ GIMT_Encode4(90914), // Rule ID 3832 // |
| 32499 | /* 90812 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 32500 | /* 90815 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 32501 | /* 90818 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 32502 | /* 90821 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 32503 | /* 90824 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 32504 | /* 90827 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 32505 | /* 90830 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 32506 | /* 90833 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 32507 | /* 90836 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 32508 | /* 90839 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32509 | /* 90843 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32510 | /* 90847 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32511 | /* 90851 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 32512 | /* 90855 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32513 | /* 90859 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8), |
| 32514 | /* 90863 */ // MIs[1] Operand 1 |
| 32515 | /* 90863 */ // No operand predicates |
| 32516 | /* 90863 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 32517 | /* 90867 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 32518 | /* 90871 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 32519 | /* 90875 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0, |
| 32520 | /* 90879 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1, |
| 32521 | /* 90883 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32522 | /* 90885 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3712:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHRUNs16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 32523 | /* 90885 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRUNs16th), |
| 32524 | /* 90888 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 32525 | /* 90890 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 32526 | /* 90892 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 32527 | /* 90894 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 32528 | /* 90897 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32529 | /* 90900 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32530 | /* 90906 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32531 | /* 90912 */ GIR_RootConstrainSelectedInstOperands, |
| 32532 | /* 90913 */ // GIR_Coverage, 3832, |
| 32533 | /* 90913 */ GIR_EraseRootFromParent_Done, |
| 32534 | /* 90914 */ // Label 1656: @90914 |
| 32535 | /* 90914 */ GIM_Try, /*On fail goto*//*Label 1657*/ GIMT_Encode4(91021), // Rule ID 3834 // |
| 32536 | /* 90919 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 32537 | /* 90922 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 32538 | /* 90925 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 32539 | /* 90928 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 32540 | /* 90931 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 32541 | /* 90934 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 32542 | /* 90937 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 32543 | /* 90940 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 32544 | /* 90943 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 32545 | /* 90946 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32546 | /* 90950 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32547 | /* 90954 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32548 | /* 90958 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 32549 | /* 90962 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32550 | /* 90966 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16), |
| 32551 | /* 90970 */ // MIs[1] Operand 1 |
| 32552 | /* 90970 */ // No operand predicates |
| 32553 | /* 90970 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 32554 | /* 90974 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 32555 | /* 90978 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 32556 | /* 90982 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0, |
| 32557 | /* 90986 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0, |
| 32558 | /* 90990 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32559 | /* 90992 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3712:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHRUNs32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 32560 | /* 90992 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRUNs32bh), |
| 32561 | /* 90995 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 32562 | /* 90997 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 32563 | /* 90999 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 32564 | /* 91001 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 32565 | /* 91004 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32566 | /* 91007 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32567 | /* 91013 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32568 | /* 91019 */ GIR_RootConstrainSelectedInstOperands, |
| 32569 | /* 91020 */ // GIR_Coverage, 3834, |
| 32570 | /* 91020 */ GIR_EraseRootFromParent_Done, |
| 32571 | /* 91021 */ // Label 1657: @91021 |
| 32572 | /* 91021 */ GIM_Try, /*On fail goto*//*Label 1658*/ GIMT_Encode4(91128), // Rule ID 3836 // |
| 32573 | /* 91026 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 32574 | /* 91029 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 32575 | /* 91032 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 32576 | /* 91035 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 32577 | /* 91038 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 32578 | /* 91041 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 32579 | /* 91044 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 32580 | /* 91047 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 32581 | /* 91050 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 32582 | /* 91053 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32583 | /* 91057 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32584 | /* 91061 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32585 | /* 91065 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 32586 | /* 91069 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32587 | /* 91073 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16), |
| 32588 | /* 91077 */ // MIs[1] Operand 1 |
| 32589 | /* 91077 */ // No operand predicates |
| 32590 | /* 91077 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 32591 | /* 91081 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 32592 | /* 91085 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 32593 | /* 91089 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0, |
| 32594 | /* 91093 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1, |
| 32595 | /* 91097 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32596 | /* 91099 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3712:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHRUNs32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 32597 | /* 91099 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRUNs32th), |
| 32598 | /* 91102 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 32599 | /* 91104 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 32600 | /* 91106 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 32601 | /* 91108 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 32602 | /* 91111 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32603 | /* 91114 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32604 | /* 91120 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32605 | /* 91126 */ GIR_RootConstrainSelectedInstOperands, |
| 32606 | /* 91127 */ // GIR_Coverage, 3836, |
| 32607 | /* 91127 */ GIR_EraseRootFromParent_Done, |
| 32608 | /* 91128 */ // Label 1658: @91128 |
| 32609 | /* 91128 */ GIM_Reject, |
| 32610 | /* 91129 */ // Label 1618: @91129 |
| 32611 | /* 91129 */ GIM_Reject, |
| 32612 | /* 91130 */ // Label 16: @91130 |
| 32613 | /* 91130 */ GIM_Try, /*On fail goto*//*Label 1659*/ GIMT_Encode4(91187), |
| 32614 | /* 91135 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/1, |
| 32615 | /* 91138 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_clrex), |
| 32616 | /* 91143 */ GIM_Try, /*On fail goto*//*Label 1660*/ GIMT_Encode4(91160), // Rule ID 245 // |
| 32617 | /* 91148 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6K_IsARM), |
| 32618 | /* 91151 */ // (intrinsic_void 3498:{ *:[iPTR] }) => (CLREX) |
| 32619 | /* 91151 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::CLREX), |
| 32620 | /* 91154 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 32621 | /* 91158 */ GIR_RootConstrainSelectedInstOperands, |
| 32622 | /* 91159 */ // GIR_Coverage, 245, |
| 32623 | /* 91159 */ GIR_EraseRootFromParent_Done, |
| 32624 | /* 91160 */ // Label 1660: @91160 |
| 32625 | /* 91160 */ GIM_Try, /*On fail goto*//*Label 1661*/ GIMT_Encode4(91186), // Rule ID 574 // |
| 32626 | /* 91165 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV7Clrex_IsThumb), |
| 32627 | /* 91168 */ // (intrinsic_void 3498:{ *:[iPTR] }) => (t2CLREX) |
| 32628 | /* 91168 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2CLREX), |
| 32629 | /* 91171 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 32630 | /* 91174 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32631 | /* 91180 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 32632 | /* 91184 */ GIR_RootConstrainSelectedInstOperands, |
| 32633 | /* 91185 */ // GIR_Coverage, 574, |
| 32634 | /* 91185 */ GIR_EraseRootFromParent_Done, |
| 32635 | /* 91186 */ // Label 1661: @91186 |
| 32636 | /* 91186 */ GIM_Reject, |
| 32637 | /* 91187 */ // Label 1659: @91187 |
| 32638 | /* 91187 */ GIM_Try, /*On fail goto*//*Label 1662*/ GIMT_Encode4(91989), |
| 32639 | /* 91192 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/2, |
| 32640 | /* 91195 */ GIM_Try, /*On fail goto*//*Label 1663*/ GIMT_Encode4(91231), // Rule ID 344 // |
| 32641 | /* 91200 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb_IsWindows), |
| 32642 | /* 91203 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_undefined), |
| 32643 | /* 91208 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 32644 | /* 91211 */ GIM_CheckConstantInt, /*MI*/0, /*Op*/1, GIMT_Encode8(249), |
| 32645 | /* 91222 */ // (intrinsic_void 3933:{ *:[iPTR] }, 249:{ *:[i32] }) => (t__brkdiv0) |
| 32646 | /* 91222 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t__brkdiv0), |
| 32647 | /* 91225 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 32648 | /* 91229 */ GIR_RootConstrainSelectedInstOperands, |
| 32649 | /* 91230 */ // GIR_Coverage, 344, |
| 32650 | /* 91230 */ GIR_EraseRootFromParent_Done, |
| 32651 | /* 91231 */ // Label 1663: @91231 |
| 32652 | /* 91231 */ GIM_Try, /*On fail goto*//*Label 1664*/ GIMT_Encode4(91283), // Rule ID 2 // |
| 32653 | /* 91236 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 32654 | /* 91239 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_hint), |
| 32655 | /* 91244 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 32656 | /* 91247 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 32657 | /* 91251 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32658 | /* 91255 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_239), |
| 32659 | /* 91259 */ // MIs[1] Operand 1 |
| 32660 | /* 91259 */ // No operand predicates |
| 32661 | /* 91259 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32662 | /* 91261 */ // (intrinsic_void 3516:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_239>>:$imm) => (HINT (imm:{ *:[i32] }):$imm) |
| 32663 | /* 91261 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::HINT), |
| 32664 | /* 91264 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 32665 | /* 91267 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 32666 | /* 91270 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32667 | /* 91276 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 32668 | /* 91281 */ GIR_RootConstrainSelectedInstOperands, |
| 32669 | /* 91282 */ // GIR_Coverage, 2, |
| 32670 | /* 91282 */ GIR_EraseRootFromParent_Done, |
| 32671 | /* 91283 */ // Label 1664: @91283 |
| 32672 | /* 91283 */ GIM_Try, /*On fail goto*//*Label 1665*/ GIMT_Encode4(91335), // Rule ID 10 // |
| 32673 | /* 91288 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV7_IsARM), |
| 32674 | /* 91291 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_dbg), |
| 32675 | /* 91296 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 32676 | /* 91299 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 32677 | /* 91303 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32678 | /* 91307 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15), |
| 32679 | /* 91311 */ // MIs[1] Operand 1 |
| 32680 | /* 91311 */ // No operand predicates |
| 32681 | /* 91311 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32682 | /* 91313 */ // (intrinsic_void 3511:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$opt) => (DBG (imm:{ *:[i32] }):$opt) |
| 32683 | /* 91313 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::DBG), |
| 32684 | /* 91316 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt |
| 32685 | /* 91319 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 32686 | /* 91322 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32687 | /* 91328 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 32688 | /* 91333 */ GIR_RootConstrainSelectedInstOperands, |
| 32689 | /* 91334 */ // GIR_Coverage, 10, |
| 32690 | /* 91334 */ GIR_EraseRootFromParent_Done, |
| 32691 | /* 91335 */ // Label 1665: @91335 |
| 32692 | /* 91335 */ GIM_Try, /*On fail goto*//*Label 1666*/ GIMT_Encode4(91378), // Rule ID 11 // |
| 32693 | /* 91340 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 32694 | /* 91343 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_undefined), |
| 32695 | /* 91348 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 32696 | /* 91351 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 32697 | /* 91355 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32698 | /* 91359 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_65535), |
| 32699 | /* 91363 */ // MIs[1] Operand 1 |
| 32700 | /* 91363 */ // No operand predicates |
| 32701 | /* 91363 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32702 | /* 91365 */ // (intrinsic_void 3933:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_65535>>:$imm16) => (UDF (imm:{ *:[i32] }):$imm16) |
| 32703 | /* 91365 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UDF), |
| 32704 | /* 91368 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm16 |
| 32705 | /* 91371 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 32706 | /* 91376 */ GIR_RootConstrainSelectedInstOperands, |
| 32707 | /* 91377 */ // GIR_Coverage, 11, |
| 32708 | /* 91377 */ GIR_EraseRootFromParent_Done, |
| 32709 | /* 91378 */ // Label 1666: @91378 |
| 32710 | /* 91378 */ GIM_Try, /*On fail goto*//*Label 1667*/ GIMT_Encode4(91421), // Rule ID 228 // |
| 32711 | /* 91383 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDB_IsARM), |
| 32712 | /* 91386 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_dmb), |
| 32713 | /* 91391 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 32714 | /* 91394 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 32715 | /* 91398 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32716 | /* 91402 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15), |
| 32717 | /* 91406 */ // MIs[1] Operand 1 |
| 32718 | /* 91406 */ // No operand predicates |
| 32719 | /* 91406 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32720 | /* 91408 */ // (intrinsic_void 3512:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$opt) => (DMB (imm:{ *:[i32] }):$opt) |
| 32721 | /* 91408 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::DMB), |
| 32722 | /* 91411 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt |
| 32723 | /* 91414 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 32724 | /* 91419 */ GIR_RootConstrainSelectedInstOperands, |
| 32725 | /* 91420 */ // GIR_Coverage, 228, |
| 32726 | /* 91420 */ GIR_EraseRootFromParent_Done, |
| 32727 | /* 91421 */ // Label 1667: @91421 |
| 32728 | /* 91421 */ GIM_Try, /*On fail goto*//*Label 1668*/ GIMT_Encode4(91464), // Rule ID 229 // |
| 32729 | /* 91426 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDB_IsARM), |
| 32730 | /* 91429 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_dsb), |
| 32731 | /* 91434 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 32732 | /* 91437 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 32733 | /* 91441 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32734 | /* 91445 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15), |
| 32735 | /* 91449 */ // MIs[1] Operand 1 |
| 32736 | /* 91449 */ // No operand predicates |
| 32737 | /* 91449 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32738 | /* 91451 */ // (intrinsic_void 3513:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$opt) => (DSB (imm:{ *:[i32] }):$opt) |
| 32739 | /* 91451 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::DSB), |
| 32740 | /* 91454 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt |
| 32741 | /* 91457 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 32742 | /* 91462 */ GIR_RootConstrainSelectedInstOperands, |
| 32743 | /* 91463 */ // GIR_Coverage, 229, |
| 32744 | /* 91463 */ GIR_EraseRootFromParent_Done, |
| 32745 | /* 91464 */ // Label 1668: @91464 |
| 32746 | /* 91464 */ GIM_Try, /*On fail goto*//*Label 1669*/ GIMT_Encode4(91507), // Rule ID 230 // |
| 32747 | /* 91469 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDB_IsARM), |
| 32748 | /* 91472 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_isb), |
| 32749 | /* 91477 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 32750 | /* 91480 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 32751 | /* 91484 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32752 | /* 91488 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15), |
| 32753 | /* 91492 */ // MIs[1] Operand 1 |
| 32754 | /* 91492 */ // No operand predicates |
| 32755 | /* 91492 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32756 | /* 91494 */ // (intrinsic_void 3517:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$opt) => (ISB (imm:{ *:[i32] }):$opt) |
| 32757 | /* 91494 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::ISB), |
| 32758 | /* 91497 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt |
| 32759 | /* 91500 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 32760 | /* 91505 */ GIR_RootConstrainSelectedInstOperands, |
| 32761 | /* 91506 */ // GIR_Coverage, 230, |
| 32762 | /* 91506 */ GIR_EraseRootFromParent_Done, |
| 32763 | /* 91507 */ // Label 1669: @91507 |
| 32764 | /* 91507 */ GIM_Try, /*On fail goto*//*Label 1670*/ GIMT_Encode4(91559), // Rule ID 276 // |
| 32765 | /* 91512 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6M_IsThumb), |
| 32766 | /* 91515 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_hint), |
| 32767 | /* 91520 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 32768 | /* 91523 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 32769 | /* 91527 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32770 | /* 91531 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15), |
| 32771 | /* 91535 */ // MIs[1] Operand 1 |
| 32772 | /* 91535 */ // No operand predicates |
| 32773 | /* 91535 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32774 | /* 91537 */ // (intrinsic_void 3516:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$imm) => (tHINT (imm:{ *:[i32] }):$imm) |
| 32775 | /* 91537 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tHINT), |
| 32776 | /* 91540 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 32777 | /* 91543 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 32778 | /* 91546 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32779 | /* 91552 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 32780 | /* 91557 */ GIR_RootConstrainSelectedInstOperands, |
| 32781 | /* 91558 */ // GIR_Coverage, 276, |
| 32782 | /* 91558 */ GIR_EraseRootFromParent_Done, |
| 32783 | /* 91559 */ // Label 1670: @91559 |
| 32784 | /* 91559 */ GIM_Try, /*On fail goto*//*Label 1671*/ GIMT_Encode4(91602), // Rule ID 343 // |
| 32785 | /* 91564 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb), |
| 32786 | /* 91567 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_undefined), |
| 32787 | /* 91572 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 32788 | /* 91575 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 32789 | /* 91579 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32790 | /* 91583 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_255), |
| 32791 | /* 91587 */ // MIs[1] Operand 1 |
| 32792 | /* 91587 */ // No operand predicates |
| 32793 | /* 91587 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32794 | /* 91589 */ // (intrinsic_void 3933:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_255>>:$imm8) => (tUDF (imm:{ *:[i32] }):$imm8) |
| 32795 | /* 91589 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tUDF), |
| 32796 | /* 91592 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm8 |
| 32797 | /* 91595 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 32798 | /* 91600 */ GIR_RootConstrainSelectedInstOperands, |
| 32799 | /* 91601 */ // GIR_Coverage, 343, |
| 32800 | /* 91601 */ GIR_EraseRootFromParent_Done, |
| 32801 | /* 91602 */ // Label 1671: @91602 |
| 32802 | /* 91602 */ GIM_Try, /*On fail goto*//*Label 1672*/ GIMT_Encode4(91645), // Rule ID 494 // |
| 32803 | /* 91607 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 32804 | /* 91610 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_undefined), |
| 32805 | /* 91615 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 32806 | /* 91618 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 32807 | /* 91622 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32808 | /* 91626 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_65535), |
| 32809 | /* 91630 */ // MIs[1] Operand 1 |
| 32810 | /* 91630 */ // No operand predicates |
| 32811 | /* 91630 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32812 | /* 91632 */ // (intrinsic_void 3933:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_65535>>:$imm16) => (t2UDF (imm:{ *:[i32] }):$imm16) |
| 32813 | /* 91632 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UDF), |
| 32814 | /* 91635 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm16 |
| 32815 | /* 91638 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 32816 | /* 91643 */ GIR_RootConstrainSelectedInstOperands, |
| 32817 | /* 91644 */ // GIR_Coverage, 494, |
| 32818 | /* 91644 */ GIR_EraseRootFromParent_Done, |
| 32819 | /* 91645 */ // Label 1672: @91645 |
| 32820 | /* 91645 */ GIM_Try, /*On fail goto*//*Label 1673*/ GIMT_Encode4(91697), // Rule ID 559 // |
| 32821 | /* 91650 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDB_IsThumb), |
| 32822 | /* 91653 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_dmb), |
| 32823 | /* 91658 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 32824 | /* 91661 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 32825 | /* 91665 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32826 | /* 91669 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15), |
| 32827 | /* 91673 */ // MIs[1] Operand 1 |
| 32828 | /* 91673 */ // No operand predicates |
| 32829 | /* 91673 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32830 | /* 91675 */ // (intrinsic_void 3512:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$opt) => (t2DMB (imm:{ *:[i32] }):$opt) |
| 32831 | /* 91675 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2DMB), |
| 32832 | /* 91678 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt |
| 32833 | /* 91681 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 32834 | /* 91684 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32835 | /* 91690 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 32836 | /* 91695 */ GIR_RootConstrainSelectedInstOperands, |
| 32837 | /* 91696 */ // GIR_Coverage, 559, |
| 32838 | /* 91696 */ GIR_EraseRootFromParent_Done, |
| 32839 | /* 91697 */ // Label 1673: @91697 |
| 32840 | /* 91697 */ GIM_Try, /*On fail goto*//*Label 1674*/ GIMT_Encode4(91749), // Rule ID 560 // |
| 32841 | /* 91702 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDB_IsThumb), |
| 32842 | /* 91705 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_dsb), |
| 32843 | /* 91710 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 32844 | /* 91713 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 32845 | /* 91717 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32846 | /* 91721 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15), |
| 32847 | /* 91725 */ // MIs[1] Operand 1 |
| 32848 | /* 91725 */ // No operand predicates |
| 32849 | /* 91725 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32850 | /* 91727 */ // (intrinsic_void 3513:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$opt) => (t2DSB (imm:{ *:[i32] }):$opt) |
| 32851 | /* 91727 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2DSB), |
| 32852 | /* 91730 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt |
| 32853 | /* 91733 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 32854 | /* 91736 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32855 | /* 91742 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 32856 | /* 91747 */ GIR_RootConstrainSelectedInstOperands, |
| 32857 | /* 91748 */ // GIR_Coverage, 560, |
| 32858 | /* 91748 */ GIR_EraseRootFromParent_Done, |
| 32859 | /* 91749 */ // Label 1674: @91749 |
| 32860 | /* 91749 */ GIM_Try, /*On fail goto*//*Label 1675*/ GIMT_Encode4(91801), // Rule ID 561 // |
| 32861 | /* 91754 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDB_IsThumb), |
| 32862 | /* 91757 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_isb), |
| 32863 | /* 91762 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 32864 | /* 91765 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 32865 | /* 91769 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32866 | /* 91773 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15), |
| 32867 | /* 91777 */ // MIs[1] Operand 1 |
| 32868 | /* 91777 */ // No operand predicates |
| 32869 | /* 91777 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32870 | /* 91779 */ // (intrinsic_void 3517:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$opt) => (t2ISB (imm:{ *:[i32] }):$opt) |
| 32871 | /* 91779 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ISB), |
| 32872 | /* 91782 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt |
| 32873 | /* 91785 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 32874 | /* 91788 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32875 | /* 91794 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 32876 | /* 91799 */ GIR_RootConstrainSelectedInstOperands, |
| 32877 | /* 91800 */ // GIR_Coverage, 561, |
| 32878 | /* 91800 */ GIR_EraseRootFromParent_Done, |
| 32879 | /* 91801 */ // Label 1675: @91801 |
| 32880 | /* 91801 */ GIM_Try, /*On fail goto*//*Label 1676*/ GIMT_Encode4(91853), // Rule ID 579 // |
| 32881 | /* 91806 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 32882 | /* 91809 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_hint), |
| 32883 | /* 91814 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 32884 | /* 91817 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 32885 | /* 91821 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32886 | /* 91825 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_239), |
| 32887 | /* 91829 */ // MIs[1] Operand 1 |
| 32888 | /* 91829 */ // No operand predicates |
| 32889 | /* 91829 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32890 | /* 91831 */ // (intrinsic_void 3516:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_239>>:$imm) => (t2HINT (imm:{ *:[i32] }):$imm) |
| 32891 | /* 91831 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2HINT), |
| 32892 | /* 91834 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 32893 | /* 91837 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 32894 | /* 91840 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32895 | /* 91846 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 32896 | /* 91851 */ GIR_RootConstrainSelectedInstOperands, |
| 32897 | /* 91852 */ // GIR_Coverage, 579, |
| 32898 | /* 91852 */ GIR_EraseRootFromParent_Done, |
| 32899 | /* 91853 */ // Label 1676: @91853 |
| 32900 | /* 91853 */ GIM_Try, /*On fail goto*//*Label 1677*/ GIMT_Encode4(91905), // Rule ID 580 // |
| 32901 | /* 91858 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 32902 | /* 91861 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_dbg), |
| 32903 | /* 91866 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 32904 | /* 91869 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 32905 | /* 91873 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32906 | /* 91877 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15), |
| 32907 | /* 91881 */ // MIs[1] Operand 1 |
| 32908 | /* 91881 */ // No operand predicates |
| 32909 | /* 91881 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32910 | /* 91883 */ // (intrinsic_void 3511:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$opt) => (t2DBG (imm:{ *:[i32] }):$opt) |
| 32911 | /* 91883 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2DBG), |
| 32912 | /* 91886 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt |
| 32913 | /* 91889 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 32914 | /* 91892 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32915 | /* 91898 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 32916 | /* 91903 */ GIR_RootConstrainSelectedInstOperands, |
| 32917 | /* 91904 */ // GIR_Coverage, 580, |
| 32918 | /* 91904 */ GIR_EraseRootFromParent_Done, |
| 32919 | /* 91905 */ // Label 1677: @91905 |
| 32920 | /* 91905 */ GIM_Try, /*On fail goto*//*Label 1678*/ GIMT_Encode4(91945), // Rule ID 725 // |
| 32921 | /* 91910 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRegs), |
| 32922 | /* 91913 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_get_fpscr), |
| 32923 | /* 91918 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 32924 | /* 91921 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 32925 | /* 91925 */ // (intrinsic_w_chain:{ *:[i32] } 3514:{ *:[iPTR] }) => (VMRS:{ *:[i32] }) |
| 32926 | /* 91925 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMRS), |
| 32927 | /* 91928 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt] |
| 32928 | /* 91930 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 32929 | /* 91933 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32930 | /* 91939 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 32931 | /* 91943 */ GIR_RootConstrainSelectedInstOperands, |
| 32932 | /* 91944 */ // GIR_Coverage, 725, |
| 32933 | /* 91944 */ GIR_EraseRootFromParent_Done, |
| 32934 | /* 91945 */ // Label 1678: @91945 |
| 32935 | /* 91945 */ GIM_Try, /*On fail goto*//*Label 1679*/ GIMT_Encode4(91988), // Rule ID 726 // |
| 32936 | /* 91950 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRegs), |
| 32937 | /* 91953 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_set_fpscr), |
| 32938 | /* 91958 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 32939 | /* 91961 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 32940 | /* 91965 */ // (intrinsic_void 3877:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rt) => (VMSR:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rt) |
| 32941 | /* 91965 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMSR), |
| 32942 | /* 91968 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rt |
| 32943 | /* 91970 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 32944 | /* 91973 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32945 | /* 91979 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for ARM::FPSCR*/0, |
| 32946 | /* 91982 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 32947 | /* 91986 */ GIR_RootConstrainSelectedInstOperands, |
| 32948 | /* 91987 */ // GIR_Coverage, 726, |
| 32949 | /* 91987 */ GIR_EraseRootFromParent_Done, |
| 32950 | /* 91988 */ // Label 1679: @91988 |
| 32951 | /* 91988 */ GIM_Reject, |
| 32952 | /* 91989 */ // Label 1662: @91989 |
| 32953 | /* 91989 */ GIM_Try, /*On fail goto*//*Label 1680*/ GIMT_Encode4(92032), // Rule ID 604 // |
| 32954 | /* 91994 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLOB_HasV8_1MMainline_IsThumb2), |
| 32955 | /* 91997 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, |
| 32956 | /* 92000 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::start_loop_iterations), |
| 32957 | /* 92005 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 32958 | /* 92008 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 32959 | /* 92011 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRlrRegClassID), |
| 32960 | /* 92015 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 32961 | /* 92019 */ // (intrinsic_w_chain:{ *:[i32] } 348:{ *:[iPTR] }, rGPR:{ *:[i32] }:$tc) => (t2DoLoopStart:{ *:[i32] } rGPR:{ *:[i32] }:$tc) |
| 32962 | /* 92019 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2DoLoopStart), |
| 32963 | /* 92022 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[X] |
| 32964 | /* 92024 */ GIR_RootToRootCopy, /*OpIdx*/2, // tc |
| 32965 | /* 92026 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 32966 | /* 92030 */ GIR_RootConstrainSelectedInstOperands, |
| 32967 | /* 92031 */ // GIR_Coverage, 604, |
| 32968 | /* 92031 */ GIR_EraseRootFromParent_Done, |
| 32969 | /* 92032 */ // Label 1680: @92032 |
| 32970 | /* 92032 */ GIM_Try, /*On fail goto*//*Label 1681*/ GIMT_Encode4(94023), |
| 32971 | /* 92037 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/4, |
| 32972 | /* 92040 */ GIM_Try, /*On fail goto*//*Label 1682*/ GIMT_Encode4(92094), // Rule ID 5051 // |
| 32973 | /* 92045 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_base), |
| 32974 | /* 92050 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 32975 | /* 92053 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 32976 | /* 92056 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 32977 | /* 92059 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32978 | /* 92063 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32979 | /* 92067 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 32980 | /* 92071 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32981 | /* 92075 */ // MIs[1] Operand 1 |
| 32982 | /* 92075 */ // No operand predicates |
| 32983 | /* 92075 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32984 | /* 92077 */ // (intrinsic_w_chain:{ *:[v4i32] } 3647:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset) => (MVE_VLDRWU32_qi:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset) |
| 32985 | /* 92077 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_qi), |
| 32986 | /* 92080 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 32987 | /* 92082 */ GIR_RootToRootCopy, /*OpIdx*/2, // addr |
| 32988 | /* 92084 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset |
| 32989 | /* 92087 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 32990 | /* 92092 */ GIR_RootConstrainSelectedInstOperands, |
| 32991 | /* 92093 */ // GIR_Coverage, 5051, |
| 32992 | /* 92093 */ GIR_EraseRootFromParent_Done, |
| 32993 | /* 92094 */ // Label 1682: @92094 |
| 32994 | /* 92094 */ GIM_Try, /*On fail goto*//*Label 1683*/ GIMT_Encode4(92148), // Rule ID 5057 // |
| 32995 | /* 92099 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_base), |
| 32996 | /* 92104 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 32997 | /* 92107 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 32998 | /* 92110 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 32999 | /* 92113 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33000 | /* 92117 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33001 | /* 92121 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 33002 | /* 92125 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 33003 | /* 92129 */ // MIs[1] Operand 1 |
| 33004 | /* 92129 */ // No operand predicates |
| 33005 | /* 92129 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 33006 | /* 92131 */ // (intrinsic_w_chain:{ *:[v4f32] } 3647:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset) => (MVE_VLDRWU32_qi:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset) |
| 33007 | /* 92131 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_qi), |
| 33008 | /* 92134 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 33009 | /* 92136 */ GIR_RootToRootCopy, /*OpIdx*/2, // addr |
| 33010 | /* 92138 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset |
| 33011 | /* 92141 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 33012 | /* 92146 */ GIR_RootConstrainSelectedInstOperands, |
| 33013 | /* 92147 */ // GIR_Coverage, 5057, |
| 33014 | /* 92147 */ GIR_EraseRootFromParent_Done, |
| 33015 | /* 92148 */ // Label 1683: @92148 |
| 33016 | /* 92148 */ GIM_Try, /*On fail goto*//*Label 1684*/ GIMT_Encode4(92202), // Rule ID 5059 // |
| 33017 | /* 92153 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_base), |
| 33018 | /* 92158 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 33019 | /* 92161 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 33020 | /* 92164 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 33021 | /* 92167 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33022 | /* 92171 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33023 | /* 92175 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 33024 | /* 92179 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 33025 | /* 92183 */ // MIs[1] Operand 1 |
| 33026 | /* 92183 */ // No operand predicates |
| 33027 | /* 92183 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 33028 | /* 92185 */ // (intrinsic_w_chain:{ *:[v2i64] } 3647:{ *:[iPTR] }, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset) => (MVE_VLDRDU64_qi:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset) |
| 33029 | /* 92185 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRDU64_qi), |
| 33030 | /* 92188 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 33031 | /* 92190 */ GIR_RootToRootCopy, /*OpIdx*/2, // addr |
| 33032 | /* 92192 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset |
| 33033 | /* 92195 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 33034 | /* 92200 */ GIR_RootConstrainSelectedInstOperands, |
| 33035 | /* 92201 */ // GIR_Coverage, 5059, |
| 33036 | /* 92201 */ GIR_EraseRootFromParent_Done, |
| 33037 | /* 92202 */ // Label 1684: @92202 |
| 33038 | /* 92202 */ GIM_Try, /*On fail goto*//*Label 1685*/ GIMT_Encode4(92256), // Rule ID 5061 // |
| 33039 | /* 92207 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_base), |
| 33040 | /* 92212 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 33041 | /* 92215 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 33042 | /* 92218 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 33043 | /* 92221 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33044 | /* 92225 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33045 | /* 92229 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 33046 | /* 92233 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 33047 | /* 92237 */ // MIs[1] Operand 1 |
| 33048 | /* 92237 */ // No operand predicates |
| 33049 | /* 92237 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 33050 | /* 92239 */ // (intrinsic_w_chain:{ *:[v2f64] } 3647:{ *:[iPTR] }, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset) => (MVE_VLDRDU64_qi:{ *:[v2f64] } MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset) |
| 33051 | /* 92239 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRDU64_qi), |
| 33052 | /* 92242 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 33053 | /* 92244 */ GIR_RootToRootCopy, /*OpIdx*/2, // addr |
| 33054 | /* 92246 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset |
| 33055 | /* 92249 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 33056 | /* 92254 */ GIR_RootConstrainSelectedInstOperands, |
| 33057 | /* 92255 */ // GIR_Coverage, 5061, |
| 33058 | /* 92255 */ GIR_EraseRootFromParent_Done, |
| 33059 | /* 92256 */ // Label 1685: @92256 |
| 33060 | /* 92256 */ GIM_Try, /*On fail goto*//*Label 1686*/ GIMT_Encode4(92298), // Rule ID 1741 // |
| 33061 | /* 92261 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_space), |
| 33062 | /* 92266 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 33063 | /* 92269 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 33064 | /* 92272 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 33065 | /* 92276 */ // MIs[0] size |
| 33066 | /* 92276 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2, |
| 33067 | /* 92279 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 33068 | /* 92283 */ // (intrinsic_w_chain:{ *:[i32] } 3908:{ *:[iPTR] }, (timm:{ *:[i32] }):$size, GPR:{ *:[i32] }:$Rn) => (SPACE:{ *:[i32] } (timm:{ *:[i32] }):$size, GPR:{ *:[i32] }:$Rn) |
| 33069 | /* 92283 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SPACE), |
| 33070 | /* 92286 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 33071 | /* 92288 */ GIR_RootToRootCopy, /*OpIdx*/2, // size |
| 33072 | /* 92290 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rn |
| 33073 | /* 92292 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33074 | /* 92296 */ GIR_RootConstrainSelectedInstOperands, |
| 33075 | /* 92297 */ // GIR_Coverage, 1741, |
| 33076 | /* 92297 */ GIR_EraseRootFromParent_Done, |
| 33077 | /* 92298 */ // Label 1686: @92298 |
| 33078 | /* 92298 */ GIM_Try, /*On fail goto*//*Label 1687*/ GIMT_Encode4(92352), // Rule ID 5053 // |
| 33079 | /* 92303 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_base), |
| 33080 | /* 92308 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 33081 | /* 92311 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 33082 | /* 92314 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 33083 | /* 92317 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33084 | /* 92321 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 33085 | /* 92325 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 33086 | /* 92329 */ // MIs[1] Operand 1 |
| 33087 | /* 92329 */ // No operand predicates |
| 33088 | /* 92329 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33089 | /* 92333 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 33090 | /* 92335 */ // (intrinsic_void 3720:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset, MQPR:{ *:[v4i32] }:$data) => (MVE_VSTRW32_qi MQPR:{ *:[v4i32] }:$data, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset) |
| 33091 | /* 92335 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRW32_qi), |
| 33092 | /* 92338 */ GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 33093 | /* 92340 */ GIR_RootToRootCopy, /*OpIdx*/1, // addr |
| 33094 | /* 92342 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset |
| 33095 | /* 92345 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 33096 | /* 92350 */ GIR_RootConstrainSelectedInstOperands, |
| 33097 | /* 92351 */ // GIR_Coverage, 5053, |
| 33098 | /* 92351 */ GIR_EraseRootFromParent_Done, |
| 33099 | /* 92352 */ // Label 1687: @92352 |
| 33100 | /* 92352 */ GIM_Try, /*On fail goto*//*Label 1688*/ GIMT_Encode4(92406), // Rule ID 5063 // |
| 33101 | /* 92357 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_base), |
| 33102 | /* 92362 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 33103 | /* 92365 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 33104 | /* 92368 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 33105 | /* 92371 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33106 | /* 92375 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 33107 | /* 92379 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 33108 | /* 92383 */ // MIs[1] Operand 1 |
| 33109 | /* 92383 */ // No operand predicates |
| 33110 | /* 92383 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33111 | /* 92387 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 33112 | /* 92389 */ // (intrinsic_void 3720:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset, MQPR:{ *:[v4f32] }:$data) => (MVE_VSTRW32_qi MQPR:{ *:[v4f32] }:$data, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset) |
| 33113 | /* 92389 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRW32_qi), |
| 33114 | /* 92392 */ GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 33115 | /* 92394 */ GIR_RootToRootCopy, /*OpIdx*/1, // addr |
| 33116 | /* 92396 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset |
| 33117 | /* 92399 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 33118 | /* 92404 */ GIR_RootConstrainSelectedInstOperands, |
| 33119 | /* 92405 */ // GIR_Coverage, 5063, |
| 33120 | /* 92405 */ GIR_EraseRootFromParent_Done, |
| 33121 | /* 92406 */ // Label 1688: @92406 |
| 33122 | /* 92406 */ GIM_Try, /*On fail goto*//*Label 1689*/ GIMT_Encode4(92460), // Rule ID 5067 // |
| 33123 | /* 92411 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_base), |
| 33124 | /* 92416 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 33125 | /* 92419 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 33126 | /* 92422 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 33127 | /* 92425 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33128 | /* 92429 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 33129 | /* 92433 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 33130 | /* 92437 */ // MIs[1] Operand 1 |
| 33131 | /* 92437 */ // No operand predicates |
| 33132 | /* 92437 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33133 | /* 92441 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 33134 | /* 92443 */ // (intrinsic_void 3720:{ *:[iPTR] }, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset, MQPR:{ *:[v2i64] }:$data) => (MVE_VSTRD64_qi MQPR:{ *:[v2i64] }:$data, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset) |
| 33135 | /* 92443 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRD64_qi), |
| 33136 | /* 92446 */ GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 33137 | /* 92448 */ GIR_RootToRootCopy, /*OpIdx*/1, // addr |
| 33138 | /* 92450 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset |
| 33139 | /* 92453 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 33140 | /* 92458 */ GIR_RootConstrainSelectedInstOperands, |
| 33141 | /* 92459 */ // GIR_Coverage, 5067, |
| 33142 | /* 92459 */ GIR_EraseRootFromParent_Done, |
| 33143 | /* 92460 */ // Label 1689: @92460 |
| 33144 | /* 92460 */ GIM_Try, /*On fail goto*//*Label 1690*/ GIMT_Encode4(92514), // Rule ID 5071 // |
| 33145 | /* 92465 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_base), |
| 33146 | /* 92470 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 33147 | /* 92473 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 33148 | /* 92476 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 33149 | /* 92479 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33150 | /* 92483 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 33151 | /* 92487 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 33152 | /* 92491 */ // MIs[1] Operand 1 |
| 33153 | /* 92491 */ // No operand predicates |
| 33154 | /* 92491 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33155 | /* 92495 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 33156 | /* 92497 */ // (intrinsic_void 3720:{ *:[iPTR] }, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset, MQPR:{ *:[v2f64] }:$data) => (MVE_VSTRD64_qi MQPR:{ *:[v2f64] }:$data, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset) |
| 33157 | /* 92497 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRD64_qi), |
| 33158 | /* 92500 */ GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 33159 | /* 92502 */ GIR_RootToRootCopy, /*OpIdx*/1, // addr |
| 33160 | /* 92504 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset |
| 33161 | /* 92507 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 33162 | /* 92512 */ GIR_RootConstrainSelectedInstOperands, |
| 33163 | /* 92513 */ // GIR_Coverage, 5071, |
| 33164 | /* 92513 */ GIR_EraseRootFromParent_Done, |
| 33165 | /* 92514 */ // Label 1690: @92514 |
| 33166 | /* 92514 */ GIM_Try, /*On fail goto*//*Label 1691*/ GIMT_Encode4(92572), // Rule ID 3 // |
| 33167 | /* 92519 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 33168 | /* 92522 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sel), |
| 33169 | /* 92527 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 33170 | /* 92530 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 33171 | /* 92533 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 33172 | /* 92536 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 33173 | /* 92540 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 33174 | /* 92544 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 33175 | /* 92548 */ // (intrinsic_w_chain:{ *:[i32] } 3876:{ *:[iPTR] }, GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (SEL:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) |
| 33176 | /* 92548 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SEL), |
| 33177 | /* 92551 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 33178 | /* 92553 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 33179 | /* 92555 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 33180 | /* 92557 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 33181 | /* 92560 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33182 | /* 92566 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33183 | /* 92570 */ GIR_RootConstrainSelectedInstOperands, |
| 33184 | /* 92571 */ // GIR_Coverage, 3, |
| 33185 | /* 92571 */ GIR_EraseRootFromParent_Done, |
| 33186 | /* 92572 */ // Label 1691: @92572 |
| 33187 | /* 92572 */ GIM_Try, /*On fail goto*//*Label 1692*/ GIMT_Encode4(92630), // Rule ID 121 // |
| 33188 | /* 92577 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 33189 | /* 92580 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sasx), |
| 33190 | /* 92585 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 33191 | /* 92588 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 33192 | /* 92591 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 33193 | /* 92594 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33194 | /* 92598 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33195 | /* 92602 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33196 | /* 92606 */ // (intrinsic_w_chain:{ *:[i32] } 3875:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SASX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 33197 | /* 92606 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SASX), |
| 33198 | /* 92609 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 33199 | /* 92611 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 33200 | /* 92613 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 33201 | /* 92615 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 33202 | /* 92618 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33203 | /* 92624 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33204 | /* 92628 */ GIR_RootConstrainSelectedInstOperands, |
| 33205 | /* 92629 */ // GIR_Coverage, 121, |
| 33206 | /* 92629 */ GIR_EraseRootFromParent_Done, |
| 33207 | /* 92630 */ // Label 1692: @92630 |
| 33208 | /* 92630 */ GIM_Try, /*On fail goto*//*Label 1693*/ GIMT_Encode4(92688), // Rule ID 122 // |
| 33209 | /* 92635 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 33210 | /* 92638 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sadd16), |
| 33211 | /* 92643 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 33212 | /* 92646 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 33213 | /* 92649 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 33214 | /* 92652 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33215 | /* 92656 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33216 | /* 92660 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33217 | /* 92664 */ // (intrinsic_w_chain:{ *:[i32] } 3873:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SADD16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 33218 | /* 92664 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SADD16), |
| 33219 | /* 92667 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 33220 | /* 92669 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 33221 | /* 92671 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 33222 | /* 92673 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 33223 | /* 92676 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33224 | /* 92682 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33225 | /* 92686 */ GIR_RootConstrainSelectedInstOperands, |
| 33226 | /* 92687 */ // GIR_Coverage, 122, |
| 33227 | /* 92687 */ GIR_EraseRootFromParent_Done, |
| 33228 | /* 92688 */ // Label 1693: @92688 |
| 33229 | /* 92688 */ GIM_Try, /*On fail goto*//*Label 1694*/ GIMT_Encode4(92746), // Rule ID 123 // |
| 33230 | /* 92693 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 33231 | /* 92696 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sadd8), |
| 33232 | /* 92701 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 33233 | /* 92704 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 33234 | /* 92707 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 33235 | /* 92710 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33236 | /* 92714 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33237 | /* 92718 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33238 | /* 92722 */ // (intrinsic_w_chain:{ *:[i32] } 3874:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SADD8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 33239 | /* 92722 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SADD8), |
| 33240 | /* 92725 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 33241 | /* 92727 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 33242 | /* 92729 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 33243 | /* 92731 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 33244 | /* 92734 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33245 | /* 92740 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33246 | /* 92744 */ GIR_RootConstrainSelectedInstOperands, |
| 33247 | /* 92745 */ // GIR_Coverage, 123, |
| 33248 | /* 92745 */ GIR_EraseRootFromParent_Done, |
| 33249 | /* 92746 */ // Label 1694: @92746 |
| 33250 | /* 92746 */ GIM_Try, /*On fail goto*//*Label 1695*/ GIMT_Encode4(92804), // Rule ID 124 // |
| 33251 | /* 92751 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 33252 | /* 92754 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_ssax), |
| 33253 | /* 92759 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 33254 | /* 92762 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 33255 | /* 92765 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 33256 | /* 92768 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33257 | /* 92772 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33258 | /* 92776 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33259 | /* 92780 */ // (intrinsic_w_chain:{ *:[i32] } 3911:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SSAX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 33260 | /* 92780 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SSAX), |
| 33261 | /* 92783 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 33262 | /* 92785 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 33263 | /* 92787 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 33264 | /* 92789 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 33265 | /* 92792 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33266 | /* 92798 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33267 | /* 92802 */ GIR_RootConstrainSelectedInstOperands, |
| 33268 | /* 92803 */ // GIR_Coverage, 124, |
| 33269 | /* 92803 */ GIR_EraseRootFromParent_Done, |
| 33270 | /* 92804 */ // Label 1695: @92804 |
| 33271 | /* 92804 */ GIM_Try, /*On fail goto*//*Label 1696*/ GIMT_Encode4(92862), // Rule ID 125 // |
| 33272 | /* 92809 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 33273 | /* 92812 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_ssub16), |
| 33274 | /* 92817 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 33275 | /* 92820 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 33276 | /* 92823 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 33277 | /* 92826 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33278 | /* 92830 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33279 | /* 92834 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33280 | /* 92838 */ // (intrinsic_w_chain:{ *:[i32] } 3912:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SSUB16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 33281 | /* 92838 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SSUB16), |
| 33282 | /* 92841 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 33283 | /* 92843 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 33284 | /* 92845 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 33285 | /* 92847 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 33286 | /* 92850 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33287 | /* 92856 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33288 | /* 92860 */ GIR_RootConstrainSelectedInstOperands, |
| 33289 | /* 92861 */ // GIR_Coverage, 125, |
| 33290 | /* 92861 */ GIR_EraseRootFromParent_Done, |
| 33291 | /* 92862 */ // Label 1696: @92862 |
| 33292 | /* 92862 */ GIM_Try, /*On fail goto*//*Label 1697*/ GIMT_Encode4(92920), // Rule ID 126 // |
| 33293 | /* 92867 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 33294 | /* 92870 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_ssub8), |
| 33295 | /* 92875 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 33296 | /* 92878 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 33297 | /* 92881 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 33298 | /* 92884 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33299 | /* 92888 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33300 | /* 92892 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33301 | /* 92896 */ // (intrinsic_w_chain:{ *:[i32] } 3913:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SSUB8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 33302 | /* 92896 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SSUB8), |
| 33303 | /* 92899 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 33304 | /* 92901 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 33305 | /* 92903 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 33306 | /* 92905 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 33307 | /* 92908 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33308 | /* 92914 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33309 | /* 92918 */ GIR_RootConstrainSelectedInstOperands, |
| 33310 | /* 92919 */ // GIR_Coverage, 126, |
| 33311 | /* 92919 */ GIR_EraseRootFromParent_Done, |
| 33312 | /* 92920 */ // Label 1697: @92920 |
| 33313 | /* 92920 */ GIM_Try, /*On fail goto*//*Label 1698*/ GIMT_Encode4(92978), // Rule ID 127 // |
| 33314 | /* 92925 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 33315 | /* 92928 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uasx), |
| 33316 | /* 92933 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 33317 | /* 92936 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 33318 | /* 92939 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 33319 | /* 92942 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33320 | /* 92946 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33321 | /* 92950 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33322 | /* 92954 */ // (intrinsic_w_chain:{ *:[i32] } 3926:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UASX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 33323 | /* 92954 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UASX), |
| 33324 | /* 92957 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 33325 | /* 92959 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 33326 | /* 92961 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 33327 | /* 92963 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 33328 | /* 92966 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33329 | /* 92972 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33330 | /* 92976 */ GIR_RootConstrainSelectedInstOperands, |
| 33331 | /* 92977 */ // GIR_Coverage, 127, |
| 33332 | /* 92977 */ GIR_EraseRootFromParent_Done, |
| 33333 | /* 92978 */ // Label 1698: @92978 |
| 33334 | /* 92978 */ GIM_Try, /*On fail goto*//*Label 1699*/ GIMT_Encode4(93036), // Rule ID 128 // |
| 33335 | /* 92983 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 33336 | /* 92986 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uadd16), |
| 33337 | /* 92991 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 33338 | /* 92994 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 33339 | /* 92997 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 33340 | /* 93000 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33341 | /* 93004 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33342 | /* 93008 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33343 | /* 93012 */ // (intrinsic_w_chain:{ *:[i32] } 3924:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UADD16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 33344 | /* 93012 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UADD16), |
| 33345 | /* 93015 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 33346 | /* 93017 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 33347 | /* 93019 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 33348 | /* 93021 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 33349 | /* 93024 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33350 | /* 93030 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33351 | /* 93034 */ GIR_RootConstrainSelectedInstOperands, |
| 33352 | /* 93035 */ // GIR_Coverage, 128, |
| 33353 | /* 93035 */ GIR_EraseRootFromParent_Done, |
| 33354 | /* 93036 */ // Label 1699: @93036 |
| 33355 | /* 93036 */ GIM_Try, /*On fail goto*//*Label 1700*/ GIMT_Encode4(93094), // Rule ID 129 // |
| 33356 | /* 93041 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 33357 | /* 93044 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uadd8), |
| 33358 | /* 93049 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 33359 | /* 93052 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 33360 | /* 93055 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 33361 | /* 93058 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33362 | /* 93062 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33363 | /* 93066 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33364 | /* 93070 */ // (intrinsic_w_chain:{ *:[i32] } 3925:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UADD8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 33365 | /* 93070 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UADD8), |
| 33366 | /* 93073 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 33367 | /* 93075 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 33368 | /* 93077 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 33369 | /* 93079 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 33370 | /* 93082 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33371 | /* 93088 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33372 | /* 93092 */ GIR_RootConstrainSelectedInstOperands, |
| 33373 | /* 93093 */ // GIR_Coverage, 129, |
| 33374 | /* 93093 */ GIR_EraseRootFromParent_Done, |
| 33375 | /* 93094 */ // Label 1700: @93094 |
| 33376 | /* 93094 */ GIM_Try, /*On fail goto*//*Label 1701*/ GIMT_Encode4(93152), // Rule ID 130 // |
| 33377 | /* 93099 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 33378 | /* 93102 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usax), |
| 33379 | /* 93107 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 33380 | /* 93110 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 33381 | /* 93113 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 33382 | /* 93116 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33383 | /* 93120 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33384 | /* 93124 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33385 | /* 93128 */ // (intrinsic_w_chain:{ *:[i32] } 3944:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (USAX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 33386 | /* 93128 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::USAX), |
| 33387 | /* 93131 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 33388 | /* 93133 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 33389 | /* 93135 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 33390 | /* 93137 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 33391 | /* 93140 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33392 | /* 93146 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33393 | /* 93150 */ GIR_RootConstrainSelectedInstOperands, |
| 33394 | /* 93151 */ // GIR_Coverage, 130, |
| 33395 | /* 93151 */ GIR_EraseRootFromParent_Done, |
| 33396 | /* 93152 */ // Label 1701: @93152 |
| 33397 | /* 93152 */ GIM_Try, /*On fail goto*//*Label 1702*/ GIMT_Encode4(93210), // Rule ID 131 // |
| 33398 | /* 93157 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 33399 | /* 93160 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usub16), |
| 33400 | /* 93165 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 33401 | /* 93168 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 33402 | /* 93171 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 33403 | /* 93174 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33404 | /* 93178 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33405 | /* 93182 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33406 | /* 93186 */ // (intrinsic_w_chain:{ *:[i32] } 3945:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (USUB16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 33407 | /* 93186 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::USUB16), |
| 33408 | /* 93189 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 33409 | /* 93191 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 33410 | /* 93193 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 33411 | /* 93195 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 33412 | /* 93198 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33413 | /* 93204 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33414 | /* 93208 */ GIR_RootConstrainSelectedInstOperands, |
| 33415 | /* 93209 */ // GIR_Coverage, 131, |
| 33416 | /* 93209 */ GIR_EraseRootFromParent_Done, |
| 33417 | /* 93210 */ // Label 1702: @93210 |
| 33418 | /* 93210 */ GIM_Try, /*On fail goto*//*Label 1703*/ GIMT_Encode4(93268), // Rule ID 132 // |
| 33419 | /* 93215 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 33420 | /* 93218 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usub8), |
| 33421 | /* 93223 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 33422 | /* 93226 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 33423 | /* 93229 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 33424 | /* 93232 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33425 | /* 93236 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33426 | /* 93240 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33427 | /* 93244 */ // (intrinsic_w_chain:{ *:[i32] } 3946:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (USUB8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 33428 | /* 93244 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::USUB8), |
| 33429 | /* 93247 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 33430 | /* 93249 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 33431 | /* 93251 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 33432 | /* 93253 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 33433 | /* 93256 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33434 | /* 93262 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33435 | /* 93266 */ GIR_RootConstrainSelectedInstOperands, |
| 33436 | /* 93267 */ // GIR_Coverage, 132, |
| 33437 | /* 93267 */ GIR_EraseRootFromParent_Done, |
| 33438 | /* 93268 */ // Label 1703: @93268 |
| 33439 | /* 93268 */ GIM_Try, /*On fail goto*//*Label 1704*/ GIMT_Encode4(93326), // Rule ID 431 // |
| 33440 | /* 93273 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 33441 | /* 93276 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sel), |
| 33442 | /* 93281 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 33443 | /* 93284 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 33444 | /* 93287 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 33445 | /* 93290 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 33446 | /* 93294 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 33447 | /* 93298 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 33448 | /* 93302 */ // (intrinsic_w_chain:{ *:[i32] } 3876:{ *:[iPTR] }, GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (t2SEL:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) |
| 33449 | /* 93302 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SEL), |
| 33450 | /* 93305 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 33451 | /* 93307 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 33452 | /* 93309 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 33453 | /* 93311 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 33454 | /* 93314 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33455 | /* 93320 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33456 | /* 93324 */ GIR_RootConstrainSelectedInstOperands, |
| 33457 | /* 93325 */ // GIR_Coverage, 431, |
| 33458 | /* 93325 */ GIR_EraseRootFromParent_Done, |
| 33459 | /* 93326 */ // Label 1704: @93326 |
| 33460 | /* 93326 */ GIM_Try, /*On fail goto*//*Label 1705*/ GIMT_Encode4(93384), // Rule ID 444 // |
| 33461 | /* 93331 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 33462 | /* 93334 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sasx), |
| 33463 | /* 93339 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 33464 | /* 93342 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 33465 | /* 93345 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 33466 | /* 93348 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33467 | /* 93352 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33468 | /* 93356 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33469 | /* 93360 */ // (intrinsic_w_chain:{ *:[i32] } 3875:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SASX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 33470 | /* 93360 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SASX), |
| 33471 | /* 93363 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 33472 | /* 93365 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 33473 | /* 93367 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 33474 | /* 93369 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 33475 | /* 93372 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33476 | /* 93378 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33477 | /* 93382 */ GIR_RootConstrainSelectedInstOperands, |
| 33478 | /* 93383 */ // GIR_Coverage, 444, |
| 33479 | /* 93383 */ GIR_EraseRootFromParent_Done, |
| 33480 | /* 93384 */ // Label 1705: @93384 |
| 33481 | /* 93384 */ GIM_Try, /*On fail goto*//*Label 1706*/ GIMT_Encode4(93442), // Rule ID 445 // |
| 33482 | /* 93389 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 33483 | /* 93392 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sadd16), |
| 33484 | /* 93397 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 33485 | /* 93400 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 33486 | /* 93403 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 33487 | /* 93406 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33488 | /* 93410 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33489 | /* 93414 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33490 | /* 93418 */ // (intrinsic_w_chain:{ *:[i32] } 3873:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SADD16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 33491 | /* 93418 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SADD16), |
| 33492 | /* 93421 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 33493 | /* 93423 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 33494 | /* 93425 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 33495 | /* 93427 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 33496 | /* 93430 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33497 | /* 93436 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33498 | /* 93440 */ GIR_RootConstrainSelectedInstOperands, |
| 33499 | /* 93441 */ // GIR_Coverage, 445, |
| 33500 | /* 93441 */ GIR_EraseRootFromParent_Done, |
| 33501 | /* 93442 */ // Label 1706: @93442 |
| 33502 | /* 93442 */ GIM_Try, /*On fail goto*//*Label 1707*/ GIMT_Encode4(93500), // Rule ID 446 // |
| 33503 | /* 93447 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 33504 | /* 93450 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sadd8), |
| 33505 | /* 93455 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 33506 | /* 93458 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 33507 | /* 93461 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 33508 | /* 93464 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33509 | /* 93468 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33510 | /* 93472 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33511 | /* 93476 */ // (intrinsic_w_chain:{ *:[i32] } 3874:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SADD8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 33512 | /* 93476 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SADD8), |
| 33513 | /* 93479 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 33514 | /* 93481 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 33515 | /* 93483 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 33516 | /* 93485 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 33517 | /* 93488 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33518 | /* 93494 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33519 | /* 93498 */ GIR_RootConstrainSelectedInstOperands, |
| 33520 | /* 93499 */ // GIR_Coverage, 446, |
| 33521 | /* 93499 */ GIR_EraseRootFromParent_Done, |
| 33522 | /* 93500 */ // Label 1707: @93500 |
| 33523 | /* 93500 */ GIM_Try, /*On fail goto*//*Label 1708*/ GIMT_Encode4(93558), // Rule ID 447 // |
| 33524 | /* 93505 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 33525 | /* 93508 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_ssax), |
| 33526 | /* 93513 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 33527 | /* 93516 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 33528 | /* 93519 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 33529 | /* 93522 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33530 | /* 93526 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33531 | /* 93530 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33532 | /* 93534 */ // (intrinsic_w_chain:{ *:[i32] } 3911:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SSAX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 33533 | /* 93534 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SSAX), |
| 33534 | /* 93537 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 33535 | /* 93539 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 33536 | /* 93541 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 33537 | /* 93543 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 33538 | /* 93546 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33539 | /* 93552 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33540 | /* 93556 */ GIR_RootConstrainSelectedInstOperands, |
| 33541 | /* 93557 */ // GIR_Coverage, 447, |
| 33542 | /* 93557 */ GIR_EraseRootFromParent_Done, |
| 33543 | /* 93558 */ // Label 1708: @93558 |
| 33544 | /* 93558 */ GIM_Try, /*On fail goto*//*Label 1709*/ GIMT_Encode4(93616), // Rule ID 448 // |
| 33545 | /* 93563 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 33546 | /* 93566 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_ssub16), |
| 33547 | /* 93571 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 33548 | /* 93574 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 33549 | /* 93577 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 33550 | /* 93580 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33551 | /* 93584 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33552 | /* 93588 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33553 | /* 93592 */ // (intrinsic_w_chain:{ *:[i32] } 3912:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SSUB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 33554 | /* 93592 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SSUB16), |
| 33555 | /* 93595 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 33556 | /* 93597 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 33557 | /* 93599 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 33558 | /* 93601 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 33559 | /* 93604 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33560 | /* 93610 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33561 | /* 93614 */ GIR_RootConstrainSelectedInstOperands, |
| 33562 | /* 93615 */ // GIR_Coverage, 448, |
| 33563 | /* 93615 */ GIR_EraseRootFromParent_Done, |
| 33564 | /* 93616 */ // Label 1709: @93616 |
| 33565 | /* 93616 */ GIM_Try, /*On fail goto*//*Label 1710*/ GIMT_Encode4(93674), // Rule ID 449 // |
| 33566 | /* 93621 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 33567 | /* 93624 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_ssub8), |
| 33568 | /* 93629 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 33569 | /* 93632 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 33570 | /* 93635 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 33571 | /* 93638 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33572 | /* 93642 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33573 | /* 93646 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33574 | /* 93650 */ // (intrinsic_w_chain:{ *:[i32] } 3913:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SSUB8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 33575 | /* 93650 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SSUB8), |
| 33576 | /* 93653 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 33577 | /* 93655 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 33578 | /* 93657 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 33579 | /* 93659 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 33580 | /* 93662 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33581 | /* 93668 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33582 | /* 93672 */ GIR_RootConstrainSelectedInstOperands, |
| 33583 | /* 93673 */ // GIR_Coverage, 449, |
| 33584 | /* 93673 */ GIR_EraseRootFromParent_Done, |
| 33585 | /* 93674 */ // Label 1710: @93674 |
| 33586 | /* 93674 */ GIM_Try, /*On fail goto*//*Label 1711*/ GIMT_Encode4(93732), // Rule ID 450 // |
| 33587 | /* 93679 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 33588 | /* 93682 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uasx), |
| 33589 | /* 93687 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 33590 | /* 93690 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 33591 | /* 93693 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 33592 | /* 93696 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33593 | /* 93700 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33594 | /* 93704 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33595 | /* 93708 */ // (intrinsic_w_chain:{ *:[i32] } 3926:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UASX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 33596 | /* 93708 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UASX), |
| 33597 | /* 93711 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 33598 | /* 93713 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 33599 | /* 93715 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 33600 | /* 93717 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 33601 | /* 93720 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33602 | /* 93726 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33603 | /* 93730 */ GIR_RootConstrainSelectedInstOperands, |
| 33604 | /* 93731 */ // GIR_Coverage, 450, |
| 33605 | /* 93731 */ GIR_EraseRootFromParent_Done, |
| 33606 | /* 93732 */ // Label 1711: @93732 |
| 33607 | /* 93732 */ GIM_Try, /*On fail goto*//*Label 1712*/ GIMT_Encode4(93790), // Rule ID 451 // |
| 33608 | /* 93737 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 33609 | /* 93740 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uadd16), |
| 33610 | /* 93745 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 33611 | /* 93748 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 33612 | /* 93751 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 33613 | /* 93754 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33614 | /* 93758 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33615 | /* 93762 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33616 | /* 93766 */ // (intrinsic_w_chain:{ *:[i32] } 3924:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UADD16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 33617 | /* 93766 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UADD16), |
| 33618 | /* 93769 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 33619 | /* 93771 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 33620 | /* 93773 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 33621 | /* 93775 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 33622 | /* 93778 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33623 | /* 93784 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33624 | /* 93788 */ GIR_RootConstrainSelectedInstOperands, |
| 33625 | /* 93789 */ // GIR_Coverage, 451, |
| 33626 | /* 93789 */ GIR_EraseRootFromParent_Done, |
| 33627 | /* 93790 */ // Label 1712: @93790 |
| 33628 | /* 93790 */ GIM_Try, /*On fail goto*//*Label 1713*/ GIMT_Encode4(93848), // Rule ID 452 // |
| 33629 | /* 93795 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 33630 | /* 93798 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uadd8), |
| 33631 | /* 93803 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 33632 | /* 93806 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 33633 | /* 93809 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 33634 | /* 93812 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33635 | /* 93816 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33636 | /* 93820 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33637 | /* 93824 */ // (intrinsic_w_chain:{ *:[i32] } 3925:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UADD8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 33638 | /* 93824 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UADD8), |
| 33639 | /* 93827 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 33640 | /* 93829 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 33641 | /* 93831 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 33642 | /* 93833 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 33643 | /* 93836 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33644 | /* 93842 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33645 | /* 93846 */ GIR_RootConstrainSelectedInstOperands, |
| 33646 | /* 93847 */ // GIR_Coverage, 452, |
| 33647 | /* 93847 */ GIR_EraseRootFromParent_Done, |
| 33648 | /* 93848 */ // Label 1713: @93848 |
| 33649 | /* 93848 */ GIM_Try, /*On fail goto*//*Label 1714*/ GIMT_Encode4(93906), // Rule ID 453 // |
| 33650 | /* 93853 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 33651 | /* 93856 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usax), |
| 33652 | /* 93861 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 33653 | /* 93864 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 33654 | /* 93867 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 33655 | /* 93870 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33656 | /* 93874 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33657 | /* 93878 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33658 | /* 93882 */ // (intrinsic_w_chain:{ *:[i32] } 3944:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2USAX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 33659 | /* 93882 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2USAX), |
| 33660 | /* 93885 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 33661 | /* 93887 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 33662 | /* 93889 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 33663 | /* 93891 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 33664 | /* 93894 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33665 | /* 93900 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33666 | /* 93904 */ GIR_RootConstrainSelectedInstOperands, |
| 33667 | /* 93905 */ // GIR_Coverage, 453, |
| 33668 | /* 93905 */ GIR_EraseRootFromParent_Done, |
| 33669 | /* 93906 */ // Label 1714: @93906 |
| 33670 | /* 93906 */ GIM_Try, /*On fail goto*//*Label 1715*/ GIMT_Encode4(93964), // Rule ID 454 // |
| 33671 | /* 93911 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 33672 | /* 93914 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usub16), |
| 33673 | /* 93919 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 33674 | /* 93922 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 33675 | /* 93925 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 33676 | /* 93928 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33677 | /* 93932 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33678 | /* 93936 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33679 | /* 93940 */ // (intrinsic_w_chain:{ *:[i32] } 3945:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2USUB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 33680 | /* 93940 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2USUB16), |
| 33681 | /* 93943 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 33682 | /* 93945 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 33683 | /* 93947 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 33684 | /* 93949 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 33685 | /* 93952 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33686 | /* 93958 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33687 | /* 93962 */ GIR_RootConstrainSelectedInstOperands, |
| 33688 | /* 93963 */ // GIR_Coverage, 454, |
| 33689 | /* 93963 */ GIR_EraseRootFromParent_Done, |
| 33690 | /* 93964 */ // Label 1715: @93964 |
| 33691 | /* 93964 */ GIM_Try, /*On fail goto*//*Label 1716*/ GIMT_Encode4(94022), // Rule ID 455 // |
| 33692 | /* 93969 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 33693 | /* 93972 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usub8), |
| 33694 | /* 93977 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 33695 | /* 93980 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 33696 | /* 93983 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 33697 | /* 93986 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33698 | /* 93990 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33699 | /* 93994 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33700 | /* 93998 */ // (intrinsic_w_chain:{ *:[i32] } 3946:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2USUB8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 33701 | /* 93998 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2USUB8), |
| 33702 | /* 94001 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 33703 | /* 94003 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 33704 | /* 94005 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 33705 | /* 94007 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 33706 | /* 94010 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33707 | /* 94016 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33708 | /* 94020 */ GIR_RootConstrainSelectedInstOperands, |
| 33709 | /* 94021 */ // GIR_Coverage, 455, |
| 33710 | /* 94021 */ GIR_EraseRootFromParent_Done, |
| 33711 | /* 94022 */ // Label 1716: @94022 |
| 33712 | /* 94022 */ GIM_Reject, |
| 33713 | /* 94023 */ // Label 1681: @94023 |
| 33714 | /* 94023 */ GIM_Try, /*On fail goto*//*Label 1717*/ GIMT_Encode4(94269), |
| 33715 | /* 94028 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/5, |
| 33716 | /* 94031 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_base_wb), |
| 33717 | /* 94036 */ GIM_Try, /*On fail goto*//*Label 1718*/ GIMT_Encode4(94094), // Rule ID 5055 // |
| 33718 | /* 94041 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 33719 | /* 94044 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 33720 | /* 94047 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 33721 | /* 94050 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 33722 | /* 94053 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33723 | /* 94057 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33724 | /* 94061 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 33725 | /* 94065 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 33726 | /* 94069 */ // MIs[1] Operand 1 |
| 33727 | /* 94069 */ // No operand predicates |
| 33728 | /* 94069 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33729 | /* 94073 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 33730 | /* 94075 */ // (intrinsic_w_chain:{ *:[v4i32] } 3722:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset, MQPR:{ *:[v4i32] }:$data) => (MVE_VSTRW32_qi_pre:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$data, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset) |
| 33731 | /* 94075 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRW32_qi_pre), |
| 33732 | /* 94078 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wb] |
| 33733 | /* 94080 */ GIR_RootToRootCopy, /*OpIdx*/4, // data |
| 33734 | /* 94082 */ GIR_RootToRootCopy, /*OpIdx*/2, // addr |
| 33735 | /* 94084 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset |
| 33736 | /* 94087 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 33737 | /* 94092 */ GIR_RootConstrainSelectedInstOperands, |
| 33738 | /* 94093 */ // GIR_Coverage, 5055, |
| 33739 | /* 94093 */ GIR_EraseRootFromParent_Done, |
| 33740 | /* 94094 */ // Label 1718: @94094 |
| 33741 | /* 94094 */ GIM_Try, /*On fail goto*//*Label 1719*/ GIMT_Encode4(94152), // Rule ID 5065 // |
| 33742 | /* 94099 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 33743 | /* 94102 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 33744 | /* 94105 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 33745 | /* 94108 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 33746 | /* 94111 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33747 | /* 94115 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33748 | /* 94119 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 33749 | /* 94123 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 33750 | /* 94127 */ // MIs[1] Operand 1 |
| 33751 | /* 94127 */ // No operand predicates |
| 33752 | /* 94127 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33753 | /* 94131 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 33754 | /* 94133 */ // (intrinsic_w_chain:{ *:[v4i32] } 3722:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset, MQPR:{ *:[v4f32] }:$data) => (MVE_VSTRW32_qi_pre:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$data, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset) |
| 33755 | /* 94133 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRW32_qi_pre), |
| 33756 | /* 94136 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wb] |
| 33757 | /* 94138 */ GIR_RootToRootCopy, /*OpIdx*/4, // data |
| 33758 | /* 94140 */ GIR_RootToRootCopy, /*OpIdx*/2, // addr |
| 33759 | /* 94142 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset |
| 33760 | /* 94145 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 33761 | /* 94150 */ GIR_RootConstrainSelectedInstOperands, |
| 33762 | /* 94151 */ // GIR_Coverage, 5065, |
| 33763 | /* 94151 */ GIR_EraseRootFromParent_Done, |
| 33764 | /* 94152 */ // Label 1719: @94152 |
| 33765 | /* 94152 */ GIM_Try, /*On fail goto*//*Label 1720*/ GIMT_Encode4(94210), // Rule ID 5069 // |
| 33766 | /* 94157 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 33767 | /* 94160 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 33768 | /* 94163 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 33769 | /* 94166 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s64, |
| 33770 | /* 94169 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33771 | /* 94173 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33772 | /* 94177 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 33773 | /* 94181 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 33774 | /* 94185 */ // MIs[1] Operand 1 |
| 33775 | /* 94185 */ // No operand predicates |
| 33776 | /* 94185 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33777 | /* 94189 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 33778 | /* 94191 */ // (intrinsic_w_chain:{ *:[v2i64] } 3722:{ *:[iPTR] }, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset, MQPR:{ *:[v2i64] }:$data) => (MVE_VSTRD64_qi_pre:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$data, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset) |
| 33779 | /* 94191 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRD64_qi_pre), |
| 33780 | /* 94194 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wb] |
| 33781 | /* 94196 */ GIR_RootToRootCopy, /*OpIdx*/4, // data |
| 33782 | /* 94198 */ GIR_RootToRootCopy, /*OpIdx*/2, // addr |
| 33783 | /* 94200 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset |
| 33784 | /* 94203 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 33785 | /* 94208 */ GIR_RootConstrainSelectedInstOperands, |
| 33786 | /* 94209 */ // GIR_Coverage, 5069, |
| 33787 | /* 94209 */ GIR_EraseRootFromParent_Done, |
| 33788 | /* 94210 */ // Label 1720: @94210 |
| 33789 | /* 94210 */ GIM_Try, /*On fail goto*//*Label 1721*/ GIMT_Encode4(94268), // Rule ID 5073 // |
| 33790 | /* 94215 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 33791 | /* 94218 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 33792 | /* 94221 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 33793 | /* 94224 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s64, |
| 33794 | /* 94227 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33795 | /* 94231 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33796 | /* 94235 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 33797 | /* 94239 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 33798 | /* 94243 */ // MIs[1] Operand 1 |
| 33799 | /* 94243 */ // No operand predicates |
| 33800 | /* 94243 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33801 | /* 94247 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 33802 | /* 94249 */ // (intrinsic_w_chain:{ *:[v2i64] } 3722:{ *:[iPTR] }, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset, MQPR:{ *:[v2f64] }:$data) => (MVE_VSTRD64_qi_pre:{ *:[v2i64] } MQPR:{ *:[v2f64] }:$data, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset) |
| 33803 | /* 94249 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRD64_qi_pre), |
| 33804 | /* 94252 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wb] |
| 33805 | /* 94254 */ GIR_RootToRootCopy, /*OpIdx*/4, // data |
| 33806 | /* 94256 */ GIR_RootToRootCopy, /*OpIdx*/2, // addr |
| 33807 | /* 94258 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset |
| 33808 | /* 94261 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 33809 | /* 94266 */ GIR_RootConstrainSelectedInstOperands, |
| 33810 | /* 94267 */ // GIR_Coverage, 5073, |
| 33811 | /* 94267 */ GIR_EraseRootFromParent_Done, |
| 33812 | /* 94268 */ // Label 1721: @94268 |
| 33813 | /* 94268 */ GIM_Reject, |
| 33814 | /* 94269 */ // Label 1717: @94269 |
| 33815 | /* 94269 */ GIM_Try, /*On fail goto*//*Label 1722*/ GIMT_Encode4(95440), |
| 33816 | /* 94274 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/6, |
| 33817 | /* 94277 */ GIM_Try, /*On fail goto*//*Label 1723*/ GIMT_Encode4(94338), // Rule ID 4943 // |
| 33818 | /* 94282 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_offset), |
| 33819 | /* 94287 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 33820 | /* 94290 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 33821 | /* 94293 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 33822 | /* 94296 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 33823 | /* 94299 */ // MIs[0] base |
| 33824 | /* 94299 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 33825 | /* 94303 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 33826 | /* 94307 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33827 | /* 94311 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33828 | /* 94315 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16, |
| 33829 | /* 94319 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 33830 | /* 94323 */ // (intrinsic_void 3724:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, MQPR:{ *:[v8i16] }:$data, 16:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSTRH16_rq_u MQPR:{ *:[v8i16] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets) |
| 33831 | /* 94323 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRH16_rq_u), |
| 33832 | /* 94326 */ GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 33833 | /* 94328 */ GIR_RootToRootCopy, /*OpIdx*/1, // base |
| 33834 | /* 94330 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets |
| 33835 | /* 94332 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33836 | /* 94336 */ GIR_RootConstrainSelectedInstOperands, |
| 33837 | /* 94337 */ // GIR_Coverage, 4943, |
| 33838 | /* 94337 */ GIR_EraseRootFromParent_Done, |
| 33839 | /* 94338 */ // Label 1723: @94338 |
| 33840 | /* 94338 */ GIM_Try, /*On fail goto*//*Label 1724*/ GIMT_Encode4(94399), // Rule ID 4944 // |
| 33841 | /* 94343 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_offset), |
| 33842 | /* 94348 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 33843 | /* 94351 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 33844 | /* 94354 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 33845 | /* 94357 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 33846 | /* 94360 */ // MIs[0] base |
| 33847 | /* 94360 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 33848 | /* 94364 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 33849 | /* 94368 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33850 | /* 94372 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33851 | /* 94376 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16, |
| 33852 | /* 94380 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 33853 | /* 94384 */ // (intrinsic_void 3724:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, MQPR:{ *:[v8i16] }:$data, 16:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSTRH16_rq MQPR:{ *:[v8i16] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets) |
| 33854 | /* 94384 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRH16_rq), |
| 33855 | /* 94387 */ GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 33856 | /* 94389 */ GIR_RootToRootCopy, /*OpIdx*/1, // base |
| 33857 | /* 94391 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets |
| 33858 | /* 94393 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33859 | /* 94397 */ GIR_RootConstrainSelectedInstOperands, |
| 33860 | /* 94398 */ // GIR_Coverage, 4944, |
| 33861 | /* 94398 */ GIR_EraseRootFromParent_Done, |
| 33862 | /* 94399 */ // Label 1724: @94399 |
| 33863 | /* 94399 */ GIM_Try, /*On fail goto*//*Label 1725*/ GIMT_Encode4(94460), // Rule ID 4947 // |
| 33864 | /* 94404 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_offset), |
| 33865 | /* 94409 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 33866 | /* 94412 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 33867 | /* 94415 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 33868 | /* 94418 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 33869 | /* 94421 */ // MIs[0] base |
| 33870 | /* 94421 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 33871 | /* 94425 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 33872 | /* 94429 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33873 | /* 94433 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33874 | /* 94437 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 8, |
| 33875 | /* 94441 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 33876 | /* 94445 */ // (intrinsic_void 3724:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v16i8] }:$offsets, MQPR:{ *:[v16i8] }:$data, 8:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSTRB8_rq MQPR:{ *:[v16i8] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v16i8] }:$offsets) |
| 33877 | /* 94445 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRB8_rq), |
| 33878 | /* 94448 */ GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 33879 | /* 94450 */ GIR_RootToRootCopy, /*OpIdx*/1, // base |
| 33880 | /* 94452 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets |
| 33881 | /* 94454 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33882 | /* 94458 */ GIR_RootConstrainSelectedInstOperands, |
| 33883 | /* 94459 */ // GIR_Coverage, 4947, |
| 33884 | /* 94459 */ GIR_EraseRootFromParent_Done, |
| 33885 | /* 94460 */ // Label 1725: @94460 |
| 33886 | /* 94460 */ GIM_Try, /*On fail goto*//*Label 1726*/ GIMT_Encode4(94521), // Rule ID 5027 // |
| 33887 | /* 94465 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_offset), |
| 33888 | /* 94470 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 33889 | /* 94473 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 33890 | /* 94476 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 33891 | /* 94479 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 33892 | /* 94482 */ // MIs[0] base |
| 33893 | /* 94482 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 33894 | /* 94486 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 33895 | /* 94490 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33896 | /* 94494 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33897 | /* 94498 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 8, |
| 33898 | /* 94502 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 33899 | /* 94506 */ // (intrinsic_void 3724:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, MQPR:{ *:[v8i16] }:$data, 8:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSTRB16_rq MQPR:{ *:[v8i16] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets) |
| 33900 | /* 94506 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRB16_rq), |
| 33901 | /* 94509 */ GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 33902 | /* 94511 */ GIR_RootToRootCopy, /*OpIdx*/1, // base |
| 33903 | /* 94513 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets |
| 33904 | /* 94515 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33905 | /* 94519 */ GIR_RootConstrainSelectedInstOperands, |
| 33906 | /* 94520 */ // GIR_Coverage, 5027, |
| 33907 | /* 94520 */ GIR_EraseRootFromParent_Done, |
| 33908 | /* 94521 */ // Label 1726: @94521 |
| 33909 | /* 94521 */ GIM_Try, /*On fail goto*//*Label 1727*/ GIMT_Encode4(94582), // Rule ID 5029 // |
| 33910 | /* 94526 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_offset), |
| 33911 | /* 94531 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 33912 | /* 94534 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 33913 | /* 94537 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 33914 | /* 94540 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 33915 | /* 94543 */ // MIs[0] base |
| 33916 | /* 94543 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 33917 | /* 94547 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 33918 | /* 94551 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33919 | /* 94555 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33920 | /* 94559 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 8, |
| 33921 | /* 94563 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 33922 | /* 94567 */ // (intrinsic_void 3724:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, MQPR:{ *:[v4i32] }:$data, 8:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSTRB32_rq MQPR:{ *:[v4i32] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 33923 | /* 94567 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRB32_rq), |
| 33924 | /* 94570 */ GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 33925 | /* 94572 */ GIR_RootToRootCopy, /*OpIdx*/1, // base |
| 33926 | /* 94574 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets |
| 33927 | /* 94576 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33928 | /* 94580 */ GIR_RootConstrainSelectedInstOperands, |
| 33929 | /* 94581 */ // GIR_Coverage, 5029, |
| 33930 | /* 94581 */ GIR_EraseRootFromParent_Done, |
| 33931 | /* 94582 */ // Label 1727: @94582 |
| 33932 | /* 94582 */ GIM_Try, /*On fail goto*//*Label 1728*/ GIMT_Encode4(94643), // Rule ID 5031 // |
| 33933 | /* 94587 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_offset), |
| 33934 | /* 94592 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 33935 | /* 94595 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 33936 | /* 94598 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 33937 | /* 94601 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 33938 | /* 94604 */ // MIs[0] base |
| 33939 | /* 94604 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 33940 | /* 94608 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 33941 | /* 94612 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33942 | /* 94616 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33943 | /* 94620 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16, |
| 33944 | /* 94624 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 33945 | /* 94628 */ // (intrinsic_void 3724:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, MQPR:{ *:[v8f16] }:$data, 16:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSTRH16_rq_u MQPR:{ *:[v8f16] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets) |
| 33946 | /* 94628 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRH16_rq_u), |
| 33947 | /* 94631 */ GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 33948 | /* 94633 */ GIR_RootToRootCopy, /*OpIdx*/1, // base |
| 33949 | /* 94635 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets |
| 33950 | /* 94637 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33951 | /* 94641 */ GIR_RootConstrainSelectedInstOperands, |
| 33952 | /* 94642 */ // GIR_Coverage, 5031, |
| 33953 | /* 94642 */ GIR_EraseRootFromParent_Done, |
| 33954 | /* 94643 */ // Label 1728: @94643 |
| 33955 | /* 94643 */ GIM_Try, /*On fail goto*//*Label 1729*/ GIMT_Encode4(94704), // Rule ID 5032 // |
| 33956 | /* 94648 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_offset), |
| 33957 | /* 94653 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 33958 | /* 94656 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 33959 | /* 94659 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 33960 | /* 94662 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 33961 | /* 94665 */ // MIs[0] base |
| 33962 | /* 94665 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 33963 | /* 94669 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 33964 | /* 94673 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33965 | /* 94677 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33966 | /* 94681 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16, |
| 33967 | /* 94685 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 33968 | /* 94689 */ // (intrinsic_void 3724:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, MQPR:{ *:[v8f16] }:$data, 16:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSTRH16_rq MQPR:{ *:[v8f16] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets) |
| 33969 | /* 94689 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRH16_rq), |
| 33970 | /* 94692 */ GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 33971 | /* 94694 */ GIR_RootToRootCopy, /*OpIdx*/1, // base |
| 33972 | /* 94696 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets |
| 33973 | /* 94698 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33974 | /* 94702 */ GIR_RootConstrainSelectedInstOperands, |
| 33975 | /* 94703 */ // GIR_Coverage, 5032, |
| 33976 | /* 94703 */ GIR_EraseRootFromParent_Done, |
| 33977 | /* 94704 */ // Label 1729: @94704 |
| 33978 | /* 94704 */ GIM_Try, /*On fail goto*//*Label 1730*/ GIMT_Encode4(94765), // Rule ID 5035 // |
| 33979 | /* 94709 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_offset), |
| 33980 | /* 94714 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 33981 | /* 94717 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 33982 | /* 94720 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 33983 | /* 94723 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 33984 | /* 94726 */ // MIs[0] base |
| 33985 | /* 94726 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 33986 | /* 94730 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 33987 | /* 94734 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33988 | /* 94738 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33989 | /* 94742 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16, |
| 33990 | /* 94746 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 33991 | /* 94750 */ // (intrinsic_void 3724:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, MQPR:{ *:[v4i32] }:$data, 16:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSTRH32_rq_u MQPR:{ *:[v4i32] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 33992 | /* 94750 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRH32_rq_u), |
| 33993 | /* 94753 */ GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 33994 | /* 94755 */ GIR_RootToRootCopy, /*OpIdx*/1, // base |
| 33995 | /* 94757 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets |
| 33996 | /* 94759 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33997 | /* 94763 */ GIR_RootConstrainSelectedInstOperands, |
| 33998 | /* 94764 */ // GIR_Coverage, 5035, |
| 33999 | /* 94764 */ GIR_EraseRootFromParent_Done, |
| 34000 | /* 94765 */ // Label 1730: @94765 |
| 34001 | /* 94765 */ GIM_Try, /*On fail goto*//*Label 1731*/ GIMT_Encode4(94826), // Rule ID 5036 // |
| 34002 | /* 94770 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_offset), |
| 34003 | /* 94775 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 34004 | /* 94778 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 34005 | /* 94781 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34006 | /* 94784 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 34007 | /* 94787 */ // MIs[0] base |
| 34008 | /* 94787 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 34009 | /* 94791 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 34010 | /* 94795 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34011 | /* 94799 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34012 | /* 94803 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16, |
| 34013 | /* 94807 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 34014 | /* 94811 */ // (intrinsic_void 3724:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, MQPR:{ *:[v4i32] }:$data, 16:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSTRH32_rq MQPR:{ *:[v4i32] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 34015 | /* 94811 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRH32_rq), |
| 34016 | /* 94814 */ GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 34017 | /* 94816 */ GIR_RootToRootCopy, /*OpIdx*/1, // base |
| 34018 | /* 94818 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets |
| 34019 | /* 94820 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34020 | /* 94824 */ GIR_RootConstrainSelectedInstOperands, |
| 34021 | /* 94825 */ // GIR_Coverage, 5036, |
| 34022 | /* 94825 */ GIR_EraseRootFromParent_Done, |
| 34023 | /* 94826 */ // Label 1731: @94826 |
| 34024 | /* 94826 */ GIM_Try, /*On fail goto*//*Label 1732*/ GIMT_Encode4(94887), // Rule ID 5039 // |
| 34025 | /* 94831 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_offset), |
| 34026 | /* 94836 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 34027 | /* 94839 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 34028 | /* 94842 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34029 | /* 94845 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 34030 | /* 94848 */ // MIs[0] base |
| 34031 | /* 94848 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 34032 | /* 94852 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 34033 | /* 94856 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34034 | /* 94860 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34035 | /* 94864 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 32, |
| 34036 | /* 94868 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 34037 | /* 94872 */ // (intrinsic_void 3724:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, MQPR:{ *:[v4i32] }:$data, 32:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSTRW32_rq_u MQPR:{ *:[v4i32] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 34038 | /* 94872 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRW32_rq_u), |
| 34039 | /* 94875 */ GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 34040 | /* 94877 */ GIR_RootToRootCopy, /*OpIdx*/1, // base |
| 34041 | /* 94879 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets |
| 34042 | /* 94881 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34043 | /* 94885 */ GIR_RootConstrainSelectedInstOperands, |
| 34044 | /* 94886 */ // GIR_Coverage, 5039, |
| 34045 | /* 94886 */ GIR_EraseRootFromParent_Done, |
| 34046 | /* 94887 */ // Label 1732: @94887 |
| 34047 | /* 94887 */ GIM_Try, /*On fail goto*//*Label 1733*/ GIMT_Encode4(94948), // Rule ID 5040 // |
| 34048 | /* 94892 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_offset), |
| 34049 | /* 94897 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 34050 | /* 94900 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 34051 | /* 94903 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34052 | /* 94906 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 34053 | /* 94909 */ // MIs[0] base |
| 34054 | /* 94909 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 34055 | /* 94913 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 34056 | /* 94917 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34057 | /* 94921 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34058 | /* 94925 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 32, |
| 34059 | /* 94929 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 2, |
| 34060 | /* 94933 */ // (intrinsic_void 3724:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, MQPR:{ *:[v4i32] }:$data, 32:{ *:[i32] }, 2:{ *:[i32] }) => (MVE_VSTRW32_rq MQPR:{ *:[v4i32] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 34061 | /* 94933 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRW32_rq), |
| 34062 | /* 94936 */ GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 34063 | /* 94938 */ GIR_RootToRootCopy, /*OpIdx*/1, // base |
| 34064 | /* 94940 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets |
| 34065 | /* 94942 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34066 | /* 94946 */ GIR_RootConstrainSelectedInstOperands, |
| 34067 | /* 94947 */ // GIR_Coverage, 5040, |
| 34068 | /* 94947 */ GIR_EraseRootFromParent_Done, |
| 34069 | /* 94948 */ // Label 1733: @94948 |
| 34070 | /* 94948 */ GIM_Try, /*On fail goto*//*Label 1734*/ GIMT_Encode4(95009), // Rule ID 5043 // |
| 34071 | /* 94953 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_offset), |
| 34072 | /* 94958 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 34073 | /* 94961 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 34074 | /* 94964 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34075 | /* 94967 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 34076 | /* 94970 */ // MIs[0] base |
| 34077 | /* 94970 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 34078 | /* 94974 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 34079 | /* 94978 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34080 | /* 94982 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34081 | /* 94986 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 32, |
| 34082 | /* 94990 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 34083 | /* 94994 */ // (intrinsic_void 3724:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, MQPR:{ *:[v4f32] }:$data, 32:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSTRW32_rq_u MQPR:{ *:[v4f32] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 34084 | /* 94994 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRW32_rq_u), |
| 34085 | /* 94997 */ GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 34086 | /* 94999 */ GIR_RootToRootCopy, /*OpIdx*/1, // base |
| 34087 | /* 95001 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets |
| 34088 | /* 95003 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34089 | /* 95007 */ GIR_RootConstrainSelectedInstOperands, |
| 34090 | /* 95008 */ // GIR_Coverage, 5043, |
| 34091 | /* 95008 */ GIR_EraseRootFromParent_Done, |
| 34092 | /* 95009 */ // Label 1734: @95009 |
| 34093 | /* 95009 */ GIM_Try, /*On fail goto*//*Label 1735*/ GIMT_Encode4(95070), // Rule ID 5044 // |
| 34094 | /* 95014 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_offset), |
| 34095 | /* 95019 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 34096 | /* 95022 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 34097 | /* 95025 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34098 | /* 95028 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 34099 | /* 95031 */ // MIs[0] base |
| 34100 | /* 95031 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 34101 | /* 95035 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 34102 | /* 95039 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34103 | /* 95043 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34104 | /* 95047 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 32, |
| 34105 | /* 95051 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 2, |
| 34106 | /* 95055 */ // (intrinsic_void 3724:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, MQPR:{ *:[v4f32] }:$data, 32:{ *:[i32] }, 2:{ *:[i32] }) => (MVE_VSTRW32_rq MQPR:{ *:[v4f32] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 34107 | /* 95055 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRW32_rq), |
| 34108 | /* 95058 */ GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 34109 | /* 95060 */ GIR_RootToRootCopy, /*OpIdx*/1, // base |
| 34110 | /* 95062 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets |
| 34111 | /* 95064 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34112 | /* 95068 */ GIR_RootConstrainSelectedInstOperands, |
| 34113 | /* 95069 */ // GIR_Coverage, 5044, |
| 34114 | /* 95069 */ GIR_EraseRootFromParent_Done, |
| 34115 | /* 95070 */ // Label 1735: @95070 |
| 34116 | /* 95070 */ GIM_Try, /*On fail goto*//*Label 1736*/ GIMT_Encode4(95131), // Rule ID 5047 // |
| 34117 | /* 95075 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_offset), |
| 34118 | /* 95080 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 34119 | /* 95083 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 34120 | /* 95086 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34121 | /* 95089 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 34122 | /* 95092 */ // MIs[0] base |
| 34123 | /* 95092 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 34124 | /* 95096 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 34125 | /* 95100 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34126 | /* 95104 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34127 | /* 95108 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 64, |
| 34128 | /* 95112 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 34129 | /* 95116 */ // (intrinsic_void 3724:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, MQPR:{ *:[v2i64] }:$data, 64:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSTRD64_rq_u MQPR:{ *:[v2i64] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets) |
| 34130 | /* 95116 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRD64_rq_u), |
| 34131 | /* 95119 */ GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 34132 | /* 95121 */ GIR_RootToRootCopy, /*OpIdx*/1, // base |
| 34133 | /* 95123 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets |
| 34134 | /* 95125 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34135 | /* 95129 */ GIR_RootConstrainSelectedInstOperands, |
| 34136 | /* 95130 */ // GIR_Coverage, 5047, |
| 34137 | /* 95130 */ GIR_EraseRootFromParent_Done, |
| 34138 | /* 95131 */ // Label 1736: @95131 |
| 34139 | /* 95131 */ GIM_Try, /*On fail goto*//*Label 1737*/ GIMT_Encode4(95192), // Rule ID 5048 // |
| 34140 | /* 95136 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_offset), |
| 34141 | /* 95141 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 34142 | /* 95144 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 34143 | /* 95147 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34144 | /* 95150 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 34145 | /* 95153 */ // MIs[0] base |
| 34146 | /* 95153 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 34147 | /* 95157 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 34148 | /* 95161 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34149 | /* 95165 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34150 | /* 95169 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 64, |
| 34151 | /* 95173 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 3, |
| 34152 | /* 95177 */ // (intrinsic_void 3724:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, MQPR:{ *:[v2i64] }:$data, 64:{ *:[i32] }, 3:{ *:[i32] }) => (MVE_VSTRD64_rq MQPR:{ *:[v2i64] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets) |
| 34153 | /* 95177 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRD64_rq), |
| 34154 | /* 95180 */ GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 34155 | /* 95182 */ GIR_RootToRootCopy, /*OpIdx*/1, // base |
| 34156 | /* 95184 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets |
| 34157 | /* 95186 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34158 | /* 95190 */ GIR_RootConstrainSelectedInstOperands, |
| 34159 | /* 95191 */ // GIR_Coverage, 5048, |
| 34160 | /* 95191 */ GIR_EraseRootFromParent_Done, |
| 34161 | /* 95192 */ // Label 1737: @95192 |
| 34162 | /* 95192 */ GIM_Try, /*On fail goto*//*Label 1738*/ GIMT_Encode4(95256), // Rule ID 258 // |
| 34163 | /* 95197 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 34164 | /* 95200 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mcrr), |
| 34165 | /* 95205 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 34166 | /* 95208 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34167 | /* 95211 */ // MIs[0] cop |
| 34168 | /* 95211 */ GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 34169 | /* 95214 */ // MIs[0] opc1 |
| 34170 | /* 95214 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2, |
| 34171 | /* 95217 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 34172 | /* 95221 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 34173 | /* 95225 */ // MIs[0] CRm |
| 34174 | /* 95225 */ GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 34175 | /* 95228 */ // (intrinsic_void 3528:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPRnopc:{ *:[i32] }:$Rt, GPRnopc:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm) => (MCRR (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPRnopc:{ *:[i32] }:$Rt, GPRnopc:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm) |
| 34176 | /* 95228 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MCRR), |
| 34177 | /* 95231 */ GIR_RootToRootCopy, /*OpIdx*/1, // cop |
| 34178 | /* 95233 */ GIR_RootToRootCopy, /*OpIdx*/2, // opc1 |
| 34179 | /* 95235 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rt |
| 34180 | /* 95237 */ GIR_RootToRootCopy, /*OpIdx*/4, // Rt2 |
| 34181 | /* 95239 */ GIR_RootToRootCopy, /*OpIdx*/5, // CRm |
| 34182 | /* 95241 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 34183 | /* 95244 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 34184 | /* 95250 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34185 | /* 95254 */ GIR_RootConstrainSelectedInstOperands, |
| 34186 | /* 95255 */ // GIR_Coverage, 258, |
| 34187 | /* 95255 */ GIR_EraseRootFromParent_Done, |
| 34188 | /* 95256 */ // Label 1738: @95256 |
| 34189 | /* 95256 */ GIM_Try, /*On fail goto*//*Label 1739*/ GIMT_Encode4(95311), // Rule ID 259 // |
| 34190 | /* 95261 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM_PreV8), |
| 34191 | /* 95264 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mcrr2), |
| 34192 | /* 95269 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 34193 | /* 95272 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34194 | /* 95275 */ // MIs[0] cop |
| 34195 | /* 95275 */ GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 34196 | /* 95278 */ // MIs[0] opc1 |
| 34197 | /* 95278 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2, |
| 34198 | /* 95281 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 34199 | /* 95285 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 34200 | /* 95289 */ // MIs[0] CRm |
| 34201 | /* 95289 */ GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 34202 | /* 95292 */ // (intrinsic_void 3529:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPRnopc:{ *:[i32] }:$Rt, GPRnopc:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm) => (MCRR2 (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPRnopc:{ *:[i32] }:$Rt, GPRnopc:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm) |
| 34203 | /* 95292 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MCRR2), |
| 34204 | /* 95295 */ GIR_RootToRootCopy, /*OpIdx*/1, // cop |
| 34205 | /* 95297 */ GIR_RootToRootCopy, /*OpIdx*/2, // opc1 |
| 34206 | /* 95299 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rt |
| 34207 | /* 95301 */ GIR_RootToRootCopy, /*OpIdx*/4, // Rt2 |
| 34208 | /* 95303 */ GIR_RootToRootCopy, /*OpIdx*/5, // CRm |
| 34209 | /* 95305 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34210 | /* 95309 */ GIR_RootConstrainSelectedInstOperands, |
| 34211 | /* 95310 */ // GIR_Coverage, 259, |
| 34212 | /* 95310 */ GIR_EraseRootFromParent_Done, |
| 34213 | /* 95311 */ // Label 1739: @95311 |
| 34214 | /* 95311 */ GIM_Try, /*On fail goto*//*Label 1740*/ GIMT_Encode4(95375), // Rule ID 596 // |
| 34215 | /* 95316 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 34216 | /* 95319 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mcrr), |
| 34217 | /* 95324 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 34218 | /* 95327 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34219 | /* 95330 */ // MIs[0] cop |
| 34220 | /* 95330 */ GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 34221 | /* 95333 */ // MIs[0] opc1 |
| 34222 | /* 95333 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2, |
| 34223 | /* 95336 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 34224 | /* 95340 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 34225 | /* 95344 */ // MIs[0] CRm |
| 34226 | /* 95344 */ GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 34227 | /* 95347 */ // (intrinsic_void 3528:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, GPR:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm) => (t2MCRR (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, GPR:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm) |
| 34228 | /* 95347 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MCRR), |
| 34229 | /* 95350 */ GIR_RootToRootCopy, /*OpIdx*/1, // cop |
| 34230 | /* 95352 */ GIR_RootToRootCopy, /*OpIdx*/2, // opc1 |
| 34231 | /* 95354 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rt |
| 34232 | /* 95356 */ GIR_RootToRootCopy, /*OpIdx*/4, // Rt2 |
| 34233 | /* 95358 */ GIR_RootToRootCopy, /*OpIdx*/5, // CRm |
| 34234 | /* 95360 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 34235 | /* 95363 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 34236 | /* 95369 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34237 | /* 95373 */ GIR_RootConstrainSelectedInstOperands, |
| 34238 | /* 95374 */ // GIR_Coverage, 596, |
| 34239 | /* 95374 */ GIR_EraseRootFromParent_Done, |
| 34240 | /* 95375 */ // Label 1740: @95375 |
| 34241 | /* 95375 */ GIM_Try, /*On fail goto*//*Label 1741*/ GIMT_Encode4(95439), // Rule ID 597 // |
| 34242 | /* 95380 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2_PreV8), |
| 34243 | /* 95383 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mcrr2), |
| 34244 | /* 95388 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 34245 | /* 95391 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34246 | /* 95394 */ // MIs[0] cop |
| 34247 | /* 95394 */ GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 34248 | /* 95397 */ // MIs[0] opc1 |
| 34249 | /* 95397 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2, |
| 34250 | /* 95400 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 34251 | /* 95404 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 34252 | /* 95408 */ // MIs[0] CRm |
| 34253 | /* 95408 */ GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 34254 | /* 95411 */ // (intrinsic_void 3529:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, GPR:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm) => (t2MCRR2 (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, GPR:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm) |
| 34255 | /* 95411 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MCRR2), |
| 34256 | /* 95414 */ GIR_RootToRootCopy, /*OpIdx*/1, // cop |
| 34257 | /* 95416 */ GIR_RootToRootCopy, /*OpIdx*/2, // opc1 |
| 34258 | /* 95418 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rt |
| 34259 | /* 95420 */ GIR_RootToRootCopy, /*OpIdx*/4, // Rt2 |
| 34260 | /* 95422 */ GIR_RootToRootCopy, /*OpIdx*/5, // CRm |
| 34261 | /* 95424 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 34262 | /* 95427 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 34263 | /* 95433 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34264 | /* 95437 */ GIR_RootConstrainSelectedInstOperands, |
| 34265 | /* 95438 */ // GIR_Coverage, 597, |
| 34266 | /* 95438 */ GIR_EraseRootFromParent_Done, |
| 34267 | /* 95439 */ // Label 1741: @95439 |
| 34268 | /* 95439 */ GIM_Reject, |
| 34269 | /* 95440 */ // Label 1722: @95440 |
| 34270 | /* 95440 */ GIM_Try, /*On fail goto*//*Label 1742*/ GIMT_Encode4(98791), |
| 34271 | /* 95445 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/7, |
| 34272 | /* 95448 */ GIM_Try, /*On fail goto*//*Label 1743*/ GIMT_Encode4(95509), // Rule ID 246 // |
| 34273 | /* 95453 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM_PreV8), |
| 34274 | /* 95456 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_cdp), |
| 34275 | /* 95461 */ // MIs[0] cop |
| 34276 | /* 95461 */ GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 34277 | /* 95464 */ // MIs[0] opc1 |
| 34278 | /* 95464 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2, |
| 34279 | /* 95467 */ // MIs[0] CRd |
| 34280 | /* 95467 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3, |
| 34281 | /* 95470 */ // MIs[0] CRn |
| 34282 | /* 95470 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4, |
| 34283 | /* 95473 */ // MIs[0] CRm |
| 34284 | /* 95473 */ GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 34285 | /* 95476 */ // MIs[0] opc2 |
| 34286 | /* 95476 */ GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 34287 | /* 95479 */ // (intrinsic_void 3496:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) => (CDP (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) |
| 34288 | /* 95479 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::CDP), |
| 34289 | /* 95482 */ GIR_RootToRootCopy, /*OpIdx*/1, // cop |
| 34290 | /* 95484 */ GIR_RootToRootCopy, /*OpIdx*/2, // opc1 |
| 34291 | /* 95486 */ GIR_RootToRootCopy, /*OpIdx*/3, // CRd |
| 34292 | /* 95488 */ GIR_RootToRootCopy, /*OpIdx*/4, // CRn |
| 34293 | /* 95490 */ GIR_RootToRootCopy, /*OpIdx*/5, // CRm |
| 34294 | /* 95492 */ GIR_RootToRootCopy, /*OpIdx*/6, // opc2 |
| 34295 | /* 95494 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 34296 | /* 95497 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 34297 | /* 95503 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34298 | /* 95507 */ GIR_RootConstrainSelectedInstOperands, |
| 34299 | /* 95508 */ // GIR_Coverage, 246, |
| 34300 | /* 95508 */ GIR_EraseRootFromParent_Done, |
| 34301 | /* 95509 */ // Label 1743: @95509 |
| 34302 | /* 95509 */ GIM_Try, /*On fail goto*//*Label 1744*/ GIMT_Encode4(95561), // Rule ID 247 // |
| 34303 | /* 95514 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM_PreV8), |
| 34304 | /* 95517 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_cdp2), |
| 34305 | /* 95522 */ // MIs[0] cop |
| 34306 | /* 95522 */ GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 34307 | /* 95525 */ // MIs[0] opc1 |
| 34308 | /* 95525 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2, |
| 34309 | /* 95528 */ // MIs[0] CRd |
| 34310 | /* 95528 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3, |
| 34311 | /* 95531 */ // MIs[0] CRn |
| 34312 | /* 95531 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4, |
| 34313 | /* 95534 */ // MIs[0] CRm |
| 34314 | /* 95534 */ GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 34315 | /* 95537 */ // MIs[0] opc2 |
| 34316 | /* 95537 */ GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 34317 | /* 95540 */ // (intrinsic_void 3497:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) => (CDP2 (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) |
| 34318 | /* 95540 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::CDP2), |
| 34319 | /* 95543 */ GIR_RootToRootCopy, /*OpIdx*/1, // cop |
| 34320 | /* 95545 */ GIR_RootToRootCopy, /*OpIdx*/2, // opc1 |
| 34321 | /* 95547 */ GIR_RootToRootCopy, /*OpIdx*/3, // CRd |
| 34322 | /* 95549 */ GIR_RootToRootCopy, /*OpIdx*/4, // CRn |
| 34323 | /* 95551 */ GIR_RootToRootCopy, /*OpIdx*/5, // CRm |
| 34324 | /* 95553 */ GIR_RootToRootCopy, /*OpIdx*/6, // opc2 |
| 34325 | /* 95555 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34326 | /* 95559 */ GIR_RootConstrainSelectedInstOperands, |
| 34327 | /* 95560 */ // GIR_Coverage, 247, |
| 34328 | /* 95560 */ GIR_EraseRootFromParent_Done, |
| 34329 | /* 95561 */ // Label 1744: @95561 |
| 34330 | /* 95561 */ GIM_Try, /*On fail goto*//*Label 1745*/ GIMT_Encode4(95622), // Rule ID 598 // |
| 34331 | /* 95566 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2_PreV8), |
| 34332 | /* 95569 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_cdp), |
| 34333 | /* 95574 */ // MIs[0] cop |
| 34334 | /* 95574 */ GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 34335 | /* 95577 */ // MIs[0] opc1 |
| 34336 | /* 95577 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2, |
| 34337 | /* 95580 */ // MIs[0] CRd |
| 34338 | /* 95580 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3, |
| 34339 | /* 95583 */ // MIs[0] CRn |
| 34340 | /* 95583 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4, |
| 34341 | /* 95586 */ // MIs[0] CRm |
| 34342 | /* 95586 */ GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 34343 | /* 95589 */ // MIs[0] opc2 |
| 34344 | /* 95589 */ GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 34345 | /* 95592 */ // (intrinsic_void 3496:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) => (t2CDP (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) |
| 34346 | /* 95592 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2CDP), |
| 34347 | /* 95595 */ GIR_RootToRootCopy, /*OpIdx*/1, // cop |
| 34348 | /* 95597 */ GIR_RootToRootCopy, /*OpIdx*/2, // opc1 |
| 34349 | /* 95599 */ GIR_RootToRootCopy, /*OpIdx*/3, // CRd |
| 34350 | /* 95601 */ GIR_RootToRootCopy, /*OpIdx*/4, // CRn |
| 34351 | /* 95603 */ GIR_RootToRootCopy, /*OpIdx*/5, // CRm |
| 34352 | /* 95605 */ GIR_RootToRootCopy, /*OpIdx*/6, // opc2 |
| 34353 | /* 95607 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 34354 | /* 95610 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 34355 | /* 95616 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34356 | /* 95620 */ GIR_RootConstrainSelectedInstOperands, |
| 34357 | /* 95621 */ // GIR_Coverage, 598, |
| 34358 | /* 95621 */ GIR_EraseRootFromParent_Done, |
| 34359 | /* 95622 */ // Label 1745: @95622 |
| 34360 | /* 95622 */ GIM_Try, /*On fail goto*//*Label 1746*/ GIMT_Encode4(95683), // Rule ID 599 // |
| 34361 | /* 95627 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2_PreV8), |
| 34362 | /* 95630 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_cdp2), |
| 34363 | /* 95635 */ // MIs[0] cop |
| 34364 | /* 95635 */ GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 34365 | /* 95638 */ // MIs[0] opc1 |
| 34366 | /* 95638 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2, |
| 34367 | /* 95641 */ // MIs[0] CRd |
| 34368 | /* 95641 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3, |
| 34369 | /* 95644 */ // MIs[0] CRn |
| 34370 | /* 95644 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4, |
| 34371 | /* 95647 */ // MIs[0] CRm |
| 34372 | /* 95647 */ GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 34373 | /* 95650 */ // MIs[0] opc2 |
| 34374 | /* 95650 */ GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 34375 | /* 95653 */ // (intrinsic_void 3497:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) => (t2CDP2 (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) |
| 34376 | /* 95653 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2CDP2), |
| 34377 | /* 95656 */ GIR_RootToRootCopy, /*OpIdx*/1, // cop |
| 34378 | /* 95658 */ GIR_RootToRootCopy, /*OpIdx*/2, // opc1 |
| 34379 | /* 95660 */ GIR_RootToRootCopy, /*OpIdx*/3, // CRd |
| 34380 | /* 95662 */ GIR_RootToRootCopy, /*OpIdx*/4, // CRn |
| 34381 | /* 95664 */ GIR_RootToRootCopy, /*OpIdx*/5, // CRm |
| 34382 | /* 95666 */ GIR_RootToRootCopy, /*OpIdx*/6, // opc2 |
| 34383 | /* 95668 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 34384 | /* 95671 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 34385 | /* 95677 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34386 | /* 95681 */ GIR_RootConstrainSelectedInstOperands, |
| 34387 | /* 95682 */ // GIR_Coverage, 599, |
| 34388 | /* 95682 */ GIR_EraseRootFromParent_Done, |
| 34389 | /* 95683 */ // Label 1746: @95683 |
| 34390 | /* 95683 */ GIM_Try, /*On fail goto*//*Label 1747*/ GIMT_Encode4(95751), // Rule ID 4937 // |
| 34391 | /* 95688 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 34392 | /* 95693 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 34393 | /* 95696 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 34394 | /* 95699 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34395 | /* 95702 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 34396 | /* 95705 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 34397 | /* 95708 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34398 | /* 95712 */ // MIs[0] base |
| 34399 | /* 95712 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 34400 | /* 95716 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 34401 | /* 95720 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34402 | /* 95724 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16, |
| 34403 | /* 95728 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 34404 | /* 95732 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 34405 | /* 95736 */ // (intrinsic_w_chain:{ *:[v8i16] } 3651:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRHU16_rq_u:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets) |
| 34406 | /* 95736 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq_u), |
| 34407 | /* 95739 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34408 | /* 95741 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34409 | /* 95743 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34410 | /* 95745 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34411 | /* 95749 */ GIR_RootConstrainSelectedInstOperands, |
| 34412 | /* 95750 */ // GIR_Coverage, 4937, |
| 34413 | /* 95750 */ GIR_EraseRootFromParent_Done, |
| 34414 | /* 95751 */ // Label 1747: @95751 |
| 34415 | /* 95751 */ GIM_Try, /*On fail goto*//*Label 1748*/ GIMT_Encode4(95819), // Rule ID 4938 // |
| 34416 | /* 95756 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 34417 | /* 95761 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 34418 | /* 95764 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 34419 | /* 95767 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34420 | /* 95770 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 34421 | /* 95773 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 34422 | /* 95776 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34423 | /* 95780 */ // MIs[0] base |
| 34424 | /* 95780 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 34425 | /* 95784 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 34426 | /* 95788 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34427 | /* 95792 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16, |
| 34428 | /* 95796 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 34429 | /* 95800 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 34430 | /* 95804 */ // (intrinsic_w_chain:{ *:[v8i16] } 3651:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRHU16_rq:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets) |
| 34431 | /* 95804 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq), |
| 34432 | /* 95807 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34433 | /* 95809 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34434 | /* 95811 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34435 | /* 95813 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34436 | /* 95817 */ GIR_RootConstrainSelectedInstOperands, |
| 34437 | /* 95818 */ // GIR_Coverage, 4938, |
| 34438 | /* 95818 */ GIR_EraseRootFromParent_Done, |
| 34439 | /* 95819 */ // Label 1748: @95819 |
| 34440 | /* 95819 */ GIM_Try, /*On fail goto*//*Label 1749*/ GIMT_Encode4(95887), // Rule ID 4941 // |
| 34441 | /* 95824 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 34442 | /* 95829 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 34443 | /* 95832 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 34444 | /* 95835 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34445 | /* 95838 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 34446 | /* 95841 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 34447 | /* 95844 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34448 | /* 95848 */ // MIs[0] base |
| 34449 | /* 95848 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 34450 | /* 95852 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 34451 | /* 95856 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34452 | /* 95860 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 8, |
| 34453 | /* 95864 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 34454 | /* 95868 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 34455 | /* 95872 */ // (intrinsic_w_chain:{ *:[v16i8] } 3651:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v16i8] }:$offsets, 8:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRBU8_rq:{ *:[v16i8] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v16i8] }:$offsets) |
| 34456 | /* 95872 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRBU8_rq), |
| 34457 | /* 95875 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34458 | /* 95877 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34459 | /* 95879 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34460 | /* 95881 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34461 | /* 95885 */ GIR_RootConstrainSelectedInstOperands, |
| 34462 | /* 95886 */ // GIR_Coverage, 4941, |
| 34463 | /* 95886 */ GIR_EraseRootFromParent_Done, |
| 34464 | /* 95887 */ // Label 1749: @95887 |
| 34465 | /* 95887 */ GIM_Try, /*On fail goto*//*Label 1750*/ GIMT_Encode4(95955), // Rule ID 4949 // |
| 34466 | /* 95892 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 34467 | /* 95897 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 34468 | /* 95900 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 34469 | /* 95903 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34470 | /* 95906 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 34471 | /* 95909 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 34472 | /* 95912 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34473 | /* 95916 */ // MIs[0] base |
| 34474 | /* 95916 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 34475 | /* 95920 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 34476 | /* 95924 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34477 | /* 95928 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 8, |
| 34478 | /* 95932 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 34479 | /* 95936 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 34480 | /* 95940 */ // (intrinsic_w_chain:{ *:[v16i8] } 3651:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v16i8] }:$offsets, 8:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRBU8_rq:{ *:[v16i8] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v16i8] }:$offsets) |
| 34481 | /* 95940 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRBU8_rq), |
| 34482 | /* 95943 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34483 | /* 95945 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34484 | /* 95947 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34485 | /* 95949 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34486 | /* 95953 */ GIR_RootConstrainSelectedInstOperands, |
| 34487 | /* 95954 */ // GIR_Coverage, 4949, |
| 34488 | /* 95954 */ GIR_EraseRootFromParent_Done, |
| 34489 | /* 95955 */ // Label 1750: @95955 |
| 34490 | /* 95955 */ GIM_Try, /*On fail goto*//*Label 1751*/ GIMT_Encode4(96023), // Rule ID 4951 // |
| 34491 | /* 95960 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 34492 | /* 95965 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 34493 | /* 95968 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 34494 | /* 95971 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34495 | /* 95974 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 34496 | /* 95977 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 34497 | /* 95980 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34498 | /* 95984 */ // MIs[0] base |
| 34499 | /* 95984 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 34500 | /* 95988 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 34501 | /* 95992 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34502 | /* 95996 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 8, |
| 34503 | /* 96000 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 34504 | /* 96004 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 34505 | /* 96008 */ // (intrinsic_w_chain:{ *:[v8i16] } 3651:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 8:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRBU16_rq:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets) |
| 34506 | /* 96008 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRBU16_rq), |
| 34507 | /* 96011 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34508 | /* 96013 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34509 | /* 96015 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34510 | /* 96017 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34511 | /* 96021 */ GIR_RootConstrainSelectedInstOperands, |
| 34512 | /* 96022 */ // GIR_Coverage, 4951, |
| 34513 | /* 96022 */ GIR_EraseRootFromParent_Done, |
| 34514 | /* 96023 */ // Label 1751: @96023 |
| 34515 | /* 96023 */ GIM_Try, /*On fail goto*//*Label 1752*/ GIMT_Encode4(96091), // Rule ID 4953 // |
| 34516 | /* 96028 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 34517 | /* 96033 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 34518 | /* 96036 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 34519 | /* 96039 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34520 | /* 96042 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 34521 | /* 96045 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 34522 | /* 96048 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34523 | /* 96052 */ // MIs[0] base |
| 34524 | /* 96052 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 34525 | /* 96056 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 34526 | /* 96060 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34527 | /* 96064 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 8, |
| 34528 | /* 96068 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 34529 | /* 96072 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 34530 | /* 96076 */ // (intrinsic_w_chain:{ *:[v8i16] } 3651:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 8:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRBS16_rq:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets) |
| 34531 | /* 96076 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRBS16_rq), |
| 34532 | /* 96079 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34533 | /* 96081 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34534 | /* 96083 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34535 | /* 96085 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34536 | /* 96089 */ GIR_RootConstrainSelectedInstOperands, |
| 34537 | /* 96090 */ // GIR_Coverage, 4953, |
| 34538 | /* 96090 */ GIR_EraseRootFromParent_Done, |
| 34539 | /* 96091 */ // Label 1752: @96091 |
| 34540 | /* 96091 */ GIM_Try, /*On fail goto*//*Label 1753*/ GIMT_Encode4(96159), // Rule ID 4955 // |
| 34541 | /* 96096 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 34542 | /* 96101 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 34543 | /* 96104 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 34544 | /* 96107 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34545 | /* 96110 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 34546 | /* 96113 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 34547 | /* 96116 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34548 | /* 96120 */ // MIs[0] base |
| 34549 | /* 96120 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 34550 | /* 96124 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 34551 | /* 96128 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34552 | /* 96132 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 8, |
| 34553 | /* 96136 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 34554 | /* 96140 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 34555 | /* 96144 */ // (intrinsic_w_chain:{ *:[v4i32] } 3651:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 8:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRBU32_rq:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 34556 | /* 96144 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRBU32_rq), |
| 34557 | /* 96147 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34558 | /* 96149 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34559 | /* 96151 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34560 | /* 96153 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34561 | /* 96157 */ GIR_RootConstrainSelectedInstOperands, |
| 34562 | /* 96158 */ // GIR_Coverage, 4955, |
| 34563 | /* 96158 */ GIR_EraseRootFromParent_Done, |
| 34564 | /* 96159 */ // Label 1753: @96159 |
| 34565 | /* 96159 */ GIM_Try, /*On fail goto*//*Label 1754*/ GIMT_Encode4(96227), // Rule ID 4957 // |
| 34566 | /* 96164 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 34567 | /* 96169 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 34568 | /* 96172 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 34569 | /* 96175 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34570 | /* 96178 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 34571 | /* 96181 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 34572 | /* 96184 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34573 | /* 96188 */ // MIs[0] base |
| 34574 | /* 96188 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 34575 | /* 96192 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 34576 | /* 96196 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34577 | /* 96200 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 8, |
| 34578 | /* 96204 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 34579 | /* 96208 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 34580 | /* 96212 */ // (intrinsic_w_chain:{ *:[v4i32] } 3651:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 8:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRBS32_rq:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 34581 | /* 96212 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRBS32_rq), |
| 34582 | /* 96215 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34583 | /* 96217 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34584 | /* 96219 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34585 | /* 96221 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34586 | /* 96225 */ GIR_RootConstrainSelectedInstOperands, |
| 34587 | /* 96226 */ // GIR_Coverage, 4957, |
| 34588 | /* 96226 */ GIR_EraseRootFromParent_Done, |
| 34589 | /* 96227 */ // Label 1754: @96227 |
| 34590 | /* 96227 */ GIM_Try, /*On fail goto*//*Label 1755*/ GIMT_Encode4(96295), // Rule ID 4959 // |
| 34591 | /* 96232 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 34592 | /* 96237 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 34593 | /* 96240 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 34594 | /* 96243 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34595 | /* 96246 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 34596 | /* 96249 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 34597 | /* 96252 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34598 | /* 96256 */ // MIs[0] base |
| 34599 | /* 96256 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 34600 | /* 96260 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 34601 | /* 96264 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34602 | /* 96268 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16, |
| 34603 | /* 96272 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 34604 | /* 96276 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 34605 | /* 96280 */ // (intrinsic_w_chain:{ *:[v8i16] } 3651:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRHU16_rq_u:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets) |
| 34606 | /* 96280 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq_u), |
| 34607 | /* 96283 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34608 | /* 96285 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34609 | /* 96287 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34610 | /* 96289 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34611 | /* 96293 */ GIR_RootConstrainSelectedInstOperands, |
| 34612 | /* 96294 */ // GIR_Coverage, 4959, |
| 34613 | /* 96294 */ GIR_EraseRootFromParent_Done, |
| 34614 | /* 96295 */ // Label 1755: @96295 |
| 34615 | /* 96295 */ GIM_Try, /*On fail goto*//*Label 1756*/ GIMT_Encode4(96363), // Rule ID 4960 // |
| 34616 | /* 96300 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 34617 | /* 96305 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 34618 | /* 96308 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 34619 | /* 96311 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34620 | /* 96314 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 34621 | /* 96317 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 34622 | /* 96320 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34623 | /* 96324 */ // MIs[0] base |
| 34624 | /* 96324 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 34625 | /* 96328 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 34626 | /* 96332 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34627 | /* 96336 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16, |
| 34628 | /* 96340 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 34629 | /* 96344 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 34630 | /* 96348 */ // (intrinsic_w_chain:{ *:[v8i16] } 3651:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRHU16_rq:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets) |
| 34631 | /* 96348 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq), |
| 34632 | /* 96351 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34633 | /* 96353 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34634 | /* 96355 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34635 | /* 96357 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34636 | /* 96361 */ GIR_RootConstrainSelectedInstOperands, |
| 34637 | /* 96362 */ // GIR_Coverage, 4960, |
| 34638 | /* 96362 */ GIR_EraseRootFromParent_Done, |
| 34639 | /* 96363 */ // Label 1756: @96363 |
| 34640 | /* 96363 */ GIM_Try, /*On fail goto*//*Label 1757*/ GIMT_Encode4(96431), // Rule ID 4963 // |
| 34641 | /* 96368 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 34642 | /* 96373 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 34643 | /* 96376 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 34644 | /* 96379 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34645 | /* 96382 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 34646 | /* 96385 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 34647 | /* 96388 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34648 | /* 96392 */ // MIs[0] base |
| 34649 | /* 96392 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 34650 | /* 96396 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 34651 | /* 96400 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34652 | /* 96404 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16, |
| 34653 | /* 96408 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 34654 | /* 96412 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 34655 | /* 96416 */ // (intrinsic_w_chain:{ *:[v8i16] } 3651:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRHU16_rq_u:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets) |
| 34656 | /* 96416 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq_u), |
| 34657 | /* 96419 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34658 | /* 96421 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34659 | /* 96423 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34660 | /* 96425 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34661 | /* 96429 */ GIR_RootConstrainSelectedInstOperands, |
| 34662 | /* 96430 */ // GIR_Coverage, 4963, |
| 34663 | /* 96430 */ GIR_EraseRootFromParent_Done, |
| 34664 | /* 96431 */ // Label 1757: @96431 |
| 34665 | /* 96431 */ GIM_Try, /*On fail goto*//*Label 1758*/ GIMT_Encode4(96499), // Rule ID 4964 // |
| 34666 | /* 96436 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 34667 | /* 96441 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 34668 | /* 96444 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 34669 | /* 96447 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34670 | /* 96450 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 34671 | /* 96453 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 34672 | /* 96456 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34673 | /* 96460 */ // MIs[0] base |
| 34674 | /* 96460 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 34675 | /* 96464 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 34676 | /* 96468 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34677 | /* 96472 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16, |
| 34678 | /* 96476 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 34679 | /* 96480 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 34680 | /* 96484 */ // (intrinsic_w_chain:{ *:[v8i16] } 3651:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRHU16_rq:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets) |
| 34681 | /* 96484 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq), |
| 34682 | /* 96487 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34683 | /* 96489 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34684 | /* 96491 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34685 | /* 96493 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34686 | /* 96497 */ GIR_RootConstrainSelectedInstOperands, |
| 34687 | /* 96498 */ // GIR_Coverage, 4964, |
| 34688 | /* 96498 */ GIR_EraseRootFromParent_Done, |
| 34689 | /* 96499 */ // Label 1758: @96499 |
| 34690 | /* 96499 */ GIM_Try, /*On fail goto*//*Label 1759*/ GIMT_Encode4(96567), // Rule ID 4967 // |
| 34691 | /* 96504 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 34692 | /* 96509 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 34693 | /* 96512 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 34694 | /* 96515 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34695 | /* 96518 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 34696 | /* 96521 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 34697 | /* 96524 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34698 | /* 96528 */ // MIs[0] base |
| 34699 | /* 96528 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 34700 | /* 96532 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 34701 | /* 96536 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34702 | /* 96540 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16, |
| 34703 | /* 96544 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 34704 | /* 96548 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 34705 | /* 96552 */ // (intrinsic_w_chain:{ *:[v8i16] } 3651:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRHU16_rq_u:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets) |
| 34706 | /* 96552 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq_u), |
| 34707 | /* 96555 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34708 | /* 96557 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34709 | /* 96559 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34710 | /* 96561 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34711 | /* 96565 */ GIR_RootConstrainSelectedInstOperands, |
| 34712 | /* 96566 */ // GIR_Coverage, 4967, |
| 34713 | /* 96566 */ GIR_EraseRootFromParent_Done, |
| 34714 | /* 96567 */ // Label 1759: @96567 |
| 34715 | /* 96567 */ GIM_Try, /*On fail goto*//*Label 1760*/ GIMT_Encode4(96635), // Rule ID 4968 // |
| 34716 | /* 96572 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 34717 | /* 96577 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 34718 | /* 96580 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 34719 | /* 96583 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34720 | /* 96586 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 34721 | /* 96589 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 34722 | /* 96592 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34723 | /* 96596 */ // MIs[0] base |
| 34724 | /* 96596 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 34725 | /* 96600 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 34726 | /* 96604 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34727 | /* 96608 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16, |
| 34728 | /* 96612 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 34729 | /* 96616 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 34730 | /* 96620 */ // (intrinsic_w_chain:{ *:[v8i16] } 3651:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRHU16_rq:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets) |
| 34731 | /* 96620 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq), |
| 34732 | /* 96623 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34733 | /* 96625 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34734 | /* 96627 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34735 | /* 96629 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34736 | /* 96633 */ GIR_RootConstrainSelectedInstOperands, |
| 34737 | /* 96634 */ // GIR_Coverage, 4968, |
| 34738 | /* 96634 */ GIR_EraseRootFromParent_Done, |
| 34739 | /* 96635 */ // Label 1760: @96635 |
| 34740 | /* 96635 */ GIM_Try, /*On fail goto*//*Label 1761*/ GIMT_Encode4(96703), // Rule ID 4971 // |
| 34741 | /* 96640 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 34742 | /* 96645 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 34743 | /* 96648 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 34744 | /* 96651 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34745 | /* 96654 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 34746 | /* 96657 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 34747 | /* 96660 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34748 | /* 96664 */ // MIs[0] base |
| 34749 | /* 96664 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 34750 | /* 96668 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 34751 | /* 96672 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34752 | /* 96676 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16, |
| 34753 | /* 96680 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 34754 | /* 96684 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 34755 | /* 96688 */ // (intrinsic_w_chain:{ *:[v8f16] } 3651:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRHU16_rq_u:{ *:[v8f16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets) |
| 34756 | /* 96688 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq_u), |
| 34757 | /* 96691 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34758 | /* 96693 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34759 | /* 96695 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34760 | /* 96697 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34761 | /* 96701 */ GIR_RootConstrainSelectedInstOperands, |
| 34762 | /* 96702 */ // GIR_Coverage, 4971, |
| 34763 | /* 96702 */ GIR_EraseRootFromParent_Done, |
| 34764 | /* 96703 */ // Label 1761: @96703 |
| 34765 | /* 96703 */ GIM_Try, /*On fail goto*//*Label 1762*/ GIMT_Encode4(96771), // Rule ID 4972 // |
| 34766 | /* 96708 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 34767 | /* 96713 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 34768 | /* 96716 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 34769 | /* 96719 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34770 | /* 96722 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 34771 | /* 96725 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 34772 | /* 96728 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34773 | /* 96732 */ // MIs[0] base |
| 34774 | /* 96732 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 34775 | /* 96736 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 34776 | /* 96740 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34777 | /* 96744 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16, |
| 34778 | /* 96748 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 34779 | /* 96752 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 34780 | /* 96756 */ // (intrinsic_w_chain:{ *:[v8f16] } 3651:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRHU16_rq:{ *:[v8f16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets) |
| 34781 | /* 96756 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq), |
| 34782 | /* 96759 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34783 | /* 96761 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34784 | /* 96763 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34785 | /* 96765 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34786 | /* 96769 */ GIR_RootConstrainSelectedInstOperands, |
| 34787 | /* 96770 */ // GIR_Coverage, 4972, |
| 34788 | /* 96770 */ GIR_EraseRootFromParent_Done, |
| 34789 | /* 96771 */ // Label 1762: @96771 |
| 34790 | /* 96771 */ GIM_Try, /*On fail goto*//*Label 1763*/ GIMT_Encode4(96839), // Rule ID 4975 // |
| 34791 | /* 96776 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 34792 | /* 96781 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 34793 | /* 96784 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 34794 | /* 96787 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34795 | /* 96790 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 34796 | /* 96793 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 34797 | /* 96796 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34798 | /* 96800 */ // MIs[0] base |
| 34799 | /* 96800 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 34800 | /* 96804 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 34801 | /* 96808 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34802 | /* 96812 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16, |
| 34803 | /* 96816 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 34804 | /* 96820 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 34805 | /* 96824 */ // (intrinsic_w_chain:{ *:[v8f16] } 3651:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRHU16_rq_u:{ *:[v8f16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets) |
| 34806 | /* 96824 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq_u), |
| 34807 | /* 96827 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34808 | /* 96829 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34809 | /* 96831 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34810 | /* 96833 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34811 | /* 96837 */ GIR_RootConstrainSelectedInstOperands, |
| 34812 | /* 96838 */ // GIR_Coverage, 4975, |
| 34813 | /* 96838 */ GIR_EraseRootFromParent_Done, |
| 34814 | /* 96839 */ // Label 1763: @96839 |
| 34815 | /* 96839 */ GIM_Try, /*On fail goto*//*Label 1764*/ GIMT_Encode4(96907), // Rule ID 4976 // |
| 34816 | /* 96844 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 34817 | /* 96849 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 34818 | /* 96852 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 34819 | /* 96855 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34820 | /* 96858 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 34821 | /* 96861 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 34822 | /* 96864 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34823 | /* 96868 */ // MIs[0] base |
| 34824 | /* 96868 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 34825 | /* 96872 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 34826 | /* 96876 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34827 | /* 96880 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16, |
| 34828 | /* 96884 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 34829 | /* 96888 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 34830 | /* 96892 */ // (intrinsic_w_chain:{ *:[v8f16] } 3651:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRHU16_rq:{ *:[v8f16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets) |
| 34831 | /* 96892 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq), |
| 34832 | /* 96895 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34833 | /* 96897 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34834 | /* 96899 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34835 | /* 96901 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34836 | /* 96905 */ GIR_RootConstrainSelectedInstOperands, |
| 34837 | /* 96906 */ // GIR_Coverage, 4976, |
| 34838 | /* 96906 */ GIR_EraseRootFromParent_Done, |
| 34839 | /* 96907 */ // Label 1764: @96907 |
| 34840 | /* 96907 */ GIM_Try, /*On fail goto*//*Label 1765*/ GIMT_Encode4(96975), // Rule ID 4979 // |
| 34841 | /* 96912 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 34842 | /* 96917 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 34843 | /* 96920 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 34844 | /* 96923 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34845 | /* 96926 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 34846 | /* 96929 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 34847 | /* 96932 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34848 | /* 96936 */ // MIs[0] base |
| 34849 | /* 96936 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 34850 | /* 96940 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 34851 | /* 96944 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34852 | /* 96948 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16, |
| 34853 | /* 96952 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 34854 | /* 96956 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 34855 | /* 96960 */ // (intrinsic_w_chain:{ *:[v4i32] } 3651:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 16:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRHU32_rq_u:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 34856 | /* 96960 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU32_rq_u), |
| 34857 | /* 96963 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34858 | /* 96965 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34859 | /* 96967 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34860 | /* 96969 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34861 | /* 96973 */ GIR_RootConstrainSelectedInstOperands, |
| 34862 | /* 96974 */ // GIR_Coverage, 4979, |
| 34863 | /* 96974 */ GIR_EraseRootFromParent_Done, |
| 34864 | /* 96975 */ // Label 1765: @96975 |
| 34865 | /* 96975 */ GIM_Try, /*On fail goto*//*Label 1766*/ GIMT_Encode4(97043), // Rule ID 4980 // |
| 34866 | /* 96980 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 34867 | /* 96985 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 34868 | /* 96988 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 34869 | /* 96991 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34870 | /* 96994 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 34871 | /* 96997 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 34872 | /* 97000 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34873 | /* 97004 */ // MIs[0] base |
| 34874 | /* 97004 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 34875 | /* 97008 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 34876 | /* 97012 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34877 | /* 97016 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16, |
| 34878 | /* 97020 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 34879 | /* 97024 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 34880 | /* 97028 */ // (intrinsic_w_chain:{ *:[v4i32] } 3651:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 16:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRHU32_rq:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 34881 | /* 97028 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU32_rq), |
| 34882 | /* 97031 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34883 | /* 97033 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34884 | /* 97035 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34885 | /* 97037 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34886 | /* 97041 */ GIR_RootConstrainSelectedInstOperands, |
| 34887 | /* 97042 */ // GIR_Coverage, 4980, |
| 34888 | /* 97042 */ GIR_EraseRootFromParent_Done, |
| 34889 | /* 97043 */ // Label 1766: @97043 |
| 34890 | /* 97043 */ GIM_Try, /*On fail goto*//*Label 1767*/ GIMT_Encode4(97111), // Rule ID 4983 // |
| 34891 | /* 97048 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 34892 | /* 97053 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 34893 | /* 97056 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 34894 | /* 97059 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34895 | /* 97062 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 34896 | /* 97065 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 34897 | /* 97068 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34898 | /* 97072 */ // MIs[0] base |
| 34899 | /* 97072 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 34900 | /* 97076 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 34901 | /* 97080 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34902 | /* 97084 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16, |
| 34903 | /* 97088 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 34904 | /* 97092 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 34905 | /* 97096 */ // (intrinsic_w_chain:{ *:[v4i32] } 3651:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 16:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRHS32_rq_u:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 34906 | /* 97096 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHS32_rq_u), |
| 34907 | /* 97099 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34908 | /* 97101 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34909 | /* 97103 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34910 | /* 97105 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34911 | /* 97109 */ GIR_RootConstrainSelectedInstOperands, |
| 34912 | /* 97110 */ // GIR_Coverage, 4983, |
| 34913 | /* 97110 */ GIR_EraseRootFromParent_Done, |
| 34914 | /* 97111 */ // Label 1767: @97111 |
| 34915 | /* 97111 */ GIM_Try, /*On fail goto*//*Label 1768*/ GIMT_Encode4(97179), // Rule ID 4984 // |
| 34916 | /* 97116 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 34917 | /* 97121 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 34918 | /* 97124 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 34919 | /* 97127 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34920 | /* 97130 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 34921 | /* 97133 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 34922 | /* 97136 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34923 | /* 97140 */ // MIs[0] base |
| 34924 | /* 97140 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 34925 | /* 97144 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 34926 | /* 97148 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34927 | /* 97152 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16, |
| 34928 | /* 97156 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 34929 | /* 97160 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 34930 | /* 97164 */ // (intrinsic_w_chain:{ *:[v4i32] } 3651:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 16:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRHS32_rq:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 34931 | /* 97164 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHS32_rq), |
| 34932 | /* 97167 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34933 | /* 97169 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34934 | /* 97171 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34935 | /* 97173 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34936 | /* 97177 */ GIR_RootConstrainSelectedInstOperands, |
| 34937 | /* 97178 */ // GIR_Coverage, 4984, |
| 34938 | /* 97178 */ GIR_EraseRootFromParent_Done, |
| 34939 | /* 97179 */ // Label 1768: @97179 |
| 34940 | /* 97179 */ GIM_Try, /*On fail goto*//*Label 1769*/ GIMT_Encode4(97247), // Rule ID 4987 // |
| 34941 | /* 97184 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 34942 | /* 97189 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 34943 | /* 97192 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 34944 | /* 97195 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34945 | /* 97198 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 34946 | /* 97201 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 34947 | /* 97204 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34948 | /* 97208 */ // MIs[0] base |
| 34949 | /* 97208 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 34950 | /* 97212 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 34951 | /* 97216 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34952 | /* 97220 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 32, |
| 34953 | /* 97224 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 34954 | /* 97228 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 34955 | /* 97232 */ // (intrinsic_w_chain:{ *:[v4i32] } 3651:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRWU32_rq_u:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 34956 | /* 97232 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq_u), |
| 34957 | /* 97235 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34958 | /* 97237 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34959 | /* 97239 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34960 | /* 97241 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34961 | /* 97245 */ GIR_RootConstrainSelectedInstOperands, |
| 34962 | /* 97246 */ // GIR_Coverage, 4987, |
| 34963 | /* 97246 */ GIR_EraseRootFromParent_Done, |
| 34964 | /* 97247 */ // Label 1769: @97247 |
| 34965 | /* 97247 */ GIM_Try, /*On fail goto*//*Label 1770*/ GIMT_Encode4(97315), // Rule ID 4988 // |
| 34966 | /* 97252 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 34967 | /* 97257 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 34968 | /* 97260 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 34969 | /* 97263 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34970 | /* 97266 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 34971 | /* 97269 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 34972 | /* 97272 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34973 | /* 97276 */ // MIs[0] base |
| 34974 | /* 97276 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 34975 | /* 97280 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 34976 | /* 97284 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34977 | /* 97288 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 32, |
| 34978 | /* 97292 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 2, |
| 34979 | /* 97296 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 34980 | /* 97300 */ // (intrinsic_w_chain:{ *:[v4i32] } 3651:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 2:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRWU32_rq:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 34981 | /* 97300 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq), |
| 34982 | /* 97303 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34983 | /* 97305 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34984 | /* 97307 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34985 | /* 97309 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34986 | /* 97313 */ GIR_RootConstrainSelectedInstOperands, |
| 34987 | /* 97314 */ // GIR_Coverage, 4988, |
| 34988 | /* 97314 */ GIR_EraseRootFromParent_Done, |
| 34989 | /* 97315 */ // Label 1770: @97315 |
| 34990 | /* 97315 */ GIM_Try, /*On fail goto*//*Label 1771*/ GIMT_Encode4(97383), // Rule ID 4991 // |
| 34991 | /* 97320 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 34992 | /* 97325 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 34993 | /* 97328 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 34994 | /* 97331 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34995 | /* 97334 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 34996 | /* 97337 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 34997 | /* 97340 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34998 | /* 97344 */ // MIs[0] base |
| 34999 | /* 97344 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 35000 | /* 97348 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 35001 | /* 97352 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 35002 | /* 97356 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 32, |
| 35003 | /* 97360 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 35004 | /* 97364 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 35005 | /* 97368 */ // (intrinsic_w_chain:{ *:[v4i32] } 3651:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRWU32_rq_u:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 35006 | /* 97368 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq_u), |
| 35007 | /* 97371 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 35008 | /* 97373 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 35009 | /* 97375 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 35010 | /* 97377 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 35011 | /* 97381 */ GIR_RootConstrainSelectedInstOperands, |
| 35012 | /* 97382 */ // GIR_Coverage, 4991, |
| 35013 | /* 97382 */ GIR_EraseRootFromParent_Done, |
| 35014 | /* 97383 */ // Label 1771: @97383 |
| 35015 | /* 97383 */ GIM_Try, /*On fail goto*//*Label 1772*/ GIMT_Encode4(97451), // Rule ID 4992 // |
| 35016 | /* 97388 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 35017 | /* 97393 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 35018 | /* 97396 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 35019 | /* 97399 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 35020 | /* 97402 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 35021 | /* 97405 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 35022 | /* 97408 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 35023 | /* 97412 */ // MIs[0] base |
| 35024 | /* 97412 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 35025 | /* 97416 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 35026 | /* 97420 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 35027 | /* 97424 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 32, |
| 35028 | /* 97428 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 2, |
| 35029 | /* 97432 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 35030 | /* 97436 */ // (intrinsic_w_chain:{ *:[v4i32] } 3651:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 2:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRWU32_rq:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 35031 | /* 97436 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq), |
| 35032 | /* 97439 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 35033 | /* 97441 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 35034 | /* 97443 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 35035 | /* 97445 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 35036 | /* 97449 */ GIR_RootConstrainSelectedInstOperands, |
| 35037 | /* 97450 */ // GIR_Coverage, 4992, |
| 35038 | /* 97450 */ GIR_EraseRootFromParent_Done, |
| 35039 | /* 97451 */ // Label 1772: @97451 |
| 35040 | /* 97451 */ GIM_Try, /*On fail goto*//*Label 1773*/ GIMT_Encode4(97519), // Rule ID 4995 // |
| 35041 | /* 97456 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 35042 | /* 97461 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 35043 | /* 97464 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 35044 | /* 97467 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 35045 | /* 97470 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 35046 | /* 97473 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 35047 | /* 97476 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 35048 | /* 97480 */ // MIs[0] base |
| 35049 | /* 97480 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 35050 | /* 97484 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 35051 | /* 97488 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 35052 | /* 97492 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 32, |
| 35053 | /* 97496 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 35054 | /* 97500 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 35055 | /* 97504 */ // (intrinsic_w_chain:{ *:[v4i32] } 3651:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRWU32_rq_u:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 35056 | /* 97504 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq_u), |
| 35057 | /* 97507 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 35058 | /* 97509 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 35059 | /* 97511 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 35060 | /* 97513 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 35061 | /* 97517 */ GIR_RootConstrainSelectedInstOperands, |
| 35062 | /* 97518 */ // GIR_Coverage, 4995, |
| 35063 | /* 97518 */ GIR_EraseRootFromParent_Done, |
| 35064 | /* 97519 */ // Label 1773: @97519 |
| 35065 | /* 97519 */ GIM_Try, /*On fail goto*//*Label 1774*/ GIMT_Encode4(97587), // Rule ID 4996 // |
| 35066 | /* 97524 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 35067 | /* 97529 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 35068 | /* 97532 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 35069 | /* 97535 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 35070 | /* 97538 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 35071 | /* 97541 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 35072 | /* 97544 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 35073 | /* 97548 */ // MIs[0] base |
| 35074 | /* 97548 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 35075 | /* 97552 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 35076 | /* 97556 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 35077 | /* 97560 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 32, |
| 35078 | /* 97564 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 2, |
| 35079 | /* 97568 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 35080 | /* 97572 */ // (intrinsic_w_chain:{ *:[v4i32] } 3651:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 2:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRWU32_rq:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 35081 | /* 97572 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq), |
| 35082 | /* 97575 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 35083 | /* 97577 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 35084 | /* 97579 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 35085 | /* 97581 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 35086 | /* 97585 */ GIR_RootConstrainSelectedInstOperands, |
| 35087 | /* 97586 */ // GIR_Coverage, 4996, |
| 35088 | /* 97586 */ GIR_EraseRootFromParent_Done, |
| 35089 | /* 97587 */ // Label 1774: @97587 |
| 35090 | /* 97587 */ GIM_Try, /*On fail goto*//*Label 1775*/ GIMT_Encode4(97655), // Rule ID 4999 // |
| 35091 | /* 97592 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 35092 | /* 97597 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 35093 | /* 97600 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 35094 | /* 97603 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 35095 | /* 97606 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 35096 | /* 97609 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 35097 | /* 97612 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 35098 | /* 97616 */ // MIs[0] base |
| 35099 | /* 97616 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 35100 | /* 97620 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 35101 | /* 97624 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 35102 | /* 97628 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 32, |
| 35103 | /* 97632 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 35104 | /* 97636 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 35105 | /* 97640 */ // (intrinsic_w_chain:{ *:[v4i32] } 3651:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRWU32_rq_u:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 35106 | /* 97640 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq_u), |
| 35107 | /* 97643 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 35108 | /* 97645 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 35109 | /* 97647 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 35110 | /* 97649 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 35111 | /* 97653 */ GIR_RootConstrainSelectedInstOperands, |
| 35112 | /* 97654 */ // GIR_Coverage, 4999, |
| 35113 | /* 97654 */ GIR_EraseRootFromParent_Done, |
| 35114 | /* 97655 */ // Label 1775: @97655 |
| 35115 | /* 97655 */ GIM_Try, /*On fail goto*//*Label 1776*/ GIMT_Encode4(97723), // Rule ID 5000 // |
| 35116 | /* 97660 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 35117 | /* 97665 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 35118 | /* 97668 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 35119 | /* 97671 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 35120 | /* 97674 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 35121 | /* 97677 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 35122 | /* 97680 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 35123 | /* 97684 */ // MIs[0] base |
| 35124 | /* 97684 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 35125 | /* 97688 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 35126 | /* 97692 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 35127 | /* 97696 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 32, |
| 35128 | /* 97700 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 2, |
| 35129 | /* 97704 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 35130 | /* 97708 */ // (intrinsic_w_chain:{ *:[v4i32] } 3651:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 2:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRWU32_rq:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 35131 | /* 97708 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq), |
| 35132 | /* 97711 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 35133 | /* 97713 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 35134 | /* 97715 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 35135 | /* 97717 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 35136 | /* 97721 */ GIR_RootConstrainSelectedInstOperands, |
| 35137 | /* 97722 */ // GIR_Coverage, 5000, |
| 35138 | /* 97722 */ GIR_EraseRootFromParent_Done, |
| 35139 | /* 97723 */ // Label 1776: @97723 |
| 35140 | /* 97723 */ GIM_Try, /*On fail goto*//*Label 1777*/ GIMT_Encode4(97791), // Rule ID 5003 // |
| 35141 | /* 97728 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 35142 | /* 97733 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 35143 | /* 97736 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 35144 | /* 97739 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 35145 | /* 97742 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 35146 | /* 97745 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 35147 | /* 97748 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 35148 | /* 97752 */ // MIs[0] base |
| 35149 | /* 97752 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 35150 | /* 97756 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 35151 | /* 97760 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 35152 | /* 97764 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 32, |
| 35153 | /* 97768 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 35154 | /* 97772 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 35155 | /* 97776 */ // (intrinsic_w_chain:{ *:[v4f32] } 3651:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRWU32_rq_u:{ *:[v4f32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 35156 | /* 97776 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq_u), |
| 35157 | /* 97779 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 35158 | /* 97781 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 35159 | /* 97783 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 35160 | /* 97785 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 35161 | /* 97789 */ GIR_RootConstrainSelectedInstOperands, |
| 35162 | /* 97790 */ // GIR_Coverage, 5003, |
| 35163 | /* 97790 */ GIR_EraseRootFromParent_Done, |
| 35164 | /* 97791 */ // Label 1777: @97791 |
| 35165 | /* 97791 */ GIM_Try, /*On fail goto*//*Label 1778*/ GIMT_Encode4(97859), // Rule ID 5004 // |
| 35166 | /* 97796 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 35167 | /* 97801 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 35168 | /* 97804 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 35169 | /* 97807 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 35170 | /* 97810 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 35171 | /* 97813 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 35172 | /* 97816 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 35173 | /* 97820 */ // MIs[0] base |
| 35174 | /* 97820 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 35175 | /* 97824 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 35176 | /* 97828 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 35177 | /* 97832 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 32, |
| 35178 | /* 97836 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 2, |
| 35179 | /* 97840 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 35180 | /* 97844 */ // (intrinsic_w_chain:{ *:[v4f32] } 3651:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 2:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRWU32_rq:{ *:[v4f32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 35181 | /* 97844 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq), |
| 35182 | /* 97847 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 35183 | /* 97849 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 35184 | /* 97851 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 35185 | /* 97853 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 35186 | /* 97857 */ GIR_RootConstrainSelectedInstOperands, |
| 35187 | /* 97858 */ // GIR_Coverage, 5004, |
| 35188 | /* 97858 */ GIR_EraseRootFromParent_Done, |
| 35189 | /* 97859 */ // Label 1778: @97859 |
| 35190 | /* 97859 */ GIM_Try, /*On fail goto*//*Label 1779*/ GIMT_Encode4(97927), // Rule ID 5007 // |
| 35191 | /* 97864 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 35192 | /* 97869 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 35193 | /* 97872 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 35194 | /* 97875 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 35195 | /* 97878 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 35196 | /* 97881 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 35197 | /* 97884 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 35198 | /* 97888 */ // MIs[0] base |
| 35199 | /* 97888 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 35200 | /* 97892 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 35201 | /* 97896 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 35202 | /* 97900 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 32, |
| 35203 | /* 97904 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 35204 | /* 97908 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 35205 | /* 97912 */ // (intrinsic_w_chain:{ *:[v4f32] } 3651:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRWU32_rq_u:{ *:[v4f32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 35206 | /* 97912 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq_u), |
| 35207 | /* 97915 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 35208 | /* 97917 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 35209 | /* 97919 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 35210 | /* 97921 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 35211 | /* 97925 */ GIR_RootConstrainSelectedInstOperands, |
| 35212 | /* 97926 */ // GIR_Coverage, 5007, |
| 35213 | /* 97926 */ GIR_EraseRootFromParent_Done, |
| 35214 | /* 97927 */ // Label 1779: @97927 |
| 35215 | /* 97927 */ GIM_Try, /*On fail goto*//*Label 1780*/ GIMT_Encode4(97995), // Rule ID 5008 // |
| 35216 | /* 97932 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 35217 | /* 97937 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 35218 | /* 97940 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 35219 | /* 97943 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 35220 | /* 97946 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 35221 | /* 97949 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 35222 | /* 97952 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 35223 | /* 97956 */ // MIs[0] base |
| 35224 | /* 97956 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 35225 | /* 97960 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 35226 | /* 97964 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 35227 | /* 97968 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 32, |
| 35228 | /* 97972 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 2, |
| 35229 | /* 97976 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 35230 | /* 97980 */ // (intrinsic_w_chain:{ *:[v4f32] } 3651:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 2:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRWU32_rq:{ *:[v4f32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 35231 | /* 97980 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq), |
| 35232 | /* 97983 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 35233 | /* 97985 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 35234 | /* 97987 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 35235 | /* 97989 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 35236 | /* 97993 */ GIR_RootConstrainSelectedInstOperands, |
| 35237 | /* 97994 */ // GIR_Coverage, 5008, |
| 35238 | /* 97994 */ GIR_EraseRootFromParent_Done, |
| 35239 | /* 97995 */ // Label 1780: @97995 |
| 35240 | /* 97995 */ GIM_Try, /*On fail goto*//*Label 1781*/ GIMT_Encode4(98063), // Rule ID 5011 // |
| 35241 | /* 98000 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 35242 | /* 98005 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 35243 | /* 98008 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 35244 | /* 98011 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 35245 | /* 98014 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 35246 | /* 98017 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 35247 | /* 98020 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 35248 | /* 98024 */ // MIs[0] base |
| 35249 | /* 98024 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 35250 | /* 98028 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 35251 | /* 98032 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 35252 | /* 98036 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 64, |
| 35253 | /* 98040 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 35254 | /* 98044 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 35255 | /* 98048 */ // (intrinsic_w_chain:{ *:[v2i64] } 3651:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, 64:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRDU64_rq_u:{ *:[v2i64] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets) |
| 35256 | /* 98048 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRDU64_rq_u), |
| 35257 | /* 98051 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 35258 | /* 98053 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 35259 | /* 98055 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 35260 | /* 98057 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 35261 | /* 98061 */ GIR_RootConstrainSelectedInstOperands, |
| 35262 | /* 98062 */ // GIR_Coverage, 5011, |
| 35263 | /* 98062 */ GIR_EraseRootFromParent_Done, |
| 35264 | /* 98063 */ // Label 1781: @98063 |
| 35265 | /* 98063 */ GIM_Try, /*On fail goto*//*Label 1782*/ GIMT_Encode4(98131), // Rule ID 5012 // |
| 35266 | /* 98068 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 35267 | /* 98073 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 35268 | /* 98076 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 35269 | /* 98079 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 35270 | /* 98082 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 35271 | /* 98085 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 35272 | /* 98088 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 35273 | /* 98092 */ // MIs[0] base |
| 35274 | /* 98092 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 35275 | /* 98096 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 35276 | /* 98100 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 35277 | /* 98104 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 64, |
| 35278 | /* 98108 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 3, |
| 35279 | /* 98112 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 35280 | /* 98116 */ // (intrinsic_w_chain:{ *:[v2i64] } 3651:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, 64:{ *:[i32] }, 3:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRDU64_rq:{ *:[v2i64] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets) |
| 35281 | /* 98116 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRDU64_rq), |
| 35282 | /* 98119 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 35283 | /* 98121 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 35284 | /* 98123 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 35285 | /* 98125 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 35286 | /* 98129 */ GIR_RootConstrainSelectedInstOperands, |
| 35287 | /* 98130 */ // GIR_Coverage, 5012, |
| 35288 | /* 98130 */ GIR_EraseRootFromParent_Done, |
| 35289 | /* 98131 */ // Label 1782: @98131 |
| 35290 | /* 98131 */ GIM_Try, /*On fail goto*//*Label 1783*/ GIMT_Encode4(98199), // Rule ID 5015 // |
| 35291 | /* 98136 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 35292 | /* 98141 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 35293 | /* 98144 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 35294 | /* 98147 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 35295 | /* 98150 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 35296 | /* 98153 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 35297 | /* 98156 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 35298 | /* 98160 */ // MIs[0] base |
| 35299 | /* 98160 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 35300 | /* 98164 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 35301 | /* 98168 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 35302 | /* 98172 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 64, |
| 35303 | /* 98176 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 35304 | /* 98180 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 35305 | /* 98184 */ // (intrinsic_w_chain:{ *:[v2i64] } 3651:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, 64:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRDU64_rq_u:{ *:[v2i64] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets) |
| 35306 | /* 98184 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRDU64_rq_u), |
| 35307 | /* 98187 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 35308 | /* 98189 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 35309 | /* 98191 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 35310 | /* 98193 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 35311 | /* 98197 */ GIR_RootConstrainSelectedInstOperands, |
| 35312 | /* 98198 */ // GIR_Coverage, 5015, |
| 35313 | /* 98198 */ GIR_EraseRootFromParent_Done, |
| 35314 | /* 98199 */ // Label 1783: @98199 |
| 35315 | /* 98199 */ GIM_Try, /*On fail goto*//*Label 1784*/ GIMT_Encode4(98267), // Rule ID 5016 // |
| 35316 | /* 98204 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 35317 | /* 98209 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 35318 | /* 98212 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 35319 | /* 98215 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 35320 | /* 98218 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 35321 | /* 98221 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 35322 | /* 98224 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 35323 | /* 98228 */ // MIs[0] base |
| 35324 | /* 98228 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 35325 | /* 98232 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 35326 | /* 98236 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 35327 | /* 98240 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 64, |
| 35328 | /* 98244 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 3, |
| 35329 | /* 98248 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 35330 | /* 98252 */ // (intrinsic_w_chain:{ *:[v2i64] } 3651:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, 64:{ *:[i32] }, 3:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRDU64_rq:{ *:[v2i64] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets) |
| 35331 | /* 98252 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRDU64_rq), |
| 35332 | /* 98255 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 35333 | /* 98257 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 35334 | /* 98259 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 35335 | /* 98261 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 35336 | /* 98265 */ GIR_RootConstrainSelectedInstOperands, |
| 35337 | /* 98266 */ // GIR_Coverage, 5016, |
| 35338 | /* 98266 */ GIR_EraseRootFromParent_Done, |
| 35339 | /* 98267 */ // Label 1784: @98267 |
| 35340 | /* 98267 */ GIM_Try, /*On fail goto*//*Label 1785*/ GIMT_Encode4(98335), // Rule ID 5019 // |
| 35341 | /* 98272 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 35342 | /* 98277 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 35343 | /* 98280 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 35344 | /* 98283 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 35345 | /* 98286 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 35346 | /* 98289 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 35347 | /* 98292 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 35348 | /* 98296 */ // MIs[0] base |
| 35349 | /* 98296 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 35350 | /* 98300 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 35351 | /* 98304 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 35352 | /* 98308 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 64, |
| 35353 | /* 98312 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 35354 | /* 98316 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 35355 | /* 98320 */ // (intrinsic_w_chain:{ *:[v2i64] } 3651:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, 64:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRDU64_rq_u:{ *:[v2i64] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets) |
| 35356 | /* 98320 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRDU64_rq_u), |
| 35357 | /* 98323 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 35358 | /* 98325 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 35359 | /* 98327 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 35360 | /* 98329 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 35361 | /* 98333 */ GIR_RootConstrainSelectedInstOperands, |
| 35362 | /* 98334 */ // GIR_Coverage, 5019, |
| 35363 | /* 98334 */ GIR_EraseRootFromParent_Done, |
| 35364 | /* 98335 */ // Label 1785: @98335 |
| 35365 | /* 98335 */ GIM_Try, /*On fail goto*//*Label 1786*/ GIMT_Encode4(98403), // Rule ID 5020 // |
| 35366 | /* 98340 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 35367 | /* 98345 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 35368 | /* 98348 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 35369 | /* 98351 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 35370 | /* 98354 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 35371 | /* 98357 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 35372 | /* 98360 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 35373 | /* 98364 */ // MIs[0] base |
| 35374 | /* 98364 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 35375 | /* 98368 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 35376 | /* 98372 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 35377 | /* 98376 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 64, |
| 35378 | /* 98380 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 3, |
| 35379 | /* 98384 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 35380 | /* 98388 */ // (intrinsic_w_chain:{ *:[v2i64] } 3651:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, 64:{ *:[i32] }, 3:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRDU64_rq:{ *:[v2i64] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets) |
| 35381 | /* 98388 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRDU64_rq), |
| 35382 | /* 98391 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 35383 | /* 98393 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 35384 | /* 98395 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 35385 | /* 98397 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 35386 | /* 98401 */ GIR_RootConstrainSelectedInstOperands, |
| 35387 | /* 98402 */ // GIR_Coverage, 5020, |
| 35388 | /* 98402 */ GIR_EraseRootFromParent_Done, |
| 35389 | /* 98403 */ // Label 1786: @98403 |
| 35390 | /* 98403 */ GIM_Try, /*On fail goto*//*Label 1787*/ GIMT_Encode4(98471), // Rule ID 5023 // |
| 35391 | /* 98408 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 35392 | /* 98413 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 35393 | /* 98416 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 35394 | /* 98419 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 35395 | /* 98422 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 35396 | /* 98425 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 35397 | /* 98428 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 35398 | /* 98432 */ // MIs[0] base |
| 35399 | /* 98432 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 35400 | /* 98436 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 35401 | /* 98440 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 35402 | /* 98444 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 64, |
| 35403 | /* 98448 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 35404 | /* 98452 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 35405 | /* 98456 */ // (intrinsic_w_chain:{ *:[v2i64] } 3651:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, 64:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRDU64_rq_u:{ *:[v2i64] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets) |
| 35406 | /* 98456 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRDU64_rq_u), |
| 35407 | /* 98459 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 35408 | /* 98461 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 35409 | /* 98463 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 35410 | /* 98465 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 35411 | /* 98469 */ GIR_RootConstrainSelectedInstOperands, |
| 35412 | /* 98470 */ // GIR_Coverage, 5023, |
| 35413 | /* 98470 */ GIR_EraseRootFromParent_Done, |
| 35414 | /* 98471 */ // Label 1787: @98471 |
| 35415 | /* 98471 */ GIM_Try, /*On fail goto*//*Label 1788*/ GIMT_Encode4(98539), // Rule ID 5024 // |
| 35416 | /* 98476 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 35417 | /* 98481 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 35418 | /* 98484 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 35419 | /* 98487 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 35420 | /* 98490 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 35421 | /* 98493 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 35422 | /* 98496 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 35423 | /* 98500 */ // MIs[0] base |
| 35424 | /* 98500 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 35425 | /* 98504 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 35426 | /* 98508 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 35427 | /* 98512 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 64, |
| 35428 | /* 98516 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 3, |
| 35429 | /* 98520 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 35430 | /* 98524 */ // (intrinsic_w_chain:{ *:[v2i64] } 3651:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, 64:{ *:[i32] }, 3:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRDU64_rq:{ *:[v2i64] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets) |
| 35431 | /* 98524 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRDU64_rq), |
| 35432 | /* 98527 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 35433 | /* 98529 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 35434 | /* 98531 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 35435 | /* 98533 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 35436 | /* 98537 */ GIR_RootConstrainSelectedInstOperands, |
| 35437 | /* 98538 */ // GIR_Coverage, 5024, |
| 35438 | /* 98538 */ GIR_EraseRootFromParent_Done, |
| 35439 | /* 98539 */ // Label 1788: @98539 |
| 35440 | /* 98539 */ GIM_Try, /*On fail goto*//*Label 1789*/ GIMT_Encode4(98604), // Rule ID 256 // |
| 35441 | /* 98544 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 35442 | /* 98547 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mcr), |
| 35443 | /* 98552 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 35444 | /* 98555 */ // MIs[0] cop |
| 35445 | /* 98555 */ GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 35446 | /* 98558 */ // MIs[0] opc1 |
| 35447 | /* 98558 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2, |
| 35448 | /* 98561 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 35449 | /* 98565 */ // MIs[0] CRn |
| 35450 | /* 98565 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4, |
| 35451 | /* 98568 */ // MIs[0] CRm |
| 35452 | /* 98568 */ GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 35453 | /* 98571 */ // MIs[0] opc2 |
| 35454 | /* 98571 */ GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 35455 | /* 98574 */ // (intrinsic_void 3526:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) => (MCR (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) |
| 35456 | /* 98574 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MCR), |
| 35457 | /* 98577 */ GIR_RootToRootCopy, /*OpIdx*/1, // cop |
| 35458 | /* 98579 */ GIR_RootToRootCopy, /*OpIdx*/2, // opc1 |
| 35459 | /* 98581 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rt |
| 35460 | /* 98583 */ GIR_RootToRootCopy, /*OpIdx*/4, // CRn |
| 35461 | /* 98585 */ GIR_RootToRootCopy, /*OpIdx*/5, // CRm |
| 35462 | /* 98587 */ GIR_RootToRootCopy, /*OpIdx*/6, // opc2 |
| 35463 | /* 98589 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35464 | /* 98592 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35465 | /* 98598 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 35466 | /* 98602 */ GIR_RootConstrainSelectedInstOperands, |
| 35467 | /* 98603 */ // GIR_Coverage, 256, |
| 35468 | /* 98603 */ GIR_EraseRootFromParent_Done, |
| 35469 | /* 98604 */ // Label 1789: @98604 |
| 35470 | /* 98604 */ GIM_Try, /*On fail goto*//*Label 1790*/ GIMT_Encode4(98660), // Rule ID 257 // |
| 35471 | /* 98609 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM_PreV8), |
| 35472 | /* 98612 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mcr2), |
| 35473 | /* 98617 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 35474 | /* 98620 */ // MIs[0] cop |
| 35475 | /* 98620 */ GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 35476 | /* 98623 */ // MIs[0] opc1 |
| 35477 | /* 98623 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2, |
| 35478 | /* 98626 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 35479 | /* 98630 */ // MIs[0] CRn |
| 35480 | /* 98630 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4, |
| 35481 | /* 98633 */ // MIs[0] CRm |
| 35482 | /* 98633 */ GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 35483 | /* 98636 */ // MIs[0] opc2 |
| 35484 | /* 98636 */ GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 35485 | /* 98639 */ // (intrinsic_void 3527:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) => (MCR2 (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) |
| 35486 | /* 98639 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MCR2), |
| 35487 | /* 98642 */ GIR_RootToRootCopy, /*OpIdx*/1, // cop |
| 35488 | /* 98644 */ GIR_RootToRootCopy, /*OpIdx*/2, // opc1 |
| 35489 | /* 98646 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rt |
| 35490 | /* 98648 */ GIR_RootToRootCopy, /*OpIdx*/4, // CRn |
| 35491 | /* 98650 */ GIR_RootToRootCopy, /*OpIdx*/5, // CRm |
| 35492 | /* 98652 */ GIR_RootToRootCopy, /*OpIdx*/6, // opc2 |
| 35493 | /* 98654 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 35494 | /* 98658 */ GIR_RootConstrainSelectedInstOperands, |
| 35495 | /* 98659 */ // GIR_Coverage, 257, |
| 35496 | /* 98659 */ GIR_EraseRootFromParent_Done, |
| 35497 | /* 98660 */ // Label 1790: @98660 |
| 35498 | /* 98660 */ GIM_Try, /*On fail goto*//*Label 1791*/ GIMT_Encode4(98725), // Rule ID 594 // |
| 35499 | /* 98665 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 35500 | /* 98668 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mcr), |
| 35501 | /* 98673 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 35502 | /* 98676 */ // MIs[0] cop |
| 35503 | /* 98676 */ GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 35504 | /* 98679 */ // MIs[0] opc1 |
| 35505 | /* 98679 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2, |
| 35506 | /* 98682 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 35507 | /* 98686 */ // MIs[0] CRn |
| 35508 | /* 98686 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4, |
| 35509 | /* 98689 */ // MIs[0] CRm |
| 35510 | /* 98689 */ GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 35511 | /* 98692 */ // MIs[0] opc2 |
| 35512 | /* 98692 */ GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 35513 | /* 98695 */ // (intrinsic_void 3526:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) => (t2MCR (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) |
| 35514 | /* 98695 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MCR), |
| 35515 | /* 98698 */ GIR_RootToRootCopy, /*OpIdx*/1, // cop |
| 35516 | /* 98700 */ GIR_RootToRootCopy, /*OpIdx*/2, // opc1 |
| 35517 | /* 98702 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rt |
| 35518 | /* 98704 */ GIR_RootToRootCopy, /*OpIdx*/4, // CRn |
| 35519 | /* 98706 */ GIR_RootToRootCopy, /*OpIdx*/5, // CRm |
| 35520 | /* 98708 */ GIR_RootToRootCopy, /*OpIdx*/6, // opc2 |
| 35521 | /* 98710 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35522 | /* 98713 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35523 | /* 98719 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 35524 | /* 98723 */ GIR_RootConstrainSelectedInstOperands, |
| 35525 | /* 98724 */ // GIR_Coverage, 594, |
| 35526 | /* 98724 */ GIR_EraseRootFromParent_Done, |
| 35527 | /* 98725 */ // Label 1791: @98725 |
| 35528 | /* 98725 */ GIM_Try, /*On fail goto*//*Label 1792*/ GIMT_Encode4(98790), // Rule ID 595 // |
| 35529 | /* 98730 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2_PreV8), |
| 35530 | /* 98733 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mcr2), |
| 35531 | /* 98738 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 35532 | /* 98741 */ // MIs[0] cop |
| 35533 | /* 98741 */ GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 35534 | /* 98744 */ // MIs[0] opc1 |
| 35535 | /* 98744 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2, |
| 35536 | /* 98747 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 35537 | /* 98751 */ // MIs[0] CRn |
| 35538 | /* 98751 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4, |
| 35539 | /* 98754 */ // MIs[0] CRm |
| 35540 | /* 98754 */ GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 35541 | /* 98757 */ // MIs[0] opc2 |
| 35542 | /* 98757 */ GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 35543 | /* 98760 */ // (intrinsic_void 3527:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) => (t2MCR2 (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) |
| 35544 | /* 98760 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MCR2), |
| 35545 | /* 98763 */ GIR_RootToRootCopy, /*OpIdx*/1, // cop |
| 35546 | /* 98765 */ GIR_RootToRootCopy, /*OpIdx*/2, // opc1 |
| 35547 | /* 98767 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rt |
| 35548 | /* 98769 */ GIR_RootToRootCopy, /*OpIdx*/4, // CRn |
| 35549 | /* 98771 */ GIR_RootToRootCopy, /*OpIdx*/5, // CRm |
| 35550 | /* 98773 */ GIR_RootToRootCopy, /*OpIdx*/6, // opc2 |
| 35551 | /* 98775 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35552 | /* 98778 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35553 | /* 98784 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 35554 | /* 98788 */ GIR_RootConstrainSelectedInstOperands, |
| 35555 | /* 98789 */ // GIR_Coverage, 595, |
| 35556 | /* 98789 */ GIR_EraseRootFromParent_Done, |
| 35557 | /* 98790 */ // Label 1792: @98790 |
| 35558 | /* 98790 */ GIM_Reject, |
| 35559 | /* 98791 */ // Label 1742: @98791 |
| 35560 | /* 98791 */ GIM_Reject, |
| 35561 | /* 98792 */ // Label 17: @98792 |
| 35562 | /* 98792 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(5), GIMT_Encode2(13), /*)*//*default:*//*Label 1796*/ GIMT_Encode4(98949), |
| 35563 | /* 98803 */ /*GILLT_v2s64*//*Label 1793*/ GIMT_Encode4(98835), GIMT_Encode4(0), GIMT_Encode4(0), |
| 35564 | /* 98815 */ /*GILLT_v4s32*//*Label 1794*/ GIMT_Encode4(98873), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 35565 | /* 98831 */ /*GILLT_v8s16*//*Label 1795*/ GIMT_Encode4(98911), |
| 35566 | /* 98835 */ // Label 1793: @98835 |
| 35567 | /* 98835 */ GIM_Try, /*On fail goto*//*Label 1797*/ GIMT_Encode4(98872), // Rule ID 2668 // |
| 35568 | /* 98840 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 35569 | /* 98843 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 35570 | /* 98846 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 35571 | /* 98850 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 35572 | /* 98854 */ // (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm) => (VMOVLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm) |
| 35573 | /* 98854 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVLuv2i64), |
| 35574 | /* 98857 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 35575 | /* 98859 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 35576 | /* 98861 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35577 | /* 98864 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35578 | /* 98870 */ GIR_RootConstrainSelectedInstOperands, |
| 35579 | /* 98871 */ // GIR_Coverage, 2668, |
| 35580 | /* 98871 */ GIR_EraseRootFromParent_Done, |
| 35581 | /* 98872 */ // Label 1797: @98872 |
| 35582 | /* 98872 */ GIM_Reject, |
| 35583 | /* 98873 */ // Label 1794: @98873 |
| 35584 | /* 98873 */ GIM_Try, /*On fail goto*//*Label 1798*/ GIMT_Encode4(98910), // Rule ID 2667 // |
| 35585 | /* 98878 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 35586 | /* 98881 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 35587 | /* 98884 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 35588 | /* 98888 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 35589 | /* 98892 */ // (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm) => (VMOVLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm) |
| 35590 | /* 98892 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVLuv4i32), |
| 35591 | /* 98895 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 35592 | /* 98897 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 35593 | /* 98899 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35594 | /* 98902 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35595 | /* 98908 */ GIR_RootConstrainSelectedInstOperands, |
| 35596 | /* 98909 */ // GIR_Coverage, 2667, |
| 35597 | /* 98909 */ GIR_EraseRootFromParent_Done, |
| 35598 | /* 98910 */ // Label 1798: @98910 |
| 35599 | /* 98910 */ GIM_Reject, |
| 35600 | /* 98911 */ // Label 1795: @98911 |
| 35601 | /* 98911 */ GIM_Try, /*On fail goto*//*Label 1799*/ GIMT_Encode4(98948), // Rule ID 2666 // |
| 35602 | /* 98916 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 35603 | /* 98919 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 35604 | /* 98922 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 35605 | /* 98926 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 35606 | /* 98930 */ // (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm) => (VMOVLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm) |
| 35607 | /* 98930 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVLuv8i16), |
| 35608 | /* 98933 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 35609 | /* 98935 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 35610 | /* 98937 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35611 | /* 98940 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35612 | /* 98946 */ GIR_RootConstrainSelectedInstOperands, |
| 35613 | /* 98947 */ // GIR_Coverage, 2666, |
| 35614 | /* 98947 */ GIR_EraseRootFromParent_Done, |
| 35615 | /* 98948 */ // Label 1799: @98948 |
| 35616 | /* 98948 */ GIM_Reject, |
| 35617 | /* 98949 */ // Label 1796: @98949 |
| 35618 | /* 98949 */ GIM_Reject, |
| 35619 | /* 98950 */ // Label 18: @98950 |
| 35620 | /* 98950 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(12), /*)*//*default:*//*Label 1803*/ GIMT_Encode4(99107), |
| 35621 | /* 98961 */ /*GILLT_v2s32*//*Label 1800*/ GIMT_Encode4(98993), GIMT_Encode4(0), GIMT_Encode4(0), |
| 35622 | /* 98973 */ /*GILLT_v4s16*//*Label 1801*/ GIMT_Encode4(99031), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 35623 | /* 98989 */ /*GILLT_v8s8*//*Label 1802*/ GIMT_Encode4(99069), |
| 35624 | /* 98993 */ // Label 1800: @98993 |
| 35625 | /* 98993 */ GIM_Try, /*On fail goto*//*Label 1804*/ GIMT_Encode4(99030), // Rule ID 1588 // |
| 35626 | /* 98998 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 35627 | /* 99001 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 35628 | /* 99004 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 35629 | /* 99008 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 35630 | /* 99012 */ // (trunc:{ *:[v2i32] } QPR:{ *:[v2i64] }:$Vm) => (VMOVNv2i32:{ *:[v2i32] } QPR:{ *:[v2i64] }:$Vm) |
| 35631 | /* 99012 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVNv2i32), |
| 35632 | /* 99015 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 35633 | /* 99017 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 35634 | /* 99019 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35635 | /* 99022 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35636 | /* 99028 */ GIR_RootConstrainSelectedInstOperands, |
| 35637 | /* 99029 */ // GIR_Coverage, 1588, |
| 35638 | /* 99029 */ GIR_EraseRootFromParent_Done, |
| 35639 | /* 99030 */ // Label 1804: @99030 |
| 35640 | /* 99030 */ GIM_Reject, |
| 35641 | /* 99031 */ // Label 1801: @99031 |
| 35642 | /* 99031 */ GIM_Try, /*On fail goto*//*Label 1805*/ GIMT_Encode4(99068), // Rule ID 1587 // |
| 35643 | /* 99036 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 35644 | /* 99039 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 35645 | /* 99042 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 35646 | /* 99046 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 35647 | /* 99050 */ // (trunc:{ *:[v4i16] } QPR:{ *:[v4i32] }:$Vm) => (VMOVNv4i16:{ *:[v4i16] } QPR:{ *:[v4i32] }:$Vm) |
| 35648 | /* 99050 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVNv4i16), |
| 35649 | /* 99053 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 35650 | /* 99055 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 35651 | /* 99057 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35652 | /* 99060 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35653 | /* 99066 */ GIR_RootConstrainSelectedInstOperands, |
| 35654 | /* 99067 */ // GIR_Coverage, 1587, |
| 35655 | /* 99067 */ GIR_EraseRootFromParent_Done, |
| 35656 | /* 99068 */ // Label 1805: @99068 |
| 35657 | /* 99068 */ GIM_Reject, |
| 35658 | /* 99069 */ // Label 1802: @99069 |
| 35659 | /* 99069 */ GIM_Try, /*On fail goto*//*Label 1806*/ GIMT_Encode4(99106), // Rule ID 1586 // |
| 35660 | /* 99074 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 35661 | /* 99077 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 35662 | /* 99080 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 35663 | /* 99084 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 35664 | /* 99088 */ // (trunc:{ *:[v8i8] } QPR:{ *:[v8i16] }:$Vm) => (VMOVNv8i8:{ *:[v8i8] } QPR:{ *:[v8i16] }:$Vm) |
| 35665 | /* 99088 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVNv8i8), |
| 35666 | /* 99091 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 35667 | /* 99093 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 35668 | /* 99095 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35669 | /* 99098 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35670 | /* 99104 */ GIR_RootConstrainSelectedInstOperands, |
| 35671 | /* 99105 */ // GIR_Coverage, 1586, |
| 35672 | /* 99105 */ GIR_EraseRootFromParent_Done, |
| 35673 | /* 99106 */ // Label 1806: @99106 |
| 35674 | /* 99106 */ GIM_Reject, |
| 35675 | /* 99107 */ // Label 1803: @99107 |
| 35676 | /* 99107 */ GIM_Reject, |
| 35677 | /* 99108 */ // Label 19: @99108 |
| 35678 | /* 99108 */ GIM_Try, /*On fail goto*//*Label 1807*/ GIMT_Encode4(99428), |
| 35679 | /* 99113 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 35680 | /* 99116 */ GIM_Try, /*On fail goto*//*Label 1808*/ GIMT_Encode4(99157), // Rule ID 404 // |
| 35681 | /* 99121 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 35682 | /* 99124 */ GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm), |
| 35683 | /* 99128 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 35684 | /* 99132 */ // MIs[0] Operand 1 |
| 35685 | /* 99132 */ // No operand predicates |
| 35686 | /* 99132 */ // (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm => (t2MOVi:{ *:[i32] } (imm:{ *:[i32] }):$imm) |
| 35687 | /* 99132 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MOVi), |
| 35688 | /* 99135 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 35689 | /* 99137 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm |
| 35690 | /* 99140 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35691 | /* 99143 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35692 | /* 99149 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35693 | /* 99155 */ GIR_RootConstrainSelectedInstOperands, |
| 35694 | /* 99156 */ // GIR_Coverage, 404, |
| 35695 | /* 99156 */ GIR_EraseRootFromParent_Done, |
| 35696 | /* 99157 */ // Label 1808: @99157 |
| 35697 | /* 99157 */ GIM_Try, /*On fail goto*//*Label 1809*/ GIMT_Encode4(99198), // Rule ID 57 // |
| 35698 | /* 99162 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 35699 | /* 99165 */ GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm), |
| 35700 | /* 99169 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 35701 | /* 99173 */ // MIs[0] Operand 1 |
| 35702 | /* 99173 */ // No operand predicates |
| 35703 | /* 99173 */ // (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm => (MOVi:{ *:[i32] } (imm:{ *:[i32] }):$imm) |
| 35704 | /* 99173 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MOVi), |
| 35705 | /* 99176 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 35706 | /* 99178 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm |
| 35707 | /* 99181 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35708 | /* 99184 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35709 | /* 99190 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35710 | /* 99196 */ GIR_RootConstrainSelectedInstOperands, |
| 35711 | /* 99197 */ // GIR_Coverage, 57, |
| 35712 | /* 99197 */ GIR_EraseRootFromParent_Done, |
| 35713 | /* 99198 */ // Label 1809: @99198 |
| 35714 | /* 99198 */ GIM_Try, /*On fail goto*//*Label 1810*/ GIMT_Encode4(99233), // Rule ID 58 // |
| 35715 | /* 99203 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6T2_IsARM), |
| 35716 | /* 99206 */ GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_65535), |
| 35717 | /* 99210 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 35718 | /* 99214 */ // MIs[0] Operand 1 |
| 35719 | /* 99214 */ // No operand predicates |
| 35720 | /* 99214 */ // (imm:{ *:[i32] })<<P:Predicate_imm0_65535>>:$imm => (MOVi16:{ *:[i32] } (imm:{ *:[i32] }):$imm) |
| 35721 | /* 99214 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MOVi16), |
| 35722 | /* 99217 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 35723 | /* 99219 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm |
| 35724 | /* 99222 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35725 | /* 99225 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35726 | /* 99231 */ GIR_RootConstrainSelectedInstOperands, |
| 35727 | /* 99232 */ // GIR_Coverage, 58, |
| 35728 | /* 99232 */ GIR_EraseRootFromParent_Done, |
| 35729 | /* 99233 */ // Label 1810: @99233 |
| 35730 | /* 99233 */ GIM_Try, /*On fail goto*//*Label 1811*/ GIMT_Encode4(99276), // Rule ID 168 // |
| 35731 | /* 99238 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 35732 | /* 99241 */ GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm_not), |
| 35733 | /* 99245 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 35734 | /* 99249 */ // MIs[0] Operand 1 |
| 35735 | /* 99249 */ // No operand predicates |
| 35736 | /* 99249 */ // (imm:{ *:[i32] })<<P:Predicate_mod_imm_not>><<X:imm_not_XFORM>>:$imm => (MVNi:{ *:[i32] } (imm_not_XFORM:{ *:[i32] } (imm:{ *:[i32] }):$imm)) |
| 35737 | /* 99249 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVNi), |
| 35738 | /* 99252 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 35739 | /* 99254 */ GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/0, /*Renderer*/GIMT_Encode2(GICR_renderInvertedImm), // imm |
| 35740 | /* 99259 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35741 | /* 99262 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35742 | /* 99268 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35743 | /* 99274 */ GIR_RootConstrainSelectedInstOperands, |
| 35744 | /* 99275 */ // GIR_Coverage, 168, |
| 35745 | /* 99275 */ GIR_EraseRootFromParent_Done, |
| 35746 | /* 99276 */ // Label 1811: @99276 |
| 35747 | /* 99276 */ GIM_Try, /*On fail goto*//*Label 1812*/ GIMT_Encode4(99302), // Rule ID 268 // |
| 35748 | /* 99281 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 35749 | /* 99284 */ GIM_CheckAPIntImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_APInt_Predicate_arm_i32imm), |
| 35750 | /* 99288 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 35751 | /* 99292 */ // MIs[0] Operand 1 |
| 35752 | /* 99292 */ // No operand predicates |
| 35753 | /* 99292 */ // (imm:{ *:[i32] })<<P:Predicate_arm_i32imm>>:$src => (MOVi32imm:{ *:[i32] } (imm:{ *:[i32] }):$src) |
| 35754 | /* 99292 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MOVi32imm), |
| 35755 | /* 99295 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 35756 | /* 99297 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // src |
| 35757 | /* 99300 */ GIR_RootConstrainSelectedInstOperands, |
| 35758 | /* 99301 */ // GIR_Coverage, 268, |
| 35759 | /* 99301 */ GIR_EraseRootFromParent_Done, |
| 35760 | /* 99302 */ // Label 1812: @99302 |
| 35761 | /* 99302 */ GIM_Try, /*On fail goto*//*Label 1813*/ GIMT_Encode4(99343), // Rule ID 322 // |
| 35762 | /* 99307 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), |
| 35763 | /* 99310 */ GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_255_expr), |
| 35764 | /* 99314 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 35765 | /* 99318 */ // MIs[0] Operand 1 |
| 35766 | /* 99318 */ // No operand predicates |
| 35767 | /* 99318 */ // (imm:{ *:[i32] })<<P:Predicate_imm0_255_expr>>:$imm8 => (tMOVi8:{ *:[i32] } (imm:{ *:[i32] }):$imm8) |
| 35768 | /* 99318 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tMOVi8), |
| 35769 | /* 99321 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 35770 | /* 99323 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define | RegState::Dead), |
| 35771 | /* 99329 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm8 |
| 35772 | /* 99332 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35773 | /* 99335 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35774 | /* 99341 */ GIR_RootConstrainSelectedInstOperands, |
| 35775 | /* 99342 */ // GIR_Coverage, 322, |
| 35776 | /* 99342 */ GIR_EraseRootFromParent_Done, |
| 35777 | /* 99343 */ // Label 1813: @99343 |
| 35778 | /* 99343 */ GIM_Try, /*On fail goto*//*Label 1814*/ GIMT_Encode4(99378), // Rule ID 405 // |
| 35779 | /* 99348 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV8MBaseline_IsThumb), |
| 35780 | /* 99351 */ GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_65535), |
| 35781 | /* 99355 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 35782 | /* 99359 */ // MIs[0] Operand 1 |
| 35783 | /* 99359 */ // No operand predicates |
| 35784 | /* 99359 */ // (imm:{ *:[i32] })<<P:Predicate_imm0_65535>>:$imm => (t2MOVi16:{ *:[i32] } (imm:{ *:[i32] }):$imm) |
| 35785 | /* 99359 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MOVi16), |
| 35786 | /* 99362 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 35787 | /* 99364 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm |
| 35788 | /* 99367 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35789 | /* 99370 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35790 | /* 99376 */ GIR_RootConstrainSelectedInstOperands, |
| 35791 | /* 99377 */ // GIR_Coverage, 405, |
| 35792 | /* 99377 */ GIR_EraseRootFromParent_Done, |
| 35793 | /* 99378 */ // Label 1814: @99378 |
| 35794 | /* 99378 */ GIM_Try, /*On fail goto*//*Label 1815*/ GIMT_Encode4(99427), |
| 35795 | /* 99383 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 35796 | /* 99387 */ GIM_Try, /*On fail goto*//*Label 1816*/ GIMT_Encode4(99408), // Rule ID 353 // |
| 35797 | /* 99392 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseMovt_GenExecuteOnly_IsThumb1Only), |
| 35798 | /* 99395 */ // MIs[0] Operand 1 |
| 35799 | /* 99395 */ // No operand predicates |
| 35800 | /* 99395 */ // (imm:{ *:[i32] }):$src => (tMOVi32imm:{ *:[i32] }:{ *:[i32] } (imm:{ *:[i32] }):$src) |
| 35801 | /* 99395 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tMOVi32imm), |
| 35802 | /* 99398 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 35803 | /* 99400 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // src |
| 35804 | /* 99403 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for ARM::CPSR*/0, |
| 35805 | /* 99406 */ GIR_RootConstrainSelectedInstOperands, |
| 35806 | /* 99407 */ // GIR_Coverage, 353, |
| 35807 | /* 99407 */ GIR_EraseRootFromParent_Done, |
| 35808 | /* 99408 */ // Label 1816: @99408 |
| 35809 | /* 99408 */ GIM_Try, /*On fail goto*//*Label 1817*/ GIMT_Encode4(99426), // Rule ID 582 // |
| 35810 | /* 99413 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb_UseMovt), |
| 35811 | /* 99416 */ // MIs[0] Operand 1 |
| 35812 | /* 99416 */ // No operand predicates |
| 35813 | /* 99416 */ // (imm:{ *:[i32] }):$src => (t2MOVi32imm:{ *:[i32] } (imm:{ *:[i32] }):$src) |
| 35814 | /* 99416 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MOVi32imm), |
| 35815 | /* 99419 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 35816 | /* 99421 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // src |
| 35817 | /* 99424 */ GIR_RootConstrainSelectedInstOperands, |
| 35818 | /* 99425 */ // GIR_Coverage, 582, |
| 35819 | /* 99425 */ GIR_EraseRootFromParent_Done, |
| 35820 | /* 99426 */ // Label 1817: @99426 |
| 35821 | /* 99426 */ GIM_Reject, |
| 35822 | /* 99427 */ // Label 1815: @99427 |
| 35823 | /* 99427 */ GIM_Reject, |
| 35824 | /* 99428 */ // Label 1807: @99428 |
| 35825 | /* 99428 */ GIM_Reject, |
| 35826 | /* 99429 */ // Label 20: @99429 |
| 35827 | /* 99429 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1820*/ GIMT_Encode4(99524), |
| 35828 | /* 99440 */ /*GILLT_s32*//*Label 1818*/ GIMT_Encode4(99448), |
| 35829 | /* 99444 */ /*GILLT_s64*//*Label 1819*/ GIMT_Encode4(99486), |
| 35830 | /* 99448 */ // Label 1818: @99448 |
| 35831 | /* 99448 */ GIM_Try, /*On fail goto*//*Label 1821*/ GIMT_Encode4(99485), // Rule ID 728 // |
| 35832 | /* 99453 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP3), |
| 35833 | /* 99456 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 35834 | /* 99460 */ // MIs[0] Operand 1 |
| 35835 | /* 99460 */ // No operand predicates |
| 35836 | /* 99460 */ GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_vfp_f32imm), |
| 35837 | /* 99464 */ // (fpimm:{ *:[f32] })<<P:Predicate_vfp_f32imm>><<X:vfp_f32imm_xform>>:$imm => (FCONSTS:{ *:[f32] } (vfp_f32imm_xform:{ *:[f32] } (fpimm:{ *:[f32] }):$imm)) |
| 35838 | /* 99464 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::FCONSTS), |
| 35839 | /* 99467 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 35840 | /* 99469 */ GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/0, /*Renderer*/GIMT_Encode2(GICR_renderVFPF32Imm), // imm |
| 35841 | /* 99474 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35842 | /* 99477 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35843 | /* 99483 */ GIR_RootConstrainSelectedInstOperands, |
| 35844 | /* 99484 */ // GIR_Coverage, 728, |
| 35845 | /* 99484 */ GIR_EraseRootFromParent_Done, |
| 35846 | /* 99485 */ // Label 1821: @99485 |
| 35847 | /* 99485 */ GIM_Reject, |
| 35848 | /* 99486 */ // Label 1819: @99486 |
| 35849 | /* 99486 */ GIM_Try, /*On fail goto*//*Label 1822*/ GIMT_Encode4(99523), // Rule ID 727 // |
| 35850 | /* 99491 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP3), |
| 35851 | /* 99494 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 35852 | /* 99498 */ // MIs[0] Operand 1 |
| 35853 | /* 99498 */ // No operand predicates |
| 35854 | /* 99498 */ GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_vfp_f64imm), |
| 35855 | /* 99502 */ // (fpimm:{ *:[f64] })<<P:Predicate_vfp_f64imm>><<X:vfp_f64imm_xform>>:$imm => (FCONSTD:{ *:[f64] } (vfp_f64imm_xform:{ *:[f64] } (fpimm:{ *:[f64] }):$imm)) |
| 35856 | /* 99502 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::FCONSTD), |
| 35857 | /* 99505 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 35858 | /* 99507 */ GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/0, /*Renderer*/GIMT_Encode2(GICR_renderVFPF64Imm), // imm |
| 35859 | /* 99512 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35860 | /* 99515 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35861 | /* 99521 */ GIR_RootConstrainSelectedInstOperands, |
| 35862 | /* 99522 */ // GIR_Coverage, 727, |
| 35863 | /* 99522 */ GIR_EraseRootFromParent_Done, |
| 35864 | /* 99523 */ // Label 1822: @99523 |
| 35865 | /* 99523 */ GIM_Reject, |
| 35866 | /* 99524 */ // Label 1820: @99524 |
| 35867 | /* 99524 */ GIM_Reject, |
| 35868 | /* 99525 */ // Label 21: @99525 |
| 35869 | /* 99525 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(5), GIMT_Encode2(13), /*)*//*default:*//*Label 1826*/ GIMT_Encode4(99682), |
| 35870 | /* 99536 */ /*GILLT_v2s64*//*Label 1823*/ GIMT_Encode4(99568), GIMT_Encode4(0), GIMT_Encode4(0), |
| 35871 | /* 99548 */ /*GILLT_v4s32*//*Label 1824*/ GIMT_Encode4(99606), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 35872 | /* 99564 */ /*GILLT_v8s16*//*Label 1825*/ GIMT_Encode4(99644), |
| 35873 | /* 99568 */ // Label 1823: @99568 |
| 35874 | /* 99568 */ GIM_Try, /*On fail goto*//*Label 1827*/ GIMT_Encode4(99605), // Rule ID 1600 // |
| 35875 | /* 99573 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 35876 | /* 99576 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 35877 | /* 99579 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 35878 | /* 99583 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 35879 | /* 99587 */ // (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm) => (VMOVLsv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm) |
| 35880 | /* 99587 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVLsv2i64), |
| 35881 | /* 99590 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 35882 | /* 99592 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 35883 | /* 99594 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35884 | /* 99597 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35885 | /* 99603 */ GIR_RootConstrainSelectedInstOperands, |
| 35886 | /* 99604 */ // GIR_Coverage, 1600, |
| 35887 | /* 99604 */ GIR_EraseRootFromParent_Done, |
| 35888 | /* 99605 */ // Label 1827: @99605 |
| 35889 | /* 99605 */ GIM_Reject, |
| 35890 | /* 99606 */ // Label 1824: @99606 |
| 35891 | /* 99606 */ GIM_Try, /*On fail goto*//*Label 1828*/ GIMT_Encode4(99643), // Rule ID 1599 // |
| 35892 | /* 99611 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 35893 | /* 99614 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 35894 | /* 99617 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 35895 | /* 99621 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 35896 | /* 99625 */ // (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm) => (VMOVLsv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm) |
| 35897 | /* 99625 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVLsv4i32), |
| 35898 | /* 99628 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 35899 | /* 99630 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 35900 | /* 99632 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35901 | /* 99635 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35902 | /* 99641 */ GIR_RootConstrainSelectedInstOperands, |
| 35903 | /* 99642 */ // GIR_Coverage, 1599, |
| 35904 | /* 99642 */ GIR_EraseRootFromParent_Done, |
| 35905 | /* 99643 */ // Label 1828: @99643 |
| 35906 | /* 99643 */ GIM_Reject, |
| 35907 | /* 99644 */ // Label 1825: @99644 |
| 35908 | /* 99644 */ GIM_Try, /*On fail goto*//*Label 1829*/ GIMT_Encode4(99681), // Rule ID 1598 // |
| 35909 | /* 99649 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 35910 | /* 99652 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 35911 | /* 99655 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 35912 | /* 99659 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 35913 | /* 99663 */ // (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm) => (VMOVLsv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm) |
| 35914 | /* 99663 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVLsv8i16), |
| 35915 | /* 99666 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 35916 | /* 99668 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 35917 | /* 99670 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35918 | /* 99673 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35919 | /* 99679 */ GIR_RootConstrainSelectedInstOperands, |
| 35920 | /* 99680 */ // GIR_Coverage, 1598, |
| 35921 | /* 99680 */ GIR_EraseRootFromParent_Done, |
| 35922 | /* 99681 */ // Label 1829: @99681 |
| 35923 | /* 99681 */ GIM_Reject, |
| 35924 | /* 99682 */ // Label 1826: @99682 |
| 35925 | /* 99682 */ GIM_Reject, |
| 35926 | /* 99683 */ // Label 22: @99683 |
| 35927 | /* 99683 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(13), /*)*//*default:*//*Label 1833*/ GIMT_Encode4(100287), |
| 35928 | /* 99694 */ /*GILLT_s32*//*Label 1830*/ GIMT_Encode4(99742), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 35929 | /* 99722 */ /*GILLT_v4s32*//*Label 1831*/ GIMT_Encode4(100034), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 35930 | /* 99738 */ /*GILLT_v8s16*//*Label 1832*/ GIMT_Encode4(100217), |
| 35931 | /* 99742 */ // Label 1830: @99742 |
| 35932 | /* 99742 */ GIM_Try, /*On fail goto*//*Label 1834*/ GIMT_Encode4(100033), |
| 35933 | /* 99747 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 35934 | /* 99750 */ GIM_Try, /*On fail goto*//*Label 1835*/ GIMT_Encode4(99795), // Rule ID 340 // |
| 35935 | /* 99755 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsThumb_IsThumb1Only), |
| 35936 | /* 99758 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 35937 | /* 99762 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 35938 | /* 99766 */ // MIs[0] Operand 2 |
| 35939 | /* 99766 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(8), |
| 35940 | /* 99777 */ // (sext_inreg:{ *:[i32] } tGPR:{ *:[i32] }:$Rm, i8:{ *:[Other] }) => (tSXTB:{ *:[i32] } tGPR:{ *:[i32] }:$Rm) |
| 35941 | /* 99777 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tSXTB), |
| 35942 | /* 99780 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 35943 | /* 99782 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 35944 | /* 99784 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35945 | /* 99787 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35946 | /* 99793 */ GIR_RootConstrainSelectedInstOperands, |
| 35947 | /* 99794 */ // GIR_Coverage, 340, |
| 35948 | /* 99794 */ GIR_EraseRootFromParent_Done, |
| 35949 | /* 99795 */ // Label 1835: @99795 |
| 35950 | /* 99795 */ GIM_Try, /*On fail goto*//*Label 1836*/ GIMT_Encode4(99840), // Rule ID 341 // |
| 35951 | /* 99800 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsThumb_IsThumb1Only), |
| 35952 | /* 99803 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 35953 | /* 99807 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 35954 | /* 99811 */ // MIs[0] Operand 2 |
| 35955 | /* 99811 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16), |
| 35956 | /* 99822 */ // (sext_inreg:{ *:[i32] } tGPR:{ *:[i32] }:$Rm, i16:{ *:[Other] }) => (tSXTH:{ *:[i32] } tGPR:{ *:[i32] }:$Rm) |
| 35957 | /* 99822 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tSXTH), |
| 35958 | /* 99825 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 35959 | /* 99827 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 35960 | /* 99829 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35961 | /* 99832 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35962 | /* 99838 */ GIR_RootConstrainSelectedInstOperands, |
| 35963 | /* 99839 */ // GIR_Coverage, 341, |
| 35964 | /* 99839 */ GIR_EraseRootFromParent_Done, |
| 35965 | /* 99840 */ // Label 1836: @99840 |
| 35966 | /* 99840 */ GIM_Try, /*On fail goto*//*Label 1837*/ GIMT_Encode4(99888), // Rule ID 2002 // |
| 35967 | /* 99845 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 35968 | /* 99848 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 35969 | /* 99852 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 35970 | /* 99856 */ // MIs[0] Operand 2 |
| 35971 | /* 99856 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(8), |
| 35972 | /* 99867 */ // (sext_inreg:{ *:[i32] } GPR:{ *:[i32] }:$Src, i8:{ *:[Other] }) => (SXTB:{ *:[i32] } GPR:{ *:[i32] }:$Src, 0:{ *:[i32] }) |
| 35973 | /* 99867 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SXTB), |
| 35974 | /* 99870 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 35975 | /* 99872 */ GIR_RootToRootCopy, /*OpIdx*/1, // Src |
| 35976 | /* 99874 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 35977 | /* 99877 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35978 | /* 99880 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35979 | /* 99886 */ GIR_RootConstrainSelectedInstOperands, |
| 35980 | /* 99887 */ // GIR_Coverage, 2002, |
| 35981 | /* 99887 */ GIR_EraseRootFromParent_Done, |
| 35982 | /* 99888 */ // Label 1837: @99888 |
| 35983 | /* 99888 */ GIM_Try, /*On fail goto*//*Label 1838*/ GIMT_Encode4(99936), // Rule ID 2003 // |
| 35984 | /* 99893 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 35985 | /* 99896 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 35986 | /* 99900 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 35987 | /* 99904 */ // MIs[0] Operand 2 |
| 35988 | /* 99904 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16), |
| 35989 | /* 99915 */ // (sext_inreg:{ *:[i32] } GPR:{ *:[i32] }:$Src, i16:{ *:[Other] }) => (SXTH:{ *:[i32] } GPR:{ *:[i32] }:$Src, 0:{ *:[i32] }) |
| 35990 | /* 99915 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SXTH), |
| 35991 | /* 99918 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 35992 | /* 99920 */ GIR_RootToRootCopy, /*OpIdx*/1, // Src |
| 35993 | /* 99922 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 35994 | /* 99925 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35995 | /* 99928 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35996 | /* 99934 */ GIR_RootConstrainSelectedInstOperands, |
| 35997 | /* 99935 */ // GIR_Coverage, 2003, |
| 35998 | /* 99935 */ GIR_EraseRootFromParent_Done, |
| 35999 | /* 99936 */ // Label 1838: @99936 |
| 36000 | /* 99936 */ GIM_Try, /*On fail goto*//*Label 1839*/ GIMT_Encode4(99984), // Rule ID 2241 // |
| 36001 | /* 99941 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 36002 | /* 99944 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36003 | /* 99948 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36004 | /* 99952 */ // MIs[0] Operand 2 |
| 36005 | /* 99952 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(8), |
| 36006 | /* 99963 */ // (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Src, i8:{ *:[Other] }) => (t2SXTB:{ *:[i32] } rGPR:{ *:[i32] }:$Src, 0:{ *:[i32] }) |
| 36007 | /* 99963 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SXTB), |
| 36008 | /* 99966 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 36009 | /* 99968 */ GIR_RootToRootCopy, /*OpIdx*/1, // Src |
| 36010 | /* 99970 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36011 | /* 99973 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36012 | /* 99976 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36013 | /* 99982 */ GIR_RootConstrainSelectedInstOperands, |
| 36014 | /* 99983 */ // GIR_Coverage, 2241, |
| 36015 | /* 99983 */ GIR_EraseRootFromParent_Done, |
| 36016 | /* 99984 */ // Label 1839: @99984 |
| 36017 | /* 99984 */ GIM_Try, /*On fail goto*//*Label 1840*/ GIMT_Encode4(100032), // Rule ID 2242 // |
| 36018 | /* 99989 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 36019 | /* 99992 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36020 | /* 99996 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36021 | /* 100000 */ // MIs[0] Operand 2 |
| 36022 | /* 100000 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16), |
| 36023 | /* 100011 */ // (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Src, i16:{ *:[Other] }) => (t2SXTH:{ *:[i32] } rGPR:{ *:[i32] }:$Src, 0:{ *:[i32] }) |
| 36024 | /* 100011 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SXTH), |
| 36025 | /* 100014 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 36026 | /* 100016 */ GIR_RootToRootCopy, /*OpIdx*/1, // Src |
| 36027 | /* 100018 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36028 | /* 100021 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36029 | /* 100024 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36030 | /* 100030 */ GIR_RootConstrainSelectedInstOperands, |
| 36031 | /* 100031 */ // GIR_Coverage, 2242, |
| 36032 | /* 100031 */ GIR_EraseRootFromParent_Done, |
| 36033 | /* 100032 */ // Label 1840: @100032 |
| 36034 | /* 100032 */ GIM_Reject, |
| 36035 | /* 100033 */ // Label 1834: @100033 |
| 36036 | /* 100033 */ GIM_Reject, |
| 36037 | /* 100034 */ // Label 1831: @100034 |
| 36038 | /* 100034 */ GIM_Try, /*On fail goto*//*Label 1841*/ GIMT_Encode4(100216), |
| 36039 | /* 100039 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 36040 | /* 100042 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36041 | /* 100046 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36042 | /* 100050 */ GIM_Try, /*On fail goto*//*Label 1842*/ GIMT_Encode4(100108), // Rule ID 3713 // |
| 36043 | /* 100055 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 36044 | /* 100058 */ // MIs[0] Operand 2 |
| 36045 | /* 100058 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16), |
| 36046 | /* 100069 */ // (sext_inreg:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src, v4i16:{ *:[Other] }) => (MVE_VMOVLs16bh:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src) |
| 36047 | /* 100069 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 36048 | /* 100072 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 36049 | /* 100076 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 36050 | /* 100081 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMOVLs16bh), |
| 36051 | /* 100084 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 36052 | /* 100086 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 36053 | /* 100088 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36054 | /* 100091 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36055 | /* 100097 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36056 | /* 100103 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 36057 | /* 100106 */ GIR_RootConstrainSelectedInstOperands, |
| 36058 | /* 100107 */ // GIR_Coverage, 3713, |
| 36059 | /* 100107 */ GIR_EraseRootFromParent_Done, |
| 36060 | /* 100108 */ // Label 1842: @100108 |
| 36061 | /* 100108 */ GIM_Try, /*On fail goto*//*Label 1843*/ GIMT_Encode4(100215), // Rule ID 3715 // |
| 36062 | /* 100113 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 36063 | /* 100116 */ // MIs[0] Operand 2 |
| 36064 | /* 100116 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(8), |
| 36065 | /* 100127 */ // (sext_inreg:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src, v4i8:{ *:[Other] }) => (MVE_VMOVLs16bh:{ *:[v4i32] } (MVE_VMOVLs8bh:{ *:[v16i8] } MQPR:{ *:[v4i32] }:$src)) |
| 36066 | /* 100127 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 36067 | /* 100130 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 36068 | /* 100134 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 36069 | /* 100139 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32, |
| 36070 | /* 100142 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 36071 | /* 100146 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 36072 | /* 100151 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, |
| 36073 | /* 100154 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::MVE_VMOVLs8bh), |
| 36074 | /* 100158 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 36075 | /* 100163 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 36076 | /* 100167 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 36077 | /* 100170 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36078 | /* 100176 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36079 | /* 100182 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 36080 | /* 100185 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 36081 | /* 100187 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMOVLs16bh), |
| 36082 | /* 100190 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 36083 | /* 100192 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 36084 | /* 100195 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36085 | /* 100198 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36086 | /* 100204 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36087 | /* 100210 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2, |
| 36088 | /* 100213 */ GIR_RootConstrainSelectedInstOperands, |
| 36089 | /* 100214 */ // GIR_Coverage, 3715, |
| 36090 | /* 100214 */ GIR_EraseRootFromParent_Done, |
| 36091 | /* 100215 */ // Label 1843: @100215 |
| 36092 | /* 100215 */ GIM_Reject, |
| 36093 | /* 100216 */ // Label 1841: @100216 |
| 36094 | /* 100216 */ GIM_Reject, |
| 36095 | /* 100217 */ // Label 1832: @100217 |
| 36096 | /* 100217 */ GIM_Try, /*On fail goto*//*Label 1844*/ GIMT_Encode4(100286), // Rule ID 3714 // |
| 36097 | /* 100222 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 36098 | /* 100225 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 36099 | /* 100228 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36100 | /* 100232 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36101 | /* 100236 */ // MIs[0] Operand 2 |
| 36102 | /* 100236 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(8), |
| 36103 | /* 100247 */ // (sext_inreg:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src, v8i8:{ *:[Other] }) => (MVE_VMOVLs8bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src) |
| 36104 | /* 100247 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 36105 | /* 100250 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 36106 | /* 100254 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 36107 | /* 100259 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMOVLs8bh), |
| 36108 | /* 100262 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 36109 | /* 100264 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 36110 | /* 100266 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36111 | /* 100269 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36112 | /* 100275 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36113 | /* 100281 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 36114 | /* 100284 */ GIR_RootConstrainSelectedInstOperands, |
| 36115 | /* 100285 */ // GIR_Coverage, 3714, |
| 36116 | /* 100285 */ GIR_EraseRootFromParent_Done, |
| 36117 | /* 100286 */ // Label 1844: @100286 |
| 36118 | /* 100286 */ GIM_Reject, |
| 36119 | /* 100287 */ // Label 1833: @100287 |
| 36120 | /* 100287 */ GIM_Reject, |
| 36121 | /* 100288 */ // Label 23: @100288 |
| 36122 | /* 100288 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(5), GIMT_Encode2(13), /*)*//*default:*//*Label 1848*/ GIMT_Encode4(100445), |
| 36123 | /* 100299 */ /*GILLT_v2s64*//*Label 1845*/ GIMT_Encode4(100331), GIMT_Encode4(0), GIMT_Encode4(0), |
| 36124 | /* 100311 */ /*GILLT_v4s32*//*Label 1846*/ GIMT_Encode4(100369), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 36125 | /* 100327 */ /*GILLT_v8s16*//*Label 1847*/ GIMT_Encode4(100407), |
| 36126 | /* 100331 */ // Label 1845: @100331 |
| 36127 | /* 100331 */ GIM_Try, /*On fail goto*//*Label 1849*/ GIMT_Encode4(100368), // Rule ID 1603 // |
| 36128 | /* 100336 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 36129 | /* 100339 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 36130 | /* 100342 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 36131 | /* 100346 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 36132 | /* 100350 */ // (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm) => (VMOVLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm) |
| 36133 | /* 100350 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVLuv2i64), |
| 36134 | /* 100353 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 36135 | /* 100355 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 36136 | /* 100357 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36137 | /* 100360 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36138 | /* 100366 */ GIR_RootConstrainSelectedInstOperands, |
| 36139 | /* 100367 */ // GIR_Coverage, 1603, |
| 36140 | /* 100367 */ GIR_EraseRootFromParent_Done, |
| 36141 | /* 100368 */ // Label 1849: @100368 |
| 36142 | /* 100368 */ GIM_Reject, |
| 36143 | /* 100369 */ // Label 1846: @100369 |
| 36144 | /* 100369 */ GIM_Try, /*On fail goto*//*Label 1850*/ GIMT_Encode4(100406), // Rule ID 1602 // |
| 36145 | /* 100374 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 36146 | /* 100377 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 36147 | /* 100380 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 36148 | /* 100384 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 36149 | /* 100388 */ // (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm) => (VMOVLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm) |
| 36150 | /* 100388 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVLuv4i32), |
| 36151 | /* 100391 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 36152 | /* 100393 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 36153 | /* 100395 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36154 | /* 100398 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36155 | /* 100404 */ GIR_RootConstrainSelectedInstOperands, |
| 36156 | /* 100405 */ // GIR_Coverage, 1602, |
| 36157 | /* 100405 */ GIR_EraseRootFromParent_Done, |
| 36158 | /* 100406 */ // Label 1850: @100406 |
| 36159 | /* 100406 */ GIM_Reject, |
| 36160 | /* 100407 */ // Label 1847: @100407 |
| 36161 | /* 100407 */ GIM_Try, /*On fail goto*//*Label 1851*/ GIMT_Encode4(100444), // Rule ID 1601 // |
| 36162 | /* 100412 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 36163 | /* 100415 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 36164 | /* 100418 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 36165 | /* 100422 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 36166 | /* 100426 */ // (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm) => (VMOVLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm) |
| 36167 | /* 100426 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVLuv8i16), |
| 36168 | /* 100429 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 36169 | /* 100431 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 36170 | /* 100433 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36171 | /* 100436 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36172 | /* 100442 */ GIR_RootConstrainSelectedInstOperands, |
| 36173 | /* 100443 */ // GIR_Coverage, 1601, |
| 36174 | /* 100443 */ GIR_EraseRootFromParent_Done, |
| 36175 | /* 100444 */ // Label 1851: @100444 |
| 36176 | /* 100444 */ GIM_Reject, |
| 36177 | /* 100445 */ // Label 1848: @100445 |
| 36178 | /* 100445 */ GIM_Reject, |
| 36179 | /* 100446 */ // Label 24: @100446 |
| 36180 | /* 100446 */ GIM_Try, /*On fail goto*//*Label 1852*/ GIMT_Encode4(100661), |
| 36181 | /* 100451 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 36182 | /* 100454 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 36183 | /* 100457 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 36184 | /* 100460 */ GIM_Try, /*On fail goto*//*Label 1853*/ GIMT_Encode4(100517), // Rule ID 470 // |
| 36185 | /* 100465 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 36186 | /* 100468 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36187 | /* 100472 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36188 | /* 100476 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 36189 | /* 100480 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 36190 | /* 100484 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm1_31), |
| 36191 | /* 100488 */ // MIs[1] Operand 1 |
| 36192 | /* 100488 */ // No operand predicates |
| 36193 | /* 100488 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 36194 | /* 100490 */ // (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_imm1_31>>:$imm) => (t2LSLri:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$imm) |
| 36195 | /* 100490 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2LSLri), |
| 36196 | /* 100493 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 36197 | /* 100495 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 36198 | /* 100497 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 36199 | /* 100500 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36200 | /* 100503 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36201 | /* 100509 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36202 | /* 100515 */ GIR_RootConstrainSelectedInstOperands, |
| 36203 | /* 100516 */ // GIR_Coverage, 470, |
| 36204 | /* 100516 */ GIR_EraseRootFromParent_Done, |
| 36205 | /* 100517 */ // Label 1853: @100517 |
| 36206 | /* 100517 */ GIM_Try, /*On fail goto*//*Label 1854*/ GIMT_Encode4(100614), |
| 36207 | /* 100522 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 36208 | /* 100526 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 36209 | /* 100530 */ GIM_Try, /*On fail goto*//*Label 1855*/ GIMT_Encode4(100575), // Rule ID 318 // |
| 36210 | /* 100535 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), |
| 36211 | /* 100538 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 36212 | /* 100542 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 36213 | /* 100546 */ // MIs[1] Operand 1 |
| 36214 | /* 100546 */ // No operand predicates |
| 36215 | /* 100546 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 36216 | /* 100548 */ // (shl:{ *:[i32] } tGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$imm5) => (tLSLri:{ *:[i32] } tGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$imm5) |
| 36217 | /* 100548 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tLSLri), |
| 36218 | /* 100551 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 36219 | /* 100553 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define | RegState::Dead), |
| 36220 | /* 100559 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 36221 | /* 100561 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm5 |
| 36222 | /* 100564 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36223 | /* 100567 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36224 | /* 100573 */ GIR_RootConstrainSelectedInstOperands, |
| 36225 | /* 100574 */ // GIR_Coverage, 318, |
| 36226 | /* 100574 */ GIR_EraseRootFromParent_Done, |
| 36227 | /* 100575 */ // Label 1855: @100575 |
| 36228 | /* 100575 */ GIM_Try, /*On fail goto*//*Label 1856*/ GIMT_Encode4(100613), // Rule ID 319 // |
| 36229 | /* 100580 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), |
| 36230 | /* 100583 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 36231 | /* 100587 */ // (shl:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) => (tLSLrr:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) |
| 36232 | /* 100587 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tLSLrr), |
| 36233 | /* 100590 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn] |
| 36234 | /* 100592 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define | RegState::Dead), |
| 36235 | /* 100598 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 36236 | /* 100600 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 36237 | /* 100602 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36238 | /* 100605 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36239 | /* 100611 */ GIR_RootConstrainSelectedInstOperands, |
| 36240 | /* 100612 */ // GIR_Coverage, 319, |
| 36241 | /* 100612 */ GIR_EraseRootFromParent_Done, |
| 36242 | /* 100613 */ // Label 1856: @100613 |
| 36243 | /* 100613 */ GIM_Reject, |
| 36244 | /* 100614 */ // Label 1854: @100614 |
| 36245 | /* 100614 */ GIM_Try, /*On fail goto*//*Label 1857*/ GIMT_Encode4(100660), // Rule ID 471 // |
| 36246 | /* 100619 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 36247 | /* 100622 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36248 | /* 100626 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36249 | /* 100630 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36250 | /* 100634 */ // (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2LSLrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 36251 | /* 100634 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2LSLrr), |
| 36252 | /* 100637 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 36253 | /* 100639 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 36254 | /* 100641 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 36255 | /* 100643 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36256 | /* 100646 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36257 | /* 100652 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36258 | /* 100658 */ GIR_RootConstrainSelectedInstOperands, |
| 36259 | /* 100659 */ // GIR_Coverage, 471, |
| 36260 | /* 100659 */ GIR_EraseRootFromParent_Done, |
| 36261 | /* 100660 */ // Label 1857: @100660 |
| 36262 | /* 100660 */ GIM_Reject, |
| 36263 | /* 100661 */ // Label 1852: @100661 |
| 36264 | /* 100661 */ GIM_Reject, |
| 36265 | /* 100662 */ // Label 25: @100662 |
| 36266 | /* 100662 */ GIM_Try, /*On fail goto*//*Label 1858*/ GIMT_Encode4(100769), |
| 36267 | /* 100667 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 36268 | /* 100670 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 36269 | /* 100673 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 36270 | /* 100676 */ GIM_Try, /*On fail goto*//*Label 1859*/ GIMT_Encode4(100722), // Rule ID 321 // |
| 36271 | /* 100681 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), |
| 36272 | /* 100684 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 36273 | /* 100688 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 36274 | /* 100692 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 36275 | /* 100696 */ // (srl:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) => (tLSRrr:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) |
| 36276 | /* 100696 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tLSRrr), |
| 36277 | /* 100699 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn] |
| 36278 | /* 100701 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define | RegState::Dead), |
| 36279 | /* 100707 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 36280 | /* 100709 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 36281 | /* 100711 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36282 | /* 100714 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36283 | /* 100720 */ GIR_RootConstrainSelectedInstOperands, |
| 36284 | /* 100721 */ // GIR_Coverage, 321, |
| 36285 | /* 100721 */ GIR_EraseRootFromParent_Done, |
| 36286 | /* 100722 */ // Label 1859: @100722 |
| 36287 | /* 100722 */ GIM_Try, /*On fail goto*//*Label 1860*/ GIMT_Encode4(100768), // Rule ID 473 // |
| 36288 | /* 100727 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 36289 | /* 100730 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36290 | /* 100734 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36291 | /* 100738 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36292 | /* 100742 */ // (srl:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2LSRrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 36293 | /* 100742 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2LSRrr), |
| 36294 | /* 100745 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 36295 | /* 100747 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 36296 | /* 100749 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 36297 | /* 100751 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36298 | /* 100754 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36299 | /* 100760 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36300 | /* 100766 */ GIR_RootConstrainSelectedInstOperands, |
| 36301 | /* 100767 */ // GIR_Coverage, 473, |
| 36302 | /* 100767 */ GIR_EraseRootFromParent_Done, |
| 36303 | /* 100768 */ // Label 1860: @100768 |
| 36304 | /* 100768 */ GIM_Reject, |
| 36305 | /* 100769 */ // Label 1858: @100769 |
| 36306 | /* 100769 */ GIM_Reject, |
| 36307 | /* 100770 */ // Label 26: @100770 |
| 36308 | /* 100770 */ GIM_Try, /*On fail goto*//*Label 1861*/ GIMT_Encode4(101042), |
| 36309 | /* 100775 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 36310 | /* 100778 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 36311 | /* 100781 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 36312 | /* 100784 */ GIM_Try, /*On fail goto*//*Label 1862*/ GIMT_Encode4(100839), // Rule ID 201 // |
| 36313 | /* 100789 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 36314 | /* 100792 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 36315 | /* 100796 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 36316 | /* 100800 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BSWAP), |
| 36317 | /* 100804 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 36318 | /* 100808 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 36319 | /* 100813 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 16, |
| 36320 | /* 100817 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 36321 | /* 100819 */ // (sra:{ *:[i32] } (bswap:{ *:[i32] } GPR:{ *:[i32] }:$Rm), 16:{ *:[i32] }) => (REVSH:{ *:[i32] } GPR:{ *:[i32] }:$Rm) |
| 36322 | /* 100819 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::REVSH), |
| 36323 | /* 100822 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 36324 | /* 100824 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 36325 | /* 100828 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36326 | /* 100831 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36327 | /* 100837 */ GIR_RootConstrainSelectedInstOperands, |
| 36328 | /* 100838 */ // GIR_Coverage, 201, |
| 36329 | /* 100838 */ GIR_EraseRootFromParent_Done, |
| 36330 | /* 100839 */ // Label 1862: @100839 |
| 36331 | /* 100839 */ GIM_Try, /*On fail goto*//*Label 1863*/ GIMT_Encode4(100894), // Rule ID 328 // |
| 36332 | /* 100844 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsThumb_IsThumb1Only), |
| 36333 | /* 100847 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 36334 | /* 100851 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 36335 | /* 100855 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BSWAP), |
| 36336 | /* 100859 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 36337 | /* 100863 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 36338 | /* 100868 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 16, |
| 36339 | /* 100872 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 36340 | /* 100874 */ // (sra:{ *:[i32] } (bswap:{ *:[i32] } tGPR:{ *:[i32] }:$Rm), 16:{ *:[i32] }) => (tREVSH:{ *:[i32] } tGPR:{ *:[i32] }:$Rm) |
| 36341 | /* 100874 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tREVSH), |
| 36342 | /* 100877 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 36343 | /* 100879 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 36344 | /* 100883 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36345 | /* 100886 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36346 | /* 100892 */ GIR_RootConstrainSelectedInstOperands, |
| 36347 | /* 100893 */ // GIR_Coverage, 328, |
| 36348 | /* 100893 */ GIR_EraseRootFromParent_Done, |
| 36349 | /* 100894 */ // Label 1863: @100894 |
| 36350 | /* 100894 */ GIM_Try, /*On fail goto*//*Label 1864*/ GIMT_Encode4(100949), // Rule ID 538 // |
| 36351 | /* 100899 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 36352 | /* 100902 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36353 | /* 100906 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 36354 | /* 100910 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BSWAP), |
| 36355 | /* 100914 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 36356 | /* 100918 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36357 | /* 100923 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 16, |
| 36358 | /* 100927 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 36359 | /* 100929 */ // (sra:{ *:[i32] } (bswap:{ *:[i32] } rGPR:{ *:[i32] }:$Rm), 16:{ *:[i32] }) => (t2REVSH:{ *:[i32] } rGPR:{ *:[i32] }:$Rm) |
| 36360 | /* 100929 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2REVSH), |
| 36361 | /* 100932 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 36362 | /* 100934 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 36363 | /* 100938 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36364 | /* 100941 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36365 | /* 100947 */ GIR_RootConstrainSelectedInstOperands, |
| 36366 | /* 100948 */ // GIR_Coverage, 538, |
| 36367 | /* 100948 */ GIR_EraseRootFromParent_Done, |
| 36368 | /* 100949 */ // Label 1864: @100949 |
| 36369 | /* 100949 */ GIM_Try, /*On fail goto*//*Label 1865*/ GIMT_Encode4(100995), // Rule ID 312 // |
| 36370 | /* 100954 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), |
| 36371 | /* 100957 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 36372 | /* 100961 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 36373 | /* 100965 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 36374 | /* 100969 */ // (sra:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) => (tASRrr:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) |
| 36375 | /* 100969 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tASRrr), |
| 36376 | /* 100972 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn] |
| 36377 | /* 100974 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define | RegState::Dead), |
| 36378 | /* 100980 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 36379 | /* 100982 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 36380 | /* 100984 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36381 | /* 100987 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36382 | /* 100993 */ GIR_RootConstrainSelectedInstOperands, |
| 36383 | /* 100994 */ // GIR_Coverage, 312, |
| 36384 | /* 100994 */ GIR_EraseRootFromParent_Done, |
| 36385 | /* 100995 */ // Label 1865: @100995 |
| 36386 | /* 100995 */ GIM_Try, /*On fail goto*//*Label 1866*/ GIMT_Encode4(101041), // Rule ID 475 // |
| 36387 | /* 101000 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 36388 | /* 101003 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36389 | /* 101007 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36390 | /* 101011 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36391 | /* 101015 */ // (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2ASRrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 36392 | /* 101015 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ASRrr), |
| 36393 | /* 101018 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 36394 | /* 101020 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 36395 | /* 101022 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 36396 | /* 101024 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36397 | /* 101027 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36398 | /* 101033 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36399 | /* 101039 */ GIR_RootConstrainSelectedInstOperands, |
| 36400 | /* 101040 */ // GIR_Coverage, 475, |
| 36401 | /* 101040 */ GIR_EraseRootFromParent_Done, |
| 36402 | /* 101041 */ // Label 1866: @101041 |
| 36403 | /* 101041 */ GIM_Reject, |
| 36404 | /* 101042 */ // Label 1861: @101042 |
| 36405 | /* 101042 */ GIM_Reject, |
| 36406 | /* 101043 */ // Label 27: @101043 |
| 36407 | /* 101043 */ GIM_Try, /*On fail goto*//*Label 1867*/ GIMT_Encode4(101374), |
| 36408 | /* 101048 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 36409 | /* 101051 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 36410 | /* 101054 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 36411 | /* 101057 */ GIM_Try, /*On fail goto*//*Label 1868*/ GIMT_Encode4(101112), // Rule ID 200 // |
| 36412 | /* 101062 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 36413 | /* 101065 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 36414 | /* 101069 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 36415 | /* 101073 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BSWAP), |
| 36416 | /* 101077 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 36417 | /* 101081 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 36418 | /* 101086 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 16, |
| 36419 | /* 101090 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 36420 | /* 101092 */ // (rotr:{ *:[i32] } (bswap:{ *:[i32] } GPR:{ *:[i32] }:$Rm), 16:{ *:[i32] }) => (REV16:{ *:[i32] } GPR:{ *:[i32] }:$Rm) |
| 36421 | /* 101092 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::REV16), |
| 36422 | /* 101095 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 36423 | /* 101097 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 36424 | /* 101101 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36425 | /* 101104 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36426 | /* 101110 */ GIR_RootConstrainSelectedInstOperands, |
| 36427 | /* 101111 */ // GIR_Coverage, 200, |
| 36428 | /* 101111 */ GIR_EraseRootFromParent_Done, |
| 36429 | /* 101112 */ // Label 1868: @101112 |
| 36430 | /* 101112 */ GIM_Try, /*On fail goto*//*Label 1869*/ GIMT_Encode4(101167), // Rule ID 327 // |
| 36431 | /* 101117 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsThumb_IsThumb1Only), |
| 36432 | /* 101120 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 36433 | /* 101124 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 36434 | /* 101128 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BSWAP), |
| 36435 | /* 101132 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 36436 | /* 101136 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 36437 | /* 101141 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 16, |
| 36438 | /* 101145 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 36439 | /* 101147 */ // (rotr:{ *:[i32] } (bswap:{ *:[i32] } tGPR:{ *:[i32] }:$Rm), 16:{ *:[i32] }) => (tREV16:{ *:[i32] } tGPR:{ *:[i32] }:$Rm) |
| 36440 | /* 101147 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tREV16), |
| 36441 | /* 101150 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 36442 | /* 101152 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 36443 | /* 101156 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36444 | /* 101159 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36445 | /* 101165 */ GIR_RootConstrainSelectedInstOperands, |
| 36446 | /* 101166 */ // GIR_Coverage, 327, |
| 36447 | /* 101166 */ GIR_EraseRootFromParent_Done, |
| 36448 | /* 101167 */ // Label 1869: @101167 |
| 36449 | /* 101167 */ GIM_Try, /*On fail goto*//*Label 1870*/ GIMT_Encode4(101281), |
| 36450 | /* 101172 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36451 | /* 101176 */ GIM_Try, /*On fail goto*//*Label 1871*/ GIMT_Encode4(101227), // Rule ID 537 // |
| 36452 | /* 101181 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 36453 | /* 101184 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 36454 | /* 101188 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BSWAP), |
| 36455 | /* 101192 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 36456 | /* 101196 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36457 | /* 101201 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 16, |
| 36458 | /* 101205 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 36459 | /* 101207 */ // (rotr:{ *:[i32] } (bswap:{ *:[i32] } rGPR:{ *:[i32] }:$Rm), 16:{ *:[i32] }) => (t2REV16:{ *:[i32] } rGPR:{ *:[i32] }:$Rm) |
| 36460 | /* 101207 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2REV16), |
| 36461 | /* 101210 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 36462 | /* 101212 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 36463 | /* 101216 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36464 | /* 101219 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36465 | /* 101225 */ GIR_RootConstrainSelectedInstOperands, |
| 36466 | /* 101226 */ // GIR_Coverage, 537, |
| 36467 | /* 101226 */ GIR_EraseRootFromParent_Done, |
| 36468 | /* 101227 */ // Label 1871: @101227 |
| 36469 | /* 101227 */ GIM_Try, /*On fail goto*//*Label 1872*/ GIMT_Encode4(101280), // Rule ID 476 // |
| 36470 | /* 101232 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 36471 | /* 101235 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36472 | /* 101239 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 36473 | /* 101243 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 36474 | /* 101247 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm1_31), |
| 36475 | /* 101251 */ // MIs[1] Operand 1 |
| 36476 | /* 101251 */ // No operand predicates |
| 36477 | /* 101251 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 36478 | /* 101253 */ // (rotr:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_imm1_31>>:$imm) => (t2RORri:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$imm) |
| 36479 | /* 101253 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2RORri), |
| 36480 | /* 101256 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 36481 | /* 101258 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 36482 | /* 101260 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 36483 | /* 101263 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36484 | /* 101266 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36485 | /* 101272 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36486 | /* 101278 */ GIR_RootConstrainSelectedInstOperands, |
| 36487 | /* 101279 */ // GIR_Coverage, 476, |
| 36488 | /* 101279 */ GIR_EraseRootFromParent_Done, |
| 36489 | /* 101280 */ // Label 1872: @101280 |
| 36490 | /* 101280 */ GIM_Reject, |
| 36491 | /* 101281 */ // Label 1870: @101281 |
| 36492 | /* 101281 */ GIM_Try, /*On fail goto*//*Label 1873*/ GIMT_Encode4(101327), // Rule ID 329 // |
| 36493 | /* 101286 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), |
| 36494 | /* 101289 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 36495 | /* 101293 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 36496 | /* 101297 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 36497 | /* 101301 */ // (rotr:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) => (tROR:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) |
| 36498 | /* 101301 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tROR), |
| 36499 | /* 101304 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn] |
| 36500 | /* 101306 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define | RegState::Dead), |
| 36501 | /* 101312 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 36502 | /* 101314 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 36503 | /* 101316 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36504 | /* 101319 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36505 | /* 101325 */ GIR_RootConstrainSelectedInstOperands, |
| 36506 | /* 101326 */ // GIR_Coverage, 329, |
| 36507 | /* 101326 */ GIR_EraseRootFromParent_Done, |
| 36508 | /* 101327 */ // Label 1873: @101327 |
| 36509 | /* 101327 */ GIM_Try, /*On fail goto*//*Label 1874*/ GIMT_Encode4(101373), // Rule ID 477 // |
| 36510 | /* 101332 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 36511 | /* 101335 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36512 | /* 101339 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36513 | /* 101343 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36514 | /* 101347 */ // (rotr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2RORrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 36515 | /* 101347 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2RORrr), |
| 36516 | /* 101350 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 36517 | /* 101352 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 36518 | /* 101354 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 36519 | /* 101356 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36520 | /* 101359 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36521 | /* 101365 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36522 | /* 101371 */ GIR_RootConstrainSelectedInstOperands, |
| 36523 | /* 101372 */ // GIR_Coverage, 477, |
| 36524 | /* 101372 */ GIR_EraseRootFromParent_Done, |
| 36525 | /* 101373 */ // Label 1874: @101373 |
| 36526 | /* 101373 */ GIM_Reject, |
| 36527 | /* 101374 */ // Label 1867: @101374 |
| 36528 | /* 101374 */ GIM_Reject, |
| 36529 | /* 101375 */ // Label 28: @101375 |
| 36530 | /* 101375 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(16), /*)*//*default:*//*Label 1878*/ GIMT_Encode4(101622), |
| 36531 | /* 101386 */ /*GILLT_v4s32*//*Label 1875*/ GIMT_Encode4(101418), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 36532 | /* 101402 */ /*GILLT_v8s16*//*Label 1876*/ GIMT_Encode4(101486), GIMT_Encode4(0), GIMT_Encode4(0), |
| 36533 | /* 101414 */ /*GILLT_v16s8*//*Label 1877*/ GIMT_Encode4(101554), |
| 36534 | /* 101418 */ // Label 1875: @101418 |
| 36535 | /* 101418 */ GIM_Try, /*On fail goto*//*Label 1879*/ GIMT_Encode4(101485), // Rule ID 4464 // |
| 36536 | /* 101423 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 36537 | /* 101426 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 36538 | /* 101429 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 36539 | /* 101432 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36540 | /* 101436 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36541 | /* 101440 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36542 | /* 101444 */ // (mulhu:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VMULHu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 36543 | /* 101444 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 36544 | /* 101447 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 36545 | /* 101451 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 36546 | /* 101456 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHu32), |
| 36547 | /* 101459 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 36548 | /* 101461 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 36549 | /* 101463 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 36550 | /* 101465 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36551 | /* 101468 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36552 | /* 101474 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36553 | /* 101480 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 36554 | /* 101483 */ GIR_RootConstrainSelectedInstOperands, |
| 36555 | /* 101484 */ // GIR_Coverage, 4464, |
| 36556 | /* 101484 */ GIR_EraseRootFromParent_Done, |
| 36557 | /* 101485 */ // Label 1879: @101485 |
| 36558 | /* 101485 */ GIM_Reject, |
| 36559 | /* 101486 */ // Label 1876: @101486 |
| 36560 | /* 101486 */ GIM_Try, /*On fail goto*//*Label 1880*/ GIMT_Encode4(101553), // Rule ID 4460 // |
| 36561 | /* 101491 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 36562 | /* 101494 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 36563 | /* 101497 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 36564 | /* 101500 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36565 | /* 101504 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36566 | /* 101508 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36567 | /* 101512 */ // (mulhu:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VMULHu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 36568 | /* 101512 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 36569 | /* 101515 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 36570 | /* 101519 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 36571 | /* 101524 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHu16), |
| 36572 | /* 101527 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 36573 | /* 101529 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 36574 | /* 101531 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 36575 | /* 101533 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36576 | /* 101536 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36577 | /* 101542 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36578 | /* 101548 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 36579 | /* 101551 */ GIR_RootConstrainSelectedInstOperands, |
| 36580 | /* 101552 */ // GIR_Coverage, 4460, |
| 36581 | /* 101552 */ GIR_EraseRootFromParent_Done, |
| 36582 | /* 101553 */ // Label 1880: @101553 |
| 36583 | /* 101553 */ GIM_Reject, |
| 36584 | /* 101554 */ // Label 1877: @101554 |
| 36585 | /* 101554 */ GIM_Try, /*On fail goto*//*Label 1881*/ GIMT_Encode4(101621), // Rule ID 4456 // |
| 36586 | /* 101559 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 36587 | /* 101562 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 36588 | /* 101565 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 36589 | /* 101568 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36590 | /* 101572 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36591 | /* 101576 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36592 | /* 101580 */ // (mulhu:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VMULHu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 36593 | /* 101580 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 36594 | /* 101583 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 36595 | /* 101587 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 36596 | /* 101592 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHu8), |
| 36597 | /* 101595 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 36598 | /* 101597 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 36599 | /* 101599 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 36600 | /* 101601 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36601 | /* 101604 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36602 | /* 101610 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36603 | /* 101616 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 36604 | /* 101619 */ GIR_RootConstrainSelectedInstOperands, |
| 36605 | /* 101620 */ // GIR_Coverage, 4456, |
| 36606 | /* 101620 */ GIR_EraseRootFromParent_Done, |
| 36607 | /* 101621 */ // Label 1881: @101621 |
| 36608 | /* 101621 */ GIM_Reject, |
| 36609 | /* 101622 */ // Label 1878: @101622 |
| 36610 | /* 101622 */ GIM_Reject, |
| 36611 | /* 101623 */ // Label 29: @101623 |
| 36612 | /* 101623 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(16), /*)*//*default:*//*Label 1886*/ GIMT_Encode4(101991), |
| 36613 | /* 101634 */ /*GILLT_s32*//*Label 1882*/ GIMT_Encode4(101694), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 36614 | /* 101662 */ /*GILLT_v4s32*//*Label 1883*/ GIMT_Encode4(101787), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 36615 | /* 101678 */ /*GILLT_v8s16*//*Label 1884*/ GIMT_Encode4(101855), GIMT_Encode4(0), GIMT_Encode4(0), |
| 36616 | /* 101690 */ /*GILLT_v16s8*//*Label 1885*/ GIMT_Encode4(101923), |
| 36617 | /* 101694 */ // Label 1882: @101694 |
| 36618 | /* 101694 */ GIM_Try, /*On fail goto*//*Label 1887*/ GIMT_Encode4(101786), |
| 36619 | /* 101699 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 36620 | /* 101702 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 36621 | /* 101705 */ GIM_Try, /*On fail goto*//*Label 1888*/ GIMT_Encode4(101745), // Rule ID 178 // |
| 36622 | /* 101710 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 36623 | /* 101713 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 36624 | /* 101717 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 36625 | /* 101721 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 36626 | /* 101725 */ // (mulhs:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (SMMUL:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) |
| 36627 | /* 101725 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMMUL), |
| 36628 | /* 101728 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 36629 | /* 101730 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 36630 | /* 101732 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 36631 | /* 101734 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36632 | /* 101737 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36633 | /* 101743 */ GIR_RootConstrainSelectedInstOperands, |
| 36634 | /* 101744 */ // GIR_Coverage, 178, |
| 36635 | /* 101744 */ GIR_EraseRootFromParent_Done, |
| 36636 | /* 101745 */ // Label 1888: @101745 |
| 36637 | /* 101745 */ GIM_Try, /*On fail goto*//*Label 1889*/ GIMT_Encode4(101785), // Rule ID 507 // |
| 36638 | /* 101750 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 36639 | /* 101753 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36640 | /* 101757 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36641 | /* 101761 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36642 | /* 101765 */ // (mulhs:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMMUL:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 36643 | /* 101765 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMMUL), |
| 36644 | /* 101768 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 36645 | /* 101770 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 36646 | /* 101772 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 36647 | /* 101774 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36648 | /* 101777 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36649 | /* 101783 */ GIR_RootConstrainSelectedInstOperands, |
| 36650 | /* 101784 */ // GIR_Coverage, 507, |
| 36651 | /* 101784 */ GIR_EraseRootFromParent_Done, |
| 36652 | /* 101785 */ // Label 1889: @101785 |
| 36653 | /* 101785 */ GIM_Reject, |
| 36654 | /* 101786 */ // Label 1887: @101786 |
| 36655 | /* 101786 */ GIM_Reject, |
| 36656 | /* 101787 */ // Label 1883: @101787 |
| 36657 | /* 101787 */ GIM_Try, /*On fail goto*//*Label 1890*/ GIMT_Encode4(101854), // Rule ID 4452 // |
| 36658 | /* 101792 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 36659 | /* 101795 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 36660 | /* 101798 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 36661 | /* 101801 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36662 | /* 101805 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36663 | /* 101809 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36664 | /* 101813 */ // (mulhs:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VMULHs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 36665 | /* 101813 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 36666 | /* 101816 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 36667 | /* 101820 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 36668 | /* 101825 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHs32), |
| 36669 | /* 101828 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 36670 | /* 101830 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 36671 | /* 101832 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 36672 | /* 101834 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36673 | /* 101837 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36674 | /* 101843 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36675 | /* 101849 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 36676 | /* 101852 */ GIR_RootConstrainSelectedInstOperands, |
| 36677 | /* 101853 */ // GIR_Coverage, 4452, |
| 36678 | /* 101853 */ GIR_EraseRootFromParent_Done, |
| 36679 | /* 101854 */ // Label 1890: @101854 |
| 36680 | /* 101854 */ GIM_Reject, |
| 36681 | /* 101855 */ // Label 1884: @101855 |
| 36682 | /* 101855 */ GIM_Try, /*On fail goto*//*Label 1891*/ GIMT_Encode4(101922), // Rule ID 4448 // |
| 36683 | /* 101860 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 36684 | /* 101863 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 36685 | /* 101866 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 36686 | /* 101869 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36687 | /* 101873 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36688 | /* 101877 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36689 | /* 101881 */ // (mulhs:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VMULHs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 36690 | /* 101881 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 36691 | /* 101884 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 36692 | /* 101888 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 36693 | /* 101893 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHs16), |
| 36694 | /* 101896 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 36695 | /* 101898 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 36696 | /* 101900 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 36697 | /* 101902 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36698 | /* 101905 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36699 | /* 101911 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36700 | /* 101917 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 36701 | /* 101920 */ GIR_RootConstrainSelectedInstOperands, |
| 36702 | /* 101921 */ // GIR_Coverage, 4448, |
| 36703 | /* 101921 */ GIR_EraseRootFromParent_Done, |
| 36704 | /* 101922 */ // Label 1891: @101922 |
| 36705 | /* 101922 */ GIM_Reject, |
| 36706 | /* 101923 */ // Label 1885: @101923 |
| 36707 | /* 101923 */ GIM_Try, /*On fail goto*//*Label 1892*/ GIMT_Encode4(101990), // Rule ID 4445 // |
| 36708 | /* 101928 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 36709 | /* 101931 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 36710 | /* 101934 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 36711 | /* 101937 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36712 | /* 101941 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36713 | /* 101945 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36714 | /* 101949 */ // (mulhs:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VMULHs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 36715 | /* 101949 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 36716 | /* 101952 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 36717 | /* 101956 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 36718 | /* 101961 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHs8), |
| 36719 | /* 101964 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 36720 | /* 101966 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 36721 | /* 101968 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 36722 | /* 101970 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36723 | /* 101973 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36724 | /* 101979 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36725 | /* 101985 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 36726 | /* 101988 */ GIR_RootConstrainSelectedInstOperands, |
| 36727 | /* 101989 */ // GIR_Coverage, 4445, |
| 36728 | /* 101989 */ GIR_EraseRootFromParent_Done, |
| 36729 | /* 101990 */ // Label 1892: @101990 |
| 36730 | /* 101990 */ GIM_Reject, |
| 36731 | /* 101991 */ // Label 1886: @101991 |
| 36732 | /* 101991 */ GIM_Reject, |
| 36733 | /* 101992 */ // Label 30: @101992 |
| 36734 | /* 101992 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(16), /*)*//*default:*//*Label 1901*/ GIMT_Encode4(102636), |
| 36735 | /* 102003 */ /*GILLT_s64*//*Label 1893*/ GIMT_Encode4(102059), GIMT_Encode4(0), |
| 36736 | /* 102011 */ /*GILLT_v2s32*//*Label 1894*/ GIMT_Encode4(102106), |
| 36737 | /* 102015 */ /*GILLT_v2s64*//*Label 1895*/ GIMT_Encode4(102153), GIMT_Encode4(0), |
| 36738 | /* 102023 */ /*GILLT_v4s16*//*Label 1896*/ GIMT_Encode4(102200), |
| 36739 | /* 102027 */ /*GILLT_v4s32*//*Label 1897*/ GIMT_Encode4(102247), GIMT_Encode4(0), GIMT_Encode4(0), |
| 36740 | /* 102039 */ /*GILLT_v8s8*//*Label 1898*/ GIMT_Encode4(102361), |
| 36741 | /* 102043 */ /*GILLT_v8s16*//*Label 1899*/ GIMT_Encode4(102408), GIMT_Encode4(0), GIMT_Encode4(0), |
| 36742 | /* 102055 */ /*GILLT_v16s8*//*Label 1900*/ GIMT_Encode4(102522), |
| 36743 | /* 102059 */ // Label 1893: @102059 |
| 36744 | /* 102059 */ GIM_Try, /*On fail goto*//*Label 1902*/ GIMT_Encode4(102105), // Rule ID 830 // |
| 36745 | /* 102064 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 36746 | /* 102067 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 36747 | /* 102070 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 36748 | /* 102073 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 36749 | /* 102077 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 36750 | /* 102081 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 36751 | /* 102085 */ // (uaddsat:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) => (VQADDuv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) |
| 36752 | /* 102085 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDuv1i64), |
| 36753 | /* 102088 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 36754 | /* 102090 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 36755 | /* 102092 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 36756 | /* 102094 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36757 | /* 102097 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36758 | /* 102103 */ GIR_RootConstrainSelectedInstOperands, |
| 36759 | /* 102104 */ // GIR_Coverage, 830, |
| 36760 | /* 102104 */ GIR_EraseRootFromParent_Done, |
| 36761 | /* 102105 */ // Label 1902: @102105 |
| 36762 | /* 102105 */ GIM_Reject, |
| 36763 | /* 102106 */ // Label 1894: @102106 |
| 36764 | /* 102106 */ GIM_Try, /*On fail goto*//*Label 1903*/ GIMT_Encode4(102152), // Rule ID 825 // |
| 36765 | /* 102111 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 36766 | /* 102114 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 36767 | /* 102117 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 36768 | /* 102120 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 36769 | /* 102124 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 36770 | /* 102128 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 36771 | /* 102132 */ // (uaddsat:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VQADDuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 36772 | /* 102132 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDuv2i32), |
| 36773 | /* 102135 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 36774 | /* 102137 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 36775 | /* 102139 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 36776 | /* 102141 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36777 | /* 102144 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36778 | /* 102150 */ GIR_RootConstrainSelectedInstOperands, |
| 36779 | /* 102151 */ // GIR_Coverage, 825, |
| 36780 | /* 102151 */ GIR_EraseRootFromParent_Done, |
| 36781 | /* 102152 */ // Label 1903: @102152 |
| 36782 | /* 102152 */ GIM_Reject, |
| 36783 | /* 102153 */ // Label 1895: @102153 |
| 36784 | /* 102153 */ GIM_Try, /*On fail goto*//*Label 1904*/ GIMT_Encode4(102199), // Rule ID 831 // |
| 36785 | /* 102158 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 36786 | /* 102161 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 36787 | /* 102164 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 36788 | /* 102167 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 36789 | /* 102171 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 36790 | /* 102175 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 36791 | /* 102179 */ // (uaddsat:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) => (VQADDuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) |
| 36792 | /* 102179 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDuv2i64), |
| 36793 | /* 102182 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 36794 | /* 102184 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 36795 | /* 102186 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 36796 | /* 102188 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36797 | /* 102191 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36798 | /* 102197 */ GIR_RootConstrainSelectedInstOperands, |
| 36799 | /* 102198 */ // GIR_Coverage, 831, |
| 36800 | /* 102198 */ GIR_EraseRootFromParent_Done, |
| 36801 | /* 102199 */ // Label 1904: @102199 |
| 36802 | /* 102199 */ GIM_Reject, |
| 36803 | /* 102200 */ // Label 1896: @102200 |
| 36804 | /* 102200 */ GIM_Try, /*On fail goto*//*Label 1905*/ GIMT_Encode4(102246), // Rule ID 824 // |
| 36805 | /* 102205 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 36806 | /* 102208 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 36807 | /* 102211 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 36808 | /* 102214 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 36809 | /* 102218 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 36810 | /* 102222 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 36811 | /* 102226 */ // (uaddsat:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VQADDuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 36812 | /* 102226 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDuv4i16), |
| 36813 | /* 102229 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 36814 | /* 102231 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 36815 | /* 102233 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 36816 | /* 102235 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36817 | /* 102238 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36818 | /* 102244 */ GIR_RootConstrainSelectedInstOperands, |
| 36819 | /* 102245 */ // GIR_Coverage, 824, |
| 36820 | /* 102245 */ GIR_EraseRootFromParent_Done, |
| 36821 | /* 102246 */ // Label 1905: @102246 |
| 36822 | /* 102246 */ GIM_Reject, |
| 36823 | /* 102247 */ // Label 1897: @102247 |
| 36824 | /* 102247 */ GIM_Try, /*On fail goto*//*Label 1906*/ GIMT_Encode4(102360), |
| 36825 | /* 102252 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 36826 | /* 102255 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 36827 | /* 102258 */ GIM_Try, /*On fail goto*//*Label 1907*/ GIMT_Encode4(102298), // Rule ID 827 // |
| 36828 | /* 102263 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 36829 | /* 102266 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 36830 | /* 102270 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 36831 | /* 102274 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 36832 | /* 102278 */ // (uaddsat:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VQADDuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 36833 | /* 102278 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDuv4i32), |
| 36834 | /* 102281 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 36835 | /* 102283 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 36836 | /* 102285 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 36837 | /* 102287 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36838 | /* 102290 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36839 | /* 102296 */ GIR_RootConstrainSelectedInstOperands, |
| 36840 | /* 102297 */ // GIR_Coverage, 827, |
| 36841 | /* 102297 */ GIR_EraseRootFromParent_Done, |
| 36842 | /* 102298 */ // Label 1907: @102298 |
| 36843 | /* 102298 */ GIM_Try, /*On fail goto*//*Label 1908*/ GIMT_Encode4(102359), // Rule ID 3527 // |
| 36844 | /* 102303 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 36845 | /* 102306 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36846 | /* 102310 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36847 | /* 102314 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36848 | /* 102318 */ // (uaddsat:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VQADDu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 36849 | /* 102318 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 36850 | /* 102321 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 36851 | /* 102325 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 36852 | /* 102330 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQADDu32), |
| 36853 | /* 102333 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 36854 | /* 102335 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 36855 | /* 102337 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 36856 | /* 102339 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36857 | /* 102342 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36858 | /* 102348 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36859 | /* 102354 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 36860 | /* 102357 */ GIR_RootConstrainSelectedInstOperands, |
| 36861 | /* 102358 */ // GIR_Coverage, 3527, |
| 36862 | /* 102358 */ GIR_EraseRootFromParent_Done, |
| 36863 | /* 102359 */ // Label 1908: @102359 |
| 36864 | /* 102359 */ GIM_Reject, |
| 36865 | /* 102360 */ // Label 1906: @102360 |
| 36866 | /* 102360 */ GIM_Reject, |
| 36867 | /* 102361 */ // Label 1898: @102361 |
| 36868 | /* 102361 */ GIM_Try, /*On fail goto*//*Label 1909*/ GIMT_Encode4(102407), // Rule ID 828 // |
| 36869 | /* 102366 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 36870 | /* 102369 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 36871 | /* 102372 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 36872 | /* 102375 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 36873 | /* 102379 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 36874 | /* 102383 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 36875 | /* 102387 */ // (uaddsat:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VQADDuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 36876 | /* 102387 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDuv8i8), |
| 36877 | /* 102390 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 36878 | /* 102392 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 36879 | /* 102394 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 36880 | /* 102396 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36881 | /* 102399 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36882 | /* 102405 */ GIR_RootConstrainSelectedInstOperands, |
| 36883 | /* 102406 */ // GIR_Coverage, 828, |
| 36884 | /* 102406 */ GIR_EraseRootFromParent_Done, |
| 36885 | /* 102407 */ // Label 1909: @102407 |
| 36886 | /* 102407 */ GIM_Reject, |
| 36887 | /* 102408 */ // Label 1899: @102408 |
| 36888 | /* 102408 */ GIM_Try, /*On fail goto*//*Label 1910*/ GIMT_Encode4(102521), |
| 36889 | /* 102413 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 36890 | /* 102416 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 36891 | /* 102419 */ GIM_Try, /*On fail goto*//*Label 1911*/ GIMT_Encode4(102459), // Rule ID 826 // |
| 36892 | /* 102424 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 36893 | /* 102427 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 36894 | /* 102431 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 36895 | /* 102435 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 36896 | /* 102439 */ // (uaddsat:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VQADDuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 36897 | /* 102439 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDuv8i16), |
| 36898 | /* 102442 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 36899 | /* 102444 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 36900 | /* 102446 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 36901 | /* 102448 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36902 | /* 102451 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36903 | /* 102457 */ GIR_RootConstrainSelectedInstOperands, |
| 36904 | /* 102458 */ // GIR_Coverage, 826, |
| 36905 | /* 102458 */ GIR_EraseRootFromParent_Done, |
| 36906 | /* 102459 */ // Label 1911: @102459 |
| 36907 | /* 102459 */ GIM_Try, /*On fail goto*//*Label 1912*/ GIMT_Encode4(102520), // Rule ID 3524 // |
| 36908 | /* 102464 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 36909 | /* 102467 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36910 | /* 102471 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36911 | /* 102475 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36912 | /* 102479 */ // (uaddsat:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VQADDu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 36913 | /* 102479 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 36914 | /* 102482 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 36915 | /* 102486 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 36916 | /* 102491 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQADDu16), |
| 36917 | /* 102494 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 36918 | /* 102496 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 36919 | /* 102498 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 36920 | /* 102500 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36921 | /* 102503 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36922 | /* 102509 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36923 | /* 102515 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 36924 | /* 102518 */ GIR_RootConstrainSelectedInstOperands, |
| 36925 | /* 102519 */ // GIR_Coverage, 3524, |
| 36926 | /* 102519 */ GIR_EraseRootFromParent_Done, |
| 36927 | /* 102520 */ // Label 1912: @102520 |
| 36928 | /* 102520 */ GIM_Reject, |
| 36929 | /* 102521 */ // Label 1910: @102521 |
| 36930 | /* 102521 */ GIM_Reject, |
| 36931 | /* 102522 */ // Label 1900: @102522 |
| 36932 | /* 102522 */ GIM_Try, /*On fail goto*//*Label 1913*/ GIMT_Encode4(102635), |
| 36933 | /* 102527 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 36934 | /* 102530 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 36935 | /* 102533 */ GIM_Try, /*On fail goto*//*Label 1914*/ GIMT_Encode4(102573), // Rule ID 829 // |
| 36936 | /* 102538 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 36937 | /* 102541 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 36938 | /* 102545 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 36939 | /* 102549 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 36940 | /* 102553 */ // (uaddsat:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VQADDuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 36941 | /* 102553 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDuv16i8), |
| 36942 | /* 102556 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 36943 | /* 102558 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 36944 | /* 102560 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 36945 | /* 102562 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36946 | /* 102565 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36947 | /* 102571 */ GIR_RootConstrainSelectedInstOperands, |
| 36948 | /* 102572 */ // GIR_Coverage, 829, |
| 36949 | /* 102572 */ GIR_EraseRootFromParent_Done, |
| 36950 | /* 102573 */ // Label 1914: @102573 |
| 36951 | /* 102573 */ GIM_Try, /*On fail goto*//*Label 1915*/ GIMT_Encode4(102634), // Rule ID 3521 // |
| 36952 | /* 102578 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 36953 | /* 102581 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36954 | /* 102585 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36955 | /* 102589 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36956 | /* 102593 */ // (uaddsat:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VQADDu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 36957 | /* 102593 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 36958 | /* 102596 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 36959 | /* 102600 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 36960 | /* 102605 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQADDu8), |
| 36961 | /* 102608 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 36962 | /* 102610 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 36963 | /* 102612 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 36964 | /* 102614 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36965 | /* 102617 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36966 | /* 102623 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36967 | /* 102629 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 36968 | /* 102632 */ GIR_RootConstrainSelectedInstOperands, |
| 36969 | /* 102633 */ // GIR_Coverage, 3521, |
| 36970 | /* 102633 */ GIR_EraseRootFromParent_Done, |
| 36971 | /* 102634 */ // Label 1915: @102634 |
| 36972 | /* 102634 */ GIM_Reject, |
| 36973 | /* 102635 */ // Label 1913: @102635 |
| 36974 | /* 102635 */ GIM_Reject, |
| 36975 | /* 102636 */ // Label 1901: @102636 |
| 36976 | /* 102636 */ GIM_Reject, |
| 36977 | /* 102637 */ // Label 31: @102637 |
| 36978 | /* 102637 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(16), /*)*//*default:*//*Label 1925*/ GIMT_Encode4(103936), |
| 36979 | /* 102648 */ /*GILLT_s32*//*Label 1916*/ GIMT_Encode4(102708), |
| 36980 | /* 102652 */ /*GILLT_s64*//*Label 1917*/ GIMT_Encode4(103049), GIMT_Encode4(0), |
| 36981 | /* 102660 */ /*GILLT_v2s32*//*Label 1918*/ GIMT_Encode4(103096), |
| 36982 | /* 102664 */ /*GILLT_v2s64*//*Label 1919*/ GIMT_Encode4(103143), GIMT_Encode4(0), |
| 36983 | /* 102672 */ /*GILLT_v4s16*//*Label 1920*/ GIMT_Encode4(103344), |
| 36984 | /* 102676 */ /*GILLT_v4s32*//*Label 1921*/ GIMT_Encode4(103391), GIMT_Encode4(0), GIMT_Encode4(0), |
| 36985 | /* 102688 */ /*GILLT_v8s8*//*Label 1922*/ GIMT_Encode4(103661), |
| 36986 | /* 102692 */ /*GILLT_v8s16*//*Label 1923*/ GIMT_Encode4(103708), GIMT_Encode4(0), GIMT_Encode4(0), |
| 36987 | /* 102704 */ /*GILLT_v16s8*//*Label 1924*/ GIMT_Encode4(103822), |
| 36988 | /* 102708 */ // Label 1916: @102708 |
| 36989 | /* 102708 */ GIM_Try, /*On fail goto*//*Label 1926*/ GIMT_Encode4(103048), |
| 36990 | /* 102713 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 36991 | /* 102716 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 36992 | /* 102719 */ GIM_Try, /*On fail goto*//*Label 1927*/ GIMT_Encode4(102781), // Rule ID 5654 // |
| 36993 | /* 102724 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM), |
| 36994 | /* 102727 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 36995 | /* 102731 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 36996 | /* 102735 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SADDSAT), |
| 36997 | /* 102739 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 36998 | /* 102743 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36999 | /* 102748 */ // MIs[1] Rn |
| 37000 | /* 102748 */ GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 37001 | /* 102753 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 37002 | /* 102757 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 37003 | /* 102759 */ // (saddsat:{ *:[i32] } (saddsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rn), rGPR:{ *:[i32] }:$Rm) => (QDADD:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn) |
| 37004 | /* 102759 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QDADD), |
| 37005 | /* 102762 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 37006 | /* 102764 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 37007 | /* 102766 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 37008 | /* 102770 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37009 | /* 102773 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37010 | /* 102779 */ GIR_RootConstrainSelectedInstOperands, |
| 37011 | /* 102780 */ // GIR_Coverage, 5654, |
| 37012 | /* 102780 */ GIR_EraseRootFromParent_Done, |
| 37013 | /* 102781 */ // Label 1927: @102781 |
| 37014 | /* 102781 */ GIM_Try, /*On fail goto*//*Label 1928*/ GIMT_Encode4(102843), // Rule ID 5688 // |
| 37015 | /* 102786 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 37016 | /* 102789 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 37017 | /* 102793 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 37018 | /* 102797 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SADDSAT), |
| 37019 | /* 102801 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 37020 | /* 102805 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 37021 | /* 102810 */ // MIs[1] Rn |
| 37022 | /* 102810 */ GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 37023 | /* 102815 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 37024 | /* 102819 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 37025 | /* 102821 */ // (saddsat:{ *:[i32] } (saddsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rn), rGPR:{ *:[i32] }:$Rm) => (t2QDADD:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn) |
| 37026 | /* 102821 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QDADD), |
| 37027 | /* 102824 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 37028 | /* 102826 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 37029 | /* 102828 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 37030 | /* 102832 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37031 | /* 102835 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37032 | /* 102841 */ GIR_RootConstrainSelectedInstOperands, |
| 37033 | /* 102842 */ // GIR_Coverage, 5688, |
| 37034 | /* 102842 */ GIR_EraseRootFromParent_Done, |
| 37035 | /* 102843 */ // Label 1928: @102843 |
| 37036 | /* 102843 */ GIM_Try, /*On fail goto*//*Label 1929*/ GIMT_Encode4(102905), // Rule ID 1870 // |
| 37037 | /* 102848 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM), |
| 37038 | /* 102851 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 37039 | /* 102855 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 37040 | /* 102859 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 37041 | /* 102863 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SADDSAT), |
| 37042 | /* 102867 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 37043 | /* 102871 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 37044 | /* 102876 */ // MIs[1] Rn |
| 37045 | /* 102876 */ GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 37046 | /* 102881 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 37047 | /* 102883 */ // (saddsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (saddsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rn)) => (QDADD:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn) |
| 37048 | /* 102883 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QDADD), |
| 37049 | /* 102886 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 37050 | /* 102888 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 37051 | /* 102890 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 37052 | /* 102894 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37053 | /* 102897 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37054 | /* 102903 */ GIR_RootConstrainSelectedInstOperands, |
| 37055 | /* 102904 */ // GIR_Coverage, 1870, |
| 37056 | /* 102904 */ GIR_EraseRootFromParent_Done, |
| 37057 | /* 102905 */ // Label 1929: @102905 |
| 37058 | /* 102905 */ GIM_Try, /*On fail goto*//*Label 1930*/ GIMT_Encode4(102967), // Rule ID 2136 // |
| 37059 | /* 102910 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 37060 | /* 102913 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 37061 | /* 102917 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 37062 | /* 102921 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 37063 | /* 102925 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SADDSAT), |
| 37064 | /* 102929 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 37065 | /* 102933 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 37066 | /* 102938 */ // MIs[1] Rn |
| 37067 | /* 102938 */ GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 37068 | /* 102943 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 37069 | /* 102945 */ // (saddsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (saddsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rn)) => (t2QDADD:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn) |
| 37070 | /* 102945 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QDADD), |
| 37071 | /* 102948 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 37072 | /* 102950 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 37073 | /* 102952 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 37074 | /* 102956 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37075 | /* 102959 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37076 | /* 102965 */ GIR_RootConstrainSelectedInstOperands, |
| 37077 | /* 102966 */ // GIR_Coverage, 2136, |
| 37078 | /* 102966 */ GIR_EraseRootFromParent_Done, |
| 37079 | /* 102967 */ // Label 1930: @102967 |
| 37080 | /* 102967 */ GIM_Try, /*On fail goto*//*Label 1931*/ GIMT_Encode4(103007), // Rule ID 1868 // |
| 37081 | /* 102972 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM), |
| 37082 | /* 102975 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 37083 | /* 102979 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 37084 | /* 102983 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 37085 | /* 102987 */ // (saddsat:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) => (QADD:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) |
| 37086 | /* 102987 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QADD), |
| 37087 | /* 102990 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 37088 | /* 102992 */ GIR_RootToRootCopy, /*OpIdx*/1, // a |
| 37089 | /* 102994 */ GIR_RootToRootCopy, /*OpIdx*/2, // b |
| 37090 | /* 102996 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37091 | /* 102999 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37092 | /* 103005 */ GIR_RootConstrainSelectedInstOperands, |
| 37093 | /* 103006 */ // GIR_Coverage, 1868, |
| 37094 | /* 103006 */ GIR_EraseRootFromParent_Done, |
| 37095 | /* 103007 */ // Label 1931: @103007 |
| 37096 | /* 103007 */ GIM_Try, /*On fail goto*//*Label 1932*/ GIMT_Encode4(103047), // Rule ID 2134 // |
| 37097 | /* 103012 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 37098 | /* 103015 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 37099 | /* 103019 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 37100 | /* 103023 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 37101 | /* 103027 */ // (saddsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn) => (t2QADD:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn) |
| 37102 | /* 103027 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QADD), |
| 37103 | /* 103030 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 37104 | /* 103032 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 37105 | /* 103034 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 37106 | /* 103036 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37107 | /* 103039 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37108 | /* 103045 */ GIR_RootConstrainSelectedInstOperands, |
| 37109 | /* 103046 */ // GIR_Coverage, 2134, |
| 37110 | /* 103046 */ GIR_EraseRootFromParent_Done, |
| 37111 | /* 103047 */ // Label 1932: @103047 |
| 37112 | /* 103047 */ GIM_Reject, |
| 37113 | /* 103048 */ // Label 1926: @103048 |
| 37114 | /* 103048 */ GIM_Reject, |
| 37115 | /* 103049 */ // Label 1917: @103049 |
| 37116 | /* 103049 */ GIM_Try, /*On fail goto*//*Label 1933*/ GIMT_Encode4(103095), // Rule ID 822 // |
| 37117 | /* 103054 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 37118 | /* 103057 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 37119 | /* 103060 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 37120 | /* 103063 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37121 | /* 103067 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37122 | /* 103071 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37123 | /* 103075 */ // (saddsat:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) => (VQADDsv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) |
| 37124 | /* 103075 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDsv1i64), |
| 37125 | /* 103078 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 37126 | /* 103080 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 37127 | /* 103082 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 37128 | /* 103084 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37129 | /* 103087 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37130 | /* 103093 */ GIR_RootConstrainSelectedInstOperands, |
| 37131 | /* 103094 */ // GIR_Coverage, 822, |
| 37132 | /* 103094 */ GIR_EraseRootFromParent_Done, |
| 37133 | /* 103095 */ // Label 1933: @103095 |
| 37134 | /* 103095 */ GIM_Reject, |
| 37135 | /* 103096 */ // Label 1918: @103096 |
| 37136 | /* 103096 */ GIM_Try, /*On fail goto*//*Label 1934*/ GIMT_Encode4(103142), // Rule ID 817 // |
| 37137 | /* 103101 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 37138 | /* 103104 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 37139 | /* 103107 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 37140 | /* 103110 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37141 | /* 103114 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37142 | /* 103118 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37143 | /* 103122 */ // (saddsat:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VQADDsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 37144 | /* 103122 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDsv2i32), |
| 37145 | /* 103125 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 37146 | /* 103127 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 37147 | /* 103129 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 37148 | /* 103131 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37149 | /* 103134 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37150 | /* 103140 */ GIR_RootConstrainSelectedInstOperands, |
| 37151 | /* 103141 */ // GIR_Coverage, 817, |
| 37152 | /* 103141 */ GIR_EraseRootFromParent_Done, |
| 37153 | /* 103142 */ // Label 1934: @103142 |
| 37154 | /* 103142 */ GIM_Reject, |
| 37155 | /* 103143 */ // Label 1919: @103143 |
| 37156 | /* 103143 */ GIM_Try, /*On fail goto*//*Label 1935*/ GIMT_Encode4(103343), |
| 37157 | /* 103148 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 37158 | /* 103151 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 37159 | /* 103154 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37160 | /* 103158 */ GIM_Try, /*On fail goto*//*Label 1936*/ GIMT_Encode4(103232), // Rule ID 5745 // |
| 37161 | /* 103163 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 37162 | /* 103166 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 37163 | /* 103170 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC), |
| 37164 | /* 103174 */ GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 37165 | /* 103177 */ GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqdmull), |
| 37166 | /* 103182 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, |
| 37167 | /* 103186 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32, |
| 37168 | /* 103190 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37169 | /* 103195 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37170 | /* 103200 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37171 | /* 103204 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 37172 | /* 103206 */ // (saddsat:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i64] } 3813:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm), QPR:{ *:[v2i64] }:$src1) => (VQDMLALv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 37173 | /* 103206 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQDMLALv2i64), |
| 37174 | /* 103209 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 37175 | /* 103211 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 37176 | /* 103213 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn |
| 37177 | /* 103217 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm |
| 37178 | /* 103221 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37179 | /* 103224 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37180 | /* 103230 */ GIR_RootConstrainSelectedInstOperands, |
| 37181 | /* 103231 */ // GIR_Coverage, 5745, |
| 37182 | /* 103231 */ GIR_EraseRootFromParent_Done, |
| 37183 | /* 103232 */ // Label 1936: @103232 |
| 37184 | /* 103232 */ GIM_Try, /*On fail goto*//*Label 1937*/ GIMT_Encode4(103306), // Rule ID 2489 // |
| 37185 | /* 103237 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 37186 | /* 103240 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37187 | /* 103244 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 37188 | /* 103248 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC), |
| 37189 | /* 103252 */ GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 37190 | /* 103255 */ GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqdmull), |
| 37191 | /* 103260 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, |
| 37192 | /* 103264 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32, |
| 37193 | /* 103268 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37194 | /* 103273 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37195 | /* 103278 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 37196 | /* 103280 */ // (saddsat:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, (intrinsic_wo_chain:{ *:[v2i64] } 3813:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)) => (VQDMLALv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 37197 | /* 103280 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQDMLALv2i64), |
| 37198 | /* 103283 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 37199 | /* 103285 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 37200 | /* 103287 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn |
| 37201 | /* 103291 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm |
| 37202 | /* 103295 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37203 | /* 103298 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37204 | /* 103304 */ GIR_RootConstrainSelectedInstOperands, |
| 37205 | /* 103305 */ // GIR_Coverage, 2489, |
| 37206 | /* 103305 */ GIR_EraseRootFromParent_Done, |
| 37207 | /* 103306 */ // Label 1937: @103306 |
| 37208 | /* 103306 */ GIM_Try, /*On fail goto*//*Label 1938*/ GIMT_Encode4(103342), // Rule ID 823 // |
| 37209 | /* 103311 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 37210 | /* 103314 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37211 | /* 103318 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37212 | /* 103322 */ // (saddsat:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) => (VQADDsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) |
| 37213 | /* 103322 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDsv2i64), |
| 37214 | /* 103325 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 37215 | /* 103327 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 37216 | /* 103329 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 37217 | /* 103331 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37218 | /* 103334 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37219 | /* 103340 */ GIR_RootConstrainSelectedInstOperands, |
| 37220 | /* 103341 */ // GIR_Coverage, 823, |
| 37221 | /* 103341 */ GIR_EraseRootFromParent_Done, |
| 37222 | /* 103342 */ // Label 1938: @103342 |
| 37223 | /* 103342 */ GIM_Reject, |
| 37224 | /* 103343 */ // Label 1935: @103343 |
| 37225 | /* 103343 */ GIM_Reject, |
| 37226 | /* 103344 */ // Label 1920: @103344 |
| 37227 | /* 103344 */ GIM_Try, /*On fail goto*//*Label 1939*/ GIMT_Encode4(103390), // Rule ID 816 // |
| 37228 | /* 103349 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 37229 | /* 103352 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 37230 | /* 103355 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 37231 | /* 103358 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37232 | /* 103362 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37233 | /* 103366 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37234 | /* 103370 */ // (saddsat:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VQADDsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 37235 | /* 103370 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDsv4i16), |
| 37236 | /* 103373 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 37237 | /* 103375 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 37238 | /* 103377 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 37239 | /* 103379 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37240 | /* 103382 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37241 | /* 103388 */ GIR_RootConstrainSelectedInstOperands, |
| 37242 | /* 103389 */ // GIR_Coverage, 816, |
| 37243 | /* 103389 */ GIR_EraseRootFromParent_Done, |
| 37244 | /* 103390 */ // Label 1939: @103390 |
| 37245 | /* 103390 */ GIM_Reject, |
| 37246 | /* 103391 */ // Label 1921: @103391 |
| 37247 | /* 103391 */ GIM_Try, /*On fail goto*//*Label 1940*/ GIMT_Encode4(103660), |
| 37248 | /* 103396 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 37249 | /* 103399 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 37250 | /* 103402 */ GIM_Try, /*On fail goto*//*Label 1941*/ GIMT_Encode4(103480), // Rule ID 5744 // |
| 37251 | /* 103407 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 37252 | /* 103410 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37253 | /* 103414 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 37254 | /* 103418 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC), |
| 37255 | /* 103422 */ GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 37256 | /* 103425 */ GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqdmull), |
| 37257 | /* 103430 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 37258 | /* 103434 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16, |
| 37259 | /* 103438 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37260 | /* 103443 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37261 | /* 103448 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37262 | /* 103452 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 37263 | /* 103454 */ // (saddsat:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i32] } 3813:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm), QPR:{ *:[v4i32] }:$src1) => (VQDMLALv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 37264 | /* 103454 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQDMLALv4i32), |
| 37265 | /* 103457 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 37266 | /* 103459 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 37267 | /* 103461 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn |
| 37268 | /* 103465 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm |
| 37269 | /* 103469 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37270 | /* 103472 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37271 | /* 103478 */ GIR_RootConstrainSelectedInstOperands, |
| 37272 | /* 103479 */ // GIR_Coverage, 5744, |
| 37273 | /* 103479 */ GIR_EraseRootFromParent_Done, |
| 37274 | /* 103480 */ // Label 1941: @103480 |
| 37275 | /* 103480 */ GIM_Try, /*On fail goto*//*Label 1942*/ GIMT_Encode4(103558), // Rule ID 2488 // |
| 37276 | /* 103485 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 37277 | /* 103488 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37278 | /* 103492 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37279 | /* 103496 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 37280 | /* 103500 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC), |
| 37281 | /* 103504 */ GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 37282 | /* 103507 */ GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqdmull), |
| 37283 | /* 103512 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 37284 | /* 103516 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16, |
| 37285 | /* 103520 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37286 | /* 103525 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37287 | /* 103530 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 37288 | /* 103532 */ // (saddsat:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (intrinsic_wo_chain:{ *:[v4i32] } 3813:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)) => (VQDMLALv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 37289 | /* 103532 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQDMLALv4i32), |
| 37290 | /* 103535 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 37291 | /* 103537 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 37292 | /* 103539 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn |
| 37293 | /* 103543 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm |
| 37294 | /* 103547 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37295 | /* 103550 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37296 | /* 103556 */ GIR_RootConstrainSelectedInstOperands, |
| 37297 | /* 103557 */ // GIR_Coverage, 2488, |
| 37298 | /* 103557 */ GIR_EraseRootFromParent_Done, |
| 37299 | /* 103558 */ // Label 1942: @103558 |
| 37300 | /* 103558 */ GIM_Try, /*On fail goto*//*Label 1943*/ GIMT_Encode4(103598), // Rule ID 819 // |
| 37301 | /* 103563 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 37302 | /* 103566 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37303 | /* 103570 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37304 | /* 103574 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37305 | /* 103578 */ // (saddsat:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VQADDsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 37306 | /* 103578 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDsv4i32), |
| 37307 | /* 103581 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 37308 | /* 103583 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 37309 | /* 103585 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 37310 | /* 103587 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37311 | /* 103590 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37312 | /* 103596 */ GIR_RootConstrainSelectedInstOperands, |
| 37313 | /* 103597 */ // GIR_Coverage, 819, |
| 37314 | /* 103597 */ GIR_EraseRootFromParent_Done, |
| 37315 | /* 103598 */ // Label 1943: @103598 |
| 37316 | /* 103598 */ GIM_Try, /*On fail goto*//*Label 1944*/ GIMT_Encode4(103659), // Rule ID 3518 // |
| 37317 | /* 103603 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 37318 | /* 103606 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37319 | /* 103610 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37320 | /* 103614 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37321 | /* 103618 */ // (saddsat:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VQADDs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 37322 | /* 103618 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 37323 | /* 103621 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 37324 | /* 103625 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 37325 | /* 103630 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQADDs32), |
| 37326 | /* 103633 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 37327 | /* 103635 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 37328 | /* 103637 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 37329 | /* 103639 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 37330 | /* 103642 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37331 | /* 103648 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37332 | /* 103654 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 37333 | /* 103657 */ GIR_RootConstrainSelectedInstOperands, |
| 37334 | /* 103658 */ // GIR_Coverage, 3518, |
| 37335 | /* 103658 */ GIR_EraseRootFromParent_Done, |
| 37336 | /* 103659 */ // Label 1944: @103659 |
| 37337 | /* 103659 */ GIM_Reject, |
| 37338 | /* 103660 */ // Label 1940: @103660 |
| 37339 | /* 103660 */ GIM_Reject, |
| 37340 | /* 103661 */ // Label 1922: @103661 |
| 37341 | /* 103661 */ GIM_Try, /*On fail goto*//*Label 1945*/ GIMT_Encode4(103707), // Rule ID 820 // |
| 37342 | /* 103666 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 37343 | /* 103669 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 37344 | /* 103672 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 37345 | /* 103675 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37346 | /* 103679 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37347 | /* 103683 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37348 | /* 103687 */ // (saddsat:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VQADDsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 37349 | /* 103687 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDsv8i8), |
| 37350 | /* 103690 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 37351 | /* 103692 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 37352 | /* 103694 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 37353 | /* 103696 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37354 | /* 103699 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37355 | /* 103705 */ GIR_RootConstrainSelectedInstOperands, |
| 37356 | /* 103706 */ // GIR_Coverage, 820, |
| 37357 | /* 103706 */ GIR_EraseRootFromParent_Done, |
| 37358 | /* 103707 */ // Label 1945: @103707 |
| 37359 | /* 103707 */ GIM_Reject, |
| 37360 | /* 103708 */ // Label 1923: @103708 |
| 37361 | /* 103708 */ GIM_Try, /*On fail goto*//*Label 1946*/ GIMT_Encode4(103821), |
| 37362 | /* 103713 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 37363 | /* 103716 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 37364 | /* 103719 */ GIM_Try, /*On fail goto*//*Label 1947*/ GIMT_Encode4(103759), // Rule ID 818 // |
| 37365 | /* 103724 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 37366 | /* 103727 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37367 | /* 103731 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37368 | /* 103735 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37369 | /* 103739 */ // (saddsat:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VQADDsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 37370 | /* 103739 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDsv8i16), |
| 37371 | /* 103742 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 37372 | /* 103744 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 37373 | /* 103746 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 37374 | /* 103748 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37375 | /* 103751 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37376 | /* 103757 */ GIR_RootConstrainSelectedInstOperands, |
| 37377 | /* 103758 */ // GIR_Coverage, 818, |
| 37378 | /* 103758 */ GIR_EraseRootFromParent_Done, |
| 37379 | /* 103759 */ // Label 1947: @103759 |
| 37380 | /* 103759 */ GIM_Try, /*On fail goto*//*Label 1948*/ GIMT_Encode4(103820), // Rule ID 3515 // |
| 37381 | /* 103764 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 37382 | /* 103767 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37383 | /* 103771 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37384 | /* 103775 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37385 | /* 103779 */ // (saddsat:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VQADDs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 37386 | /* 103779 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 37387 | /* 103782 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 37388 | /* 103786 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 37389 | /* 103791 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQADDs16), |
| 37390 | /* 103794 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 37391 | /* 103796 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 37392 | /* 103798 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 37393 | /* 103800 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 37394 | /* 103803 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37395 | /* 103809 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37396 | /* 103815 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 37397 | /* 103818 */ GIR_RootConstrainSelectedInstOperands, |
| 37398 | /* 103819 */ // GIR_Coverage, 3515, |
| 37399 | /* 103819 */ GIR_EraseRootFromParent_Done, |
| 37400 | /* 103820 */ // Label 1948: @103820 |
| 37401 | /* 103820 */ GIM_Reject, |
| 37402 | /* 103821 */ // Label 1946: @103821 |
| 37403 | /* 103821 */ GIM_Reject, |
| 37404 | /* 103822 */ // Label 1924: @103822 |
| 37405 | /* 103822 */ GIM_Try, /*On fail goto*//*Label 1949*/ GIMT_Encode4(103935), |
| 37406 | /* 103827 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 37407 | /* 103830 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 37408 | /* 103833 */ GIM_Try, /*On fail goto*//*Label 1950*/ GIMT_Encode4(103873), // Rule ID 821 // |
| 37409 | /* 103838 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 37410 | /* 103841 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37411 | /* 103845 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37412 | /* 103849 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37413 | /* 103853 */ // (saddsat:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VQADDsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 37414 | /* 103853 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDsv16i8), |
| 37415 | /* 103856 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 37416 | /* 103858 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 37417 | /* 103860 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 37418 | /* 103862 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37419 | /* 103865 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37420 | /* 103871 */ GIR_RootConstrainSelectedInstOperands, |
| 37421 | /* 103872 */ // GIR_Coverage, 821, |
| 37422 | /* 103872 */ GIR_EraseRootFromParent_Done, |
| 37423 | /* 103873 */ // Label 1950: @103873 |
| 37424 | /* 103873 */ GIM_Try, /*On fail goto*//*Label 1951*/ GIMT_Encode4(103934), // Rule ID 3512 // |
| 37425 | /* 103878 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 37426 | /* 103881 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37427 | /* 103885 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37428 | /* 103889 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37429 | /* 103893 */ // (saddsat:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VQADDs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 37430 | /* 103893 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 37431 | /* 103896 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 37432 | /* 103900 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 37433 | /* 103905 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQADDs8), |
| 37434 | /* 103908 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 37435 | /* 103910 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 37436 | /* 103912 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 37437 | /* 103914 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 37438 | /* 103917 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37439 | /* 103923 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37440 | /* 103929 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 37441 | /* 103932 */ GIR_RootConstrainSelectedInstOperands, |
| 37442 | /* 103933 */ // GIR_Coverage, 3512, |
| 37443 | /* 103933 */ GIR_EraseRootFromParent_Done, |
| 37444 | /* 103934 */ // Label 1951: @103934 |
| 37445 | /* 103934 */ GIM_Reject, |
| 37446 | /* 103935 */ // Label 1949: @103935 |
| 37447 | /* 103935 */ GIM_Reject, |
| 37448 | /* 103936 */ // Label 1925: @103936 |
| 37449 | /* 103936 */ GIM_Reject, |
| 37450 | /* 103937 */ // Label 32: @103937 |
| 37451 | /* 103937 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(16), /*)*//*default:*//*Label 1960*/ GIMT_Encode4(104581), |
| 37452 | /* 103948 */ /*GILLT_s64*//*Label 1952*/ GIMT_Encode4(104004), GIMT_Encode4(0), |
| 37453 | /* 103956 */ /*GILLT_v2s32*//*Label 1953*/ GIMT_Encode4(104051), |
| 37454 | /* 103960 */ /*GILLT_v2s64*//*Label 1954*/ GIMT_Encode4(104098), GIMT_Encode4(0), |
| 37455 | /* 103968 */ /*GILLT_v4s16*//*Label 1955*/ GIMT_Encode4(104145), |
| 37456 | /* 103972 */ /*GILLT_v4s32*//*Label 1956*/ GIMT_Encode4(104192), GIMT_Encode4(0), GIMT_Encode4(0), |
| 37457 | /* 103984 */ /*GILLT_v8s8*//*Label 1957*/ GIMT_Encode4(104306), |
| 37458 | /* 103988 */ /*GILLT_v8s16*//*Label 1958*/ GIMT_Encode4(104353), GIMT_Encode4(0), GIMT_Encode4(0), |
| 37459 | /* 104000 */ /*GILLT_v16s8*//*Label 1959*/ GIMT_Encode4(104467), |
| 37460 | /* 104004 */ // Label 1952: @104004 |
| 37461 | /* 104004 */ GIM_Try, /*On fail goto*//*Label 1961*/ GIMT_Encode4(104050), // Rule ID 1022 // |
| 37462 | /* 104009 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 37463 | /* 104012 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 37464 | /* 104015 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 37465 | /* 104018 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37466 | /* 104022 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37467 | /* 104026 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37468 | /* 104030 */ // (usubsat:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) => (VQSUBuv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) |
| 37469 | /* 104030 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBuv1i64), |
| 37470 | /* 104033 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 37471 | /* 104035 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 37472 | /* 104037 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 37473 | /* 104039 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37474 | /* 104042 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37475 | /* 104048 */ GIR_RootConstrainSelectedInstOperands, |
| 37476 | /* 104049 */ // GIR_Coverage, 1022, |
| 37477 | /* 104049 */ GIR_EraseRootFromParent_Done, |
| 37478 | /* 104050 */ // Label 1961: @104050 |
| 37479 | /* 104050 */ GIM_Reject, |
| 37480 | /* 104051 */ // Label 1953: @104051 |
| 37481 | /* 104051 */ GIM_Try, /*On fail goto*//*Label 1962*/ GIMT_Encode4(104097), // Rule ID 1017 // |
| 37482 | /* 104056 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 37483 | /* 104059 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 37484 | /* 104062 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 37485 | /* 104065 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37486 | /* 104069 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37487 | /* 104073 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37488 | /* 104077 */ // (usubsat:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VQSUBuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 37489 | /* 104077 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBuv2i32), |
| 37490 | /* 104080 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 37491 | /* 104082 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 37492 | /* 104084 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 37493 | /* 104086 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37494 | /* 104089 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37495 | /* 104095 */ GIR_RootConstrainSelectedInstOperands, |
| 37496 | /* 104096 */ // GIR_Coverage, 1017, |
| 37497 | /* 104096 */ GIR_EraseRootFromParent_Done, |
| 37498 | /* 104097 */ // Label 1962: @104097 |
| 37499 | /* 104097 */ GIM_Reject, |
| 37500 | /* 104098 */ // Label 1954: @104098 |
| 37501 | /* 104098 */ GIM_Try, /*On fail goto*//*Label 1963*/ GIMT_Encode4(104144), // Rule ID 1023 // |
| 37502 | /* 104103 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 37503 | /* 104106 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 37504 | /* 104109 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 37505 | /* 104112 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37506 | /* 104116 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37507 | /* 104120 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37508 | /* 104124 */ // (usubsat:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) => (VQSUBuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) |
| 37509 | /* 104124 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBuv2i64), |
| 37510 | /* 104127 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 37511 | /* 104129 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 37512 | /* 104131 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 37513 | /* 104133 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37514 | /* 104136 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37515 | /* 104142 */ GIR_RootConstrainSelectedInstOperands, |
| 37516 | /* 104143 */ // GIR_Coverage, 1023, |
| 37517 | /* 104143 */ GIR_EraseRootFromParent_Done, |
| 37518 | /* 104144 */ // Label 1963: @104144 |
| 37519 | /* 104144 */ GIM_Reject, |
| 37520 | /* 104145 */ // Label 1955: @104145 |
| 37521 | /* 104145 */ GIM_Try, /*On fail goto*//*Label 1964*/ GIMT_Encode4(104191), // Rule ID 1016 // |
| 37522 | /* 104150 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 37523 | /* 104153 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 37524 | /* 104156 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 37525 | /* 104159 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37526 | /* 104163 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37527 | /* 104167 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37528 | /* 104171 */ // (usubsat:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VQSUBuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 37529 | /* 104171 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBuv4i16), |
| 37530 | /* 104174 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 37531 | /* 104176 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 37532 | /* 104178 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 37533 | /* 104180 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37534 | /* 104183 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37535 | /* 104189 */ GIR_RootConstrainSelectedInstOperands, |
| 37536 | /* 104190 */ // GIR_Coverage, 1016, |
| 37537 | /* 104190 */ GIR_EraseRootFromParent_Done, |
| 37538 | /* 104191 */ // Label 1964: @104191 |
| 37539 | /* 104191 */ GIM_Reject, |
| 37540 | /* 104192 */ // Label 1956: @104192 |
| 37541 | /* 104192 */ GIM_Try, /*On fail goto*//*Label 1965*/ GIMT_Encode4(104305), |
| 37542 | /* 104197 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 37543 | /* 104200 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 37544 | /* 104203 */ GIM_Try, /*On fail goto*//*Label 1966*/ GIMT_Encode4(104243), // Rule ID 1019 // |
| 37545 | /* 104208 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 37546 | /* 104211 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37547 | /* 104215 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37548 | /* 104219 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37549 | /* 104223 */ // (usubsat:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VQSUBuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 37550 | /* 104223 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBuv4i32), |
| 37551 | /* 104226 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 37552 | /* 104228 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 37553 | /* 104230 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 37554 | /* 104232 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37555 | /* 104235 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37556 | /* 104241 */ GIR_RootConstrainSelectedInstOperands, |
| 37557 | /* 104242 */ // GIR_Coverage, 1019, |
| 37558 | /* 104242 */ GIR_EraseRootFromParent_Done, |
| 37559 | /* 104243 */ // Label 1966: @104243 |
| 37560 | /* 104243 */ GIM_Try, /*On fail goto*//*Label 1967*/ GIMT_Encode4(104304), // Rule ID 3545 // |
| 37561 | /* 104248 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 37562 | /* 104251 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37563 | /* 104255 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37564 | /* 104259 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37565 | /* 104263 */ // (usubsat:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VQSUBu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 37566 | /* 104263 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 37567 | /* 104266 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 37568 | /* 104270 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 37569 | /* 104275 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSUBu32), |
| 37570 | /* 104278 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 37571 | /* 104280 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 37572 | /* 104282 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 37573 | /* 104284 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 37574 | /* 104287 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37575 | /* 104293 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37576 | /* 104299 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 37577 | /* 104302 */ GIR_RootConstrainSelectedInstOperands, |
| 37578 | /* 104303 */ // GIR_Coverage, 3545, |
| 37579 | /* 104303 */ GIR_EraseRootFromParent_Done, |
| 37580 | /* 104304 */ // Label 1967: @104304 |
| 37581 | /* 104304 */ GIM_Reject, |
| 37582 | /* 104305 */ // Label 1965: @104305 |
| 37583 | /* 104305 */ GIM_Reject, |
| 37584 | /* 104306 */ // Label 1957: @104306 |
| 37585 | /* 104306 */ GIM_Try, /*On fail goto*//*Label 1968*/ GIMT_Encode4(104352), // Rule ID 1020 // |
| 37586 | /* 104311 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 37587 | /* 104314 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 37588 | /* 104317 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 37589 | /* 104320 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37590 | /* 104324 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37591 | /* 104328 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37592 | /* 104332 */ // (usubsat:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VQSUBuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 37593 | /* 104332 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBuv8i8), |
| 37594 | /* 104335 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 37595 | /* 104337 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 37596 | /* 104339 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 37597 | /* 104341 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37598 | /* 104344 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37599 | /* 104350 */ GIR_RootConstrainSelectedInstOperands, |
| 37600 | /* 104351 */ // GIR_Coverage, 1020, |
| 37601 | /* 104351 */ GIR_EraseRootFromParent_Done, |
| 37602 | /* 104352 */ // Label 1968: @104352 |
| 37603 | /* 104352 */ GIM_Reject, |
| 37604 | /* 104353 */ // Label 1958: @104353 |
| 37605 | /* 104353 */ GIM_Try, /*On fail goto*//*Label 1969*/ GIMT_Encode4(104466), |
| 37606 | /* 104358 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 37607 | /* 104361 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 37608 | /* 104364 */ GIM_Try, /*On fail goto*//*Label 1970*/ GIMT_Encode4(104404), // Rule ID 1018 // |
| 37609 | /* 104369 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 37610 | /* 104372 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37611 | /* 104376 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37612 | /* 104380 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37613 | /* 104384 */ // (usubsat:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VQSUBuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 37614 | /* 104384 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBuv8i16), |
| 37615 | /* 104387 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 37616 | /* 104389 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 37617 | /* 104391 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 37618 | /* 104393 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37619 | /* 104396 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37620 | /* 104402 */ GIR_RootConstrainSelectedInstOperands, |
| 37621 | /* 104403 */ // GIR_Coverage, 1018, |
| 37622 | /* 104403 */ GIR_EraseRootFromParent_Done, |
| 37623 | /* 104404 */ // Label 1970: @104404 |
| 37624 | /* 104404 */ GIM_Try, /*On fail goto*//*Label 1971*/ GIMT_Encode4(104465), // Rule ID 3542 // |
| 37625 | /* 104409 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 37626 | /* 104412 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37627 | /* 104416 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37628 | /* 104420 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37629 | /* 104424 */ // (usubsat:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VQSUBu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 37630 | /* 104424 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 37631 | /* 104427 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 37632 | /* 104431 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 37633 | /* 104436 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSUBu16), |
| 37634 | /* 104439 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 37635 | /* 104441 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 37636 | /* 104443 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 37637 | /* 104445 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 37638 | /* 104448 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37639 | /* 104454 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37640 | /* 104460 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 37641 | /* 104463 */ GIR_RootConstrainSelectedInstOperands, |
| 37642 | /* 104464 */ // GIR_Coverage, 3542, |
| 37643 | /* 104464 */ GIR_EraseRootFromParent_Done, |
| 37644 | /* 104465 */ // Label 1971: @104465 |
| 37645 | /* 104465 */ GIM_Reject, |
| 37646 | /* 104466 */ // Label 1969: @104466 |
| 37647 | /* 104466 */ GIM_Reject, |
| 37648 | /* 104467 */ // Label 1959: @104467 |
| 37649 | /* 104467 */ GIM_Try, /*On fail goto*//*Label 1972*/ GIMT_Encode4(104580), |
| 37650 | /* 104472 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 37651 | /* 104475 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 37652 | /* 104478 */ GIM_Try, /*On fail goto*//*Label 1973*/ GIMT_Encode4(104518), // Rule ID 1021 // |
| 37653 | /* 104483 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 37654 | /* 104486 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37655 | /* 104490 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37656 | /* 104494 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37657 | /* 104498 */ // (usubsat:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VQSUBuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 37658 | /* 104498 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBuv16i8), |
| 37659 | /* 104501 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 37660 | /* 104503 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 37661 | /* 104505 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 37662 | /* 104507 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37663 | /* 104510 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37664 | /* 104516 */ GIR_RootConstrainSelectedInstOperands, |
| 37665 | /* 104517 */ // GIR_Coverage, 1021, |
| 37666 | /* 104517 */ GIR_EraseRootFromParent_Done, |
| 37667 | /* 104518 */ // Label 1973: @104518 |
| 37668 | /* 104518 */ GIM_Try, /*On fail goto*//*Label 1974*/ GIMT_Encode4(104579), // Rule ID 3539 // |
| 37669 | /* 104523 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 37670 | /* 104526 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37671 | /* 104530 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37672 | /* 104534 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37673 | /* 104538 */ // (usubsat:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VQSUBu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 37674 | /* 104538 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 37675 | /* 104541 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 37676 | /* 104545 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 37677 | /* 104550 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSUBu8), |
| 37678 | /* 104553 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 37679 | /* 104555 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 37680 | /* 104557 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 37681 | /* 104559 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 37682 | /* 104562 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37683 | /* 104568 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37684 | /* 104574 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 37685 | /* 104577 */ GIR_RootConstrainSelectedInstOperands, |
| 37686 | /* 104578 */ // GIR_Coverage, 3539, |
| 37687 | /* 104578 */ GIR_EraseRootFromParent_Done, |
| 37688 | /* 104579 */ // Label 1974: @104579 |
| 37689 | /* 104579 */ GIM_Reject, |
| 37690 | /* 104580 */ // Label 1972: @104580 |
| 37691 | /* 104580 */ GIM_Reject, |
| 37692 | /* 104581 */ // Label 1960: @104581 |
| 37693 | /* 104581 */ GIM_Reject, |
| 37694 | /* 104582 */ // Label 33: @104582 |
| 37695 | /* 104582 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(16), /*)*//*default:*//*Label 1984*/ GIMT_Encode4(105601), |
| 37696 | /* 104593 */ /*GILLT_s32*//*Label 1975*/ GIMT_Encode4(104653), |
| 37697 | /* 104597 */ /*GILLT_s64*//*Label 1976*/ GIMT_Encode4(104870), GIMT_Encode4(0), |
| 37698 | /* 104605 */ /*GILLT_v2s32*//*Label 1977*/ GIMT_Encode4(104917), |
| 37699 | /* 104609 */ /*GILLT_v2s64*//*Label 1978*/ GIMT_Encode4(104964), GIMT_Encode4(0), |
| 37700 | /* 104617 */ /*GILLT_v4s16*//*Label 1979*/ GIMT_Encode4(105087), |
| 37701 | /* 104621 */ /*GILLT_v4s32*//*Label 1980*/ GIMT_Encode4(105134), GIMT_Encode4(0), GIMT_Encode4(0), |
| 37702 | /* 104633 */ /*GILLT_v8s8*//*Label 1981*/ GIMT_Encode4(105326), |
| 37703 | /* 104637 */ /*GILLT_v8s16*//*Label 1982*/ GIMT_Encode4(105373), GIMT_Encode4(0), GIMT_Encode4(0), |
| 37704 | /* 104649 */ /*GILLT_v16s8*//*Label 1983*/ GIMT_Encode4(105487), |
| 37705 | /* 104653 */ // Label 1975: @104653 |
| 37706 | /* 104653 */ GIM_Try, /*On fail goto*//*Label 1985*/ GIMT_Encode4(104869), |
| 37707 | /* 104658 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 37708 | /* 104661 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 37709 | /* 104664 */ GIM_Try, /*On fail goto*//*Label 1986*/ GIMT_Encode4(104726), // Rule ID 1871 // |
| 37710 | /* 104669 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM), |
| 37711 | /* 104672 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 37712 | /* 104676 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 37713 | /* 104680 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 37714 | /* 104684 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SADDSAT), |
| 37715 | /* 104688 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 37716 | /* 104692 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 37717 | /* 104697 */ // MIs[1] Rn |
| 37718 | /* 104697 */ GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 37719 | /* 104702 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 37720 | /* 104704 */ // (ssubsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (saddsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rn)) => (QDSUB:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn) |
| 37721 | /* 104704 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QDSUB), |
| 37722 | /* 104707 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 37723 | /* 104709 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 37724 | /* 104711 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 37725 | /* 104715 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37726 | /* 104718 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37727 | /* 104724 */ GIR_RootConstrainSelectedInstOperands, |
| 37728 | /* 104725 */ // GIR_Coverage, 1871, |
| 37729 | /* 104725 */ GIR_EraseRootFromParent_Done, |
| 37730 | /* 104726 */ // Label 1986: @104726 |
| 37731 | /* 104726 */ GIM_Try, /*On fail goto*//*Label 1987*/ GIMT_Encode4(104788), // Rule ID 2137 // |
| 37732 | /* 104731 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 37733 | /* 104734 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 37734 | /* 104738 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 37735 | /* 104742 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 37736 | /* 104746 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SADDSAT), |
| 37737 | /* 104750 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 37738 | /* 104754 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 37739 | /* 104759 */ // MIs[1] Rn |
| 37740 | /* 104759 */ GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 37741 | /* 104764 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 37742 | /* 104766 */ // (ssubsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (saddsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rn)) => (t2QDSUB:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn) |
| 37743 | /* 104766 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QDSUB), |
| 37744 | /* 104769 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 37745 | /* 104771 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 37746 | /* 104773 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 37747 | /* 104777 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37748 | /* 104780 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37749 | /* 104786 */ GIR_RootConstrainSelectedInstOperands, |
| 37750 | /* 104787 */ // GIR_Coverage, 2137, |
| 37751 | /* 104787 */ GIR_EraseRootFromParent_Done, |
| 37752 | /* 104788 */ // Label 1987: @104788 |
| 37753 | /* 104788 */ GIM_Try, /*On fail goto*//*Label 1988*/ GIMT_Encode4(104828), // Rule ID 1869 // |
| 37754 | /* 104793 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM), |
| 37755 | /* 104796 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 37756 | /* 104800 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 37757 | /* 104804 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 37758 | /* 104808 */ // (ssubsat:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) => (QSUB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) |
| 37759 | /* 104808 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QSUB), |
| 37760 | /* 104811 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 37761 | /* 104813 */ GIR_RootToRootCopy, /*OpIdx*/1, // a |
| 37762 | /* 104815 */ GIR_RootToRootCopy, /*OpIdx*/2, // b |
| 37763 | /* 104817 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37764 | /* 104820 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37765 | /* 104826 */ GIR_RootConstrainSelectedInstOperands, |
| 37766 | /* 104827 */ // GIR_Coverage, 1869, |
| 37767 | /* 104827 */ GIR_EraseRootFromParent_Done, |
| 37768 | /* 104828 */ // Label 1988: @104828 |
| 37769 | /* 104828 */ GIM_Try, /*On fail goto*//*Label 1989*/ GIMT_Encode4(104868), // Rule ID 2135 // |
| 37770 | /* 104833 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2), |
| 37771 | /* 104836 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 37772 | /* 104840 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 37773 | /* 104844 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 37774 | /* 104848 */ // (ssubsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn) => (t2QSUB:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn) |
| 37775 | /* 104848 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QSUB), |
| 37776 | /* 104851 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 37777 | /* 104853 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 37778 | /* 104855 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 37779 | /* 104857 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37780 | /* 104860 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37781 | /* 104866 */ GIR_RootConstrainSelectedInstOperands, |
| 37782 | /* 104867 */ // GIR_Coverage, 2135, |
| 37783 | /* 104867 */ GIR_EraseRootFromParent_Done, |
| 37784 | /* 104868 */ // Label 1989: @104868 |
| 37785 | /* 104868 */ GIM_Reject, |
| 37786 | /* 104869 */ // Label 1985: @104869 |
| 37787 | /* 104869 */ GIM_Reject, |
| 37788 | /* 104870 */ // Label 1976: @104870 |
| 37789 | /* 104870 */ GIM_Try, /*On fail goto*//*Label 1990*/ GIMT_Encode4(104916), // Rule ID 1014 // |
| 37790 | /* 104875 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 37791 | /* 104878 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 37792 | /* 104881 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 37793 | /* 104884 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37794 | /* 104888 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37795 | /* 104892 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37796 | /* 104896 */ // (ssubsat:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) => (VQSUBsv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) |
| 37797 | /* 104896 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBsv1i64), |
| 37798 | /* 104899 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 37799 | /* 104901 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 37800 | /* 104903 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 37801 | /* 104905 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37802 | /* 104908 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37803 | /* 104914 */ GIR_RootConstrainSelectedInstOperands, |
| 37804 | /* 104915 */ // GIR_Coverage, 1014, |
| 37805 | /* 104915 */ GIR_EraseRootFromParent_Done, |
| 37806 | /* 104916 */ // Label 1990: @104916 |
| 37807 | /* 104916 */ GIM_Reject, |
| 37808 | /* 104917 */ // Label 1977: @104917 |
| 37809 | /* 104917 */ GIM_Try, /*On fail goto*//*Label 1991*/ GIMT_Encode4(104963), // Rule ID 1009 // |
| 37810 | /* 104922 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 37811 | /* 104925 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 37812 | /* 104928 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 37813 | /* 104931 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37814 | /* 104935 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37815 | /* 104939 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37816 | /* 104943 */ // (ssubsat:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VQSUBsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 37817 | /* 104943 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBsv2i32), |
| 37818 | /* 104946 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 37819 | /* 104948 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 37820 | /* 104950 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 37821 | /* 104952 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37822 | /* 104955 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37823 | /* 104961 */ GIR_RootConstrainSelectedInstOperands, |
| 37824 | /* 104962 */ // GIR_Coverage, 1009, |
| 37825 | /* 104962 */ GIR_EraseRootFromParent_Done, |
| 37826 | /* 104963 */ // Label 1991: @104963 |
| 37827 | /* 104963 */ GIM_Reject, |
| 37828 | /* 104964 */ // Label 1978: @104964 |
| 37829 | /* 104964 */ GIM_Try, /*On fail goto*//*Label 1992*/ GIMT_Encode4(105086), |
| 37830 | /* 104969 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 37831 | /* 104972 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 37832 | /* 104975 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37833 | /* 104979 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37834 | /* 104983 */ GIM_Try, /*On fail goto*//*Label 1993*/ GIMT_Encode4(105053), // Rule ID 2496 // |
| 37835 | /* 104988 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 37836 | /* 104991 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 37837 | /* 104995 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC), |
| 37838 | /* 104999 */ GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 37839 | /* 105002 */ GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqdmull), |
| 37840 | /* 105007 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, |
| 37841 | /* 105011 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32, |
| 37842 | /* 105015 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37843 | /* 105020 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37844 | /* 105025 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 37845 | /* 105027 */ // (ssubsat:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, (intrinsic_wo_chain:{ *:[v2i64] } 3813:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)) => (VQDMLSLv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 37846 | /* 105027 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQDMLSLv2i64), |
| 37847 | /* 105030 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 37848 | /* 105032 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 37849 | /* 105034 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn |
| 37850 | /* 105038 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm |
| 37851 | /* 105042 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37852 | /* 105045 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37853 | /* 105051 */ GIR_RootConstrainSelectedInstOperands, |
| 37854 | /* 105052 */ // GIR_Coverage, 2496, |
| 37855 | /* 105052 */ GIR_EraseRootFromParent_Done, |
| 37856 | /* 105053 */ // Label 1993: @105053 |
| 37857 | /* 105053 */ GIM_Try, /*On fail goto*//*Label 1994*/ GIMT_Encode4(105085), // Rule ID 1015 // |
| 37858 | /* 105058 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 37859 | /* 105061 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37860 | /* 105065 */ // (ssubsat:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) => (VQSUBsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) |
| 37861 | /* 105065 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBsv2i64), |
| 37862 | /* 105068 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 37863 | /* 105070 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 37864 | /* 105072 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 37865 | /* 105074 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37866 | /* 105077 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37867 | /* 105083 */ GIR_RootConstrainSelectedInstOperands, |
| 37868 | /* 105084 */ // GIR_Coverage, 1015, |
| 37869 | /* 105084 */ GIR_EraseRootFromParent_Done, |
| 37870 | /* 105085 */ // Label 1994: @105085 |
| 37871 | /* 105085 */ GIM_Reject, |
| 37872 | /* 105086 */ // Label 1992: @105086 |
| 37873 | /* 105086 */ GIM_Reject, |
| 37874 | /* 105087 */ // Label 1979: @105087 |
| 37875 | /* 105087 */ GIM_Try, /*On fail goto*//*Label 1995*/ GIMT_Encode4(105133), // Rule ID 1008 // |
| 37876 | /* 105092 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 37877 | /* 105095 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 37878 | /* 105098 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 37879 | /* 105101 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37880 | /* 105105 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37881 | /* 105109 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37882 | /* 105113 */ // (ssubsat:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VQSUBsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 37883 | /* 105113 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBsv4i16), |
| 37884 | /* 105116 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 37885 | /* 105118 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 37886 | /* 105120 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 37887 | /* 105122 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37888 | /* 105125 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37889 | /* 105131 */ GIR_RootConstrainSelectedInstOperands, |
| 37890 | /* 105132 */ // GIR_Coverage, 1008, |
| 37891 | /* 105132 */ GIR_EraseRootFromParent_Done, |
| 37892 | /* 105133 */ // Label 1995: @105133 |
| 37893 | /* 105133 */ GIM_Reject, |
| 37894 | /* 105134 */ // Label 1980: @105134 |
| 37895 | /* 105134 */ GIM_Try, /*On fail goto*//*Label 1996*/ GIMT_Encode4(105325), |
| 37896 | /* 105139 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 37897 | /* 105142 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 37898 | /* 105145 */ GIM_Try, /*On fail goto*//*Label 1997*/ GIMT_Encode4(105223), // Rule ID 2495 // |
| 37899 | /* 105150 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 37900 | /* 105153 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37901 | /* 105157 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37902 | /* 105161 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 37903 | /* 105165 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC), |
| 37904 | /* 105169 */ GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 37905 | /* 105172 */ GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqdmull), |
| 37906 | /* 105177 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 37907 | /* 105181 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16, |
| 37908 | /* 105185 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37909 | /* 105190 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37910 | /* 105195 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 37911 | /* 105197 */ // (ssubsat:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (intrinsic_wo_chain:{ *:[v4i32] } 3813:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)) => (VQDMLSLv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 37912 | /* 105197 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQDMLSLv4i32), |
| 37913 | /* 105200 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 37914 | /* 105202 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 37915 | /* 105204 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn |
| 37916 | /* 105208 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm |
| 37917 | /* 105212 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37918 | /* 105215 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37919 | /* 105221 */ GIR_RootConstrainSelectedInstOperands, |
| 37920 | /* 105222 */ // GIR_Coverage, 2495, |
| 37921 | /* 105222 */ GIR_EraseRootFromParent_Done, |
| 37922 | /* 105223 */ // Label 1997: @105223 |
| 37923 | /* 105223 */ GIM_Try, /*On fail goto*//*Label 1998*/ GIMT_Encode4(105263), // Rule ID 1011 // |
| 37924 | /* 105228 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 37925 | /* 105231 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37926 | /* 105235 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37927 | /* 105239 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37928 | /* 105243 */ // (ssubsat:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VQSUBsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 37929 | /* 105243 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBsv4i32), |
| 37930 | /* 105246 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 37931 | /* 105248 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 37932 | /* 105250 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 37933 | /* 105252 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37934 | /* 105255 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37935 | /* 105261 */ GIR_RootConstrainSelectedInstOperands, |
| 37936 | /* 105262 */ // GIR_Coverage, 1011, |
| 37937 | /* 105262 */ GIR_EraseRootFromParent_Done, |
| 37938 | /* 105263 */ // Label 1998: @105263 |
| 37939 | /* 105263 */ GIM_Try, /*On fail goto*//*Label 1999*/ GIMT_Encode4(105324), // Rule ID 3536 // |
| 37940 | /* 105268 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 37941 | /* 105271 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37942 | /* 105275 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37943 | /* 105279 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37944 | /* 105283 */ // (ssubsat:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VQSUBs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 37945 | /* 105283 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 37946 | /* 105286 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 37947 | /* 105290 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 37948 | /* 105295 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSUBs32), |
| 37949 | /* 105298 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 37950 | /* 105300 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 37951 | /* 105302 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 37952 | /* 105304 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 37953 | /* 105307 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37954 | /* 105313 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37955 | /* 105319 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 37956 | /* 105322 */ GIR_RootConstrainSelectedInstOperands, |
| 37957 | /* 105323 */ // GIR_Coverage, 3536, |
| 37958 | /* 105323 */ GIR_EraseRootFromParent_Done, |
| 37959 | /* 105324 */ // Label 1999: @105324 |
| 37960 | /* 105324 */ GIM_Reject, |
| 37961 | /* 105325 */ // Label 1996: @105325 |
| 37962 | /* 105325 */ GIM_Reject, |
| 37963 | /* 105326 */ // Label 1981: @105326 |
| 37964 | /* 105326 */ GIM_Try, /*On fail goto*//*Label 2000*/ GIMT_Encode4(105372), // Rule ID 1012 // |
| 37965 | /* 105331 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 37966 | /* 105334 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 37967 | /* 105337 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 37968 | /* 105340 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37969 | /* 105344 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37970 | /* 105348 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37971 | /* 105352 */ // (ssubsat:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VQSUBsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 37972 | /* 105352 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBsv8i8), |
| 37973 | /* 105355 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 37974 | /* 105357 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 37975 | /* 105359 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 37976 | /* 105361 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37977 | /* 105364 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37978 | /* 105370 */ GIR_RootConstrainSelectedInstOperands, |
| 37979 | /* 105371 */ // GIR_Coverage, 1012, |
| 37980 | /* 105371 */ GIR_EraseRootFromParent_Done, |
| 37981 | /* 105372 */ // Label 2000: @105372 |
| 37982 | /* 105372 */ GIM_Reject, |
| 37983 | /* 105373 */ // Label 1982: @105373 |
| 37984 | /* 105373 */ GIM_Try, /*On fail goto*//*Label 2001*/ GIMT_Encode4(105486), |
| 37985 | /* 105378 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 37986 | /* 105381 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 37987 | /* 105384 */ GIM_Try, /*On fail goto*//*Label 2002*/ GIMT_Encode4(105424), // Rule ID 1010 // |
| 37988 | /* 105389 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 37989 | /* 105392 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37990 | /* 105396 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37991 | /* 105400 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37992 | /* 105404 */ // (ssubsat:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VQSUBsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 37993 | /* 105404 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBsv8i16), |
| 37994 | /* 105407 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 37995 | /* 105409 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 37996 | /* 105411 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 37997 | /* 105413 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37998 | /* 105416 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37999 | /* 105422 */ GIR_RootConstrainSelectedInstOperands, |
| 38000 | /* 105423 */ // GIR_Coverage, 1010, |
| 38001 | /* 105423 */ GIR_EraseRootFromParent_Done, |
| 38002 | /* 105424 */ // Label 2002: @105424 |
| 38003 | /* 105424 */ GIM_Try, /*On fail goto*//*Label 2003*/ GIMT_Encode4(105485), // Rule ID 3533 // |
| 38004 | /* 105429 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 38005 | /* 105432 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 38006 | /* 105436 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 38007 | /* 105440 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 38008 | /* 105444 */ // (ssubsat:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VQSUBs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 38009 | /* 105444 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 38010 | /* 105447 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 38011 | /* 105451 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38012 | /* 105456 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSUBs16), |
| 38013 | /* 105459 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 38014 | /* 105461 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 38015 | /* 105463 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 38016 | /* 105465 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 38017 | /* 105468 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38018 | /* 105474 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38019 | /* 105480 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 38020 | /* 105483 */ GIR_RootConstrainSelectedInstOperands, |
| 38021 | /* 105484 */ // GIR_Coverage, 3533, |
| 38022 | /* 105484 */ GIR_EraseRootFromParent_Done, |
| 38023 | /* 105485 */ // Label 2003: @105485 |
| 38024 | /* 105485 */ GIM_Reject, |
| 38025 | /* 105486 */ // Label 2001: @105486 |
| 38026 | /* 105486 */ GIM_Reject, |
| 38027 | /* 105487 */ // Label 1983: @105487 |
| 38028 | /* 105487 */ GIM_Try, /*On fail goto*//*Label 2004*/ GIMT_Encode4(105600), |
| 38029 | /* 105492 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 38030 | /* 105495 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 38031 | /* 105498 */ GIM_Try, /*On fail goto*//*Label 2005*/ GIMT_Encode4(105538), // Rule ID 1013 // |
| 38032 | /* 105503 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 38033 | /* 105506 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 38034 | /* 105510 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 38035 | /* 105514 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 38036 | /* 105518 */ // (ssubsat:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VQSUBsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 38037 | /* 105518 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBsv16i8), |
| 38038 | /* 105521 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 38039 | /* 105523 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 38040 | /* 105525 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 38041 | /* 105527 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38042 | /* 105530 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38043 | /* 105536 */ GIR_RootConstrainSelectedInstOperands, |
| 38044 | /* 105537 */ // GIR_Coverage, 1013, |
| 38045 | /* 105537 */ GIR_EraseRootFromParent_Done, |
| 38046 | /* 105538 */ // Label 2005: @105538 |
| 38047 | /* 105538 */ GIM_Try, /*On fail goto*//*Label 2006*/ GIMT_Encode4(105599), // Rule ID 3530 // |
| 38048 | /* 105543 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 38049 | /* 105546 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 38050 | /* 105550 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 38051 | /* 105554 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 38052 | /* 105558 */ // (ssubsat:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VQSUBs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 38053 | /* 105558 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 38054 | /* 105561 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 38055 | /* 105565 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38056 | /* 105570 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSUBs8), |
| 38057 | /* 105573 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 38058 | /* 105575 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 38059 | /* 105577 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 38060 | /* 105579 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 38061 | /* 105582 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38062 | /* 105588 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38063 | /* 105594 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 38064 | /* 105597 */ GIR_RootConstrainSelectedInstOperands, |
| 38065 | /* 105598 */ // GIR_Coverage, 3530, |
| 38066 | /* 105598 */ GIR_EraseRootFromParent_Done, |
| 38067 | /* 105599 */ // Label 2006: @105599 |
| 38068 | /* 105599 */ GIM_Reject, |
| 38069 | /* 105600 */ // Label 2004: @105600 |
| 38070 | /* 105600 */ GIM_Reject, |
| 38071 | /* 105601 */ // Label 1984: @105601 |
| 38072 | /* 105601 */ GIM_Reject, |
| 38073 | /* 105602 */ // Label 34: @105602 |
| 38074 | /* 105602 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 2014*/ GIMT_Encode4(107954), |
| 38075 | /* 105613 */ /*GILLT_s16*//*Label 2007*/ GIMT_Encode4(105665), |
| 38076 | /* 105617 */ /*GILLT_s32*//*Label 2008*/ GIMT_Encode4(105712), |
| 38077 | /* 105621 */ /*GILLT_s64*//*Label 2009*/ GIMT_Encode4(107307), GIMT_Encode4(0), |
| 38078 | /* 105629 */ /*GILLT_v2s32*//*Label 2010*/ GIMT_Encode4(107354), GIMT_Encode4(0), GIMT_Encode4(0), |
| 38079 | /* 105641 */ /*GILLT_v4s16*//*Label 2011*/ GIMT_Encode4(107401), |
| 38080 | /* 105645 */ /*GILLT_v4s32*//*Label 2012*/ GIMT_Encode4(107586), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 38081 | /* 105661 */ /*GILLT_v8s16*//*Label 2013*/ GIMT_Encode4(107700), |
| 38082 | /* 105665 */ // Label 2007: @105665 |
| 38083 | /* 105665 */ GIM_Try, /*On fail goto*//*Label 2015*/ GIMT_Encode4(105711), // Rule ID 614 // |
| 38084 | /* 105670 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 38085 | /* 105673 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 38086 | /* 105676 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 38087 | /* 105679 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 38088 | /* 105683 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 38089 | /* 105687 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 38090 | /* 105691 */ // (fadd:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) => (VADDH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 38091 | /* 105691 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDH), |
| 38092 | /* 105694 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 38093 | /* 105696 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn |
| 38094 | /* 105698 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 38095 | /* 105700 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38096 | /* 105703 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38097 | /* 105709 */ GIR_RootConstrainSelectedInstOperands, |
| 38098 | /* 105710 */ // GIR_Coverage, 614, |
| 38099 | /* 105710 */ GIR_EraseRootFromParent_Done, |
| 38100 | /* 105711 */ // Label 2015: @105711 |
| 38101 | /* 105711 */ GIM_Reject, |
| 38102 | /* 105712 */ // Label 2008: @105712 |
| 38103 | /* 105712 */ GIM_Try, /*On fail goto*//*Label 2016*/ GIMT_Encode4(107306), |
| 38104 | /* 105717 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 38105 | /* 105720 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 38106 | /* 105723 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 38107 | /* 105727 */ GIM_Try, /*On fail goto*//*Label 2017*/ GIMT_Encode4(106055), // Rule ID 5921 // |
| 38108 | /* 105732 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_UseFPVMLx_UseNEONForFP), |
| 38109 | /* 105735 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 38110 | /* 105739 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL), |
| 38111 | /* 105743 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 38112 | /* 105747 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 38113 | /* 105751 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 38114 | /* 105756 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 38115 | /* 105761 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 38116 | /* 105765 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 38117 | /* 105767 */ // (fadd:{ *:[f32] } (fmul:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b), SPR:{ *:[f32] }:$acc) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VMLAfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$acc, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] }) |
| 38118 | /* 105767 */ GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_v2s32, |
| 38119 | /* 105770 */ GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 38120 | /* 105774 */ GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38121 | /* 105779 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/11, |
| 38122 | /* 105781 */ GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_v2s32, |
| 38123 | /* 105784 */ GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 38124 | /* 105788 */ GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38125 | /* 105793 */ GIR_AddSimpleTempRegister, /*InsnID*/10, /*TempRegID*/10, |
| 38126 | /* 105796 */ GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38127 | /* 105801 */ GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_v2s32, |
| 38128 | /* 105804 */ GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 38129 | /* 105808 */ GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38130 | /* 105813 */ GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/9, |
| 38131 | /* 105816 */ GIR_Copy, /*NewInsnID*/9, /*OldInsnID*/1, /*OpIdx*/2, // b |
| 38132 | /* 105820 */ GIR_AddImm8, /*InsnID*/9, /*Imm*/17, |
| 38133 | /* 105823 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38134 | /* 105828 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38135 | /* 105833 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 38136 | /* 105838 */ GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32, |
| 38137 | /* 105841 */ GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 38138 | /* 105845 */ GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38139 | /* 105850 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/8, |
| 38140 | /* 105852 */ GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32, |
| 38141 | /* 105855 */ GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 38142 | /* 105859 */ GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38143 | /* 105864 */ GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7, |
| 38144 | /* 105867 */ GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38145 | /* 105872 */ GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32, |
| 38146 | /* 105875 */ GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 38147 | /* 105879 */ GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38148 | /* 105884 */ GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6, |
| 38149 | /* 105887 */ GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 38150 | /* 105891 */ GIR_AddImm8, /*InsnID*/6, /*Imm*/17, |
| 38151 | /* 105894 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38152 | /* 105899 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38153 | /* 105904 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 38154 | /* 105909 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32, |
| 38155 | /* 105912 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 38156 | /* 105916 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38157 | /* 105921 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 38158 | /* 105923 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32, |
| 38159 | /* 105926 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 38160 | /* 105930 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38161 | /* 105935 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4, |
| 38162 | /* 105938 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38163 | /* 105943 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32, |
| 38164 | /* 105946 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 38165 | /* 105950 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38166 | /* 105955 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3, |
| 38167 | /* 105958 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // acc |
| 38168 | /* 105962 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17, |
| 38169 | /* 105965 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38170 | /* 105970 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38171 | /* 105975 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 38172 | /* 105980 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 38173 | /* 105983 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VMLAfd), |
| 38174 | /* 105987 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38175 | /* 105992 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 38176 | /* 105995 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5, |
| 38177 | /* 105998 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/8, |
| 38178 | /* 106001 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14, |
| 38179 | /* 106004 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38180 | /* 106010 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 38181 | /* 106012 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32, |
| 38182 | /* 106015 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 38183 | /* 106019 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38184 | /* 106024 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 38185 | /* 106027 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38186 | /* 106032 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 38187 | /* 106035 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 38188 | /* 106037 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0), |
| 38189 | /* 106044 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 38190 | /* 106049 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38191 | /* 106054 */ // GIR_Coverage, 5921, |
| 38192 | /* 106054 */ GIR_EraseRootFromParent_Done, |
| 38193 | /* 106055 */ // Label 2017: @106055 |
| 38194 | /* 106055 */ GIM_Try, /*On fail goto*//*Label 2018*/ GIMT_Encode4(106383), // Rule ID 5922 // |
| 38195 | /* 106060 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP4_UseFusedMAC_UseNEONForFP), |
| 38196 | /* 106063 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 38197 | /* 106067 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL), |
| 38198 | /* 106071 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 38199 | /* 106075 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 38200 | /* 106079 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 38201 | /* 106084 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 38202 | /* 106089 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 38203 | /* 106093 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 38204 | /* 106095 */ // (fadd:{ *:[f32] } (fmul:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b), SPR:{ *:[f32] }:$acc) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VFMAfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$acc, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] }) |
| 38205 | /* 106095 */ GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_v2s32, |
| 38206 | /* 106098 */ GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 38207 | /* 106102 */ GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38208 | /* 106107 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/11, |
| 38209 | /* 106109 */ GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_v2s32, |
| 38210 | /* 106112 */ GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 38211 | /* 106116 */ GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38212 | /* 106121 */ GIR_AddSimpleTempRegister, /*InsnID*/10, /*TempRegID*/10, |
| 38213 | /* 106124 */ GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38214 | /* 106129 */ GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_v2s32, |
| 38215 | /* 106132 */ GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 38216 | /* 106136 */ GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38217 | /* 106141 */ GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/9, |
| 38218 | /* 106144 */ GIR_Copy, /*NewInsnID*/9, /*OldInsnID*/1, /*OpIdx*/2, // b |
| 38219 | /* 106148 */ GIR_AddImm8, /*InsnID*/9, /*Imm*/17, |
| 38220 | /* 106151 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38221 | /* 106156 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38222 | /* 106161 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 38223 | /* 106166 */ GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32, |
| 38224 | /* 106169 */ GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 38225 | /* 106173 */ GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38226 | /* 106178 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/8, |
| 38227 | /* 106180 */ GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32, |
| 38228 | /* 106183 */ GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 38229 | /* 106187 */ GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38230 | /* 106192 */ GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7, |
| 38231 | /* 106195 */ GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38232 | /* 106200 */ GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32, |
| 38233 | /* 106203 */ GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 38234 | /* 106207 */ GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38235 | /* 106212 */ GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6, |
| 38236 | /* 106215 */ GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 38237 | /* 106219 */ GIR_AddImm8, /*InsnID*/6, /*Imm*/17, |
| 38238 | /* 106222 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38239 | /* 106227 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38240 | /* 106232 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 38241 | /* 106237 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32, |
| 38242 | /* 106240 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 38243 | /* 106244 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38244 | /* 106249 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 38245 | /* 106251 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32, |
| 38246 | /* 106254 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 38247 | /* 106258 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38248 | /* 106263 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4, |
| 38249 | /* 106266 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38250 | /* 106271 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32, |
| 38251 | /* 106274 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 38252 | /* 106278 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38253 | /* 106283 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3, |
| 38254 | /* 106286 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // acc |
| 38255 | /* 106290 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17, |
| 38256 | /* 106293 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38257 | /* 106298 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38258 | /* 106303 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 38259 | /* 106308 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 38260 | /* 106311 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VFMAfd), |
| 38261 | /* 106315 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38262 | /* 106320 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 38263 | /* 106323 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5, |
| 38264 | /* 106326 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/8, |
| 38265 | /* 106329 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14, |
| 38266 | /* 106332 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38267 | /* 106338 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 38268 | /* 106340 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32, |
| 38269 | /* 106343 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 38270 | /* 106347 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38271 | /* 106352 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 38272 | /* 106355 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38273 | /* 106360 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 38274 | /* 106363 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 38275 | /* 106365 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0), |
| 38276 | /* 106372 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 38277 | /* 106377 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38278 | /* 106382 */ // GIR_Coverage, 5922, |
| 38279 | /* 106382 */ GIR_EraseRootFromParent_Done, |
| 38280 | /* 106383 */ // Label 2018: @106383 |
| 38281 | /* 106383 */ GIM_Try, /*On fail goto*//*Label 2019*/ GIMT_Encode4(106711), // Rule ID 2700 // |
| 38282 | /* 106388 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_UseFPVMLx_UseNEONForFP), |
| 38283 | /* 106391 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 38284 | /* 106395 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 38285 | /* 106399 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL), |
| 38286 | /* 106403 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 38287 | /* 106407 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 38288 | /* 106411 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 38289 | /* 106416 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 38290 | /* 106421 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 38291 | /* 106423 */ // (fadd:{ *:[f32] } SPR:{ *:[f32] }:$acc, (fmul:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b)) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VMLAfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$acc, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] }) |
| 38292 | /* 106423 */ GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_v2s32, |
| 38293 | /* 106426 */ GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 38294 | /* 106430 */ GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38295 | /* 106435 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/11, |
| 38296 | /* 106437 */ GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_v2s32, |
| 38297 | /* 106440 */ GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 38298 | /* 106444 */ GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38299 | /* 106449 */ GIR_AddSimpleTempRegister, /*InsnID*/10, /*TempRegID*/10, |
| 38300 | /* 106452 */ GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38301 | /* 106457 */ GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_v2s32, |
| 38302 | /* 106460 */ GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 38303 | /* 106464 */ GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38304 | /* 106469 */ GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/9, |
| 38305 | /* 106472 */ GIR_Copy, /*NewInsnID*/9, /*OldInsnID*/1, /*OpIdx*/2, // b |
| 38306 | /* 106476 */ GIR_AddImm8, /*InsnID*/9, /*Imm*/17, |
| 38307 | /* 106479 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38308 | /* 106484 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38309 | /* 106489 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 38310 | /* 106494 */ GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32, |
| 38311 | /* 106497 */ GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 38312 | /* 106501 */ GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38313 | /* 106506 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/8, |
| 38314 | /* 106508 */ GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32, |
| 38315 | /* 106511 */ GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 38316 | /* 106515 */ GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38317 | /* 106520 */ GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7, |
| 38318 | /* 106523 */ GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38319 | /* 106528 */ GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32, |
| 38320 | /* 106531 */ GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 38321 | /* 106535 */ GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38322 | /* 106540 */ GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6, |
| 38323 | /* 106543 */ GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 38324 | /* 106547 */ GIR_AddImm8, /*InsnID*/6, /*Imm*/17, |
| 38325 | /* 106550 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38326 | /* 106555 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38327 | /* 106560 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 38328 | /* 106565 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32, |
| 38329 | /* 106568 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 38330 | /* 106572 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38331 | /* 106577 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 38332 | /* 106579 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32, |
| 38333 | /* 106582 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 38334 | /* 106586 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38335 | /* 106591 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4, |
| 38336 | /* 106594 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38337 | /* 106599 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32, |
| 38338 | /* 106602 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 38339 | /* 106606 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38340 | /* 106611 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3, |
| 38341 | /* 106614 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // acc |
| 38342 | /* 106618 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17, |
| 38343 | /* 106621 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38344 | /* 106626 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38345 | /* 106631 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 38346 | /* 106636 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 38347 | /* 106639 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VMLAfd), |
| 38348 | /* 106643 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38349 | /* 106648 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 38350 | /* 106651 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5, |
| 38351 | /* 106654 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/8, |
| 38352 | /* 106657 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14, |
| 38353 | /* 106660 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38354 | /* 106666 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 38355 | /* 106668 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32, |
| 38356 | /* 106671 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 38357 | /* 106675 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38358 | /* 106680 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 38359 | /* 106683 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38360 | /* 106688 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 38361 | /* 106691 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 38362 | /* 106693 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0), |
| 38363 | /* 106700 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 38364 | /* 106705 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38365 | /* 106710 */ // GIR_Coverage, 2700, |
| 38366 | /* 106710 */ GIR_EraseRootFromParent_Done, |
| 38367 | /* 106711 */ // Label 2019: @106711 |
| 38368 | /* 106711 */ GIM_Try, /*On fail goto*//*Label 2020*/ GIMT_Encode4(107039), // Rule ID 2702 // |
| 38369 | /* 106716 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP4_UseFusedMAC_UseNEONForFP), |
| 38370 | /* 106719 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 38371 | /* 106723 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 38372 | /* 106727 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL), |
| 38373 | /* 106731 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 38374 | /* 106735 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 38375 | /* 106739 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 38376 | /* 106744 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 38377 | /* 106749 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 38378 | /* 106751 */ // (fadd:{ *:[f32] } SPR:{ *:[f32] }:$acc, (fmul:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b)) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VFMAfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$acc, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] }) |
| 38379 | /* 106751 */ GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_v2s32, |
| 38380 | /* 106754 */ GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 38381 | /* 106758 */ GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38382 | /* 106763 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/11, |
| 38383 | /* 106765 */ GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_v2s32, |
| 38384 | /* 106768 */ GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 38385 | /* 106772 */ GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38386 | /* 106777 */ GIR_AddSimpleTempRegister, /*InsnID*/10, /*TempRegID*/10, |
| 38387 | /* 106780 */ GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38388 | /* 106785 */ GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_v2s32, |
| 38389 | /* 106788 */ GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 38390 | /* 106792 */ GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38391 | /* 106797 */ GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/9, |
| 38392 | /* 106800 */ GIR_Copy, /*NewInsnID*/9, /*OldInsnID*/1, /*OpIdx*/2, // b |
| 38393 | /* 106804 */ GIR_AddImm8, /*InsnID*/9, /*Imm*/17, |
| 38394 | /* 106807 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38395 | /* 106812 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38396 | /* 106817 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 38397 | /* 106822 */ GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32, |
| 38398 | /* 106825 */ GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 38399 | /* 106829 */ GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38400 | /* 106834 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/8, |
| 38401 | /* 106836 */ GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32, |
| 38402 | /* 106839 */ GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 38403 | /* 106843 */ GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38404 | /* 106848 */ GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7, |
| 38405 | /* 106851 */ GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38406 | /* 106856 */ GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32, |
| 38407 | /* 106859 */ GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 38408 | /* 106863 */ GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38409 | /* 106868 */ GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6, |
| 38410 | /* 106871 */ GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 38411 | /* 106875 */ GIR_AddImm8, /*InsnID*/6, /*Imm*/17, |
| 38412 | /* 106878 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38413 | /* 106883 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38414 | /* 106888 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 38415 | /* 106893 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32, |
| 38416 | /* 106896 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 38417 | /* 106900 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38418 | /* 106905 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 38419 | /* 106907 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32, |
| 38420 | /* 106910 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 38421 | /* 106914 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38422 | /* 106919 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4, |
| 38423 | /* 106922 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38424 | /* 106927 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32, |
| 38425 | /* 106930 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 38426 | /* 106934 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38427 | /* 106939 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3, |
| 38428 | /* 106942 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // acc |
| 38429 | /* 106946 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17, |
| 38430 | /* 106949 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38431 | /* 106954 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38432 | /* 106959 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 38433 | /* 106964 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 38434 | /* 106967 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VFMAfd), |
| 38435 | /* 106971 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38436 | /* 106976 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 38437 | /* 106979 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5, |
| 38438 | /* 106982 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/8, |
| 38439 | /* 106985 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14, |
| 38440 | /* 106988 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38441 | /* 106994 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 38442 | /* 106996 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32, |
| 38443 | /* 106999 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 38444 | /* 107003 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38445 | /* 107008 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 38446 | /* 107011 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38447 | /* 107016 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 38448 | /* 107019 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 38449 | /* 107021 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0), |
| 38450 | /* 107028 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 38451 | /* 107033 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38452 | /* 107038 */ // GIR_Coverage, 2702, |
| 38453 | /* 107038 */ GIR_EraseRootFromParent_Done, |
| 38454 | /* 107039 */ // Label 2020: @107039 |
| 38455 | /* 107039 */ GIM_Try, /*On fail goto*//*Label 2021*/ GIMT_Encode4(107075), // Rule ID 613 // |
| 38456 | /* 107044 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), |
| 38457 | /* 107047 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 38458 | /* 107051 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 38459 | /* 107055 */ // (fadd:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) => (VADDS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 38460 | /* 107055 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDS), |
| 38461 | /* 107058 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 38462 | /* 107060 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn |
| 38463 | /* 107062 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 38464 | /* 107064 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38465 | /* 107067 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38466 | /* 107073 */ GIR_RootConstrainSelectedInstOperands, |
| 38467 | /* 107074 */ // GIR_Coverage, 613, |
| 38468 | /* 107074 */ GIR_EraseRootFromParent_Done, |
| 38469 | /* 107075 */ // Label 2021: @107075 |
| 38470 | /* 107075 */ GIM_Try, /*On fail goto*//*Label 2022*/ GIMT_Encode4(107305), // Rule ID 2697 // |
| 38471 | /* 107080 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_UseNEONForFP), |
| 38472 | /* 107083 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 38473 | /* 107087 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 38474 | /* 107091 */ // (fadd:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VADDfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] }) |
| 38475 | /* 107091 */ GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32, |
| 38476 | /* 107094 */ GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 38477 | /* 107098 */ GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38478 | /* 107103 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/8, |
| 38479 | /* 107105 */ GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32, |
| 38480 | /* 107108 */ GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 38481 | /* 107112 */ GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38482 | /* 107117 */ GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7, |
| 38483 | /* 107120 */ GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38484 | /* 107125 */ GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32, |
| 38485 | /* 107128 */ GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 38486 | /* 107132 */ GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38487 | /* 107137 */ GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6, |
| 38488 | /* 107140 */ GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/2, // b |
| 38489 | /* 107144 */ GIR_AddImm8, /*InsnID*/6, /*Imm*/17, |
| 38490 | /* 107147 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38491 | /* 107152 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38492 | /* 107157 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 38493 | /* 107162 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32, |
| 38494 | /* 107165 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 38495 | /* 107169 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38496 | /* 107174 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 38497 | /* 107176 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32, |
| 38498 | /* 107179 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 38499 | /* 107183 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38500 | /* 107188 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4, |
| 38501 | /* 107191 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38502 | /* 107196 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32, |
| 38503 | /* 107199 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 38504 | /* 107203 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38505 | /* 107208 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3, |
| 38506 | /* 107211 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 38507 | /* 107215 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17, |
| 38508 | /* 107218 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38509 | /* 107223 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38510 | /* 107228 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 38511 | /* 107233 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 38512 | /* 107236 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VADDfd), |
| 38513 | /* 107240 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38514 | /* 107245 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 38515 | /* 107248 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5, |
| 38516 | /* 107251 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14, |
| 38517 | /* 107254 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38518 | /* 107260 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 38519 | /* 107262 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32, |
| 38520 | /* 107265 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 38521 | /* 107269 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38522 | /* 107274 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 38523 | /* 107277 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38524 | /* 107282 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 38525 | /* 107285 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 38526 | /* 107287 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0), |
| 38527 | /* 107294 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 38528 | /* 107299 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38529 | /* 107304 */ // GIR_Coverage, 2697, |
| 38530 | /* 107304 */ GIR_EraseRootFromParent_Done, |
| 38531 | /* 107305 */ // Label 2022: @107305 |
| 38532 | /* 107305 */ GIM_Reject, |
| 38533 | /* 107306 */ // Label 2016: @107306 |
| 38534 | /* 107306 */ GIM_Reject, |
| 38535 | /* 107307 */ // Label 2009: @107307 |
| 38536 | /* 107307 */ GIM_Try, /*On fail goto*//*Label 2023*/ GIMT_Encode4(107353), // Rule ID 612 // |
| 38537 | /* 107312 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), |
| 38538 | /* 107315 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 38539 | /* 107318 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 38540 | /* 107321 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38541 | /* 107325 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38542 | /* 107329 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38543 | /* 107333 */ // (fadd:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) => (VADDD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 38544 | /* 107333 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDD), |
| 38545 | /* 107336 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 38546 | /* 107338 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dn |
| 38547 | /* 107340 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm |
| 38548 | /* 107342 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38549 | /* 107345 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38550 | /* 107351 */ GIR_RootConstrainSelectedInstOperands, |
| 38551 | /* 107352 */ // GIR_Coverage, 612, |
| 38552 | /* 107352 */ GIR_EraseRootFromParent_Done, |
| 38553 | /* 107353 */ // Label 2023: @107353 |
| 38554 | /* 107353 */ GIM_Reject, |
| 38555 | /* 107354 */ // Label 2010: @107354 |
| 38556 | /* 107354 */ GIM_Try, /*On fail goto*//*Label 2024*/ GIMT_Encode4(107400), // Rule ID 764 // |
| 38557 | /* 107359 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 38558 | /* 107362 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 38559 | /* 107365 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 38560 | /* 107368 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38561 | /* 107372 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38562 | /* 107376 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38563 | /* 107380 */ // (fadd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VADDfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) |
| 38564 | /* 107380 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDfd), |
| 38565 | /* 107383 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 38566 | /* 107385 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 38567 | /* 107387 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 38568 | /* 107389 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38569 | /* 107392 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38570 | /* 107398 */ GIR_RootConstrainSelectedInstOperands, |
| 38571 | /* 107399 */ // GIR_Coverage, 764, |
| 38572 | /* 107399 */ GIR_EraseRootFromParent_Done, |
| 38573 | /* 107400 */ // Label 2024: @107400 |
| 38574 | /* 107400 */ GIM_Reject, |
| 38575 | /* 107401 */ // Label 2011: @107401 |
| 38576 | /* 107401 */ GIM_Try, /*On fail goto*//*Label 2025*/ GIMT_Encode4(107585), |
| 38577 | /* 107406 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 38578 | /* 107409 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 38579 | /* 107412 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38580 | /* 107416 */ GIM_Try, /*On fail goto*//*Label 2026*/ GIMT_Encode4(107482), // Rule ID 5584 // |
| 38581 | /* 107421 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_UseFusedMAC), |
| 38582 | /* 107424 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 38583 | /* 107428 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL), |
| 38584 | /* 107432 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 38585 | /* 107436 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 38586 | /* 107440 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38587 | /* 107445 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38588 | /* 107450 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38589 | /* 107454 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 38590 | /* 107456 */ // (fadd:{ *:[v4f16] } (fmul:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm), DPR:{ *:[v4f16] }:$src1) => (VFMAhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) |
| 38591 | /* 107456 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAhd), |
| 38592 | /* 107459 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 38593 | /* 107461 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 38594 | /* 107463 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 38595 | /* 107467 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 38596 | /* 107471 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38597 | /* 107474 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38598 | /* 107480 */ GIR_RootConstrainSelectedInstOperands, |
| 38599 | /* 107481 */ // GIR_Coverage, 5584, |
| 38600 | /* 107481 */ GIR_EraseRootFromParent_Done, |
| 38601 | /* 107482 */ // Label 2026: @107482 |
| 38602 | /* 107482 */ GIM_Try, /*On fail goto*//*Label 2027*/ GIMT_Encode4(107548), // Rule ID 945 // |
| 38603 | /* 107487 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_UseFusedMAC), |
| 38604 | /* 107490 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38605 | /* 107494 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 38606 | /* 107498 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL), |
| 38607 | /* 107502 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 38608 | /* 107506 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 38609 | /* 107510 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38610 | /* 107515 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38611 | /* 107520 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 38612 | /* 107522 */ // (fadd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, (fmul:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)) => (VFMAhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) |
| 38613 | /* 107522 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAhd), |
| 38614 | /* 107525 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 38615 | /* 107527 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 38616 | /* 107529 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 38617 | /* 107533 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 38618 | /* 107537 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38619 | /* 107540 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38620 | /* 107546 */ GIR_RootConstrainSelectedInstOperands, |
| 38621 | /* 107547 */ // GIR_Coverage, 945, |
| 38622 | /* 107547 */ GIR_EraseRootFromParent_Done, |
| 38623 | /* 107548 */ // Label 2027: @107548 |
| 38624 | /* 107548 */ GIM_Try, /*On fail goto*//*Label 2028*/ GIMT_Encode4(107584), // Rule ID 766 // |
| 38625 | /* 107553 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 38626 | /* 107556 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38627 | /* 107560 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38628 | /* 107564 */ // (fadd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VADDhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) |
| 38629 | /* 107564 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDhd), |
| 38630 | /* 107567 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 38631 | /* 107569 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 38632 | /* 107571 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 38633 | /* 107573 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38634 | /* 107576 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38635 | /* 107582 */ GIR_RootConstrainSelectedInstOperands, |
| 38636 | /* 107583 */ // GIR_Coverage, 766, |
| 38637 | /* 107583 */ GIR_EraseRootFromParent_Done, |
| 38638 | /* 107584 */ // Label 2028: @107584 |
| 38639 | /* 107584 */ GIM_Reject, |
| 38640 | /* 107585 */ // Label 2025: @107585 |
| 38641 | /* 107585 */ GIM_Reject, |
| 38642 | /* 107586 */ // Label 2012: @107586 |
| 38643 | /* 107586 */ GIM_Try, /*On fail goto*//*Label 2029*/ GIMT_Encode4(107699), |
| 38644 | /* 107591 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 38645 | /* 107594 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 38646 | /* 107597 */ GIM_Try, /*On fail goto*//*Label 2030*/ GIMT_Encode4(107637), // Rule ID 765 // |
| 38647 | /* 107602 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 38648 | /* 107605 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 38649 | /* 107609 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 38650 | /* 107613 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 38651 | /* 107617 */ // (fadd:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (VADDfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) |
| 38652 | /* 107617 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDfq), |
| 38653 | /* 107620 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 38654 | /* 107622 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 38655 | /* 107624 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 38656 | /* 107626 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38657 | /* 107629 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38658 | /* 107635 */ GIR_RootConstrainSelectedInstOperands, |
| 38659 | /* 107636 */ // GIR_Coverage, 765, |
| 38660 | /* 107636 */ GIR_EraseRootFromParent_Done, |
| 38661 | /* 107637 */ // Label 2030: @107637 |
| 38662 | /* 107637 */ GIM_Try, /*On fail goto*//*Label 2031*/ GIMT_Encode4(107698), // Rule ID 4016 // |
| 38663 | /* 107642 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 38664 | /* 107645 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 38665 | /* 107649 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 38666 | /* 107653 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 38667 | /* 107657 */ // (fadd:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) => (MVE_VADDf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) |
| 38668 | /* 107657 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 38669 | /* 107660 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 38670 | /* 107664 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38671 | /* 107669 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDf32), |
| 38672 | /* 107672 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 38673 | /* 107674 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 38674 | /* 107676 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 38675 | /* 107678 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 38676 | /* 107681 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38677 | /* 107687 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38678 | /* 107693 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 38679 | /* 107696 */ GIR_RootConstrainSelectedInstOperands, |
| 38680 | /* 107697 */ // GIR_Coverage, 4016, |
| 38681 | /* 107697 */ GIR_EraseRootFromParent_Done, |
| 38682 | /* 107698 */ // Label 2031: @107698 |
| 38683 | /* 107698 */ GIM_Reject, |
| 38684 | /* 107699 */ // Label 2029: @107699 |
| 38685 | /* 107699 */ GIM_Reject, |
| 38686 | /* 107700 */ // Label 2013: @107700 |
| 38687 | /* 107700 */ GIM_Try, /*On fail goto*//*Label 2032*/ GIMT_Encode4(107953), |
| 38688 | /* 107705 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 38689 | /* 107708 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 38690 | /* 107711 */ GIM_Try, /*On fail goto*//*Label 2033*/ GIMT_Encode4(107781), // Rule ID 5585 // |
| 38691 | /* 107716 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_UseFusedMAC), |
| 38692 | /* 107719 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 38693 | /* 107723 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 38694 | /* 107727 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL), |
| 38695 | /* 107731 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 38696 | /* 107735 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 38697 | /* 107739 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 38698 | /* 107744 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 38699 | /* 107749 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 38700 | /* 107753 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 38701 | /* 107755 */ // (fadd:{ *:[v8f16] } (fmul:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm), QPR:{ *:[v8f16] }:$src1) => (VFMAhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) |
| 38702 | /* 107755 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAhq), |
| 38703 | /* 107758 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 38704 | /* 107760 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 38705 | /* 107762 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 38706 | /* 107766 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 38707 | /* 107770 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38708 | /* 107773 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38709 | /* 107779 */ GIR_RootConstrainSelectedInstOperands, |
| 38710 | /* 107780 */ // GIR_Coverage, 5585, |
| 38711 | /* 107780 */ GIR_EraseRootFromParent_Done, |
| 38712 | /* 107781 */ // Label 2033: @107781 |
| 38713 | /* 107781 */ GIM_Try, /*On fail goto*//*Label 2034*/ GIMT_Encode4(107851), // Rule ID 946 // |
| 38714 | /* 107786 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_UseFusedMAC), |
| 38715 | /* 107789 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 38716 | /* 107793 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 38717 | /* 107797 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 38718 | /* 107801 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL), |
| 38719 | /* 107805 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 38720 | /* 107809 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 38721 | /* 107813 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 38722 | /* 107818 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 38723 | /* 107823 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 38724 | /* 107825 */ // (fadd:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, (fmul:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)) => (VFMAhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) |
| 38725 | /* 107825 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAhq), |
| 38726 | /* 107828 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 38727 | /* 107830 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 38728 | /* 107832 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 38729 | /* 107836 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 38730 | /* 107840 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38731 | /* 107843 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38732 | /* 107849 */ GIR_RootConstrainSelectedInstOperands, |
| 38733 | /* 107850 */ // GIR_Coverage, 946, |
| 38734 | /* 107850 */ GIR_EraseRootFromParent_Done, |
| 38735 | /* 107851 */ // Label 2034: @107851 |
| 38736 | /* 107851 */ GIM_Try, /*On fail goto*//*Label 2035*/ GIMT_Encode4(107891), // Rule ID 767 // |
| 38737 | /* 107856 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 38738 | /* 107859 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 38739 | /* 107863 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 38740 | /* 107867 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 38741 | /* 107871 */ // (fadd:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (VADDhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) |
| 38742 | /* 107871 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDhq), |
| 38743 | /* 107874 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 38744 | /* 107876 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 38745 | /* 107878 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 38746 | /* 107880 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38747 | /* 107883 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38748 | /* 107889 */ GIR_RootConstrainSelectedInstOperands, |
| 38749 | /* 107890 */ // GIR_Coverage, 767, |
| 38750 | /* 107890 */ GIR_EraseRootFromParent_Done, |
| 38751 | /* 107891 */ // Label 2035: @107891 |
| 38752 | /* 107891 */ GIM_Try, /*On fail goto*//*Label 2036*/ GIMT_Encode4(107952), // Rule ID 4020 // |
| 38753 | /* 107896 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 38754 | /* 107899 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 38755 | /* 107903 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 38756 | /* 107907 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 38757 | /* 107911 */ // (fadd:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) => (MVE_VADDf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) |
| 38758 | /* 107911 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 38759 | /* 107914 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 38760 | /* 107918 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38761 | /* 107923 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDf16), |
| 38762 | /* 107926 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 38763 | /* 107928 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 38764 | /* 107930 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 38765 | /* 107932 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 38766 | /* 107935 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38767 | /* 107941 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38768 | /* 107947 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 38769 | /* 107950 */ GIR_RootConstrainSelectedInstOperands, |
| 38770 | /* 107951 */ // GIR_Coverage, 4020, |
| 38771 | /* 107951 */ GIR_EraseRootFromParent_Done, |
| 38772 | /* 107952 */ // Label 2036: @107952 |
| 38773 | /* 107952 */ GIM_Reject, |
| 38774 | /* 107953 */ // Label 2032: @107953 |
| 38775 | /* 107953 */ GIM_Reject, |
| 38776 | /* 107954 */ // Label 2014: @107954 |
| 38777 | /* 107954 */ GIM_Reject, |
| 38778 | /* 107955 */ // Label 35: @107955 |
| 38779 | /* 107955 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 2044*/ GIMT_Encode4(109631), |
| 38780 | /* 107966 */ /*GILLT_s16*//*Label 2037*/ GIMT_Encode4(108018), |
| 38781 | /* 107970 */ /*GILLT_s32*//*Label 2038*/ GIMT_Encode4(108065), |
| 38782 | /* 107974 */ /*GILLT_s64*//*Label 2039*/ GIMT_Encode4(108992), GIMT_Encode4(0), |
| 38783 | /* 107982 */ /*GILLT_v2s32*//*Label 2040*/ GIMT_Encode4(109039), GIMT_Encode4(0), GIMT_Encode4(0), |
| 38784 | /* 107994 */ /*GILLT_v4s16*//*Label 2041*/ GIMT_Encode4(109086), |
| 38785 | /* 107998 */ /*GILLT_v4s32*//*Label 2042*/ GIMT_Encode4(109263), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 38786 | /* 108014 */ /*GILLT_v8s16*//*Label 2043*/ GIMT_Encode4(109377), |
| 38787 | /* 108018 */ // Label 2037: @108018 |
| 38788 | /* 108018 */ GIM_Try, /*On fail goto*//*Label 2045*/ GIMT_Encode4(108064), // Rule ID 617 // |
| 38789 | /* 108023 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 38790 | /* 108026 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 38791 | /* 108029 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 38792 | /* 108032 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 38793 | /* 108036 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 38794 | /* 108040 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 38795 | /* 108044 */ // (fsub:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) => (VSUBH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 38796 | /* 108044 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBH), |
| 38797 | /* 108047 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 38798 | /* 108049 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn |
| 38799 | /* 108051 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 38800 | /* 108053 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38801 | /* 108056 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38802 | /* 108062 */ GIR_RootConstrainSelectedInstOperands, |
| 38803 | /* 108063 */ // GIR_Coverage, 617, |
| 38804 | /* 108063 */ GIR_EraseRootFromParent_Done, |
| 38805 | /* 108064 */ // Label 2045: @108064 |
| 38806 | /* 108064 */ GIM_Reject, |
| 38807 | /* 108065 */ // Label 2038: @108065 |
| 38808 | /* 108065 */ GIM_Try, /*On fail goto*//*Label 2046*/ GIMT_Encode4(108991), |
| 38809 | /* 108070 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 38810 | /* 108073 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 38811 | /* 108076 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 38812 | /* 108080 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 38813 | /* 108084 */ GIM_Try, /*On fail goto*//*Label 2047*/ GIMT_Encode4(108408), // Rule ID 2701 // |
| 38814 | /* 108089 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_UseFPVMLx_UseNEONForFP), |
| 38815 | /* 108092 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 38816 | /* 108096 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL), |
| 38817 | /* 108100 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 38818 | /* 108104 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 38819 | /* 108108 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 38820 | /* 108113 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 38821 | /* 108118 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 38822 | /* 108120 */ // (fsub:{ *:[f32] } SPR:{ *:[f32] }:$acc, (fmul:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b)) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VMLSfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$acc, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] }) |
| 38823 | /* 108120 */ GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_v2s32, |
| 38824 | /* 108123 */ GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 38825 | /* 108127 */ GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38826 | /* 108132 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/11, |
| 38827 | /* 108134 */ GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_v2s32, |
| 38828 | /* 108137 */ GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 38829 | /* 108141 */ GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38830 | /* 108146 */ GIR_AddSimpleTempRegister, /*InsnID*/10, /*TempRegID*/10, |
| 38831 | /* 108149 */ GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38832 | /* 108154 */ GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_v2s32, |
| 38833 | /* 108157 */ GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 38834 | /* 108161 */ GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38835 | /* 108166 */ GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/9, |
| 38836 | /* 108169 */ GIR_Copy, /*NewInsnID*/9, /*OldInsnID*/1, /*OpIdx*/2, // b |
| 38837 | /* 108173 */ GIR_AddImm8, /*InsnID*/9, /*Imm*/17, |
| 38838 | /* 108176 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38839 | /* 108181 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38840 | /* 108186 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 38841 | /* 108191 */ GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32, |
| 38842 | /* 108194 */ GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 38843 | /* 108198 */ GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38844 | /* 108203 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/8, |
| 38845 | /* 108205 */ GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32, |
| 38846 | /* 108208 */ GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 38847 | /* 108212 */ GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38848 | /* 108217 */ GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7, |
| 38849 | /* 108220 */ GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38850 | /* 108225 */ GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32, |
| 38851 | /* 108228 */ GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 38852 | /* 108232 */ GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38853 | /* 108237 */ GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6, |
| 38854 | /* 108240 */ GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 38855 | /* 108244 */ GIR_AddImm8, /*InsnID*/6, /*Imm*/17, |
| 38856 | /* 108247 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38857 | /* 108252 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38858 | /* 108257 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 38859 | /* 108262 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32, |
| 38860 | /* 108265 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 38861 | /* 108269 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38862 | /* 108274 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 38863 | /* 108276 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32, |
| 38864 | /* 108279 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 38865 | /* 108283 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38866 | /* 108288 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4, |
| 38867 | /* 108291 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38868 | /* 108296 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32, |
| 38869 | /* 108299 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 38870 | /* 108303 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38871 | /* 108308 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3, |
| 38872 | /* 108311 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // acc |
| 38873 | /* 108315 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17, |
| 38874 | /* 108318 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38875 | /* 108323 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38876 | /* 108328 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 38877 | /* 108333 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 38878 | /* 108336 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VMLSfd), |
| 38879 | /* 108340 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38880 | /* 108345 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 38881 | /* 108348 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5, |
| 38882 | /* 108351 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/8, |
| 38883 | /* 108354 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14, |
| 38884 | /* 108357 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38885 | /* 108363 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 38886 | /* 108365 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32, |
| 38887 | /* 108368 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 38888 | /* 108372 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38889 | /* 108377 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 38890 | /* 108380 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38891 | /* 108385 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 38892 | /* 108388 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 38893 | /* 108390 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0), |
| 38894 | /* 108397 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 38895 | /* 108402 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38896 | /* 108407 */ // GIR_Coverage, 2701, |
| 38897 | /* 108407 */ GIR_EraseRootFromParent_Done, |
| 38898 | /* 108408 */ // Label 2047: @108408 |
| 38899 | /* 108408 */ GIM_Try, /*On fail goto*//*Label 2048*/ GIMT_Encode4(108732), // Rule ID 2703 // |
| 38900 | /* 108413 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP4_UseFusedMAC_UseNEONForFP), |
| 38901 | /* 108416 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 38902 | /* 108420 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL), |
| 38903 | /* 108424 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 38904 | /* 108428 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 38905 | /* 108432 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 38906 | /* 108437 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 38907 | /* 108442 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 38908 | /* 108444 */ // (fsub:{ *:[f32] } SPR:{ *:[f32] }:$acc, (fmul:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b)) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VFMSfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$acc, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] }) |
| 38909 | /* 108444 */ GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_v2s32, |
| 38910 | /* 108447 */ GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 38911 | /* 108451 */ GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38912 | /* 108456 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/11, |
| 38913 | /* 108458 */ GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_v2s32, |
| 38914 | /* 108461 */ GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 38915 | /* 108465 */ GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38916 | /* 108470 */ GIR_AddSimpleTempRegister, /*InsnID*/10, /*TempRegID*/10, |
| 38917 | /* 108473 */ GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38918 | /* 108478 */ GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_v2s32, |
| 38919 | /* 108481 */ GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 38920 | /* 108485 */ GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38921 | /* 108490 */ GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/9, |
| 38922 | /* 108493 */ GIR_Copy, /*NewInsnID*/9, /*OldInsnID*/1, /*OpIdx*/2, // b |
| 38923 | /* 108497 */ GIR_AddImm8, /*InsnID*/9, /*Imm*/17, |
| 38924 | /* 108500 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38925 | /* 108505 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38926 | /* 108510 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 38927 | /* 108515 */ GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32, |
| 38928 | /* 108518 */ GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 38929 | /* 108522 */ GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38930 | /* 108527 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/8, |
| 38931 | /* 108529 */ GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32, |
| 38932 | /* 108532 */ GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 38933 | /* 108536 */ GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38934 | /* 108541 */ GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7, |
| 38935 | /* 108544 */ GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38936 | /* 108549 */ GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32, |
| 38937 | /* 108552 */ GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 38938 | /* 108556 */ GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38939 | /* 108561 */ GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6, |
| 38940 | /* 108564 */ GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 38941 | /* 108568 */ GIR_AddImm8, /*InsnID*/6, /*Imm*/17, |
| 38942 | /* 108571 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38943 | /* 108576 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38944 | /* 108581 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 38945 | /* 108586 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32, |
| 38946 | /* 108589 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 38947 | /* 108593 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38948 | /* 108598 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 38949 | /* 108600 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32, |
| 38950 | /* 108603 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 38951 | /* 108607 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38952 | /* 108612 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4, |
| 38953 | /* 108615 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38954 | /* 108620 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32, |
| 38955 | /* 108623 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 38956 | /* 108627 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38957 | /* 108632 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3, |
| 38958 | /* 108635 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // acc |
| 38959 | /* 108639 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17, |
| 38960 | /* 108642 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38961 | /* 108647 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38962 | /* 108652 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 38963 | /* 108657 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 38964 | /* 108660 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VFMSfd), |
| 38965 | /* 108664 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38966 | /* 108669 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 38967 | /* 108672 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5, |
| 38968 | /* 108675 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/8, |
| 38969 | /* 108678 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14, |
| 38970 | /* 108681 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38971 | /* 108687 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 38972 | /* 108689 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32, |
| 38973 | /* 108692 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 38974 | /* 108696 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 38975 | /* 108701 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 38976 | /* 108704 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38977 | /* 108709 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 38978 | /* 108712 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 38979 | /* 108714 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0), |
| 38980 | /* 108721 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 38981 | /* 108726 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38982 | /* 108731 */ // GIR_Coverage, 2703, |
| 38983 | /* 108731 */ GIR_EraseRootFromParent_Done, |
| 38984 | /* 108732 */ // Label 2048: @108732 |
| 38985 | /* 108732 */ GIM_Try, /*On fail goto*//*Label 2049*/ GIMT_Encode4(108764), // Rule ID 616 // |
| 38986 | /* 108737 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), |
| 38987 | /* 108740 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 38988 | /* 108744 */ // (fsub:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) => (VSUBS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 38989 | /* 108744 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBS), |
| 38990 | /* 108747 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 38991 | /* 108749 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn |
| 38992 | /* 108751 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 38993 | /* 108753 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38994 | /* 108756 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38995 | /* 108762 */ GIR_RootConstrainSelectedInstOperands, |
| 38996 | /* 108763 */ // GIR_Coverage, 616, |
| 38997 | /* 108763 */ GIR_EraseRootFromParent_Done, |
| 38998 | /* 108764 */ // Label 2049: @108764 |
| 38999 | /* 108764 */ GIM_Try, /*On fail goto*//*Label 2050*/ GIMT_Encode4(108990), // Rule ID 2698 // |
| 39000 | /* 108769 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_UseNEONForFP), |
| 39001 | /* 108772 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 39002 | /* 108776 */ // (fsub:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VSUBfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] }) |
| 39003 | /* 108776 */ GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32, |
| 39004 | /* 108779 */ GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 39005 | /* 108783 */ GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 39006 | /* 108788 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/8, |
| 39007 | /* 108790 */ GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32, |
| 39008 | /* 108793 */ GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 39009 | /* 108797 */ GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 39010 | /* 108802 */ GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7, |
| 39011 | /* 108805 */ GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 39012 | /* 108810 */ GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32, |
| 39013 | /* 108813 */ GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 39014 | /* 108817 */ GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 39015 | /* 108822 */ GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6, |
| 39016 | /* 108825 */ GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/2, // b |
| 39017 | /* 108829 */ GIR_AddImm8, /*InsnID*/6, /*Imm*/17, |
| 39018 | /* 108832 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 39019 | /* 108837 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 39020 | /* 108842 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 39021 | /* 108847 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32, |
| 39022 | /* 108850 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 39023 | /* 108854 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 39024 | /* 108859 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 39025 | /* 108861 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32, |
| 39026 | /* 108864 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 39027 | /* 108868 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 39028 | /* 108873 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4, |
| 39029 | /* 108876 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 39030 | /* 108881 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32, |
| 39031 | /* 108884 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 39032 | /* 108888 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 39033 | /* 108893 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3, |
| 39034 | /* 108896 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 39035 | /* 108900 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17, |
| 39036 | /* 108903 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 39037 | /* 108908 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 39038 | /* 108913 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 39039 | /* 108918 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 39040 | /* 108921 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VSUBfd), |
| 39041 | /* 108925 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 39042 | /* 108930 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 39043 | /* 108933 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5, |
| 39044 | /* 108936 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14, |
| 39045 | /* 108939 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39046 | /* 108945 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 39047 | /* 108947 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32, |
| 39048 | /* 108950 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 39049 | /* 108954 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 39050 | /* 108959 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 39051 | /* 108962 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 39052 | /* 108967 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 39053 | /* 108970 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 39054 | /* 108972 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0), |
| 39055 | /* 108979 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 39056 | /* 108984 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 39057 | /* 108989 */ // GIR_Coverage, 2698, |
| 39058 | /* 108989 */ GIR_EraseRootFromParent_Done, |
| 39059 | /* 108990 */ // Label 2050: @108990 |
| 39060 | /* 108990 */ GIM_Reject, |
| 39061 | /* 108991 */ // Label 2046: @108991 |
| 39062 | /* 108991 */ GIM_Reject, |
| 39063 | /* 108992 */ // Label 2039: @108992 |
| 39064 | /* 108992 */ GIM_Try, /*On fail goto*//*Label 2051*/ GIMT_Encode4(109038), // Rule ID 615 // |
| 39065 | /* 108997 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), |
| 39066 | /* 109000 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 39067 | /* 109003 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 39068 | /* 109006 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39069 | /* 109010 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39070 | /* 109014 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39071 | /* 109018 */ // (fsub:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) => (VSUBD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 39072 | /* 109018 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBD), |
| 39073 | /* 109021 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 39074 | /* 109023 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dn |
| 39075 | /* 109025 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm |
| 39076 | /* 109027 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39077 | /* 109030 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39078 | /* 109036 */ GIR_RootConstrainSelectedInstOperands, |
| 39079 | /* 109037 */ // GIR_Coverage, 615, |
| 39080 | /* 109037 */ GIR_EraseRootFromParent_Done, |
| 39081 | /* 109038 */ // Label 2051: @109038 |
| 39082 | /* 109038 */ GIM_Reject, |
| 39083 | /* 109039 */ // Label 2040: @109039 |
| 39084 | /* 109039 */ GIM_Try, /*On fail goto*//*Label 2052*/ GIMT_Encode4(109085), // Rule ID 968 // |
| 39085 | /* 109044 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 39086 | /* 109047 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 39087 | /* 109050 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 39088 | /* 109053 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39089 | /* 109057 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39090 | /* 109061 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39091 | /* 109065 */ // (fsub:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VSUBfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) |
| 39092 | /* 109065 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBfd), |
| 39093 | /* 109068 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 39094 | /* 109070 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 39095 | /* 109072 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 39096 | /* 109074 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39097 | /* 109077 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39098 | /* 109083 */ GIR_RootConstrainSelectedInstOperands, |
| 39099 | /* 109084 */ // GIR_Coverage, 968, |
| 39100 | /* 109084 */ GIR_EraseRootFromParent_Done, |
| 39101 | /* 109085 */ // Label 2052: @109085 |
| 39102 | /* 109085 */ GIM_Reject, |
| 39103 | /* 109086 */ // Label 2041: @109086 |
| 39104 | /* 109086 */ GIM_Try, /*On fail goto*//*Label 2053*/ GIMT_Encode4(109262), |
| 39105 | /* 109091 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 39106 | /* 109094 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 39107 | /* 109097 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39108 | /* 109101 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39109 | /* 109105 */ GIM_Try, /*On fail goto*//*Label 2054*/ GIMT_Encode4(109167), // Rule ID 923 // |
| 39110 | /* 109110 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_UseFPVMLx), |
| 39111 | /* 109113 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 39112 | /* 109117 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL), |
| 39113 | /* 109121 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 39114 | /* 109125 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 39115 | /* 109129 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39116 | /* 109134 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39117 | /* 109139 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 39118 | /* 109141 */ // (fsub:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, (fmul:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)) => (VMLShd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) |
| 39119 | /* 109141 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLShd), |
| 39120 | /* 109144 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 39121 | /* 109146 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 39122 | /* 109148 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 39123 | /* 109152 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 39124 | /* 109156 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39125 | /* 109159 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39126 | /* 109165 */ GIR_RootConstrainSelectedInstOperands, |
| 39127 | /* 109166 */ // GIR_Coverage, 923, |
| 39128 | /* 109166 */ GIR_EraseRootFromParent_Done, |
| 39129 | /* 109167 */ // Label 2054: @109167 |
| 39130 | /* 109167 */ GIM_Try, /*On fail goto*//*Label 2055*/ GIMT_Encode4(109229), // Rule ID 949 // |
| 39131 | /* 109172 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_UseFusedMAC), |
| 39132 | /* 109175 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 39133 | /* 109179 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL), |
| 39134 | /* 109183 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 39135 | /* 109187 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 39136 | /* 109191 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39137 | /* 109196 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39138 | /* 109201 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 39139 | /* 109203 */ // (fsub:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, (fmul:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)) => (VFMShd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) |
| 39140 | /* 109203 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMShd), |
| 39141 | /* 109206 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 39142 | /* 109208 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 39143 | /* 109210 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 39144 | /* 109214 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 39145 | /* 109218 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39146 | /* 109221 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39147 | /* 109227 */ GIR_RootConstrainSelectedInstOperands, |
| 39148 | /* 109228 */ // GIR_Coverage, 949, |
| 39149 | /* 109228 */ GIR_EraseRootFromParent_Done, |
| 39150 | /* 109229 */ // Label 2055: @109229 |
| 39151 | /* 109229 */ GIM_Try, /*On fail goto*//*Label 2056*/ GIMT_Encode4(109261), // Rule ID 970 // |
| 39152 | /* 109234 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 39153 | /* 109237 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39154 | /* 109241 */ // (fsub:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VSUBhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) |
| 39155 | /* 109241 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBhd), |
| 39156 | /* 109244 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 39157 | /* 109246 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 39158 | /* 109248 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 39159 | /* 109250 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39160 | /* 109253 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39161 | /* 109259 */ GIR_RootConstrainSelectedInstOperands, |
| 39162 | /* 109260 */ // GIR_Coverage, 970, |
| 39163 | /* 109260 */ GIR_EraseRootFromParent_Done, |
| 39164 | /* 109261 */ // Label 2056: @109261 |
| 39165 | /* 109261 */ GIM_Reject, |
| 39166 | /* 109262 */ // Label 2053: @109262 |
| 39167 | /* 109262 */ GIM_Reject, |
| 39168 | /* 109263 */ // Label 2042: @109263 |
| 39169 | /* 109263 */ GIM_Try, /*On fail goto*//*Label 2057*/ GIMT_Encode4(109376), |
| 39170 | /* 109268 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 39171 | /* 109271 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 39172 | /* 109274 */ GIM_Try, /*On fail goto*//*Label 2058*/ GIMT_Encode4(109314), // Rule ID 969 // |
| 39173 | /* 109279 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 39174 | /* 109282 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 39175 | /* 109286 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 39176 | /* 109290 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 39177 | /* 109294 */ // (fsub:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (VSUBfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) |
| 39178 | /* 109294 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBfq), |
| 39179 | /* 109297 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 39180 | /* 109299 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 39181 | /* 109301 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 39182 | /* 109303 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39183 | /* 109306 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39184 | /* 109312 */ GIR_RootConstrainSelectedInstOperands, |
| 39185 | /* 109313 */ // GIR_Coverage, 969, |
| 39186 | /* 109313 */ GIR_EraseRootFromParent_Done, |
| 39187 | /* 109314 */ // Label 2058: @109314 |
| 39188 | /* 109314 */ GIM_Try, /*On fail goto*//*Label 2059*/ GIMT_Encode4(109375), // Rule ID 4024 // |
| 39189 | /* 109319 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 39190 | /* 109322 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 39191 | /* 109326 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 39192 | /* 109330 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 39193 | /* 109334 */ // (fsub:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) => (MVE_VSUBf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) |
| 39194 | /* 109334 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 39195 | /* 109337 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 39196 | /* 109341 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 39197 | /* 109346 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSUBf32), |
| 39198 | /* 109349 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 39199 | /* 109351 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 39200 | /* 109353 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 39201 | /* 109355 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 39202 | /* 109358 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39203 | /* 109364 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39204 | /* 109370 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 39205 | /* 109373 */ GIR_RootConstrainSelectedInstOperands, |
| 39206 | /* 109374 */ // GIR_Coverage, 4024, |
| 39207 | /* 109374 */ GIR_EraseRootFromParent_Done, |
| 39208 | /* 109375 */ // Label 2059: @109375 |
| 39209 | /* 109375 */ GIM_Reject, |
| 39210 | /* 109376 */ // Label 2057: @109376 |
| 39211 | /* 109376 */ GIM_Reject, |
| 39212 | /* 109377 */ // Label 2043: @109377 |
| 39213 | /* 109377 */ GIM_Try, /*On fail goto*//*Label 2060*/ GIMT_Encode4(109630), |
| 39214 | /* 109382 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 39215 | /* 109385 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 39216 | /* 109388 */ GIM_Try, /*On fail goto*//*Label 2061*/ GIMT_Encode4(109458), // Rule ID 924 // |
| 39217 | /* 109393 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_UseFPVMLx), |
| 39218 | /* 109396 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 39219 | /* 109400 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 39220 | /* 109404 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 39221 | /* 109408 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL), |
| 39222 | /* 109412 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 39223 | /* 109416 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 39224 | /* 109420 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 39225 | /* 109425 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 39226 | /* 109430 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 39227 | /* 109432 */ // (fsub:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, (fmul:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)) => (VMLShq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) |
| 39228 | /* 109432 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLShq), |
| 39229 | /* 109435 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 39230 | /* 109437 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 39231 | /* 109439 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 39232 | /* 109443 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 39233 | /* 109447 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39234 | /* 109450 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39235 | /* 109456 */ GIR_RootConstrainSelectedInstOperands, |
| 39236 | /* 109457 */ // GIR_Coverage, 924, |
| 39237 | /* 109457 */ GIR_EraseRootFromParent_Done, |
| 39238 | /* 109458 */ // Label 2061: @109458 |
| 39239 | /* 109458 */ GIM_Try, /*On fail goto*//*Label 2062*/ GIMT_Encode4(109528), // Rule ID 950 // |
| 39240 | /* 109463 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_UseFusedMAC), |
| 39241 | /* 109466 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 39242 | /* 109470 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 39243 | /* 109474 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 39244 | /* 109478 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL), |
| 39245 | /* 109482 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 39246 | /* 109486 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 39247 | /* 109490 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 39248 | /* 109495 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 39249 | /* 109500 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 39250 | /* 109502 */ // (fsub:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, (fmul:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)) => (VFMShq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) |
| 39251 | /* 109502 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMShq), |
| 39252 | /* 109505 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 39253 | /* 109507 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 39254 | /* 109509 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 39255 | /* 109513 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 39256 | /* 109517 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39257 | /* 109520 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39258 | /* 109526 */ GIR_RootConstrainSelectedInstOperands, |
| 39259 | /* 109527 */ // GIR_Coverage, 950, |
| 39260 | /* 109527 */ GIR_EraseRootFromParent_Done, |
| 39261 | /* 109528 */ // Label 2062: @109528 |
| 39262 | /* 109528 */ GIM_Try, /*On fail goto*//*Label 2063*/ GIMT_Encode4(109568), // Rule ID 971 // |
| 39263 | /* 109533 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 39264 | /* 109536 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 39265 | /* 109540 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 39266 | /* 109544 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 39267 | /* 109548 */ // (fsub:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (VSUBhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) |
| 39268 | /* 109548 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBhq), |
| 39269 | /* 109551 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 39270 | /* 109553 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 39271 | /* 109555 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 39272 | /* 109557 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39273 | /* 109560 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39274 | /* 109566 */ GIR_RootConstrainSelectedInstOperands, |
| 39275 | /* 109567 */ // GIR_Coverage, 971, |
| 39276 | /* 109567 */ GIR_EraseRootFromParent_Done, |
| 39277 | /* 109568 */ // Label 2063: @109568 |
| 39278 | /* 109568 */ GIM_Try, /*On fail goto*//*Label 2064*/ GIMT_Encode4(109629), // Rule ID 4028 // |
| 39279 | /* 109573 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 39280 | /* 109576 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 39281 | /* 109580 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 39282 | /* 109584 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 39283 | /* 109588 */ // (fsub:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) => (MVE_VSUBf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) |
| 39284 | /* 109588 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 39285 | /* 109591 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 39286 | /* 109595 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 39287 | /* 109600 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSUBf16), |
| 39288 | /* 109603 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 39289 | /* 109605 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 39290 | /* 109607 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 39291 | /* 109609 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 39292 | /* 109612 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39293 | /* 109618 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39294 | /* 109624 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 39295 | /* 109627 */ GIR_RootConstrainSelectedInstOperands, |
| 39296 | /* 109628 */ // GIR_Coverage, 4028, |
| 39297 | /* 109628 */ GIR_EraseRootFromParent_Done, |
| 39298 | /* 109629 */ // Label 2064: @109629 |
| 39299 | /* 109629 */ GIM_Reject, |
| 39300 | /* 109630 */ // Label 2060: @109630 |
| 39301 | /* 109630 */ GIM_Reject, |
| 39302 | /* 109631 */ // Label 2044: @109631 |
| 39303 | /* 109631 */ GIM_Reject, |
| 39304 | /* 109632 */ // Label 36: @109632 |
| 39305 | /* 109632 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 2072*/ GIMT_Encode4(110612), |
| 39306 | /* 109643 */ /*GILLT_s16*//*Label 2065*/ GIMT_Encode4(109695), |
| 39307 | /* 109647 */ /*GILLT_s32*//*Label 2066*/ GIMT_Encode4(109742), |
| 39308 | /* 109651 */ /*GILLT_s64*//*Label 2067*/ GIMT_Encode4(110131), GIMT_Encode4(0), |
| 39309 | /* 109659 */ /*GILLT_v2s32*//*Label 2068*/ GIMT_Encode4(110290), GIMT_Encode4(0), GIMT_Encode4(0), |
| 39310 | /* 109671 */ /*GILLT_v4s16*//*Label 2069*/ GIMT_Encode4(110337), |
| 39311 | /* 109675 */ /*GILLT_v4s32*//*Label 2070*/ GIMT_Encode4(110384), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 39312 | /* 109691 */ /*GILLT_v8s16*//*Label 2071*/ GIMT_Encode4(110498), |
| 39313 | /* 109695 */ // Label 2065: @109695 |
| 39314 | /* 109695 */ GIM_Try, /*On fail goto*//*Label 2073*/ GIMT_Encode4(109741), // Rule ID 623 // |
| 39315 | /* 109700 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 39316 | /* 109703 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 39317 | /* 109706 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 39318 | /* 109709 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 39319 | /* 109713 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 39320 | /* 109717 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 39321 | /* 109721 */ // (fmul:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) => (VMULH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 39322 | /* 109721 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULH), |
| 39323 | /* 109724 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 39324 | /* 109726 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn |
| 39325 | /* 109728 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 39326 | /* 109730 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39327 | /* 109733 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39328 | /* 109739 */ GIR_RootConstrainSelectedInstOperands, |
| 39329 | /* 109740 */ // GIR_Coverage, 623, |
| 39330 | /* 109740 */ GIR_EraseRootFromParent_Done, |
| 39331 | /* 109741 */ // Label 2073: @109741 |
| 39332 | /* 109741 */ GIM_Reject, |
| 39333 | /* 109742 */ // Label 2066: @109742 |
| 39334 | /* 109742 */ GIM_Try, /*On fail goto*//*Label 2074*/ GIMT_Encode4(110130), |
| 39335 | /* 109747 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 39336 | /* 109750 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 39337 | /* 109753 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 39338 | /* 109757 */ GIM_Try, /*On fail goto*//*Label 2075*/ GIMT_Encode4(109810), // Rule ID 2302 // |
| 39339 | /* 109762 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NoHonorSignDependentRounding), |
| 39340 | /* 109765 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 39341 | /* 109769 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 39342 | /* 109773 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 39343 | /* 109777 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 39344 | /* 109782 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 39345 | /* 109786 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 39346 | /* 109788 */ // (fmul:{ *:[f32] } (fneg:{ *:[f32] } SPR:{ *:[f32] }:$a), SPR:{ *:[f32] }:$b) => (VNMULS:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b) |
| 39347 | /* 109788 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNMULS), |
| 39348 | /* 109791 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 39349 | /* 109793 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 39350 | /* 109797 */ GIR_RootToRootCopy, /*OpIdx*/2, // b |
| 39351 | /* 109799 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39352 | /* 109802 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39353 | /* 109808 */ GIR_RootConstrainSelectedInstOperands, |
| 39354 | /* 109809 */ // GIR_Coverage, 2302, |
| 39355 | /* 109809 */ GIR_EraseRootFromParent_Done, |
| 39356 | /* 109810 */ // Label 2075: @109810 |
| 39357 | /* 109810 */ GIM_Try, /*On fail goto*//*Label 2076*/ GIMT_Encode4(109863), // Rule ID 5711 // |
| 39358 | /* 109815 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NoHonorSignDependentRounding), |
| 39359 | /* 109818 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 39360 | /* 109822 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 39361 | /* 109826 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 39362 | /* 109830 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 39363 | /* 109834 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 39364 | /* 109839 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 39365 | /* 109841 */ // (fmul:{ *:[f32] } SPR:{ *:[f32] }:$b, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$a)) => (VNMULS:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b) |
| 39366 | /* 109841 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNMULS), |
| 39367 | /* 109844 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 39368 | /* 109846 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 39369 | /* 109850 */ GIR_RootToRootCopy, /*OpIdx*/1, // b |
| 39370 | /* 109852 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39371 | /* 109855 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39372 | /* 109861 */ GIR_RootConstrainSelectedInstOperands, |
| 39373 | /* 109862 */ // GIR_Coverage, 5711, |
| 39374 | /* 109862 */ GIR_EraseRootFromParent_Done, |
| 39375 | /* 109863 */ // Label 2076: @109863 |
| 39376 | /* 109863 */ GIM_Try, /*On fail goto*//*Label 2077*/ GIMT_Encode4(109899), // Rule ID 622 // |
| 39377 | /* 109868 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), |
| 39378 | /* 109871 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 39379 | /* 109875 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 39380 | /* 109879 */ // (fmul:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) => (VMULS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 39381 | /* 109879 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULS), |
| 39382 | /* 109882 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 39383 | /* 109884 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn |
| 39384 | /* 109886 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 39385 | /* 109888 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39386 | /* 109891 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39387 | /* 109897 */ GIR_RootConstrainSelectedInstOperands, |
| 39388 | /* 109898 */ // GIR_Coverage, 622, |
| 39389 | /* 109898 */ GIR_EraseRootFromParent_Done, |
| 39390 | /* 109899 */ // Label 2077: @109899 |
| 39391 | /* 109899 */ GIM_Try, /*On fail goto*//*Label 2078*/ GIMT_Encode4(110129), // Rule ID 2699 // |
| 39392 | /* 109904 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_UseNEONForFP), |
| 39393 | /* 109907 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 39394 | /* 109911 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 39395 | /* 109915 */ // (fmul:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VMULfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] }) |
| 39396 | /* 109915 */ GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32, |
| 39397 | /* 109918 */ GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 39398 | /* 109922 */ GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 39399 | /* 109927 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/8, |
| 39400 | /* 109929 */ GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32, |
| 39401 | /* 109932 */ GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 39402 | /* 109936 */ GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 39403 | /* 109941 */ GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7, |
| 39404 | /* 109944 */ GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 39405 | /* 109949 */ GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32, |
| 39406 | /* 109952 */ GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 39407 | /* 109956 */ GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 39408 | /* 109961 */ GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6, |
| 39409 | /* 109964 */ GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/2, // b |
| 39410 | /* 109968 */ GIR_AddImm8, /*InsnID*/6, /*Imm*/17, |
| 39411 | /* 109971 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 39412 | /* 109976 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 39413 | /* 109981 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 39414 | /* 109986 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32, |
| 39415 | /* 109989 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 39416 | /* 109993 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 39417 | /* 109998 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 39418 | /* 110000 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32, |
| 39419 | /* 110003 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 39420 | /* 110007 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 39421 | /* 110012 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4, |
| 39422 | /* 110015 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 39423 | /* 110020 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32, |
| 39424 | /* 110023 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 39425 | /* 110027 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 39426 | /* 110032 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3, |
| 39427 | /* 110035 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 39428 | /* 110039 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17, |
| 39429 | /* 110042 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 39430 | /* 110047 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 39431 | /* 110052 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 39432 | /* 110057 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 39433 | /* 110060 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VMULfd), |
| 39434 | /* 110064 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 39435 | /* 110069 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 39436 | /* 110072 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5, |
| 39437 | /* 110075 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14, |
| 39438 | /* 110078 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39439 | /* 110084 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 39440 | /* 110086 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32, |
| 39441 | /* 110089 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 39442 | /* 110093 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 39443 | /* 110098 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 39444 | /* 110101 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 39445 | /* 110106 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 39446 | /* 110109 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 39447 | /* 110111 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0), |
| 39448 | /* 110118 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 39449 | /* 110123 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 39450 | /* 110128 */ // GIR_Coverage, 2699, |
| 39451 | /* 110128 */ GIR_EraseRootFromParent_Done, |
| 39452 | /* 110129 */ // Label 2078: @110129 |
| 39453 | /* 110129 */ GIM_Reject, |
| 39454 | /* 110130 */ // Label 2074: @110130 |
| 39455 | /* 110130 */ GIM_Reject, |
| 39456 | /* 110131 */ // Label 2067: @110131 |
| 39457 | /* 110131 */ GIM_Try, /*On fail goto*//*Label 2079*/ GIMT_Encode4(110289), |
| 39458 | /* 110136 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 39459 | /* 110139 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 39460 | /* 110142 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39461 | /* 110146 */ GIM_Try, /*On fail goto*//*Label 2080*/ GIMT_Encode4(110199), // Rule ID 2301 // |
| 39462 | /* 110151 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_NoHonorSignDependentRounding), |
| 39463 | /* 110154 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 39464 | /* 110158 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 39465 | /* 110162 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 39466 | /* 110166 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39467 | /* 110171 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39468 | /* 110175 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 39469 | /* 110177 */ // (fmul:{ *:[f64] } (fneg:{ *:[f64] } DPR:{ *:[f64] }:$a), DPR:{ *:[f64] }:$b) => (VNMULD:{ *:[f64] } DPR:{ *:[f64] }:$a, DPR:{ *:[f64] }:$b) |
| 39470 | /* 110177 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNMULD), |
| 39471 | /* 110180 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 39472 | /* 110182 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 39473 | /* 110186 */ GIR_RootToRootCopy, /*OpIdx*/2, // b |
| 39474 | /* 110188 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39475 | /* 110191 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39476 | /* 110197 */ GIR_RootConstrainSelectedInstOperands, |
| 39477 | /* 110198 */ // GIR_Coverage, 2301, |
| 39478 | /* 110198 */ GIR_EraseRootFromParent_Done, |
| 39479 | /* 110199 */ // Label 2080: @110199 |
| 39480 | /* 110199 */ GIM_Try, /*On fail goto*//*Label 2081*/ GIMT_Encode4(110252), // Rule ID 5710 // |
| 39481 | /* 110204 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_NoHonorSignDependentRounding), |
| 39482 | /* 110207 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39483 | /* 110211 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 39484 | /* 110215 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 39485 | /* 110219 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 39486 | /* 110223 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39487 | /* 110228 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 39488 | /* 110230 */ // (fmul:{ *:[f64] } DPR:{ *:[f64] }:$b, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$a)) => (VNMULD:{ *:[f64] } DPR:{ *:[f64] }:$a, DPR:{ *:[f64] }:$b) |
| 39489 | /* 110230 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNMULD), |
| 39490 | /* 110233 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 39491 | /* 110235 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 39492 | /* 110239 */ GIR_RootToRootCopy, /*OpIdx*/1, // b |
| 39493 | /* 110241 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39494 | /* 110244 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39495 | /* 110250 */ GIR_RootConstrainSelectedInstOperands, |
| 39496 | /* 110251 */ // GIR_Coverage, 5710, |
| 39497 | /* 110251 */ GIR_EraseRootFromParent_Done, |
| 39498 | /* 110252 */ // Label 2081: @110252 |
| 39499 | /* 110252 */ GIM_Try, /*On fail goto*//*Label 2082*/ GIMT_Encode4(110288), // Rule ID 621 // |
| 39500 | /* 110257 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), |
| 39501 | /* 110260 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39502 | /* 110264 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39503 | /* 110268 */ // (fmul:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) => (VMULD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 39504 | /* 110268 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULD), |
| 39505 | /* 110271 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 39506 | /* 110273 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dn |
| 39507 | /* 110275 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm |
| 39508 | /* 110277 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39509 | /* 110280 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39510 | /* 110286 */ GIR_RootConstrainSelectedInstOperands, |
| 39511 | /* 110287 */ // GIR_Coverage, 621, |
| 39512 | /* 110287 */ GIR_EraseRootFromParent_Done, |
| 39513 | /* 110288 */ // Label 2082: @110288 |
| 39514 | /* 110288 */ GIM_Reject, |
| 39515 | /* 110289 */ // Label 2079: @110289 |
| 39516 | /* 110289 */ GIM_Reject, |
| 39517 | /* 110290 */ // Label 2068: @110290 |
| 39518 | /* 110290 */ GIM_Try, /*On fail goto*//*Label 2083*/ GIMT_Encode4(110336), // Rule ID 843 // |
| 39519 | /* 110295 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 39520 | /* 110298 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 39521 | /* 110301 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 39522 | /* 110304 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39523 | /* 110308 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39524 | /* 110312 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39525 | /* 110316 */ // (fmul:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VMULfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) |
| 39526 | /* 110316 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULfd), |
| 39527 | /* 110319 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 39528 | /* 110321 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 39529 | /* 110323 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 39530 | /* 110325 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39531 | /* 110328 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39532 | /* 110334 */ GIR_RootConstrainSelectedInstOperands, |
| 39533 | /* 110335 */ // GIR_Coverage, 843, |
| 39534 | /* 110335 */ GIR_EraseRootFromParent_Done, |
| 39535 | /* 110336 */ // Label 2083: @110336 |
| 39536 | /* 110336 */ GIM_Reject, |
| 39537 | /* 110337 */ // Label 2069: @110337 |
| 39538 | /* 110337 */ GIM_Try, /*On fail goto*//*Label 2084*/ GIMT_Encode4(110383), // Rule ID 845 // |
| 39539 | /* 110342 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 39540 | /* 110345 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 39541 | /* 110348 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 39542 | /* 110351 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39543 | /* 110355 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39544 | /* 110359 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39545 | /* 110363 */ // (fmul:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VMULhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) |
| 39546 | /* 110363 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULhd), |
| 39547 | /* 110366 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 39548 | /* 110368 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 39549 | /* 110370 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 39550 | /* 110372 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39551 | /* 110375 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39552 | /* 110381 */ GIR_RootConstrainSelectedInstOperands, |
| 39553 | /* 110382 */ // GIR_Coverage, 845, |
| 39554 | /* 110382 */ GIR_EraseRootFromParent_Done, |
| 39555 | /* 110383 */ // Label 2084: @110383 |
| 39556 | /* 110383 */ GIM_Reject, |
| 39557 | /* 110384 */ // Label 2070: @110384 |
| 39558 | /* 110384 */ GIM_Try, /*On fail goto*//*Label 2085*/ GIMT_Encode4(110497), |
| 39559 | /* 110389 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 39560 | /* 110392 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 39561 | /* 110395 */ GIM_Try, /*On fail goto*//*Label 2086*/ GIMT_Encode4(110435), // Rule ID 844 // |
| 39562 | /* 110400 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 39563 | /* 110403 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 39564 | /* 110407 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 39565 | /* 110411 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 39566 | /* 110415 */ // (fmul:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (VMULfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) |
| 39567 | /* 110415 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULfq), |
| 39568 | /* 110418 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 39569 | /* 110420 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 39570 | /* 110422 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 39571 | /* 110424 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39572 | /* 110427 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39573 | /* 110433 */ GIR_RootConstrainSelectedInstOperands, |
| 39574 | /* 110434 */ // GIR_Coverage, 844, |
| 39575 | /* 110434 */ GIR_EraseRootFromParent_Done, |
| 39576 | /* 110435 */ // Label 2086: @110435 |
| 39577 | /* 110435 */ GIM_Try, /*On fail goto*//*Label 2087*/ GIMT_Encode4(110496), // Rule ID 3988 // |
| 39578 | /* 110440 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 39579 | /* 110443 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 39580 | /* 110447 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 39581 | /* 110451 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 39582 | /* 110455 */ // (fmul:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) => (MVE_VMULf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) |
| 39583 | /* 110455 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 39584 | /* 110458 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 39585 | /* 110462 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 39586 | /* 110467 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULf32), |
| 39587 | /* 110470 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 39588 | /* 110472 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 39589 | /* 110474 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 39590 | /* 110476 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 39591 | /* 110479 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39592 | /* 110485 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39593 | /* 110491 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 39594 | /* 110494 */ GIR_RootConstrainSelectedInstOperands, |
| 39595 | /* 110495 */ // GIR_Coverage, 3988, |
| 39596 | /* 110495 */ GIR_EraseRootFromParent_Done, |
| 39597 | /* 110496 */ // Label 2087: @110496 |
| 39598 | /* 110496 */ GIM_Reject, |
| 39599 | /* 110497 */ // Label 2085: @110497 |
| 39600 | /* 110497 */ GIM_Reject, |
| 39601 | /* 110498 */ // Label 2071: @110498 |
| 39602 | /* 110498 */ GIM_Try, /*On fail goto*//*Label 2088*/ GIMT_Encode4(110611), |
| 39603 | /* 110503 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 39604 | /* 110506 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 39605 | /* 110509 */ GIM_Try, /*On fail goto*//*Label 2089*/ GIMT_Encode4(110549), // Rule ID 846 // |
| 39606 | /* 110514 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 39607 | /* 110517 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 39608 | /* 110521 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 39609 | /* 110525 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 39610 | /* 110529 */ // (fmul:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (VMULhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) |
| 39611 | /* 110529 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULhq), |
| 39612 | /* 110532 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 39613 | /* 110534 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 39614 | /* 110536 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 39615 | /* 110538 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39616 | /* 110541 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39617 | /* 110547 */ GIR_RootConstrainSelectedInstOperands, |
| 39618 | /* 110548 */ // GIR_Coverage, 846, |
| 39619 | /* 110548 */ GIR_EraseRootFromParent_Done, |
| 39620 | /* 110549 */ // Label 2089: @110549 |
| 39621 | /* 110549 */ GIM_Try, /*On fail goto*//*Label 2090*/ GIMT_Encode4(110610), // Rule ID 3992 // |
| 39622 | /* 110554 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 39623 | /* 110557 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 39624 | /* 110561 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 39625 | /* 110565 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 39626 | /* 110569 */ // (fmul:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) => (MVE_VMULf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) |
| 39627 | /* 110569 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 39628 | /* 110572 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 39629 | /* 110576 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 39630 | /* 110581 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULf16), |
| 39631 | /* 110584 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 39632 | /* 110586 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 39633 | /* 110588 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 39634 | /* 110590 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 39635 | /* 110593 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39636 | /* 110599 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39637 | /* 110605 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 39638 | /* 110608 */ GIR_RootConstrainSelectedInstOperands, |
| 39639 | /* 110609 */ // GIR_Coverage, 3992, |
| 39640 | /* 110609 */ GIR_EraseRootFromParent_Done, |
| 39641 | /* 110610 */ // Label 2090: @110610 |
| 39642 | /* 110610 */ GIM_Reject, |
| 39643 | /* 110611 */ // Label 2088: @110611 |
| 39644 | /* 110611 */ GIM_Reject, |
| 39645 | /* 110612 */ // Label 2072: @110612 |
| 39646 | /* 110612 */ GIM_Reject, |
| 39647 | /* 110613 */ // Label 37: @110613 |
| 39648 | /* 110613 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 2098*/ GIMT_Encode4(112703), |
| 39649 | /* 110624 */ /*GILLT_s16*//*Label 2091*/ GIMT_Encode4(110676), |
| 39650 | /* 110628 */ /*GILLT_s32*//*Label 2092*/ GIMT_Encode4(111063), |
| 39651 | /* 110632 */ /*GILLT_s64*//*Label 2093*/ GIMT_Encode4(111450), GIMT_Encode4(0), |
| 39652 | /* 110640 */ /*GILLT_v2s32*//*Label 2094*/ GIMT_Encode4(111837), GIMT_Encode4(0), GIMT_Encode4(0), |
| 39653 | /* 110652 */ /*GILLT_v4s16*//*Label 2095*/ GIMT_Encode4(112017), |
| 39654 | /* 110656 */ /*GILLT_v4s32*//*Label 2096*/ GIMT_Encode4(112073), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 39655 | /* 110672 */ /*GILLT_v8s16*//*Label 2097*/ GIMT_Encode4(112451), |
| 39656 | /* 110676 */ // Label 2091: @110676 |
| 39657 | /* 110676 */ GIM_Try, /*On fail goto*//*Label 2099*/ GIMT_Encode4(111062), |
| 39658 | /* 110681 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 39659 | /* 110684 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 39660 | /* 110687 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s16, |
| 39661 | /* 110690 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 39662 | /* 110694 */ GIM_Try, /*On fail goto*//*Label 2100*/ GIMT_Encode4(110768), // Rule ID 2406 // |
| 39663 | /* 110699 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 39664 | /* 110702 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 39665 | /* 110706 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 39666 | /* 110710 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 39667 | /* 110714 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 39668 | /* 110719 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 39669 | /* 110723 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 39670 | /* 110727 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 39671 | /* 110731 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 39672 | /* 110735 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 39673 | /* 110740 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 39674 | /* 110742 */ // (fma:{ *:[f16] } (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), HPR:{ *:[f16] }:$Sm, (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sdin)) => (VFNMAH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 39675 | /* 110742 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAH), |
| 39676 | /* 110745 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 39677 | /* 110747 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sdin |
| 39678 | /* 110751 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn |
| 39679 | /* 110755 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 39680 | /* 110757 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39681 | /* 110760 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39682 | /* 110766 */ GIR_RootConstrainSelectedInstOperands, |
| 39683 | /* 110767 */ // GIR_Coverage, 2406, |
| 39684 | /* 110767 */ GIR_EraseRootFromParent_Done, |
| 39685 | /* 110768 */ // Label 2100: @110768 |
| 39686 | /* 110768 */ GIM_Try, /*On fail goto*//*Label 2101*/ GIMT_Encode4(110842), // Rule ID 5719 // |
| 39687 | /* 110773 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 39688 | /* 110776 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 39689 | /* 110780 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 39690 | /* 110784 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 39691 | /* 110788 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 39692 | /* 110792 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 39693 | /* 110797 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 39694 | /* 110801 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 39695 | /* 110805 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 39696 | /* 110809 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 39697 | /* 110814 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 39698 | /* 110816 */ // (fma:{ *:[f16] } HPR:{ *:[f16] }:$Sm, (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sdin)) => (VFNMAH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 39699 | /* 110816 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAH), |
| 39700 | /* 110819 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 39701 | /* 110821 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sdin |
| 39702 | /* 110825 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn |
| 39703 | /* 110829 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm |
| 39704 | /* 110831 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39705 | /* 110834 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39706 | /* 110840 */ GIR_RootConstrainSelectedInstOperands, |
| 39707 | /* 110841 */ // GIR_Coverage, 5719, |
| 39708 | /* 110841 */ GIR_EraseRootFromParent_Done, |
| 39709 | /* 110842 */ // Label 2101: @110842 |
| 39710 | /* 110842 */ GIM_Try, /*On fail goto*//*Label 2102*/ GIMT_Encode4(110901), // Rule ID 2398 // |
| 39711 | /* 110847 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 39712 | /* 110850 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 39713 | /* 110854 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 39714 | /* 110858 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 39715 | /* 110862 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 39716 | /* 110867 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 39717 | /* 110871 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 39718 | /* 110875 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 39719 | /* 110877 */ // (fma:{ *:[f16] } (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), HPR:{ *:[f16] }:$Sm, HPR:{ *:[f16] }:$Sdin) => (VFMSH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 39720 | /* 110877 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSH), |
| 39721 | /* 110880 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 39722 | /* 110882 */ GIR_RootToRootCopy, /*OpIdx*/3, // Sdin |
| 39723 | /* 110884 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn |
| 39724 | /* 110888 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 39725 | /* 110890 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39726 | /* 110893 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39727 | /* 110899 */ GIR_RootConstrainSelectedInstOperands, |
| 39728 | /* 110900 */ // GIR_Coverage, 2398, |
| 39729 | /* 110900 */ GIR_EraseRootFromParent_Done, |
| 39730 | /* 110901 */ // Label 2102: @110901 |
| 39731 | /* 110901 */ GIM_Try, /*On fail goto*//*Label 2103*/ GIMT_Encode4(110960), // Rule ID 5716 // |
| 39732 | /* 110906 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 39733 | /* 110909 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 39734 | /* 110913 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 39735 | /* 110917 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 39736 | /* 110921 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 39737 | /* 110925 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 39738 | /* 110930 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 39739 | /* 110934 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 39740 | /* 110936 */ // (fma:{ *:[f16] } HPR:{ *:[f16] }:$Sm, (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), HPR:{ *:[f16] }:$Sdin) => (VFMSH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 39741 | /* 110936 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSH), |
| 39742 | /* 110939 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 39743 | /* 110941 */ GIR_RootToRootCopy, /*OpIdx*/3, // Sdin |
| 39744 | /* 110943 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn |
| 39745 | /* 110947 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm |
| 39746 | /* 110949 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39747 | /* 110952 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39748 | /* 110958 */ GIR_RootConstrainSelectedInstOperands, |
| 39749 | /* 110959 */ // GIR_Coverage, 5716, |
| 39750 | /* 110959 */ GIR_EraseRootFromParent_Done, |
| 39751 | /* 110960 */ // Label 2103: @110960 |
| 39752 | /* 110960 */ GIM_Try, /*On fail goto*//*Label 2104*/ GIMT_Encode4(111019), // Rule ID 2411 // |
| 39753 | /* 110965 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 39754 | /* 110968 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 39755 | /* 110972 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 39756 | /* 110976 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 39757 | /* 110980 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 39758 | /* 110984 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 39759 | /* 110988 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 39760 | /* 110993 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 39761 | /* 110995 */ // (fma:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm, (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sdin)) => (VFNMSH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 39762 | /* 110995 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSH), |
| 39763 | /* 110998 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 39764 | /* 111000 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sdin |
| 39765 | /* 111004 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn |
| 39766 | /* 111006 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 39767 | /* 111008 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39768 | /* 111011 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39769 | /* 111017 */ GIR_RootConstrainSelectedInstOperands, |
| 39770 | /* 111018 */ // GIR_Coverage, 2411, |
| 39771 | /* 111018 */ GIR_EraseRootFromParent_Done, |
| 39772 | /* 111019 */ // Label 2104: @111019 |
| 39773 | /* 111019 */ GIM_Try, /*On fail goto*//*Label 2105*/ GIMT_Encode4(111061), // Rule ID 2392 // |
| 39774 | /* 111024 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 39775 | /* 111027 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 39776 | /* 111031 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 39777 | /* 111035 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 39778 | /* 111039 */ // (fma:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm, HPR:{ *:[f16] }:$Sdin) => (VFMAH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 39779 | /* 111039 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAH), |
| 39780 | /* 111042 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 39781 | /* 111044 */ GIR_RootToRootCopy, /*OpIdx*/3, // Sdin |
| 39782 | /* 111046 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn |
| 39783 | /* 111048 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 39784 | /* 111050 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39785 | /* 111053 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39786 | /* 111059 */ GIR_RootConstrainSelectedInstOperands, |
| 39787 | /* 111060 */ // GIR_Coverage, 2392, |
| 39788 | /* 111060 */ GIR_EraseRootFromParent_Done, |
| 39789 | /* 111061 */ // Label 2105: @111061 |
| 39790 | /* 111061 */ GIM_Reject, |
| 39791 | /* 111062 */ // Label 2099: @111062 |
| 39792 | /* 111062 */ GIM_Reject, |
| 39793 | /* 111063 */ // Label 2092: @111063 |
| 39794 | /* 111063 */ GIM_Try, /*On fail goto*//*Label 2106*/ GIMT_Encode4(111449), |
| 39795 | /* 111068 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 39796 | /* 111071 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 39797 | /* 111074 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 39798 | /* 111077 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 39799 | /* 111081 */ GIM_Try, /*On fail goto*//*Label 2107*/ GIMT_Encode4(111155), // Rule ID 2405 // |
| 39800 | /* 111086 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP4), |
| 39801 | /* 111089 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 39802 | /* 111093 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 39803 | /* 111097 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 39804 | /* 111101 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 39805 | /* 111106 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 39806 | /* 111110 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 39807 | /* 111114 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 39808 | /* 111118 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 39809 | /* 111122 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 39810 | /* 111127 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 39811 | /* 111129 */ // (fma:{ *:[f32] } (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), SPR:{ *:[f32] }:$Sm, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sdin)) => (VFNMAS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 39812 | /* 111129 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAS), |
| 39813 | /* 111132 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 39814 | /* 111134 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sdin |
| 39815 | /* 111138 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn |
| 39816 | /* 111142 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 39817 | /* 111144 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39818 | /* 111147 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39819 | /* 111153 */ GIR_RootConstrainSelectedInstOperands, |
| 39820 | /* 111154 */ // GIR_Coverage, 2405, |
| 39821 | /* 111154 */ GIR_EraseRootFromParent_Done, |
| 39822 | /* 111155 */ // Label 2107: @111155 |
| 39823 | /* 111155 */ GIM_Try, /*On fail goto*//*Label 2108*/ GIMT_Encode4(111229), // Rule ID 5718 // |
| 39824 | /* 111160 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP4), |
| 39825 | /* 111163 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 39826 | /* 111167 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 39827 | /* 111171 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 39828 | /* 111175 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 39829 | /* 111179 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 39830 | /* 111184 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 39831 | /* 111188 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 39832 | /* 111192 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 39833 | /* 111196 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 39834 | /* 111201 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 39835 | /* 111203 */ // (fma:{ *:[f32] } SPR:{ *:[f32] }:$Sm, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sdin)) => (VFNMAS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 39836 | /* 111203 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAS), |
| 39837 | /* 111206 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 39838 | /* 111208 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sdin |
| 39839 | /* 111212 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn |
| 39840 | /* 111216 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm |
| 39841 | /* 111218 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39842 | /* 111221 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39843 | /* 111227 */ GIR_RootConstrainSelectedInstOperands, |
| 39844 | /* 111228 */ // GIR_Coverage, 5718, |
| 39845 | /* 111228 */ GIR_EraseRootFromParent_Done, |
| 39846 | /* 111229 */ // Label 2108: @111229 |
| 39847 | /* 111229 */ GIM_Try, /*On fail goto*//*Label 2109*/ GIMT_Encode4(111288), // Rule ID 2397 // |
| 39848 | /* 111234 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP4), |
| 39849 | /* 111237 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 39850 | /* 111241 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 39851 | /* 111245 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 39852 | /* 111249 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 39853 | /* 111254 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 39854 | /* 111258 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 39855 | /* 111262 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 39856 | /* 111264 */ // (fma:{ *:[f32] } (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), SPR:{ *:[f32] }:$Sm, SPR:{ *:[f32] }:$Sdin) => (VFMSS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 39857 | /* 111264 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSS), |
| 39858 | /* 111267 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 39859 | /* 111269 */ GIR_RootToRootCopy, /*OpIdx*/3, // Sdin |
| 39860 | /* 111271 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn |
| 39861 | /* 111275 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 39862 | /* 111277 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39863 | /* 111280 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39864 | /* 111286 */ GIR_RootConstrainSelectedInstOperands, |
| 39865 | /* 111287 */ // GIR_Coverage, 2397, |
| 39866 | /* 111287 */ GIR_EraseRootFromParent_Done, |
| 39867 | /* 111288 */ // Label 2109: @111288 |
| 39868 | /* 111288 */ GIM_Try, /*On fail goto*//*Label 2110*/ GIMT_Encode4(111347), // Rule ID 5715 // |
| 39869 | /* 111293 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP4), |
| 39870 | /* 111296 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 39871 | /* 111300 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 39872 | /* 111304 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 39873 | /* 111308 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 39874 | /* 111312 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 39875 | /* 111317 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 39876 | /* 111321 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 39877 | /* 111323 */ // (fma:{ *:[f32] } SPR:{ *:[f32] }:$Sm, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), SPR:{ *:[f32] }:$Sdin) => (VFMSS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 39878 | /* 111323 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSS), |
| 39879 | /* 111326 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 39880 | /* 111328 */ GIR_RootToRootCopy, /*OpIdx*/3, // Sdin |
| 39881 | /* 111330 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn |
| 39882 | /* 111334 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm |
| 39883 | /* 111336 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39884 | /* 111339 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39885 | /* 111345 */ GIR_RootConstrainSelectedInstOperands, |
| 39886 | /* 111346 */ // GIR_Coverage, 5715, |
| 39887 | /* 111346 */ GIR_EraseRootFromParent_Done, |
| 39888 | /* 111347 */ // Label 2110: @111347 |
| 39889 | /* 111347 */ GIM_Try, /*On fail goto*//*Label 2111*/ GIMT_Encode4(111406), // Rule ID 2410 // |
| 39890 | /* 111352 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP4), |
| 39891 | /* 111355 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 39892 | /* 111359 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 39893 | /* 111363 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 39894 | /* 111367 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 39895 | /* 111371 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 39896 | /* 111375 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 39897 | /* 111380 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 39898 | /* 111382 */ // (fma:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sdin)) => (VFNMSS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 39899 | /* 111382 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSS), |
| 39900 | /* 111385 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 39901 | /* 111387 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sdin |
| 39902 | /* 111391 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn |
| 39903 | /* 111393 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 39904 | /* 111395 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39905 | /* 111398 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39906 | /* 111404 */ GIR_RootConstrainSelectedInstOperands, |
| 39907 | /* 111405 */ // GIR_Coverage, 2410, |
| 39908 | /* 111405 */ GIR_EraseRootFromParent_Done, |
| 39909 | /* 111406 */ // Label 2111: @111406 |
| 39910 | /* 111406 */ GIM_Try, /*On fail goto*//*Label 2112*/ GIMT_Encode4(111448), // Rule ID 2391 // |
| 39911 | /* 111411 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP4), |
| 39912 | /* 111414 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 39913 | /* 111418 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 39914 | /* 111422 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 39915 | /* 111426 */ // (fma:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm, SPR:{ *:[f32] }:$Sdin) => (VFMAS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 39916 | /* 111426 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAS), |
| 39917 | /* 111429 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 39918 | /* 111431 */ GIR_RootToRootCopy, /*OpIdx*/3, // Sdin |
| 39919 | /* 111433 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn |
| 39920 | /* 111435 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 39921 | /* 111437 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39922 | /* 111440 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39923 | /* 111446 */ GIR_RootConstrainSelectedInstOperands, |
| 39924 | /* 111447 */ // GIR_Coverage, 2391, |
| 39925 | /* 111447 */ GIR_EraseRootFromParent_Done, |
| 39926 | /* 111448 */ // Label 2112: @111448 |
| 39927 | /* 111448 */ GIM_Reject, |
| 39928 | /* 111449 */ // Label 2106: @111449 |
| 39929 | /* 111449 */ GIM_Reject, |
| 39930 | /* 111450 */ // Label 2093: @111450 |
| 39931 | /* 111450 */ GIM_Try, /*On fail goto*//*Label 2113*/ GIMT_Encode4(111836), |
| 39932 | /* 111455 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 39933 | /* 111458 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 39934 | /* 111461 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 39935 | /* 111464 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39936 | /* 111468 */ GIM_Try, /*On fail goto*//*Label 2114*/ GIMT_Encode4(111542), // Rule ID 2404 // |
| 39937 | /* 111473 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4), |
| 39938 | /* 111476 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 39939 | /* 111480 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 39940 | /* 111484 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 39941 | /* 111488 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39942 | /* 111493 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39943 | /* 111497 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 39944 | /* 111501 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 39945 | /* 111505 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 39946 | /* 111509 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39947 | /* 111514 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 39948 | /* 111516 */ // (fma:{ *:[f64] } (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), DPR:{ *:[f64] }:$Dm, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Ddin)) => (VFNMAD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 39949 | /* 111516 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAD), |
| 39950 | /* 111519 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 39951 | /* 111521 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ddin |
| 39952 | /* 111525 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn |
| 39953 | /* 111529 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm |
| 39954 | /* 111531 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39955 | /* 111534 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39956 | /* 111540 */ GIR_RootConstrainSelectedInstOperands, |
| 39957 | /* 111541 */ // GIR_Coverage, 2404, |
| 39958 | /* 111541 */ GIR_EraseRootFromParent_Done, |
| 39959 | /* 111542 */ // Label 2114: @111542 |
| 39960 | /* 111542 */ GIM_Try, /*On fail goto*//*Label 2115*/ GIMT_Encode4(111616), // Rule ID 5717 // |
| 39961 | /* 111547 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4), |
| 39962 | /* 111550 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39963 | /* 111554 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 39964 | /* 111558 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 39965 | /* 111562 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 39966 | /* 111566 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39967 | /* 111571 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 39968 | /* 111575 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 39969 | /* 111579 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 39970 | /* 111583 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39971 | /* 111588 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 39972 | /* 111590 */ // (fma:{ *:[f64] } DPR:{ *:[f64] }:$Dm, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Ddin)) => (VFNMAD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 39973 | /* 111590 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAD), |
| 39974 | /* 111593 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 39975 | /* 111595 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ddin |
| 39976 | /* 111599 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn |
| 39977 | /* 111603 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dm |
| 39978 | /* 111605 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39979 | /* 111608 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39980 | /* 111614 */ GIR_RootConstrainSelectedInstOperands, |
| 39981 | /* 111615 */ // GIR_Coverage, 5717, |
| 39982 | /* 111615 */ GIR_EraseRootFromParent_Done, |
| 39983 | /* 111616 */ // Label 2115: @111616 |
| 39984 | /* 111616 */ GIM_Try, /*On fail goto*//*Label 2116*/ GIMT_Encode4(111675), // Rule ID 2396 // |
| 39985 | /* 111621 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4), |
| 39986 | /* 111624 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 39987 | /* 111628 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 39988 | /* 111632 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 39989 | /* 111636 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39990 | /* 111641 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39991 | /* 111645 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39992 | /* 111649 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 39993 | /* 111651 */ // (fma:{ *:[f64] } (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), DPR:{ *:[f64] }:$Dm, DPR:{ *:[f64] }:$Ddin) => (VFMSD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 39994 | /* 111651 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSD), |
| 39995 | /* 111654 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 39996 | /* 111656 */ GIR_RootToRootCopy, /*OpIdx*/3, // Ddin |
| 39997 | /* 111658 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn |
| 39998 | /* 111662 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm |
| 39999 | /* 111664 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40000 | /* 111667 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40001 | /* 111673 */ GIR_RootConstrainSelectedInstOperands, |
| 40002 | /* 111674 */ // GIR_Coverage, 2396, |
| 40003 | /* 111674 */ GIR_EraseRootFromParent_Done, |
| 40004 | /* 111675 */ // Label 2116: @111675 |
| 40005 | /* 111675 */ GIM_Try, /*On fail goto*//*Label 2117*/ GIMT_Encode4(111734), // Rule ID 5714 // |
| 40006 | /* 111680 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4), |
| 40007 | /* 111683 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40008 | /* 111687 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 40009 | /* 111691 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 40010 | /* 111695 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 40011 | /* 111699 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40012 | /* 111704 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40013 | /* 111708 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 40014 | /* 111710 */ // (fma:{ *:[f64] } DPR:{ *:[f64] }:$Dm, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), DPR:{ *:[f64] }:$Ddin) => (VFMSD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 40015 | /* 111710 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSD), |
| 40016 | /* 111713 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 40017 | /* 111715 */ GIR_RootToRootCopy, /*OpIdx*/3, // Ddin |
| 40018 | /* 111717 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn |
| 40019 | /* 111721 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dm |
| 40020 | /* 111723 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40021 | /* 111726 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40022 | /* 111732 */ GIR_RootConstrainSelectedInstOperands, |
| 40023 | /* 111733 */ // GIR_Coverage, 5714, |
| 40024 | /* 111733 */ GIR_EraseRootFromParent_Done, |
| 40025 | /* 111734 */ // Label 2117: @111734 |
| 40026 | /* 111734 */ GIM_Try, /*On fail goto*//*Label 2118*/ GIMT_Encode4(111793), // Rule ID 2409 // |
| 40027 | /* 111739 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4), |
| 40028 | /* 111742 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40029 | /* 111746 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40030 | /* 111750 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 40031 | /* 111754 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 40032 | /* 111758 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 40033 | /* 111762 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40034 | /* 111767 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 40035 | /* 111769 */ // (fma:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Ddin)) => (VFNMSD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 40036 | /* 111769 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSD), |
| 40037 | /* 111772 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 40038 | /* 111774 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Ddin |
| 40039 | /* 111778 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dn |
| 40040 | /* 111780 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm |
| 40041 | /* 111782 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40042 | /* 111785 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40043 | /* 111791 */ GIR_RootConstrainSelectedInstOperands, |
| 40044 | /* 111792 */ // GIR_Coverage, 2409, |
| 40045 | /* 111792 */ GIR_EraseRootFromParent_Done, |
| 40046 | /* 111793 */ // Label 2118: @111793 |
| 40047 | /* 111793 */ GIM_Try, /*On fail goto*//*Label 2119*/ GIMT_Encode4(111835), // Rule ID 2390 // |
| 40048 | /* 111798 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4), |
| 40049 | /* 111801 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40050 | /* 111805 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40051 | /* 111809 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40052 | /* 111813 */ // (fma:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm, DPR:{ *:[f64] }:$Ddin) => (VFMAD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 40053 | /* 111813 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAD), |
| 40054 | /* 111816 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 40055 | /* 111818 */ GIR_RootToRootCopy, /*OpIdx*/3, // Ddin |
| 40056 | /* 111820 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dn |
| 40057 | /* 111822 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm |
| 40058 | /* 111824 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40059 | /* 111827 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40060 | /* 111833 */ GIR_RootConstrainSelectedInstOperands, |
| 40061 | /* 111834 */ // GIR_Coverage, 2390, |
| 40062 | /* 111834 */ GIR_EraseRootFromParent_Done, |
| 40063 | /* 111835 */ // Label 2119: @111835 |
| 40064 | /* 111835 */ GIM_Reject, |
| 40065 | /* 111836 */ // Label 2113: @111836 |
| 40066 | /* 111836 */ GIM_Reject, |
| 40067 | /* 111837 */ // Label 2094: @111837 |
| 40068 | /* 111837 */ GIM_Try, /*On fail goto*//*Label 2120*/ GIMT_Encode4(112016), |
| 40069 | /* 111842 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 40070 | /* 111845 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 40071 | /* 111848 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 40072 | /* 111851 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40073 | /* 111855 */ GIM_Try, /*On fail goto*//*Label 2121*/ GIMT_Encode4(111914), // Rule ID 2503 // |
| 40074 | /* 111860 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasVFP4), |
| 40075 | /* 111863 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 40076 | /* 111867 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 40077 | /* 111871 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 40078 | /* 111875 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40079 | /* 111880 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40080 | /* 111884 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40081 | /* 111888 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 40082 | /* 111890 */ // (fma:{ *:[v2f32] } (fneg:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn), DPR:{ *:[v2f32] }:$Vm, DPR:{ *:[v2f32] }:$src1) => (VFMSfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$src1, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) |
| 40083 | /* 111890 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSfd), |
| 40084 | /* 111893 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 40085 | /* 111895 */ GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 40086 | /* 111897 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 40087 | /* 111901 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 40088 | /* 111903 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40089 | /* 111906 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40090 | /* 111912 */ GIR_RootConstrainSelectedInstOperands, |
| 40091 | /* 111913 */ // GIR_Coverage, 2503, |
| 40092 | /* 111913 */ GIR_EraseRootFromParent_Done, |
| 40093 | /* 111914 */ // Label 2121: @111914 |
| 40094 | /* 111914 */ GIM_Try, /*On fail goto*//*Label 2122*/ GIMT_Encode4(111973), // Rule ID 5757 // |
| 40095 | /* 111919 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasVFP4), |
| 40096 | /* 111922 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40097 | /* 111926 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 40098 | /* 111930 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 40099 | /* 111934 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 40100 | /* 111938 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40101 | /* 111943 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40102 | /* 111947 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 40103 | /* 111949 */ // (fma:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm, (fneg:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn), DPR:{ *:[v2f32] }:$src1) => (VFMSfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$src1, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) |
| 40104 | /* 111949 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSfd), |
| 40105 | /* 111952 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 40106 | /* 111954 */ GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 40107 | /* 111956 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 40108 | /* 111960 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 40109 | /* 111962 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40110 | /* 111965 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40111 | /* 111971 */ GIR_RootConstrainSelectedInstOperands, |
| 40112 | /* 111972 */ // GIR_Coverage, 5757, |
| 40113 | /* 111972 */ GIR_EraseRootFromParent_Done, |
| 40114 | /* 111973 */ // Label 2122: @111973 |
| 40115 | /* 111973 */ GIM_Try, /*On fail goto*//*Label 2123*/ GIMT_Encode4(112015), // Rule ID 2501 // |
| 40116 | /* 111978 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasVFP4), |
| 40117 | /* 111981 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40118 | /* 111985 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40119 | /* 111989 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40120 | /* 111993 */ // (fma:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm, DPR:{ *:[v2f32] }:$src1) => (VFMAfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$src1, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) |
| 40121 | /* 111993 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAfd), |
| 40122 | /* 111996 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 40123 | /* 111998 */ GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 40124 | /* 112000 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 40125 | /* 112002 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 40126 | /* 112004 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40127 | /* 112007 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40128 | /* 112013 */ GIR_RootConstrainSelectedInstOperands, |
| 40129 | /* 112014 */ // GIR_Coverage, 2501, |
| 40130 | /* 112014 */ GIR_EraseRootFromParent_Done, |
| 40131 | /* 112015 */ // Label 2123: @112015 |
| 40132 | /* 112015 */ GIM_Reject, |
| 40133 | /* 112016 */ // Label 2120: @112016 |
| 40134 | /* 112016 */ GIM_Reject, |
| 40135 | /* 112017 */ // Label 2095: @112017 |
| 40136 | /* 112017 */ GIM_Try, /*On fail goto*//*Label 2124*/ GIMT_Encode4(112072), // Rule ID 2499 // |
| 40137 | /* 112022 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 40138 | /* 112025 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 40139 | /* 112028 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 40140 | /* 112031 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 40141 | /* 112034 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40142 | /* 112038 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40143 | /* 112042 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40144 | /* 112046 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40145 | /* 112050 */ // (fma:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm, DPR:{ *:[v4f16] }:$src1) => (VFMAhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) |
| 40146 | /* 112050 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAhd), |
| 40147 | /* 112053 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 40148 | /* 112055 */ GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 40149 | /* 112057 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 40150 | /* 112059 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 40151 | /* 112061 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40152 | /* 112064 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40153 | /* 112070 */ GIR_RootConstrainSelectedInstOperands, |
| 40154 | /* 112071 */ // GIR_Coverage, 2499, |
| 40155 | /* 112071 */ GIR_EraseRootFromParent_Done, |
| 40156 | /* 112072 */ // Label 2124: @112072 |
| 40157 | /* 112072 */ GIM_Reject, |
| 40158 | /* 112073 */ // Label 2096: @112073 |
| 40159 | /* 112073 */ GIM_Try, /*On fail goto*//*Label 2125*/ GIMT_Encode4(112450), |
| 40160 | /* 112078 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 40161 | /* 112081 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 40162 | /* 112084 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 40163 | /* 112087 */ GIM_Try, /*On fail goto*//*Label 2126*/ GIMT_Encode4(112150), // Rule ID 2504 // |
| 40164 | /* 112092 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasVFP4), |
| 40165 | /* 112095 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 40166 | /* 112099 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 40167 | /* 112103 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 40168 | /* 112107 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 40169 | /* 112111 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 40170 | /* 112116 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 40171 | /* 112120 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 40172 | /* 112124 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 40173 | /* 112126 */ // (fma:{ *:[v4f32] } (fneg:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn), QPR:{ *:[v4f32] }:$Vm, QPR:{ *:[v4f32] }:$src1) => (VFMSfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$src1, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) |
| 40174 | /* 112126 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSfq), |
| 40175 | /* 112129 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 40176 | /* 112131 */ GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 40177 | /* 112133 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 40178 | /* 112137 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 40179 | /* 112139 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40180 | /* 112142 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40181 | /* 112148 */ GIR_RootConstrainSelectedInstOperands, |
| 40182 | /* 112149 */ // GIR_Coverage, 2504, |
| 40183 | /* 112149 */ GIR_EraseRootFromParent_Done, |
| 40184 | /* 112150 */ // Label 2126: @112150 |
| 40185 | /* 112150 */ GIM_Try, /*On fail goto*//*Label 2127*/ GIMT_Encode4(112219), // Rule ID 4002 // |
| 40186 | /* 112155 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 40187 | /* 112158 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 40188 | /* 112162 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 40189 | /* 112166 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 40190 | /* 112170 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 40191 | /* 112174 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 40192 | /* 112179 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 40193 | /* 112183 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 40194 | /* 112187 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 40195 | /* 112189 */ // (fma:{ *:[v4f32] } (fneg:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$m1), MQPR:{ *:[v4f32] }:$m2, MQPR:{ *:[v4f32] }:$add) => (MVE_VFMSf32:{ *:[v4f32] } ?:{ *:[v4f32] }:$add, ?:{ *:[v4f32] }:$m1, ?:{ *:[v4f32] }:$m2) |
| 40196 | /* 112189 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VFMSf32), |
| 40197 | /* 112192 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 40198 | /* 112194 */ GIR_RootToRootCopy, /*OpIdx*/3, // add |
| 40199 | /* 112196 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // m1 |
| 40200 | /* 112200 */ GIR_RootToRootCopy, /*OpIdx*/2, // m2 |
| 40201 | /* 112202 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 40202 | /* 112205 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40203 | /* 112211 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40204 | /* 112217 */ GIR_RootConstrainSelectedInstOperands, |
| 40205 | /* 112218 */ // GIR_Coverage, 4002, |
| 40206 | /* 112218 */ GIR_EraseRootFromParent_Done, |
| 40207 | /* 112219 */ // Label 2127: @112219 |
| 40208 | /* 112219 */ GIM_Try, /*On fail goto*//*Label 2128*/ GIMT_Encode4(112282), // Rule ID 5758 // |
| 40209 | /* 112224 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasVFP4), |
| 40210 | /* 112227 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 40211 | /* 112231 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 40212 | /* 112235 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 40213 | /* 112239 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 40214 | /* 112243 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 40215 | /* 112247 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 40216 | /* 112252 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 40217 | /* 112256 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 40218 | /* 112258 */ // (fma:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm, (fneg:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn), QPR:{ *:[v4f32] }:$src1) => (VFMSfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$src1, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) |
| 40219 | /* 112258 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSfq), |
| 40220 | /* 112261 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 40221 | /* 112263 */ GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 40222 | /* 112265 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 40223 | /* 112269 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 40224 | /* 112271 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40225 | /* 112274 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40226 | /* 112280 */ GIR_RootConstrainSelectedInstOperands, |
| 40227 | /* 112281 */ // GIR_Coverage, 5758, |
| 40228 | /* 112281 */ GIR_EraseRootFromParent_Done, |
| 40229 | /* 112282 */ // Label 2128: @112282 |
| 40230 | /* 112282 */ GIM_Try, /*On fail goto*//*Label 2129*/ GIMT_Encode4(112351), // Rule ID 6038 // |
| 40231 | /* 112287 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 40232 | /* 112290 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 40233 | /* 112294 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 40234 | /* 112298 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 40235 | /* 112302 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 40236 | /* 112306 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 40237 | /* 112310 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 40238 | /* 112315 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 40239 | /* 112319 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 40240 | /* 112321 */ // (fma:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$m2, (fneg:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$m1), MQPR:{ *:[v4f32] }:$add) => (MVE_VFMSf32:{ *:[v4f32] } ?:{ *:[v4f32] }:$add, ?:{ *:[v4f32] }:$m1, ?:{ *:[v4f32] }:$m2) |
| 40241 | /* 112321 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VFMSf32), |
| 40242 | /* 112324 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 40243 | /* 112326 */ GIR_RootToRootCopy, /*OpIdx*/3, // add |
| 40244 | /* 112328 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // m1 |
| 40245 | /* 112332 */ GIR_RootToRootCopy, /*OpIdx*/1, // m2 |
| 40246 | /* 112334 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 40247 | /* 112337 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40248 | /* 112343 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40249 | /* 112349 */ GIR_RootConstrainSelectedInstOperands, |
| 40250 | /* 112350 */ // GIR_Coverage, 6038, |
| 40251 | /* 112350 */ GIR_EraseRootFromParent_Done, |
| 40252 | /* 112351 */ // Label 2129: @112351 |
| 40253 | /* 112351 */ GIM_Try, /*On fail goto*//*Label 2130*/ GIMT_Encode4(112397), // Rule ID 2502 // |
| 40254 | /* 112356 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasVFP4), |
| 40255 | /* 112359 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 40256 | /* 112363 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 40257 | /* 112367 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 40258 | /* 112371 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 40259 | /* 112375 */ // (fma:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm, QPR:{ *:[v4f32] }:$src1) => (VFMAfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$src1, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) |
| 40260 | /* 112375 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAfq), |
| 40261 | /* 112378 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 40262 | /* 112380 */ GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 40263 | /* 112382 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 40264 | /* 112384 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 40265 | /* 112386 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40266 | /* 112389 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40267 | /* 112395 */ GIR_RootConstrainSelectedInstOperands, |
| 40268 | /* 112396 */ // GIR_Coverage, 2502, |
| 40269 | /* 112396 */ GIR_EraseRootFromParent_Done, |
| 40270 | /* 112397 */ // Label 2130: @112397 |
| 40271 | /* 112397 */ GIM_Try, /*On fail goto*//*Label 2131*/ GIMT_Encode4(112449), // Rule ID 4006 // |
| 40272 | /* 112402 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 40273 | /* 112405 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 40274 | /* 112409 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 40275 | /* 112413 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 40276 | /* 112417 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 40277 | /* 112421 */ // (fma:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$m1, MQPR:{ *:[v4f32] }:$m2, MQPR:{ *:[v4f32] }:$add) => (MVE_VFMAf32:{ *:[v4f32] } ?:{ *:[v4f32] }:$add, ?:{ *:[v4f32] }:$m1, ?:{ *:[v4f32] }:$m2) |
| 40278 | /* 112421 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VFMAf32), |
| 40279 | /* 112424 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 40280 | /* 112426 */ GIR_RootToRootCopy, /*OpIdx*/3, // add |
| 40281 | /* 112428 */ GIR_RootToRootCopy, /*OpIdx*/1, // m1 |
| 40282 | /* 112430 */ GIR_RootToRootCopy, /*OpIdx*/2, // m2 |
| 40283 | /* 112432 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 40284 | /* 112435 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40285 | /* 112441 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40286 | /* 112447 */ GIR_RootConstrainSelectedInstOperands, |
| 40287 | /* 112448 */ // GIR_Coverage, 4006, |
| 40288 | /* 112448 */ GIR_EraseRootFromParent_Done, |
| 40289 | /* 112449 */ // Label 2131: @112449 |
| 40290 | /* 112449 */ GIM_Reject, |
| 40291 | /* 112450 */ // Label 2125: @112450 |
| 40292 | /* 112450 */ GIM_Reject, |
| 40293 | /* 112451 */ // Label 2097: @112451 |
| 40294 | /* 112451 */ GIM_Try, /*On fail goto*//*Label 2132*/ GIMT_Encode4(112702), |
| 40295 | /* 112456 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 40296 | /* 112459 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 40297 | /* 112462 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 40298 | /* 112465 */ GIM_Try, /*On fail goto*//*Label 2133*/ GIMT_Encode4(112534), // Rule ID 4012 // |
| 40299 | /* 112470 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 40300 | /* 112473 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 40301 | /* 112477 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 40302 | /* 112481 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 40303 | /* 112485 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 40304 | /* 112489 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 40305 | /* 112494 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 40306 | /* 112498 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 40307 | /* 112502 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 40308 | /* 112504 */ // (fma:{ *:[v8f16] } (fneg:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$m1), MQPR:{ *:[v8f16] }:$m2, MQPR:{ *:[v8f16] }:$add) => (MVE_VFMSf16:{ *:[v8f16] } ?:{ *:[v8f16] }:$add, ?:{ *:[v8f16] }:$m1, ?:{ *:[v8f16] }:$m2) |
| 40309 | /* 112504 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VFMSf16), |
| 40310 | /* 112507 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 40311 | /* 112509 */ GIR_RootToRootCopy, /*OpIdx*/3, // add |
| 40312 | /* 112511 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // m1 |
| 40313 | /* 112515 */ GIR_RootToRootCopy, /*OpIdx*/2, // m2 |
| 40314 | /* 112517 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 40315 | /* 112520 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40316 | /* 112526 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40317 | /* 112532 */ GIR_RootConstrainSelectedInstOperands, |
| 40318 | /* 112533 */ // GIR_Coverage, 4012, |
| 40319 | /* 112533 */ GIR_EraseRootFromParent_Done, |
| 40320 | /* 112534 */ // Label 2133: @112534 |
| 40321 | /* 112534 */ GIM_Try, /*On fail goto*//*Label 2134*/ GIMT_Encode4(112603), // Rule ID 6040 // |
| 40322 | /* 112539 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 40323 | /* 112542 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 40324 | /* 112546 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 40325 | /* 112550 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 40326 | /* 112554 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 40327 | /* 112558 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 40328 | /* 112562 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 40329 | /* 112567 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 40330 | /* 112571 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 40331 | /* 112573 */ // (fma:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$m2, (fneg:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$m1), MQPR:{ *:[v8f16] }:$add) => (MVE_VFMSf16:{ *:[v8f16] } ?:{ *:[v8f16] }:$add, ?:{ *:[v8f16] }:$m1, ?:{ *:[v8f16] }:$m2) |
| 40332 | /* 112573 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VFMSf16), |
| 40333 | /* 112576 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 40334 | /* 112578 */ GIR_RootToRootCopy, /*OpIdx*/3, // add |
| 40335 | /* 112580 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // m1 |
| 40336 | /* 112584 */ GIR_RootToRootCopy, /*OpIdx*/1, // m2 |
| 40337 | /* 112586 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 40338 | /* 112589 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40339 | /* 112595 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40340 | /* 112601 */ GIR_RootConstrainSelectedInstOperands, |
| 40341 | /* 112602 */ // GIR_Coverage, 6040, |
| 40342 | /* 112602 */ GIR_EraseRootFromParent_Done, |
| 40343 | /* 112603 */ // Label 2134: @112603 |
| 40344 | /* 112603 */ GIM_Try, /*On fail goto*//*Label 2135*/ GIMT_Encode4(112649), // Rule ID 2500 // |
| 40345 | /* 112608 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 40346 | /* 112611 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 40347 | /* 112615 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 40348 | /* 112619 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 40349 | /* 112623 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 40350 | /* 112627 */ // (fma:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm, QPR:{ *:[v8f16] }:$src1) => (VFMAhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) |
| 40351 | /* 112627 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAhq), |
| 40352 | /* 112630 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 40353 | /* 112632 */ GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 40354 | /* 112634 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 40355 | /* 112636 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 40356 | /* 112638 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40357 | /* 112641 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40358 | /* 112647 */ GIR_RootConstrainSelectedInstOperands, |
| 40359 | /* 112648 */ // GIR_Coverage, 2500, |
| 40360 | /* 112648 */ GIR_EraseRootFromParent_Done, |
| 40361 | /* 112649 */ // Label 2135: @112649 |
| 40362 | /* 112649 */ GIM_Try, /*On fail goto*//*Label 2136*/ GIMT_Encode4(112701), // Rule ID 4009 // |
| 40363 | /* 112654 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 40364 | /* 112657 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 40365 | /* 112661 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 40366 | /* 112665 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 40367 | /* 112669 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 40368 | /* 112673 */ // (fma:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$m1, MQPR:{ *:[v8f16] }:$m2, MQPR:{ *:[v8f16] }:$add) => (MVE_VFMAf16:{ *:[v8f16] } ?:{ *:[v8f16] }:$add, ?:{ *:[v8f16] }:$m1, ?:{ *:[v8f16] }:$m2) |
| 40369 | /* 112673 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VFMAf16), |
| 40370 | /* 112676 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 40371 | /* 112678 */ GIR_RootToRootCopy, /*OpIdx*/3, // add |
| 40372 | /* 112680 */ GIR_RootToRootCopy, /*OpIdx*/1, // m1 |
| 40373 | /* 112682 */ GIR_RootToRootCopy, /*OpIdx*/2, // m2 |
| 40374 | /* 112684 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 40375 | /* 112687 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40376 | /* 112693 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40377 | /* 112699 */ GIR_RootConstrainSelectedInstOperands, |
| 40378 | /* 112700 */ // GIR_Coverage, 4009, |
| 40379 | /* 112700 */ GIR_EraseRootFromParent_Done, |
| 40380 | /* 112701 */ // Label 2136: @112701 |
| 40381 | /* 112701 */ GIM_Reject, |
| 40382 | /* 112702 */ // Label 2132: @112702 |
| 40383 | /* 112702 */ GIM_Reject, |
| 40384 | /* 112703 */ // Label 2098: @112703 |
| 40385 | /* 112703 */ GIM_Reject, |
| 40386 | /* 112704 */ // Label 38: @112704 |
| 40387 | /* 112704 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(3), /*)*//*default:*//*Label 2140*/ GIMT_Encode4(112868), |
| 40388 | /* 112715 */ /*GILLT_s16*//*Label 2137*/ GIMT_Encode4(112727), |
| 40389 | /* 112719 */ /*GILLT_s32*//*Label 2138*/ GIMT_Encode4(112774), |
| 40390 | /* 112723 */ /*GILLT_s64*//*Label 2139*/ GIMT_Encode4(112821), |
| 40391 | /* 112727 */ // Label 2137: @112727 |
| 40392 | /* 112727 */ GIM_Try, /*On fail goto*//*Label 2141*/ GIMT_Encode4(112773), // Rule ID 620 // |
| 40393 | /* 112732 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 40394 | /* 112735 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 40395 | /* 112738 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 40396 | /* 112741 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 40397 | /* 112745 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 40398 | /* 112749 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 40399 | /* 112753 */ // (fdiv:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) => (VDIVH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 40400 | /* 112753 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VDIVH), |
| 40401 | /* 112756 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 40402 | /* 112758 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn |
| 40403 | /* 112760 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 40404 | /* 112762 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40405 | /* 112765 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40406 | /* 112771 */ GIR_RootConstrainSelectedInstOperands, |
| 40407 | /* 112772 */ // GIR_Coverage, 620, |
| 40408 | /* 112772 */ GIR_EraseRootFromParent_Done, |
| 40409 | /* 112773 */ // Label 2141: @112773 |
| 40410 | /* 112773 */ GIM_Reject, |
| 40411 | /* 112774 */ // Label 2138: @112774 |
| 40412 | /* 112774 */ GIM_Try, /*On fail goto*//*Label 2142*/ GIMT_Encode4(112820), // Rule ID 619 // |
| 40413 | /* 112779 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP2), |
| 40414 | /* 112782 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 40415 | /* 112785 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 40416 | /* 112788 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 40417 | /* 112792 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 40418 | /* 112796 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 40419 | /* 112800 */ // (fdiv:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) => (VDIVS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 40420 | /* 112800 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VDIVS), |
| 40421 | /* 112803 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 40422 | /* 112805 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn |
| 40423 | /* 112807 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 40424 | /* 112809 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40425 | /* 112812 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40426 | /* 112818 */ GIR_RootConstrainSelectedInstOperands, |
| 40427 | /* 112819 */ // GIR_Coverage, 619, |
| 40428 | /* 112819 */ GIR_EraseRootFromParent_Done, |
| 40429 | /* 112820 */ // Label 2142: @112820 |
| 40430 | /* 112820 */ GIM_Reject, |
| 40431 | /* 112821 */ // Label 2139: @112821 |
| 40432 | /* 112821 */ GIM_Try, /*On fail goto*//*Label 2143*/ GIMT_Encode4(112867), // Rule ID 618 // |
| 40433 | /* 112826 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), |
| 40434 | /* 112829 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 40435 | /* 112832 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 40436 | /* 112835 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40437 | /* 112839 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40438 | /* 112843 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40439 | /* 112847 */ // (fdiv:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) => (VDIVD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 40440 | /* 112847 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VDIVD), |
| 40441 | /* 112850 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 40442 | /* 112852 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dn |
| 40443 | /* 112854 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm |
| 40444 | /* 112856 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40445 | /* 112859 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40446 | /* 112865 */ GIR_RootConstrainSelectedInstOperands, |
| 40447 | /* 112866 */ // GIR_Coverage, 618, |
| 40448 | /* 112866 */ GIR_EraseRootFromParent_Done, |
| 40449 | /* 112867 */ // Label 2143: @112867 |
| 40450 | /* 112867 */ GIM_Reject, |
| 40451 | /* 112868 */ // Label 2140: @112868 |
| 40452 | /* 112868 */ GIM_Reject, |
| 40453 | /* 112869 */ // Label 39: @112869 |
| 40454 | /* 112869 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 2151*/ GIMT_Encode4(114399), |
| 40455 | /* 112880 */ /*GILLT_s16*//*Label 2144*/ GIMT_Encode4(112932), |
| 40456 | /* 112884 */ /*GILLT_s32*//*Label 2145*/ GIMT_Encode4(113279), |
| 40457 | /* 112888 */ /*GILLT_s64*//*Label 2146*/ GIMT_Encode4(113778), GIMT_Encode4(0), |
| 40458 | /* 112896 */ /*GILLT_v2s32*//*Label 2147*/ GIMT_Encode4(114125), GIMT_Encode4(0), GIMT_Encode4(0), |
| 40459 | /* 112908 */ /*GILLT_v4s16*//*Label 2148*/ GIMT_Encode4(114163), |
| 40460 | /* 112912 */ /*GILLT_v4s32*//*Label 2149*/ GIMT_Encode4(114201), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 40461 | /* 112928 */ /*GILLT_v8s16*//*Label 2150*/ GIMT_Encode4(114300), |
| 40462 | /* 112932 */ // Label 2144: @112932 |
| 40463 | /* 112932 */ GIM_Try, /*On fail goto*//*Label 2152*/ GIMT_Encode4(113278), |
| 40464 | /* 112937 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 40465 | /* 112940 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 40466 | /* 112944 */ GIM_Try, /*On fail goto*//*Label 2153*/ GIMT_Encode4(113029), // Rule ID 2414 // |
| 40467 | /* 112949 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 40468 | /* 112952 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 40469 | /* 112956 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA), |
| 40470 | /* 112960 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 40471 | /* 112964 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 40472 | /* 112968 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s16, |
| 40473 | /* 112972 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 40474 | /* 112976 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 40475 | /* 112980 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 40476 | /* 112984 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 40477 | /* 112989 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 40478 | /* 112994 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 40479 | /* 112999 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 40480 | /* 113001 */ // (fneg:{ *:[f16] } (fma:{ *:[f16] } (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), HPR:{ *:[f16] }:$Sm, HPR:{ *:[f16] }:$Sdin)) => (VFNMSH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 40481 | /* 113001 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSH), |
| 40482 | /* 113004 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 40483 | /* 113006 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin |
| 40484 | /* 113010 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sn |
| 40485 | /* 113014 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm |
| 40486 | /* 113018 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40487 | /* 113021 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40488 | /* 113027 */ GIR_RootConstrainSelectedInstOperands, |
| 40489 | /* 113028 */ // GIR_Coverage, 2414, |
| 40490 | /* 113028 */ GIR_EraseRootFromParent_Done, |
| 40491 | /* 113029 */ // Label 2153: @113029 |
| 40492 | /* 113029 */ GIM_Try, /*On fail goto*//*Label 2154*/ GIMT_Encode4(113114), // Rule ID 5722 // |
| 40493 | /* 113034 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 40494 | /* 113037 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 40495 | /* 113041 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA), |
| 40496 | /* 113045 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 40497 | /* 113049 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 40498 | /* 113053 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s16, |
| 40499 | /* 113057 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 40500 | /* 113062 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 40501 | /* 113066 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 40502 | /* 113070 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 40503 | /* 113074 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 40504 | /* 113079 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 40505 | /* 113084 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 40506 | /* 113086 */ // (fneg:{ *:[f16] } (fma:{ *:[f16] } HPR:{ *:[f16] }:$Sm, (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), HPR:{ *:[f16] }:$Sdin)) => (VFNMSH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 40507 | /* 113086 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSH), |
| 40508 | /* 113089 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 40509 | /* 113091 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin |
| 40510 | /* 113095 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sn |
| 40511 | /* 113099 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sm |
| 40512 | /* 113103 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40513 | /* 113106 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40514 | /* 113112 */ GIR_RootConstrainSelectedInstOperands, |
| 40515 | /* 113113 */ // GIR_Coverage, 5722, |
| 40516 | /* 113113 */ GIR_EraseRootFromParent_Done, |
| 40517 | /* 113114 */ // Label 2154: @113114 |
| 40518 | /* 113114 */ GIM_Try, /*On fail goto*//*Label 2155*/ GIMT_Encode4(113187), // Rule ID 2403 // |
| 40519 | /* 113119 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 40520 | /* 113122 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 40521 | /* 113126 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA), |
| 40522 | /* 113130 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 40523 | /* 113134 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 40524 | /* 113138 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s16, |
| 40525 | /* 113142 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 40526 | /* 113147 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 40527 | /* 113152 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 40528 | /* 113157 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 40529 | /* 113159 */ // (fneg:{ *:[f16] } (fma:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm, HPR:{ *:[f16] }:$Sdin)) => (VFNMAH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 40530 | /* 113159 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAH), |
| 40531 | /* 113162 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 40532 | /* 113164 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin |
| 40533 | /* 113168 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn |
| 40534 | /* 113172 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm |
| 40535 | /* 113176 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40536 | /* 113179 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40537 | /* 113185 */ GIR_RootConstrainSelectedInstOperands, |
| 40538 | /* 113186 */ // GIR_Coverage, 2403, |
| 40539 | /* 113186 */ GIR_EraseRootFromParent_Done, |
| 40540 | /* 113187 */ // Label 2155: @113187 |
| 40541 | /* 113187 */ GIM_Try, /*On fail goto*//*Label 2156*/ GIMT_Encode4(113247), // Rule ID 626 // |
| 40542 | /* 113192 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 40543 | /* 113195 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 40544 | /* 113199 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL), |
| 40545 | /* 113203 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 40546 | /* 113207 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 40547 | /* 113211 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 40548 | /* 113216 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 40549 | /* 113221 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 40550 | /* 113223 */ // (fneg:{ *:[f16] } (fmul:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)) => (VNMULH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 40551 | /* 113223 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNMULH), |
| 40552 | /* 113226 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 40553 | /* 113228 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn |
| 40554 | /* 113232 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm |
| 40555 | /* 113236 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40556 | /* 113239 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40557 | /* 113245 */ GIR_RootConstrainSelectedInstOperands, |
| 40558 | /* 113246 */ // GIR_Coverage, 626, |
| 40559 | /* 113246 */ GIR_EraseRootFromParent_Done, |
| 40560 | /* 113247 */ // Label 2156: @113247 |
| 40561 | /* 113247 */ GIM_Try, /*On fail goto*//*Label 2157*/ GIMT_Encode4(113277), // Rule ID 664 // |
| 40562 | /* 113252 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 40563 | /* 113255 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 40564 | /* 113259 */ // (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VNEGH:{ *:[f16] } HPR:{ *:[f16] }:$Sm) |
| 40565 | /* 113259 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNEGH), |
| 40566 | /* 113262 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 40567 | /* 113264 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm |
| 40568 | /* 113266 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40569 | /* 113269 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40570 | /* 113275 */ GIR_RootConstrainSelectedInstOperands, |
| 40571 | /* 113276 */ // GIR_Coverage, 664, |
| 40572 | /* 113276 */ GIR_EraseRootFromParent_Done, |
| 40573 | /* 113277 */ // Label 2157: @113277 |
| 40574 | /* 113277 */ GIM_Reject, |
| 40575 | /* 113278 */ // Label 2152: @113278 |
| 40576 | /* 113278 */ GIM_Reject, |
| 40577 | /* 113279 */ // Label 2145: @113279 |
| 40578 | /* 113279 */ GIM_Try, /*On fail goto*//*Label 2158*/ GIMT_Encode4(113777), |
| 40579 | /* 113284 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 40580 | /* 113287 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 40581 | /* 113291 */ GIM_Try, /*On fail goto*//*Label 2159*/ GIMT_Encode4(113376), // Rule ID 2413 // |
| 40582 | /* 113296 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP4), |
| 40583 | /* 113299 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 40584 | /* 113303 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA), |
| 40585 | /* 113307 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 40586 | /* 113311 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 40587 | /* 113315 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 40588 | /* 113319 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 40589 | /* 113323 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 40590 | /* 113327 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 40591 | /* 113331 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 40592 | /* 113336 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 40593 | /* 113341 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 40594 | /* 113346 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 40595 | /* 113348 */ // (fneg:{ *:[f32] } (fma:{ *:[f32] } (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), SPR:{ *:[f32] }:$Sm, SPR:{ *:[f32] }:$Sdin)) => (VFNMSS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 40596 | /* 113348 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSS), |
| 40597 | /* 113351 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 40598 | /* 113353 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin |
| 40599 | /* 113357 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sn |
| 40600 | /* 113361 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm |
| 40601 | /* 113365 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40602 | /* 113368 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40603 | /* 113374 */ GIR_RootConstrainSelectedInstOperands, |
| 40604 | /* 113375 */ // GIR_Coverage, 2413, |
| 40605 | /* 113375 */ GIR_EraseRootFromParent_Done, |
| 40606 | /* 113376 */ // Label 2159: @113376 |
| 40607 | /* 113376 */ GIM_Try, /*On fail goto*//*Label 2160*/ GIMT_Encode4(113461), // Rule ID 5721 // |
| 40608 | /* 113381 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP4), |
| 40609 | /* 113384 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 40610 | /* 113388 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA), |
| 40611 | /* 113392 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 40612 | /* 113396 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 40613 | /* 113400 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 40614 | /* 113404 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 40615 | /* 113409 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 40616 | /* 113413 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 40617 | /* 113417 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 40618 | /* 113421 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 40619 | /* 113426 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 40620 | /* 113431 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 40621 | /* 113433 */ // (fneg:{ *:[f32] } (fma:{ *:[f32] } SPR:{ *:[f32] }:$Sm, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), SPR:{ *:[f32] }:$Sdin)) => (VFNMSS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 40622 | /* 113433 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSS), |
| 40623 | /* 113436 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 40624 | /* 113438 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin |
| 40625 | /* 113442 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sn |
| 40626 | /* 113446 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sm |
| 40627 | /* 113450 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40628 | /* 113453 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40629 | /* 113459 */ GIR_RootConstrainSelectedInstOperands, |
| 40630 | /* 113460 */ // GIR_Coverage, 5721, |
| 40631 | /* 113460 */ GIR_EraseRootFromParent_Done, |
| 40632 | /* 113461 */ // Label 2160: @113461 |
| 40633 | /* 113461 */ GIM_Try, /*On fail goto*//*Label 2161*/ GIMT_Encode4(113534), // Rule ID 2402 // |
| 40634 | /* 113466 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP4), |
| 40635 | /* 113469 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 40636 | /* 113473 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA), |
| 40637 | /* 113477 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 40638 | /* 113481 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 40639 | /* 113485 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 40640 | /* 113489 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 40641 | /* 113494 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 40642 | /* 113499 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 40643 | /* 113504 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 40644 | /* 113506 */ // (fneg:{ *:[f32] } (fma:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm, SPR:{ *:[f32] }:$Sdin)) => (VFNMAS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 40645 | /* 113506 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAS), |
| 40646 | /* 113509 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 40647 | /* 113511 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin |
| 40648 | /* 113515 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn |
| 40649 | /* 113519 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm |
| 40650 | /* 113523 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40651 | /* 113526 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40652 | /* 113532 */ GIR_RootConstrainSelectedInstOperands, |
| 40653 | /* 113533 */ // GIR_Coverage, 2402, |
| 40654 | /* 113533 */ GIR_EraseRootFromParent_Done, |
| 40655 | /* 113534 */ // Label 2161: @113534 |
| 40656 | /* 113534 */ GIM_Try, /*On fail goto*//*Label 2162*/ GIMT_Encode4(113594), // Rule ID 625 // |
| 40657 | /* 113539 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP2), |
| 40658 | /* 113542 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 40659 | /* 113546 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL), |
| 40660 | /* 113550 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 40661 | /* 113554 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 40662 | /* 113558 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 40663 | /* 113563 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 40664 | /* 113568 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 40665 | /* 113570 */ // (fneg:{ *:[f32] } (fmul:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)) => (VNMULS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 40666 | /* 113570 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNMULS), |
| 40667 | /* 113573 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 40668 | /* 113575 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn |
| 40669 | /* 113579 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm |
| 40670 | /* 113583 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40671 | /* 113586 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40672 | /* 113592 */ GIR_RootConstrainSelectedInstOperands, |
| 40673 | /* 113593 */ // GIR_Coverage, 625, |
| 40674 | /* 113593 */ GIR_EraseRootFromParent_Done, |
| 40675 | /* 113594 */ // Label 2162: @113594 |
| 40676 | /* 113594 */ GIM_Try, /*On fail goto*//*Label 2163*/ GIMT_Encode4(113624), // Rule ID 663 // |
| 40677 | /* 113599 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), |
| 40678 | /* 113602 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 40679 | /* 113606 */ // (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VNEGS:{ *:[f32] } SPR:{ *:[f32] }:$Sm) |
| 40680 | /* 113606 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNEGS), |
| 40681 | /* 113609 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 40682 | /* 113611 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm |
| 40683 | /* 113613 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40684 | /* 113616 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40685 | /* 113622 */ GIR_RootConstrainSelectedInstOperands, |
| 40686 | /* 113623 */ // GIR_Coverage, 663, |
| 40687 | /* 113623 */ GIR_EraseRootFromParent_Done, |
| 40688 | /* 113624 */ // Label 2163: @113624 |
| 40689 | /* 113624 */ GIM_Try, /*On fail goto*//*Label 2164*/ GIMT_Encode4(113776), // Rule ID 2705 // |
| 40690 | /* 113629 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_UseNEONForFP), |
| 40691 | /* 113632 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 40692 | /* 113636 */ // (fneg:{ *:[f32] } SPR:{ *:[f32] }:$a) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VNEGfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] }) |
| 40693 | /* 113636 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32, |
| 40694 | /* 113639 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 40695 | /* 113643 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 40696 | /* 113648 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 40697 | /* 113650 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32, |
| 40698 | /* 113653 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 40699 | /* 113657 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 40700 | /* 113662 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4, |
| 40701 | /* 113665 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 40702 | /* 113670 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32, |
| 40703 | /* 113673 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 40704 | /* 113677 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 40705 | /* 113682 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3, |
| 40706 | /* 113685 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 40707 | /* 113689 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17, |
| 40708 | /* 113692 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 40709 | /* 113697 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 40710 | /* 113702 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 40711 | /* 113707 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 40712 | /* 113710 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VNEGfd), |
| 40713 | /* 113714 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 40714 | /* 113719 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 40715 | /* 113722 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14, |
| 40716 | /* 113725 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40717 | /* 113731 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 40718 | /* 113733 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32, |
| 40719 | /* 113736 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 40720 | /* 113740 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 40721 | /* 113745 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 40722 | /* 113748 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 40723 | /* 113753 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 40724 | /* 113756 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 40725 | /* 113758 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0), |
| 40726 | /* 113765 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 40727 | /* 113770 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 40728 | /* 113775 */ // GIR_Coverage, 2705, |
| 40729 | /* 113775 */ GIR_EraseRootFromParent_Done, |
| 40730 | /* 113776 */ // Label 2164: @113776 |
| 40731 | /* 113776 */ GIM_Reject, |
| 40732 | /* 113777 */ // Label 2158: @113777 |
| 40733 | /* 113777 */ GIM_Reject, |
| 40734 | /* 113778 */ // Label 2146: @113778 |
| 40735 | /* 113778 */ GIM_Try, /*On fail goto*//*Label 2165*/ GIMT_Encode4(114124), |
| 40736 | /* 113783 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 40737 | /* 113786 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40738 | /* 113790 */ GIM_Try, /*On fail goto*//*Label 2166*/ GIMT_Encode4(113875), // Rule ID 2412 // |
| 40739 | /* 113795 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4), |
| 40740 | /* 113798 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 40741 | /* 113802 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA), |
| 40742 | /* 113806 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 40743 | /* 113810 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 40744 | /* 113814 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, |
| 40745 | /* 113818 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 40746 | /* 113822 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 40747 | /* 113826 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 40748 | /* 113830 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40749 | /* 113835 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40750 | /* 113840 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40751 | /* 113845 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 40752 | /* 113847 */ // (fneg:{ *:[f64] } (fma:{ *:[f64] } (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), DPR:{ *:[f64] }:$Dm, DPR:{ *:[f64] }:$Ddin)) => (VFNMSD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 40753 | /* 113847 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSD), |
| 40754 | /* 113850 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 40755 | /* 113852 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ddin |
| 40756 | /* 113856 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Dn |
| 40757 | /* 113860 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Dm |
| 40758 | /* 113864 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40759 | /* 113867 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40760 | /* 113873 */ GIR_RootConstrainSelectedInstOperands, |
| 40761 | /* 113874 */ // GIR_Coverage, 2412, |
| 40762 | /* 113874 */ GIR_EraseRootFromParent_Done, |
| 40763 | /* 113875 */ // Label 2166: @113875 |
| 40764 | /* 113875 */ GIM_Try, /*On fail goto*//*Label 2167*/ GIMT_Encode4(113960), // Rule ID 5720 // |
| 40765 | /* 113880 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4), |
| 40766 | /* 113883 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 40767 | /* 113887 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA), |
| 40768 | /* 113891 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 40769 | /* 113895 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 40770 | /* 113899 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, |
| 40771 | /* 113903 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40772 | /* 113908 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 40773 | /* 113912 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 40774 | /* 113916 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 40775 | /* 113920 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40776 | /* 113925 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40777 | /* 113930 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 40778 | /* 113932 */ // (fneg:{ *:[f64] } (fma:{ *:[f64] } DPR:{ *:[f64] }:$Dm, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), DPR:{ *:[f64] }:$Ddin)) => (VFNMSD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 40779 | /* 113932 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSD), |
| 40780 | /* 113935 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 40781 | /* 113937 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ddin |
| 40782 | /* 113941 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Dn |
| 40783 | /* 113945 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dm |
| 40784 | /* 113949 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40785 | /* 113952 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40786 | /* 113958 */ GIR_RootConstrainSelectedInstOperands, |
| 40787 | /* 113959 */ // GIR_Coverage, 5720, |
| 40788 | /* 113959 */ GIR_EraseRootFromParent_Done, |
| 40789 | /* 113960 */ // Label 2167: @113960 |
| 40790 | /* 113960 */ GIM_Try, /*On fail goto*//*Label 2168*/ GIMT_Encode4(114033), // Rule ID 2401 // |
| 40791 | /* 113965 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4), |
| 40792 | /* 113968 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 40793 | /* 113972 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA), |
| 40794 | /* 113976 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 40795 | /* 113980 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 40796 | /* 113984 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, |
| 40797 | /* 113988 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40798 | /* 113993 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40799 | /* 113998 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40800 | /* 114003 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 40801 | /* 114005 */ // (fneg:{ *:[f64] } (fma:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm, DPR:{ *:[f64] }:$Ddin)) => (VFNMAD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 40802 | /* 114005 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAD), |
| 40803 | /* 114008 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 40804 | /* 114010 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ddin |
| 40805 | /* 114014 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn |
| 40806 | /* 114018 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Dm |
| 40807 | /* 114022 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40808 | /* 114025 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40809 | /* 114031 */ GIR_RootConstrainSelectedInstOperands, |
| 40810 | /* 114032 */ // GIR_Coverage, 2401, |
| 40811 | /* 114032 */ GIR_EraseRootFromParent_Done, |
| 40812 | /* 114033 */ // Label 2168: @114033 |
| 40813 | /* 114033 */ GIM_Try, /*On fail goto*//*Label 2169*/ GIMT_Encode4(114093), // Rule ID 624 // |
| 40814 | /* 114038 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), |
| 40815 | /* 114041 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 40816 | /* 114045 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL), |
| 40817 | /* 114049 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 40818 | /* 114053 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 40819 | /* 114057 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40820 | /* 114062 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40821 | /* 114067 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 40822 | /* 114069 */ // (fneg:{ *:[f64] } (fmul:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)) => (VNMULD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 40823 | /* 114069 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNMULD), |
| 40824 | /* 114072 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 40825 | /* 114074 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn |
| 40826 | /* 114078 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Dm |
| 40827 | /* 114082 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40828 | /* 114085 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40829 | /* 114091 */ GIR_RootConstrainSelectedInstOperands, |
| 40830 | /* 114092 */ // GIR_Coverage, 624, |
| 40831 | /* 114092 */ GIR_EraseRootFromParent_Done, |
| 40832 | /* 114093 */ // Label 2169: @114093 |
| 40833 | /* 114093 */ GIM_Try, /*On fail goto*//*Label 2170*/ GIMT_Encode4(114123), // Rule ID 662 // |
| 40834 | /* 114098 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), |
| 40835 | /* 114101 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40836 | /* 114105 */ // (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VNEGD:{ *:[f64] } DPR:{ *:[f64] }:$Dm) |
| 40837 | /* 114105 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNEGD), |
| 40838 | /* 114108 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 40839 | /* 114110 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dm |
| 40840 | /* 114112 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40841 | /* 114115 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40842 | /* 114121 */ GIR_RootConstrainSelectedInstOperands, |
| 40843 | /* 114122 */ // GIR_Coverage, 662, |
| 40844 | /* 114122 */ GIR_EraseRootFromParent_Done, |
| 40845 | /* 114123 */ // Label 2170: @114123 |
| 40846 | /* 114123 */ GIM_Reject, |
| 40847 | /* 114124 */ // Label 2165: @114124 |
| 40848 | /* 114124 */ GIM_Reject, |
| 40849 | /* 114125 */ // Label 2147: @114125 |
| 40850 | /* 114125 */ GIM_Try, /*On fail goto*//*Label 2171*/ GIMT_Encode4(114162), // Rule ID 1530 // |
| 40851 | /* 114130 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 40852 | /* 114133 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 40853 | /* 114136 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40854 | /* 114140 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40855 | /* 114144 */ // (fneg:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) => (VNEGfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) |
| 40856 | /* 114144 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNEGfd), |
| 40857 | /* 114147 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 40858 | /* 114149 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 40859 | /* 114151 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40860 | /* 114154 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40861 | /* 114160 */ GIR_RootConstrainSelectedInstOperands, |
| 40862 | /* 114161 */ // GIR_Coverage, 1530, |
| 40863 | /* 114161 */ GIR_EraseRootFromParent_Done, |
| 40864 | /* 114162 */ // Label 2171: @114162 |
| 40865 | /* 114162 */ GIM_Reject, |
| 40866 | /* 114163 */ // Label 2148: @114163 |
| 40867 | /* 114163 */ GIM_Try, /*On fail goto*//*Label 2172*/ GIMT_Encode4(114200), // Rule ID 1532 // |
| 40868 | /* 114168 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 40869 | /* 114171 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 40870 | /* 114174 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40871 | /* 114178 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40872 | /* 114182 */ // (fneg:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) => (VNEGhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) |
| 40873 | /* 114182 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNEGhd), |
| 40874 | /* 114185 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 40875 | /* 114187 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 40876 | /* 114189 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40877 | /* 114192 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40878 | /* 114198 */ GIR_RootConstrainSelectedInstOperands, |
| 40879 | /* 114199 */ // GIR_Coverage, 1532, |
| 40880 | /* 114199 */ GIR_EraseRootFromParent_Done, |
| 40881 | /* 114200 */ // Label 2172: @114200 |
| 40882 | /* 114200 */ GIM_Reject, |
| 40883 | /* 114201 */ // Label 2149: @114201 |
| 40884 | /* 114201 */ GIM_Try, /*On fail goto*//*Label 2173*/ GIMT_Encode4(114299), |
| 40885 | /* 114206 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 40886 | /* 114209 */ GIM_Try, /*On fail goto*//*Label 2174*/ GIMT_Encode4(114243), // Rule ID 1531 // |
| 40887 | /* 114214 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 40888 | /* 114217 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 40889 | /* 114221 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 40890 | /* 114225 */ // (fneg:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) => (VNEGf32q:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) |
| 40891 | /* 114225 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNEGf32q), |
| 40892 | /* 114228 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 40893 | /* 114230 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 40894 | /* 114232 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40895 | /* 114235 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40896 | /* 114241 */ GIR_RootConstrainSelectedInstOperands, |
| 40897 | /* 114242 */ // GIR_Coverage, 1531, |
| 40898 | /* 114242 */ GIR_EraseRootFromParent_Done, |
| 40899 | /* 114243 */ // Label 2174: @114243 |
| 40900 | /* 114243 */ GIM_Try, /*On fail goto*//*Label 2175*/ GIMT_Encode4(114298), // Rule ID 4116 // |
| 40901 | /* 114248 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 40902 | /* 114251 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 40903 | /* 114255 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 40904 | /* 114259 */ // (fneg:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$v) => (MVE_VNEGf32:{ *:[v4f32] } ?:{ *:[v4f32] }:$v) |
| 40905 | /* 114259 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 40906 | /* 114262 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 40907 | /* 114266 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 40908 | /* 114271 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VNEGf32), |
| 40909 | /* 114274 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 40910 | /* 114276 */ GIR_RootToRootCopy, /*OpIdx*/1, // v |
| 40911 | /* 114278 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 40912 | /* 114281 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40913 | /* 114287 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40914 | /* 114293 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 40915 | /* 114296 */ GIR_RootConstrainSelectedInstOperands, |
| 40916 | /* 114297 */ // GIR_Coverage, 4116, |
| 40917 | /* 114297 */ GIR_EraseRootFromParent_Done, |
| 40918 | /* 114298 */ // Label 2175: @114298 |
| 40919 | /* 114298 */ GIM_Reject, |
| 40920 | /* 114299 */ // Label 2173: @114299 |
| 40921 | /* 114299 */ GIM_Reject, |
| 40922 | /* 114300 */ // Label 2150: @114300 |
| 40923 | /* 114300 */ GIM_Try, /*On fail goto*//*Label 2176*/ GIMT_Encode4(114398), |
| 40924 | /* 114305 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 40925 | /* 114308 */ GIM_Try, /*On fail goto*//*Label 2177*/ GIMT_Encode4(114342), // Rule ID 1533 // |
| 40926 | /* 114313 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 40927 | /* 114316 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 40928 | /* 114320 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 40929 | /* 114324 */ // (fneg:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) => (VNEGhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) |
| 40930 | /* 114324 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNEGhq), |
| 40931 | /* 114327 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 40932 | /* 114329 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 40933 | /* 114331 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40934 | /* 114334 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40935 | /* 114340 */ GIR_RootConstrainSelectedInstOperands, |
| 40936 | /* 114341 */ // GIR_Coverage, 1533, |
| 40937 | /* 114341 */ GIR_EraseRootFromParent_Done, |
| 40938 | /* 114342 */ // Label 2177: @114342 |
| 40939 | /* 114342 */ GIM_Try, /*On fail goto*//*Label 2178*/ GIMT_Encode4(114397), // Rule ID 4114 // |
| 40940 | /* 114347 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 40941 | /* 114350 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 40942 | /* 114354 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 40943 | /* 114358 */ // (fneg:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$v) => (MVE_VNEGf16:{ *:[v8f16] } ?:{ *:[v8f16] }:$v) |
| 40944 | /* 114358 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 40945 | /* 114361 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 40946 | /* 114365 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 40947 | /* 114370 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VNEGf16), |
| 40948 | /* 114373 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 40949 | /* 114375 */ GIR_RootToRootCopy, /*OpIdx*/1, // v |
| 40950 | /* 114377 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 40951 | /* 114380 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40952 | /* 114386 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40953 | /* 114392 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 40954 | /* 114395 */ GIR_RootConstrainSelectedInstOperands, |
| 40955 | /* 114396 */ // GIR_Coverage, 4114, |
| 40956 | /* 114396 */ GIR_EraseRootFromParent_Done, |
| 40957 | /* 114397 */ // Label 2178: @114397 |
| 40958 | /* 114397 */ GIM_Reject, |
| 40959 | /* 114398 */ // Label 2176: @114398 |
| 40960 | /* 114398 */ GIM_Reject, |
| 40961 | /* 114399 */ // Label 2151: @114399 |
| 40962 | /* 114399 */ GIM_Reject, |
| 40963 | /* 114400 */ // Label 40: @114400 |
| 40964 | /* 114400 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(9), /*)*//*default:*//*Label 2182*/ GIMT_Encode4(114635), |
| 40965 | /* 114411 */ /*GILLT_s32*//*Label 2179*/ GIMT_Encode4(114443), |
| 40966 | /* 114415 */ /*GILLT_s64*//*Label 2180*/ GIMT_Encode4(114503), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 40967 | /* 114439 */ /*GILLT_v4s32*//*Label 2181*/ GIMT_Encode4(114600), |
| 40968 | /* 114443 */ // Label 2179: @114443 |
| 40969 | /* 114443 */ GIM_Try, /*On fail goto*//*Label 2183*/ GIMT_Encode4(114502), // Rule ID 2303 // |
| 40970 | /* 114448 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP16), |
| 40971 | /* 114451 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 40972 | /* 114454 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 40973 | /* 114458 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 40974 | /* 114462 */ // (fpextend:{ *:[f32] } HPR:{ *:[f16] }:$Sm) => (VCVTBHS:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[f32] } HPR:{ *:[f16] }:$Sm, SPR:{ *:[i32] })) |
| 40975 | /* 114462 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 40976 | /* 114465 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 40977 | /* 114469 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 40978 | /* 114474 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Sm |
| 40979 | /* 114478 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 40980 | /* 114483 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTBHS), |
| 40981 | /* 114486 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 40982 | /* 114488 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 40983 | /* 114491 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40984 | /* 114494 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40985 | /* 114500 */ GIR_RootConstrainSelectedInstOperands, |
| 40986 | /* 114501 */ // GIR_Coverage, 2303, |
| 40987 | /* 114501 */ GIR_EraseRootFromParent_Done, |
| 40988 | /* 114502 */ // Label 2183: @114502 |
| 40989 | /* 114502 */ GIM_Reject, |
| 40990 | /* 114503 */ // Label 2180: @114503 |
| 40991 | /* 114503 */ GIM_Try, /*On fail goto*//*Label 2184*/ GIMT_Encode4(114540), // Rule ID 660 // |
| 40992 | /* 114508 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), |
| 40993 | /* 114511 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 40994 | /* 114514 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40995 | /* 114518 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 40996 | /* 114522 */ // (fpextend:{ *:[f64] } SPR:{ *:[f32] }:$Sm) => (VCVTDS:{ *:[f64] } SPR:{ *:[f32] }:$Sm) |
| 40997 | /* 114522 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTDS), |
| 40998 | /* 114525 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 40999 | /* 114527 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm |
| 41000 | /* 114529 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 41001 | /* 114532 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41002 | /* 114538 */ GIR_RootConstrainSelectedInstOperands, |
| 41003 | /* 114539 */ // GIR_Coverage, 660, |
| 41004 | /* 114539 */ GIR_EraseRootFromParent_Done, |
| 41005 | /* 114540 */ // Label 2184: @114540 |
| 41006 | /* 114540 */ GIM_Try, /*On fail goto*//*Label 2185*/ GIMT_Encode4(114599), // Rule ID 2313 // |
| 41007 | /* 114545 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), |
| 41008 | /* 114548 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 41009 | /* 114551 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41010 | /* 114555 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 41011 | /* 114559 */ // (fpextend:{ *:[f64] } HPR:{ *:[f16] }:$Sm) => (VCVTBHD:{ *:[f64] } (COPY_TO_REGCLASS:{ *:[f32] } HPR:{ *:[f16] }:$Sm, SPR:{ *:[i32] })) |
| 41012 | /* 114559 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 41013 | /* 114562 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41014 | /* 114566 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 41015 | /* 114571 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Sm |
| 41016 | /* 114575 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 41017 | /* 114580 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTBHD), |
| 41018 | /* 114583 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 41019 | /* 114585 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 41020 | /* 114588 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 41021 | /* 114591 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41022 | /* 114597 */ GIR_RootConstrainSelectedInstOperands, |
| 41023 | /* 114598 */ // GIR_Coverage, 2313, |
| 41024 | /* 114598 */ GIR_EraseRootFromParent_Done, |
| 41025 | /* 114599 */ // Label 2185: @114599 |
| 41026 | /* 114599 */ GIM_Reject, |
| 41027 | /* 114600 */ // Label 2181: @114600 |
| 41028 | /* 114600 */ GIM_Try, /*On fail goto*//*Label 2186*/ GIMT_Encode4(114634), // Rule ID 2670 // |
| 41029 | /* 114605 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 41030 | /* 114608 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 41031 | /* 114612 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41032 | /* 114616 */ // (fpextend:{ *:[v4f32] } DPR:{ *:[v4f16] }:$src) => (VCVTh2f:{ *:[v4f32] } DPR:{ *:[v4f16] }:$src) |
| 41033 | /* 114616 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTh2f), |
| 41034 | /* 114619 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 41035 | /* 114621 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 41036 | /* 114623 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 41037 | /* 114626 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41038 | /* 114632 */ GIR_RootConstrainSelectedInstOperands, |
| 41039 | /* 114633 */ // GIR_Coverage, 2670, |
| 41040 | /* 114633 */ GIR_EraseRootFromParent_Done, |
| 41041 | /* 114634 */ // Label 2186: @114634 |
| 41042 | /* 114634 */ GIM_Reject, |
| 41043 | /* 114635 */ // Label 2182: @114635 |
| 41044 | /* 114635 */ GIM_Reject, |
| 41045 | /* 114636 */ // Label 41: @114636 |
| 41046 | /* 114636 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(8), /*)*//*default:*//*Label 2190*/ GIMT_Encode4(114907), |
| 41047 | /* 114647 */ /*GILLT_s16*//*Label 2187*/ GIMT_Encode4(114679), |
| 41048 | /* 114651 */ /*GILLT_s32*//*Label 2188*/ GIMT_Encode4(114834), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 41049 | /* 114675 */ /*GILLT_v4s16*//*Label 2189*/ GIMT_Encode4(114872), |
| 41050 | /* 114679 */ // Label 2187: @114679 |
| 41051 | /* 114679 */ GIM_Try, /*On fail goto*//*Label 2191*/ GIMT_Encode4(114756), // Rule ID 2305 // |
| 41052 | /* 114684 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP16), |
| 41053 | /* 114687 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 41054 | /* 114690 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 41055 | /* 114694 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 41056 | /* 114698 */ // (fpround:{ *:[f16] } SPR:{ *:[f32] }:$Sm) => (COPY_TO_REGCLASS:{ *:[f16] } (VCVTBSH:{ *:[f32] } (IMPLICIT_DEF:{ *:[f32] }), SPR:{ *:[f32] }:$Sm), HPR:{ *:[i32] }) |
| 41057 | /* 114698 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 41058 | /* 114701 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 41059 | /* 114705 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 41060 | /* 114710 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 41061 | /* 114712 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 41062 | /* 114715 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTBSH), |
| 41063 | /* 114719 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 41064 | /* 114724 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 41065 | /* 114727 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Sm |
| 41066 | /* 114731 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 41067 | /* 114734 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41068 | /* 114740 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 41069 | /* 114742 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41070 | /* 114745 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 41071 | /* 114747 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 41072 | /* 114750 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::HPRRegClassID), |
| 41073 | /* 114755 */ // GIR_Coverage, 2305, |
| 41074 | /* 114755 */ GIR_EraseRootFromParent_Done, |
| 41075 | /* 114756 */ // Label 2191: @114756 |
| 41076 | /* 114756 */ GIM_Try, /*On fail goto*//*Label 2192*/ GIMT_Encode4(114833), // Rule ID 2315 // |
| 41077 | /* 114761 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), |
| 41078 | /* 114764 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 41079 | /* 114767 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 41080 | /* 114771 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41081 | /* 114775 */ // (fpround:{ *:[f16] } DPR:{ *:[f64] }:$Dm) => (COPY_TO_REGCLASS:{ *:[f16] } (VCVTBDH:{ *:[f32] } (IMPLICIT_DEF:{ *:[f32] }), DPR:{ *:[f64] }:$Dm), HPR:{ *:[i32] }) |
| 41082 | /* 114775 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 41083 | /* 114778 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 41084 | /* 114782 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 41085 | /* 114787 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 41086 | /* 114789 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 41087 | /* 114792 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTBDH), |
| 41088 | /* 114796 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 41089 | /* 114801 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 41090 | /* 114804 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Dm |
| 41091 | /* 114808 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 41092 | /* 114811 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41093 | /* 114817 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 41094 | /* 114819 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41095 | /* 114822 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 41096 | /* 114824 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 41097 | /* 114827 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::HPRRegClassID), |
| 41098 | /* 114832 */ // GIR_Coverage, 2315, |
| 41099 | /* 114832 */ GIR_EraseRootFromParent_Done, |
| 41100 | /* 114833 */ // Label 2192: @114833 |
| 41101 | /* 114833 */ GIM_Reject, |
| 41102 | /* 114834 */ // Label 2188: @114834 |
| 41103 | /* 114834 */ GIM_Try, /*On fail goto*//*Label 2193*/ GIMT_Encode4(114871), // Rule ID 661 // |
| 41104 | /* 114839 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), |
| 41105 | /* 114842 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 41106 | /* 114845 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 41107 | /* 114849 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41108 | /* 114853 */ // (fpround:{ *:[f32] } DPR:{ *:[f64] }:$Dm) => (VCVTSD:{ *:[f32] } DPR:{ *:[f64] }:$Dm) |
| 41109 | /* 114853 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTSD), |
| 41110 | /* 114856 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 41111 | /* 114858 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dm |
| 41112 | /* 114860 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 41113 | /* 114863 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41114 | /* 114869 */ GIR_RootConstrainSelectedInstOperands, |
| 41115 | /* 114870 */ // GIR_Coverage, 661, |
| 41116 | /* 114870 */ GIR_EraseRootFromParent_Done, |
| 41117 | /* 114871 */ // Label 2193: @114871 |
| 41118 | /* 114871 */ GIM_Reject, |
| 41119 | /* 114872 */ // Label 2189: @114872 |
| 41120 | /* 114872 */ GIM_Try, /*On fail goto*//*Label 2194*/ GIMT_Encode4(114906), // Rule ID 2669 // |
| 41121 | /* 114877 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 41122 | /* 114880 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41123 | /* 114884 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 41124 | /* 114888 */ // (fpround:{ *:[v4f16] } QPR:{ *:[v4f32] }:$src) => (VCVTf2h:{ *:[v4f16] } QPR:{ *:[v4f32] }:$src) |
| 41125 | /* 114888 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTf2h), |
| 41126 | /* 114891 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 41127 | /* 114893 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 41128 | /* 114895 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 41129 | /* 114898 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41130 | /* 114904 */ GIR_RootConstrainSelectedInstOperands, |
| 41131 | /* 114905 */ // GIR_Coverage, 2669, |
| 41132 | /* 114905 */ GIR_EraseRootFromParent_Done, |
| 41133 | /* 114906 */ // Label 2194: @114906 |
| 41134 | /* 114906 */ GIM_Reject, |
| 41135 | /* 114907 */ // Label 2190: @114907 |
| 41136 | /* 114907 */ GIM_Reject, |
| 41137 | /* 114908 */ // Label 42: @114908 |
| 41138 | /* 114908 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(13), /*)*//*default:*//*Label 2202*/ GIMT_Encode4(116241), |
| 41139 | /* 114919 */ /*GILLT_s32*//*Label 2195*/ GIMT_Encode4(114967), GIMT_Encode4(0), GIMT_Encode4(0), |
| 41140 | /* 114931 */ /*GILLT_v2s32*//*Label 2196*/ GIMT_Encode4(115861), GIMT_Encode4(0), |
| 41141 | /* 114939 */ /*GILLT_v4s1*//*Label 2197*/ GIMT_Encode4(115899), |
| 41142 | /* 114943 */ /*GILLT_v4s16*//*Label 2198*/ GIMT_Encode4(115952), |
| 41143 | /* 114947 */ /*GILLT_v4s32*//*Label 2199*/ GIMT_Encode4(115990), GIMT_Encode4(0), |
| 41144 | /* 114955 */ /*GILLT_v8s1*//*Label 2200*/ GIMT_Encode4(116089), GIMT_Encode4(0), |
| 41145 | /* 114963 */ /*GILLT_v8s16*//*Label 2201*/ GIMT_Encode4(116142), |
| 41146 | /* 114967 */ // Label 2195: @114967 |
| 41147 | /* 114967 */ GIM_Try, /*On fail goto*//*Label 2203*/ GIMT_Encode4(115033), // Rule ID 2323 // |
| 41148 | /* 114972 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 41149 | /* 114975 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 41150 | /* 114978 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 41151 | /* 114982 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 41152 | /* 114986 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCEIL), |
| 41153 | /* 114990 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 41154 | /* 114994 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 41155 | /* 114999 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 41156 | /* 115001 */ // (fp_to_sint:{ *:[i32] } (fceil:{ *:[f16] } HPR:{ *:[f16] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTPSH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] }) |
| 41157 | /* 115001 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 41158 | /* 115004 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTPSH), |
| 41159 | /* 115008 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 41160 | /* 115013 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 41161 | /* 115017 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 41162 | /* 115019 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41163 | /* 115022 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 41164 | /* 115024 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 41165 | /* 115027 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 41166 | /* 115032 */ // GIR_Coverage, 2323, |
| 41167 | /* 115032 */ GIR_EraseRootFromParent_Done, |
| 41168 | /* 115033 */ // Label 2203: @115033 |
| 41169 | /* 115033 */ GIM_Try, /*On fail goto*//*Label 2204*/ GIMT_Encode4(115099), // Rule ID 2325 // |
| 41170 | /* 115038 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8), |
| 41171 | /* 115041 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 41172 | /* 115044 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 41173 | /* 115048 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 41174 | /* 115052 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCEIL), |
| 41175 | /* 115056 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 41176 | /* 115060 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 41177 | /* 115065 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 41178 | /* 115067 */ // (fp_to_sint:{ *:[i32] } (fceil:{ *:[f32] } SPR:{ *:[f32] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTPSS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] }) |
| 41179 | /* 115067 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 41180 | /* 115070 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTPSS), |
| 41181 | /* 115074 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 41182 | /* 115079 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 41183 | /* 115083 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 41184 | /* 115085 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41185 | /* 115088 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 41186 | /* 115090 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 41187 | /* 115093 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 41188 | /* 115098 */ // GIR_Coverage, 2325, |
| 41189 | /* 115098 */ GIR_EraseRootFromParent_Done, |
| 41190 | /* 115099 */ // Label 2204: @115099 |
| 41191 | /* 115099 */ GIM_Try, /*On fail goto*//*Label 2205*/ GIMT_Encode4(115165), // Rule ID 2327 // |
| 41192 | /* 115104 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), |
| 41193 | /* 115107 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 41194 | /* 115110 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 41195 | /* 115114 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 41196 | /* 115118 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCEIL), |
| 41197 | /* 115122 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 41198 | /* 115126 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41199 | /* 115131 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 41200 | /* 115133 */ // (fp_to_sint:{ *:[i32] } (fceil:{ *:[f64] } DPR:{ *:[f64] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTPSD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] }) |
| 41201 | /* 115133 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 41202 | /* 115136 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTPSD), |
| 41203 | /* 115140 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 41204 | /* 115145 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 41205 | /* 115149 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 41206 | /* 115151 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41207 | /* 115154 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 41208 | /* 115156 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 41209 | /* 115159 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 41210 | /* 115164 */ // GIR_Coverage, 2327, |
| 41211 | /* 115164 */ GIR_EraseRootFromParent_Done, |
| 41212 | /* 115165 */ // Label 2205: @115165 |
| 41213 | /* 115165 */ GIM_Try, /*On fail goto*//*Label 2206*/ GIMT_Encode4(115231), // Rule ID 2329 // |
| 41214 | /* 115170 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 41215 | /* 115173 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 41216 | /* 115176 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 41217 | /* 115180 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 41218 | /* 115184 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FFLOOR), |
| 41219 | /* 115188 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 41220 | /* 115192 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 41221 | /* 115197 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 41222 | /* 115199 */ // (fp_to_sint:{ *:[i32] } (ffloor:{ *:[f16] } HPR:{ *:[f16] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTMSH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] }) |
| 41223 | /* 115199 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 41224 | /* 115202 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTMSH), |
| 41225 | /* 115206 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 41226 | /* 115211 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 41227 | /* 115215 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 41228 | /* 115217 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41229 | /* 115220 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 41230 | /* 115222 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 41231 | /* 115225 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 41232 | /* 115230 */ // GIR_Coverage, 2329, |
| 41233 | /* 115230 */ GIR_EraseRootFromParent_Done, |
| 41234 | /* 115231 */ // Label 2206: @115231 |
| 41235 | /* 115231 */ GIM_Try, /*On fail goto*//*Label 2207*/ GIMT_Encode4(115297), // Rule ID 2331 // |
| 41236 | /* 115236 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8), |
| 41237 | /* 115239 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 41238 | /* 115242 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 41239 | /* 115246 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 41240 | /* 115250 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FFLOOR), |
| 41241 | /* 115254 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 41242 | /* 115258 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 41243 | /* 115263 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 41244 | /* 115265 */ // (fp_to_sint:{ *:[i32] } (ffloor:{ *:[f32] } SPR:{ *:[f32] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTMSS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] }) |
| 41245 | /* 115265 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 41246 | /* 115268 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTMSS), |
| 41247 | /* 115272 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 41248 | /* 115277 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 41249 | /* 115281 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 41250 | /* 115283 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41251 | /* 115286 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 41252 | /* 115288 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 41253 | /* 115291 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 41254 | /* 115296 */ // GIR_Coverage, 2331, |
| 41255 | /* 115296 */ GIR_EraseRootFromParent_Done, |
| 41256 | /* 115297 */ // Label 2207: @115297 |
| 41257 | /* 115297 */ GIM_Try, /*On fail goto*//*Label 2208*/ GIMT_Encode4(115363), // Rule ID 2333 // |
| 41258 | /* 115302 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), |
| 41259 | /* 115305 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 41260 | /* 115308 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 41261 | /* 115312 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 41262 | /* 115316 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FFLOOR), |
| 41263 | /* 115320 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 41264 | /* 115324 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41265 | /* 115329 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 41266 | /* 115331 */ // (fp_to_sint:{ *:[i32] } (ffloor:{ *:[f64] } DPR:{ *:[f64] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTMSD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] }) |
| 41267 | /* 115331 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 41268 | /* 115334 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTMSD), |
| 41269 | /* 115338 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 41270 | /* 115343 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 41271 | /* 115347 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 41272 | /* 115349 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41273 | /* 115352 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 41274 | /* 115354 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 41275 | /* 115357 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 41276 | /* 115362 */ // GIR_Coverage, 2333, |
| 41277 | /* 115362 */ GIR_EraseRootFromParent_Done, |
| 41278 | /* 115363 */ // Label 2208: @115363 |
| 41279 | /* 115363 */ GIM_Try, /*On fail goto*//*Label 2209*/ GIMT_Encode4(115429), // Rule ID 2317 // |
| 41280 | /* 115368 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 41281 | /* 115371 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 41282 | /* 115374 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 41283 | /* 115378 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 41284 | /* 115382 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND), |
| 41285 | /* 115386 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 41286 | /* 115390 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 41287 | /* 115395 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 41288 | /* 115397 */ // (fp_to_sint:{ *:[i32] } (fround:{ *:[f16] } HPR:{ *:[f16] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTASH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] }) |
| 41289 | /* 115397 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 41290 | /* 115400 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTASH), |
| 41291 | /* 115404 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 41292 | /* 115409 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 41293 | /* 115413 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 41294 | /* 115415 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41295 | /* 115418 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 41296 | /* 115420 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 41297 | /* 115423 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 41298 | /* 115428 */ // GIR_Coverage, 2317, |
| 41299 | /* 115428 */ GIR_EraseRootFromParent_Done, |
| 41300 | /* 115429 */ // Label 2209: @115429 |
| 41301 | /* 115429 */ GIM_Try, /*On fail goto*//*Label 2210*/ GIMT_Encode4(115495), // Rule ID 2319 // |
| 41302 | /* 115434 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8), |
| 41303 | /* 115437 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 41304 | /* 115440 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 41305 | /* 115444 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 41306 | /* 115448 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND), |
| 41307 | /* 115452 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 41308 | /* 115456 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 41309 | /* 115461 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 41310 | /* 115463 */ // (fp_to_sint:{ *:[i32] } (fround:{ *:[f32] } SPR:{ *:[f32] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTASS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] }) |
| 41311 | /* 115463 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 41312 | /* 115466 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTASS), |
| 41313 | /* 115470 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 41314 | /* 115475 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 41315 | /* 115479 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 41316 | /* 115481 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41317 | /* 115484 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 41318 | /* 115486 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 41319 | /* 115489 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 41320 | /* 115494 */ // GIR_Coverage, 2319, |
| 41321 | /* 115494 */ GIR_EraseRootFromParent_Done, |
| 41322 | /* 115495 */ // Label 2210: @115495 |
| 41323 | /* 115495 */ GIM_Try, /*On fail goto*//*Label 2211*/ GIMT_Encode4(115561), // Rule ID 2321 // |
| 41324 | /* 115500 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), |
| 41325 | /* 115503 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 41326 | /* 115506 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 41327 | /* 115510 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 41328 | /* 115514 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND), |
| 41329 | /* 115518 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 41330 | /* 115522 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41331 | /* 115527 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 41332 | /* 115529 */ // (fp_to_sint:{ *:[i32] } (fround:{ *:[f64] } DPR:{ *:[f64] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTASD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] }) |
| 41333 | /* 115529 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 41334 | /* 115532 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTASD), |
| 41335 | /* 115536 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 41336 | /* 115541 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 41337 | /* 115545 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 41338 | /* 115547 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41339 | /* 115550 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 41340 | /* 115552 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 41341 | /* 115555 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 41342 | /* 115560 */ // GIR_Coverage, 2321, |
| 41343 | /* 115560 */ GIR_EraseRootFromParent_Done, |
| 41344 | /* 115561 */ // Label 2211: @115561 |
| 41345 | /* 115561 */ GIM_Try, /*On fail goto*//*Label 2212*/ GIMT_Encode4(115621), // Rule ID 2352 // |
| 41346 | /* 115566 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), |
| 41347 | /* 115569 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 41348 | /* 115572 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 41349 | /* 115576 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41350 | /* 115580 */ // (fp_to_sint:{ *:[i32] } DPR:{ *:[f64] }:$a) => (COPY_TO_REGCLASS:{ *:[i32] } (VTOSIZD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] }) |
| 41351 | /* 115580 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 41352 | /* 115583 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VTOSIZD), |
| 41353 | /* 115587 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 41354 | /* 115592 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 41355 | /* 115596 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 41356 | /* 115599 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41357 | /* 115605 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 41358 | /* 115607 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41359 | /* 115610 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 41360 | /* 115612 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 41361 | /* 115615 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 41362 | /* 115620 */ // GIR_Coverage, 2352, |
| 41363 | /* 115620 */ GIR_EraseRootFromParent_Done, |
| 41364 | /* 115621 */ // Label 2212: @115621 |
| 41365 | /* 115621 */ GIM_Try, /*On fail goto*//*Label 2213*/ GIMT_Encode4(115681), // Rule ID 2356 // |
| 41366 | /* 115626 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), |
| 41367 | /* 115629 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 41368 | /* 115632 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 41369 | /* 115636 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 41370 | /* 115640 */ // (fp_to_sint:{ *:[i32] } SPR:{ *:[f32] }:$a) => (COPY_TO_REGCLASS:{ *:[i32] } (VTOSIZS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] }) |
| 41371 | /* 115640 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 41372 | /* 115643 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VTOSIZS), |
| 41373 | /* 115647 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 41374 | /* 115652 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 41375 | /* 115656 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 41376 | /* 115659 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41377 | /* 115665 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 41378 | /* 115667 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41379 | /* 115670 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 41380 | /* 115672 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 41381 | /* 115675 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 41382 | /* 115680 */ // GIR_Coverage, 2356, |
| 41383 | /* 115680 */ GIR_EraseRootFromParent_Done, |
| 41384 | /* 115681 */ // Label 2213: @115681 |
| 41385 | /* 115681 */ GIM_Try, /*On fail goto*//*Label 2214*/ GIMT_Encode4(115741), // Rule ID 2360 // |
| 41386 | /* 115686 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), |
| 41387 | /* 115689 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 41388 | /* 115692 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 41389 | /* 115696 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 41390 | /* 115700 */ // (fp_to_sint:{ *:[i32] } HPR:{ *:[f16] }:$a) => (COPY_TO_REGCLASS:{ *:[i32] } (VTOSIZH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] }) |
| 41391 | /* 115700 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 41392 | /* 115703 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VTOSIZH), |
| 41393 | /* 115707 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 41394 | /* 115712 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 41395 | /* 115716 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 41396 | /* 115719 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41397 | /* 115725 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 41398 | /* 115727 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41399 | /* 115730 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 41400 | /* 115732 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 41401 | /* 115735 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 41402 | /* 115740 */ // GIR_Coverage, 2360, |
| 41403 | /* 115740 */ GIR_EraseRootFromParent_Done, |
| 41404 | /* 115741 */ // Label 2214: @115741 |
| 41405 | /* 115741 */ GIM_Try, /*On fail goto*//*Label 2215*/ GIMT_Encode4(115860), // Rule ID 2710 // |
| 41406 | /* 115746 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_UseNEONForFP), |
| 41407 | /* 115749 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 41408 | /* 115752 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 41409 | /* 115756 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 41410 | /* 115760 */ // (fp_to_sint:{ *:[i32] } SPR:{ *:[f32] }:$a) => (EXTRACT_SUBREG:{ *:[i32] } (VCVTf2sd:{ *:[v2f32] } (INSERT_SUBREG:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] })), ssub_0:{ *:[i32] }) |
| 41411 | /* 115760 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32, |
| 41412 | /* 115763 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 41413 | /* 115767 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 41414 | /* 115772 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 41415 | /* 115774 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v2s32, |
| 41416 | /* 115777 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 41417 | /* 115781 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 41418 | /* 115786 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 41419 | /* 115789 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 41420 | /* 115793 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/17, |
| 41421 | /* 115796 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 41422 | /* 115801 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 41423 | /* 115806 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 41424 | /* 115811 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32, |
| 41425 | /* 115814 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTf2sd), |
| 41426 | /* 115818 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 41427 | /* 115823 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 41428 | /* 115826 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 41429 | /* 115829 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41430 | /* 115835 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 41431 | /* 115837 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41432 | /* 115840 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 41433 | /* 115842 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0), |
| 41434 | /* 115849 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 41435 | /* 115854 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 41436 | /* 115859 */ // GIR_Coverage, 2710, |
| 41437 | /* 115859 */ GIR_EraseRootFromParent_Done, |
| 41438 | /* 115860 */ // Label 2215: @115860 |
| 41439 | /* 115860 */ GIM_Reject, |
| 41440 | /* 115861 */ // Label 2196: @115861 |
| 41441 | /* 115861 */ GIM_Try, /*On fail goto*//*Label 2216*/ GIMT_Encode4(115898), // Rule ID 1604 // |
| 41442 | /* 115866 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 41443 | /* 115869 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 41444 | /* 115872 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41445 | /* 115876 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41446 | /* 115880 */ // (fp_to_sint:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm) => (VCVTf2sd:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm) |
| 41447 | /* 115880 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTf2sd), |
| 41448 | /* 115883 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 41449 | /* 115885 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 41450 | /* 115887 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 41451 | /* 115890 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41452 | /* 115896 */ GIR_RootConstrainSelectedInstOperands, |
| 41453 | /* 115897 */ // GIR_Coverage, 1604, |
| 41454 | /* 115897 */ GIR_EraseRootFromParent_Done, |
| 41455 | /* 115898 */ // Label 2216: @115898 |
| 41456 | /* 115898 */ GIM_Reject, |
| 41457 | /* 115899 */ // Label 2197: @115899 |
| 41458 | /* 115899 */ GIM_Try, /*On fail goto*//*Label 2217*/ GIMT_Encode4(115951), // Rule ID 5105 // |
| 41459 | /* 115904 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 41460 | /* 115907 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 41461 | /* 115910 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 41462 | /* 115914 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 41463 | /* 115918 */ // (fp_to_sint:{ *:[v4i1] } MQPR:{ *:[v4f32] }:$v1) => (MVE_VCMPf32r:{ *:[v4i1] } MQPR:{ *:[v4f32] }:$v1, ZR:{ *:[i32] }, 1:{ *:[i32] }) |
| 41464 | /* 115918 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf32r), |
| 41465 | /* 115921 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0] |
| 41466 | /* 115923 */ GIR_RootToRootCopy, /*OpIdx*/1, // v1 |
| 41467 | /* 115925 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::ZR), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41468 | /* 115931 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 41469 | /* 115934 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 41470 | /* 115937 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41471 | /* 115943 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41472 | /* 115949 */ GIR_RootConstrainSelectedInstOperands, |
| 41473 | /* 115950 */ // GIR_Coverage, 5105, |
| 41474 | /* 115950 */ GIR_EraseRootFromParent_Done, |
| 41475 | /* 115951 */ // Label 2217: @115951 |
| 41476 | /* 115951 */ GIM_Reject, |
| 41477 | /* 115952 */ // Label 2198: @115952 |
| 41478 | /* 115952 */ GIM_Try, /*On fail goto*//*Label 2218*/ GIMT_Encode4(115989), // Rule ID 1612 // |
| 41479 | /* 115957 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 41480 | /* 115960 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 41481 | /* 115963 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41482 | /* 115967 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41483 | /* 115971 */ // (fp_to_sint:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm) => (VCVTh2sd:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm) |
| 41484 | /* 115971 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTh2sd), |
| 41485 | /* 115974 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 41486 | /* 115976 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 41487 | /* 115978 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 41488 | /* 115981 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41489 | /* 115987 */ GIR_RootConstrainSelectedInstOperands, |
| 41490 | /* 115988 */ // GIR_Coverage, 1612, |
| 41491 | /* 115988 */ GIR_EraseRootFromParent_Done, |
| 41492 | /* 115989 */ // Label 2218: @115989 |
| 41493 | /* 115989 */ GIM_Reject, |
| 41494 | /* 115990 */ // Label 2199: @115990 |
| 41495 | /* 115990 */ GIM_Try, /*On fail goto*//*Label 2219*/ GIMT_Encode4(116088), |
| 41496 | /* 115995 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 41497 | /* 115998 */ GIM_Try, /*On fail goto*//*Label 2220*/ GIMT_Encode4(116032), // Rule ID 1608 // |
| 41498 | /* 116003 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 41499 | /* 116006 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 41500 | /* 116010 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 41501 | /* 116014 */ // (fp_to_sint:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm) => (VCVTf2sq:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm) |
| 41502 | /* 116014 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTf2sq), |
| 41503 | /* 116017 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 41504 | /* 116019 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 41505 | /* 116021 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 41506 | /* 116024 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41507 | /* 116030 */ GIR_RootConstrainSelectedInstOperands, |
| 41508 | /* 116031 */ // GIR_Coverage, 1608, |
| 41509 | /* 116031 */ GIR_EraseRootFromParent_Done, |
| 41510 | /* 116032 */ // Label 2220: @116032 |
| 41511 | /* 116032 */ GIM_Try, /*On fail goto*//*Label 2221*/ GIMT_Encode4(116087), // Rule ID 4094 // |
| 41512 | /* 116037 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 41513 | /* 116040 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 41514 | /* 116044 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 41515 | /* 116048 */ // (fp_to_sint:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$src) => (MVE_VCVTs32f32z:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$src) |
| 41516 | /* 116048 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 41517 | /* 116051 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 41518 | /* 116055 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 41519 | /* 116060 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs32f32z), |
| 41520 | /* 116063 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 41521 | /* 116065 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 41522 | /* 116067 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 41523 | /* 116070 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41524 | /* 116076 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41525 | /* 116082 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 41526 | /* 116085 */ GIR_RootConstrainSelectedInstOperands, |
| 41527 | /* 116086 */ // GIR_Coverage, 4094, |
| 41528 | /* 116086 */ GIR_EraseRootFromParent_Done, |
| 41529 | /* 116087 */ // Label 2221: @116087 |
| 41530 | /* 116087 */ GIM_Reject, |
| 41531 | /* 116088 */ // Label 2219: @116088 |
| 41532 | /* 116088 */ GIM_Reject, |
| 41533 | /* 116089 */ // Label 2200: @116089 |
| 41534 | /* 116089 */ GIM_Try, /*On fail goto*//*Label 2222*/ GIMT_Encode4(116141), // Rule ID 5106 // |
| 41535 | /* 116094 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 41536 | /* 116097 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 41537 | /* 116100 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 41538 | /* 116104 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 41539 | /* 116108 */ // (fp_to_sint:{ *:[v8i1] } MQPR:{ *:[v8f16] }:$v1) => (MVE_VCMPf16r:{ *:[v8i1] } MQPR:{ *:[v8f16] }:$v1, ZR:{ *:[i32] }, 1:{ *:[i32] }) |
| 41540 | /* 116108 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf16r), |
| 41541 | /* 116111 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0] |
| 41542 | /* 116113 */ GIR_RootToRootCopy, /*OpIdx*/1, // v1 |
| 41543 | /* 116115 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::ZR), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41544 | /* 116121 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 41545 | /* 116124 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 41546 | /* 116127 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41547 | /* 116133 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41548 | /* 116139 */ GIR_RootConstrainSelectedInstOperands, |
| 41549 | /* 116140 */ // GIR_Coverage, 5106, |
| 41550 | /* 116140 */ GIR_EraseRootFromParent_Done, |
| 41551 | /* 116141 */ // Label 2222: @116141 |
| 41552 | /* 116141 */ GIM_Reject, |
| 41553 | /* 116142 */ // Label 2201: @116142 |
| 41554 | /* 116142 */ GIM_Try, /*On fail goto*//*Label 2223*/ GIMT_Encode4(116240), |
| 41555 | /* 116147 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 41556 | /* 116150 */ GIM_Try, /*On fail goto*//*Label 2224*/ GIMT_Encode4(116184), // Rule ID 1616 // |
| 41557 | /* 116155 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 41558 | /* 116158 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 41559 | /* 116162 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 41560 | /* 116166 */ // (fp_to_sint:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm) => (VCVTh2sq:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm) |
| 41561 | /* 116166 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTh2sq), |
| 41562 | /* 116169 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 41563 | /* 116171 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 41564 | /* 116173 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 41565 | /* 116176 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41566 | /* 116182 */ GIR_RootConstrainSelectedInstOperands, |
| 41567 | /* 116183 */ // GIR_Coverage, 1616, |
| 41568 | /* 116183 */ GIR_EraseRootFromParent_Done, |
| 41569 | /* 116184 */ // Label 2224: @116184 |
| 41570 | /* 116184 */ GIM_Try, /*On fail goto*//*Label 2225*/ GIMT_Encode4(116239), // Rule ID 4090 // |
| 41571 | /* 116189 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 41572 | /* 116192 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 41573 | /* 116196 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 41574 | /* 116200 */ // (fp_to_sint:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$src) => (MVE_VCVTs16f16z:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$src) |
| 41575 | /* 116200 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 41576 | /* 116203 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 41577 | /* 116207 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 41578 | /* 116212 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs16f16z), |
| 41579 | /* 116215 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 41580 | /* 116217 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 41581 | /* 116219 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 41582 | /* 116222 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41583 | /* 116228 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41584 | /* 116234 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 41585 | /* 116237 */ GIR_RootConstrainSelectedInstOperands, |
| 41586 | /* 116238 */ // GIR_Coverage, 4090, |
| 41587 | /* 116238 */ GIR_EraseRootFromParent_Done, |
| 41588 | /* 116239 */ // Label 2225: @116239 |
| 41589 | /* 116239 */ GIM_Reject, |
| 41590 | /* 116240 */ // Label 2223: @116240 |
| 41591 | /* 116240 */ GIM_Reject, |
| 41592 | /* 116241 */ // Label 2202: @116241 |
| 41593 | /* 116241 */ GIM_Reject, |
| 41594 | /* 116242 */ // Label 43: @116242 |
| 41595 | /* 116242 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(13), /*)*//*default:*//*Label 2233*/ GIMT_Encode4(117575), |
| 41596 | /* 116253 */ /*GILLT_s32*//*Label 2226*/ GIMT_Encode4(116301), GIMT_Encode4(0), GIMT_Encode4(0), |
| 41597 | /* 116265 */ /*GILLT_v2s32*//*Label 2227*/ GIMT_Encode4(117195), GIMT_Encode4(0), |
| 41598 | /* 116273 */ /*GILLT_v4s1*//*Label 2228*/ GIMT_Encode4(117233), |
| 41599 | /* 116277 */ /*GILLT_v4s16*//*Label 2229*/ GIMT_Encode4(117286), |
| 41600 | /* 116281 */ /*GILLT_v4s32*//*Label 2230*/ GIMT_Encode4(117324), GIMT_Encode4(0), |
| 41601 | /* 116289 */ /*GILLT_v8s1*//*Label 2231*/ GIMT_Encode4(117423), GIMT_Encode4(0), |
| 41602 | /* 116297 */ /*GILLT_v8s16*//*Label 2232*/ GIMT_Encode4(117476), |
| 41603 | /* 116301 */ // Label 2226: @116301 |
| 41604 | /* 116301 */ GIM_Try, /*On fail goto*//*Label 2234*/ GIMT_Encode4(116367), // Rule ID 2324 // |
| 41605 | /* 116306 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 41606 | /* 116309 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 41607 | /* 116312 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 41608 | /* 116316 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 41609 | /* 116320 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCEIL), |
| 41610 | /* 116324 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 41611 | /* 116328 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 41612 | /* 116333 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 41613 | /* 116335 */ // (fp_to_uint:{ *:[i32] } (fceil:{ *:[f16] } HPR:{ *:[f16] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTPUH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] }) |
| 41614 | /* 116335 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 41615 | /* 116338 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTPUH), |
| 41616 | /* 116342 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 41617 | /* 116347 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 41618 | /* 116351 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 41619 | /* 116353 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41620 | /* 116356 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 41621 | /* 116358 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 41622 | /* 116361 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 41623 | /* 116366 */ // GIR_Coverage, 2324, |
| 41624 | /* 116366 */ GIR_EraseRootFromParent_Done, |
| 41625 | /* 116367 */ // Label 2234: @116367 |
| 41626 | /* 116367 */ GIM_Try, /*On fail goto*//*Label 2235*/ GIMT_Encode4(116433), // Rule ID 2326 // |
| 41627 | /* 116372 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8), |
| 41628 | /* 116375 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 41629 | /* 116378 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 41630 | /* 116382 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 41631 | /* 116386 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCEIL), |
| 41632 | /* 116390 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 41633 | /* 116394 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 41634 | /* 116399 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 41635 | /* 116401 */ // (fp_to_uint:{ *:[i32] } (fceil:{ *:[f32] } SPR:{ *:[f32] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTPUS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] }) |
| 41636 | /* 116401 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 41637 | /* 116404 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTPUS), |
| 41638 | /* 116408 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 41639 | /* 116413 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 41640 | /* 116417 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 41641 | /* 116419 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41642 | /* 116422 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 41643 | /* 116424 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 41644 | /* 116427 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 41645 | /* 116432 */ // GIR_Coverage, 2326, |
| 41646 | /* 116432 */ GIR_EraseRootFromParent_Done, |
| 41647 | /* 116433 */ // Label 2235: @116433 |
| 41648 | /* 116433 */ GIM_Try, /*On fail goto*//*Label 2236*/ GIMT_Encode4(116499), // Rule ID 2328 // |
| 41649 | /* 116438 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), |
| 41650 | /* 116441 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 41651 | /* 116444 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 41652 | /* 116448 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 41653 | /* 116452 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCEIL), |
| 41654 | /* 116456 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 41655 | /* 116460 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41656 | /* 116465 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 41657 | /* 116467 */ // (fp_to_uint:{ *:[i32] } (fceil:{ *:[f64] } DPR:{ *:[f64] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTPUD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] }) |
| 41658 | /* 116467 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 41659 | /* 116470 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTPUD), |
| 41660 | /* 116474 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 41661 | /* 116479 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 41662 | /* 116483 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 41663 | /* 116485 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41664 | /* 116488 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 41665 | /* 116490 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 41666 | /* 116493 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 41667 | /* 116498 */ // GIR_Coverage, 2328, |
| 41668 | /* 116498 */ GIR_EraseRootFromParent_Done, |
| 41669 | /* 116499 */ // Label 2236: @116499 |
| 41670 | /* 116499 */ GIM_Try, /*On fail goto*//*Label 2237*/ GIMT_Encode4(116565), // Rule ID 2330 // |
| 41671 | /* 116504 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 41672 | /* 116507 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 41673 | /* 116510 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 41674 | /* 116514 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 41675 | /* 116518 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FFLOOR), |
| 41676 | /* 116522 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 41677 | /* 116526 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 41678 | /* 116531 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 41679 | /* 116533 */ // (fp_to_uint:{ *:[i32] } (ffloor:{ *:[f16] } HPR:{ *:[f16] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTMUH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] }) |
| 41680 | /* 116533 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 41681 | /* 116536 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTMUH), |
| 41682 | /* 116540 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 41683 | /* 116545 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 41684 | /* 116549 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 41685 | /* 116551 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41686 | /* 116554 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 41687 | /* 116556 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 41688 | /* 116559 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 41689 | /* 116564 */ // GIR_Coverage, 2330, |
| 41690 | /* 116564 */ GIR_EraseRootFromParent_Done, |
| 41691 | /* 116565 */ // Label 2237: @116565 |
| 41692 | /* 116565 */ GIM_Try, /*On fail goto*//*Label 2238*/ GIMT_Encode4(116631), // Rule ID 2332 // |
| 41693 | /* 116570 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8), |
| 41694 | /* 116573 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 41695 | /* 116576 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 41696 | /* 116580 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 41697 | /* 116584 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FFLOOR), |
| 41698 | /* 116588 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 41699 | /* 116592 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 41700 | /* 116597 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 41701 | /* 116599 */ // (fp_to_uint:{ *:[i32] } (ffloor:{ *:[f32] } SPR:{ *:[f32] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTMUS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] }) |
| 41702 | /* 116599 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 41703 | /* 116602 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTMUS), |
| 41704 | /* 116606 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 41705 | /* 116611 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 41706 | /* 116615 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 41707 | /* 116617 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41708 | /* 116620 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 41709 | /* 116622 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 41710 | /* 116625 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 41711 | /* 116630 */ // GIR_Coverage, 2332, |
| 41712 | /* 116630 */ GIR_EraseRootFromParent_Done, |
| 41713 | /* 116631 */ // Label 2238: @116631 |
| 41714 | /* 116631 */ GIM_Try, /*On fail goto*//*Label 2239*/ GIMT_Encode4(116697), // Rule ID 2334 // |
| 41715 | /* 116636 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), |
| 41716 | /* 116639 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 41717 | /* 116642 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 41718 | /* 116646 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 41719 | /* 116650 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FFLOOR), |
| 41720 | /* 116654 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 41721 | /* 116658 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41722 | /* 116663 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 41723 | /* 116665 */ // (fp_to_uint:{ *:[i32] } (ffloor:{ *:[f64] } DPR:{ *:[f64] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTMUD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] }) |
| 41724 | /* 116665 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 41725 | /* 116668 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTMUD), |
| 41726 | /* 116672 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 41727 | /* 116677 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 41728 | /* 116681 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 41729 | /* 116683 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41730 | /* 116686 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 41731 | /* 116688 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 41732 | /* 116691 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 41733 | /* 116696 */ // GIR_Coverage, 2334, |
| 41734 | /* 116696 */ GIR_EraseRootFromParent_Done, |
| 41735 | /* 116697 */ // Label 2239: @116697 |
| 41736 | /* 116697 */ GIM_Try, /*On fail goto*//*Label 2240*/ GIMT_Encode4(116763), // Rule ID 2318 // |
| 41737 | /* 116702 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 41738 | /* 116705 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 41739 | /* 116708 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 41740 | /* 116712 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 41741 | /* 116716 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND), |
| 41742 | /* 116720 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 41743 | /* 116724 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 41744 | /* 116729 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 41745 | /* 116731 */ // (fp_to_uint:{ *:[i32] } (fround:{ *:[f16] } HPR:{ *:[f16] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTAUH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] }) |
| 41746 | /* 116731 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 41747 | /* 116734 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTAUH), |
| 41748 | /* 116738 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 41749 | /* 116743 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 41750 | /* 116747 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 41751 | /* 116749 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41752 | /* 116752 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 41753 | /* 116754 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 41754 | /* 116757 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 41755 | /* 116762 */ // GIR_Coverage, 2318, |
| 41756 | /* 116762 */ GIR_EraseRootFromParent_Done, |
| 41757 | /* 116763 */ // Label 2240: @116763 |
| 41758 | /* 116763 */ GIM_Try, /*On fail goto*//*Label 2241*/ GIMT_Encode4(116829), // Rule ID 2320 // |
| 41759 | /* 116768 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8), |
| 41760 | /* 116771 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 41761 | /* 116774 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 41762 | /* 116778 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 41763 | /* 116782 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND), |
| 41764 | /* 116786 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 41765 | /* 116790 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 41766 | /* 116795 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 41767 | /* 116797 */ // (fp_to_uint:{ *:[i32] } (fround:{ *:[f32] } SPR:{ *:[f32] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTAUS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] }) |
| 41768 | /* 116797 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 41769 | /* 116800 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTAUS), |
| 41770 | /* 116804 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 41771 | /* 116809 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 41772 | /* 116813 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 41773 | /* 116815 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41774 | /* 116818 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 41775 | /* 116820 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 41776 | /* 116823 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 41777 | /* 116828 */ // GIR_Coverage, 2320, |
| 41778 | /* 116828 */ GIR_EraseRootFromParent_Done, |
| 41779 | /* 116829 */ // Label 2241: @116829 |
| 41780 | /* 116829 */ GIM_Try, /*On fail goto*//*Label 2242*/ GIMT_Encode4(116895), // Rule ID 2322 // |
| 41781 | /* 116834 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), |
| 41782 | /* 116837 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 41783 | /* 116840 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 41784 | /* 116844 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 41785 | /* 116848 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND), |
| 41786 | /* 116852 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 41787 | /* 116856 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41788 | /* 116861 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 41789 | /* 116863 */ // (fp_to_uint:{ *:[i32] } (fround:{ *:[f64] } DPR:{ *:[f64] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTAUD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] }) |
| 41790 | /* 116863 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 41791 | /* 116866 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTAUD), |
| 41792 | /* 116870 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 41793 | /* 116875 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 41794 | /* 116879 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 41795 | /* 116881 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41796 | /* 116884 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 41797 | /* 116886 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 41798 | /* 116889 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 41799 | /* 116894 */ // GIR_Coverage, 2322, |
| 41800 | /* 116894 */ GIR_EraseRootFromParent_Done, |
| 41801 | /* 116895 */ // Label 2242: @116895 |
| 41802 | /* 116895 */ GIM_Try, /*On fail goto*//*Label 2243*/ GIMT_Encode4(116955), // Rule ID 2362 // |
| 41803 | /* 116900 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), |
| 41804 | /* 116903 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 41805 | /* 116906 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 41806 | /* 116910 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41807 | /* 116914 */ // (fp_to_uint:{ *:[i32] } DPR:{ *:[f64] }:$a) => (COPY_TO_REGCLASS:{ *:[i32] } (VTOUIZD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] }) |
| 41808 | /* 116914 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 41809 | /* 116917 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VTOUIZD), |
| 41810 | /* 116921 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 41811 | /* 116926 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 41812 | /* 116930 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 41813 | /* 116933 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41814 | /* 116939 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 41815 | /* 116941 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41816 | /* 116944 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 41817 | /* 116946 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 41818 | /* 116949 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 41819 | /* 116954 */ // GIR_Coverage, 2362, |
| 41820 | /* 116954 */ GIR_EraseRootFromParent_Done, |
| 41821 | /* 116955 */ // Label 2243: @116955 |
| 41822 | /* 116955 */ GIM_Try, /*On fail goto*//*Label 2244*/ GIMT_Encode4(117015), // Rule ID 2366 // |
| 41823 | /* 116960 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), |
| 41824 | /* 116963 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 41825 | /* 116966 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 41826 | /* 116970 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 41827 | /* 116974 */ // (fp_to_uint:{ *:[i32] } SPR:{ *:[f32] }:$a) => (COPY_TO_REGCLASS:{ *:[i32] } (VTOUIZS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] }) |
| 41828 | /* 116974 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 41829 | /* 116977 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VTOUIZS), |
| 41830 | /* 116981 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 41831 | /* 116986 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 41832 | /* 116990 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 41833 | /* 116993 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41834 | /* 116999 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 41835 | /* 117001 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41836 | /* 117004 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 41837 | /* 117006 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 41838 | /* 117009 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 41839 | /* 117014 */ // GIR_Coverage, 2366, |
| 41840 | /* 117014 */ GIR_EraseRootFromParent_Done, |
| 41841 | /* 117015 */ // Label 2244: @117015 |
| 41842 | /* 117015 */ GIM_Try, /*On fail goto*//*Label 2245*/ GIMT_Encode4(117075), // Rule ID 2370 // |
| 41843 | /* 117020 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), |
| 41844 | /* 117023 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 41845 | /* 117026 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 41846 | /* 117030 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 41847 | /* 117034 */ // (fp_to_uint:{ *:[i32] } HPR:{ *:[f16] }:$a) => (COPY_TO_REGCLASS:{ *:[i32] } (VTOUIZH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] }) |
| 41848 | /* 117034 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 41849 | /* 117037 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VTOUIZH), |
| 41850 | /* 117041 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 41851 | /* 117046 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 41852 | /* 117050 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 41853 | /* 117053 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41854 | /* 117059 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 41855 | /* 117061 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41856 | /* 117064 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 41857 | /* 117066 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 41858 | /* 117069 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 41859 | /* 117074 */ // GIR_Coverage, 2370, |
| 41860 | /* 117074 */ GIR_EraseRootFromParent_Done, |
| 41861 | /* 117075 */ // Label 2245: @117075 |
| 41862 | /* 117075 */ GIM_Try, /*On fail goto*//*Label 2246*/ GIMT_Encode4(117194), // Rule ID 2711 // |
| 41863 | /* 117080 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_UseNEONForFP), |
| 41864 | /* 117083 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 41865 | /* 117086 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 41866 | /* 117090 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 41867 | /* 117094 */ // (fp_to_uint:{ *:[i32] } SPR:{ *:[f32] }:$a) => (EXTRACT_SUBREG:{ *:[i32] } (VCVTf2ud:{ *:[v2f32] } (INSERT_SUBREG:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] })), ssub_0:{ *:[i32] }) |
| 41868 | /* 117094 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32, |
| 41869 | /* 117097 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 41870 | /* 117101 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 41871 | /* 117106 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 41872 | /* 117108 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v2s32, |
| 41873 | /* 117111 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 41874 | /* 117115 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 41875 | /* 117120 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 41876 | /* 117123 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 41877 | /* 117127 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/17, |
| 41878 | /* 117130 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 41879 | /* 117135 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 41880 | /* 117140 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 41881 | /* 117145 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32, |
| 41882 | /* 117148 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTf2ud), |
| 41883 | /* 117152 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 41884 | /* 117157 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 41885 | /* 117160 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 41886 | /* 117163 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41887 | /* 117169 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 41888 | /* 117171 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41889 | /* 117174 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 41890 | /* 117176 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0), |
| 41891 | /* 117183 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 41892 | /* 117188 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 41893 | /* 117193 */ // GIR_Coverage, 2711, |
| 41894 | /* 117193 */ GIR_EraseRootFromParent_Done, |
| 41895 | /* 117194 */ // Label 2246: @117194 |
| 41896 | /* 117194 */ GIM_Reject, |
| 41897 | /* 117195 */ // Label 2227: @117195 |
| 41898 | /* 117195 */ GIM_Try, /*On fail goto*//*Label 2247*/ GIMT_Encode4(117232), // Rule ID 1605 // |
| 41899 | /* 117200 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 41900 | /* 117203 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 41901 | /* 117206 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41902 | /* 117210 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41903 | /* 117214 */ // (fp_to_uint:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm) => (VCVTf2ud:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm) |
| 41904 | /* 117214 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTf2ud), |
| 41905 | /* 117217 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 41906 | /* 117219 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 41907 | /* 117221 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 41908 | /* 117224 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41909 | /* 117230 */ GIR_RootConstrainSelectedInstOperands, |
| 41910 | /* 117231 */ // GIR_Coverage, 1605, |
| 41911 | /* 117231 */ GIR_EraseRootFromParent_Done, |
| 41912 | /* 117232 */ // Label 2247: @117232 |
| 41913 | /* 117232 */ GIM_Reject, |
| 41914 | /* 117233 */ // Label 2228: @117233 |
| 41915 | /* 117233 */ GIM_Try, /*On fail goto*//*Label 2248*/ GIMT_Encode4(117285), // Rule ID 5103 // |
| 41916 | /* 117238 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 41917 | /* 117241 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 41918 | /* 117244 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 41919 | /* 117248 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 41920 | /* 117252 */ // (fp_to_uint:{ *:[v4i1] } MQPR:{ *:[v4f32] }:$v1) => (MVE_VCMPf32r:{ *:[v4i1] } MQPR:{ *:[v4f32] }:$v1, ZR:{ *:[i32] }, 1:{ *:[i32] }) |
| 41921 | /* 117252 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf32r), |
| 41922 | /* 117255 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0] |
| 41923 | /* 117257 */ GIR_RootToRootCopy, /*OpIdx*/1, // v1 |
| 41924 | /* 117259 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::ZR), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41925 | /* 117265 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 41926 | /* 117268 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 41927 | /* 117271 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41928 | /* 117277 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41929 | /* 117283 */ GIR_RootConstrainSelectedInstOperands, |
| 41930 | /* 117284 */ // GIR_Coverage, 5103, |
| 41931 | /* 117284 */ GIR_EraseRootFromParent_Done, |
| 41932 | /* 117285 */ // Label 2248: @117285 |
| 41933 | /* 117285 */ GIM_Reject, |
| 41934 | /* 117286 */ // Label 2229: @117286 |
| 41935 | /* 117286 */ GIM_Try, /*On fail goto*//*Label 2249*/ GIMT_Encode4(117323), // Rule ID 1613 // |
| 41936 | /* 117291 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 41937 | /* 117294 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 41938 | /* 117297 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41939 | /* 117301 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41940 | /* 117305 */ // (fp_to_uint:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm) => (VCVTh2ud:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm) |
| 41941 | /* 117305 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTh2ud), |
| 41942 | /* 117308 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 41943 | /* 117310 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 41944 | /* 117312 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 41945 | /* 117315 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41946 | /* 117321 */ GIR_RootConstrainSelectedInstOperands, |
| 41947 | /* 117322 */ // GIR_Coverage, 1613, |
| 41948 | /* 117322 */ GIR_EraseRootFromParent_Done, |
| 41949 | /* 117323 */ // Label 2249: @117323 |
| 41950 | /* 117323 */ GIM_Reject, |
| 41951 | /* 117324 */ // Label 2230: @117324 |
| 41952 | /* 117324 */ GIM_Try, /*On fail goto*//*Label 2250*/ GIMT_Encode4(117422), |
| 41953 | /* 117329 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 41954 | /* 117332 */ GIM_Try, /*On fail goto*//*Label 2251*/ GIMT_Encode4(117366), // Rule ID 1609 // |
| 41955 | /* 117337 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 41956 | /* 117340 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 41957 | /* 117344 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 41958 | /* 117348 */ // (fp_to_uint:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm) => (VCVTf2uq:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm) |
| 41959 | /* 117348 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTf2uq), |
| 41960 | /* 117351 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 41961 | /* 117353 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 41962 | /* 117355 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 41963 | /* 117358 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41964 | /* 117364 */ GIR_RootConstrainSelectedInstOperands, |
| 41965 | /* 117365 */ // GIR_Coverage, 1609, |
| 41966 | /* 117365 */ GIR_EraseRootFromParent_Done, |
| 41967 | /* 117366 */ // Label 2251: @117366 |
| 41968 | /* 117366 */ GIM_Try, /*On fail goto*//*Label 2252*/ GIMT_Encode4(117421), // Rule ID 4096 // |
| 41969 | /* 117371 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 41970 | /* 117374 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 41971 | /* 117378 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 41972 | /* 117382 */ // (fp_to_uint:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$src) => (MVE_VCVTu32f32z:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$src) |
| 41973 | /* 117382 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 41974 | /* 117385 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 41975 | /* 117389 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 41976 | /* 117394 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu32f32z), |
| 41977 | /* 117397 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 41978 | /* 117399 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 41979 | /* 117401 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 41980 | /* 117404 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41981 | /* 117410 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41982 | /* 117416 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 41983 | /* 117419 */ GIR_RootConstrainSelectedInstOperands, |
| 41984 | /* 117420 */ // GIR_Coverage, 4096, |
| 41985 | /* 117420 */ GIR_EraseRootFromParent_Done, |
| 41986 | /* 117421 */ // Label 2252: @117421 |
| 41987 | /* 117421 */ GIM_Reject, |
| 41988 | /* 117422 */ // Label 2250: @117422 |
| 41989 | /* 117422 */ GIM_Reject, |
| 41990 | /* 117423 */ // Label 2231: @117423 |
| 41991 | /* 117423 */ GIM_Try, /*On fail goto*//*Label 2253*/ GIMT_Encode4(117475), // Rule ID 5104 // |
| 41992 | /* 117428 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 41993 | /* 117431 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 41994 | /* 117434 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 41995 | /* 117438 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 41996 | /* 117442 */ // (fp_to_uint:{ *:[v8i1] } MQPR:{ *:[v8f16] }:$v1) => (MVE_VCMPf16r:{ *:[v8i1] } MQPR:{ *:[v8f16] }:$v1, ZR:{ *:[i32] }, 1:{ *:[i32] }) |
| 41997 | /* 117442 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf16r), |
| 41998 | /* 117445 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0] |
| 41999 | /* 117447 */ GIR_RootToRootCopy, /*OpIdx*/1, // v1 |
| 42000 | /* 117449 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::ZR), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42001 | /* 117455 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 42002 | /* 117458 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42003 | /* 117461 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42004 | /* 117467 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42005 | /* 117473 */ GIR_RootConstrainSelectedInstOperands, |
| 42006 | /* 117474 */ // GIR_Coverage, 5104, |
| 42007 | /* 117474 */ GIR_EraseRootFromParent_Done, |
| 42008 | /* 117475 */ // Label 2253: @117475 |
| 42009 | /* 117475 */ GIM_Reject, |
| 42010 | /* 117476 */ // Label 2232: @117476 |
| 42011 | /* 117476 */ GIM_Try, /*On fail goto*//*Label 2254*/ GIMT_Encode4(117574), |
| 42012 | /* 117481 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 42013 | /* 117484 */ GIM_Try, /*On fail goto*//*Label 2255*/ GIMT_Encode4(117518), // Rule ID 1617 // |
| 42014 | /* 117489 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 42015 | /* 117492 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 42016 | /* 117496 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 42017 | /* 117500 */ // (fp_to_uint:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm) => (VCVTh2uq:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm) |
| 42018 | /* 117500 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTh2uq), |
| 42019 | /* 117503 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 42020 | /* 117505 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 42021 | /* 117507 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42022 | /* 117510 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42023 | /* 117516 */ GIR_RootConstrainSelectedInstOperands, |
| 42024 | /* 117517 */ // GIR_Coverage, 1617, |
| 42025 | /* 117517 */ GIR_EraseRootFromParent_Done, |
| 42026 | /* 117518 */ // Label 2255: @117518 |
| 42027 | /* 117518 */ GIM_Try, /*On fail goto*//*Label 2256*/ GIMT_Encode4(117573), // Rule ID 4092 // |
| 42028 | /* 117523 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 42029 | /* 117526 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42030 | /* 117530 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42031 | /* 117534 */ // (fp_to_uint:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$src) => (MVE_VCVTu16f16z:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$src) |
| 42032 | /* 117534 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 42033 | /* 117537 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 42034 | /* 117541 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 42035 | /* 117546 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu16f16z), |
| 42036 | /* 117549 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 42037 | /* 117551 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 42038 | /* 117553 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42039 | /* 117556 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42040 | /* 117562 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42041 | /* 117568 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 42042 | /* 117571 */ GIR_RootConstrainSelectedInstOperands, |
| 42043 | /* 117572 */ // GIR_Coverage, 4092, |
| 42044 | /* 117572 */ GIR_EraseRootFromParent_Done, |
| 42045 | /* 117573 */ // Label 2256: @117573 |
| 42046 | /* 117573 */ GIM_Reject, |
| 42047 | /* 117574 */ // Label 2254: @117574 |
| 42048 | /* 117574 */ GIM_Reject, |
| 42049 | /* 117575 */ // Label 2233: @117575 |
| 42050 | /* 117575 */ GIM_Reject, |
| 42051 | /* 117576 */ // Label 44: @117576 |
| 42052 | /* 117576 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 2264*/ GIMT_Encode4(118227), |
| 42053 | /* 117587 */ /*GILLT_s16*//*Label 2257*/ GIMT_Encode4(117639), |
| 42054 | /* 117591 */ /*GILLT_s32*//*Label 2258*/ GIMT_Encode4(117699), |
| 42055 | /* 117595 */ /*GILLT_s64*//*Label 2259*/ GIMT_Encode4(117893), GIMT_Encode4(0), |
| 42056 | /* 117603 */ /*GILLT_v2s32*//*Label 2260*/ GIMT_Encode4(117953), GIMT_Encode4(0), GIMT_Encode4(0), |
| 42057 | /* 117615 */ /*GILLT_v4s16*//*Label 2261*/ GIMT_Encode4(117991), |
| 42058 | /* 117619 */ /*GILLT_v4s32*//*Label 2262*/ GIMT_Encode4(118029), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 42059 | /* 117635 */ /*GILLT_v8s16*//*Label 2263*/ GIMT_Encode4(118128), |
| 42060 | /* 117639 */ // Label 2257: @117639 |
| 42061 | /* 117639 */ GIM_Try, /*On fail goto*//*Label 2265*/ GIMT_Encode4(117698), // Rule ID 2346 // |
| 42062 | /* 117644 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), |
| 42063 | /* 117647 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 42064 | /* 117650 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 42065 | /* 117654 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 42066 | /* 117658 */ // (sint_to_fp:{ *:[f16] } GPR:{ *:[i32] }:$a) => (VSITOH:{ *:[f16] } (COPY_TO_REGCLASS:{ *:[f32] } GPR:{ *:[i32] }:$a, SPR:{ *:[i32] })) |
| 42067 | /* 117658 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 42068 | /* 117661 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 42069 | /* 117665 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 42070 | /* 117670 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 42071 | /* 117674 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 42072 | /* 117679 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSITOH), |
| 42073 | /* 117682 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 42074 | /* 117684 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 42075 | /* 117687 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42076 | /* 117690 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42077 | /* 117696 */ GIR_RootConstrainSelectedInstOperands, |
| 42078 | /* 117697 */ // GIR_Coverage, 2346, |
| 42079 | /* 117697 */ GIR_EraseRootFromParent_Done, |
| 42080 | /* 117698 */ // Label 2265: @117698 |
| 42081 | /* 117698 */ GIM_Reject, |
| 42082 | /* 117699 */ // Label 2258: @117699 |
| 42083 | /* 117699 */ GIM_Try, /*On fail goto*//*Label 2266*/ GIMT_Encode4(117892), |
| 42084 | /* 117704 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 42085 | /* 117707 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 42086 | /* 117711 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 42087 | /* 117715 */ GIM_Try, /*On fail goto*//*Label 2267*/ GIMT_Encode4(117763), // Rule ID 2344 // |
| 42088 | /* 117720 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), |
| 42089 | /* 117723 */ // (sint_to_fp:{ *:[f32] } GPR:{ *:[i32] }:$a) => (VSITOS:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[f32] } GPR:{ *:[i32] }:$a, SPR:{ *:[i32] })) |
| 42090 | /* 117723 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 42091 | /* 117726 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 42092 | /* 117730 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 42093 | /* 117735 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 42094 | /* 117739 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 42095 | /* 117744 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSITOS), |
| 42096 | /* 117747 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 42097 | /* 117749 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 42098 | /* 117752 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42099 | /* 117755 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42100 | /* 117761 */ GIR_RootConstrainSelectedInstOperands, |
| 42101 | /* 117762 */ // GIR_Coverage, 2344, |
| 42102 | /* 117762 */ GIR_EraseRootFromParent_Done, |
| 42103 | /* 117763 */ // Label 2267: @117763 |
| 42104 | /* 117763 */ GIM_Try, /*On fail goto*//*Label 2268*/ GIMT_Encode4(117891), // Rule ID 2712 // |
| 42105 | /* 117768 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_UseNEONForFP), |
| 42106 | /* 117771 */ // (sint_to_fp:{ *:[f32] } GPR:{ *:[i32] }:$a) => (EXTRACT_SUBREG:{ *:[f32] } (VCVTs2fd:{ *:[v2f32] } (INSERT_SUBREG:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), (COPY_TO_REGCLASS:{ *:[i32] } GPR:{ *:[i32] }:$a, SPR:{ *:[i32] }), ssub_0:{ *:[i32] })), ssub_0:{ *:[i32] }) |
| 42107 | /* 117771 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32, |
| 42108 | /* 117774 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 42109 | /* 117778 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 42110 | /* 117783 */ GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 42111 | /* 117787 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 42112 | /* 117792 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32, |
| 42113 | /* 117795 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 42114 | /* 117799 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 42115 | /* 117804 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 42116 | /* 117806 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v2s32, |
| 42117 | /* 117809 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 42118 | /* 117813 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 42119 | /* 117818 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 42120 | /* 117821 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3, |
| 42121 | /* 117824 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/17, |
| 42122 | /* 117827 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 42123 | /* 117832 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 42124 | /* 117837 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 42125 | /* 117842 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32, |
| 42126 | /* 117845 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTs2fd), |
| 42127 | /* 117849 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 42128 | /* 117854 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 42129 | /* 117857 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 42130 | /* 117860 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42131 | /* 117866 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 42132 | /* 117868 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 42133 | /* 117871 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 42134 | /* 117873 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0), |
| 42135 | /* 117880 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 42136 | /* 117885 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 42137 | /* 117890 */ // GIR_Coverage, 2712, |
| 42138 | /* 117890 */ GIR_EraseRootFromParent_Done, |
| 42139 | /* 117891 */ // Label 2268: @117891 |
| 42140 | /* 117891 */ GIM_Reject, |
| 42141 | /* 117892 */ // Label 2266: @117892 |
| 42142 | /* 117892 */ GIM_Reject, |
| 42143 | /* 117893 */ // Label 2259: @117893 |
| 42144 | /* 117893 */ GIM_Try, /*On fail goto*//*Label 2269*/ GIMT_Encode4(117952), // Rule ID 2342 // |
| 42145 | /* 117898 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), |
| 42146 | /* 117901 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 42147 | /* 117904 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42148 | /* 117908 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 42149 | /* 117912 */ // (sint_to_fp:{ *:[f64] } GPR:{ *:[i32] }:$a) => (VSITOD:{ *:[f64] } (COPY_TO_REGCLASS:{ *:[f32] } GPR:{ *:[i32] }:$a, SPR:{ *:[i32] })) |
| 42150 | /* 117912 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 42151 | /* 117915 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 42152 | /* 117919 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 42153 | /* 117924 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 42154 | /* 117928 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 42155 | /* 117933 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSITOD), |
| 42156 | /* 117936 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 42157 | /* 117938 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 42158 | /* 117941 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42159 | /* 117944 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42160 | /* 117950 */ GIR_RootConstrainSelectedInstOperands, |
| 42161 | /* 117951 */ // GIR_Coverage, 2342, |
| 42162 | /* 117951 */ GIR_EraseRootFromParent_Done, |
| 42163 | /* 117952 */ // Label 2269: @117952 |
| 42164 | /* 117952 */ GIM_Reject, |
| 42165 | /* 117953 */ // Label 2260: @117953 |
| 42166 | /* 117953 */ GIM_Try, /*On fail goto*//*Label 2270*/ GIMT_Encode4(117990), // Rule ID 1606 // |
| 42167 | /* 117958 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 42168 | /* 117961 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 42169 | /* 117964 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42170 | /* 117968 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42171 | /* 117972 */ // (sint_to_fp:{ *:[v2f32] } DPR:{ *:[v2i32] }:$Vm) => (VCVTs2fd:{ *:[v2f32] } DPR:{ *:[v2i32] }:$Vm) |
| 42172 | /* 117972 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTs2fd), |
| 42173 | /* 117975 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 42174 | /* 117977 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 42175 | /* 117979 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42176 | /* 117982 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42177 | /* 117988 */ GIR_RootConstrainSelectedInstOperands, |
| 42178 | /* 117989 */ // GIR_Coverage, 1606, |
| 42179 | /* 117989 */ GIR_EraseRootFromParent_Done, |
| 42180 | /* 117990 */ // Label 2270: @117990 |
| 42181 | /* 117990 */ GIM_Reject, |
| 42182 | /* 117991 */ // Label 2261: @117991 |
| 42183 | /* 117991 */ GIM_Try, /*On fail goto*//*Label 2271*/ GIMT_Encode4(118028), // Rule ID 1614 // |
| 42184 | /* 117996 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 42185 | /* 117999 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 42186 | /* 118002 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42187 | /* 118006 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42188 | /* 118010 */ // (sint_to_fp:{ *:[v4f16] } DPR:{ *:[v4i16] }:$Vm) => (VCVTs2hd:{ *:[v4f16] } DPR:{ *:[v4i16] }:$Vm) |
| 42189 | /* 118010 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTs2hd), |
| 42190 | /* 118013 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 42191 | /* 118015 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 42192 | /* 118017 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42193 | /* 118020 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42194 | /* 118026 */ GIR_RootConstrainSelectedInstOperands, |
| 42195 | /* 118027 */ // GIR_Coverage, 1614, |
| 42196 | /* 118027 */ GIR_EraseRootFromParent_Done, |
| 42197 | /* 118028 */ // Label 2271: @118028 |
| 42198 | /* 118028 */ GIM_Reject, |
| 42199 | /* 118029 */ // Label 2262: @118029 |
| 42200 | /* 118029 */ GIM_Try, /*On fail goto*//*Label 2272*/ GIMT_Encode4(118127), |
| 42201 | /* 118034 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 42202 | /* 118037 */ GIM_Try, /*On fail goto*//*Label 2273*/ GIMT_Encode4(118071), // Rule ID 1610 // |
| 42203 | /* 118042 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 42204 | /* 118045 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 42205 | /* 118049 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 42206 | /* 118053 */ // (sint_to_fp:{ *:[v4f32] } QPR:{ *:[v4i32] }:$Vm) => (VCVTs2fq:{ *:[v4f32] } QPR:{ *:[v4i32] }:$Vm) |
| 42207 | /* 118053 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTs2fq), |
| 42208 | /* 118056 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 42209 | /* 118058 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 42210 | /* 118060 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42211 | /* 118063 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42212 | /* 118069 */ GIR_RootConstrainSelectedInstOperands, |
| 42213 | /* 118070 */ // GIR_Coverage, 1610, |
| 42214 | /* 118070 */ GIR_EraseRootFromParent_Done, |
| 42215 | /* 118071 */ // Label 2273: @118071 |
| 42216 | /* 118071 */ GIM_Try, /*On fail goto*//*Label 2274*/ GIMT_Encode4(118126), // Rule ID 4102 // |
| 42217 | /* 118076 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 42218 | /* 118079 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42219 | /* 118083 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42220 | /* 118087 */ // (sint_to_fp:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$src) => (MVE_VCVTf32s32n:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$src) |
| 42221 | /* 118087 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 42222 | /* 118090 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 42223 | /* 118094 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 42224 | /* 118099 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf32s32n), |
| 42225 | /* 118102 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 42226 | /* 118104 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 42227 | /* 118106 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42228 | /* 118109 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42229 | /* 118115 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42230 | /* 118121 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 42231 | /* 118124 */ GIR_RootConstrainSelectedInstOperands, |
| 42232 | /* 118125 */ // GIR_Coverage, 4102, |
| 42233 | /* 118125 */ GIR_EraseRootFromParent_Done, |
| 42234 | /* 118126 */ // Label 2274: @118126 |
| 42235 | /* 118126 */ GIM_Reject, |
| 42236 | /* 118127 */ // Label 2272: @118127 |
| 42237 | /* 118127 */ GIM_Reject, |
| 42238 | /* 118128 */ // Label 2263: @118128 |
| 42239 | /* 118128 */ GIM_Try, /*On fail goto*//*Label 2275*/ GIMT_Encode4(118226), |
| 42240 | /* 118133 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 42241 | /* 118136 */ GIM_Try, /*On fail goto*//*Label 2276*/ GIMT_Encode4(118170), // Rule ID 1618 // |
| 42242 | /* 118141 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 42243 | /* 118144 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 42244 | /* 118148 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 42245 | /* 118152 */ // (sint_to_fp:{ *:[v8f16] } QPR:{ *:[v8i16] }:$Vm) => (VCVTs2hq:{ *:[v8f16] } QPR:{ *:[v8i16] }:$Vm) |
| 42246 | /* 118152 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTs2hq), |
| 42247 | /* 118155 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 42248 | /* 118157 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 42249 | /* 118159 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42250 | /* 118162 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42251 | /* 118168 */ GIR_RootConstrainSelectedInstOperands, |
| 42252 | /* 118169 */ // GIR_Coverage, 1618, |
| 42253 | /* 118169 */ GIR_EraseRootFromParent_Done, |
| 42254 | /* 118170 */ // Label 2276: @118170 |
| 42255 | /* 118170 */ GIM_Try, /*On fail goto*//*Label 2277*/ GIMT_Encode4(118225), // Rule ID 4098 // |
| 42256 | /* 118175 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 42257 | /* 118178 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42258 | /* 118182 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42259 | /* 118186 */ // (sint_to_fp:{ *:[v8f16] } MQPR:{ *:[v8i16] }:$src) => (MVE_VCVTf16s16n:{ *:[v8f16] } MQPR:{ *:[v8i16] }:$src) |
| 42260 | /* 118186 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 42261 | /* 118189 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 42262 | /* 118193 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 42263 | /* 118198 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf16s16n), |
| 42264 | /* 118201 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 42265 | /* 118203 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 42266 | /* 118205 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42267 | /* 118208 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42268 | /* 118214 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42269 | /* 118220 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 42270 | /* 118223 */ GIR_RootConstrainSelectedInstOperands, |
| 42271 | /* 118224 */ // GIR_Coverage, 4098, |
| 42272 | /* 118224 */ GIR_EraseRootFromParent_Done, |
| 42273 | /* 118225 */ // Label 2277: @118225 |
| 42274 | /* 118225 */ GIM_Reject, |
| 42275 | /* 118226 */ // Label 2275: @118226 |
| 42276 | /* 118226 */ GIM_Reject, |
| 42277 | /* 118227 */ // Label 2264: @118227 |
| 42278 | /* 118227 */ GIM_Reject, |
| 42279 | /* 118228 */ // Label 45: @118228 |
| 42280 | /* 118228 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 2285*/ GIMT_Encode4(118879), |
| 42281 | /* 118239 */ /*GILLT_s16*//*Label 2278*/ GIMT_Encode4(118291), |
| 42282 | /* 118243 */ /*GILLT_s32*//*Label 2279*/ GIMT_Encode4(118351), |
| 42283 | /* 118247 */ /*GILLT_s64*//*Label 2280*/ GIMT_Encode4(118545), GIMT_Encode4(0), |
| 42284 | /* 118255 */ /*GILLT_v2s32*//*Label 2281*/ GIMT_Encode4(118605), GIMT_Encode4(0), GIMT_Encode4(0), |
| 42285 | /* 118267 */ /*GILLT_v4s16*//*Label 2282*/ GIMT_Encode4(118643), |
| 42286 | /* 118271 */ /*GILLT_v4s32*//*Label 2283*/ GIMT_Encode4(118681), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 42287 | /* 118287 */ /*GILLT_v8s16*//*Label 2284*/ GIMT_Encode4(118780), |
| 42288 | /* 118291 */ // Label 2278: @118291 |
| 42289 | /* 118291 */ GIM_Try, /*On fail goto*//*Label 2286*/ GIMT_Encode4(118350), // Rule ID 2351 // |
| 42290 | /* 118296 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), |
| 42291 | /* 118299 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 42292 | /* 118302 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 42293 | /* 118306 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 42294 | /* 118310 */ // (uint_to_fp:{ *:[f16] } GPR:{ *:[i32] }:$a) => (VUITOH:{ *:[f16] } (COPY_TO_REGCLASS:{ *:[f32] } GPR:{ *:[i32] }:$a, SPR:{ *:[i32] })) |
| 42295 | /* 118310 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 42296 | /* 118313 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 42297 | /* 118317 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 42298 | /* 118322 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 42299 | /* 118326 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 42300 | /* 118331 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VUITOH), |
| 42301 | /* 118334 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 42302 | /* 118336 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 42303 | /* 118339 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42304 | /* 118342 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42305 | /* 118348 */ GIR_RootConstrainSelectedInstOperands, |
| 42306 | /* 118349 */ // GIR_Coverage, 2351, |
| 42307 | /* 118349 */ GIR_EraseRootFromParent_Done, |
| 42308 | /* 118350 */ // Label 2286: @118350 |
| 42309 | /* 118350 */ GIM_Reject, |
| 42310 | /* 118351 */ // Label 2279: @118351 |
| 42311 | /* 118351 */ GIM_Try, /*On fail goto*//*Label 2287*/ GIMT_Encode4(118544), |
| 42312 | /* 118356 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 42313 | /* 118359 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 42314 | /* 118363 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 42315 | /* 118367 */ GIM_Try, /*On fail goto*//*Label 2288*/ GIMT_Encode4(118415), // Rule ID 2349 // |
| 42316 | /* 118372 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), |
| 42317 | /* 118375 */ // (uint_to_fp:{ *:[f32] } GPR:{ *:[i32] }:$a) => (VUITOS:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[f32] } GPR:{ *:[i32] }:$a, SPR:{ *:[i32] })) |
| 42318 | /* 118375 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 42319 | /* 118378 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 42320 | /* 118382 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 42321 | /* 118387 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 42322 | /* 118391 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 42323 | /* 118396 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VUITOS), |
| 42324 | /* 118399 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 42325 | /* 118401 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 42326 | /* 118404 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42327 | /* 118407 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42328 | /* 118413 */ GIR_RootConstrainSelectedInstOperands, |
| 42329 | /* 118414 */ // GIR_Coverage, 2349, |
| 42330 | /* 118414 */ GIR_EraseRootFromParent_Done, |
| 42331 | /* 118415 */ // Label 2288: @118415 |
| 42332 | /* 118415 */ GIM_Try, /*On fail goto*//*Label 2289*/ GIMT_Encode4(118543), // Rule ID 2713 // |
| 42333 | /* 118420 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_UseNEONForFP), |
| 42334 | /* 118423 */ // (uint_to_fp:{ *:[f32] } GPR:{ *:[i32] }:$a) => (EXTRACT_SUBREG:{ *:[f32] } (VCVTu2fd:{ *:[v2f32] } (INSERT_SUBREG:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), (COPY_TO_REGCLASS:{ *:[i32] } GPR:{ *:[i32] }:$a, SPR:{ *:[i32] }), ssub_0:{ *:[i32] })), ssub_0:{ *:[i32] }) |
| 42335 | /* 118423 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32, |
| 42336 | /* 118426 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 42337 | /* 118430 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 42338 | /* 118435 */ GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 42339 | /* 118439 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 42340 | /* 118444 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32, |
| 42341 | /* 118447 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 42342 | /* 118451 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 42343 | /* 118456 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 42344 | /* 118458 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v2s32, |
| 42345 | /* 118461 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 42346 | /* 118465 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 42347 | /* 118470 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 42348 | /* 118473 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3, |
| 42349 | /* 118476 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/17, |
| 42350 | /* 118479 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 42351 | /* 118484 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 42352 | /* 118489 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 42353 | /* 118494 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32, |
| 42354 | /* 118497 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTu2fd), |
| 42355 | /* 118501 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 42356 | /* 118506 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 42357 | /* 118509 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 42358 | /* 118512 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42359 | /* 118518 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 42360 | /* 118520 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 42361 | /* 118523 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 42362 | /* 118525 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0), |
| 42363 | /* 118532 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 42364 | /* 118537 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 42365 | /* 118542 */ // GIR_Coverage, 2713, |
| 42366 | /* 118542 */ GIR_EraseRootFromParent_Done, |
| 42367 | /* 118543 */ // Label 2289: @118543 |
| 42368 | /* 118543 */ GIM_Reject, |
| 42369 | /* 118544 */ // Label 2287: @118544 |
| 42370 | /* 118544 */ GIM_Reject, |
| 42371 | /* 118545 */ // Label 2280: @118545 |
| 42372 | /* 118545 */ GIM_Try, /*On fail goto*//*Label 2290*/ GIMT_Encode4(118604), // Rule ID 2347 // |
| 42373 | /* 118550 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), |
| 42374 | /* 118553 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 42375 | /* 118556 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42376 | /* 118560 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 42377 | /* 118564 */ // (uint_to_fp:{ *:[f64] } GPR:{ *:[i32] }:$a) => (VUITOD:{ *:[f64] } (COPY_TO_REGCLASS:{ *:[f32] } GPR:{ *:[i32] }:$a, SPR:{ *:[i32] })) |
| 42378 | /* 118564 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 42379 | /* 118567 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 42380 | /* 118571 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 42381 | /* 118576 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 42382 | /* 118580 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 42383 | /* 118585 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VUITOD), |
| 42384 | /* 118588 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 42385 | /* 118590 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 42386 | /* 118593 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42387 | /* 118596 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42388 | /* 118602 */ GIR_RootConstrainSelectedInstOperands, |
| 42389 | /* 118603 */ // GIR_Coverage, 2347, |
| 42390 | /* 118603 */ GIR_EraseRootFromParent_Done, |
| 42391 | /* 118604 */ // Label 2290: @118604 |
| 42392 | /* 118604 */ GIM_Reject, |
| 42393 | /* 118605 */ // Label 2281: @118605 |
| 42394 | /* 118605 */ GIM_Try, /*On fail goto*//*Label 2291*/ GIMT_Encode4(118642), // Rule ID 1607 // |
| 42395 | /* 118610 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 42396 | /* 118613 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 42397 | /* 118616 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42398 | /* 118620 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42399 | /* 118624 */ // (uint_to_fp:{ *:[v2f32] } DPR:{ *:[v2i32] }:$Vm) => (VCVTu2fd:{ *:[v2f32] } DPR:{ *:[v2i32] }:$Vm) |
| 42400 | /* 118624 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTu2fd), |
| 42401 | /* 118627 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 42402 | /* 118629 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 42403 | /* 118631 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42404 | /* 118634 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42405 | /* 118640 */ GIR_RootConstrainSelectedInstOperands, |
| 42406 | /* 118641 */ // GIR_Coverage, 1607, |
| 42407 | /* 118641 */ GIR_EraseRootFromParent_Done, |
| 42408 | /* 118642 */ // Label 2291: @118642 |
| 42409 | /* 118642 */ GIM_Reject, |
| 42410 | /* 118643 */ // Label 2282: @118643 |
| 42411 | /* 118643 */ GIM_Try, /*On fail goto*//*Label 2292*/ GIMT_Encode4(118680), // Rule ID 1615 // |
| 42412 | /* 118648 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 42413 | /* 118651 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 42414 | /* 118654 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42415 | /* 118658 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42416 | /* 118662 */ // (uint_to_fp:{ *:[v4f16] } DPR:{ *:[v4i16] }:$Vm) => (VCVTu2hd:{ *:[v4f16] } DPR:{ *:[v4i16] }:$Vm) |
| 42417 | /* 118662 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTu2hd), |
| 42418 | /* 118665 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 42419 | /* 118667 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 42420 | /* 118669 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42421 | /* 118672 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42422 | /* 118678 */ GIR_RootConstrainSelectedInstOperands, |
| 42423 | /* 118679 */ // GIR_Coverage, 1615, |
| 42424 | /* 118679 */ GIR_EraseRootFromParent_Done, |
| 42425 | /* 118680 */ // Label 2292: @118680 |
| 42426 | /* 118680 */ GIM_Reject, |
| 42427 | /* 118681 */ // Label 2283: @118681 |
| 42428 | /* 118681 */ GIM_Try, /*On fail goto*//*Label 2293*/ GIMT_Encode4(118779), |
| 42429 | /* 118686 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 42430 | /* 118689 */ GIM_Try, /*On fail goto*//*Label 2294*/ GIMT_Encode4(118723), // Rule ID 1611 // |
| 42431 | /* 118694 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 42432 | /* 118697 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 42433 | /* 118701 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 42434 | /* 118705 */ // (uint_to_fp:{ *:[v4f32] } QPR:{ *:[v4i32] }:$Vm) => (VCVTu2fq:{ *:[v4f32] } QPR:{ *:[v4i32] }:$Vm) |
| 42435 | /* 118705 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTu2fq), |
| 42436 | /* 118708 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 42437 | /* 118710 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 42438 | /* 118712 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42439 | /* 118715 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42440 | /* 118721 */ GIR_RootConstrainSelectedInstOperands, |
| 42441 | /* 118722 */ // GIR_Coverage, 1611, |
| 42442 | /* 118722 */ GIR_EraseRootFromParent_Done, |
| 42443 | /* 118723 */ // Label 2294: @118723 |
| 42444 | /* 118723 */ GIM_Try, /*On fail goto*//*Label 2295*/ GIMT_Encode4(118778), // Rule ID 4104 // |
| 42445 | /* 118728 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 42446 | /* 118731 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42447 | /* 118735 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42448 | /* 118739 */ // (uint_to_fp:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$src) => (MVE_VCVTf32u32n:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$src) |
| 42449 | /* 118739 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 42450 | /* 118742 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 42451 | /* 118746 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 42452 | /* 118751 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf32u32n), |
| 42453 | /* 118754 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 42454 | /* 118756 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 42455 | /* 118758 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42456 | /* 118761 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42457 | /* 118767 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42458 | /* 118773 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 42459 | /* 118776 */ GIR_RootConstrainSelectedInstOperands, |
| 42460 | /* 118777 */ // GIR_Coverage, 4104, |
| 42461 | /* 118777 */ GIR_EraseRootFromParent_Done, |
| 42462 | /* 118778 */ // Label 2295: @118778 |
| 42463 | /* 118778 */ GIM_Reject, |
| 42464 | /* 118779 */ // Label 2293: @118779 |
| 42465 | /* 118779 */ GIM_Reject, |
| 42466 | /* 118780 */ // Label 2284: @118780 |
| 42467 | /* 118780 */ GIM_Try, /*On fail goto*//*Label 2296*/ GIMT_Encode4(118878), |
| 42468 | /* 118785 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 42469 | /* 118788 */ GIM_Try, /*On fail goto*//*Label 2297*/ GIMT_Encode4(118822), // Rule ID 1619 // |
| 42470 | /* 118793 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 42471 | /* 118796 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 42472 | /* 118800 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 42473 | /* 118804 */ // (uint_to_fp:{ *:[v8f16] } QPR:{ *:[v8i16] }:$Vm) => (VCVTu2hq:{ *:[v8f16] } QPR:{ *:[v8i16] }:$Vm) |
| 42474 | /* 118804 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTu2hq), |
| 42475 | /* 118807 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 42476 | /* 118809 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 42477 | /* 118811 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42478 | /* 118814 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42479 | /* 118820 */ GIR_RootConstrainSelectedInstOperands, |
| 42480 | /* 118821 */ // GIR_Coverage, 1619, |
| 42481 | /* 118821 */ GIR_EraseRootFromParent_Done, |
| 42482 | /* 118822 */ // Label 2297: @118822 |
| 42483 | /* 118822 */ GIM_Try, /*On fail goto*//*Label 2298*/ GIMT_Encode4(118877), // Rule ID 4100 // |
| 42484 | /* 118827 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 42485 | /* 118830 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42486 | /* 118834 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42487 | /* 118838 */ // (uint_to_fp:{ *:[v8f16] } MQPR:{ *:[v8i16] }:$src) => (MVE_VCVTf16u16n:{ *:[v8f16] } MQPR:{ *:[v8i16] }:$src) |
| 42488 | /* 118838 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 42489 | /* 118841 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 42490 | /* 118845 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 42491 | /* 118850 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf16u16n), |
| 42492 | /* 118853 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 42493 | /* 118855 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 42494 | /* 118857 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42495 | /* 118860 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42496 | /* 118866 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42497 | /* 118872 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 42498 | /* 118875 */ GIR_RootConstrainSelectedInstOperands, |
| 42499 | /* 118876 */ // GIR_Coverage, 4100, |
| 42500 | /* 118876 */ GIR_EraseRootFromParent_Done, |
| 42501 | /* 118877 */ // Label 2298: @118877 |
| 42502 | /* 118877 */ GIM_Reject, |
| 42503 | /* 118878 */ // Label 2296: @118878 |
| 42504 | /* 118878 */ GIM_Reject, |
| 42505 | /* 118879 */ // Label 2285: @118879 |
| 42506 | /* 118879 */ GIM_Reject, |
| 42507 | /* 118880 */ // Label 46: @118880 |
| 42508 | /* 118880 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 2306*/ GIMT_Encode4(119655), |
| 42509 | /* 118891 */ /*GILLT_s16*//*Label 2299*/ GIMT_Encode4(118943), |
| 42510 | /* 118895 */ /*GILLT_s32*//*Label 2300*/ GIMT_Encode4(118981), |
| 42511 | /* 118899 */ /*GILLT_s64*//*Label 2301*/ GIMT_Encode4(119173), GIMT_Encode4(0), |
| 42512 | /* 118907 */ /*GILLT_v2s32*//*Label 2302*/ GIMT_Encode4(119211), GIMT_Encode4(0), GIMT_Encode4(0), |
| 42513 | /* 118919 */ /*GILLT_v4s16*//*Label 2303*/ GIMT_Encode4(119249), |
| 42514 | /* 118923 */ /*GILLT_v4s32*//*Label 2304*/ GIMT_Encode4(119287), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 42515 | /* 118939 */ /*GILLT_v8s16*//*Label 2305*/ GIMT_Encode4(119471), |
| 42516 | /* 118943 */ // Label 2299: @118943 |
| 42517 | /* 118943 */ GIM_Try, /*On fail goto*//*Label 2307*/ GIMT_Encode4(118980), // Rule ID 653 // |
| 42518 | /* 118948 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 42519 | /* 118951 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 42520 | /* 118954 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 42521 | /* 118958 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 42522 | /* 118962 */ // (fabs:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VABSH:{ *:[f16] } HPR:{ *:[f16] }:$Sm) |
| 42523 | /* 118962 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABSH), |
| 42524 | /* 118965 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 42525 | /* 118967 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm |
| 42526 | /* 118969 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42527 | /* 118972 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42528 | /* 118978 */ GIR_RootConstrainSelectedInstOperands, |
| 42529 | /* 118979 */ // GIR_Coverage, 653, |
| 42530 | /* 118979 */ GIR_EraseRootFromParent_Done, |
| 42531 | /* 118980 */ // Label 2307: @118980 |
| 42532 | /* 118980 */ GIM_Reject, |
| 42533 | /* 118981 */ // Label 2300: @118981 |
| 42534 | /* 118981 */ GIM_Try, /*On fail goto*//*Label 2308*/ GIMT_Encode4(119172), |
| 42535 | /* 118986 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 42536 | /* 118989 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 42537 | /* 118993 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 42538 | /* 118997 */ GIM_Try, /*On fail goto*//*Label 2309*/ GIMT_Encode4(119023), // Rule ID 652 // |
| 42539 | /* 119002 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), |
| 42540 | /* 119005 */ // (fabs:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VABSS:{ *:[f32] } SPR:{ *:[f32] }:$Sm) |
| 42541 | /* 119005 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABSS), |
| 42542 | /* 119008 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 42543 | /* 119010 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm |
| 42544 | /* 119012 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42545 | /* 119015 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42546 | /* 119021 */ GIR_RootConstrainSelectedInstOperands, |
| 42547 | /* 119022 */ // GIR_Coverage, 652, |
| 42548 | /* 119022 */ GIR_EraseRootFromParent_Done, |
| 42549 | /* 119023 */ // Label 2309: @119023 |
| 42550 | /* 119023 */ GIM_Try, /*On fail goto*//*Label 2310*/ GIMT_Encode4(119171), // Rule ID 2704 // |
| 42551 | /* 119028 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_UseNEONForFP), |
| 42552 | /* 119031 */ // (fabs:{ *:[f32] } SPR:{ *:[f32] }:$a) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VABSfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] }) |
| 42553 | /* 119031 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32, |
| 42554 | /* 119034 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 42555 | /* 119038 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 42556 | /* 119043 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 42557 | /* 119045 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32, |
| 42558 | /* 119048 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 42559 | /* 119052 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 42560 | /* 119057 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4, |
| 42561 | /* 119060 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 42562 | /* 119065 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32, |
| 42563 | /* 119068 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 42564 | /* 119072 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 42565 | /* 119077 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3, |
| 42566 | /* 119080 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 42567 | /* 119084 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17, |
| 42568 | /* 119087 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 42569 | /* 119092 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 42570 | /* 119097 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 42571 | /* 119102 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 42572 | /* 119105 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VABSfd), |
| 42573 | /* 119109 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 42574 | /* 119114 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 42575 | /* 119117 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14, |
| 42576 | /* 119120 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42577 | /* 119126 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 42578 | /* 119128 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32, |
| 42579 | /* 119131 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 42580 | /* 119135 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 42581 | /* 119140 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 42582 | /* 119143 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 42583 | /* 119148 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 42584 | /* 119151 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 42585 | /* 119153 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0), |
| 42586 | /* 119160 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 42587 | /* 119165 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 42588 | /* 119170 */ // GIR_Coverage, 2704, |
| 42589 | /* 119170 */ GIR_EraseRootFromParent_Done, |
| 42590 | /* 119171 */ // Label 2310: @119171 |
| 42591 | /* 119171 */ GIM_Reject, |
| 42592 | /* 119172 */ // Label 2308: @119172 |
| 42593 | /* 119172 */ GIM_Reject, |
| 42594 | /* 119173 */ // Label 2301: @119173 |
| 42595 | /* 119173 */ GIM_Try, /*On fail goto*//*Label 2311*/ GIMT_Encode4(119210), // Rule ID 651 // |
| 42596 | /* 119178 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), |
| 42597 | /* 119181 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 42598 | /* 119184 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42599 | /* 119188 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42600 | /* 119192 */ // (fabs:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VABSD:{ *:[f64] } DPR:{ *:[f64] }:$Dm) |
| 42601 | /* 119192 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABSD), |
| 42602 | /* 119195 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 42603 | /* 119197 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dm |
| 42604 | /* 119199 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42605 | /* 119202 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42606 | /* 119208 */ GIR_RootConstrainSelectedInstOperands, |
| 42607 | /* 119209 */ // GIR_Coverage, 651, |
| 42608 | /* 119209 */ GIR_EraseRootFromParent_Done, |
| 42609 | /* 119210 */ // Label 2311: @119210 |
| 42610 | /* 119210 */ GIM_Reject, |
| 42611 | /* 119211 */ // Label 2302: @119211 |
| 42612 | /* 119211 */ GIM_Try, /*On fail goto*//*Label 2312*/ GIMT_Encode4(119248), // Rule ID 1514 // |
| 42613 | /* 119216 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 42614 | /* 119219 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 42615 | /* 119222 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42616 | /* 119226 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42617 | /* 119230 */ // (fabs:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) => (VABSfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) |
| 42618 | /* 119230 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABSfd), |
| 42619 | /* 119233 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 42620 | /* 119235 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 42621 | /* 119237 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42622 | /* 119240 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42623 | /* 119246 */ GIR_RootConstrainSelectedInstOperands, |
| 42624 | /* 119247 */ // GIR_Coverage, 1514, |
| 42625 | /* 119247 */ GIR_EraseRootFromParent_Done, |
| 42626 | /* 119248 */ // Label 2312: @119248 |
| 42627 | /* 119248 */ GIM_Reject, |
| 42628 | /* 119249 */ // Label 2303: @119249 |
| 42629 | /* 119249 */ GIM_Try, /*On fail goto*//*Label 2313*/ GIMT_Encode4(119286), // Rule ID 1516 // |
| 42630 | /* 119254 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 42631 | /* 119257 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 42632 | /* 119260 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42633 | /* 119264 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42634 | /* 119268 */ // (fabs:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) => (VABShd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) |
| 42635 | /* 119268 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABShd), |
| 42636 | /* 119271 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 42637 | /* 119273 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 42638 | /* 119275 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42639 | /* 119278 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42640 | /* 119284 */ GIR_RootConstrainSelectedInstOperands, |
| 42641 | /* 119285 */ // GIR_Coverage, 1516, |
| 42642 | /* 119285 */ GIR_EraseRootFromParent_Done, |
| 42643 | /* 119286 */ // Label 2313: @119286 |
| 42644 | /* 119286 */ GIM_Reject, |
| 42645 | /* 119287 */ // Label 2304: @119287 |
| 42646 | /* 119287 */ GIM_Try, /*On fail goto*//*Label 2314*/ GIMT_Encode4(119470), |
| 42647 | /* 119292 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 42648 | /* 119295 */ GIM_Try, /*On fail goto*//*Label 2315*/ GIMT_Encode4(119380), // Rule ID 4041 // |
| 42649 | /* 119300 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 42650 | /* 119303 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42651 | /* 119307 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 42652 | /* 119311 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FSUB), |
| 42653 | /* 119315 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 42654 | /* 119319 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 42655 | /* 119323 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42656 | /* 119328 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42657 | /* 119333 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 42658 | /* 119335 */ // (fabs:{ *:[v4f32] } (fsub:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn)) => (MVE_VABDf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) |
| 42659 | /* 119335 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 42660 | /* 119338 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 42661 | /* 119342 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 42662 | /* 119347 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDf32), |
| 42663 | /* 119350 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 42664 | /* 119352 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm |
| 42665 | /* 119356 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Qn |
| 42666 | /* 119360 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42667 | /* 119363 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42668 | /* 119369 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42669 | /* 119375 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 42670 | /* 119378 */ GIR_RootConstrainSelectedInstOperands, |
| 42671 | /* 119379 */ // GIR_Coverage, 4041, |
| 42672 | /* 119379 */ GIR_EraseRootFromParent_Done, |
| 42673 | /* 119380 */ // Label 2315: @119380 |
| 42674 | /* 119380 */ GIM_Try, /*On fail goto*//*Label 2316*/ GIMT_Encode4(119414), // Rule ID 1515 // |
| 42675 | /* 119385 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 42676 | /* 119388 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 42677 | /* 119392 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 42678 | /* 119396 */ // (fabs:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) => (VABSfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) |
| 42679 | /* 119396 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABSfq), |
| 42680 | /* 119399 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 42681 | /* 119401 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 42682 | /* 119403 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42683 | /* 119406 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42684 | /* 119412 */ GIR_RootConstrainSelectedInstOperands, |
| 42685 | /* 119413 */ // GIR_Coverage, 1515, |
| 42686 | /* 119413 */ GIR_EraseRootFromParent_Done, |
| 42687 | /* 119414 */ // Label 2316: @119414 |
| 42688 | /* 119414 */ GIM_Try, /*On fail goto*//*Label 2317*/ GIMT_Encode4(119469), // Rule ID 4112 // |
| 42689 | /* 119419 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 42690 | /* 119422 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42691 | /* 119426 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42692 | /* 119430 */ // (fabs:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$v) => (MVE_VABSf32:{ *:[v4f32] } ?:{ *:[v4f32] }:$v) |
| 42693 | /* 119430 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 42694 | /* 119433 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 42695 | /* 119437 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 42696 | /* 119442 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABSf32), |
| 42697 | /* 119445 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 42698 | /* 119447 */ GIR_RootToRootCopy, /*OpIdx*/1, // v |
| 42699 | /* 119449 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42700 | /* 119452 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42701 | /* 119458 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42702 | /* 119464 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 42703 | /* 119467 */ GIR_RootConstrainSelectedInstOperands, |
| 42704 | /* 119468 */ // GIR_Coverage, 4112, |
| 42705 | /* 119468 */ GIR_EraseRootFromParent_Done, |
| 42706 | /* 119469 */ // Label 2317: @119469 |
| 42707 | /* 119469 */ GIM_Reject, |
| 42708 | /* 119470 */ // Label 2314: @119470 |
| 42709 | /* 119470 */ GIM_Reject, |
| 42710 | /* 119471 */ // Label 2305: @119471 |
| 42711 | /* 119471 */ GIM_Try, /*On fail goto*//*Label 2318*/ GIMT_Encode4(119654), |
| 42712 | /* 119476 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 42713 | /* 119479 */ GIM_Try, /*On fail goto*//*Label 2319*/ GIMT_Encode4(119564), // Rule ID 4040 // |
| 42714 | /* 119484 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 42715 | /* 119487 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42716 | /* 119491 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 42717 | /* 119495 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FSUB), |
| 42718 | /* 119499 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 42719 | /* 119503 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 42720 | /* 119507 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42721 | /* 119512 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42722 | /* 119517 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 42723 | /* 119519 */ // (fabs:{ *:[v8f16] } (fsub:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn)) => (MVE_VABDf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) |
| 42724 | /* 119519 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 42725 | /* 119522 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 42726 | /* 119526 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 42727 | /* 119531 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDf16), |
| 42728 | /* 119534 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 42729 | /* 119536 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm |
| 42730 | /* 119540 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Qn |
| 42731 | /* 119544 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42732 | /* 119547 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42733 | /* 119553 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42734 | /* 119559 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 42735 | /* 119562 */ GIR_RootConstrainSelectedInstOperands, |
| 42736 | /* 119563 */ // GIR_Coverage, 4040, |
| 42737 | /* 119563 */ GIR_EraseRootFromParent_Done, |
| 42738 | /* 119564 */ // Label 2319: @119564 |
| 42739 | /* 119564 */ GIM_Try, /*On fail goto*//*Label 2320*/ GIMT_Encode4(119598), // Rule ID 1517 // |
| 42740 | /* 119569 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 42741 | /* 119572 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 42742 | /* 119576 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 42743 | /* 119580 */ // (fabs:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) => (VABShq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) |
| 42744 | /* 119580 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABShq), |
| 42745 | /* 119583 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 42746 | /* 119585 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 42747 | /* 119587 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42748 | /* 119590 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42749 | /* 119596 */ GIR_RootConstrainSelectedInstOperands, |
| 42750 | /* 119597 */ // GIR_Coverage, 1517, |
| 42751 | /* 119597 */ GIR_EraseRootFromParent_Done, |
| 42752 | /* 119598 */ // Label 2320: @119598 |
| 42753 | /* 119598 */ GIM_Try, /*On fail goto*//*Label 2321*/ GIMT_Encode4(119653), // Rule ID 4110 // |
| 42754 | /* 119603 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 42755 | /* 119606 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42756 | /* 119610 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42757 | /* 119614 */ // (fabs:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$v) => (MVE_VABSf16:{ *:[v8f16] } ?:{ *:[v8f16] }:$v) |
| 42758 | /* 119614 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 42759 | /* 119617 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 42760 | /* 119621 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 42761 | /* 119626 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABSf16), |
| 42762 | /* 119629 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 42763 | /* 119631 */ GIR_RootToRootCopy, /*OpIdx*/1, // v |
| 42764 | /* 119633 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42765 | /* 119636 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42766 | /* 119642 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42767 | /* 119648 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 42768 | /* 119651 */ GIR_RootConstrainSelectedInstOperands, |
| 42769 | /* 119652 */ // GIR_Coverage, 4110, |
| 42770 | /* 119652 */ GIR_EraseRootFromParent_Done, |
| 42771 | /* 119653 */ // Label 2321: @119653 |
| 42772 | /* 119653 */ GIM_Reject, |
| 42773 | /* 119654 */ // Label 2318: @119654 |
| 42774 | /* 119654 */ GIM_Reject, |
| 42775 | /* 119655 */ // Label 2306: @119655 |
| 42776 | /* 119655 */ GIM_Reject, |
| 42777 | /* 119656 */ // Label 47: @119656 |
| 42778 | /* 119656 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 2329*/ GIMT_Encode4(120247), |
| 42779 | /* 119667 */ /*GILLT_s16*//*Label 2322*/ GIMT_Encode4(119719), |
| 42780 | /* 119671 */ /*GILLT_s32*//*Label 2323*/ GIMT_Encode4(119753), |
| 42781 | /* 119675 */ /*GILLT_s64*//*Label 2324*/ GIMT_Encode4(119787), GIMT_Encode4(0), |
| 42782 | /* 119683 */ /*GILLT_v2s32*//*Label 2325*/ GIMT_Encode4(119821), GIMT_Encode4(0), GIMT_Encode4(0), |
| 42783 | /* 119695 */ /*GILLT_v4s16*//*Label 2326*/ GIMT_Encode4(119855), |
| 42784 | /* 119699 */ /*GILLT_v4s32*//*Label 2327*/ GIMT_Encode4(119889), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 42785 | /* 119715 */ /*GILLT_v8s16*//*Label 2328*/ GIMT_Encode4(120068), |
| 42786 | /* 119719 */ // Label 2322: @119719 |
| 42787 | /* 119719 */ GIM_Try, /*On fail goto*//*Label 2330*/ GIMT_Encode4(119752), // Rule ID 642 // |
| 42788 | /* 119724 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 42789 | /* 119727 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 42790 | /* 119730 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 42791 | /* 119733 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 42792 | /* 119737 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 42793 | /* 119741 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 42794 | /* 119745 */ // (fminnum:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) => (VFP_VMINNMH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 42795 | /* 119745 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VFP_VMINNMH), |
| 42796 | /* 119750 */ GIR_RootConstrainSelectedInstOperands, |
| 42797 | /* 119751 */ // GIR_Coverage, 642, |
| 42798 | /* 119751 */ GIR_Done, |
| 42799 | /* 119752 */ // Label 2330: @119752 |
| 42800 | /* 119752 */ GIM_Reject, |
| 42801 | /* 119753 */ // Label 2323: @119753 |
| 42802 | /* 119753 */ GIM_Try, /*On fail goto*//*Label 2331*/ GIMT_Encode4(119786), // Rule ID 643 // |
| 42803 | /* 119758 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8), |
| 42804 | /* 119761 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 42805 | /* 119764 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 42806 | /* 119767 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 42807 | /* 119771 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 42808 | /* 119775 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 42809 | /* 119779 */ // (fminnum:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) => (VFP_VMINNMS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 42810 | /* 119779 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VFP_VMINNMS), |
| 42811 | /* 119784 */ GIR_RootConstrainSelectedInstOperands, |
| 42812 | /* 119785 */ // GIR_Coverage, 643, |
| 42813 | /* 119785 */ GIR_Done, |
| 42814 | /* 119786 */ // Label 2331: @119786 |
| 42815 | /* 119786 */ GIM_Reject, |
| 42816 | /* 119787 */ // Label 2324: @119787 |
| 42817 | /* 119787 */ GIM_Try, /*On fail goto*//*Label 2332*/ GIMT_Encode4(119820), // Rule ID 644 // |
| 42818 | /* 119792 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), |
| 42819 | /* 119795 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 42820 | /* 119798 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 42821 | /* 119801 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42822 | /* 119805 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42823 | /* 119809 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42824 | /* 119813 */ // (fminnum:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) => (VFP_VMINNMD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 42825 | /* 119813 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VFP_VMINNMD), |
| 42826 | /* 119818 */ GIR_RootConstrainSelectedInstOperands, |
| 42827 | /* 119819 */ // GIR_Coverage, 644, |
| 42828 | /* 119819 */ GIR_Done, |
| 42829 | /* 119820 */ // Label 2332: @119820 |
| 42830 | /* 119820 */ GIM_Reject, |
| 42831 | /* 119821 */ // Label 2325: @119821 |
| 42832 | /* 119821 */ GIM_Try, /*On fail goto*//*Label 2333*/ GIMT_Encode4(119854), // Rule ID 1233 // |
| 42833 | /* 119826 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8_HasNEON), |
| 42834 | /* 119829 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 42835 | /* 119832 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 42836 | /* 119835 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42837 | /* 119839 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42838 | /* 119843 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42839 | /* 119847 */ // (fminnum:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (NEON_VMINNMNDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) |
| 42840 | /* 119847 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::NEON_VMINNMNDf), |
| 42841 | /* 119852 */ GIR_RootConstrainSelectedInstOperands, |
| 42842 | /* 119853 */ // GIR_Coverage, 1233, |
| 42843 | /* 119853 */ GIR_Done, |
| 42844 | /* 119854 */ // Label 2333: @119854 |
| 42845 | /* 119854 */ GIM_Reject, |
| 42846 | /* 119855 */ // Label 2326: @119855 |
| 42847 | /* 119855 */ GIM_Try, /*On fail goto*//*Label 2334*/ GIMT_Encode4(119888), // Rule ID 1235 // |
| 42848 | /* 119860 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8_HasFullFP16_HasNEON), |
| 42849 | /* 119863 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 42850 | /* 119866 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 42851 | /* 119869 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42852 | /* 119873 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42853 | /* 119877 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42854 | /* 119881 */ // (fminnum:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (NEON_VMINNMNDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) |
| 42855 | /* 119881 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::NEON_VMINNMNDh), |
| 42856 | /* 119886 */ GIR_RootConstrainSelectedInstOperands, |
| 42857 | /* 119887 */ // GIR_Coverage, 1235, |
| 42858 | /* 119887 */ GIR_Done, |
| 42859 | /* 119888 */ // Label 2334: @119888 |
| 42860 | /* 119888 */ GIM_Reject, |
| 42861 | /* 119889 */ // Label 2327: @119889 |
| 42862 | /* 119889 */ GIM_Try, /*On fail goto*//*Label 2335*/ GIMT_Encode4(120067), |
| 42863 | /* 119894 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 42864 | /* 119897 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 42865 | /* 119900 */ GIM_Try, /*On fail goto*//*Label 2336*/ GIMT_Encode4(119978), // Rule ID 4122 // |
| 42866 | /* 119905 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 42867 | /* 119908 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42868 | /* 119912 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 42869 | /* 119916 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS), |
| 42870 | /* 119920 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 42871 | /* 119924 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42872 | /* 119929 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 42873 | /* 119933 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS), |
| 42874 | /* 119937 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, |
| 42875 | /* 119941 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42876 | /* 119946 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 42877 | /* 119948 */ // (fminnum:{ *:[v4f32] } (fabs:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qd), (fabs:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm)) => (MVE_VMINNMAf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qd, MQPR:{ *:[v4f32] }:$Qm) |
| 42878 | /* 119948 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINNMAf32), |
| 42879 | /* 119951 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 42880 | /* 119953 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qd |
| 42881 | /* 119957 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Qm |
| 42882 | /* 119961 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42883 | /* 119964 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42884 | /* 119970 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42885 | /* 119976 */ GIR_RootConstrainSelectedInstOperands, |
| 42886 | /* 119977 */ // GIR_Coverage, 4122, |
| 42887 | /* 119977 */ GIR_EraseRootFromParent_Done, |
| 42888 | /* 119978 */ // Label 2336: @119978 |
| 42889 | /* 119978 */ GIM_Try, /*On fail goto*//*Label 2337*/ GIMT_Encode4(120005), // Rule ID 1234 // |
| 42890 | /* 119983 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8_HasNEON), |
| 42891 | /* 119986 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 42892 | /* 119990 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 42893 | /* 119994 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 42894 | /* 119998 */ // (fminnum:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (NEON_VMINNMNQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) |
| 42895 | /* 119998 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::NEON_VMINNMNQf), |
| 42896 | /* 120003 */ GIR_RootConstrainSelectedInstOperands, |
| 42897 | /* 120004 */ // GIR_Coverage, 1234, |
| 42898 | /* 120004 */ GIR_Done, |
| 42899 | /* 120005 */ // Label 2337: @120005 |
| 42900 | /* 120005 */ GIM_Try, /*On fail goto*//*Label 2338*/ GIMT_Encode4(120066), // Rule ID 3288 // |
| 42901 | /* 120010 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 42902 | /* 120013 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42903 | /* 120017 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42904 | /* 120021 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42905 | /* 120025 */ // (fminnum:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) => (MVE_VMINNMf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) |
| 42906 | /* 120025 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 42907 | /* 120028 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 42908 | /* 120032 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 42909 | /* 120037 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINNMf32), |
| 42910 | /* 120040 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 42911 | /* 120042 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 42912 | /* 120044 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 42913 | /* 120046 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42914 | /* 120049 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42915 | /* 120055 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42916 | /* 120061 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 42917 | /* 120064 */ GIR_RootConstrainSelectedInstOperands, |
| 42918 | /* 120065 */ // GIR_Coverage, 3288, |
| 42919 | /* 120065 */ GIR_EraseRootFromParent_Done, |
| 42920 | /* 120066 */ // Label 2338: @120066 |
| 42921 | /* 120066 */ GIM_Reject, |
| 42922 | /* 120067 */ // Label 2335: @120067 |
| 42923 | /* 120067 */ GIM_Reject, |
| 42924 | /* 120068 */ // Label 2328: @120068 |
| 42925 | /* 120068 */ GIM_Try, /*On fail goto*//*Label 2339*/ GIMT_Encode4(120246), |
| 42926 | /* 120073 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 42927 | /* 120076 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 42928 | /* 120079 */ GIM_Try, /*On fail goto*//*Label 2340*/ GIMT_Encode4(120157), // Rule ID 4124 // |
| 42929 | /* 120084 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 42930 | /* 120087 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42931 | /* 120091 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 42932 | /* 120095 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS), |
| 42933 | /* 120099 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 42934 | /* 120103 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42935 | /* 120108 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 42936 | /* 120112 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS), |
| 42937 | /* 120116 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, |
| 42938 | /* 120120 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42939 | /* 120125 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 42940 | /* 120127 */ // (fminnum:{ *:[v8f16] } (fabs:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd), (fabs:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm)) => (MVE_VMINNMAf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd, MQPR:{ *:[v8f16] }:$Qm) |
| 42941 | /* 120127 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINNMAf16), |
| 42942 | /* 120130 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 42943 | /* 120132 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qd |
| 42944 | /* 120136 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Qm |
| 42945 | /* 120140 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42946 | /* 120143 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42947 | /* 120149 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42948 | /* 120155 */ GIR_RootConstrainSelectedInstOperands, |
| 42949 | /* 120156 */ // GIR_Coverage, 4124, |
| 42950 | /* 120156 */ GIR_EraseRootFromParent_Done, |
| 42951 | /* 120157 */ // Label 2340: @120157 |
| 42952 | /* 120157 */ GIM_Try, /*On fail goto*//*Label 2341*/ GIMT_Encode4(120184), // Rule ID 1236 // |
| 42953 | /* 120162 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8_HasFullFP16_HasNEON), |
| 42954 | /* 120165 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 42955 | /* 120169 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 42956 | /* 120173 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 42957 | /* 120177 */ // (fminnum:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (NEON_VMINNMNQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) |
| 42958 | /* 120177 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::NEON_VMINNMNQh), |
| 42959 | /* 120182 */ GIR_RootConstrainSelectedInstOperands, |
| 42960 | /* 120183 */ // GIR_Coverage, 1236, |
| 42961 | /* 120183 */ GIR_Done, |
| 42962 | /* 120184 */ // Label 2341: @120184 |
| 42963 | /* 120184 */ GIM_Try, /*On fail goto*//*Label 2342*/ GIMT_Encode4(120245), // Rule ID 3291 // |
| 42964 | /* 120189 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 42965 | /* 120192 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42966 | /* 120196 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42967 | /* 120200 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42968 | /* 120204 */ // (fminnum:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) => (MVE_VMINNMf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) |
| 42969 | /* 120204 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 42970 | /* 120207 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 42971 | /* 120211 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 42972 | /* 120216 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINNMf16), |
| 42973 | /* 120219 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 42974 | /* 120221 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 42975 | /* 120223 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 42976 | /* 120225 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42977 | /* 120228 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42978 | /* 120234 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42979 | /* 120240 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 42980 | /* 120243 */ GIR_RootConstrainSelectedInstOperands, |
| 42981 | /* 120244 */ // GIR_Coverage, 3291, |
| 42982 | /* 120244 */ GIR_EraseRootFromParent_Done, |
| 42983 | /* 120245 */ // Label 2342: @120245 |
| 42984 | /* 120245 */ GIM_Reject, |
| 42985 | /* 120246 */ // Label 2339: @120246 |
| 42986 | /* 120246 */ GIM_Reject, |
| 42987 | /* 120247 */ // Label 2329: @120247 |
| 42988 | /* 120247 */ GIM_Reject, |
| 42989 | /* 120248 */ // Label 48: @120248 |
| 42990 | /* 120248 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 2350*/ GIMT_Encode4(120839), |
| 42991 | /* 120259 */ /*GILLT_s16*//*Label 2343*/ GIMT_Encode4(120311), |
| 42992 | /* 120263 */ /*GILLT_s32*//*Label 2344*/ GIMT_Encode4(120345), |
| 42993 | /* 120267 */ /*GILLT_s64*//*Label 2345*/ GIMT_Encode4(120379), GIMT_Encode4(0), |
| 42994 | /* 120275 */ /*GILLT_v2s32*//*Label 2346*/ GIMT_Encode4(120413), GIMT_Encode4(0), GIMT_Encode4(0), |
| 42995 | /* 120287 */ /*GILLT_v4s16*//*Label 2347*/ GIMT_Encode4(120447), |
| 42996 | /* 120291 */ /*GILLT_v4s32*//*Label 2348*/ GIMT_Encode4(120481), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 42997 | /* 120307 */ /*GILLT_v8s16*//*Label 2349*/ GIMT_Encode4(120660), |
| 42998 | /* 120311 */ // Label 2343: @120311 |
| 42999 | /* 120311 */ GIM_Try, /*On fail goto*//*Label 2351*/ GIMT_Encode4(120344), // Rule ID 639 // |
| 43000 | /* 120316 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 43001 | /* 120319 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 43002 | /* 120322 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 43003 | /* 120325 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 43004 | /* 120329 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 43005 | /* 120333 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 43006 | /* 120337 */ // (fmaxnum:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) => (VFP_VMAXNMH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 43007 | /* 120337 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VFP_VMAXNMH), |
| 43008 | /* 120342 */ GIR_RootConstrainSelectedInstOperands, |
| 43009 | /* 120343 */ // GIR_Coverage, 639, |
| 43010 | /* 120343 */ GIR_Done, |
| 43011 | /* 120344 */ // Label 2351: @120344 |
| 43012 | /* 120344 */ GIM_Reject, |
| 43013 | /* 120345 */ // Label 2344: @120345 |
| 43014 | /* 120345 */ GIM_Try, /*On fail goto*//*Label 2352*/ GIMT_Encode4(120378), // Rule ID 640 // |
| 43015 | /* 120350 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8), |
| 43016 | /* 120353 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 43017 | /* 120356 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 43018 | /* 120359 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 43019 | /* 120363 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 43020 | /* 120367 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 43021 | /* 120371 */ // (fmaxnum:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) => (VFP_VMAXNMS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 43022 | /* 120371 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VFP_VMAXNMS), |
| 43023 | /* 120376 */ GIR_RootConstrainSelectedInstOperands, |
| 43024 | /* 120377 */ // GIR_Coverage, 640, |
| 43025 | /* 120377 */ GIR_Done, |
| 43026 | /* 120378 */ // Label 2352: @120378 |
| 43027 | /* 120378 */ GIM_Reject, |
| 43028 | /* 120379 */ // Label 2345: @120379 |
| 43029 | /* 120379 */ GIM_Try, /*On fail goto*//*Label 2353*/ GIMT_Encode4(120412), // Rule ID 641 // |
| 43030 | /* 120384 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), |
| 43031 | /* 120387 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 43032 | /* 120390 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 43033 | /* 120393 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43034 | /* 120397 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43035 | /* 120401 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43036 | /* 120405 */ // (fmaxnum:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) => (VFP_VMAXNMD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 43037 | /* 120405 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VFP_VMAXNMD), |
| 43038 | /* 120410 */ GIR_RootConstrainSelectedInstOperands, |
| 43039 | /* 120411 */ // GIR_Coverage, 641, |
| 43040 | /* 120411 */ GIR_Done, |
| 43041 | /* 120412 */ // Label 2353: @120412 |
| 43042 | /* 120412 */ GIM_Reject, |
| 43043 | /* 120413 */ // Label 2346: @120413 |
| 43044 | /* 120413 */ GIM_Try, /*On fail goto*//*Label 2354*/ GIMT_Encode4(120446), // Rule ID 1213 // |
| 43045 | /* 120418 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8_HasNEON), |
| 43046 | /* 120421 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 43047 | /* 120424 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 43048 | /* 120427 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43049 | /* 120431 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43050 | /* 120435 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43051 | /* 120439 */ // (fmaxnum:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (NEON_VMAXNMNDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) |
| 43052 | /* 120439 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::NEON_VMAXNMNDf), |
| 43053 | /* 120444 */ GIR_RootConstrainSelectedInstOperands, |
| 43054 | /* 120445 */ // GIR_Coverage, 1213, |
| 43055 | /* 120445 */ GIR_Done, |
| 43056 | /* 120446 */ // Label 2354: @120446 |
| 43057 | /* 120446 */ GIM_Reject, |
| 43058 | /* 120447 */ // Label 2347: @120447 |
| 43059 | /* 120447 */ GIM_Try, /*On fail goto*//*Label 2355*/ GIMT_Encode4(120480), // Rule ID 1215 // |
| 43060 | /* 120452 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8_HasFullFP16_HasNEON), |
| 43061 | /* 120455 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 43062 | /* 120458 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 43063 | /* 120461 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43064 | /* 120465 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43065 | /* 120469 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43066 | /* 120473 */ // (fmaxnum:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (NEON_VMAXNMNDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) |
| 43067 | /* 120473 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::NEON_VMAXNMNDh), |
| 43068 | /* 120478 */ GIR_RootConstrainSelectedInstOperands, |
| 43069 | /* 120479 */ // GIR_Coverage, 1215, |
| 43070 | /* 120479 */ GIR_Done, |
| 43071 | /* 120480 */ // Label 2355: @120480 |
| 43072 | /* 120480 */ GIM_Reject, |
| 43073 | /* 120481 */ // Label 2348: @120481 |
| 43074 | /* 120481 */ GIM_Try, /*On fail goto*//*Label 2356*/ GIMT_Encode4(120659), |
| 43075 | /* 120486 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 43076 | /* 120489 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 43077 | /* 120492 */ GIM_Try, /*On fail goto*//*Label 2357*/ GIMT_Encode4(120570), // Rule ID 4118 // |
| 43078 | /* 120497 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 43079 | /* 120500 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43080 | /* 120504 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 43081 | /* 120508 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS), |
| 43082 | /* 120512 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 43083 | /* 120516 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43084 | /* 120521 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 43085 | /* 120525 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS), |
| 43086 | /* 120529 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, |
| 43087 | /* 120533 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43088 | /* 120538 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 43089 | /* 120540 */ // (fmaxnum:{ *:[v4f32] } (fabs:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qd), (fabs:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm)) => (MVE_VMAXNMAf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qd, MQPR:{ *:[v4f32] }:$Qm) |
| 43090 | /* 120540 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXNMAf32), |
| 43091 | /* 120543 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 43092 | /* 120545 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qd |
| 43093 | /* 120549 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Qm |
| 43094 | /* 120553 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43095 | /* 120556 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43096 | /* 120562 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43097 | /* 120568 */ GIR_RootConstrainSelectedInstOperands, |
| 43098 | /* 120569 */ // GIR_Coverage, 4118, |
| 43099 | /* 120569 */ GIR_EraseRootFromParent_Done, |
| 43100 | /* 120570 */ // Label 2357: @120570 |
| 43101 | /* 120570 */ GIM_Try, /*On fail goto*//*Label 2358*/ GIMT_Encode4(120597), // Rule ID 1214 // |
| 43102 | /* 120575 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8_HasNEON), |
| 43103 | /* 120578 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43104 | /* 120582 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43105 | /* 120586 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43106 | /* 120590 */ // (fmaxnum:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (NEON_VMAXNMNQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) |
| 43107 | /* 120590 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::NEON_VMAXNMNQf), |
| 43108 | /* 120595 */ GIR_RootConstrainSelectedInstOperands, |
| 43109 | /* 120596 */ // GIR_Coverage, 1214, |
| 43110 | /* 120596 */ GIR_Done, |
| 43111 | /* 120597 */ // Label 2358: @120597 |
| 43112 | /* 120597 */ GIM_Try, /*On fail goto*//*Label 2359*/ GIMT_Encode4(120658), // Rule ID 3030 // |
| 43113 | /* 120602 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 43114 | /* 120605 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43115 | /* 120609 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43116 | /* 120613 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43117 | /* 120617 */ // (fmaxnum:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) => (MVE_VMAXNMf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) |
| 43118 | /* 120617 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 43119 | /* 120620 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 43120 | /* 120624 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 43121 | /* 120629 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXNMf32), |
| 43122 | /* 120632 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 43123 | /* 120634 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 43124 | /* 120636 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 43125 | /* 120638 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43126 | /* 120641 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43127 | /* 120647 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43128 | /* 120653 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 43129 | /* 120656 */ GIR_RootConstrainSelectedInstOperands, |
| 43130 | /* 120657 */ // GIR_Coverage, 3030, |
| 43131 | /* 120657 */ GIR_EraseRootFromParent_Done, |
| 43132 | /* 120658 */ // Label 2359: @120658 |
| 43133 | /* 120658 */ GIM_Reject, |
| 43134 | /* 120659 */ // Label 2356: @120659 |
| 43135 | /* 120659 */ GIM_Reject, |
| 43136 | /* 120660 */ // Label 2349: @120660 |
| 43137 | /* 120660 */ GIM_Try, /*On fail goto*//*Label 2360*/ GIMT_Encode4(120838), |
| 43138 | /* 120665 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 43139 | /* 120668 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 43140 | /* 120671 */ GIM_Try, /*On fail goto*//*Label 2361*/ GIMT_Encode4(120749), // Rule ID 4120 // |
| 43141 | /* 120676 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 43142 | /* 120679 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43143 | /* 120683 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 43144 | /* 120687 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS), |
| 43145 | /* 120691 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 43146 | /* 120695 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43147 | /* 120700 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 43148 | /* 120704 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS), |
| 43149 | /* 120708 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, |
| 43150 | /* 120712 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43151 | /* 120717 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 43152 | /* 120719 */ // (fmaxnum:{ *:[v8f16] } (fabs:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd), (fabs:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm)) => (MVE_VMAXNMAf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd, MQPR:{ *:[v8f16] }:$Qm) |
| 43153 | /* 120719 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXNMAf16), |
| 43154 | /* 120722 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 43155 | /* 120724 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qd |
| 43156 | /* 120728 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Qm |
| 43157 | /* 120732 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43158 | /* 120735 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43159 | /* 120741 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43160 | /* 120747 */ GIR_RootConstrainSelectedInstOperands, |
| 43161 | /* 120748 */ // GIR_Coverage, 4120, |
| 43162 | /* 120748 */ GIR_EraseRootFromParent_Done, |
| 43163 | /* 120749 */ // Label 2361: @120749 |
| 43164 | /* 120749 */ GIM_Try, /*On fail goto*//*Label 2362*/ GIMT_Encode4(120776), // Rule ID 1216 // |
| 43165 | /* 120754 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8_HasFullFP16_HasNEON), |
| 43166 | /* 120757 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43167 | /* 120761 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43168 | /* 120765 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43169 | /* 120769 */ // (fmaxnum:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (NEON_VMAXNMNQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) |
| 43170 | /* 120769 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::NEON_VMAXNMNQh), |
| 43171 | /* 120774 */ GIR_RootConstrainSelectedInstOperands, |
| 43172 | /* 120775 */ // GIR_Coverage, 1216, |
| 43173 | /* 120775 */ GIR_Done, |
| 43174 | /* 120776 */ // Label 2362: @120776 |
| 43175 | /* 120776 */ GIM_Try, /*On fail goto*//*Label 2363*/ GIMT_Encode4(120837), // Rule ID 3285 // |
| 43176 | /* 120781 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 43177 | /* 120784 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43178 | /* 120788 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43179 | /* 120792 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43180 | /* 120796 */ // (fmaxnum:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) => (MVE_VMAXNMf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) |
| 43181 | /* 120796 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 43182 | /* 120799 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 43183 | /* 120803 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 43184 | /* 120808 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXNMf16), |
| 43185 | /* 120811 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 43186 | /* 120813 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 43187 | /* 120815 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 43188 | /* 120817 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43189 | /* 120820 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43190 | /* 120826 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43191 | /* 120832 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 43192 | /* 120835 */ GIR_RootConstrainSelectedInstOperands, |
| 43193 | /* 120836 */ // GIR_Coverage, 3285, |
| 43194 | /* 120836 */ GIR_EraseRootFromParent_Done, |
| 43195 | /* 120837 */ // Label 2363: @120837 |
| 43196 | /* 120837 */ GIM_Reject, |
| 43197 | /* 120838 */ // Label 2360: @120838 |
| 43198 | /* 120838 */ GIM_Reject, |
| 43199 | /* 120839 */ // Label 2350: @120839 |
| 43200 | /* 120839 */ GIM_Reject, |
| 43201 | /* 120840 */ // Label 49: @120840 |
| 43202 | /* 120840 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 2370*/ GIMT_Encode4(121573), |
| 43203 | /* 120851 */ /*GILLT_s16*//*Label 2364*/ GIMT_Encode4(120903), |
| 43204 | /* 120855 */ /*GILLT_s32*//*Label 2365*/ GIMT_Encode4(121144), GIMT_Encode4(0), GIMT_Encode4(0), |
| 43205 | /* 120867 */ /*GILLT_v2s32*//*Label 2366*/ GIMT_Encode4(121385), GIMT_Encode4(0), GIMT_Encode4(0), |
| 43206 | /* 120879 */ /*GILLT_v4s16*//*Label 2367*/ GIMT_Encode4(121432), |
| 43207 | /* 120883 */ /*GILLT_v4s32*//*Label 2368*/ GIMT_Encode4(121479), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 43208 | /* 120899 */ /*GILLT_v8s16*//*Label 2369*/ GIMT_Encode4(121526), |
| 43209 | /* 120903 */ // Label 2364: @120903 |
| 43210 | /* 120903 */ GIM_Try, /*On fail goto*//*Label 2371*/ GIMT_Encode4(121143), // Rule ID 2707 // |
| 43211 | /* 120908 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 43212 | /* 120911 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 43213 | /* 120914 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 43214 | /* 120917 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 43215 | /* 120921 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 43216 | /* 120925 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 43217 | /* 120929 */ // (fminimum:{ *:[f16] } HPR:{ *:[f16] }:$a, HPR:{ *:[f16] }:$b) => (EXTRACT_SUBREG:{ *:[f16] } (COPY_TO_REGCLASS:{ *:[v4f16] } (VMINhd:{ *:[f64] } (INSERT_SUBREG:{ *:[v4f16] } (COPY_TO_REGCLASS:{ *:[v4f16] } (IMPLICIT_DEF:{ *:[v4f16] }), DPR_VFP2:{ *:[i32] }), HPR:{ *:[f16] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v4f16] } (COPY_TO_REGCLASS:{ *:[v4f16] } (IMPLICIT_DEF:{ *:[v4f16] }), DPR_VFP2:{ *:[i32] }), HPR:{ *:[f16] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] }) |
| 43218 | /* 120929 */ GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v4s16, |
| 43219 | /* 120932 */ GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 43220 | /* 120936 */ GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 43221 | /* 120941 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/8, |
| 43222 | /* 120943 */ GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v4s16, |
| 43223 | /* 120946 */ GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 43224 | /* 120950 */ GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 43225 | /* 120955 */ GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7, |
| 43226 | /* 120958 */ GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 43227 | /* 120963 */ GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v4s16, |
| 43228 | /* 120966 */ GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 43229 | /* 120970 */ GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 43230 | /* 120975 */ GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6, |
| 43231 | /* 120978 */ GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/2, // b |
| 43232 | /* 120982 */ GIR_AddImm8, /*InsnID*/6, /*Imm*/17, |
| 43233 | /* 120985 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 43234 | /* 120990 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 43235 | /* 120995 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::HPRRegClassID), |
| 43236 | /* 121000 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v4s16, |
| 43237 | /* 121003 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 43238 | /* 121007 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 43239 | /* 121012 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 43240 | /* 121014 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s16, |
| 43241 | /* 121017 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 43242 | /* 121021 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 43243 | /* 121026 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4, |
| 43244 | /* 121029 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 43245 | /* 121034 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s16, |
| 43246 | /* 121037 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 43247 | /* 121041 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 43248 | /* 121046 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3, |
| 43249 | /* 121049 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 43250 | /* 121053 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17, |
| 43251 | /* 121056 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 43252 | /* 121061 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 43253 | /* 121066 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::HPRRegClassID), |
| 43254 | /* 121071 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 43255 | /* 121074 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VMINhd), |
| 43256 | /* 121078 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 43257 | /* 121083 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 43258 | /* 121086 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5, |
| 43259 | /* 121089 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14, |
| 43260 | /* 121092 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43261 | /* 121098 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 43262 | /* 121100 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s16, |
| 43263 | /* 121103 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 43264 | /* 121107 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 43265 | /* 121112 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 43266 | /* 121115 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 43267 | /* 121120 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 43268 | /* 121123 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 43269 | /* 121125 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0), |
| 43270 | /* 121132 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 43271 | /* 121137 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 43272 | /* 121142 */ // GIR_Coverage, 2707, |
| 43273 | /* 121142 */ GIR_EraseRootFromParent_Done, |
| 43274 | /* 121143 */ // Label 2371: @121143 |
| 43275 | /* 121143 */ GIM_Reject, |
| 43276 | /* 121144 */ // Label 2365: @121144 |
| 43277 | /* 121144 */ GIM_Try, /*On fail goto*//*Label 2372*/ GIMT_Encode4(121384), // Rule ID 2709 // |
| 43278 | /* 121149 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 43279 | /* 121152 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 43280 | /* 121155 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 43281 | /* 121158 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 43282 | /* 121162 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 43283 | /* 121166 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 43284 | /* 121170 */ // (fminimum:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VMINfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] }) |
| 43285 | /* 121170 */ GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32, |
| 43286 | /* 121173 */ GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 43287 | /* 121177 */ GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 43288 | /* 121182 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/8, |
| 43289 | /* 121184 */ GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32, |
| 43290 | /* 121187 */ GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 43291 | /* 121191 */ GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 43292 | /* 121196 */ GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7, |
| 43293 | /* 121199 */ GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 43294 | /* 121204 */ GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32, |
| 43295 | /* 121207 */ GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 43296 | /* 121211 */ GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 43297 | /* 121216 */ GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6, |
| 43298 | /* 121219 */ GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/2, // b |
| 43299 | /* 121223 */ GIR_AddImm8, /*InsnID*/6, /*Imm*/17, |
| 43300 | /* 121226 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 43301 | /* 121231 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 43302 | /* 121236 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 43303 | /* 121241 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32, |
| 43304 | /* 121244 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 43305 | /* 121248 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 43306 | /* 121253 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 43307 | /* 121255 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32, |
| 43308 | /* 121258 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 43309 | /* 121262 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 43310 | /* 121267 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4, |
| 43311 | /* 121270 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 43312 | /* 121275 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32, |
| 43313 | /* 121278 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 43314 | /* 121282 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 43315 | /* 121287 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3, |
| 43316 | /* 121290 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 43317 | /* 121294 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17, |
| 43318 | /* 121297 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 43319 | /* 121302 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 43320 | /* 121307 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 43321 | /* 121312 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 43322 | /* 121315 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VMINfd), |
| 43323 | /* 121319 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 43324 | /* 121324 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 43325 | /* 121327 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5, |
| 43326 | /* 121330 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14, |
| 43327 | /* 121333 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43328 | /* 121339 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 43329 | /* 121341 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32, |
| 43330 | /* 121344 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 43331 | /* 121348 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 43332 | /* 121353 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 43333 | /* 121356 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 43334 | /* 121361 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 43335 | /* 121364 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 43336 | /* 121366 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0), |
| 43337 | /* 121373 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 43338 | /* 121378 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 43339 | /* 121383 */ // GIR_Coverage, 2709, |
| 43340 | /* 121383 */ GIR_EraseRootFromParent_Done, |
| 43341 | /* 121384 */ // Label 2372: @121384 |
| 43342 | /* 121384 */ GIM_Reject, |
| 43343 | /* 121385 */ // Label 2366: @121385 |
| 43344 | /* 121385 */ GIM_Try, /*On fail goto*//*Label 2373*/ GIMT_Encode4(121431), // Rule ID 1229 // |
| 43345 | /* 121390 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 43346 | /* 121393 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 43347 | /* 121396 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 43348 | /* 121399 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43349 | /* 121403 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43350 | /* 121407 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43351 | /* 121411 */ // (fminimum:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VMINfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) |
| 43352 | /* 121411 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINfd), |
| 43353 | /* 121414 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 43354 | /* 121416 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 43355 | /* 121418 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 43356 | /* 121420 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43357 | /* 121423 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43358 | /* 121429 */ GIR_RootConstrainSelectedInstOperands, |
| 43359 | /* 121430 */ // GIR_Coverage, 1229, |
| 43360 | /* 121430 */ GIR_EraseRootFromParent_Done, |
| 43361 | /* 121431 */ // Label 2373: @121431 |
| 43362 | /* 121431 */ GIM_Reject, |
| 43363 | /* 121432 */ // Label 2367: @121432 |
| 43364 | /* 121432 */ GIM_Try, /*On fail goto*//*Label 2374*/ GIMT_Encode4(121478), // Rule ID 1231 // |
| 43365 | /* 121437 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 43366 | /* 121440 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 43367 | /* 121443 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 43368 | /* 121446 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43369 | /* 121450 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43370 | /* 121454 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43371 | /* 121458 */ // (fminimum:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VMINhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) |
| 43372 | /* 121458 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINhd), |
| 43373 | /* 121461 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 43374 | /* 121463 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 43375 | /* 121465 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 43376 | /* 121467 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43377 | /* 121470 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43378 | /* 121476 */ GIR_RootConstrainSelectedInstOperands, |
| 43379 | /* 121477 */ // GIR_Coverage, 1231, |
| 43380 | /* 121477 */ GIR_EraseRootFromParent_Done, |
| 43381 | /* 121478 */ // Label 2374: @121478 |
| 43382 | /* 121478 */ GIM_Reject, |
| 43383 | /* 121479 */ // Label 2368: @121479 |
| 43384 | /* 121479 */ GIM_Try, /*On fail goto*//*Label 2375*/ GIMT_Encode4(121525), // Rule ID 1230 // |
| 43385 | /* 121484 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 43386 | /* 121487 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 43387 | /* 121490 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 43388 | /* 121493 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43389 | /* 121497 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43390 | /* 121501 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43391 | /* 121505 */ // (fminimum:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (VMINfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) |
| 43392 | /* 121505 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINfq), |
| 43393 | /* 121508 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 43394 | /* 121510 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 43395 | /* 121512 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 43396 | /* 121514 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43397 | /* 121517 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43398 | /* 121523 */ GIR_RootConstrainSelectedInstOperands, |
| 43399 | /* 121524 */ // GIR_Coverage, 1230, |
| 43400 | /* 121524 */ GIR_EraseRootFromParent_Done, |
| 43401 | /* 121525 */ // Label 2375: @121525 |
| 43402 | /* 121525 */ GIM_Reject, |
| 43403 | /* 121526 */ // Label 2369: @121526 |
| 43404 | /* 121526 */ GIM_Try, /*On fail goto*//*Label 2376*/ GIMT_Encode4(121572), // Rule ID 1232 // |
| 43405 | /* 121531 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 43406 | /* 121534 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 43407 | /* 121537 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 43408 | /* 121540 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43409 | /* 121544 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43410 | /* 121548 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43411 | /* 121552 */ // (fminimum:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (VMINhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) |
| 43412 | /* 121552 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINhq), |
| 43413 | /* 121555 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 43414 | /* 121557 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 43415 | /* 121559 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 43416 | /* 121561 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43417 | /* 121564 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43418 | /* 121570 */ GIR_RootConstrainSelectedInstOperands, |
| 43419 | /* 121571 */ // GIR_Coverage, 1232, |
| 43420 | /* 121571 */ GIR_EraseRootFromParent_Done, |
| 43421 | /* 121572 */ // Label 2376: @121572 |
| 43422 | /* 121572 */ GIM_Reject, |
| 43423 | /* 121573 */ // Label 2370: @121573 |
| 43424 | /* 121573 */ GIM_Reject, |
| 43425 | /* 121574 */ // Label 50: @121574 |
| 43426 | /* 121574 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 2383*/ GIMT_Encode4(122307), |
| 43427 | /* 121585 */ /*GILLT_s16*//*Label 2377*/ GIMT_Encode4(121637), |
| 43428 | /* 121589 */ /*GILLT_s32*//*Label 2378*/ GIMT_Encode4(121878), GIMT_Encode4(0), GIMT_Encode4(0), |
| 43429 | /* 121601 */ /*GILLT_v2s32*//*Label 2379*/ GIMT_Encode4(122119), GIMT_Encode4(0), GIMT_Encode4(0), |
| 43430 | /* 121613 */ /*GILLT_v4s16*//*Label 2380*/ GIMT_Encode4(122166), |
| 43431 | /* 121617 */ /*GILLT_v4s32*//*Label 2381*/ GIMT_Encode4(122213), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 43432 | /* 121633 */ /*GILLT_v8s16*//*Label 2382*/ GIMT_Encode4(122260), |
| 43433 | /* 121637 */ // Label 2377: @121637 |
| 43434 | /* 121637 */ GIM_Try, /*On fail goto*//*Label 2384*/ GIMT_Encode4(121877), // Rule ID 2706 // |
| 43435 | /* 121642 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 43436 | /* 121645 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 43437 | /* 121648 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 43438 | /* 121651 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 43439 | /* 121655 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 43440 | /* 121659 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 43441 | /* 121663 */ // (fmaximum:{ *:[f16] } HPR:{ *:[f16] }:$a, HPR:{ *:[f16] }:$b) => (EXTRACT_SUBREG:{ *:[f16] } (COPY_TO_REGCLASS:{ *:[v4f16] } (VMAXhd:{ *:[f64] } (INSERT_SUBREG:{ *:[v4f16] } (COPY_TO_REGCLASS:{ *:[v4f16] } (IMPLICIT_DEF:{ *:[v4f16] }), DPR_VFP2:{ *:[i32] }), HPR:{ *:[f16] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v4f16] } (COPY_TO_REGCLASS:{ *:[v4f16] } (IMPLICIT_DEF:{ *:[v4f16] }), DPR_VFP2:{ *:[i32] }), HPR:{ *:[f16] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] }) |
| 43442 | /* 121663 */ GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v4s16, |
| 43443 | /* 121666 */ GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 43444 | /* 121670 */ GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 43445 | /* 121675 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/8, |
| 43446 | /* 121677 */ GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v4s16, |
| 43447 | /* 121680 */ GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 43448 | /* 121684 */ GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 43449 | /* 121689 */ GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7, |
| 43450 | /* 121692 */ GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 43451 | /* 121697 */ GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v4s16, |
| 43452 | /* 121700 */ GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 43453 | /* 121704 */ GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 43454 | /* 121709 */ GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6, |
| 43455 | /* 121712 */ GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/2, // b |
| 43456 | /* 121716 */ GIR_AddImm8, /*InsnID*/6, /*Imm*/17, |
| 43457 | /* 121719 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 43458 | /* 121724 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 43459 | /* 121729 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::HPRRegClassID), |
| 43460 | /* 121734 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v4s16, |
| 43461 | /* 121737 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 43462 | /* 121741 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 43463 | /* 121746 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 43464 | /* 121748 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s16, |
| 43465 | /* 121751 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 43466 | /* 121755 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 43467 | /* 121760 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4, |
| 43468 | /* 121763 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 43469 | /* 121768 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s16, |
| 43470 | /* 121771 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 43471 | /* 121775 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 43472 | /* 121780 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3, |
| 43473 | /* 121783 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 43474 | /* 121787 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17, |
| 43475 | /* 121790 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 43476 | /* 121795 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 43477 | /* 121800 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::HPRRegClassID), |
| 43478 | /* 121805 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 43479 | /* 121808 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VMAXhd), |
| 43480 | /* 121812 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 43481 | /* 121817 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 43482 | /* 121820 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5, |
| 43483 | /* 121823 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14, |
| 43484 | /* 121826 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43485 | /* 121832 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 43486 | /* 121834 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s16, |
| 43487 | /* 121837 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 43488 | /* 121841 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 43489 | /* 121846 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 43490 | /* 121849 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 43491 | /* 121854 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 43492 | /* 121857 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 43493 | /* 121859 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0), |
| 43494 | /* 121866 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 43495 | /* 121871 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 43496 | /* 121876 */ // GIR_Coverage, 2706, |
| 43497 | /* 121876 */ GIR_EraseRootFromParent_Done, |
| 43498 | /* 121877 */ // Label 2384: @121877 |
| 43499 | /* 121877 */ GIM_Reject, |
| 43500 | /* 121878 */ // Label 2378: @121878 |
| 43501 | /* 121878 */ GIM_Try, /*On fail goto*//*Label 2385*/ GIMT_Encode4(122118), // Rule ID 2708 // |
| 43502 | /* 121883 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 43503 | /* 121886 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 43504 | /* 121889 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 43505 | /* 121892 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 43506 | /* 121896 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 43507 | /* 121900 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 43508 | /* 121904 */ // (fmaximum:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VMAXfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] }) |
| 43509 | /* 121904 */ GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32, |
| 43510 | /* 121907 */ GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 43511 | /* 121911 */ GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 43512 | /* 121916 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/8, |
| 43513 | /* 121918 */ GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32, |
| 43514 | /* 121921 */ GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 43515 | /* 121925 */ GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 43516 | /* 121930 */ GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7, |
| 43517 | /* 121933 */ GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 43518 | /* 121938 */ GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32, |
| 43519 | /* 121941 */ GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 43520 | /* 121945 */ GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 43521 | /* 121950 */ GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6, |
| 43522 | /* 121953 */ GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/2, // b |
| 43523 | /* 121957 */ GIR_AddImm8, /*InsnID*/6, /*Imm*/17, |
| 43524 | /* 121960 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 43525 | /* 121965 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 43526 | /* 121970 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 43527 | /* 121975 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32, |
| 43528 | /* 121978 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 43529 | /* 121982 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 43530 | /* 121987 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 43531 | /* 121989 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32, |
| 43532 | /* 121992 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 43533 | /* 121996 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 43534 | /* 122001 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4, |
| 43535 | /* 122004 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 43536 | /* 122009 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32, |
| 43537 | /* 122012 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 43538 | /* 122016 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 43539 | /* 122021 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3, |
| 43540 | /* 122024 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 43541 | /* 122028 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17, |
| 43542 | /* 122031 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 43543 | /* 122036 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 43544 | /* 122041 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 43545 | /* 122046 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 43546 | /* 122049 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VMAXfd), |
| 43547 | /* 122053 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 43548 | /* 122058 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 43549 | /* 122061 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5, |
| 43550 | /* 122064 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14, |
| 43551 | /* 122067 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43552 | /* 122073 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 43553 | /* 122075 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32, |
| 43554 | /* 122078 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 43555 | /* 122082 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 43556 | /* 122087 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 43557 | /* 122090 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 43558 | /* 122095 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 43559 | /* 122098 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 43560 | /* 122100 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0), |
| 43561 | /* 122107 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 43562 | /* 122112 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 43563 | /* 122117 */ // GIR_Coverage, 2708, |
| 43564 | /* 122117 */ GIR_EraseRootFromParent_Done, |
| 43565 | /* 122118 */ // Label 2385: @122118 |
| 43566 | /* 122118 */ GIM_Reject, |
| 43567 | /* 122119 */ // Label 2379: @122119 |
| 43568 | /* 122119 */ GIM_Try, /*On fail goto*//*Label 2386*/ GIMT_Encode4(122165), // Rule ID 1209 // |
| 43569 | /* 122124 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 43570 | /* 122127 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 43571 | /* 122130 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 43572 | /* 122133 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43573 | /* 122137 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43574 | /* 122141 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43575 | /* 122145 */ // (fmaximum:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VMAXfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) |
| 43576 | /* 122145 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXfd), |
| 43577 | /* 122148 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 43578 | /* 122150 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 43579 | /* 122152 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 43580 | /* 122154 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43581 | /* 122157 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43582 | /* 122163 */ GIR_RootConstrainSelectedInstOperands, |
| 43583 | /* 122164 */ // GIR_Coverage, 1209, |
| 43584 | /* 122164 */ GIR_EraseRootFromParent_Done, |
| 43585 | /* 122165 */ // Label 2386: @122165 |
| 43586 | /* 122165 */ GIM_Reject, |
| 43587 | /* 122166 */ // Label 2380: @122166 |
| 43588 | /* 122166 */ GIM_Try, /*On fail goto*//*Label 2387*/ GIMT_Encode4(122212), // Rule ID 1211 // |
| 43589 | /* 122171 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 43590 | /* 122174 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 43591 | /* 122177 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 43592 | /* 122180 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43593 | /* 122184 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43594 | /* 122188 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43595 | /* 122192 */ // (fmaximum:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VMAXhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) |
| 43596 | /* 122192 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXhd), |
| 43597 | /* 122195 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 43598 | /* 122197 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 43599 | /* 122199 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 43600 | /* 122201 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43601 | /* 122204 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43602 | /* 122210 */ GIR_RootConstrainSelectedInstOperands, |
| 43603 | /* 122211 */ // GIR_Coverage, 1211, |
| 43604 | /* 122211 */ GIR_EraseRootFromParent_Done, |
| 43605 | /* 122212 */ // Label 2387: @122212 |
| 43606 | /* 122212 */ GIM_Reject, |
| 43607 | /* 122213 */ // Label 2381: @122213 |
| 43608 | /* 122213 */ GIM_Try, /*On fail goto*//*Label 2388*/ GIMT_Encode4(122259), // Rule ID 1210 // |
| 43609 | /* 122218 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 43610 | /* 122221 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 43611 | /* 122224 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 43612 | /* 122227 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43613 | /* 122231 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43614 | /* 122235 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43615 | /* 122239 */ // (fmaximum:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (VMAXfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) |
| 43616 | /* 122239 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXfq), |
| 43617 | /* 122242 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 43618 | /* 122244 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 43619 | /* 122246 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 43620 | /* 122248 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43621 | /* 122251 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43622 | /* 122257 */ GIR_RootConstrainSelectedInstOperands, |
| 43623 | /* 122258 */ // GIR_Coverage, 1210, |
| 43624 | /* 122258 */ GIR_EraseRootFromParent_Done, |
| 43625 | /* 122259 */ // Label 2388: @122259 |
| 43626 | /* 122259 */ GIM_Reject, |
| 43627 | /* 122260 */ // Label 2382: @122260 |
| 43628 | /* 122260 */ GIM_Try, /*On fail goto*//*Label 2389*/ GIMT_Encode4(122306), // Rule ID 1212 // |
| 43629 | /* 122265 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), |
| 43630 | /* 122268 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 43631 | /* 122271 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 43632 | /* 122274 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43633 | /* 122278 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43634 | /* 122282 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43635 | /* 122286 */ // (fmaximum:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (VMAXhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) |
| 43636 | /* 122286 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXhq), |
| 43637 | /* 122289 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 43638 | /* 122291 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 43639 | /* 122293 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 43640 | /* 122295 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43641 | /* 122298 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43642 | /* 122304 */ GIR_RootConstrainSelectedInstOperands, |
| 43643 | /* 122305 */ // GIR_Coverage, 1212, |
| 43644 | /* 122305 */ GIR_EraseRootFromParent_Done, |
| 43645 | /* 122306 */ // Label 2389: @122306 |
| 43646 | /* 122306 */ GIM_Reject, |
| 43647 | /* 122307 */ // Label 2383: @122307 |
| 43648 | /* 122307 */ GIM_Reject, |
| 43649 | /* 122308 */ // Label 51: @122308 |
| 43650 | /* 122308 */ GIM_Try, /*On fail goto*//*Label 2390*/ GIMT_Encode4(122340), // Rule ID 2419 // |
| 43651 | /* 122313 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 43652 | /* 122316 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 43653 | /* 122320 */ // (get_fpenv:{ *:[i32] }) => (VMRS:{ *:[i32] }) |
| 43654 | /* 122320 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMRS), |
| 43655 | /* 122323 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt] |
| 43656 | /* 122325 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43657 | /* 122328 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43658 | /* 122334 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 43659 | /* 122338 */ GIR_RootConstrainSelectedInstOperands, |
| 43660 | /* 122339 */ // GIR_Coverage, 2419, |
| 43661 | /* 122339 */ GIR_EraseRootFromParent_Done, |
| 43662 | /* 122340 */ // Label 2390: @122340 |
| 43663 | /* 122340 */ GIM_Reject, |
| 43664 | /* 122341 */ // Label 52: @122341 |
| 43665 | /* 122341 */ GIM_Try, /*On fail goto*//*Label 2391*/ GIMT_Encode4(122376), // Rule ID 2420 // |
| 43666 | /* 122346 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 43667 | /* 122349 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 43668 | /* 122353 */ // (set_fpenv GPRnopc:{ *:[i32] }:$Rt) => (VMSR:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rt) |
| 43669 | /* 122353 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMSR), |
| 43670 | /* 122356 */ GIR_RootToRootCopy, /*OpIdx*/0, // Rt |
| 43671 | /* 122358 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43672 | /* 122361 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43673 | /* 122367 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for ARM::FPSCR*/0, |
| 43674 | /* 122370 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 43675 | /* 122374 */ GIR_RootConstrainSelectedInstOperands, |
| 43676 | /* 122375 */ // GIR_Coverage, 2420, |
| 43677 | /* 122375 */ GIR_EraseRootFromParent_Done, |
| 43678 | /* 122376 */ // Label 2391: @122376 |
| 43679 | /* 122376 */ GIM_Reject, |
| 43680 | /* 122377 */ // Label 53: @122377 |
| 43681 | /* 122377 */ GIM_Try, /*On fail goto*//*Label 2392*/ GIMT_Encode4(122441), // Rule ID 2421 // |
| 43682 | /* 122382 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 43683 | /* 122385 */ // (reset_fpenv) => (VMSR:{ *:[i32] } (MOVi:{ *:[i32] } 0:{ *:[i32] })) |
| 43684 | /* 122385 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 43685 | /* 122388 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::MOVi), |
| 43686 | /* 122392 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 43687 | /* 122397 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 43688 | /* 122400 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 43689 | /* 122403 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43690 | /* 122409 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43691 | /* 122415 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 43692 | /* 122417 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMSR), |
| 43693 | /* 122420 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 43694 | /* 122423 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43695 | /* 122426 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43696 | /* 122432 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for ARM::FPSCR*/0, |
| 43697 | /* 122435 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 43698 | /* 122439 */ GIR_RootConstrainSelectedInstOperands, |
| 43699 | /* 122440 */ // GIR_Coverage, 2421, |
| 43700 | /* 122440 */ GIR_EraseRootFromParent_Done, |
| 43701 | /* 122441 */ // Label 2392: @122441 |
| 43702 | /* 122441 */ GIM_Try, /*On fail goto*//*Label 2393*/ GIMT_Encode4(122505), // Rule ID 2422 // |
| 43703 | /* 122446 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb), |
| 43704 | /* 122449 */ // (reset_fpenv) => (VMSR:{ *:[i32] } (tMOVi8:{ *:[i32] } 0:{ *:[i32] })) |
| 43705 | /* 122449 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 43706 | /* 122452 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::tMOVi8), |
| 43707 | /* 122456 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 43708 | /* 122461 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define | RegState::Dead), |
| 43709 | /* 122467 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 43710 | /* 122470 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 43711 | /* 122473 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43712 | /* 122479 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 43713 | /* 122481 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMSR), |
| 43714 | /* 122484 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 43715 | /* 122487 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43716 | /* 122490 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43717 | /* 122496 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for ARM::FPSCR*/0, |
| 43718 | /* 122499 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 43719 | /* 122503 */ GIR_RootConstrainSelectedInstOperands, |
| 43720 | /* 122504 */ // GIR_Coverage, 2422, |
| 43721 | /* 122504 */ GIR_EraseRootFromParent_Done, |
| 43722 | /* 122505 */ // Label 2393: @122505 |
| 43723 | /* 122505 */ GIM_Reject, |
| 43724 | /* 122506 */ // Label 54: @122506 |
| 43725 | /* 122506 */ GIM_Try, /*On fail goto*//*Label 2394*/ GIMT_Encode4(122538), // Rule ID 2423 // |
| 43726 | /* 122511 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 43727 | /* 122514 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 43728 | /* 122518 */ // (get_fpmode:{ *:[i32] }) => (VMRS:{ *:[i32] }) |
| 43729 | /* 122518 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMRS), |
| 43730 | /* 122521 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt] |
| 43731 | /* 122523 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43732 | /* 122526 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43733 | /* 122532 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 43734 | /* 122536 */ GIR_RootConstrainSelectedInstOperands, |
| 43735 | /* 122537 */ // GIR_Coverage, 2423, |
| 43736 | /* 122537 */ GIR_EraseRootFromParent_Done, |
| 43737 | /* 122538 */ // Label 2394: @122538 |
| 43738 | /* 122538 */ GIM_Reject, |
| 43739 | /* 122539 */ // Label 55: @122539 |
| 43740 | /* 122539 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(16), /*)*//*default:*//*Label 2401*/ GIMT_Encode4(123081), |
| 43741 | /* 122550 */ /*GILLT_v2s32*//*Label 2395*/ GIMT_Encode4(122598), GIMT_Encode4(0), GIMT_Encode4(0), |
| 43742 | /* 122562 */ /*GILLT_v4s16*//*Label 2396*/ GIMT_Encode4(122645), |
| 43743 | /* 122566 */ /*GILLT_v4s32*//*Label 2397*/ GIMT_Encode4(122692), GIMT_Encode4(0), GIMT_Encode4(0), |
| 43744 | /* 122578 */ /*GILLT_v8s8*//*Label 2398*/ GIMT_Encode4(122806), |
| 43745 | /* 122582 */ /*GILLT_v8s16*//*Label 2399*/ GIMT_Encode4(122853), GIMT_Encode4(0), GIMT_Encode4(0), |
| 43746 | /* 122594 */ /*GILLT_v16s8*//*Label 2400*/ GIMT_Encode4(122967), |
| 43747 | /* 122598 */ // Label 2395: @122598 |
| 43748 | /* 122598 */ GIM_Try, /*On fail goto*//*Label 2402*/ GIMT_Encode4(122644), // Rule ID 1218 // |
| 43749 | /* 122603 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 43750 | /* 122606 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 43751 | /* 122609 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 43752 | /* 122612 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43753 | /* 122616 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43754 | /* 122620 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43755 | /* 122624 */ // (smin:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VMINsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 43756 | /* 122624 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINsv2i32), |
| 43757 | /* 122627 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 43758 | /* 122629 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 43759 | /* 122631 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 43760 | /* 122633 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43761 | /* 122636 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43762 | /* 122642 */ GIR_RootConstrainSelectedInstOperands, |
| 43763 | /* 122643 */ // GIR_Coverage, 1218, |
| 43764 | /* 122643 */ GIR_EraseRootFromParent_Done, |
| 43765 | /* 122644 */ // Label 2402: @122644 |
| 43766 | /* 122644 */ GIM_Reject, |
| 43767 | /* 122645 */ // Label 2396: @122645 |
| 43768 | /* 122645 */ GIM_Try, /*On fail goto*//*Label 2403*/ GIMT_Encode4(122691), // Rule ID 1217 // |
| 43769 | /* 122650 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 43770 | /* 122653 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 43771 | /* 122656 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 43772 | /* 122659 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43773 | /* 122663 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43774 | /* 122667 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43775 | /* 122671 */ // (smin:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VMINsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 43776 | /* 122671 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINsv4i16), |
| 43777 | /* 122674 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 43778 | /* 122676 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 43779 | /* 122678 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 43780 | /* 122680 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43781 | /* 122683 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43782 | /* 122689 */ GIR_RootConstrainSelectedInstOperands, |
| 43783 | /* 122690 */ // GIR_Coverage, 1217, |
| 43784 | /* 122690 */ GIR_EraseRootFromParent_Done, |
| 43785 | /* 122691 */ // Label 2403: @122691 |
| 43786 | /* 122691 */ GIM_Reject, |
| 43787 | /* 122692 */ // Label 2397: @122692 |
| 43788 | /* 122692 */ GIM_Try, /*On fail goto*//*Label 2404*/ GIMT_Encode4(122805), |
| 43789 | /* 122697 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 43790 | /* 122700 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 43791 | /* 122703 */ GIM_Try, /*On fail goto*//*Label 2405*/ GIMT_Encode4(122743), // Rule ID 1220 // |
| 43792 | /* 122708 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 43793 | /* 122711 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43794 | /* 122715 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43795 | /* 122719 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43796 | /* 122723 */ // (smin:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VMINsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 43797 | /* 122723 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINsv4i32), |
| 43798 | /* 122726 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 43799 | /* 122728 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 43800 | /* 122730 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 43801 | /* 122732 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43802 | /* 122735 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43803 | /* 122741 */ GIR_RootConstrainSelectedInstOperands, |
| 43804 | /* 122742 */ // GIR_Coverage, 1220, |
| 43805 | /* 122742 */ GIR_EraseRootFromParent_Done, |
| 43806 | /* 122743 */ // Label 2405: @122743 |
| 43807 | /* 122743 */ GIM_Try, /*On fail goto*//*Label 2406*/ GIMT_Encode4(122804), // Rule ID 3300 // |
| 43808 | /* 122748 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 43809 | /* 122751 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43810 | /* 122755 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43811 | /* 122759 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43812 | /* 122763 */ // (smin:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VMINs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 43813 | /* 122763 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 43814 | /* 122766 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 43815 | /* 122770 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 43816 | /* 122775 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINs32), |
| 43817 | /* 122778 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 43818 | /* 122780 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 43819 | /* 122782 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 43820 | /* 122784 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43821 | /* 122787 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43822 | /* 122793 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43823 | /* 122799 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 43824 | /* 122802 */ GIR_RootConstrainSelectedInstOperands, |
| 43825 | /* 122803 */ // GIR_Coverage, 3300, |
| 43826 | /* 122803 */ GIR_EraseRootFromParent_Done, |
| 43827 | /* 122804 */ // Label 2406: @122804 |
| 43828 | /* 122804 */ GIM_Reject, |
| 43829 | /* 122805 */ // Label 2404: @122805 |
| 43830 | /* 122805 */ GIM_Reject, |
| 43831 | /* 122806 */ // Label 2398: @122806 |
| 43832 | /* 122806 */ GIM_Try, /*On fail goto*//*Label 2407*/ GIMT_Encode4(122852), // Rule ID 1221 // |
| 43833 | /* 122811 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 43834 | /* 122814 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 43835 | /* 122817 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 43836 | /* 122820 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43837 | /* 122824 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43838 | /* 122828 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43839 | /* 122832 */ // (smin:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VMINsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 43840 | /* 122832 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINsv8i8), |
| 43841 | /* 122835 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 43842 | /* 122837 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 43843 | /* 122839 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 43844 | /* 122841 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43845 | /* 122844 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43846 | /* 122850 */ GIR_RootConstrainSelectedInstOperands, |
| 43847 | /* 122851 */ // GIR_Coverage, 1221, |
| 43848 | /* 122851 */ GIR_EraseRootFromParent_Done, |
| 43849 | /* 122852 */ // Label 2407: @122852 |
| 43850 | /* 122852 */ GIM_Reject, |
| 43851 | /* 122853 */ // Label 2399: @122853 |
| 43852 | /* 122853 */ GIM_Try, /*On fail goto*//*Label 2408*/ GIMT_Encode4(122966), |
| 43853 | /* 122858 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 43854 | /* 122861 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 43855 | /* 122864 */ GIM_Try, /*On fail goto*//*Label 2409*/ GIMT_Encode4(122904), // Rule ID 1219 // |
| 43856 | /* 122869 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 43857 | /* 122872 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43858 | /* 122876 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43859 | /* 122880 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43860 | /* 122884 */ // (smin:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VMINsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 43861 | /* 122884 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINsv8i16), |
| 43862 | /* 122887 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 43863 | /* 122889 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 43864 | /* 122891 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 43865 | /* 122893 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43866 | /* 122896 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43867 | /* 122902 */ GIR_RootConstrainSelectedInstOperands, |
| 43868 | /* 122903 */ // GIR_Coverage, 1219, |
| 43869 | /* 122903 */ GIR_EraseRootFromParent_Done, |
| 43870 | /* 122904 */ // Label 2409: @122904 |
| 43871 | /* 122904 */ GIM_Try, /*On fail goto*//*Label 2410*/ GIMT_Encode4(122965), // Rule ID 3297 // |
| 43872 | /* 122909 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 43873 | /* 122912 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43874 | /* 122916 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43875 | /* 122920 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43876 | /* 122924 */ // (smin:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VMINs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 43877 | /* 122924 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 43878 | /* 122927 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 43879 | /* 122931 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 43880 | /* 122936 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINs16), |
| 43881 | /* 122939 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 43882 | /* 122941 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 43883 | /* 122943 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 43884 | /* 122945 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43885 | /* 122948 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43886 | /* 122954 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43887 | /* 122960 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 43888 | /* 122963 */ GIR_RootConstrainSelectedInstOperands, |
| 43889 | /* 122964 */ // GIR_Coverage, 3297, |
| 43890 | /* 122964 */ GIR_EraseRootFromParent_Done, |
| 43891 | /* 122965 */ // Label 2410: @122965 |
| 43892 | /* 122965 */ GIM_Reject, |
| 43893 | /* 122966 */ // Label 2408: @122966 |
| 43894 | /* 122966 */ GIM_Reject, |
| 43895 | /* 122967 */ // Label 2400: @122967 |
| 43896 | /* 122967 */ GIM_Try, /*On fail goto*//*Label 2411*/ GIMT_Encode4(123080), |
| 43897 | /* 122972 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 43898 | /* 122975 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 43899 | /* 122978 */ GIM_Try, /*On fail goto*//*Label 2412*/ GIMT_Encode4(123018), // Rule ID 1222 // |
| 43900 | /* 122983 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 43901 | /* 122986 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43902 | /* 122990 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43903 | /* 122994 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43904 | /* 122998 */ // (smin:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VMINsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 43905 | /* 122998 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINsv16i8), |
| 43906 | /* 123001 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 43907 | /* 123003 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 43908 | /* 123005 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 43909 | /* 123007 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43910 | /* 123010 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43911 | /* 123016 */ GIR_RootConstrainSelectedInstOperands, |
| 43912 | /* 123017 */ // GIR_Coverage, 1222, |
| 43913 | /* 123017 */ GIR_EraseRootFromParent_Done, |
| 43914 | /* 123018 */ // Label 2412: @123018 |
| 43915 | /* 123018 */ GIM_Try, /*On fail goto*//*Label 2413*/ GIMT_Encode4(123079), // Rule ID 3294 // |
| 43916 | /* 123023 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 43917 | /* 123026 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43918 | /* 123030 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43919 | /* 123034 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43920 | /* 123038 */ // (smin:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VMINs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 43921 | /* 123038 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 43922 | /* 123041 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 43923 | /* 123045 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 43924 | /* 123050 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINs8), |
| 43925 | /* 123053 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 43926 | /* 123055 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 43927 | /* 123057 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 43928 | /* 123059 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43929 | /* 123062 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43930 | /* 123068 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43931 | /* 123074 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 43932 | /* 123077 */ GIR_RootConstrainSelectedInstOperands, |
| 43933 | /* 123078 */ // GIR_Coverage, 3294, |
| 43934 | /* 123078 */ GIR_EraseRootFromParent_Done, |
| 43935 | /* 123079 */ // Label 2413: @123079 |
| 43936 | /* 123079 */ GIM_Reject, |
| 43937 | /* 123080 */ // Label 2411: @123080 |
| 43938 | /* 123080 */ GIM_Reject, |
| 43939 | /* 123081 */ // Label 2401: @123081 |
| 43940 | /* 123081 */ GIM_Reject, |
| 43941 | /* 123082 */ // Label 56: @123082 |
| 43942 | /* 123082 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(16), /*)*//*default:*//*Label 2420*/ GIMT_Encode4(123624), |
| 43943 | /* 123093 */ /*GILLT_v2s32*//*Label 2414*/ GIMT_Encode4(123141), GIMT_Encode4(0), GIMT_Encode4(0), |
| 43944 | /* 123105 */ /*GILLT_v4s16*//*Label 2415*/ GIMT_Encode4(123188), |
| 43945 | /* 123109 */ /*GILLT_v4s32*//*Label 2416*/ GIMT_Encode4(123235), GIMT_Encode4(0), GIMT_Encode4(0), |
| 43946 | /* 123121 */ /*GILLT_v8s8*//*Label 2417*/ GIMT_Encode4(123349), |
| 43947 | /* 123125 */ /*GILLT_v8s16*//*Label 2418*/ GIMT_Encode4(123396), GIMT_Encode4(0), GIMT_Encode4(0), |
| 43948 | /* 123137 */ /*GILLT_v16s8*//*Label 2419*/ GIMT_Encode4(123510), |
| 43949 | /* 123141 */ // Label 2414: @123141 |
| 43950 | /* 123141 */ GIM_Try, /*On fail goto*//*Label 2421*/ GIMT_Encode4(123187), // Rule ID 1198 // |
| 43951 | /* 123146 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 43952 | /* 123149 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 43953 | /* 123152 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 43954 | /* 123155 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43955 | /* 123159 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43956 | /* 123163 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43957 | /* 123167 */ // (smax:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VMAXsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 43958 | /* 123167 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXsv2i32), |
| 43959 | /* 123170 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 43960 | /* 123172 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 43961 | /* 123174 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 43962 | /* 123176 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43963 | /* 123179 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43964 | /* 123185 */ GIR_RootConstrainSelectedInstOperands, |
| 43965 | /* 123186 */ // GIR_Coverage, 1198, |
| 43966 | /* 123186 */ GIR_EraseRootFromParent_Done, |
| 43967 | /* 123187 */ // Label 2421: @123187 |
| 43968 | /* 123187 */ GIM_Reject, |
| 43969 | /* 123188 */ // Label 2415: @123188 |
| 43970 | /* 123188 */ GIM_Try, /*On fail goto*//*Label 2422*/ GIMT_Encode4(123234), // Rule ID 1197 // |
| 43971 | /* 123193 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 43972 | /* 123196 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 43973 | /* 123199 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 43974 | /* 123202 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43975 | /* 123206 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43976 | /* 123210 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43977 | /* 123214 */ // (smax:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VMAXsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 43978 | /* 123214 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXsv4i16), |
| 43979 | /* 123217 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 43980 | /* 123219 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 43981 | /* 123221 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 43982 | /* 123223 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43983 | /* 123226 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43984 | /* 123232 */ GIR_RootConstrainSelectedInstOperands, |
| 43985 | /* 123233 */ // GIR_Coverage, 1197, |
| 43986 | /* 123233 */ GIR_EraseRootFromParent_Done, |
| 43987 | /* 123234 */ // Label 2422: @123234 |
| 43988 | /* 123234 */ GIM_Reject, |
| 43989 | /* 123235 */ // Label 2416: @123235 |
| 43990 | /* 123235 */ GIM_Try, /*On fail goto*//*Label 2423*/ GIMT_Encode4(123348), |
| 43991 | /* 123240 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 43992 | /* 123243 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 43993 | /* 123246 */ GIM_Try, /*On fail goto*//*Label 2424*/ GIMT_Encode4(123286), // Rule ID 1200 // |
| 43994 | /* 123251 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 43995 | /* 123254 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43996 | /* 123258 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43997 | /* 123262 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43998 | /* 123266 */ // (smax:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VMAXsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 43999 | /* 123266 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXsv4i32), |
| 44000 | /* 123269 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 44001 | /* 123271 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 44002 | /* 123273 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 44003 | /* 123275 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 44004 | /* 123278 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44005 | /* 123284 */ GIR_RootConstrainSelectedInstOperands, |
| 44006 | /* 123285 */ // GIR_Coverage, 1200, |
| 44007 | /* 123285 */ GIR_EraseRootFromParent_Done, |
| 44008 | /* 123286 */ // Label 2424: @123286 |
| 44009 | /* 123286 */ GIM_Try, /*On fail goto*//*Label 2425*/ GIMT_Encode4(123347), // Rule ID 3318 // |
| 44010 | /* 123291 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 44011 | /* 123294 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44012 | /* 123298 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44013 | /* 123302 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44014 | /* 123306 */ // (smax:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VMAXs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 44015 | /* 123306 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 44016 | /* 123309 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 44017 | /* 123313 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 44018 | /* 123318 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXs32), |
| 44019 | /* 123321 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 44020 | /* 123323 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 44021 | /* 123325 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 44022 | /* 123327 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44023 | /* 123330 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44024 | /* 123336 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44025 | /* 123342 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 44026 | /* 123345 */ GIR_RootConstrainSelectedInstOperands, |
| 44027 | /* 123346 */ // GIR_Coverage, 3318, |
| 44028 | /* 123346 */ GIR_EraseRootFromParent_Done, |
| 44029 | /* 123347 */ // Label 2425: @123347 |
| 44030 | /* 123347 */ GIM_Reject, |
| 44031 | /* 123348 */ // Label 2423: @123348 |
| 44032 | /* 123348 */ GIM_Reject, |
| 44033 | /* 123349 */ // Label 2417: @123349 |
| 44034 | /* 123349 */ GIM_Try, /*On fail goto*//*Label 2426*/ GIMT_Encode4(123395), // Rule ID 1201 // |
| 44035 | /* 123354 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 44036 | /* 123357 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 44037 | /* 123360 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 44038 | /* 123363 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44039 | /* 123367 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44040 | /* 123371 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44041 | /* 123375 */ // (smax:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VMAXsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 44042 | /* 123375 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXsv8i8), |
| 44043 | /* 123378 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 44044 | /* 123380 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 44045 | /* 123382 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 44046 | /* 123384 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 44047 | /* 123387 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44048 | /* 123393 */ GIR_RootConstrainSelectedInstOperands, |
| 44049 | /* 123394 */ // GIR_Coverage, 1201, |
| 44050 | /* 123394 */ GIR_EraseRootFromParent_Done, |
| 44051 | /* 123395 */ // Label 2426: @123395 |
| 44052 | /* 123395 */ GIM_Reject, |
| 44053 | /* 123396 */ // Label 2418: @123396 |
| 44054 | /* 123396 */ GIM_Try, /*On fail goto*//*Label 2427*/ GIMT_Encode4(123509), |
| 44055 | /* 123401 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 44056 | /* 123404 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 44057 | /* 123407 */ GIM_Try, /*On fail goto*//*Label 2428*/ GIMT_Encode4(123447), // Rule ID 1199 // |
| 44058 | /* 123412 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 44059 | /* 123415 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 44060 | /* 123419 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 44061 | /* 123423 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 44062 | /* 123427 */ // (smax:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VMAXsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 44063 | /* 123427 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXsv8i16), |
| 44064 | /* 123430 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 44065 | /* 123432 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 44066 | /* 123434 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 44067 | /* 123436 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 44068 | /* 123439 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44069 | /* 123445 */ GIR_RootConstrainSelectedInstOperands, |
| 44070 | /* 123446 */ // GIR_Coverage, 1199, |
| 44071 | /* 123446 */ GIR_EraseRootFromParent_Done, |
| 44072 | /* 123447 */ // Label 2428: @123447 |
| 44073 | /* 123447 */ GIM_Try, /*On fail goto*//*Label 2429*/ GIMT_Encode4(123508), // Rule ID 3315 // |
| 44074 | /* 123452 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 44075 | /* 123455 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44076 | /* 123459 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44077 | /* 123463 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44078 | /* 123467 */ // (smax:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VMAXs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 44079 | /* 123467 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 44080 | /* 123470 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 44081 | /* 123474 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 44082 | /* 123479 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXs16), |
| 44083 | /* 123482 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 44084 | /* 123484 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 44085 | /* 123486 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 44086 | /* 123488 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44087 | /* 123491 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44088 | /* 123497 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44089 | /* 123503 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 44090 | /* 123506 */ GIR_RootConstrainSelectedInstOperands, |
| 44091 | /* 123507 */ // GIR_Coverage, 3315, |
| 44092 | /* 123507 */ GIR_EraseRootFromParent_Done, |
| 44093 | /* 123508 */ // Label 2429: @123508 |
| 44094 | /* 123508 */ GIM_Reject, |
| 44095 | /* 123509 */ // Label 2427: @123509 |
| 44096 | /* 123509 */ GIM_Reject, |
| 44097 | /* 123510 */ // Label 2419: @123510 |
| 44098 | /* 123510 */ GIM_Try, /*On fail goto*//*Label 2430*/ GIMT_Encode4(123623), |
| 44099 | /* 123515 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 44100 | /* 123518 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 44101 | /* 123521 */ GIM_Try, /*On fail goto*//*Label 2431*/ GIMT_Encode4(123561), // Rule ID 1202 // |
| 44102 | /* 123526 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 44103 | /* 123529 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 44104 | /* 123533 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 44105 | /* 123537 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 44106 | /* 123541 */ // (smax:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VMAXsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 44107 | /* 123541 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXsv16i8), |
| 44108 | /* 123544 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 44109 | /* 123546 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 44110 | /* 123548 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 44111 | /* 123550 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 44112 | /* 123553 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44113 | /* 123559 */ GIR_RootConstrainSelectedInstOperands, |
| 44114 | /* 123560 */ // GIR_Coverage, 1202, |
| 44115 | /* 123560 */ GIR_EraseRootFromParent_Done, |
| 44116 | /* 123561 */ // Label 2431: @123561 |
| 44117 | /* 123561 */ GIM_Try, /*On fail goto*//*Label 2432*/ GIMT_Encode4(123622), // Rule ID 3312 // |
| 44118 | /* 123566 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 44119 | /* 123569 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44120 | /* 123573 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44121 | /* 123577 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44122 | /* 123581 */ // (smax:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VMAXs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 44123 | /* 123581 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 44124 | /* 123584 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 44125 | /* 123588 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 44126 | /* 123593 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXs8), |
| 44127 | /* 123596 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 44128 | /* 123598 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 44129 | /* 123600 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 44130 | /* 123602 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44131 | /* 123605 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44132 | /* 123611 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44133 | /* 123617 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 44134 | /* 123620 */ GIR_RootConstrainSelectedInstOperands, |
| 44135 | /* 123621 */ // GIR_Coverage, 3312, |
| 44136 | /* 123621 */ GIR_EraseRootFromParent_Done, |
| 44137 | /* 123622 */ // Label 2432: @123622 |
| 44138 | /* 123622 */ GIM_Reject, |
| 44139 | /* 123623 */ // Label 2430: @123623 |
| 44140 | /* 123623 */ GIM_Reject, |
| 44141 | /* 123624 */ // Label 2420: @123624 |
| 44142 | /* 123624 */ GIM_Reject, |
| 44143 | /* 123625 */ // Label 57: @123625 |
| 44144 | /* 123625 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(16), /*)*//*default:*//*Label 2439*/ GIMT_Encode4(124545), |
| 44145 | /* 123636 */ /*GILLT_v2s32*//*Label 2433*/ GIMT_Encode4(123684), GIMT_Encode4(0), GIMT_Encode4(0), |
| 44146 | /* 123648 */ /*GILLT_v4s16*//*Label 2434*/ GIMT_Encode4(123731), |
| 44147 | /* 123652 */ /*GILLT_v4s32*//*Label 2435*/ GIMT_Encode4(123778), GIMT_Encode4(0), GIMT_Encode4(0), |
| 44148 | /* 123664 */ /*GILLT_v8s8*//*Label 2436*/ GIMT_Encode4(124018), |
| 44149 | /* 123668 */ /*GILLT_v8s16*//*Label 2437*/ GIMT_Encode4(124065), GIMT_Encode4(0), GIMT_Encode4(0), |
| 44150 | /* 123680 */ /*GILLT_v16s8*//*Label 2438*/ GIMT_Encode4(124305), |
| 44151 | /* 123684 */ // Label 2433: @123684 |
| 44152 | /* 123684 */ GIM_Try, /*On fail goto*//*Label 2440*/ GIMT_Encode4(123730), // Rule ID 1224 // |
| 44153 | /* 123689 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 44154 | /* 123692 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 44155 | /* 123695 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 44156 | /* 123698 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44157 | /* 123702 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44158 | /* 123706 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44159 | /* 123710 */ // (umin:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VMINuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 44160 | /* 123710 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINuv2i32), |
| 44161 | /* 123713 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 44162 | /* 123715 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 44163 | /* 123717 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 44164 | /* 123719 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 44165 | /* 123722 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44166 | /* 123728 */ GIR_RootConstrainSelectedInstOperands, |
| 44167 | /* 123729 */ // GIR_Coverage, 1224, |
| 44168 | /* 123729 */ GIR_EraseRootFromParent_Done, |
| 44169 | /* 123730 */ // Label 2440: @123730 |
| 44170 | /* 123730 */ GIM_Reject, |
| 44171 | /* 123731 */ // Label 2434: @123731 |
| 44172 | /* 123731 */ GIM_Try, /*On fail goto*//*Label 2441*/ GIMT_Encode4(123777), // Rule ID 1223 // |
| 44173 | /* 123736 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 44174 | /* 123739 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 44175 | /* 123742 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 44176 | /* 123745 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44177 | /* 123749 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44178 | /* 123753 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44179 | /* 123757 */ // (umin:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VMINuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 44180 | /* 123757 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINuv4i16), |
| 44181 | /* 123760 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 44182 | /* 123762 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 44183 | /* 123764 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 44184 | /* 123766 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 44185 | /* 123769 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44186 | /* 123775 */ GIR_RootConstrainSelectedInstOperands, |
| 44187 | /* 123776 */ // GIR_Coverage, 1223, |
| 44188 | /* 123776 */ GIR_EraseRootFromParent_Done, |
| 44189 | /* 123777 */ // Label 2441: @123777 |
| 44190 | /* 123777 */ GIM_Reject, |
| 44191 | /* 123778 */ // Label 2435: @123778 |
| 44192 | /* 123778 */ GIM_Try, /*On fail goto*//*Label 2442*/ GIMT_Encode4(124017), |
| 44193 | /* 123783 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 44194 | /* 123786 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 44195 | /* 123789 */ GIM_Try, /*On fail goto*//*Label 2443*/ GIMT_Encode4(123852), // Rule ID 6027 // |
| 44196 | /* 123794 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 44197 | /* 123797 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44198 | /* 123801 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 44199 | /* 123805 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS), |
| 44200 | /* 123809 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 44201 | /* 123813 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44202 | /* 123818 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44203 | /* 123822 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 44204 | /* 123824 */ // (umin:{ *:[v4i32] } (abs:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm), MQPR:{ *:[v4i32] }:$Qd) => (MVE_VMINAs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qd, MQPR:{ *:[v4i32] }:$Qm) |
| 44205 | /* 123824 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINAs32), |
| 44206 | /* 123827 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 44207 | /* 123829 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd |
| 44208 | /* 123831 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm |
| 44209 | /* 123835 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44210 | /* 123838 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44211 | /* 123844 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44212 | /* 123850 */ GIR_RootConstrainSelectedInstOperands, |
| 44213 | /* 123851 */ // GIR_Coverage, 6027, |
| 44214 | /* 123851 */ GIR_EraseRootFromParent_Done, |
| 44215 | /* 123852 */ // Label 2443: @123852 |
| 44216 | /* 123852 */ GIM_Try, /*On fail goto*//*Label 2444*/ GIMT_Encode4(123915), // Rule ID 3697 // |
| 44217 | /* 123857 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 44218 | /* 123860 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44219 | /* 123864 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44220 | /* 123868 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 44221 | /* 123872 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS), |
| 44222 | /* 123876 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 44223 | /* 123880 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44224 | /* 123885 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 44225 | /* 123887 */ // (umin:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qd, (abs:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm)) => (MVE_VMINAs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qd, MQPR:{ *:[v4i32] }:$Qm) |
| 44226 | /* 123887 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINAs32), |
| 44227 | /* 123890 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 44228 | /* 123892 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qd |
| 44229 | /* 123894 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm |
| 44230 | /* 123898 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44231 | /* 123901 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44232 | /* 123907 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44233 | /* 123913 */ GIR_RootConstrainSelectedInstOperands, |
| 44234 | /* 123914 */ // GIR_Coverage, 3697, |
| 44235 | /* 123914 */ GIR_EraseRootFromParent_Done, |
| 44236 | /* 123915 */ // Label 2444: @123915 |
| 44237 | /* 123915 */ GIM_Try, /*On fail goto*//*Label 2445*/ GIMT_Encode4(123955), // Rule ID 1226 // |
| 44238 | /* 123920 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 44239 | /* 123923 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 44240 | /* 123927 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 44241 | /* 123931 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 44242 | /* 123935 */ // (umin:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VMINuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 44243 | /* 123935 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINuv4i32), |
| 44244 | /* 123938 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 44245 | /* 123940 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 44246 | /* 123942 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 44247 | /* 123944 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 44248 | /* 123947 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44249 | /* 123953 */ GIR_RootConstrainSelectedInstOperands, |
| 44250 | /* 123954 */ // GIR_Coverage, 1226, |
| 44251 | /* 123954 */ GIR_EraseRootFromParent_Done, |
| 44252 | /* 123955 */ // Label 2445: @123955 |
| 44253 | /* 123955 */ GIM_Try, /*On fail goto*//*Label 2446*/ GIMT_Encode4(124016), // Rule ID 3309 // |
| 44254 | /* 123960 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 44255 | /* 123963 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44256 | /* 123967 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44257 | /* 123971 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44258 | /* 123975 */ // (umin:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VMINu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 44259 | /* 123975 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 44260 | /* 123978 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 44261 | /* 123982 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 44262 | /* 123987 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINu32), |
| 44263 | /* 123990 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 44264 | /* 123992 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 44265 | /* 123994 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 44266 | /* 123996 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44267 | /* 123999 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44268 | /* 124005 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44269 | /* 124011 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 44270 | /* 124014 */ GIR_RootConstrainSelectedInstOperands, |
| 44271 | /* 124015 */ // GIR_Coverage, 3309, |
| 44272 | /* 124015 */ GIR_EraseRootFromParent_Done, |
| 44273 | /* 124016 */ // Label 2446: @124016 |
| 44274 | /* 124016 */ GIM_Reject, |
| 44275 | /* 124017 */ // Label 2442: @124017 |
| 44276 | /* 124017 */ GIM_Reject, |
| 44277 | /* 124018 */ // Label 2436: @124018 |
| 44278 | /* 124018 */ GIM_Try, /*On fail goto*//*Label 2447*/ GIMT_Encode4(124064), // Rule ID 1227 // |
| 44279 | /* 124023 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 44280 | /* 124026 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 44281 | /* 124029 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 44282 | /* 124032 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44283 | /* 124036 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44284 | /* 124040 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44285 | /* 124044 */ // (umin:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VMINuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 44286 | /* 124044 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINuv8i8), |
| 44287 | /* 124047 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 44288 | /* 124049 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 44289 | /* 124051 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 44290 | /* 124053 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 44291 | /* 124056 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44292 | /* 124062 */ GIR_RootConstrainSelectedInstOperands, |
| 44293 | /* 124063 */ // GIR_Coverage, 1227, |
| 44294 | /* 124063 */ GIR_EraseRootFromParent_Done, |
| 44295 | /* 124064 */ // Label 2447: @124064 |
| 44296 | /* 124064 */ GIM_Reject, |
| 44297 | /* 124065 */ // Label 2437: @124065 |
| 44298 | /* 124065 */ GIM_Try, /*On fail goto*//*Label 2448*/ GIMT_Encode4(124304), |
| 44299 | /* 124070 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 44300 | /* 124073 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 44301 | /* 124076 */ GIM_Try, /*On fail goto*//*Label 2449*/ GIMT_Encode4(124139), // Rule ID 6026 // |
| 44302 | /* 124081 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 44303 | /* 124084 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44304 | /* 124088 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 44305 | /* 124092 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS), |
| 44306 | /* 124096 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 44307 | /* 124100 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44308 | /* 124105 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44309 | /* 124109 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 44310 | /* 124111 */ // (umin:{ *:[v8i16] } (abs:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm), MQPR:{ *:[v8i16] }:$Qd) => (MVE_VMINAs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd, MQPR:{ *:[v8i16] }:$Qm) |
| 44311 | /* 124111 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINAs16), |
| 44312 | /* 124114 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 44313 | /* 124116 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd |
| 44314 | /* 124118 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm |
| 44315 | /* 124122 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44316 | /* 124125 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44317 | /* 124131 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44318 | /* 124137 */ GIR_RootConstrainSelectedInstOperands, |
| 44319 | /* 124138 */ // GIR_Coverage, 6026, |
| 44320 | /* 124138 */ GIR_EraseRootFromParent_Done, |
| 44321 | /* 124139 */ // Label 2449: @124139 |
| 44322 | /* 124139 */ GIM_Try, /*On fail goto*//*Label 2450*/ GIMT_Encode4(124202), // Rule ID 3695 // |
| 44323 | /* 124144 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 44324 | /* 124147 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44325 | /* 124151 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44326 | /* 124155 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 44327 | /* 124159 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS), |
| 44328 | /* 124163 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 44329 | /* 124167 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44330 | /* 124172 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 44331 | /* 124174 */ // (umin:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd, (abs:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm)) => (MVE_VMINAs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd, MQPR:{ *:[v8i16] }:$Qm) |
| 44332 | /* 124174 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINAs16), |
| 44333 | /* 124177 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 44334 | /* 124179 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qd |
| 44335 | /* 124181 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm |
| 44336 | /* 124185 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44337 | /* 124188 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44338 | /* 124194 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44339 | /* 124200 */ GIR_RootConstrainSelectedInstOperands, |
| 44340 | /* 124201 */ // GIR_Coverage, 3695, |
| 44341 | /* 124201 */ GIR_EraseRootFromParent_Done, |
| 44342 | /* 124202 */ // Label 2450: @124202 |
| 44343 | /* 124202 */ GIM_Try, /*On fail goto*//*Label 2451*/ GIMT_Encode4(124242), // Rule ID 1225 // |
| 44344 | /* 124207 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 44345 | /* 124210 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 44346 | /* 124214 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 44347 | /* 124218 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 44348 | /* 124222 */ // (umin:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VMINuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 44349 | /* 124222 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINuv8i16), |
| 44350 | /* 124225 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 44351 | /* 124227 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 44352 | /* 124229 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 44353 | /* 124231 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 44354 | /* 124234 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44355 | /* 124240 */ GIR_RootConstrainSelectedInstOperands, |
| 44356 | /* 124241 */ // GIR_Coverage, 1225, |
| 44357 | /* 124241 */ GIR_EraseRootFromParent_Done, |
| 44358 | /* 124242 */ // Label 2451: @124242 |
| 44359 | /* 124242 */ GIM_Try, /*On fail goto*//*Label 2452*/ GIMT_Encode4(124303), // Rule ID 3306 // |
| 44360 | /* 124247 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 44361 | /* 124250 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44362 | /* 124254 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44363 | /* 124258 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44364 | /* 124262 */ // (umin:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VMINu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 44365 | /* 124262 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 44366 | /* 124265 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 44367 | /* 124269 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 44368 | /* 124274 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINu16), |
| 44369 | /* 124277 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 44370 | /* 124279 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 44371 | /* 124281 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 44372 | /* 124283 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44373 | /* 124286 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44374 | /* 124292 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44375 | /* 124298 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 44376 | /* 124301 */ GIR_RootConstrainSelectedInstOperands, |
| 44377 | /* 124302 */ // GIR_Coverage, 3306, |
| 44378 | /* 124302 */ GIR_EraseRootFromParent_Done, |
| 44379 | /* 124303 */ // Label 2452: @124303 |
| 44380 | /* 124303 */ GIM_Reject, |
| 44381 | /* 124304 */ // Label 2448: @124304 |
| 44382 | /* 124304 */ GIM_Reject, |
| 44383 | /* 124305 */ // Label 2438: @124305 |
| 44384 | /* 124305 */ GIM_Try, /*On fail goto*//*Label 2453*/ GIMT_Encode4(124544), |
| 44385 | /* 124310 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 44386 | /* 124313 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 44387 | /* 124316 */ GIM_Try, /*On fail goto*//*Label 2454*/ GIMT_Encode4(124379), // Rule ID 6025 // |
| 44388 | /* 124321 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 44389 | /* 124324 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44390 | /* 124328 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 44391 | /* 124332 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS), |
| 44392 | /* 124336 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, |
| 44393 | /* 124340 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44394 | /* 124345 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44395 | /* 124349 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 44396 | /* 124351 */ // (umin:{ *:[v16i8] } (abs:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm), MQPR:{ *:[v16i8] }:$Qd) => (MVE_VMINAs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd, MQPR:{ *:[v16i8] }:$Qm) |
| 44397 | /* 124351 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINAs8), |
| 44398 | /* 124354 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 44399 | /* 124356 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd |
| 44400 | /* 124358 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm |
| 44401 | /* 124362 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44402 | /* 124365 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44403 | /* 124371 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44404 | /* 124377 */ GIR_RootConstrainSelectedInstOperands, |
| 44405 | /* 124378 */ // GIR_Coverage, 6025, |
| 44406 | /* 124378 */ GIR_EraseRootFromParent_Done, |
| 44407 | /* 124379 */ // Label 2454: @124379 |
| 44408 | /* 124379 */ GIM_Try, /*On fail goto*//*Label 2455*/ GIMT_Encode4(124442), // Rule ID 3693 // |
| 44409 | /* 124384 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 44410 | /* 124387 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44411 | /* 124391 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44412 | /* 124395 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 44413 | /* 124399 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS), |
| 44414 | /* 124403 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, |
| 44415 | /* 124407 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44416 | /* 124412 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 44417 | /* 124414 */ // (umin:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd, (abs:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm)) => (MVE_VMINAs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd, MQPR:{ *:[v16i8] }:$Qm) |
| 44418 | /* 124414 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINAs8), |
| 44419 | /* 124417 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 44420 | /* 124419 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qd |
| 44421 | /* 124421 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm |
| 44422 | /* 124425 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44423 | /* 124428 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44424 | /* 124434 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44425 | /* 124440 */ GIR_RootConstrainSelectedInstOperands, |
| 44426 | /* 124441 */ // GIR_Coverage, 3693, |
| 44427 | /* 124441 */ GIR_EraseRootFromParent_Done, |
| 44428 | /* 124442 */ // Label 2455: @124442 |
| 44429 | /* 124442 */ GIM_Try, /*On fail goto*//*Label 2456*/ GIMT_Encode4(124482), // Rule ID 1228 // |
| 44430 | /* 124447 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 44431 | /* 124450 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 44432 | /* 124454 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 44433 | /* 124458 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 44434 | /* 124462 */ // (umin:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VMINuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 44435 | /* 124462 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINuv16i8), |
| 44436 | /* 124465 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 44437 | /* 124467 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 44438 | /* 124469 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 44439 | /* 124471 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 44440 | /* 124474 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44441 | /* 124480 */ GIR_RootConstrainSelectedInstOperands, |
| 44442 | /* 124481 */ // GIR_Coverage, 1228, |
| 44443 | /* 124481 */ GIR_EraseRootFromParent_Done, |
| 44444 | /* 124482 */ // Label 2456: @124482 |
| 44445 | /* 124482 */ GIM_Try, /*On fail goto*//*Label 2457*/ GIMT_Encode4(124543), // Rule ID 3303 // |
| 44446 | /* 124487 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 44447 | /* 124490 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44448 | /* 124494 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44449 | /* 124498 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44450 | /* 124502 */ // (umin:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VMINu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 44451 | /* 124502 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 44452 | /* 124505 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 44453 | /* 124509 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 44454 | /* 124514 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINu8), |
| 44455 | /* 124517 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 44456 | /* 124519 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 44457 | /* 124521 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 44458 | /* 124523 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44459 | /* 124526 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44460 | /* 124532 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44461 | /* 124538 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 44462 | /* 124541 */ GIR_RootConstrainSelectedInstOperands, |
| 44463 | /* 124542 */ // GIR_Coverage, 3303, |
| 44464 | /* 124542 */ GIR_EraseRootFromParent_Done, |
| 44465 | /* 124543 */ // Label 2457: @124543 |
| 44466 | /* 124543 */ GIM_Reject, |
| 44467 | /* 124544 */ // Label 2453: @124544 |
| 44468 | /* 124544 */ GIM_Reject, |
| 44469 | /* 124545 */ // Label 2439: @124545 |
| 44470 | /* 124545 */ GIM_Reject, |
| 44471 | /* 124546 */ // Label 58: @124546 |
| 44472 | /* 124546 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(16), /*)*//*default:*//*Label 2464*/ GIMT_Encode4(125466), |
| 44473 | /* 124557 */ /*GILLT_v2s32*//*Label 2458*/ GIMT_Encode4(124605), GIMT_Encode4(0), GIMT_Encode4(0), |
| 44474 | /* 124569 */ /*GILLT_v4s16*//*Label 2459*/ GIMT_Encode4(124652), |
| 44475 | /* 124573 */ /*GILLT_v4s32*//*Label 2460*/ GIMT_Encode4(124699), GIMT_Encode4(0), GIMT_Encode4(0), |
| 44476 | /* 124585 */ /*GILLT_v8s8*//*Label 2461*/ GIMT_Encode4(124939), |
| 44477 | /* 124589 */ /*GILLT_v8s16*//*Label 2462*/ GIMT_Encode4(124986), GIMT_Encode4(0), GIMT_Encode4(0), |
| 44478 | /* 124601 */ /*GILLT_v16s8*//*Label 2463*/ GIMT_Encode4(125226), |
| 44479 | /* 124605 */ // Label 2458: @124605 |
| 44480 | /* 124605 */ GIM_Try, /*On fail goto*//*Label 2465*/ GIMT_Encode4(124651), // Rule ID 1204 // |
| 44481 | /* 124610 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 44482 | /* 124613 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 44483 | /* 124616 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 44484 | /* 124619 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44485 | /* 124623 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44486 | /* 124627 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44487 | /* 124631 */ // (umax:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VMAXuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 44488 | /* 124631 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXuv2i32), |
| 44489 | /* 124634 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 44490 | /* 124636 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 44491 | /* 124638 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 44492 | /* 124640 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 44493 | /* 124643 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44494 | /* 124649 */ GIR_RootConstrainSelectedInstOperands, |
| 44495 | /* 124650 */ // GIR_Coverage, 1204, |
| 44496 | /* 124650 */ GIR_EraseRootFromParent_Done, |
| 44497 | /* 124651 */ // Label 2465: @124651 |
| 44498 | /* 124651 */ GIM_Reject, |
| 44499 | /* 124652 */ // Label 2459: @124652 |
| 44500 | /* 124652 */ GIM_Try, /*On fail goto*//*Label 2466*/ GIMT_Encode4(124698), // Rule ID 1203 // |
| 44501 | /* 124657 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 44502 | /* 124660 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 44503 | /* 124663 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 44504 | /* 124666 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44505 | /* 124670 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44506 | /* 124674 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44507 | /* 124678 */ // (umax:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VMAXuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 44508 | /* 124678 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXuv4i16), |
| 44509 | /* 124681 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 44510 | /* 124683 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 44511 | /* 124685 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 44512 | /* 124687 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 44513 | /* 124690 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44514 | /* 124696 */ GIR_RootConstrainSelectedInstOperands, |
| 44515 | /* 124697 */ // GIR_Coverage, 1203, |
| 44516 | /* 124697 */ GIR_EraseRootFromParent_Done, |
| 44517 | /* 124698 */ // Label 2466: @124698 |
| 44518 | /* 124698 */ GIM_Reject, |
| 44519 | /* 124699 */ // Label 2460: @124699 |
| 44520 | /* 124699 */ GIM_Try, /*On fail goto*//*Label 2467*/ GIMT_Encode4(124938), |
| 44521 | /* 124704 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 44522 | /* 124707 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 44523 | /* 124710 */ GIM_Try, /*On fail goto*//*Label 2468*/ GIMT_Encode4(124773), // Rule ID 6030 // |
| 44524 | /* 124715 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 44525 | /* 124718 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44526 | /* 124722 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 44527 | /* 124726 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS), |
| 44528 | /* 124730 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 44529 | /* 124734 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44530 | /* 124739 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44531 | /* 124743 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 44532 | /* 124745 */ // (umax:{ *:[v4i32] } (abs:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm), MQPR:{ *:[v4i32] }:$Qd) => (MVE_VMAXAs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qd, MQPR:{ *:[v4i32] }:$Qm) |
| 44533 | /* 124745 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXAs32), |
| 44534 | /* 124748 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 44535 | /* 124750 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd |
| 44536 | /* 124752 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm |
| 44537 | /* 124756 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44538 | /* 124759 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44539 | /* 124765 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44540 | /* 124771 */ GIR_RootConstrainSelectedInstOperands, |
| 44541 | /* 124772 */ // GIR_Coverage, 6030, |
| 44542 | /* 124772 */ GIR_EraseRootFromParent_Done, |
| 44543 | /* 124773 */ // Label 2468: @124773 |
| 44544 | /* 124773 */ GIM_Try, /*On fail goto*//*Label 2469*/ GIMT_Encode4(124836), // Rule ID 3703 // |
| 44545 | /* 124778 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 44546 | /* 124781 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44547 | /* 124785 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44548 | /* 124789 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 44549 | /* 124793 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS), |
| 44550 | /* 124797 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 44551 | /* 124801 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44552 | /* 124806 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 44553 | /* 124808 */ // (umax:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qd, (abs:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm)) => (MVE_VMAXAs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qd, MQPR:{ *:[v4i32] }:$Qm) |
| 44554 | /* 124808 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXAs32), |
| 44555 | /* 124811 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 44556 | /* 124813 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qd |
| 44557 | /* 124815 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm |
| 44558 | /* 124819 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44559 | /* 124822 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44560 | /* 124828 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44561 | /* 124834 */ GIR_RootConstrainSelectedInstOperands, |
| 44562 | /* 124835 */ // GIR_Coverage, 3703, |
| 44563 | /* 124835 */ GIR_EraseRootFromParent_Done, |
| 44564 | /* 124836 */ // Label 2469: @124836 |
| 44565 | /* 124836 */ GIM_Try, /*On fail goto*//*Label 2470*/ GIMT_Encode4(124876), // Rule ID 1206 // |
| 44566 | /* 124841 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 44567 | /* 124844 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 44568 | /* 124848 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 44569 | /* 124852 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 44570 | /* 124856 */ // (umax:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VMAXuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 44571 | /* 124856 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXuv4i32), |
| 44572 | /* 124859 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 44573 | /* 124861 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 44574 | /* 124863 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 44575 | /* 124865 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 44576 | /* 124868 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44577 | /* 124874 */ GIR_RootConstrainSelectedInstOperands, |
| 44578 | /* 124875 */ // GIR_Coverage, 1206, |
| 44579 | /* 124875 */ GIR_EraseRootFromParent_Done, |
| 44580 | /* 124876 */ // Label 2470: @124876 |
| 44581 | /* 124876 */ GIM_Try, /*On fail goto*//*Label 2471*/ GIMT_Encode4(124937), // Rule ID 3327 // |
| 44582 | /* 124881 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 44583 | /* 124884 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44584 | /* 124888 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44585 | /* 124892 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44586 | /* 124896 */ // (umax:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VMAXu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 44587 | /* 124896 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 44588 | /* 124899 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 44589 | /* 124903 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 44590 | /* 124908 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXu32), |
| 44591 | /* 124911 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 44592 | /* 124913 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 44593 | /* 124915 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 44594 | /* 124917 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44595 | /* 124920 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44596 | /* 124926 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44597 | /* 124932 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 44598 | /* 124935 */ GIR_RootConstrainSelectedInstOperands, |
| 44599 | /* 124936 */ // GIR_Coverage, 3327, |
| 44600 | /* 124936 */ GIR_EraseRootFromParent_Done, |
| 44601 | /* 124937 */ // Label 2471: @124937 |
| 44602 | /* 124937 */ GIM_Reject, |
| 44603 | /* 124938 */ // Label 2467: @124938 |
| 44604 | /* 124938 */ GIM_Reject, |
| 44605 | /* 124939 */ // Label 2461: @124939 |
| 44606 | /* 124939 */ GIM_Try, /*On fail goto*//*Label 2472*/ GIMT_Encode4(124985), // Rule ID 1207 // |
| 44607 | /* 124944 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 44608 | /* 124947 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 44609 | /* 124950 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 44610 | /* 124953 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44611 | /* 124957 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44612 | /* 124961 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44613 | /* 124965 */ // (umax:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VMAXuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 44614 | /* 124965 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXuv8i8), |
| 44615 | /* 124968 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 44616 | /* 124970 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 44617 | /* 124972 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 44618 | /* 124974 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 44619 | /* 124977 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44620 | /* 124983 */ GIR_RootConstrainSelectedInstOperands, |
| 44621 | /* 124984 */ // GIR_Coverage, 1207, |
| 44622 | /* 124984 */ GIR_EraseRootFromParent_Done, |
| 44623 | /* 124985 */ // Label 2472: @124985 |
| 44624 | /* 124985 */ GIM_Reject, |
| 44625 | /* 124986 */ // Label 2462: @124986 |
| 44626 | /* 124986 */ GIM_Try, /*On fail goto*//*Label 2473*/ GIMT_Encode4(125225), |
| 44627 | /* 124991 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 44628 | /* 124994 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 44629 | /* 124997 */ GIM_Try, /*On fail goto*//*Label 2474*/ GIMT_Encode4(125060), // Rule ID 6029 // |
| 44630 | /* 125002 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 44631 | /* 125005 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44632 | /* 125009 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 44633 | /* 125013 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS), |
| 44634 | /* 125017 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 44635 | /* 125021 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44636 | /* 125026 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44637 | /* 125030 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 44638 | /* 125032 */ // (umax:{ *:[v8i16] } (abs:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm), MQPR:{ *:[v8i16] }:$Qd) => (MVE_VMAXAs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd, MQPR:{ *:[v8i16] }:$Qm) |
| 44639 | /* 125032 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXAs16), |
| 44640 | /* 125035 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 44641 | /* 125037 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd |
| 44642 | /* 125039 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm |
| 44643 | /* 125043 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44644 | /* 125046 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44645 | /* 125052 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44646 | /* 125058 */ GIR_RootConstrainSelectedInstOperands, |
| 44647 | /* 125059 */ // GIR_Coverage, 6029, |
| 44648 | /* 125059 */ GIR_EraseRootFromParent_Done, |
| 44649 | /* 125060 */ // Label 2474: @125060 |
| 44650 | /* 125060 */ GIM_Try, /*On fail goto*//*Label 2475*/ GIMT_Encode4(125123), // Rule ID 3701 // |
| 44651 | /* 125065 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 44652 | /* 125068 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44653 | /* 125072 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44654 | /* 125076 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 44655 | /* 125080 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS), |
| 44656 | /* 125084 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 44657 | /* 125088 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44658 | /* 125093 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 44659 | /* 125095 */ // (umax:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd, (abs:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm)) => (MVE_VMAXAs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd, MQPR:{ *:[v8i16] }:$Qm) |
| 44660 | /* 125095 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXAs16), |
| 44661 | /* 125098 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 44662 | /* 125100 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qd |
| 44663 | /* 125102 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm |
| 44664 | /* 125106 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44665 | /* 125109 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44666 | /* 125115 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44667 | /* 125121 */ GIR_RootConstrainSelectedInstOperands, |
| 44668 | /* 125122 */ // GIR_Coverage, 3701, |
| 44669 | /* 125122 */ GIR_EraseRootFromParent_Done, |
| 44670 | /* 125123 */ // Label 2475: @125123 |
| 44671 | /* 125123 */ GIM_Try, /*On fail goto*//*Label 2476*/ GIMT_Encode4(125163), // Rule ID 1205 // |
| 44672 | /* 125128 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 44673 | /* 125131 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 44674 | /* 125135 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 44675 | /* 125139 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 44676 | /* 125143 */ // (umax:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VMAXuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 44677 | /* 125143 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXuv8i16), |
| 44678 | /* 125146 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 44679 | /* 125148 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 44680 | /* 125150 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 44681 | /* 125152 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 44682 | /* 125155 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44683 | /* 125161 */ GIR_RootConstrainSelectedInstOperands, |
| 44684 | /* 125162 */ // GIR_Coverage, 1205, |
| 44685 | /* 125162 */ GIR_EraseRootFromParent_Done, |
| 44686 | /* 125163 */ // Label 2476: @125163 |
| 44687 | /* 125163 */ GIM_Try, /*On fail goto*//*Label 2477*/ GIMT_Encode4(125224), // Rule ID 3324 // |
| 44688 | /* 125168 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 44689 | /* 125171 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44690 | /* 125175 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44691 | /* 125179 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44692 | /* 125183 */ // (umax:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VMAXu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 44693 | /* 125183 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 44694 | /* 125186 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 44695 | /* 125190 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 44696 | /* 125195 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXu16), |
| 44697 | /* 125198 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 44698 | /* 125200 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 44699 | /* 125202 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 44700 | /* 125204 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44701 | /* 125207 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44702 | /* 125213 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44703 | /* 125219 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 44704 | /* 125222 */ GIR_RootConstrainSelectedInstOperands, |
| 44705 | /* 125223 */ // GIR_Coverage, 3324, |
| 44706 | /* 125223 */ GIR_EraseRootFromParent_Done, |
| 44707 | /* 125224 */ // Label 2477: @125224 |
| 44708 | /* 125224 */ GIM_Reject, |
| 44709 | /* 125225 */ // Label 2473: @125225 |
| 44710 | /* 125225 */ GIM_Reject, |
| 44711 | /* 125226 */ // Label 2463: @125226 |
| 44712 | /* 125226 */ GIM_Try, /*On fail goto*//*Label 2478*/ GIMT_Encode4(125465), |
| 44713 | /* 125231 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 44714 | /* 125234 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 44715 | /* 125237 */ GIM_Try, /*On fail goto*//*Label 2479*/ GIMT_Encode4(125300), // Rule ID 6028 // |
| 44716 | /* 125242 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 44717 | /* 125245 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44718 | /* 125249 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 44719 | /* 125253 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS), |
| 44720 | /* 125257 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, |
| 44721 | /* 125261 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44722 | /* 125266 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44723 | /* 125270 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 44724 | /* 125272 */ // (umax:{ *:[v16i8] } (abs:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm), MQPR:{ *:[v16i8] }:$Qd) => (MVE_VMAXAs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd, MQPR:{ *:[v16i8] }:$Qm) |
| 44725 | /* 125272 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXAs8), |
| 44726 | /* 125275 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 44727 | /* 125277 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd |
| 44728 | /* 125279 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm |
| 44729 | /* 125283 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44730 | /* 125286 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44731 | /* 125292 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44732 | /* 125298 */ GIR_RootConstrainSelectedInstOperands, |
| 44733 | /* 125299 */ // GIR_Coverage, 6028, |
| 44734 | /* 125299 */ GIR_EraseRootFromParent_Done, |
| 44735 | /* 125300 */ // Label 2479: @125300 |
| 44736 | /* 125300 */ GIM_Try, /*On fail goto*//*Label 2480*/ GIMT_Encode4(125363), // Rule ID 3699 // |
| 44737 | /* 125305 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 44738 | /* 125308 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44739 | /* 125312 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44740 | /* 125316 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 44741 | /* 125320 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS), |
| 44742 | /* 125324 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, |
| 44743 | /* 125328 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44744 | /* 125333 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 44745 | /* 125335 */ // (umax:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd, (abs:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm)) => (MVE_VMAXAs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd, MQPR:{ *:[v16i8] }:$Qm) |
| 44746 | /* 125335 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXAs8), |
| 44747 | /* 125338 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 44748 | /* 125340 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qd |
| 44749 | /* 125342 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm |
| 44750 | /* 125346 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44751 | /* 125349 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44752 | /* 125355 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44753 | /* 125361 */ GIR_RootConstrainSelectedInstOperands, |
| 44754 | /* 125362 */ // GIR_Coverage, 3699, |
| 44755 | /* 125362 */ GIR_EraseRootFromParent_Done, |
| 44756 | /* 125363 */ // Label 2480: @125363 |
| 44757 | /* 125363 */ GIM_Try, /*On fail goto*//*Label 2481*/ GIMT_Encode4(125403), // Rule ID 1208 // |
| 44758 | /* 125368 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 44759 | /* 125371 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 44760 | /* 125375 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 44761 | /* 125379 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 44762 | /* 125383 */ // (umax:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VMAXuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 44763 | /* 125383 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXuv16i8), |
| 44764 | /* 125386 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 44765 | /* 125388 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 44766 | /* 125390 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 44767 | /* 125392 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 44768 | /* 125395 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44769 | /* 125401 */ GIR_RootConstrainSelectedInstOperands, |
| 44770 | /* 125402 */ // GIR_Coverage, 1208, |
| 44771 | /* 125402 */ GIR_EraseRootFromParent_Done, |
| 44772 | /* 125403 */ // Label 2481: @125403 |
| 44773 | /* 125403 */ GIM_Try, /*On fail goto*//*Label 2482*/ GIMT_Encode4(125464), // Rule ID 3321 // |
| 44774 | /* 125408 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 44775 | /* 125411 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44776 | /* 125415 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44777 | /* 125419 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44778 | /* 125423 */ // (umax:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VMAXu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 44779 | /* 125423 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 44780 | /* 125426 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 44781 | /* 125430 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 44782 | /* 125435 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXu8), |
| 44783 | /* 125438 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 44784 | /* 125440 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 44785 | /* 125442 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 44786 | /* 125444 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44787 | /* 125447 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44788 | /* 125453 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44789 | /* 125459 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 44790 | /* 125462 */ GIR_RootConstrainSelectedInstOperands, |
| 44791 | /* 125463 */ // GIR_Coverage, 3321, |
| 44792 | /* 125463 */ GIR_EraseRootFromParent_Done, |
| 44793 | /* 125464 */ // Label 2482: @125464 |
| 44794 | /* 125464 */ GIM_Reject, |
| 44795 | /* 125465 */ // Label 2478: @125465 |
| 44796 | /* 125465 */ GIM_Reject, |
| 44797 | /* 125466 */ // Label 2464: @125466 |
| 44798 | /* 125466 */ GIM_Reject, |
| 44799 | /* 125467 */ // Label 59: @125467 |
| 44800 | /* 125467 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(16), /*)*//*default:*//*Label 2489*/ GIMT_Encode4(125937), |
| 44801 | /* 125478 */ /*GILLT_v2s32*//*Label 2483*/ GIMT_Encode4(125526), GIMT_Encode4(0), GIMT_Encode4(0), |
| 44802 | /* 125490 */ /*GILLT_v4s16*//*Label 2484*/ GIMT_Encode4(125564), |
| 44803 | /* 125494 */ /*GILLT_v4s32*//*Label 2485*/ GIMT_Encode4(125602), GIMT_Encode4(0), GIMT_Encode4(0), |
| 44804 | /* 125506 */ /*GILLT_v8s8*//*Label 2486*/ GIMT_Encode4(125701), |
| 44805 | /* 125510 */ /*GILLT_v8s16*//*Label 2487*/ GIMT_Encode4(125739), GIMT_Encode4(0), GIMT_Encode4(0), |
| 44806 | /* 125522 */ /*GILLT_v16s8*//*Label 2488*/ GIMT_Encode4(125838), |
| 44807 | /* 125526 */ // Label 2483: @125526 |
| 44808 | /* 125526 */ GIM_Try, /*On fail goto*//*Label 2490*/ GIMT_Encode4(125563), // Rule ID 1510 // |
| 44809 | /* 125531 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 44810 | /* 125534 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 44811 | /* 125537 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44812 | /* 125541 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44813 | /* 125545 */ // (abs:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm) => (VABSv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm) |
| 44814 | /* 125545 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABSv2i32), |
| 44815 | /* 125548 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 44816 | /* 125550 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 44817 | /* 125552 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 44818 | /* 125555 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44819 | /* 125561 */ GIR_RootConstrainSelectedInstOperands, |
| 44820 | /* 125562 */ // GIR_Coverage, 1510, |
| 44821 | /* 125562 */ GIR_EraseRootFromParent_Done, |
| 44822 | /* 125563 */ // Label 2490: @125563 |
| 44823 | /* 125563 */ GIM_Reject, |
| 44824 | /* 125564 */ // Label 2484: @125564 |
| 44825 | /* 125564 */ GIM_Try, /*On fail goto*//*Label 2491*/ GIMT_Encode4(125601), // Rule ID 1509 // |
| 44826 | /* 125569 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 44827 | /* 125572 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 44828 | /* 125575 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44829 | /* 125579 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44830 | /* 125583 */ // (abs:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm) => (VABSv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm) |
| 44831 | /* 125583 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABSv4i16), |
| 44832 | /* 125586 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 44833 | /* 125588 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 44834 | /* 125590 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 44835 | /* 125593 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44836 | /* 125599 */ GIR_RootConstrainSelectedInstOperands, |
| 44837 | /* 125600 */ // GIR_Coverage, 1509, |
| 44838 | /* 125600 */ GIR_EraseRootFromParent_Done, |
| 44839 | /* 125601 */ // Label 2491: @125601 |
| 44840 | /* 125601 */ GIM_Reject, |
| 44841 | /* 125602 */ // Label 2485: @125602 |
| 44842 | /* 125602 */ GIM_Try, /*On fail goto*//*Label 2492*/ GIMT_Encode4(125700), |
| 44843 | /* 125607 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 44844 | /* 125610 */ GIM_Try, /*On fail goto*//*Label 2493*/ GIMT_Encode4(125644), // Rule ID 1513 // |
| 44845 | /* 125615 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 44846 | /* 125618 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 44847 | /* 125622 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 44848 | /* 125626 */ // (abs:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm) => (VABSv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm) |
| 44849 | /* 125626 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABSv4i32), |
| 44850 | /* 125629 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 44851 | /* 125631 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 44852 | /* 125633 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 44853 | /* 125636 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44854 | /* 125642 */ GIR_RootConstrainSelectedInstOperands, |
| 44855 | /* 125643 */ // GIR_Coverage, 1513, |
| 44856 | /* 125643 */ GIR_EraseRootFromParent_Done, |
| 44857 | /* 125644 */ // Label 2493: @125644 |
| 44858 | /* 125644 */ GIM_Try, /*On fail goto*//*Label 2494*/ GIMT_Encode4(125699), // Rule ID 3672 // |
| 44859 | /* 125649 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 44860 | /* 125652 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44861 | /* 125656 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44862 | /* 125660 */ // (abs:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$v) => (MVE_VABSs32:{ *:[v4i32] } ?:{ *:[v4i32] }:$v) |
| 44863 | /* 125660 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 44864 | /* 125663 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 44865 | /* 125667 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 44866 | /* 125672 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABSs32), |
| 44867 | /* 125675 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 44868 | /* 125677 */ GIR_RootToRootCopy, /*OpIdx*/1, // v |
| 44869 | /* 125679 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44870 | /* 125682 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44871 | /* 125688 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44872 | /* 125694 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 44873 | /* 125697 */ GIR_RootConstrainSelectedInstOperands, |
| 44874 | /* 125698 */ // GIR_Coverage, 3672, |
| 44875 | /* 125698 */ GIR_EraseRootFromParent_Done, |
| 44876 | /* 125699 */ // Label 2494: @125699 |
| 44877 | /* 125699 */ GIM_Reject, |
| 44878 | /* 125700 */ // Label 2492: @125700 |
| 44879 | /* 125700 */ GIM_Reject, |
| 44880 | /* 125701 */ // Label 2486: @125701 |
| 44881 | /* 125701 */ GIM_Try, /*On fail goto*//*Label 2495*/ GIMT_Encode4(125738), // Rule ID 1508 // |
| 44882 | /* 125706 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 44883 | /* 125709 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 44884 | /* 125712 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44885 | /* 125716 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44886 | /* 125720 */ // (abs:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm) => (VABSv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm) |
| 44887 | /* 125720 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABSv8i8), |
| 44888 | /* 125723 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 44889 | /* 125725 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 44890 | /* 125727 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 44891 | /* 125730 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44892 | /* 125736 */ GIR_RootConstrainSelectedInstOperands, |
| 44893 | /* 125737 */ // GIR_Coverage, 1508, |
| 44894 | /* 125737 */ GIR_EraseRootFromParent_Done, |
| 44895 | /* 125738 */ // Label 2495: @125738 |
| 44896 | /* 125738 */ GIM_Reject, |
| 44897 | /* 125739 */ // Label 2487: @125739 |
| 44898 | /* 125739 */ GIM_Try, /*On fail goto*//*Label 2496*/ GIMT_Encode4(125837), |
| 44899 | /* 125744 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 44900 | /* 125747 */ GIM_Try, /*On fail goto*//*Label 2497*/ GIMT_Encode4(125781), // Rule ID 1512 // |
| 44901 | /* 125752 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 44902 | /* 125755 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 44903 | /* 125759 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 44904 | /* 125763 */ // (abs:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm) => (VABSv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm) |
| 44905 | /* 125763 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABSv8i16), |
| 44906 | /* 125766 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 44907 | /* 125768 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 44908 | /* 125770 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 44909 | /* 125773 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44910 | /* 125779 */ GIR_RootConstrainSelectedInstOperands, |
| 44911 | /* 125780 */ // GIR_Coverage, 1512, |
| 44912 | /* 125780 */ GIR_EraseRootFromParent_Done, |
| 44913 | /* 125781 */ // Label 2497: @125781 |
| 44914 | /* 125781 */ GIM_Try, /*On fail goto*//*Label 2498*/ GIMT_Encode4(125836), // Rule ID 3666 // |
| 44915 | /* 125786 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 44916 | /* 125789 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44917 | /* 125793 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44918 | /* 125797 */ // (abs:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$v) => (MVE_VABSs16:{ *:[v8i16] } ?:{ *:[v8i16] }:$v) |
| 44919 | /* 125797 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 44920 | /* 125800 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 44921 | /* 125804 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 44922 | /* 125809 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABSs16), |
| 44923 | /* 125812 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 44924 | /* 125814 */ GIR_RootToRootCopy, /*OpIdx*/1, // v |
| 44925 | /* 125816 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44926 | /* 125819 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44927 | /* 125825 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44928 | /* 125831 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 44929 | /* 125834 */ GIR_RootConstrainSelectedInstOperands, |
| 44930 | /* 125835 */ // GIR_Coverage, 3666, |
| 44931 | /* 125835 */ GIR_EraseRootFromParent_Done, |
| 44932 | /* 125836 */ // Label 2498: @125836 |
| 44933 | /* 125836 */ GIM_Reject, |
| 44934 | /* 125837 */ // Label 2496: @125837 |
| 44935 | /* 125837 */ GIM_Reject, |
| 44936 | /* 125838 */ // Label 2488: @125838 |
| 44937 | /* 125838 */ GIM_Try, /*On fail goto*//*Label 2499*/ GIMT_Encode4(125936), |
| 44938 | /* 125843 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 44939 | /* 125846 */ GIM_Try, /*On fail goto*//*Label 2500*/ GIMT_Encode4(125880), // Rule ID 1511 // |
| 44940 | /* 125851 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 44941 | /* 125854 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 44942 | /* 125858 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 44943 | /* 125862 */ // (abs:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm) => (VABSv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm) |
| 44944 | /* 125862 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABSv16i8), |
| 44945 | /* 125865 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 44946 | /* 125867 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 44947 | /* 125869 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 44948 | /* 125872 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44949 | /* 125878 */ GIR_RootConstrainSelectedInstOperands, |
| 44950 | /* 125879 */ // GIR_Coverage, 1511, |
| 44951 | /* 125879 */ GIR_EraseRootFromParent_Done, |
| 44952 | /* 125880 */ // Label 2500: @125880 |
| 44953 | /* 125880 */ GIM_Try, /*On fail goto*//*Label 2501*/ GIMT_Encode4(125935), // Rule ID 3660 // |
| 44954 | /* 125885 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 44955 | /* 125888 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44956 | /* 125892 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44957 | /* 125896 */ // (abs:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$v) => (MVE_VABSs8:{ *:[v16i8] } ?:{ *:[v16i8] }:$v) |
| 44958 | /* 125896 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 44959 | /* 125899 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 44960 | /* 125903 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 44961 | /* 125908 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABSs8), |
| 44962 | /* 125911 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 44963 | /* 125913 */ GIR_RootToRootCopy, /*OpIdx*/1, // v |
| 44964 | /* 125915 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44965 | /* 125918 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44966 | /* 125924 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44967 | /* 125930 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 44968 | /* 125933 */ GIR_RootConstrainSelectedInstOperands, |
| 44969 | /* 125934 */ // GIR_Coverage, 3660, |
| 44970 | /* 125934 */ GIR_EraseRootFromParent_Done, |
| 44971 | /* 125935 */ // Label 2501: @125935 |
| 44972 | /* 125935 */ GIM_Reject, |
| 44973 | /* 125936 */ // Label 2499: @125936 |
| 44974 | /* 125936 */ GIM_Reject, |
| 44975 | /* 125937 */ // Label 2489: @125937 |
| 44976 | /* 125937 */ GIM_Reject, |
| 44977 | /* 125938 */ // Label 60: @125938 |
| 44978 | /* 125938 */ GIM_Try, /*On fail goto*//*Label 2502*/ GIMT_Encode4(126010), |
| 44979 | /* 125943 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/0, |
| 44980 | /* 125946 */ GIM_Try, /*On fail goto*//*Label 2503*/ GIMT_Encode4(125961), // Rule ID 32 // |
| 44981 | /* 125951 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM), |
| 44982 | /* 125954 */ // (br (bb:{ *:[Other] }):$target) => (B (bb:{ *:[Other] }):$target) |
| 44983 | /* 125954 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::B), |
| 44984 | /* 125959 */ GIR_RootConstrainSelectedInstOperands, |
| 44985 | /* 125960 */ // GIR_Coverage, 32, |
| 44986 | /* 125960 */ GIR_Done, |
| 44987 | /* 125961 */ // Label 2503: @125961 |
| 44988 | /* 125961 */ GIM_Try, /*On fail goto*//*Label 2504*/ GIMT_Encode4(125985), // Rule ID 283 // |
| 44989 | /* 125966 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), |
| 44990 | /* 125969 */ // (br (bb:{ *:[Other] }):$target) => (tB (bb:{ *:[Other] }):$target) |
| 44991 | /* 125969 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tB), |
| 44992 | /* 125972 */ GIR_RootToRootCopy, /*OpIdx*/0, // target |
| 44993 | /* 125974 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 44994 | /* 125977 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44995 | /* 125983 */ GIR_RootConstrainSelectedInstOperands, |
| 44996 | /* 125984 */ // GIR_Coverage, 283, |
| 44997 | /* 125984 */ GIR_EraseRootFromParent_Done, |
| 44998 | /* 125985 */ // Label 2504: @125985 |
| 44999 | /* 125985 */ GIM_Try, /*On fail goto*//*Label 2505*/ GIMT_Encode4(126009), // Rule ID 577 // |
| 45000 | /* 125990 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV8MBaseline_IsThumb), |
| 45001 | /* 125993 */ // (br (bb:{ *:[Other] }):$target) => (t2B (bb:{ *:[Other] }):$target) |
| 45002 | /* 125993 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2B), |
| 45003 | /* 125996 */ GIR_RootToRootCopy, /*OpIdx*/0, // target |
| 45004 | /* 125998 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 45005 | /* 126001 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45006 | /* 126007 */ GIR_RootConstrainSelectedInstOperands, |
| 45007 | /* 126008 */ // GIR_Coverage, 577, |
| 45008 | /* 126008 */ GIR_EraseRootFromParent_Done, |
| 45009 | /* 126009 */ // Label 2505: @126009 |
| 45010 | /* 126009 */ GIM_Reject, |
| 45011 | /* 126010 */ // Label 2502: @126010 |
| 45012 | /* 126010 */ GIM_Reject, |
| 45013 | /* 126011 */ // Label 61: @126011 |
| 45014 | /* 126011 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(16), /*)*//*default:*//*Label 2510*/ GIMT_Encode4(126310), |
| 45015 | /* 126022 */ /*GILLT_v4s16*//*Label 2506*/ GIMT_Encode4(126058), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 45016 | /* 126038 */ /*GILLT_v8s8*//*Label 2507*/ GIMT_Encode4(126121), |
| 45017 | /* 126042 */ /*GILLT_v8s16*//*Label 2508*/ GIMT_Encode4(126184), GIMT_Encode4(0), GIMT_Encode4(0), |
| 45018 | /* 126054 */ /*GILLT_v16s8*//*Label 2509*/ GIMT_Encode4(126247), |
| 45019 | /* 126058 */ // Label 2506: @126058 |
| 45020 | /* 126058 */ GIM_Try, /*On fail goto*//*Label 2511*/ GIMT_Encode4(126120), // Rule ID 1572 // |
| 45021 | /* 126063 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 45022 | /* 126066 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 45023 | /* 126069 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 45024 | /* 126072 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 45025 | /* 126075 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45026 | /* 126079 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45027 | /* 126083 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 45028 | /* 126087 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 45029 | /* 126091 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 45030 | /* 126095 */ // MIs[1] Operand 1 |
| 45031 | /* 126095 */ // No operand predicates |
| 45032 | /* 126095 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 45033 | /* 126097 */ // (vector_insert:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, GPR:{ *:[i32] }:$R, (imm:{ *:[i32] }):$lane) => (VSETLNi16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, GPR:{ *:[i32] }:$R, (imm:{ *:[i32] }):$lane) |
| 45034 | /* 126097 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSETLNi16), |
| 45035 | /* 126100 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[V] |
| 45036 | /* 126102 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 45037 | /* 126104 */ GIR_RootToRootCopy, /*OpIdx*/2, // R |
| 45038 | /* 126106 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // lane |
| 45039 | /* 126109 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 45040 | /* 126112 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45041 | /* 126118 */ GIR_RootConstrainSelectedInstOperands, |
| 45042 | /* 126119 */ // GIR_Coverage, 1572, |
| 45043 | /* 126119 */ GIR_EraseRootFromParent_Done, |
| 45044 | /* 126120 */ // Label 2511: @126120 |
| 45045 | /* 126120 */ GIM_Reject, |
| 45046 | /* 126121 */ // Label 2507: @126121 |
| 45047 | /* 126121 */ GIM_Try, /*On fail goto*//*Label 2512*/ GIMT_Encode4(126183), // Rule ID 1571 // |
| 45048 | /* 126126 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 45049 | /* 126129 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 45050 | /* 126132 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 45051 | /* 126135 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 45052 | /* 126138 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45053 | /* 126142 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45054 | /* 126146 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 45055 | /* 126150 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 45056 | /* 126154 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 45057 | /* 126158 */ // MIs[1] Operand 1 |
| 45058 | /* 126158 */ // No operand predicates |
| 45059 | /* 126158 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 45060 | /* 126160 */ // (vector_insert:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, GPR:{ *:[i32] }:$R, (imm:{ *:[i32] }):$lane) => (VSETLNi8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, GPR:{ *:[i32] }:$R, (imm:{ *:[i32] }):$lane) |
| 45061 | /* 126160 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSETLNi8), |
| 45062 | /* 126163 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[V] |
| 45063 | /* 126165 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 45064 | /* 126167 */ GIR_RootToRootCopy, /*OpIdx*/2, // R |
| 45065 | /* 126169 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // lane |
| 45066 | /* 126172 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 45067 | /* 126175 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45068 | /* 126181 */ GIR_RootConstrainSelectedInstOperands, |
| 45069 | /* 126182 */ // GIR_Coverage, 1571, |
| 45070 | /* 126182 */ GIR_EraseRootFromParent_Done, |
| 45071 | /* 126183 */ // Label 2512: @126183 |
| 45072 | /* 126183 */ GIM_Reject, |
| 45073 | /* 126184 */ // Label 2508: @126184 |
| 45074 | /* 126184 */ GIM_Try, /*On fail goto*//*Label 2513*/ GIMT_Encode4(126246), // Rule ID 3436 // |
| 45075 | /* 126189 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 45076 | /* 126192 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 45077 | /* 126195 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 45078 | /* 126198 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 45079 | /* 126201 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45080 | /* 126205 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45081 | /* 126209 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 45082 | /* 126213 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 45083 | /* 126217 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 45084 | /* 126221 */ // MIs[1] Operand 1 |
| 45085 | /* 126221 */ // No operand predicates |
| 45086 | /* 126221 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 45087 | /* 126223 */ // (vector_insert:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] }):$lane) => (MVE_VMOV_to_lane_16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] }):$lane) |
| 45088 | /* 126223 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMOV_to_lane_16), |
| 45089 | /* 126226 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 45090 | /* 126228 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 45091 | /* 126230 */ GIR_RootToRootCopy, /*OpIdx*/2, // src2 |
| 45092 | /* 126232 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // lane |
| 45093 | /* 126235 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 45094 | /* 126238 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45095 | /* 126244 */ GIR_RootConstrainSelectedInstOperands, |
| 45096 | /* 126245 */ // GIR_Coverage, 3436, |
| 45097 | /* 126245 */ GIR_EraseRootFromParent_Done, |
| 45098 | /* 126246 */ // Label 2513: @126246 |
| 45099 | /* 126246 */ GIM_Reject, |
| 45100 | /* 126247 */ // Label 2509: @126247 |
| 45101 | /* 126247 */ GIM_Try, /*On fail goto*//*Label 2514*/ GIMT_Encode4(126309), // Rule ID 3435 // |
| 45102 | /* 126252 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 45103 | /* 126255 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 45104 | /* 126258 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 45105 | /* 126261 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 45106 | /* 126264 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45107 | /* 126268 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45108 | /* 126272 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 45109 | /* 126276 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 45110 | /* 126280 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 45111 | /* 126284 */ // MIs[1] Operand 1 |
| 45112 | /* 126284 */ // No operand predicates |
| 45113 | /* 126284 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 45114 | /* 126286 */ // (vector_insert:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] }):$lane) => (MVE_VMOV_to_lane_8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] }):$lane) |
| 45115 | /* 126286 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMOV_to_lane_8), |
| 45116 | /* 126289 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 45117 | /* 126291 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 45118 | /* 126293 */ GIR_RootToRootCopy, /*OpIdx*/2, // src2 |
| 45119 | /* 126295 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // lane |
| 45120 | /* 126298 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 45121 | /* 126301 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45122 | /* 126307 */ GIR_RootConstrainSelectedInstOperands, |
| 45123 | /* 126308 */ // GIR_Coverage, 3435, |
| 45124 | /* 126308 */ GIR_EraseRootFromParent_Done, |
| 45125 | /* 126309 */ // Label 2514: @126309 |
| 45126 | /* 126309 */ GIM_Reject, |
| 45127 | /* 126310 */ // Label 2510: @126310 |
| 45128 | /* 126310 */ GIM_Reject, |
| 45129 | /* 126311 */ // Label 62: @126311 |
| 45130 | /* 126311 */ GIM_Try, /*On fail goto*//*Label 2515*/ GIMT_Encode4(126367), // Rule ID 1570 // |
| 45131 | /* 126316 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRegs_HasFastVGETLNi32), |
| 45132 | /* 126319 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 45133 | /* 126322 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 45134 | /* 126325 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 45135 | /* 126328 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 45136 | /* 126332 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45137 | /* 126336 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 45138 | /* 126340 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 45139 | /* 126344 */ // MIs[1] Operand 1 |
| 45140 | /* 126344 */ // No operand predicates |
| 45141 | /* 126344 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 45142 | /* 126346 */ // (extractelt:{ *:[i32] } DPR:{ *:[v2i32] }:$V, (imm:{ *:[i32] }):$lane) => (VGETLNi32:{ *:[i32] } DPR:{ *:[v2i32] }:$V, (imm:{ *:[i32] }):$lane) |
| 45143 | /* 126346 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VGETLNi32), |
| 45144 | /* 126349 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[R] |
| 45145 | /* 126351 */ GIR_RootToRootCopy, /*OpIdx*/1, // V |
| 45146 | /* 126353 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // lane |
| 45147 | /* 126356 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 45148 | /* 126359 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45149 | /* 126365 */ GIR_RootConstrainSelectedInstOperands, |
| 45150 | /* 126366 */ // GIR_Coverage, 1570, |
| 45151 | /* 126366 */ GIR_EraseRootFromParent_Done, |
| 45152 | /* 126367 */ // Label 2515: @126367 |
| 45153 | /* 126367 */ GIM_Reject, |
| 45154 | /* 126368 */ // Label 63: @126368 |
| 45155 | /* 126368 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(16), /*)*//*default:*//*Label 2523*/ GIMT_Encode4(126928), |
| 45156 | /* 126379 */ /*GILLT_s32*//*Label 2516*/ GIMT_Encode4(126439), GIMT_Encode4(0), GIMT_Encode4(0), |
| 45157 | /* 126391 */ /*GILLT_v2s32*//*Label 2517*/ GIMT_Encode4(126517), GIMT_Encode4(0), GIMT_Encode4(0), |
| 45158 | /* 126403 */ /*GILLT_v4s16*//*Label 2518*/ GIMT_Encode4(126555), |
| 45159 | /* 126407 */ /*GILLT_v4s32*//*Label 2519*/ GIMT_Encode4(126593), GIMT_Encode4(0), GIMT_Encode4(0), |
| 45160 | /* 126419 */ /*GILLT_v8s8*//*Label 2520*/ GIMT_Encode4(126692), |
| 45161 | /* 126423 */ /*GILLT_v8s16*//*Label 2521*/ GIMT_Encode4(126730), GIMT_Encode4(0), GIMT_Encode4(0), |
| 45162 | /* 126435 */ /*GILLT_v16s8*//*Label 2522*/ GIMT_Encode4(126829), |
| 45163 | /* 126439 */ // Label 2516: @126439 |
| 45164 | /* 126439 */ GIM_Try, /*On fail goto*//*Label 2524*/ GIMT_Encode4(126516), |
| 45165 | /* 126444 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 45166 | /* 126447 */ GIM_Try, /*On fail goto*//*Label 2525*/ GIMT_Encode4(126481), // Rule ID 197 // |
| 45167 | /* 126452 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5T_IsARM), |
| 45168 | /* 126455 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 45169 | /* 126459 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 45170 | /* 126463 */ // (ctlz:{ *:[i32] } GPR:{ *:[i32] }:$Rm) => (CLZ:{ *:[i32] } GPR:{ *:[i32] }:$Rm) |
| 45171 | /* 126463 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::CLZ), |
| 45172 | /* 126466 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 45173 | /* 126468 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 45174 | /* 126470 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 45175 | /* 126473 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45176 | /* 126479 */ GIR_RootConstrainSelectedInstOperands, |
| 45177 | /* 126480 */ // GIR_Coverage, 197, |
| 45178 | /* 126480 */ GIR_EraseRootFromParent_Done, |
| 45179 | /* 126481 */ // Label 2525: @126481 |
| 45180 | /* 126481 */ GIM_Try, /*On fail goto*//*Label 2526*/ GIMT_Encode4(126515), // Rule ID 534 // |
| 45181 | /* 126486 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 45182 | /* 126489 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 45183 | /* 126493 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 45184 | /* 126497 */ // (ctlz:{ *:[i32] } rGPR:{ *:[i32] }:$Rm) => (t2CLZ:{ *:[i32] } rGPR:{ *:[i32] }:$Rm) |
| 45185 | /* 126497 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2CLZ), |
| 45186 | /* 126500 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 45187 | /* 126502 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 45188 | /* 126504 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 45189 | /* 126507 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45190 | /* 126513 */ GIR_RootConstrainSelectedInstOperands, |
| 45191 | /* 126514 */ // GIR_Coverage, 534, |
| 45192 | /* 126514 */ GIR_EraseRootFromParent_Done, |
| 45193 | /* 126515 */ // Label 2526: @126515 |
| 45194 | /* 126515 */ GIM_Reject, |
| 45195 | /* 126516 */ // Label 2524: @126516 |
| 45196 | /* 126516 */ GIM_Reject, |
| 45197 | /* 126517 */ // Label 2517: @126517 |
| 45198 | /* 126517 */ GIM_Try, /*On fail goto*//*Label 2527*/ GIMT_Encode4(126554), // Rule ID 1548 // |
| 45199 | /* 126522 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 45200 | /* 126525 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 45201 | /* 126528 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45202 | /* 126532 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45203 | /* 126536 */ // (ctlz:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm) => (VCLZv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm) |
| 45204 | /* 126536 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCLZv2i32), |
| 45205 | /* 126539 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 45206 | /* 126541 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 45207 | /* 126543 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 45208 | /* 126546 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45209 | /* 126552 */ GIR_RootConstrainSelectedInstOperands, |
| 45210 | /* 126553 */ // GIR_Coverage, 1548, |
| 45211 | /* 126553 */ GIR_EraseRootFromParent_Done, |
| 45212 | /* 126554 */ // Label 2527: @126554 |
| 45213 | /* 126554 */ GIM_Reject, |
| 45214 | /* 126555 */ // Label 2518: @126555 |
| 45215 | /* 126555 */ GIM_Try, /*On fail goto*//*Label 2528*/ GIMT_Encode4(126592), // Rule ID 1547 // |
| 45216 | /* 126560 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 45217 | /* 126563 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 45218 | /* 126566 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45219 | /* 126570 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45220 | /* 126574 */ // (ctlz:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm) => (VCLZv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm) |
| 45221 | /* 126574 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCLZv4i16), |
| 45222 | /* 126577 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 45223 | /* 126579 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 45224 | /* 126581 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 45225 | /* 126584 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45226 | /* 126590 */ GIR_RootConstrainSelectedInstOperands, |
| 45227 | /* 126591 */ // GIR_Coverage, 1547, |
| 45228 | /* 126591 */ GIR_EraseRootFromParent_Done, |
| 45229 | /* 126592 */ // Label 2528: @126592 |
| 45230 | /* 126592 */ GIM_Reject, |
| 45231 | /* 126593 */ // Label 2519: @126593 |
| 45232 | /* 126593 */ GIM_Try, /*On fail goto*//*Label 2529*/ GIMT_Encode4(126691), |
| 45233 | /* 126598 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 45234 | /* 126601 */ GIM_Try, /*On fail goto*//*Label 2530*/ GIMT_Encode4(126635), // Rule ID 1551 // |
| 45235 | /* 126606 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 45236 | /* 126609 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 45237 | /* 126613 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 45238 | /* 126617 */ // (ctlz:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm) => (VCLZv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm) |
| 45239 | /* 126617 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCLZv4i32), |
| 45240 | /* 126620 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 45241 | /* 126622 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 45242 | /* 126624 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 45243 | /* 126627 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45244 | /* 126633 */ GIR_RootConstrainSelectedInstOperands, |
| 45245 | /* 126634 */ // GIR_Coverage, 1551, |
| 45246 | /* 126634 */ GIR_EraseRootFromParent_Done, |
| 45247 | /* 126635 */ // Label 2530: @126635 |
| 45248 | /* 126635 */ GIM_Try, /*On fail goto*//*Label 2531*/ GIMT_Encode4(126690), // Rule ID 3658 // |
| 45249 | /* 126640 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 45250 | /* 126643 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45251 | /* 126647 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45252 | /* 126651 */ // (ctlz:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$val) => (MVE_VCLZs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$val) |
| 45253 | /* 126651 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 45254 | /* 126654 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 45255 | /* 126658 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 45256 | /* 126663 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCLZs32), |
| 45257 | /* 126666 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 45258 | /* 126668 */ GIR_RootToRootCopy, /*OpIdx*/1, // val |
| 45259 | /* 126670 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45260 | /* 126673 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45261 | /* 126679 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45262 | /* 126685 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45263 | /* 126688 */ GIR_RootConstrainSelectedInstOperands, |
| 45264 | /* 126689 */ // GIR_Coverage, 3658, |
| 45265 | /* 126689 */ GIR_EraseRootFromParent_Done, |
| 45266 | /* 126690 */ // Label 2531: @126690 |
| 45267 | /* 126690 */ GIM_Reject, |
| 45268 | /* 126691 */ // Label 2529: @126691 |
| 45269 | /* 126691 */ GIM_Reject, |
| 45270 | /* 126692 */ // Label 2520: @126692 |
| 45271 | /* 126692 */ GIM_Try, /*On fail goto*//*Label 2532*/ GIMT_Encode4(126729), // Rule ID 1546 // |
| 45272 | /* 126697 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 45273 | /* 126700 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 45274 | /* 126703 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45275 | /* 126707 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45276 | /* 126711 */ // (ctlz:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm) => (VCLZv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm) |
| 45277 | /* 126711 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCLZv8i8), |
| 45278 | /* 126714 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 45279 | /* 126716 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 45280 | /* 126718 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 45281 | /* 126721 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45282 | /* 126727 */ GIR_RootConstrainSelectedInstOperands, |
| 45283 | /* 126728 */ // GIR_Coverage, 1546, |
| 45284 | /* 126728 */ GIR_EraseRootFromParent_Done, |
| 45285 | /* 126729 */ // Label 2532: @126729 |
| 45286 | /* 126729 */ GIM_Reject, |
| 45287 | /* 126730 */ // Label 2521: @126730 |
| 45288 | /* 126730 */ GIM_Try, /*On fail goto*//*Label 2533*/ GIMT_Encode4(126828), |
| 45289 | /* 126735 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 45290 | /* 126738 */ GIM_Try, /*On fail goto*//*Label 2534*/ GIMT_Encode4(126772), // Rule ID 1550 // |
| 45291 | /* 126743 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 45292 | /* 126746 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 45293 | /* 126750 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 45294 | /* 126754 */ // (ctlz:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm) => (VCLZv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm) |
| 45295 | /* 126754 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCLZv8i16), |
| 45296 | /* 126757 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 45297 | /* 126759 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 45298 | /* 126761 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 45299 | /* 126764 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45300 | /* 126770 */ GIR_RootConstrainSelectedInstOperands, |
| 45301 | /* 126771 */ // GIR_Coverage, 1550, |
| 45302 | /* 126771 */ GIR_EraseRootFromParent_Done, |
| 45303 | /* 126772 */ // Label 2534: @126772 |
| 45304 | /* 126772 */ GIM_Try, /*On fail goto*//*Label 2535*/ GIMT_Encode4(126827), // Rule ID 3656 // |
| 45305 | /* 126777 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 45306 | /* 126780 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45307 | /* 126784 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45308 | /* 126788 */ // (ctlz:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$val) => (MVE_VCLZs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$val) |
| 45309 | /* 126788 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 45310 | /* 126791 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 45311 | /* 126795 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 45312 | /* 126800 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCLZs16), |
| 45313 | /* 126803 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 45314 | /* 126805 */ GIR_RootToRootCopy, /*OpIdx*/1, // val |
| 45315 | /* 126807 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45316 | /* 126810 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45317 | /* 126816 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45318 | /* 126822 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45319 | /* 126825 */ GIR_RootConstrainSelectedInstOperands, |
| 45320 | /* 126826 */ // GIR_Coverage, 3656, |
| 45321 | /* 126826 */ GIR_EraseRootFromParent_Done, |
| 45322 | /* 126827 */ // Label 2535: @126827 |
| 45323 | /* 126827 */ GIM_Reject, |
| 45324 | /* 126828 */ // Label 2533: @126828 |
| 45325 | /* 126828 */ GIM_Reject, |
| 45326 | /* 126829 */ // Label 2522: @126829 |
| 45327 | /* 126829 */ GIM_Try, /*On fail goto*//*Label 2536*/ GIMT_Encode4(126927), |
| 45328 | /* 126834 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 45329 | /* 126837 */ GIM_Try, /*On fail goto*//*Label 2537*/ GIMT_Encode4(126871), // Rule ID 1549 // |
| 45330 | /* 126842 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 45331 | /* 126845 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 45332 | /* 126849 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 45333 | /* 126853 */ // (ctlz:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm) => (VCLZv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm) |
| 45334 | /* 126853 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCLZv16i8), |
| 45335 | /* 126856 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 45336 | /* 126858 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 45337 | /* 126860 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 45338 | /* 126863 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45339 | /* 126869 */ GIR_RootConstrainSelectedInstOperands, |
| 45340 | /* 126870 */ // GIR_Coverage, 1549, |
| 45341 | /* 126870 */ GIR_EraseRootFromParent_Done, |
| 45342 | /* 126871 */ // Label 2537: @126871 |
| 45343 | /* 126871 */ GIM_Try, /*On fail goto*//*Label 2538*/ GIMT_Encode4(126926), // Rule ID 3654 // |
| 45344 | /* 126876 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 45345 | /* 126879 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45346 | /* 126883 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45347 | /* 126887 */ // (ctlz:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$val) => (MVE_VCLZs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$val) |
| 45348 | /* 126887 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 45349 | /* 126890 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 45350 | /* 126894 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 45351 | /* 126899 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCLZs8), |
| 45352 | /* 126902 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 45353 | /* 126904 */ GIR_RootToRootCopy, /*OpIdx*/1, // val |
| 45354 | /* 126906 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45355 | /* 126909 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45356 | /* 126915 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45357 | /* 126921 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45358 | /* 126924 */ GIR_RootConstrainSelectedInstOperands, |
| 45359 | /* 126925 */ // GIR_Coverage, 3654, |
| 45360 | /* 126925 */ GIR_EraseRootFromParent_Done, |
| 45361 | /* 126926 */ // Label 2538: @126926 |
| 45362 | /* 126926 */ GIM_Reject, |
| 45363 | /* 126927 */ // Label 2536: @126927 |
| 45364 | /* 126927 */ GIM_Reject, |
| 45365 | /* 126928 */ // Label 2523: @126928 |
| 45366 | /* 126928 */ GIM_Reject, |
| 45367 | /* 126929 */ // Label 64: @126929 |
| 45368 | /* 126929 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(11), GIMT_Encode2(16), /*)*//*default:*//*Label 2541*/ GIMT_Encode4(127036), |
| 45369 | /* 126940 */ /*GILLT_v8s8*//*Label 2539*/ GIMT_Encode4(126960), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 45370 | /* 126956 */ /*GILLT_v16s8*//*Label 2540*/ GIMT_Encode4(126998), |
| 45371 | /* 126960 */ // Label 2539: @126960 |
| 45372 | /* 126960 */ GIM_Try, /*On fail goto*//*Label 2542*/ GIMT_Encode4(126997), // Rule ID 1552 // |
| 45373 | /* 126965 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 45374 | /* 126968 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 45375 | /* 126971 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45376 | /* 126975 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45377 | /* 126979 */ // (ctpop:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm) => (VCNTd:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm) |
| 45378 | /* 126979 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCNTd), |
| 45379 | /* 126982 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 45380 | /* 126984 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 45381 | /* 126986 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 45382 | /* 126989 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45383 | /* 126995 */ GIR_RootConstrainSelectedInstOperands, |
| 45384 | /* 126996 */ // GIR_Coverage, 1552, |
| 45385 | /* 126996 */ GIR_EraseRootFromParent_Done, |
| 45386 | /* 126997 */ // Label 2542: @126997 |
| 45387 | /* 126997 */ GIM_Reject, |
| 45388 | /* 126998 */ // Label 2540: @126998 |
| 45389 | /* 126998 */ GIM_Try, /*On fail goto*//*Label 2543*/ GIMT_Encode4(127035), // Rule ID 1553 // |
| 45390 | /* 127003 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON), |
| 45391 | /* 127006 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 45392 | /* 127009 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 45393 | /* 127013 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 45394 | /* 127017 */ // (ctpop:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm) => (VCNTq:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm) |
| 45395 | /* 127017 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCNTq), |
| 45396 | /* 127020 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 45397 | /* 127022 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 45398 | /* 127024 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 45399 | /* 127027 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45400 | /* 127033 */ GIR_RootConstrainSelectedInstOperands, |
| 45401 | /* 127034 */ // GIR_Coverage, 1553, |
| 45402 | /* 127034 */ GIR_EraseRootFromParent_Done, |
| 45403 | /* 127035 */ // Label 2543: @127035 |
| 45404 | /* 127035 */ GIM_Reject, |
| 45405 | /* 127036 */ // Label 2541: @127036 |
| 45406 | /* 127036 */ GIM_Reject, |
| 45407 | /* 127037 */ // Label 65: @127037 |
| 45408 | /* 127037 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(13), /*)*//*default:*//*Label 2547*/ GIMT_Encode4(127326), |
| 45409 | /* 127048 */ /*GILLT_s32*//*Label 2544*/ GIMT_Encode4(127096), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 45410 | /* 127076 */ /*GILLT_v4s32*//*Label 2545*/ GIMT_Encode4(127208), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 45411 | /* 127092 */ /*GILLT_v8s16*//*Label 2546*/ GIMT_Encode4(127267), |
| 45412 | /* 127096 */ // Label 2544: @127096 |
| 45413 | /* 127096 */ GIM_Try, /*On fail goto*//*Label 2548*/ GIMT_Encode4(127207), |
| 45414 | /* 127101 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 45415 | /* 127104 */ GIM_Try, /*On fail goto*//*Label 2549*/ GIMT_Encode4(127138), // Rule ID 199 // |
| 45416 | /* 127109 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM), |
| 45417 | /* 127112 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 45418 | /* 127116 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 45419 | /* 127120 */ // (bswap:{ *:[i32] } GPR:{ *:[i32] }:$Rm) => (REV:{ *:[i32] } GPR:{ *:[i32] }:$Rm) |
| 45420 | /* 127120 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::REV), |
| 45421 | /* 127123 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 45422 | /* 127125 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 45423 | /* 127127 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 45424 | /* 127130 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45425 | /* 127136 */ GIR_RootConstrainSelectedInstOperands, |
| 45426 | /* 127137 */ // GIR_Coverage, 199, |
| 45427 | /* 127137 */ GIR_EraseRootFromParent_Done, |
| 45428 | /* 127138 */ // Label 2549: @127138 |
| 45429 | /* 127138 */ GIM_Try, /*On fail goto*//*Label 2550*/ GIMT_Encode4(127172), // Rule ID 326 // |
| 45430 | /* 127143 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsThumb_IsThumb1Only), |
| 45431 | /* 127146 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 45432 | /* 127150 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 45433 | /* 127154 */ // (bswap:{ *:[i32] } tGPR:{ *:[i32] }:$Rm) => (tREV:{ *:[i32] } tGPR:{ *:[i32] }:$Rm) |
| 45434 | /* 127154 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tREV), |
| 45435 | /* 127157 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 45436 | /* 127159 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 45437 | /* 127161 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 45438 | /* 127164 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45439 | /* 127170 */ GIR_RootConstrainSelectedInstOperands, |
| 45440 | /* 127171 */ // GIR_Coverage, 326, |
| 45441 | /* 127171 */ GIR_EraseRootFromParent_Done, |
| 45442 | /* 127172 */ // Label 2550: @127172 |
| 45443 | /* 127172 */ GIM_Try, /*On fail goto*//*Label 2551*/ GIMT_Encode4(127206), // Rule ID 536 // |
| 45444 | /* 127177 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 45445 | /* 127180 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 45446 | /* 127184 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 45447 | /* 127188 */ // (bswap:{ *:[i32] } rGPR:{ *:[i32] }:$Rm) => (t2REV:{ *:[i32] } rGPR:{ *:[i32] }:$Rm) |
| 45448 | /* 127188 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2REV), |
| 45449 | /* 127191 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 45450 | /* 127193 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 45451 | /* 127195 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 45452 | /* 127198 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45453 | /* 127204 */ GIR_RootConstrainSelectedInstOperands, |
| 45454 | /* 127205 */ // GIR_Coverage, 536, |
| 45455 | /* 127205 */ GIR_EraseRootFromParent_Done, |
| 45456 | /* 127206 */ // Label 2551: @127206 |
| 45457 | /* 127206 */ GIM_Reject, |
| 45458 | /* 127207 */ // Label 2548: @127207 |
| 45459 | /* 127207 */ GIM_Reject, |
| 45460 | /* 127208 */ // Label 2545: @127208 |
| 45461 | /* 127208 */ GIM_Try, /*On fail goto*//*Label 2552*/ GIMT_Encode4(127266), // Rule ID 3331 // |
| 45462 | /* 127213 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 45463 | /* 127216 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 45464 | /* 127219 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45465 | /* 127223 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45466 | /* 127227 */ // (bswap:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src) => (MVE_VREV32_8:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src) |
| 45467 | /* 127227 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 45468 | /* 127230 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 45469 | /* 127234 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 45470 | /* 127239 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_8), |
| 45471 | /* 127242 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 45472 | /* 127244 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 45473 | /* 127246 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45474 | /* 127249 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45475 | /* 127255 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45476 | /* 127261 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45477 | /* 127264 */ GIR_RootConstrainSelectedInstOperands, |
| 45478 | /* 127265 */ // GIR_Coverage, 3331, |
| 45479 | /* 127265 */ GIR_EraseRootFromParent_Done, |
| 45480 | /* 127266 */ // Label 2552: @127266 |
| 45481 | /* 127266 */ GIM_Reject, |
| 45482 | /* 127267 */ // Label 2546: @127267 |
| 45483 | /* 127267 */ GIM_Try, /*On fail goto*//*Label 2553*/ GIMT_Encode4(127325), // Rule ID 3330 // |
| 45484 | /* 127272 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 45485 | /* 127275 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 45486 | /* 127278 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45487 | /* 127282 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45488 | /* 127286 */ // (bswap:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src) => (MVE_VREV16_8:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src) |
| 45489 | /* 127286 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 45490 | /* 127289 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 45491 | /* 127293 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 45492 | /* 127298 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV16_8), |
| 45493 | /* 127301 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 45494 | /* 127303 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 45495 | /* 127305 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45496 | /* 127308 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45497 | /* 127314 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45498 | /* 127320 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45499 | /* 127323 */ GIR_RootConstrainSelectedInstOperands, |
| 45500 | /* 127324 */ // GIR_Coverage, 3330, |
| 45501 | /* 127324 */ GIR_EraseRootFromParent_Done, |
| 45502 | /* 127325 */ // Label 2553: @127325 |
| 45503 | /* 127325 */ GIM_Reject, |
| 45504 | /* 127326 */ // Label 2547: @127326 |
| 45505 | /* 127326 */ GIM_Reject, |
| 45506 | /* 127327 */ // Label 66: @127327 |
| 45507 | /* 127327 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(16), /*)*//*default:*//*Label 2558*/ GIMT_Encode4(127758), |
| 45508 | /* 127338 */ /*GILLT_s32*//*Label 2554*/ GIMT_Encode4(127398), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 45509 | /* 127366 */ /*GILLT_v4s32*//*Label 2555*/ GIMT_Encode4(127476), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 45510 | /* 127382 */ /*GILLT_v8s16*//*Label 2556*/ GIMT_Encode4(127570), GIMT_Encode4(0), GIMT_Encode4(0), |
| 45511 | /* 127394 */ /*GILLT_v16s8*//*Label 2557*/ GIMT_Encode4(127664), |
| 45512 | /* 127398 */ // Label 2554: @127398 |
| 45513 | /* 127398 */ GIM_Try, /*On fail goto*//*Label 2559*/ GIMT_Encode4(127475), |
| 45514 | /* 127403 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 45515 | /* 127406 */ GIM_Try, /*On fail goto*//*Label 2560*/ GIMT_Encode4(127440), // Rule ID 198 // |
| 45516 | /* 127411 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6T2_IsARM), |
| 45517 | /* 127414 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 45518 | /* 127418 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 45519 | /* 127422 */ // (bitreverse:{ *:[i32] } GPR:{ *:[i32] }:$Rm) => (RBIT:{ *:[i32] } GPR:{ *:[i32] }:$Rm) |
| 45520 | /* 127422 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::RBIT), |
| 45521 | /* 127425 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 45522 | /* 127427 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 45523 | /* 127429 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 45524 | /* 127432 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45525 | /* 127438 */ GIR_RootConstrainSelectedInstOperands, |
| 45526 | /* 127439 */ // GIR_Coverage, 198, |
| 45527 | /* 127439 */ GIR_EraseRootFromParent_Done, |
| 45528 | /* 127440 */ // Label 2560: @127440 |
| 45529 | /* 127440 */ GIM_Try, /*On fail goto*//*Label 2561*/ GIMT_Encode4(127474), // Rule ID 535 // |
| 45530 | /* 127445 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2), |
| 45531 | /* 127448 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 45532 | /* 127452 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 45533 | /* 127456 */ // (bitreverse:{ *:[i32] } rGPR:{ *:[i32] }:$Rm) => (t2RBIT:{ *:[i32] } rGPR:{ *:[i32] }:$Rm) |
| 45534 | /* 127456 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2RBIT), |
| 45535 | /* 127459 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 45536 | /* 127461 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 45537 | /* 127463 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 45538 | /* 127466 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45539 | /* 127472 */ GIR_RootConstrainSelectedInstOperands, |
| 45540 | /* 127473 */ // GIR_Coverage, 535, |
| 45541 | /* 127473 */ GIR_EraseRootFromParent_Done, |
| 45542 | /* 127474 */ // Label 2561: @127474 |
| 45543 | /* 127474 */ GIM_Reject, |
| 45544 | /* 127475 */ // Label 2559: @127475 |
| 45545 | /* 127475 */ GIM_Reject, |
| 45546 | /* 127476 */ // Label 2555: @127476 |
| 45547 | /* 127476 */ GIM_Try, /*On fail goto*//*Label 2562*/ GIMT_Encode4(127569), // Rule ID 4758 // |
| 45548 | /* 127481 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 45549 | /* 127484 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 45550 | /* 127487 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45551 | /* 127491 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45552 | /* 127495 */ // (bitreverse:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$val1) => (MVE_VBRSR32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$val1, (t2MOVi:{ *:[i32] } 32:{ *:[i32] })) |
| 45553 | /* 127495 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 45554 | /* 127498 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 45555 | /* 127502 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 45556 | /* 127507 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 45557 | /* 127510 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi), |
| 45558 | /* 127514 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 45559 | /* 127519 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/32, |
| 45560 | /* 127522 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 45561 | /* 127525 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45562 | /* 127531 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45563 | /* 127537 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 45564 | /* 127539 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VBRSR32), |
| 45565 | /* 127542 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 45566 | /* 127544 */ GIR_RootToRootCopy, /*OpIdx*/1, // val1 |
| 45567 | /* 127546 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45568 | /* 127549 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45569 | /* 127552 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45570 | /* 127558 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45571 | /* 127564 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 45572 | /* 127567 */ GIR_RootConstrainSelectedInstOperands, |
| 45573 | /* 127568 */ // GIR_Coverage, 4758, |
| 45574 | /* 127568 */ GIR_EraseRootFromParent_Done, |
| 45575 | /* 127569 */ // Label 2562: @127569 |
| 45576 | /* 127569 */ GIM_Reject, |
| 45577 | /* 127570 */ // Label 2556: @127570 |
| 45578 | /* 127570 */ GIM_Try, /*On fail goto*//*Label 2563*/ GIMT_Encode4(127663), // Rule ID 4759 // |
| 45579 | /* 127575 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 45580 | /* 127578 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 45581 | /* 127581 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45582 | /* 127585 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45583 | /* 127589 */ // (bitreverse:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$val1) => (MVE_VBRSR16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$val1, (t2MOVi:{ *:[i32] } 16:{ *:[i32] })) |
| 45584 | /* 127589 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 45585 | /* 127592 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 45586 | /* 127596 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 45587 | /* 127601 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 45588 | /* 127604 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi), |
| 45589 | /* 127608 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 45590 | /* 127613 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/16, |
| 45591 | /* 127616 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 45592 | /* 127619 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45593 | /* 127625 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45594 | /* 127631 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 45595 | /* 127633 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VBRSR16), |
| 45596 | /* 127636 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 45597 | /* 127638 */ GIR_RootToRootCopy, /*OpIdx*/1, // val1 |
| 45598 | /* 127640 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45599 | /* 127643 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45600 | /* 127646 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45601 | /* 127652 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45602 | /* 127658 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 45603 | /* 127661 */ GIR_RootConstrainSelectedInstOperands, |
| 45604 | /* 127662 */ // GIR_Coverage, 4759, |
| 45605 | /* 127662 */ GIR_EraseRootFromParent_Done, |
| 45606 | /* 127663 */ // Label 2563: @127663 |
| 45607 | /* 127663 */ GIM_Reject, |
| 45608 | /* 127664 */ // Label 2557: @127664 |
| 45609 | /* 127664 */ GIM_Try, /*On fail goto*//*Label 2564*/ GIMT_Encode4(127757), // Rule ID 4757 // |
| 45610 | /* 127669 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 45611 | /* 127672 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 45612 | /* 127675 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45613 | /* 127679 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45614 | /* 127683 */ // (bitreverse:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$val1) => (MVE_VBRSR8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$val1, (t2MOVi:{ *:[i32] } 8:{ *:[i32] })) |
| 45615 | /* 127683 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 45616 | /* 127686 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 45617 | /* 127690 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 45618 | /* 127695 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 45619 | /* 127698 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi), |
| 45620 | /* 127702 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 45621 | /* 127707 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/8, |
| 45622 | /* 127710 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 45623 | /* 127713 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45624 | /* 127719 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45625 | /* 127725 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 45626 | /* 127727 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VBRSR8), |
| 45627 | /* 127730 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 45628 | /* 127732 */ GIR_RootToRootCopy, /*OpIdx*/1, // val1 |
| 45629 | /* 127734 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45630 | /* 127737 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45631 | /* 127740 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45632 | /* 127746 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45633 | /* 127752 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 45634 | /* 127755 */ GIR_RootConstrainSelectedInstOperands, |
| 45635 | /* 127756 */ // GIR_Coverage, 4757, |
| 45636 | /* 127756 */ GIR_EraseRootFromParent_Done, |
| 45637 | /* 127757 */ // Label 2564: @127757 |
| 45638 | /* 127757 */ GIM_Reject, |
| 45639 | /* 127758 */ // Label 2558: @127758 |
| 45640 | /* 127758 */ GIM_Reject, |
| 45641 | /* 127759 */ // Label 67: @127759 |
| 45642 | /* 127759 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 2572*/ GIMT_Encode4(128133), |
| 45643 | /* 127770 */ /*GILLT_s16*//*Label 2565*/ GIMT_Encode4(127822), |
| 45644 | /* 127774 */ /*GILLT_s32*//*Label 2566*/ GIMT_Encode4(127849), |
| 45645 | /* 127778 */ /*GILLT_s64*//*Label 2567*/ GIMT_Encode4(127876), GIMT_Encode4(0), |
| 45646 | /* 127786 */ /*GILLT_v2s32*//*Label 2568*/ GIMT_Encode4(127903), GIMT_Encode4(0), GIMT_Encode4(0), |
| 45647 | /* 127798 */ /*GILLT_v4s16*//*Label 2569*/ GIMT_Encode4(127930), |
| 45648 | /* 127802 */ /*GILLT_v4s32*//*Label 2570*/ GIMT_Encode4(127957), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 45649 | /* 127818 */ /*GILLT_v8s16*//*Label 2571*/ GIMT_Encode4(128045), |
| 45650 | /* 127822 */ // Label 2565: @127822 |
| 45651 | /* 127822 */ GIM_Try, /*On fail goto*//*Label 2573*/ GIMT_Encode4(127848), // Rule ID 683 // |
| 45652 | /* 127827 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 45653 | /* 127830 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 45654 | /* 127833 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 45655 | /* 127837 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 45656 | /* 127841 */ // (fceil:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VRINTPH:{ *:[f16] } HPR:{ *:[f16] }:$Sm) |
| 45657 | /* 127841 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTPH), |
| 45658 | /* 127846 */ GIR_RootConstrainSelectedInstOperands, |
| 45659 | /* 127847 */ // GIR_Coverage, 683, |
| 45660 | /* 127847 */ GIR_Done, |
| 45661 | /* 127848 */ // Label 2573: @127848 |
| 45662 | /* 127848 */ GIM_Reject, |
| 45663 | /* 127849 */ // Label 2566: @127849 |
| 45664 | /* 127849 */ GIM_Try, /*On fail goto*//*Label 2574*/ GIMT_Encode4(127875), // Rule ID 684 // |
| 45665 | /* 127854 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8), |
| 45666 | /* 127857 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 45667 | /* 127860 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 45668 | /* 127864 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 45669 | /* 127868 */ // (fceil:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VRINTPS:{ *:[f32] } SPR:{ *:[f32] }:$Sm) |
| 45670 | /* 127868 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTPS), |
| 45671 | /* 127873 */ GIR_RootConstrainSelectedInstOperands, |
| 45672 | /* 127874 */ // GIR_Coverage, 684, |
| 45673 | /* 127874 */ GIR_Done, |
| 45674 | /* 127875 */ // Label 2574: @127875 |
| 45675 | /* 127875 */ GIM_Reject, |
| 45676 | /* 127876 */ // Label 2567: @127876 |
| 45677 | /* 127876 */ GIM_Try, /*On fail goto*//*Label 2575*/ GIMT_Encode4(127902), // Rule ID 685 // |
| 45678 | /* 127881 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), |
| 45679 | /* 127884 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 45680 | /* 127887 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45681 | /* 127891 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45682 | /* 127895 */ // (fceil:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VRINTPD:{ *:[f64] } DPR:{ *:[f64] }:$Dm) |
| 45683 | /* 127895 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTPD), |
| 45684 | /* 127900 */ GIR_RootConstrainSelectedInstOperands, |
| 45685 | /* 127901 */ // GIR_Coverage, 685, |
| 45686 | /* 127901 */ GIR_Done, |
| 45687 | /* 127902 */ // Label 2575: @127902 |
| 45688 | /* 127902 */ GIM_Reject, |
| 45689 | /* 127903 */ // Label 2568: @127903 |
| 45690 | /* 127903 */ GIM_Try, /*On fail goto*//*Label 2576*/ GIMT_Encode4(127929), // Rule ID 1711 // |
| 45691 | /* 127908 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8), |
| 45692 | /* 127911 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 45693 | /* 127914 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45694 | /* 127918 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45695 | /* 127922 */ // (fceil:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) => (VRINTPNDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) |
| 45696 | /* 127922 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTPNDf), |
| 45697 | /* 127927 */ GIR_RootConstrainSelectedInstOperands, |
| 45698 | /* 127928 */ // GIR_Coverage, 1711, |
| 45699 | /* 127928 */ GIR_Done, |
| 45700 | /* 127929 */ // Label 2576: @127929 |
| 45701 | /* 127929 */ GIM_Reject, |
| 45702 | /* 127930 */ // Label 2569: @127930 |
| 45703 | /* 127930 */ GIM_Try, /*On fail goto*//*Label 2577*/ GIMT_Encode4(127956), // Rule ID 1713 // |
| 45704 | /* 127935 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), |
| 45705 | /* 127938 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 45706 | /* 127941 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45707 | /* 127945 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45708 | /* 127949 */ // (fceil:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) => (VRINTPNDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) |
| 45709 | /* 127949 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTPNDh), |
| 45710 | /* 127954 */ GIR_RootConstrainSelectedInstOperands, |
| 45711 | /* 127955 */ // GIR_Coverage, 1713, |
| 45712 | /* 127955 */ GIR_Done, |
| 45713 | /* 127956 */ // Label 2577: @127956 |
| 45714 | /* 127956 */ GIM_Reject, |
| 45715 | /* 127957 */ // Label 2570: @127957 |
| 45716 | /* 127957 */ GIM_Try, /*On fail goto*//*Label 2578*/ GIMT_Encode4(128044), |
| 45717 | /* 127962 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 45718 | /* 127965 */ GIM_Try, /*On fail goto*//*Label 2579*/ GIMT_Encode4(127988), // Rule ID 1712 // |
| 45719 | /* 127970 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8), |
| 45720 | /* 127973 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 45721 | /* 127977 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 45722 | /* 127981 */ // (fceil:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) => (VRINTPNQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) |
| 45723 | /* 127981 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTPNQf), |
| 45724 | /* 127986 */ GIR_RootConstrainSelectedInstOperands, |
| 45725 | /* 127987 */ // GIR_Coverage, 1712, |
| 45726 | /* 127987 */ GIR_Done, |
| 45727 | /* 127988 */ // Label 2579: @127988 |
| 45728 | /* 127988 */ GIM_Try, /*On fail goto*//*Label 2580*/ GIMT_Encode4(128043), // Rule ID 3986 // |
| 45729 | /* 127993 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 45730 | /* 127996 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45731 | /* 128000 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45732 | /* 128004 */ // (fceil:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val) => (MVE_VRINTf32P:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val) |
| 45733 | /* 128004 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 45734 | /* 128007 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 45735 | /* 128011 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 45736 | /* 128016 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf32P), |
| 45737 | /* 128019 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 45738 | /* 128021 */ GIR_RootToRootCopy, /*OpIdx*/1, // val |
| 45739 | /* 128023 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45740 | /* 128026 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45741 | /* 128032 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45742 | /* 128038 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45743 | /* 128041 */ GIR_RootConstrainSelectedInstOperands, |
| 45744 | /* 128042 */ // GIR_Coverage, 3986, |
| 45745 | /* 128042 */ GIR_EraseRootFromParent_Done, |
| 45746 | /* 128043 */ // Label 2580: @128043 |
| 45747 | /* 128043 */ GIM_Reject, |
| 45748 | /* 128044 */ // Label 2578: @128044 |
| 45749 | /* 128044 */ GIM_Reject, |
| 45750 | /* 128045 */ // Label 2571: @128045 |
| 45751 | /* 128045 */ GIM_Try, /*On fail goto*//*Label 2581*/ GIMT_Encode4(128132), |
| 45752 | /* 128050 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 45753 | /* 128053 */ GIM_Try, /*On fail goto*//*Label 2582*/ GIMT_Encode4(128076), // Rule ID 1714 // |
| 45754 | /* 128058 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), |
| 45755 | /* 128061 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 45756 | /* 128065 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 45757 | /* 128069 */ // (fceil:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) => (VRINTPNQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) |
| 45758 | /* 128069 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTPNQh), |
| 45759 | /* 128074 */ GIR_RootConstrainSelectedInstOperands, |
| 45760 | /* 128075 */ // GIR_Coverage, 1714, |
| 45761 | /* 128075 */ GIR_Done, |
| 45762 | /* 128076 */ // Label 2582: @128076 |
| 45763 | /* 128076 */ GIM_Try, /*On fail goto*//*Label 2583*/ GIMT_Encode4(128131), // Rule ID 3974 // |
| 45764 | /* 128081 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 45765 | /* 128084 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45766 | /* 128088 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45767 | /* 128092 */ // (fceil:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val) => (MVE_VRINTf16P:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val) |
| 45768 | /* 128092 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 45769 | /* 128095 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 45770 | /* 128099 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 45771 | /* 128104 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf16P), |
| 45772 | /* 128107 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 45773 | /* 128109 */ GIR_RootToRootCopy, /*OpIdx*/1, // val |
| 45774 | /* 128111 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45775 | /* 128114 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45776 | /* 128120 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45777 | /* 128126 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45778 | /* 128129 */ GIR_RootConstrainSelectedInstOperands, |
| 45779 | /* 128130 */ // GIR_Coverage, 3974, |
| 45780 | /* 128130 */ GIR_EraseRootFromParent_Done, |
| 45781 | /* 128131 */ // Label 2583: @128131 |
| 45782 | /* 128131 */ GIM_Reject, |
| 45783 | /* 128132 */ // Label 2581: @128132 |
| 45784 | /* 128132 */ GIM_Reject, |
| 45785 | /* 128133 */ // Label 2572: @128133 |
| 45786 | /* 128133 */ GIM_Reject, |
| 45787 | /* 128134 */ // Label 68: @128134 |
| 45788 | /* 128134 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(3), /*)*//*default:*//*Label 2587*/ GIMT_Encode4(128271), |
| 45789 | /* 128145 */ /*GILLT_s16*//*Label 2584*/ GIMT_Encode4(128157), |
| 45790 | /* 128149 */ /*GILLT_s32*//*Label 2585*/ GIMT_Encode4(128195), |
| 45791 | /* 128153 */ /*GILLT_s64*//*Label 2586*/ GIMT_Encode4(128233), |
| 45792 | /* 128157 */ // Label 2584: @128157 |
| 45793 | /* 128157 */ GIM_Try, /*On fail goto*//*Label 2588*/ GIMT_Encode4(128194), // Rule ID 691 // |
| 45794 | /* 128162 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 45795 | /* 128165 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 45796 | /* 128168 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 45797 | /* 128172 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 45798 | /* 128176 */ // (fsqrt:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VSQRTH:{ *:[f16] } HPR:{ *:[f16] }:$Sm) |
| 45799 | /* 128176 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSQRTH), |
| 45800 | /* 128179 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 45801 | /* 128181 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm |
| 45802 | /* 128183 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 45803 | /* 128186 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45804 | /* 128192 */ GIR_RootConstrainSelectedInstOperands, |
| 45805 | /* 128193 */ // GIR_Coverage, 691, |
| 45806 | /* 128193 */ GIR_EraseRootFromParent_Done, |
| 45807 | /* 128194 */ // Label 2588: @128194 |
| 45808 | /* 128194 */ GIM_Reject, |
| 45809 | /* 128195 */ // Label 2585: @128195 |
| 45810 | /* 128195 */ GIM_Try, /*On fail goto*//*Label 2589*/ GIMT_Encode4(128232), // Rule ID 690 // |
| 45811 | /* 128200 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP2), |
| 45812 | /* 128203 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 45813 | /* 128206 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 45814 | /* 128210 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 45815 | /* 128214 */ // (fsqrt:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VSQRTS:{ *:[f32] } SPR:{ *:[f32] }:$Sm) |
| 45816 | /* 128214 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSQRTS), |
| 45817 | /* 128217 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 45818 | /* 128219 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm |
| 45819 | /* 128221 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 45820 | /* 128224 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45821 | /* 128230 */ GIR_RootConstrainSelectedInstOperands, |
| 45822 | /* 128231 */ // GIR_Coverage, 690, |
| 45823 | /* 128231 */ GIR_EraseRootFromParent_Done, |
| 45824 | /* 128232 */ // Label 2589: @128232 |
| 45825 | /* 128232 */ GIM_Reject, |
| 45826 | /* 128233 */ // Label 2586: @128233 |
| 45827 | /* 128233 */ GIM_Try, /*On fail goto*//*Label 2590*/ GIMT_Encode4(128270), // Rule ID 689 // |
| 45828 | /* 128238 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), |
| 45829 | /* 128241 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 45830 | /* 128244 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45831 | /* 128248 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45832 | /* 128252 */ // (fsqrt:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VSQRTD:{ *:[f64] } DPR:{ *:[f64] }:$Dm) |
| 45833 | /* 128252 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSQRTD), |
| 45834 | /* 128255 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 45835 | /* 128257 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dm |
| 45836 | /* 128259 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 45837 | /* 128262 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45838 | /* 128268 */ GIR_RootConstrainSelectedInstOperands, |
| 45839 | /* 128269 */ // GIR_Coverage, 689, |
| 45840 | /* 128269 */ GIR_EraseRootFromParent_Done, |
| 45841 | /* 128270 */ // Label 2590: @128270 |
| 45842 | /* 128270 */ GIM_Reject, |
| 45843 | /* 128271 */ // Label 2587: @128271 |
| 45844 | /* 128271 */ GIM_Reject, |
| 45845 | /* 128272 */ // Label 69: @128272 |
| 45846 | /* 128272 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 2598*/ GIMT_Encode4(128646), |
| 45847 | /* 128283 */ /*GILLT_s16*//*Label 2591*/ GIMT_Encode4(128335), |
| 45848 | /* 128287 */ /*GILLT_s32*//*Label 2592*/ GIMT_Encode4(128362), |
| 45849 | /* 128291 */ /*GILLT_s64*//*Label 2593*/ GIMT_Encode4(128389), GIMT_Encode4(0), |
| 45850 | /* 128299 */ /*GILLT_v2s32*//*Label 2594*/ GIMT_Encode4(128416), GIMT_Encode4(0), GIMT_Encode4(0), |
| 45851 | /* 128311 */ /*GILLT_v4s16*//*Label 2595*/ GIMT_Encode4(128443), |
| 45852 | /* 128315 */ /*GILLT_v4s32*//*Label 2596*/ GIMT_Encode4(128470), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 45853 | /* 128331 */ /*GILLT_v8s16*//*Label 2597*/ GIMT_Encode4(128558), |
| 45854 | /* 128335 */ // Label 2591: @128335 |
| 45855 | /* 128335 */ GIM_Try, /*On fail goto*//*Label 2599*/ GIMT_Encode4(128361), // Rule ID 686 // |
| 45856 | /* 128340 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 45857 | /* 128343 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 45858 | /* 128346 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 45859 | /* 128350 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 45860 | /* 128354 */ // (ffloor:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VRINTMH:{ *:[f16] } HPR:{ *:[f16] }:$Sm) |
| 45861 | /* 128354 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTMH), |
| 45862 | /* 128359 */ GIR_RootConstrainSelectedInstOperands, |
| 45863 | /* 128360 */ // GIR_Coverage, 686, |
| 45864 | /* 128360 */ GIR_Done, |
| 45865 | /* 128361 */ // Label 2599: @128361 |
| 45866 | /* 128361 */ GIM_Reject, |
| 45867 | /* 128362 */ // Label 2592: @128362 |
| 45868 | /* 128362 */ GIM_Try, /*On fail goto*//*Label 2600*/ GIMT_Encode4(128388), // Rule ID 687 // |
| 45869 | /* 128367 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8), |
| 45870 | /* 128370 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 45871 | /* 128373 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 45872 | /* 128377 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 45873 | /* 128381 */ // (ffloor:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VRINTMS:{ *:[f32] } SPR:{ *:[f32] }:$Sm) |
| 45874 | /* 128381 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTMS), |
| 45875 | /* 128386 */ GIR_RootConstrainSelectedInstOperands, |
| 45876 | /* 128387 */ // GIR_Coverage, 687, |
| 45877 | /* 128387 */ GIR_Done, |
| 45878 | /* 128388 */ // Label 2600: @128388 |
| 45879 | /* 128388 */ GIM_Reject, |
| 45880 | /* 128389 */ // Label 2593: @128389 |
| 45881 | /* 128389 */ GIM_Try, /*On fail goto*//*Label 2601*/ GIMT_Encode4(128415), // Rule ID 688 // |
| 45882 | /* 128394 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), |
| 45883 | /* 128397 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 45884 | /* 128400 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45885 | /* 128404 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45886 | /* 128408 */ // (ffloor:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VRINTMD:{ *:[f64] } DPR:{ *:[f64] }:$Dm) |
| 45887 | /* 128408 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTMD), |
| 45888 | /* 128413 */ GIR_RootConstrainSelectedInstOperands, |
| 45889 | /* 128414 */ // GIR_Coverage, 688, |
| 45890 | /* 128414 */ GIR_Done, |
| 45891 | /* 128415 */ // Label 2601: @128415 |
| 45892 | /* 128415 */ GIM_Reject, |
| 45893 | /* 128416 */ // Label 2594: @128416 |
| 45894 | /* 128416 */ GIM_Try, /*On fail goto*//*Label 2602*/ GIMT_Encode4(128442), // Rule ID 1707 // |
| 45895 | /* 128421 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8), |
| 45896 | /* 128424 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 45897 | /* 128427 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45898 | /* 128431 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45899 | /* 128435 */ // (ffloor:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) => (VRINTMNDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) |
| 45900 | /* 128435 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTMNDf), |
| 45901 | /* 128440 */ GIR_RootConstrainSelectedInstOperands, |
| 45902 | /* 128441 */ // GIR_Coverage, 1707, |
| 45903 | /* 128441 */ GIR_Done, |
| 45904 | /* 128442 */ // Label 2602: @128442 |
| 45905 | /* 128442 */ GIM_Reject, |
| 45906 | /* 128443 */ // Label 2595: @128443 |
| 45907 | /* 128443 */ GIM_Try, /*On fail goto*//*Label 2603*/ GIMT_Encode4(128469), // Rule ID 1709 // |
| 45908 | /* 128448 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), |
| 45909 | /* 128451 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 45910 | /* 128454 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45911 | /* 128458 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45912 | /* 128462 */ // (ffloor:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) => (VRINTMNDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) |
| 45913 | /* 128462 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTMNDh), |
| 45914 | /* 128467 */ GIR_RootConstrainSelectedInstOperands, |
| 45915 | /* 128468 */ // GIR_Coverage, 1709, |
| 45916 | /* 128468 */ GIR_Done, |
| 45917 | /* 128469 */ // Label 2603: @128469 |
| 45918 | /* 128469 */ GIM_Reject, |
| 45919 | /* 128470 */ // Label 2596: @128470 |
| 45920 | /* 128470 */ GIM_Try, /*On fail goto*//*Label 2604*/ GIMT_Encode4(128557), |
| 45921 | /* 128475 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 45922 | /* 128478 */ GIM_Try, /*On fail goto*//*Label 2605*/ GIMT_Encode4(128501), // Rule ID 1708 // |
| 45923 | /* 128483 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8), |
| 45924 | /* 128486 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 45925 | /* 128490 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 45926 | /* 128494 */ // (ffloor:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) => (VRINTMNQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) |
| 45927 | /* 128494 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTMNQf), |
| 45928 | /* 128499 */ GIR_RootConstrainSelectedInstOperands, |
| 45929 | /* 128500 */ // GIR_Coverage, 1708, |
| 45930 | /* 128500 */ GIR_Done, |
| 45931 | /* 128501 */ // Label 2605: @128501 |
| 45932 | /* 128501 */ GIM_Try, /*On fail goto*//*Label 2606*/ GIMT_Encode4(128556), // Rule ID 3984 // |
| 45933 | /* 128506 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 45934 | /* 128509 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45935 | /* 128513 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45936 | /* 128517 */ // (ffloor:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val) => (MVE_VRINTf32M:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val) |
| 45937 | /* 128517 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 45938 | /* 128520 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 45939 | /* 128524 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 45940 | /* 128529 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf32M), |
| 45941 | /* 128532 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 45942 | /* 128534 */ GIR_RootToRootCopy, /*OpIdx*/1, // val |
| 45943 | /* 128536 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45944 | /* 128539 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45945 | /* 128545 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45946 | /* 128551 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45947 | /* 128554 */ GIR_RootConstrainSelectedInstOperands, |
| 45948 | /* 128555 */ // GIR_Coverage, 3984, |
| 45949 | /* 128555 */ GIR_EraseRootFromParent_Done, |
| 45950 | /* 128556 */ // Label 2606: @128556 |
| 45951 | /* 128556 */ GIM_Reject, |
| 45952 | /* 128557 */ // Label 2604: @128557 |
| 45953 | /* 128557 */ GIM_Reject, |
| 45954 | /* 128558 */ // Label 2597: @128558 |
| 45955 | /* 128558 */ GIM_Try, /*On fail goto*//*Label 2607*/ GIMT_Encode4(128645), |
| 45956 | /* 128563 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 45957 | /* 128566 */ GIM_Try, /*On fail goto*//*Label 2608*/ GIMT_Encode4(128589), // Rule ID 1710 // |
| 45958 | /* 128571 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), |
| 45959 | /* 128574 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 45960 | /* 128578 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 45961 | /* 128582 */ // (ffloor:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) => (VRINTMNQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) |
| 45962 | /* 128582 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTMNQh), |
| 45963 | /* 128587 */ GIR_RootConstrainSelectedInstOperands, |
| 45964 | /* 128588 */ // GIR_Coverage, 1710, |
| 45965 | /* 128588 */ GIR_Done, |
| 45966 | /* 128589 */ // Label 2608: @128589 |
| 45967 | /* 128589 */ GIM_Try, /*On fail goto*//*Label 2609*/ GIMT_Encode4(128644), // Rule ID 3972 // |
| 45968 | /* 128594 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 45969 | /* 128597 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45970 | /* 128601 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45971 | /* 128605 */ // (ffloor:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val) => (MVE_VRINTf16M:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val) |
| 45972 | /* 128605 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 45973 | /* 128608 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 45974 | /* 128612 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 45975 | /* 128617 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf16M), |
| 45976 | /* 128620 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 45977 | /* 128622 */ GIR_RootToRootCopy, /*OpIdx*/1, // val |
| 45978 | /* 128624 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45979 | /* 128627 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45980 | /* 128633 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45981 | /* 128639 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45982 | /* 128642 */ GIR_RootConstrainSelectedInstOperands, |
| 45983 | /* 128643 */ // GIR_Coverage, 3972, |
| 45984 | /* 128643 */ GIR_EraseRootFromParent_Done, |
| 45985 | /* 128644 */ // Label 2609: @128644 |
| 45986 | /* 128644 */ GIM_Reject, |
| 45987 | /* 128645 */ // Label 2607: @128645 |
| 45988 | /* 128645 */ GIM_Reject, |
| 45989 | /* 128646 */ // Label 2598: @128646 |
| 45990 | /* 128646 */ GIM_Reject, |
| 45991 | /* 128647 */ // Label 70: @128647 |
| 45992 | /* 128647 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 2617*/ GIMT_Encode4(129054), |
| 45993 | /* 128658 */ /*GILLT_s16*//*Label 2610*/ GIMT_Encode4(128710), |
| 45994 | /* 128662 */ /*GILLT_s32*//*Label 2611*/ GIMT_Encode4(128748), |
| 45995 | /* 128666 */ /*GILLT_s64*//*Label 2612*/ GIMT_Encode4(128786), GIMT_Encode4(0), |
| 45996 | /* 128674 */ /*GILLT_v2s32*//*Label 2613*/ GIMT_Encode4(128824), GIMT_Encode4(0), GIMT_Encode4(0), |
| 45997 | /* 128686 */ /*GILLT_v4s16*//*Label 2614*/ GIMT_Encode4(128851), |
| 45998 | /* 128690 */ /*GILLT_v4s32*//*Label 2615*/ GIMT_Encode4(128878), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 45999 | /* 128706 */ /*GILLT_v8s16*//*Label 2616*/ GIMT_Encode4(128966), |
| 46000 | /* 128710 */ // Label 2610: @128710 |
| 46001 | /* 128710 */ GIM_Try, /*On fail goto*//*Label 2618*/ GIMT_Encode4(128747), // Rule ID 671 // |
| 46002 | /* 128715 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 46003 | /* 128718 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 46004 | /* 128721 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 46005 | /* 128725 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 46006 | /* 128729 */ // (frint:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VRINTXH:{ *:[f16] } HPR:{ *:[f16] }:$Sm) |
| 46007 | /* 128729 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTXH), |
| 46008 | /* 128732 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 46009 | /* 128734 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm |
| 46010 | /* 128736 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 46011 | /* 128739 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46012 | /* 128745 */ GIR_RootConstrainSelectedInstOperands, |
| 46013 | /* 128746 */ // GIR_Coverage, 671, |
| 46014 | /* 128746 */ GIR_EraseRootFromParent_Done, |
| 46015 | /* 128747 */ // Label 2618: @128747 |
| 46016 | /* 128747 */ GIM_Reject, |
| 46017 | /* 128748 */ // Label 2611: @128748 |
| 46018 | /* 128748 */ GIM_Try, /*On fail goto*//*Label 2619*/ GIMT_Encode4(128785), // Rule ID 672 // |
| 46019 | /* 128753 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8), |
| 46020 | /* 128756 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 46021 | /* 128759 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 46022 | /* 128763 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 46023 | /* 128767 */ // (frint:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VRINTXS:{ *:[f32] } SPR:{ *:[f32] }:$Sm) |
| 46024 | /* 128767 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTXS), |
| 46025 | /* 128770 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 46026 | /* 128772 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm |
| 46027 | /* 128774 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 46028 | /* 128777 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46029 | /* 128783 */ GIR_RootConstrainSelectedInstOperands, |
| 46030 | /* 128784 */ // GIR_Coverage, 672, |
| 46031 | /* 128784 */ GIR_EraseRootFromParent_Done, |
| 46032 | /* 128785 */ // Label 2619: @128785 |
| 46033 | /* 128785 */ GIM_Reject, |
| 46034 | /* 128786 */ // Label 2612: @128786 |
| 46035 | /* 128786 */ GIM_Try, /*On fail goto*//*Label 2620*/ GIMT_Encode4(128823), // Rule ID 673 // |
| 46036 | /* 128791 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), |
| 46037 | /* 128794 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 46038 | /* 128797 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 46039 | /* 128801 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 46040 | /* 128805 */ // (frint:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VRINTXD:{ *:[f64] } DPR:{ *:[f64] }:$Dm) |
| 46041 | /* 128805 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTXD), |
| 46042 | /* 128808 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 46043 | /* 128810 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dm |
| 46044 | /* 128812 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 46045 | /* 128815 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46046 | /* 128821 */ GIR_RootConstrainSelectedInstOperands, |
| 46047 | /* 128822 */ // GIR_Coverage, 673, |
| 46048 | /* 128822 */ GIR_EraseRootFromParent_Done, |
| 46049 | /* 128823 */ // Label 2620: @128823 |
| 46050 | /* 128823 */ GIM_Reject, |
| 46051 | /* 128824 */ // Label 2613: @128824 |
| 46052 | /* 128824 */ GIM_Try, /*On fail goto*//*Label 2621*/ GIMT_Encode4(128850), // Rule ID 1695 // |
| 46053 | /* 128829 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8), |
| 46054 | /* 128832 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 46055 | /* 128835 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 46056 | /* 128839 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 46057 | /* 128843 */ // (frint:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) => (VRINTXNDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) |
| 46058 | /* 128843 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTXNDf), |
| 46059 | /* 128848 */ GIR_RootConstrainSelectedInstOperands, |
| 46060 | /* 128849 */ // GIR_Coverage, 1695, |
| 46061 | /* 128849 */ GIR_Done, |
| 46062 | /* 128850 */ // Label 2621: @128850 |
| 46063 | /* 128850 */ GIM_Reject, |
| 46064 | /* 128851 */ // Label 2614: @128851 |
| 46065 | /* 128851 */ GIM_Try, /*On fail goto*//*Label 2622*/ GIMT_Encode4(128877), // Rule ID 1697 // |
| 46066 | /* 128856 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), |
| 46067 | /* 128859 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 46068 | /* 128862 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 46069 | /* 128866 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 46070 | /* 128870 */ // (frint:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) => (VRINTXNDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) |
| 46071 | /* 128870 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTXNDh), |
| 46072 | /* 128875 */ GIR_RootConstrainSelectedInstOperands, |
| 46073 | /* 128876 */ // GIR_Coverage, 1697, |
| 46074 | /* 128876 */ GIR_Done, |
| 46075 | /* 128877 */ // Label 2622: @128877 |
| 46076 | /* 128877 */ GIM_Reject, |
| 46077 | /* 128878 */ // Label 2615: @128878 |
| 46078 | /* 128878 */ GIM_Try, /*On fail goto*//*Label 2623*/ GIMT_Encode4(128965), |
| 46079 | /* 128883 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 46080 | /* 128886 */ GIM_Try, /*On fail goto*//*Label 2624*/ GIMT_Encode4(128909), // Rule ID 1696 // |
| 46081 | /* 128891 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8), |
| 46082 | /* 128894 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 46083 | /* 128898 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 46084 | /* 128902 */ // (frint:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) => (VRINTXNQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) |
| 46085 | /* 128902 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTXNQf), |
| 46086 | /* 128907 */ GIR_RootConstrainSelectedInstOperands, |
| 46087 | /* 128908 */ // GIR_Coverage, 1696, |
| 46088 | /* 128908 */ GIR_Done, |
| 46089 | /* 128909 */ // Label 2624: @128909 |
| 46090 | /* 128909 */ GIM_Try, /*On fail goto*//*Label 2625*/ GIMT_Encode4(128964), // Rule ID 3978 // |
| 46091 | /* 128914 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 46092 | /* 128917 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 46093 | /* 128921 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 46094 | /* 128925 */ // (frint:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val) => (MVE_VRINTf32X:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val) |
| 46095 | /* 128925 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 46096 | /* 128928 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 46097 | /* 128932 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 46098 | /* 128937 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf32X), |
| 46099 | /* 128940 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 46100 | /* 128942 */ GIR_RootToRootCopy, /*OpIdx*/1, // val |
| 46101 | /* 128944 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 46102 | /* 128947 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46103 | /* 128953 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46104 | /* 128959 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 46105 | /* 128962 */ GIR_RootConstrainSelectedInstOperands, |
| 46106 | /* 128963 */ // GIR_Coverage, 3978, |
| 46107 | /* 128963 */ GIR_EraseRootFromParent_Done, |
| 46108 | /* 128964 */ // Label 2625: @128964 |
| 46109 | /* 128964 */ GIM_Reject, |
| 46110 | /* 128965 */ // Label 2623: @128965 |
| 46111 | /* 128965 */ GIM_Reject, |
| 46112 | /* 128966 */ // Label 2616: @128966 |
| 46113 | /* 128966 */ GIM_Try, /*On fail goto*//*Label 2626*/ GIMT_Encode4(129053), |
| 46114 | /* 128971 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 46115 | /* 128974 */ GIM_Try, /*On fail goto*//*Label 2627*/ GIMT_Encode4(128997), // Rule ID 1698 // |
| 46116 | /* 128979 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), |
| 46117 | /* 128982 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 46118 | /* 128986 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 46119 | /* 128990 */ // (frint:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) => (VRINTXNQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) |
| 46120 | /* 128990 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTXNQh), |
| 46121 | /* 128995 */ GIR_RootConstrainSelectedInstOperands, |
| 46122 | /* 128996 */ // GIR_Coverage, 1698, |
| 46123 | /* 128996 */ GIR_Done, |
| 46124 | /* 128997 */ // Label 2627: @128997 |
| 46125 | /* 128997 */ GIM_Try, /*On fail goto*//*Label 2628*/ GIMT_Encode4(129052), // Rule ID 3966 // |
| 46126 | /* 129002 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat), |
| 46127 | /* 129005 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 46128 | /* 129009 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 46129 | /* 129013 */ // (frint:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val) => (MVE_VRINTf16X:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val) |
| 46130 | /* 129013 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 46131 | /* 129016 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 46132 | /* 129020 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 46133 | /* 129025 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf16X), |
| 46134 | /* 129028 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 46135 | /* 129030 */ GIR_RootToRootCopy, /*OpIdx*/1, // val |
| 46136 | /* 129032 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 46137 | /* 129035 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46138 | /* 129041 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46139 | /* 129047 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 46140 | /* 129050 */ GIR_RootConstrainSelectedInstOperands, |
| 46141 | /* 129051 */ // GIR_Coverage, 3966, |
| 46142 | /* 129051 */ GIR_EraseRootFromParent_Done, |
| 46143 | /* 129052 */ // Label 2628: @129052 |
| 46144 | /* 129052 */ GIM_Reject, |
| 46145 | /* 129053 */ // Label 2626: @129053 |
| 46146 | /* 129053 */ GIM_Reject, |
| 46147 | /* 129054 */ // Label 2617: @129054 |
| 46148 | /* 129054 */ GIM_Reject, |
| 46149 | /* 129055 */ // Label 71: @129055 |
| 46150 | /* 129055 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(3), /*)*//*default:*//*Label 2632*/ GIMT_Encode4(129192), |
| 46151 | /* 129066 */ /*GILLT_s16*//*Label 2629*/ GIMT_Encode4(129078), |
| 46152 | /* 129070 */ /*GILLT_s32*//*Label 2630*/ GIMT_Encode4(129116), |
| 46153 | /* 129074 */ /*GILLT_s64*//*Label 2631*/ GIMT_Encode4(129154), |
| 46154 | /* 129078 */ // Label 2629: @129078 |
| 46155 | /* 129078 */ GIM_Try, /*On fail goto*//*Label 2633*/ GIMT_Encode4(129115), // Rule ID 668 // |
| 46156 | /* 129083 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16), |
| 46157 | /* 129086 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 46158 | /* 129089 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 46159 | /* 129093 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 46160 | /* 129097 */ // (fnearbyint:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VRINTRH:{ *:[f16] } HPR:{ *:[f16] }:$Sm) |
| 46161 | /* 129097 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTRH), |
| 46162 | /* 129100 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 46163 | /* 129102 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm |
| 46164 | /* 129104 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 46165 | /* 129107 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46166 | /* 129113 */ GIR_RootConstrainSelectedInstOperands, |
| 46167 | /* 129114 */ // GIR_Coverage, 668, |
| 46168 | /* 129114 */ GIR_EraseRootFromParent_Done, |
| 46169 | /* 129115 */ // Label 2633: @129115 |
| 46170 | /* 129115 */ GIM_Reject, |
| 46171 | /* 129116 */ // Label 2630: @129116 |
| 46172 | /* 129116 */ GIM_Try, /*On fail goto*//*Label 2634*/ GIMT_Encode4(129153), // Rule ID 669 // |
| 46173 | /* 129121 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8), |
| 46174 | /* 129124 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 46175 | /* 129127 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 46176 | /* 129131 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 46177 | /* 129135 */ // (fnearbyint:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VRINTRS:{ *:[f32] } SPR:{ *:[f32] }:$Sm) |
| 46178 | /* 129135 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTRS), |
| 46179 | /* 129138 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 46180 | /* 129140 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm |
| 46181 | /* 129142 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 46182 | /* 129145 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46183 | /* 129151 */ GIR_RootConstrainSelectedInstOperands, |
| 46184 | /* 129152 */ // GIR_Coverage, 669, |
| 46185 | /* 129152 */ GIR_EraseRootFromParent_Done, |
| 46186 | /* 129153 */ // Label 2634: @129153 |
| 46187 | /* 129153 */ GIM_Reject, |
| 46188 | /* 129154 */ // Label 2631: @129154 |
| 46189 | /* 129154 */ GIM_Try, /*On fail goto*//*Label 2635*/ GIMT_Encode4(129191), // Rule ID 670 // |
| 46190 | /* 129159 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), |
| 46191 | /* 129162 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 46192 | /* 129165 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 46193 | /* 129169 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 46194 | /* 129173 */ // (fnearbyint:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VRINTRD:{ *:[f64] } DPR:{ *:[f64] }:$Dm) |
| 46195 | /* 129173 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTRD), |
| 46196 | /* 129176 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 46197 | /* 129178 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dm |
| 46198 | /* 129180 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 46199 | /* 129183 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46200 | /* 129189 */ GIR_RootConstrainSelectedInstOperands, |
| 46201 | /* 129190 */ // GIR_Coverage, 670, |
| 46202 | /* 129190 */ GIR_EraseRootFromParent_Done, |
| 46203 | /* 129191 */ // Label 2635: @129191 |
| 46204 | /* 129191 */ GIM_Reject, |
| 46205 | /* 129192 */ // Label 2632: @129192 |
| 46206 | /* 129192 */ GIM_Reject, |
| 46207 | /* 129193 */ // Label 72: @129193 |
| 46208 | /* 129193 */ GIM_Try, /*On fail goto*//*Label 2636*/ GIMT_Encode4(129208), // Rule ID 12 // |
| 46209 | /* 129198 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM_UseNaClTrap), |
| 46210 | /* 129201 */ // (trap) => (TRAPNaCl) |
| 46211 | /* 129201 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::TRAPNaCl), |
| 46212 | /* 129206 */ GIR_RootConstrainSelectedInstOperands, |
| 46213 | /* 129207 */ // GIR_Coverage, 12, |
| 46214 | /* 129207 */ GIR_Done, |
| 46215 | /* 129208 */ // Label 2636: @129208 |
| 46216 | /* 129208 */ GIM_Try, /*On fail goto*//*Label 2637*/ GIMT_Encode4(129223), // Rule ID 13 // |
| 46217 | /* 129213 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseNaClTrap_IsARM), |
| 46218 | /* 129216 */ // (trap) => (TRAP) |
| 46219 | /* 129216 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::TRAP), |
| 46220 | /* 129221 */ GIR_RootConstrainSelectedInstOperands, |
| 46221 | /* 129222 */ // GIR_Coverage, 13, |
| 46222 | /* 129222 */ GIR_Done, |
| 46223 | /* 129223 */ // Label 2637: @129223 |
| 46224 | /* 129223 */ GIM_Try, /*On fail goto*//*Label 2638*/ GIMT_Encode4(129238), // Rule ID 285 // |
| 46225 | /* 129228 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb), |
| 46226 | /* 129231 */ // (trap) => (tTRAP) |
| 46227 | /* 129231 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::tTRAP), |
| 46228 | /* 129236 */ GIR_RootConstrainSelectedInstOperands, |
| 46229 | /* 129237 */ // GIR_Coverage, 285, |
| 46230 | /* 129237 */ GIR_Done, |
| 46231 | /* 129238 */ // Label 2638: @129238 |
| 46232 | /* 129238 */ GIM_Reject, |
| 46233 | /* 129239 */ // Label 73: @129239 |
| 46234 | /* 129239 */ GIM_Try, /*On fail goto*//*Label 2639*/ GIMT_Encode4(129255), // Rule ID 1838 // |
| 46235 | /* 129244 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5T_IsARM), |
| 46236 | /* 129247 */ // (debugtrap) => (BKPT 0:{ *:[i32] }) |
| 46237 | /* 129247 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::BKPT), |
| 46238 | /* 129250 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 46239 | /* 129253 */ GIR_RootConstrainSelectedInstOperands, |
| 46240 | /* 129254 */ // GIR_Coverage, 1838, |
| 46241 | /* 129254 */ GIR_EraseRootFromParent_Done, |
| 46242 | /* 129255 */ // Label 2639: @129255 |
| 46243 | /* 129255 */ GIM_Try, /*On fail goto*//*Label 2640*/ GIMT_Encode4(129282), // Rule ID 1839 // |
| 46244 | /* 129260 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM_NoV5T), |
| 46245 | /* 129263 */ // (debugtrap) => (UDF 254:{ *:[i32] }) |
| 46246 | /* 129263 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UDF), |
| 46247 | /* 129266 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(254), |
| 46248 | /* 129276 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 46249 | /* 129280 */ GIR_RootConstrainSelectedInstOperands, |
| 46250 | /* 129281 */ // GIR_Coverage, 1839, |
| 46251 | /* 129281 */ GIR_EraseRootFromParent_Done, |
| 46252 | /* 129282 */ // Label 2640: @129282 |
| 46253 | /* 129282 */ GIM_Try, /*On fail goto*//*Label 2641*/ GIMT_Encode4(129298), // Rule ID 2024 // |
| 46254 | /* 129287 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5T_IsThumb), |
| 46255 | /* 129290 */ // (debugtrap) => (tBKPT 0:{ *:[i32] }) |
| 46256 | /* 129290 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tBKPT), |
| 46257 | /* 129293 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 46258 | /* 129296 */ GIR_RootConstrainSelectedInstOperands, |
| 46259 | /* 129297 */ // GIR_Coverage, 2024, |
| 46260 | /* 129297 */ GIR_EraseRootFromParent_Done, |
| 46261 | /* 129298 */ // Label 2641: @129298 |
| 46262 | /* 129298 */ GIM_Try, /*On fail goto*//*Label 2642*/ GIMT_Encode4(129325), // Rule ID 2025 // |
| 46263 | /* 129303 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb_NoV5T), |
| 46264 | /* 129306 */ // (debugtrap) => (tUDF 254:{ *:[i32] }) |
| 46265 | /* 129306 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tUDF), |
| 46266 | /* 129309 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(254), |
| 46267 | /* 129319 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 46268 | /* 129323 */ GIR_RootConstrainSelectedInstOperands, |
| 46269 | /* 129324 */ // GIR_Coverage, 2025, |
| 46270 | /* 129324 */ GIR_EraseRootFromParent_Done, |
| 46271 | /* 129325 */ // Label 2642: @129325 |
| 46272 | /* 129325 */ GIM_Reject, |
| 46273 | /* 129326 */ // Label 74: @129326 |
| 46274 | /* 129326 */ GIM_Try, /*On fail goto*//*Label 2643*/ GIMT_Encode4(129746), |
| 46275 | /* 129331 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 46276 | /* 129334 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(8), GIMT_Encode2(16), /*)*//*default:*//*Label 2647*/ GIMT_Encode4(129632), |
| 46277 | /* 129345 */ /*GILLT_v4s32*//*Label 2644*/ GIMT_Encode4(129377), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 46278 | /* 129361 */ /*GILLT_v8s16*//*Label 2645*/ GIMT_Encode4(129448), GIMT_Encode4(0), GIMT_Encode4(0), |
| 46279 | /* 129373 */ /*GILLT_v16s8*//*Label 2646*/ GIMT_Encode4(129519), |
| 46280 | /* 129377 */ // Label 2644: @129377 |
| 46281 | /* 129377 */ GIM_Try, /*On fail goto*//*Label 2648*/ GIMT_Encode4(129447), // Rule ID 3241 // |
| 46282 | /* 129382 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 46283 | /* 129385 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 46284 | /* 129389 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 46285 | /* 129393 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 46286 | /* 129397 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 46287 | /* 129401 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 46288 | /* 129405 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 46289 | /* 129410 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 46290 | /* 129415 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 46291 | /* 129417 */ // (vecreduce_add:{ *:[i32] } (mul:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src1, MQPR:{ *:[v4i32] }:$src2)) => (MVE_VMLADAVu32:{ *:[i32] } ?:{ *:[v4i32] }:$src1, ?:{ *:[v4i32] }:$src2) |
| 46292 | /* 129417 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVu32), |
| 46293 | /* 129420 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 46294 | /* 129422 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 46295 | /* 129426 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2 |
| 46296 | /* 129430 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 46297 | /* 129433 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46298 | /* 129439 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46299 | /* 129445 */ GIR_RootConstrainSelectedInstOperands, |
| 46300 | /* 129446 */ // GIR_Coverage, 3241, |
| 46301 | /* 129446 */ GIR_EraseRootFromParent_Done, |
| 46302 | /* 129447 */ // Label 2648: @129447 |
| 46303 | /* 129447 */ GIM_Reject, |
| 46304 | /* 129448 */ // Label 2645: @129448 |
| 46305 | /* 129448 */ GIM_Try, /*On fail goto*//*Label 2649*/ GIMT_Encode4(129518), // Rule ID 3242 // |
| 46306 | /* 129453 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 46307 | /* 129456 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 46308 | /* 129460 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 46309 | /* 129464 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 46310 | /* 129468 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 46311 | /* 129472 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 46312 | /* 129476 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 46313 | /* 129481 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 46314 | /* 129486 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 46315 | /* 129488 */ // (vecreduce_add:{ *:[i32] } (mul:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src1, MQPR:{ *:[v8i16] }:$src2)) => (MVE_VMLADAVu16:{ *:[i32] } ?:{ *:[v8i16] }:$src1, ?:{ *:[v8i16] }:$src2) |
| 46316 | /* 129488 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVu16), |
| 46317 | /* 129491 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 46318 | /* 129493 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 46319 | /* 129497 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2 |
| 46320 | /* 129501 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 46321 | /* 129504 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46322 | /* 129510 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46323 | /* 129516 */ GIR_RootConstrainSelectedInstOperands, |
| 46324 | /* 129517 */ // GIR_Coverage, 3242, |
| 46325 | /* 129517 */ GIR_EraseRootFromParent_Done, |
| 46326 | /* 129518 */ // Label 2649: @129518 |
| 46327 | /* 129518 */ GIM_Reject, |
| 46328 | /* 129519 */ // Label 2646: @129519 |
| 46329 | /* 129519 */ GIM_Try, /*On fail goto*//*Label 2650*/ GIMT_Encode4(129631), |
| 46330 | /* 129524 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 46331 | /* 129528 */ GIM_Try, /*On fail goto*//*Label 2651*/ GIMT_Encode4(129594), // Rule ID 3245 // |
| 46332 | /* 129533 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 46333 | /* 129536 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 46334 | /* 129540 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 46335 | /* 129544 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, |
| 46336 | /* 129548 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, |
| 46337 | /* 129552 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 46338 | /* 129557 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 46339 | /* 129562 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 46340 | /* 129564 */ // (vecreduce_add:{ *:[i32] } (mul:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$src1, MQPR:{ *:[v16i8] }:$src2)) => (MVE_VMLADAVu8:{ *:[i32] } ?:{ *:[v16i8] }:$src1, ?:{ *:[v16i8] }:$src2) |
| 46341 | /* 129564 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVu8), |
| 46342 | /* 129567 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 46343 | /* 129569 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 46344 | /* 129573 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2 |
| 46345 | /* 129577 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 46346 | /* 129580 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46347 | /* 129586 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46348 | /* 129592 */ GIR_RootConstrainSelectedInstOperands, |
| 46349 | /* 129593 */ // GIR_Coverage, 3245, |
| 46350 | /* 129593 */ GIR_EraseRootFromParent_Done, |
| 46351 | /* 129594 */ // Label 2651: @129594 |
| 46352 | /* 129594 */ GIM_Try, /*On fail goto*//*Label 2652*/ GIMT_Encode4(129630), // Rule ID 3049 // |
| 46353 | /* 129599 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 46354 | /* 129602 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 46355 | /* 129606 */ // (vecreduce_add:{ *:[i32] } MQPR:{ *:[v16i8] }:$vec) => (MVE_VADDVu8no_acc:{ *:[i32] } ?:{ *:[v16i8] }:$vec) |
| 46356 | /* 129606 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDVu8no_acc), |
| 46357 | /* 129609 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda] |
| 46358 | /* 129611 */ GIR_RootToRootCopy, /*OpIdx*/1, // vec |
| 46359 | /* 129613 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 46360 | /* 129616 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46361 | /* 129622 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46362 | /* 129628 */ GIR_RootConstrainSelectedInstOperands, |
| 46363 | /* 129629 */ // GIR_Coverage, 3049, |
| 46364 | /* 129629 */ GIR_EraseRootFromParent_Done, |
| 46365 | /* 129630 */ // Label 2652: @129630 |
| 46366 | /* 129630 */ GIM_Reject, |
| 46367 | /* 129631 */ // Label 2650: @129631 |
| 46368 | /* 129631 */ GIM_Reject, |
| 46369 | /* 129632 */ // Label 2647: @129632 |
| 46370 | /* 129632 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 2655*/ GIMT_Encode4(129745), |
| 46371 | /* 129643 */ /*GILLT_v4s32*//*Label 2653*/ GIMT_Encode4(129663), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 46372 | /* 129659 */ /*GILLT_v8s16*//*Label 2654*/ GIMT_Encode4(129704), |
| 46373 | /* 129663 */ // Label 2653: @129663 |
| 46374 | /* 129663 */ GIM_Try, /*On fail goto*//*Label 2656*/ GIMT_Encode4(129703), // Rule ID 3087 // |
| 46375 | /* 129668 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 46376 | /* 129671 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 46377 | /* 129675 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 46378 | /* 129679 */ // (vecreduce_add:{ *:[i32] } MQPR:{ *:[v4i32] }:$vec) => (MVE_VADDVu32no_acc:{ *:[i32] } ?:{ *:[v4i32] }:$vec) |
| 46379 | /* 129679 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDVu32no_acc), |
| 46380 | /* 129682 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda] |
| 46381 | /* 129684 */ GIR_RootToRootCopy, /*OpIdx*/1, // vec |
| 46382 | /* 129686 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 46383 | /* 129689 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46384 | /* 129695 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46385 | /* 129701 */ GIR_RootConstrainSelectedInstOperands, |
| 46386 | /* 129702 */ // GIR_Coverage, 3087, |
| 46387 | /* 129702 */ GIR_EraseRootFromParent_Done, |
| 46388 | /* 129703 */ // Label 2656: @129703 |
| 46389 | /* 129703 */ GIM_Reject, |
| 46390 | /* 129704 */ // Label 2654: @129704 |
| 46391 | /* 129704 */ GIM_Try, /*On fail goto*//*Label 2657*/ GIMT_Encode4(129744), // Rule ID 3077 // |
| 46392 | /* 129709 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 46393 | /* 129712 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 46394 | /* 129716 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 46395 | /* 129720 */ // (vecreduce_add:{ *:[i32] } MQPR:{ *:[v8i16] }:$vec) => (MVE_VADDVu16no_acc:{ *:[i32] } ?:{ *:[v8i16] }:$vec) |
| 46396 | /* 129720 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDVu16no_acc), |
| 46397 | /* 129723 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda] |
| 46398 | /* 129725 */ GIR_RootToRootCopy, /*OpIdx*/1, // vec |
| 46399 | /* 129727 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 46400 | /* 129730 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46401 | /* 129736 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46402 | /* 129742 */ GIR_RootConstrainSelectedInstOperands, |
| 46403 | /* 129743 */ // GIR_Coverage, 3077, |
| 46404 | /* 129743 */ GIR_EraseRootFromParent_Done, |
| 46405 | /* 129744 */ // Label 2657: @129744 |
| 46406 | /* 129744 */ GIM_Reject, |
| 46407 | /* 129745 */ // Label 2655: @129745 |
| 46408 | /* 129745 */ GIM_Reject, |
| 46409 | /* 129746 */ // Label 2643: @129746 |
| 46410 | /* 129746 */ GIM_Reject, |
| 46411 | /* 129747 */ // Label 75: @129747 |
| 46412 | /* 129747 */ GIM_Try, /*On fail goto*//*Label 2658*/ GIMT_Encode4(130026), |
| 46413 | /* 129752 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 46414 | /* 129755 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(8), GIMT_Encode2(16), /*)*//*default:*//*Label 2662*/ GIMT_Encode4(130025), |
| 46415 | /* 129766 */ /*GILLT_v4s32*//*Label 2659*/ GIMT_Encode4(129798), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 46416 | /* 129782 */ /*GILLT_v8s16*//*Label 2660*/ GIMT_Encode4(129881), GIMT_Encode4(0), GIMT_Encode4(0), |
| 46417 | /* 129794 */ /*GILLT_v16s8*//*Label 2661*/ GIMT_Encode4(129949), |
| 46418 | /* 129798 */ // Label 2659: @129798 |
| 46419 | /* 129798 */ GIM_Try, /*On fail goto*//*Label 2663*/ GIMT_Encode4(129880), // Rule ID 3147 // |
| 46420 | /* 129803 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 46421 | /* 129806 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 46422 | /* 129810 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 46423 | /* 129814 */ // (vecreduce_smax:{ *:[i32] } MQPR:{ *:[v4i32] }:$src) => (MVE_VMAXVs32:{ *:[i32] } (t2MOVi:{ *:[i32] } -2147483648:{ *:[i32] }), ?:{ *:[v4i32] }:$src) |
| 46424 | /* 129814 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 46425 | /* 129817 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi), |
| 46426 | /* 129821 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 46427 | /* 129826 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(-2147483648), |
| 46428 | /* 129836 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 46429 | /* 129839 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46430 | /* 129845 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46431 | /* 129851 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 46432 | /* 129853 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVs32), |
| 46433 | /* 129856 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 46434 | /* 129858 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 46435 | /* 129861 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 46436 | /* 129863 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 46437 | /* 129866 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46438 | /* 129872 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46439 | /* 129878 */ GIR_RootConstrainSelectedInstOperands, |
| 46440 | /* 129879 */ // GIR_Coverage, 3147, |
| 46441 | /* 129879 */ GIR_EraseRootFromParent_Done, |
| 46442 | /* 129880 */ // Label 2663: @129880 |
| 46443 | /* 129880 */ GIM_Reject, |
| 46444 | /* 129881 */ // Label 2660: @129881 |
| 46445 | /* 129881 */ GIM_Try, /*On fail goto*//*Label 2664*/ GIMT_Encode4(129948), // Rule ID 3146 // |
| 46446 | /* 129886 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 46447 | /* 129889 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 46448 | /* 129893 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 46449 | /* 129897 */ // (vecreduce_smax:{ *:[i32] } MQPR:{ *:[v8i16] }:$src) => (MVE_VMAXVs16:{ *:[i32] } (t2MOVi32imm:{ *:[i32] } -32768:{ *:[i32] }), ?:{ *:[v8i16] }:$src) |
| 46450 | /* 129897 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 46451 | /* 129900 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi32imm), |
| 46452 | /* 129904 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 46453 | /* 129909 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(-32768), |
| 46454 | /* 129919 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 46455 | /* 129921 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVs16), |
| 46456 | /* 129924 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 46457 | /* 129926 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 46458 | /* 129929 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 46459 | /* 129931 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 46460 | /* 129934 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46461 | /* 129940 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46462 | /* 129946 */ GIR_RootConstrainSelectedInstOperands, |
| 46463 | /* 129947 */ // GIR_Coverage, 3146, |
| 46464 | /* 129947 */ GIR_EraseRootFromParent_Done, |
| 46465 | /* 129948 */ // Label 2664: @129948 |
| 46466 | /* 129948 */ GIM_Reject, |
| 46467 | /* 129949 */ // Label 2661: @129949 |
| 46468 | /* 129949 */ GIM_Try, /*On fail goto*//*Label 2665*/ GIMT_Encode4(130024), // Rule ID 3145 // |
| 46469 | /* 129954 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 46470 | /* 129957 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 46471 | /* 129961 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 46472 | /* 129965 */ // (vecreduce_smax:{ *:[i32] } MQPR:{ *:[v16i8] }:$src) => (MVE_VMAXVs8:{ *:[i32] } (t2MVNi:{ *:[i32] } 127:{ *:[i32] }), ?:{ *:[v16i8] }:$src) |
| 46473 | /* 129965 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 46474 | /* 129968 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MVNi), |
| 46475 | /* 129972 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 46476 | /* 129977 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/127, |
| 46477 | /* 129980 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 46478 | /* 129983 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46479 | /* 129989 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46480 | /* 129995 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 46481 | /* 129997 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVs8), |
| 46482 | /* 130000 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 46483 | /* 130002 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 46484 | /* 130005 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 46485 | /* 130007 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 46486 | /* 130010 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46487 | /* 130016 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46488 | /* 130022 */ GIR_RootConstrainSelectedInstOperands, |
| 46489 | /* 130023 */ // GIR_Coverage, 3145, |
| 46490 | /* 130023 */ GIR_EraseRootFromParent_Done, |
| 46491 | /* 130024 */ // Label 2665: @130024 |
| 46492 | /* 130024 */ GIM_Reject, |
| 46493 | /* 130025 */ // Label 2662: @130025 |
| 46494 | /* 130025 */ GIM_Reject, |
| 46495 | /* 130026 */ // Label 2658: @130026 |
| 46496 | /* 130026 */ GIM_Reject, |
| 46497 | /* 130027 */ // Label 76: @130027 |
| 46498 | /* 130027 */ GIM_Try, /*On fail goto*//*Label 2666*/ GIMT_Encode4(130315), |
| 46499 | /* 130032 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 46500 | /* 130035 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(8), GIMT_Encode2(16), /*)*//*default:*//*Label 2670*/ GIMT_Encode4(130314), |
| 46501 | /* 130046 */ /*GILLT_v4s32*//*Label 2667*/ GIMT_Encode4(130078), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 46502 | /* 130062 */ /*GILLT_v8s16*//*Label 2668*/ GIMT_Encode4(130161), GIMT_Encode4(0), GIMT_Encode4(0), |
| 46503 | /* 130074 */ /*GILLT_v16s8*//*Label 2669*/ GIMT_Encode4(130238), |
| 46504 | /* 130078 */ // Label 2667: @130078 |
| 46505 | /* 130078 */ GIM_Try, /*On fail goto*//*Label 2671*/ GIMT_Encode4(130160), // Rule ID 3153 // |
| 46506 | /* 130083 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 46507 | /* 130086 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 46508 | /* 130090 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 46509 | /* 130094 */ // (vecreduce_smin:{ *:[i32] } MQPR:{ *:[v4i32] }:$src) => (MVE_VMINVs32:{ *:[i32] } (t2MVNi:{ *:[i32] } -2147483648:{ *:[i32] }), ?:{ *:[v4i32] }:$src) |
| 46510 | /* 130094 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 46511 | /* 130097 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MVNi), |
| 46512 | /* 130101 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 46513 | /* 130106 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(-2147483648), |
| 46514 | /* 130116 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 46515 | /* 130119 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46516 | /* 130125 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46517 | /* 130131 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 46518 | /* 130133 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVs32), |
| 46519 | /* 130136 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 46520 | /* 130138 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 46521 | /* 130141 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 46522 | /* 130143 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 46523 | /* 130146 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46524 | /* 130152 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46525 | /* 130158 */ GIR_RootConstrainSelectedInstOperands, |
| 46526 | /* 130159 */ // GIR_Coverage, 3153, |
| 46527 | /* 130159 */ GIR_EraseRootFromParent_Done, |
| 46528 | /* 130160 */ // Label 2671: @130160 |
| 46529 | /* 130160 */ GIM_Reject, |
| 46530 | /* 130161 */ // Label 2668: @130161 |
| 46531 | /* 130161 */ GIM_Try, /*On fail goto*//*Label 2672*/ GIMT_Encode4(130237), // Rule ID 3152 // |
| 46532 | /* 130166 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 46533 | /* 130169 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 46534 | /* 130173 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 46535 | /* 130177 */ // (vecreduce_smin:{ *:[i32] } MQPR:{ *:[v8i16] }:$src) => (MVE_VMINVs16:{ *:[i32] } (t2MOVi16:{ *:[i32] } 32767:{ *:[i32] }), ?:{ *:[v8i16] }:$src) |
| 46536 | /* 130177 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 46537 | /* 130180 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi16), |
| 46538 | /* 130184 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 46539 | /* 130189 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(32767), |
| 46540 | /* 130199 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 46541 | /* 130202 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46542 | /* 130208 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 46543 | /* 130210 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVs16), |
| 46544 | /* 130213 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 46545 | /* 130215 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 46546 | /* 130218 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 46547 | /* 130220 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 46548 | /* 130223 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46549 | /* 130229 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46550 | /* 130235 */ GIR_RootConstrainSelectedInstOperands, |
| 46551 | /* 130236 */ // GIR_Coverage, 3152, |
| 46552 | /* 130236 */ GIR_EraseRootFromParent_Done, |
| 46553 | /* 130237 */ // Label 2672: @130237 |
| 46554 | /* 130237 */ GIM_Reject, |
| 46555 | /* 130238 */ // Label 2669: @130238 |
| 46556 | /* 130238 */ GIM_Try, /*On fail goto*//*Label 2673*/ GIMT_Encode4(130313), // Rule ID 3151 // |
| 46557 | /* 130243 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 46558 | /* 130246 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 46559 | /* 130250 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 46560 | /* 130254 */ // (vecreduce_smin:{ *:[i32] } MQPR:{ *:[v16i8] }:$src) => (MVE_VMINVs8:{ *:[i32] } (t2MOVi:{ *:[i32] } 127:{ *:[i32] }), ?:{ *:[v16i8] }:$src) |
| 46561 | /* 130254 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 46562 | /* 130257 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi), |
| 46563 | /* 130261 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 46564 | /* 130266 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/127, |
| 46565 | /* 130269 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 46566 | /* 130272 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46567 | /* 130278 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46568 | /* 130284 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 46569 | /* 130286 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVs8), |
| 46570 | /* 130289 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 46571 | /* 130291 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 46572 | /* 130294 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 46573 | /* 130296 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 46574 | /* 130299 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46575 | /* 130305 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46576 | /* 130311 */ GIR_RootConstrainSelectedInstOperands, |
| 46577 | /* 130312 */ // GIR_Coverage, 3151, |
| 46578 | /* 130312 */ GIR_EraseRootFromParent_Done, |
| 46579 | /* 130313 */ // Label 2673: @130313 |
| 46580 | /* 130313 */ GIM_Reject, |
| 46581 | /* 130314 */ // Label 2670: @130314 |
| 46582 | /* 130314 */ GIM_Reject, |
| 46583 | /* 130315 */ // Label 2666: @130315 |
| 46584 | /* 130315 */ GIM_Reject, |
| 46585 | /* 130316 */ // Label 77: @130316 |
| 46586 | /* 130316 */ GIM_Try, /*On fail goto*//*Label 2674*/ GIMT_Encode4(130596), |
| 46587 | /* 130321 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 46588 | /* 130324 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(8), GIMT_Encode2(16), /*)*//*default:*//*Label 2678*/ GIMT_Encode4(130595), |
| 46589 | /* 130335 */ /*GILLT_v4s32*//*Label 2675*/ GIMT_Encode4(130367), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 46590 | /* 130351 */ /*GILLT_v8s16*//*Label 2676*/ GIMT_Encode4(130443), GIMT_Encode4(0), GIMT_Encode4(0), |
| 46591 | /* 130363 */ /*GILLT_v16s8*//*Label 2677*/ GIMT_Encode4(130519), |
| 46592 | /* 130367 */ // Label 2675: @130367 |
| 46593 | /* 130367 */ GIM_Try, /*On fail goto*//*Label 2679*/ GIMT_Encode4(130442), // Rule ID 3150 // |
| 46594 | /* 130372 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 46595 | /* 130375 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 46596 | /* 130379 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 46597 | /* 130383 */ // (vecreduce_umax:{ *:[i32] } MQPR:{ *:[v4i32] }:$src) => (MVE_VMAXVu32:{ *:[i32] } (t2MOVi:{ *:[i32] } 0:{ *:[i32] }), ?:{ *:[v4i32] }:$src) |
| 46598 | /* 130383 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 46599 | /* 130386 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi), |
| 46600 | /* 130390 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 46601 | /* 130395 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 46602 | /* 130398 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 46603 | /* 130401 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46604 | /* 130407 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46605 | /* 130413 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 46606 | /* 130415 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVu32), |
| 46607 | /* 130418 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 46608 | /* 130420 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 46609 | /* 130423 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 46610 | /* 130425 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 46611 | /* 130428 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46612 | /* 130434 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46613 | /* 130440 */ GIR_RootConstrainSelectedInstOperands, |
| 46614 | /* 130441 */ // GIR_Coverage, 3150, |
| 46615 | /* 130441 */ GIR_EraseRootFromParent_Done, |
| 46616 | /* 130442 */ // Label 2679: @130442 |
| 46617 | /* 130442 */ GIM_Reject, |
| 46618 | /* 130443 */ // Label 2676: @130443 |
| 46619 | /* 130443 */ GIM_Try, /*On fail goto*//*Label 2680*/ GIMT_Encode4(130518), // Rule ID 3149 // |
| 46620 | /* 130448 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 46621 | /* 130451 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 46622 | /* 130455 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 46623 | /* 130459 */ // (vecreduce_umax:{ *:[i32] } MQPR:{ *:[v8i16] }:$src) => (MVE_VMAXVu16:{ *:[i32] } (t2MOVi:{ *:[i32] } 0:{ *:[i32] }), ?:{ *:[v8i16] }:$src) |
| 46624 | /* 130459 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 46625 | /* 130462 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi), |
| 46626 | /* 130466 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 46627 | /* 130471 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 46628 | /* 130474 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 46629 | /* 130477 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46630 | /* 130483 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46631 | /* 130489 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 46632 | /* 130491 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVu16), |
| 46633 | /* 130494 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 46634 | /* 130496 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 46635 | /* 130499 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 46636 | /* 130501 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 46637 | /* 130504 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46638 | /* 130510 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46639 | /* 130516 */ GIR_RootConstrainSelectedInstOperands, |
| 46640 | /* 130517 */ // GIR_Coverage, 3149, |
| 46641 | /* 130517 */ GIR_EraseRootFromParent_Done, |
| 46642 | /* 130518 */ // Label 2680: @130518 |
| 46643 | /* 130518 */ GIM_Reject, |
| 46644 | /* 130519 */ // Label 2677: @130519 |
| 46645 | /* 130519 */ GIM_Try, /*On fail goto*//*Label 2681*/ GIMT_Encode4(130594), // Rule ID 3148 // |
| 46646 | /* 130524 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 46647 | /* 130527 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 46648 | /* 130531 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 46649 | /* 130535 */ // (vecreduce_umax:{ *:[i32] } MQPR:{ *:[v16i8] }:$src) => (MVE_VMAXVu8:{ *:[i32] } (t2MOVi:{ *:[i32] } 0:{ *:[i32] }), ?:{ *:[v16i8] }:$src) |
| 46650 | /* 130535 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 46651 | /* 130538 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi), |
| 46652 | /* 130542 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 46653 | /* 130547 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 46654 | /* 130550 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 46655 | /* 130553 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46656 | /* 130559 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46657 | /* 130565 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 46658 | /* 130567 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVu8), |
| 46659 | /* 130570 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 46660 | /* 130572 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 46661 | /* 130575 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 46662 | /* 130577 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 46663 | /* 130580 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46664 | /* 130586 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46665 | /* 130592 */ GIR_RootConstrainSelectedInstOperands, |
| 46666 | /* 130593 */ // GIR_Coverage, 3148, |
| 46667 | /* 130593 */ GIR_EraseRootFromParent_Done, |
| 46668 | /* 130594 */ // Label 2681: @130594 |
| 46669 | /* 130594 */ GIM_Reject, |
| 46670 | /* 130595 */ // Label 2678: @130595 |
| 46671 | /* 130595 */ GIM_Reject, |
| 46672 | /* 130596 */ // Label 2674: @130596 |
| 46673 | /* 130596 */ GIM_Reject, |
| 46674 | /* 130597 */ // Label 78: @130597 |
| 46675 | /* 130597 */ GIM_Try, /*On fail goto*//*Label 2682*/ GIMT_Encode4(130892), |
| 46676 | /* 130602 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 46677 | /* 130605 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(8), GIMT_Encode2(16), /*)*//*default:*//*Label 2686*/ GIMT_Encode4(130891), |
| 46678 | /* 130616 */ /*GILLT_v4s32*//*Label 2683*/ GIMT_Encode4(130648), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 46679 | /* 130632 */ /*GILLT_v8s16*//*Label 2684*/ GIMT_Encode4(130731), GIMT_Encode4(0), GIMT_Encode4(0), |
| 46680 | /* 130644 */ /*GILLT_v16s8*//*Label 2685*/ GIMT_Encode4(130808), |
| 46681 | /* 130648 */ // Label 2683: @130648 |
| 46682 | /* 130648 */ GIM_Try, /*On fail goto*//*Label 2687*/ GIMT_Encode4(130730), // Rule ID 3156 // |
| 46683 | /* 130653 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 46684 | /* 130656 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 46685 | /* 130660 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 46686 | /* 130664 */ // (vecreduce_umin:{ *:[i32] } MQPR:{ *:[v4i32] }:$src) => (MVE_VMINVu32:{ *:[i32] } (t2MOVi:{ *:[i32] } 4294967295:{ *:[i32] }), ?:{ *:[v4i32] }:$src) |
| 46687 | /* 130664 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 46688 | /* 130667 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi), |
| 46689 | /* 130671 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 46690 | /* 130676 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(4294967295), |
| 46691 | /* 130686 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 46692 | /* 130689 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46693 | /* 130695 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46694 | /* 130701 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 46695 | /* 130703 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVu32), |
| 46696 | /* 130706 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 46697 | /* 130708 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 46698 | /* 130711 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 46699 | /* 130713 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 46700 | /* 130716 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46701 | /* 130722 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46702 | /* 130728 */ GIR_RootConstrainSelectedInstOperands, |
| 46703 | /* 130729 */ // GIR_Coverage, 3156, |
| 46704 | /* 130729 */ GIR_EraseRootFromParent_Done, |
| 46705 | /* 130730 */ // Label 2687: @130730 |
| 46706 | /* 130730 */ GIM_Reject, |
| 46707 | /* 130731 */ // Label 2684: @130731 |
| 46708 | /* 130731 */ GIM_Try, /*On fail goto*//*Label 2688*/ GIMT_Encode4(130807), // Rule ID 3155 // |
| 46709 | /* 130736 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 46710 | /* 130739 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 46711 | /* 130743 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 46712 | /* 130747 */ // (vecreduce_umin:{ *:[i32] } MQPR:{ *:[v8i16] }:$src) => (MVE_VMINVu16:{ *:[i32] } (t2MOVi16:{ *:[i32] } 65535:{ *:[i32] }), ?:{ *:[v8i16] }:$src) |
| 46713 | /* 130747 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 46714 | /* 130750 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi16), |
| 46715 | /* 130754 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 46716 | /* 130759 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(65535), |
| 46717 | /* 130769 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 46718 | /* 130772 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46719 | /* 130778 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 46720 | /* 130780 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVu16), |
| 46721 | /* 130783 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 46722 | /* 130785 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 46723 | /* 130788 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 46724 | /* 130790 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 46725 | /* 130793 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46726 | /* 130799 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46727 | /* 130805 */ GIR_RootConstrainSelectedInstOperands, |
| 46728 | /* 130806 */ // GIR_Coverage, 3155, |
| 46729 | /* 130806 */ GIR_EraseRootFromParent_Done, |
| 46730 | /* 130807 */ // Label 2688: @130807 |
| 46731 | /* 130807 */ GIM_Reject, |
| 46732 | /* 130808 */ // Label 2685: @130808 |
| 46733 | /* 130808 */ GIM_Try, /*On fail goto*//*Label 2689*/ GIMT_Encode4(130890), // Rule ID 3154 // |
| 46734 | /* 130813 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt), |
| 46735 | /* 130816 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 46736 | /* 130820 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 46737 | /* 130824 */ // (vecreduce_umin:{ *:[i32] } MQPR:{ *:[v16i8] }:$src) => (MVE_VMINVu8:{ *:[i32] } (t2MOVi:{ *:[i32] } 255:{ *:[i32] }), ?:{ *:[v16i8] }:$src) |
| 46738 | /* 130824 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 46739 | /* 130827 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi), |
| 46740 | /* 130831 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 46741 | /* 130836 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(255), |
| 46742 | /* 130846 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 46743 | /* 130849 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46744 | /* 130855 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46745 | /* 130861 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 46746 | /* 130863 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVu8), |
| 46747 | /* 130866 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 46748 | /* 130868 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 46749 | /* 130871 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 46750 | /* 130873 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 46751 | /* 130876 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46752 | /* 130882 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46753 | /* 130888 */ GIR_RootConstrainSelectedInstOperands, |
| 46754 | /* 130889 */ // GIR_Coverage, 3154, |
| 46755 | /* 130889 */ GIR_EraseRootFromParent_Done, |
| 46756 | /* 130890 */ // Label 2689: @130890 |
| 46757 | /* 130890 */ GIM_Reject, |
| 46758 | /* 130891 */ // Label 2686: @130891 |
| 46759 | /* 130891 */ GIM_Reject, |
| 46760 | /* 130892 */ // Label 2682: @130892 |
| 46761 | /* 130892 */ GIM_Reject, |
| 46762 | /* 130893 */ // Label 79: @130893 |
| 46763 | /* 130893 */ GIM_Reject, |
| 46764 | /* 130894 */ }; // Size: 130894 bytes |
| 46765 | return MatchTable0; |
| 46766 | } |
| 46767 | #undef GIMT_Encode2 |
| 46768 | #undef GIMT_Encode4 |
| 46769 | #undef GIMT_Encode8 |
| 46770 | |
| 46771 | #endif // ifdef GET_GLOBALISEL_IMPL |
| 46772 | |
| 46773 | #ifdef GET_GLOBALISEL_PREDICATES_DECL |
| 46774 | PredicateBitset AvailableModuleFeatures; |
| 46775 | mutable PredicateBitset AvailableFunctionFeatures; |
| 46776 | PredicateBitset getAvailableFeatures() const { |
| 46777 | return AvailableModuleFeatures | AvailableFunctionFeatures; |
| 46778 | } |
| 46779 | PredicateBitset |
| 46780 | computeAvailableModuleFeatures(const ARMSubtarget *Subtarget) const; |
| 46781 | PredicateBitset |
| 46782 | computeAvailableFunctionFeatures(const ARMSubtarget *Subtarget, |
| 46783 | const MachineFunction *MF) const; |
| 46784 | void setupGeneratedPerFunctionState(MachineFunction &MF) override; |
| 46785 | #endif // ifdef GET_GLOBALISEL_PREDICATES_DECL |
| 46786 | #ifdef GET_GLOBALISEL_PREDICATES_INIT |
| 46787 | AvailableModuleFeatures(computeAvailableModuleFeatures(&STI)), |
| 46788 | AvailableFunctionFeatures() |
| 46789 | #endif // ifdef GET_GLOBALISEL_PREDICATES_INIT |
| 46790 |
Generated while processing llvm_projects/llvm/lib/Target/ARM/ARMInstructionSelector.cpp
Generated on 2025-Jul-04 from project llvm_projects revision main-0ba59587f
Powered by 
Code Browser 2.1
Generator usage only permitted with license.