| 1 | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
|---|---|
| 2 | |* *| |
| 3 | |* Target Instruction Enum Values and Descriptors *| |
| 4 | |* *| |
| 5 | |* Automatically generated file, do not edit! *| |
| 6 | |* *| |
| 7 | \*===----------------------------------------------------------------------===*/ |
| 8 | |
| 9 | #ifdef GET_INSTRINFO_ENUM |
| 10 | #undef GET_INSTRINFO_ENUM |
| 11 | namespace llvm::ARM { |
| 12 | enum { |
| 13 | PHI = 0, |
| 14 | INLINEASM = 1, |
| 15 | INLINEASM_BR = 2, |
| 16 | CFI_INSTRUCTION = 3, |
| 17 | EH_LABEL = 4, |
| 18 | GC_LABEL = 5, |
| 19 | ANNOTATION_LABEL = 6, |
| 20 | KILL = 7, |
| 21 | EXTRACT_SUBREG = 8, |
| 22 | INSERT_SUBREG = 9, |
| 23 | IMPLICIT_DEF = 10, |
| 24 | INIT_UNDEF = 11, |
| 25 | SUBREG_TO_REG = 12, |
| 26 | COPY_TO_REGCLASS = 13, |
| 27 | DBG_VALUE = 14, |
| 28 | DBG_VALUE_LIST = 15, |
| 29 | DBG_INSTR_REF = 16, |
| 30 | DBG_PHI = 17, |
| 31 | DBG_LABEL = 18, |
| 32 | REG_SEQUENCE = 19, |
| 33 | COPY = 20, |
| 34 | BUNDLE = 21, |
| 35 | LIFETIME_START = 22, |
| 36 | LIFETIME_END = 23, |
| 37 | PSEUDO_PROBE = 24, |
| 38 | ARITH_FENCE = 25, |
| 39 | STACKMAP = 26, |
| 40 | FENTRY_CALL = 27, |
| 41 | PATCHPOINT = 28, |
| 42 | LOAD_STACK_GUARD = 29, |
| 43 | PREALLOCATED_SETUP = 30, |
| 44 | PREALLOCATED_ARG = 31, |
| 45 | STATEPOINT = 32, |
| 46 | LOCAL_ESCAPE = 33, |
| 47 | FAULTING_OP = 34, |
| 48 | PATCHABLE_OP = 35, |
| 49 | PATCHABLE_FUNCTION_ENTER = 36, |
| 50 | PATCHABLE_RET = 37, |
| 51 | PATCHABLE_FUNCTION_EXIT = 38, |
| 52 | PATCHABLE_TAIL_CALL = 39, |
| 53 | PATCHABLE_EVENT_CALL = 40, |
| 54 | PATCHABLE_TYPED_EVENT_CALL = 41, |
| 55 | ICALL_BRANCH_FUNNEL = 42, |
| 56 | FAKE_USE = 43, |
| 57 | MEMBARRIER = 44, |
| 58 | JUMP_TABLE_DEBUG_INFO = 45, |
| 59 | CONVERGENCECTRL_ENTRY = 46, |
| 60 | CONVERGENCECTRL_ANCHOR = 47, |
| 61 | CONVERGENCECTRL_LOOP = 48, |
| 62 | CONVERGENCECTRL_GLUE = 49, |
| 63 | G_ASSERT_SEXT = 50, |
| 64 | G_ASSERT_ZEXT = 51, |
| 65 | G_ASSERT_ALIGN = 52, |
| 66 | G_ADD = 53, |
| 67 | G_SUB = 54, |
| 68 | G_MUL = 55, |
| 69 | G_SDIV = 56, |
| 70 | G_UDIV = 57, |
| 71 | G_SREM = 58, |
| 72 | G_UREM = 59, |
| 73 | G_SDIVREM = 60, |
| 74 | G_UDIVREM = 61, |
| 75 | G_AND = 62, |
| 76 | G_OR = 63, |
| 77 | G_XOR = 64, |
| 78 | G_ABDS = 65, |
| 79 | G_ABDU = 66, |
| 80 | G_IMPLICIT_DEF = 67, |
| 81 | G_PHI = 68, |
| 82 | G_FRAME_INDEX = 69, |
| 83 | G_GLOBAL_VALUE = 70, |
| 84 | G_PTRAUTH_GLOBAL_VALUE = 71, |
| 85 | G_CONSTANT_POOL = 72, |
| 86 | G_EXTRACT = 73, |
| 87 | G_UNMERGE_VALUES = 74, |
| 88 | G_INSERT = 75, |
| 89 | G_MERGE_VALUES = 76, |
| 90 | G_BUILD_VECTOR = 77, |
| 91 | G_BUILD_VECTOR_TRUNC = 78, |
| 92 | G_CONCAT_VECTORS = 79, |
| 93 | G_PTRTOINT = 80, |
| 94 | G_INTTOPTR = 81, |
| 95 | G_BITCAST = 82, |
| 96 | G_FREEZE = 83, |
| 97 | G_CONSTANT_FOLD_BARRIER = 84, |
| 98 | G_INTRINSIC_FPTRUNC_ROUND = 85, |
| 99 | G_INTRINSIC_TRUNC = 86, |
| 100 | G_INTRINSIC_ROUND = 87, |
| 101 | G_INTRINSIC_LRINT = 88, |
| 102 | G_INTRINSIC_LLRINT = 89, |
| 103 | G_INTRINSIC_ROUNDEVEN = 90, |
| 104 | G_READCYCLECOUNTER = 91, |
| 105 | G_READSTEADYCOUNTER = 92, |
| 106 | G_LOAD = 93, |
| 107 | G_SEXTLOAD = 94, |
| 108 | G_ZEXTLOAD = 95, |
| 109 | G_INDEXED_LOAD = 96, |
| 110 | G_INDEXED_SEXTLOAD = 97, |
| 111 | G_INDEXED_ZEXTLOAD = 98, |
| 112 | G_STORE = 99, |
| 113 | G_INDEXED_STORE = 100, |
| 114 | G_ATOMIC_CMPXCHG_WITH_SUCCESS = 101, |
| 115 | G_ATOMIC_CMPXCHG = 102, |
| 116 | G_ATOMICRMW_XCHG = 103, |
| 117 | G_ATOMICRMW_ADD = 104, |
| 118 | G_ATOMICRMW_SUB = 105, |
| 119 | G_ATOMICRMW_AND = 106, |
| 120 | G_ATOMICRMW_NAND = 107, |
| 121 | G_ATOMICRMW_OR = 108, |
| 122 | G_ATOMICRMW_XOR = 109, |
| 123 | G_ATOMICRMW_MAX = 110, |
| 124 | G_ATOMICRMW_MIN = 111, |
| 125 | G_ATOMICRMW_UMAX = 112, |
| 126 | G_ATOMICRMW_UMIN = 113, |
| 127 | G_ATOMICRMW_FADD = 114, |
| 128 | G_ATOMICRMW_FSUB = 115, |
| 129 | G_ATOMICRMW_FMAX = 116, |
| 130 | G_ATOMICRMW_FMIN = 117, |
| 131 | G_ATOMICRMW_FMAXIMUM = 118, |
| 132 | G_ATOMICRMW_FMINIMUM = 119, |
| 133 | G_ATOMICRMW_UINC_WRAP = 120, |
| 134 | G_ATOMICRMW_UDEC_WRAP = 121, |
| 135 | G_ATOMICRMW_USUB_COND = 122, |
| 136 | G_ATOMICRMW_USUB_SAT = 123, |
| 137 | G_FENCE = 124, |
| 138 | G_PREFETCH = 125, |
| 139 | G_BRCOND = 126, |
| 140 | G_BRINDIRECT = 127, |
| 141 | G_INVOKE_REGION_START = 128, |
| 142 | G_INTRINSIC = 129, |
| 143 | G_INTRINSIC_W_SIDE_EFFECTS = 130, |
| 144 | G_INTRINSIC_CONVERGENT = 131, |
| 145 | G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 132, |
| 146 | G_ANYEXT = 133, |
| 147 | G_TRUNC = 134, |
| 148 | G_CONSTANT = 135, |
| 149 | G_FCONSTANT = 136, |
| 150 | G_VASTART = 137, |
| 151 | G_VAARG = 138, |
| 152 | G_SEXT = 139, |
| 153 | G_SEXT_INREG = 140, |
| 154 | G_ZEXT = 141, |
| 155 | G_SHL = 142, |
| 156 | G_LSHR = 143, |
| 157 | G_ASHR = 144, |
| 158 | G_FSHL = 145, |
| 159 | G_FSHR = 146, |
| 160 | G_ROTR = 147, |
| 161 | G_ROTL = 148, |
| 162 | G_ICMP = 149, |
| 163 | G_FCMP = 150, |
| 164 | G_SCMP = 151, |
| 165 | G_UCMP = 152, |
| 166 | G_SELECT = 153, |
| 167 | G_UADDO = 154, |
| 168 | G_UADDE = 155, |
| 169 | G_USUBO = 156, |
| 170 | G_USUBE = 157, |
| 171 | G_SADDO = 158, |
| 172 | G_SADDE = 159, |
| 173 | G_SSUBO = 160, |
| 174 | G_SSUBE = 161, |
| 175 | G_UMULO = 162, |
| 176 | G_SMULO = 163, |
| 177 | G_UMULH = 164, |
| 178 | G_SMULH = 165, |
| 179 | G_UADDSAT = 166, |
| 180 | G_SADDSAT = 167, |
| 181 | G_USUBSAT = 168, |
| 182 | G_SSUBSAT = 169, |
| 183 | G_USHLSAT = 170, |
| 184 | G_SSHLSAT = 171, |
| 185 | G_SMULFIX = 172, |
| 186 | G_UMULFIX = 173, |
| 187 | G_SMULFIXSAT = 174, |
| 188 | G_UMULFIXSAT = 175, |
| 189 | G_SDIVFIX = 176, |
| 190 | G_UDIVFIX = 177, |
| 191 | G_SDIVFIXSAT = 178, |
| 192 | G_UDIVFIXSAT = 179, |
| 193 | G_FADD = 180, |
| 194 | G_FSUB = 181, |
| 195 | G_FMUL = 182, |
| 196 | G_FMA = 183, |
| 197 | G_FMAD = 184, |
| 198 | G_FDIV = 185, |
| 199 | G_FREM = 186, |
| 200 | G_FPOW = 187, |
| 201 | G_FPOWI = 188, |
| 202 | G_FEXP = 189, |
| 203 | G_FEXP2 = 190, |
| 204 | G_FEXP10 = 191, |
| 205 | G_FLOG = 192, |
| 206 | G_FLOG2 = 193, |
| 207 | G_FLOG10 = 194, |
| 208 | G_FLDEXP = 195, |
| 209 | G_FFREXP = 196, |
| 210 | G_FNEG = 197, |
| 211 | G_FPEXT = 198, |
| 212 | G_FPTRUNC = 199, |
| 213 | G_FPTOSI = 200, |
| 214 | G_FPTOUI = 201, |
| 215 | G_SITOFP = 202, |
| 216 | G_UITOFP = 203, |
| 217 | G_FPTOSI_SAT = 204, |
| 218 | G_FPTOUI_SAT = 205, |
| 219 | G_FABS = 206, |
| 220 | G_FCOPYSIGN = 207, |
| 221 | G_IS_FPCLASS = 208, |
| 222 | G_FCANONICALIZE = 209, |
| 223 | G_FMINNUM = 210, |
| 224 | G_FMAXNUM = 211, |
| 225 | G_FMINNUM_IEEE = 212, |
| 226 | G_FMAXNUM_IEEE = 213, |
| 227 | G_FMINIMUM = 214, |
| 228 | G_FMAXIMUM = 215, |
| 229 | G_FMINIMUMNUM = 216, |
| 230 | G_FMAXIMUMNUM = 217, |
| 231 | G_GET_FPENV = 218, |
| 232 | G_SET_FPENV = 219, |
| 233 | G_RESET_FPENV = 220, |
| 234 | G_GET_FPMODE = 221, |
| 235 | G_SET_FPMODE = 222, |
| 236 | G_RESET_FPMODE = 223, |
| 237 | G_PTR_ADD = 224, |
| 238 | G_PTRMASK = 225, |
| 239 | G_SMIN = 226, |
| 240 | G_SMAX = 227, |
| 241 | G_UMIN = 228, |
| 242 | G_UMAX = 229, |
| 243 | G_ABS = 230, |
| 244 | G_LROUND = 231, |
| 245 | G_LLROUND = 232, |
| 246 | G_BR = 233, |
| 247 | G_BRJT = 234, |
| 248 | G_VSCALE = 235, |
| 249 | G_INSERT_SUBVECTOR = 236, |
| 250 | G_EXTRACT_SUBVECTOR = 237, |
| 251 | G_INSERT_VECTOR_ELT = 238, |
| 252 | G_EXTRACT_VECTOR_ELT = 239, |
| 253 | G_SHUFFLE_VECTOR = 240, |
| 254 | G_SPLAT_VECTOR = 241, |
| 255 | G_STEP_VECTOR = 242, |
| 256 | G_VECTOR_COMPRESS = 243, |
| 257 | G_CTTZ = 244, |
| 258 | G_CTTZ_ZERO_UNDEF = 245, |
| 259 | G_CTLZ = 246, |
| 260 | G_CTLZ_ZERO_UNDEF = 247, |
| 261 | G_CTPOP = 248, |
| 262 | G_BSWAP = 249, |
| 263 | G_BITREVERSE = 250, |
| 264 | G_FCEIL = 251, |
| 265 | G_FCOS = 252, |
| 266 | G_FSIN = 253, |
| 267 | G_FSINCOS = 254, |
| 268 | G_FTAN = 255, |
| 269 | G_FACOS = 256, |
| 270 | G_FASIN = 257, |
| 271 | G_FATAN = 258, |
| 272 | G_FATAN2 = 259, |
| 273 | G_FCOSH = 260, |
| 274 | G_FSINH = 261, |
| 275 | G_FTANH = 262, |
| 276 | G_FSQRT = 263, |
| 277 | G_FFLOOR = 264, |
| 278 | G_FRINT = 265, |
| 279 | G_FNEARBYINT = 266, |
| 280 | G_ADDRSPACE_CAST = 267, |
| 281 | G_BLOCK_ADDR = 268, |
| 282 | G_JUMP_TABLE = 269, |
| 283 | G_DYN_STACKALLOC = 270, |
| 284 | G_STACKSAVE = 271, |
| 285 | G_STACKRESTORE = 272, |
| 286 | G_STRICT_FADD = 273, |
| 287 | G_STRICT_FSUB = 274, |
| 288 | G_STRICT_FMUL = 275, |
| 289 | G_STRICT_FDIV = 276, |
| 290 | G_STRICT_FREM = 277, |
| 291 | G_STRICT_FMA = 278, |
| 292 | G_STRICT_FSQRT = 279, |
| 293 | G_STRICT_FLDEXP = 280, |
| 294 | G_READ_REGISTER = 281, |
| 295 | G_WRITE_REGISTER = 282, |
| 296 | G_MEMCPY = 283, |
| 297 | G_MEMCPY_INLINE = 284, |
| 298 | G_MEMMOVE = 285, |
| 299 | G_MEMSET = 286, |
| 300 | G_BZERO = 287, |
| 301 | G_TRAP = 288, |
| 302 | G_DEBUGTRAP = 289, |
| 303 | G_UBSANTRAP = 290, |
| 304 | G_VECREDUCE_SEQ_FADD = 291, |
| 305 | G_VECREDUCE_SEQ_FMUL = 292, |
| 306 | G_VECREDUCE_FADD = 293, |
| 307 | G_VECREDUCE_FMUL = 294, |
| 308 | G_VECREDUCE_FMAX = 295, |
| 309 | G_VECREDUCE_FMIN = 296, |
| 310 | G_VECREDUCE_FMAXIMUM = 297, |
| 311 | G_VECREDUCE_FMINIMUM = 298, |
| 312 | G_VECREDUCE_ADD = 299, |
| 313 | G_VECREDUCE_MUL = 300, |
| 314 | G_VECREDUCE_AND = 301, |
| 315 | G_VECREDUCE_OR = 302, |
| 316 | G_VECREDUCE_XOR = 303, |
| 317 | G_VECREDUCE_SMAX = 304, |
| 318 | G_VECREDUCE_SMIN = 305, |
| 319 | G_VECREDUCE_UMAX = 306, |
| 320 | G_VECREDUCE_UMIN = 307, |
| 321 | G_SBFX = 308, |
| 322 | G_UBFX = 309, |
| 323 | ABS = 310, |
| 324 | ADDSri = 311, |
| 325 | ADDSrr = 312, |
| 326 | ADDSrsi = 313, |
| 327 | ADDSrsr = 314, |
| 328 | ADJCALLSTACKDOWN = 315, |
| 329 | ADJCALLSTACKUP = 316, |
| 330 | ASRi = 317, |
| 331 | ASRr = 318, |
| 332 | ASRs1 = 319, |
| 333 | B = 320, |
| 334 | BCCZi64 = 321, |
| 335 | BCCi64 = 322, |
| 336 | BLX_noip = 323, |
| 337 | BLX_pred_noip = 324, |
| 338 | BL_PUSHLR = 325, |
| 339 | BMOVPCB_CALL = 326, |
| 340 | BMOVPCRX_CALL = 327, |
| 341 | BR_JTadd = 328, |
| 342 | BR_JTm_i12 = 329, |
| 343 | BR_JTm_rs = 330, |
| 344 | BR_JTr = 331, |
| 345 | BX_CALL = 332, |
| 346 | CMP_SWAP_16 = 333, |
| 347 | CMP_SWAP_32 = 334, |
| 348 | CMP_SWAP_64 = 335, |
| 349 | CMP_SWAP_8 = 336, |
| 350 | CONSTPOOL_ENTRY = 337, |
| 351 | COPY_STRUCT_BYVAL_I32 = 338, |
| 352 | ITasm = 339, |
| 353 | Int_eh_sjlj_dispatchsetup = 340, |
| 354 | Int_eh_sjlj_longjmp = 341, |
| 355 | Int_eh_sjlj_setjmp = 342, |
| 356 | Int_eh_sjlj_setjmp_nofp = 343, |
| 357 | Int_eh_sjlj_setup_dispatch = 344, |
| 358 | JUMPTABLE_ADDRS = 345, |
| 359 | JUMPTABLE_INSTS = 346, |
| 360 | JUMPTABLE_TBB = 347, |
| 361 | JUMPTABLE_TBH = 348, |
| 362 | LDMIA_RET = 349, |
| 363 | LDRBT_POST = 350, |
| 364 | LDRConstPool = 351, |
| 365 | LDRHTii = 352, |
| 366 | LDRLIT_ga_abs = 353, |
| 367 | LDRLIT_ga_pcrel = 354, |
| 368 | LDRLIT_ga_pcrel_ldr = 355, |
| 369 | LDRSBTii = 356, |
| 370 | LDRSHTii = 357, |
| 371 | LDRT_POST = 358, |
| 372 | LEApcrel = 359, |
| 373 | LEApcrelJT = 360, |
| 374 | LOADDUAL = 361, |
| 375 | LSLi = 362, |
| 376 | LSLr = 363, |
| 377 | LSRi = 364, |
| 378 | LSRr = 365, |
| 379 | LSRs1 = 366, |
| 380 | MEMCPY = 367, |
| 381 | MLAv5 = 368, |
| 382 | MOVCCi = 369, |
| 383 | MOVCCi16 = 370, |
| 384 | MOVCCi32imm = 371, |
| 385 | MOVCCr = 372, |
| 386 | MOVCCsi = 373, |
| 387 | MOVCCsr = 374, |
| 388 | MOVPCRX = 375, |
| 389 | MOVTi16_ga_pcrel = 376, |
| 390 | MOV_ga_pcrel = 377, |
| 391 | MOV_ga_pcrel_ldr = 378, |
| 392 | MOVi16_ga_pcrel = 379, |
| 393 | MOVi32imm = 380, |
| 394 | MQPRCopy = 381, |
| 395 | MQQPRLoad = 382, |
| 396 | MQQPRStore = 383, |
| 397 | MQQQQPRLoad = 384, |
| 398 | MQQQQPRStore = 385, |
| 399 | MULv5 = 386, |
| 400 | MVE_MEMCPYLOOPINST = 387, |
| 401 | MVE_MEMSETLOOPINST = 388, |
| 402 | MVNCCi = 389, |
| 403 | PICADD = 390, |
| 404 | PICLDR = 391, |
| 405 | PICLDRB = 392, |
| 406 | PICLDRH = 393, |
| 407 | PICLDRSB = 394, |
| 408 | PICLDRSH = 395, |
| 409 | PICSTR = 396, |
| 410 | PICSTRB = 397, |
| 411 | PICSTRH = 398, |
| 412 | RORi = 399, |
| 413 | RORr = 400, |
| 414 | RRX = 401, |
| 415 | RRXi = 402, |
| 416 | RSBSri = 403, |
| 417 | RSBSrsi = 404, |
| 418 | RSBSrsr = 405, |
| 419 | SEH_EpilogEnd = 406, |
| 420 | SEH_EpilogStart = 407, |
| 421 | SEH_Nop = 408, |
| 422 | SEH_Nop_Ret = 409, |
| 423 | SEH_PrologEnd = 410, |
| 424 | SEH_SaveFRegs = 411, |
| 425 | SEH_SaveLR = 412, |
| 426 | SEH_SaveRegs = 413, |
| 427 | SEH_SaveRegs_Ret = 414, |
| 428 | SEH_SaveSP = 415, |
| 429 | SEH_StackAlloc = 416, |
| 430 | SMLALv5 = 417, |
| 431 | SMULLv5 = 418, |
| 432 | SPACE = 419, |
| 433 | STOREDUAL = 420, |
| 434 | STRBT_POST = 421, |
| 435 | STRBi_preidx = 422, |
| 436 | STRBr_preidx = 423, |
| 437 | STRH_preidx = 424, |
| 438 | STRT_POST = 425, |
| 439 | STRi_preidx = 426, |
| 440 | STRr_preidx = 427, |
| 441 | SUBS_PC_LR = 428, |
| 442 | SUBSri = 429, |
| 443 | SUBSrr = 430, |
| 444 | SUBSrsi = 431, |
| 445 | SUBSrsr = 432, |
| 446 | SpeculationBarrierISBDSBEndBB = 433, |
| 447 | SpeculationBarrierSBEndBB = 434, |
| 448 | TAILJMPd = 435, |
| 449 | TAILJMPr = 436, |
| 450 | TAILJMPr4 = 437, |
| 451 | TCRETURNdi = 438, |
| 452 | TCRETURNri = 439, |
| 453 | TCRETURNrinotr12 = 440, |
| 454 | TPsoft = 441, |
| 455 | UMLALv5 = 442, |
| 456 | UMULLv5 = 443, |
| 457 | VLD1LNdAsm_16 = 444, |
| 458 | VLD1LNdAsm_32 = 445, |
| 459 | VLD1LNdAsm_8 = 446, |
| 460 | VLD1LNdWB_fixed_Asm_16 = 447, |
| 461 | VLD1LNdWB_fixed_Asm_32 = 448, |
| 462 | VLD1LNdWB_fixed_Asm_8 = 449, |
| 463 | VLD1LNdWB_register_Asm_16 = 450, |
| 464 | VLD1LNdWB_register_Asm_32 = 451, |
| 465 | VLD1LNdWB_register_Asm_8 = 452, |
| 466 | VLD2LNdAsm_16 = 453, |
| 467 | VLD2LNdAsm_32 = 454, |
| 468 | VLD2LNdAsm_8 = 455, |
| 469 | VLD2LNdWB_fixed_Asm_16 = 456, |
| 470 | VLD2LNdWB_fixed_Asm_32 = 457, |
| 471 | VLD2LNdWB_fixed_Asm_8 = 458, |
| 472 | VLD2LNdWB_register_Asm_16 = 459, |
| 473 | VLD2LNdWB_register_Asm_32 = 460, |
| 474 | VLD2LNdWB_register_Asm_8 = 461, |
| 475 | VLD2LNqAsm_16 = 462, |
| 476 | VLD2LNqAsm_32 = 463, |
| 477 | VLD2LNqWB_fixed_Asm_16 = 464, |
| 478 | VLD2LNqWB_fixed_Asm_32 = 465, |
| 479 | VLD2LNqWB_register_Asm_16 = 466, |
| 480 | VLD2LNqWB_register_Asm_32 = 467, |
| 481 | VLD3DUPdAsm_16 = 468, |
| 482 | VLD3DUPdAsm_32 = 469, |
| 483 | VLD3DUPdAsm_8 = 470, |
| 484 | VLD3DUPdWB_fixed_Asm_16 = 471, |
| 485 | VLD3DUPdWB_fixed_Asm_32 = 472, |
| 486 | VLD3DUPdWB_fixed_Asm_8 = 473, |
| 487 | VLD3DUPdWB_register_Asm_16 = 474, |
| 488 | VLD3DUPdWB_register_Asm_32 = 475, |
| 489 | VLD3DUPdWB_register_Asm_8 = 476, |
| 490 | VLD3DUPqAsm_16 = 477, |
| 491 | VLD3DUPqAsm_32 = 478, |
| 492 | VLD3DUPqAsm_8 = 479, |
| 493 | VLD3DUPqWB_fixed_Asm_16 = 480, |
| 494 | VLD3DUPqWB_fixed_Asm_32 = 481, |
| 495 | VLD3DUPqWB_fixed_Asm_8 = 482, |
| 496 | VLD3DUPqWB_register_Asm_16 = 483, |
| 497 | VLD3DUPqWB_register_Asm_32 = 484, |
| 498 | VLD3DUPqWB_register_Asm_8 = 485, |
| 499 | VLD3LNdAsm_16 = 486, |
| 500 | VLD3LNdAsm_32 = 487, |
| 501 | VLD3LNdAsm_8 = 488, |
| 502 | VLD3LNdWB_fixed_Asm_16 = 489, |
| 503 | VLD3LNdWB_fixed_Asm_32 = 490, |
| 504 | VLD3LNdWB_fixed_Asm_8 = 491, |
| 505 | VLD3LNdWB_register_Asm_16 = 492, |
| 506 | VLD3LNdWB_register_Asm_32 = 493, |
| 507 | VLD3LNdWB_register_Asm_8 = 494, |
| 508 | VLD3LNqAsm_16 = 495, |
| 509 | VLD3LNqAsm_32 = 496, |
| 510 | VLD3LNqWB_fixed_Asm_16 = 497, |
| 511 | VLD3LNqWB_fixed_Asm_32 = 498, |
| 512 | VLD3LNqWB_register_Asm_16 = 499, |
| 513 | VLD3LNqWB_register_Asm_32 = 500, |
| 514 | VLD3dAsm_16 = 501, |
| 515 | VLD3dAsm_32 = 502, |
| 516 | VLD3dAsm_8 = 503, |
| 517 | VLD3dWB_fixed_Asm_16 = 504, |
| 518 | VLD3dWB_fixed_Asm_32 = 505, |
| 519 | VLD3dWB_fixed_Asm_8 = 506, |
| 520 | VLD3dWB_register_Asm_16 = 507, |
| 521 | VLD3dWB_register_Asm_32 = 508, |
| 522 | VLD3dWB_register_Asm_8 = 509, |
| 523 | VLD3qAsm_16 = 510, |
| 524 | VLD3qAsm_32 = 511, |
| 525 | VLD3qAsm_8 = 512, |
| 526 | VLD3qWB_fixed_Asm_16 = 513, |
| 527 | VLD3qWB_fixed_Asm_32 = 514, |
| 528 | VLD3qWB_fixed_Asm_8 = 515, |
| 529 | VLD3qWB_register_Asm_16 = 516, |
| 530 | VLD3qWB_register_Asm_32 = 517, |
| 531 | VLD3qWB_register_Asm_8 = 518, |
| 532 | VLD4DUPdAsm_16 = 519, |
| 533 | VLD4DUPdAsm_32 = 520, |
| 534 | VLD4DUPdAsm_8 = 521, |
| 535 | VLD4DUPdWB_fixed_Asm_16 = 522, |
| 536 | VLD4DUPdWB_fixed_Asm_32 = 523, |
| 537 | VLD4DUPdWB_fixed_Asm_8 = 524, |
| 538 | VLD4DUPdWB_register_Asm_16 = 525, |
| 539 | VLD4DUPdWB_register_Asm_32 = 526, |
| 540 | VLD4DUPdWB_register_Asm_8 = 527, |
| 541 | VLD4DUPqAsm_16 = 528, |
| 542 | VLD4DUPqAsm_32 = 529, |
| 543 | VLD4DUPqAsm_8 = 530, |
| 544 | VLD4DUPqWB_fixed_Asm_16 = 531, |
| 545 | VLD4DUPqWB_fixed_Asm_32 = 532, |
| 546 | VLD4DUPqWB_fixed_Asm_8 = 533, |
| 547 | VLD4DUPqWB_register_Asm_16 = 534, |
| 548 | VLD4DUPqWB_register_Asm_32 = 535, |
| 549 | VLD4DUPqWB_register_Asm_8 = 536, |
| 550 | VLD4LNdAsm_16 = 537, |
| 551 | VLD4LNdAsm_32 = 538, |
| 552 | VLD4LNdAsm_8 = 539, |
| 553 | VLD4LNdWB_fixed_Asm_16 = 540, |
| 554 | VLD4LNdWB_fixed_Asm_32 = 541, |
| 555 | VLD4LNdWB_fixed_Asm_8 = 542, |
| 556 | VLD4LNdWB_register_Asm_16 = 543, |
| 557 | VLD4LNdWB_register_Asm_32 = 544, |
| 558 | VLD4LNdWB_register_Asm_8 = 545, |
| 559 | VLD4LNqAsm_16 = 546, |
| 560 | VLD4LNqAsm_32 = 547, |
| 561 | VLD4LNqWB_fixed_Asm_16 = 548, |
| 562 | VLD4LNqWB_fixed_Asm_32 = 549, |
| 563 | VLD4LNqWB_register_Asm_16 = 550, |
| 564 | VLD4LNqWB_register_Asm_32 = 551, |
| 565 | VLD4dAsm_16 = 552, |
| 566 | VLD4dAsm_32 = 553, |
| 567 | VLD4dAsm_8 = 554, |
| 568 | VLD4dWB_fixed_Asm_16 = 555, |
| 569 | VLD4dWB_fixed_Asm_32 = 556, |
| 570 | VLD4dWB_fixed_Asm_8 = 557, |
| 571 | VLD4dWB_register_Asm_16 = 558, |
| 572 | VLD4dWB_register_Asm_32 = 559, |
| 573 | VLD4dWB_register_Asm_8 = 560, |
| 574 | VLD4qAsm_16 = 561, |
| 575 | VLD4qAsm_32 = 562, |
| 576 | VLD4qAsm_8 = 563, |
| 577 | VLD4qWB_fixed_Asm_16 = 564, |
| 578 | VLD4qWB_fixed_Asm_32 = 565, |
| 579 | VLD4qWB_fixed_Asm_8 = 566, |
| 580 | VLD4qWB_register_Asm_16 = 567, |
| 581 | VLD4qWB_register_Asm_32 = 568, |
| 582 | VLD4qWB_register_Asm_8 = 569, |
| 583 | VMOVD0 = 570, |
| 584 | VMOVDcc = 571, |
| 585 | VMOVHcc = 572, |
| 586 | VMOVQ0 = 573, |
| 587 | VMOVScc = 574, |
| 588 | VST1LNdAsm_16 = 575, |
| 589 | VST1LNdAsm_32 = 576, |
| 590 | VST1LNdAsm_8 = 577, |
| 591 | VST1LNdWB_fixed_Asm_16 = 578, |
| 592 | VST1LNdWB_fixed_Asm_32 = 579, |
| 593 | VST1LNdWB_fixed_Asm_8 = 580, |
| 594 | VST1LNdWB_register_Asm_16 = 581, |
| 595 | VST1LNdWB_register_Asm_32 = 582, |
| 596 | VST1LNdWB_register_Asm_8 = 583, |
| 597 | VST2LNdAsm_16 = 584, |
| 598 | VST2LNdAsm_32 = 585, |
| 599 | VST2LNdAsm_8 = 586, |
| 600 | VST2LNdWB_fixed_Asm_16 = 587, |
| 601 | VST2LNdWB_fixed_Asm_32 = 588, |
| 602 | VST2LNdWB_fixed_Asm_8 = 589, |
| 603 | VST2LNdWB_register_Asm_16 = 590, |
| 604 | VST2LNdWB_register_Asm_32 = 591, |
| 605 | VST2LNdWB_register_Asm_8 = 592, |
| 606 | VST2LNqAsm_16 = 593, |
| 607 | VST2LNqAsm_32 = 594, |
| 608 | VST2LNqWB_fixed_Asm_16 = 595, |
| 609 | VST2LNqWB_fixed_Asm_32 = 596, |
| 610 | VST2LNqWB_register_Asm_16 = 597, |
| 611 | VST2LNqWB_register_Asm_32 = 598, |
| 612 | VST3LNdAsm_16 = 599, |
| 613 | VST3LNdAsm_32 = 600, |
| 614 | VST3LNdAsm_8 = 601, |
| 615 | VST3LNdWB_fixed_Asm_16 = 602, |
| 616 | VST3LNdWB_fixed_Asm_32 = 603, |
| 617 | VST3LNdWB_fixed_Asm_8 = 604, |
| 618 | VST3LNdWB_register_Asm_16 = 605, |
| 619 | VST3LNdWB_register_Asm_32 = 606, |
| 620 | VST3LNdWB_register_Asm_8 = 607, |
| 621 | VST3LNqAsm_16 = 608, |
| 622 | VST3LNqAsm_32 = 609, |
| 623 | VST3LNqWB_fixed_Asm_16 = 610, |
| 624 | VST3LNqWB_fixed_Asm_32 = 611, |
| 625 | VST3LNqWB_register_Asm_16 = 612, |
| 626 | VST3LNqWB_register_Asm_32 = 613, |
| 627 | VST3dAsm_16 = 614, |
| 628 | VST3dAsm_32 = 615, |
| 629 | VST3dAsm_8 = 616, |
| 630 | VST3dWB_fixed_Asm_16 = 617, |
| 631 | VST3dWB_fixed_Asm_32 = 618, |
| 632 | VST3dWB_fixed_Asm_8 = 619, |
| 633 | VST3dWB_register_Asm_16 = 620, |
| 634 | VST3dWB_register_Asm_32 = 621, |
| 635 | VST3dWB_register_Asm_8 = 622, |
| 636 | VST3qAsm_16 = 623, |
| 637 | VST3qAsm_32 = 624, |
| 638 | VST3qAsm_8 = 625, |
| 639 | VST3qWB_fixed_Asm_16 = 626, |
| 640 | VST3qWB_fixed_Asm_32 = 627, |
| 641 | VST3qWB_fixed_Asm_8 = 628, |
| 642 | VST3qWB_register_Asm_16 = 629, |
| 643 | VST3qWB_register_Asm_32 = 630, |
| 644 | VST3qWB_register_Asm_8 = 631, |
| 645 | VST4LNdAsm_16 = 632, |
| 646 | VST4LNdAsm_32 = 633, |
| 647 | VST4LNdAsm_8 = 634, |
| 648 | VST4LNdWB_fixed_Asm_16 = 635, |
| 649 | VST4LNdWB_fixed_Asm_32 = 636, |
| 650 | VST4LNdWB_fixed_Asm_8 = 637, |
| 651 | VST4LNdWB_register_Asm_16 = 638, |
| 652 | VST4LNdWB_register_Asm_32 = 639, |
| 653 | VST4LNdWB_register_Asm_8 = 640, |
| 654 | VST4LNqAsm_16 = 641, |
| 655 | VST4LNqAsm_32 = 642, |
| 656 | VST4LNqWB_fixed_Asm_16 = 643, |
| 657 | VST4LNqWB_fixed_Asm_32 = 644, |
| 658 | VST4LNqWB_register_Asm_16 = 645, |
| 659 | VST4LNqWB_register_Asm_32 = 646, |
| 660 | VST4dAsm_16 = 647, |
| 661 | VST4dAsm_32 = 648, |
| 662 | VST4dAsm_8 = 649, |
| 663 | VST4dWB_fixed_Asm_16 = 650, |
| 664 | VST4dWB_fixed_Asm_32 = 651, |
| 665 | VST4dWB_fixed_Asm_8 = 652, |
| 666 | VST4dWB_register_Asm_16 = 653, |
| 667 | VST4dWB_register_Asm_32 = 654, |
| 668 | VST4dWB_register_Asm_8 = 655, |
| 669 | VST4qAsm_16 = 656, |
| 670 | VST4qAsm_32 = 657, |
| 671 | VST4qAsm_8 = 658, |
| 672 | VST4qWB_fixed_Asm_16 = 659, |
| 673 | VST4qWB_fixed_Asm_32 = 660, |
| 674 | VST4qWB_fixed_Asm_8 = 661, |
| 675 | VST4qWB_register_Asm_16 = 662, |
| 676 | VST4qWB_register_Asm_32 = 663, |
| 677 | VST4qWB_register_Asm_8 = 664, |
| 678 | WIN__CHKSTK = 665, |
| 679 | WIN__DBZCHK = 666, |
| 680 | t2ABS = 667, |
| 681 | t2ADDSri = 668, |
| 682 | t2ADDSrr = 669, |
| 683 | t2ADDSrs = 670, |
| 684 | t2BF_LabelPseudo = 671, |
| 685 | t2BR_JT = 672, |
| 686 | t2CALL_BTI = 673, |
| 687 | t2DoLoopStart = 674, |
| 688 | t2DoLoopStartTP = 675, |
| 689 | t2LDMIA_RET = 676, |
| 690 | t2LDRB_OFFSET_imm = 677, |
| 691 | t2LDRB_POST_imm = 678, |
| 692 | t2LDRB_PRE_imm = 679, |
| 693 | t2LDRBpcrel = 680, |
| 694 | t2LDRConstPool = 681, |
| 695 | t2LDRH_OFFSET_imm = 682, |
| 696 | t2LDRH_POST_imm = 683, |
| 697 | t2LDRH_PRE_imm = 684, |
| 698 | t2LDRHpcrel = 685, |
| 699 | t2LDRLIT_ga_pcrel = 686, |
| 700 | t2LDRSB_OFFSET_imm = 687, |
| 701 | t2LDRSB_POST_imm = 688, |
| 702 | t2LDRSB_PRE_imm = 689, |
| 703 | t2LDRSBpcrel = 690, |
| 704 | t2LDRSH_OFFSET_imm = 691, |
| 705 | t2LDRSH_POST_imm = 692, |
| 706 | t2LDRSH_PRE_imm = 693, |
| 707 | t2LDRSHpcrel = 694, |
| 708 | t2LDR_POST_imm = 695, |
| 709 | t2LDR_PRE_imm = 696, |
| 710 | t2LDRpci_pic = 697, |
| 711 | t2LDRpcrel = 698, |
| 712 | t2LEApcrel = 699, |
| 713 | t2LEApcrelJT = 700, |
| 714 | t2LoopDec = 701, |
| 715 | t2LoopEnd = 702, |
| 716 | t2LoopEndDec = 703, |
| 717 | t2MOVCCasr = 704, |
| 718 | t2MOVCCi = 705, |
| 719 | t2MOVCCi16 = 706, |
| 720 | t2MOVCCi32imm = 707, |
| 721 | t2MOVCClsl = 708, |
| 722 | t2MOVCClsr = 709, |
| 723 | t2MOVCCr = 710, |
| 724 | t2MOVCCror = 711, |
| 725 | t2MOVSsi = 712, |
| 726 | t2MOVSsr = 713, |
| 727 | t2MOVTi16_ga_pcrel = 714, |
| 728 | t2MOV_ga_pcrel = 715, |
| 729 | t2MOVi16_ga_pcrel = 716, |
| 730 | t2MOVi32imm = 717, |
| 731 | t2MOVsi = 718, |
| 732 | t2MOVsr = 719, |
| 733 | t2MVNCCi = 720, |
| 734 | t2RSBSri = 721, |
| 735 | t2RSBSrs = 722, |
| 736 | t2STRB_OFFSET_imm = 723, |
| 737 | t2STRB_POST_imm = 724, |
| 738 | t2STRB_PRE_imm = 725, |
| 739 | t2STRB_preidx = 726, |
| 740 | t2STRH_OFFSET_imm = 727, |
| 741 | t2STRH_POST_imm = 728, |
| 742 | t2STRH_PRE_imm = 729, |
| 743 | t2STRH_preidx = 730, |
| 744 | t2STR_POST_imm = 731, |
| 745 | t2STR_PRE_imm = 732, |
| 746 | t2STR_preidx = 733, |
| 747 | t2SUBSri = 734, |
| 748 | t2SUBSrr = 735, |
| 749 | t2SUBSrs = 736, |
| 750 | t2SpeculationBarrierISBDSBEndBB = 737, |
| 751 | t2SpeculationBarrierSBEndBB = 738, |
| 752 | t2TBB_JT = 739, |
| 753 | t2TBH_JT = 740, |
| 754 | t2WhileLoopSetup = 741, |
| 755 | t2WhileLoopStart = 742, |
| 756 | t2WhileLoopStartLR = 743, |
| 757 | t2WhileLoopStartTP = 744, |
| 758 | tADCS = 745, |
| 759 | tADDSi3 = 746, |
| 760 | tADDSi8 = 747, |
| 761 | tADDSrr = 748, |
| 762 | tADDframe = 749, |
| 763 | tADJCALLSTACKDOWN = 750, |
| 764 | tADJCALLSTACKUP = 751, |
| 765 | tBLXNS_CALL = 752, |
| 766 | tBLXr_noip = 753, |
| 767 | tBL_PUSHLR = 754, |
| 768 | tBRIND = 755, |
| 769 | tBR_JTr = 756, |
| 770 | tBXNS_RET = 757, |
| 771 | tBX_CALL = 758, |
| 772 | tBX_RET = 759, |
| 773 | tBX_RET_vararg = 760, |
| 774 | tBfar = 761, |
| 775 | tCMP_SWAP_16 = 762, |
| 776 | tCMP_SWAP_32 = 763, |
| 777 | tCMP_SWAP_8 = 764, |
| 778 | tLDMIA_UPD = 765, |
| 779 | tLDRConstPool = 766, |
| 780 | tLDRLIT_ga_abs = 767, |
| 781 | tLDRLIT_ga_pcrel = 768, |
| 782 | tLDR_postidx = 769, |
| 783 | tLDRpci_pic = 770, |
| 784 | tLEApcrel = 771, |
| 785 | tLEApcrelJT = 772, |
| 786 | tLSLSri = 773, |
| 787 | tMOVCCr_pseudo = 774, |
| 788 | tMOVi32imm = 775, |
| 789 | tPOP_RET = 776, |
| 790 | tRSBS = 777, |
| 791 | tSBCS = 778, |
| 792 | tSUBSi3 = 779, |
| 793 | tSUBSi8 = 780, |
| 794 | tSUBSrr = 781, |
| 795 | tTAILJMPd = 782, |
| 796 | tTAILJMPdND = 783, |
| 797 | tTAILJMPr = 784, |
| 798 | tTBB_JT = 785, |
| 799 | tTBH_JT = 786, |
| 800 | tTPsoft = 787, |
| 801 | ADCri = 788, |
| 802 | ADCrr = 789, |
| 803 | ADCrsi = 790, |
| 804 | ADCrsr = 791, |
| 805 | ADDri = 792, |
| 806 | ADDrr = 793, |
| 807 | ADDrsi = 794, |
| 808 | ADDrsr = 795, |
| 809 | ADR = 796, |
| 810 | AESD = 797, |
| 811 | AESE = 798, |
| 812 | AESIMC = 799, |
| 813 | AESMC = 800, |
| 814 | ANDri = 801, |
| 815 | ANDrr = 802, |
| 816 | ANDrsi = 803, |
| 817 | ANDrsr = 804, |
| 818 | BF16VDOTI_VDOTD = 805, |
| 819 | BF16VDOTI_VDOTQ = 806, |
| 820 | BF16VDOTS_VDOTD = 807, |
| 821 | BF16VDOTS_VDOTQ = 808, |
| 822 | BF16_VCVT = 809, |
| 823 | BF16_VCVTB = 810, |
| 824 | BF16_VCVTT = 811, |
| 825 | BFC = 812, |
| 826 | BFI = 813, |
| 827 | BICri = 814, |
| 828 | BICrr = 815, |
| 829 | BICrsi = 816, |
| 830 | BICrsr = 817, |
| 831 | BKPT = 818, |
| 832 | BL = 819, |
| 833 | BLX = 820, |
| 834 | BLX_pred = 821, |
| 835 | BLXi = 822, |
| 836 | BL_pred = 823, |
| 837 | BX = 824, |
| 838 | BXJ = 825, |
| 839 | BX_RET = 826, |
| 840 | BX_pred = 827, |
| 841 | Bcc = 828, |
| 842 | CDE_CX1 = 829, |
| 843 | CDE_CX1A = 830, |
| 844 | CDE_CX1D = 831, |
| 845 | CDE_CX1DA = 832, |
| 846 | CDE_CX2 = 833, |
| 847 | CDE_CX2A = 834, |
| 848 | CDE_CX2D = 835, |
| 849 | CDE_CX2DA = 836, |
| 850 | CDE_CX3 = 837, |
| 851 | CDE_CX3A = 838, |
| 852 | CDE_CX3D = 839, |
| 853 | CDE_CX3DA = 840, |
| 854 | CDE_VCX1A_fpdp = 841, |
| 855 | CDE_VCX1A_fpsp = 842, |
| 856 | CDE_VCX1A_vec = 843, |
| 857 | CDE_VCX1_fpdp = 844, |
| 858 | CDE_VCX1_fpsp = 845, |
| 859 | CDE_VCX1_vec = 846, |
| 860 | CDE_VCX2A_fpdp = 847, |
| 861 | CDE_VCX2A_fpsp = 848, |
| 862 | CDE_VCX2A_vec = 849, |
| 863 | CDE_VCX2_fpdp = 850, |
| 864 | CDE_VCX2_fpsp = 851, |
| 865 | CDE_VCX2_vec = 852, |
| 866 | CDE_VCX3A_fpdp = 853, |
| 867 | CDE_VCX3A_fpsp = 854, |
| 868 | CDE_VCX3A_vec = 855, |
| 869 | CDE_VCX3_fpdp = 856, |
| 870 | CDE_VCX3_fpsp = 857, |
| 871 | CDE_VCX3_vec = 858, |
| 872 | CDP = 859, |
| 873 | CDP2 = 860, |
| 874 | CLREX = 861, |
| 875 | CLZ = 862, |
| 876 | CMNri = 863, |
| 877 | CMNzrr = 864, |
| 878 | CMNzrsi = 865, |
| 879 | CMNzrsr = 866, |
| 880 | CMPri = 867, |
| 881 | CMPrr = 868, |
| 882 | CMPrsi = 869, |
| 883 | CMPrsr = 870, |
| 884 | CPS1p = 871, |
| 885 | CPS2p = 872, |
| 886 | CPS3p = 873, |
| 887 | CRC32B = 874, |
| 888 | CRC32CB = 875, |
| 889 | CRC32CH = 876, |
| 890 | CRC32CW = 877, |
| 891 | CRC32H = 878, |
| 892 | CRC32W = 879, |
| 893 | DBG = 880, |
| 894 | DMB = 881, |
| 895 | DSB = 882, |
| 896 | EORri = 883, |
| 897 | EORrr = 884, |
| 898 | EORrsi = 885, |
| 899 | EORrsr = 886, |
| 900 | ERET = 887, |
| 901 | FCONSTD = 888, |
| 902 | FCONSTH = 889, |
| 903 | FCONSTS = 890, |
| 904 | FLDMXDB_UPD = 891, |
| 905 | FLDMXIA = 892, |
| 906 | FLDMXIA_UPD = 893, |
| 907 | FMSTAT = 894, |
| 908 | FSTMXDB_UPD = 895, |
| 909 | FSTMXIA = 896, |
| 910 | FSTMXIA_UPD = 897, |
| 911 | HINT = 898, |
| 912 | HLT = 899, |
| 913 | HVC = 900, |
| 914 | ISB = 901, |
| 915 | LDA = 902, |
| 916 | LDAB = 903, |
| 917 | LDAEX = 904, |
| 918 | LDAEXB = 905, |
| 919 | LDAEXD = 906, |
| 920 | LDAEXH = 907, |
| 921 | LDAH = 908, |
| 922 | LDC2L_OFFSET = 909, |
| 923 | LDC2L_OPTION = 910, |
| 924 | LDC2L_POST = 911, |
| 925 | LDC2L_PRE = 912, |
| 926 | LDC2_OFFSET = 913, |
| 927 | LDC2_OPTION = 914, |
| 928 | LDC2_POST = 915, |
| 929 | LDC2_PRE = 916, |
| 930 | LDCL_OFFSET = 917, |
| 931 | LDCL_OPTION = 918, |
| 932 | LDCL_POST = 919, |
| 933 | LDCL_PRE = 920, |
| 934 | LDC_OFFSET = 921, |
| 935 | LDC_OPTION = 922, |
| 936 | LDC_POST = 923, |
| 937 | LDC_PRE = 924, |
| 938 | LDMDA = 925, |
| 939 | LDMDA_UPD = 926, |
| 940 | LDMDB = 927, |
| 941 | LDMDB_UPD = 928, |
| 942 | LDMIA = 929, |
| 943 | LDMIA_UPD = 930, |
| 944 | LDMIB = 931, |
| 945 | LDMIB_UPD = 932, |
| 946 | LDRBT_POST_IMM = 933, |
| 947 | LDRBT_POST_REG = 934, |
| 948 | LDRB_POST_IMM = 935, |
| 949 | LDRB_POST_REG = 936, |
| 950 | LDRB_PRE_IMM = 937, |
| 951 | LDRB_PRE_REG = 938, |
| 952 | LDRBi12 = 939, |
| 953 | LDRBrs = 940, |
| 954 | LDRD = 941, |
| 955 | LDRD_POST = 942, |
| 956 | LDRD_PRE = 943, |
| 957 | LDREX = 944, |
| 958 | LDREXB = 945, |
| 959 | LDREXD = 946, |
| 960 | LDREXH = 947, |
| 961 | LDRH = 948, |
| 962 | LDRHTi = 949, |
| 963 | LDRHTr = 950, |
| 964 | LDRH_POST = 951, |
| 965 | LDRH_PRE = 952, |
| 966 | LDRSB = 953, |
| 967 | LDRSBTi = 954, |
| 968 | LDRSBTr = 955, |
| 969 | LDRSB_POST = 956, |
| 970 | LDRSB_PRE = 957, |
| 971 | LDRSH = 958, |
| 972 | LDRSHTi = 959, |
| 973 | LDRSHTr = 960, |
| 974 | LDRSH_POST = 961, |
| 975 | LDRSH_PRE = 962, |
| 976 | LDRT_POST_IMM = 963, |
| 977 | LDRT_POST_REG = 964, |
| 978 | LDR_POST_IMM = 965, |
| 979 | LDR_POST_REG = 966, |
| 980 | LDR_PRE_IMM = 967, |
| 981 | LDR_PRE_REG = 968, |
| 982 | LDRcp = 969, |
| 983 | LDRi12 = 970, |
| 984 | LDRrs = 971, |
| 985 | MCR = 972, |
| 986 | MCR2 = 973, |
| 987 | MCRR = 974, |
| 988 | MCRR2 = 975, |
| 989 | MLA = 976, |
| 990 | MLS = 977, |
| 991 | MOVPCLR = 978, |
| 992 | MOVTi16 = 979, |
| 993 | MOVi = 980, |
| 994 | MOVi16 = 981, |
| 995 | MOVr = 982, |
| 996 | MOVr_TC = 983, |
| 997 | MOVsi = 984, |
| 998 | MOVsr = 985, |
| 999 | MRC = 986, |
| 1000 | MRC2 = 987, |
| 1001 | MRRC = 988, |
| 1002 | MRRC2 = 989, |
| 1003 | MRS = 990, |
| 1004 | MRSbanked = 991, |
| 1005 | MRSsys = 992, |
| 1006 | MSR = 993, |
| 1007 | MSRbanked = 994, |
| 1008 | MSRi = 995, |
| 1009 | MUL = 996, |
| 1010 | MVE_ASRLi = 997, |
| 1011 | MVE_ASRLr = 998, |
| 1012 | MVE_DLSTP_16 = 999, |
| 1013 | MVE_DLSTP_32 = 1000, |
| 1014 | MVE_DLSTP_64 = 1001, |
| 1015 | MVE_DLSTP_8 = 1002, |
| 1016 | MVE_LCTP = 1003, |
| 1017 | MVE_LETP = 1004, |
| 1018 | MVE_LSLLi = 1005, |
| 1019 | MVE_LSLLr = 1006, |
| 1020 | MVE_LSRL = 1007, |
| 1021 | MVE_SQRSHR = 1008, |
| 1022 | MVE_SQRSHRL = 1009, |
| 1023 | MVE_SQSHL = 1010, |
| 1024 | MVE_SQSHLL = 1011, |
| 1025 | MVE_SRSHR = 1012, |
| 1026 | MVE_SRSHRL = 1013, |
| 1027 | MVE_UQRSHL = 1014, |
| 1028 | MVE_UQRSHLL = 1015, |
| 1029 | MVE_UQSHL = 1016, |
| 1030 | MVE_UQSHLL = 1017, |
| 1031 | MVE_URSHR = 1018, |
| 1032 | MVE_URSHRL = 1019, |
| 1033 | MVE_VABAVs16 = 1020, |
| 1034 | MVE_VABAVs32 = 1021, |
| 1035 | MVE_VABAVs8 = 1022, |
| 1036 | MVE_VABAVu16 = 1023, |
| 1037 | MVE_VABAVu32 = 1024, |
| 1038 | MVE_VABAVu8 = 1025, |
| 1039 | MVE_VABDf16 = 1026, |
| 1040 | MVE_VABDf32 = 1027, |
| 1041 | MVE_VABDs16 = 1028, |
| 1042 | MVE_VABDs32 = 1029, |
| 1043 | MVE_VABDs8 = 1030, |
| 1044 | MVE_VABDu16 = 1031, |
| 1045 | MVE_VABDu32 = 1032, |
| 1046 | MVE_VABDu8 = 1033, |
| 1047 | MVE_VABSf16 = 1034, |
| 1048 | MVE_VABSf32 = 1035, |
| 1049 | MVE_VABSs16 = 1036, |
| 1050 | MVE_VABSs32 = 1037, |
| 1051 | MVE_VABSs8 = 1038, |
| 1052 | MVE_VADC = 1039, |
| 1053 | MVE_VADCI = 1040, |
| 1054 | MVE_VADDLVs32acc = 1041, |
| 1055 | MVE_VADDLVs32no_acc = 1042, |
| 1056 | MVE_VADDLVu32acc = 1043, |
| 1057 | MVE_VADDLVu32no_acc = 1044, |
| 1058 | MVE_VADDVs16acc = 1045, |
| 1059 | MVE_VADDVs16no_acc = 1046, |
| 1060 | MVE_VADDVs32acc = 1047, |
| 1061 | MVE_VADDVs32no_acc = 1048, |
| 1062 | MVE_VADDVs8acc = 1049, |
| 1063 | MVE_VADDVs8no_acc = 1050, |
| 1064 | MVE_VADDVu16acc = 1051, |
| 1065 | MVE_VADDVu16no_acc = 1052, |
| 1066 | MVE_VADDVu32acc = 1053, |
| 1067 | MVE_VADDVu32no_acc = 1054, |
| 1068 | MVE_VADDVu8acc = 1055, |
| 1069 | MVE_VADDVu8no_acc = 1056, |
| 1070 | MVE_VADD_qr_f16 = 1057, |
| 1071 | MVE_VADD_qr_f32 = 1058, |
| 1072 | MVE_VADD_qr_i16 = 1059, |
| 1073 | MVE_VADD_qr_i32 = 1060, |
| 1074 | MVE_VADD_qr_i8 = 1061, |
| 1075 | MVE_VADDf16 = 1062, |
| 1076 | MVE_VADDf32 = 1063, |
| 1077 | MVE_VADDi16 = 1064, |
| 1078 | MVE_VADDi32 = 1065, |
| 1079 | MVE_VADDi8 = 1066, |
| 1080 | MVE_VAND = 1067, |
| 1081 | MVE_VBIC = 1068, |
| 1082 | MVE_VBICimmi16 = 1069, |
| 1083 | MVE_VBICimmi32 = 1070, |
| 1084 | MVE_VBRSR16 = 1071, |
| 1085 | MVE_VBRSR32 = 1072, |
| 1086 | MVE_VBRSR8 = 1073, |
| 1087 | MVE_VCADDf16 = 1074, |
| 1088 | MVE_VCADDf32 = 1075, |
| 1089 | MVE_VCADDi16 = 1076, |
| 1090 | MVE_VCADDi32 = 1077, |
| 1091 | MVE_VCADDi8 = 1078, |
| 1092 | MVE_VCLSs16 = 1079, |
| 1093 | MVE_VCLSs32 = 1080, |
| 1094 | MVE_VCLSs8 = 1081, |
| 1095 | MVE_VCLZs16 = 1082, |
| 1096 | MVE_VCLZs32 = 1083, |
| 1097 | MVE_VCLZs8 = 1084, |
| 1098 | MVE_VCMLAf16 = 1085, |
| 1099 | MVE_VCMLAf32 = 1086, |
| 1100 | MVE_VCMPf16 = 1087, |
| 1101 | MVE_VCMPf16r = 1088, |
| 1102 | MVE_VCMPf32 = 1089, |
| 1103 | MVE_VCMPf32r = 1090, |
| 1104 | MVE_VCMPi16 = 1091, |
| 1105 | MVE_VCMPi16r = 1092, |
| 1106 | MVE_VCMPi32 = 1093, |
| 1107 | MVE_VCMPi32r = 1094, |
| 1108 | MVE_VCMPi8 = 1095, |
| 1109 | MVE_VCMPi8r = 1096, |
| 1110 | MVE_VCMPs16 = 1097, |
| 1111 | MVE_VCMPs16r = 1098, |
| 1112 | MVE_VCMPs32 = 1099, |
| 1113 | MVE_VCMPs32r = 1100, |
| 1114 | MVE_VCMPs8 = 1101, |
| 1115 | MVE_VCMPs8r = 1102, |
| 1116 | MVE_VCMPu16 = 1103, |
| 1117 | MVE_VCMPu16r = 1104, |
| 1118 | MVE_VCMPu32 = 1105, |
| 1119 | MVE_VCMPu32r = 1106, |
| 1120 | MVE_VCMPu8 = 1107, |
| 1121 | MVE_VCMPu8r = 1108, |
| 1122 | MVE_VCMULf16 = 1109, |
| 1123 | MVE_VCMULf32 = 1110, |
| 1124 | MVE_VCTP16 = 1111, |
| 1125 | MVE_VCTP32 = 1112, |
| 1126 | MVE_VCTP64 = 1113, |
| 1127 | MVE_VCTP8 = 1114, |
| 1128 | MVE_VCVTf16f32bh = 1115, |
| 1129 | MVE_VCVTf16f32th = 1116, |
| 1130 | MVE_VCVTf16s16_fix = 1117, |
| 1131 | MVE_VCVTf16s16n = 1118, |
| 1132 | MVE_VCVTf16u16_fix = 1119, |
| 1133 | MVE_VCVTf16u16n = 1120, |
| 1134 | MVE_VCVTf32f16bh = 1121, |
| 1135 | MVE_VCVTf32f16th = 1122, |
| 1136 | MVE_VCVTf32s32_fix = 1123, |
| 1137 | MVE_VCVTf32s32n = 1124, |
| 1138 | MVE_VCVTf32u32_fix = 1125, |
| 1139 | MVE_VCVTf32u32n = 1126, |
| 1140 | MVE_VCVTs16f16_fix = 1127, |
| 1141 | MVE_VCVTs16f16a = 1128, |
| 1142 | MVE_VCVTs16f16m = 1129, |
| 1143 | MVE_VCVTs16f16n = 1130, |
| 1144 | MVE_VCVTs16f16p = 1131, |
| 1145 | MVE_VCVTs16f16z = 1132, |
| 1146 | MVE_VCVTs32f32_fix = 1133, |
| 1147 | MVE_VCVTs32f32a = 1134, |
| 1148 | MVE_VCVTs32f32m = 1135, |
| 1149 | MVE_VCVTs32f32n = 1136, |
| 1150 | MVE_VCVTs32f32p = 1137, |
| 1151 | MVE_VCVTs32f32z = 1138, |
| 1152 | MVE_VCVTu16f16_fix = 1139, |
| 1153 | MVE_VCVTu16f16a = 1140, |
| 1154 | MVE_VCVTu16f16m = 1141, |
| 1155 | MVE_VCVTu16f16n = 1142, |
| 1156 | MVE_VCVTu16f16p = 1143, |
| 1157 | MVE_VCVTu16f16z = 1144, |
| 1158 | MVE_VCVTu32f32_fix = 1145, |
| 1159 | MVE_VCVTu32f32a = 1146, |
| 1160 | MVE_VCVTu32f32m = 1147, |
| 1161 | MVE_VCVTu32f32n = 1148, |
| 1162 | MVE_VCVTu32f32p = 1149, |
| 1163 | MVE_VCVTu32f32z = 1150, |
| 1164 | MVE_VDDUPu16 = 1151, |
| 1165 | MVE_VDDUPu32 = 1152, |
| 1166 | MVE_VDDUPu8 = 1153, |
| 1167 | MVE_VDUP16 = 1154, |
| 1168 | MVE_VDUP32 = 1155, |
| 1169 | MVE_VDUP8 = 1156, |
| 1170 | MVE_VDWDUPu16 = 1157, |
| 1171 | MVE_VDWDUPu32 = 1158, |
| 1172 | MVE_VDWDUPu8 = 1159, |
| 1173 | MVE_VEOR = 1160, |
| 1174 | MVE_VFMA_qr_Sf16 = 1161, |
| 1175 | MVE_VFMA_qr_Sf32 = 1162, |
| 1176 | MVE_VFMA_qr_f16 = 1163, |
| 1177 | MVE_VFMA_qr_f32 = 1164, |
| 1178 | MVE_VFMAf16 = 1165, |
| 1179 | MVE_VFMAf32 = 1166, |
| 1180 | MVE_VFMSf16 = 1167, |
| 1181 | MVE_VFMSf32 = 1168, |
| 1182 | MVE_VHADD_qr_s16 = 1169, |
| 1183 | MVE_VHADD_qr_s32 = 1170, |
| 1184 | MVE_VHADD_qr_s8 = 1171, |
| 1185 | MVE_VHADD_qr_u16 = 1172, |
| 1186 | MVE_VHADD_qr_u32 = 1173, |
| 1187 | MVE_VHADD_qr_u8 = 1174, |
| 1188 | MVE_VHADDs16 = 1175, |
| 1189 | MVE_VHADDs32 = 1176, |
| 1190 | MVE_VHADDs8 = 1177, |
| 1191 | MVE_VHADDu16 = 1178, |
| 1192 | MVE_VHADDu32 = 1179, |
| 1193 | MVE_VHADDu8 = 1180, |
| 1194 | MVE_VHCADDs16 = 1181, |
| 1195 | MVE_VHCADDs32 = 1182, |
| 1196 | MVE_VHCADDs8 = 1183, |
| 1197 | MVE_VHSUB_qr_s16 = 1184, |
| 1198 | MVE_VHSUB_qr_s32 = 1185, |
| 1199 | MVE_VHSUB_qr_s8 = 1186, |
| 1200 | MVE_VHSUB_qr_u16 = 1187, |
| 1201 | MVE_VHSUB_qr_u32 = 1188, |
| 1202 | MVE_VHSUB_qr_u8 = 1189, |
| 1203 | MVE_VHSUBs16 = 1190, |
| 1204 | MVE_VHSUBs32 = 1191, |
| 1205 | MVE_VHSUBs8 = 1192, |
| 1206 | MVE_VHSUBu16 = 1193, |
| 1207 | MVE_VHSUBu32 = 1194, |
| 1208 | MVE_VHSUBu8 = 1195, |
| 1209 | MVE_VIDUPu16 = 1196, |
| 1210 | MVE_VIDUPu32 = 1197, |
| 1211 | MVE_VIDUPu8 = 1198, |
| 1212 | MVE_VIWDUPu16 = 1199, |
| 1213 | MVE_VIWDUPu32 = 1200, |
| 1214 | MVE_VIWDUPu8 = 1201, |
| 1215 | MVE_VLD20_16 = 1202, |
| 1216 | MVE_VLD20_16_wb = 1203, |
| 1217 | MVE_VLD20_32 = 1204, |
| 1218 | MVE_VLD20_32_wb = 1205, |
| 1219 | MVE_VLD20_8 = 1206, |
| 1220 | MVE_VLD20_8_wb = 1207, |
| 1221 | MVE_VLD21_16 = 1208, |
| 1222 | MVE_VLD21_16_wb = 1209, |
| 1223 | MVE_VLD21_32 = 1210, |
| 1224 | MVE_VLD21_32_wb = 1211, |
| 1225 | MVE_VLD21_8 = 1212, |
| 1226 | MVE_VLD21_8_wb = 1213, |
| 1227 | MVE_VLD40_16 = 1214, |
| 1228 | MVE_VLD40_16_wb = 1215, |
| 1229 | MVE_VLD40_32 = 1216, |
| 1230 | MVE_VLD40_32_wb = 1217, |
| 1231 | MVE_VLD40_8 = 1218, |
| 1232 | MVE_VLD40_8_wb = 1219, |
| 1233 | MVE_VLD41_16 = 1220, |
| 1234 | MVE_VLD41_16_wb = 1221, |
| 1235 | MVE_VLD41_32 = 1222, |
| 1236 | MVE_VLD41_32_wb = 1223, |
| 1237 | MVE_VLD41_8 = 1224, |
| 1238 | MVE_VLD41_8_wb = 1225, |
| 1239 | MVE_VLD42_16 = 1226, |
| 1240 | MVE_VLD42_16_wb = 1227, |
| 1241 | MVE_VLD42_32 = 1228, |
| 1242 | MVE_VLD42_32_wb = 1229, |
| 1243 | MVE_VLD42_8 = 1230, |
| 1244 | MVE_VLD42_8_wb = 1231, |
| 1245 | MVE_VLD43_16 = 1232, |
| 1246 | MVE_VLD43_16_wb = 1233, |
| 1247 | MVE_VLD43_32 = 1234, |
| 1248 | MVE_VLD43_32_wb = 1235, |
| 1249 | MVE_VLD43_8 = 1236, |
| 1250 | MVE_VLD43_8_wb = 1237, |
| 1251 | MVE_VLDRBS16 = 1238, |
| 1252 | MVE_VLDRBS16_post = 1239, |
| 1253 | MVE_VLDRBS16_pre = 1240, |
| 1254 | MVE_VLDRBS16_rq = 1241, |
| 1255 | MVE_VLDRBS32 = 1242, |
| 1256 | MVE_VLDRBS32_post = 1243, |
| 1257 | MVE_VLDRBS32_pre = 1244, |
| 1258 | MVE_VLDRBS32_rq = 1245, |
| 1259 | MVE_VLDRBU16 = 1246, |
| 1260 | MVE_VLDRBU16_post = 1247, |
| 1261 | MVE_VLDRBU16_pre = 1248, |
| 1262 | MVE_VLDRBU16_rq = 1249, |
| 1263 | MVE_VLDRBU32 = 1250, |
| 1264 | MVE_VLDRBU32_post = 1251, |
| 1265 | MVE_VLDRBU32_pre = 1252, |
| 1266 | MVE_VLDRBU32_rq = 1253, |
| 1267 | MVE_VLDRBU8 = 1254, |
| 1268 | MVE_VLDRBU8_post = 1255, |
| 1269 | MVE_VLDRBU8_pre = 1256, |
| 1270 | MVE_VLDRBU8_rq = 1257, |
| 1271 | MVE_VLDRDU64_qi = 1258, |
| 1272 | MVE_VLDRDU64_qi_pre = 1259, |
| 1273 | MVE_VLDRDU64_rq = 1260, |
| 1274 | MVE_VLDRDU64_rq_u = 1261, |
| 1275 | MVE_VLDRHS32 = 1262, |
| 1276 | MVE_VLDRHS32_post = 1263, |
| 1277 | MVE_VLDRHS32_pre = 1264, |
| 1278 | MVE_VLDRHS32_rq = 1265, |
| 1279 | MVE_VLDRHS32_rq_u = 1266, |
| 1280 | MVE_VLDRHU16 = 1267, |
| 1281 | MVE_VLDRHU16_post = 1268, |
| 1282 | MVE_VLDRHU16_pre = 1269, |
| 1283 | MVE_VLDRHU16_rq = 1270, |
| 1284 | MVE_VLDRHU16_rq_u = 1271, |
| 1285 | MVE_VLDRHU32 = 1272, |
| 1286 | MVE_VLDRHU32_post = 1273, |
| 1287 | MVE_VLDRHU32_pre = 1274, |
| 1288 | MVE_VLDRHU32_rq = 1275, |
| 1289 | MVE_VLDRHU32_rq_u = 1276, |
| 1290 | MVE_VLDRWU32 = 1277, |
| 1291 | MVE_VLDRWU32_post = 1278, |
| 1292 | MVE_VLDRWU32_pre = 1279, |
| 1293 | MVE_VLDRWU32_qi = 1280, |
| 1294 | MVE_VLDRWU32_qi_pre = 1281, |
| 1295 | MVE_VLDRWU32_rq = 1282, |
| 1296 | MVE_VLDRWU32_rq_u = 1283, |
| 1297 | MVE_VMAXAVs16 = 1284, |
| 1298 | MVE_VMAXAVs32 = 1285, |
| 1299 | MVE_VMAXAVs8 = 1286, |
| 1300 | MVE_VMAXAs16 = 1287, |
| 1301 | MVE_VMAXAs32 = 1288, |
| 1302 | MVE_VMAXAs8 = 1289, |
| 1303 | MVE_VMAXNMAVf16 = 1290, |
| 1304 | MVE_VMAXNMAVf32 = 1291, |
| 1305 | MVE_VMAXNMAf16 = 1292, |
| 1306 | MVE_VMAXNMAf32 = 1293, |
| 1307 | MVE_VMAXNMVf16 = 1294, |
| 1308 | MVE_VMAXNMVf32 = 1295, |
| 1309 | MVE_VMAXNMf16 = 1296, |
| 1310 | MVE_VMAXNMf32 = 1297, |
| 1311 | MVE_VMAXVs16 = 1298, |
| 1312 | MVE_VMAXVs32 = 1299, |
| 1313 | MVE_VMAXVs8 = 1300, |
| 1314 | MVE_VMAXVu16 = 1301, |
| 1315 | MVE_VMAXVu32 = 1302, |
| 1316 | MVE_VMAXVu8 = 1303, |
| 1317 | MVE_VMAXs16 = 1304, |
| 1318 | MVE_VMAXs32 = 1305, |
| 1319 | MVE_VMAXs8 = 1306, |
| 1320 | MVE_VMAXu16 = 1307, |
| 1321 | MVE_VMAXu32 = 1308, |
| 1322 | MVE_VMAXu8 = 1309, |
| 1323 | MVE_VMINAVs16 = 1310, |
| 1324 | MVE_VMINAVs32 = 1311, |
| 1325 | MVE_VMINAVs8 = 1312, |
| 1326 | MVE_VMINAs16 = 1313, |
| 1327 | MVE_VMINAs32 = 1314, |
| 1328 | MVE_VMINAs8 = 1315, |
| 1329 | MVE_VMINNMAVf16 = 1316, |
| 1330 | MVE_VMINNMAVf32 = 1317, |
| 1331 | MVE_VMINNMAf16 = 1318, |
| 1332 | MVE_VMINNMAf32 = 1319, |
| 1333 | MVE_VMINNMVf16 = 1320, |
| 1334 | MVE_VMINNMVf32 = 1321, |
| 1335 | MVE_VMINNMf16 = 1322, |
| 1336 | MVE_VMINNMf32 = 1323, |
| 1337 | MVE_VMINVs16 = 1324, |
| 1338 | MVE_VMINVs32 = 1325, |
| 1339 | MVE_VMINVs8 = 1326, |
| 1340 | MVE_VMINVu16 = 1327, |
| 1341 | MVE_VMINVu32 = 1328, |
| 1342 | MVE_VMINVu8 = 1329, |
| 1343 | MVE_VMINs16 = 1330, |
| 1344 | MVE_VMINs32 = 1331, |
| 1345 | MVE_VMINs8 = 1332, |
| 1346 | MVE_VMINu16 = 1333, |
| 1347 | MVE_VMINu32 = 1334, |
| 1348 | MVE_VMINu8 = 1335, |
| 1349 | MVE_VMLADAVas16 = 1336, |
| 1350 | MVE_VMLADAVas32 = 1337, |
| 1351 | MVE_VMLADAVas8 = 1338, |
| 1352 | MVE_VMLADAVau16 = 1339, |
| 1353 | MVE_VMLADAVau32 = 1340, |
| 1354 | MVE_VMLADAVau8 = 1341, |
| 1355 | MVE_VMLADAVaxs16 = 1342, |
| 1356 | MVE_VMLADAVaxs32 = 1343, |
| 1357 | MVE_VMLADAVaxs8 = 1344, |
| 1358 | MVE_VMLADAVs16 = 1345, |
| 1359 | MVE_VMLADAVs32 = 1346, |
| 1360 | MVE_VMLADAVs8 = 1347, |
| 1361 | MVE_VMLADAVu16 = 1348, |
| 1362 | MVE_VMLADAVu32 = 1349, |
| 1363 | MVE_VMLADAVu8 = 1350, |
| 1364 | MVE_VMLADAVxs16 = 1351, |
| 1365 | MVE_VMLADAVxs32 = 1352, |
| 1366 | MVE_VMLADAVxs8 = 1353, |
| 1367 | MVE_VMLALDAVas16 = 1354, |
| 1368 | MVE_VMLALDAVas32 = 1355, |
| 1369 | MVE_VMLALDAVau16 = 1356, |
| 1370 | MVE_VMLALDAVau32 = 1357, |
| 1371 | MVE_VMLALDAVaxs16 = 1358, |
| 1372 | MVE_VMLALDAVaxs32 = 1359, |
| 1373 | MVE_VMLALDAVs16 = 1360, |
| 1374 | MVE_VMLALDAVs32 = 1361, |
| 1375 | MVE_VMLALDAVu16 = 1362, |
| 1376 | MVE_VMLALDAVu32 = 1363, |
| 1377 | MVE_VMLALDAVxs16 = 1364, |
| 1378 | MVE_VMLALDAVxs32 = 1365, |
| 1379 | MVE_VMLAS_qr_i16 = 1366, |
| 1380 | MVE_VMLAS_qr_i32 = 1367, |
| 1381 | MVE_VMLAS_qr_i8 = 1368, |
| 1382 | MVE_VMLA_qr_i16 = 1369, |
| 1383 | MVE_VMLA_qr_i32 = 1370, |
| 1384 | MVE_VMLA_qr_i8 = 1371, |
| 1385 | MVE_VMLSDAVas16 = 1372, |
| 1386 | MVE_VMLSDAVas32 = 1373, |
| 1387 | MVE_VMLSDAVas8 = 1374, |
| 1388 | MVE_VMLSDAVaxs16 = 1375, |
| 1389 | MVE_VMLSDAVaxs32 = 1376, |
| 1390 | MVE_VMLSDAVaxs8 = 1377, |
| 1391 | MVE_VMLSDAVs16 = 1378, |
| 1392 | MVE_VMLSDAVs32 = 1379, |
| 1393 | MVE_VMLSDAVs8 = 1380, |
| 1394 | MVE_VMLSDAVxs16 = 1381, |
| 1395 | MVE_VMLSDAVxs32 = 1382, |
| 1396 | MVE_VMLSDAVxs8 = 1383, |
| 1397 | MVE_VMLSLDAVas16 = 1384, |
| 1398 | MVE_VMLSLDAVas32 = 1385, |
| 1399 | MVE_VMLSLDAVaxs16 = 1386, |
| 1400 | MVE_VMLSLDAVaxs32 = 1387, |
| 1401 | MVE_VMLSLDAVs16 = 1388, |
| 1402 | MVE_VMLSLDAVs32 = 1389, |
| 1403 | MVE_VMLSLDAVxs16 = 1390, |
| 1404 | MVE_VMLSLDAVxs32 = 1391, |
| 1405 | MVE_VMOVLs16bh = 1392, |
| 1406 | MVE_VMOVLs16th = 1393, |
| 1407 | MVE_VMOVLs8bh = 1394, |
| 1408 | MVE_VMOVLs8th = 1395, |
| 1409 | MVE_VMOVLu16bh = 1396, |
| 1410 | MVE_VMOVLu16th = 1397, |
| 1411 | MVE_VMOVLu8bh = 1398, |
| 1412 | MVE_VMOVLu8th = 1399, |
| 1413 | MVE_VMOVNi16bh = 1400, |
| 1414 | MVE_VMOVNi16th = 1401, |
| 1415 | MVE_VMOVNi32bh = 1402, |
| 1416 | MVE_VMOVNi32th = 1403, |
| 1417 | MVE_VMOV_from_lane_32 = 1404, |
| 1418 | MVE_VMOV_from_lane_s16 = 1405, |
| 1419 | MVE_VMOV_from_lane_s8 = 1406, |
| 1420 | MVE_VMOV_from_lane_u16 = 1407, |
| 1421 | MVE_VMOV_from_lane_u8 = 1408, |
| 1422 | MVE_VMOV_q_rr = 1409, |
| 1423 | MVE_VMOV_rr_q = 1410, |
| 1424 | MVE_VMOV_to_lane_16 = 1411, |
| 1425 | MVE_VMOV_to_lane_32 = 1412, |
| 1426 | MVE_VMOV_to_lane_8 = 1413, |
| 1427 | MVE_VMOVimmf32 = 1414, |
| 1428 | MVE_VMOVimmi16 = 1415, |
| 1429 | MVE_VMOVimmi32 = 1416, |
| 1430 | MVE_VMOVimmi64 = 1417, |
| 1431 | MVE_VMOVimmi8 = 1418, |
| 1432 | MVE_VMULHs16 = 1419, |
| 1433 | MVE_VMULHs32 = 1420, |
| 1434 | MVE_VMULHs8 = 1421, |
| 1435 | MVE_VMULHu16 = 1422, |
| 1436 | MVE_VMULHu32 = 1423, |
| 1437 | MVE_VMULHu8 = 1424, |
| 1438 | MVE_VMULLBp16 = 1425, |
| 1439 | MVE_VMULLBp8 = 1426, |
| 1440 | MVE_VMULLBs16 = 1427, |
| 1441 | MVE_VMULLBs32 = 1428, |
| 1442 | MVE_VMULLBs8 = 1429, |
| 1443 | MVE_VMULLBu16 = 1430, |
| 1444 | MVE_VMULLBu32 = 1431, |
| 1445 | MVE_VMULLBu8 = 1432, |
| 1446 | MVE_VMULLTp16 = 1433, |
| 1447 | MVE_VMULLTp8 = 1434, |
| 1448 | MVE_VMULLTs16 = 1435, |
| 1449 | MVE_VMULLTs32 = 1436, |
| 1450 | MVE_VMULLTs8 = 1437, |
| 1451 | MVE_VMULLTu16 = 1438, |
| 1452 | MVE_VMULLTu32 = 1439, |
| 1453 | MVE_VMULLTu8 = 1440, |
| 1454 | MVE_VMUL_qr_f16 = 1441, |
| 1455 | MVE_VMUL_qr_f32 = 1442, |
| 1456 | MVE_VMUL_qr_i16 = 1443, |
| 1457 | MVE_VMUL_qr_i32 = 1444, |
| 1458 | MVE_VMUL_qr_i8 = 1445, |
| 1459 | MVE_VMULf16 = 1446, |
| 1460 | MVE_VMULf32 = 1447, |
| 1461 | MVE_VMULi16 = 1448, |
| 1462 | MVE_VMULi32 = 1449, |
| 1463 | MVE_VMULi8 = 1450, |
| 1464 | MVE_VMVN = 1451, |
| 1465 | MVE_VMVNimmi16 = 1452, |
| 1466 | MVE_VMVNimmi32 = 1453, |
| 1467 | MVE_VNEGf16 = 1454, |
| 1468 | MVE_VNEGf32 = 1455, |
| 1469 | MVE_VNEGs16 = 1456, |
| 1470 | MVE_VNEGs32 = 1457, |
| 1471 | MVE_VNEGs8 = 1458, |
| 1472 | MVE_VORN = 1459, |
| 1473 | MVE_VORR = 1460, |
| 1474 | MVE_VORRimmi16 = 1461, |
| 1475 | MVE_VORRimmi32 = 1462, |
| 1476 | MVE_VPNOT = 1463, |
| 1477 | MVE_VPSEL = 1464, |
| 1478 | MVE_VPST = 1465, |
| 1479 | MVE_VPTv16i8 = 1466, |
| 1480 | MVE_VPTv16i8r = 1467, |
| 1481 | MVE_VPTv16s8 = 1468, |
| 1482 | MVE_VPTv16s8r = 1469, |
| 1483 | MVE_VPTv16u8 = 1470, |
| 1484 | MVE_VPTv16u8r = 1471, |
| 1485 | MVE_VPTv4f32 = 1472, |
| 1486 | MVE_VPTv4f32r = 1473, |
| 1487 | MVE_VPTv4i32 = 1474, |
| 1488 | MVE_VPTv4i32r = 1475, |
| 1489 | MVE_VPTv4s32 = 1476, |
| 1490 | MVE_VPTv4s32r = 1477, |
| 1491 | MVE_VPTv4u32 = 1478, |
| 1492 | MVE_VPTv4u32r = 1479, |
| 1493 | MVE_VPTv8f16 = 1480, |
| 1494 | MVE_VPTv8f16r = 1481, |
| 1495 | MVE_VPTv8i16 = 1482, |
| 1496 | MVE_VPTv8i16r = 1483, |
| 1497 | MVE_VPTv8s16 = 1484, |
| 1498 | MVE_VPTv8s16r = 1485, |
| 1499 | MVE_VPTv8u16 = 1486, |
| 1500 | MVE_VPTv8u16r = 1487, |
| 1501 | MVE_VQABSs16 = 1488, |
| 1502 | MVE_VQABSs32 = 1489, |
| 1503 | MVE_VQABSs8 = 1490, |
| 1504 | MVE_VQADD_qr_s16 = 1491, |
| 1505 | MVE_VQADD_qr_s32 = 1492, |
| 1506 | MVE_VQADD_qr_s8 = 1493, |
| 1507 | MVE_VQADD_qr_u16 = 1494, |
| 1508 | MVE_VQADD_qr_u32 = 1495, |
| 1509 | MVE_VQADD_qr_u8 = 1496, |
| 1510 | MVE_VQADDs16 = 1497, |
| 1511 | MVE_VQADDs32 = 1498, |
| 1512 | MVE_VQADDs8 = 1499, |
| 1513 | MVE_VQADDu16 = 1500, |
| 1514 | MVE_VQADDu32 = 1501, |
| 1515 | MVE_VQADDu8 = 1502, |
| 1516 | MVE_VQDMLADHXs16 = 1503, |
| 1517 | MVE_VQDMLADHXs32 = 1504, |
| 1518 | MVE_VQDMLADHXs8 = 1505, |
| 1519 | MVE_VQDMLADHs16 = 1506, |
| 1520 | MVE_VQDMLADHs32 = 1507, |
| 1521 | MVE_VQDMLADHs8 = 1508, |
| 1522 | MVE_VQDMLAH_qrs16 = 1509, |
| 1523 | MVE_VQDMLAH_qrs32 = 1510, |
| 1524 | MVE_VQDMLAH_qrs8 = 1511, |
| 1525 | MVE_VQDMLASH_qrs16 = 1512, |
| 1526 | MVE_VQDMLASH_qrs32 = 1513, |
| 1527 | MVE_VQDMLASH_qrs8 = 1514, |
| 1528 | MVE_VQDMLSDHXs16 = 1515, |
| 1529 | MVE_VQDMLSDHXs32 = 1516, |
| 1530 | MVE_VQDMLSDHXs8 = 1517, |
| 1531 | MVE_VQDMLSDHs16 = 1518, |
| 1532 | MVE_VQDMLSDHs32 = 1519, |
| 1533 | MVE_VQDMLSDHs8 = 1520, |
| 1534 | MVE_VQDMULH_qr_s16 = 1521, |
| 1535 | MVE_VQDMULH_qr_s32 = 1522, |
| 1536 | MVE_VQDMULH_qr_s8 = 1523, |
| 1537 | MVE_VQDMULHi16 = 1524, |
| 1538 | MVE_VQDMULHi32 = 1525, |
| 1539 | MVE_VQDMULHi8 = 1526, |
| 1540 | MVE_VQDMULL_qr_s16bh = 1527, |
| 1541 | MVE_VQDMULL_qr_s16th = 1528, |
| 1542 | MVE_VQDMULL_qr_s32bh = 1529, |
| 1543 | MVE_VQDMULL_qr_s32th = 1530, |
| 1544 | MVE_VQDMULLs16bh = 1531, |
| 1545 | MVE_VQDMULLs16th = 1532, |
| 1546 | MVE_VQDMULLs32bh = 1533, |
| 1547 | MVE_VQDMULLs32th = 1534, |
| 1548 | MVE_VQMOVNs16bh = 1535, |
| 1549 | MVE_VQMOVNs16th = 1536, |
| 1550 | MVE_VQMOVNs32bh = 1537, |
| 1551 | MVE_VQMOVNs32th = 1538, |
| 1552 | MVE_VQMOVNu16bh = 1539, |
| 1553 | MVE_VQMOVNu16th = 1540, |
| 1554 | MVE_VQMOVNu32bh = 1541, |
| 1555 | MVE_VQMOVNu32th = 1542, |
| 1556 | MVE_VQMOVUNs16bh = 1543, |
| 1557 | MVE_VQMOVUNs16th = 1544, |
| 1558 | MVE_VQMOVUNs32bh = 1545, |
| 1559 | MVE_VQMOVUNs32th = 1546, |
| 1560 | MVE_VQNEGs16 = 1547, |
| 1561 | MVE_VQNEGs32 = 1548, |
| 1562 | MVE_VQNEGs8 = 1549, |
| 1563 | MVE_VQRDMLADHXs16 = 1550, |
| 1564 | MVE_VQRDMLADHXs32 = 1551, |
| 1565 | MVE_VQRDMLADHXs8 = 1552, |
| 1566 | MVE_VQRDMLADHs16 = 1553, |
| 1567 | MVE_VQRDMLADHs32 = 1554, |
| 1568 | MVE_VQRDMLADHs8 = 1555, |
| 1569 | MVE_VQRDMLAH_qrs16 = 1556, |
| 1570 | MVE_VQRDMLAH_qrs32 = 1557, |
| 1571 | MVE_VQRDMLAH_qrs8 = 1558, |
| 1572 | MVE_VQRDMLASH_qrs16 = 1559, |
| 1573 | MVE_VQRDMLASH_qrs32 = 1560, |
| 1574 | MVE_VQRDMLASH_qrs8 = 1561, |
| 1575 | MVE_VQRDMLSDHXs16 = 1562, |
| 1576 | MVE_VQRDMLSDHXs32 = 1563, |
| 1577 | MVE_VQRDMLSDHXs8 = 1564, |
| 1578 | MVE_VQRDMLSDHs16 = 1565, |
| 1579 | MVE_VQRDMLSDHs32 = 1566, |
| 1580 | MVE_VQRDMLSDHs8 = 1567, |
| 1581 | MVE_VQRDMULH_qr_s16 = 1568, |
| 1582 | MVE_VQRDMULH_qr_s32 = 1569, |
| 1583 | MVE_VQRDMULH_qr_s8 = 1570, |
| 1584 | MVE_VQRDMULHi16 = 1571, |
| 1585 | MVE_VQRDMULHi32 = 1572, |
| 1586 | MVE_VQRDMULHi8 = 1573, |
| 1587 | MVE_VQRSHL_by_vecs16 = 1574, |
| 1588 | MVE_VQRSHL_by_vecs32 = 1575, |
| 1589 | MVE_VQRSHL_by_vecs8 = 1576, |
| 1590 | MVE_VQRSHL_by_vecu16 = 1577, |
| 1591 | MVE_VQRSHL_by_vecu32 = 1578, |
| 1592 | MVE_VQRSHL_by_vecu8 = 1579, |
| 1593 | MVE_VQRSHL_qrs16 = 1580, |
| 1594 | MVE_VQRSHL_qrs32 = 1581, |
| 1595 | MVE_VQRSHL_qrs8 = 1582, |
| 1596 | MVE_VQRSHL_qru16 = 1583, |
| 1597 | MVE_VQRSHL_qru32 = 1584, |
| 1598 | MVE_VQRSHL_qru8 = 1585, |
| 1599 | MVE_VQRSHRNbhs16 = 1586, |
| 1600 | MVE_VQRSHRNbhs32 = 1587, |
| 1601 | MVE_VQRSHRNbhu16 = 1588, |
| 1602 | MVE_VQRSHRNbhu32 = 1589, |
| 1603 | MVE_VQRSHRNths16 = 1590, |
| 1604 | MVE_VQRSHRNths32 = 1591, |
| 1605 | MVE_VQRSHRNthu16 = 1592, |
| 1606 | MVE_VQRSHRNthu32 = 1593, |
| 1607 | MVE_VQRSHRUNs16bh = 1594, |
| 1608 | MVE_VQRSHRUNs16th = 1595, |
| 1609 | MVE_VQRSHRUNs32bh = 1596, |
| 1610 | MVE_VQRSHRUNs32th = 1597, |
| 1611 | MVE_VQSHLU_imms16 = 1598, |
| 1612 | MVE_VQSHLU_imms32 = 1599, |
| 1613 | MVE_VQSHLU_imms8 = 1600, |
| 1614 | MVE_VQSHL_by_vecs16 = 1601, |
| 1615 | MVE_VQSHL_by_vecs32 = 1602, |
| 1616 | MVE_VQSHL_by_vecs8 = 1603, |
| 1617 | MVE_VQSHL_by_vecu16 = 1604, |
| 1618 | MVE_VQSHL_by_vecu32 = 1605, |
| 1619 | MVE_VQSHL_by_vecu8 = 1606, |
| 1620 | MVE_VQSHL_qrs16 = 1607, |
| 1621 | MVE_VQSHL_qrs32 = 1608, |
| 1622 | MVE_VQSHL_qrs8 = 1609, |
| 1623 | MVE_VQSHL_qru16 = 1610, |
| 1624 | MVE_VQSHL_qru32 = 1611, |
| 1625 | MVE_VQSHL_qru8 = 1612, |
| 1626 | MVE_VQSHLimms16 = 1613, |
| 1627 | MVE_VQSHLimms32 = 1614, |
| 1628 | MVE_VQSHLimms8 = 1615, |
| 1629 | MVE_VQSHLimmu16 = 1616, |
| 1630 | MVE_VQSHLimmu32 = 1617, |
| 1631 | MVE_VQSHLimmu8 = 1618, |
| 1632 | MVE_VQSHRNbhs16 = 1619, |
| 1633 | MVE_VQSHRNbhs32 = 1620, |
| 1634 | MVE_VQSHRNbhu16 = 1621, |
| 1635 | MVE_VQSHRNbhu32 = 1622, |
| 1636 | MVE_VQSHRNths16 = 1623, |
| 1637 | MVE_VQSHRNths32 = 1624, |
| 1638 | MVE_VQSHRNthu16 = 1625, |
| 1639 | MVE_VQSHRNthu32 = 1626, |
| 1640 | MVE_VQSHRUNs16bh = 1627, |
| 1641 | MVE_VQSHRUNs16th = 1628, |
| 1642 | MVE_VQSHRUNs32bh = 1629, |
| 1643 | MVE_VQSHRUNs32th = 1630, |
| 1644 | MVE_VQSUB_qr_s16 = 1631, |
| 1645 | MVE_VQSUB_qr_s32 = 1632, |
| 1646 | MVE_VQSUB_qr_s8 = 1633, |
| 1647 | MVE_VQSUB_qr_u16 = 1634, |
| 1648 | MVE_VQSUB_qr_u32 = 1635, |
| 1649 | MVE_VQSUB_qr_u8 = 1636, |
| 1650 | MVE_VQSUBs16 = 1637, |
| 1651 | MVE_VQSUBs32 = 1638, |
| 1652 | MVE_VQSUBs8 = 1639, |
| 1653 | MVE_VQSUBu16 = 1640, |
| 1654 | MVE_VQSUBu32 = 1641, |
| 1655 | MVE_VQSUBu8 = 1642, |
| 1656 | MVE_VREV16_8 = 1643, |
| 1657 | MVE_VREV32_16 = 1644, |
| 1658 | MVE_VREV32_8 = 1645, |
| 1659 | MVE_VREV64_16 = 1646, |
| 1660 | MVE_VREV64_32 = 1647, |
| 1661 | MVE_VREV64_8 = 1648, |
| 1662 | MVE_VRHADDs16 = 1649, |
| 1663 | MVE_VRHADDs32 = 1650, |
| 1664 | MVE_VRHADDs8 = 1651, |
| 1665 | MVE_VRHADDu16 = 1652, |
| 1666 | MVE_VRHADDu32 = 1653, |
| 1667 | MVE_VRHADDu8 = 1654, |
| 1668 | MVE_VRINTf16A = 1655, |
| 1669 | MVE_VRINTf16M = 1656, |
| 1670 | MVE_VRINTf16N = 1657, |
| 1671 | MVE_VRINTf16P = 1658, |
| 1672 | MVE_VRINTf16X = 1659, |
| 1673 | MVE_VRINTf16Z = 1660, |
| 1674 | MVE_VRINTf32A = 1661, |
| 1675 | MVE_VRINTf32M = 1662, |
| 1676 | MVE_VRINTf32N = 1663, |
| 1677 | MVE_VRINTf32P = 1664, |
| 1678 | MVE_VRINTf32X = 1665, |
| 1679 | MVE_VRINTf32Z = 1666, |
| 1680 | MVE_VRMLALDAVHas32 = 1667, |
| 1681 | MVE_VRMLALDAVHau32 = 1668, |
| 1682 | MVE_VRMLALDAVHaxs32 = 1669, |
| 1683 | MVE_VRMLALDAVHs32 = 1670, |
| 1684 | MVE_VRMLALDAVHu32 = 1671, |
| 1685 | MVE_VRMLALDAVHxs32 = 1672, |
| 1686 | MVE_VRMLSLDAVHas32 = 1673, |
| 1687 | MVE_VRMLSLDAVHaxs32 = 1674, |
| 1688 | MVE_VRMLSLDAVHs32 = 1675, |
| 1689 | MVE_VRMLSLDAVHxs32 = 1676, |
| 1690 | MVE_VRMULHs16 = 1677, |
| 1691 | MVE_VRMULHs32 = 1678, |
| 1692 | MVE_VRMULHs8 = 1679, |
| 1693 | MVE_VRMULHu16 = 1680, |
| 1694 | MVE_VRMULHu32 = 1681, |
| 1695 | MVE_VRMULHu8 = 1682, |
| 1696 | MVE_VRSHL_by_vecs16 = 1683, |
| 1697 | MVE_VRSHL_by_vecs32 = 1684, |
| 1698 | MVE_VRSHL_by_vecs8 = 1685, |
| 1699 | MVE_VRSHL_by_vecu16 = 1686, |
| 1700 | MVE_VRSHL_by_vecu32 = 1687, |
| 1701 | MVE_VRSHL_by_vecu8 = 1688, |
| 1702 | MVE_VRSHL_qrs16 = 1689, |
| 1703 | MVE_VRSHL_qrs32 = 1690, |
| 1704 | MVE_VRSHL_qrs8 = 1691, |
| 1705 | MVE_VRSHL_qru16 = 1692, |
| 1706 | MVE_VRSHL_qru32 = 1693, |
| 1707 | MVE_VRSHL_qru8 = 1694, |
| 1708 | MVE_VRSHRNi16bh = 1695, |
| 1709 | MVE_VRSHRNi16th = 1696, |
| 1710 | MVE_VRSHRNi32bh = 1697, |
| 1711 | MVE_VRSHRNi32th = 1698, |
| 1712 | MVE_VRSHR_imms16 = 1699, |
| 1713 | MVE_VRSHR_imms32 = 1700, |
| 1714 | MVE_VRSHR_imms8 = 1701, |
| 1715 | MVE_VRSHR_immu16 = 1702, |
| 1716 | MVE_VRSHR_immu32 = 1703, |
| 1717 | MVE_VRSHR_immu8 = 1704, |
| 1718 | MVE_VSBC = 1705, |
| 1719 | MVE_VSBCI = 1706, |
| 1720 | MVE_VSHLC = 1707, |
| 1721 | MVE_VSHLL_imms16bh = 1708, |
| 1722 | MVE_VSHLL_imms16th = 1709, |
| 1723 | MVE_VSHLL_imms8bh = 1710, |
| 1724 | MVE_VSHLL_imms8th = 1711, |
| 1725 | MVE_VSHLL_immu16bh = 1712, |
| 1726 | MVE_VSHLL_immu16th = 1713, |
| 1727 | MVE_VSHLL_immu8bh = 1714, |
| 1728 | MVE_VSHLL_immu8th = 1715, |
| 1729 | MVE_VSHLL_lws16bh = 1716, |
| 1730 | MVE_VSHLL_lws16th = 1717, |
| 1731 | MVE_VSHLL_lws8bh = 1718, |
| 1732 | MVE_VSHLL_lws8th = 1719, |
| 1733 | MVE_VSHLL_lwu16bh = 1720, |
| 1734 | MVE_VSHLL_lwu16th = 1721, |
| 1735 | MVE_VSHLL_lwu8bh = 1722, |
| 1736 | MVE_VSHLL_lwu8th = 1723, |
| 1737 | MVE_VSHL_by_vecs16 = 1724, |
| 1738 | MVE_VSHL_by_vecs32 = 1725, |
| 1739 | MVE_VSHL_by_vecs8 = 1726, |
| 1740 | MVE_VSHL_by_vecu16 = 1727, |
| 1741 | MVE_VSHL_by_vecu32 = 1728, |
| 1742 | MVE_VSHL_by_vecu8 = 1729, |
| 1743 | MVE_VSHL_immi16 = 1730, |
| 1744 | MVE_VSHL_immi32 = 1731, |
| 1745 | MVE_VSHL_immi8 = 1732, |
| 1746 | MVE_VSHL_qrs16 = 1733, |
| 1747 | MVE_VSHL_qrs32 = 1734, |
| 1748 | MVE_VSHL_qrs8 = 1735, |
| 1749 | MVE_VSHL_qru16 = 1736, |
| 1750 | MVE_VSHL_qru32 = 1737, |
| 1751 | MVE_VSHL_qru8 = 1738, |
| 1752 | MVE_VSHRNi16bh = 1739, |
| 1753 | MVE_VSHRNi16th = 1740, |
| 1754 | MVE_VSHRNi32bh = 1741, |
| 1755 | MVE_VSHRNi32th = 1742, |
| 1756 | MVE_VSHR_imms16 = 1743, |
| 1757 | MVE_VSHR_imms32 = 1744, |
| 1758 | MVE_VSHR_imms8 = 1745, |
| 1759 | MVE_VSHR_immu16 = 1746, |
| 1760 | MVE_VSHR_immu32 = 1747, |
| 1761 | MVE_VSHR_immu8 = 1748, |
| 1762 | MVE_VSLIimm16 = 1749, |
| 1763 | MVE_VSLIimm32 = 1750, |
| 1764 | MVE_VSLIimm8 = 1751, |
| 1765 | MVE_VSRIimm16 = 1752, |
| 1766 | MVE_VSRIimm32 = 1753, |
| 1767 | MVE_VSRIimm8 = 1754, |
| 1768 | MVE_VST20_16 = 1755, |
| 1769 | MVE_VST20_16_wb = 1756, |
| 1770 | MVE_VST20_32 = 1757, |
| 1771 | MVE_VST20_32_wb = 1758, |
| 1772 | MVE_VST20_8 = 1759, |
| 1773 | MVE_VST20_8_wb = 1760, |
| 1774 | MVE_VST21_16 = 1761, |
| 1775 | MVE_VST21_16_wb = 1762, |
| 1776 | MVE_VST21_32 = 1763, |
| 1777 | MVE_VST21_32_wb = 1764, |
| 1778 | MVE_VST21_8 = 1765, |
| 1779 | MVE_VST21_8_wb = 1766, |
| 1780 | MVE_VST40_16 = 1767, |
| 1781 | MVE_VST40_16_wb = 1768, |
| 1782 | MVE_VST40_32 = 1769, |
| 1783 | MVE_VST40_32_wb = 1770, |
| 1784 | MVE_VST40_8 = 1771, |
| 1785 | MVE_VST40_8_wb = 1772, |
| 1786 | MVE_VST41_16 = 1773, |
| 1787 | MVE_VST41_16_wb = 1774, |
| 1788 | MVE_VST41_32 = 1775, |
| 1789 | MVE_VST41_32_wb = 1776, |
| 1790 | MVE_VST41_8 = 1777, |
| 1791 | MVE_VST41_8_wb = 1778, |
| 1792 | MVE_VST42_16 = 1779, |
| 1793 | MVE_VST42_16_wb = 1780, |
| 1794 | MVE_VST42_32 = 1781, |
| 1795 | MVE_VST42_32_wb = 1782, |
| 1796 | MVE_VST42_8 = 1783, |
| 1797 | MVE_VST42_8_wb = 1784, |
| 1798 | MVE_VST43_16 = 1785, |
| 1799 | MVE_VST43_16_wb = 1786, |
| 1800 | MVE_VST43_32 = 1787, |
| 1801 | MVE_VST43_32_wb = 1788, |
| 1802 | MVE_VST43_8 = 1789, |
| 1803 | MVE_VST43_8_wb = 1790, |
| 1804 | MVE_VSTRB16 = 1791, |
| 1805 | MVE_VSTRB16_post = 1792, |
| 1806 | MVE_VSTRB16_pre = 1793, |
| 1807 | MVE_VSTRB16_rq = 1794, |
| 1808 | MVE_VSTRB32 = 1795, |
| 1809 | MVE_VSTRB32_post = 1796, |
| 1810 | MVE_VSTRB32_pre = 1797, |
| 1811 | MVE_VSTRB32_rq = 1798, |
| 1812 | MVE_VSTRB8_rq = 1799, |
| 1813 | MVE_VSTRBU8 = 1800, |
| 1814 | MVE_VSTRBU8_post = 1801, |
| 1815 | MVE_VSTRBU8_pre = 1802, |
| 1816 | MVE_VSTRD64_qi = 1803, |
| 1817 | MVE_VSTRD64_qi_pre = 1804, |
| 1818 | MVE_VSTRD64_rq = 1805, |
| 1819 | MVE_VSTRD64_rq_u = 1806, |
| 1820 | MVE_VSTRH16_rq = 1807, |
| 1821 | MVE_VSTRH16_rq_u = 1808, |
| 1822 | MVE_VSTRH32 = 1809, |
| 1823 | MVE_VSTRH32_post = 1810, |
| 1824 | MVE_VSTRH32_pre = 1811, |
| 1825 | MVE_VSTRH32_rq = 1812, |
| 1826 | MVE_VSTRH32_rq_u = 1813, |
| 1827 | MVE_VSTRHU16 = 1814, |
| 1828 | MVE_VSTRHU16_post = 1815, |
| 1829 | MVE_VSTRHU16_pre = 1816, |
| 1830 | MVE_VSTRW32_qi = 1817, |
| 1831 | MVE_VSTRW32_qi_pre = 1818, |
| 1832 | MVE_VSTRW32_rq = 1819, |
| 1833 | MVE_VSTRW32_rq_u = 1820, |
| 1834 | MVE_VSTRWU32 = 1821, |
| 1835 | MVE_VSTRWU32_post = 1822, |
| 1836 | MVE_VSTRWU32_pre = 1823, |
| 1837 | MVE_VSUB_qr_f16 = 1824, |
| 1838 | MVE_VSUB_qr_f32 = 1825, |
| 1839 | MVE_VSUB_qr_i16 = 1826, |
| 1840 | MVE_VSUB_qr_i32 = 1827, |
| 1841 | MVE_VSUB_qr_i8 = 1828, |
| 1842 | MVE_VSUBf16 = 1829, |
| 1843 | MVE_VSUBf32 = 1830, |
| 1844 | MVE_VSUBi16 = 1831, |
| 1845 | MVE_VSUBi32 = 1832, |
| 1846 | MVE_VSUBi8 = 1833, |
| 1847 | MVE_WLSTP_16 = 1834, |
| 1848 | MVE_WLSTP_32 = 1835, |
| 1849 | MVE_WLSTP_64 = 1836, |
| 1850 | MVE_WLSTP_8 = 1837, |
| 1851 | MVNi = 1838, |
| 1852 | MVNr = 1839, |
| 1853 | MVNsi = 1840, |
| 1854 | MVNsr = 1841, |
| 1855 | NEON_VMAXNMNDf = 1842, |
| 1856 | NEON_VMAXNMNDh = 1843, |
| 1857 | NEON_VMAXNMNQf = 1844, |
| 1858 | NEON_VMAXNMNQh = 1845, |
| 1859 | NEON_VMINNMNDf = 1846, |
| 1860 | NEON_VMINNMNDh = 1847, |
| 1861 | NEON_VMINNMNQf = 1848, |
| 1862 | NEON_VMINNMNQh = 1849, |
| 1863 | ORRri = 1850, |
| 1864 | ORRrr = 1851, |
| 1865 | ORRrsi = 1852, |
| 1866 | ORRrsr = 1853, |
| 1867 | PKHBT = 1854, |
| 1868 | PKHTB = 1855, |
| 1869 | PLDWi12 = 1856, |
| 1870 | PLDWrs = 1857, |
| 1871 | PLDi12 = 1858, |
| 1872 | PLDrs = 1859, |
| 1873 | PLIi12 = 1860, |
| 1874 | PLIrs = 1861, |
| 1875 | QADD = 1862, |
| 1876 | QADD16 = 1863, |
| 1877 | QADD8 = 1864, |
| 1878 | QASX = 1865, |
| 1879 | QDADD = 1866, |
| 1880 | QDSUB = 1867, |
| 1881 | QSAX = 1868, |
| 1882 | QSUB = 1869, |
| 1883 | QSUB16 = 1870, |
| 1884 | QSUB8 = 1871, |
| 1885 | RBIT = 1872, |
| 1886 | REV = 1873, |
| 1887 | REV16 = 1874, |
| 1888 | REVSH = 1875, |
| 1889 | RFEDA = 1876, |
| 1890 | RFEDA_UPD = 1877, |
| 1891 | RFEDB = 1878, |
| 1892 | RFEDB_UPD = 1879, |
| 1893 | RFEIA = 1880, |
| 1894 | RFEIA_UPD = 1881, |
| 1895 | RFEIB = 1882, |
| 1896 | RFEIB_UPD = 1883, |
| 1897 | RSBri = 1884, |
| 1898 | RSBrr = 1885, |
| 1899 | RSBrsi = 1886, |
| 1900 | RSBrsr = 1887, |
| 1901 | RSCri = 1888, |
| 1902 | RSCrr = 1889, |
| 1903 | RSCrsi = 1890, |
| 1904 | RSCrsr = 1891, |
| 1905 | SADD16 = 1892, |
| 1906 | SADD8 = 1893, |
| 1907 | SASX = 1894, |
| 1908 | SB = 1895, |
| 1909 | SBCri = 1896, |
| 1910 | SBCrr = 1897, |
| 1911 | SBCrsi = 1898, |
| 1912 | SBCrsr = 1899, |
| 1913 | SBFX = 1900, |
| 1914 | SDIV = 1901, |
| 1915 | SEL = 1902, |
| 1916 | SETEND = 1903, |
| 1917 | SETPAN = 1904, |
| 1918 | SHA1C = 1905, |
| 1919 | SHA1H = 1906, |
| 1920 | SHA1M = 1907, |
| 1921 | SHA1P = 1908, |
| 1922 | SHA1SU0 = 1909, |
| 1923 | SHA1SU1 = 1910, |
| 1924 | SHA256H = 1911, |
| 1925 | SHA256H2 = 1912, |
| 1926 | SHA256SU0 = 1913, |
| 1927 | SHA256SU1 = 1914, |
| 1928 | SHADD16 = 1915, |
| 1929 | SHADD8 = 1916, |
| 1930 | SHASX = 1917, |
| 1931 | SHSAX = 1918, |
| 1932 | SHSUB16 = 1919, |
| 1933 | SHSUB8 = 1920, |
| 1934 | SMC = 1921, |
| 1935 | SMLABB = 1922, |
| 1936 | SMLABT = 1923, |
| 1937 | SMLAD = 1924, |
| 1938 | SMLADX = 1925, |
| 1939 | SMLAL = 1926, |
| 1940 | SMLALBB = 1927, |
| 1941 | SMLALBT = 1928, |
| 1942 | SMLALD = 1929, |
| 1943 | SMLALDX = 1930, |
| 1944 | SMLALTB = 1931, |
| 1945 | SMLALTT = 1932, |
| 1946 | SMLATB = 1933, |
| 1947 | SMLATT = 1934, |
| 1948 | SMLAWB = 1935, |
| 1949 | SMLAWT = 1936, |
| 1950 | SMLSD = 1937, |
| 1951 | SMLSDX = 1938, |
| 1952 | SMLSLD = 1939, |
| 1953 | SMLSLDX = 1940, |
| 1954 | SMMLA = 1941, |
| 1955 | SMMLAR = 1942, |
| 1956 | SMMLS = 1943, |
| 1957 | SMMLSR = 1944, |
| 1958 | SMMUL = 1945, |
| 1959 | SMMULR = 1946, |
| 1960 | SMUAD = 1947, |
| 1961 | SMUADX = 1948, |
| 1962 | SMULBB = 1949, |
| 1963 | SMULBT = 1950, |
| 1964 | SMULL = 1951, |
| 1965 | SMULTB = 1952, |
| 1966 | SMULTT = 1953, |
| 1967 | SMULWB = 1954, |
| 1968 | SMULWT = 1955, |
| 1969 | SMUSD = 1956, |
| 1970 | SMUSDX = 1957, |
| 1971 | SRSDA = 1958, |
| 1972 | SRSDA_UPD = 1959, |
| 1973 | SRSDB = 1960, |
| 1974 | SRSDB_UPD = 1961, |
| 1975 | SRSIA = 1962, |
| 1976 | SRSIA_UPD = 1963, |
| 1977 | SRSIB = 1964, |
| 1978 | SRSIB_UPD = 1965, |
| 1979 | SSAT = 1966, |
| 1980 | SSAT16 = 1967, |
| 1981 | SSAX = 1968, |
| 1982 | SSUB16 = 1969, |
| 1983 | SSUB8 = 1970, |
| 1984 | STC2L_OFFSET = 1971, |
| 1985 | STC2L_OPTION = 1972, |
| 1986 | STC2L_POST = 1973, |
| 1987 | STC2L_PRE = 1974, |
| 1988 | STC2_OFFSET = 1975, |
| 1989 | STC2_OPTION = 1976, |
| 1990 | STC2_POST = 1977, |
| 1991 | STC2_PRE = 1978, |
| 1992 | STCL_OFFSET = 1979, |
| 1993 | STCL_OPTION = 1980, |
| 1994 | STCL_POST = 1981, |
| 1995 | STCL_PRE = 1982, |
| 1996 | STC_OFFSET = 1983, |
| 1997 | STC_OPTION = 1984, |
| 1998 | STC_POST = 1985, |
| 1999 | STC_PRE = 1986, |
| 2000 | STL = 1987, |
| 2001 | STLB = 1988, |
| 2002 | STLEX = 1989, |
| 2003 | STLEXB = 1990, |
| 2004 | STLEXD = 1991, |
| 2005 | STLEXH = 1992, |
| 2006 | STLH = 1993, |
| 2007 | STMDA = 1994, |
| 2008 | STMDA_UPD = 1995, |
| 2009 | STMDB = 1996, |
| 2010 | STMDB_UPD = 1997, |
| 2011 | STMIA = 1998, |
| 2012 | STMIA_UPD = 1999, |
| 2013 | STMIB = 2000, |
| 2014 | STMIB_UPD = 2001, |
| 2015 | STRBT_POST_IMM = 2002, |
| 2016 | STRBT_POST_REG = 2003, |
| 2017 | STRB_POST_IMM = 2004, |
| 2018 | STRB_POST_REG = 2005, |
| 2019 | STRB_PRE_IMM = 2006, |
| 2020 | STRB_PRE_REG = 2007, |
| 2021 | STRBi12 = 2008, |
| 2022 | STRBrs = 2009, |
| 2023 | STRD = 2010, |
| 2024 | STRD_POST = 2011, |
| 2025 | STRD_PRE = 2012, |
| 2026 | STREX = 2013, |
| 2027 | STREXB = 2014, |
| 2028 | STREXD = 2015, |
| 2029 | STREXH = 2016, |
| 2030 | STRH = 2017, |
| 2031 | STRHTi = 2018, |
| 2032 | STRHTr = 2019, |
| 2033 | STRH_POST = 2020, |
| 2034 | STRH_PRE = 2021, |
| 2035 | STRT_POST_IMM = 2022, |
| 2036 | STRT_POST_REG = 2023, |
| 2037 | STR_POST_IMM = 2024, |
| 2038 | STR_POST_REG = 2025, |
| 2039 | STR_PRE_IMM = 2026, |
| 2040 | STR_PRE_REG = 2027, |
| 2041 | STRi12 = 2028, |
| 2042 | STRrs = 2029, |
| 2043 | SUBri = 2030, |
| 2044 | SUBrr = 2031, |
| 2045 | SUBrsi = 2032, |
| 2046 | SUBrsr = 2033, |
| 2047 | SVC = 2034, |
| 2048 | SWP = 2035, |
| 2049 | SWPB = 2036, |
| 2050 | SXTAB = 2037, |
| 2051 | SXTAB16 = 2038, |
| 2052 | SXTAH = 2039, |
| 2053 | SXTB = 2040, |
| 2054 | SXTB16 = 2041, |
| 2055 | SXTH = 2042, |
| 2056 | TEQri = 2043, |
| 2057 | TEQrr = 2044, |
| 2058 | TEQrsi = 2045, |
| 2059 | TEQrsr = 2046, |
| 2060 | TRAP = 2047, |
| 2061 | TRAPNaCl = 2048, |
| 2062 | TSB = 2049, |
| 2063 | TSTri = 2050, |
| 2064 | TSTrr = 2051, |
| 2065 | TSTrsi = 2052, |
| 2066 | TSTrsr = 2053, |
| 2067 | UADD16 = 2054, |
| 2068 | UADD8 = 2055, |
| 2069 | UASX = 2056, |
| 2070 | UBFX = 2057, |
| 2071 | UDF = 2058, |
| 2072 | UDIV = 2059, |
| 2073 | UHADD16 = 2060, |
| 2074 | UHADD8 = 2061, |
| 2075 | UHASX = 2062, |
| 2076 | UHSAX = 2063, |
| 2077 | UHSUB16 = 2064, |
| 2078 | UHSUB8 = 2065, |
| 2079 | UMAAL = 2066, |
| 2080 | UMLAL = 2067, |
| 2081 | UMULL = 2068, |
| 2082 | UQADD16 = 2069, |
| 2083 | UQADD8 = 2070, |
| 2084 | UQASX = 2071, |
| 2085 | UQSAX = 2072, |
| 2086 | UQSUB16 = 2073, |
| 2087 | UQSUB8 = 2074, |
| 2088 | USAD8 = 2075, |
| 2089 | USADA8 = 2076, |
| 2090 | USAT = 2077, |
| 2091 | USAT16 = 2078, |
| 2092 | USAX = 2079, |
| 2093 | USUB16 = 2080, |
| 2094 | USUB8 = 2081, |
| 2095 | UXTAB = 2082, |
| 2096 | UXTAB16 = 2083, |
| 2097 | UXTAH = 2084, |
| 2098 | UXTB = 2085, |
| 2099 | UXTB16 = 2086, |
| 2100 | UXTH = 2087, |
| 2101 | VABALsv2i64 = 2088, |
| 2102 | VABALsv4i32 = 2089, |
| 2103 | VABALsv8i16 = 2090, |
| 2104 | VABALuv2i64 = 2091, |
| 2105 | VABALuv4i32 = 2092, |
| 2106 | VABALuv8i16 = 2093, |
| 2107 | VABAsv16i8 = 2094, |
| 2108 | VABAsv2i32 = 2095, |
| 2109 | VABAsv4i16 = 2096, |
| 2110 | VABAsv4i32 = 2097, |
| 2111 | VABAsv8i16 = 2098, |
| 2112 | VABAsv8i8 = 2099, |
| 2113 | VABAuv16i8 = 2100, |
| 2114 | VABAuv2i32 = 2101, |
| 2115 | VABAuv4i16 = 2102, |
| 2116 | VABAuv4i32 = 2103, |
| 2117 | VABAuv8i16 = 2104, |
| 2118 | VABAuv8i8 = 2105, |
| 2119 | VABDLsv2i64 = 2106, |
| 2120 | VABDLsv4i32 = 2107, |
| 2121 | VABDLsv8i16 = 2108, |
| 2122 | VABDLuv2i64 = 2109, |
| 2123 | VABDLuv4i32 = 2110, |
| 2124 | VABDLuv8i16 = 2111, |
| 2125 | VABDfd = 2112, |
| 2126 | VABDfq = 2113, |
| 2127 | VABDhd = 2114, |
| 2128 | VABDhq = 2115, |
| 2129 | VABDsv16i8 = 2116, |
| 2130 | VABDsv2i32 = 2117, |
| 2131 | VABDsv4i16 = 2118, |
| 2132 | VABDsv4i32 = 2119, |
| 2133 | VABDsv8i16 = 2120, |
| 2134 | VABDsv8i8 = 2121, |
| 2135 | VABDuv16i8 = 2122, |
| 2136 | VABDuv2i32 = 2123, |
| 2137 | VABDuv4i16 = 2124, |
| 2138 | VABDuv4i32 = 2125, |
| 2139 | VABDuv8i16 = 2126, |
| 2140 | VABDuv8i8 = 2127, |
| 2141 | VABSD = 2128, |
| 2142 | VABSH = 2129, |
| 2143 | VABSS = 2130, |
| 2144 | VABSfd = 2131, |
| 2145 | VABSfq = 2132, |
| 2146 | VABShd = 2133, |
| 2147 | VABShq = 2134, |
| 2148 | VABSv16i8 = 2135, |
| 2149 | VABSv2i32 = 2136, |
| 2150 | VABSv4i16 = 2137, |
| 2151 | VABSv4i32 = 2138, |
| 2152 | VABSv8i16 = 2139, |
| 2153 | VABSv8i8 = 2140, |
| 2154 | VACGEfd = 2141, |
| 2155 | VACGEfq = 2142, |
| 2156 | VACGEhd = 2143, |
| 2157 | VACGEhq = 2144, |
| 2158 | VACGTfd = 2145, |
| 2159 | VACGTfq = 2146, |
| 2160 | VACGThd = 2147, |
| 2161 | VACGThq = 2148, |
| 2162 | VADDD = 2149, |
| 2163 | VADDH = 2150, |
| 2164 | VADDHNv2i32 = 2151, |
| 2165 | VADDHNv4i16 = 2152, |
| 2166 | VADDHNv8i8 = 2153, |
| 2167 | VADDLsv2i64 = 2154, |
| 2168 | VADDLsv4i32 = 2155, |
| 2169 | VADDLsv8i16 = 2156, |
| 2170 | VADDLuv2i64 = 2157, |
| 2171 | VADDLuv4i32 = 2158, |
| 2172 | VADDLuv8i16 = 2159, |
| 2173 | VADDS = 2160, |
| 2174 | VADDWsv2i64 = 2161, |
| 2175 | VADDWsv4i32 = 2162, |
| 2176 | VADDWsv8i16 = 2163, |
| 2177 | VADDWuv2i64 = 2164, |
| 2178 | VADDWuv4i32 = 2165, |
| 2179 | VADDWuv8i16 = 2166, |
| 2180 | VADDfd = 2167, |
| 2181 | VADDfq = 2168, |
| 2182 | VADDhd = 2169, |
| 2183 | VADDhq = 2170, |
| 2184 | VADDv16i8 = 2171, |
| 2185 | VADDv1i64 = 2172, |
| 2186 | VADDv2i32 = 2173, |
| 2187 | VADDv2i64 = 2174, |
| 2188 | VADDv4i16 = 2175, |
| 2189 | VADDv4i32 = 2176, |
| 2190 | VADDv8i16 = 2177, |
| 2191 | VADDv8i8 = 2178, |
| 2192 | VANDd = 2179, |
| 2193 | VANDq = 2180, |
| 2194 | VBF16MALBQ = 2181, |
| 2195 | VBF16MALBQI = 2182, |
| 2196 | VBF16MALTQ = 2183, |
| 2197 | VBF16MALTQI = 2184, |
| 2198 | VBICd = 2185, |
| 2199 | VBICiv2i32 = 2186, |
| 2200 | VBICiv4i16 = 2187, |
| 2201 | VBICiv4i32 = 2188, |
| 2202 | VBICiv8i16 = 2189, |
| 2203 | VBICq = 2190, |
| 2204 | VBIFd = 2191, |
| 2205 | VBIFq = 2192, |
| 2206 | VBITd = 2193, |
| 2207 | VBITq = 2194, |
| 2208 | VBSLd = 2195, |
| 2209 | VBSLq = 2196, |
| 2210 | VBSPd = 2197, |
| 2211 | VBSPq = 2198, |
| 2212 | VCADDv2f32 = 2199, |
| 2213 | VCADDv4f16 = 2200, |
| 2214 | VCADDv4f32 = 2201, |
| 2215 | VCADDv8f16 = 2202, |
| 2216 | VCEQfd = 2203, |
| 2217 | VCEQfq = 2204, |
| 2218 | VCEQhd = 2205, |
| 2219 | VCEQhq = 2206, |
| 2220 | VCEQv16i8 = 2207, |
| 2221 | VCEQv2i32 = 2208, |
| 2222 | VCEQv4i16 = 2209, |
| 2223 | VCEQv4i32 = 2210, |
| 2224 | VCEQv8i16 = 2211, |
| 2225 | VCEQv8i8 = 2212, |
| 2226 | VCEQzv16i8 = 2213, |
| 2227 | VCEQzv2f32 = 2214, |
| 2228 | VCEQzv2i32 = 2215, |
| 2229 | VCEQzv4f16 = 2216, |
| 2230 | VCEQzv4f32 = 2217, |
| 2231 | VCEQzv4i16 = 2218, |
| 2232 | VCEQzv4i32 = 2219, |
| 2233 | VCEQzv8f16 = 2220, |
| 2234 | VCEQzv8i16 = 2221, |
| 2235 | VCEQzv8i8 = 2222, |
| 2236 | VCGEfd = 2223, |
| 2237 | VCGEfq = 2224, |
| 2238 | VCGEhd = 2225, |
| 2239 | VCGEhq = 2226, |
| 2240 | VCGEsv16i8 = 2227, |
| 2241 | VCGEsv2i32 = 2228, |
| 2242 | VCGEsv4i16 = 2229, |
| 2243 | VCGEsv4i32 = 2230, |
| 2244 | VCGEsv8i16 = 2231, |
| 2245 | VCGEsv8i8 = 2232, |
| 2246 | VCGEuv16i8 = 2233, |
| 2247 | VCGEuv2i32 = 2234, |
| 2248 | VCGEuv4i16 = 2235, |
| 2249 | VCGEuv4i32 = 2236, |
| 2250 | VCGEuv8i16 = 2237, |
| 2251 | VCGEuv8i8 = 2238, |
| 2252 | VCGEzv16i8 = 2239, |
| 2253 | VCGEzv2f32 = 2240, |
| 2254 | VCGEzv2i32 = 2241, |
| 2255 | VCGEzv4f16 = 2242, |
| 2256 | VCGEzv4f32 = 2243, |
| 2257 | VCGEzv4i16 = 2244, |
| 2258 | VCGEzv4i32 = 2245, |
| 2259 | VCGEzv8f16 = 2246, |
| 2260 | VCGEzv8i16 = 2247, |
| 2261 | VCGEzv8i8 = 2248, |
| 2262 | VCGTfd = 2249, |
| 2263 | VCGTfq = 2250, |
| 2264 | VCGThd = 2251, |
| 2265 | VCGThq = 2252, |
| 2266 | VCGTsv16i8 = 2253, |
| 2267 | VCGTsv2i32 = 2254, |
| 2268 | VCGTsv4i16 = 2255, |
| 2269 | VCGTsv4i32 = 2256, |
| 2270 | VCGTsv8i16 = 2257, |
| 2271 | VCGTsv8i8 = 2258, |
| 2272 | VCGTuv16i8 = 2259, |
| 2273 | VCGTuv2i32 = 2260, |
| 2274 | VCGTuv4i16 = 2261, |
| 2275 | VCGTuv4i32 = 2262, |
| 2276 | VCGTuv8i16 = 2263, |
| 2277 | VCGTuv8i8 = 2264, |
| 2278 | VCGTzv16i8 = 2265, |
| 2279 | VCGTzv2f32 = 2266, |
| 2280 | VCGTzv2i32 = 2267, |
| 2281 | VCGTzv4f16 = 2268, |
| 2282 | VCGTzv4f32 = 2269, |
| 2283 | VCGTzv4i16 = 2270, |
| 2284 | VCGTzv4i32 = 2271, |
| 2285 | VCGTzv8f16 = 2272, |
| 2286 | VCGTzv8i16 = 2273, |
| 2287 | VCGTzv8i8 = 2274, |
| 2288 | VCLEzv16i8 = 2275, |
| 2289 | VCLEzv2f32 = 2276, |
| 2290 | VCLEzv2i32 = 2277, |
| 2291 | VCLEzv4f16 = 2278, |
| 2292 | VCLEzv4f32 = 2279, |
| 2293 | VCLEzv4i16 = 2280, |
| 2294 | VCLEzv4i32 = 2281, |
| 2295 | VCLEzv8f16 = 2282, |
| 2296 | VCLEzv8i16 = 2283, |
| 2297 | VCLEzv8i8 = 2284, |
| 2298 | VCLSv16i8 = 2285, |
| 2299 | VCLSv2i32 = 2286, |
| 2300 | VCLSv4i16 = 2287, |
| 2301 | VCLSv4i32 = 2288, |
| 2302 | VCLSv8i16 = 2289, |
| 2303 | VCLSv8i8 = 2290, |
| 2304 | VCLTzv16i8 = 2291, |
| 2305 | VCLTzv2f32 = 2292, |
| 2306 | VCLTzv2i32 = 2293, |
| 2307 | VCLTzv4f16 = 2294, |
| 2308 | VCLTzv4f32 = 2295, |
| 2309 | VCLTzv4i16 = 2296, |
| 2310 | VCLTzv4i32 = 2297, |
| 2311 | VCLTzv8f16 = 2298, |
| 2312 | VCLTzv8i16 = 2299, |
| 2313 | VCLTzv8i8 = 2300, |
| 2314 | VCLZv16i8 = 2301, |
| 2315 | VCLZv2i32 = 2302, |
| 2316 | VCLZv4i16 = 2303, |
| 2317 | VCLZv4i32 = 2304, |
| 2318 | VCLZv8i16 = 2305, |
| 2319 | VCLZv8i8 = 2306, |
| 2320 | VCMLAv2f32 = 2307, |
| 2321 | VCMLAv2f32_indexed = 2308, |
| 2322 | VCMLAv4f16 = 2309, |
| 2323 | VCMLAv4f16_indexed = 2310, |
| 2324 | VCMLAv4f32 = 2311, |
| 2325 | VCMLAv4f32_indexed = 2312, |
| 2326 | VCMLAv8f16 = 2313, |
| 2327 | VCMLAv8f16_indexed = 2314, |
| 2328 | VCMPD = 2315, |
| 2329 | VCMPED = 2316, |
| 2330 | VCMPEH = 2317, |
| 2331 | VCMPES = 2318, |
| 2332 | VCMPEZD = 2319, |
| 2333 | VCMPEZH = 2320, |
| 2334 | VCMPEZS = 2321, |
| 2335 | VCMPH = 2322, |
| 2336 | VCMPS = 2323, |
| 2337 | VCMPZD = 2324, |
| 2338 | VCMPZH = 2325, |
| 2339 | VCMPZS = 2326, |
| 2340 | VCNTd = 2327, |
| 2341 | VCNTq = 2328, |
| 2342 | VCVTANSDf = 2329, |
| 2343 | VCVTANSDh = 2330, |
| 2344 | VCVTANSQf = 2331, |
| 2345 | VCVTANSQh = 2332, |
| 2346 | VCVTANUDf = 2333, |
| 2347 | VCVTANUDh = 2334, |
| 2348 | VCVTANUQf = 2335, |
| 2349 | VCVTANUQh = 2336, |
| 2350 | VCVTASD = 2337, |
| 2351 | VCVTASH = 2338, |
| 2352 | VCVTASS = 2339, |
| 2353 | VCVTAUD = 2340, |
| 2354 | VCVTAUH = 2341, |
| 2355 | VCVTAUS = 2342, |
| 2356 | VCVTBDH = 2343, |
| 2357 | VCVTBHD = 2344, |
| 2358 | VCVTBHS = 2345, |
| 2359 | VCVTBSH = 2346, |
| 2360 | VCVTDS = 2347, |
| 2361 | VCVTMNSDf = 2348, |
| 2362 | VCVTMNSDh = 2349, |
| 2363 | VCVTMNSQf = 2350, |
| 2364 | VCVTMNSQh = 2351, |
| 2365 | VCVTMNUDf = 2352, |
| 2366 | VCVTMNUDh = 2353, |
| 2367 | VCVTMNUQf = 2354, |
| 2368 | VCVTMNUQh = 2355, |
| 2369 | VCVTMSD = 2356, |
| 2370 | VCVTMSH = 2357, |
| 2371 | VCVTMSS = 2358, |
| 2372 | VCVTMUD = 2359, |
| 2373 | VCVTMUH = 2360, |
| 2374 | VCVTMUS = 2361, |
| 2375 | VCVTNNSDf = 2362, |
| 2376 | VCVTNNSDh = 2363, |
| 2377 | VCVTNNSQf = 2364, |
| 2378 | VCVTNNSQh = 2365, |
| 2379 | VCVTNNUDf = 2366, |
| 2380 | VCVTNNUDh = 2367, |
| 2381 | VCVTNNUQf = 2368, |
| 2382 | VCVTNNUQh = 2369, |
| 2383 | VCVTNSD = 2370, |
| 2384 | VCVTNSH = 2371, |
| 2385 | VCVTNSS = 2372, |
| 2386 | VCVTNUD = 2373, |
| 2387 | VCVTNUH = 2374, |
| 2388 | VCVTNUS = 2375, |
| 2389 | VCVTPNSDf = 2376, |
| 2390 | VCVTPNSDh = 2377, |
| 2391 | VCVTPNSQf = 2378, |
| 2392 | VCVTPNSQh = 2379, |
| 2393 | VCVTPNUDf = 2380, |
| 2394 | VCVTPNUDh = 2381, |
| 2395 | VCVTPNUQf = 2382, |
| 2396 | VCVTPNUQh = 2383, |
| 2397 | VCVTPSD = 2384, |
| 2398 | VCVTPSH = 2385, |
| 2399 | VCVTPSS = 2386, |
| 2400 | VCVTPUD = 2387, |
| 2401 | VCVTPUH = 2388, |
| 2402 | VCVTPUS = 2389, |
| 2403 | VCVTSD = 2390, |
| 2404 | VCVTTDH = 2391, |
| 2405 | VCVTTHD = 2392, |
| 2406 | VCVTTHS = 2393, |
| 2407 | VCVTTSH = 2394, |
| 2408 | VCVTf2h = 2395, |
| 2409 | VCVTf2sd = 2396, |
| 2410 | VCVTf2sq = 2397, |
| 2411 | VCVTf2ud = 2398, |
| 2412 | VCVTf2uq = 2399, |
| 2413 | VCVTf2xsd = 2400, |
| 2414 | VCVTf2xsq = 2401, |
| 2415 | VCVTf2xud = 2402, |
| 2416 | VCVTf2xuq = 2403, |
| 2417 | VCVTh2f = 2404, |
| 2418 | VCVTh2sd = 2405, |
| 2419 | VCVTh2sq = 2406, |
| 2420 | VCVTh2ud = 2407, |
| 2421 | VCVTh2uq = 2408, |
| 2422 | VCVTh2xsd = 2409, |
| 2423 | VCVTh2xsq = 2410, |
| 2424 | VCVTh2xud = 2411, |
| 2425 | VCVTh2xuq = 2412, |
| 2426 | VCVTs2fd = 2413, |
| 2427 | VCVTs2fq = 2414, |
| 2428 | VCVTs2hd = 2415, |
| 2429 | VCVTs2hq = 2416, |
| 2430 | VCVTu2fd = 2417, |
| 2431 | VCVTu2fq = 2418, |
| 2432 | VCVTu2hd = 2419, |
| 2433 | VCVTu2hq = 2420, |
| 2434 | VCVTxs2fd = 2421, |
| 2435 | VCVTxs2fq = 2422, |
| 2436 | VCVTxs2hd = 2423, |
| 2437 | VCVTxs2hq = 2424, |
| 2438 | VCVTxu2fd = 2425, |
| 2439 | VCVTxu2fq = 2426, |
| 2440 | VCVTxu2hd = 2427, |
| 2441 | VCVTxu2hq = 2428, |
| 2442 | VDIVD = 2429, |
| 2443 | VDIVH = 2430, |
| 2444 | VDIVS = 2431, |
| 2445 | VDUP16d = 2432, |
| 2446 | VDUP16q = 2433, |
| 2447 | VDUP32d = 2434, |
| 2448 | VDUP32q = 2435, |
| 2449 | VDUP8d = 2436, |
| 2450 | VDUP8q = 2437, |
| 2451 | VDUPLN16d = 2438, |
| 2452 | VDUPLN16q = 2439, |
| 2453 | VDUPLN32d = 2440, |
| 2454 | VDUPLN32q = 2441, |
| 2455 | VDUPLN8d = 2442, |
| 2456 | VDUPLN8q = 2443, |
| 2457 | VEORd = 2444, |
| 2458 | VEORq = 2445, |
| 2459 | VEXTd16 = 2446, |
| 2460 | VEXTd32 = 2447, |
| 2461 | VEXTd8 = 2448, |
| 2462 | VEXTq16 = 2449, |
| 2463 | VEXTq32 = 2450, |
| 2464 | VEXTq64 = 2451, |
| 2465 | VEXTq8 = 2452, |
| 2466 | VFMAD = 2453, |
| 2467 | VFMAH = 2454, |
| 2468 | VFMALD = 2455, |
| 2469 | VFMALDI = 2456, |
| 2470 | VFMALQ = 2457, |
| 2471 | VFMALQI = 2458, |
| 2472 | VFMAS = 2459, |
| 2473 | VFMAfd = 2460, |
| 2474 | VFMAfq = 2461, |
| 2475 | VFMAhd = 2462, |
| 2476 | VFMAhq = 2463, |
| 2477 | VFMSD = 2464, |
| 2478 | VFMSH = 2465, |
| 2479 | VFMSLD = 2466, |
| 2480 | VFMSLDI = 2467, |
| 2481 | VFMSLQ = 2468, |
| 2482 | VFMSLQI = 2469, |
| 2483 | VFMSS = 2470, |
| 2484 | VFMSfd = 2471, |
| 2485 | VFMSfq = 2472, |
| 2486 | VFMShd = 2473, |
| 2487 | VFMShq = 2474, |
| 2488 | VFNMAD = 2475, |
| 2489 | VFNMAH = 2476, |
| 2490 | VFNMAS = 2477, |
| 2491 | VFNMSD = 2478, |
| 2492 | VFNMSH = 2479, |
| 2493 | VFNMSS = 2480, |
| 2494 | VFP_VMAXNMD = 2481, |
| 2495 | VFP_VMAXNMH = 2482, |
| 2496 | VFP_VMAXNMS = 2483, |
| 2497 | VFP_VMINNMD = 2484, |
| 2498 | VFP_VMINNMH = 2485, |
| 2499 | VFP_VMINNMS = 2486, |
| 2500 | VGETLNi32 = 2487, |
| 2501 | VGETLNs16 = 2488, |
| 2502 | VGETLNs8 = 2489, |
| 2503 | VGETLNu16 = 2490, |
| 2504 | VGETLNu8 = 2491, |
| 2505 | VHADDsv16i8 = 2492, |
| 2506 | VHADDsv2i32 = 2493, |
| 2507 | VHADDsv4i16 = 2494, |
| 2508 | VHADDsv4i32 = 2495, |
| 2509 | VHADDsv8i16 = 2496, |
| 2510 | VHADDsv8i8 = 2497, |
| 2511 | VHADDuv16i8 = 2498, |
| 2512 | VHADDuv2i32 = 2499, |
| 2513 | VHADDuv4i16 = 2500, |
| 2514 | VHADDuv4i32 = 2501, |
| 2515 | VHADDuv8i16 = 2502, |
| 2516 | VHADDuv8i8 = 2503, |
| 2517 | VHSUBsv16i8 = 2504, |
| 2518 | VHSUBsv2i32 = 2505, |
| 2519 | VHSUBsv4i16 = 2506, |
| 2520 | VHSUBsv4i32 = 2507, |
| 2521 | VHSUBsv8i16 = 2508, |
| 2522 | VHSUBsv8i8 = 2509, |
| 2523 | VHSUBuv16i8 = 2510, |
| 2524 | VHSUBuv2i32 = 2511, |
| 2525 | VHSUBuv4i16 = 2512, |
| 2526 | VHSUBuv4i32 = 2513, |
| 2527 | VHSUBuv8i16 = 2514, |
| 2528 | VHSUBuv8i8 = 2515, |
| 2529 | VINSH = 2516, |
| 2530 | VJCVT = 2517, |
| 2531 | VLD1DUPd16 = 2518, |
| 2532 | VLD1DUPd16wb_fixed = 2519, |
| 2533 | VLD1DUPd16wb_register = 2520, |
| 2534 | VLD1DUPd32 = 2521, |
| 2535 | VLD1DUPd32wb_fixed = 2522, |
| 2536 | VLD1DUPd32wb_register = 2523, |
| 2537 | VLD1DUPd8 = 2524, |
| 2538 | VLD1DUPd8wb_fixed = 2525, |
| 2539 | VLD1DUPd8wb_register = 2526, |
| 2540 | VLD1DUPq16 = 2527, |
| 2541 | VLD1DUPq16wb_fixed = 2528, |
| 2542 | VLD1DUPq16wb_register = 2529, |
| 2543 | VLD1DUPq32 = 2530, |
| 2544 | VLD1DUPq32wb_fixed = 2531, |
| 2545 | VLD1DUPq32wb_register = 2532, |
| 2546 | VLD1DUPq8 = 2533, |
| 2547 | VLD1DUPq8wb_fixed = 2534, |
| 2548 | VLD1DUPq8wb_register = 2535, |
| 2549 | VLD1LNd16 = 2536, |
| 2550 | VLD1LNd16_UPD = 2537, |
| 2551 | VLD1LNd32 = 2538, |
| 2552 | VLD1LNd32_UPD = 2539, |
| 2553 | VLD1LNd8 = 2540, |
| 2554 | VLD1LNd8_UPD = 2541, |
| 2555 | VLD1LNq16Pseudo = 2542, |
| 2556 | VLD1LNq16Pseudo_UPD = 2543, |
| 2557 | VLD1LNq32Pseudo = 2544, |
| 2558 | VLD1LNq32Pseudo_UPD = 2545, |
| 2559 | VLD1LNq8Pseudo = 2546, |
| 2560 | VLD1LNq8Pseudo_UPD = 2547, |
| 2561 | VLD1d16 = 2548, |
| 2562 | VLD1d16Q = 2549, |
| 2563 | VLD1d16QPseudo = 2550, |
| 2564 | VLD1d16QPseudoWB_fixed = 2551, |
| 2565 | VLD1d16QPseudoWB_register = 2552, |
| 2566 | VLD1d16Qwb_fixed = 2553, |
| 2567 | VLD1d16Qwb_register = 2554, |
| 2568 | VLD1d16T = 2555, |
| 2569 | VLD1d16TPseudo = 2556, |
| 2570 | VLD1d16TPseudoWB_fixed = 2557, |
| 2571 | VLD1d16TPseudoWB_register = 2558, |
| 2572 | VLD1d16Twb_fixed = 2559, |
| 2573 | VLD1d16Twb_register = 2560, |
| 2574 | VLD1d16wb_fixed = 2561, |
| 2575 | VLD1d16wb_register = 2562, |
| 2576 | VLD1d32 = 2563, |
| 2577 | VLD1d32Q = 2564, |
| 2578 | VLD1d32QPseudo = 2565, |
| 2579 | VLD1d32QPseudoWB_fixed = 2566, |
| 2580 | VLD1d32QPseudoWB_register = 2567, |
| 2581 | VLD1d32Qwb_fixed = 2568, |
| 2582 | VLD1d32Qwb_register = 2569, |
| 2583 | VLD1d32T = 2570, |
| 2584 | VLD1d32TPseudo = 2571, |
| 2585 | VLD1d32TPseudoWB_fixed = 2572, |
| 2586 | VLD1d32TPseudoWB_register = 2573, |
| 2587 | VLD1d32Twb_fixed = 2574, |
| 2588 | VLD1d32Twb_register = 2575, |
| 2589 | VLD1d32wb_fixed = 2576, |
| 2590 | VLD1d32wb_register = 2577, |
| 2591 | VLD1d64 = 2578, |
| 2592 | VLD1d64Q = 2579, |
| 2593 | VLD1d64QPseudo = 2580, |
| 2594 | VLD1d64QPseudoWB_fixed = 2581, |
| 2595 | VLD1d64QPseudoWB_register = 2582, |
| 2596 | VLD1d64Qwb_fixed = 2583, |
| 2597 | VLD1d64Qwb_register = 2584, |
| 2598 | VLD1d64T = 2585, |
| 2599 | VLD1d64TPseudo = 2586, |
| 2600 | VLD1d64TPseudoWB_fixed = 2587, |
| 2601 | VLD1d64TPseudoWB_register = 2588, |
| 2602 | VLD1d64Twb_fixed = 2589, |
| 2603 | VLD1d64Twb_register = 2590, |
| 2604 | VLD1d64wb_fixed = 2591, |
| 2605 | VLD1d64wb_register = 2592, |
| 2606 | VLD1d8 = 2593, |
| 2607 | VLD1d8Q = 2594, |
| 2608 | VLD1d8QPseudo = 2595, |
| 2609 | VLD1d8QPseudoWB_fixed = 2596, |
| 2610 | VLD1d8QPseudoWB_register = 2597, |
| 2611 | VLD1d8Qwb_fixed = 2598, |
| 2612 | VLD1d8Qwb_register = 2599, |
| 2613 | VLD1d8T = 2600, |
| 2614 | VLD1d8TPseudo = 2601, |
| 2615 | VLD1d8TPseudoWB_fixed = 2602, |
| 2616 | VLD1d8TPseudoWB_register = 2603, |
| 2617 | VLD1d8Twb_fixed = 2604, |
| 2618 | VLD1d8Twb_register = 2605, |
| 2619 | VLD1d8wb_fixed = 2606, |
| 2620 | VLD1d8wb_register = 2607, |
| 2621 | VLD1q16 = 2608, |
| 2622 | VLD1q16HighQPseudo = 2609, |
| 2623 | VLD1q16HighQPseudo_UPD = 2610, |
| 2624 | VLD1q16HighTPseudo = 2611, |
| 2625 | VLD1q16HighTPseudo_UPD = 2612, |
| 2626 | VLD1q16LowQPseudo_UPD = 2613, |
| 2627 | VLD1q16LowTPseudo_UPD = 2614, |
| 2628 | VLD1q16wb_fixed = 2615, |
| 2629 | VLD1q16wb_register = 2616, |
| 2630 | VLD1q32 = 2617, |
| 2631 | VLD1q32HighQPseudo = 2618, |
| 2632 | VLD1q32HighQPseudo_UPD = 2619, |
| 2633 | VLD1q32HighTPseudo = 2620, |
| 2634 | VLD1q32HighTPseudo_UPD = 2621, |
| 2635 | VLD1q32LowQPseudo_UPD = 2622, |
| 2636 | VLD1q32LowTPseudo_UPD = 2623, |
| 2637 | VLD1q32wb_fixed = 2624, |
| 2638 | VLD1q32wb_register = 2625, |
| 2639 | VLD1q64 = 2626, |
| 2640 | VLD1q64HighQPseudo = 2627, |
| 2641 | VLD1q64HighQPseudo_UPD = 2628, |
| 2642 | VLD1q64HighTPseudo = 2629, |
| 2643 | VLD1q64HighTPseudo_UPD = 2630, |
| 2644 | VLD1q64LowQPseudo_UPD = 2631, |
| 2645 | VLD1q64LowTPseudo_UPD = 2632, |
| 2646 | VLD1q64wb_fixed = 2633, |
| 2647 | VLD1q64wb_register = 2634, |
| 2648 | VLD1q8 = 2635, |
| 2649 | VLD1q8HighQPseudo = 2636, |
| 2650 | VLD1q8HighQPseudo_UPD = 2637, |
| 2651 | VLD1q8HighTPseudo = 2638, |
| 2652 | VLD1q8HighTPseudo_UPD = 2639, |
| 2653 | VLD1q8LowQPseudo_UPD = 2640, |
| 2654 | VLD1q8LowTPseudo_UPD = 2641, |
| 2655 | VLD1q8wb_fixed = 2642, |
| 2656 | VLD1q8wb_register = 2643, |
| 2657 | VLD2DUPd16 = 2644, |
| 2658 | VLD2DUPd16wb_fixed = 2645, |
| 2659 | VLD2DUPd16wb_register = 2646, |
| 2660 | VLD2DUPd16x2 = 2647, |
| 2661 | VLD2DUPd16x2wb_fixed = 2648, |
| 2662 | VLD2DUPd16x2wb_register = 2649, |
| 2663 | VLD2DUPd32 = 2650, |
| 2664 | VLD2DUPd32wb_fixed = 2651, |
| 2665 | VLD2DUPd32wb_register = 2652, |
| 2666 | VLD2DUPd32x2 = 2653, |
| 2667 | VLD2DUPd32x2wb_fixed = 2654, |
| 2668 | VLD2DUPd32x2wb_register = 2655, |
| 2669 | VLD2DUPd8 = 2656, |
| 2670 | VLD2DUPd8wb_fixed = 2657, |
| 2671 | VLD2DUPd8wb_register = 2658, |
| 2672 | VLD2DUPd8x2 = 2659, |
| 2673 | VLD2DUPd8x2wb_fixed = 2660, |
| 2674 | VLD2DUPd8x2wb_register = 2661, |
| 2675 | VLD2DUPq16EvenPseudo = 2662, |
| 2676 | VLD2DUPq16OddPseudo = 2663, |
| 2677 | VLD2DUPq16OddPseudoWB_fixed = 2664, |
| 2678 | VLD2DUPq16OddPseudoWB_register = 2665, |
| 2679 | VLD2DUPq32EvenPseudo = 2666, |
| 2680 | VLD2DUPq32OddPseudo = 2667, |
| 2681 | VLD2DUPq32OddPseudoWB_fixed = 2668, |
| 2682 | VLD2DUPq32OddPseudoWB_register = 2669, |
| 2683 | VLD2DUPq8EvenPseudo = 2670, |
| 2684 | VLD2DUPq8OddPseudo = 2671, |
| 2685 | VLD2DUPq8OddPseudoWB_fixed = 2672, |
| 2686 | VLD2DUPq8OddPseudoWB_register = 2673, |
| 2687 | VLD2LNd16 = 2674, |
| 2688 | VLD2LNd16Pseudo = 2675, |
| 2689 | VLD2LNd16Pseudo_UPD = 2676, |
| 2690 | VLD2LNd16_UPD = 2677, |
| 2691 | VLD2LNd32 = 2678, |
| 2692 | VLD2LNd32Pseudo = 2679, |
| 2693 | VLD2LNd32Pseudo_UPD = 2680, |
| 2694 | VLD2LNd32_UPD = 2681, |
| 2695 | VLD2LNd8 = 2682, |
| 2696 | VLD2LNd8Pseudo = 2683, |
| 2697 | VLD2LNd8Pseudo_UPD = 2684, |
| 2698 | VLD2LNd8_UPD = 2685, |
| 2699 | VLD2LNq16 = 2686, |
| 2700 | VLD2LNq16Pseudo = 2687, |
| 2701 | VLD2LNq16Pseudo_UPD = 2688, |
| 2702 | VLD2LNq16_UPD = 2689, |
| 2703 | VLD2LNq32 = 2690, |
| 2704 | VLD2LNq32Pseudo = 2691, |
| 2705 | VLD2LNq32Pseudo_UPD = 2692, |
| 2706 | VLD2LNq32_UPD = 2693, |
| 2707 | VLD2b16 = 2694, |
| 2708 | VLD2b16wb_fixed = 2695, |
| 2709 | VLD2b16wb_register = 2696, |
| 2710 | VLD2b32 = 2697, |
| 2711 | VLD2b32wb_fixed = 2698, |
| 2712 | VLD2b32wb_register = 2699, |
| 2713 | VLD2b8 = 2700, |
| 2714 | VLD2b8wb_fixed = 2701, |
| 2715 | VLD2b8wb_register = 2702, |
| 2716 | VLD2d16 = 2703, |
| 2717 | VLD2d16wb_fixed = 2704, |
| 2718 | VLD2d16wb_register = 2705, |
| 2719 | VLD2d32 = 2706, |
| 2720 | VLD2d32wb_fixed = 2707, |
| 2721 | VLD2d32wb_register = 2708, |
| 2722 | VLD2d8 = 2709, |
| 2723 | VLD2d8wb_fixed = 2710, |
| 2724 | VLD2d8wb_register = 2711, |
| 2725 | VLD2q16 = 2712, |
| 2726 | VLD2q16Pseudo = 2713, |
| 2727 | VLD2q16PseudoWB_fixed = 2714, |
| 2728 | VLD2q16PseudoWB_register = 2715, |
| 2729 | VLD2q16wb_fixed = 2716, |
| 2730 | VLD2q16wb_register = 2717, |
| 2731 | VLD2q32 = 2718, |
| 2732 | VLD2q32Pseudo = 2719, |
| 2733 | VLD2q32PseudoWB_fixed = 2720, |
| 2734 | VLD2q32PseudoWB_register = 2721, |
| 2735 | VLD2q32wb_fixed = 2722, |
| 2736 | VLD2q32wb_register = 2723, |
| 2737 | VLD2q8 = 2724, |
| 2738 | VLD2q8Pseudo = 2725, |
| 2739 | VLD2q8PseudoWB_fixed = 2726, |
| 2740 | VLD2q8PseudoWB_register = 2727, |
| 2741 | VLD2q8wb_fixed = 2728, |
| 2742 | VLD2q8wb_register = 2729, |
| 2743 | VLD3DUPd16 = 2730, |
| 2744 | VLD3DUPd16Pseudo = 2731, |
| 2745 | VLD3DUPd16Pseudo_UPD = 2732, |
| 2746 | VLD3DUPd16_UPD = 2733, |
| 2747 | VLD3DUPd32 = 2734, |
| 2748 | VLD3DUPd32Pseudo = 2735, |
| 2749 | VLD3DUPd32Pseudo_UPD = 2736, |
| 2750 | VLD3DUPd32_UPD = 2737, |
| 2751 | VLD3DUPd8 = 2738, |
| 2752 | VLD3DUPd8Pseudo = 2739, |
| 2753 | VLD3DUPd8Pseudo_UPD = 2740, |
| 2754 | VLD3DUPd8_UPD = 2741, |
| 2755 | VLD3DUPq16 = 2742, |
| 2756 | VLD3DUPq16EvenPseudo = 2743, |
| 2757 | VLD3DUPq16OddPseudo = 2744, |
| 2758 | VLD3DUPq16OddPseudo_UPD = 2745, |
| 2759 | VLD3DUPq16_UPD = 2746, |
| 2760 | VLD3DUPq32 = 2747, |
| 2761 | VLD3DUPq32EvenPseudo = 2748, |
| 2762 | VLD3DUPq32OddPseudo = 2749, |
| 2763 | VLD3DUPq32OddPseudo_UPD = 2750, |
| 2764 | VLD3DUPq32_UPD = 2751, |
| 2765 | VLD3DUPq8 = 2752, |
| 2766 | VLD3DUPq8EvenPseudo = 2753, |
| 2767 | VLD3DUPq8OddPseudo = 2754, |
| 2768 | VLD3DUPq8OddPseudo_UPD = 2755, |
| 2769 | VLD3DUPq8_UPD = 2756, |
| 2770 | VLD3LNd16 = 2757, |
| 2771 | VLD3LNd16Pseudo = 2758, |
| 2772 | VLD3LNd16Pseudo_UPD = 2759, |
| 2773 | VLD3LNd16_UPD = 2760, |
| 2774 | VLD3LNd32 = 2761, |
| 2775 | VLD3LNd32Pseudo = 2762, |
| 2776 | VLD3LNd32Pseudo_UPD = 2763, |
| 2777 | VLD3LNd32_UPD = 2764, |
| 2778 | VLD3LNd8 = 2765, |
| 2779 | VLD3LNd8Pseudo = 2766, |
| 2780 | VLD3LNd8Pseudo_UPD = 2767, |
| 2781 | VLD3LNd8_UPD = 2768, |
| 2782 | VLD3LNq16 = 2769, |
| 2783 | VLD3LNq16Pseudo = 2770, |
| 2784 | VLD3LNq16Pseudo_UPD = 2771, |
| 2785 | VLD3LNq16_UPD = 2772, |
| 2786 | VLD3LNq32 = 2773, |
| 2787 | VLD3LNq32Pseudo = 2774, |
| 2788 | VLD3LNq32Pseudo_UPD = 2775, |
| 2789 | VLD3LNq32_UPD = 2776, |
| 2790 | VLD3d16 = 2777, |
| 2791 | VLD3d16Pseudo = 2778, |
| 2792 | VLD3d16Pseudo_UPD = 2779, |
| 2793 | VLD3d16_UPD = 2780, |
| 2794 | VLD3d32 = 2781, |
| 2795 | VLD3d32Pseudo = 2782, |
| 2796 | VLD3d32Pseudo_UPD = 2783, |
| 2797 | VLD3d32_UPD = 2784, |
| 2798 | VLD3d8 = 2785, |
| 2799 | VLD3d8Pseudo = 2786, |
| 2800 | VLD3d8Pseudo_UPD = 2787, |
| 2801 | VLD3d8_UPD = 2788, |
| 2802 | VLD3q16 = 2789, |
| 2803 | VLD3q16Pseudo_UPD = 2790, |
| 2804 | VLD3q16_UPD = 2791, |
| 2805 | VLD3q16oddPseudo = 2792, |
| 2806 | VLD3q16oddPseudo_UPD = 2793, |
| 2807 | VLD3q32 = 2794, |
| 2808 | VLD3q32Pseudo_UPD = 2795, |
| 2809 | VLD3q32_UPD = 2796, |
| 2810 | VLD3q32oddPseudo = 2797, |
| 2811 | VLD3q32oddPseudo_UPD = 2798, |
| 2812 | VLD3q8 = 2799, |
| 2813 | VLD3q8Pseudo_UPD = 2800, |
| 2814 | VLD3q8_UPD = 2801, |
| 2815 | VLD3q8oddPseudo = 2802, |
| 2816 | VLD3q8oddPseudo_UPD = 2803, |
| 2817 | VLD4DUPd16 = 2804, |
| 2818 | VLD4DUPd16Pseudo = 2805, |
| 2819 | VLD4DUPd16Pseudo_UPD = 2806, |
| 2820 | VLD4DUPd16_UPD = 2807, |
| 2821 | VLD4DUPd32 = 2808, |
| 2822 | VLD4DUPd32Pseudo = 2809, |
| 2823 | VLD4DUPd32Pseudo_UPD = 2810, |
| 2824 | VLD4DUPd32_UPD = 2811, |
| 2825 | VLD4DUPd8 = 2812, |
| 2826 | VLD4DUPd8Pseudo = 2813, |
| 2827 | VLD4DUPd8Pseudo_UPD = 2814, |
| 2828 | VLD4DUPd8_UPD = 2815, |
| 2829 | VLD4DUPq16 = 2816, |
| 2830 | VLD4DUPq16EvenPseudo = 2817, |
| 2831 | VLD4DUPq16OddPseudo = 2818, |
| 2832 | VLD4DUPq16OddPseudo_UPD = 2819, |
| 2833 | VLD4DUPq16_UPD = 2820, |
| 2834 | VLD4DUPq32 = 2821, |
| 2835 | VLD4DUPq32EvenPseudo = 2822, |
| 2836 | VLD4DUPq32OddPseudo = 2823, |
| 2837 | VLD4DUPq32OddPseudo_UPD = 2824, |
| 2838 | VLD4DUPq32_UPD = 2825, |
| 2839 | VLD4DUPq8 = 2826, |
| 2840 | VLD4DUPq8EvenPseudo = 2827, |
| 2841 | VLD4DUPq8OddPseudo = 2828, |
| 2842 | VLD4DUPq8OddPseudo_UPD = 2829, |
| 2843 | VLD4DUPq8_UPD = 2830, |
| 2844 | VLD4LNd16 = 2831, |
| 2845 | VLD4LNd16Pseudo = 2832, |
| 2846 | VLD4LNd16Pseudo_UPD = 2833, |
| 2847 | VLD4LNd16_UPD = 2834, |
| 2848 | VLD4LNd32 = 2835, |
| 2849 | VLD4LNd32Pseudo = 2836, |
| 2850 | VLD4LNd32Pseudo_UPD = 2837, |
| 2851 | VLD4LNd32_UPD = 2838, |
| 2852 | VLD4LNd8 = 2839, |
| 2853 | VLD4LNd8Pseudo = 2840, |
| 2854 | VLD4LNd8Pseudo_UPD = 2841, |
| 2855 | VLD4LNd8_UPD = 2842, |
| 2856 | VLD4LNq16 = 2843, |
| 2857 | VLD4LNq16Pseudo = 2844, |
| 2858 | VLD4LNq16Pseudo_UPD = 2845, |
| 2859 | VLD4LNq16_UPD = 2846, |
| 2860 | VLD4LNq32 = 2847, |
| 2861 | VLD4LNq32Pseudo = 2848, |
| 2862 | VLD4LNq32Pseudo_UPD = 2849, |
| 2863 | VLD4LNq32_UPD = 2850, |
| 2864 | VLD4d16 = 2851, |
| 2865 | VLD4d16Pseudo = 2852, |
| 2866 | VLD4d16Pseudo_UPD = 2853, |
| 2867 | VLD4d16_UPD = 2854, |
| 2868 | VLD4d32 = 2855, |
| 2869 | VLD4d32Pseudo = 2856, |
| 2870 | VLD4d32Pseudo_UPD = 2857, |
| 2871 | VLD4d32_UPD = 2858, |
| 2872 | VLD4d8 = 2859, |
| 2873 | VLD4d8Pseudo = 2860, |
| 2874 | VLD4d8Pseudo_UPD = 2861, |
| 2875 | VLD4d8_UPD = 2862, |
| 2876 | VLD4q16 = 2863, |
| 2877 | VLD4q16Pseudo_UPD = 2864, |
| 2878 | VLD4q16_UPD = 2865, |
| 2879 | VLD4q16oddPseudo = 2866, |
| 2880 | VLD4q16oddPseudo_UPD = 2867, |
| 2881 | VLD4q32 = 2868, |
| 2882 | VLD4q32Pseudo_UPD = 2869, |
| 2883 | VLD4q32_UPD = 2870, |
| 2884 | VLD4q32oddPseudo = 2871, |
| 2885 | VLD4q32oddPseudo_UPD = 2872, |
| 2886 | VLD4q8 = 2873, |
| 2887 | VLD4q8Pseudo_UPD = 2874, |
| 2888 | VLD4q8_UPD = 2875, |
| 2889 | VLD4q8oddPseudo = 2876, |
| 2890 | VLD4q8oddPseudo_UPD = 2877, |
| 2891 | VLDMDDB_UPD = 2878, |
| 2892 | VLDMDIA = 2879, |
| 2893 | VLDMDIA_UPD = 2880, |
| 2894 | VLDMQIA = 2881, |
| 2895 | VLDMSDB_UPD = 2882, |
| 2896 | VLDMSIA = 2883, |
| 2897 | VLDMSIA_UPD = 2884, |
| 2898 | VLDRD = 2885, |
| 2899 | VLDRH = 2886, |
| 2900 | VLDRS = 2887, |
| 2901 | VLDR_FPCXTNS_off = 2888, |
| 2902 | VLDR_FPCXTNS_post = 2889, |
| 2903 | VLDR_FPCXTNS_pre = 2890, |
| 2904 | VLDR_FPCXTS_off = 2891, |
| 2905 | VLDR_FPCXTS_post = 2892, |
| 2906 | VLDR_FPCXTS_pre = 2893, |
| 2907 | VLDR_FPSCR_NZCVQC_off = 2894, |
| 2908 | VLDR_FPSCR_NZCVQC_post = 2895, |
| 2909 | VLDR_FPSCR_NZCVQC_pre = 2896, |
| 2910 | VLDR_FPSCR_off = 2897, |
| 2911 | VLDR_FPSCR_post = 2898, |
| 2912 | VLDR_FPSCR_pre = 2899, |
| 2913 | VLDR_P0_off = 2900, |
| 2914 | VLDR_P0_post = 2901, |
| 2915 | VLDR_P0_pre = 2902, |
| 2916 | VLDR_VPR_off = 2903, |
| 2917 | VLDR_VPR_post = 2904, |
| 2918 | VLDR_VPR_pre = 2905, |
| 2919 | VLLDM = 2906, |
| 2920 | VLLDM_T2 = 2907, |
| 2921 | VLSTM = 2908, |
| 2922 | VLSTM_T2 = 2909, |
| 2923 | VMAXfd = 2910, |
| 2924 | VMAXfq = 2911, |
| 2925 | VMAXhd = 2912, |
| 2926 | VMAXhq = 2913, |
| 2927 | VMAXsv16i8 = 2914, |
| 2928 | VMAXsv2i32 = 2915, |
| 2929 | VMAXsv4i16 = 2916, |
| 2930 | VMAXsv4i32 = 2917, |
| 2931 | VMAXsv8i16 = 2918, |
| 2932 | VMAXsv8i8 = 2919, |
| 2933 | VMAXuv16i8 = 2920, |
| 2934 | VMAXuv2i32 = 2921, |
| 2935 | VMAXuv4i16 = 2922, |
| 2936 | VMAXuv4i32 = 2923, |
| 2937 | VMAXuv8i16 = 2924, |
| 2938 | VMAXuv8i8 = 2925, |
| 2939 | VMINfd = 2926, |
| 2940 | VMINfq = 2927, |
| 2941 | VMINhd = 2928, |
| 2942 | VMINhq = 2929, |
| 2943 | VMINsv16i8 = 2930, |
| 2944 | VMINsv2i32 = 2931, |
| 2945 | VMINsv4i16 = 2932, |
| 2946 | VMINsv4i32 = 2933, |
| 2947 | VMINsv8i16 = 2934, |
| 2948 | VMINsv8i8 = 2935, |
| 2949 | VMINuv16i8 = 2936, |
| 2950 | VMINuv2i32 = 2937, |
| 2951 | VMINuv4i16 = 2938, |
| 2952 | VMINuv4i32 = 2939, |
| 2953 | VMINuv8i16 = 2940, |
| 2954 | VMINuv8i8 = 2941, |
| 2955 | VMLAD = 2942, |
| 2956 | VMLAH = 2943, |
| 2957 | VMLALslsv2i32 = 2944, |
| 2958 | VMLALslsv4i16 = 2945, |
| 2959 | VMLALsluv2i32 = 2946, |
| 2960 | VMLALsluv4i16 = 2947, |
| 2961 | VMLALsv2i64 = 2948, |
| 2962 | VMLALsv4i32 = 2949, |
| 2963 | VMLALsv8i16 = 2950, |
| 2964 | VMLALuv2i64 = 2951, |
| 2965 | VMLALuv4i32 = 2952, |
| 2966 | VMLALuv8i16 = 2953, |
| 2967 | VMLAS = 2954, |
| 2968 | VMLAfd = 2955, |
| 2969 | VMLAfq = 2956, |
| 2970 | VMLAhd = 2957, |
| 2971 | VMLAhq = 2958, |
| 2972 | VMLAslfd = 2959, |
| 2973 | VMLAslfq = 2960, |
| 2974 | VMLAslhd = 2961, |
| 2975 | VMLAslhq = 2962, |
| 2976 | VMLAslv2i32 = 2963, |
| 2977 | VMLAslv4i16 = 2964, |
| 2978 | VMLAslv4i32 = 2965, |
| 2979 | VMLAslv8i16 = 2966, |
| 2980 | VMLAv16i8 = 2967, |
| 2981 | VMLAv2i32 = 2968, |
| 2982 | VMLAv4i16 = 2969, |
| 2983 | VMLAv4i32 = 2970, |
| 2984 | VMLAv8i16 = 2971, |
| 2985 | VMLAv8i8 = 2972, |
| 2986 | VMLSD = 2973, |
| 2987 | VMLSH = 2974, |
| 2988 | VMLSLslsv2i32 = 2975, |
| 2989 | VMLSLslsv4i16 = 2976, |
| 2990 | VMLSLsluv2i32 = 2977, |
| 2991 | VMLSLsluv4i16 = 2978, |
| 2992 | VMLSLsv2i64 = 2979, |
| 2993 | VMLSLsv4i32 = 2980, |
| 2994 | VMLSLsv8i16 = 2981, |
| 2995 | VMLSLuv2i64 = 2982, |
| 2996 | VMLSLuv4i32 = 2983, |
| 2997 | VMLSLuv8i16 = 2984, |
| 2998 | VMLSS = 2985, |
| 2999 | VMLSfd = 2986, |
| 3000 | VMLSfq = 2987, |
| 3001 | VMLShd = 2988, |
| 3002 | VMLShq = 2989, |
| 3003 | VMLSslfd = 2990, |
| 3004 | VMLSslfq = 2991, |
| 3005 | VMLSslhd = 2992, |
| 3006 | VMLSslhq = 2993, |
| 3007 | VMLSslv2i32 = 2994, |
| 3008 | VMLSslv4i16 = 2995, |
| 3009 | VMLSslv4i32 = 2996, |
| 3010 | VMLSslv8i16 = 2997, |
| 3011 | VMLSv16i8 = 2998, |
| 3012 | VMLSv2i32 = 2999, |
| 3013 | VMLSv4i16 = 3000, |
| 3014 | VMLSv4i32 = 3001, |
| 3015 | VMLSv8i16 = 3002, |
| 3016 | VMLSv8i8 = 3003, |
| 3017 | VMMLA = 3004, |
| 3018 | VMOVD = 3005, |
| 3019 | VMOVDRR = 3006, |
| 3020 | VMOVH = 3007, |
| 3021 | VMOVHR = 3008, |
| 3022 | VMOVLsv2i64 = 3009, |
| 3023 | VMOVLsv4i32 = 3010, |
| 3024 | VMOVLsv8i16 = 3011, |
| 3025 | VMOVLuv2i64 = 3012, |
| 3026 | VMOVLuv4i32 = 3013, |
| 3027 | VMOVLuv8i16 = 3014, |
| 3028 | VMOVNv2i32 = 3015, |
| 3029 | VMOVNv4i16 = 3016, |
| 3030 | VMOVNv8i8 = 3017, |
| 3031 | VMOVRH = 3018, |
| 3032 | VMOVRRD = 3019, |
| 3033 | VMOVRRS = 3020, |
| 3034 | VMOVRS = 3021, |
| 3035 | VMOVS = 3022, |
| 3036 | VMOVSR = 3023, |
| 3037 | VMOVSRR = 3024, |
| 3038 | VMOVv16i8 = 3025, |
| 3039 | VMOVv1i64 = 3026, |
| 3040 | VMOVv2f32 = 3027, |
| 3041 | VMOVv2i32 = 3028, |
| 3042 | VMOVv2i64 = 3029, |
| 3043 | VMOVv4f32 = 3030, |
| 3044 | VMOVv4i16 = 3031, |
| 3045 | VMOVv4i32 = 3032, |
| 3046 | VMOVv8i16 = 3033, |
| 3047 | VMOVv8i8 = 3034, |
| 3048 | VMRS = 3035, |
| 3049 | VMRS_FPCXTNS = 3036, |
| 3050 | VMRS_FPCXTS = 3037, |
| 3051 | VMRS_FPEXC = 3038, |
| 3052 | VMRS_FPINST = 3039, |
| 3053 | VMRS_FPINST2 = 3040, |
| 3054 | VMRS_FPSCR_NZCVQC = 3041, |
| 3055 | VMRS_FPSID = 3042, |
| 3056 | VMRS_MVFR0 = 3043, |
| 3057 | VMRS_MVFR1 = 3044, |
| 3058 | VMRS_MVFR2 = 3045, |
| 3059 | VMRS_P0 = 3046, |
| 3060 | VMRS_VPR = 3047, |
| 3061 | VMSR = 3048, |
| 3062 | VMSR_FPCXTNS = 3049, |
| 3063 | VMSR_FPCXTS = 3050, |
| 3064 | VMSR_FPEXC = 3051, |
| 3065 | VMSR_FPINST = 3052, |
| 3066 | VMSR_FPINST2 = 3053, |
| 3067 | VMSR_FPSCR_NZCVQC = 3054, |
| 3068 | VMSR_FPSID = 3055, |
| 3069 | VMSR_P0 = 3056, |
| 3070 | VMSR_VPR = 3057, |
| 3071 | VMULD = 3058, |
| 3072 | VMULH = 3059, |
| 3073 | VMULLp64 = 3060, |
| 3074 | VMULLp8 = 3061, |
| 3075 | VMULLslsv2i32 = 3062, |
| 3076 | VMULLslsv4i16 = 3063, |
| 3077 | VMULLsluv2i32 = 3064, |
| 3078 | VMULLsluv4i16 = 3065, |
| 3079 | VMULLsv2i64 = 3066, |
| 3080 | VMULLsv4i32 = 3067, |
| 3081 | VMULLsv8i16 = 3068, |
| 3082 | VMULLuv2i64 = 3069, |
| 3083 | VMULLuv4i32 = 3070, |
| 3084 | VMULLuv8i16 = 3071, |
| 3085 | VMULS = 3072, |
| 3086 | VMULfd = 3073, |
| 3087 | VMULfq = 3074, |
| 3088 | VMULhd = 3075, |
| 3089 | VMULhq = 3076, |
| 3090 | VMULpd = 3077, |
| 3091 | VMULpq = 3078, |
| 3092 | VMULslfd = 3079, |
| 3093 | VMULslfq = 3080, |
| 3094 | VMULslhd = 3081, |
| 3095 | VMULslhq = 3082, |
| 3096 | VMULslv2i32 = 3083, |
| 3097 | VMULslv4i16 = 3084, |
| 3098 | VMULslv4i32 = 3085, |
| 3099 | VMULslv8i16 = 3086, |
| 3100 | VMULv16i8 = 3087, |
| 3101 | VMULv2i32 = 3088, |
| 3102 | VMULv4i16 = 3089, |
| 3103 | VMULv4i32 = 3090, |
| 3104 | VMULv8i16 = 3091, |
| 3105 | VMULv8i8 = 3092, |
| 3106 | VMVNd = 3093, |
| 3107 | VMVNq = 3094, |
| 3108 | VMVNv2i32 = 3095, |
| 3109 | VMVNv4i16 = 3096, |
| 3110 | VMVNv4i32 = 3097, |
| 3111 | VMVNv8i16 = 3098, |
| 3112 | VNEGD = 3099, |
| 3113 | VNEGH = 3100, |
| 3114 | VNEGS = 3101, |
| 3115 | VNEGf32q = 3102, |
| 3116 | VNEGfd = 3103, |
| 3117 | VNEGhd = 3104, |
| 3118 | VNEGhq = 3105, |
| 3119 | VNEGs16d = 3106, |
| 3120 | VNEGs16q = 3107, |
| 3121 | VNEGs32d = 3108, |
| 3122 | VNEGs32q = 3109, |
| 3123 | VNEGs8d = 3110, |
| 3124 | VNEGs8q = 3111, |
| 3125 | VNMLAD = 3112, |
| 3126 | VNMLAH = 3113, |
| 3127 | VNMLAS = 3114, |
| 3128 | VNMLSD = 3115, |
| 3129 | VNMLSH = 3116, |
| 3130 | VNMLSS = 3117, |
| 3131 | VNMULD = 3118, |
| 3132 | VNMULH = 3119, |
| 3133 | VNMULS = 3120, |
| 3134 | VORNd = 3121, |
| 3135 | VORNq = 3122, |
| 3136 | VORRd = 3123, |
| 3137 | VORRiv2i32 = 3124, |
| 3138 | VORRiv4i16 = 3125, |
| 3139 | VORRiv4i32 = 3126, |
| 3140 | VORRiv8i16 = 3127, |
| 3141 | VORRq = 3128, |
| 3142 | VPADALsv16i8 = 3129, |
| 3143 | VPADALsv2i32 = 3130, |
| 3144 | VPADALsv4i16 = 3131, |
| 3145 | VPADALsv4i32 = 3132, |
| 3146 | VPADALsv8i16 = 3133, |
| 3147 | VPADALsv8i8 = 3134, |
| 3148 | VPADALuv16i8 = 3135, |
| 3149 | VPADALuv2i32 = 3136, |
| 3150 | VPADALuv4i16 = 3137, |
| 3151 | VPADALuv4i32 = 3138, |
| 3152 | VPADALuv8i16 = 3139, |
| 3153 | VPADALuv8i8 = 3140, |
| 3154 | VPADDLsv16i8 = 3141, |
| 3155 | VPADDLsv2i32 = 3142, |
| 3156 | VPADDLsv4i16 = 3143, |
| 3157 | VPADDLsv4i32 = 3144, |
| 3158 | VPADDLsv8i16 = 3145, |
| 3159 | VPADDLsv8i8 = 3146, |
| 3160 | VPADDLuv16i8 = 3147, |
| 3161 | VPADDLuv2i32 = 3148, |
| 3162 | VPADDLuv4i16 = 3149, |
| 3163 | VPADDLuv4i32 = 3150, |
| 3164 | VPADDLuv8i16 = 3151, |
| 3165 | VPADDLuv8i8 = 3152, |
| 3166 | VPADDf = 3153, |
| 3167 | VPADDh = 3154, |
| 3168 | VPADDi16 = 3155, |
| 3169 | VPADDi32 = 3156, |
| 3170 | VPADDi8 = 3157, |
| 3171 | VPMAXf = 3158, |
| 3172 | VPMAXh = 3159, |
| 3173 | VPMAXs16 = 3160, |
| 3174 | VPMAXs32 = 3161, |
| 3175 | VPMAXs8 = 3162, |
| 3176 | VPMAXu16 = 3163, |
| 3177 | VPMAXu32 = 3164, |
| 3178 | VPMAXu8 = 3165, |
| 3179 | VPMINf = 3166, |
| 3180 | VPMINh = 3167, |
| 3181 | VPMINs16 = 3168, |
| 3182 | VPMINs32 = 3169, |
| 3183 | VPMINs8 = 3170, |
| 3184 | VPMINu16 = 3171, |
| 3185 | VPMINu32 = 3172, |
| 3186 | VPMINu8 = 3173, |
| 3187 | VQABSv16i8 = 3174, |
| 3188 | VQABSv2i32 = 3175, |
| 3189 | VQABSv4i16 = 3176, |
| 3190 | VQABSv4i32 = 3177, |
| 3191 | VQABSv8i16 = 3178, |
| 3192 | VQABSv8i8 = 3179, |
| 3193 | VQADDsv16i8 = 3180, |
| 3194 | VQADDsv1i64 = 3181, |
| 3195 | VQADDsv2i32 = 3182, |
| 3196 | VQADDsv2i64 = 3183, |
| 3197 | VQADDsv4i16 = 3184, |
| 3198 | VQADDsv4i32 = 3185, |
| 3199 | VQADDsv8i16 = 3186, |
| 3200 | VQADDsv8i8 = 3187, |
| 3201 | VQADDuv16i8 = 3188, |
| 3202 | VQADDuv1i64 = 3189, |
| 3203 | VQADDuv2i32 = 3190, |
| 3204 | VQADDuv2i64 = 3191, |
| 3205 | VQADDuv4i16 = 3192, |
| 3206 | VQADDuv4i32 = 3193, |
| 3207 | VQADDuv8i16 = 3194, |
| 3208 | VQADDuv8i8 = 3195, |
| 3209 | VQDMLALslv2i32 = 3196, |
| 3210 | VQDMLALslv4i16 = 3197, |
| 3211 | VQDMLALv2i64 = 3198, |
| 3212 | VQDMLALv4i32 = 3199, |
| 3213 | VQDMLSLslv2i32 = 3200, |
| 3214 | VQDMLSLslv4i16 = 3201, |
| 3215 | VQDMLSLv2i64 = 3202, |
| 3216 | VQDMLSLv4i32 = 3203, |
| 3217 | VQDMULHslv2i32 = 3204, |
| 3218 | VQDMULHslv4i16 = 3205, |
| 3219 | VQDMULHslv4i32 = 3206, |
| 3220 | VQDMULHslv8i16 = 3207, |
| 3221 | VQDMULHv2i32 = 3208, |
| 3222 | VQDMULHv4i16 = 3209, |
| 3223 | VQDMULHv4i32 = 3210, |
| 3224 | VQDMULHv8i16 = 3211, |
| 3225 | VQDMULLslv2i32 = 3212, |
| 3226 | VQDMULLslv4i16 = 3213, |
| 3227 | VQDMULLv2i64 = 3214, |
| 3228 | VQDMULLv4i32 = 3215, |
| 3229 | VQMOVNsuv2i32 = 3216, |
| 3230 | VQMOVNsuv4i16 = 3217, |
| 3231 | VQMOVNsuv8i8 = 3218, |
| 3232 | VQMOVNsv2i32 = 3219, |
| 3233 | VQMOVNsv4i16 = 3220, |
| 3234 | VQMOVNsv8i8 = 3221, |
| 3235 | VQMOVNuv2i32 = 3222, |
| 3236 | VQMOVNuv4i16 = 3223, |
| 3237 | VQMOVNuv8i8 = 3224, |
| 3238 | VQNEGv16i8 = 3225, |
| 3239 | VQNEGv2i32 = 3226, |
| 3240 | VQNEGv4i16 = 3227, |
| 3241 | VQNEGv4i32 = 3228, |
| 3242 | VQNEGv8i16 = 3229, |
| 3243 | VQNEGv8i8 = 3230, |
| 3244 | VQRDMLAHslv2i32 = 3231, |
| 3245 | VQRDMLAHslv4i16 = 3232, |
| 3246 | VQRDMLAHslv4i32 = 3233, |
| 3247 | VQRDMLAHslv8i16 = 3234, |
| 3248 | VQRDMLAHv2i32 = 3235, |
| 3249 | VQRDMLAHv4i16 = 3236, |
| 3250 | VQRDMLAHv4i32 = 3237, |
| 3251 | VQRDMLAHv8i16 = 3238, |
| 3252 | VQRDMLSHslv2i32 = 3239, |
| 3253 | VQRDMLSHslv4i16 = 3240, |
| 3254 | VQRDMLSHslv4i32 = 3241, |
| 3255 | VQRDMLSHslv8i16 = 3242, |
| 3256 | VQRDMLSHv2i32 = 3243, |
| 3257 | VQRDMLSHv4i16 = 3244, |
| 3258 | VQRDMLSHv4i32 = 3245, |
| 3259 | VQRDMLSHv8i16 = 3246, |
| 3260 | VQRDMULHslv2i32 = 3247, |
| 3261 | VQRDMULHslv4i16 = 3248, |
| 3262 | VQRDMULHslv4i32 = 3249, |
| 3263 | VQRDMULHslv8i16 = 3250, |
| 3264 | VQRDMULHv2i32 = 3251, |
| 3265 | VQRDMULHv4i16 = 3252, |
| 3266 | VQRDMULHv4i32 = 3253, |
| 3267 | VQRDMULHv8i16 = 3254, |
| 3268 | VQRSHLsv16i8 = 3255, |
| 3269 | VQRSHLsv1i64 = 3256, |
| 3270 | VQRSHLsv2i32 = 3257, |
| 3271 | VQRSHLsv2i64 = 3258, |
| 3272 | VQRSHLsv4i16 = 3259, |
| 3273 | VQRSHLsv4i32 = 3260, |
| 3274 | VQRSHLsv8i16 = 3261, |
| 3275 | VQRSHLsv8i8 = 3262, |
| 3276 | VQRSHLuv16i8 = 3263, |
| 3277 | VQRSHLuv1i64 = 3264, |
| 3278 | VQRSHLuv2i32 = 3265, |
| 3279 | VQRSHLuv2i64 = 3266, |
| 3280 | VQRSHLuv4i16 = 3267, |
| 3281 | VQRSHLuv4i32 = 3268, |
| 3282 | VQRSHLuv8i16 = 3269, |
| 3283 | VQRSHLuv8i8 = 3270, |
| 3284 | VQRSHRNsv2i32 = 3271, |
| 3285 | VQRSHRNsv4i16 = 3272, |
| 3286 | VQRSHRNsv8i8 = 3273, |
| 3287 | VQRSHRNuv2i32 = 3274, |
| 3288 | VQRSHRNuv4i16 = 3275, |
| 3289 | VQRSHRNuv8i8 = 3276, |
| 3290 | VQRSHRUNv2i32 = 3277, |
| 3291 | VQRSHRUNv4i16 = 3278, |
| 3292 | VQRSHRUNv8i8 = 3279, |
| 3293 | VQSHLsiv16i8 = 3280, |
| 3294 | VQSHLsiv1i64 = 3281, |
| 3295 | VQSHLsiv2i32 = 3282, |
| 3296 | VQSHLsiv2i64 = 3283, |
| 3297 | VQSHLsiv4i16 = 3284, |
| 3298 | VQSHLsiv4i32 = 3285, |
| 3299 | VQSHLsiv8i16 = 3286, |
| 3300 | VQSHLsiv8i8 = 3287, |
| 3301 | VQSHLsuv16i8 = 3288, |
| 3302 | VQSHLsuv1i64 = 3289, |
| 3303 | VQSHLsuv2i32 = 3290, |
| 3304 | VQSHLsuv2i64 = 3291, |
| 3305 | VQSHLsuv4i16 = 3292, |
| 3306 | VQSHLsuv4i32 = 3293, |
| 3307 | VQSHLsuv8i16 = 3294, |
| 3308 | VQSHLsuv8i8 = 3295, |
| 3309 | VQSHLsv16i8 = 3296, |
| 3310 | VQSHLsv1i64 = 3297, |
| 3311 | VQSHLsv2i32 = 3298, |
| 3312 | VQSHLsv2i64 = 3299, |
| 3313 | VQSHLsv4i16 = 3300, |
| 3314 | VQSHLsv4i32 = 3301, |
| 3315 | VQSHLsv8i16 = 3302, |
| 3316 | VQSHLsv8i8 = 3303, |
| 3317 | VQSHLuiv16i8 = 3304, |
| 3318 | VQSHLuiv1i64 = 3305, |
| 3319 | VQSHLuiv2i32 = 3306, |
| 3320 | VQSHLuiv2i64 = 3307, |
| 3321 | VQSHLuiv4i16 = 3308, |
| 3322 | VQSHLuiv4i32 = 3309, |
| 3323 | VQSHLuiv8i16 = 3310, |
| 3324 | VQSHLuiv8i8 = 3311, |
| 3325 | VQSHLuv16i8 = 3312, |
| 3326 | VQSHLuv1i64 = 3313, |
| 3327 | VQSHLuv2i32 = 3314, |
| 3328 | VQSHLuv2i64 = 3315, |
| 3329 | VQSHLuv4i16 = 3316, |
| 3330 | VQSHLuv4i32 = 3317, |
| 3331 | VQSHLuv8i16 = 3318, |
| 3332 | VQSHLuv8i8 = 3319, |
| 3333 | VQSHRNsv2i32 = 3320, |
| 3334 | VQSHRNsv4i16 = 3321, |
| 3335 | VQSHRNsv8i8 = 3322, |
| 3336 | VQSHRNuv2i32 = 3323, |
| 3337 | VQSHRNuv4i16 = 3324, |
| 3338 | VQSHRNuv8i8 = 3325, |
| 3339 | VQSHRUNv2i32 = 3326, |
| 3340 | VQSHRUNv4i16 = 3327, |
| 3341 | VQSHRUNv8i8 = 3328, |
| 3342 | VQSUBsv16i8 = 3329, |
| 3343 | VQSUBsv1i64 = 3330, |
| 3344 | VQSUBsv2i32 = 3331, |
| 3345 | VQSUBsv2i64 = 3332, |
| 3346 | VQSUBsv4i16 = 3333, |
| 3347 | VQSUBsv4i32 = 3334, |
| 3348 | VQSUBsv8i16 = 3335, |
| 3349 | VQSUBsv8i8 = 3336, |
| 3350 | VQSUBuv16i8 = 3337, |
| 3351 | VQSUBuv1i64 = 3338, |
| 3352 | VQSUBuv2i32 = 3339, |
| 3353 | VQSUBuv2i64 = 3340, |
| 3354 | VQSUBuv4i16 = 3341, |
| 3355 | VQSUBuv4i32 = 3342, |
| 3356 | VQSUBuv8i16 = 3343, |
| 3357 | VQSUBuv8i8 = 3344, |
| 3358 | VRADDHNv2i32 = 3345, |
| 3359 | VRADDHNv4i16 = 3346, |
| 3360 | VRADDHNv8i8 = 3347, |
| 3361 | VRECPEd = 3348, |
| 3362 | VRECPEfd = 3349, |
| 3363 | VRECPEfq = 3350, |
| 3364 | VRECPEhd = 3351, |
| 3365 | VRECPEhq = 3352, |
| 3366 | VRECPEq = 3353, |
| 3367 | VRECPSfd = 3354, |
| 3368 | VRECPSfq = 3355, |
| 3369 | VRECPShd = 3356, |
| 3370 | VRECPShq = 3357, |
| 3371 | VREV16d8 = 3358, |
| 3372 | VREV16q8 = 3359, |
| 3373 | VREV32d16 = 3360, |
| 3374 | VREV32d8 = 3361, |
| 3375 | VREV32q16 = 3362, |
| 3376 | VREV32q8 = 3363, |
| 3377 | VREV64d16 = 3364, |
| 3378 | VREV64d32 = 3365, |
| 3379 | VREV64d8 = 3366, |
| 3380 | VREV64q16 = 3367, |
| 3381 | VREV64q32 = 3368, |
| 3382 | VREV64q8 = 3369, |
| 3383 | VRHADDsv16i8 = 3370, |
| 3384 | VRHADDsv2i32 = 3371, |
| 3385 | VRHADDsv4i16 = 3372, |
| 3386 | VRHADDsv4i32 = 3373, |
| 3387 | VRHADDsv8i16 = 3374, |
| 3388 | VRHADDsv8i8 = 3375, |
| 3389 | VRHADDuv16i8 = 3376, |
| 3390 | VRHADDuv2i32 = 3377, |
| 3391 | VRHADDuv4i16 = 3378, |
| 3392 | VRHADDuv4i32 = 3379, |
| 3393 | VRHADDuv8i16 = 3380, |
| 3394 | VRHADDuv8i8 = 3381, |
| 3395 | VRINTAD = 3382, |
| 3396 | VRINTAH = 3383, |
| 3397 | VRINTANDf = 3384, |
| 3398 | VRINTANDh = 3385, |
| 3399 | VRINTANQf = 3386, |
| 3400 | VRINTANQh = 3387, |
| 3401 | VRINTAS = 3388, |
| 3402 | VRINTMD = 3389, |
| 3403 | VRINTMH = 3390, |
| 3404 | VRINTMNDf = 3391, |
| 3405 | VRINTMNDh = 3392, |
| 3406 | VRINTMNQf = 3393, |
| 3407 | VRINTMNQh = 3394, |
| 3408 | VRINTMS = 3395, |
| 3409 | VRINTND = 3396, |
| 3410 | VRINTNH = 3397, |
| 3411 | VRINTNNDf = 3398, |
| 3412 | VRINTNNDh = 3399, |
| 3413 | VRINTNNQf = 3400, |
| 3414 | VRINTNNQh = 3401, |
| 3415 | VRINTNS = 3402, |
| 3416 | VRINTPD = 3403, |
| 3417 | VRINTPH = 3404, |
| 3418 | VRINTPNDf = 3405, |
| 3419 | VRINTPNDh = 3406, |
| 3420 | VRINTPNQf = 3407, |
| 3421 | VRINTPNQh = 3408, |
| 3422 | VRINTPS = 3409, |
| 3423 | VRINTRD = 3410, |
| 3424 | VRINTRH = 3411, |
| 3425 | VRINTRS = 3412, |
| 3426 | VRINTXD = 3413, |
| 3427 | VRINTXH = 3414, |
| 3428 | VRINTXNDf = 3415, |
| 3429 | VRINTXNDh = 3416, |
| 3430 | VRINTXNQf = 3417, |
| 3431 | VRINTXNQh = 3418, |
| 3432 | VRINTXS = 3419, |
| 3433 | VRINTZD = 3420, |
| 3434 | VRINTZH = 3421, |
| 3435 | VRINTZNDf = 3422, |
| 3436 | VRINTZNDh = 3423, |
| 3437 | VRINTZNQf = 3424, |
| 3438 | VRINTZNQh = 3425, |
| 3439 | VRINTZS = 3426, |
| 3440 | VRSHLsv16i8 = 3427, |
| 3441 | VRSHLsv1i64 = 3428, |
| 3442 | VRSHLsv2i32 = 3429, |
| 3443 | VRSHLsv2i64 = 3430, |
| 3444 | VRSHLsv4i16 = 3431, |
| 3445 | VRSHLsv4i32 = 3432, |
| 3446 | VRSHLsv8i16 = 3433, |
| 3447 | VRSHLsv8i8 = 3434, |
| 3448 | VRSHLuv16i8 = 3435, |
| 3449 | VRSHLuv1i64 = 3436, |
| 3450 | VRSHLuv2i32 = 3437, |
| 3451 | VRSHLuv2i64 = 3438, |
| 3452 | VRSHLuv4i16 = 3439, |
| 3453 | VRSHLuv4i32 = 3440, |
| 3454 | VRSHLuv8i16 = 3441, |
| 3455 | VRSHLuv8i8 = 3442, |
| 3456 | VRSHRNv2i32 = 3443, |
| 3457 | VRSHRNv4i16 = 3444, |
| 3458 | VRSHRNv8i8 = 3445, |
| 3459 | VRSHRsv16i8 = 3446, |
| 3460 | VRSHRsv1i64 = 3447, |
| 3461 | VRSHRsv2i32 = 3448, |
| 3462 | VRSHRsv2i64 = 3449, |
| 3463 | VRSHRsv4i16 = 3450, |
| 3464 | VRSHRsv4i32 = 3451, |
| 3465 | VRSHRsv8i16 = 3452, |
| 3466 | VRSHRsv8i8 = 3453, |
| 3467 | VRSHRuv16i8 = 3454, |
| 3468 | VRSHRuv1i64 = 3455, |
| 3469 | VRSHRuv2i32 = 3456, |
| 3470 | VRSHRuv2i64 = 3457, |
| 3471 | VRSHRuv4i16 = 3458, |
| 3472 | VRSHRuv4i32 = 3459, |
| 3473 | VRSHRuv8i16 = 3460, |
| 3474 | VRSHRuv8i8 = 3461, |
| 3475 | VRSQRTEd = 3462, |
| 3476 | VRSQRTEfd = 3463, |
| 3477 | VRSQRTEfq = 3464, |
| 3478 | VRSQRTEhd = 3465, |
| 3479 | VRSQRTEhq = 3466, |
| 3480 | VRSQRTEq = 3467, |
| 3481 | VRSQRTSfd = 3468, |
| 3482 | VRSQRTSfq = 3469, |
| 3483 | VRSQRTShd = 3470, |
| 3484 | VRSQRTShq = 3471, |
| 3485 | VRSRAsv16i8 = 3472, |
| 3486 | VRSRAsv1i64 = 3473, |
| 3487 | VRSRAsv2i32 = 3474, |
| 3488 | VRSRAsv2i64 = 3475, |
| 3489 | VRSRAsv4i16 = 3476, |
| 3490 | VRSRAsv4i32 = 3477, |
| 3491 | VRSRAsv8i16 = 3478, |
| 3492 | VRSRAsv8i8 = 3479, |
| 3493 | VRSRAuv16i8 = 3480, |
| 3494 | VRSRAuv1i64 = 3481, |
| 3495 | VRSRAuv2i32 = 3482, |
| 3496 | VRSRAuv2i64 = 3483, |
| 3497 | VRSRAuv4i16 = 3484, |
| 3498 | VRSRAuv4i32 = 3485, |
| 3499 | VRSRAuv8i16 = 3486, |
| 3500 | VRSRAuv8i8 = 3487, |
| 3501 | VRSUBHNv2i32 = 3488, |
| 3502 | VRSUBHNv4i16 = 3489, |
| 3503 | VRSUBHNv8i8 = 3490, |
| 3504 | VSCCLRMD = 3491, |
| 3505 | VSCCLRMS = 3492, |
| 3506 | VSDOTD = 3493, |
| 3507 | VSDOTDI = 3494, |
| 3508 | VSDOTQ = 3495, |
| 3509 | VSDOTQI = 3496, |
| 3510 | VSELEQD = 3497, |
| 3511 | VSELEQH = 3498, |
| 3512 | VSELEQS = 3499, |
| 3513 | VSELGED = 3500, |
| 3514 | VSELGEH = 3501, |
| 3515 | VSELGES = 3502, |
| 3516 | VSELGTD = 3503, |
| 3517 | VSELGTH = 3504, |
| 3518 | VSELGTS = 3505, |
| 3519 | VSELVSD = 3506, |
| 3520 | VSELVSH = 3507, |
| 3521 | VSELVSS = 3508, |
| 3522 | VSETLNi16 = 3509, |
| 3523 | VSETLNi32 = 3510, |
| 3524 | VSETLNi8 = 3511, |
| 3525 | VSHLLi16 = 3512, |
| 3526 | VSHLLi32 = 3513, |
| 3527 | VSHLLi8 = 3514, |
| 3528 | VSHLLsv2i64 = 3515, |
| 3529 | VSHLLsv4i32 = 3516, |
| 3530 | VSHLLsv8i16 = 3517, |
| 3531 | VSHLLuv2i64 = 3518, |
| 3532 | VSHLLuv4i32 = 3519, |
| 3533 | VSHLLuv8i16 = 3520, |
| 3534 | VSHLiv16i8 = 3521, |
| 3535 | VSHLiv1i64 = 3522, |
| 3536 | VSHLiv2i32 = 3523, |
| 3537 | VSHLiv2i64 = 3524, |
| 3538 | VSHLiv4i16 = 3525, |
| 3539 | VSHLiv4i32 = 3526, |
| 3540 | VSHLiv8i16 = 3527, |
| 3541 | VSHLiv8i8 = 3528, |
| 3542 | VSHLsv16i8 = 3529, |
| 3543 | VSHLsv1i64 = 3530, |
| 3544 | VSHLsv2i32 = 3531, |
| 3545 | VSHLsv2i64 = 3532, |
| 3546 | VSHLsv4i16 = 3533, |
| 3547 | VSHLsv4i32 = 3534, |
| 3548 | VSHLsv8i16 = 3535, |
| 3549 | VSHLsv8i8 = 3536, |
| 3550 | VSHLuv16i8 = 3537, |
| 3551 | VSHLuv1i64 = 3538, |
| 3552 | VSHLuv2i32 = 3539, |
| 3553 | VSHLuv2i64 = 3540, |
| 3554 | VSHLuv4i16 = 3541, |
| 3555 | VSHLuv4i32 = 3542, |
| 3556 | VSHLuv8i16 = 3543, |
| 3557 | VSHLuv8i8 = 3544, |
| 3558 | VSHRNv2i32 = 3545, |
| 3559 | VSHRNv4i16 = 3546, |
| 3560 | VSHRNv8i8 = 3547, |
| 3561 | VSHRsv16i8 = 3548, |
| 3562 | VSHRsv1i64 = 3549, |
| 3563 | VSHRsv2i32 = 3550, |
| 3564 | VSHRsv2i64 = 3551, |
| 3565 | VSHRsv4i16 = 3552, |
| 3566 | VSHRsv4i32 = 3553, |
| 3567 | VSHRsv8i16 = 3554, |
| 3568 | VSHRsv8i8 = 3555, |
| 3569 | VSHRuv16i8 = 3556, |
| 3570 | VSHRuv1i64 = 3557, |
| 3571 | VSHRuv2i32 = 3558, |
| 3572 | VSHRuv2i64 = 3559, |
| 3573 | VSHRuv4i16 = 3560, |
| 3574 | VSHRuv4i32 = 3561, |
| 3575 | VSHRuv8i16 = 3562, |
| 3576 | VSHRuv8i8 = 3563, |
| 3577 | VSHTOD = 3564, |
| 3578 | VSHTOH = 3565, |
| 3579 | VSHTOS = 3566, |
| 3580 | VSITOD = 3567, |
| 3581 | VSITOH = 3568, |
| 3582 | VSITOS = 3569, |
| 3583 | VSLIv16i8 = 3570, |
| 3584 | VSLIv1i64 = 3571, |
| 3585 | VSLIv2i32 = 3572, |
| 3586 | VSLIv2i64 = 3573, |
| 3587 | VSLIv4i16 = 3574, |
| 3588 | VSLIv4i32 = 3575, |
| 3589 | VSLIv8i16 = 3576, |
| 3590 | VSLIv8i8 = 3577, |
| 3591 | VSLTOD = 3578, |
| 3592 | VSLTOH = 3579, |
| 3593 | VSLTOS = 3580, |
| 3594 | VSMMLA = 3581, |
| 3595 | VSQRTD = 3582, |
| 3596 | VSQRTH = 3583, |
| 3597 | VSQRTS = 3584, |
| 3598 | VSRAsv16i8 = 3585, |
| 3599 | VSRAsv1i64 = 3586, |
| 3600 | VSRAsv2i32 = 3587, |
| 3601 | VSRAsv2i64 = 3588, |
| 3602 | VSRAsv4i16 = 3589, |
| 3603 | VSRAsv4i32 = 3590, |
| 3604 | VSRAsv8i16 = 3591, |
| 3605 | VSRAsv8i8 = 3592, |
| 3606 | VSRAuv16i8 = 3593, |
| 3607 | VSRAuv1i64 = 3594, |
| 3608 | VSRAuv2i32 = 3595, |
| 3609 | VSRAuv2i64 = 3596, |
| 3610 | VSRAuv4i16 = 3597, |
| 3611 | VSRAuv4i32 = 3598, |
| 3612 | VSRAuv8i16 = 3599, |
| 3613 | VSRAuv8i8 = 3600, |
| 3614 | VSRIv16i8 = 3601, |
| 3615 | VSRIv1i64 = 3602, |
| 3616 | VSRIv2i32 = 3603, |
| 3617 | VSRIv2i64 = 3604, |
| 3618 | VSRIv4i16 = 3605, |
| 3619 | VSRIv4i32 = 3606, |
| 3620 | VSRIv8i16 = 3607, |
| 3621 | VSRIv8i8 = 3608, |
| 3622 | VST1LNd16 = 3609, |
| 3623 | VST1LNd16_UPD = 3610, |
| 3624 | VST1LNd32 = 3611, |
| 3625 | VST1LNd32_UPD = 3612, |
| 3626 | VST1LNd8 = 3613, |
| 3627 | VST1LNd8_UPD = 3614, |
| 3628 | VST1LNq16Pseudo = 3615, |
| 3629 | VST1LNq16Pseudo_UPD = 3616, |
| 3630 | VST1LNq32Pseudo = 3617, |
| 3631 | VST1LNq32Pseudo_UPD = 3618, |
| 3632 | VST1LNq8Pseudo = 3619, |
| 3633 | VST1LNq8Pseudo_UPD = 3620, |
| 3634 | VST1d16 = 3621, |
| 3635 | VST1d16Q = 3622, |
| 3636 | VST1d16QPseudo = 3623, |
| 3637 | VST1d16QPseudoWB_fixed = 3624, |
| 3638 | VST1d16QPseudoWB_register = 3625, |
| 3639 | VST1d16Qwb_fixed = 3626, |
| 3640 | VST1d16Qwb_register = 3627, |
| 3641 | VST1d16T = 3628, |
| 3642 | VST1d16TPseudo = 3629, |
| 3643 | VST1d16TPseudoWB_fixed = 3630, |
| 3644 | VST1d16TPseudoWB_register = 3631, |
| 3645 | VST1d16Twb_fixed = 3632, |
| 3646 | VST1d16Twb_register = 3633, |
| 3647 | VST1d16wb_fixed = 3634, |
| 3648 | VST1d16wb_register = 3635, |
| 3649 | VST1d32 = 3636, |
| 3650 | VST1d32Q = 3637, |
| 3651 | VST1d32QPseudo = 3638, |
| 3652 | VST1d32QPseudoWB_fixed = 3639, |
| 3653 | VST1d32QPseudoWB_register = 3640, |
| 3654 | VST1d32Qwb_fixed = 3641, |
| 3655 | VST1d32Qwb_register = 3642, |
| 3656 | VST1d32T = 3643, |
| 3657 | VST1d32TPseudo = 3644, |
| 3658 | VST1d32TPseudoWB_fixed = 3645, |
| 3659 | VST1d32TPseudoWB_register = 3646, |
| 3660 | VST1d32Twb_fixed = 3647, |
| 3661 | VST1d32Twb_register = 3648, |
| 3662 | VST1d32wb_fixed = 3649, |
| 3663 | VST1d32wb_register = 3650, |
| 3664 | VST1d64 = 3651, |
| 3665 | VST1d64Q = 3652, |
| 3666 | VST1d64QPseudo = 3653, |
| 3667 | VST1d64QPseudoWB_fixed = 3654, |
| 3668 | VST1d64QPseudoWB_register = 3655, |
| 3669 | VST1d64Qwb_fixed = 3656, |
| 3670 | VST1d64Qwb_register = 3657, |
| 3671 | VST1d64T = 3658, |
| 3672 | VST1d64TPseudo = 3659, |
| 3673 | VST1d64TPseudoWB_fixed = 3660, |
| 3674 | VST1d64TPseudoWB_register = 3661, |
| 3675 | VST1d64Twb_fixed = 3662, |
| 3676 | VST1d64Twb_register = 3663, |
| 3677 | VST1d64wb_fixed = 3664, |
| 3678 | VST1d64wb_register = 3665, |
| 3679 | VST1d8 = 3666, |
| 3680 | VST1d8Q = 3667, |
| 3681 | VST1d8QPseudo = 3668, |
| 3682 | VST1d8QPseudoWB_fixed = 3669, |
| 3683 | VST1d8QPseudoWB_register = 3670, |
| 3684 | VST1d8Qwb_fixed = 3671, |
| 3685 | VST1d8Qwb_register = 3672, |
| 3686 | VST1d8T = 3673, |
| 3687 | VST1d8TPseudo = 3674, |
| 3688 | VST1d8TPseudoWB_fixed = 3675, |
| 3689 | VST1d8TPseudoWB_register = 3676, |
| 3690 | VST1d8Twb_fixed = 3677, |
| 3691 | VST1d8Twb_register = 3678, |
| 3692 | VST1d8wb_fixed = 3679, |
| 3693 | VST1d8wb_register = 3680, |
| 3694 | VST1q16 = 3681, |
| 3695 | VST1q16HighQPseudo = 3682, |
| 3696 | VST1q16HighQPseudo_UPD = 3683, |
| 3697 | VST1q16HighTPseudo = 3684, |
| 3698 | VST1q16HighTPseudo_UPD = 3685, |
| 3699 | VST1q16LowQPseudo_UPD = 3686, |
| 3700 | VST1q16LowTPseudo_UPD = 3687, |
| 3701 | VST1q16wb_fixed = 3688, |
| 3702 | VST1q16wb_register = 3689, |
| 3703 | VST1q32 = 3690, |
| 3704 | VST1q32HighQPseudo = 3691, |
| 3705 | VST1q32HighQPseudo_UPD = 3692, |
| 3706 | VST1q32HighTPseudo = 3693, |
| 3707 | VST1q32HighTPseudo_UPD = 3694, |
| 3708 | VST1q32LowQPseudo_UPD = 3695, |
| 3709 | VST1q32LowTPseudo_UPD = 3696, |
| 3710 | VST1q32wb_fixed = 3697, |
| 3711 | VST1q32wb_register = 3698, |
| 3712 | VST1q64 = 3699, |
| 3713 | VST1q64HighQPseudo = 3700, |
| 3714 | VST1q64HighQPseudo_UPD = 3701, |
| 3715 | VST1q64HighTPseudo = 3702, |
| 3716 | VST1q64HighTPseudo_UPD = 3703, |
| 3717 | VST1q64LowQPseudo_UPD = 3704, |
| 3718 | VST1q64LowTPseudo_UPD = 3705, |
| 3719 | VST1q64wb_fixed = 3706, |
| 3720 | VST1q64wb_register = 3707, |
| 3721 | VST1q8 = 3708, |
| 3722 | VST1q8HighQPseudo = 3709, |
| 3723 | VST1q8HighQPseudo_UPD = 3710, |
| 3724 | VST1q8HighTPseudo = 3711, |
| 3725 | VST1q8HighTPseudo_UPD = 3712, |
| 3726 | VST1q8LowQPseudo_UPD = 3713, |
| 3727 | VST1q8LowTPseudo_UPD = 3714, |
| 3728 | VST1q8wb_fixed = 3715, |
| 3729 | VST1q8wb_register = 3716, |
| 3730 | VST2LNd16 = 3717, |
| 3731 | VST2LNd16Pseudo = 3718, |
| 3732 | VST2LNd16Pseudo_UPD = 3719, |
| 3733 | VST2LNd16_UPD = 3720, |
| 3734 | VST2LNd32 = 3721, |
| 3735 | VST2LNd32Pseudo = 3722, |
| 3736 | VST2LNd32Pseudo_UPD = 3723, |
| 3737 | VST2LNd32_UPD = 3724, |
| 3738 | VST2LNd8 = 3725, |
| 3739 | VST2LNd8Pseudo = 3726, |
| 3740 | VST2LNd8Pseudo_UPD = 3727, |
| 3741 | VST2LNd8_UPD = 3728, |
| 3742 | VST2LNq16 = 3729, |
| 3743 | VST2LNq16Pseudo = 3730, |
| 3744 | VST2LNq16Pseudo_UPD = 3731, |
| 3745 | VST2LNq16_UPD = 3732, |
| 3746 | VST2LNq32 = 3733, |
| 3747 | VST2LNq32Pseudo = 3734, |
| 3748 | VST2LNq32Pseudo_UPD = 3735, |
| 3749 | VST2LNq32_UPD = 3736, |
| 3750 | VST2b16 = 3737, |
| 3751 | VST2b16wb_fixed = 3738, |
| 3752 | VST2b16wb_register = 3739, |
| 3753 | VST2b32 = 3740, |
| 3754 | VST2b32wb_fixed = 3741, |
| 3755 | VST2b32wb_register = 3742, |
| 3756 | VST2b8 = 3743, |
| 3757 | VST2b8wb_fixed = 3744, |
| 3758 | VST2b8wb_register = 3745, |
| 3759 | VST2d16 = 3746, |
| 3760 | VST2d16wb_fixed = 3747, |
| 3761 | VST2d16wb_register = 3748, |
| 3762 | VST2d32 = 3749, |
| 3763 | VST2d32wb_fixed = 3750, |
| 3764 | VST2d32wb_register = 3751, |
| 3765 | VST2d8 = 3752, |
| 3766 | VST2d8wb_fixed = 3753, |
| 3767 | VST2d8wb_register = 3754, |
| 3768 | VST2q16 = 3755, |
| 3769 | VST2q16Pseudo = 3756, |
| 3770 | VST2q16PseudoWB_fixed = 3757, |
| 3771 | VST2q16PseudoWB_register = 3758, |
| 3772 | VST2q16wb_fixed = 3759, |
| 3773 | VST2q16wb_register = 3760, |
| 3774 | VST2q32 = 3761, |
| 3775 | VST2q32Pseudo = 3762, |
| 3776 | VST2q32PseudoWB_fixed = 3763, |
| 3777 | VST2q32PseudoWB_register = 3764, |
| 3778 | VST2q32wb_fixed = 3765, |
| 3779 | VST2q32wb_register = 3766, |
| 3780 | VST2q8 = 3767, |
| 3781 | VST2q8Pseudo = 3768, |
| 3782 | VST2q8PseudoWB_fixed = 3769, |
| 3783 | VST2q8PseudoWB_register = 3770, |
| 3784 | VST2q8wb_fixed = 3771, |
| 3785 | VST2q8wb_register = 3772, |
| 3786 | VST3LNd16 = 3773, |
| 3787 | VST3LNd16Pseudo = 3774, |
| 3788 | VST3LNd16Pseudo_UPD = 3775, |
| 3789 | VST3LNd16_UPD = 3776, |
| 3790 | VST3LNd32 = 3777, |
| 3791 | VST3LNd32Pseudo = 3778, |
| 3792 | VST3LNd32Pseudo_UPD = 3779, |
| 3793 | VST3LNd32_UPD = 3780, |
| 3794 | VST3LNd8 = 3781, |
| 3795 | VST3LNd8Pseudo = 3782, |
| 3796 | VST3LNd8Pseudo_UPD = 3783, |
| 3797 | VST3LNd8_UPD = 3784, |
| 3798 | VST3LNq16 = 3785, |
| 3799 | VST3LNq16Pseudo = 3786, |
| 3800 | VST3LNq16Pseudo_UPD = 3787, |
| 3801 | VST3LNq16_UPD = 3788, |
| 3802 | VST3LNq32 = 3789, |
| 3803 | VST3LNq32Pseudo = 3790, |
| 3804 | VST3LNq32Pseudo_UPD = 3791, |
| 3805 | VST3LNq32_UPD = 3792, |
| 3806 | VST3d16 = 3793, |
| 3807 | VST3d16Pseudo = 3794, |
| 3808 | VST3d16Pseudo_UPD = 3795, |
| 3809 | VST3d16_UPD = 3796, |
| 3810 | VST3d32 = 3797, |
| 3811 | VST3d32Pseudo = 3798, |
| 3812 | VST3d32Pseudo_UPD = 3799, |
| 3813 | VST3d32_UPD = 3800, |
| 3814 | VST3d8 = 3801, |
| 3815 | VST3d8Pseudo = 3802, |
| 3816 | VST3d8Pseudo_UPD = 3803, |
| 3817 | VST3d8_UPD = 3804, |
| 3818 | VST3q16 = 3805, |
| 3819 | VST3q16Pseudo_UPD = 3806, |
| 3820 | VST3q16_UPD = 3807, |
| 3821 | VST3q16oddPseudo = 3808, |
| 3822 | VST3q16oddPseudo_UPD = 3809, |
| 3823 | VST3q32 = 3810, |
| 3824 | VST3q32Pseudo_UPD = 3811, |
| 3825 | VST3q32_UPD = 3812, |
| 3826 | VST3q32oddPseudo = 3813, |
| 3827 | VST3q32oddPseudo_UPD = 3814, |
| 3828 | VST3q8 = 3815, |
| 3829 | VST3q8Pseudo_UPD = 3816, |
| 3830 | VST3q8_UPD = 3817, |
| 3831 | VST3q8oddPseudo = 3818, |
| 3832 | VST3q8oddPseudo_UPD = 3819, |
| 3833 | VST4LNd16 = 3820, |
| 3834 | VST4LNd16Pseudo = 3821, |
| 3835 | VST4LNd16Pseudo_UPD = 3822, |
| 3836 | VST4LNd16_UPD = 3823, |
| 3837 | VST4LNd32 = 3824, |
| 3838 | VST4LNd32Pseudo = 3825, |
| 3839 | VST4LNd32Pseudo_UPD = 3826, |
| 3840 | VST4LNd32_UPD = 3827, |
| 3841 | VST4LNd8 = 3828, |
| 3842 | VST4LNd8Pseudo = 3829, |
| 3843 | VST4LNd8Pseudo_UPD = 3830, |
| 3844 | VST4LNd8_UPD = 3831, |
| 3845 | VST4LNq16 = 3832, |
| 3846 | VST4LNq16Pseudo = 3833, |
| 3847 | VST4LNq16Pseudo_UPD = 3834, |
| 3848 | VST4LNq16_UPD = 3835, |
| 3849 | VST4LNq32 = 3836, |
| 3850 | VST4LNq32Pseudo = 3837, |
| 3851 | VST4LNq32Pseudo_UPD = 3838, |
| 3852 | VST4LNq32_UPD = 3839, |
| 3853 | VST4d16 = 3840, |
| 3854 | VST4d16Pseudo = 3841, |
| 3855 | VST4d16Pseudo_UPD = 3842, |
| 3856 | VST4d16_UPD = 3843, |
| 3857 | VST4d32 = 3844, |
| 3858 | VST4d32Pseudo = 3845, |
| 3859 | VST4d32Pseudo_UPD = 3846, |
| 3860 | VST4d32_UPD = 3847, |
| 3861 | VST4d8 = 3848, |
| 3862 | VST4d8Pseudo = 3849, |
| 3863 | VST4d8Pseudo_UPD = 3850, |
| 3864 | VST4d8_UPD = 3851, |
| 3865 | VST4q16 = 3852, |
| 3866 | VST4q16Pseudo_UPD = 3853, |
| 3867 | VST4q16_UPD = 3854, |
| 3868 | VST4q16oddPseudo = 3855, |
| 3869 | VST4q16oddPseudo_UPD = 3856, |
| 3870 | VST4q32 = 3857, |
| 3871 | VST4q32Pseudo_UPD = 3858, |
| 3872 | VST4q32_UPD = 3859, |
| 3873 | VST4q32oddPseudo = 3860, |
| 3874 | VST4q32oddPseudo_UPD = 3861, |
| 3875 | VST4q8 = 3862, |
| 3876 | VST4q8Pseudo_UPD = 3863, |
| 3877 | VST4q8_UPD = 3864, |
| 3878 | VST4q8oddPseudo = 3865, |
| 3879 | VST4q8oddPseudo_UPD = 3866, |
| 3880 | VSTMDDB_UPD = 3867, |
| 3881 | VSTMDIA = 3868, |
| 3882 | VSTMDIA_UPD = 3869, |
| 3883 | VSTMQIA = 3870, |
| 3884 | VSTMSDB_UPD = 3871, |
| 3885 | VSTMSIA = 3872, |
| 3886 | VSTMSIA_UPD = 3873, |
| 3887 | VSTRD = 3874, |
| 3888 | VSTRH = 3875, |
| 3889 | VSTRS = 3876, |
| 3890 | VSTR_FPCXTNS_off = 3877, |
| 3891 | VSTR_FPCXTNS_post = 3878, |
| 3892 | VSTR_FPCXTNS_pre = 3879, |
| 3893 | VSTR_FPCXTS_off = 3880, |
| 3894 | VSTR_FPCXTS_post = 3881, |
| 3895 | VSTR_FPCXTS_pre = 3882, |
| 3896 | VSTR_FPSCR_NZCVQC_off = 3883, |
| 3897 | VSTR_FPSCR_NZCVQC_post = 3884, |
| 3898 | VSTR_FPSCR_NZCVQC_pre = 3885, |
| 3899 | VSTR_FPSCR_off = 3886, |
| 3900 | VSTR_FPSCR_post = 3887, |
| 3901 | VSTR_FPSCR_pre = 3888, |
| 3902 | VSTR_P0_off = 3889, |
| 3903 | VSTR_P0_post = 3890, |
| 3904 | VSTR_P0_pre = 3891, |
| 3905 | VSTR_VPR_off = 3892, |
| 3906 | VSTR_VPR_post = 3893, |
| 3907 | VSTR_VPR_pre = 3894, |
| 3908 | VSUBD = 3895, |
| 3909 | VSUBH = 3896, |
| 3910 | VSUBHNv2i32 = 3897, |
| 3911 | VSUBHNv4i16 = 3898, |
| 3912 | VSUBHNv8i8 = 3899, |
| 3913 | VSUBLsv2i64 = 3900, |
| 3914 | VSUBLsv4i32 = 3901, |
| 3915 | VSUBLsv8i16 = 3902, |
| 3916 | VSUBLuv2i64 = 3903, |
| 3917 | VSUBLuv4i32 = 3904, |
| 3918 | VSUBLuv8i16 = 3905, |
| 3919 | VSUBS = 3906, |
| 3920 | VSUBWsv2i64 = 3907, |
| 3921 | VSUBWsv4i32 = 3908, |
| 3922 | VSUBWsv8i16 = 3909, |
| 3923 | VSUBWuv2i64 = 3910, |
| 3924 | VSUBWuv4i32 = 3911, |
| 3925 | VSUBWuv8i16 = 3912, |
| 3926 | VSUBfd = 3913, |
| 3927 | VSUBfq = 3914, |
| 3928 | VSUBhd = 3915, |
| 3929 | VSUBhq = 3916, |
| 3930 | VSUBv16i8 = 3917, |
| 3931 | VSUBv1i64 = 3918, |
| 3932 | VSUBv2i32 = 3919, |
| 3933 | VSUBv2i64 = 3920, |
| 3934 | VSUBv4i16 = 3921, |
| 3935 | VSUBv4i32 = 3922, |
| 3936 | VSUBv8i16 = 3923, |
| 3937 | VSUBv8i8 = 3924, |
| 3938 | VSUDOTDI = 3925, |
| 3939 | VSUDOTQI = 3926, |
| 3940 | VSWPd = 3927, |
| 3941 | VSWPq = 3928, |
| 3942 | VTBL1 = 3929, |
| 3943 | VTBL2 = 3930, |
| 3944 | VTBL3 = 3931, |
| 3945 | VTBL3Pseudo = 3932, |
| 3946 | VTBL4 = 3933, |
| 3947 | VTBL4Pseudo = 3934, |
| 3948 | VTBX1 = 3935, |
| 3949 | VTBX2 = 3936, |
| 3950 | VTBX3 = 3937, |
| 3951 | VTBX3Pseudo = 3938, |
| 3952 | VTBX4 = 3939, |
| 3953 | VTBX4Pseudo = 3940, |
| 3954 | VTOSHD = 3941, |
| 3955 | VTOSHH = 3942, |
| 3956 | VTOSHS = 3943, |
| 3957 | VTOSIRD = 3944, |
| 3958 | VTOSIRH = 3945, |
| 3959 | VTOSIRS = 3946, |
| 3960 | VTOSIZD = 3947, |
| 3961 | VTOSIZH = 3948, |
| 3962 | VTOSIZS = 3949, |
| 3963 | VTOSLD = 3950, |
| 3964 | VTOSLH = 3951, |
| 3965 | VTOSLS = 3952, |
| 3966 | VTOUHD = 3953, |
| 3967 | VTOUHH = 3954, |
| 3968 | VTOUHS = 3955, |
| 3969 | VTOUIRD = 3956, |
| 3970 | VTOUIRH = 3957, |
| 3971 | VTOUIRS = 3958, |
| 3972 | VTOUIZD = 3959, |
| 3973 | VTOUIZH = 3960, |
| 3974 | VTOUIZS = 3961, |
| 3975 | VTOULD = 3962, |
| 3976 | VTOULH = 3963, |
| 3977 | VTOULS = 3964, |
| 3978 | VTRNd16 = 3965, |
| 3979 | VTRNd32 = 3966, |
| 3980 | VTRNd8 = 3967, |
| 3981 | VTRNq16 = 3968, |
| 3982 | VTRNq32 = 3969, |
| 3983 | VTRNq8 = 3970, |
| 3984 | VTSTv16i8 = 3971, |
| 3985 | VTSTv2i32 = 3972, |
| 3986 | VTSTv4i16 = 3973, |
| 3987 | VTSTv4i32 = 3974, |
| 3988 | VTSTv8i16 = 3975, |
| 3989 | VTSTv8i8 = 3976, |
| 3990 | VUDOTD = 3977, |
| 3991 | VUDOTDI = 3978, |
| 3992 | VUDOTQ = 3979, |
| 3993 | VUDOTQI = 3980, |
| 3994 | VUHTOD = 3981, |
| 3995 | VUHTOH = 3982, |
| 3996 | VUHTOS = 3983, |
| 3997 | VUITOD = 3984, |
| 3998 | VUITOH = 3985, |
| 3999 | VUITOS = 3986, |
| 4000 | VULTOD = 3987, |
| 4001 | VULTOH = 3988, |
| 4002 | VULTOS = 3989, |
| 4003 | VUMMLA = 3990, |
| 4004 | VUSDOTD = 3991, |
| 4005 | VUSDOTDI = 3992, |
| 4006 | VUSDOTQ = 3993, |
| 4007 | VUSDOTQI = 3994, |
| 4008 | VUSMMLA = 3995, |
| 4009 | VUZPd16 = 3996, |
| 4010 | VUZPd8 = 3997, |
| 4011 | VUZPq16 = 3998, |
| 4012 | VUZPq32 = 3999, |
| 4013 | VUZPq8 = 4000, |
| 4014 | VZIPd16 = 4001, |
| 4015 | VZIPd8 = 4002, |
| 4016 | VZIPq16 = 4003, |
| 4017 | VZIPq32 = 4004, |
| 4018 | VZIPq8 = 4005, |
| 4019 | sysLDMDA = 4006, |
| 4020 | sysLDMDA_UPD = 4007, |
| 4021 | sysLDMDB = 4008, |
| 4022 | sysLDMDB_UPD = 4009, |
| 4023 | sysLDMIA = 4010, |
| 4024 | sysLDMIA_UPD = 4011, |
| 4025 | sysLDMIB = 4012, |
| 4026 | sysLDMIB_UPD = 4013, |
| 4027 | sysSTMDA = 4014, |
| 4028 | sysSTMDA_UPD = 4015, |
| 4029 | sysSTMDB = 4016, |
| 4030 | sysSTMDB_UPD = 4017, |
| 4031 | sysSTMIA = 4018, |
| 4032 | sysSTMIA_UPD = 4019, |
| 4033 | sysSTMIB = 4020, |
| 4034 | sysSTMIB_UPD = 4021, |
| 4035 | t2ADCri = 4022, |
| 4036 | t2ADCrr = 4023, |
| 4037 | t2ADCrs = 4024, |
| 4038 | t2ADDri = 4025, |
| 4039 | t2ADDri12 = 4026, |
| 4040 | t2ADDrr = 4027, |
| 4041 | t2ADDrs = 4028, |
| 4042 | t2ADDspImm = 4029, |
| 4043 | t2ADDspImm12 = 4030, |
| 4044 | t2ADR = 4031, |
| 4045 | t2ANDri = 4032, |
| 4046 | t2ANDrr = 4033, |
| 4047 | t2ANDrs = 4034, |
| 4048 | t2ASRri = 4035, |
| 4049 | t2ASRrr = 4036, |
| 4050 | t2ASRs1 = 4037, |
| 4051 | t2AUT = 4038, |
| 4052 | t2AUTG = 4039, |
| 4053 | t2B = 4040, |
| 4054 | t2BFC = 4041, |
| 4055 | t2BFI = 4042, |
| 4056 | t2BFLi = 4043, |
| 4057 | t2BFLr = 4044, |
| 4058 | t2BFi = 4045, |
| 4059 | t2BFic = 4046, |
| 4060 | t2BFr = 4047, |
| 4061 | t2BICri = 4048, |
| 4062 | t2BICrr = 4049, |
| 4063 | t2BICrs = 4050, |
| 4064 | t2BTI = 4051, |
| 4065 | t2BXAUT = 4052, |
| 4066 | t2BXJ = 4053, |
| 4067 | t2Bcc = 4054, |
| 4068 | t2CDP = 4055, |
| 4069 | t2CDP2 = 4056, |
| 4070 | t2CLREX = 4057, |
| 4071 | t2CLRM = 4058, |
| 4072 | t2CLZ = 4059, |
| 4073 | t2CMNri = 4060, |
| 4074 | t2CMNzrr = 4061, |
| 4075 | t2CMNzrs = 4062, |
| 4076 | t2CMPri = 4063, |
| 4077 | t2CMPrr = 4064, |
| 4078 | t2CMPrs = 4065, |
| 4079 | t2CPS1p = 4066, |
| 4080 | t2CPS2p = 4067, |
| 4081 | t2CPS3p = 4068, |
| 4082 | t2CRC32B = 4069, |
| 4083 | t2CRC32CB = 4070, |
| 4084 | t2CRC32CH = 4071, |
| 4085 | t2CRC32CW = 4072, |
| 4086 | t2CRC32H = 4073, |
| 4087 | t2CRC32W = 4074, |
| 4088 | t2CSEL = 4075, |
| 4089 | t2CSINC = 4076, |
| 4090 | t2CSINV = 4077, |
| 4091 | t2CSNEG = 4078, |
| 4092 | t2DBG = 4079, |
| 4093 | t2DCPS1 = 4080, |
| 4094 | t2DCPS2 = 4081, |
| 4095 | t2DCPS3 = 4082, |
| 4096 | t2DLS = 4083, |
| 4097 | t2DMB = 4084, |
| 4098 | t2DSB = 4085, |
| 4099 | t2EORri = 4086, |
| 4100 | t2EORrr = 4087, |
| 4101 | t2EORrs = 4088, |
| 4102 | t2HINT = 4089, |
| 4103 | t2HVC = 4090, |
| 4104 | t2ISB = 4091, |
| 4105 | t2IT = 4092, |
| 4106 | t2Int_eh_sjlj_setjmp = 4093, |
| 4107 | t2Int_eh_sjlj_setjmp_nofp = 4094, |
| 4108 | t2LDA = 4095, |
| 4109 | t2LDAB = 4096, |
| 4110 | t2LDAEX = 4097, |
| 4111 | t2LDAEXB = 4098, |
| 4112 | t2LDAEXD = 4099, |
| 4113 | t2LDAEXH = 4100, |
| 4114 | t2LDAH = 4101, |
| 4115 | t2LDC2L_OFFSET = 4102, |
| 4116 | t2LDC2L_OPTION = 4103, |
| 4117 | t2LDC2L_POST = 4104, |
| 4118 | t2LDC2L_PRE = 4105, |
| 4119 | t2LDC2_OFFSET = 4106, |
| 4120 | t2LDC2_OPTION = 4107, |
| 4121 | t2LDC2_POST = 4108, |
| 4122 | t2LDC2_PRE = 4109, |
| 4123 | t2LDCL_OFFSET = 4110, |
| 4124 | t2LDCL_OPTION = 4111, |
| 4125 | t2LDCL_POST = 4112, |
| 4126 | t2LDCL_PRE = 4113, |
| 4127 | t2LDC_OFFSET = 4114, |
| 4128 | t2LDC_OPTION = 4115, |
| 4129 | t2LDC_POST = 4116, |
| 4130 | t2LDC_PRE = 4117, |
| 4131 | t2LDMDB = 4118, |
| 4132 | t2LDMDB_UPD = 4119, |
| 4133 | t2LDMIA = 4120, |
| 4134 | t2LDMIA_UPD = 4121, |
| 4135 | t2LDRBT = 4122, |
| 4136 | t2LDRB_POST = 4123, |
| 4137 | t2LDRB_PRE = 4124, |
| 4138 | t2LDRBi12 = 4125, |
| 4139 | t2LDRBi8 = 4126, |
| 4140 | t2LDRBpci = 4127, |
| 4141 | t2LDRBs = 4128, |
| 4142 | t2LDRD_POST = 4129, |
| 4143 | t2LDRD_PRE = 4130, |
| 4144 | t2LDRDi8 = 4131, |
| 4145 | t2LDREX = 4132, |
| 4146 | t2LDREXB = 4133, |
| 4147 | t2LDREXD = 4134, |
| 4148 | t2LDREXH = 4135, |
| 4149 | t2LDRHT = 4136, |
| 4150 | t2LDRH_POST = 4137, |
| 4151 | t2LDRH_PRE = 4138, |
| 4152 | t2LDRHi12 = 4139, |
| 4153 | t2LDRHi8 = 4140, |
| 4154 | t2LDRHpci = 4141, |
| 4155 | t2LDRHs = 4142, |
| 4156 | t2LDRSBT = 4143, |
| 4157 | t2LDRSB_POST = 4144, |
| 4158 | t2LDRSB_PRE = 4145, |
| 4159 | t2LDRSBi12 = 4146, |
| 4160 | t2LDRSBi8 = 4147, |
| 4161 | t2LDRSBpci = 4148, |
| 4162 | t2LDRSBs = 4149, |
| 4163 | t2LDRSHT = 4150, |
| 4164 | t2LDRSH_POST = 4151, |
| 4165 | t2LDRSH_PRE = 4152, |
| 4166 | t2LDRSHi12 = 4153, |
| 4167 | t2LDRSHi8 = 4154, |
| 4168 | t2LDRSHpci = 4155, |
| 4169 | t2LDRSHs = 4156, |
| 4170 | t2LDRT = 4157, |
| 4171 | t2LDR_POST = 4158, |
| 4172 | t2LDR_PRE = 4159, |
| 4173 | t2LDRi12 = 4160, |
| 4174 | t2LDRi8 = 4161, |
| 4175 | t2LDRpci = 4162, |
| 4176 | t2LDRs = 4163, |
| 4177 | t2LE = 4164, |
| 4178 | t2LEUpdate = 4165, |
| 4179 | t2LSLri = 4166, |
| 4180 | t2LSLrr = 4167, |
| 4181 | t2LSRri = 4168, |
| 4182 | t2LSRrr = 4169, |
| 4183 | t2LSRs1 = 4170, |
| 4184 | t2MCR = 4171, |
| 4185 | t2MCR2 = 4172, |
| 4186 | t2MCRR = 4173, |
| 4187 | t2MCRR2 = 4174, |
| 4188 | t2MLA = 4175, |
| 4189 | t2MLS = 4176, |
| 4190 | t2MOVTi16 = 4177, |
| 4191 | t2MOVi = 4178, |
| 4192 | t2MOVi16 = 4179, |
| 4193 | t2MOVr = 4180, |
| 4194 | t2MRC = 4181, |
| 4195 | t2MRC2 = 4182, |
| 4196 | t2MRRC = 4183, |
| 4197 | t2MRRC2 = 4184, |
| 4198 | t2MRS_AR = 4185, |
| 4199 | t2MRS_M = 4186, |
| 4200 | t2MRSbanked = 4187, |
| 4201 | t2MRSsys_AR = 4188, |
| 4202 | t2MSR_AR = 4189, |
| 4203 | t2MSR_M = 4190, |
| 4204 | t2MSRbanked = 4191, |
| 4205 | t2MUL = 4192, |
| 4206 | t2MVNi = 4193, |
| 4207 | t2MVNr = 4194, |
| 4208 | t2MVNs = 4195, |
| 4209 | t2ORNri = 4196, |
| 4210 | t2ORNrr = 4197, |
| 4211 | t2ORNrs = 4198, |
| 4212 | t2ORRri = 4199, |
| 4213 | t2ORRrr = 4200, |
| 4214 | t2ORRrs = 4201, |
| 4215 | t2PAC = 4202, |
| 4216 | t2PACBTI = 4203, |
| 4217 | t2PACG = 4204, |
| 4218 | t2PKHBT = 4205, |
| 4219 | t2PKHTB = 4206, |
| 4220 | t2PLDWi12 = 4207, |
| 4221 | t2PLDWi8 = 4208, |
| 4222 | t2PLDWs = 4209, |
| 4223 | t2PLDi12 = 4210, |
| 4224 | t2PLDi8 = 4211, |
| 4225 | t2PLDpci = 4212, |
| 4226 | t2PLDs = 4213, |
| 4227 | t2PLIi12 = 4214, |
| 4228 | t2PLIi8 = 4215, |
| 4229 | t2PLIpci = 4216, |
| 4230 | t2PLIs = 4217, |
| 4231 | t2QADD = 4218, |
| 4232 | t2QADD16 = 4219, |
| 4233 | t2QADD8 = 4220, |
| 4234 | t2QASX = 4221, |
| 4235 | t2QDADD = 4222, |
| 4236 | t2QDSUB = 4223, |
| 4237 | t2QSAX = 4224, |
| 4238 | t2QSUB = 4225, |
| 4239 | t2QSUB16 = 4226, |
| 4240 | t2QSUB8 = 4227, |
| 4241 | t2RBIT = 4228, |
| 4242 | t2REV = 4229, |
| 4243 | t2REV16 = 4230, |
| 4244 | t2REVSH = 4231, |
| 4245 | t2RFEDB = 4232, |
| 4246 | t2RFEDBW = 4233, |
| 4247 | t2RFEIA = 4234, |
| 4248 | t2RFEIAW = 4235, |
| 4249 | t2RORri = 4236, |
| 4250 | t2RORrr = 4237, |
| 4251 | t2RRX = 4238, |
| 4252 | t2RSBri = 4239, |
| 4253 | t2RSBrr = 4240, |
| 4254 | t2RSBrs = 4241, |
| 4255 | t2SADD16 = 4242, |
| 4256 | t2SADD8 = 4243, |
| 4257 | t2SASX = 4244, |
| 4258 | t2SB = 4245, |
| 4259 | t2SBCri = 4246, |
| 4260 | t2SBCrr = 4247, |
| 4261 | t2SBCrs = 4248, |
| 4262 | t2SBFX = 4249, |
| 4263 | t2SDIV = 4250, |
| 4264 | t2SEL = 4251, |
| 4265 | t2SETPAN = 4252, |
| 4266 | t2SG = 4253, |
| 4267 | t2SHADD16 = 4254, |
| 4268 | t2SHADD8 = 4255, |
| 4269 | t2SHASX = 4256, |
| 4270 | t2SHSAX = 4257, |
| 4271 | t2SHSUB16 = 4258, |
| 4272 | t2SHSUB8 = 4259, |
| 4273 | t2SMC = 4260, |
| 4274 | t2SMLABB = 4261, |
| 4275 | t2SMLABT = 4262, |
| 4276 | t2SMLAD = 4263, |
| 4277 | t2SMLADX = 4264, |
| 4278 | t2SMLAL = 4265, |
| 4279 | t2SMLALBB = 4266, |
| 4280 | t2SMLALBT = 4267, |
| 4281 | t2SMLALD = 4268, |
| 4282 | t2SMLALDX = 4269, |
| 4283 | t2SMLALTB = 4270, |
| 4284 | t2SMLALTT = 4271, |
| 4285 | t2SMLATB = 4272, |
| 4286 | t2SMLATT = 4273, |
| 4287 | t2SMLAWB = 4274, |
| 4288 | t2SMLAWT = 4275, |
| 4289 | t2SMLSD = 4276, |
| 4290 | t2SMLSDX = 4277, |
| 4291 | t2SMLSLD = 4278, |
| 4292 | t2SMLSLDX = 4279, |
| 4293 | t2SMMLA = 4280, |
| 4294 | t2SMMLAR = 4281, |
| 4295 | t2SMMLS = 4282, |
| 4296 | t2SMMLSR = 4283, |
| 4297 | t2SMMUL = 4284, |
| 4298 | t2SMMULR = 4285, |
| 4299 | t2SMUAD = 4286, |
| 4300 | t2SMUADX = 4287, |
| 4301 | t2SMULBB = 4288, |
| 4302 | t2SMULBT = 4289, |
| 4303 | t2SMULL = 4290, |
| 4304 | t2SMULTB = 4291, |
| 4305 | t2SMULTT = 4292, |
| 4306 | t2SMULWB = 4293, |
| 4307 | t2SMULWT = 4294, |
| 4308 | t2SMUSD = 4295, |
| 4309 | t2SMUSDX = 4296, |
| 4310 | t2SRSDB = 4297, |
| 4311 | t2SRSDB_UPD = 4298, |
| 4312 | t2SRSIA = 4299, |
| 4313 | t2SRSIA_UPD = 4300, |
| 4314 | t2SSAT = 4301, |
| 4315 | t2SSAT16 = 4302, |
| 4316 | t2SSAX = 4303, |
| 4317 | t2SSUB16 = 4304, |
| 4318 | t2SSUB8 = 4305, |
| 4319 | t2STC2L_OFFSET = 4306, |
| 4320 | t2STC2L_OPTION = 4307, |
| 4321 | t2STC2L_POST = 4308, |
| 4322 | t2STC2L_PRE = 4309, |
| 4323 | t2STC2_OFFSET = 4310, |
| 4324 | t2STC2_OPTION = 4311, |
| 4325 | t2STC2_POST = 4312, |
| 4326 | t2STC2_PRE = 4313, |
| 4327 | t2STCL_OFFSET = 4314, |
| 4328 | t2STCL_OPTION = 4315, |
| 4329 | t2STCL_POST = 4316, |
| 4330 | t2STCL_PRE = 4317, |
| 4331 | t2STC_OFFSET = 4318, |
| 4332 | t2STC_OPTION = 4319, |
| 4333 | t2STC_POST = 4320, |
| 4334 | t2STC_PRE = 4321, |
| 4335 | t2STL = 4322, |
| 4336 | t2STLB = 4323, |
| 4337 | t2STLEX = 4324, |
| 4338 | t2STLEXB = 4325, |
| 4339 | t2STLEXD = 4326, |
| 4340 | t2STLEXH = 4327, |
| 4341 | t2STLH = 4328, |
| 4342 | t2STMDB = 4329, |
| 4343 | t2STMDB_UPD = 4330, |
| 4344 | t2STMIA = 4331, |
| 4345 | t2STMIA_UPD = 4332, |
| 4346 | t2STRBT = 4333, |
| 4347 | t2STRB_POST = 4334, |
| 4348 | t2STRB_PRE = 4335, |
| 4349 | t2STRBi12 = 4336, |
| 4350 | t2STRBi8 = 4337, |
| 4351 | t2STRBs = 4338, |
| 4352 | t2STRD_POST = 4339, |
| 4353 | t2STRD_PRE = 4340, |
| 4354 | t2STRDi8 = 4341, |
| 4355 | t2STREX = 4342, |
| 4356 | t2STREXB = 4343, |
| 4357 | t2STREXD = 4344, |
| 4358 | t2STREXH = 4345, |
| 4359 | t2STRHT = 4346, |
| 4360 | t2STRH_POST = 4347, |
| 4361 | t2STRH_PRE = 4348, |
| 4362 | t2STRHi12 = 4349, |
| 4363 | t2STRHi8 = 4350, |
| 4364 | t2STRHs = 4351, |
| 4365 | t2STRT = 4352, |
| 4366 | t2STR_POST = 4353, |
| 4367 | t2STR_PRE = 4354, |
| 4368 | t2STRi12 = 4355, |
| 4369 | t2STRi8 = 4356, |
| 4370 | t2STRs = 4357, |
| 4371 | t2SUBS_PC_LR = 4358, |
| 4372 | t2SUBri = 4359, |
| 4373 | t2SUBri12 = 4360, |
| 4374 | t2SUBrr = 4361, |
| 4375 | t2SUBrs = 4362, |
| 4376 | t2SUBspImm = 4363, |
| 4377 | t2SUBspImm12 = 4364, |
| 4378 | t2SXTAB = 4365, |
| 4379 | t2SXTAB16 = 4366, |
| 4380 | t2SXTAH = 4367, |
| 4381 | t2SXTB = 4368, |
| 4382 | t2SXTB16 = 4369, |
| 4383 | t2SXTH = 4370, |
| 4384 | t2TBB = 4371, |
| 4385 | t2TBH = 4372, |
| 4386 | t2TEQri = 4373, |
| 4387 | t2TEQrr = 4374, |
| 4388 | t2TEQrs = 4375, |
| 4389 | t2TSB = 4376, |
| 4390 | t2TSTri = 4377, |
| 4391 | t2TSTrr = 4378, |
| 4392 | t2TSTrs = 4379, |
| 4393 | t2TT = 4380, |
| 4394 | t2TTA = 4381, |
| 4395 | t2TTAT = 4382, |
| 4396 | t2TTT = 4383, |
| 4397 | t2UADD16 = 4384, |
| 4398 | t2UADD8 = 4385, |
| 4399 | t2UASX = 4386, |
| 4400 | t2UBFX = 4387, |
| 4401 | t2UDF = 4388, |
| 4402 | t2UDIV = 4389, |
| 4403 | t2UHADD16 = 4390, |
| 4404 | t2UHADD8 = 4391, |
| 4405 | t2UHASX = 4392, |
| 4406 | t2UHSAX = 4393, |
| 4407 | t2UHSUB16 = 4394, |
| 4408 | t2UHSUB8 = 4395, |
| 4409 | t2UMAAL = 4396, |
| 4410 | t2UMLAL = 4397, |
| 4411 | t2UMULL = 4398, |
| 4412 | t2UQADD16 = 4399, |
| 4413 | t2UQADD8 = 4400, |
| 4414 | t2UQASX = 4401, |
| 4415 | t2UQSAX = 4402, |
| 4416 | t2UQSUB16 = 4403, |
| 4417 | t2UQSUB8 = 4404, |
| 4418 | t2USAD8 = 4405, |
| 4419 | t2USADA8 = 4406, |
| 4420 | t2USAT = 4407, |
| 4421 | t2USAT16 = 4408, |
| 4422 | t2USAX = 4409, |
| 4423 | t2USUB16 = 4410, |
| 4424 | t2USUB8 = 4411, |
| 4425 | t2UXTAB = 4412, |
| 4426 | t2UXTAB16 = 4413, |
| 4427 | t2UXTAH = 4414, |
| 4428 | t2UXTB = 4415, |
| 4429 | t2UXTB16 = 4416, |
| 4430 | t2UXTH = 4417, |
| 4431 | t2WLS = 4418, |
| 4432 | tADC = 4419, |
| 4433 | tADDhirr = 4420, |
| 4434 | tADDi3 = 4421, |
| 4435 | tADDi8 = 4422, |
| 4436 | tADDrSP = 4423, |
| 4437 | tADDrSPi = 4424, |
| 4438 | tADDrr = 4425, |
| 4439 | tADDspi = 4426, |
| 4440 | tADDspr = 4427, |
| 4441 | tADR = 4428, |
| 4442 | tAND = 4429, |
| 4443 | tASRri = 4430, |
| 4444 | tASRrr = 4431, |
| 4445 | tB = 4432, |
| 4446 | tBIC = 4433, |
| 4447 | tBKPT = 4434, |
| 4448 | tBL = 4435, |
| 4449 | tBLXNSr = 4436, |
| 4450 | tBLXi = 4437, |
| 4451 | tBLXr = 4438, |
| 4452 | tBX = 4439, |
| 4453 | tBXNS = 4440, |
| 4454 | tBcc = 4441, |
| 4455 | tCBNZ = 4442, |
| 4456 | tCBZ = 4443, |
| 4457 | tCMNz = 4444, |
| 4458 | tCMPhir = 4445, |
| 4459 | tCMPi8 = 4446, |
| 4460 | tCMPr = 4447, |
| 4461 | tCPS = 4448, |
| 4462 | tEOR = 4449, |
| 4463 | tHINT = 4450, |
| 4464 | tHLT = 4451, |
| 4465 | tInt_WIN_eh_sjlj_longjmp = 4452, |
| 4466 | tInt_eh_sjlj_longjmp = 4453, |
| 4467 | tInt_eh_sjlj_setjmp = 4454, |
| 4468 | tLDMIA = 4455, |
| 4469 | tLDRBi = 4456, |
| 4470 | tLDRBr = 4457, |
| 4471 | tLDRHi = 4458, |
| 4472 | tLDRHr = 4459, |
| 4473 | tLDRSB = 4460, |
| 4474 | tLDRSH = 4461, |
| 4475 | tLDRi = 4462, |
| 4476 | tLDRpci = 4463, |
| 4477 | tLDRr = 4464, |
| 4478 | tLDRspi = 4465, |
| 4479 | tLSLri = 4466, |
| 4480 | tLSLrr = 4467, |
| 4481 | tLSRri = 4468, |
| 4482 | tLSRrr = 4469, |
| 4483 | tMOVSr = 4470, |
| 4484 | tMOVi8 = 4471, |
| 4485 | tMOVr = 4472, |
| 4486 | tMUL = 4473, |
| 4487 | tMVN = 4474, |
| 4488 | tORR = 4475, |
| 4489 | tPICADD = 4476, |
| 4490 | tPOP = 4477, |
| 4491 | tPUSH = 4478, |
| 4492 | tREV = 4479, |
| 4493 | tREV16 = 4480, |
| 4494 | tREVSH = 4481, |
| 4495 | tROR = 4482, |
| 4496 | tRSB = 4483, |
| 4497 | tSBC = 4484, |
| 4498 | tSETEND = 4485, |
| 4499 | tSTMIA_UPD = 4486, |
| 4500 | tSTRBi = 4487, |
| 4501 | tSTRBr = 4488, |
| 4502 | tSTRHi = 4489, |
| 4503 | tSTRHr = 4490, |
| 4504 | tSTRi = 4491, |
| 4505 | tSTRr = 4492, |
| 4506 | tSTRspi = 4493, |
| 4507 | tSUBi3 = 4494, |
| 4508 | tSUBi8 = 4495, |
| 4509 | tSUBrr = 4496, |
| 4510 | tSUBspi = 4497, |
| 4511 | tSVC = 4498, |
| 4512 | tSXTB = 4499, |
| 4513 | tSXTH = 4500, |
| 4514 | tTRAP = 4501, |
| 4515 | tTST = 4502, |
| 4516 | tUDF = 4503, |
| 4517 | tUXTB = 4504, |
| 4518 | tUXTH = 4505, |
| 4519 | t__brkdiv0 = 4506, |
| 4520 | INSTRUCTION_LIST_END = 4507 |
| 4521 | }; |
| 4522 | |
| 4523 | } // end namespace llvm::ARM |
| 4524 | #endif // GET_INSTRINFO_ENUM |
| 4525 | |
| 4526 | #ifdef GET_INSTRINFO_SCHED_ENUM |
| 4527 | #undef GET_INSTRINFO_SCHED_ENUM |
| 4528 | namespace llvm::ARM::Sched { |
| 4529 | |
| 4530 | enum { |
| 4531 | NoInstrModel = 0, |
| 4532 | IIC_iALUi_WriteALU_ReadALU = 1, |
| 4533 | IIC_iALUr_WriteALU_ReadALU_ReadALU = 2, |
| 4534 | IIC_iALUsr_WriteALUsi_ReadALU = 3, |
| 4535 | IIC_iALUsr_WriteALUSsr_ReadALUsr = 4, |
| 4536 | IIC_iMOVsi_WriteALU = 5, |
| 4537 | IIC_Br_WriteBr = 6, |
| 4538 | IIC_Br_WriteBrL = 7, |
| 4539 | IIC_Br_WriteBrTbl = 8, |
| 4540 | IIC_iLoad_mBr = 9, |
| 4541 | IIC_iLoad_i = 10, |
| 4542 | IIC_iLoadiALU = 11, |
| 4543 | IIC_iLoad_d_r = 12, |
| 4544 | IIC_iMAC32_WriteMAC32_ReadMUL_ReadMUL_ReadMAC = 13, |
| 4545 | IIC_iCMOVi_WriteALU = 14, |
| 4546 | IIC_iMOVi_WriteALU = 15, |
| 4547 | IIC_iCMOVix2 = 16, |
| 4548 | IIC_iCMOVr_WriteALU = 17, |
| 4549 | IIC_iCMOVsr_WriteALU = 18, |
| 4550 | IIC_iMOVix2addpc = 19, |
| 4551 | IIC_iMOVix2ld = 20, |
| 4552 | IIC_iMOVix2 = 21, |
| 4553 | IIC_iMUL32_WriteMUL32_ReadMUL_ReadMUL = 22, |
| 4554 | IIC_iALUr_WriteALU_ReadALU = 23, |
| 4555 | IIC_iLoad_r = 24, |
| 4556 | IIC_iLoad_bh_r = 25, |
| 4557 | IIC_iStore_r = 26, |
| 4558 | IIC_iStore_bh_r = 27, |
| 4559 | IIC_iMAC64_WriteMAC64Lo_WriteMAC64Hi_ReadMUL_ReadMUL_ReadMAC_ReadMAC = 28, |
| 4560 | IIC_iMUL64_WriteMUL64Lo_WriteMUL64Hi_ReadMUL_ReadMUL = 29, |
| 4561 | IIC_iStore_d_r = 30, |
| 4562 | IIC_iStore_ru = 31, |
| 4563 | IIC_Br = 32, |
| 4564 | IIC_VMOVImm = 33, |
| 4565 | IIC_fpUNA64 = 34, |
| 4566 | IIC_fpUNA16 = 35, |
| 4567 | IIC_fpUNA32 = 36, |
| 4568 | IIC_iALUsi_WriteALUsi_ReadALUsr = 37, |
| 4569 | IIC_iCMOVsi_WriteALU = 38, |
| 4570 | IIC_iALUsi_WriteALUsi_ReadALU = 39, |
| 4571 | IIC_iStore_ru_WriteST = 40, |
| 4572 | IIC_iALUr_WriteALU = 41, |
| 4573 | IIC_iALUi_WriteALU = 42, |
| 4574 | IIC_iLoad_mu = 43, |
| 4575 | IIC_iPop_Br_WriteBrL = 44, |
| 4576 | IIC_iALUsr_WriteALUsr_ReadALUsr = 45, |
| 4577 | IIC_iBITi_WriteALU_ReadALU = 46, |
| 4578 | IIC_iBITr_WriteALU_ReadALU_ReadALU = 47, |
| 4579 | IIC_iBITsr_WriteALUsi_ReadALU = 48, |
| 4580 | IIC_iBITsr_WriteALUsr_ReadALUsr = 49, |
| 4581 | IIC_VDOTPROD = 50, |
| 4582 | IIC_iUNAsi = 51, |
| 4583 | WriteBrL = 52, |
| 4584 | WriteBr = 53, |
| 4585 | IIC_iUNAr_WriteALU = 54, |
| 4586 | IIC_iCMPi_WriteCMP_ReadALU = 55, |
| 4587 | IIC_iCMPr_WriteCMP_ReadALU_ReadALU = 56, |
| 4588 | IIC_iCMPsr_WriteCMPsi_ReadALU = 57, |
| 4589 | IIC_iCMPsr_WriteCMPsr_ReadALU = 58, |
| 4590 | IIC_fpSTAT = 59, |
| 4591 | IIC_iLoad_m = 60, |
| 4592 | IIC_iLoad_bh_ru = 61, |
| 4593 | IIC_iLoad_bh_iu = 62, |
| 4594 | IIC_iLoad_bh_si = 63, |
| 4595 | IIC_iLoad_d_ru = 64, |
| 4596 | IIC_iLoad_ru = 65, |
| 4597 | IIC_iLoad_iu = 66, |
| 4598 | IIC_iLoad_si = 67, |
| 4599 | IIC_iMOVr_WriteALU = 68, |
| 4600 | IIC_iMOVsr_WriteALU = 69, |
| 4601 | IIC_iMVNi_WriteALU = 70, |
| 4602 | IIC_iMVNr_WriteALU = 71, |
| 4603 | IIC_iMVNsr_WriteALU = 72, |
| 4604 | IIC_iBITsi_WriteALUsi_ReadALU = 73, |
| 4605 | IIC_Preload_WritePreLd = 74, |
| 4606 | IIC_iDIV_WriteDIV = 75, |
| 4607 | IIC_iMAC16_WriteMAC16_ReadMUL_ReadMUL_ReadMAC = 76, |
| 4608 | WriteMAC32_ReadMUL_ReadMUL_ReadMAC = 77, |
| 4609 | WriteMAC64Lo_WriteMAC64Hi_ReadMUL_ReadMUL_ReadMAC_ReadMAC = 78, |
| 4610 | WriteMUL64Lo_WriteMUL64Hi_ReadMUL_ReadMUL = 79, |
| 4611 | WriteMUL32_ReadMUL_ReadMUL = 80, |
| 4612 | IIC_iMUL16_WriteMUL16_ReadMUL_ReadMUL = 81, |
| 4613 | IIC_iStore_m = 82, |
| 4614 | IIC_iStore_mu = 83, |
| 4615 | IIC_iStore_bh_ru = 84, |
| 4616 | IIC_iStore_bh_iu = 85, |
| 4617 | IIC_iStore_bh_si = 86, |
| 4618 | IIC_iStore_d_ru = 87, |
| 4619 | IIC_iStore_iu = 88, |
| 4620 | IIC_iStore_si = 89, |
| 4621 | IIC_iEXTAr_WriteALUsr = 90, |
| 4622 | IIC_iEXTr_WriteALUsi = 91, |
| 4623 | IIC_iTSTi_WriteCMP_ReadALU = 92, |
| 4624 | IIC_iTSTr_WriteCMP_ReadALU_ReadALU = 93, |
| 4625 | IIC_iTSTsr_WriteCMPsi_ReadALU = 94, |
| 4626 | IIC_iTSTsr_WriteCMPsr_ReadALU = 95, |
| 4627 | IIC_iMUL64_WriteMAC64Lo_WriteMAC64Hi_ReadMUL_ReadMUL = 96, |
| 4628 | WriteALU_ReadALU_ReadALU = 97, |
| 4629 | IIC_VABAD = 98, |
| 4630 | IIC_VABAQ = 99, |
| 4631 | IIC_VSUBi4Q = 100, |
| 4632 | IIC_VBIND = 101, |
| 4633 | IIC_VBINQ = 102, |
| 4634 | IIC_VSUBi4D = 103, |
| 4635 | IIC_VUNAD = 104, |
| 4636 | IIC_VUNAQ = 105, |
| 4637 | IIC_VUNAiQ = 106, |
| 4638 | IIC_VUNAiD = 107, |
| 4639 | IIC_fpALU64_WriteFPALU64 = 108, |
| 4640 | IIC_fpALU16_WriteFPALU32 = 109, |
| 4641 | IIC_VBINi4D = 110, |
| 4642 | IIC_VSHLiD = 111, |
| 4643 | IIC_fpALU32_WriteFPALU32 = 112, |
| 4644 | IIC_VSUBiD = 113, |
| 4645 | IIC_VBINiQ = 114, |
| 4646 | IIC_VBINiD = 115, |
| 4647 | IIC_VMACD = 116, |
| 4648 | IIC_VMACQ = 117, |
| 4649 | IIC_VCNTiQ = 118, |
| 4650 | IIC_VCNTiD = 119, |
| 4651 | IIC_fpCMP64 = 120, |
| 4652 | IIC_fpCMP16 = 121, |
| 4653 | IIC_fpCMP32 = 122, |
| 4654 | WriteFPCVT = 123, |
| 4655 | IIC_fpCVTSH_WriteFPCVT = 124, |
| 4656 | IIC_fpCVTHS_WriteFPCVT = 125, |
| 4657 | IIC_fpCVTDS_WriteFPCVT = 126, |
| 4658 | IIC_fpCVTSD_WriteFPCVT = 127, |
| 4659 | IIC_fpDIV64_WriteFPDIV64 = 128, |
| 4660 | IIC_fpDIV16_WriteFPDIV32 = 129, |
| 4661 | IIC_fpDIV32_WriteFPDIV32 = 130, |
| 4662 | IIC_VMOVIS = 131, |
| 4663 | IIC_VMOVD = 132, |
| 4664 | IIC_VMOVQ = 133, |
| 4665 | IIC_VEXTD = 134, |
| 4666 | IIC_VEXTQ = 135, |
| 4667 | IIC_fpFMAC64_WriteFPMAC64_ReadFPMAC_ReadFPMUL_ReadFPMUL = 136, |
| 4668 | IIC_fpFMAC16_WriteFPMAC32_ReadFPMAC_ReadFPMUL_ReadFPMUL = 137, |
| 4669 | IIC_fpFMAC32_WriteFPMAC32_ReadFPMAC_ReadFPMUL_ReadFPMUL = 138, |
| 4670 | IIC_VFMACD = 139, |
| 4671 | IIC_VFMACQ = 140, |
| 4672 | IIC_VMOVSI = 141, |
| 4673 | IIC_VBINi4Q = 142, |
| 4674 | IIC_fpCVTDI = 143, |
| 4675 | IIC_VLD1dup_WriteVLD2 = 144, |
| 4676 | IIC_VLD1dupu = 145, |
| 4677 | IIC_VLD1dup = 146, |
| 4678 | IIC_VLD1dupu_WriteVLD1 = 147, |
| 4679 | IIC_VLD1ln = 148, |
| 4680 | IIC_VLD1lnu_WriteVLD1 = 149, |
| 4681 | IIC_VLD1ln_WriteVLD1 = 150, |
| 4682 | IIC_VLD1_WriteVLD1 = 151, |
| 4683 | IIC_VLD1x4_WriteVLD4 = 152, |
| 4684 | IIC_VLD1x2u_WriteVLD4 = 153, |
| 4685 | IIC_VLD1x3_WriteVLD3 = 154, |
| 4686 | IIC_VLD1x2u_WriteVLD3 = 155, |
| 4687 | IIC_VLD1u_WriteVLD1 = 156, |
| 4688 | IIC_VLD1x2_WriteVLD2 = 157, |
| 4689 | IIC_VLD1x2u_WriteVLD2 = 158, |
| 4690 | IIC_VLD2dup = 159, |
| 4691 | IIC_VLD2dupu_WriteVLD1 = 160, |
| 4692 | IIC_VLD2dup_WriteVLD2 = 161, |
| 4693 | IIC_VLD2ln_WriteVLD1 = 162, |
| 4694 | IIC_VLD2lnu_WriteVLD1 = 163, |
| 4695 | IIC_VLD2lnu = 164, |
| 4696 | IIC_VLD2_WriteVLD2 = 165, |
| 4697 | IIC_VLD2u_WriteVLD2 = 166, |
| 4698 | IIC_VLD2x2_WriteVLD4 = 167, |
| 4699 | IIC_VLD2x2u_WriteVLD4 = 168, |
| 4700 | IIC_VLD3dup_WriteVLD2 = 169, |
| 4701 | IIC_VLD3dupu_WriteVLD2 = 170, |
| 4702 | IIC_VLD3ln_WriteVLD2 = 171, |
| 4703 | IIC_VLD3lnu_WriteVLD2 = 172, |
| 4704 | IIC_VLD3_WriteVLD3 = 173, |
| 4705 | IIC_VLD3u_WriteVLD3 = 174, |
| 4706 | IIC_VLD4dup = 175, |
| 4707 | IIC_VLD4dup_WriteVLD2 = 176, |
| 4708 | IIC_VLD4dupu_WriteVLD2 = 177, |
| 4709 | IIC_VLD4ln_WriteVLD2 = 178, |
| 4710 | IIC_VLD4lnu_WriteVLD2 = 179, |
| 4711 | IIC_VLD4lnu = 180, |
| 4712 | IIC_VLD4_WriteVLD4 = 181, |
| 4713 | IIC_VLD4u_WriteVLD4 = 182, |
| 4714 | IIC_fpLoad_mu = 183, |
| 4715 | IIC_fpLoad_m = 184, |
| 4716 | IIC_fpLoad64 = 185, |
| 4717 | IIC_fpLoad16 = 186, |
| 4718 | IIC_fpLoad32 = 187, |
| 4719 | IIC_fpMAC64_WriteFPMAC64_ReadFPMAC_ReadFPMUL_ReadFPMUL = 188, |
| 4720 | IIC_fpMAC16 = 189, |
| 4721 | IIC_VMACi32D = 190, |
| 4722 | IIC_VMACi16D = 191, |
| 4723 | IIC_fpMAC32_WriteFPMAC32_ReadFPMAC_ReadFPMUL_ReadFPMUL = 192, |
| 4724 | IIC_VMACi32Q = 193, |
| 4725 | IIC_VMACi16Q = 194, |
| 4726 | IIC_fpMOVID_WriteFPMOV = 195, |
| 4727 | IIC_fpMOVIS_WriteFPMOV = 196, |
| 4728 | IIC_VQUNAiD = 197, |
| 4729 | IIC_VMOVN = 198, |
| 4730 | IIC_fpMOVSI_WriteFPMOV = 199, |
| 4731 | IIC_fpMOVDI_WriteFPMOV = 200, |
| 4732 | IIC_fpMUL64_WriteFPMUL64_ReadFPMUL_ReadFPMUL = 201, |
| 4733 | IIC_fpMUL16_WriteFPMUL32_ReadFPMUL_ReadFPMUL = 202, |
| 4734 | IIC_VMULi16D = 203, |
| 4735 | IIC_VMULi32D = 204, |
| 4736 | IIC_fpMUL32_WriteFPMUL32_ReadFPMUL_ReadFPMUL = 205, |
| 4737 | IIC_VFMULD = 206, |
| 4738 | IIC_VFMULQ = 207, |
| 4739 | IIC_VMULi16Q = 208, |
| 4740 | IIC_VMULi32Q = 209, |
| 4741 | IIC_VSHLiQ = 210, |
| 4742 | IIC_VPALiQ = 211, |
| 4743 | IIC_VPALiD = 212, |
| 4744 | IIC_VPBIND = 213, |
| 4745 | IIC_VQUNAiQ = 214, |
| 4746 | IIC_VSHLi4Q = 215, |
| 4747 | IIC_VSHLi4D = 216, |
| 4748 | IIC_VRECSD = 217, |
| 4749 | IIC_VRECSQ = 218, |
| 4750 | IIC_VMOVISL = 219, |
| 4751 | IIC_fpCVTID_WriteFPCVT = 220, |
| 4752 | IIC_fpCVTIH_WriteFPCVT = 221, |
| 4753 | IIC_fpCVTIS_WriteFPCVT = 222, |
| 4754 | IIC_fpSQRT64_WriteFPSQRT64 = 223, |
| 4755 | IIC_fpSQRT16 = 224, |
| 4756 | IIC_fpSQRT32_WriteFPSQRT32 = 225, |
| 4757 | IIC_VST1ln_WriteVST1 = 226, |
| 4758 | IIC_VST1lnu_WriteVST1 = 227, |
| 4759 | IIC_VST1_WriteVST1 = 228, |
| 4760 | IIC_VST1x4_WriteVST4 = 229, |
| 4761 | IIC_VST1x4u_WriteVST4 = 230, |
| 4762 | IIC_VLD1x4u_WriteVST4 = 231, |
| 4763 | IIC_VST1x3_WriteVST3 = 232, |
| 4764 | IIC_VST1x3u_WriteVST3 = 233, |
| 4765 | IIC_VLD1x3u_WriteVST3 = 234, |
| 4766 | IIC_VLD1u_WriteVST1 = 235, |
| 4767 | IIC_VST1x2_WriteVST2 = 236, |
| 4768 | IIC_VLD1x2u_WriteVST2 = 237, |
| 4769 | IIC_VST2ln_WriteVST1 = 238, |
| 4770 | IIC_VST2lnu_WriteVST1 = 239, |
| 4771 | IIC_VST2lnu = 240, |
| 4772 | IIC_VST2 = 241, |
| 4773 | IIC_VLD1u_WriteVST2 = 242, |
| 4774 | IIC_VST2_WriteVST2 = 243, |
| 4775 | IIC_VST2x2_WriteVST4 = 244, |
| 4776 | IIC_VST2x2u_WriteVST4 = 245, |
| 4777 | IIC_VLD1u_WriteVST4 = 246, |
| 4778 | IIC_VST3ln_WriteVST2 = 247, |
| 4779 | IIC_VST3lnu_WriteVST2 = 248, |
| 4780 | IIC_VST3lnu = 249, |
| 4781 | IIC_VST3ln = 250, |
| 4782 | IIC_VST3_WriteVST3 = 251, |
| 4783 | IIC_VST3u_WriteVST3 = 252, |
| 4784 | IIC_VST4ln_WriteVST2 = 253, |
| 4785 | IIC_VST4lnu_WriteVST2 = 254, |
| 4786 | IIC_VST4lnu = 255, |
| 4787 | IIC_VST4_WriteVST4 = 256, |
| 4788 | IIC_VST4u_WriteVST4 = 257, |
| 4789 | IIC_fpStore_mu = 258, |
| 4790 | IIC_fpStore_m = 259, |
| 4791 | IIC_fpStore64 = 260, |
| 4792 | IIC_fpStore16 = 261, |
| 4793 | IIC_fpStore32 = 262, |
| 4794 | IIC_VSUBiQ = 263, |
| 4795 | IIC_VTB1 = 264, |
| 4796 | IIC_VTB2 = 265, |
| 4797 | IIC_VTB3 = 266, |
| 4798 | IIC_VTB4 = 267, |
| 4799 | IIC_VTBX1 = 268, |
| 4800 | IIC_VTBX2 = 269, |
| 4801 | IIC_VTBX3 = 270, |
| 4802 | IIC_VTBX4 = 271, |
| 4803 | IIC_fpCVTDI_WriteFPCVT = 272, |
| 4804 | IIC_fpCVTHI_WriteFPCVT = 273, |
| 4805 | IIC_fpCVTSI_WriteFPCVT = 274, |
| 4806 | IIC_VPERMD = 275, |
| 4807 | IIC_VPERMQ = 276, |
| 4808 | IIC_VPERMQ3 = 277, |
| 4809 | IIC_iUNAsi_WriteALU = 278, |
| 4810 | IIC_iBITi_WriteALU = 279, |
| 4811 | IIC_iCMPsi_WriteCMPsi_ReadALU_ReadALU = 280, |
| 4812 | IIC_iCMPi_WriteCMP = 281, |
| 4813 | IIC_iCMPr_WriteCMP = 282, |
| 4814 | IIC_iCMPsi_WriteCMPsi = 283, |
| 4815 | IIC_iALUx = 284, |
| 4816 | WriteLd = 285, |
| 4817 | IIC_iLoad_bh_i_WriteLd = 286, |
| 4818 | IIC_iLoad_bh_iu_WriteLd = 287, |
| 4819 | IIC_iLoad_bh_si_WriteLd = 288, |
| 4820 | IIC_iLoad_d_ru_WriteLd = 289, |
| 4821 | IIC_iLoad_d_i_WriteLd = 290, |
| 4822 | IIC_iLoad_i_WriteLd = 291, |
| 4823 | IIC_iLoad_iu_WriteLd = 292, |
| 4824 | IIC_iLoad_si_WriteLd = 293, |
| 4825 | IIC_iMVNsi_WriteALU = 294, |
| 4826 | IIC_iALUsir_WriteALUsi_ReadALU = 295, |
| 4827 | IIC_iMUL16_WriteMAC16_ReadMUL_ReadMUL_ReadMAC = 296, |
| 4828 | IIC_iMAC32 = 297, |
| 4829 | WriteALU = 298, |
| 4830 | WriteST = 299, |
| 4831 | IIC_iStore_bh_i_WriteST = 300, |
| 4832 | IIC_iStore_bh_iu_WriteST = 301, |
| 4833 | IIC_iStore_bh_si_WriteST = 302, |
| 4834 | IIC_iStore_d_ru_WriteST = 303, |
| 4835 | IIC_iStore_d_r_WriteST = 304, |
| 4836 | IIC_iStore_iu_WriteST = 305, |
| 4837 | IIC_iStore_i_WriteST = 306, |
| 4838 | IIC_iStore_si_WriteST = 307, |
| 4839 | IIC_iEXTAsr_WriteALU_ReadALU = 308, |
| 4840 | IIC_iEXTr_WriteALU_ReadALU = 309, |
| 4841 | IIC_iTSTi_WriteCMP = 310, |
| 4842 | IIC_iTSTr_WriteCMP = 311, |
| 4843 | IIC_iTSTsi_WriteCMPsi = 312, |
| 4844 | IIC_iBITr_WriteALU = 313, |
| 4845 | IIC_iLoad_bh_r_WriteLd = 314, |
| 4846 | IIC_iLoad_r_WriteLd = 315, |
| 4847 | IIC_iPop_WriteLd = 316, |
| 4848 | IIC_iStore_m_WriteST = 317, |
| 4849 | IIC_iStore_bh_r_WriteST = 318, |
| 4850 | IIC_iStore_r_WriteST = 319, |
| 4851 | IIC_iTSTr_WriteALU = 320, |
| 4852 | ANDri_ORRri_EORri_BICri = 321, |
| 4853 | ANDrr_ORRrr_EORrr_BICrr = 322, |
| 4854 | ANDrsi_ORRrsi_EORrsi_BICrsi = 323, |
| 4855 | ANDrsr_ORRrsr_EORrsr_BICrsr = 324, |
| 4856 | MOVsr_MOVsi = 325, |
| 4857 | MVNsr = 326, |
| 4858 | MOVCCsi_MOVCCsr = 327, |
| 4859 | MVNr = 328, |
| 4860 | MOVCCi32imm = 329, |
| 4861 | MOVi32imm = 330, |
| 4862 | MOV_ga_pcrel = 331, |
| 4863 | MOV_ga_pcrel_ldr = 332, |
| 4864 | SEL = 333, |
| 4865 | BFC_BFI_UBFX_SBFX = 334, |
| 4866 | MULv5_MUL_SMMUL_SMMULR = 335, |
| 4867 | MLAv5_MLA_MLS_SMMLA_SMMLAR_SMMLS_SMMLSR = 336, |
| 4868 | SMULLv5_SMULL_UMULLv5 = 337, |
| 4869 | UMULL = 338, |
| 4870 | SMLAL_UMLALv5_UMLAL_UMAAL_SMLALv5_SMLALBB_SMLALBT_SMLALTB_SMLALTT = 339, |
| 4871 | SMLAD_SMLADX_SMLSD_SMLSDX = 340, |
| 4872 | SMLALD_SMLSLD = 341, |
| 4873 | SMLALDX_SMLSLDX = 342, |
| 4874 | SMUAD_SMUADX_SMUSD_SMUSDX = 343, |
| 4875 | SMULBB_SMULBT_SMULTB_SMULTT_SMULWB_SMULWT = 344, |
| 4876 | SMLABB_SMLABT_SMLATB_SMLATT_SMLAWB_SMLAWT = 345, |
| 4877 | LDRi12_PICLDR = 346, |
| 4878 | LDRrs = 347, |
| 4879 | LDRBi12_PICLDRH_PICLDRB_PICLDRSH_PICLDRSB_LDRH_LDRSH_LDRSB = 348, |
| 4880 | LDRHTii_LDRSHTii_LDRSBTii = 349, |
| 4881 | LDRHTi_LDRHTr_LDRH_POST_LDRH_PRE_LDRSHTi_LDRSHTr_LDRSH_POST_LDRSH_PRE_LDRSBTi_LDRSBTr_LDRSB_POST_LDRSB_PRE = 350, |
| 4882 | SXTB_SXTB16_SXTH_UXTB_UXTB16_UXTH = 351, |
| 4883 | t2SXTB_t2SXTB16_t2SXTH_t2UXTB_t2UXTB16_t2UXTH = 352, |
| 4884 | t2MOVCCi32imm = 353, |
| 4885 | t2MOVi32imm = 354, |
| 4886 | t2MOV_ga_pcrel = 355, |
| 4887 | t2MOVi16_ga_pcrel = 356, |
| 4888 | t2SEL = 357, |
| 4889 | t2BFC_t2UBFX_t2SBFX = 358, |
| 4890 | t2BFI = 359, |
| 4891 | QADD_QADD16_QADD8_QSUB_QSUB16_QSUB8_QDADD_QDSUB_QASX_QSAX_UQADD8_UQADD16_UQSUB8_UQSUB16_UQASX_UQSAX = 360, |
| 4892 | SSAT_SSAT16_USAT_USAT16_t2QADD_t2QADD16_t2QADD8_t2QSUB_t2QSUB16_t2QSUB8_t2QDADD_t2QDSUB_t2QASX_t2QSAX_t2UQADD8_t2UQADD16_t2UQSUB8_t2UQSUB16_t2UQASX_t2UQSAX = 361, |
| 4893 | t2SSAT_t2SSAT16_t2USAT_t2USAT16 = 362, |
| 4894 | SADD8_SADD16_SSUB8_SSUB16_SASX_SSAX_UADD8_UADD16_USUB8_USUB16_UASX_USAX = 363, |
| 4895 | t2SADD8_t2SADD16_t2SSUB8_t2SSUB16_t2SASX_t2SSAX_t2UADD8_t2UADD16_t2USUB8_t2USUB16_t2UASX_t2USAX = 364, |
| 4896 | SHADD8_SHADD16_SHSUB8_SHSUB16_SHASX_SHSAX_UHADD8_UHADD16_UHSUB8_UHSUB16_UHASX_UHSAX = 365, |
| 4897 | SXTAB_SXTAB16_SXTAH_UXTAB_UXTAB16_UXTAH = 366, |
| 4898 | t2SHADD8_t2SHADD16_t2SHSUB8_t2SHSUB16_t2SHASX_t2SHSAX_t2UHADD8_t2UHADD16_t2UHSUB8_t2UHSUB16_t2UHASX_t2UHSAX = 367, |
| 4899 | t2SXTAB_t2SXTAB16_t2SXTAH_t2UXTAB_t2UXTAB16_t2UXTAH = 368, |
| 4900 | USAD8 = 369, |
| 4901 | USADA8 = 370, |
| 4902 | SMUSD_SMUSDX = 371, |
| 4903 | t2MUL_t2SMMUL_t2SMMULR = 372, |
| 4904 | t2SMULBB_t2SMULBT_t2SMULTB_t2SMULTT_t2SMULWB_t2SMULWT = 373, |
| 4905 | t2SMUSD_t2SMUSDX = 374, |
| 4906 | t2MLA_t2MLS_t2SMMLA_t2SMMLAR_t2SMMLS_t2SMMLSR = 375, |
| 4907 | t2SMUAD_t2SMUADX = 376, |
| 4908 | SMLSD_SMLSDX = 377, |
| 4909 | t2SMLABB_t2SMLABT_t2SMLATB_t2SMLATT_t2SMLAWB_t2SMLAWT = 378, |
| 4910 | t2SMLSD_t2SMLSDX = 379, |
| 4911 | t2SMLAD_t2SMLADX = 380, |
| 4912 | SMULL = 381, |
| 4913 | t2SMULL_t2UMULL = 382, |
| 4914 | t2SMLAL_t2SMLALBB_t2SMLALBT_t2SMLALD_t2SMLALDX_t2SMLALTB_t2SMLALTT_t2UMLAL_t2SMLSLD_t2SMLSLDX_t2UMAAL = 383, |
| 4915 | SDIV_UDIV_t2SDIV_t2UDIV = 384, |
| 4916 | LDRi12 = 385, |
| 4917 | LDRBi12 = 386, |
| 4918 | LDRBrs = 387, |
| 4919 | t2LDRpci_pic = 388, |
| 4920 | t2LDRi12_t2LDRi8_t2LDRpci_tLDRi_tLDRpci_tLDRspi = 389, |
| 4921 | t2LDRs = 390, |
| 4922 | t2LDRBi12_t2LDRBi8_t2LDRBpci_t2LDRHi12_t2LDRHi8_t2LDRHpci_tLDRBi_tLDRHi = 391, |
| 4923 | t2LDRBs_t2LDRHs = 392, |
| 4924 | LDREX_LDREXB_LDREXD_LDREXH_tLDRpci_pic = 393, |
| 4925 | tLDRBr_tLDRHr = 394, |
| 4926 | tLDRr = 395, |
| 4927 | LDRH_PICLDRB_PICLDRH = 396, |
| 4928 | LDRcp = 397, |
| 4929 | t2LDRSBpcrel_t2LDRSHpcrel = 398, |
| 4930 | t2LDRSBi12_t2LDRSBi8_t2LDRSBpci_t2LDRSHi12_t2LDRSHi8_t2LDRSHpci = 399, |
| 4931 | t2LDRSBs_t2LDRSHs = 400, |
| 4932 | tLDRSB_tLDRSH = 401, |
| 4933 | LDRBT_POST_IMM_LDRBT_POST_REG_LDRB_POST_REG_LDRB_PRE_REG = 402, |
| 4934 | LDRB_POST_IMM_LDRB_PRE_IMM = 403, |
| 4935 | LDRT_POST_IMM_LDRT_POST_REG_LDR_POST_REG_LDR_PRE_REG = 404, |
| 4936 | LDR_POST_IMM_LDR_PRE_IMM = 405, |
| 4937 | LDRH_POST_LDRH_PRE_LDRHTi_LDRHTr = 406, |
| 4938 | LDRHTii = 407, |
| 4939 | t2LDRB_POST_imm_t2LDRB_PRE_imm_t2LDRH_POST_imm_t2LDRH_PRE_imm_t2LDR_POST_imm_t2LDR_PRE_imm = 408, |
| 4940 | t2LDRB_POST_t2LDRB_PRE_t2LDRH_POST_t2LDRH_PRE = 409, |
| 4941 | t2LDR_POST_t2LDR_PRE = 410, |
| 4942 | t2LDRBT_t2LDRHT = 411, |
| 4943 | t2LDRT = 412, |
| 4944 | t2LDRSB_POST_imm_t2LDRSB_PRE_imm_t2LDRSH_POST_imm_t2LDRSH_PRE_imm = 413, |
| 4945 | t2LDRSB_POST_t2LDRSB_PRE_t2LDRSH_POST_t2LDRSH_PRE = 414, |
| 4946 | t2LDRSBT_t2LDRSHT = 415, |
| 4947 | t2LDRDi8 = 416, |
| 4948 | LDRD = 417, |
| 4949 | LDRD_POST_LDRD_PRE = 418, |
| 4950 | t2LDRD_POST_t2LDRD_PRE = 419, |
| 4951 | LDMDA_LDMDB_LDMIA_LDMIB_t2LDMDB_t2LDMIA_sysLDMDA_sysLDMDB_sysLDMIA_sysLDMIB_tLDMIA = 420, |
| 4952 | LDMDA_UPD_LDMDB_UPD_LDMIA_UPD_LDMIB_UPD_tLDMIA_UPD_sysLDMDA_UPD_sysLDMDB_UPD_sysLDMIA_UPD_sysLDMIB_UPD_t2LDMDB_UPD_t2LDMIA_UPD = 421, |
| 4953 | LDMIA_RET_t2LDMIA_RET = 422, |
| 4954 | tPOP_RET = 423, |
| 4955 | tPOP = 424, |
| 4956 | PICSTR_STRi12 = 425, |
| 4957 | PICSTRB_PICSTRH_STRBi12_STRH = 426, |
| 4958 | STRrs = 427, |
| 4959 | STRBrs = 428, |
| 4960 | STREX_STREXB_STREXD_STREXH = 429, |
| 4961 | t2STRi12_t2STRi8_tSTRi_tSTRspi = 430, |
| 4962 | t2STRs = 431, |
| 4963 | t2STRBi12_t2STRBi8_t2STRHi12_t2STRHi8_tSTRBi_tSTRHi = 432, |
| 4964 | t2STRBs_t2STRHs = 433, |
| 4965 | tSTRBr_tSTRHr = 434, |
| 4966 | tSTRr = 435, |
| 4967 | STRBT_POST_IMM_STRBT_POST_REG_STRB_POST_REG_STRB_PRE_REG_STRH_POST_STRH_PRE_STRHTi_STRHTr = 436, |
| 4968 | STRB_POST_IMM_STRB_PRE_IMM = 437, |
| 4969 | STRT_POST_IMM_STRT_POST_REG_STR_POST_REG_STR_PRE_REG_STRi_preidx_STRr_preidx_STRBi_preidx_STRBr_preidx_STRH_preidx = 438, |
| 4970 | STR_POST_IMM_STR_PRE_IMM = 439, |
| 4971 | STRBT_POST_STRT_POST_t2STR_POST_imm_t2STR_PRE_imm_t2STRB_POST_imm_t2STRB_PRE_imm_t2STRH_POST_imm_t2STRH_PRE_imm = 440, |
| 4972 | t2STR_POST_t2STR_PRE_t2STRH_PRE = 441, |
| 4973 | t2STRB_POST_t2STRB_PRE_t2STRH_POST = 442, |
| 4974 | t2STR_preidx_t2STRB_preidx_t2STRH_preidx = 443, |
| 4975 | t2STRBT_t2STRHT = 444, |
| 4976 | t2STRT = 445, |
| 4977 | STRD = 446, |
| 4978 | t2STRDi8 = 447, |
| 4979 | t2STRD_POST_t2STRD_PRE = 448, |
| 4980 | STRD_POST_STRD_PRE = 449, |
| 4981 | STMDA_STMDB_STMIA_STMIB_sysSTMDA_sysSTMDB_sysSTMIA_sysSTMIB_t2STMDB_t2STMIA = 450, |
| 4982 | STMDA_UPD_STMDB_UPD_STMIA_UPD_STMIB_UPD_sysSTMDA_UPD_sysSTMDB_UPD_sysSTMIA_UPD_sysSTMIB_UPD_t2STMDB_UPD_t2STMIA_UPD_tSTMIA_UPD = 451, |
| 4983 | tPUSH = 452, |
| 4984 | LDRLIT_ga_abs_tLDRLIT_ga_abs = 453, |
| 4985 | LDRLIT_ga_pcrel_tLDRLIT_ga_pcrel = 454, |
| 4986 | LDRLIT_ga_pcrel_ldr = 455, |
| 4987 | t2IT = 456, |
| 4988 | ITasm = 457, |
| 4989 | VADDv16i8_VADDv2i64_VADDv4i32_VADDv8i16_VANDq_VBICq_VEORq_VORNq_VORRq_VBIFq_VBITq_VBSLq_VBSPq = 458, |
| 4990 | VADDv1i64_VADDv2i32_VADDv4i16_VADDv8i8_VANDd_VBICd_VEORd_VORNd_VORRd_VBIFd_VBITd_VBSLd_VBSPd = 459, |
| 4991 | VSUBv16i8_VSUBv2i64_VSUBv4i32_VSUBv8i16 = 460, |
| 4992 | VSUBv1i64_VSUBv2i32_VSUBv4i16_VSUBv8i8_VADDWsv2i64_VADDWsv4i32_VADDWsv8i16_VADDWuv2i64_VADDWuv4i32_VADDWuv8i16_VSUBWsv2i64_VSUBWsv4i32_VSUBWsv8i16_VSUBWuv2i64_VSUBWuv4i32_VSUBWuv8i16 = 461, |
| 4993 | VNEGf32q = 462, |
| 4994 | VNEGfd = 463, |
| 4995 | VNEGs16d_VNEGs32d_VNEGs8d_VADDLsv2i64_VADDLsv4i32_VADDLsv8i16_VADDLuv2i64_VADDLuv4i32_VADDLuv8i16_VSUBLsv2i64_VSUBLsv4i32_VSUBLsv8i16_VSUBLuv2i64_VSUBLuv4i32_VSUBLuv8i16_VPADDi16_VPADDi32_VPADDi8_VPADDLsv16i8_VPADDLsv2i32_VPADDLsv4i16_VPADDLsv4i32_VPADDLsv8i16_VPADDLsv8i8_VPADDLuv16i8_VPADDLuv2i32_VPADDLuv4i16_VPADDLuv4i32_VPADDLuv8i16_VPADDLuv8i8_VSHLLi16_VSHLLi32_VSHLLi8_VSHLLsv2i64_VSHLLsv4i32_VSHLLsv8i16_VSHLLuv2i64_VSHLLuv4i32_VSHLLuv8i16_VSHLiv16i8_VSHLiv1i64_VSHLiv2i32_VSHLiv2i64_VSHLiv4i16_VSHLiv4i32_VSHLiv8i16_VSHLiv8i8_VSHLsv1i64_VSHLsv2i32_VSHLsv4i16_VSHLsv8i8_VSHLuv1i64_VSHLuv2i32_VSHLuv4i16_VSHLuv8i8_VSHRsv16i8_VSHRsv1i64_VSHRsv2i32_VSHRsv2i64_VSHRsv4i16_VSHRsv4i32_VSHRsv8i16_VSHRsv8i8_VSHRuv16i8_VSHRuv1i64_VSHRuv2i32_VSHRuv2i64_VSHRuv4i16_VSHRuv4i32_VSHRuv8i16_VSHRuv8i8_VSLIv1i64_VSLIv2i32_VSLIv4i16_VSLIv8i8_VSRIv1i64_VSRIv2i32_VSRIv4i16_VSRIv8i8 = 464, |
| 4996 | VNEGs16q_VNEGs32q_VNEGs8q_VSHLsv16i8_VSHLsv2i64_VSHLsv4i32_VSHLsv8i16_VSHLuv16i8_VSHLuv2i64_VSHLuv4i32_VSHLuv8i16_VSLIv16i8_VSLIv2i64_VSLIv4i32_VSLIv8i16_VSRIv16i8_VSRIv2i64_VSRIv4i32_VSRIv8i16 = 465, |
| 4997 | VHADDsv16i8_VHADDsv4i32_VHADDsv8i16_VHADDuv16i8_VHADDuv4i32_VHADDuv8i16_VRHADDsv16i8_VRHADDsv4i32_VRHADDsv8i16_VRHADDuv16i8_VRHADDuv4i32_VRHADDuv8i16_VTSTv16i8_VTSTv4i32_VTSTv8i16 = 466, |
| 4998 | VHADDsv2i32_VHADDsv4i16_VHADDsv8i8_VHADDuv2i32_VHADDuv4i16_VHADDuv8i8_VRHADDsv2i32_VRHADDsv4i16_VRHADDsv8i8_VRHADDuv2i32_VRHADDuv4i16_VRHADDuv8i8_VTSTv2i32_VTSTv4i16_VTSTv8i8 = 467, |
| 4999 | VHSUBsv16i8_VHSUBsv4i32_VHSUBsv8i16_VHSUBuv16i8_VHSUBuv4i32_VHSUBuv8i16 = 468, |
| 5000 | VHSUBsv2i32_VHSUBsv4i16_VHSUBsv8i8_VHSUBuv2i32_VHSUBuv4i16_VHSUBuv8i8 = 469, |
| 5001 | VBICiv2i32_VBICiv4i16_VBICiv4i32_VBICiv8i16_VORRiv2i32_VORRiv4i16_VORRiv4i32_VORRiv8i16 = 470, |
| 5002 | VQSHLsiv16i8_VQSHLsiv1i64_VQSHLsiv2i32_VQSHLsiv2i64_VQSHLsiv4i16_VQSHLsiv4i32_VQSHLsiv8i16_VQSHLsiv8i8_VQSHLsuv16i8_VQSHLsuv1i64_VQSHLsuv2i32_VQSHLsuv2i64_VQSHLsuv4i16_VQSHLsuv4i32_VQSHLsuv8i16_VQSHLsuv8i8_VQSHLsv1i64_VQSHLsv2i32_VQSHLsv4i16_VQSHLsv8i8_VQSHLuiv16i8_VQSHLuiv1i64_VQSHLuiv2i32_VQSHLuiv2i64_VQSHLuiv4i16_VQSHLuiv4i32_VQSHLuiv8i16_VQSHLuiv8i8_VQSHLuv1i64_VQSHLuv2i32_VQSHLuv4i16_VQSHLuv8i8 = 471, |
| 5003 | VQSHLsv16i8_VQSHLsv2i64_VQSHLsv4i32_VQSHLsv8i16_VQSHLuv16i8_VQSHLuv2i64_VQSHLuv4i32_VQSHLuv8i16 = 472, |
| 5004 | VCLSv16i8_VCLSv4i32_VCLSv8i16_VCLZv16i8_VCLZv4i32_VCLZv8i16_VCNTq = 473, |
| 5005 | VCLSv2i32_VCLSv4i16_VCLSv8i8_VCLZv2i32_VCLZv4i16_VCLZv8i8_VCNTd = 474, |
| 5006 | VEXTd16_VEXTd32_VEXTd8 = 475, |
| 5007 | VEXTq16_VEXTq32_VEXTq64_VEXTq8 = 476, |
| 5008 | VREV16d8_VREV32d16_VREV32d8_VREV64d16_VREV64d32_VREV64d8 = 477, |
| 5009 | VREV16q8_VREV32q16_VREV32q8_VREV64q16_VREV64q32_VREV64q8 = 478, |
| 5010 | VABALsv2i64_VABALsv4i32_VABALsv8i16_VABALuv2i64_VABALuv4i32_VABALuv8i16_VABAsv2i32_VABAsv4i16_VABAsv8i8_VABAuv2i32_VABAuv4i16_VABAuv8i8 = 479, |
| 5011 | VABAsv16i8_VABAsv4i32_VABAsv8i16_VABAuv16i8_VABAuv4i32_VABAuv8i16 = 480, |
| 5012 | VPADALsv16i8_VPADALsv4i32_VPADALsv8i16_VPADALuv16i8_VPADALuv4i32_VPADALuv8i16 = 481, |
| 5013 | VPADALsv2i32_VPADALsv4i16_VPADALsv8i8_VPADALuv2i32_VPADALuv4i16_VPADALuv8i8_VRSRAsv16i8_VRSRAsv1i64_VRSRAsv2i32_VRSRAsv2i64_VRSRAsv4i16_VRSRAsv4i32_VRSRAsv8i16_VRSRAsv8i8_VRSRAuv16i8_VRSRAuv1i64_VRSRAuv2i32_VRSRAuv2i64_VRSRAuv4i16_VRSRAuv4i32_VRSRAuv8i16_VRSRAuv8i8_VSRAsv16i8_VSRAsv1i64_VSRAsv2i32_VSRAsv2i64_VSRAsv4i16_VSRAsv4i32_VSRAsv8i16_VSRAsv8i8_VSRAuv16i8_VSRAuv1i64_VSRAuv2i32_VSRAuv2i64_VSRAuv4i16_VSRAuv4i32_VSRAuv8i16_VSRAuv8i8 = 482, |
| 5014 | VACGEfd_VACGEhd_VACGTfd_VACGThd_VCEQfd_VCEQhd_VCGEfd_VCGEhd_VCGTfd_VCGThd = 483, |
| 5015 | VACGEfq_VACGEhq_VACGTfq_VACGThq_VCEQfq_VCEQhq_VCGEfq_VCGEhq_VCGTfq_VCGThq = 484, |
| 5016 | VCEQv16i8_VCEQv4i32_VCEQv8i16_VCGEsv16i8_VCGEsv4i32_VCGEsv8i16_VCGEuv16i8_VCGEuv4i32_VCGEuv8i16_VCGTsv16i8_VCGTsv4i32_VCGTsv8i16_VCGTuv16i8_VCGTuv4i32_VCGTuv8i16_VQSUBsv16i8_VQSUBsv2i64_VQSUBsv4i32_VQSUBsv8i16_VQSUBuv16i8_VQSUBuv2i64_VQSUBuv4i32_VQSUBuv8i16 = 485, |
| 5017 | VCEQv2i32_VCEQv4i16_VCEQv8i8_VCGEsv2i32_VCGEsv4i16_VCGEsv8i8_VCGEuv2i32_VCGEuv4i16_VCGEuv8i8_VCGTsv2i32_VCGTsv4i16_VCGTsv8i8_VCGTuv2i32_VCGTuv4i16_VCGTuv8i8_VQSUBsv1i64_VQSUBsv2i32_VQSUBsv4i16_VQSUBsv8i8_VQSUBuv1i64_VQSUBuv2i32_VQSUBuv4i16_VQSUBuv8i8 = 486, |
| 5018 | VCEQzv16i8_VCEQzv2f32_VCEQzv2i32_VCEQzv4f16_VCEQzv4f32_VCEQzv4i16_VCEQzv4i32_VCEQzv8f16_VCEQzv8i16_VCEQzv8i8_VCGEzv16i8_VCGEzv2f32_VCGEzv2i32_VCGEzv4f16_VCGEzv4f32_VCGEzv4i16_VCGEzv4i32_VCGEzv8f16_VCGEzv8i16_VCGEzv8i8_VCGTzv16i8_VCGTzv2f32_VCGTzv2i32_VCGTzv4f16_VCGTzv4f32_VCGTzv4i16_VCGTzv4i32_VCGTzv8f16_VCGTzv8i16_VCGTzv8i8_VCLEzv16i8_VCLEzv2f32_VCLEzv2i32_VCLEzv4f16_VCLEzv4f32_VCLEzv4i16_VCLEzv4i32_VCLEzv8f16_VCLEzv8i16_VCLEzv8i8_VCLTzv16i8_VCLTzv2f32_VCLTzv2i32_VCLTzv4f16_VCLTzv4f32_VCLTzv4i16_VCLTzv4i32_VCLTzv8f16_VCLTzv8i16_VCLTzv8i8 = 487, |
| 5019 | VRSHLsv16i8_VRSHLsv2i64_VRSHLsv4i32_VRSHLsv8i16_VRSHLuv16i8_VRSHLuv2i64_VRSHLuv4i32_VRSHLuv8i16_VQRSHLsv16i8_VQRSHLsv2i64_VQRSHLsv4i32_VQRSHLsv8i16_VQRSHLuv16i8_VQRSHLuv2i64_VQRSHLuv4i32_VQRSHLuv8i16 = 488, |
| 5020 | VRSHLsv1i64_VRSHLsv2i32_VRSHLsv4i16_VRSHLsv8i8_VRSHLuv1i64_VRSHLuv2i32_VRSHLuv4i16_VRSHLuv8i8_VQRSHLsv1i64_VQRSHLsv2i32_VQRSHLsv4i16_VQRSHLsv8i8_VQRSHLuv1i64_VQRSHLuv2i32_VQRSHLuv4i16_VQRSHLuv8i8_VRSHRsv16i8_VRSHRsv1i64_VRSHRsv2i32_VRSHRsv2i64_VRSHRsv4i16_VRSHRsv4i32_VRSHRsv8i16_VRSHRsv8i8_VRSHRuv16i8_VRSHRuv1i64_VRSHRuv2i32_VRSHRuv2i64_VRSHRuv4i16_VRSHRuv4i32_VRSHRuv8i16_VRSHRuv8i8 = 489, |
| 5021 | VABSfd = 490, |
| 5022 | VABSfq = 491, |
| 5023 | VABSv16i8_VABSv4i32_VABSv8i16 = 492, |
| 5024 | VABSv2i32_VABSv4i16_VABSv8i8 = 493, |
| 5025 | VQABSv16i8_VQABSv4i32_VQABSv8i16_VQNEGv16i8_VQNEGv4i32_VQNEGv8i16 = 494, |
| 5026 | VQABSv2i32_VQABSv4i16_VQABSv8i8_VQNEGv2i32_VQNEGv4i16_VQNEGv8i8 = 495, |
| 5027 | VQADDsv16i8_VQADDsv2i64_VQADDsv4i32_VQADDsv8i16_VQADDuv16i8_VQADDuv2i64_VQADDuv4i32_VQADDuv8i16 = 496, |
| 5028 | VQADDsv1i64_VQADDsv2i32_VQADDsv4i16_VQADDsv8i8_VQADDuv1i64_VQADDuv2i32_VQADDuv4i16_VQADDuv8i8 = 497, |
| 5029 | VRECPEd_VRECPEfd_VRECPEhd_VRSQRTEd_VRSQRTEfd_VRSQRTEhd = 498, |
| 5030 | VRECPEfq_VRECPEhq_VRECPEq_VRSQRTEfq_VRSQRTEhq_VRSQRTEq = 499, |
| 5031 | VADDHNv2i32_VADDHNv4i16_VADDHNv8i8_VSUBHNv2i32_VSUBHNv4i16_VSUBHNv8i8 = 500, |
| 5032 | VSHRNv2i32_VSHRNv4i16_VSHRNv8i8 = 501, |
| 5033 | VRADDHNv2i32_VRADDHNv4i16_VRADDHNv8i8_VRSUBHNv2i32_VRSUBHNv4i16_VRSUBHNv8i8 = 502, |
| 5034 | VRSHRNv2i32_VRSHRNv4i16_VRSHRNv8i8_VQSHRNsv2i32_VQSHRNsv4i16_VQSHRNsv8i8_VQSHRNuv2i32_VQSHRNuv4i16_VQSHRNuv8i8_VQSHRUNv2i32_VQSHRUNv4i16_VQSHRUNv8i8_VQRSHRNsv2i32_VQRSHRNsv4i16_VQRSHRNsv8i8_VQRSHRNuv2i32_VQRSHRNuv4i16_VQRSHRNuv8i8_VQRSHRUNv2i32_VQRSHRUNv4i16_VQRSHRUNv8i8 = 503, |
| 5035 | VTBL1 = 504, |
| 5036 | VTBX1 = 505, |
| 5037 | VTBL2 = 506, |
| 5038 | VTBX2 = 507, |
| 5039 | VTBL3_VTBL3Pseudo = 508, |
| 5040 | VTBX3_VTBX3Pseudo = 509, |
| 5041 | VTBL4_VTBL4Pseudo = 510, |
| 5042 | VTBX4_VTBX4Pseudo = 511, |
| 5043 | VSWPd_VSWPq = 512, |
| 5044 | VTRNd16_VTRNd32_VTRNd8_VUZPd16_VUZPd8_VZIPd16_VZIPd8 = 513, |
| 5045 | VTRNq16_VTRNq32_VTRNq8 = 514, |
| 5046 | VUZPq16_VUZPq32_VUZPq8_VZIPq16_VZIPq32_VZIPq8 = 515, |
| 5047 | VABSD_VNEGD = 516, |
| 5048 | VABSS_VNEGS = 517, |
| 5049 | VCMPD_VCMPZD_VCMPED_VCMPEZD = 518, |
| 5050 | VCMPS_VCMPZS_VCMPES_VCMPEZS = 519, |
| 5051 | VADDS_VSUBS = 520, |
| 5052 | VADDfd_VSUBfd_VABDfd_VABDhd_VMAXfd_VMAXhd_VMINfd_VMINhd = 521, |
| 5053 | VADDfq_VSUBfq_VABDfq_VABDhq_VMAXfq_VMAXhq_VMINfq_VMINhq = 522, |
| 5054 | VABDLsv2i64_VABDLsv4i32_VABDLsv8i16_VABDLuv2i64_VABDLuv4i32_VABDLuv8i16_VABDsv16i8_VABDsv4i32_VABDsv8i16_VABDuv16i8_VABDuv4i32_VABDuv8i16_VMAXsv16i8_VMAXsv4i32_VMAXsv8i16_VMAXuv16i8_VMAXuv4i32_VMAXuv8i16_VMINsv16i8_VMINsv4i32_VMINsv8i16_VMINuv16i8_VMINuv4i32_VMINuv8i16 = 523, |
| 5055 | VABDsv2i32_VABDsv4i16_VABDsv8i8_VABDuv2i32_VABDuv4i16_VABDuv8i8_VMAXsv2i32_VMAXsv4i16_VMAXsv8i8_VMAXuv2i32_VMAXuv4i16_VMAXuv8i8_VMINsv2i32_VMINsv4i16_VMINsv8i8_VMINuv2i32_VMINuv4i16_VMINuv8i8_VPMAXs16_VPMAXs32_VPMAXs8_VPMAXu16_VPMAXu32_VPMAXu8_VPMINs16_VPMINs32_VPMINs8_VPMINu16_VPMINu32_VPMINu8 = 524, |
| 5056 | VPADDf_VPMAXf_VPMAXh_VPMINf_VPMINh = 525, |
| 5057 | VADDD_VSUBD = 526, |
| 5058 | VRECPSfd_VRECPShd_VRSQRTSfd_VRSQRTShd = 527, |
| 5059 | VRECPSfq_VRECPShq_VRSQRTSfq_VRSQRTShq = 528, |
| 5060 | VMULS_VNMULS = 529, |
| 5061 | VMULfd = 530, |
| 5062 | VMULfq = 531, |
| 5063 | VMULpd_VMULslhd_VMULslv4i16_VMULv4i16_VMULv8i8_VQDMULHslv4i16_VQDMULHv4i16_VQRDMULHslv4i16_VQRDMULHv4i16_VMULLp8_VMULLslsv2i32_VMULLslsv4i16_VMULLsluv2i32_VMULLsluv4i16_VMULLsv4i32_VMULLsv8i16_VMULLuv4i32_VMULLuv8i16_VQDMULLslv2i32_VQDMULLslv4i16_VQDMULLv4i32 = 532, |
| 5064 | VMULpq_VMULslhq_VMULslv8i16_VMULv16i8_VMULv8i16_VQDMULHslv8i16_VQDMULHv8i16_VQRDMULHslv8i16_VQRDMULHv8i16 = 533, |
| 5065 | VMULslfd = 534, |
| 5066 | VMULslfq = 535, |
| 5067 | VMULslv2i32_VMULv2i32_VQDMULHslv2i32_VQDMULHv2i32_VQRDMULHslv2i32_VQRDMULHv2i32_VMULLsv2i64_VMULLuv2i64_VQDMULLv2i64 = 536, |
| 5068 | VMULslv4i32_VMULv4i32_VQDMULHslv4i32_VQDMULHv4i32_VQRDMULHslv4i32_VQRDMULHv4i32 = 537, |
| 5069 | VMULLp64 = 538, |
| 5070 | VMLAD_VMLSD_VNMLAD_VNMLSD = 539, |
| 5071 | VMLAH_VMLSH_VNMLAH_VNMLSH = 540, |
| 5072 | VMLALslsv2i32_VMLALsluv2i32_VMLALsv2i64_VMLALuv2i64_VMLAslv2i32_VMLAv2i32_VMLSLslsv2i32_VMLSLsluv2i32_VMLSLsv2i64_VMLSLuv2i64_VMLSslv2i32_VMLSv2i32_VQDMLALslv2i32_VQDMLALv2i64_VQDMLSLslv2i32_VQDMLSLv2i64 = 541, |
| 5073 | VMLALslsv4i16_VMLALsluv4i16_VMLALsv4i32_VMLALsv8i16_VMLALuv4i32_VMLALuv8i16_VMLAslv4i16_VMLAv4i16_VMLAv8i8_VMLSLslsv4i16_VMLSLsluv4i16_VMLSLsv4i32_VMLSLsv8i16_VMLSLuv4i32_VMLSLuv8i16_VMLSslv4i16_VMLSv4i16_VMLSv8i8_VQDMLALslv4i16_VQDMLALv4i32_VQDMLSLslv4i16_VQDMLSLv4i32 = 542, |
| 5074 | VMLAS_VMLSS_VNMLAS_VNMLSS = 543, |
| 5075 | VMLAfd_VMLAhd_VMLAslfd_VMLAslhd_VMLSfd_VMLShd_VMLSslfd_VMLSslhd = 544, |
| 5076 | VMLAfq_VMLAhq_VMLAslfq_VMLAslhq_VMLSfq_VMLShq_VMLSslfq_VMLSslhq = 545, |
| 5077 | VMLAslv4i32_VMLAv4i32_VMLSslv4i32_VMLSv4i32 = 546, |
| 5078 | VMLAslv8i16_VMLAv16i8_VMLAv8i16_VMLSslv8i16_VMLSv16i8_VMLSv8i16 = 547, |
| 5079 | VFMAD_VFMSD_VFNMAD_VFNMSD = 548, |
| 5080 | VFMAS_VFMSS_VFNMAS_VFNMSS = 549, |
| 5081 | VFNMAH_VFNMSH = 550, |
| 5082 | VFMAfd_VFMSfd = 551, |
| 5083 | VFMAfq_VFMSfq = 552, |
| 5084 | VCVTANSDf_VCVTANSDh_VCVTANSQf_VCVTANSQh_VCVTANUDf_VCVTANUDh_VCVTANUQf_VCVTANUQh_VCVTASD_VCVTASH_VCVTASS_VCVTAUD_VCVTAUH_VCVTAUS_VCVTBDH_VCVTMNSDf_VCVTMNSDh_VCVTMNSQf_VCVTMNSQh_VCVTMNUDf_VCVTMNUDh_VCVTMNUQf_VCVTMNUQh_VCVTMSD_VCVTMSH_VCVTMSS_VCVTMUD_VCVTMUH_VCVTMUS_VCVTNNSDf_VCVTNNSDh_VCVTNNSQf_VCVTNNSQh_VCVTNNUDf_VCVTNNUDh_VCVTNNUQf_VCVTNNUQh_VCVTNSD_VCVTNSH_VCVTNSS_VCVTNUD_VCVTNUH_VCVTNUS_VCVTPNSDf_VCVTPNSDh_VCVTPNSQf_VCVTPNSQh_VCVTPNUDf_VCVTPNUDh_VCVTPNUQf_VCVTPNUQh_VCVTPSD_VCVTPSH_VCVTPSS_VCVTPUD_VCVTPUH_VCVTPUS_VCVTTDH_VCVTTHD = 553, |
| 5085 | VCVTBHD = 554, |
| 5086 | VCVTBHS_VCVTTHS = 555, |
| 5087 | VCVTBSH_VCVTTSH = 556, |
| 5088 | VCVTDS = 557, |
| 5089 | VCVTSD = 558, |
| 5090 | VCVTf2h_VCVTf2sq_VCVTf2uq_VCVTf2xsq_VCVTf2xuq_VCVTh2f_VCVTh2sq_VCVTh2uq_VCVTh2xsq_VCVTh2xuq_VCVTs2fq_VCVTs2hq_VCVTu2fq_VCVTu2hq_VCVTxs2fq_VCVTxs2hq_VCVTxu2fq_VCVTxu2hq = 559, |
| 5091 | VCVTf2sd_VCVTf2ud_VCVTf2xsd_VCVTf2xud_VCVTh2sd_VCVTh2ud_VCVTh2xsd_VCVTh2xud_VCVTs2fd_VCVTs2hd_VCVTu2fd_VCVTu2hd_VCVTxs2fd_VCVTxs2hd_VCVTxu2fd_VCVTxu2hd = 560, |
| 5092 | VSITOD_VUITOD = 561, |
| 5093 | VSITOH_VUITOH = 562, |
| 5094 | VSITOS_VUITOS = 563, |
| 5095 | VTOSHD_VTOSIRD_VTOSIZD_VTOSLD_VTOUHD_VTOUIRD_VTOUIZD_VTOULD = 564, |
| 5096 | VTOSHH_VTOSIRH_VTOSIZH_VTOSLH_VTOUHH_VTOUIRH_VTOUIZH_VTOULH = 565, |
| 5097 | VTOSHS_VTOSIRS_VTOSIZS_VTOSLS_VTOUHS_VTOUIRS_VTOUIZS_VTOULS = 566, |
| 5098 | VMOVv16i8_VMOVv1i64_VMOVv2f32_VMOVv2i32_VMOVv2i64_VMOVv4f32_VMOVv4i16_VMOVv4i32_VMOVv8i16_VMOVv8i8_VMVNv2i32_VMVNv4i16_VMVNv4i32_VMVNv8i16 = 567, |
| 5099 | VMOVD_VMOVDcc_FCONSTD = 568, |
| 5100 | VMOVS_VMOVScc_FCONSTS = 569, |
| 5101 | VMVNd_VMVNq = 570, |
| 5102 | VMOVNv2i32_VMOVNv4i16_VMOVNv8i8 = 571, |
| 5103 | VMOVLsv2i64_VMOVLsv4i32_VMOVLsv8i16_VMOVLuv2i64_VMOVLuv4i32_VMOVLuv8i16 = 572, |
| 5104 | VQMOVNsuv2i32_VQMOVNsuv4i16_VQMOVNsuv8i8_VQMOVNsv2i32_VQMOVNsv4i16_VQMOVNsv8i8_VQMOVNuv2i32_VQMOVNuv4i16_VQMOVNuv8i8 = 573, |
| 5105 | VDUPLN16d_VDUPLN32d_VDUPLN8d = 574, |
| 5106 | VDUPLN16q_VDUPLN32q_VDUPLN8q = 575, |
| 5107 | VDUP16d_VDUP16q_VDUP32d_VDUP32q_VDUP8d_VDUP8q = 576, |
| 5108 | VMOVRS = 577, |
| 5109 | VMOVSR = 578, |
| 5110 | VSETLNi16_VSETLNi32_VSETLNi8 = 579, |
| 5111 | VMOVRRD_VMOVRRS = 580, |
| 5112 | VMOVDRR = 581, |
| 5113 | VMOVSRR = 582, |
| 5114 | VGETLNi32_VGETLNu16_VGETLNu8 = 583, |
| 5115 | VGETLNs16_VGETLNs8 = 584, |
| 5116 | VMRS_VMRS_FPCXTNS_VMRS_FPCXTS_VMRS_FPEXC_VMRS_FPINST_VMRS_FPINST2_VMRS_FPSCR_NZCVQC_VMRS_FPSID_VMRS_MVFR0_VMRS_MVFR1_VMRS_MVFR2_VMRS_P0_VMRS_VPR = 585, |
| 5117 | VMSR_VMSR_FPCXTNS_VMSR_FPCXTS_VMSR_FPEXC_VMSR_FPINST_VMSR_FPINST2_VMSR_FPSCR_NZCVQC_VMSR_FPSID_VMSR_P0_VMSR_VPR = 586, |
| 5118 | FMSTAT = 587, |
| 5119 | VLDRD = 588, |
| 5120 | VLDRS = 589, |
| 5121 | VSTRD = 590, |
| 5122 | VSTRS = 591, |
| 5123 | VLDMQIA = 592, |
| 5124 | VSTMQIA = 593, |
| 5125 | VLDMDIA_VLDMSIA = 594, |
| 5126 | VLDMDDB_UPD_VLDMDIA_UPD_VLDMSDB_UPD_VLDMSIA_UPD = 595, |
| 5127 | VSTMDIA_VSTMSIA = 596, |
| 5128 | VSTMDDB_UPD_VSTMDIA_UPD_VSTMSDB_UPD_VSTMSIA_UPD = 597, |
| 5129 | VLD1d16_VLD1d32_VLD1d64_VLD1d8 = 598, |
| 5130 | VLD1q16_VLD1q32_VLD1q64_VLD1q8 = 599, |
| 5131 | VLD1d16wb_fixed_VLD1d16wb_register_VLD1d32wb_fixed_VLD1d32wb_register_VLD1d64wb_fixed_VLD1d64wb_register_VLD1d8wb_fixed_VLD1d8wb_register = 600, |
| 5132 | VLD1q16wb_fixed_VLD1q16wb_register_VLD1q32wb_fixed_VLD1q32wb_register_VLD1q64wb_fixed_VLD1q64wb_register_VLD1q8wb_fixed_VLD1q8wb_register = 601, |
| 5133 | VLD1d16T_VLD1d32T_VLD1d64T_VLD1d8T_VLD1d64TPseudo_VLD1d64TPseudoWB_fixed_VLD1d64TPseudoWB_register = 602, |
| 5134 | VLD1d16Twb_fixed_VLD1d16Twb_register_VLD1d32Twb_fixed_VLD1d32Twb_register_VLD1d64Twb_fixed_VLD1d64Twb_register_VLD1d8Twb_fixed_VLD1d8Twb_register = 603, |
| 5135 | VLD1d16Q_VLD1d32Q_VLD1d64Q_VLD1d8Q_VLD1d64QPseudo_VLD1d64QPseudoWB_fixed_VLD1d64QPseudoWB_register = 604, |
| 5136 | VLD1d16Qwb_fixed_VLD1d16Qwb_register_VLD1d32Qwb_fixed_VLD1d32Qwb_register_VLD1d64Qwb_fixed_VLD1d64Qwb_register_VLD1d8Qwb_fixed_VLD1d8Qwb_register = 605, |
| 5137 | VLD2b16_VLD2b32_VLD2b8_VLD2d16_VLD2d32_VLD2d8 = 606, |
| 5138 | VLD2q16_VLD2q32_VLD2q8_VLD2q16Pseudo_VLD2q32Pseudo_VLD2q8Pseudo = 607, |
| 5139 | VLD2b16wb_fixed_VLD2b16wb_register_VLD2b32wb_fixed_VLD2b32wb_register_VLD2b8wb_fixed_VLD2b8wb_register_VLD2d16wb_fixed_VLD2d16wb_register_VLD2d32wb_fixed_VLD2d32wb_register_VLD2d8wb_fixed_VLD2d8wb_register = 608, |
| 5140 | VLD2q16wb_fixed_VLD2q16wb_register_VLD2q32wb_fixed_VLD2q32wb_register_VLD2q8wb_fixed_VLD2q8wb_register_VLD2q16PseudoWB_fixed_VLD2q16PseudoWB_register_VLD2q32PseudoWB_fixed_VLD2q32PseudoWB_register_VLD2q8PseudoWB_fixed_VLD2q8PseudoWB_register = 609, |
| 5141 | VLD3d16_VLD3d32_VLD3d8_VLD3q16_VLD3q32_VLD3q8 = 610, |
| 5142 | VLD3d16Pseudo_VLD3d32Pseudo_VLD3d8Pseudo_VLD3q16oddPseudo_VLD3q32oddPseudo_VLD3q8oddPseudo = 611, |
| 5143 | VLD3d16_UPD_VLD3d32_UPD_VLD3d8_UPD_VLD3q16_UPD_VLD3q32_UPD_VLD3q8_UPD = 612, |
| 5144 | VLD3d16Pseudo_UPD_VLD3d32Pseudo_UPD_VLD3d8Pseudo_UPD_VLD3q16Pseudo_UPD_VLD3q16oddPseudo_UPD_VLD3q32Pseudo_UPD_VLD3q32oddPseudo_UPD_VLD3q8Pseudo_UPD_VLD3q8oddPseudo_UPD = 613, |
| 5145 | VLD4d16_VLD4d32_VLD4d8_VLD4q16_VLD4q32_VLD4q8 = 614, |
| 5146 | VLD4d16Pseudo_VLD4d32Pseudo_VLD4d8Pseudo_VLD4q16oddPseudo_VLD4q32oddPseudo_VLD4q8oddPseudo = 615, |
| 5147 | VLD4d16_UPD_VLD4d32_UPD_VLD4d8_UPD_VLD4q16_UPD_VLD4q32_UPD_VLD4q8_UPD = 616, |
| 5148 | VLD4d16Pseudo_UPD_VLD4d32Pseudo_UPD_VLD4d8Pseudo_UPD_VLD4q16Pseudo_UPD_VLD4q16oddPseudo_UPD_VLD4q32Pseudo_UPD_VLD4q32oddPseudo_UPD_VLD4q8Pseudo_UPD_VLD4q8oddPseudo_UPD = 617, |
| 5149 | VLD1DUPd16_VLD1DUPd32_VLD1DUPd8 = 618, |
| 5150 | VLD1DUPq16_VLD1DUPq32_VLD1DUPq8 = 619, |
| 5151 | VLD1LNd16_VLD1LNd8 = 620, |
| 5152 | VLD1LNd32_VLD1LNq16Pseudo_VLD1LNq32Pseudo_VLD1LNq8Pseudo = 621, |
| 5153 | VLD1DUPd16wb_fixed_VLD1DUPd16wb_register_VLD1DUPd32wb_fixed_VLD1DUPd32wb_register_VLD1DUPd8wb_fixed_VLD1DUPd8wb_register_VLD1DUPq16wb_register_VLD1DUPq32wb_register_VLD1DUPq8wb_register = 622, |
| 5154 | VLD1DUPq16wb_fixed_VLD1DUPq32wb_fixed_VLD1DUPq8wb_fixed = 623, |
| 5155 | VLD1LNd16_UPD_VLD1LNd32_UPD_VLD1LNd8_UPD_VLD1LNq16Pseudo_UPD_VLD1LNq32Pseudo_UPD_VLD1LNq8Pseudo_UPD = 624, |
| 5156 | VLD2DUPd16_VLD2DUPd16x2_VLD2DUPd32_VLD2DUPd32x2_VLD2DUPd8_VLD2DUPd8x2 = 625, |
| 5157 | VLD2LNd16_VLD2LNd32_VLD2LNd8_VLD2LNq16_VLD2LNq32_VLD2LNd16Pseudo_VLD2LNd32Pseudo_VLD2LNd8Pseudo_VLD2LNq16Pseudo_VLD2LNq32Pseudo = 626, |
| 5158 | VLD2LNd16_UPD_VLD2LNd32_UPD_VLD2LNd8_UPD_VLD2LNq16_UPD_VLD2LNq32_UPD = 627, |
| 5159 | VLD2DUPd16wb_fixed_VLD2DUPd16wb_register_VLD2DUPd16x2wb_fixed_VLD2DUPd16x2wb_register_VLD2DUPd32wb_fixed_VLD2DUPd32wb_register_VLD2DUPd32x2wb_fixed_VLD2DUPd32x2wb_register_VLD2DUPd8wb_fixed_VLD2DUPd8wb_register_VLD2DUPd8x2wb_fixed_VLD2DUPd8x2wb_register = 628, |
| 5160 | VLD2LNd16Pseudo_UPD_VLD2LNd32Pseudo_UPD_VLD2LNd8Pseudo_UPD_VLD2LNq16Pseudo_UPD_VLD2LNq32Pseudo_UPD = 629, |
| 5161 | VLD3DUPd16_VLD3DUPd32_VLD3DUPd8_VLD3DUPq16_VLD3DUPq32_VLD3DUPq8_VLD3DUPd16Pseudo_VLD3DUPd32Pseudo_VLD3DUPd8Pseudo = 630, |
| 5162 | VLD3LNd16_VLD3LNd32_VLD3LNd8_VLD3LNq16_VLD3LNq32_VLD3LNd16Pseudo_VLD3LNd32Pseudo_VLD3LNd8Pseudo_VLD3LNq16Pseudo_VLD3LNq32Pseudo = 631, |
| 5163 | VLD3DUPd16_UPD_VLD3DUPd32_UPD_VLD3DUPd8_UPD_VLD3DUPq16_UPD_VLD3DUPq32_UPD_VLD3DUPq8_UPD = 632, |
| 5164 | VLD3LNd16_UPD_VLD3LNd32_UPD_VLD3LNd8_UPD_VLD3LNq16_UPD_VLD3LNq32_UPD = 633, |
| 5165 | VLD3DUPd16Pseudo_UPD_VLD3DUPd32Pseudo_UPD_VLD3DUPd8Pseudo_UPD = 634, |
| 5166 | VLD3LNd16Pseudo_UPD_VLD3LNd32Pseudo_UPD_VLD3LNd8Pseudo_UPD_VLD3LNq16Pseudo_UPD_VLD3LNq32Pseudo_UPD = 635, |
| 5167 | VLD4DUPd16_VLD4DUPd32_VLD4DUPd8_VLD4DUPq16_VLD4DUPq32_VLD4DUPq8 = 636, |
| 5168 | VLD4LNd16_VLD4LNd32_VLD4LNd8_VLD4LNq16_VLD4LNq32_VLD4LNd16Pseudo_VLD4LNd32Pseudo_VLD4LNd8Pseudo_VLD4LNq16Pseudo_VLD4LNq32Pseudo = 637, |
| 5169 | VLD4DUPd16Pseudo_VLD4DUPd32Pseudo_VLD4DUPd8Pseudo = 638, |
| 5170 | VLD4DUPd16_UPD_VLD4DUPd32_UPD_VLD4DUPd8_UPD_VLD4DUPq16_UPD_VLD4DUPq32_UPD_VLD4DUPq8_UPD = 639, |
| 5171 | VLD4LNd16_UPD_VLD4LNd32_UPD_VLD4LNd8_UPD_VLD4LNq16_UPD_VLD4LNq32_UPD = 640, |
| 5172 | VLD4DUPd16Pseudo_UPD_VLD4DUPd32Pseudo_UPD_VLD4DUPd8Pseudo_UPD = 641, |
| 5173 | VLD4LNd16Pseudo_UPD_VLD4LNd32Pseudo_UPD_VLD4LNd8Pseudo_UPD_VLD4LNq16Pseudo_UPD_VLD4LNq32Pseudo_UPD = 642, |
| 5174 | VST1d16_VST1d32_VST1d64_VST1d8 = 643, |
| 5175 | VST1q16_VST1q32_VST1q64_VST1q8 = 644, |
| 5176 | VST1d16wb_fixed_VST1d16wb_register_VST1d32wb_fixed_VST1d32wb_register_VST1d64wb_fixed_VST1d64wb_register_VST1d8wb_fixed_VST1d8wb_register = 645, |
| 5177 | VST1q16wb_fixed_VST1q16wb_register_VST1q32wb_fixed_VST1q32wb_register_VST1q64wb_fixed_VST1q64wb_register_VST1q8wb_fixed_VST1q8wb_register = 646, |
| 5178 | VST1d16T_VST1d32T_VST1d64T_VST1d8T_VST1d64TPseudo = 647, |
| 5179 | VST1d16Twb_fixed_VST1d16Twb_register_VST1d32Twb_fixed_VST1d32Twb_register_VST1d64Twb_fixed_VST1d64Twb_register_VST1d8Twb_fixed_VST1d8Twb_register = 648, |
| 5180 | VST1d64TPseudoWB_fixed_VST1d64TPseudoWB_register = 649, |
| 5181 | VST1d16Q_VST1d16QPseudo_VST1d32Q_VST1d32QPseudo_VST1d64Q_VST1d64QPseudo_VST1d8Q_VST1d8QPseudo = 650, |
| 5182 | VST1d16QPseudoWB_fixed_VST1d16QPseudoWB_register_VST1d32QPseudoWB_fixed_VST1d32QPseudoWB_register_VST1d64QPseudoWB_fixed_VST1d64QPseudoWB_register_VST1d8QPseudoWB_fixed_VST1d8QPseudoWB_register = 651, |
| 5183 | VST1d16Qwb_fixed_VST1d16Qwb_register_VST1d32Qwb_fixed_VST1d32Qwb_register_VST1d64Qwb_fixed_VST1d64Qwb_register_VST1d8Qwb_fixed_VST1d8Qwb_register = 652, |
| 5184 | VST2b16_VST2b32_VST2b8 = 653, |
| 5185 | VST2d16_VST2d32_VST2d8 = 654, |
| 5186 | VST2b16wb_fixed_VST2b16wb_register_VST2b32wb_fixed_VST2b32wb_register_VST2b8wb_fixed_VST2b8wb_register_VST2d16wb_fixed_VST2d16wb_register_VST2d32wb_fixed_VST2d32wb_register_VST2d8wb_fixed_VST2d8wb_register = 655, |
| 5187 | VST2q16_VST2q32_VST2q8_VST2q16Pseudo_VST2q32Pseudo_VST2q8Pseudo = 656, |
| 5188 | VST2q16wb_fixed_VST2q16wb_register_VST2q32wb_fixed_VST2q32wb_register_VST2q8wb_fixed_VST2q8wb_register = 657, |
| 5189 | VST2q16PseudoWB_fixed_VST2q16PseudoWB_register_VST2q32PseudoWB_fixed_VST2q32PseudoWB_register_VST2q8PseudoWB_fixed_VST2q8PseudoWB_register = 658, |
| 5190 | VST3d16_VST3d32_VST3d8_VST3q16_VST3q32_VST3q8_VST3d16Pseudo_VST3d32Pseudo_VST3d8Pseudo_VST3q16oddPseudo_VST3q32oddPseudo_VST3q8oddPseudo = 659, |
| 5191 | VST3d16_UPD_VST3d32_UPD_VST3d8_UPD_VST3q16_UPD_VST3q32_UPD_VST3q8_UPD_VST3d16Pseudo_UPD_VST3d32Pseudo_UPD_VST3d8Pseudo_UPD_VST3q16Pseudo_UPD_VST3q16oddPseudo_UPD_VST3q32Pseudo_UPD_VST3q32oddPseudo_UPD_VST3q8Pseudo_UPD_VST3q8oddPseudo_UPD = 660, |
| 5192 | VST4d16_VST4d32_VST4d8_VST4q16_VST4q32_VST4q8_VST4d16Pseudo_VST4d32Pseudo_VST4d8Pseudo_VST4q16oddPseudo_VST4q32oddPseudo_VST4q8oddPseudo = 661, |
| 5193 | VST4d16_UPD_VST4d32_UPD_VST4d8_UPD_VST4q16_UPD_VST4q32_UPD_VST4q8_UPD_VST4d16Pseudo_UPD_VST4d32Pseudo_UPD_VST4d8Pseudo_UPD_VST4q16Pseudo_UPD_VST4q16oddPseudo_UPD_VST4q32Pseudo_UPD_VST4q32oddPseudo_UPD_VST4q8Pseudo_UPD_VST4q8oddPseudo_UPD = 662, |
| 5194 | VST1LNd16_VST1LNd32_VST1LNd8_VST1LNq16Pseudo_VST1LNq32Pseudo_VST1LNq8Pseudo = 663, |
| 5195 | VST1LNd16_UPD_VST1LNd32_UPD_VST1LNd8_UPD_VST1LNq16Pseudo_UPD_VST1LNq32Pseudo_UPD_VST1LNq8Pseudo_UPD = 664, |
| 5196 | VST2LNd16_VST2LNd32_VST2LNd8_VST2LNq16_VST2LNq32_VST2LNd16Pseudo_VST2LNd32Pseudo_VST2LNd8Pseudo_VST2LNq16Pseudo_VST2LNq32Pseudo = 665, |
| 5197 | VST2LNd16_UPD_VST2LNd32_UPD_VST2LNd8_UPD_VST2LNq16_UPD_VST2LNq32_UPD = 666, |
| 5198 | VST2LNd16Pseudo_UPD_VST2LNd32Pseudo_UPD_VST2LNd8Pseudo_UPD_VST2LNq16Pseudo_UPD_VST2LNq32Pseudo_UPD = 667, |
| 5199 | VST3LNd16_VST3LNd32_VST3LNd8_VST3LNq16_VST3LNq32_VST3LNd16Pseudo_VST3LNd32Pseudo_VST3LNd8Pseudo = 668, |
| 5200 | VST3LNq16Pseudo_VST3LNq32Pseudo = 669, |
| 5201 | VST3LNd16_UPD_VST3LNd32_UPD_VST3LNd8_UPD_VST3LNq16_UPD_VST3LNq32_UPD = 670, |
| 5202 | VST3LNd16Pseudo_UPD_VST3LNd32Pseudo_UPD_VST3LNd8Pseudo_UPD_VST3LNq16Pseudo_UPD_VST3LNq32Pseudo_UPD = 671, |
| 5203 | VST4LNd16_VST4LNd32_VST4LNd8_VST4LNq16_VST4LNq32_VST4LNd16Pseudo_VST4LNd32Pseudo_VST4LNd8Pseudo_VST4LNq16Pseudo_VST4LNq32Pseudo = 672, |
| 5204 | VST4LNd16_UPD_VST4LNd32_UPD_VST4LNd8_UPD_VST4LNq16_UPD_VST4LNq32_UPD = 673, |
| 5205 | VST4LNd16Pseudo_UPD_VST4LNd32Pseudo_UPD_VST4LNd8Pseudo_UPD_VST4LNq16Pseudo_UPD_VST4LNq32Pseudo_UPD = 674, |
| 5206 | VDIVS = 675, |
| 5207 | VSQRTS = 676, |
| 5208 | VDIVD = 677, |
| 5209 | VSQRTD = 678, |
| 5210 | ABS = 679, |
| 5211 | COPY = 680, |
| 5212 | t2MOVCCi_t2MOVCCi16 = 681, |
| 5213 | t2MOVi_t2MOVi16 = 682, |
| 5214 | t2ABS = 683, |
| 5215 | t2USAD8_t2USADA8 = 684, |
| 5216 | t2SDIV_t2UDIV = 685, |
| 5217 | t2LDREX_t2LDREXB_t2LDREXD_t2LDREXH_t2LDA_t2LDAB_t2LDAEX_t2LDAEXB_t2LDAEXD_t2LDAEXH_t2LDAH = 686, |
| 5218 | LDA_LDAB_LDAEX_LDAEXB_LDAEXD_LDAEXH_LDAH = 687, |
| 5219 | LDRBT_POST = 688, |
| 5220 | MOVsr = 689, |
| 5221 | t2MOVSsr_t2MOVsr = 690, |
| 5222 | MOVTi16_ga_pcrel_MOVTi16_t2MOVTi16_ga_pcrel_t2MOVTi16 = 691, |
| 5223 | ADDSri_ADCri_ADDri_RSBSri_RSBri_RSCri_SBCri_t2ADDSri_t2ADCri_t2ADDri_t2ADDri12_t2RSBSri_t2RSBri_t2SBCri = 692, |
| 5224 | CLZ_t2CLZ = 693, |
| 5225 | t2ANDri_t2BICri_t2EORri_t2ORRri = 694, |
| 5226 | t2MVNCCi = 695, |
| 5227 | t2MVNi = 696, |
| 5228 | t2MVNr = 697, |
| 5229 | t2MVNs = 698, |
| 5230 | ADDSrr_ADCrr_ADDrr_RSBrr_RSCrr_SBCrr_t2ADDSrr_t2ADCrr_t2ADDrr_t2SBCrr = 699, |
| 5231 | CRC32B_CRC32CB_CRC32CH_CRC32CW_CRC32H_CRC32W_t2CRC32B_t2CRC32CB_t2CRC32CH_t2CRC32CW_t2CRC32H_t2CRC32W = 700, |
| 5232 | t2ANDrr_t2BICrr_t2EORrr = 701, |
| 5233 | ADDSrsi_ADCrsi_ADDrsi_RSBrsi_RSCrsi_SBCrsi = 702, |
| 5234 | t2ADDSrs = 703, |
| 5235 | t2ADCrs_t2ADDrs_t2SBCrs = 704, |
| 5236 | t2ANDrs_t2BICrs_t2EORrs_t2ORRrs = 705, |
| 5237 | t2RSBrs = 706, |
| 5238 | ADDSrsr = 707, |
| 5239 | ADCrsr_ADDrsr_RSBrsr_RSCrsr_SBCrsr = 708, |
| 5240 | ADR = 709, |
| 5241 | MVNi = 710, |
| 5242 | MVNsi = 711, |
| 5243 | t2MOVSsi_t2MOVsi = 712, |
| 5244 | ASRi_RORi = 713, |
| 5245 | ASRr_RORr_LSRi_LSRr_LSLi_LSLr = 714, |
| 5246 | LSRs1 = 715, |
| 5247 | CMPri_CMNri = 716, |
| 5248 | CMPrr_CMNzrr = 717, |
| 5249 | CMPrsi_CMNzrsi = 718, |
| 5250 | CMPrsr_CMNzrsr = 719, |
| 5251 | t2LDC2L_OFFSET_t2LDC2L_OPTION_t2LDC2L_POST_t2LDC2L_PRE_t2LDC2_OFFSET_t2LDC2_OPTION_t2LDC2_POST_t2LDC2_PRE_t2LDCL_OFFSET_t2LDCL_OPTION_t2LDCL_POST_t2LDCL_PRE_t2LDC_OFFSET_t2LDC_OPTION_t2LDC_POST_t2LDC_PRE_RRXi = 720, |
| 5252 | RBIT_REV_REV16_REVSH = 721, |
| 5253 | RRX = 722, |
| 5254 | TSTri = 723, |
| 5255 | TSTrr = 724, |
| 5256 | TSTrsi = 725, |
| 5257 | TSTrsr = 726, |
| 5258 | MRS_MRSbanked_MRSsys = 727, |
| 5259 | MSR_MSRbanked_MSRi = 728, |
| 5260 | SRSDA_SRSDA_UPD_SRSDB_SRSDB_UPD_SRSIA_SRSIA_UPD_SRSIB_SRSIB_UPD_t2SRSDB_t2SRSDB_UPD_t2SRSIA_t2SRSIA_UPD_RFEDA_RFEDA_UPD_RFEDB_RFEDB_UPD_RFEIA_RFEIA_UPD_RFEIB_RFEIB_UPD_t2RFEDB_t2RFEDBW_t2RFEIA_t2RFEIAW = 729, |
| 5261 | t2STREX_t2STREXB_t2STREXD_t2STREXH = 730, |
| 5262 | STL_STLB_STLEX_STLEXB_STLEXD_STLEXH_STLH = 731, |
| 5263 | t2STL_t2STLB_t2STLEX_t2STLEXB_t2STLEXD_t2STLEXH_t2STLH = 732, |
| 5264 | VABDfd_VABDhd = 733, |
| 5265 | VABDfq_VABDhq = 734, |
| 5266 | VABSD = 735, |
| 5267 | VABSH = 736, |
| 5268 | VABSS = 737, |
| 5269 | VABShd = 738, |
| 5270 | VABShq = 739, |
| 5271 | VACGEfd_VACGEhd_VACGTfd_VACGThd = 740, |
| 5272 | VACGEfq_VACGEhq_VACGTfq_VACGThq = 741, |
| 5273 | VADDH_VSUBH = 742, |
| 5274 | VADDfd_VSUBfd = 743, |
| 5275 | VADDhd_VSUBhd = 744, |
| 5276 | VADDfq_VSUBfq = 745, |
| 5277 | VADDhq_VSUBhq = 746, |
| 5278 | VLDRH = 747, |
| 5279 | VLDR_FPCXTNS_off_VLDR_FPCXTNS_post_VLDR_FPCXTNS_pre_VLDR_FPCXTS_off_VLDR_FPCXTS_post_VLDR_FPCXTS_pre_VLDR_FPSCR_NZCVQC_off_VLDR_FPSCR_NZCVQC_post_VLDR_FPSCR_NZCVQC_pre_VLDR_FPSCR_off_VLDR_FPSCR_post_VLDR_FPSCR_pre_VLDR_P0_off_VLDR_P0_post_VLDR_P0_pre_VLDR_VPR_off_VLDR_VPR_post_VLDR_VPR_pre = 748, |
| 5280 | VSTRH = 749, |
| 5281 | VSTR_FPCXTNS_off_VSTR_FPCXTNS_post_VSTR_FPCXTNS_pre_VSTR_FPCXTS_off_VSTR_FPCXTS_post_VSTR_FPCXTS_pre_VSTR_FPSCR_NZCVQC_off_VSTR_FPSCR_NZCVQC_post_VSTR_FPSCR_NZCVQC_pre_VSTR_FPSCR_off_VSTR_FPSCR_post_VSTR_FPSCR_pre_VSTR_P0_off_VSTR_P0_post_VSTR_P0_pre_VSTR_VPR_off_VSTR_VPR_post_VSTR_VPR_pre = 750, |
| 5282 | VABAsv2i32_VABAsv4i16_VABAsv8i8_VABAuv2i32_VABAuv4i16_VABAuv8i8 = 751, |
| 5283 | VABDsv2i32_VABDsv4i16_VABDsv8i8_VABDuv2i32_VABDuv4i16_VABDuv8i8 = 752, |
| 5284 | VABDsv16i8_VABDsv4i32_VABDsv8i16_VABDuv16i8_VABDuv4i32_VABDuv8i16 = 753, |
| 5285 | VABDLsv4i32_VABDLsv8i16_VABDLuv4i32_VABDLuv8i16 = 754, |
| 5286 | VADDv1i64_VADDv2i32_VADDv4i16_VADDv8i8 = 755, |
| 5287 | VSUBv1i64_VSUBv2i32_VSUBv4i16_VSUBv8i8 = 756, |
| 5288 | VADDv16i8_VADDv2i64_VADDv4i32_VADDv8i16 = 757, |
| 5289 | VADDLsv2i64_VADDLsv4i32_VADDLsv8i16_VADDLuv2i64_VADDLuv4i32_VADDLuv8i16_VSUBLsv2i64_VSUBLsv4i32_VSUBLsv8i16_VSUBLuv2i64_VSUBLuv4i32_VSUBLuv8i16 = 758, |
| 5290 | VANDd_VBICd_VEORd = 759, |
| 5291 | VANDq_VBICq_VEORq = 760, |
| 5292 | VBICiv2i32_VBICiv4i16 = 761, |
| 5293 | VBICiv4i32_VBICiv8i16 = 762, |
| 5294 | VBIFd_VBITd_VBSLd_VBSPd = 763, |
| 5295 | VBIFq_VBITq_VBSLq_VBSPq = 764, |
| 5296 | VCEQv16i8_VCEQv4i32_VCEQv8i16_VCGEsv16i8_VCGEsv4i32_VCGEsv8i16_VCGEuv16i8_VCGEuv4i32_VCGEuv8i16_VCGTsv16i8_VCGTsv4i32_VCGTsv8i16_VCGTuv16i8_VCGTuv4i32_VCGTuv8i16 = 765, |
| 5297 | VCEQv2i32_VCEQv4i16_VCEQv8i8_VCGEsv2i32_VCGEsv4i16_VCGEsv8i8_VCGEuv2i32_VCGEuv4i16_VCGEuv8i8_VCGTsv2i32_VCGTsv4i16_VCGTsv8i8_VCGTuv2i32_VCGTuv4i16_VCGTuv8i8 = 766, |
| 5298 | VCLZv16i8_VCLZv4i32_VCLZv8i16_VCNTq = 767, |
| 5299 | VCLZv2i32_VCLZv4i16_VCLZv8i8_VCNTd = 768, |
| 5300 | VCMPEH_VCMPEZH_VCMPH_VCMPZH = 769, |
| 5301 | VDUP16d_VDUP32d_VDUP8d = 770, |
| 5302 | VSELEQD_VSELEQH_VSELEQS_VSELGED_VSELGEH_VSELGES_VSELGTD_VSELGTH_VSELGTS_VSELVSD_VSELVSH_VSELVSS = 771, |
| 5303 | VFMAhd_VFMShd = 772, |
| 5304 | VFMAhq_VFMShq = 773, |
| 5305 | VHADDsv2i32_VHADDsv4i16_VHADDsv8i8_VHADDuv2i32_VHADDuv4i16_VHADDuv8i8 = 774, |
| 5306 | VHADDsv16i8_VHADDsv4i32_VHADDsv8i16_VHADDuv16i8_VHADDuv4i32_VHADDuv8i16 = 775, |
| 5307 | VMAXsv16i8_VMAXsv4i32_VMAXsv8i16_VMAXuv16i8_VMAXuv4i32_VMAXuv8i16_VMINsv16i8_VMINsv4i32_VMINsv8i16_VMINuv16i8_VMINuv4i32_VMINuv8i16 = 776, |
| 5308 | VPMAXf_VPMAXh_VPMINf_VPMINh = 777, |
| 5309 | VNEGH = 778, |
| 5310 | VNEGhd = 779, |
| 5311 | VNEGhq = 780, |
| 5312 | VNEGs16d_VNEGs32d_VNEGs8d = 781, |
| 5313 | VNEGs16q_VNEGs32q_VNEGs8q = 782, |
| 5314 | VPADDi16_VPADDi32_VPADDi8 = 783, |
| 5315 | VPADALsv2i32_VPADALsv4i16_VPADALsv8i8_VPADALuv2i32_VPADALuv4i16_VPADALuv8i8 = 784, |
| 5316 | VPADDLsv16i8_VPADDLsv2i32_VPADDLsv4i16_VPADDLsv4i32_VPADDLsv8i16_VPADDLsv8i8_VPADDLuv16i8_VPADDLuv2i32_VPADDLuv4i16_VPADDLuv4i32_VPADDLuv8i16_VPADDLuv8i8 = 785, |
| 5317 | VQABSv2i32_VQABSv4i16_VQABSv8i8 = 786, |
| 5318 | VQABSv16i8_VQABSv4i32_VQABSv8i16 = 787, |
| 5319 | VQDMLALslv2i32_VQDMLALv2i64_VQDMLSLslv2i32_VQDMLSLv2i64 = 788, |
| 5320 | VQDMLALslv4i16_VQDMLALv4i32_VQDMLSLslv4i16_VQDMLSLv4i32 = 789, |
| 5321 | VQDMULHslv2i32_VQDMULHv2i32_VQDMULLv2i64_VQRDMULHslv2i32_VQRDMULHv2i32 = 790, |
| 5322 | VQDMULHslv4i16_VQDMULHv4i16_VQDMULLslv2i32_VQDMULLslv4i16_VQDMULLv4i32_VQRDMULHslv4i16_VQRDMULHv4i16 = 791, |
| 5323 | VQDMULHslv4i32_VQDMULHv4i32_VQRDMULHslv4i32_VQRDMULHv4i32 = 792, |
| 5324 | VQDMULHslv8i16_VQDMULHv8i16_VQRDMULHslv8i16_VQRDMULHv8i16 = 793, |
| 5325 | VQSHRNsv2i32_VQSHRNsv4i16_VQSHRNsv8i8_VQSHRNuv2i32_VQSHRNuv4i16_VQSHRNuv8i8 = 794, |
| 5326 | VRSHLsv16i8_VRSHLsv2i64_VRSHLsv4i32_VRSHLsv8i16_VRSHLuv16i8_VRSHLuv2i64_VRSHLuv4i32_VRSHLuv8i16 = 795, |
| 5327 | VRSHLsv1i64_VRSHLsv2i32_VRSHLsv4i16_VRSHLsv8i8_VRSHLuv1i64_VRSHLuv2i32_VRSHLuv4i16_VRSHLuv8i8_VRSHRsv16i8_VRSHRsv1i64_VRSHRsv2i32_VRSHRsv2i64_VRSHRsv4i16_VRSHRsv4i32_VRSHRsv8i16_VRSHRsv8i8_VRSHRuv16i8_VRSHRuv1i64_VRSHRuv2i32_VRSHRuv2i64_VRSHRuv4i16_VRSHRuv4i32_VRSHRuv8i16_VRSHRuv8i8 = 796, |
| 5328 | VRSHRNv2i32_VRSHRNv4i16_VRSHRNv8i8 = 797, |
| 5329 | VST1d16T_VST1d32T_VST1d64T_VST1d8T = 798, |
| 5330 | VST1d16Q_VST1d32Q_VST1d64Q_VST1d8Q = 799, |
| 5331 | VST1d64QPseudo = 800, |
| 5332 | VST1LNd16_VST1LNd32_VST1LNd8 = 801, |
| 5333 | VST1LNdAsm_16_VST1LNdAsm_32_VST1LNdAsm_8 = 802, |
| 5334 | VST1d64QPseudoWB_fixed_VST1d64QPseudoWB_register = 803, |
| 5335 | VST1LNd16_UPD_VST1LNd32_UPD_VST1LNd8_UPD = 804, |
| 5336 | VST1LNdWB_fixed_Asm_16_VST1LNdWB_fixed_Asm_32_VST1LNdWB_fixed_Asm_8_VST1LNdWB_register_Asm_16_VST1LNdWB_register_Asm_32_VST1LNdWB_register_Asm_8 = 805, |
| 5337 | VST2q16_VST2q32_VST2q8 = 806, |
| 5338 | VST2LNd16_VST2LNd32_VST2LNd8 = 807, |
| 5339 | VST2LNdAsm_16_VST2LNdAsm_32_VST2LNdAsm_8 = 808, |
| 5340 | VST2LNd16Pseudo_VST2LNd32Pseudo_VST2LNd8Pseudo = 809, |
| 5341 | VST2LNq16_VST2LNq32 = 810, |
| 5342 | VST2LNqAsm_16_VST2LNqAsm_32 = 811, |
| 5343 | VST2LNd16_UPD_VST2LNd32_UPD_VST2LNd8_UPD = 812, |
| 5344 | VST2LNdWB_fixed_Asm_16_VST2LNdWB_fixed_Asm_32_VST2LNdWB_fixed_Asm_8_VST2LNdWB_register_Asm_16_VST2LNdWB_register_Asm_32_VST2LNdWB_register_Asm_8 = 813, |
| 5345 | VST2LNd16Pseudo_UPD_VST2LNd32Pseudo_UPD_VST2LNd8Pseudo_UPD = 814, |
| 5346 | VST2LNqWB_fixed_Asm_16_VST2LNqWB_fixed_Asm_32_VST2LNqWB_register_Asm_16_VST2LNqWB_register_Asm_32 = 815, |
| 5347 | VST3d16_VST3d32_VST3d8_VST3q16_VST3q32_VST3q8 = 816, |
| 5348 | VST3dAsm_16_VST3dAsm_32_VST3dAsm_8_VST3qAsm_16_VST3qAsm_32_VST3qAsm_8 = 817, |
| 5349 | VST3d16Pseudo_VST3d32Pseudo_VST3d8Pseudo = 818, |
| 5350 | VST3LNd16_VST3LNd32_VST3LNd8 = 819, |
| 5351 | VST3LNdAsm_16_VST3LNdAsm_32_VST3LNdAsm_8 = 820, |
| 5352 | VST3LNd16Pseudo_VST3LNd32Pseudo_VST3LNd8Pseudo = 821, |
| 5353 | VST3LNqAsm_16_VST3LNqAsm_32 = 822, |
| 5354 | VST3d16_UPD_VST3d32_UPD_VST3d8_UPD_VST3q16_UPD_VST3q32_UPD_VST3q8_UPD = 823, |
| 5355 | VST3dWB_fixed_Asm_16_VST3dWB_fixed_Asm_32_VST3dWB_fixed_Asm_8_VST3dWB_register_Asm_16_VST3dWB_register_Asm_32_VST3dWB_register_Asm_8_VST3qWB_fixed_Asm_16_VST3qWB_fixed_Asm_32_VST3qWB_fixed_Asm_8_VST3qWB_register_Asm_16_VST3qWB_register_Asm_32_VST3qWB_register_Asm_8 = 824, |
| 5356 | VST3LNd16_UPD_VST3LNd32_UPD_VST3LNd8_UPD = 825, |
| 5357 | VST3LNdWB_fixed_Asm_16_VST3LNdWB_fixed_Asm_32_VST3LNdWB_fixed_Asm_8_VST3LNdWB_register_Asm_16_VST3LNdWB_register_Asm_32_VST3LNdWB_register_Asm_8 = 826, |
| 5358 | VST3LNd16Pseudo_UPD_VST3LNd32Pseudo_UPD_VST3LNd8Pseudo_UPD = 827, |
| 5359 | VST3LNqWB_fixed_Asm_16_VST3LNqWB_fixed_Asm_32_VST3LNqWB_register_Asm_16_VST3LNqWB_register_Asm_32 = 828, |
| 5360 | VST4d16_VST4d32_VST4d8_VST4q16_VST4q32_VST4q8 = 829, |
| 5361 | VST4dAsm_16_VST4dAsm_32_VST4dAsm_8_VST4qAsm_16_VST4qAsm_32_VST4qAsm_8 = 830, |
| 5362 | VST4d16Pseudo_VST4d32Pseudo_VST4d8Pseudo = 831, |
| 5363 | VST4LNd16_VST4LNd32_VST4LNd8 = 832, |
| 5364 | VST4LNdAsm_16_VST4LNdAsm_32_VST4LNdAsm_8 = 833, |
| 5365 | VST4LNd16Pseudo_VST4LNd32Pseudo_VST4LNd8Pseudo = 834, |
| 5366 | VST4LNq16_VST4LNq32 = 835, |
| 5367 | VST4LNqAsm_16_VST4LNqAsm_32 = 836, |
| 5368 | VST4d16_UPD_VST4d32_UPD_VST4d8_UPD_VST4q16_UPD_VST4q32_UPD_VST4q8_UPD = 837, |
| 5369 | VST4dWB_fixed_Asm_16_VST4dWB_fixed_Asm_32_VST4dWB_fixed_Asm_8_VST4dWB_register_Asm_16_VST4dWB_register_Asm_32_VST4dWB_register_Asm_8_VST4qWB_fixed_Asm_16_VST4qWB_fixed_Asm_32_VST4qWB_fixed_Asm_8_VST4qWB_register_Asm_16_VST4qWB_register_Asm_32_VST4qWB_register_Asm_8 = 838, |
| 5370 | VST4LNd16_UPD_VST4LNd32_UPD_VST4LNd8_UPD = 839, |
| 5371 | VST4LNdWB_fixed_Asm_16_VST4LNdWB_fixed_Asm_32_VST4LNdWB_fixed_Asm_8_VST4LNdWB_register_Asm_16_VST4LNdWB_register_Asm_32_VST4LNdWB_register_Asm_8 = 840, |
| 5372 | VST4LNd16Pseudo_UPD_VST4LNd32Pseudo_UPD_VST4LNd8Pseudo_UPD = 841, |
| 5373 | VST4LNqWB_fixed_Asm_16_VST4LNqWB_fixed_Asm_32_VST4LNqWB_register_Asm_16_VST4LNqWB_register_Asm_32 = 842, |
| 5374 | BKPT_tBKPT_CDP_CDP2_t2CDP_t2CDP2_CLREX_t2CLREX_CONSTPOOL_ENTRY_COPY_STRUCT_BYVAL_I32_CPS1p_CPS2p_CPS3p_t2CPS1p_t2CPS2p_t2CPS3p_DBG_t2DBG_DMB_t2DMB_DSB_t2DSB_ERET_HINT_t2HINT_tHINT_HLT_tHLT_HVC_ISB_t2ISB_SETEND_tSETEND_SETPAN_t2SETPAN_SMC_t2SMC_SPACE_SWP_SWPB_TRAP_TRAPNaCl_UDF_t2DCPS1_t2DCPS2_t2DCPS3_t2SG_t2TT_t2TTA_t2TTAT_t2TTT_tCPS_CMP_SWAP_16_CMP_SWAP_32_CMP_SWAP_64_CMP_SWAP_8 = 843, |
| 5375 | t2HVC_tTRAP_SVC_tSVC = 844, |
| 5376 | t2UDF_tUDF_t__brkdiv0 = 845, |
| 5377 | LDC2L_OFFSET_LDC2L_OPTION_LDC2L_POST_LDC2L_PRE_LDC2_OFFSET_LDC2_OPTION_LDC2_POST_LDC2_PRE_LDCL_OFFSET_LDCL_OPTION_LDCL_POST_LDCL_PRE_LDC_OFFSET_LDC_OPTION_LDC_POST_LDC_PRE_STC2L_OFFSET_STC2L_OPTION_STC2L_POST_STC2L_PRE_STC2_OFFSET_STC2_OPTION_STC2_POST_STC2_PRE_STCL_OFFSET_STCL_OPTION_STCL_POST_STCL_PRE_STC_OFFSET_STC_OPTION_STC_POST_STC_PRE_t2STC2L_OFFSET_t2STC2L_OPTION_t2STC2L_POST_t2STC2L_PRE_t2STC2_OFFSET_t2STC2_OPTION_t2STC2_POST_t2STC2_PRE_t2STCL_OFFSET_t2STCL_OPTION_t2STCL_POST_t2STCL_PRE_t2STC_OFFSET_t2STC_OPTION_t2STC_POST_t2STC_PRE_MEMCPY = 846, |
| 5378 | t2LDC2L_OFFSET_t2LDC2L_OPTION_t2LDC2L_POST_t2LDC2L_PRE_t2LDC2_OFFSET_t2LDC2_OPTION_t2LDC2_POST_t2LDC2_PRE_t2LDCL_OFFSET_t2LDCL_OPTION_t2LDCL_POST_t2LDCL_PRE_t2LDC_OFFSET_t2LDC_OPTION_t2LDC_POST_t2LDC_PRE = 847, |
| 5379 | LDREX_LDREXB_LDREXD_LDREXH = 848, |
| 5380 | MCR_MCR2_MCRR_MCRR2_t2MCR_t2MCR2_t2MCRR_t2MCRR2_MRC_MRC2_t2MRC_t2MRC2_MRRC_MRRC2_t2MRRC_t2MRRC2_t2MRS_AR_t2MRS_M_t2MRSbanked_t2MRSsys_AR_t2MSR_AR_t2MSR_M_t2MSRbanked = 849, |
| 5381 | FLDMXDB_UPD_FLDMXIA_FLDMXIA_UPD_FSTMXDB_UPD_FSTMXIA_FSTMXIA_UPD = 850, |
| 5382 | ADJCALLSTACKDOWN_tADJCALLSTACKDOWN_ADJCALLSTACKUP_tADJCALLSTACKUP_Int_eh_sjlj_dispatchsetup_Int_eh_sjlj_longjmp_Int_eh_sjlj_setjmp_Int_eh_sjlj_setjmp_nofp_Int_eh_sjlj_setup_dispatch_t2Int_eh_sjlj_setjmp_t2Int_eh_sjlj_setjmp_nofp_tInt_eh_sjlj_longjmp_tInt_eh_sjlj_setjmp_t2SUBS_PC_LR_JUMPTABLE_ADDRS_JUMPTABLE_INSTS_JUMPTABLE_TBB_JUMPTABLE_TBH_tInt_WIN_eh_sjlj_longjmp_VLD1LNdAsm_16_VLD1LNdAsm_32_VLD1LNdAsm_8_VLD1LNdWB_fixed_Asm_16_VLD1LNdWB_fixed_Asm_32_VLD1LNdWB_fixed_Asm_8_VLD1LNdWB_register_Asm_16_VLD1LNdWB_register_Asm_32_VLD1LNdWB_register_Asm_8_VLD2LNdAsm_16_VLD2LNdAsm_32_VLD2LNdAsm_8_VLD2LNdWB_fixed_Asm_16_VLD2LNdWB_fixed_Asm_32_VLD2LNdWB_fixed_Asm_8_VLD2LNdWB_register_Asm_16_VLD2LNdWB_register_Asm_32_VLD2LNdWB_register_Asm_8_VLD2LNqAsm_16_VLD2LNqAsm_32_VLD2LNqWB_fixed_Asm_16_VLD2LNqWB_fixed_Asm_32_VLD2LNqWB_register_Asm_16_VLD2LNqWB_register_Asm_32_VLD3DUPdAsm_16_VLD3DUPdAsm_32_VLD3DUPdAsm_8_VLD3DUPdWB_fixed_Asm_16_VLD3DUPdWB_fixed_Asm_32_VLD3DUPdWB_fixed_Asm_8_VLD3DUPdWB_register_Asm_16_VLD3DUPdWB_register_Asm_32_VLD3DUPdWB_register_Asm_8_VLD3DUPqAsm_16_VLD3DUPqAsm_32_VLD3DUPqAsm_8_VLD3DUPqWB_fixed_Asm_16_VLD3DUPqWB_fixed_Asm_32_VLD3DUPqWB_fixed_Asm_8_VLD3DUPqWB_register_Asm_16_VLD3DUPqWB_register_Asm_32_VLD3DUPqWB_register_Asm_8_VLD3LNdAsm_16_VLD3LNdAsm_32_VLD3LNdAsm_8_VLD3LNdWB_fixed_Asm_16_VLD3LNdWB_fixed_Asm_32_VLD3LNdWB_fixed_Asm_8_VLD3LNdWB_register_Asm_16_VLD3LNdWB_register_Asm_32_VLD3LNdWB_register_Asm_8_VLD3LNqAsm_16_VLD3LNqAsm_32_VLD3LNqWB_fixed_Asm_16_VLD3LNqWB_fixed_Asm_32_VLD3LNqWB_register_Asm_16_VLD3LNqWB_register_Asm_32_VLD3dAsm_16_VLD3dAsm_32_VLD3dAsm_8_VLD3dWB_fixed_Asm_16_VLD3dWB_fixed_Asm_32_VLD3dWB_fixed_Asm_8_VLD3dWB_register_Asm_16_VLD3dWB_register_Asm_32_VLD3dWB_register_Asm_8_VLD3qAsm_16_VLD3qAsm_32_VLD3qAsm_8_VLD3qWB_fixed_Asm_16_VLD3qWB_fixed_Asm_32_VLD3qWB_fixed_Asm_8_VLD3qWB_register_Asm_16_VLD3qWB_register_Asm_32_VLD3qWB_register_Asm_8_VLD4DUPdAsm_16_VLD4DUPdAsm_32_VLD4DUPdAsm_8_VLD4DUPdWB_fixed_Asm_16_VLD4DUPdWB_fixed_Asm_32_VLD4DUPdWB_fixed_Asm_8_VLD4DUPdWB_register_Asm_16_VLD4DUPdWB_register_Asm_32_VLD4DUPdWB_register_Asm_8_VLD4DUPqAsm_16_VLD4DUPqAsm_32_VLD4DUPqAsm_8_VLD4DUPqWB_fixed_Asm_16_VLD4DUPqWB_fixed_Asm_32_VLD4DUPqWB_fixed_Asm_8_VLD4DUPqWB_register_Asm_16_VLD4DUPqWB_register_Asm_32_VLD4DUPqWB_register_Asm_8_VLD4LNdAsm_16_VLD4LNdAsm_32_VLD4LNdAsm_8_VLD4LNdWB_fixed_Asm_16_VLD4LNdWB_fixed_Asm_32_VLD4LNdWB_fixed_Asm_8_VLD4LNdWB_register_Asm_16_VLD4LNdWB_register_Asm_32_VLD4LNdWB_register_Asm_8_VLD4LNqAsm_16_VLD4LNqAsm_32_VLD4LNqWB_fixed_Asm_16_VLD4LNqWB_fixed_Asm_32_VLD4LNqWB_register_Asm_16_VLD4LNqWB_register_Asm_32_VLD4dAsm_16_VLD4dAsm_32_VLD4dAsm_8_VLD4dWB_fixed_Asm_16_VLD4dWB_fixed_Asm_32_VLD4dWB_fixed_Asm_8_VLD4dWB_register_Asm_16_VLD4dWB_register_Asm_32_VLD4dWB_register_Asm_8_VLD4qAsm_16_VLD4qAsm_32_VLD4qAsm_8_VLD4qWB_fixed_Asm_16_VLD4qWB_fixed_Asm_32_VLD4qWB_fixed_Asm_8_VLD4qWB_register_Asm_16_VLD4qWB_register_Asm_32_VLD4qWB_register_Asm_8_WIN__CHKSTK_WIN__DBZCHK = 851, |
| 5383 | SUBS_PC_LR = 852, |
| 5384 | B_t2B_tB_BX_CALL_tBXNS_RET_tBX_CALL_tBX_RET_tBX_RET_vararg_BX_BX_RET_BX_pred_tBX_tBXNS_Bcc_t2Bcc_tBcc_TAILJMPd_TAILJMPr_TAILJMPr4_tTAILJMPd_tTAILJMPdND_tTAILJMPr_TCRETURNdi_TCRETURNri_TCRETURNrinotr12_tCBNZ_tCBZ = 853, |
| 5385 | BXJ = 854, |
| 5386 | tBfar = 855, |
| 5387 | BL_tBL_BL_pred_tBLXi = 856, |
| 5388 | BLXi = 857, |
| 5389 | TPsoft_tTPsoft = 858, |
| 5390 | BLX_noip_BLX_pred_noip_BLX_BLX_pred_tBLXr_noip_tBLXNSr_tBLXr = 859, |
| 5391 | BCCi64_BCCZi64 = 860, |
| 5392 | BR_JTadd_tBR_JTr_t2TBB_t2TBH = 861, |
| 5393 | BR_JTr_t2BR_JT_t2TBB_JT_t2TBH_JT_tBRIND = 862, |
| 5394 | t2BXJ = 863, |
| 5395 | BR_JTm_i12_BR_JTm_rs = 864, |
| 5396 | tADDframe = 865, |
| 5397 | MOVi16_ga_pcrel_MOVi_MOVi16_MOVCCi16_tMOVi8 = 866, |
| 5398 | MOVr_MOVr_TC_tMOVSr_tMOVr = 867, |
| 5399 | MVNCCi_MOVCCi = 868, |
| 5400 | BMOVPCB_CALL_BMOVPCRX_CALL = 869, |
| 5401 | MOVCCr = 870, |
| 5402 | tMOVCCr_pseudo_tMOVi32imm = 871, |
| 5403 | tMVN = 872, |
| 5404 | MOVCCsi = 873, |
| 5405 | t2ASRri_tASRri_t2LSRri_tLSRri_t2LSLri_tLSLri_t2RORri_t2RRX = 874, |
| 5406 | LSRi_LSLi = 875, |
| 5407 | t2MOVCCasr_t2MOVCClsl_t2MOVCClsr_t2MOVCCror = 876, |
| 5408 | t2MOVCCr = 877, |
| 5409 | t2MOVTi16_ga_pcrel_t2MOVTi16 = 878, |
| 5410 | t2MOVr = 879, |
| 5411 | tROR = 880, |
| 5412 | t2ASRrr_tASRrr_t2LSRrr_tLSRrr_t2LSLrr_tLSLrr_t2RORrr = 881, |
| 5413 | MOVPCRX_MOVPCLR = 882, |
| 5414 | tMUL = 883, |
| 5415 | SADD16_SADD8_SSUB16_SSUB8_UADD16_UADD8_USUB16_USUB8 = 884, |
| 5416 | t2SADD16_t2SADD8_t2SSUB16_t2SSUB8_t2UADD16_t2UADD8_t2USUB16_t2USUB8 = 885, |
| 5417 | SHADD16_SHADD8_SHSUB16_SHSUB8_UHADD16_UHADD8_UHSUB16_UHSUB8 = 886, |
| 5418 | t2SHADD16_t2SHADD8_t2SHSUB16_t2SHSUB8_t2UHADD16_t2UHADD8_t2UHSUB16_t2UHSUB8 = 887, |
| 5419 | QADD16_QADD8_QSUB16_QSUB8_UQADD16_UQADD8_UQSUB16_UQSUB8 = 888, |
| 5420 | t2QADD_t2QADD16_t2QADD8_t2UQADD16_t2UQADD8_t2QSUB_t2QSUB16_t2QSUB8_t2UQSUB16_t2UQSUB8 = 889, |
| 5421 | QASX_QSAX_UQASX_UQSAX = 890, |
| 5422 | t2QASX_t2QSAX_t2UQASX_t2UQSAX = 891, |
| 5423 | SSAT_SSAT16_USAT_USAT16 = 892, |
| 5424 | QADD_QSUB = 893, |
| 5425 | SBFX_UBFX = 894, |
| 5426 | t2SBFX_t2UBFX = 895, |
| 5427 | SXTB_SXTH_UXTB_UXTH = 896, |
| 5428 | t2SXTB_t2SXTH_t2UXTB_t2UXTH = 897, |
| 5429 | tSXTB_tSXTH_tUXTB_tUXTH = 898, |
| 5430 | SXTAB_SXTAH_UXTAB_UXTAH = 899, |
| 5431 | t2SXTAB_t2SXTAH_t2UXTAB_t2UXTAH = 900, |
| 5432 | LDRConstPool_t2LDRConstPool_tLDRConstPool = 901, |
| 5433 | PICLDRB_PICLDRH = 902, |
| 5434 | PICLDRSB_PICLDRSH = 903, |
| 5435 | tLDR_postidx = 904, |
| 5436 | tLDRBi_tLDRHi = 905, |
| 5437 | tLDRi_tLDRpci_tLDRspi = 906, |
| 5438 | t2LDRBpcrel_t2LDRHpcrel_t2LDRpcrel = 907, |
| 5439 | LDR_PRE_IMM = 908, |
| 5440 | LDRB_PRE_IMM = 909, |
| 5441 | t2LDRB_PRE_imm = 910, |
| 5442 | t2LDRB_PRE = 911, |
| 5443 | LDR_PRE_REG = 912, |
| 5444 | LDRB_PRE_REG = 913, |
| 5445 | LDRH_PRE = 914, |
| 5446 | LDRSB_PRE_LDRSH_PRE = 915, |
| 5447 | t2LDRH_PRE_imm_t2LDR_PRE_imm = 916, |
| 5448 | t2LDRSB_PRE_imm_t2LDRSH_PRE_imm = 917, |
| 5449 | t2LDRH_PRE = 918, |
| 5450 | t2LDRSB_PRE_t2LDRSH_PRE = 919, |
| 5451 | t2LDR_PRE = 920, |
| 5452 | LDRD_PRE = 921, |
| 5453 | t2LDRD_PRE = 922, |
| 5454 | LDRT_POST_IMM = 923, |
| 5455 | LDRBT_POST_IMM = 924, |
| 5456 | LDRHTi = 925, |
| 5457 | LDRSBTi_LDRSHTi = 926, |
| 5458 | t2LDRB_POST_imm = 927, |
| 5459 | t2LDRB_POST = 928, |
| 5460 | LDRH_POST = 929, |
| 5461 | LDRSB_POST_LDRSH_POST = 930, |
| 5462 | LDR_POST_REG = 931, |
| 5463 | LDRB_POST_REG = 932, |
| 5464 | LDRT_POST = 933, |
| 5465 | PLDi12_t2PLDi12_PLDWi12_t2PLDWi12_t2PLDWi8_t2PLDWs_t2PLDi8_t2PLDpci_t2PLDs_PLIi12_PLIrs_t2PLIi12_t2PLIi8_t2PLIpci_t2PLIs = 934, |
| 5466 | PLDrs_PLDWrs = 935, |
| 5467 | VLLDM_VLLDM_T2 = 936, |
| 5468 | STRBi12_PICSTRB_PICSTRH = 937, |
| 5469 | t2STRBT = 938, |
| 5470 | STR_PRE_IMM = 939, |
| 5471 | STRB_PRE_IMM = 940, |
| 5472 | STRBi_preidx_STRBr_preidx_STRi_preidx_STRr_preidx_STRH_preidx = 941, |
| 5473 | t2STRH_PRE_imm_t2STRB_PRE_imm_t2STR_PRE_imm = 942, |
| 5474 | STRH_PRE = 943, |
| 5475 | t2STRH_PRE_t2STR_PRE = 944, |
| 5476 | t2STRB_PRE = 945, |
| 5477 | t2STRD_PRE = 946, |
| 5478 | STR_PRE_REG = 947, |
| 5479 | STRB_PRE_REG = 948, |
| 5480 | STRD_PRE = 949, |
| 5481 | STRT_POST_IMM = 950, |
| 5482 | STRBT_POST_IMM = 951, |
| 5483 | t2STRB_POST_imm_t2STR_POST_imm = 952, |
| 5484 | t2STRB_POST = 953, |
| 5485 | STRBT_POST_REG_STRB_POST_REG = 954, |
| 5486 | STRBT_POST_STRT_POST = 955, |
| 5487 | VLSTM_VLSTM_T2 = 956, |
| 5488 | VCVTASD_VCVTASH_VCVTASS_VCVTAUD_VCVTAUH_VCVTAUS_VCVTMSD_VCVTMSH_VCVTMSS_VCVTMUD_VCVTMUH_VCVTMUS_VCVTNSD_VCVTNSH_VCVTNSS_VCVTNUD_VCVTNUH_VCVTNUS_VCVTPSD_VCVTPSH_VCVTPSS_VCVTPUD_VCVTPUH_VCVTPUS_VCVTBDH_VCVTTDH_VCVTTHD = 957, |
| 5489 | VTOSLS_VTOUHS_VTOULS = 958, |
| 5490 | VJCVT = 959, |
| 5491 | VRINTAD_VRINTAH_VRINTAS_VRINTMD_VRINTMH_VRINTMS_VRINTND_VRINTNH_VRINTNS_VRINTPD_VRINTPH_VRINTPS_VRINTRD_VRINTRH_VRINTRS_VRINTXD_VRINTXH_VRINTXS_VRINTZD_VRINTZH_VRINTZS = 960, |
| 5492 | VSQRTH = 961, |
| 5493 | VMAXsv2i32_VMAXsv4i16_VMAXsv8i8_VMAXuv2i32_VMAXuv4i16_VMAXuv8i8_VMINsv2i32_VMINsv4i16_VMINsv8i8_VMINuv2i32_VMINuv4i16_VMINuv8i8 = 962, |
| 5494 | VUDOTD_VUDOTDI_VSDOTD_VSDOTDI_VUDOTQ_VUDOTQI_VSDOTQ_VSDOTQI = 963, |
| 5495 | FCONSTD = 964, |
| 5496 | FCONSTH = 965, |
| 5497 | FCONSTS = 966, |
| 5498 | VMOVHcc_VMOVH = 967, |
| 5499 | VINSH = 968, |
| 5500 | VSTMSIA = 969, |
| 5501 | VSTMSDB_UPD_VSTMSIA_UPD = 970, |
| 5502 | VRHADDsv16i8_VRHADDsv4i32_VRHADDsv8i16_VRHADDuv16i8_VRHADDuv4i32_VRHADDuv8i16 = 971, |
| 5503 | VRHADDsv2i32_VRHADDsv4i16_VRHADDsv8i8_VRHADDuv2i32_VRHADDuv4i16_VRHADDuv8i8 = 972, |
| 5504 | VMVNv2i32_VMVNv4i16_VMVNv4i32_VMVNv8i16 = 973, |
| 5505 | VMULpd_VMULv4i16_VMULv8i8_VMULslv4i16 = 974, |
| 5506 | VMULv2i32_VMULslv2i32 = 975, |
| 5507 | VQDMULHslv2i32_VQDMULHv2i32_VQRDMULHslv2i32_VQRDMULHv2i32 = 976, |
| 5508 | VQDMULHslv4i16_VQDMULHv4i16_VQRDMULHslv4i16_VQRDMULHv4i16 = 977, |
| 5509 | VMULpq_VMULv16i8_VMULv8i16_VMULslv8i16 = 978, |
| 5510 | VMLAslv2i32_VMLAv2i32_VMLSslv2i32_VMLSv2i32 = 979, |
| 5511 | VMLAslv4i16_VMLAv4i16_VMLAv8i8_VMLSslv4i16_VMLSv4i16_VMLSv8i8 = 980, |
| 5512 | VQRDMLAHslv2i32_VQRDMLAHv2i32_VQRDMLSHslv2i32_VQRDMLSHv2i32 = 981, |
| 5513 | VQRDMLAHslv4i16_VQRDMLAHv4i16_VQRDMLSHslv4i16_VQRDMLSHv4i16 = 982, |
| 5514 | VQRDMLAHslv4i32_VQRDMLAHv4i32_VQRDMLSHslv4i32_VQRDMLSHv4i32 = 983, |
| 5515 | VQRDMLAHslv8i16_VQRDMLAHv8i16_VQRDMLSHslv8i16_VQRDMLSHv8i16 = 984, |
| 5516 | VMULLp8_VMULLslsv2i32_VMULLslsv4i16_VMULLsluv2i32_VMULLsluv4i16_VMULLsv4i32_VMULLsv8i16_VMULLuv4i32_VMULLuv8i16 = 985, |
| 5517 | VSHLiv16i8_VSHLiv1i64_VSHLiv2i32_VSHLiv2i64_VSHLiv4i16_VSHLiv4i32_VSHLiv8i16_VSHLiv8i8_VSHLLi16_VSHLLi32_VSHLLi8_VSHLLsv2i64_VSHLLsv4i32_VSHLLsv8i16_VSHLLuv2i64_VSHLLuv4i32_VSHLLuv8i16_VSHRsv16i8_VSHRsv1i64_VSHRsv2i32_VSHRsv2i64_VSHRsv4i16_VSHRsv4i32_VSHRsv8i16_VSHRsv8i8_VSHRuv16i8_VSHRuv1i64_VSHRuv2i32_VSHRuv2i64_VSHRuv4i16_VSHRuv4i32_VSHRuv8i16_VSHRuv8i8 = 986, |
| 5518 | VQSHLsiv16i8_VQSHLsiv1i64_VQSHLsiv2i32_VQSHLsiv2i64_VQSHLsiv4i16_VQSHLsiv4i32_VQSHLsiv8i16_VQSHLsiv8i8_VQSHLsuv16i8_VQSHLsuv1i64_VQSHLsuv2i32_VQSHLsuv2i64_VQSHLsuv4i16_VQSHLsuv4i32_VQSHLsuv8i16_VQSHLsuv8i8_VQSHLuiv16i8_VQSHLuiv1i64_VQSHLuiv2i32_VQSHLuiv2i64_VQSHLuiv4i16_VQSHLuiv4i32_VQSHLuiv8i16_VQSHLuiv8i8 = 987, |
| 5519 | VRSHRsv16i8_VRSHRsv1i64_VRSHRsv2i32_VRSHRsv2i64_VRSHRsv4i16_VRSHRsv4i32_VRSHRsv8i16_VRSHRsv8i8_VRSHRuv16i8_VRSHRuv1i64_VRSHRuv2i32_VRSHRuv2i64_VRSHRuv4i16_VRSHRuv4i32_VRSHRuv8i16_VRSHRuv8i8 = 988, |
| 5520 | VSLIv1i64_VSLIv2i32_VSLIv4i16_VSLIv8i8_VSRIv1i64_VSRIv2i32_VSRIv4i16_VSRIv8i8 = 989, |
| 5521 | VSLIv16i8_VSLIv2i64_VSLIv4i32_VSLIv8i16_VSRIv16i8_VSRIv2i64_VSRIv4i32_VSRIv8i16 = 990, |
| 5522 | VPADDh = 991, |
| 5523 | VCADDv2f32_VCADDv4f16_VCMLAv2f32_VCMLAv2f32_indexed_VCMLAv4f16_VCMLAv4f16_indexed = 992, |
| 5524 | VCADDv4f32_VCADDv8f16_VCMLAv4f32_VCMLAv4f32_indexed_VCMLAv8f16_VCMLAv8f16_indexed = 993, |
| 5525 | VCVTf2sd_VCVTf2ud_VCVTf2xsd_VCVTf2xud_VCVTs2fd_VCVTu2fd_VCVTxs2fd_VCVTxu2fd = 994, |
| 5526 | VCVTf2sq_VCVTf2uq_VCVTs2fq_VCVTu2fq_VCVTf2xsq_VCVTf2xuq_VCVTxs2fq_VCVTxu2fq = 995, |
| 5527 | NEON_VMAXNMNDf_NEON_VMAXNMNDh_NEON_VMAXNMNQf_NEON_VMAXNMNQh_VFP_VMAXNMD_VFP_VMAXNMH_VFP_VMAXNMS_NEON_VMINNMNDf_NEON_VMINNMNDh_NEON_VMINNMNQf_NEON_VMINNMNQh_VFP_VMINNMD_VFP_VMINNMH_VFP_VMINNMS = 996, |
| 5528 | VMULhd = 997, |
| 5529 | VMULhq = 998, |
| 5530 | VRINTANDf_VRINTANDh_VRINTANQf_VRINTANQh_VRINTMNDf_VRINTMNDh_VRINTMNQf_VRINTMNQh_VRINTNNDf_VRINTNNDh_VRINTNNQf_VRINTNNQh_VRINTPNDf_VRINTPNDh_VRINTPNQf_VRINTPNQh_VRINTXNDf_VRINTXNDh_VRINTXNQf_VRINTXNQh_VRINTZNDf_VRINTZNDh_VRINTZNQf_VRINTZNQh = 999, |
| 5531 | VMOVD0_VMOVQ0 = 1000, |
| 5532 | VTRNd16_VTRNd32_VTRNd8 = 1001, |
| 5533 | VLD2d16_VLD2d32_VLD2d8 = 1002, |
| 5534 | VLD2d16wb_fixed_VLD2d16wb_register_VLD2d32wb_fixed_VLD2d32wb_register_VLD2d8wb_fixed_VLD2d8wb_register = 1003, |
| 5535 | VLD3LNd32_VLD3LNq32_VLD3LNd32Pseudo_VLD3LNq32Pseudo = 1004, |
| 5536 | VLD3LNd32_UPD_VLD3LNq32_UPD = 1005, |
| 5537 | VLD3LNd32Pseudo_UPD_VLD3LNq32Pseudo_UPD = 1006, |
| 5538 | VLD4LNd32_VLD4LNq32_VLD4LNd32Pseudo_VLD4LNq32Pseudo = 1007, |
| 5539 | VLD4LNd32_UPD_VLD4LNq32_UPD = 1008, |
| 5540 | VLD4LNd32Pseudo_UPD_VLD4LNq32Pseudo_UPD = 1009, |
| 5541 | AESD_AESE_AESIMC_AESMC = 1010, |
| 5542 | SHA1SU0 = 1011, |
| 5543 | SHA1H_SHA1SU1 = 1012, |
| 5544 | SHA1C_SHA1M_SHA1P = 1013, |
| 5545 | SHA256SU0 = 1014, |
| 5546 | SHA256H_SHA256H2_SHA256SU1 = 1015, |
| 5547 | t2LDMIA_RET = 1016, |
| 5548 | tLDMIA_UPD_t2LDMDB_UPD_t2LDMIA_UPD = 1017, |
| 5549 | t2LDMDB_t2LDMIA_tLDMIA = 1018, |
| 5550 | t2LDRB_OFFSET_imm_t2LDRH_OFFSET_imm_t2LDRSB_OFFSET_imm_t2LDRSH_OFFSET_imm = 1019, |
| 5551 | t2LDRConstPool_tLDRConstPool = 1020, |
| 5552 | t2LDRLIT_ga_pcrel = 1021, |
| 5553 | tLDRLIT_ga_abs = 1022, |
| 5554 | tLDRLIT_ga_pcrel = 1023, |
| 5555 | t2LDREX_t2LDREXB_t2LDREXD_t2LDREXH = 1024, |
| 5556 | t2STMDB_t2STMIA = 1025, |
| 5557 | t2STMDB_UPD_t2STMIA_UPD_tSTMIA_UPD = 1026, |
| 5558 | tMOVSr_tMOVr = 1027, |
| 5559 | tMOVi8 = 1028, |
| 5560 | t2MSR_AR_t2MSR_M_t2MSRbanked_t2MRS_AR_t2MRS_M_t2MRSbanked_t2MRSsys_AR = 1029, |
| 5561 | t2CLREX = 1030, |
| 5562 | t2SMLAL_t2SMLALBB_t2SMLALBT_t2SMLALD_t2SMLALDX_t2SMLALTB_t2SMLALTT_t2SMLSLD_t2SMLSLDX = 1031, |
| 5563 | t2REV_t2REV16_t2REVSH_tREV_tREV16_tREVSH = 1032, |
| 5564 | t2CDP_t2CDP2 = 1033, |
| 5565 | t2MCR_t2MCR2_t2MCRR_t2MCRR2_t2MRC_t2MRC2_t2MRRC_t2MRRC2 = 1034, |
| 5566 | t2STC2L_OFFSET_t2STC2L_OPTION_t2STC2L_POST_t2STC2L_PRE_t2STC2_OFFSET_t2STC2_OPTION_t2STC2_POST_t2STC2_PRE_t2STCL_OFFSET_t2STCL_OPTION_t2STCL_POST_t2STCL_PRE_t2STC_OFFSET_t2STC_OPTION_t2STC_POST_t2STC_PRE = 1035, |
| 5567 | tCPS_t2ISB_t2DSB_t2DMB_t2HINT_tHINT = 1036, |
| 5568 | t2UDF_tUDF = 1037, |
| 5569 | tBKPT_t2DBG = 1038, |
| 5570 | Int_eh_sjlj_dispatchsetup_Int_eh_sjlj_longjmp_Int_eh_sjlj_setjmp_Int_eh_sjlj_setjmp_nofp_Int_eh_sjlj_setup_dispatch_t2Int_eh_sjlj_setjmp_t2Int_eh_sjlj_setjmp_nofp_tInt_eh_sjlj_longjmp_tInt_eh_sjlj_setjmp_ADJCALLSTACKDOWN_ADJCALLSTACKUP_tADJCALLSTACKDOWN_tADJCALLSTACKUP = 1039, |
| 5571 | CMP_SWAP_16_CMP_SWAP_32_CMP_SWAP_64_CMP_SWAP_8 = 1040, |
| 5572 | JUMPTABLE_ADDRS_JUMPTABLE_INSTS_JUMPTABLE_TBB_JUMPTABLE_TBH = 1041, |
| 5573 | MEMCPY = 1042, |
| 5574 | VSETLNi32 = 1043, |
| 5575 | VGETLNi32 = 1044, |
| 5576 | VLD1LNdAsm_16_VLD1LNdAsm_32_VLD1LNdAsm_8_VLD1LNdWB_fixed_Asm_16_VLD1LNdWB_fixed_Asm_32_VLD1LNdWB_fixed_Asm_8_VLD1LNdWB_register_Asm_16_VLD1LNdWB_register_Asm_32_VLD1LNdWB_register_Asm_8_VLD2LNdAsm_16_VLD2LNdAsm_32_VLD2LNdAsm_8_VLD2LNdWB_fixed_Asm_16_VLD2LNdWB_fixed_Asm_32_VLD2LNdWB_fixed_Asm_8_VLD2LNdWB_register_Asm_16_VLD2LNdWB_register_Asm_32_VLD2LNdWB_register_Asm_8_VLD2LNqAsm_16_VLD2LNqAsm_32_VLD2LNqWB_fixed_Asm_16_VLD2LNqWB_fixed_Asm_32_VLD2LNqWB_register_Asm_16_VLD2LNqWB_register_Asm_32_VLD3DUPdAsm_16_VLD3DUPdAsm_32_VLD3DUPdAsm_8_VLD3DUPdWB_fixed_Asm_16_VLD3DUPdWB_fixed_Asm_32_VLD3DUPdWB_fixed_Asm_8_VLD3DUPdWB_register_Asm_16_VLD3DUPdWB_register_Asm_32_VLD3DUPdWB_register_Asm_8_VLD3DUPqAsm_16_VLD3DUPqAsm_32_VLD3DUPqAsm_8_VLD3DUPqWB_fixed_Asm_16_VLD3DUPqWB_fixed_Asm_32_VLD3DUPqWB_fixed_Asm_8_VLD3DUPqWB_register_Asm_16_VLD3DUPqWB_register_Asm_32_VLD3DUPqWB_register_Asm_8_VLD3LNdAsm_16_VLD3LNdAsm_32_VLD3LNdAsm_8_VLD3LNdWB_fixed_Asm_16_VLD3LNdWB_fixed_Asm_32_VLD3LNdWB_fixed_Asm_8_VLD3LNdWB_register_Asm_16_VLD3LNdWB_register_Asm_32_VLD3LNdWB_register_Asm_8_VLD3LNqAsm_16_VLD3LNqAsm_32_VLD3LNqWB_fixed_Asm_16_VLD3LNqWB_fixed_Asm_32_VLD3LNqWB_register_Asm_16_VLD3LNqWB_register_Asm_32_VLD3dAsm_16_VLD3dAsm_32_VLD3dAsm_8_VLD3dWB_fixed_Asm_16_VLD3dWB_fixed_Asm_32_VLD3dWB_fixed_Asm_8_VLD3dWB_register_Asm_16_VLD3dWB_register_Asm_32_VLD3dWB_register_Asm_8_VLD3qAsm_16_VLD3qAsm_32_VLD3qAsm_8_VLD3qWB_fixed_Asm_16_VLD3qWB_fixed_Asm_32_VLD3qWB_fixed_Asm_8_VLD3qWB_register_Asm_16_VLD3qWB_register_Asm_32_VLD3qWB_register_Asm_8_VLD4DUPdAsm_16_VLD4DUPdAsm_32_VLD4DUPdAsm_8_VLD4DUPdWB_fixed_Asm_16_VLD4DUPdWB_fixed_Asm_32_VLD4DUPdWB_fixed_Asm_8_VLD4DUPdWB_register_Asm_16_VLD4DUPdWB_register_Asm_32_VLD4DUPdWB_register_Asm_8_VLD4DUPqAsm_16_VLD4DUPqAsm_32_VLD4DUPqAsm_8_VLD4DUPqWB_fixed_Asm_16_VLD4DUPqWB_fixed_Asm_32_VLD4DUPqWB_fixed_Asm_8_VLD4DUPqWB_register_Asm_16_VLD4DUPqWB_register_Asm_32_VLD4DUPqWB_register_Asm_8_VLD4LNdAsm_16_VLD4LNdAsm_32_VLD4LNdAsm_8_VLD4LNdWB_fixed_Asm_16_VLD4LNdWB_fixed_Asm_32_VLD4LNdWB_fixed_Asm_8_VLD4LNdWB_register_Asm_16_VLD4LNdWB_register_Asm_32_VLD4LNdWB_register_Asm_8_VLD4LNqAsm_16_VLD4LNqAsm_32_VLD4LNqWB_fixed_Asm_16_VLD4LNqWB_fixed_Asm_32_VLD4LNqWB_register_Asm_16_VLD4LNqWB_register_Asm_32_VLD4dAsm_16_VLD4dAsm_32_VLD4dAsm_8_VLD4dWB_fixed_Asm_16_VLD4dWB_fixed_Asm_32_VLD4dWB_fixed_Asm_8_VLD4dWB_register_Asm_16_VLD4dWB_register_Asm_32_VLD4dWB_register_Asm_8_VLD4qAsm_16_VLD4qAsm_32_VLD4qAsm_8_VLD4qWB_fixed_Asm_16_VLD4qWB_fixed_Asm_32_VLD4qWB_fixed_Asm_8_VLD4qWB_register_Asm_16_VLD4qWB_register_Asm_32_VLD4qWB_register_Asm_8 = 1045, |
| 5577 | VLD1d16QPseudo_VLD1d16QPseudoWB_fixed_VLD1d16QPseudoWB_register_VLD1d32QPseudo_VLD1d32QPseudoWB_fixed_VLD1d32QPseudoWB_register_VLD1d8QPseudo_VLD1d8QPseudoWB_fixed_VLD1d8QPseudoWB_register_VLD1q16HighQPseudo_VLD1q16HighQPseudo_UPD_VLD1q16LowQPseudo_UPD_VLD1q32HighQPseudo_VLD1q32HighQPseudo_UPD_VLD1q32LowQPseudo_UPD_VLD1q64HighQPseudo_VLD1q64HighQPseudo_UPD_VLD1q64LowQPseudo_UPD_VLD1q8HighQPseudo_VLD1q8HighQPseudo_UPD_VLD1q8LowQPseudo_UPD = 1046, |
| 5578 | VLD1d16TPseudo_VLD1d16TPseudoWB_fixed_VLD1d16TPseudoWB_register_VLD1d32TPseudo_VLD1d32TPseudoWB_fixed_VLD1d32TPseudoWB_register_VLD1d8TPseudo_VLD1d8TPseudoWB_fixed_VLD1d8TPseudoWB_register_VLD1q16HighTPseudo_VLD1q16HighTPseudo_UPD_VLD1q16LowTPseudo_UPD_VLD1q32HighTPseudo_VLD1q32HighTPseudo_UPD_VLD1q32LowTPseudo_UPD_VLD1q64HighTPseudo_VLD1q64HighTPseudo_UPD_VLD1q64LowTPseudo_UPD_VLD1q8HighTPseudo_VLD1q8HighTPseudo_UPD_VLD1q8LowTPseudo_UPD = 1047, |
| 5579 | VLD2DUPq16EvenPseudo_VLD2DUPq16OddPseudo_VLD2DUPq16OddPseudoWB_fixed_VLD2DUPq16OddPseudoWB_register_VLD2DUPq32EvenPseudo_VLD2DUPq32OddPseudo_VLD2DUPq32OddPseudoWB_fixed_VLD2DUPq32OddPseudoWB_register_VLD2DUPq8EvenPseudo_VLD2DUPq8OddPseudo_VLD2DUPq8OddPseudoWB_fixed_VLD2DUPq8OddPseudoWB_register = 1048, |
| 5580 | VLD3DUPq16EvenPseudo_VLD3DUPq16OddPseudo_VLD3DUPq32EvenPseudo_VLD3DUPq32OddPseudo_VLD3DUPq8EvenPseudo_VLD3DUPq8OddPseudo = 1049, |
| 5581 | VLD3DUPq16OddPseudo_UPD_VLD3DUPq32OddPseudo_UPD_VLD3DUPq8OddPseudo_UPD = 1050, |
| 5582 | VLD4DUPq16EvenPseudo_VLD4DUPq16OddPseudo_VLD4DUPq32EvenPseudo_VLD4DUPq32OddPseudo_VLD4DUPq8EvenPseudo_VLD4DUPq8OddPseudo = 1051, |
| 5583 | VLD4DUPq16OddPseudo_UPD_VLD4DUPq32OddPseudo_UPD_VLD4DUPq8OddPseudo_UPD = 1052, |
| 5584 | VST1d16TPseudo_VST1d32TPseudo_VST1d8TPseudo_VST1q16HighTPseudo_VST1q16HighTPseudo_UPD_VST1q16LowTPseudo_UPD_VST1q32HighTPseudo_VST1q32HighTPseudo_UPD_VST1q32LowTPseudo_UPD_VST1q64HighTPseudo_VST1q64HighTPseudo_UPD_VST1q64LowTPseudo_UPD_VST1q8HighTPseudo_VST1q8HighTPseudo_UPD_VST1q8LowTPseudo_UPD = 1053, |
| 5585 | VST1d16TPseudoWB_fixed_VST1d16TPseudoWB_register_VST1d32TPseudoWB_fixed_VST1d32TPseudoWB_register_VST1d8TPseudoWB_fixed_VST1d8TPseudoWB_register = 1054, |
| 5586 | VST1q16HighQPseudo_VST1q16HighQPseudo_UPD_VST1q16LowQPseudo_UPD_VST1q32HighQPseudo_VST1q32HighQPseudo_UPD_VST1q32LowQPseudo_UPD_VST1q64HighQPseudo_VST1q64HighQPseudo_UPD_VST1q64LowQPseudo_UPD_VST1q8HighQPseudo_VST1q8HighQPseudo_UPD_VST1q8LowQPseudo_UPD = 1055, |
| 5587 | VMOVD0 = 1056, |
| 5588 | t2CPS1p_t2CPS2p_t2CPS3p_t2SG_t2TT_t2TTA_t2TTAT_t2TTT = 1057, |
| 5589 | t2DBG = 1058, |
| 5590 | t2SUBS_PC_LR = 1059, |
| 5591 | COPY_TO_REGCLASS = 1060, |
| 5592 | COPY_STRUCT_BYVAL_I32 = 1061, |
| 5593 | t2CSEL_t2CSINC_t2CSINV_t2CSNEG = 1062, |
| 5594 | t2ADDrr_t2ADDSrr_t2SBCrr = 1063, |
| 5595 | t2ASRri_t2LSLri_t2LSRri = 1064, |
| 5596 | t2ASRrr_t2LSLrr_t2LSRrr_t2RORrr = 1065, |
| 5597 | t2CMNzrr = 1066, |
| 5598 | t2CMPri = 1067, |
| 5599 | t2CMPrr = 1068, |
| 5600 | t2ORRrr = 1069, |
| 5601 | t2REV_t2REV16_t2REVSH = 1070, |
| 5602 | t2RSBri_t2RSBSri = 1071, |
| 5603 | t2RSBrr_t2SUBSrr_t2SUBrr = 1072, |
| 5604 | t2TEQrr_t2TSTrr = 1073, |
| 5605 | t2STRi12 = 1074, |
| 5606 | t2STRBi12_t2STRHi12 = 1075, |
| 5607 | t2STMIA_UPD_t2STMDB_UPD = 1076, |
| 5608 | t2SETPAN_tHLT_tSETEND = 1077, |
| 5609 | tADC_tADDhirr_tADDrSP_tADDrr_tADDspr_tPICADD_tSBC_tSUBrr = 1078, |
| 5610 | tADDrSPi_tADDspi_tADR_tRSB_tSUBspi = 1079, |
| 5611 | tAND_tBIC_tEOR_tORR = 1080, |
| 5612 | tASRri_tLSLri_tLSRri = 1081, |
| 5613 | tCBNZ_tCBZ = 1082, |
| 5614 | tCMNz_tCMPhir_tCMPr = 1083, |
| 5615 | tCMPi8 = 1084, |
| 5616 | tCPS_tHINT = 1085, |
| 5617 | tMOVSr = 1086, |
| 5618 | tSTRBi_tSTRHi = 1087, |
| 5619 | tSTRi_tSTRspi = 1088, |
| 5620 | tSVC_tTRAP = 1089, |
| 5621 | tTST = 1090, |
| 5622 | tUDF = 1091, |
| 5623 | tB_tBX_tBXNS_tBcc = 1092, |
| 5624 | tBLXNSr_tBLXr = 1093, |
| 5625 | t2DMB_t2DSB_t2ISB = 1094, |
| 5626 | t2MCR_t2MCR2_t2MCRR_t2MCRR2_t2MRC_t2MRC2 = 1095, |
| 5627 | t2MOVSsi = 1096, |
| 5628 | t2MOVSsr = 1097, |
| 5629 | t2MUL = 1098, |
| 5630 | t2SMMLA_t2SMMLAR_t2SMMLS_t2SMMLSR = 1099, |
| 5631 | t2UXTAB_t2UXTAH = 1100, |
| 5632 | t2UXTAB16 = 1101, |
| 5633 | MVE_SQRSHR_MVE_SQSHL_MVE_SRSHR_MVE_UQRSHL_MVE_UQSHL_MVE_URSHR = 1102, |
| 5634 | MVE_ASRLi_MVE_ASRLr_MVE_LSLLi_MVE_LSLLr_MVE_LSRL_MVE_SQRSHRL_MVE_SQSHLL_MVE_SRSHRL_MVE_UQRSHLL_MVE_UQSHLL_MVE_URSHRL = 1103, |
| 5635 | t2CLRM = 1104, |
| 5636 | t2LDRBi12_t2LDRHi12 = 1105, |
| 5637 | t2LDRi12 = 1106, |
| 5638 | t2LDMDB_t2LDMIA = 1107, |
| 5639 | t2LDMDB_UPD_t2LDMIA_UPD = 1108, |
| 5640 | tADDi3_tADDi8_tSUBi3_tSUBi8 = 1109, |
| 5641 | t2ADDSri_t2ADDri = 1110, |
| 5642 | t2SUBSri_t2SUBri = 1111, |
| 5643 | t2LoopDec = 1112, |
| 5644 | MVE_VLDRBS16_MVE_VLDRBS32_MVE_VLDRBU16_MVE_VLDRBU32_MVE_VLDRBU8_MVE_VLDRHS32_MVE_VLDRHU16_MVE_VLDRHU32_MVE_VLDRWU32 = 1113, |
| 5645 | MVE_VLDRBS16_post_MVE_VLDRBS16_pre_MVE_VLDRBS32_post_MVE_VLDRBS32_pre_MVE_VLDRBU16_post_MVE_VLDRBU16_pre_MVE_VLDRBU32_post_MVE_VLDRBU32_pre_MVE_VLDRBU8_post_MVE_VLDRBU8_pre_MVE_VLDRHS32_post_MVE_VLDRHS32_pre_MVE_VLDRHU16_post_MVE_VLDRHU16_pre_MVE_VLDRHU32_post_MVE_VLDRHU32_pre_MVE_VLDRWU32_post_MVE_VLDRWU32_pre = 1114, |
| 5646 | MVE_VLDRBS16_rq_MVE_VLDRBS32_rq_MVE_VLDRBU16_rq_MVE_VLDRBU32_rq_MVE_VLDRBU8_rq_MVE_VLDRDU64_rq_MVE_VLDRDU64_rq_u_MVE_VLDRHS32_rq_MVE_VLDRHS32_rq_u_MVE_VLDRHU16_rq_MVE_VLDRHU16_rq_u_MVE_VLDRHU32_rq_MVE_VLDRHU32_rq_u_MVE_VLDRWU32_rq_MVE_VLDRWU32_rq_u = 1115, |
| 5647 | MVE_VLDRDU64_qi_MVE_VLDRWU32_qi = 1116, |
| 5648 | MVE_VLDRDU64_qi_pre_MVE_VLDRWU32_qi_pre = 1117, |
| 5649 | MVE_VLD20_16_MVE_VLD20_32_MVE_VLD20_8_MVE_VLD21_16_MVE_VLD21_32_MVE_VLD21_8_MVE_VLD40_16_MVE_VLD40_32_MVE_VLD40_8_MVE_VLD41_16_MVE_VLD41_32_MVE_VLD41_8_MVE_VLD42_16_MVE_VLD42_32_MVE_VLD42_8_MVE_VLD43_16_MVE_VLD43_32_MVE_VLD43_8 = 1118, |
| 5650 | MVE_VLD20_16_wb_MVE_VLD20_32_wb_MVE_VLD20_8_wb_MVE_VLD21_16_wb_MVE_VLD21_32_wb_MVE_VLD21_8_wb_MVE_VLD40_16_wb_MVE_VLD40_32_wb_MVE_VLD40_8_wb_MVE_VLD41_16_wb_MVE_VLD41_32_wb_MVE_VLD41_8_wb_MVE_VLD42_16_wb_MVE_VLD42_32_wb_MVE_VLD42_8_wb_MVE_VLD43_16_wb_MVE_VLD43_32_wb_MVE_VLD43_8_wb = 1119, |
| 5651 | MVE_VSTRB16_MVE_VSTRB32_MVE_VSTRBU8_MVE_VSTRH32_MVE_VSTRHU16_MVE_VSTRWU32 = 1120, |
| 5652 | MVE_VSTRB16_post_MVE_VSTRB16_pre_MVE_VSTRB32_post_MVE_VSTRB32_pre_MVE_VSTRBU8_post_MVE_VSTRBU8_pre_MVE_VSTRH32_post_MVE_VSTRH32_pre_MVE_VSTRHU16_post_MVE_VSTRHU16_pre_MVE_VSTRWU32_post_MVE_VSTRWU32_pre = 1121, |
| 5653 | MVE_VSTRB16_rq_MVE_VSTRB32_rq_MVE_VSTRB8_rq_MVE_VSTRD64_rq_MVE_VSTRD64_rq_u_MVE_VSTRH16_rq_MVE_VSTRH16_rq_u_MVE_VSTRH32_rq_MVE_VSTRH32_rq_u_MVE_VSTRW32_rq_MVE_VSTRW32_rq_u = 1122, |
| 5654 | MVE_VSTRD64_qi_MVE_VSTRD64_qi_pre_MVE_VSTRW32_qi_MVE_VSTRW32_qi_pre = 1123, |
| 5655 | MVE_VST20_16_MVE_VST20_16_wb_MVE_VST20_32_MVE_VST20_32_wb_MVE_VST20_8_MVE_VST20_8_wb_MVE_VST21_16_MVE_VST21_16_wb_MVE_VST21_32_MVE_VST21_32_wb_MVE_VST21_8_MVE_VST21_8_wb_MVE_VST40_16_MVE_VST40_16_wb_MVE_VST40_32_MVE_VST40_32_wb_MVE_VST40_8_MVE_VST40_8_wb_MVE_VST41_16_MVE_VST41_16_wb_MVE_VST41_32_MVE_VST41_32_wb_MVE_VST41_8_MVE_VST41_8_wb_MVE_VST42_16_MVE_VST42_16_wb_MVE_VST42_32_MVE_VST42_32_wb_MVE_VST42_8_MVE_VST42_8_wb_MVE_VST43_16_MVE_VST43_16_wb_MVE_VST43_32_MVE_VST43_32_wb_MVE_VST43_8_MVE_VST43_8_wb = 1124, |
| 5656 | MVE_VABAVs16_MVE_VABAVs32_MVE_VABAVs8_MVE_VABAVu16_MVE_VABAVu32_MVE_VABAVu8 = 1125, |
| 5657 | MVE_VABDs16_MVE_VABDs32_MVE_VABDs8_MVE_VABDu16_MVE_VABDu32_MVE_VABDu8 = 1126, |
| 5658 | MVE_VABSs16_MVE_VABSs32_MVE_VABSs8 = 1127, |
| 5659 | MVE_VADC_MVE_VADCI = 1128, |
| 5660 | MVE_VADD_qr_i16_MVE_VADD_qr_i32_MVE_VADD_qr_i8_MVE_VADDi16_MVE_VADDi32_MVE_VADDi8 = 1129, |
| 5661 | MVE_VAND = 1130, |
| 5662 | MVE_VBIC_MVE_VBICimmi16_MVE_VBICimmi32 = 1131, |
| 5663 | MVE_VBRSR16_MVE_VBRSR32_MVE_VBRSR8 = 1132, |
| 5664 | MVE_VCADDi16_MVE_VCADDi32_MVE_VCADDi8 = 1133, |
| 5665 | MVE_VCLSs16_MVE_VCLSs32_MVE_VCLSs8 = 1134, |
| 5666 | MVE_VCLZs16_MVE_VCLZs32_MVE_VCLZs8 = 1135, |
| 5667 | MVE_VDDUPu16_MVE_VDDUPu32_MVE_VDDUPu8_MVE_VDUP16_MVE_VDUP32_MVE_VDUP8_MVE_VDWDUPu16_MVE_VDWDUPu32_MVE_VDWDUPu8_MVE_VIDUPu16_MVE_VIDUPu32_MVE_VIDUPu8_MVE_VIWDUPu16_MVE_VIWDUPu32_MVE_VIWDUPu8 = 1136, |
| 5668 | MVE_VEOR = 1137, |
| 5669 | MVE_VHADD_qr_s16_MVE_VHADD_qr_s32_MVE_VHADD_qr_s8_MVE_VHADD_qr_u16_MVE_VHADD_qr_u32_MVE_VHADD_qr_u8_MVE_VHADDs16_MVE_VHADDs32_MVE_VHADDs8_MVE_VHADDu16_MVE_VHADDu32_MVE_VHADDu8 = 1138, |
| 5670 | MVE_VHCADDs16_MVE_VHCADDs32_MVE_VHCADDs8 = 1139, |
| 5671 | MVE_VHSUB_qr_s16_MVE_VHSUB_qr_s32_MVE_VHSUB_qr_s8_MVE_VHSUB_qr_u16_MVE_VHSUB_qr_u32_MVE_VHSUB_qr_u8_MVE_VHSUBs16_MVE_VHSUBs32_MVE_VHSUBs8_MVE_VHSUBu16_MVE_VHSUBu32_MVE_VHSUBu8 = 1140, |
| 5672 | MVE_VMAXAs16_MVE_VMAXAs32_MVE_VMAXAs8_MVE_VMAXs16_MVE_VMAXs32_MVE_VMAXs8_MVE_VMAXu16_MVE_VMAXu32_MVE_VMAXu8_MVE_VMINAs16_MVE_VMINAs32_MVE_VMINAs8_MVE_VMINs16_MVE_VMINs32_MVE_VMINs8_MVE_VMINu16_MVE_VMINu32_MVE_VMINu8 = 1141, |
| 5673 | MVE_VMAXAVs8_MVE_VMAXVs8_MVE_VMAXVu8_MVE_VMINAVs8_MVE_VMINVs8_MVE_VMINVu8 = 1142, |
| 5674 | MVE_VMAXAVs16_MVE_VMAXVs16_MVE_VMAXVu16_MVE_VMINAVs16_MVE_VMINVs16_MVE_VMINVu16 = 1143, |
| 5675 | MVE_VMAXAVs32_MVE_VMAXVs32_MVE_VMAXVu32_MVE_VMINAVs32_MVE_VMINVs32_MVE_VMINVu32 = 1144, |
| 5676 | MVE_VMOVNi16bh_MVE_VMOVNi16th_MVE_VMOVNi32bh_MVE_VMOVNi32th = 1145, |
| 5677 | MVE_VMOVLs16bh_MVE_VMOVLs16th_MVE_VMOVLs8bh_MVE_VMOVLs8th_MVE_VMOVLu16bh_MVE_VMOVLu16th_MVE_VMOVLu8bh_MVE_VMOVLu8th = 1146, |
| 5678 | MVE_VMULLBp16_MVE_VMULLBp8_MVE_VMULLTp16_MVE_VMULLTp8 = 1147, |
| 5679 | MVE_VMVN_MVE_VMVNimmi16_MVE_VMVNimmi32 = 1148, |
| 5680 | MVE_VNEGs16_MVE_VNEGs32_MVE_VNEGs8 = 1149, |
| 5681 | MVE_VORN = 1150, |
| 5682 | MVE_VORR_MVE_VORRimmi16_MVE_VORRimmi32 = 1151, |
| 5683 | MVE_VPSEL = 1152, |
| 5684 | MQPRCopy = 1153, |
| 5685 | MVE_VQABSs16_MVE_VQABSs32_MVE_VQABSs8 = 1154, |
| 5686 | MVE_VQADD_qr_s16_MVE_VQADD_qr_s32_MVE_VQADD_qr_s8_MVE_VQADD_qr_u16_MVE_VQADD_qr_u32_MVE_VQADD_qr_u8_MVE_VQADDs16_MVE_VQADDs32_MVE_VQADDs8_MVE_VQADDu16_MVE_VQADDu32_MVE_VQADDu8 = 1155, |
| 5687 | MVE_VQMOVNs16bh_MVE_VQMOVNs16th_MVE_VQMOVNs32bh_MVE_VQMOVNs32th_MVE_VQMOVNu16bh_MVE_VQMOVNu16th_MVE_VQMOVNu32bh_MVE_VQMOVNu32th_MVE_VQMOVUNs16bh_MVE_VQMOVUNs16th_MVE_VQMOVUNs32bh_MVE_VQMOVUNs32th = 1156, |
| 5688 | MVE_VQNEGs16_MVE_VQNEGs32_MVE_VQNEGs8 = 1157, |
| 5689 | MVE_VSHLC_MVE_VSHLL_imms16bh_MVE_VSHLL_imms16th_MVE_VSHLL_imms8bh_MVE_VSHLL_imms8th_MVE_VSHLL_immu16bh_MVE_VSHLL_immu16th_MVE_VSHLL_immu8bh_MVE_VSHLL_immu8th_MVE_VSHLL_lws16bh_MVE_VSHLL_lws16th_MVE_VSHLL_lws8bh_MVE_VSHLL_lws8th_MVE_VSHLL_lwu16bh_MVE_VSHLL_lwu16th_MVE_VSHLL_lwu8bh_MVE_VSHLL_lwu8th_MVE_VSHL_by_vecs16_MVE_VSHL_by_vecs32_MVE_VSHL_by_vecs8_MVE_VSHL_by_vecu16_MVE_VSHL_by_vecu32_MVE_VSHL_by_vecu8_MVE_VSHL_immi16_MVE_VSHL_immi32_MVE_VSHL_immi8_MVE_VSHL_qrs16_MVE_VSHL_qrs32_MVE_VSHL_qrs8_MVE_VSHL_qru16_MVE_VSHL_qru32_MVE_VSHL_qru8 = 1158, |
| 5690 | MVE_VQSHLU_imms16_MVE_VQSHLU_imms32_MVE_VQSHLU_imms8_MVE_VQSHL_by_vecs16_MVE_VQSHL_by_vecs32_MVE_VQSHL_by_vecs8_MVE_VQSHL_by_vecu16_MVE_VQSHL_by_vecu32_MVE_VQSHL_by_vecu8_MVE_VQSHL_qrs16_MVE_VQSHL_qrs32_MVE_VQSHL_qrs8_MVE_VQSHL_qru16_MVE_VQSHL_qru32_MVE_VQSHL_qru8_MVE_VQSHLimms16_MVE_VQSHLimms32_MVE_VQSHLimms8_MVE_VQSHLimmu16_MVE_VQSHLimmu32_MVE_VQSHLimmu8_MVE_VRSHL_by_vecs16_MVE_VRSHL_by_vecs32_MVE_VRSHL_by_vecs8_MVE_VRSHL_by_vecu16_MVE_VRSHL_by_vecu32_MVE_VRSHL_by_vecu8_MVE_VRSHL_qrs16_MVE_VRSHL_qrs32_MVE_VRSHL_qrs8_MVE_VRSHL_qru16_MVE_VRSHL_qru32_MVE_VRSHL_qru8 = 1159, |
| 5691 | MVE_VQRSHL_by_vecs16_MVE_VQRSHL_by_vecs32_MVE_VQRSHL_by_vecs8_MVE_VQRSHL_by_vecu16_MVE_VQRSHL_by_vecu32_MVE_VQRSHL_by_vecu8_MVE_VQRSHL_qrs16_MVE_VQRSHL_qrs32_MVE_VQRSHL_qrs8_MVE_VQRSHL_qru16_MVE_VQRSHL_qru32_MVE_VQRSHL_qru8 = 1160, |
| 5692 | MVE_VQRSHRNbhs16_MVE_VQRSHRNbhs32_MVE_VQRSHRNbhu16_MVE_VQRSHRNbhu32_MVE_VQRSHRNths16_MVE_VQRSHRNths32_MVE_VQRSHRNthu16_MVE_VQRSHRNthu32_MVE_VQRSHRUNs16bh_MVE_VQRSHRUNs16th_MVE_VQRSHRUNs32bh_MVE_VQRSHRUNs32th_MVE_VQSHRNbhs16_MVE_VQSHRNbhs32_MVE_VQSHRNbhu16_MVE_VQSHRNbhu32_MVE_VQSHRNths16_MVE_VQSHRNths32_MVE_VQSHRNthu16_MVE_VQSHRNthu32_MVE_VQSHRUNs16bh_MVE_VQSHRUNs16th_MVE_VQSHRUNs32bh_MVE_VQSHRUNs32th_MVE_VRSHRNi16bh_MVE_VRSHRNi16th_MVE_VRSHRNi32bh_MVE_VRSHRNi32th_MVE_VSHRNi16bh_MVE_VSHRNi16th_MVE_VSHRNi32bh_MVE_VSHRNi32th = 1161, |
| 5693 | MVE_VSHR_imms16_MVE_VSHR_imms32_MVE_VSHR_imms8_MVE_VSHR_immu16_MVE_VSHR_immu32_MVE_VSHR_immu8 = 1162, |
| 5694 | MVE_VRSHR_imms16_MVE_VRSHR_imms32_MVE_VRSHR_imms8_MVE_VRSHR_immu16_MVE_VRSHR_immu32_MVE_VRSHR_immu8 = 1163, |
| 5695 | MVE_VQSUB_qr_s16_MVE_VQSUB_qr_s32_MVE_VQSUB_qr_s8_MVE_VQSUB_qr_u16_MVE_VQSUB_qr_u32_MVE_VQSUB_qr_u8_MVE_VQSUBs16_MVE_VQSUBs32_MVE_VQSUBs8_MVE_VQSUBu16_MVE_VQSUBu32_MVE_VQSUBu8 = 1164, |
| 5696 | MVE_VREV16_8_MVE_VREV32_16_MVE_VREV32_8_MVE_VREV64_16_MVE_VREV64_32_MVE_VREV64_8 = 1165, |
| 5697 | MVE_VRHADDs16_MVE_VRHADDs32_MVE_VRHADDs8_MVE_VRHADDu16_MVE_VRHADDu32_MVE_VRHADDu8 = 1166, |
| 5698 | MVE_VSBC_MVE_VSBCI = 1167, |
| 5699 | MVE_VSLIimm16_MVE_VSLIimm32_MVE_VSLIimm8 = 1168, |
| 5700 | MVE_VSRIimm16_MVE_VSRIimm32_MVE_VSRIimm8 = 1169, |
| 5701 | MVE_VSUB_qr_i16_MVE_VSUB_qr_i32_MVE_VSUB_qr_i8_MVE_VSUBi16_MVE_VSUBi32_MVE_VSUBi8 = 1170, |
| 5702 | MVE_VABDf16_MVE_VABDf32 = 1171, |
| 5703 | MVE_VABSf16_MVE_VABSf32 = 1172, |
| 5704 | MVE_VADDf16_MVE_VADDf32 = 1173, |
| 5705 | MVE_VADD_qr_f16_MVE_VADD_qr_f32 = 1174, |
| 5706 | MVE_VADDLVs32acc_MVE_VADDLVs32no_acc_MVE_VADDLVu32acc_MVE_VADDLVu32no_acc = 1175, |
| 5707 | MVE_VADDVs16acc_MVE_VADDVs16no_acc_MVE_VADDVs32acc_MVE_VADDVs32no_acc_MVE_VADDVs8acc_MVE_VADDVs8no_acc_MVE_VADDVu16acc_MVE_VADDVu16no_acc_MVE_VADDVu32acc_MVE_VADDVu32no_acc_MVE_VADDVu8acc_MVE_VADDVu8no_acc = 1176, |
| 5708 | MVE_VCADDf16_MVE_VCADDf32 = 1177, |
| 5709 | MVE_VCMLAf16_MVE_VCMLAf32 = 1178, |
| 5710 | MVE_VCMULf16_MVE_VCMULf32 = 1179, |
| 5711 | MVE_VCMPi16_MVE_VCMPi16r_MVE_VCMPi32_MVE_VCMPi32r_MVE_VCMPi8_MVE_VCMPi8r_MVE_VCMPs16_MVE_VCMPs16r_MVE_VCMPs32_MVE_VCMPs32r_MVE_VCMPs8_MVE_VCMPs8r_MVE_VCMPu16_MVE_VCMPu16r_MVE_VCMPu32_MVE_VCMPu32r_MVE_VCMPu8_MVE_VCMPu8r_MVE_VPTv16i8_MVE_VPTv16i8r_MVE_VPTv16s8_MVE_VPTv16s8r_MVE_VPTv16u8_MVE_VPTv16u8r_MVE_VPTv4i32_MVE_VPTv4i32r_MVE_VPTv4s32_MVE_VPTv4s32r_MVE_VPTv4u32_MVE_VPTv4u32r_MVE_VPTv8i16_MVE_VPTv8i16r_MVE_VPTv8s16_MVE_VPTv8s16r_MVE_VPTv8u16_MVE_VPTv8u16r = 1180, |
| 5712 | MVE_VCMPf16_MVE_VCMPf16r_MVE_VCMPf32_MVE_VCMPf32r_MVE_VPTv4f32_MVE_VPTv4f32r_MVE_VPTv8f16_MVE_VPTv8f16r = 1181, |
| 5713 | MVE_VCVTf16s16_fix_MVE_VCVTf16s16n_MVE_VCVTf16u16_fix_MVE_VCVTf16u16n = 1182, |
| 5714 | MVE_VCVTf32s32_fix_MVE_VCVTf32s32n_MVE_VCVTf32u32_fix_MVE_VCVTf32u32n = 1183, |
| 5715 | MVE_VCVTs16f16_fix_MVE_VCVTs16f16a_MVE_VCVTs16f16m_MVE_VCVTs16f16n_MVE_VCVTs16f16p_MVE_VCVTs16f16z_MVE_VCVTu16f16_fix_MVE_VCVTu16f16a_MVE_VCVTu16f16m_MVE_VCVTu16f16n_MVE_VCVTu16f16p_MVE_VCVTu16f16z = 1184, |
| 5716 | MVE_VCVTs32f32_fix_MVE_VCVTs32f32a_MVE_VCVTs32f32m_MVE_VCVTs32f32n_MVE_VCVTs32f32p_MVE_VCVTs32f32z_MVE_VCVTu32f32_fix_MVE_VCVTu32f32a_MVE_VCVTu32f32m_MVE_VCVTu32f32n_MVE_VCVTu32f32p_MVE_VCVTu32f32z = 1185, |
| 5717 | MVE_VCVTf16f32bh_MVE_VCVTf16f32th = 1186, |
| 5718 | MVE_VCVTf32f16bh_MVE_VCVTf32f16th = 1187, |
| 5719 | MVE_VFMA_qr_Sf16_MVE_VFMA_qr_Sf32_MVE_VFMA_qr_f16_MVE_VFMA_qr_f32_MVE_VFMAf16_MVE_VFMAf32_MVE_VFMSf16_MVE_VFMSf32 = 1188, |
| 5720 | MVE_VMAXNMAVf16_MVE_VMAXNMAVf32_MVE_VMAXNMAf16_MVE_VMAXNMAf32_MVE_VMAXNMVf16_MVE_VMAXNMVf32_MVE_VMAXNMf16_MVE_VMAXNMf32_MVE_VMINNMAVf16_MVE_VMINNMAVf32_MVE_VMINNMAf16_MVE_VMINNMAf32_MVE_VMINNMVf16_MVE_VMINNMVf32_MVE_VMINNMf16_MVE_VMINNMf32 = 1189, |
| 5721 | MVE_VMOV_from_lane_32_MVE_VMOV_from_lane_s16_MVE_VMOV_from_lane_s8_MVE_VMOV_from_lane_u16_MVE_VMOV_from_lane_u8 = 1190, |
| 5722 | MVE_VMOV_rr_q = 1191, |
| 5723 | MVE_VMOVimmf32_MVE_VMOVimmi16_MVE_VMOVimmi32_MVE_VMOVimmi64_MVE_VMOVimmi8 = 1192, |
| 5724 | MVE_VMUL_qr_f16_MVE_VMUL_qr_f32_MVE_VMUL_qr_i16_MVE_VMUL_qr_i32_MVE_VMUL_qr_i8_MVE_VMULf16_MVE_VMULf32_MVE_VMULi16_MVE_VMULi32_MVE_VMULi8 = 1193, |
| 5725 | MVE_VMULHs16_MVE_VMULHs32_MVE_VMULHs8_MVE_VMULHu16_MVE_VMULHu32_MVE_VMULHu8_MVE_VQDMULH_qr_s16_MVE_VQDMULH_qr_s32_MVE_VQDMULH_qr_s8_MVE_VQDMULHi16_MVE_VQDMULHi32_MVE_VQDMULHi8_MVE_VQRDMULH_qr_s16_MVE_VQRDMULH_qr_s32_MVE_VQRDMULH_qr_s8_MVE_VQRDMULHi16_MVE_VQRDMULHi32_MVE_VQRDMULHi8_MVE_VRMULHs16_MVE_VRMULHs32_MVE_VRMULHs8_MVE_VRMULHu16_MVE_VRMULHu32_MVE_VRMULHu8 = 1194, |
| 5726 | MVE_VMULLBs16_MVE_VMULLBs32_MVE_VMULLBs8_MVE_VMULLBu16_MVE_VMULLBu32_MVE_VMULLBu8_MVE_VMULLTs16_MVE_VMULLTs32_MVE_VMULLTs8_MVE_VMULLTu16_MVE_VMULLTu32_MVE_VMULLTu8_MVE_VQDMULLs16bh_MVE_VQDMULLs16th_MVE_VQDMULLs32bh_MVE_VQDMULLs32th = 1195, |
| 5727 | MVE_VQDMULL_qr_s16bh_MVE_VQDMULL_qr_s16th_MVE_VQDMULL_qr_s32bh_MVE_VQDMULL_qr_s32th = 1196, |
| 5728 | MVE_VMLADAVas16_MVE_VMLADAVas32_MVE_VMLADAVas8_MVE_VMLADAVau16_MVE_VMLADAVau32_MVE_VMLADAVau8_MVE_VMLADAVaxs16_MVE_VMLADAVaxs32_MVE_VMLADAVaxs8_MVE_VMLADAVs16_MVE_VMLADAVs32_MVE_VMLADAVs8_MVE_VMLADAVu16_MVE_VMLADAVu32_MVE_VMLADAVu8_MVE_VMLADAVxs16_MVE_VMLADAVxs32_MVE_VMLADAVxs8_MVE_VMLAS_qr_i16_MVE_VMLAS_qr_i32_MVE_VMLAS_qr_i8_MVE_VMLA_qr_i16_MVE_VMLA_qr_i32_MVE_VMLA_qr_i8_MVE_VMLSDAVas16_MVE_VMLSDAVas32_MVE_VMLSDAVas8_MVE_VMLSDAVaxs16_MVE_VMLSDAVaxs32_MVE_VMLSDAVaxs8_MVE_VMLSDAVs16_MVE_VMLSDAVs32_MVE_VMLSDAVs8_MVE_VMLSDAVxs16_MVE_VMLSDAVxs32_MVE_VMLSDAVxs8_MVE_VQDMLADHXs16_MVE_VQDMLADHXs32_MVE_VQDMLADHXs8_MVE_VQDMLADHs16_MVE_VQDMLADHs32_MVE_VQDMLADHs8_MVE_VQDMLAH_qrs16_MVE_VQDMLAH_qrs32_MVE_VQDMLAH_qrs8_MVE_VQDMLASH_qrs16_MVE_VQDMLASH_qrs32_MVE_VQDMLASH_qrs8_MVE_VQDMLSDHXs16_MVE_VQDMLSDHXs32_MVE_VQDMLSDHXs8_MVE_VQDMLSDHs16_MVE_VQDMLSDHs32_MVE_VQDMLSDHs8_MVE_VQRDMLADHXs16_MVE_VQRDMLADHXs32_MVE_VQRDMLADHXs8_MVE_VQRDMLADHs16_MVE_VQRDMLADHs32_MVE_VQRDMLADHs8_MVE_VQRDMLAH_qrs16_MVE_VQRDMLAH_qrs32_MVE_VQRDMLAH_qrs8_MVE_VQRDMLASH_qrs16_MVE_VQRDMLASH_qrs32_MVE_VQRDMLASH_qrs8_MVE_VQRDMLSDHXs16_MVE_VQRDMLSDHXs32_MVE_VQRDMLSDHXs8_MVE_VQRDMLSDHs16_MVE_VQRDMLSDHs32_MVE_VQRDMLSDHs8 = 1197, |
| 5729 | MVE_VMLALDAVas16_MVE_VMLALDAVas32_MVE_VMLALDAVau16_MVE_VMLALDAVau32_MVE_VMLALDAVaxs16_MVE_VMLALDAVaxs32_MVE_VMLALDAVs16_MVE_VMLALDAVs32_MVE_VMLALDAVu16_MVE_VMLALDAVu32_MVE_VMLALDAVxs16_MVE_VMLALDAVxs32_MVE_VMLSLDAVas16_MVE_VMLSLDAVas32_MVE_VMLSLDAVaxs16_MVE_VMLSLDAVaxs32_MVE_VMLSLDAVs16_MVE_VMLSLDAVs32_MVE_VMLSLDAVxs16_MVE_VMLSLDAVxs32_MVE_VRMLALDAVHas32_MVE_VRMLALDAVHau32_MVE_VRMLALDAVHaxs32_MVE_VRMLALDAVHs32_MVE_VRMLALDAVHu32_MVE_VRMLALDAVHxs32_MVE_VRMLSLDAVHas32_MVE_VRMLSLDAVHaxs32_MVE_VRMLSLDAVHs32_MVE_VRMLSLDAVHxs32 = 1198, |
| 5730 | MVE_VNEGf16_MVE_VNEGf32 = 1199, |
| 5731 | MVE_VRINTf16A_MVE_VRINTf16M_MVE_VRINTf16N_MVE_VRINTf16P_MVE_VRINTf16X_MVE_VRINTf16Z_MVE_VRINTf32A_MVE_VRINTf32M_MVE_VRINTf32N_MVE_VRINTf32P_MVE_VRINTf32X_MVE_VRINTf32Z = 1200, |
| 5732 | MVE_VSUBf16_MVE_VSUBf32 = 1201, |
| 5733 | MVE_VSUB_qr_f16_MVE_VSUB_qr_f32 = 1202, |
| 5734 | MVE_VMOV_to_lane_16_MVE_VMOV_to_lane_32_MVE_VMOV_to_lane_8_MVE_VMOV_q_rr = 1203, |
| 5735 | MVE_VCTP16_MVE_VCTP32_MVE_VCTP64_MVE_VCTP8 = 1204, |
| 5736 | MVE_VPNOT = 1205, |
| 5737 | MVE_VPST = 1206, |
| 5738 | VCVTASD_VCVTASH_VCVTASS_VCVTAUD_VCVTAUH_VCVTAUS_VCVTMSD_VCVTMSH_VCVTMSS_VCVTMUD_VCVTMUH_VCVTMUS_VCVTNSD_VCVTNSH_VCVTNSS_VCVTNUD_VCVTNUH_VCVTNUS_VCVTPSD_VCVTPSH_VCVTPSS_VCVTPUD_VCVTPUH_VCVTPUS = 1207, |
| 5739 | VDIVH = 1208, |
| 5740 | VFMAH_VFMSH = 1209, |
| 5741 | VFP_VMAXNMD_VFP_VMAXNMH_VFP_VMAXNMS_VFP_VMINNMD_VFP_VMINNMH_VFP_VMINNMS = 1210, |
| 5742 | VMOVH = 1211, |
| 5743 | VMOVHR = 1212, |
| 5744 | VMOVD = 1213, |
| 5745 | VMOVS = 1214, |
| 5746 | VMOVRH = 1215, |
| 5747 | tSVC = 1216, |
| 5748 | t2HVC = 1217, |
| 5749 | t2SMC_ERET = 1218, |
| 5750 | tHINT = 1219, |
| 5751 | BUNDLE = 1220, |
| 5752 | t2LDRBpcrel_t2LDRHpcrel = 1221, |
| 5753 | t2LDRBpci_t2LDRHpci = 1222, |
| 5754 | t2LDRSBpci_t2LDRSHpci = 1223, |
| 5755 | t2LDRH_POST_imm = 1224, |
| 5756 | t2LDRH_PRE_imm = 1225, |
| 5757 | t2LDREX = 1226, |
| 5758 | t2LDREXB_t2LDREXH = 1227, |
| 5759 | t2STREX_t2STREXB_t2STREXH = 1228, |
| 5760 | t2LDRpci = 1229, |
| 5761 | t2PLDpci_t2PLIpci = 1230, |
| 5762 | tLDRpci = 1231, |
| 5763 | t2PLDWi12_t2PLDWi8_t2PLDi12_t2PLDi8_t2PLIi12_t2PLIi8 = 1232, |
| 5764 | t2PLDs_t2PLIs = 1233, |
| 5765 | t2TBB_JT_t2TBH_JT = 1234, |
| 5766 | t2TBB_t2TBH = 1235, |
| 5767 | t2RSBSrs_t2SUBrs = 1236, |
| 5768 | t2SUBSrs = 1237, |
| 5769 | t2BICrs_t2EORrs_t2ORRrs = 1238, |
| 5770 | t2ORNrs = 1239, |
| 5771 | t2CMNzrs = 1240, |
| 5772 | t2CMPrs = 1241, |
| 5773 | t2TEQrs_t2TSTrs = 1242, |
| 5774 | t2ASRs1_t2LSRs1 = 1243, |
| 5775 | t2RRX = 1244, |
| 5776 | t2CLZ = 1245, |
| 5777 | t2USAD8 = 1246, |
| 5778 | t2RBIT = 1247, |
| 5779 | t2PKHBT_t2PKHTB = 1248, |
| 5780 | VCVTASS_VCVTAUS_VCVTMSS_VCVTMUS_VCVTNSS_VCVTNUS_VCVTPSS_VCVTPUS = 1249, |
| 5781 | VFP_VMAXNMS_VFP_VMINNMS = 1250, |
| 5782 | VRINTAS_VRINTMS_VRINTNS_VRINTPS_VRINTRS_VRINTXS_VRINTZS = 1251, |
| 5783 | VCVTASD_VCVTAUD_VCVTMSD_VCVTMUD_VCVTNSD_VCVTNUD_VCVTPSD_VCVTPUD = 1252, |
| 5784 | VCVTTHD = 1253, |
| 5785 | VFP_VMAXNMD_VFP_VMINNMD = 1254, |
| 5786 | VRINTAD_VRINTMD_VRINTND_VRINTPD_VRINTRD_VRINTXD_VRINTZD = 1255, |
| 5787 | VCMPS = 1256, |
| 5788 | VCMPD = 1257, |
| 5789 | VSELEQS_VSELGES_VSELGTS_VSELVSS = 1258, |
| 5790 | VSELEQD_VSELGED_VSELGTD_VSELVSD = 1259, |
| 5791 | VMULD_VNMULD = 1260, |
| 5792 | tLDRspi = 1261, |
| 5793 | t2LDA_t2LDAEX = 1262, |
| 5794 | t2LDAEXD = 1263, |
| 5795 | t2STL_t2STLB_t2STLEX_t2STLEXB_t2STLEXH_t2STLH = 1264, |
| 5796 | MVE_VST20_16_MVE_VST20_32_MVE_VST20_8_MVE_VST21_16_MVE_VST21_32_MVE_VST21_8_MVE_VST40_16_MVE_VST40_32_MVE_VST40_8_MVE_VST41_16_MVE_VST41_32_MVE_VST41_8_MVE_VST42_16_MVE_VST42_32_MVE_VST42_8_MVE_VST43_16_MVE_VST43_32_MVE_VST43_8 = 1265, |
| 5797 | MVE_VSTRD64_qi_MVE_VSTRW32_qi = 1266, |
| 5798 | t2RSBSrs = 1267, |
| 5799 | t2ADCrs_t2SBCrs = 1268, |
| 5800 | t2ADDSrr_t2SBCrr = 1269, |
| 5801 | t2SUBSrr_t2RSBrr = 1270, |
| 5802 | t2ADCrr = 1271, |
| 5803 | t2BICrr_t2EORrr = 1272, |
| 5804 | t2ORNrr = 1273, |
| 5805 | tLSLSri = 1274, |
| 5806 | tADDspi_tSUBspi = 1275, |
| 5807 | t2ADDri = 1276, |
| 5808 | t2ADDri12 = 1277, |
| 5809 | t2SUBri = 1278, |
| 5810 | t2SUBri12 = 1279, |
| 5811 | tADDrSP_tADDspr_tADDhirr = 1280, |
| 5812 | tADDrSPi = 1281, |
| 5813 | MVE_ASRLi_MVE_LSLLi_MVE_LSRL_MVE_SQSHLL_MVE_SRSHRL_MVE_UQSHLL_MVE_URSHRL = 1282, |
| 5814 | MVE_SQRSHR_MVE_UQRSHL = 1283, |
| 5815 | t2BF_LabelPseudo_t2BFLi_t2BFLr_t2BFi_t2BFic_t2BFr = 1284, |
| 5816 | MVE_LCTP = 1285, |
| 5817 | t2DLS_t2WLS_MVE_DLSTP_16_MVE_DLSTP_32_MVE_DLSTP_64_MVE_DLSTP_8_MVE_WLSTP_16_MVE_WLSTP_32_MVE_WLSTP_64_MVE_WLSTP_8 = 1286, |
| 5818 | t2LE = 1287, |
| 5819 | t2LEUpdate_MVE_LETP = 1288, |
| 5820 | VSHTOD_VSLTOD_VUHTOD_VULTOD = 1289, |
| 5821 | VMSR_VMSR_FPSCR_NZCVQC_VMSR_P0_VMSR_VPR = 1290, |
| 5822 | VMRS_P0_VMRS_VPR = 1291, |
| 5823 | VMRS_FPSCR_NZCVQC = 1292, |
| 5824 | VMRS = 1293, |
| 5825 | MVE_VMOV_q_rr = 1294, |
| 5826 | MVE_VADC = 1295, |
| 5827 | MVE_VADD_qr_i16_MVE_VADD_qr_i32_MVE_VADD_qr_i8 = 1296, |
| 5828 | MVE_VHADD_qr_s16_MVE_VHADD_qr_s32_MVE_VHADD_qr_s8_MVE_VHADD_qr_u16_MVE_VHADD_qr_u32_MVE_VHADD_qr_u8 = 1297, |
| 5829 | MVE_VHSUB_qr_s16_MVE_VHSUB_qr_s32_MVE_VHSUB_qr_s8_MVE_VHSUB_qr_u16_MVE_VHSUB_qr_u32_MVE_VHSUB_qr_u8 = 1298, |
| 5830 | MVE_VQADD_qr_s16_MVE_VQADD_qr_s32_MVE_VQADD_qr_s8_MVE_VQADD_qr_u16_MVE_VQADD_qr_u32_MVE_VQADD_qr_u8 = 1299, |
| 5831 | MVE_VQSUB_qr_s16_MVE_VQSUB_qr_s32_MVE_VQSUB_qr_s8_MVE_VQSUB_qr_u16_MVE_VQSUB_qr_u32_MVE_VQSUB_qr_u8 = 1300, |
| 5832 | MVE_VSHL_qrs16_MVE_VSHL_qrs32_MVE_VSHL_qrs8_MVE_VSHL_qru16_MVE_VSHL_qru32_MVE_VSHL_qru8 = 1301, |
| 5833 | MVE_VSUB_qr_i16_MVE_VSUB_qr_i32_MVE_VSUB_qr_i8 = 1302, |
| 5834 | MVE_VSHL_by_vecs16_MVE_VSHL_by_vecs32_MVE_VSHL_by_vecs8_MVE_VSHL_by_vecu16_MVE_VSHL_by_vecu32_MVE_VSHL_by_vecu8_MVE_VSHL_immi16_MVE_VSHL_immi32_MVE_VSHL_immi8_MVE_VSHLL_imms16bh_MVE_VSHLL_imms16th_MVE_VSHLL_imms8bh_MVE_VSHLL_imms8th_MVE_VSHLL_immu16bh_MVE_VSHLL_immu16th_MVE_VSHLL_immu8bh_MVE_VSHLL_immu8th_MVE_VSHLL_lws16bh_MVE_VSHLL_lws16th_MVE_VSHLL_lws8bh_MVE_VSHLL_lws8th_MVE_VSHLL_lwu16bh_MVE_VSHLL_lwu16th_MVE_VSHLL_lwu8bh_MVE_VSHLL_lwu8th = 1303, |
| 5835 | MVE_VSHRNi16bh_MVE_VSHRNi16th_MVE_VSHRNi32bh_MVE_VSHRNi32th = 1304, |
| 5836 | MVE_VDWDUPu16_MVE_VDWDUPu32_MVE_VDWDUPu8_MVE_VIWDUPu16_MVE_VIWDUPu32_MVE_VIWDUPu8 = 1305, |
| 5837 | MVE_VDDUPu16_MVE_VDDUPu32_MVE_VDDUPu8_MVE_VIDUPu16_MVE_VIDUPu32_MVE_VIDUPu8 = 1306, |
| 5838 | MVE_VQRSHL_qrs16_MVE_VQRSHL_qrs32_MVE_VQRSHL_qrs8_MVE_VQRSHL_qru16_MVE_VQRSHL_qru32_MVE_VQRSHL_qru8 = 1307, |
| 5839 | MVE_VQSHL_qrs16_MVE_VQSHL_qrs32_MVE_VQSHL_qrs8_MVE_VQSHL_qru16_MVE_VQSHL_qru32_MVE_VQSHL_qru8_MVE_VRSHL_qrs16_MVE_VRSHL_qrs32_MVE_VRSHL_qrs8_MVE_VRSHL_qru16_MVE_VRSHL_qru32_MVE_VRSHL_qru8 = 1308, |
| 5840 | MVE_VMAXNMAf16_MVE_VMAXNMAf32_MVE_VMAXNMf16_MVE_VMAXNMf32_MVE_VMINNMAf16_MVE_VMINNMAf32_MVE_VMINNMf16_MVE_VMINNMf32 = 1309, |
| 5841 | MVE_VADDLVs32acc_MVE_VADDLVu32acc = 1310, |
| 5842 | MVE_VADDVs16acc_MVE_VADDVs32acc_MVE_VADDVs8acc_MVE_VADDVu16acc_MVE_VADDVu32acc_MVE_VADDVu8acc = 1311, |
| 5843 | MVE_VMUL_qr_i16_MVE_VMUL_qr_i32_MVE_VMUL_qr_i8 = 1312, |
| 5844 | MVE_VQDMULH_qr_s16_MVE_VQDMULH_qr_s32_MVE_VQDMULH_qr_s8_MVE_VQRDMULH_qr_s16_MVE_VQRDMULH_qr_s32_MVE_VQRDMULH_qr_s8 = 1313, |
| 5845 | MVE_VMLAS_qr_i16_MVE_VMLAS_qr_i32_MVE_VMLAS_qr_i8_MVE_VMLA_qr_i16_MVE_VMLA_qr_i32_MVE_VMLA_qr_i8 = 1314, |
| 5846 | MVE_VQDMLAH_qrs16_MVE_VQDMLAH_qrs32_MVE_VQDMLAH_qrs8_MVE_VQDMLASH_qrs16_MVE_VQDMLASH_qrs32_MVE_VQDMLASH_qrs8_MVE_VQRDMLAH_qrs16_MVE_VQRDMLAH_qrs32_MVE_VQRDMLAH_qrs8_MVE_VQRDMLASH_qrs16_MVE_VQRDMLASH_qrs32_MVE_VQRDMLASH_qrs8 = 1315, |
| 5847 | MVE_VQDMLADHXs16_MVE_VQDMLADHXs32_MVE_VQDMLADHXs8_MVE_VQDMLADHs16_MVE_VQDMLADHs32_MVE_VQDMLADHs8_MVE_VQDMLSDHXs16_MVE_VQDMLSDHXs32_MVE_VQDMLSDHXs8_MVE_VQDMLSDHs16_MVE_VQDMLSDHs32_MVE_VQDMLSDHs8_MVE_VQRDMLADHXs16_MVE_VQRDMLADHXs32_MVE_VQRDMLADHXs8_MVE_VQRDMLADHs16_MVE_VQRDMLADHs32_MVE_VQRDMLADHs8_MVE_VQRDMLSDHXs16_MVE_VQRDMLSDHXs32_MVE_VQRDMLSDHXs8_MVE_VQRDMLSDHs16_MVE_VQRDMLSDHs32_MVE_VQRDMLSDHs8 = 1316, |
| 5848 | MVE_VMLALDAVas16_MVE_VMLALDAVas32_MVE_VMLALDAVau16_MVE_VMLALDAVau32_MVE_VMLALDAVaxs16_MVE_VMLALDAVaxs32_MVE_VMLSLDAVas16_MVE_VMLSLDAVas32_MVE_VMLSLDAVaxs16_MVE_VMLSLDAVaxs32_MVE_VRMLALDAVHas32_MVE_VRMLALDAVHau32_MVE_VRMLALDAVHaxs32_MVE_VRMLSLDAVHas32_MVE_VRMLSLDAVHaxs32 = 1317, |
| 5849 | MVE_VMLADAVas16_MVE_VMLADAVas32_MVE_VMLADAVas8_MVE_VMLADAVau16_MVE_VMLADAVau32_MVE_VMLADAVau8_MVE_VMLADAVaxs16_MVE_VMLADAVaxs32_MVE_VMLADAVaxs8_MVE_VMLSDAVas16_MVE_VMLSDAVas32_MVE_VMLSDAVas8_MVE_VMLSDAVaxs16_MVE_VMLSDAVaxs32_MVE_VMLSDAVaxs8 = 1318, |
| 5850 | MVE_VMULi16_MVE_VMULi32_MVE_VMULi8 = 1319, |
| 5851 | MVE_VMUL_qr_f16_MVE_VMUL_qr_f32 = 1320, |
| 5852 | MVE_VFMA_qr_Sf16_MVE_VFMA_qr_Sf32_MVE_VFMA_qr_f16_MVE_VFMA_qr_f32 = 1321, |
| 5853 | MVE_VPTv4f32r_MVE_VPTv8f16r = 1322, |
| 5854 | MVE_VPTv16i8r_MVE_VPTv16s8r_MVE_VPTv16u8r_MVE_VPTv4i32r_MVE_VPTv4s32r_MVE_VPTv4u32r_MVE_VPTv8i16r_MVE_VPTv8s16r_MVE_VPTv8u16r = 1323, |
| 5855 | MVE_VCMPi16r_MVE_VCMPi32r_MVE_VCMPi8r_MVE_VCMPs16r_MVE_VCMPs32r_MVE_VCMPs8r_MVE_VCMPu16r_MVE_VCMPu32r_MVE_VCMPu8r = 1324, |
| 5856 | MVE_VCMPf16r_MVE_VCMPf32r = 1325, |
| 5857 | SCHED_LIST_END = 1326 |
| 5858 | }; |
| 5859 | } // end namespace llvm::ARM::Sched |
| 5860 | #endif // GET_INSTRINFO_SCHED_ENUM |
| 5861 | |
| 5862 | #if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR) |
| 5863 | namespace llvm { |
| 5864 | |
| 5865 | struct ARMInstrTable { |
| 5866 | MCInstrDesc Insts[4507]; |
| 5867 | static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo"); |
| 5868 | MCOperandInfo OperandInfo[3099]; |
| 5869 | static_assert(alignof(MCOperandInfo) >= alignof(MCPhysReg), "Unwanted padding between OperandInfo and ImplicitOps"); |
| 5870 | MCPhysReg ImplicitOps[233]; |
| 5871 | }; |
| 5872 | |
| 5873 | } // end namespace llvm |
| 5874 | #endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR) |
| 5875 | |
| 5876 | #ifdef GET_INSTRINFO_MC_DESC |
| 5877 | #undef GET_INSTRINFO_MC_DESC |
| 5878 | namespace llvm { |
| 5879 | |
| 5880 | static_assert(sizeof(MCOperandInfo) % sizeof(MCPhysReg) == 0); |
| 5881 | static constexpr unsigned ARMImpOpBase = sizeof ARMInstrTable::OperandInfo / (sizeof(MCPhysReg)); |
| 5882 | |
| 5883 | extern const ARMInstrTable ARMDescs = { |
| 5884 | { |
| 5885 | { 4506, 0, 0, 2, 845, 0, 0, 1, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4506 = t__brkdiv0 |
| 5886 | { 4505, 4, 1, 2, 898, 0, 0, 3053, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4505 = tUXTH |
| 5887 | { 4504, 4, 1, 2, 898, 0, 0, 3053, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4504 = tUXTB |
| 5888 | { 4503, 1, 0, 2, 1091, 0, 0, 0, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4503 = tUDF |
| 5889 | { 4502, 4, 0, 2, 1090, 0, 1, 3053, ARMImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0xc80ULL }, // Inst #4502 = tTST |
| 5890 | { 4501, 0, 0, 2, 1089, 0, 0, 1, ARMImpOpBase + 0, 0|(1ULL<<MCID::Trap)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4501 = tTRAP |
| 5891 | { 4500, 4, 1, 2, 898, 0, 0, 3053, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4500 = tSXTH |
| 5892 | { 4499, 4, 1, 2, 898, 0, 0, 3053, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4499 = tSXTB |
| 5893 | { 4498, 3, 0, 2, 1216, 1, 0, 858, ARMImpOpBase + 54, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4498 = tSVC |
| 5894 | { 4497, 5, 1, 2, 1275, 0, 0, 3031, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4497 = tSUBspi |
| 5895 | { 4496, 6, 2, 2, 1078, 0, 0, 3025, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL }, // Inst #4496 = tSUBrr |
| 5896 | { 4495, 6, 2, 2, 1109, 0, 0, 3009, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL }, // Inst #4495 = tSUBi8 |
| 5897 | { 4494, 6, 2, 2, 1109, 0, 0, 3003, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL }, // Inst #4494 = tSUBi3 |
| 5898 | { 4493, 5, 0, 2, 1088, 0, 0, 3075, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8aULL }, // Inst #4493 = tSTRspi |
| 5899 | { 4492, 5, 0, 2, 435, 0, 0, 3066, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc89ULL }, // Inst #4492 = tSTRr |
| 5900 | { 4491, 5, 0, 2, 1088, 0, 0, 3061, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc89ULL }, // Inst #4491 = tSTRi |
| 5901 | { 4490, 5, 0, 2, 434, 0, 0, 3066, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc88ULL }, // Inst #4490 = tSTRHr |
| 5902 | { 4489, 5, 0, 2, 1087, 0, 0, 3061, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc88ULL }, // Inst #4489 = tSTRHi |
| 5903 | { 4488, 5, 0, 2, 434, 0, 0, 3066, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc87ULL }, // Inst #4488 = tSTRBr |
| 5904 | { 4487, 5, 0, 2, 1087, 0, 0, 3061, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc87ULL }, // Inst #4487 = tSTRBi |
| 5905 | { 4486, 5, 1, 2, 1026, 0, 0, 558, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc80ULL }, // Inst #4486 = tSTMIA_UPD |
| 5906 | { 4485, 1, 0, 2, 1077, 0, 0, 0, ARMImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4485 = tSETEND |
| 5907 | { 4484, 6, 2, 2, 1078, 1, 0, 2997, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::UnmodeledSideEffects), 0x80c80ULL }, // Inst #4484 = tSBC |
| 5908 | { 4483, 5, 2, 2, 1079, 0, 0, 3091, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL }, // Inst #4483 = tRSB |
| 5909 | { 4482, 6, 2, 2, 880, 0, 0, 2997, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL }, // Inst #4482 = tROR |
| 5910 | { 4481, 4, 1, 2, 1032, 0, 0, 3053, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4481 = tREVSH |
| 5911 | { 4480, 4, 1, 2, 1032, 0, 0, 3053, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4480 = tREV16 |
| 5912 | { 4479, 4, 1, 2, 1032, 0, 0, 3053, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4479 = tREV |
| 5913 | { 4478, 3, 0, 2, 452, 1, 1, 584, ARMImpOpBase + 1, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc80ULL }, // Inst #4478 = tPUSH |
| 5914 | { 4477, 3, 0, 2, 424, 1, 1, 584, ARMImpOpBase + 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0xc80ULL }, // Inst #4477 = tPOP |
| 5915 | { 4476, 3, 1, 2, 1078, 0, 0, 3096, ARMImpOpBase + 0, 0|(1ULL<<MCID::NotDuplicable), 0xc80ULL }, // Inst #4476 = tPICADD |
| 5916 | { 4475, 6, 2, 2, 1080, 0, 0, 2997, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL }, // Inst #4475 = tORR |
| 5917 | { 4474, 5, 2, 2, 872, 0, 0, 3091, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL }, // Inst #4474 = tMVN |
| 5918 | { 4473, 6, 2, 2, 883, 0, 0, 3085, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL }, // Inst #4473 = tMUL |
| 5919 | { 4472, 4, 1, 2, 1027, 0, 0, 837, ARMImpOpBase + 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4472 = tMOVr |
| 5920 | { 4471, 5, 2, 2, 1028, 0, 0, 3080, ARMImpOpBase + 0, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL }, // Inst #4471 = tMOVi8 |
| 5921 | { 4470, 2, 1, 2, 1086, 0, 1, 587, ARMImpOpBase + 0, 0|(1ULL<<MCID::MoveReg), 0xc80ULL }, // Inst #4470 = tMOVSr |
| 5922 | { 4469, 6, 2, 2, 881, 0, 0, 2997, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL }, // Inst #4469 = tLSRrr |
| 5923 | { 4468, 6, 2, 2, 1081, 0, 0, 3003, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL }, // Inst #4468 = tLSRri |
| 5924 | { 4467, 6, 2, 2, 881, 0, 0, 2997, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL }, // Inst #4467 = tLSLrr |
| 5925 | { 4466, 6, 2, 2, 1081, 0, 0, 3003, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL }, // Inst #4466 = tLSLri |
| 5926 | { 4465, 5, 1, 2, 1261, 0, 0, 3075, ARMImpOpBase + 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc8aULL }, // Inst #4465 = tLDRspi |
| 5927 | { 4464, 5, 1, 2, 395, 0, 0, 3066, ARMImpOpBase + 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc89ULL }, // Inst #4464 = tLDRr |
| 5928 | { 4463, 4, 1, 2, 1231, 0, 0, 3071, ARMImpOpBase + 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc8aULL }, // Inst #4463 = tLDRpci |
| 5929 | { 4462, 5, 1, 2, 906, 0, 0, 3061, ARMImpOpBase + 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc89ULL }, // Inst #4462 = tLDRi |
| 5930 | { 4461, 5, 1, 2, 401, 0, 0, 3066, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc88ULL }, // Inst #4461 = tLDRSH |
| 5931 | { 4460, 5, 1, 2, 401, 0, 0, 3066, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc87ULL }, // Inst #4460 = tLDRSB |
| 5932 | { 4459, 5, 1, 2, 394, 0, 0, 3066, ARMImpOpBase + 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc88ULL }, // Inst #4459 = tLDRHr |
| 5933 | { 4458, 5, 1, 2, 905, 0, 0, 3061, ARMImpOpBase + 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc88ULL }, // Inst #4458 = tLDRHi |
| 5934 | { 4457, 5, 1, 2, 394, 0, 0, 3066, ARMImpOpBase + 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc87ULL }, // Inst #4457 = tLDRBr |
| 5935 | { 4456, 5, 1, 2, 905, 0, 0, 3061, ARMImpOpBase + 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc87ULL }, // Inst #4456 = tLDRBi |
| 5936 | { 4455, 4, 0, 2, 1018, 0, 0, 3057, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0xc80ULL }, // Inst #4455 = tLDMIA |
| 5937 | { 4454, 2, 0, 12, 1039, 0, 10, 587, ARMImpOpBase + 223, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4454 = tInt_eh_sjlj_setjmp |
| 5938 | { 4453, 2, 0, 10, 1039, 0, 3, 587, ARMImpOpBase + 5, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #4453 = tInt_eh_sjlj_longjmp |
| 5939 | { 4452, 2, 0, 12, 851, 0, 3, 152, ARMImpOpBase + 220, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #4452 = tInt_WIN_eh_sjlj_longjmp |
| 5940 | { 4451, 1, 0, 2, 1077, 0, 0, 0, ARMImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4451 = tHLT |
| 5941 | { 4450, 3, 0, 2, 1219, 0, 0, 858, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4450 = tHINT |
| 5942 | { 4449, 6, 2, 2, 1080, 0, 0, 2997, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL }, // Inst #4449 = tEOR |
| 5943 | { 4448, 2, 0, 2, 1085, 0, 0, 13, ARMImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4448 = tCPS |
| 5944 | { 4447, 4, 0, 2, 1083, 0, 1, 3053, ARMImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4447 = tCMPr |
| 5945 | { 4446, 4, 0, 2, 1084, 0, 1, 563, ARMImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4446 = tCMPi8 |
| 5946 | { 4445, 4, 0, 2, 1083, 0, 1, 837, ARMImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4445 = tCMPhir |
| 5947 | { 4444, 4, 0, 2, 1083, 0, 1, 3053, ARMImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4444 = tCMNz |
| 5948 | { 4443, 2, 0, 2, 1082, 0, 0, 3051, ARMImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4443 = tCBZ |
| 5949 | { 4442, 2, 0, 2, 1082, 0, 0, 3051, ARMImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4442 = tCBNZ |
| 5950 | { 4441, 3, 0, 2, 1092, 0, 0, 545, ARMImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4441 = tBcc |
| 5951 | { 4440, 3, 0, 2, 1092, 0, 0, 535, ARMImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4440 = tBXNS |
| 5952 | { 4439, 3, 0, 2, 1092, 0, 0, 535, ARMImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4439 = tBX |
| 5953 | { 4438, 3, 0, 2, 1093, 1, 1, 3048, ARMImpOpBase + 3, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4438 = tBLXr |
| 5954 | { 4437, 3, 0, 4, 856, 1, 1, 431, ARMImpOpBase + 3, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4437 = tBLXi |
| 5955 | { 4436, 3, 0, 2, 1093, 1, 1, 3045, ARMImpOpBase + 3, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4436 = tBLXNSr |
| 5956 | { 4435, 3, 0, 4, 856, 1, 1, 431, ARMImpOpBase + 3, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4435 = tBL |
| 5957 | { 4434, 1, 0, 2, 1038, 0, 0, 0, ARMImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4434 = tBKPT |
| 5958 | { 4433, 6, 2, 2, 1080, 0, 0, 2997, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL }, // Inst #4433 = tBIC |
| 5959 | { 4432, 3, 0, 2, 1092, 0, 0, 545, ARMImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0xc80ULL }, // Inst #4432 = tB |
| 5960 | { 4431, 6, 2, 2, 881, 0, 0, 2997, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL }, // Inst #4431 = tASRrr |
| 5961 | { 4430, 6, 2, 2, 1081, 0, 0, 3003, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL }, // Inst #4430 = tASRri |
| 5962 | { 4429, 6, 2, 2, 1080, 0, 0, 2997, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL }, // Inst #4429 = tAND |
| 5963 | { 4428, 4, 1, 2, 1079, 0, 0, 3041, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4428 = tADR |
| 5964 | { 4427, 5, 1, 2, 1280, 0, 0, 3036, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4427 = tADDspr |
| 5965 | { 4426, 5, 1, 2, 1275, 0, 0, 3031, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4426 = tADDspi |
| 5966 | { 4425, 6, 2, 2, 1078, 0, 0, 3025, ARMImpOpBase + 0, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL }, // Inst #4425 = tADDrr |
| 5967 | { 4424, 5, 1, 2, 1281, 0, 0, 3020, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4424 = tADDrSPi |
| 5968 | { 4423, 5, 1, 2, 1280, 0, 0, 3015, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4423 = tADDrSP |
| 5969 | { 4422, 6, 2, 2, 1109, 0, 0, 3009, ARMImpOpBase + 0, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL }, // Inst #4422 = tADDi8 |
| 5970 | { 4421, 6, 2, 2, 1109, 0, 0, 3003, ARMImpOpBase + 0, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL }, // Inst #4421 = tADDi3 |
| 5971 | { 4420, 5, 1, 2, 1280, 0, 0, 277, ARMImpOpBase + 0, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4420 = tADDhirr |
| 5972 | { 4419, 6, 2, 2, 1078, 1, 0, 2997, ARMImpOpBase + 0, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::UnmodeledSideEffects), 0x80c80ULL }, // Inst #4419 = tADC |
| 5973 | { 4418, 3, 1, 4, 1286, 0, 0, 511, ARMImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4418 = t2WLS |
| 5974 | { 4417, 5, 1, 4, 897, 0, 0, 494, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4417 = t2UXTH |
| 5975 | { 4416, 5, 1, 4, 352, 0, 0, 494, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4416 = t2UXTB16 |
| 5976 | { 4415, 5, 1, 4, 897, 0, 0, 494, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4415 = t2UXTB |
| 5977 | { 4414, 6, 1, 4, 1100, 0, 0, 2904, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4414 = t2UXTAH |
| 5978 | { 4413, 6, 1, 4, 1101, 0, 0, 2904, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4413 = t2UXTAB16 |
| 5979 | { 4412, 6, 1, 4, 1100, 0, 0, 2904, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4412 = t2UXTAB |
| 5980 | { 4411, 5, 1, 4, 885, 0, 0, 2883, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4411 = t2USUB8 |
| 5981 | { 4410, 5, 1, 4, 885, 0, 0, 2883, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4410 = t2USUB16 |
| 5982 | { 4409, 5, 1, 4, 364, 0, 0, 2883, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4409 = t2USAX |
| 5983 | { 4408, 5, 1, 4, 362, 0, 0, 2942, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4408 = t2USAT16 |
| 5984 | { 4407, 6, 1, 4, 362, 0, 0, 2936, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4407 = t2USAT |
| 5985 | { 4406, 6, 1, 4, 684, 0, 0, 2856, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4406 = t2USADA8 |
| 5986 | { 4405, 5, 1, 4, 1246, 0, 0, 2883, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4405 = t2USAD8 |
| 5987 | { 4404, 5, 1, 4, 889, 0, 0, 2883, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4404 = t2UQSUB8 |
| 5988 | { 4403, 5, 1, 4, 889, 0, 0, 2883, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4403 = t2UQSUB16 |
| 5989 | { 4402, 5, 1, 4, 891, 0, 0, 2883, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4402 = t2UQSAX |
| 5990 | { 4401, 5, 1, 4, 891, 0, 0, 2883, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4401 = t2UQASX |
| 5991 | { 4400, 5, 1, 4, 889, 0, 0, 2883, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4400 = t2UQADD8 |
| 5992 | { 4399, 5, 1, 4, 889, 0, 0, 2883, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4399 = t2UQADD16 |
| 5993 | { 4398, 6, 2, 4, 382, 0, 0, 2856, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0xc80ULL }, // Inst #4398 = t2UMULL |
| 5994 | { 4397, 8, 2, 4, 383, 0, 0, 2928, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4397 = t2UMLAL |
| 5995 | { 4396, 8, 2, 4, 383, 0, 0, 2928, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4396 = t2UMAAL |
| 5996 | { 4395, 5, 1, 4, 887, 0, 0, 2883, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4395 = t2UHSUB8 |
| 5997 | { 4394, 5, 1, 4, 887, 0, 0, 2883, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4394 = t2UHSUB16 |
| 5998 | { 4393, 5, 1, 4, 367, 0, 0, 2883, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4393 = t2UHSAX |
| 5999 | { 4392, 5, 1, 4, 367, 0, 0, 2883, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4392 = t2UHASX |
| 6000 | { 4391, 5, 1, 4, 887, 0, 0, 2883, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4391 = t2UHADD8 |
| 6001 | { 4390, 5, 1, 4, 887, 0, 0, 2883, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4390 = t2UHADD16 |
| 6002 | { 4389, 5, 1, 4, 685, 0, 0, 2883, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4389 = t2UDIV |
| 6003 | { 4388, 1, 0, 4, 1037, 0, 0, 0, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4388 = t2UDF |
| 6004 | { 4387, 6, 1, 4, 895, 0, 0, 2922, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4387 = t2UBFX |
| 6005 | { 4386, 5, 1, 4, 364, 0, 0, 2883, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4386 = t2UASX |
| 6006 | { 4385, 5, 1, 4, 885, 0, 0, 2883, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4385 = t2UADD8 |
| 6007 | { 4384, 5, 1, 4, 885, 0, 0, 2883, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4384 = t2UADD16 |
| 6008 | { 4383, 4, 1, 4, 1057, 0, 0, 2993, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4383 = t2TTT |
| 6009 | { 4382, 4, 1, 4, 1057, 0, 0, 2993, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4382 = t2TTAT |
| 6010 | { 4381, 4, 1, 4, 1057, 0, 0, 2993, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4381 = t2TTA |
| 6011 | { 4380, 4, 1, 4, 1057, 0, 0, 2993, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4380 = t2TT |
| 6012 | { 4379, 5, 0, 4, 1242, 0, 1, 479, ARMImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4379 = t2TSTrs |
| 6013 | { 4378, 4, 0, 4, 1073, 0, 1, 2752, ARMImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4378 = t2TSTrr |
| 6014 | { 4377, 4, 0, 4, 310, 0, 1, 2748, ARMImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4377 = t2TSTri |
| 6015 | { 4376, 3, 0, 4, 0, 0, 0, 858, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4376 = t2TSB |
| 6016 | { 4375, 5, 0, 4, 1242, 0, 1, 479, ARMImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4375 = t2TEQrs |
| 6017 | { 4374, 4, 0, 4, 1073, 0, 1, 2752, ARMImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4374 = t2TEQrr |
| 6018 | { 4373, 4, 0, 4, 310, 0, 1, 2748, ARMImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4373 = t2TEQri |
| 6019 | { 4372, 4, 0, 4, 1235, 0, 0, 2989, ARMImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4372 = t2TBH |
| 6020 | { 4371, 4, 0, 4, 1235, 0, 0, 2989, ARMImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4371 = t2TBB |
| 6021 | { 4370, 5, 1, 4, 897, 0, 0, 494, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4370 = t2SXTH |
| 6022 | { 4369, 5, 1, 4, 352, 0, 0, 494, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4369 = t2SXTB16 |
| 6023 | { 4368, 5, 1, 4, 897, 0, 0, 494, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4368 = t2SXTB |
| 6024 | { 4367, 6, 1, 4, 900, 0, 0, 2904, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4367 = t2SXTAH |
| 6025 | { 4366, 6, 1, 4, 368, 0, 0, 2904, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4366 = t2SXTAB16 |
| 6026 | { 4365, 6, 1, 4, 900, 0, 0, 2904, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4365 = t2SXTAB |
| 6027 | { 4364, 5, 1, 4, 1, 0, 0, 2743, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4364 = t2SUBspImm12 |
| 6028 | { 4363, 6, 1, 4, 1, 0, 0, 2737, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4363 = t2SUBspImm |
| 6029 | { 4362, 7, 1, 4, 1236, 0, 0, 2730, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // Inst #4362 = t2SUBrs |
| 6030 | { 4361, 6, 1, 4, 1072, 0, 0, 2724, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // Inst #4361 = t2SUBrr |
| 6031 | { 4360, 5, 1, 4, 1279, 0, 0, 2719, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4360 = t2SUBri12 |
| 6032 | { 4359, 6, 1, 4, 1278, 0, 0, 2713, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // Inst #4359 = t2SUBri |
| 6033 | { 4358, 3, 0, 4, 1059, 0, 1, 858, ARMImpOpBase + 66, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0xc80ULL }, // Inst #4358 = t2SUBS_PC_LR |
| 6034 | { 4357, 6, 0, 4, 431, 0, 0, 2843, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8fULL }, // Inst #4357 = t2STRs |
| 6035 | { 4356, 5, 0, 4, 430, 0, 0, 321, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8eULL }, // Inst #4356 = t2STRi8 |
| 6036 | { 4355, 5, 0, 4, 1074, 0, 0, 321, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8bULL }, // Inst #4355 = t2STRi12 |
| 6037 | { 4354, 6, 1, 4, 944, 0, 0, 2983, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xcacULL }, // Inst #4354 = t2STR_PRE |
| 6038 | { 4353, 6, 1, 4, 441, 0, 0, 2983, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xcccULL }, // Inst #4353 = t2STR_POST |
| 6039 | { 4352, 5, 0, 4, 445, 0, 0, 2806, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8dULL }, // Inst #4352 = t2STRT |
| 6040 | { 4351, 6, 0, 4, 433, 0, 0, 2964, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8fULL }, // Inst #4351 = t2STRHs |
| 6041 | { 4350, 5, 0, 4, 432, 0, 0, 2806, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8eULL }, // Inst #4350 = t2STRHi8 |
| 6042 | { 4349, 5, 0, 4, 1075, 0, 0, 2806, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8bULL }, // Inst #4349 = t2STRHi12 |
| 6043 | { 4348, 6, 1, 4, 944, 0, 0, 2958, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xcacULL }, // Inst #4348 = t2STRH_PRE |
| 6044 | { 4347, 6, 1, 4, 442, 0, 0, 2958, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xcccULL }, // Inst #4347 = t2STRH_POST |
| 6045 | { 4346, 5, 0, 4, 444, 0, 0, 2806, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8dULL }, // Inst #4346 = t2STRHT |
| 6046 | { 4345, 5, 1, 4, 1228, 0, 0, 2947, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4345 = t2STREXH |
| 6047 | { 4344, 6, 1, 4, 730, 0, 0, 2952, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc80ULL }, // Inst #4344 = t2STREXD |
| 6048 | { 4343, 5, 1, 4, 1228, 0, 0, 2947, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4343 = t2STREXB |
| 6049 | { 4342, 6, 1, 4, 1228, 0, 0, 2977, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc94ULL }, // Inst #4342 = t2STREX |
| 6050 | { 4341, 6, 0, 4, 447, 0, 0, 2828, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc91ULL }, // Inst #4341 = t2STRDi8 |
| 6051 | { 4340, 7, 1, 4, 946, 0, 0, 2970, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc91ULL }, // Inst #4340 = t2STRD_PRE |
| 6052 | { 4339, 7, 1, 4, 448, 0, 0, 2970, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc91ULL }, // Inst #4339 = t2STRD_POST |
| 6053 | { 4338, 6, 0, 4, 433, 0, 0, 2964, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8fULL }, // Inst #4338 = t2STRBs |
| 6054 | { 4337, 5, 0, 4, 432, 0, 0, 2806, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8eULL }, // Inst #4337 = t2STRBi8 |
| 6055 | { 4336, 5, 0, 4, 1075, 0, 0, 2806, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8bULL }, // Inst #4336 = t2STRBi12 |
| 6056 | { 4335, 6, 1, 4, 945, 0, 0, 2958, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xcacULL }, // Inst #4335 = t2STRB_PRE |
| 6057 | { 4334, 6, 1, 4, 953, 0, 0, 2958, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xcccULL }, // Inst #4334 = t2STRB_POST |
| 6058 | { 4333, 5, 0, 4, 938, 0, 0, 2806, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8dULL }, // Inst #4333 = t2STRBT |
| 6059 | { 4332, 5, 1, 4, 1076, 0, 0, 234, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc80ULL }, // Inst #4332 = t2STMIA_UPD |
| 6060 | { 4331, 4, 0, 4, 1025, 0, 0, 873, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc80ULL }, // Inst #4331 = t2STMIA |
| 6061 | { 4330, 5, 1, 4, 1076, 0, 0, 234, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc80ULL }, // Inst #4330 = t2STMDB_UPD |
| 6062 | { 4329, 4, 0, 4, 1025, 0, 0, 873, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc80ULL }, // Inst #4329 = t2STMDB |
| 6063 | { 4328, 4, 0, 4, 1264, 0, 0, 2797, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4328 = t2STLH |
| 6064 | { 4327, 5, 1, 4, 1264, 0, 0, 2947, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4327 = t2STLEXH |
| 6065 | { 4326, 6, 1, 4, 732, 0, 0, 2952, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc80ULL }, // Inst #4326 = t2STLEXD |
| 6066 | { 4325, 5, 1, 4, 1264, 0, 0, 2947, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4325 = t2STLEXB |
| 6067 | { 4324, 5, 1, 4, 1264, 0, 0, 2947, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4324 = t2STLEX |
| 6068 | { 4323, 4, 0, 4, 1264, 0, 0, 2797, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4323 = t2STLB |
| 6069 | { 4322, 4, 0, 4, 1264, 0, 0, 2797, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4322 = t2STL |
| 6070 | { 4321, 6, 0, 4, 1035, 0, 0, 889, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4321 = t2STC_PRE |
| 6071 | { 4320, 6, 0, 4, 1035, 0, 0, 889, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4320 = t2STC_POST |
| 6072 | { 4319, 6, 0, 4, 1035, 0, 0, 895, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4319 = t2STC_OPTION |
| 6073 | { 4318, 6, 0, 4, 1035, 0, 0, 889, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc85ULL }, // Inst #4318 = t2STC_OFFSET |
| 6074 | { 4317, 6, 0, 4, 1035, 0, 0, 889, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4317 = t2STCL_PRE |
| 6075 | { 4316, 6, 0, 4, 1035, 0, 0, 889, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4316 = t2STCL_POST |
| 6076 | { 4315, 6, 0, 4, 1035, 0, 0, 895, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4315 = t2STCL_OPTION |
| 6077 | { 4314, 6, 0, 4, 1035, 0, 0, 889, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc85ULL }, // Inst #4314 = t2STCL_OFFSET |
| 6078 | { 4313, 6, 0, 4, 1035, 0, 0, 889, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4313 = t2STC2_PRE |
| 6079 | { 4312, 6, 0, 4, 1035, 0, 0, 889, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4312 = t2STC2_POST |
| 6080 | { 4311, 6, 0, 4, 1035, 0, 0, 895, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4311 = t2STC2_OPTION |
| 6081 | { 4310, 6, 0, 4, 1035, 0, 0, 889, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc85ULL }, // Inst #4310 = t2STC2_OFFSET |
| 6082 | { 4309, 6, 0, 4, 1035, 0, 0, 889, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4309 = t2STC2L_PRE |
| 6083 | { 4308, 6, 0, 4, 1035, 0, 0, 889, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4308 = t2STC2L_POST |
| 6084 | { 4307, 6, 0, 4, 1035, 0, 0, 895, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4307 = t2STC2L_OPTION |
| 6085 | { 4306, 6, 0, 4, 1035, 0, 0, 889, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc85ULL }, // Inst #4306 = t2STC2L_OFFSET |
| 6086 | { 4305, 5, 1, 4, 885, 0, 0, 2883, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4305 = t2SSUB8 |
| 6087 | { 4304, 5, 1, 4, 885, 0, 0, 2883, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4304 = t2SSUB16 |
| 6088 | { 4303, 5, 1, 4, 364, 0, 0, 2883, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4303 = t2SSAX |
| 6089 | { 4302, 5, 1, 4, 362, 0, 0, 2942, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4302 = t2SSAT16 |
| 6090 | { 4301, 6, 1, 4, 362, 0, 0, 2936, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4301 = t2SSAT |
| 6091 | { 4300, 3, 0, 4, 729, 0, 0, 858, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4300 = t2SRSIA_UPD |
| 6092 | { 4299, 3, 0, 4, 729, 0, 0, 858, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4299 = t2SRSIA |
| 6093 | { 4298, 3, 0, 4, 729, 0, 0, 858, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4298 = t2SRSDB_UPD |
| 6094 | { 4297, 3, 0, 4, 729, 0, 0, 858, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4297 = t2SRSDB |
| 6095 | { 4296, 5, 1, 4, 374, 0, 0, 2883, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4296 = t2SMUSDX |
| 6096 | { 4295, 5, 1, 4, 374, 0, 0, 2883, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4295 = t2SMUSD |
| 6097 | { 4294, 5, 1, 4, 373, 0, 0, 2883, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4294 = t2SMULWT |
| 6098 | { 4293, 5, 1, 4, 373, 0, 0, 2883, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4293 = t2SMULWB |
| 6099 | { 4292, 5, 1, 4, 373, 0, 0, 2883, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4292 = t2SMULTT |
| 6100 | { 4291, 5, 1, 4, 373, 0, 0, 2883, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4291 = t2SMULTB |
| 6101 | { 4290, 6, 2, 4, 382, 0, 0, 2856, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0xc80ULL }, // Inst #4290 = t2SMULL |
| 6102 | { 4289, 5, 1, 4, 373, 0, 0, 2883, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4289 = t2SMULBT |
| 6103 | { 4288, 5, 1, 4, 373, 0, 0, 2883, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4288 = t2SMULBB |
| 6104 | { 4287, 5, 1, 4, 376, 0, 0, 2883, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4287 = t2SMUADX |
| 6105 | { 4286, 5, 1, 4, 376, 0, 0, 2883, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4286 = t2SMUAD |
| 6106 | { 4285, 5, 1, 4, 372, 0, 0, 2883, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4285 = t2SMMULR |
| 6107 | { 4284, 5, 1, 4, 372, 0, 0, 2883, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4284 = t2SMMUL |
| 6108 | { 4283, 6, 1, 4, 1099, 0, 0, 2856, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4283 = t2SMMLSR |
| 6109 | { 4282, 6, 1, 4, 1099, 0, 0, 2856, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4282 = t2SMMLS |
| 6110 | { 4281, 6, 1, 4, 1099, 0, 0, 2856, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4281 = t2SMMLAR |
| 6111 | { 4280, 6, 1, 4, 1099, 0, 0, 2856, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4280 = t2SMMLA |
| 6112 | { 4279, 8, 2, 4, 1031, 0, 0, 2928, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4279 = t2SMLSLDX |
| 6113 | { 4278, 8, 2, 4, 1031, 0, 0, 2928, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4278 = t2SMLSLD |
| 6114 | { 4277, 6, 1, 4, 379, 0, 0, 2856, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4277 = t2SMLSDX |
| 6115 | { 4276, 6, 1, 4, 379, 0, 0, 2856, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4276 = t2SMLSD |
| 6116 | { 4275, 6, 1, 4, 378, 0, 0, 2856, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4275 = t2SMLAWT |
| 6117 | { 4274, 6, 1, 4, 378, 0, 0, 2856, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4274 = t2SMLAWB |
| 6118 | { 4273, 6, 1, 4, 378, 0, 0, 2856, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4273 = t2SMLATT |
| 6119 | { 4272, 6, 1, 4, 378, 0, 0, 2856, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4272 = t2SMLATB |
| 6120 | { 4271, 8, 2, 4, 1031, 0, 0, 2928, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4271 = t2SMLALTT |
| 6121 | { 4270, 8, 2, 4, 1031, 0, 0, 2928, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4270 = t2SMLALTB |
| 6122 | { 4269, 8, 2, 4, 1031, 0, 0, 2928, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4269 = t2SMLALDX |
| 6123 | { 4268, 8, 2, 4, 1031, 0, 0, 2928, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4268 = t2SMLALD |
| 6124 | { 4267, 8, 2, 4, 1031, 0, 0, 2928, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4267 = t2SMLALBT |
| 6125 | { 4266, 8, 2, 4, 1031, 0, 0, 2928, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4266 = t2SMLALBB |
| 6126 | { 4265, 8, 2, 4, 1031, 0, 0, 2928, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4265 = t2SMLAL |
| 6127 | { 4264, 6, 1, 4, 380, 0, 0, 2856, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4264 = t2SMLADX |
| 6128 | { 4263, 6, 1, 4, 380, 0, 0, 2856, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4263 = t2SMLAD |
| 6129 | { 4262, 6, 1, 4, 378, 0, 0, 2856, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4262 = t2SMLABT |
| 6130 | { 4261, 6, 1, 4, 378, 0, 0, 2856, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4261 = t2SMLABB |
| 6131 | { 4260, 3, 0, 4, 1218, 1, 0, 858, ARMImpOpBase + 54, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4260 = t2SMC |
| 6132 | { 4259, 5, 1, 4, 887, 0, 0, 2883, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4259 = t2SHSUB8 |
| 6133 | { 4258, 5, 1, 4, 887, 0, 0, 2883, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4258 = t2SHSUB16 |
| 6134 | { 4257, 5, 1, 4, 367, 0, 0, 2883, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4257 = t2SHSAX |
| 6135 | { 4256, 5, 1, 4, 367, 0, 0, 2883, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4256 = t2SHASX |
| 6136 | { 4255, 5, 1, 4, 887, 0, 0, 2883, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4255 = t2SHADD8 |
| 6137 | { 4254, 5, 1, 4, 887, 0, 0, 2883, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4254 = t2SHADD16 |
| 6138 | { 4253, 2, 0, 4, 1057, 0, 0, 540, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4253 = t2SG |
| 6139 | { 4252, 1, 0, 2, 1077, 0, 0, 0, ARMImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4252 = t2SETPAN |
| 6140 | { 4251, 5, 1, 4, 357, 0, 0, 159, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4251 = t2SEL |
| 6141 | { 4250, 5, 1, 4, 685, 0, 0, 2883, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4250 = t2SDIV |
| 6142 | { 4249, 6, 1, 4, 895, 0, 0, 2922, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4249 = t2SBFX |
| 6143 | { 4248, 7, 1, 4, 1268, 1, 1, 2706, ARMImpOpBase + 63, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0xc80ULL }, // Inst #4248 = t2SBCrs |
| 6144 | { 4247, 6, 1, 4, 1269, 1, 1, 2700, ARMImpOpBase + 63, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0xc80ULL }, // Inst #4247 = t2SBCrr |
| 6145 | { 4246, 6, 1, 4, 692, 1, 1, 2694, ARMImpOpBase + 63, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0xc80ULL }, // Inst #4246 = t2SBCri |
| 6146 | { 4245, 0, 0, 4, 0, 0, 0, 1, ARMImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4245 = t2SB |
| 6147 | { 4244, 5, 1, 4, 364, 0, 0, 2883, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4244 = t2SASX |
| 6148 | { 4243, 5, 1, 4, 885, 0, 0, 2883, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4243 = t2SADD8 |
| 6149 | { 4242, 5, 1, 4, 885, 0, 0, 2883, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4242 = t2SADD16 |
| 6150 | { 4241, 7, 1, 4, 706, 0, 0, 2706, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // Inst #4241 = t2RSBrs |
| 6151 | { 4240, 6, 1, 4, 1270, 0, 0, 2700, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4240 = t2RSBrr |
| 6152 | { 4239, 6, 1, 4, 1071, 0, 0, 2694, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // Inst #4239 = t2RSBri |
| 6153 | { 4238, 5, 1, 4, 1244, 1, 0, 2888, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // Inst #4238 = t2RRX |
| 6154 | { 4237, 6, 1, 4, 1065, 0, 0, 2700, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // Inst #4237 = t2RORrr |
| 6155 | { 4236, 6, 1, 4, 874, 0, 0, 2694, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // Inst #4236 = t2RORri |
| 6156 | { 4235, 3, 0, 4, 729, 0, 1, 535, ARMImpOpBase + 66, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4235 = t2RFEIAW |
| 6157 | { 4234, 3, 0, 4, 729, 0, 1, 535, ARMImpOpBase + 66, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4234 = t2RFEIA |
| 6158 | { 4233, 3, 0, 4, 729, 0, 1, 535, ARMImpOpBase + 66, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4233 = t2RFEDBW |
| 6159 | { 4232, 3, 0, 4, 729, 0, 1, 535, ARMImpOpBase + 66, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4232 = t2RFEDB |
| 6160 | { 4231, 4, 1, 4, 1070, 0, 0, 2752, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4231 = t2REVSH |
| 6161 | { 4230, 4, 1, 4, 1070, 0, 0, 2752, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4230 = t2REV16 |
| 6162 | { 4229, 4, 1, 4, 1070, 0, 0, 2752, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4229 = t2REV |
| 6163 | { 4228, 4, 1, 4, 1247, 0, 0, 2752, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4228 = t2RBIT |
| 6164 | { 4227, 5, 1, 4, 889, 0, 0, 2883, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4227 = t2QSUB8 |
| 6165 | { 4226, 5, 1, 4, 889, 0, 0, 2883, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4226 = t2QSUB16 |
| 6166 | { 4225, 5, 1, 4, 889, 0, 0, 2883, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4225 = t2QSUB |
| 6167 | { 4224, 5, 1, 4, 891, 0, 0, 2883, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4224 = t2QSAX |
| 6168 | { 4223, 5, 1, 4, 361, 0, 0, 2883, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4223 = t2QDSUB |
| 6169 | { 4222, 5, 1, 4, 361, 0, 0, 2883, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4222 = t2QDADD |
| 6170 | { 4221, 5, 1, 4, 891, 0, 0, 2883, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4221 = t2QASX |
| 6171 | { 4220, 5, 1, 4, 889, 0, 0, 2883, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4220 = t2QADD8 |
| 6172 | { 4219, 5, 1, 4, 889, 0, 0, 2883, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4219 = t2QADD16 |
| 6173 | { 4218, 5, 1, 4, 889, 0, 0, 2883, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4218 = t2QADD |
| 6174 | { 4217, 5, 0, 4, 1233, 0, 0, 2914, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8fULL }, // Inst #4217 = t2PLIs |
| 6175 | { 4216, 3, 0, 4, 1230, 0, 0, 2919, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc90ULL }, // Inst #4216 = t2PLIpci |
| 6176 | { 4215, 4, 0, 4, 1232, 0, 0, 2910, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8eULL }, // Inst #4215 = t2PLIi8 |
| 6177 | { 4214, 4, 0, 4, 1232, 0, 0, 2910, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8bULL }, // Inst #4214 = t2PLIi12 |
| 6178 | { 4213, 5, 0, 4, 1233, 0, 0, 2914, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8fULL }, // Inst #4213 = t2PLDs |
| 6179 | { 4212, 3, 0, 4, 1230, 0, 0, 2919, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc90ULL }, // Inst #4212 = t2PLDpci |
| 6180 | { 4211, 4, 0, 4, 1232, 0, 0, 2910, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8eULL }, // Inst #4211 = t2PLDi8 |
| 6181 | { 4210, 4, 0, 4, 1232, 0, 0, 2910, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8bULL }, // Inst #4210 = t2PLDi12 |
| 6182 | { 4209, 5, 0, 4, 934, 0, 0, 2914, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8fULL }, // Inst #4209 = t2PLDWs |
| 6183 | { 4208, 4, 0, 4, 1232, 0, 0, 2910, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8eULL }, // Inst #4208 = t2PLDWi8 |
| 6184 | { 4207, 4, 0, 4, 1232, 0, 0, 2910, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8bULL }, // Inst #4207 = t2PLDWi12 |
| 6185 | { 4206, 6, 1, 4, 1248, 0, 0, 2904, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4206 = t2PKHTB |
| 6186 | { 4205, 6, 1, 4, 1248, 0, 0, 2904, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4205 = t2PKHBT |
| 6187 | { 4204, 5, 1, 4, 0, 0, 0, 2899, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4204 = t2PACG |
| 6188 | { 4203, 0, 0, 4, 0, 2, 1, 1, ARMImpOpBase + 217, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4203 = t2PACBTI |
| 6189 | { 4202, 0, 0, 4, 0, 2, 1, 1, ARMImpOpBase + 217, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4202 = t2PAC |
| 6190 | { 4201, 7, 1, 4, 1238, 0, 0, 2706, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // Inst #4201 = t2ORRrs |
| 6191 | { 4200, 6, 1, 4, 1069, 0, 0, 2700, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // Inst #4200 = t2ORRrr |
| 6192 | { 4199, 6, 1, 4, 694, 0, 0, 2694, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // Inst #4199 = t2ORRri |
| 6193 | { 4198, 7, 1, 4, 1239, 0, 0, 2706, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // Inst #4198 = t2ORNrs |
| 6194 | { 4197, 6, 1, 4, 1273, 0, 0, 2700, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // Inst #4197 = t2ORNrr |
| 6195 | { 4196, 6, 1, 4, 46, 0, 0, 2694, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // Inst #4196 = t2ORNri |
| 6196 | { 4195, 6, 1, 4, 698, 0, 0, 2893, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // Inst #4195 = t2MVNs |
| 6197 | { 4194, 5, 1, 4, 697, 0, 0, 2888, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // Inst #4194 = t2MVNr |
| 6198 | { 4193, 5, 1, 4, 696, 0, 0, 2862, ARMImpOpBase + 0, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::CheapAsAMove), 0xc80ULL }, // Inst #4193 = t2MVNi |
| 6199 | { 4192, 5, 1, 4, 1098, 0, 0, 2883, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0xc80ULL }, // Inst #4192 = t2MUL |
| 6200 | { 4191, 4, 0, 4, 1029, 0, 0, 2879, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4191 = t2MSRbanked |
| 6201 | { 4190, 4, 0, 4, 1029, 0, 1, 2879, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4190 = t2MSR_M |
| 6202 | { 4189, 4, 0, 4, 1029, 0, 1, 2879, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4189 = t2MSR_AR |
| 6203 | { 4188, 3, 1, 4, 1029, 0, 0, 535, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4188 = t2MRSsys_AR |
| 6204 | { 4187, 4, 1, 4, 1029, 0, 0, 2748, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4187 = t2MRSbanked |
| 6205 | { 4186, 4, 1, 4, 1029, 0, 0, 2748, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4186 = t2MRS_M |
| 6206 | { 4185, 3, 1, 4, 1029, 0, 0, 535, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4185 = t2MRS_AR |
| 6207 | { 4184, 7, 2, 4, 1034, 0, 0, 2872, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4184 = t2MRRC2 |
| 6208 | { 4183, 7, 2, 4, 1034, 0, 0, 2872, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4183 = t2MRRC |
| 6209 | { 4182, 8, 1, 4, 1095, 0, 0, 1033, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4182 = t2MRC2 |
| 6210 | { 4181, 8, 1, 4, 1095, 0, 0, 1033, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4181 = t2MRC |
| 6211 | { 4180, 5, 1, 4, 879, 0, 0, 2867, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // Inst #4180 = t2MOVr |
| 6212 | { 4179, 4, 1, 4, 682, 0, 0, 2748, ARMImpOpBase + 0, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0xc80ULL }, // Inst #4179 = t2MOVi16 |
| 6213 | { 4178, 5, 1, 4, 682, 0, 0, 2862, ARMImpOpBase + 0, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::CheapAsAMove), 0xc80ULL }, // Inst #4178 = t2MOVi |
| 6214 | { 4177, 5, 1, 4, 878, 0, 0, 464, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4177 = t2MOVTi16 |
| 6215 | { 4176, 6, 1, 4, 375, 0, 0, 2856, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4176 = t2MLS |
| 6216 | { 4175, 6, 1, 4, 375, 0, 0, 2856, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4175 = t2MLA |
| 6217 | { 4174, 7, 0, 4, 1095, 0, 0, 2849, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4174 = t2MCRR2 |
| 6218 | { 4173, 7, 0, 4, 1095, 0, 0, 2849, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4173 = t2MCRR |
| 6219 | { 4172, 8, 0, 4, 1095, 0, 0, 966, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4172 = t2MCR2 |
| 6220 | { 4171, 8, 0, 4, 1095, 0, 0, 966, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4171 = t2MCR |
| 6221 | { 4170, 4, 1, 4, 1243, 0, 1, 2752, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4170 = t2LSRs1 |
| 6222 | { 4169, 6, 1, 4, 1065, 0, 0, 2700, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // Inst #4169 = t2LSRrr |
| 6223 | { 4168, 6, 1, 4, 1064, 0, 0, 2694, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // Inst #4168 = t2LSRri |
| 6224 | { 4167, 6, 1, 4, 1065, 0, 0, 2700, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // Inst #4167 = t2LSLrr |
| 6225 | { 4166, 6, 1, 4, 1064, 0, 0, 2694, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // Inst #4166 = t2LSLri |
| 6226 | { 4165, 3, 1, 4, 1288, 0, 0, 455, ARMImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4165 = t2LEUpdate |
| 6227 | { 4164, 1, 0, 4, 1287, 0, 0, 193, ARMImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4164 = t2LE |
| 6228 | { 4163, 6, 1, 4, 390, 0, 0, 2843, ARMImpOpBase + 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc8fULL }, // Inst #4163 = t2LDRs |
| 6229 | { 4162, 4, 1, 4, 1229, 0, 0, 2839, ARMImpOpBase + 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc90ULL }, // Inst #4162 = t2LDRpci |
| 6230 | { 4161, 5, 1, 4, 389, 0, 0, 321, ARMImpOpBase + 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc8eULL }, // Inst #4161 = t2LDRi8 |
| 6231 | { 4160, 5, 1, 4, 1106, 0, 0, 321, ARMImpOpBase + 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc8bULL }, // Inst #4160 = t2LDRi12 |
| 6232 | { 4159, 6, 2, 4, 920, 0, 0, 908, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xcacULL }, // Inst #4159 = t2LDR_PRE |
| 6233 | { 4158, 6, 2, 4, 410, 0, 0, 908, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xcccULL }, // Inst #4158 = t2LDR_POST |
| 6234 | { 4157, 5, 1, 4, 412, 0, 0, 2806, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc8dULL }, // Inst #4157 = t2LDRT |
| 6235 | { 4156, 6, 1, 4, 400, 0, 0, 2815, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc8fULL }, // Inst #4156 = t2LDRSHs |
| 6236 | { 4155, 4, 1, 4, 1223, 0, 0, 2811, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc90ULL }, // Inst #4155 = t2LDRSHpci |
| 6237 | { 4154, 5, 1, 4, 399, 0, 0, 914, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc8eULL }, // Inst #4154 = t2LDRSHi8 |
| 6238 | { 4153, 5, 1, 4, 399, 0, 0, 914, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc8bULL }, // Inst #4153 = t2LDRSHi12 |
| 6239 | { 4152, 6, 2, 4, 919, 0, 0, 908, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xcacULL }, // Inst #4152 = t2LDRSH_PRE |
| 6240 | { 4151, 6, 2, 4, 414, 0, 0, 908, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xcccULL }, // Inst #4151 = t2LDRSH_POST |
| 6241 | { 4150, 5, 1, 4, 415, 0, 0, 2806, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc8dULL }, // Inst #4150 = t2LDRSHT |
| 6242 | { 4149, 6, 1, 4, 400, 0, 0, 2815, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc8fULL }, // Inst #4149 = t2LDRSBs |
| 6243 | { 4148, 4, 1, 4, 1223, 0, 0, 2811, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc90ULL }, // Inst #4148 = t2LDRSBpci |
| 6244 | { 4147, 5, 1, 4, 399, 0, 0, 914, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc8eULL }, // Inst #4147 = t2LDRSBi8 |
| 6245 | { 4146, 5, 1, 4, 399, 0, 0, 914, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc8bULL }, // Inst #4146 = t2LDRSBi12 |
| 6246 | { 4145, 6, 2, 4, 919, 0, 0, 908, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xcacULL }, // Inst #4145 = t2LDRSB_PRE |
| 6247 | { 4144, 6, 2, 4, 414, 0, 0, 908, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xcccULL }, // Inst #4144 = t2LDRSB_POST |
| 6248 | { 4143, 5, 1, 4, 415, 0, 0, 2806, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc8dULL }, // Inst #4143 = t2LDRSBT |
| 6249 | { 4142, 6, 1, 4, 392, 0, 0, 2815, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc8fULL }, // Inst #4142 = t2LDRHs |
| 6250 | { 4141, 4, 1, 4, 1222, 0, 0, 2811, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc90ULL }, // Inst #4141 = t2LDRHpci |
| 6251 | { 4140, 5, 1, 4, 391, 0, 0, 914, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc8eULL }, // Inst #4140 = t2LDRHi8 |
| 6252 | { 4139, 5, 1, 4, 1105, 0, 0, 914, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc8bULL }, // Inst #4139 = t2LDRHi12 |
| 6253 | { 4138, 6, 2, 4, 918, 0, 0, 908, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xcacULL }, // Inst #4138 = t2LDRH_PRE |
| 6254 | { 4137, 6, 2, 4, 409, 0, 0, 908, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xcccULL }, // Inst #4137 = t2LDRH_POST |
| 6255 | { 4136, 5, 1, 4, 411, 0, 0, 2806, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc8dULL }, // Inst #4136 = t2LDRHT |
| 6256 | { 4135, 4, 1, 4, 1227, 0, 0, 2797, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4135 = t2LDREXH |
| 6257 | { 4134, 5, 2, 4, 1024, 0, 0, 2801, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xc80ULL }, // Inst #4134 = t2LDREXD |
| 6258 | { 4133, 4, 1, 4, 1227, 0, 0, 2797, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4133 = t2LDREXB |
| 6259 | { 4132, 5, 1, 4, 1226, 0, 0, 2834, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc94ULL }, // Inst #4132 = t2LDREX |
| 6260 | { 4131, 6, 2, 4, 416, 0, 0, 2828, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xc91ULL }, // Inst #4131 = t2LDRDi8 |
| 6261 | { 4130, 7, 3, 4, 922, 0, 0, 2821, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc91ULL }, // Inst #4130 = t2LDRD_PRE |
| 6262 | { 4129, 7, 3, 4, 419, 0, 0, 2821, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc91ULL }, // Inst #4129 = t2LDRD_POST |
| 6263 | { 4128, 6, 1, 4, 392, 0, 0, 2815, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc8fULL }, // Inst #4128 = t2LDRBs |
| 6264 | { 4127, 4, 1, 4, 1222, 0, 0, 2811, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc90ULL }, // Inst #4127 = t2LDRBpci |
| 6265 | { 4126, 5, 1, 4, 391, 0, 0, 914, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc8eULL }, // Inst #4126 = t2LDRBi8 |
| 6266 | { 4125, 5, 1, 4, 1105, 0, 0, 914, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc8bULL }, // Inst #4125 = t2LDRBi12 |
| 6267 | { 4124, 6, 2, 4, 911, 0, 0, 908, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xcacULL }, // Inst #4124 = t2LDRB_PRE |
| 6268 | { 4123, 6, 2, 4, 928, 0, 0, 908, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xcccULL }, // Inst #4123 = t2LDRB_POST |
| 6269 | { 4122, 5, 1, 4, 411, 0, 0, 2806, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc8dULL }, // Inst #4122 = t2LDRBT |
| 6270 | { 4121, 5, 1, 4, 1108, 0, 0, 234, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0xc80ULL }, // Inst #4121 = t2LDMIA_UPD |
| 6271 | { 4120, 4, 0, 4, 1107, 0, 0, 873, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0xc80ULL }, // Inst #4120 = t2LDMIA |
| 6272 | { 4119, 5, 1, 4, 1108, 0, 0, 234, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0xc80ULL }, // Inst #4119 = t2LDMDB_UPD |
| 6273 | { 4118, 4, 0, 4, 1107, 0, 0, 873, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0xc80ULL }, // Inst #4118 = t2LDMDB |
| 6274 | { 4117, 6, 0, 4, 847, 0, 0, 889, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4117 = t2LDC_PRE |
| 6275 | { 4116, 6, 0, 4, 847, 0, 0, 889, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4116 = t2LDC_POST |
| 6276 | { 4115, 6, 0, 4, 847, 0, 0, 895, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4115 = t2LDC_OPTION |
| 6277 | { 4114, 6, 0, 4, 847, 0, 0, 889, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc85ULL }, // Inst #4114 = t2LDC_OFFSET |
| 6278 | { 4113, 6, 0, 4, 847, 0, 0, 889, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4113 = t2LDCL_PRE |
| 6279 | { 4112, 6, 0, 4, 847, 0, 0, 889, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4112 = t2LDCL_POST |
| 6280 | { 4111, 6, 0, 4, 847, 0, 0, 895, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4111 = t2LDCL_OPTION |
| 6281 | { 4110, 6, 0, 4, 847, 0, 0, 889, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc85ULL }, // Inst #4110 = t2LDCL_OFFSET |
| 6282 | { 4109, 6, 0, 4, 847, 0, 0, 889, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4109 = t2LDC2_PRE |
| 6283 | { 4108, 6, 0, 4, 847, 0, 0, 889, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4108 = t2LDC2_POST |
| 6284 | { 4107, 6, 0, 4, 847, 0, 0, 895, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4107 = t2LDC2_OPTION |
| 6285 | { 4106, 6, 0, 4, 847, 0, 0, 889, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc85ULL }, // Inst #4106 = t2LDC2_OFFSET |
| 6286 | { 4105, 6, 0, 4, 847, 0, 0, 889, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4105 = t2LDC2L_PRE |
| 6287 | { 4104, 6, 0, 4, 847, 0, 0, 889, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4104 = t2LDC2L_POST |
| 6288 | { 4103, 6, 0, 4, 847, 0, 0, 895, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4103 = t2LDC2L_OPTION |
| 6289 | { 4102, 6, 0, 4, 847, 0, 0, 889, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc85ULL }, // Inst #4102 = t2LDC2L_OFFSET |
| 6290 | { 4101, 4, 1, 4, 686, 0, 0, 2797, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4101 = t2LDAH |
| 6291 | { 4100, 4, 1, 4, 686, 0, 0, 2797, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4100 = t2LDAEXH |
| 6292 | { 4099, 5, 2, 4, 1263, 0, 0, 2801, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xc80ULL }, // Inst #4099 = t2LDAEXD |
| 6293 | { 4098, 4, 1, 4, 686, 0, 0, 2797, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4098 = t2LDAEXB |
| 6294 | { 4097, 4, 1, 4, 1262, 0, 0, 2797, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4097 = t2LDAEX |
| 6295 | { 4096, 4, 1, 4, 686, 0, 0, 2797, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4096 = t2LDAB |
| 6296 | { 4095, 4, 1, 4, 1262, 0, 0, 2797, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4095 = t2LDA |
| 6297 | { 4094, 2, 0, 12, 1039, 0, 15, 587, ARMImpOpBase + 39, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4094 = t2Int_eh_sjlj_setjmp_nofp |
| 6298 | { 4093, 2, 0, 12, 1039, 0, 27, 587, ARMImpOpBase + 190, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4093 = t2Int_eh_sjlj_setjmp |
| 6299 | { 4092, 2, 0, 2, 456, 0, 1, 13, ARMImpOpBase + 189, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4092 = t2IT |
| 6300 | { 4091, 3, 0, 4, 1094, 0, 0, 858, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4091 = t2ISB |
| 6301 | { 4090, 1, 0, 4, 1217, 0, 0, 0, ARMImpOpBase + 0, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4090 = t2HVC |
| 6302 | { 4089, 3, 0, 4, 1036, 0, 0, 858, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4089 = t2HINT |
| 6303 | { 4088, 7, 1, 4, 1238, 0, 0, 2706, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // Inst #4088 = t2EORrs |
| 6304 | { 4087, 6, 1, 4, 1272, 0, 0, 2700, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // Inst #4087 = t2EORrr |
| 6305 | { 4086, 6, 1, 4, 694, 0, 0, 2694, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // Inst #4086 = t2EORri |
| 6306 | { 4085, 3, 0, 4, 1094, 0, 0, 858, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4085 = t2DSB |
| 6307 | { 4084, 3, 0, 4, 1094, 0, 0, 858, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4084 = t2DMB |
| 6308 | { 4083, 2, 1, 4, 1286, 0, 0, 434, ARMImpOpBase + 0, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4083 = t2DLS |
| 6309 | { 4082, 2, 0, 4, 843, 0, 0, 540, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4082 = t2DCPS3 |
| 6310 | { 4081, 2, 0, 4, 843, 0, 0, 540, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4081 = t2DCPS2 |
| 6311 | { 4080, 2, 0, 4, 843, 0, 0, 540, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4080 = t2DCPS1 |
| 6312 | { 4079, 3, 0, 4, 1058, 0, 0, 858, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4079 = t2DBG |
| 6313 | { 4078, 4, 1, 4, 1062, 1, 0, 2793, ARMImpOpBase + 0, 0, 0xc80ULL }, // Inst #4078 = t2CSNEG |
| 6314 | { 4077, 4, 1, 4, 1062, 1, 0, 2793, ARMImpOpBase + 0, 0, 0xc80ULL }, // Inst #4077 = t2CSINV |
| 6315 | { 4076, 4, 1, 4, 1062, 1, 0, 2793, ARMImpOpBase + 0, 0, 0xc80ULL }, // Inst #4076 = t2CSINC |
| 6316 | { 4075, 4, 1, 4, 1062, 1, 0, 2793, ARMImpOpBase + 0, 0, 0xc80ULL }, // Inst #4075 = t2CSEL |
| 6317 | { 4074, 3, 1, 4, 700, 0, 0, 315, ARMImpOpBase + 0, 0, 0xc80ULL }, // Inst #4074 = t2CRC32W |
| 6318 | { 4073, 3, 1, 4, 700, 0, 0, 315, ARMImpOpBase + 0, 0, 0xc80ULL }, // Inst #4073 = t2CRC32H |
| 6319 | { 4072, 3, 1, 4, 700, 0, 0, 315, ARMImpOpBase + 0, 0, 0xc80ULL }, // Inst #4072 = t2CRC32CW |
| 6320 | { 4071, 3, 1, 4, 700, 0, 0, 315, ARMImpOpBase + 0, 0, 0xc80ULL }, // Inst #4071 = t2CRC32CH |
| 6321 | { 4070, 3, 1, 4, 700, 0, 0, 315, ARMImpOpBase + 0, 0, 0xc80ULL }, // Inst #4070 = t2CRC32CB |
| 6322 | { 4069, 3, 1, 4, 700, 0, 0, 315, ARMImpOpBase + 0, 0, 0xc80ULL }, // Inst #4069 = t2CRC32B |
| 6323 | { 4068, 3, 0, 4, 1057, 0, 0, 2, ARMImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4068 = t2CPS3p |
| 6324 | { 4067, 2, 0, 4, 1057, 0, 0, 13, ARMImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4067 = t2CPS2p |
| 6325 | { 4066, 1, 0, 4, 1057, 0, 0, 0, ARMImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4066 = t2CPS1p |
| 6326 | { 4065, 5, 0, 4, 1241, 0, 1, 2788, ARMImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4065 = t2CMPrs |
| 6327 | { 4064, 4, 0, 4, 1068, 0, 1, 2784, ARMImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4064 = t2CMPrr |
| 6328 | { 4063, 4, 0, 4, 1067, 0, 1, 439, ARMImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4063 = t2CMPri |
| 6329 | { 4062, 5, 0, 4, 1240, 0, 1, 2788, ARMImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4062 = t2CMNzrs |
| 6330 | { 4061, 4, 0, 4, 1066, 0, 1, 2784, ARMImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4061 = t2CMNzrr |
| 6331 | { 4060, 4, 0, 4, 55, 0, 1, 439, ARMImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4060 = t2CMNri |
| 6332 | { 4059, 4, 1, 4, 1245, 0, 0, 2752, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4059 = t2CLZ |
| 6333 | { 4058, 3, 0, 4, 1104, 0, 0, 584, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4058 = t2CLRM |
| 6334 | { 4057, 2, 0, 4, 1030, 0, 0, 540, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4057 = t2CLREX |
| 6335 | { 4056, 8, 0, 4, 1033, 0, 0, 823, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4056 = t2CDP2 |
| 6336 | { 4055, 8, 0, 4, 1033, 0, 0, 823, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4055 = t2CDP |
| 6337 | { 4054, 3, 0, 4, 853, 0, 0, 545, ARMImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4054 = t2Bcc |
| 6338 | { 4053, 3, 0, 4, 863, 0, 0, 1059, ARMImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4053 = t2BXJ |
| 6339 | { 4052, 5, 0, 4, 0, 0, 0, 2779, ARMImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4052 = t2BXAUT |
| 6340 | { 4051, 0, 0, 4, 0, 0, 0, 1, ARMImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4051 = t2BTI |
| 6341 | { 4050, 7, 1, 4, 1238, 0, 0, 2706, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // Inst #4050 = t2BICrs |
| 6342 | { 4049, 6, 1, 4, 1272, 0, 0, 2700, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // Inst #4049 = t2BICrr |
| 6343 | { 4048, 6, 1, 4, 694, 0, 0, 2694, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // Inst #4048 = t2BICri |
| 6344 | { 4047, 4, 0, 4, 1284, 0, 0, 2771, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4047 = t2BFr |
| 6345 | { 4046, 4, 0, 4, 1284, 0, 0, 2775, ARMImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4046 = t2BFic |
| 6346 | { 4045, 4, 0, 4, 1284, 0, 0, 2767, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4045 = t2BFi |
| 6347 | { 4044, 4, 0, 4, 1284, 0, 0, 2771, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4044 = t2BFLr |
| 6348 | { 4043, 4, 0, 4, 1284, 0, 0, 2767, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4043 = t2BFLi |
| 6349 | { 4042, 6, 1, 4, 359, 0, 0, 2761, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4042 = t2BFI |
| 6350 | { 4041, 5, 1, 4, 358, 0, 0, 464, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4041 = t2BFC |
| 6351 | { 4040, 3, 0, 4, 853, 0, 0, 545, ARMImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0xc80ULL }, // Inst #4040 = t2B |
| 6352 | { 4039, 5, 0, 4, 0, 0, 0, 2756, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4039 = t2AUTG |
| 6353 | { 4038, 0, 0, 4, 0, 3, 0, 1, ARMImpOpBase + 186, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4038 = t2AUT |
| 6354 | { 4037, 4, 1, 4, 1243, 0, 1, 2752, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4037 = t2ASRs1 |
| 6355 | { 4036, 6, 1, 4, 1065, 0, 0, 2700, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // Inst #4036 = t2ASRrr |
| 6356 | { 4035, 6, 1, 4, 1064, 0, 0, 2694, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // Inst #4035 = t2ASRri |
| 6357 | { 4034, 7, 1, 4, 705, 0, 0, 2706, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // Inst #4034 = t2ANDrs |
| 6358 | { 4033, 6, 1, 4, 701, 0, 0, 2700, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // Inst #4033 = t2ANDrr |
| 6359 | { 4032, 6, 1, 4, 694, 0, 0, 2694, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // Inst #4032 = t2ANDri |
| 6360 | { 4031, 4, 1, 4, 1, 0, 0, 2748, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4031 = t2ADR |
| 6361 | { 4030, 5, 1, 4, 1, 0, 0, 2743, ARMImpOpBase + 0, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4030 = t2ADDspImm12 |
| 6362 | { 4029, 6, 1, 4, 1, 0, 0, 2737, ARMImpOpBase + 0, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #4029 = t2ADDspImm |
| 6363 | { 4028, 7, 1, 4, 704, 0, 0, 2730, ARMImpOpBase + 0, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // Inst #4028 = t2ADDrs |
| 6364 | { 4027, 6, 1, 4, 1063, 0, 0, 2724, ARMImpOpBase + 0, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // Inst #4027 = t2ADDrr |
| 6365 | { 4026, 5, 1, 4, 1277, 0, 0, 2719, ARMImpOpBase + 0, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #4026 = t2ADDri12 |
| 6366 | { 4025, 6, 1, 4, 1276, 0, 0, 2713, ARMImpOpBase + 0, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // Inst #4025 = t2ADDri |
| 6367 | { 4024, 7, 1, 4, 1268, 1, 1, 2706, ARMImpOpBase + 63, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0xc80ULL }, // Inst #4024 = t2ADCrs |
| 6368 | { 4023, 6, 1, 4, 1271, 1, 1, 2700, ARMImpOpBase + 63, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0xc80ULL }, // Inst #4023 = t2ADCrr |
| 6369 | { 4022, 6, 1, 4, 692, 1, 1, 2694, ARMImpOpBase + 63, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0xc80ULL }, // Inst #4022 = t2ADCri |
| 6370 | { 4021, 5, 1, 4, 451, 0, 0, 234, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x564ULL }, // Inst #4021 = sysSTMIB_UPD |
| 6371 | { 4020, 4, 0, 4, 450, 0, 0, 873, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x504ULL }, // Inst #4020 = sysSTMIB |
| 6372 | { 4019, 5, 1, 4, 451, 0, 0, 234, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x564ULL }, // Inst #4019 = sysSTMIA_UPD |
| 6373 | { 4018, 4, 0, 4, 450, 0, 0, 873, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x504ULL }, // Inst #4018 = sysSTMIA |
| 6374 | { 4017, 5, 1, 4, 451, 0, 0, 234, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x564ULL }, // Inst #4017 = sysSTMDB_UPD |
| 6375 | { 4016, 4, 0, 4, 450, 0, 0, 873, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x504ULL }, // Inst #4016 = sysSTMDB |
| 6376 | { 4015, 5, 1, 4, 451, 0, 0, 234, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x564ULL }, // Inst #4015 = sysSTMDA_UPD |
| 6377 | { 4014, 4, 0, 4, 450, 0, 0, 873, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x504ULL }, // Inst #4014 = sysSTMDA |
| 6378 | { 4013, 5, 1, 4, 421, 0, 0, 234, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x564ULL }, // Inst #4013 = sysLDMIB_UPD |
| 6379 | { 4012, 4, 0, 4, 420, 0, 0, 873, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x504ULL }, // Inst #4012 = sysLDMIB |
| 6380 | { 4011, 5, 1, 4, 421, 0, 0, 234, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x564ULL }, // Inst #4011 = sysLDMIA_UPD |
| 6381 | { 4010, 4, 0, 4, 420, 0, 0, 873, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x504ULL }, // Inst #4010 = sysLDMIA |
| 6382 | { 4009, 5, 1, 4, 421, 0, 0, 234, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x564ULL }, // Inst #4009 = sysLDMDB_UPD |
| 6383 | { 4008, 4, 0, 4, 420, 0, 0, 873, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x504ULL }, // Inst #4008 = sysLDMDB |
| 6384 | { 4007, 5, 1, 4, 421, 0, 0, 234, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x564ULL }, // Inst #4007 = sysLDMDA_UPD |
| 6385 | { 4006, 4, 0, 4, 420, 0, 0, 873, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x504ULL }, // Inst #4006 = sysLDMDA |
| 6386 | { 4005, 6, 2, 4, 515, 0, 0, 2662, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11000ULL }, // Inst #4005 = VZIPq8 |
| 6387 | { 4004, 6, 2, 4, 515, 0, 0, 2662, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11000ULL }, // Inst #4004 = VZIPq32 |
| 6388 | { 4003, 6, 2, 4, 515, 0, 0, 2662, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11000ULL }, // Inst #4003 = VZIPq16 |
| 6389 | { 4002, 6, 2, 4, 513, 0, 0, 2656, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11000ULL }, // Inst #4002 = VZIPd8 |
| 6390 | { 4001, 6, 2, 4, 513, 0, 0, 2656, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11000ULL }, // Inst #4001 = VZIPd16 |
| 6391 | { 4000, 6, 2, 4, 515, 0, 0, 2662, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11000ULL }, // Inst #4000 = VUZPq8 |
| 6392 | { 3999, 6, 2, 4, 515, 0, 0, 2662, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11000ULL }, // Inst #3999 = VUZPq32 |
| 6393 | { 3998, 6, 2, 4, 515, 0, 0, 2662, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11000ULL }, // Inst #3998 = VUZPq16 |
| 6394 | { 3997, 6, 2, 4, 513, 0, 0, 2656, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11000ULL }, // Inst #3997 = VUZPd8 |
| 6395 | { 3996, 6, 2, 4, 513, 0, 0, 2656, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11000ULL }, // Inst #3996 = VUZPd16 |
| 6396 | { 3995, 4, 1, 4, 0, 0, 0, 641, ARMImpOpBase + 0, 0, 0x11280ULL }, // Inst #3995 = VUSMMLA |
| 6397 | { 3994, 5, 1, 4, 0, 0, 0, 632, ARMImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x11280ULL }, // Inst #3994 = VUSDOTQI |
| 6398 | { 3993, 4, 1, 4, 50, 0, 0, 641, ARMImpOpBase + 0, 0, 0x11280ULL }, // Inst #3993 = VUSDOTQ |
| 6399 | { 3992, 5, 1, 4, 0, 0, 0, 627, ARMImpOpBase + 0, 0, 0x11280ULL }, // Inst #3992 = VUSDOTDI |
| 6400 | { 3991, 4, 1, 4, 50, 0, 0, 637, ARMImpOpBase + 0, 0, 0x11280ULL }, // Inst #3991 = VUSDOTD |
| 6401 | { 3990, 4, 1, 4, 0, 0, 0, 641, ARMImpOpBase + 0, 0, 0x11280ULL }, // Inst #3990 = VUMMLA |
| 6402 | { 3989, 5, 1, 4, 222, 0, 0, 2406, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x28880ULL }, // Inst #3989 = VULTOS |
| 6403 | { 3988, 5, 1, 4, 221, 0, 0, 2406, ARMImpOpBase + 0, 0, 0x8880ULL }, // Inst #3988 = VULTOH |
| 6404 | { 3987, 5, 1, 4, 1289, 0, 0, 2401, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x8880ULL }, // Inst #3987 = VULTOD |
| 6405 | { 3986, 4, 1, 4, 563, 0, 0, 1691, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x28880ULL }, // Inst #3986 = VUITOS |
| 6406 | { 3985, 4, 1, 4, 562, 0, 0, 2411, ARMImpOpBase + 0, 0, 0x8880ULL }, // Inst #3985 = VUITOH |
| 6407 | { 3984, 4, 1, 4, 561, 0, 0, 1810, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x8880ULL }, // Inst #3984 = VUITOD |
| 6408 | { 3983, 5, 1, 4, 222, 0, 0, 2406, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x28880ULL }, // Inst #3983 = VUHTOS |
| 6409 | { 3982, 5, 1, 4, 221, 0, 0, 2406, ARMImpOpBase + 0, 0, 0x8880ULL }, // Inst #3982 = VUHTOH |
| 6410 | { 3981, 5, 1, 4, 1289, 0, 0, 2401, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x8880ULL }, // Inst #3981 = VUHTOD |
| 6411 | { 3980, 5, 1, 4, 963, 0, 0, 632, ARMImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x11280ULL }, // Inst #3980 = VUDOTQI |
| 6412 | { 3979, 4, 1, 4, 963, 0, 0, 641, ARMImpOpBase + 0, 0, 0x11280ULL }, // Inst #3979 = VUDOTQ |
| 6413 | { 3978, 5, 1, 4, 963, 0, 0, 627, ARMImpOpBase + 0, 0, 0x11280ULL }, // Inst #3978 = VUDOTDI |
| 6414 | { 3977, 4, 1, 4, 963, 0, 0, 637, ARMImpOpBase + 0, 0, 0x11280ULL }, // Inst #3977 = VUDOTD |
| 6415 | { 3976, 5, 1, 4, 467, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3976 = VTSTv8i8 |
| 6416 | { 3975, 5, 1, 4, 466, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3975 = VTSTv8i16 |
| 6417 | { 3974, 5, 1, 4, 466, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3974 = VTSTv4i32 |
| 6418 | { 3973, 5, 1, 4, 467, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3973 = VTSTv4i16 |
| 6419 | { 3972, 5, 1, 4, 467, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3972 = VTSTv2i32 |
| 6420 | { 3971, 5, 1, 4, 466, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3971 = VTSTv16i8 |
| 6421 | { 3970, 6, 2, 4, 514, 0, 0, 2662, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11000ULL }, // Inst #3970 = VTRNq8 |
| 6422 | { 3969, 6, 2, 4, 514, 0, 0, 2662, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11000ULL }, // Inst #3969 = VTRNq32 |
| 6423 | { 3968, 6, 2, 4, 514, 0, 0, 2662, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11000ULL }, // Inst #3968 = VTRNq16 |
| 6424 | { 3967, 6, 2, 4, 1001, 0, 0, 2656, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11000ULL }, // Inst #3967 = VTRNd8 |
| 6425 | { 3966, 6, 2, 4, 1001, 0, 0, 2656, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11000ULL }, // Inst #3966 = VTRNd32 |
| 6426 | { 3965, 6, 2, 4, 1001, 0, 0, 2656, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11000ULL }, // Inst #3965 = VTRNd16 |
| 6427 | { 3964, 5, 1, 4, 958, 0, 0, 2406, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x28880ULL }, // Inst #3964 = VTOULS |
| 6428 | { 3963, 5, 1, 4, 565, 0, 0, 2406, ARMImpOpBase + 0, 0, 0x8880ULL }, // Inst #3963 = VTOULH |
| 6429 | { 3962, 5, 1, 4, 564, 0, 0, 2401, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x8880ULL }, // Inst #3962 = VTOULD |
| 6430 | { 3961, 4, 1, 4, 566, 0, 0, 1691, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x28880ULL }, // Inst #3961 = VTOUIZS |
| 6431 | { 3960, 4, 1, 4, 565, 0, 0, 2690, ARMImpOpBase + 0, 0, 0x8880ULL }, // Inst #3960 = VTOUIZH |
| 6432 | { 3959, 4, 1, 4, 564, 0, 0, 1814, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x8880ULL }, // Inst #3959 = VTOUIZD |
| 6433 | { 3958, 4, 1, 4, 566, 1, 0, 1691, ARMImpOpBase + 71, 0|(1ULL<<MCID::Predicable), 0x8880ULL }, // Inst #3958 = VTOUIRS |
| 6434 | { 3957, 4, 1, 4, 565, 1, 0, 1691, ARMImpOpBase + 71, 0, 0x8880ULL }, // Inst #3957 = VTOUIRH |
| 6435 | { 3956, 4, 1, 4, 564, 1, 0, 1814, ARMImpOpBase + 71, 0|(1ULL<<MCID::Predicable), 0x8880ULL }, // Inst #3956 = VTOUIRD |
| 6436 | { 3955, 5, 1, 4, 958, 0, 0, 2406, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x28880ULL }, // Inst #3955 = VTOUHS |
| 6437 | { 3954, 5, 1, 4, 565, 0, 0, 2406, ARMImpOpBase + 0, 0, 0x8880ULL }, // Inst #3954 = VTOUHH |
| 6438 | { 3953, 5, 1, 4, 564, 0, 0, 2401, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x8880ULL }, // Inst #3953 = VTOUHD |
| 6439 | { 3952, 5, 1, 4, 958, 0, 0, 2406, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x28880ULL }, // Inst #3952 = VTOSLS |
| 6440 | { 3951, 5, 1, 4, 565, 0, 0, 2406, ARMImpOpBase + 0, 0, 0x8880ULL }, // Inst #3951 = VTOSLH |
| 6441 | { 3950, 5, 1, 4, 564, 0, 0, 2401, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x8880ULL }, // Inst #3950 = VTOSLD |
| 6442 | { 3949, 4, 1, 4, 566, 0, 0, 1691, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x28880ULL }, // Inst #3949 = VTOSIZS |
| 6443 | { 3948, 4, 1, 4, 565, 0, 0, 2690, ARMImpOpBase + 0, 0, 0x8880ULL }, // Inst #3948 = VTOSIZH |
| 6444 | { 3947, 4, 1, 4, 564, 0, 0, 1814, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x8880ULL }, // Inst #3947 = VTOSIZD |
| 6445 | { 3946, 4, 1, 4, 566, 1, 0, 1691, ARMImpOpBase + 71, 0|(1ULL<<MCID::Predicable), 0x8880ULL }, // Inst #3946 = VTOSIRS |
| 6446 | { 3945, 4, 1, 4, 565, 1, 0, 1691, ARMImpOpBase + 71, 0, 0x8880ULL }, // Inst #3945 = VTOSIRH |
| 6447 | { 3944, 4, 1, 4, 564, 1, 0, 1814, ARMImpOpBase + 71, 0|(1ULL<<MCID::Predicable), 0x8880ULL }, // Inst #3944 = VTOSIRD |
| 6448 | { 3943, 5, 1, 4, 566, 0, 0, 2406, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x28880ULL }, // Inst #3943 = VTOSHS |
| 6449 | { 3942, 5, 1, 4, 565, 0, 0, 2406, ARMImpOpBase + 0, 0, 0x8880ULL }, // Inst #3942 = VTOSHH |
| 6450 | { 3941, 5, 1, 4, 564, 0, 0, 2401, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x8880ULL }, // Inst #3941 = VTOSHD |
| 6451 | { 3940, 6, 1, 4, 511, 0, 0, 2684, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x10000ULL }, // Inst #3940 = VTBX4Pseudo |
| 6452 | { 3939, 6, 1, 4, 511, 0, 0, 1662, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x11480ULL }, // Inst #3939 = VTBX4 |
| 6453 | { 3938, 6, 1, 4, 509, 0, 0, 2684, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x10000ULL }, // Inst #3938 = VTBX3Pseudo |
| 6454 | { 3937, 6, 1, 4, 509, 0, 0, 1662, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x11480ULL }, // Inst #3937 = VTBX3 |
| 6455 | { 3936, 6, 1, 4, 507, 0, 0, 2678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x11480ULL }, // Inst #3936 = VTBX2 |
| 6456 | { 3935, 6, 1, 4, 505, 0, 0, 1662, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11480ULL }, // Inst #3935 = VTBX1 |
| 6457 | { 3934, 5, 1, 4, 510, 0, 0, 2673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x10000ULL }, // Inst #3934 = VTBL4Pseudo |
| 6458 | { 3933, 5, 1, 4, 510, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x11480ULL }, // Inst #3933 = VTBL4 |
| 6459 | { 3932, 5, 1, 4, 508, 0, 0, 2673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x10000ULL }, // Inst #3932 = VTBL3Pseudo |
| 6460 | { 3931, 5, 1, 4, 508, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x11480ULL }, // Inst #3931 = VTBL3 |
| 6461 | { 3930, 5, 1, 4, 506, 0, 0, 2668, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x11480ULL }, // Inst #3930 = VTBL2 |
| 6462 | { 3929, 5, 1, 4, 504, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11480ULL }, // Inst #3929 = VTBL1 |
| 6463 | { 3928, 6, 2, 4, 512, 0, 0, 2662, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11000ULL }, // Inst #3928 = VSWPq |
| 6464 | { 3927, 6, 2, 4, 512, 0, 0, 2656, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11000ULL }, // Inst #3927 = VSWPd |
| 6465 | { 3926, 5, 1, 4, 0, 0, 0, 632, ARMImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x11280ULL }, // Inst #3926 = VSUDOTQI |
| 6466 | { 3925, 5, 1, 4, 0, 0, 0, 627, ARMImpOpBase + 0, 0, 0x11280ULL }, // Inst #3925 = VSUDOTDI |
| 6467 | { 3924, 5, 1, 4, 756, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3924 = VSUBv8i8 |
| 6468 | { 3923, 5, 1, 4, 460, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3923 = VSUBv8i16 |
| 6469 | { 3922, 5, 1, 4, 460, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3922 = VSUBv4i32 |
| 6470 | { 3921, 5, 1, 4, 756, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3921 = VSUBv4i16 |
| 6471 | { 3920, 5, 1, 4, 460, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3920 = VSUBv2i64 |
| 6472 | { 3919, 5, 1, 4, 756, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3919 = VSUBv2i32 |
| 6473 | { 3918, 5, 1, 4, 756, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3918 = VSUBv1i64 |
| 6474 | { 3917, 5, 1, 4, 460, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3917 = VSUBv16i8 |
| 6475 | { 3916, 5, 1, 4, 746, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3916 = VSUBhq |
| 6476 | { 3915, 5, 1, 4, 744, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3915 = VSUBhd |
| 6477 | { 3914, 5, 1, 4, 745, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3914 = VSUBfq |
| 6478 | { 3913, 5, 1, 4, 743, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3913 = VSUBfd |
| 6479 | { 3912, 5, 1, 4, 461, 0, 0, 1714, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3912 = VSUBWuv8i16 |
| 6480 | { 3911, 5, 1, 4, 461, 0, 0, 1714, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3911 = VSUBWuv4i32 |
| 6481 | { 3910, 5, 1, 4, 461, 0, 0, 1714, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3910 = VSUBWuv2i64 |
| 6482 | { 3909, 5, 1, 4, 461, 0, 0, 1714, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3909 = VSUBWsv8i16 |
| 6483 | { 3908, 5, 1, 4, 461, 0, 0, 1714, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3908 = VSUBWsv4i32 |
| 6484 | { 3907, 5, 1, 4, 461, 0, 0, 1714, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3907 = VSUBWsv2i64 |
| 6485 | { 3906, 5, 1, 4, 520, 0, 0, 1709, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x28800ULL }, // Inst #3906 = VSUBS |
| 6486 | { 3905, 5, 1, 4, 758, 0, 0, 1668, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3905 = VSUBLuv8i16 |
| 6487 | { 3904, 5, 1, 4, 758, 0, 0, 1668, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3904 = VSUBLuv4i32 |
| 6488 | { 3903, 5, 1, 4, 758, 0, 0, 1668, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3903 = VSUBLuv2i64 |
| 6489 | { 3902, 5, 1, 4, 758, 0, 0, 1668, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3902 = VSUBLsv8i16 |
| 6490 | { 3901, 5, 1, 4, 758, 0, 0, 1668, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3901 = VSUBLsv4i32 |
| 6491 | { 3900, 5, 1, 4, 758, 0, 0, 1668, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3900 = VSUBLsv2i64 |
| 6492 | { 3899, 5, 1, 4, 500, 0, 0, 1704, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3899 = VSUBHNv8i8 |
| 6493 | { 3898, 5, 1, 4, 500, 0, 0, 1704, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3898 = VSUBHNv4i16 |
| 6494 | { 3897, 5, 1, 4, 500, 0, 0, 1704, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3897 = VSUBHNv2i32 |
| 6495 | { 3896, 5, 1, 4, 742, 0, 0, 1699, ARMImpOpBase + 0, 0, 0x8800ULL }, // Inst #3896 = VSUBH |
| 6496 | { 3895, 5, 1, 4, 526, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x8800ULL }, // Inst #3895 = VSUBD |
| 6497 | { 3894, 5, 1, 4, 750, 1, 0, 2194, ARMImpOpBase + 69, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b35ULL }, // Inst #3894 = VSTR_VPR_pre |
| 6498 | { 3893, 5, 1, 4, 750, 1, 0, 2194, ARMImpOpBase + 69, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b55ULL }, // Inst #3893 = VSTR_VPR_post |
| 6499 | { 3892, 4, 0, 4, 750, 1, 0, 2190, ARMImpOpBase + 69, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b55ULL }, // Inst #3892 = VSTR_VPR_off |
| 6500 | { 3891, 6, 1, 4, 750, 0, 0, 2650, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b35ULL }, // Inst #3891 = VSTR_P0_pre |
| 6501 | { 3890, 6, 1, 4, 750, 0, 0, 2650, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b55ULL }, // Inst #3890 = VSTR_P0_post |
| 6502 | { 3889, 5, 0, 4, 750, 0, 0, 2210, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b55ULL }, // Inst #3889 = VSTR_P0_off |
| 6503 | { 3888, 5, 1, 4, 750, 1, 0, 2194, ARMImpOpBase + 71, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b35ULL }, // Inst #3888 = VSTR_FPSCR_pre |
| 6504 | { 3887, 5, 1, 4, 750, 1, 0, 2194, ARMImpOpBase + 71, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b55ULL }, // Inst #3887 = VSTR_FPSCR_post |
| 6505 | { 3886, 4, 0, 4, 750, 1, 0, 2190, ARMImpOpBase + 71, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b55ULL }, // Inst #3886 = VSTR_FPSCR_off |
| 6506 | { 3885, 6, 1, 4, 750, 0, 0, 2644, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b35ULL }, // Inst #3885 = VSTR_FPSCR_NZCVQC_pre |
| 6507 | { 3884, 6, 1, 4, 750, 0, 0, 2644, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b55ULL }, // Inst #3884 = VSTR_FPSCR_NZCVQC_post |
| 6508 | { 3883, 5, 0, 4, 750, 0, 0, 2199, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b55ULL }, // Inst #3883 = VSTR_FPSCR_NZCVQC_off |
| 6509 | { 3882, 5, 1, 4, 750, 1, 0, 2194, ARMImpOpBase + 71, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b35ULL }, // Inst #3882 = VSTR_FPCXTS_pre |
| 6510 | { 3881, 5, 1, 4, 750, 1, 0, 2194, ARMImpOpBase + 71, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b55ULL }, // Inst #3881 = VSTR_FPCXTS_post |
| 6511 | { 3880, 4, 0, 4, 750, 1, 0, 2190, ARMImpOpBase + 71, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b55ULL }, // Inst #3880 = VSTR_FPCXTS_off |
| 6512 | { 3879, 5, 1, 4, 750, 1, 0, 2194, ARMImpOpBase + 71, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b35ULL }, // Inst #3879 = VSTR_FPCXTNS_pre |
| 6513 | { 3878, 5, 1, 4, 750, 1, 0, 2194, ARMImpOpBase + 71, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b55ULL }, // Inst #3878 = VSTR_FPCXTNS_post |
| 6514 | { 3877, 4, 0, 4, 750, 1, 0, 2190, ARMImpOpBase + 71, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b55ULL }, // Inst #3877 = VSTR_FPCXTNS_off |
| 6515 | { 3876, 5, 0, 4, 591, 0, 0, 2185, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x18b05ULL }, // Inst #3876 = VSTRS |
| 6516 | { 3875, 5, 0, 4, 749, 0, 0, 2180, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x18b13ULL }, // Inst #3875 = VSTRH |
| 6517 | { 3874, 5, 0, 4, 590, 0, 0, 385, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x18b05ULL }, // Inst #3874 = VSTRD |
| 6518 | { 3873, 5, 1, 4, 970, 0, 0, 234, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x18be4ULL }, // Inst #3873 = VSTMSIA_UPD |
| 6519 | { 3872, 4, 0, 4, 969, 0, 0, 873, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x18b84ULL }, // Inst #3872 = VSTMSIA |
| 6520 | { 3871, 5, 1, 4, 970, 0, 0, 234, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x18be4ULL }, // Inst #3871 = VSTMSDB_UPD |
| 6521 | { 3870, 4, 0, 4, 593, 0, 0, 2176, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x18004ULL }, // Inst #3870 = VSTMQIA |
| 6522 | { 3869, 5, 1, 4, 597, 0, 0, 234, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8be4ULL }, // Inst #3869 = VSTMDIA_UPD |
| 6523 | { 3868, 4, 0, 4, 596, 0, 0, 873, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8b84ULL }, // Inst #3868 = VSTMDIA |
| 6524 | { 3867, 5, 1, 4, 597, 0, 0, 234, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8be4ULL }, // Inst #3867 = VSTMDDB_UPD |
| 6525 | { 3866, 7, 1, 4, 662, 0, 0, 2501, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3866 = VST4q8oddPseudo_UPD |
| 6526 | { 3865, 5, 0, 4, 661, 0, 0, 2496, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3865 = VST4q8oddPseudo |
| 6527 | { 3864, 10, 1, 4, 837, 0, 0, 2634, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3864 = VST4q8_UPD |
| 6528 | { 3863, 7, 1, 4, 662, 0, 0, 2501, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3863 = VST4q8Pseudo_UPD |
| 6529 | { 3862, 8, 0, 4, 829, 0, 0, 2626, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3862 = VST4q8 |
| 6530 | { 3861, 7, 1, 4, 662, 0, 0, 2501, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3861 = VST4q32oddPseudo_UPD |
| 6531 | { 3860, 5, 0, 4, 661, 0, 0, 2496, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3860 = VST4q32oddPseudo |
| 6532 | { 3859, 10, 1, 4, 837, 0, 0, 2634, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3859 = VST4q32_UPD |
| 6533 | { 3858, 7, 1, 4, 662, 0, 0, 2501, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3858 = VST4q32Pseudo_UPD |
| 6534 | { 3857, 8, 0, 4, 829, 0, 0, 2626, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3857 = VST4q32 |
| 6535 | { 3856, 7, 1, 4, 662, 0, 0, 2501, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3856 = VST4q16oddPseudo_UPD |
| 6536 | { 3855, 5, 0, 4, 661, 0, 0, 2496, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3855 = VST4q16oddPseudo |
| 6537 | { 3854, 10, 1, 4, 837, 0, 0, 2634, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3854 = VST4q16_UPD |
| 6538 | { 3853, 7, 1, 4, 662, 0, 0, 2501, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3853 = VST4q16Pseudo_UPD |
| 6539 | { 3852, 8, 0, 4, 829, 0, 0, 2626, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3852 = VST4q16 |
| 6540 | { 3851, 10, 1, 4, 837, 0, 0, 2634, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3851 = VST4d8_UPD |
| 6541 | { 3850, 7, 1, 4, 662, 0, 0, 2471, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3850 = VST4d8Pseudo_UPD |
| 6542 | { 3849, 5, 0, 4, 831, 0, 0, 2460, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3849 = VST4d8Pseudo |
| 6543 | { 3848, 8, 0, 4, 829, 0, 0, 2626, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3848 = VST4d8 |
| 6544 | { 3847, 10, 1, 4, 837, 0, 0, 2634, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3847 = VST4d32_UPD |
| 6545 | { 3846, 7, 1, 4, 662, 0, 0, 2471, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3846 = VST4d32Pseudo_UPD |
| 6546 | { 3845, 5, 0, 4, 831, 0, 0, 2460, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3845 = VST4d32Pseudo |
| 6547 | { 3844, 8, 0, 4, 829, 0, 0, 2626, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3844 = VST4d32 |
| 6548 | { 3843, 10, 1, 4, 837, 0, 0, 2634, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3843 = VST4d16_UPD |
| 6549 | { 3842, 7, 1, 4, 662, 0, 0, 2471, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3842 = VST4d16Pseudo_UPD |
| 6550 | { 3841, 5, 0, 4, 831, 0, 0, 2460, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3841 = VST4d16Pseudo |
| 6551 | { 3840, 8, 0, 4, 829, 0, 0, 2626, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3840 = VST4d16 |
| 6552 | { 3839, 11, 1, 4, 673, 0, 0, 2615, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3839 = VST4LNq32_UPD |
| 6553 | { 3838, 8, 1, 4, 674, 0, 0, 2582, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3838 = VST4LNq32Pseudo_UPD |
| 6554 | { 3837, 6, 0, 4, 672, 0, 0, 2576, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3837 = VST4LNq32Pseudo |
| 6555 | { 3836, 9, 0, 4, 835, 0, 0, 2606, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3836 = VST4LNq32 |
| 6556 | { 3835, 11, 1, 4, 673, 0, 0, 2615, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3835 = VST4LNq16_UPD |
| 6557 | { 3834, 8, 1, 4, 674, 0, 0, 2582, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3834 = VST4LNq16Pseudo_UPD |
| 6558 | { 3833, 6, 0, 4, 672, 0, 0, 2576, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3833 = VST4LNq16Pseudo |
| 6559 | { 3832, 9, 0, 4, 835, 0, 0, 2606, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3832 = VST4LNq16 |
| 6560 | { 3831, 11, 1, 4, 839, 0, 0, 2615, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3831 = VST4LNd8_UPD |
| 6561 | { 3830, 8, 1, 4, 841, 0, 0, 2543, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3830 = VST4LNd8Pseudo_UPD |
| 6562 | { 3829, 6, 0, 4, 834, 0, 0, 2537, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3829 = VST4LNd8Pseudo |
| 6563 | { 3828, 9, 0, 4, 832, 0, 0, 2606, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3828 = VST4LNd8 |
| 6564 | { 3827, 11, 1, 4, 839, 0, 0, 2615, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3827 = VST4LNd32_UPD |
| 6565 | { 3826, 8, 1, 4, 841, 0, 0, 2543, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3826 = VST4LNd32Pseudo_UPD |
| 6566 | { 3825, 6, 0, 4, 834, 0, 0, 2537, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3825 = VST4LNd32Pseudo |
| 6567 | { 3824, 9, 0, 4, 832, 0, 0, 2606, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3824 = VST4LNd32 |
| 6568 | { 3823, 11, 1, 4, 839, 0, 0, 2615, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3823 = VST4LNd16_UPD |
| 6569 | { 3822, 8, 1, 4, 841, 0, 0, 2543, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3822 = VST4LNd16Pseudo_UPD |
| 6570 | { 3821, 6, 0, 4, 834, 0, 0, 2537, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3821 = VST4LNd16Pseudo |
| 6571 | { 3820, 9, 0, 4, 832, 0, 0, 2606, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3820 = VST4LNd16 |
| 6572 | { 3819, 7, 1, 4, 660, 0, 0, 2501, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3819 = VST3q8oddPseudo_UPD |
| 6573 | { 3818, 5, 0, 4, 659, 0, 0, 2496, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3818 = VST3q8oddPseudo |
| 6574 | { 3817, 9, 1, 4, 823, 0, 0, 2597, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3817 = VST3q8_UPD |
| 6575 | { 3816, 7, 1, 4, 660, 0, 0, 2501, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3816 = VST3q8Pseudo_UPD |
| 6576 | { 3815, 7, 0, 4, 816, 0, 0, 2590, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3815 = VST3q8 |
| 6577 | { 3814, 7, 1, 4, 660, 0, 0, 2501, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3814 = VST3q32oddPseudo_UPD |
| 6578 | { 3813, 5, 0, 4, 659, 0, 0, 2496, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3813 = VST3q32oddPseudo |
| 6579 | { 3812, 9, 1, 4, 823, 0, 0, 2597, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3812 = VST3q32_UPD |
| 6580 | { 3811, 7, 1, 4, 660, 0, 0, 2501, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3811 = VST3q32Pseudo_UPD |
| 6581 | { 3810, 7, 0, 4, 816, 0, 0, 2590, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3810 = VST3q32 |
| 6582 | { 3809, 7, 1, 4, 660, 0, 0, 2501, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3809 = VST3q16oddPseudo_UPD |
| 6583 | { 3808, 5, 0, 4, 659, 0, 0, 2496, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3808 = VST3q16oddPseudo |
| 6584 | { 3807, 9, 1, 4, 823, 0, 0, 2597, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3807 = VST3q16_UPD |
| 6585 | { 3806, 7, 1, 4, 660, 0, 0, 2501, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3806 = VST3q16Pseudo_UPD |
| 6586 | { 3805, 7, 0, 4, 816, 0, 0, 2590, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3805 = VST3q16 |
| 6587 | { 3804, 9, 1, 4, 823, 0, 0, 2597, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3804 = VST3d8_UPD |
| 6588 | { 3803, 7, 1, 4, 660, 0, 0, 2471, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3803 = VST3d8Pseudo_UPD |
| 6589 | { 3802, 5, 0, 4, 818, 0, 0, 2460, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3802 = VST3d8Pseudo |
| 6590 | { 3801, 7, 0, 4, 816, 0, 0, 2590, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3801 = VST3d8 |
| 6591 | { 3800, 9, 1, 4, 823, 0, 0, 2597, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3800 = VST3d32_UPD |
| 6592 | { 3799, 7, 1, 4, 660, 0, 0, 2471, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3799 = VST3d32Pseudo_UPD |
| 6593 | { 3798, 5, 0, 4, 818, 0, 0, 2460, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3798 = VST3d32Pseudo |
| 6594 | { 3797, 7, 0, 4, 816, 0, 0, 2590, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3797 = VST3d32 |
| 6595 | { 3796, 9, 1, 4, 823, 0, 0, 2597, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3796 = VST3d16_UPD |
| 6596 | { 3795, 7, 1, 4, 660, 0, 0, 2471, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3795 = VST3d16Pseudo_UPD |
| 6597 | { 3794, 5, 0, 4, 818, 0, 0, 2460, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3794 = VST3d16Pseudo |
| 6598 | { 3793, 7, 0, 4, 816, 0, 0, 2590, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3793 = VST3d16 |
| 6599 | { 3792, 10, 1, 4, 670, 0, 0, 2566, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3792 = VST3LNq32_UPD |
| 6600 | { 3791, 8, 1, 4, 671, 0, 0, 2582, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3791 = VST3LNq32Pseudo_UPD |
| 6601 | { 3790, 6, 0, 4, 669, 0, 0, 2576, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3790 = VST3LNq32Pseudo |
| 6602 | { 3789, 8, 0, 4, 668, 0, 0, 2558, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3789 = VST3LNq32 |
| 6603 | { 3788, 10, 1, 4, 670, 0, 0, 2566, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3788 = VST3LNq16_UPD |
| 6604 | { 3787, 8, 1, 4, 671, 0, 0, 2582, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3787 = VST3LNq16Pseudo_UPD |
| 6605 | { 3786, 6, 0, 4, 669, 0, 0, 2576, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3786 = VST3LNq16Pseudo |
| 6606 | { 3785, 8, 0, 4, 668, 0, 0, 2558, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3785 = VST3LNq16 |
| 6607 | { 3784, 10, 1, 4, 825, 0, 0, 2566, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3784 = VST3LNd8_UPD |
| 6608 | { 3783, 8, 1, 4, 827, 0, 0, 2543, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3783 = VST3LNd8Pseudo_UPD |
| 6609 | { 3782, 6, 0, 4, 821, 0, 0, 2537, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3782 = VST3LNd8Pseudo |
| 6610 | { 3781, 8, 0, 4, 819, 0, 0, 2558, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3781 = VST3LNd8 |
| 6611 | { 3780, 10, 1, 4, 825, 0, 0, 2566, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3780 = VST3LNd32_UPD |
| 6612 | { 3779, 8, 1, 4, 827, 0, 0, 2543, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3779 = VST3LNd32Pseudo_UPD |
| 6613 | { 3778, 6, 0, 4, 821, 0, 0, 2537, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3778 = VST3LNd32Pseudo |
| 6614 | { 3777, 8, 0, 4, 819, 0, 0, 2558, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3777 = VST3LNd32 |
| 6615 | { 3776, 10, 1, 4, 825, 0, 0, 2566, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3776 = VST3LNd16_UPD |
| 6616 | { 3775, 8, 1, 4, 827, 0, 0, 2543, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3775 = VST3LNd16Pseudo_UPD |
| 6617 | { 3774, 6, 0, 4, 821, 0, 0, 2537, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3774 = VST3LNd16Pseudo |
| 6618 | { 3773, 8, 0, 4, 819, 0, 0, 2558, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3773 = VST3LNd16 |
| 6619 | { 3772, 7, 1, 4, 657, 0, 0, 2484, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3772 = VST2q8wb_register |
| 6620 | { 3771, 6, 1, 4, 657, 0, 0, 2478, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3771 = VST2q8wb_fixed |
| 6621 | { 3770, 7, 1, 4, 658, 0, 0, 2551, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3770 = VST2q8PseudoWB_register |
| 6622 | { 3769, 6, 1, 4, 658, 0, 0, 2465, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3769 = VST2q8PseudoWB_fixed |
| 6623 | { 3768, 5, 0, 4, 656, 0, 0, 2460, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3768 = VST2q8Pseudo |
| 6624 | { 3767, 5, 0, 4, 806, 0, 0, 2455, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3767 = VST2q8 |
| 6625 | { 3766, 7, 1, 4, 657, 0, 0, 2484, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3766 = VST2q32wb_register |
| 6626 | { 3765, 6, 1, 4, 657, 0, 0, 2478, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3765 = VST2q32wb_fixed |
| 6627 | { 3764, 7, 1, 4, 658, 0, 0, 2551, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3764 = VST2q32PseudoWB_register |
| 6628 | { 3763, 6, 1, 4, 658, 0, 0, 2465, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3763 = VST2q32PseudoWB_fixed |
| 6629 | { 3762, 5, 0, 4, 656, 0, 0, 2460, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3762 = VST2q32Pseudo |
| 6630 | { 3761, 5, 0, 4, 806, 0, 0, 2455, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3761 = VST2q32 |
| 6631 | { 3760, 7, 1, 4, 657, 0, 0, 2484, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3760 = VST2q16wb_register |
| 6632 | { 3759, 6, 1, 4, 657, 0, 0, 2478, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3759 = VST2q16wb_fixed |
| 6633 | { 3758, 7, 1, 4, 658, 0, 0, 2551, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3758 = VST2q16PseudoWB_register |
| 6634 | { 3757, 6, 1, 4, 658, 0, 0, 2465, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3757 = VST2q16PseudoWB_fixed |
| 6635 | { 3756, 5, 0, 4, 656, 0, 0, 2460, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3756 = VST2q16Pseudo |
| 6636 | { 3755, 5, 0, 4, 806, 0, 0, 2455, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3755 = VST2q16 |
| 6637 | { 3754, 7, 1, 4, 655, 0, 0, 2514, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3754 = VST2d8wb_register |
| 6638 | { 3753, 6, 1, 4, 655, 0, 0, 2508, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3753 = VST2d8wb_fixed |
| 6639 | { 3752, 5, 0, 4, 654, 0, 0, 2491, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3752 = VST2d8 |
| 6640 | { 3751, 7, 1, 4, 655, 0, 0, 2514, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3751 = VST2d32wb_register |
| 6641 | { 3750, 6, 1, 4, 655, 0, 0, 2508, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3750 = VST2d32wb_fixed |
| 6642 | { 3749, 5, 0, 4, 654, 0, 0, 2491, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3749 = VST2d32 |
| 6643 | { 3748, 7, 1, 4, 655, 0, 0, 2514, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3748 = VST2d16wb_register |
| 6644 | { 3747, 6, 1, 4, 655, 0, 0, 2508, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3747 = VST2d16wb_fixed |
| 6645 | { 3746, 5, 0, 4, 654, 0, 0, 2491, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3746 = VST2d16 |
| 6646 | { 3745, 7, 1, 4, 655, 0, 0, 2514, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3745 = VST2b8wb_register |
| 6647 | { 3744, 6, 1, 4, 655, 0, 0, 2508, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3744 = VST2b8wb_fixed |
| 6648 | { 3743, 5, 0, 4, 653, 0, 0, 2491, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3743 = VST2b8 |
| 6649 | { 3742, 7, 1, 4, 655, 0, 0, 2514, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3742 = VST2b32wb_register |
| 6650 | { 3741, 6, 1, 4, 655, 0, 0, 2508, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3741 = VST2b32wb_fixed |
| 6651 | { 3740, 5, 0, 4, 653, 0, 0, 2491, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3740 = VST2b32 |
| 6652 | { 3739, 7, 1, 4, 655, 0, 0, 2514, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3739 = VST2b16wb_register |
| 6653 | { 3738, 6, 1, 4, 655, 0, 0, 2508, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3738 = VST2b16wb_fixed |
| 6654 | { 3737, 5, 0, 4, 653, 0, 0, 2491, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3737 = VST2b16 |
| 6655 | { 3736, 9, 1, 4, 666, 0, 0, 2528, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3736 = VST2LNq32_UPD |
| 6656 | { 3735, 8, 1, 4, 667, 0, 0, 2543, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3735 = VST2LNq32Pseudo_UPD |
| 6657 | { 3734, 6, 0, 4, 665, 0, 0, 2537, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3734 = VST2LNq32Pseudo |
| 6658 | { 3733, 7, 0, 4, 810, 0, 0, 2521, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3733 = VST2LNq32 |
| 6659 | { 3732, 9, 1, 4, 666, 0, 0, 2528, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3732 = VST2LNq16_UPD |
| 6660 | { 3731, 8, 1, 4, 667, 0, 0, 2543, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3731 = VST2LNq16Pseudo_UPD |
| 6661 | { 3730, 6, 0, 4, 665, 0, 0, 2537, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3730 = VST2LNq16Pseudo |
| 6662 | { 3729, 7, 0, 4, 810, 0, 0, 2521, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3729 = VST2LNq16 |
| 6663 | { 3728, 9, 1, 4, 812, 0, 0, 2528, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3728 = VST2LNd8_UPD |
| 6664 | { 3727, 8, 1, 4, 814, 0, 0, 2447, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3727 = VST2LNd8Pseudo_UPD |
| 6665 | { 3726, 6, 0, 4, 809, 0, 0, 2441, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3726 = VST2LNd8Pseudo |
| 6666 | { 3725, 7, 0, 4, 807, 0, 0, 2521, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3725 = VST2LNd8 |
| 6667 | { 3724, 9, 1, 4, 812, 0, 0, 2528, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3724 = VST2LNd32_UPD |
| 6668 | { 3723, 8, 1, 4, 814, 0, 0, 2447, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3723 = VST2LNd32Pseudo_UPD |
| 6669 | { 3722, 6, 0, 4, 809, 0, 0, 2441, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3722 = VST2LNd32Pseudo |
| 6670 | { 3721, 7, 0, 4, 807, 0, 0, 2521, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3721 = VST2LNd32 |
| 6671 | { 3720, 9, 1, 4, 812, 0, 0, 2528, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3720 = VST2LNd16_UPD |
| 6672 | { 3719, 8, 1, 4, 814, 0, 0, 2447, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3719 = VST2LNd16Pseudo_UPD |
| 6673 | { 3718, 6, 0, 4, 809, 0, 0, 2441, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3718 = VST2LNd16Pseudo |
| 6674 | { 3717, 7, 0, 4, 807, 0, 0, 2521, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3717 = VST2LNd16 |
| 6675 | { 3716, 7, 1, 4, 646, 0, 0, 2514, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3716 = VST1q8wb_register |
| 6676 | { 3715, 6, 1, 4, 646, 0, 0, 2508, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3715 = VST1q8wb_fixed |
| 6677 | { 3714, 7, 1, 4, 1053, 0, 0, 2501, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3714 = VST1q8LowTPseudo_UPD |
| 6678 | { 3713, 7, 1, 4, 1055, 0, 0, 2501, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3713 = VST1q8LowQPseudo_UPD |
| 6679 | { 3712, 7, 1, 4, 1053, 0, 0, 2501, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3712 = VST1q8HighTPseudo_UPD |
| 6680 | { 3711, 5, 0, 4, 1053, 0, 0, 2496, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3711 = VST1q8HighTPseudo |
| 6681 | { 3710, 7, 1, 4, 1055, 0, 0, 2501, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3710 = VST1q8HighQPseudo_UPD |
| 6682 | { 3709, 5, 0, 4, 1055, 0, 0, 2496, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3709 = VST1q8HighQPseudo |
| 6683 | { 3708, 5, 0, 4, 644, 0, 0, 2491, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3708 = VST1q8 |
| 6684 | { 3707, 7, 1, 4, 646, 0, 0, 2514, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3707 = VST1q64wb_register |
| 6685 | { 3706, 6, 1, 4, 646, 0, 0, 2508, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3706 = VST1q64wb_fixed |
| 6686 | { 3705, 7, 1, 4, 1053, 0, 0, 2501, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3705 = VST1q64LowTPseudo_UPD |
| 6687 | { 3704, 7, 1, 4, 1055, 0, 0, 2501, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3704 = VST1q64LowQPseudo_UPD |
| 6688 | { 3703, 7, 1, 4, 1053, 0, 0, 2501, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3703 = VST1q64HighTPseudo_UPD |
| 6689 | { 3702, 5, 0, 4, 1053, 0, 0, 2496, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3702 = VST1q64HighTPseudo |
| 6690 | { 3701, 7, 1, 4, 1055, 0, 0, 2501, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3701 = VST1q64HighQPseudo_UPD |
| 6691 | { 3700, 5, 0, 4, 1055, 0, 0, 2496, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3700 = VST1q64HighQPseudo |
| 6692 | { 3699, 5, 0, 4, 644, 0, 0, 2491, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3699 = VST1q64 |
| 6693 | { 3698, 7, 1, 4, 646, 0, 0, 2514, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3698 = VST1q32wb_register |
| 6694 | { 3697, 6, 1, 4, 646, 0, 0, 2508, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3697 = VST1q32wb_fixed |
| 6695 | { 3696, 7, 1, 4, 1053, 0, 0, 2501, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3696 = VST1q32LowTPseudo_UPD |
| 6696 | { 3695, 7, 1, 4, 1055, 0, 0, 2501, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3695 = VST1q32LowQPseudo_UPD |
| 6697 | { 3694, 7, 1, 4, 1053, 0, 0, 2501, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3694 = VST1q32HighTPseudo_UPD |
| 6698 | { 3693, 5, 0, 4, 1053, 0, 0, 2496, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3693 = VST1q32HighTPseudo |
| 6699 | { 3692, 7, 1, 4, 1055, 0, 0, 2501, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3692 = VST1q32HighQPseudo_UPD |
| 6700 | { 3691, 5, 0, 4, 1055, 0, 0, 2496, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3691 = VST1q32HighQPseudo |
| 6701 | { 3690, 5, 0, 4, 644, 0, 0, 2491, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3690 = VST1q32 |
| 6702 | { 3689, 7, 1, 4, 646, 0, 0, 2514, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3689 = VST1q16wb_register |
| 6703 | { 3688, 6, 1, 4, 646, 0, 0, 2508, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3688 = VST1q16wb_fixed |
| 6704 | { 3687, 7, 1, 4, 1053, 0, 0, 2501, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3687 = VST1q16LowTPseudo_UPD |
| 6705 | { 3686, 7, 1, 4, 1055, 0, 0, 2501, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3686 = VST1q16LowQPseudo_UPD |
| 6706 | { 3685, 7, 1, 4, 1053, 0, 0, 2501, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3685 = VST1q16HighTPseudo_UPD |
| 6707 | { 3684, 5, 0, 4, 1053, 0, 0, 2496, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3684 = VST1q16HighTPseudo |
| 6708 | { 3683, 7, 1, 4, 1055, 0, 0, 2501, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3683 = VST1q16HighQPseudo_UPD |
| 6709 | { 3682, 5, 0, 4, 1055, 0, 0, 2496, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3682 = VST1q16HighQPseudo |
| 6710 | { 3681, 5, 0, 4, 644, 0, 0, 2491, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3681 = VST1q16 |
| 6711 | { 3680, 7, 1, 4, 645, 0, 0, 2484, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3680 = VST1d8wb_register |
| 6712 | { 3679, 6, 1, 4, 645, 0, 0, 2478, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3679 = VST1d8wb_fixed |
| 6713 | { 3678, 7, 1, 4, 648, 0, 0, 2484, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3678 = VST1d8Twb_register |
| 6714 | { 3677, 6, 1, 4, 648, 0, 0, 2478, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3677 = VST1d8Twb_fixed |
| 6715 | { 3676, 7, 1, 4, 1054, 0, 0, 2471, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3676 = VST1d8TPseudoWB_register |
| 6716 | { 3675, 6, 1, 4, 1054, 0, 0, 2465, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3675 = VST1d8TPseudoWB_fixed |
| 6717 | { 3674, 5, 0, 4, 1053, 0, 0, 2460, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3674 = VST1d8TPseudo |
| 6718 | { 3673, 5, 0, 4, 798, 0, 0, 2455, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3673 = VST1d8T |
| 6719 | { 3672, 7, 1, 4, 652, 0, 0, 2484, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3672 = VST1d8Qwb_register |
| 6720 | { 3671, 6, 1, 4, 652, 0, 0, 2478, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3671 = VST1d8Qwb_fixed |
| 6721 | { 3670, 7, 1, 4, 651, 0, 0, 2471, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3670 = VST1d8QPseudoWB_register |
| 6722 | { 3669, 6, 1, 4, 651, 0, 0, 2465, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3669 = VST1d8QPseudoWB_fixed |
| 6723 | { 3668, 5, 0, 4, 650, 0, 0, 2460, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3668 = VST1d8QPseudo |
| 6724 | { 3667, 5, 0, 4, 799, 0, 0, 2455, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3667 = VST1d8Q |
| 6725 | { 3666, 5, 0, 4, 643, 0, 0, 2455, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3666 = VST1d8 |
| 6726 | { 3665, 7, 1, 4, 645, 0, 0, 2484, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3665 = VST1d64wb_register |
| 6727 | { 3664, 6, 1, 4, 645, 0, 0, 2478, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3664 = VST1d64wb_fixed |
| 6728 | { 3663, 7, 1, 4, 648, 0, 0, 2484, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3663 = VST1d64Twb_register |
| 6729 | { 3662, 6, 1, 4, 648, 0, 0, 2478, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3662 = VST1d64Twb_fixed |
| 6730 | { 3661, 7, 1, 4, 649, 0, 0, 2471, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3661 = VST1d64TPseudoWB_register |
| 6731 | { 3660, 6, 1, 4, 649, 0, 0, 2465, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3660 = VST1d64TPseudoWB_fixed |
| 6732 | { 3659, 5, 0, 4, 647, 0, 0, 2460, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3659 = VST1d64TPseudo |
| 6733 | { 3658, 5, 0, 4, 798, 0, 0, 2455, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3658 = VST1d64T |
| 6734 | { 3657, 7, 1, 4, 652, 0, 0, 2484, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3657 = VST1d64Qwb_register |
| 6735 | { 3656, 6, 1, 4, 652, 0, 0, 2478, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3656 = VST1d64Qwb_fixed |
| 6736 | { 3655, 7, 1, 4, 803, 0, 0, 2471, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3655 = VST1d64QPseudoWB_register |
| 6737 | { 3654, 6, 1, 4, 803, 0, 0, 2465, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3654 = VST1d64QPseudoWB_fixed |
| 6738 | { 3653, 5, 0, 4, 800, 0, 0, 2460, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3653 = VST1d64QPseudo |
| 6739 | { 3652, 5, 0, 4, 799, 0, 0, 2455, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3652 = VST1d64Q |
| 6740 | { 3651, 5, 0, 4, 643, 0, 0, 2455, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3651 = VST1d64 |
| 6741 | { 3650, 7, 1, 4, 645, 0, 0, 2484, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3650 = VST1d32wb_register |
| 6742 | { 3649, 6, 1, 4, 645, 0, 0, 2478, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3649 = VST1d32wb_fixed |
| 6743 | { 3648, 7, 1, 4, 648, 0, 0, 2484, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3648 = VST1d32Twb_register |
| 6744 | { 3647, 6, 1, 4, 648, 0, 0, 2478, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3647 = VST1d32Twb_fixed |
| 6745 | { 3646, 7, 1, 4, 1054, 0, 0, 2471, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3646 = VST1d32TPseudoWB_register |
| 6746 | { 3645, 6, 1, 4, 1054, 0, 0, 2465, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3645 = VST1d32TPseudoWB_fixed |
| 6747 | { 3644, 5, 0, 4, 1053, 0, 0, 2460, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3644 = VST1d32TPseudo |
| 6748 | { 3643, 5, 0, 4, 798, 0, 0, 2455, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3643 = VST1d32T |
| 6749 | { 3642, 7, 1, 4, 652, 0, 0, 2484, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3642 = VST1d32Qwb_register |
| 6750 | { 3641, 6, 1, 4, 652, 0, 0, 2478, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3641 = VST1d32Qwb_fixed |
| 6751 | { 3640, 7, 1, 4, 651, 0, 0, 2471, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3640 = VST1d32QPseudoWB_register |
| 6752 | { 3639, 6, 1, 4, 651, 0, 0, 2465, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3639 = VST1d32QPseudoWB_fixed |
| 6753 | { 3638, 5, 0, 4, 650, 0, 0, 2460, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3638 = VST1d32QPseudo |
| 6754 | { 3637, 5, 0, 4, 799, 0, 0, 2455, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3637 = VST1d32Q |
| 6755 | { 3636, 5, 0, 4, 643, 0, 0, 2455, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3636 = VST1d32 |
| 6756 | { 3635, 7, 1, 4, 645, 0, 0, 2484, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3635 = VST1d16wb_register |
| 6757 | { 3634, 6, 1, 4, 645, 0, 0, 2478, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3634 = VST1d16wb_fixed |
| 6758 | { 3633, 7, 1, 4, 648, 0, 0, 2484, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3633 = VST1d16Twb_register |
| 6759 | { 3632, 6, 1, 4, 648, 0, 0, 2478, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3632 = VST1d16Twb_fixed |
| 6760 | { 3631, 7, 1, 4, 1054, 0, 0, 2471, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3631 = VST1d16TPseudoWB_register |
| 6761 | { 3630, 6, 1, 4, 1054, 0, 0, 2465, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3630 = VST1d16TPseudoWB_fixed |
| 6762 | { 3629, 5, 0, 4, 1053, 0, 0, 2460, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3629 = VST1d16TPseudo |
| 6763 | { 3628, 5, 0, 4, 798, 0, 0, 2455, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3628 = VST1d16T |
| 6764 | { 3627, 7, 1, 4, 652, 0, 0, 2484, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3627 = VST1d16Qwb_register |
| 6765 | { 3626, 6, 1, 4, 652, 0, 0, 2478, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3626 = VST1d16Qwb_fixed |
| 6766 | { 3625, 7, 1, 4, 651, 0, 0, 2471, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3625 = VST1d16QPseudoWB_register |
| 6767 | { 3624, 6, 1, 4, 651, 0, 0, 2465, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3624 = VST1d16QPseudoWB_fixed |
| 6768 | { 3623, 5, 0, 4, 650, 0, 0, 2460, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // Inst #3623 = VST1d16QPseudo |
| 6769 | { 3622, 5, 0, 4, 799, 0, 0, 2455, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3622 = VST1d16Q |
| 6770 | { 3621, 5, 0, 4, 643, 0, 0, 2455, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // Inst #3621 = VST1d16 |
| 6771 | { 3620, 8, 1, 4, 664, 0, 0, 2447, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x10006ULL }, // Inst #3620 = VST1LNq8Pseudo_UPD |
| 6772 | { 3619, 6, 0, 4, 663, 0, 0, 2441, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x10006ULL }, // Inst #3619 = VST1LNq8Pseudo |
| 6773 | { 3618, 8, 1, 4, 664, 0, 0, 2447, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x10006ULL }, // Inst #3618 = VST1LNq32Pseudo_UPD |
| 6774 | { 3617, 6, 0, 4, 663, 0, 0, 2441, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x10006ULL }, // Inst #3617 = VST1LNq32Pseudo |
| 6775 | { 3616, 8, 1, 4, 664, 0, 0, 2447, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x10006ULL }, // Inst #3616 = VST1LNq16Pseudo_UPD |
| 6776 | { 3615, 6, 0, 4, 663, 0, 0, 2441, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x10006ULL }, // Inst #3615 = VST1LNq16Pseudo |
| 6777 | { 3614, 8, 1, 4, 804, 0, 0, 2433, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x10f06ULL }, // Inst #3614 = VST1LNd8_UPD |
| 6778 | { 3613, 6, 0, 4, 801, 0, 0, 2427, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x10f06ULL }, // Inst #3613 = VST1LNd8 |
| 6779 | { 3612, 8, 1, 4, 804, 0, 0, 2433, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x10f06ULL }, // Inst #3612 = VST1LNd32_UPD |
| 6780 | { 3611, 6, 0, 4, 801, 0, 0, 2427, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x10f06ULL }, // Inst #3611 = VST1LNd32 |
| 6781 | { 3610, 8, 1, 4, 804, 0, 0, 2433, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x10f06ULL }, // Inst #3610 = VST1LNd16_UPD |
| 6782 | { 3609, 6, 0, 4, 801, 0, 0, 2427, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x10f06ULL }, // Inst #3609 = VST1LNd16 |
| 6783 | { 3608, 6, 1, 4, 989, 0, 0, 2389, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3608 = VSRIv8i8 |
| 6784 | { 3607, 6, 1, 4, 990, 0, 0, 2383, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3607 = VSRIv8i16 |
| 6785 | { 3606, 6, 1, 4, 990, 0, 0, 2383, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3606 = VSRIv4i32 |
| 6786 | { 3605, 6, 1, 4, 989, 0, 0, 2389, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3605 = VSRIv4i16 |
| 6787 | { 3604, 6, 1, 4, 990, 0, 0, 2383, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3604 = VSRIv2i64 |
| 6788 | { 3603, 6, 1, 4, 989, 0, 0, 2389, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3603 = VSRIv2i32 |
| 6789 | { 3602, 6, 1, 4, 989, 0, 0, 2389, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3602 = VSRIv1i64 |
| 6790 | { 3601, 6, 1, 4, 990, 0, 0, 2383, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3601 = VSRIv16i8 |
| 6791 | { 3600, 6, 1, 4, 482, 0, 0, 2389, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3600 = VSRAuv8i8 |
| 6792 | { 3599, 6, 1, 4, 482, 0, 0, 2383, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3599 = VSRAuv8i16 |
| 6793 | { 3598, 6, 1, 4, 482, 0, 0, 2383, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3598 = VSRAuv4i32 |
| 6794 | { 3597, 6, 1, 4, 482, 0, 0, 2389, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3597 = VSRAuv4i16 |
| 6795 | { 3596, 6, 1, 4, 482, 0, 0, 2383, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3596 = VSRAuv2i64 |
| 6796 | { 3595, 6, 1, 4, 482, 0, 0, 2389, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3595 = VSRAuv2i32 |
| 6797 | { 3594, 6, 1, 4, 482, 0, 0, 2389, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3594 = VSRAuv1i64 |
| 6798 | { 3593, 6, 1, 4, 482, 0, 0, 2383, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3593 = VSRAuv16i8 |
| 6799 | { 3592, 6, 1, 4, 482, 0, 0, 2389, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3592 = VSRAsv8i8 |
| 6800 | { 3591, 6, 1, 4, 482, 0, 0, 2383, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3591 = VSRAsv8i16 |
| 6801 | { 3590, 6, 1, 4, 482, 0, 0, 2383, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3590 = VSRAsv4i32 |
| 6802 | { 3589, 6, 1, 4, 482, 0, 0, 2389, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3589 = VSRAsv4i16 |
| 6803 | { 3588, 6, 1, 4, 482, 0, 0, 2383, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3588 = VSRAsv2i64 |
| 6804 | { 3587, 6, 1, 4, 482, 0, 0, 2389, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3587 = VSRAsv2i32 |
| 6805 | { 3586, 6, 1, 4, 482, 0, 0, 2389, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3586 = VSRAsv1i64 |
| 6806 | { 3585, 6, 1, 4, 482, 0, 0, 2383, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3585 = VSRAsv16i8 |
| 6807 | { 3584, 4, 1, 4, 676, 0, 0, 1691, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x8780ULL }, // Inst #3584 = VSQRTS |
| 6808 | { 3583, 4, 1, 4, 961, 0, 0, 1687, ARMImpOpBase + 0, 0, 0x8780ULL }, // Inst #3583 = VSQRTH |
| 6809 | { 3582, 4, 1, 4, 678, 0, 0, 1683, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x8780ULL }, // Inst #3582 = VSQRTD |
| 6810 | { 3581, 4, 1, 4, 0, 0, 0, 641, ARMImpOpBase + 0, 0, 0x11280ULL }, // Inst #3581 = VSMMLA |
| 6811 | { 3580, 5, 1, 4, 222, 0, 0, 2406, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x28880ULL }, // Inst #3580 = VSLTOS |
| 6812 | { 3579, 5, 1, 4, 221, 0, 0, 2406, ARMImpOpBase + 0, 0, 0x8880ULL }, // Inst #3579 = VSLTOH |
| 6813 | { 3578, 5, 1, 4, 1289, 0, 0, 2401, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x8880ULL }, // Inst #3578 = VSLTOD |
| 6814 | { 3577, 6, 1, 4, 989, 0, 0, 2421, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3577 = VSLIv8i8 |
| 6815 | { 3576, 6, 1, 4, 990, 0, 0, 2415, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3576 = VSLIv8i16 |
| 6816 | { 3575, 6, 1, 4, 990, 0, 0, 2415, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3575 = VSLIv4i32 |
| 6817 | { 3574, 6, 1, 4, 989, 0, 0, 2421, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3574 = VSLIv4i16 |
| 6818 | { 3573, 6, 1, 4, 990, 0, 0, 2415, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3573 = VSLIv2i64 |
| 6819 | { 3572, 6, 1, 4, 989, 0, 0, 2421, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3572 = VSLIv2i32 |
| 6820 | { 3571, 6, 1, 4, 989, 0, 0, 2421, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3571 = VSLIv1i64 |
| 6821 | { 3570, 6, 1, 4, 990, 0, 0, 2415, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3570 = VSLIv16i8 |
| 6822 | { 3569, 4, 1, 4, 563, 0, 0, 1691, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x28880ULL }, // Inst #3569 = VSITOS |
| 6823 | { 3568, 4, 1, 4, 562, 0, 0, 2411, ARMImpOpBase + 0, 0, 0x8880ULL }, // Inst #3568 = VSITOH |
| 6824 | { 3567, 4, 1, 4, 561, 0, 0, 1810, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x8880ULL }, // Inst #3567 = VSITOD |
| 6825 | { 3566, 5, 1, 4, 222, 0, 0, 2406, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x28880ULL }, // Inst #3566 = VSHTOS |
| 6826 | { 3565, 5, 1, 4, 221, 0, 0, 2406, ARMImpOpBase + 0, 0, 0x8880ULL }, // Inst #3565 = VSHTOH |
| 6827 | { 3564, 5, 1, 4, 1289, 0, 0, 2401, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x8880ULL }, // Inst #3564 = VSHTOD |
| 6828 | { 3563, 5, 1, 4, 986, 0, 0, 1818, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3563 = VSHRuv8i8 |
| 6829 | { 3562, 5, 1, 4, 986, 0, 0, 1823, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3562 = VSHRuv8i16 |
| 6830 | { 3561, 5, 1, 4, 986, 0, 0, 1823, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3561 = VSHRuv4i32 |
| 6831 | { 3560, 5, 1, 4, 986, 0, 0, 1818, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3560 = VSHRuv4i16 |
| 6832 | { 3559, 5, 1, 4, 986, 0, 0, 1823, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3559 = VSHRuv2i64 |
| 6833 | { 3558, 5, 1, 4, 986, 0, 0, 1818, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3558 = VSHRuv2i32 |
| 6834 | { 3557, 5, 1, 4, 986, 0, 0, 1818, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3557 = VSHRuv1i64 |
| 6835 | { 3556, 5, 1, 4, 986, 0, 0, 1823, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3556 = VSHRuv16i8 |
| 6836 | { 3555, 5, 1, 4, 986, 0, 0, 1818, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3555 = VSHRsv8i8 |
| 6837 | { 3554, 5, 1, 4, 986, 0, 0, 1823, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3554 = VSHRsv8i16 |
| 6838 | { 3553, 5, 1, 4, 986, 0, 0, 1823, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3553 = VSHRsv4i32 |
| 6839 | { 3552, 5, 1, 4, 986, 0, 0, 1818, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3552 = VSHRsv4i16 |
| 6840 | { 3551, 5, 1, 4, 986, 0, 0, 1823, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3551 = VSHRsv2i64 |
| 6841 | { 3550, 5, 1, 4, 986, 0, 0, 1818, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3550 = VSHRsv2i32 |
| 6842 | { 3549, 5, 1, 4, 986, 0, 0, 1818, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3549 = VSHRsv1i64 |
| 6843 | { 3548, 5, 1, 4, 986, 0, 0, 1823, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3548 = VSHRsv16i8 |
| 6844 | { 3547, 5, 1, 4, 501, 0, 0, 2366, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3547 = VSHRNv8i8 |
| 6845 | { 3546, 5, 1, 4, 501, 0, 0, 2366, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3546 = VSHRNv4i16 |
| 6846 | { 3545, 5, 1, 4, 501, 0, 0, 2366, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3545 = VSHRNv2i32 |
| 6847 | { 3544, 5, 1, 4, 464, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3544 = VSHLuv8i8 |
| 6848 | { 3543, 5, 1, 4, 465, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3543 = VSHLuv8i16 |
| 6849 | { 3542, 5, 1, 4, 465, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3542 = VSHLuv4i32 |
| 6850 | { 3541, 5, 1, 4, 464, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3541 = VSHLuv4i16 |
| 6851 | { 3540, 5, 1, 4, 465, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3540 = VSHLuv2i64 |
| 6852 | { 3539, 5, 1, 4, 464, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3539 = VSHLuv2i32 |
| 6853 | { 3538, 5, 1, 4, 464, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3538 = VSHLuv1i64 |
| 6854 | { 3537, 5, 1, 4, 465, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3537 = VSHLuv16i8 |
| 6855 | { 3536, 5, 1, 4, 464, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3536 = VSHLsv8i8 |
| 6856 | { 3535, 5, 1, 4, 465, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3535 = VSHLsv8i16 |
| 6857 | { 3534, 5, 1, 4, 465, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3534 = VSHLsv4i32 |
| 6858 | { 3533, 5, 1, 4, 464, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3533 = VSHLsv4i16 |
| 6859 | { 3532, 5, 1, 4, 465, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3532 = VSHLsv2i64 |
| 6860 | { 3531, 5, 1, 4, 464, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3531 = VSHLsv2i32 |
| 6861 | { 3530, 5, 1, 4, 464, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3530 = VSHLsv1i64 |
| 6862 | { 3529, 5, 1, 4, 465, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3529 = VSHLsv16i8 |
| 6863 | { 3528, 5, 1, 4, 986, 0, 0, 2376, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3528 = VSHLiv8i8 |
| 6864 | { 3527, 5, 1, 4, 986, 0, 0, 2371, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3527 = VSHLiv8i16 |
| 6865 | { 3526, 5, 1, 4, 986, 0, 0, 2371, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3526 = VSHLiv4i32 |
| 6866 | { 3525, 5, 1, 4, 986, 0, 0, 2376, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3525 = VSHLiv4i16 |
| 6867 | { 3524, 5, 1, 4, 986, 0, 0, 2371, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3524 = VSHLiv2i64 |
| 6868 | { 3523, 5, 1, 4, 986, 0, 0, 2376, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3523 = VSHLiv2i32 |
| 6869 | { 3522, 5, 1, 4, 986, 0, 0, 2376, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3522 = VSHLiv1i64 |
| 6870 | { 3521, 5, 1, 4, 986, 0, 0, 2371, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3521 = VSHLiv16i8 |
| 6871 | { 3520, 5, 1, 4, 986, 0, 0, 1840, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3520 = VSHLLuv8i16 |
| 6872 | { 3519, 5, 1, 4, 986, 0, 0, 1840, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3519 = VSHLLuv4i32 |
| 6873 | { 3518, 5, 1, 4, 986, 0, 0, 1840, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3518 = VSHLLuv2i64 |
| 6874 | { 3517, 5, 1, 4, 986, 0, 0, 1840, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3517 = VSHLLsv8i16 |
| 6875 | { 3516, 5, 1, 4, 986, 0, 0, 1840, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3516 = VSHLLsv4i32 |
| 6876 | { 3515, 5, 1, 4, 986, 0, 0, 1840, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3515 = VSHLLsv2i64 |
| 6877 | { 3514, 5, 1, 4, 986, 0, 0, 1840, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3514 = VSHLLi8 |
| 6878 | { 3513, 5, 1, 4, 986, 0, 0, 1840, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3513 = VSHLLi32 |
| 6879 | { 3512, 5, 1, 4, 986, 0, 0, 1840, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3512 = VSHLLi16 |
| 6880 | { 3511, 6, 1, 4, 579, 0, 0, 2395, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x10e00ULL }, // Inst #3511 = VSETLNi8 |
| 6881 | { 3510, 6, 1, 4, 1043, 0, 0, 2395, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::InsertSubreg), 0x10e00ULL }, // Inst #3510 = VSETLNi32 |
| 6882 | { 3509, 6, 1, 4, 579, 0, 0, 2395, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x10e00ULL }, // Inst #3509 = VSETLNi16 |
| 6883 | { 3508, 3, 1, 4, 1258, 1, 0, 1886, ARMImpOpBase + 0, 0, 0x8800ULL }, // Inst #3508 = VSELVSS |
| 6884 | { 3507, 3, 1, 4, 771, 1, 0, 1883, ARMImpOpBase + 0, 0, 0x8800ULL }, // Inst #3507 = VSELVSH |
| 6885 | { 3506, 3, 1, 4, 1259, 1, 0, 1506, ARMImpOpBase + 0, 0, 0x8800ULL }, // Inst #3506 = VSELVSD |
| 6886 | { 3505, 3, 1, 4, 1258, 1, 0, 1886, ARMImpOpBase + 0, 0, 0x8800ULL }, // Inst #3505 = VSELGTS |
| 6887 | { 3504, 3, 1, 4, 771, 1, 0, 1883, ARMImpOpBase + 0, 0, 0x8800ULL }, // Inst #3504 = VSELGTH |
| 6888 | { 3503, 3, 1, 4, 1259, 1, 0, 1506, ARMImpOpBase + 0, 0, 0x8800ULL }, // Inst #3503 = VSELGTD |
| 6889 | { 3502, 3, 1, 4, 1258, 1, 0, 1886, ARMImpOpBase + 0, 0, 0x8800ULL }, // Inst #3502 = VSELGES |
| 6890 | { 3501, 3, 1, 4, 771, 1, 0, 1883, ARMImpOpBase + 0, 0, 0x8800ULL }, // Inst #3501 = VSELGEH |
| 6891 | { 3500, 3, 1, 4, 1259, 1, 0, 1506, ARMImpOpBase + 0, 0, 0x8800ULL }, // Inst #3500 = VSELGED |
| 6892 | { 3499, 3, 1, 4, 1258, 1, 0, 1886, ARMImpOpBase + 0, 0, 0x8800ULL }, // Inst #3499 = VSELEQS |
| 6893 | { 3498, 3, 1, 4, 771, 1, 0, 1883, ARMImpOpBase + 0, 0, 0x8800ULL }, // Inst #3498 = VSELEQH |
| 6894 | { 3497, 3, 1, 4, 1259, 1, 0, 1506, ARMImpOpBase + 0, 0, 0x8800ULL }, // Inst #3497 = VSELEQD |
| 6895 | { 3496, 5, 1, 4, 963, 0, 0, 632, ARMImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x11280ULL }, // Inst #3496 = VSDOTQI |
| 6896 | { 3495, 4, 1, 4, 963, 0, 0, 641, ARMImpOpBase + 0, 0, 0x11280ULL }, // Inst #3495 = VSDOTQ |
| 6897 | { 3494, 5, 1, 4, 963, 0, 0, 627, ARMImpOpBase + 0, 0, 0x11280ULL }, // Inst #3494 = VSDOTDI |
| 6898 | { 3493, 4, 1, 4, 963, 0, 0, 637, ARMImpOpBase + 0, 0, 0x11280ULL }, // Inst #3493 = VSDOTD |
| 6899 | { 3492, 3, 0, 4, 0, 0, 0, 584, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL }, // Inst #3492 = VSCCLRMS |
| 6900 | { 3491, 3, 0, 4, 0, 0, 0, 584, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL }, // Inst #3491 = VSCCLRMD |
| 6901 | { 3490, 5, 1, 4, 502, 0, 0, 1704, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3490 = VRSUBHNv8i8 |
| 6902 | { 3489, 5, 1, 4, 502, 0, 0, 1704, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3489 = VRSUBHNv4i16 |
| 6903 | { 3488, 5, 1, 4, 502, 0, 0, 1704, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3488 = VRSUBHNv2i32 |
| 6904 | { 3487, 6, 1, 4, 482, 0, 0, 2389, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3487 = VRSRAuv8i8 |
| 6905 | { 3486, 6, 1, 4, 482, 0, 0, 2383, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3486 = VRSRAuv8i16 |
| 6906 | { 3485, 6, 1, 4, 482, 0, 0, 2383, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3485 = VRSRAuv4i32 |
| 6907 | { 3484, 6, 1, 4, 482, 0, 0, 2389, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3484 = VRSRAuv4i16 |
| 6908 | { 3483, 6, 1, 4, 482, 0, 0, 2383, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3483 = VRSRAuv2i64 |
| 6909 | { 3482, 6, 1, 4, 482, 0, 0, 2389, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3482 = VRSRAuv2i32 |
| 6910 | { 3481, 6, 1, 4, 482, 0, 0, 2389, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3481 = VRSRAuv1i64 |
| 6911 | { 3480, 6, 1, 4, 482, 0, 0, 2383, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3480 = VRSRAuv16i8 |
| 6912 | { 3479, 6, 1, 4, 482, 0, 0, 2389, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3479 = VRSRAsv8i8 |
| 6913 | { 3478, 6, 1, 4, 482, 0, 0, 2383, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3478 = VRSRAsv8i16 |
| 6914 | { 3477, 6, 1, 4, 482, 0, 0, 2383, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3477 = VRSRAsv4i32 |
| 6915 | { 3476, 6, 1, 4, 482, 0, 0, 2389, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3476 = VRSRAsv4i16 |
| 6916 | { 3475, 6, 1, 4, 482, 0, 0, 2383, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3475 = VRSRAsv2i64 |
| 6917 | { 3474, 6, 1, 4, 482, 0, 0, 2389, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3474 = VRSRAsv2i32 |
| 6918 | { 3473, 6, 1, 4, 482, 0, 0, 2389, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3473 = VRSRAsv1i64 |
| 6919 | { 3472, 6, 1, 4, 482, 0, 0, 2383, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3472 = VRSRAsv16i8 |
| 6920 | { 3471, 5, 1, 4, 528, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3471 = VRSQRTShq |
| 6921 | { 3470, 5, 1, 4, 527, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3470 = VRSQRTShd |
| 6922 | { 3469, 5, 1, 4, 528, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3469 = VRSQRTSfq |
| 6923 | { 3468, 5, 1, 4, 527, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3468 = VRSQRTSfd |
| 6924 | { 3467, 4, 1, 4, 499, 0, 0, 1695, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3467 = VRSQRTEq |
| 6925 | { 3466, 4, 1, 4, 499, 0, 0, 1695, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3466 = VRSQRTEhq |
| 6926 | { 3465, 4, 1, 4, 498, 0, 0, 1683, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3465 = VRSQRTEhd |
| 6927 | { 3464, 4, 1, 4, 499, 0, 0, 1695, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3464 = VRSQRTEfq |
| 6928 | { 3463, 4, 1, 4, 498, 0, 0, 1683, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3463 = VRSQRTEfd |
| 6929 | { 3462, 4, 1, 4, 498, 0, 0, 1683, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3462 = VRSQRTEd |
| 6930 | { 3461, 5, 1, 4, 988, 0, 0, 1818, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3461 = VRSHRuv8i8 |
| 6931 | { 3460, 5, 1, 4, 988, 0, 0, 1823, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3460 = VRSHRuv8i16 |
| 6932 | { 3459, 5, 1, 4, 988, 0, 0, 1823, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3459 = VRSHRuv4i32 |
| 6933 | { 3458, 5, 1, 4, 988, 0, 0, 1818, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3458 = VRSHRuv4i16 |
| 6934 | { 3457, 5, 1, 4, 988, 0, 0, 1823, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3457 = VRSHRuv2i64 |
| 6935 | { 3456, 5, 1, 4, 988, 0, 0, 1818, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3456 = VRSHRuv2i32 |
| 6936 | { 3455, 5, 1, 4, 988, 0, 0, 1818, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3455 = VRSHRuv1i64 |
| 6937 | { 3454, 5, 1, 4, 988, 0, 0, 1823, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3454 = VRSHRuv16i8 |
| 6938 | { 3453, 5, 1, 4, 988, 0, 0, 1818, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3453 = VRSHRsv8i8 |
| 6939 | { 3452, 5, 1, 4, 988, 0, 0, 1823, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3452 = VRSHRsv8i16 |
| 6940 | { 3451, 5, 1, 4, 988, 0, 0, 1823, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3451 = VRSHRsv4i32 |
| 6941 | { 3450, 5, 1, 4, 988, 0, 0, 1818, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3450 = VRSHRsv4i16 |
| 6942 | { 3449, 5, 1, 4, 988, 0, 0, 1823, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3449 = VRSHRsv2i64 |
| 6943 | { 3448, 5, 1, 4, 988, 0, 0, 1818, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3448 = VRSHRsv2i32 |
| 6944 | { 3447, 5, 1, 4, 988, 0, 0, 1818, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3447 = VRSHRsv1i64 |
| 6945 | { 3446, 5, 1, 4, 988, 0, 0, 1823, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3446 = VRSHRsv16i8 |
| 6946 | { 3445, 5, 1, 4, 797, 0, 0, 2366, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3445 = VRSHRNv8i8 |
| 6947 | { 3444, 5, 1, 4, 797, 0, 0, 2366, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3444 = VRSHRNv4i16 |
| 6948 | { 3443, 5, 1, 4, 797, 0, 0, 2366, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3443 = VRSHRNv2i32 |
| 6949 | { 3442, 5, 1, 4, 796, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3442 = VRSHLuv8i8 |
| 6950 | { 3441, 5, 1, 4, 795, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3441 = VRSHLuv8i16 |
| 6951 | { 3440, 5, 1, 4, 795, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3440 = VRSHLuv4i32 |
| 6952 | { 3439, 5, 1, 4, 796, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3439 = VRSHLuv4i16 |
| 6953 | { 3438, 5, 1, 4, 795, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3438 = VRSHLuv2i64 |
| 6954 | { 3437, 5, 1, 4, 796, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3437 = VRSHLuv2i32 |
| 6955 | { 3436, 5, 1, 4, 796, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3436 = VRSHLuv1i64 |
| 6956 | { 3435, 5, 1, 4, 795, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3435 = VRSHLuv16i8 |
| 6957 | { 3434, 5, 1, 4, 796, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3434 = VRSHLsv8i8 |
| 6958 | { 3433, 5, 1, 4, 795, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3433 = VRSHLsv8i16 |
| 6959 | { 3432, 5, 1, 4, 795, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3432 = VRSHLsv4i32 |
| 6960 | { 3431, 5, 1, 4, 796, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3431 = VRSHLsv4i16 |
| 6961 | { 3430, 5, 1, 4, 795, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3430 = VRSHLsv2i64 |
| 6962 | { 3429, 5, 1, 4, 796, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3429 = VRSHLsv2i32 |
| 6963 | { 3428, 5, 1, 4, 796, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3428 = VRSHLsv1i64 |
| 6964 | { 3427, 5, 1, 4, 795, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3427 = VRSHLsv16i8 |
| 6965 | { 3426, 4, 1, 4, 1251, 0, 0, 1691, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x8780ULL }, // Inst #3426 = VRINTZS |
| 6966 | { 3425, 2, 1, 4, 999, 0, 0, 625, ARMImpOpBase + 0, 0, 0x11000ULL }, // Inst #3425 = VRINTZNQh |
| 6967 | { 3424, 2, 1, 4, 999, 0, 0, 625, ARMImpOpBase + 0, 0, 0x11000ULL }, // Inst #3424 = VRINTZNQf |
| 6968 | { 3423, 2, 1, 4, 999, 0, 0, 1797, ARMImpOpBase + 0, 0, 0x11000ULL }, // Inst #3423 = VRINTZNDh |
| 6969 | { 3422, 2, 1, 4, 999, 0, 0, 1797, ARMImpOpBase + 0, 0, 0x11000ULL }, // Inst #3422 = VRINTZNDf |
| 6970 | { 3421, 4, 1, 4, 960, 0, 0, 1687, ARMImpOpBase + 0, 0, 0x8780ULL }, // Inst #3421 = VRINTZH |
| 6971 | { 3420, 4, 1, 4, 1255, 0, 0, 1683, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x8780ULL }, // Inst #3420 = VRINTZD |
| 6972 | { 3419, 4, 1, 4, 1251, 0, 0, 1691, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x8780ULL }, // Inst #3419 = VRINTXS |
| 6973 | { 3418, 2, 1, 4, 999, 0, 0, 625, ARMImpOpBase + 0, 0, 0x11000ULL }, // Inst #3418 = VRINTXNQh |
| 6974 | { 3417, 2, 1, 4, 999, 0, 0, 625, ARMImpOpBase + 0, 0, 0x11000ULL }, // Inst #3417 = VRINTXNQf |
| 6975 | { 3416, 2, 1, 4, 999, 0, 0, 1797, ARMImpOpBase + 0, 0, 0x11000ULL }, // Inst #3416 = VRINTXNDh |
| 6976 | { 3415, 2, 1, 4, 999, 0, 0, 1797, ARMImpOpBase + 0, 0, 0x11000ULL }, // Inst #3415 = VRINTXNDf |
| 6977 | { 3414, 4, 1, 4, 960, 0, 0, 1687, ARMImpOpBase + 0, 0, 0x8780ULL }, // Inst #3414 = VRINTXH |
| 6978 | { 3413, 4, 1, 4, 1255, 0, 0, 1683, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x8780ULL }, // Inst #3413 = VRINTXD |
| 6979 | { 3412, 4, 1, 4, 1251, 0, 0, 1691, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x8780ULL }, // Inst #3412 = VRINTRS |
| 6980 | { 3411, 4, 1, 4, 960, 0, 0, 1687, ARMImpOpBase + 0, 0, 0x8780ULL }, // Inst #3411 = VRINTRH |
| 6981 | { 3410, 4, 1, 4, 1255, 0, 0, 1683, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x8780ULL }, // Inst #3410 = VRINTRD |
| 6982 | { 3409, 2, 1, 4, 1251, 0, 0, 1803, ARMImpOpBase + 0, 0, 0x8780ULL }, // Inst #3409 = VRINTPS |
| 6983 | { 3408, 2, 1, 4, 999, 0, 0, 625, ARMImpOpBase + 0, 0, 0x11000ULL }, // Inst #3408 = VRINTPNQh |
| 6984 | { 3407, 2, 1, 4, 999, 0, 0, 625, ARMImpOpBase + 0, 0, 0x11000ULL }, // Inst #3407 = VRINTPNQf |
| 6985 | { 3406, 2, 1, 4, 999, 0, 0, 1797, ARMImpOpBase + 0, 0, 0x11000ULL }, // Inst #3406 = VRINTPNDh |
| 6986 | { 3405, 2, 1, 4, 999, 0, 0, 1797, ARMImpOpBase + 0, 0, 0x11000ULL }, // Inst #3405 = VRINTPNDf |
| 6987 | { 3404, 2, 1, 4, 960, 0, 0, 2381, ARMImpOpBase + 0, 0, 0x8780ULL }, // Inst #3404 = VRINTPH |
| 6988 | { 3403, 2, 1, 4, 1255, 0, 0, 1797, ARMImpOpBase + 0, 0, 0x8780ULL }, // Inst #3403 = VRINTPD |
| 6989 | { 3402, 2, 1, 4, 1251, 0, 0, 1803, ARMImpOpBase + 0, 0, 0x8780ULL }, // Inst #3402 = VRINTNS |
| 6990 | { 3401, 2, 1, 4, 999, 0, 0, 625, ARMImpOpBase + 0, 0, 0x11000ULL }, // Inst #3401 = VRINTNNQh |
| 6991 | { 3400, 2, 1, 4, 999, 0, 0, 625, ARMImpOpBase + 0, 0, 0x11000ULL }, // Inst #3400 = VRINTNNQf |
| 6992 | { 3399, 2, 1, 4, 999, 0, 0, 1797, ARMImpOpBase + 0, 0, 0x11000ULL }, // Inst #3399 = VRINTNNDh |
| 6993 | { 3398, 2, 1, 4, 999, 0, 0, 1797, ARMImpOpBase + 0, 0, 0x11000ULL }, // Inst #3398 = VRINTNNDf |
| 6994 | { 3397, 2, 1, 4, 960, 0, 0, 2381, ARMImpOpBase + 0, 0, 0x8780ULL }, // Inst #3397 = VRINTNH |
| 6995 | { 3396, 2, 1, 4, 1255, 0, 0, 1797, ARMImpOpBase + 0, 0, 0x8780ULL }, // Inst #3396 = VRINTND |
| 6996 | { 3395, 2, 1, 4, 1251, 0, 0, 1803, ARMImpOpBase + 0, 0, 0x8780ULL }, // Inst #3395 = VRINTMS |
| 6997 | { 3394, 2, 1, 4, 999, 0, 0, 625, ARMImpOpBase + 0, 0, 0x11000ULL }, // Inst #3394 = VRINTMNQh |
| 6998 | { 3393, 2, 1, 4, 999, 0, 0, 625, ARMImpOpBase + 0, 0, 0x11000ULL }, // Inst #3393 = VRINTMNQf |
| 6999 | { 3392, 2, 1, 4, 999, 0, 0, 1797, ARMImpOpBase + 0, 0, 0x11000ULL }, // Inst #3392 = VRINTMNDh |
| 7000 | { 3391, 2, 1, 4, 999, 0, 0, 1797, ARMImpOpBase + 0, 0, 0x11000ULL }, // Inst #3391 = VRINTMNDf |
| 7001 | { 3390, 2, 1, 4, 960, 0, 0, 2381, ARMImpOpBase + 0, 0, 0x8780ULL }, // Inst #3390 = VRINTMH |
| 7002 | { 3389, 2, 1, 4, 1255, 0, 0, 1797, ARMImpOpBase + 0, 0, 0x8780ULL }, // Inst #3389 = VRINTMD |
| 7003 | { 3388, 2, 1, 4, 1251, 0, 0, 1803, ARMImpOpBase + 0, 0, 0x8780ULL }, // Inst #3388 = VRINTAS |
| 7004 | { 3387, 2, 1, 4, 999, 0, 0, 625, ARMImpOpBase + 0, 0, 0x11000ULL }, // Inst #3387 = VRINTANQh |
| 7005 | { 3386, 2, 1, 4, 999, 0, 0, 625, ARMImpOpBase + 0, 0, 0x11000ULL }, // Inst #3386 = VRINTANQf |
| 7006 | { 3385, 2, 1, 4, 999, 0, 0, 1797, ARMImpOpBase + 0, 0, 0x11000ULL }, // Inst #3385 = VRINTANDh |
| 7007 | { 3384, 2, 1, 4, 999, 0, 0, 1797, ARMImpOpBase + 0, 0, 0x11000ULL }, // Inst #3384 = VRINTANDf |
| 7008 | { 3383, 2, 1, 4, 960, 0, 0, 2381, ARMImpOpBase + 0, 0, 0x8780ULL }, // Inst #3383 = VRINTAH |
| 7009 | { 3382, 2, 1, 4, 1255, 0, 0, 1797, ARMImpOpBase + 0, 0, 0x8780ULL }, // Inst #3382 = VRINTAD |
| 7010 | { 3381, 5, 1, 4, 972, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3381 = VRHADDuv8i8 |
| 7011 | { 3380, 5, 1, 4, 971, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3380 = VRHADDuv8i16 |
| 7012 | { 3379, 5, 1, 4, 971, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3379 = VRHADDuv4i32 |
| 7013 | { 3378, 5, 1, 4, 972, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3378 = VRHADDuv4i16 |
| 7014 | { 3377, 5, 1, 4, 972, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3377 = VRHADDuv2i32 |
| 7015 | { 3376, 5, 1, 4, 971, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3376 = VRHADDuv16i8 |
| 7016 | { 3375, 5, 1, 4, 972, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3375 = VRHADDsv8i8 |
| 7017 | { 3374, 5, 1, 4, 971, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3374 = VRHADDsv8i16 |
| 7018 | { 3373, 5, 1, 4, 971, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3373 = VRHADDsv4i32 |
| 7019 | { 3372, 5, 1, 4, 972, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3372 = VRHADDsv4i16 |
| 7020 | { 3371, 5, 1, 4, 972, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3371 = VRHADDsv2i32 |
| 7021 | { 3370, 5, 1, 4, 971, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3370 = VRHADDsv16i8 |
| 7022 | { 3369, 4, 1, 4, 478, 0, 0, 1695, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3369 = VREV64q8 |
| 7023 | { 3368, 4, 1, 4, 478, 0, 0, 1695, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3368 = VREV64q32 |
| 7024 | { 3367, 4, 1, 4, 478, 0, 0, 1695, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3367 = VREV64q16 |
| 7025 | { 3366, 4, 1, 4, 477, 0, 0, 1683, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3366 = VREV64d8 |
| 7026 | { 3365, 4, 1, 4, 477, 0, 0, 1683, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3365 = VREV64d32 |
| 7027 | { 3364, 4, 1, 4, 477, 0, 0, 1683, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3364 = VREV64d16 |
| 7028 | { 3363, 4, 1, 4, 478, 0, 0, 1695, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3363 = VREV32q8 |
| 7029 | { 3362, 4, 1, 4, 478, 0, 0, 1695, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3362 = VREV32q16 |
| 7030 | { 3361, 4, 1, 4, 477, 0, 0, 1683, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3361 = VREV32d8 |
| 7031 | { 3360, 4, 1, 4, 477, 0, 0, 1683, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3360 = VREV32d16 |
| 7032 | { 3359, 4, 1, 4, 478, 0, 0, 1695, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3359 = VREV16q8 |
| 7033 | { 3358, 4, 1, 4, 477, 0, 0, 1683, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3358 = VREV16d8 |
| 7034 | { 3357, 5, 1, 4, 528, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3357 = VRECPShq |
| 7035 | { 3356, 5, 1, 4, 527, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3356 = VRECPShd |
| 7036 | { 3355, 5, 1, 4, 528, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3355 = VRECPSfq |
| 7037 | { 3354, 5, 1, 4, 527, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3354 = VRECPSfd |
| 7038 | { 3353, 4, 1, 4, 499, 0, 0, 1695, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3353 = VRECPEq |
| 7039 | { 3352, 4, 1, 4, 499, 0, 0, 1695, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3352 = VRECPEhq |
| 7040 | { 3351, 4, 1, 4, 498, 0, 0, 1683, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3351 = VRECPEhd |
| 7041 | { 3350, 4, 1, 4, 499, 0, 0, 1695, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3350 = VRECPEfq |
| 7042 | { 3349, 4, 1, 4, 498, 0, 0, 1683, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3349 = VRECPEfd |
| 7043 | { 3348, 4, 1, 4, 498, 0, 0, 1683, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3348 = VRECPEd |
| 7044 | { 3347, 5, 1, 4, 502, 0, 0, 1704, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3347 = VRADDHNv8i8 |
| 7045 | { 3346, 5, 1, 4, 502, 0, 0, 1704, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3346 = VRADDHNv4i16 |
| 7046 | { 3345, 5, 1, 4, 502, 0, 0, 1704, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3345 = VRADDHNv2i32 |
| 7047 | { 3344, 5, 1, 4, 486, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3344 = VQSUBuv8i8 |
| 7048 | { 3343, 5, 1, 4, 485, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3343 = VQSUBuv8i16 |
| 7049 | { 3342, 5, 1, 4, 485, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3342 = VQSUBuv4i32 |
| 7050 | { 3341, 5, 1, 4, 486, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3341 = VQSUBuv4i16 |
| 7051 | { 3340, 5, 1, 4, 485, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3340 = VQSUBuv2i64 |
| 7052 | { 3339, 5, 1, 4, 486, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3339 = VQSUBuv2i32 |
| 7053 | { 3338, 5, 1, 4, 486, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3338 = VQSUBuv1i64 |
| 7054 | { 3337, 5, 1, 4, 485, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3337 = VQSUBuv16i8 |
| 7055 | { 3336, 5, 1, 4, 486, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3336 = VQSUBsv8i8 |
| 7056 | { 3335, 5, 1, 4, 485, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3335 = VQSUBsv8i16 |
| 7057 | { 3334, 5, 1, 4, 485, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3334 = VQSUBsv4i32 |
| 7058 | { 3333, 5, 1, 4, 486, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3333 = VQSUBsv4i16 |
| 7059 | { 3332, 5, 1, 4, 485, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3332 = VQSUBsv2i64 |
| 7060 | { 3331, 5, 1, 4, 486, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3331 = VQSUBsv2i32 |
| 7061 | { 3330, 5, 1, 4, 486, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3330 = VQSUBsv1i64 |
| 7062 | { 3329, 5, 1, 4, 485, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3329 = VQSUBsv16i8 |
| 7063 | { 3328, 5, 1, 4, 503, 0, 0, 2366, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3328 = VQSHRUNv8i8 |
| 7064 | { 3327, 5, 1, 4, 503, 0, 0, 2366, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3327 = VQSHRUNv4i16 |
| 7065 | { 3326, 5, 1, 4, 503, 0, 0, 2366, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3326 = VQSHRUNv2i32 |
| 7066 | { 3325, 5, 1, 4, 794, 0, 0, 2366, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3325 = VQSHRNuv8i8 |
| 7067 | { 3324, 5, 1, 4, 794, 0, 0, 2366, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3324 = VQSHRNuv4i16 |
| 7068 | { 3323, 5, 1, 4, 794, 0, 0, 2366, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3323 = VQSHRNuv2i32 |
| 7069 | { 3322, 5, 1, 4, 794, 0, 0, 2366, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3322 = VQSHRNsv8i8 |
| 7070 | { 3321, 5, 1, 4, 794, 0, 0, 2366, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3321 = VQSHRNsv4i16 |
| 7071 | { 3320, 5, 1, 4, 794, 0, 0, 2366, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3320 = VQSHRNsv2i32 |
| 7072 | { 3319, 5, 1, 4, 471, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3319 = VQSHLuv8i8 |
| 7073 | { 3318, 5, 1, 4, 472, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3318 = VQSHLuv8i16 |
| 7074 | { 3317, 5, 1, 4, 472, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3317 = VQSHLuv4i32 |
| 7075 | { 3316, 5, 1, 4, 471, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3316 = VQSHLuv4i16 |
| 7076 | { 3315, 5, 1, 4, 472, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3315 = VQSHLuv2i64 |
| 7077 | { 3314, 5, 1, 4, 471, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3314 = VQSHLuv2i32 |
| 7078 | { 3313, 5, 1, 4, 471, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3313 = VQSHLuv1i64 |
| 7079 | { 3312, 5, 1, 4, 472, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3312 = VQSHLuv16i8 |
| 7080 | { 3311, 5, 1, 4, 987, 0, 0, 2376, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3311 = VQSHLuiv8i8 |
| 7081 | { 3310, 5, 1, 4, 987, 0, 0, 2371, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3310 = VQSHLuiv8i16 |
| 7082 | { 3309, 5, 1, 4, 987, 0, 0, 2371, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3309 = VQSHLuiv4i32 |
| 7083 | { 3308, 5, 1, 4, 987, 0, 0, 2376, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3308 = VQSHLuiv4i16 |
| 7084 | { 3307, 5, 1, 4, 987, 0, 0, 2371, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3307 = VQSHLuiv2i64 |
| 7085 | { 3306, 5, 1, 4, 987, 0, 0, 2376, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3306 = VQSHLuiv2i32 |
| 7086 | { 3305, 5, 1, 4, 987, 0, 0, 2376, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3305 = VQSHLuiv1i64 |
| 7087 | { 3304, 5, 1, 4, 987, 0, 0, 2371, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3304 = VQSHLuiv16i8 |
| 7088 | { 3303, 5, 1, 4, 471, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3303 = VQSHLsv8i8 |
| 7089 | { 3302, 5, 1, 4, 472, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3302 = VQSHLsv8i16 |
| 7090 | { 3301, 5, 1, 4, 472, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3301 = VQSHLsv4i32 |
| 7091 | { 3300, 5, 1, 4, 471, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3300 = VQSHLsv4i16 |
| 7092 | { 3299, 5, 1, 4, 472, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3299 = VQSHLsv2i64 |
| 7093 | { 3298, 5, 1, 4, 471, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3298 = VQSHLsv2i32 |
| 7094 | { 3297, 5, 1, 4, 471, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3297 = VQSHLsv1i64 |
| 7095 | { 3296, 5, 1, 4, 472, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3296 = VQSHLsv16i8 |
| 7096 | { 3295, 5, 1, 4, 987, 0, 0, 2376, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3295 = VQSHLsuv8i8 |
| 7097 | { 3294, 5, 1, 4, 987, 0, 0, 2371, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3294 = VQSHLsuv8i16 |
| 7098 | { 3293, 5, 1, 4, 987, 0, 0, 2371, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3293 = VQSHLsuv4i32 |
| 7099 | { 3292, 5, 1, 4, 987, 0, 0, 2376, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3292 = VQSHLsuv4i16 |
| 7100 | { 3291, 5, 1, 4, 987, 0, 0, 2371, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3291 = VQSHLsuv2i64 |
| 7101 | { 3290, 5, 1, 4, 987, 0, 0, 2376, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3290 = VQSHLsuv2i32 |
| 7102 | { 3289, 5, 1, 4, 987, 0, 0, 2376, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3289 = VQSHLsuv1i64 |
| 7103 | { 3288, 5, 1, 4, 987, 0, 0, 2371, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3288 = VQSHLsuv16i8 |
| 7104 | { 3287, 5, 1, 4, 987, 0, 0, 2376, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3287 = VQSHLsiv8i8 |
| 7105 | { 3286, 5, 1, 4, 987, 0, 0, 2371, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3286 = VQSHLsiv8i16 |
| 7106 | { 3285, 5, 1, 4, 987, 0, 0, 2371, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3285 = VQSHLsiv4i32 |
| 7107 | { 3284, 5, 1, 4, 987, 0, 0, 2376, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3284 = VQSHLsiv4i16 |
| 7108 | { 3283, 5, 1, 4, 987, 0, 0, 2371, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3283 = VQSHLsiv2i64 |
| 7109 | { 3282, 5, 1, 4, 987, 0, 0, 2376, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3282 = VQSHLsiv2i32 |
| 7110 | { 3281, 5, 1, 4, 987, 0, 0, 2376, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3281 = VQSHLsiv1i64 |
| 7111 | { 3280, 5, 1, 4, 987, 0, 0, 2371, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // Inst #3280 = VQSHLsiv16i8 |
| 7112 | { 3279, 5, 1, 4, 503, 0, 0, 2366, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3279 = VQRSHRUNv8i8 |
| 7113 | { 3278, 5, 1, 4, 503, 0, 0, 2366, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3278 = VQRSHRUNv4i16 |
| 7114 | { 3277, 5, 1, 4, 503, 0, 0, 2366, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3277 = VQRSHRUNv2i32 |
| 7115 | { 3276, 5, 1, 4, 503, 0, 0, 2366, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3276 = VQRSHRNuv8i8 |
| 7116 | { 3275, 5, 1, 4, 503, 0, 0, 2366, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3275 = VQRSHRNuv4i16 |
| 7117 | { 3274, 5, 1, 4, 503, 0, 0, 2366, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3274 = VQRSHRNuv2i32 |
| 7118 | { 3273, 5, 1, 4, 503, 0, 0, 2366, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3273 = VQRSHRNsv8i8 |
| 7119 | { 3272, 5, 1, 4, 503, 0, 0, 2366, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3272 = VQRSHRNsv4i16 |
| 7120 | { 3271, 5, 1, 4, 503, 0, 0, 2366, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // Inst #3271 = VQRSHRNsv2i32 |
| 7121 | { 3270, 5, 1, 4, 489, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3270 = VQRSHLuv8i8 |
| 7122 | { 3269, 5, 1, 4, 488, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3269 = VQRSHLuv8i16 |
| 7123 | { 3268, 5, 1, 4, 488, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3268 = VQRSHLuv4i32 |
| 7124 | { 3267, 5, 1, 4, 489, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3267 = VQRSHLuv4i16 |
| 7125 | { 3266, 5, 1, 4, 488, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3266 = VQRSHLuv2i64 |
| 7126 | { 3265, 5, 1, 4, 489, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3265 = VQRSHLuv2i32 |
| 7127 | { 3264, 5, 1, 4, 489, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3264 = VQRSHLuv1i64 |
| 7128 | { 3263, 5, 1, 4, 488, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3263 = VQRSHLuv16i8 |
| 7129 | { 3262, 5, 1, 4, 489, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3262 = VQRSHLsv8i8 |
| 7130 | { 3261, 5, 1, 4, 488, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3261 = VQRSHLsv8i16 |
| 7131 | { 3260, 5, 1, 4, 488, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3260 = VQRSHLsv4i32 |
| 7132 | { 3259, 5, 1, 4, 489, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3259 = VQRSHLsv4i16 |
| 7133 | { 3258, 5, 1, 4, 488, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3258 = VQRSHLsv2i64 |
| 7134 | { 3257, 5, 1, 4, 489, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3257 = VQRSHLsv2i32 |
| 7135 | { 3256, 5, 1, 4, 489, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3256 = VQRSHLsv1i64 |
| 7136 | { 3255, 5, 1, 4, 488, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // Inst #3255 = VQRSHLsv16i8 |
| 7137 | { 3254, 5, 1, 4, 793, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3254 = VQRDMULHv8i16 |
| 7138 | { 3253, 5, 1, 4, 792, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3253 = VQRDMULHv4i32 |
| 7139 | { 3252, 5, 1, 4, 977, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3252 = VQRDMULHv4i16 |
| 7140 | { 3251, 5, 1, 4, 976, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3251 = VQRDMULHv2i32 |
| 7141 | { 3250, 6, 1, 4, 793, 0, 0, 2355, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #3250 = VQRDMULHslv8i16 |
| 7142 | { 3249, 6, 1, 4, 792, 0, 0, 2343, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #3249 = VQRDMULHslv4i32 |
| 7143 | { 3248, 6, 1, 4, 977, 0, 0, 2349, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #3248 = VQRDMULHslv4i16 |
| 7144 | { 3247, 6, 1, 4, 976, 0, 0, 2337, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #3247 = VQRDMULHslv2i32 |
| 7145 | { 3246, 6, 1, 4, 984, 0, 0, 1656, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3246 = VQRDMLSHv8i16 |
| 7146 | { 3245, 6, 1, 4, 983, 0, 0, 1656, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3245 = VQRDMLSHv4i32 |
| 7147 | { 3244, 6, 1, 4, 982, 0, 0, 1662, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3244 = VQRDMLSHv4i16 |
| 7148 | { 3243, 6, 1, 4, 981, 0, 0, 1662, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3243 = VQRDMLSHv2i32 |
| 7149 | { 3242, 7, 1, 4, 984, 0, 0, 2260, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11400ULL }, // Inst #3242 = VQRDMLSHslv8i16 |
| 7150 | { 3241, 7, 1, 4, 983, 0, 0, 2246, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11400ULL }, // Inst #3241 = VQRDMLSHslv4i32 |
| 7151 | { 3240, 7, 1, 4, 982, 0, 0, 2253, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #3240 = VQRDMLSHslv4i16 |
| 7152 | { 3239, 7, 1, 4, 981, 0, 0, 2239, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #3239 = VQRDMLSHslv2i32 |
| 7153 | { 3238, 6, 1, 4, 984, 0, 0, 1656, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3238 = VQRDMLAHv8i16 |
| 7154 | { 3237, 6, 1, 4, 983, 0, 0, 1656, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3237 = VQRDMLAHv4i32 |
| 7155 | { 3236, 6, 1, 4, 982, 0, 0, 1662, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3236 = VQRDMLAHv4i16 |
| 7156 | { 3235, 6, 1, 4, 981, 0, 0, 1662, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3235 = VQRDMLAHv2i32 |
| 7157 | { 3234, 7, 1, 4, 984, 0, 0, 2260, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11400ULL }, // Inst #3234 = VQRDMLAHslv8i16 |
| 7158 | { 3233, 7, 1, 4, 983, 0, 0, 2246, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11400ULL }, // Inst #3233 = VQRDMLAHslv4i32 |
| 7159 | { 3232, 7, 1, 4, 982, 0, 0, 2253, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #3232 = VQRDMLAHslv4i16 |
| 7160 | { 3231, 7, 1, 4, 981, 0, 0, 2239, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #3231 = VQRDMLAHslv2i32 |
| 7161 | { 3230, 4, 1, 4, 495, 0, 0, 1683, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3230 = VQNEGv8i8 |
| 7162 | { 3229, 4, 1, 4, 494, 0, 0, 1695, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3229 = VQNEGv8i16 |
| 7163 | { 3228, 4, 1, 4, 494, 0, 0, 1695, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3228 = VQNEGv4i32 |
| 7164 | { 3227, 4, 1, 4, 495, 0, 0, 1683, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3227 = VQNEGv4i16 |
| 7165 | { 3226, 4, 1, 4, 495, 0, 0, 1683, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3226 = VQNEGv2i32 |
| 7166 | { 3225, 4, 1, 4, 494, 0, 0, 1695, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3225 = VQNEGv16i8 |
| 7167 | { 3224, 4, 1, 4, 573, 0, 0, 645, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3224 = VQMOVNuv8i8 |
| 7168 | { 3223, 4, 1, 4, 573, 0, 0, 645, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3223 = VQMOVNuv4i16 |
| 7169 | { 3222, 4, 1, 4, 573, 0, 0, 645, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3222 = VQMOVNuv2i32 |
| 7170 | { 3221, 4, 1, 4, 573, 0, 0, 645, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3221 = VQMOVNsv8i8 |
| 7171 | { 3220, 4, 1, 4, 573, 0, 0, 645, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3220 = VQMOVNsv4i16 |
| 7172 | { 3219, 4, 1, 4, 573, 0, 0, 645, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3219 = VQMOVNsv2i32 |
| 7173 | { 3218, 4, 1, 4, 573, 0, 0, 645, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3218 = VQMOVNsuv8i8 |
| 7174 | { 3217, 4, 1, 4, 573, 0, 0, 645, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3217 = VQMOVNsuv4i16 |
| 7175 | { 3216, 4, 1, 4, 573, 0, 0, 645, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3216 = VQMOVNsuv2i32 |
| 7176 | { 3215, 5, 1, 4, 791, 0, 0, 1668, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3215 = VQDMULLv4i32 |
| 7177 | { 3214, 5, 1, 4, 790, 0, 0, 1668, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3214 = VQDMULLv2i64 |
| 7178 | { 3213, 6, 1, 4, 791, 0, 0, 2331, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #3213 = VQDMULLslv4i16 |
| 7179 | { 3212, 6, 1, 4, 791, 0, 0, 2325, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #3212 = VQDMULLslv2i32 |
| 7180 | { 3211, 5, 1, 4, 793, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3211 = VQDMULHv8i16 |
| 7181 | { 3210, 5, 1, 4, 792, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3210 = VQDMULHv4i32 |
| 7182 | { 3209, 5, 1, 4, 977, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3209 = VQDMULHv4i16 |
| 7183 | { 3208, 5, 1, 4, 976, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3208 = VQDMULHv2i32 |
| 7184 | { 3207, 6, 1, 4, 793, 0, 0, 2355, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #3207 = VQDMULHslv8i16 |
| 7185 | { 3206, 6, 1, 4, 792, 0, 0, 2343, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #3206 = VQDMULHslv4i32 |
| 7186 | { 3205, 6, 1, 4, 977, 0, 0, 2349, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #3205 = VQDMULHslv4i16 |
| 7187 | { 3204, 6, 1, 4, 976, 0, 0, 2337, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #3204 = VQDMULHslv2i32 |
| 7188 | { 3203, 6, 1, 4, 789, 0, 0, 1650, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3203 = VQDMLSLv4i32 |
| 7189 | { 3202, 6, 1, 4, 788, 0, 0, 1650, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3202 = VQDMLSLv2i64 |
| 7190 | { 3201, 7, 1, 4, 789, 0, 0, 2232, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #3201 = VQDMLSLslv4i16 |
| 7191 | { 3200, 7, 1, 4, 788, 0, 0, 2225, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #3200 = VQDMLSLslv2i32 |
| 7192 | { 3199, 6, 1, 4, 789, 0, 0, 1650, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3199 = VQDMLALv4i32 |
| 7193 | { 3198, 6, 1, 4, 788, 0, 0, 1650, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3198 = VQDMLALv2i64 |
| 7194 | { 3197, 7, 1, 4, 789, 0, 0, 2232, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #3197 = VQDMLALslv4i16 |
| 7195 | { 3196, 7, 1, 4, 788, 0, 0, 2225, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #3196 = VQDMLALslv2i32 |
| 7196 | { 3195, 5, 1, 4, 497, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3195 = VQADDuv8i8 |
| 7197 | { 3194, 5, 1, 4, 496, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3194 = VQADDuv8i16 |
| 7198 | { 3193, 5, 1, 4, 496, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3193 = VQADDuv4i32 |
| 7199 | { 3192, 5, 1, 4, 497, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3192 = VQADDuv4i16 |
| 7200 | { 3191, 5, 1, 4, 496, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3191 = VQADDuv2i64 |
| 7201 | { 3190, 5, 1, 4, 497, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3190 = VQADDuv2i32 |
| 7202 | { 3189, 5, 1, 4, 497, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3189 = VQADDuv1i64 |
| 7203 | { 3188, 5, 1, 4, 496, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3188 = VQADDuv16i8 |
| 7204 | { 3187, 5, 1, 4, 497, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3187 = VQADDsv8i8 |
| 7205 | { 3186, 5, 1, 4, 496, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3186 = VQADDsv8i16 |
| 7206 | { 3185, 5, 1, 4, 496, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3185 = VQADDsv4i32 |
| 7207 | { 3184, 5, 1, 4, 497, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3184 = VQADDsv4i16 |
| 7208 | { 3183, 5, 1, 4, 496, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3183 = VQADDsv2i64 |
| 7209 | { 3182, 5, 1, 4, 497, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3182 = VQADDsv2i32 |
| 7210 | { 3181, 5, 1, 4, 497, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3181 = VQADDsv1i64 |
| 7211 | { 3180, 5, 1, 4, 496, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3180 = VQADDsv16i8 |
| 7212 | { 3179, 4, 1, 4, 786, 0, 0, 1683, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3179 = VQABSv8i8 |
| 7213 | { 3178, 4, 1, 4, 787, 0, 0, 1695, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3178 = VQABSv8i16 |
| 7214 | { 3177, 4, 1, 4, 787, 0, 0, 1695, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3177 = VQABSv4i32 |
| 7215 | { 3176, 4, 1, 4, 786, 0, 0, 1683, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3176 = VQABSv4i16 |
| 7216 | { 3175, 4, 1, 4, 786, 0, 0, 1683, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3175 = VQABSv2i32 |
| 7217 | { 3174, 4, 1, 4, 787, 0, 0, 1695, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3174 = VQABSv16i8 |
| 7218 | { 3173, 5, 1, 4, 524, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3173 = VPMINu8 |
| 7219 | { 3172, 5, 1, 4, 524, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3172 = VPMINu32 |
| 7220 | { 3171, 5, 1, 4, 524, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3171 = VPMINu16 |
| 7221 | { 3170, 5, 1, 4, 524, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3170 = VPMINs8 |
| 7222 | { 3169, 5, 1, 4, 524, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3169 = VPMINs32 |
| 7223 | { 3168, 5, 1, 4, 524, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3168 = VPMINs16 |
| 7224 | { 3167, 5, 1, 4, 777, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3167 = VPMINh |
| 7225 | { 3166, 5, 1, 4, 777, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3166 = VPMINf |
| 7226 | { 3165, 5, 1, 4, 524, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3165 = VPMAXu8 |
| 7227 | { 3164, 5, 1, 4, 524, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3164 = VPMAXu32 |
| 7228 | { 3163, 5, 1, 4, 524, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3163 = VPMAXu16 |
| 7229 | { 3162, 5, 1, 4, 524, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3162 = VPMAXs8 |
| 7230 | { 3161, 5, 1, 4, 524, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3161 = VPMAXs32 |
| 7231 | { 3160, 5, 1, 4, 524, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3160 = VPMAXs16 |
| 7232 | { 3159, 5, 1, 4, 777, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3159 = VPMAXh |
| 7233 | { 3158, 5, 1, 4, 777, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3158 = VPMAXf |
| 7234 | { 3157, 5, 1, 4, 783, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3157 = VPADDi8 |
| 7235 | { 3156, 5, 1, 4, 783, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3156 = VPADDi32 |
| 7236 | { 3155, 5, 1, 4, 783, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3155 = VPADDi16 |
| 7237 | { 3154, 5, 1, 4, 991, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3154 = VPADDh |
| 7238 | { 3153, 5, 1, 4, 525, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3153 = VPADDf |
| 7239 | { 3152, 4, 1, 4, 785, 0, 0, 1683, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3152 = VPADDLuv8i8 |
| 7240 | { 3151, 4, 1, 4, 785, 0, 0, 1695, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3151 = VPADDLuv8i16 |
| 7241 | { 3150, 4, 1, 4, 785, 0, 0, 1695, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3150 = VPADDLuv4i32 |
| 7242 | { 3149, 4, 1, 4, 785, 0, 0, 1683, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3149 = VPADDLuv4i16 |
| 7243 | { 3148, 4, 1, 4, 785, 0, 0, 1683, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3148 = VPADDLuv2i32 |
| 7244 | { 3147, 4, 1, 4, 785, 0, 0, 1695, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3147 = VPADDLuv16i8 |
| 7245 | { 3146, 4, 1, 4, 785, 0, 0, 1683, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3146 = VPADDLsv8i8 |
| 7246 | { 3145, 4, 1, 4, 785, 0, 0, 1695, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3145 = VPADDLsv8i16 |
| 7247 | { 3144, 4, 1, 4, 785, 0, 0, 1695, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3144 = VPADDLsv4i32 |
| 7248 | { 3143, 4, 1, 4, 785, 0, 0, 1683, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3143 = VPADDLsv4i16 |
| 7249 | { 3142, 4, 1, 4, 785, 0, 0, 1683, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3142 = VPADDLsv2i32 |
| 7250 | { 3141, 4, 1, 4, 785, 0, 0, 1695, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3141 = VPADDLsv16i8 |
| 7251 | { 3140, 5, 1, 4, 784, 0, 0, 397, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3140 = VPADALuv8i8 |
| 7252 | { 3139, 5, 1, 4, 481, 0, 0, 2361, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3139 = VPADALuv8i16 |
| 7253 | { 3138, 5, 1, 4, 481, 0, 0, 2361, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3138 = VPADALuv4i32 |
| 7254 | { 3137, 5, 1, 4, 784, 0, 0, 397, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3137 = VPADALuv4i16 |
| 7255 | { 3136, 5, 1, 4, 784, 0, 0, 397, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3136 = VPADALuv2i32 |
| 7256 | { 3135, 5, 1, 4, 481, 0, 0, 2361, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3135 = VPADALuv16i8 |
| 7257 | { 3134, 5, 1, 4, 784, 0, 0, 397, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3134 = VPADALsv8i8 |
| 7258 | { 3133, 5, 1, 4, 481, 0, 0, 2361, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3133 = VPADALsv8i16 |
| 7259 | { 3132, 5, 1, 4, 481, 0, 0, 2361, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3132 = VPADALsv4i32 |
| 7260 | { 3131, 5, 1, 4, 784, 0, 0, 397, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3131 = VPADALsv4i16 |
| 7261 | { 3130, 5, 1, 4, 784, 0, 0, 397, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3130 = VPADALsv2i32 |
| 7262 | { 3129, 5, 1, 4, 481, 0, 0, 2361, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3129 = VPADALsv16i8 |
| 7263 | { 3128, 5, 1, 4, 458, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3128 = VORRq |
| 7264 | { 3127, 5, 1, 4, 470, 0, 0, 1729, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x10f80ULL }, // Inst #3127 = VORRiv8i16 |
| 7265 | { 3126, 5, 1, 4, 470, 0, 0, 1729, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x10f80ULL }, // Inst #3126 = VORRiv4i32 |
| 7266 | { 3125, 5, 1, 4, 470, 0, 0, 1724, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x10f80ULL }, // Inst #3125 = VORRiv4i16 |
| 7267 | { 3124, 5, 1, 4, 470, 0, 0, 1724, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x10f80ULL }, // Inst #3124 = VORRiv2i32 |
| 7268 | { 3123, 5, 1, 4, 459, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3123 = VORRd |
| 7269 | { 3122, 5, 1, 4, 458, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3122 = VORNq |
| 7270 | { 3121, 5, 1, 4, 459, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3121 = VORNd |
| 7271 | { 3120, 5, 1, 4, 529, 0, 0, 1709, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x28800ULL }, // Inst #3120 = VNMULS |
| 7272 | { 3119, 5, 1, 4, 202, 0, 0, 1699, ARMImpOpBase + 0, 0, 0x8800ULL }, // Inst #3119 = VNMULH |
| 7273 | { 3118, 5, 1, 4, 1260, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x8800ULL }, // Inst #3118 = VNMULD |
| 7274 | { 3117, 6, 1, 4, 543, 0, 0, 1877, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x28800ULL }, // Inst #3117 = VNMLSS |
| 7275 | { 3116, 6, 1, 4, 540, 0, 0, 1857, ARMImpOpBase + 0, 0, 0x8800ULL }, // Inst #3116 = VNMLSH |
| 7276 | { 3115, 6, 1, 4, 539, 0, 0, 1662, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x8800ULL }, // Inst #3115 = VNMLSD |
| 7277 | { 3114, 6, 1, 4, 543, 0, 0, 1877, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x28800ULL }, // Inst #3114 = VNMLAS |
| 7278 | { 3113, 6, 1, 4, 540, 0, 0, 1857, ARMImpOpBase + 0, 0, 0x8800ULL }, // Inst #3113 = VNMLAH |
| 7279 | { 3112, 6, 1, 4, 539, 0, 0, 1662, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x8800ULL }, // Inst #3112 = VNMLAD |
| 7280 | { 3111, 4, 1, 4, 782, 0, 0, 1695, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3111 = VNEGs8q |
| 7281 | { 3110, 4, 1, 4, 781, 0, 0, 1683, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3110 = VNEGs8d |
| 7282 | { 3109, 4, 1, 4, 782, 0, 0, 1695, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3109 = VNEGs32q |
| 7283 | { 3108, 4, 1, 4, 781, 0, 0, 1683, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3108 = VNEGs32d |
| 7284 | { 3107, 4, 1, 4, 782, 0, 0, 1695, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3107 = VNEGs16q |
| 7285 | { 3106, 4, 1, 4, 781, 0, 0, 1683, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3106 = VNEGs16d |
| 7286 | { 3105, 4, 1, 4, 780, 0, 0, 1695, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3105 = VNEGhq |
| 7287 | { 3104, 4, 1, 4, 779, 0, 0, 1683, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3104 = VNEGhd |
| 7288 | { 3103, 4, 1, 4, 463, 0, 0, 1683, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3103 = VNEGfd |
| 7289 | { 3102, 4, 1, 4, 462, 0, 0, 1695, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3102 = VNEGf32q |
| 7290 | { 3101, 4, 1, 4, 517, 0, 0, 1691, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x28780ULL }, // Inst #3101 = VNEGS |
| 7291 | { 3100, 4, 1, 4, 778, 0, 0, 1687, ARMImpOpBase + 0, 0, 0x8780ULL }, // Inst #3100 = VNEGH |
| 7292 | { 3099, 4, 1, 4, 516, 0, 0, 1683, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x8780ULL }, // Inst #3099 = VNEGD |
| 7293 | { 3098, 4, 1, 4, 973, 0, 0, 2305, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0x10f80ULL }, // Inst #3098 = VMVNv8i16 |
| 7294 | { 3097, 4, 1, 4, 973, 0, 0, 2305, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0x10f80ULL }, // Inst #3097 = VMVNv4i32 |
| 7295 | { 3096, 4, 1, 4, 973, 0, 0, 861, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0x10f80ULL }, // Inst #3096 = VMVNv4i16 |
| 7296 | { 3095, 4, 1, 4, 973, 0, 0, 861, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0x10f80ULL }, // Inst #3095 = VMVNv2i32 |
| 7297 | { 3094, 4, 1, 4, 570, 0, 0, 1695, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3094 = VMVNq |
| 7298 | { 3093, 4, 1, 4, 570, 0, 0, 1683, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3093 = VMVNd |
| 7299 | { 3092, 5, 1, 4, 974, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3092 = VMULv8i8 |
| 7300 | { 3091, 5, 1, 4, 978, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3091 = VMULv8i16 |
| 7301 | { 3090, 5, 1, 4, 537, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3090 = VMULv4i32 |
| 7302 | { 3089, 5, 1, 4, 974, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3089 = VMULv4i16 |
| 7303 | { 3088, 5, 1, 4, 975, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3088 = VMULv2i32 |
| 7304 | { 3087, 5, 1, 4, 978, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3087 = VMULv16i8 |
| 7305 | { 3086, 6, 1, 4, 978, 0, 0, 2355, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #3086 = VMULslv8i16 |
| 7306 | { 3085, 6, 1, 4, 537, 0, 0, 2343, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #3085 = VMULslv4i32 |
| 7307 | { 3084, 6, 1, 4, 974, 0, 0, 2349, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #3084 = VMULslv4i16 |
| 7308 | { 3083, 6, 1, 4, 975, 0, 0, 2337, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #3083 = VMULslv2i32 |
| 7309 | { 3082, 6, 1, 4, 533, 0, 0, 2355, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #3082 = VMULslhq |
| 7310 | { 3081, 6, 1, 4, 532, 0, 0, 2349, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #3081 = VMULslhd |
| 7311 | { 3080, 6, 1, 4, 535, 0, 0, 2343, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #3080 = VMULslfq |
| 7312 | { 3079, 6, 1, 4, 534, 0, 0, 2337, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #3079 = VMULslfd |
| 7313 | { 3078, 5, 1, 4, 978, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3078 = VMULpq |
| 7314 | { 3077, 5, 1, 4, 974, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3077 = VMULpd |
| 7315 | { 3076, 5, 1, 4, 998, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3076 = VMULhq |
| 7316 | { 3075, 5, 1, 4, 997, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3075 = VMULhd |
| 7317 | { 3074, 5, 1, 4, 531, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3074 = VMULfq |
| 7318 | { 3073, 5, 1, 4, 530, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3073 = VMULfd |
| 7319 | { 3072, 5, 1, 4, 529, 0, 0, 1709, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x28800ULL }, // Inst #3072 = VMULS |
| 7320 | { 3071, 5, 1, 4, 985, 0, 0, 1668, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3071 = VMULLuv8i16 |
| 7321 | { 3070, 5, 1, 4, 985, 0, 0, 1668, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3070 = VMULLuv4i32 |
| 7322 | { 3069, 5, 1, 4, 536, 0, 0, 1668, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3069 = VMULLuv2i64 |
| 7323 | { 3068, 5, 1, 4, 985, 0, 0, 1668, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3068 = VMULLsv8i16 |
| 7324 | { 3067, 5, 1, 4, 985, 0, 0, 1668, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3067 = VMULLsv4i32 |
| 7325 | { 3066, 5, 1, 4, 536, 0, 0, 1668, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3066 = VMULLsv2i64 |
| 7326 | { 3065, 6, 1, 4, 985, 0, 0, 2331, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #3065 = VMULLsluv4i16 |
| 7327 | { 3064, 6, 1, 4, 985, 0, 0, 2325, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #3064 = VMULLsluv2i32 |
| 7328 | { 3063, 6, 1, 4, 985, 0, 0, 2331, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #3063 = VMULLslsv4i16 |
| 7329 | { 3062, 6, 1, 4, 985, 0, 0, 2325, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #3062 = VMULLslsv2i32 |
| 7330 | { 3061, 5, 1, 4, 985, 0, 0, 1668, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3061 = VMULLp8 |
| 7331 | { 3060, 3, 1, 4, 538, 0, 0, 1870, ARMImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #3060 = VMULLp64 |
| 7332 | { 3059, 5, 1, 4, 202, 0, 0, 1699, ARMImpOpBase + 0, 0, 0x8800ULL }, // Inst #3059 = VMULH |
| 7333 | { 3058, 5, 1, 4, 1260, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x8800ULL }, // Inst #3058 = VMULD |
| 7334 | { 3057, 3, 0, 4, 1290, 0, 1, 535, ARMImpOpBase + 69, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL }, // Inst #3057 = VMSR_VPR |
| 7335 | { 3056, 4, 1, 4, 1290, 0, 0, 2321, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL }, // Inst #3056 = VMSR_P0 |
| 7336 | { 3055, 3, 0, 4, 586, 0, 1, 1059, ARMImpOpBase + 71, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL }, // Inst #3055 = VMSR_FPSID |
| 7337 | { 3054, 4, 1, 4, 1290, 0, 0, 2317, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL }, // Inst #3054 = VMSR_FPSCR_NZCVQC |
| 7338 | { 3053, 3, 0, 4, 586, 0, 1, 1059, ARMImpOpBase + 71, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL }, // Inst #3053 = VMSR_FPINST2 |
| 7339 | { 3052, 3, 0, 4, 586, 0, 1, 1059, ARMImpOpBase + 71, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL }, // Inst #3052 = VMSR_FPINST |
| 7340 | { 3051, 3, 0, 4, 586, 0, 1, 1059, ARMImpOpBase + 71, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL }, // Inst #3051 = VMSR_FPEXC |
| 7341 | { 3050, 3, 0, 4, 586, 0, 0, 535, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL }, // Inst #3050 = VMSR_FPCXTS |
| 7342 | { 3049, 3, 0, 4, 586, 0, 0, 535, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL }, // Inst #3049 = VMSR_FPCXTNS |
| 7343 | { 3048, 3, 0, 4, 1290, 0, 1, 1059, ARMImpOpBase + 71, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL }, // Inst #3048 = VMSR |
| 7344 | { 3047, 3, 1, 4, 1291, 1, 0, 535, ARMImpOpBase + 69, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL }, // Inst #3047 = VMRS_VPR |
| 7345 | { 3046, 4, 1, 4, 1291, 0, 0, 2313, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL }, // Inst #3046 = VMRS_P0 |
| 7346 | { 3045, 3, 1, 4, 585, 1, 0, 1059, ARMImpOpBase + 71, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL }, // Inst #3045 = VMRS_MVFR2 |
| 7347 | { 3044, 3, 1, 4, 585, 1, 0, 1059, ARMImpOpBase + 71, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL }, // Inst #3044 = VMRS_MVFR1 |
| 7348 | { 3043, 3, 1, 4, 585, 1, 0, 1059, ARMImpOpBase + 71, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL }, // Inst #3043 = VMRS_MVFR0 |
| 7349 | { 3042, 3, 1, 4, 585, 1, 0, 1059, ARMImpOpBase + 71, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL }, // Inst #3042 = VMRS_FPSID |
| 7350 | { 3041, 4, 1, 4, 1292, 1, 0, 2309, ARMImpOpBase + 71, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL }, // Inst #3041 = VMRS_FPSCR_NZCVQC |
| 7351 | { 3040, 3, 1, 4, 585, 1, 0, 1059, ARMImpOpBase + 71, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL }, // Inst #3040 = VMRS_FPINST2 |
| 7352 | { 3039, 3, 1, 4, 585, 1, 0, 1059, ARMImpOpBase + 71, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL }, // Inst #3039 = VMRS_FPINST |
| 7353 | { 3038, 3, 1, 4, 585, 1, 0, 1059, ARMImpOpBase + 71, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL }, // Inst #3038 = VMRS_FPEXC |
| 7354 | { 3037, 3, 1, 4, 585, 0, 0, 535, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL }, // Inst #3037 = VMRS_FPCXTS |
| 7355 | { 3036, 3, 1, 4, 585, 0, 0, 535, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL }, // Inst #3036 = VMRS_FPCXTNS |
| 7356 | { 3035, 3, 1, 4, 1293, 1, 0, 1059, ARMImpOpBase + 71, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL }, // Inst #3035 = VMRS |
| 7357 | { 3034, 4, 1, 4, 567, 0, 0, 861, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x10f80ULL }, // Inst #3034 = VMOVv8i8 |
| 7358 | { 3033, 4, 1, 4, 567, 0, 0, 2305, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x10f80ULL }, // Inst #3033 = VMOVv8i16 |
| 7359 | { 3032, 4, 1, 4, 567, 0, 0, 2305, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x10f80ULL }, // Inst #3032 = VMOVv4i32 |
| 7360 | { 3031, 4, 1, 4, 567, 0, 0, 861, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x10f80ULL }, // Inst #3031 = VMOVv4i16 |
| 7361 | { 3030, 4, 1, 4, 567, 0, 0, 2305, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x10f80ULL }, // Inst #3030 = VMOVv4f32 |
| 7362 | { 3029, 4, 1, 4, 567, 0, 0, 2305, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x10f80ULL }, // Inst #3029 = VMOVv2i64 |
| 7363 | { 3028, 4, 1, 4, 567, 0, 0, 861, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x10f80ULL }, // Inst #3028 = VMOVv2i32 |
| 7364 | { 3027, 4, 1, 4, 567, 0, 0, 861, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x10f80ULL }, // Inst #3027 = VMOVv2f32 |
| 7365 | { 3026, 4, 1, 4, 567, 0, 0, 861, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x10f80ULL }, // Inst #3026 = VMOVv1i64 |
| 7366 | { 3025, 4, 1, 4, 567, 0, 0, 2305, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x10f80ULL }, // Inst #3025 = VMOVv16i8 |
| 7367 | { 3024, 6, 2, 4, 582, 0, 0, 2299, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x18a80ULL }, // Inst #3024 = VMOVSRR |
| 7368 | { 3023, 4, 1, 4, 578, 0, 0, 2295, ARMImpOpBase + 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Bitcast)|(1ULL<<MCID::Predicable), 0x18a00ULL }, // Inst #3023 = VMOVSR |
| 7369 | { 3022, 4, 1, 4, 1214, 0, 0, 1691, ARMImpOpBase + 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Predicable), 0x8780ULL }, // Inst #3022 = VMOVS |
| 7370 | { 3021, 4, 1, 4, 577, 0, 0, 2291, ARMImpOpBase + 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Bitcast)|(1ULL<<MCID::Predicable), 0x18900ULL }, // Inst #3021 = VMOVRS |
| 7371 | { 3020, 6, 2, 4, 580, 0, 0, 2285, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x18980ULL }, // Inst #3020 = VMOVRRS |
| 7372 | { 3019, 5, 2, 4, 580, 0, 0, 2280, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtractSubreg), 0x18980ULL }, // Inst #3019 = VMOVRRD |
| 7373 | { 3018, 4, 1, 4, 1215, 0, 0, 2276, ARMImpOpBase + 0, 0, 0x8900ULL }, // Inst #3018 = VMOVRH |
| 7374 | { 3017, 4, 1, 4, 571, 0, 0, 645, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3017 = VMOVNv8i8 |
| 7375 | { 3016, 4, 1, 4, 571, 0, 0, 645, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3016 = VMOVNv4i16 |
| 7376 | { 3015, 4, 1, 4, 571, 0, 0, 645, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3015 = VMOVNv2i32 |
| 7377 | { 3014, 4, 1, 4, 572, 0, 0, 1828, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3014 = VMOVLuv8i16 |
| 7378 | { 3013, 4, 1, 4, 572, 0, 0, 1828, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3013 = VMOVLuv4i32 |
| 7379 | { 3012, 4, 1, 4, 572, 0, 0, 1828, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3012 = VMOVLuv2i64 |
| 7380 | { 3011, 4, 1, 4, 572, 0, 0, 1828, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3011 = VMOVLsv8i16 |
| 7381 | { 3010, 4, 1, 4, 572, 0, 0, 1828, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3010 = VMOVLsv4i32 |
| 7382 | { 3009, 4, 1, 4, 572, 0, 0, 1828, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #3009 = VMOVLsv2i64 |
| 7383 | { 3008, 4, 1, 4, 1212, 0, 0, 2272, ARMImpOpBase + 0, 0, 0x8a00ULL }, // Inst #3008 = VMOVHR |
| 7384 | { 3007, 2, 1, 4, 1211, 0, 0, 1803, ARMImpOpBase + 0, 0, 0x8780ULL }, // Inst #3007 = VMOVH |
| 7385 | { 3006, 5, 1, 4, 581, 0, 0, 2267, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::RegSequence), 0x18a80ULL }, // Inst #3006 = VMOVDRR |
| 7386 | { 3005, 4, 1, 4, 1213, 0, 0, 1683, ARMImpOpBase + 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Predicable), 0x8780ULL }, // Inst #3005 = VMOVD |
| 7387 | { 3004, 4, 1, 4, 50, 0, 0, 641, ARMImpOpBase + 0, 0, 0x11280ULL }, // Inst #3004 = VMMLA |
| 7388 | { 3003, 6, 1, 4, 980, 0, 0, 1662, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3003 = VMLSv8i8 |
| 7389 | { 3002, 6, 1, 4, 547, 0, 0, 1656, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3002 = VMLSv8i16 |
| 7390 | { 3001, 6, 1, 4, 546, 0, 0, 1656, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3001 = VMLSv4i32 |
| 7391 | { 3000, 6, 1, 4, 980, 0, 0, 1662, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #3000 = VMLSv4i16 |
| 7392 | { 2999, 6, 1, 4, 979, 0, 0, 1662, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2999 = VMLSv2i32 |
| 7393 | { 2998, 6, 1, 4, 547, 0, 0, 1656, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2998 = VMLSv16i8 |
| 7394 | { 2997, 7, 1, 4, 547, 0, 0, 2260, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #2997 = VMLSslv8i16 |
| 7395 | { 2996, 7, 1, 4, 546, 0, 0, 2246, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #2996 = VMLSslv4i32 |
| 7396 | { 2995, 7, 1, 4, 980, 0, 0, 2253, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #2995 = VMLSslv4i16 |
| 7397 | { 2994, 7, 1, 4, 979, 0, 0, 2239, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #2994 = VMLSslv2i32 |
| 7398 | { 2993, 7, 1, 4, 545, 0, 0, 2260, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #2993 = VMLSslhq |
| 7399 | { 2992, 7, 1, 4, 544, 0, 0, 2253, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #2992 = VMLSslhd |
| 7400 | { 2991, 7, 1, 4, 545, 0, 0, 2246, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #2991 = VMLSslfq |
| 7401 | { 2990, 7, 1, 4, 544, 0, 0, 2239, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #2990 = VMLSslfd |
| 7402 | { 2989, 6, 1, 4, 545, 0, 0, 1656, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2989 = VMLShq |
| 7403 | { 2988, 6, 1, 4, 544, 0, 0, 1662, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2988 = VMLShd |
| 7404 | { 2987, 6, 1, 4, 545, 0, 0, 1656, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2987 = VMLSfq |
| 7405 | { 2986, 6, 1, 4, 544, 0, 0, 1662, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2986 = VMLSfd |
| 7406 | { 2985, 6, 1, 4, 543, 0, 0, 1877, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x28800ULL }, // Inst #2985 = VMLSS |
| 7407 | { 2984, 6, 1, 4, 542, 0, 0, 1650, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2984 = VMLSLuv8i16 |
| 7408 | { 2983, 6, 1, 4, 542, 0, 0, 1650, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2983 = VMLSLuv4i32 |
| 7409 | { 2982, 6, 1, 4, 541, 0, 0, 1650, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2982 = VMLSLuv2i64 |
| 7410 | { 2981, 6, 1, 4, 542, 0, 0, 1650, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2981 = VMLSLsv8i16 |
| 7411 | { 2980, 6, 1, 4, 542, 0, 0, 1650, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2980 = VMLSLsv4i32 |
| 7412 | { 2979, 6, 1, 4, 541, 0, 0, 1650, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2979 = VMLSLsv2i64 |
| 7413 | { 2978, 7, 1, 4, 542, 0, 0, 2232, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #2978 = VMLSLsluv4i16 |
| 7414 | { 2977, 7, 1, 4, 541, 0, 0, 2225, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #2977 = VMLSLsluv2i32 |
| 7415 | { 2976, 7, 1, 4, 542, 0, 0, 2232, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #2976 = VMLSLslsv4i16 |
| 7416 | { 2975, 7, 1, 4, 541, 0, 0, 2225, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #2975 = VMLSLslsv2i32 |
| 7417 | { 2974, 6, 1, 4, 540, 0, 0, 1857, ARMImpOpBase + 0, 0, 0x8800ULL }, // Inst #2974 = VMLSH |
| 7418 | { 2973, 6, 1, 4, 539, 0, 0, 1662, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x8800ULL }, // Inst #2973 = VMLSD |
| 7419 | { 2972, 6, 1, 4, 980, 0, 0, 1662, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2972 = VMLAv8i8 |
| 7420 | { 2971, 6, 1, 4, 547, 0, 0, 1656, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2971 = VMLAv8i16 |
| 7421 | { 2970, 6, 1, 4, 546, 0, 0, 1656, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2970 = VMLAv4i32 |
| 7422 | { 2969, 6, 1, 4, 980, 0, 0, 1662, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2969 = VMLAv4i16 |
| 7423 | { 2968, 6, 1, 4, 979, 0, 0, 1662, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2968 = VMLAv2i32 |
| 7424 | { 2967, 6, 1, 4, 547, 0, 0, 1656, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2967 = VMLAv16i8 |
| 7425 | { 2966, 7, 1, 4, 547, 0, 0, 2260, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #2966 = VMLAslv8i16 |
| 7426 | { 2965, 7, 1, 4, 546, 0, 0, 2246, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #2965 = VMLAslv4i32 |
| 7427 | { 2964, 7, 1, 4, 980, 0, 0, 2253, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #2964 = VMLAslv4i16 |
| 7428 | { 2963, 7, 1, 4, 979, 0, 0, 2239, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #2963 = VMLAslv2i32 |
| 7429 | { 2962, 7, 1, 4, 545, 0, 0, 2260, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #2962 = VMLAslhq |
| 7430 | { 2961, 7, 1, 4, 544, 0, 0, 2253, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #2961 = VMLAslhd |
| 7431 | { 2960, 7, 1, 4, 545, 0, 0, 2246, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #2960 = VMLAslfq |
| 7432 | { 2959, 7, 1, 4, 544, 0, 0, 2239, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #2959 = VMLAslfd |
| 7433 | { 2958, 6, 1, 4, 545, 0, 0, 1656, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2958 = VMLAhq |
| 7434 | { 2957, 6, 1, 4, 544, 0, 0, 1662, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2957 = VMLAhd |
| 7435 | { 2956, 6, 1, 4, 545, 0, 0, 1656, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2956 = VMLAfq |
| 7436 | { 2955, 6, 1, 4, 544, 0, 0, 1662, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2955 = VMLAfd |
| 7437 | { 2954, 6, 1, 4, 543, 0, 0, 1877, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x28800ULL }, // Inst #2954 = VMLAS |
| 7438 | { 2953, 6, 1, 4, 542, 0, 0, 1650, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2953 = VMLALuv8i16 |
| 7439 | { 2952, 6, 1, 4, 542, 0, 0, 1650, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2952 = VMLALuv4i32 |
| 7440 | { 2951, 6, 1, 4, 541, 0, 0, 1650, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2951 = VMLALuv2i64 |
| 7441 | { 2950, 6, 1, 4, 542, 0, 0, 1650, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2950 = VMLALsv8i16 |
| 7442 | { 2949, 6, 1, 4, 542, 0, 0, 1650, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2949 = VMLALsv4i32 |
| 7443 | { 2948, 6, 1, 4, 541, 0, 0, 1650, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2948 = VMLALsv2i64 |
| 7444 | { 2947, 7, 1, 4, 542, 0, 0, 2232, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #2947 = VMLALsluv4i16 |
| 7445 | { 2946, 7, 1, 4, 541, 0, 0, 2225, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #2946 = VMLALsluv2i32 |
| 7446 | { 2945, 7, 1, 4, 542, 0, 0, 2232, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #2945 = VMLALslsv4i16 |
| 7447 | { 2944, 7, 1, 4, 541, 0, 0, 2225, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // Inst #2944 = VMLALslsv2i32 |
| 7448 | { 2943, 6, 1, 4, 540, 0, 0, 1857, ARMImpOpBase + 0, 0, 0x8800ULL }, // Inst #2943 = VMLAH |
| 7449 | { 2942, 6, 1, 4, 539, 0, 0, 1662, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x8800ULL }, // Inst #2942 = VMLAD |
| 7450 | { 2941, 5, 1, 4, 962, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2941 = VMINuv8i8 |
| 7451 | { 2940, 5, 1, 4, 776, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2940 = VMINuv8i16 |
| 7452 | { 2939, 5, 1, 4, 776, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2939 = VMINuv4i32 |
| 7453 | { 2938, 5, 1, 4, 962, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2938 = VMINuv4i16 |
| 7454 | { 2937, 5, 1, 4, 962, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2937 = VMINuv2i32 |
| 7455 | { 2936, 5, 1, 4, 776, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2936 = VMINuv16i8 |
| 7456 | { 2935, 5, 1, 4, 962, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2935 = VMINsv8i8 |
| 7457 | { 2934, 5, 1, 4, 776, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2934 = VMINsv8i16 |
| 7458 | { 2933, 5, 1, 4, 776, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2933 = VMINsv4i32 |
| 7459 | { 2932, 5, 1, 4, 962, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2932 = VMINsv4i16 |
| 7460 | { 2931, 5, 1, 4, 962, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2931 = VMINsv2i32 |
| 7461 | { 2930, 5, 1, 4, 776, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2930 = VMINsv16i8 |
| 7462 | { 2929, 5, 1, 4, 522, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2929 = VMINhq |
| 7463 | { 2928, 5, 1, 4, 521, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2928 = VMINhd |
| 7464 | { 2927, 5, 1, 4, 522, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2927 = VMINfq |
| 7465 | { 2926, 5, 1, 4, 521, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2926 = VMINfd |
| 7466 | { 2925, 5, 1, 4, 962, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2925 = VMAXuv8i8 |
| 7467 | { 2924, 5, 1, 4, 776, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2924 = VMAXuv8i16 |
| 7468 | { 2923, 5, 1, 4, 776, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2923 = VMAXuv4i32 |
| 7469 | { 2922, 5, 1, 4, 962, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2922 = VMAXuv4i16 |
| 7470 | { 2921, 5, 1, 4, 962, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2921 = VMAXuv2i32 |
| 7471 | { 2920, 5, 1, 4, 776, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2920 = VMAXuv16i8 |
| 7472 | { 2919, 5, 1, 4, 962, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2919 = VMAXsv8i8 |
| 7473 | { 2918, 5, 1, 4, 776, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2918 = VMAXsv8i16 |
| 7474 | { 2917, 5, 1, 4, 776, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2917 = VMAXsv4i32 |
| 7475 | { 2916, 5, 1, 4, 962, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2916 = VMAXsv4i16 |
| 7476 | { 2915, 5, 1, 4, 962, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2915 = VMAXsv2i32 |
| 7477 | { 2914, 5, 1, 4, 776, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2914 = VMAXsv16i8 |
| 7478 | { 2913, 5, 1, 4, 522, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2913 = VMAXhq |
| 7479 | { 2912, 5, 1, 4, 521, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2912 = VMAXhd |
| 7480 | { 2911, 5, 1, 4, 522, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2911 = VMAXfq |
| 7481 | { 2910, 5, 1, 4, 521, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2910 = VMAXfd |
| 7482 | { 2909, 4, 0, 4, 956, 35, 3, 2221, ARMImpOpBase + 148, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b84ULL }, // Inst #2909 = VLSTM_T2 |
| 7483 | { 2908, 4, 0, 4, 956, 19, 3, 2221, ARMImpOpBase + 126, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b84ULL }, // Inst #2908 = VLSTM |
| 7484 | { 2907, 4, 0, 4, 936, 0, 35, 2221, ARMImpOpBase + 91, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b84ULL }, // Inst #2907 = VLLDM_T2 |
| 7485 | { 2906, 4, 0, 4, 936, 0, 19, 2221, ARMImpOpBase + 72, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b84ULL }, // Inst #2906 = VLLDM |
| 7486 | { 2905, 5, 1, 4, 748, 0, 1, 2194, ARMImpOpBase + 69, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b35ULL }, // Inst #2905 = VLDR_VPR_pre |
| 7487 | { 2904, 5, 1, 4, 748, 0, 1, 2194, ARMImpOpBase + 69, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b55ULL }, // Inst #2904 = VLDR_VPR_post |
| 7488 | { 2903, 4, 0, 4, 748, 0, 1, 2190, ARMImpOpBase + 69, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b55ULL }, // Inst #2903 = VLDR_VPR_off |
| 7489 | { 2902, 6, 2, 4, 748, 0, 0, 2215, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b35ULL }, // Inst #2902 = VLDR_P0_pre |
| 7490 | { 2901, 6, 2, 4, 748, 0, 0, 2215, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b55ULL }, // Inst #2901 = VLDR_P0_post |
| 7491 | { 2900, 5, 1, 4, 748, 0, 0, 2210, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b55ULL }, // Inst #2900 = VLDR_P0_off |
| 7492 | { 2899, 5, 1, 4, 748, 0, 1, 2194, ARMImpOpBase + 71, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b35ULL }, // Inst #2899 = VLDR_FPSCR_pre |
| 7493 | { 2898, 5, 1, 4, 748, 0, 1, 2194, ARMImpOpBase + 71, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b55ULL }, // Inst #2898 = VLDR_FPSCR_post |
| 7494 | { 2897, 4, 0, 4, 748, 0, 1, 2190, ARMImpOpBase + 71, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b55ULL }, // Inst #2897 = VLDR_FPSCR_off |
| 7495 | { 2896, 6, 2, 4, 748, 0, 0, 2204, ARMImpOpBase + 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b35ULL }, // Inst #2896 = VLDR_FPSCR_NZCVQC_pre |
| 7496 | { 2895, 6, 2, 4, 748, 0, 0, 2204, ARMImpOpBase + 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b55ULL }, // Inst #2895 = VLDR_FPSCR_NZCVQC_post |
| 7497 | { 2894, 5, 1, 4, 748, 0, 0, 2199, ARMImpOpBase + 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b55ULL }, // Inst #2894 = VLDR_FPSCR_NZCVQC_off |
| 7498 | { 2893, 5, 1, 4, 748, 0, 1, 2194, ARMImpOpBase + 71, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b35ULL }, // Inst #2893 = VLDR_FPCXTS_pre |
| 7499 | { 2892, 5, 1, 4, 748, 0, 1, 2194, ARMImpOpBase + 71, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b55ULL }, // Inst #2892 = VLDR_FPCXTS_post |
| 7500 | { 2891, 4, 0, 4, 748, 0, 1, 2190, ARMImpOpBase + 71, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b55ULL }, // Inst #2891 = VLDR_FPCXTS_off |
| 7501 | { 2890, 5, 1, 4, 748, 0, 1, 2194, ARMImpOpBase + 71, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b35ULL }, // Inst #2890 = VLDR_FPCXTNS_pre |
| 7502 | { 2889, 5, 1, 4, 748, 0, 1, 2194, ARMImpOpBase + 71, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b55ULL }, // Inst #2889 = VLDR_FPCXTNS_post |
| 7503 | { 2888, 4, 0, 4, 748, 0, 1, 2190, ARMImpOpBase + 71, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b55ULL }, // Inst #2888 = VLDR_FPCXTNS_off |
| 7504 | { 2887, 5, 1, 4, 589, 0, 0, 2185, ARMImpOpBase + 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0x18b05ULL }, // Inst #2887 = VLDRS |
| 7505 | { 2886, 5, 1, 4, 747, 0, 0, 2180, ARMImpOpBase + 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x18b13ULL }, // Inst #2886 = VLDRH |
| 7506 | { 2885, 5, 1, 4, 588, 0, 0, 385, ARMImpOpBase + 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0x18b05ULL }, // Inst #2885 = VLDRD |
| 7507 | { 2884, 5, 1, 4, 595, 0, 0, 234, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x18be4ULL }, // Inst #2884 = VLDMSIA_UPD |
| 7508 | { 2883, 4, 0, 4, 594, 0, 0, 873, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x18b84ULL }, // Inst #2883 = VLDMSIA |
| 7509 | { 2882, 5, 1, 4, 595, 0, 0, 234, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x18be4ULL }, // Inst #2882 = VLDMSDB_UPD |
| 7510 | { 2881, 4, 1, 4, 592, 0, 0, 2176, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x18004ULL }, // Inst #2881 = VLDMQIA |
| 7511 | { 2880, 5, 1, 4, 595, 0, 0, 234, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x8be4ULL }, // Inst #2880 = VLDMDIA_UPD |
| 7512 | { 2879, 4, 0, 4, 594, 0, 0, 873, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x8b84ULL }, // Inst #2879 = VLDMDIA |
| 7513 | { 2878, 5, 1, 4, 595, 0, 0, 234, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x8be4ULL }, // Inst #2878 = VLDMDDB_UPD |
| 7514 | { 2877, 8, 2, 4, 617, 0, 0, 1984, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2877 = VLD4q8oddPseudo_UPD |
| 7515 | { 2876, 6, 1, 4, 615, 0, 0, 1978, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2876 = VLD4q8oddPseudo |
| 7516 | { 2875, 10, 5, 4, 616, 0, 0, 2138, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2875 = VLD4q8_UPD |
| 7517 | { 2874, 8, 2, 4, 617, 0, 0, 1984, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2874 = VLD4q8Pseudo_UPD |
| 7518 | { 2873, 8, 4, 4, 614, 0, 0, 2130, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2873 = VLD4q8 |
| 7519 | { 2872, 8, 2, 4, 617, 0, 0, 1984, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2872 = VLD4q32oddPseudo_UPD |
| 7520 | { 2871, 6, 1, 4, 615, 0, 0, 1978, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2871 = VLD4q32oddPseudo |
| 7521 | { 2870, 10, 5, 4, 616, 0, 0, 2138, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2870 = VLD4q32_UPD |
| 7522 | { 2869, 8, 2, 4, 617, 0, 0, 1984, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2869 = VLD4q32Pseudo_UPD |
| 7523 | { 2868, 8, 4, 4, 614, 0, 0, 2130, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2868 = VLD4q32 |
| 7524 | { 2867, 8, 2, 4, 617, 0, 0, 1984, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2867 = VLD4q16oddPseudo_UPD |
| 7525 | { 2866, 6, 1, 4, 615, 0, 0, 1978, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2866 = VLD4q16oddPseudo |
| 7526 | { 2865, 10, 5, 4, 616, 0, 0, 2138, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2865 = VLD4q16_UPD |
| 7527 | { 2864, 8, 2, 4, 617, 0, 0, 1984, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2864 = VLD4q16Pseudo_UPD |
| 7528 | { 2863, 8, 4, 4, 614, 0, 0, 2130, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2863 = VLD4q16 |
| 7529 | { 2862, 10, 5, 4, 616, 0, 0, 2138, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2862 = VLD4d8_UPD |
| 7530 | { 2861, 7, 2, 4, 617, 0, 0, 2074, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2861 = VLD4d8Pseudo_UPD |
| 7531 | { 2860, 5, 1, 4, 615, 0, 0, 1960, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2860 = VLD4d8Pseudo |
| 7532 | { 2859, 8, 4, 4, 614, 0, 0, 2130, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2859 = VLD4d8 |
| 7533 | { 2858, 10, 5, 4, 616, 0, 0, 2138, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2858 = VLD4d32_UPD |
| 7534 | { 2857, 7, 2, 4, 617, 0, 0, 2074, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2857 = VLD4d32Pseudo_UPD |
| 7535 | { 2856, 5, 1, 4, 615, 0, 0, 1960, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2856 = VLD4d32Pseudo |
| 7536 | { 2855, 8, 4, 4, 614, 0, 0, 2130, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2855 = VLD4d32 |
| 7537 | { 2854, 10, 5, 4, 616, 0, 0, 2138, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2854 = VLD4d16_UPD |
| 7538 | { 2853, 7, 2, 4, 617, 0, 0, 2074, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2853 = VLD4d16Pseudo_UPD |
| 7539 | { 2852, 5, 1, 4, 615, 0, 0, 1960, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2852 = VLD4d16Pseudo |
| 7540 | { 2851, 8, 4, 4, 614, 0, 0, 2130, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2851 = VLD4d16 |
| 7541 | { 2850, 15, 5, 4, 1008, 0, 0, 2161, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2850 = VLD4LNq32_UPD |
| 7542 | { 2849, 9, 2, 4, 1009, 0, 0, 2121, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2849 = VLD4LNq32Pseudo_UPD |
| 7543 | { 2848, 7, 1, 4, 1007, 0, 0, 2114, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2848 = VLD4LNq32Pseudo |
| 7544 | { 2847, 13, 4, 4, 1007, 0, 0, 2148, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2847 = VLD4LNq32 |
| 7545 | { 2846, 15, 5, 4, 640, 0, 0, 2161, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2846 = VLD4LNq16_UPD |
| 7546 | { 2845, 9, 2, 4, 642, 0, 0, 2121, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2845 = VLD4LNq16Pseudo_UPD |
| 7547 | { 2844, 7, 1, 4, 637, 0, 0, 2114, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2844 = VLD4LNq16Pseudo |
| 7548 | { 2843, 13, 4, 4, 637, 0, 0, 2148, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2843 = VLD4LNq16 |
| 7549 | { 2842, 15, 5, 4, 640, 0, 0, 2161, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2842 = VLD4LNd8_UPD |
| 7550 | { 2841, 9, 2, 4, 642, 0, 0, 2058, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2841 = VLD4LNd8Pseudo_UPD |
| 7551 | { 2840, 7, 1, 4, 637, 0, 0, 2051, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2840 = VLD4LNd8Pseudo |
| 7552 | { 2839, 13, 4, 4, 637, 0, 0, 2148, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2839 = VLD4LNd8 |
| 7553 | { 2838, 15, 5, 4, 1008, 0, 0, 2161, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2838 = VLD4LNd32_UPD |
| 7554 | { 2837, 9, 2, 4, 1009, 0, 0, 2058, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2837 = VLD4LNd32Pseudo_UPD |
| 7555 | { 2836, 7, 1, 4, 1007, 0, 0, 2051, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2836 = VLD4LNd32Pseudo |
| 7556 | { 2835, 13, 4, 4, 1007, 0, 0, 2148, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2835 = VLD4LNd32 |
| 7557 | { 2834, 15, 5, 4, 640, 0, 0, 2161, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2834 = VLD4LNd16_UPD |
| 7558 | { 2833, 9, 2, 4, 642, 0, 0, 2058, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2833 = VLD4LNd16Pseudo_UPD |
| 7559 | { 2832, 7, 1, 4, 637, 0, 0, 2051, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2832 = VLD4LNd16Pseudo |
| 7560 | { 2831, 13, 4, 4, 637, 0, 0, 2148, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2831 = VLD4LNd16 |
| 7561 | { 2830, 10, 5, 4, 639, 0, 0, 2138, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2830 = VLD4DUPq8_UPD |
| 7562 | { 2829, 8, 2, 4, 1052, 0, 0, 1984, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2829 = VLD4DUPq8OddPseudo_UPD |
| 7563 | { 2828, 6, 1, 4, 1051, 0, 0, 1978, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2828 = VLD4DUPq8OddPseudo |
| 7564 | { 2827, 6, 1, 4, 1051, 0, 0, 1978, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2827 = VLD4DUPq8EvenPseudo |
| 7565 | { 2826, 8, 4, 4, 636, 0, 0, 2130, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2826 = VLD4DUPq8 |
| 7566 | { 2825, 10, 5, 4, 639, 0, 0, 2138, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2825 = VLD4DUPq32_UPD |
| 7567 | { 2824, 8, 2, 4, 1052, 0, 0, 1984, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2824 = VLD4DUPq32OddPseudo_UPD |
| 7568 | { 2823, 6, 1, 4, 1051, 0, 0, 1978, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2823 = VLD4DUPq32OddPseudo |
| 7569 | { 2822, 6, 1, 4, 1051, 0, 0, 1978, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2822 = VLD4DUPq32EvenPseudo |
| 7570 | { 2821, 8, 4, 4, 636, 0, 0, 2130, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2821 = VLD4DUPq32 |
| 7571 | { 2820, 10, 5, 4, 639, 0, 0, 2138, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2820 = VLD4DUPq16_UPD |
| 7572 | { 2819, 8, 2, 4, 1052, 0, 0, 1984, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2819 = VLD4DUPq16OddPseudo_UPD |
| 7573 | { 2818, 6, 1, 4, 1051, 0, 0, 1978, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2818 = VLD4DUPq16OddPseudo |
| 7574 | { 2817, 6, 1, 4, 1051, 0, 0, 1978, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2817 = VLD4DUPq16EvenPseudo |
| 7575 | { 2816, 8, 4, 4, 636, 0, 0, 2130, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2816 = VLD4DUPq16 |
| 7576 | { 2815, 10, 5, 4, 639, 0, 0, 2138, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2815 = VLD4DUPd8_UPD |
| 7577 | { 2814, 7, 2, 4, 641, 0, 0, 2074, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2814 = VLD4DUPd8Pseudo_UPD |
| 7578 | { 2813, 5, 1, 4, 638, 0, 0, 1960, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2813 = VLD4DUPd8Pseudo |
| 7579 | { 2812, 8, 4, 4, 636, 0, 0, 2130, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2812 = VLD4DUPd8 |
| 7580 | { 2811, 10, 5, 4, 639, 0, 0, 2138, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2811 = VLD4DUPd32_UPD |
| 7581 | { 2810, 7, 2, 4, 641, 0, 0, 2074, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2810 = VLD4DUPd32Pseudo_UPD |
| 7582 | { 2809, 5, 1, 4, 638, 0, 0, 1960, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2809 = VLD4DUPd32Pseudo |
| 7583 | { 2808, 8, 4, 4, 636, 0, 0, 2130, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2808 = VLD4DUPd32 |
| 7584 | { 2807, 10, 5, 4, 639, 0, 0, 2138, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2807 = VLD4DUPd16_UPD |
| 7585 | { 2806, 7, 2, 4, 641, 0, 0, 2074, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2806 = VLD4DUPd16Pseudo_UPD |
| 7586 | { 2805, 5, 1, 4, 638, 0, 0, 1960, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2805 = VLD4DUPd16Pseudo |
| 7587 | { 2804, 8, 4, 4, 636, 0, 0, 2130, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2804 = VLD4DUPd16 |
| 7588 | { 2803, 8, 2, 4, 613, 0, 0, 1984, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2803 = VLD3q8oddPseudo_UPD |
| 7589 | { 2802, 6, 1, 4, 611, 0, 0, 1978, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2802 = VLD3q8oddPseudo |
| 7590 | { 2801, 9, 4, 4, 612, 0, 0, 2081, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2801 = VLD3q8_UPD |
| 7591 | { 2800, 8, 2, 4, 613, 0, 0, 1984, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2800 = VLD3q8Pseudo_UPD |
| 7592 | { 2799, 7, 3, 4, 610, 0, 0, 2067, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2799 = VLD3q8 |
| 7593 | { 2798, 8, 2, 4, 613, 0, 0, 1984, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2798 = VLD3q32oddPseudo_UPD |
| 7594 | { 2797, 6, 1, 4, 611, 0, 0, 1978, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2797 = VLD3q32oddPseudo |
| 7595 | { 2796, 9, 4, 4, 612, 0, 0, 2081, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2796 = VLD3q32_UPD |
| 7596 | { 2795, 8, 2, 4, 613, 0, 0, 1984, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2795 = VLD3q32Pseudo_UPD |
| 7597 | { 2794, 7, 3, 4, 610, 0, 0, 2067, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2794 = VLD3q32 |
| 7598 | { 2793, 8, 2, 4, 613, 0, 0, 1984, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2793 = VLD3q16oddPseudo_UPD |
| 7599 | { 2792, 6, 1, 4, 611, 0, 0, 1978, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2792 = VLD3q16oddPseudo |
| 7600 | { 2791, 9, 4, 4, 612, 0, 0, 2081, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2791 = VLD3q16_UPD |
| 7601 | { 2790, 8, 2, 4, 613, 0, 0, 1984, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2790 = VLD3q16Pseudo_UPD |
| 7602 | { 2789, 7, 3, 4, 610, 0, 0, 2067, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2789 = VLD3q16 |
| 7603 | { 2788, 9, 4, 4, 612, 0, 0, 2081, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2788 = VLD3d8_UPD |
| 7604 | { 2787, 7, 2, 4, 613, 0, 0, 2074, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2787 = VLD3d8Pseudo_UPD |
| 7605 | { 2786, 5, 1, 4, 611, 0, 0, 1960, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2786 = VLD3d8Pseudo |
| 7606 | { 2785, 7, 3, 4, 610, 0, 0, 2067, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2785 = VLD3d8 |
| 7607 | { 2784, 9, 4, 4, 612, 0, 0, 2081, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2784 = VLD3d32_UPD |
| 7608 | { 2783, 7, 2, 4, 613, 0, 0, 2074, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2783 = VLD3d32Pseudo_UPD |
| 7609 | { 2782, 5, 1, 4, 611, 0, 0, 1960, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2782 = VLD3d32Pseudo |
| 7610 | { 2781, 7, 3, 4, 610, 0, 0, 2067, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2781 = VLD3d32 |
| 7611 | { 2780, 9, 4, 4, 612, 0, 0, 2081, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2780 = VLD3d16_UPD |
| 7612 | { 2779, 7, 2, 4, 613, 0, 0, 2074, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2779 = VLD3d16Pseudo_UPD |
| 7613 | { 2778, 5, 1, 4, 611, 0, 0, 1960, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2778 = VLD3d16Pseudo |
| 7614 | { 2777, 7, 3, 4, 610, 0, 0, 2067, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2777 = VLD3d16 |
| 7615 | { 2776, 13, 4, 4, 1005, 0, 0, 2101, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2776 = VLD3LNq32_UPD |
| 7616 | { 2775, 9, 2, 4, 1006, 0, 0, 2121, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2775 = VLD3LNq32Pseudo_UPD |
| 7617 | { 2774, 7, 1, 4, 1004, 0, 0, 2114, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2774 = VLD3LNq32Pseudo |
| 7618 | { 2773, 11, 3, 4, 1004, 0, 0, 2090, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2773 = VLD3LNq32 |
| 7619 | { 2772, 13, 4, 4, 633, 0, 0, 2101, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2772 = VLD3LNq16_UPD |
| 7620 | { 2771, 9, 2, 4, 635, 0, 0, 2121, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2771 = VLD3LNq16Pseudo_UPD |
| 7621 | { 2770, 7, 1, 4, 631, 0, 0, 2114, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2770 = VLD3LNq16Pseudo |
| 7622 | { 2769, 11, 3, 4, 631, 0, 0, 2090, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2769 = VLD3LNq16 |
| 7623 | { 2768, 13, 4, 4, 633, 0, 0, 2101, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2768 = VLD3LNd8_UPD |
| 7624 | { 2767, 9, 2, 4, 635, 0, 0, 2058, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2767 = VLD3LNd8Pseudo_UPD |
| 7625 | { 2766, 7, 1, 4, 631, 0, 0, 2051, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2766 = VLD3LNd8Pseudo |
| 7626 | { 2765, 11, 3, 4, 631, 0, 0, 2090, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2765 = VLD3LNd8 |
| 7627 | { 2764, 13, 4, 4, 1005, 0, 0, 2101, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2764 = VLD3LNd32_UPD |
| 7628 | { 2763, 9, 2, 4, 1006, 0, 0, 2058, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2763 = VLD3LNd32Pseudo_UPD |
| 7629 | { 2762, 7, 1, 4, 1004, 0, 0, 2051, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2762 = VLD3LNd32Pseudo |
| 7630 | { 2761, 11, 3, 4, 1004, 0, 0, 2090, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2761 = VLD3LNd32 |
| 7631 | { 2760, 13, 4, 4, 633, 0, 0, 2101, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2760 = VLD3LNd16_UPD |
| 7632 | { 2759, 9, 2, 4, 635, 0, 0, 2058, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2759 = VLD3LNd16Pseudo_UPD |
| 7633 | { 2758, 7, 1, 4, 631, 0, 0, 2051, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2758 = VLD3LNd16Pseudo |
| 7634 | { 2757, 11, 3, 4, 631, 0, 0, 2090, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2757 = VLD3LNd16 |
| 7635 | { 2756, 9, 4, 4, 632, 0, 0, 2081, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2756 = VLD3DUPq8_UPD |
| 7636 | { 2755, 8, 2, 4, 1050, 0, 0, 1984, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2755 = VLD3DUPq8OddPseudo_UPD |
| 7637 | { 2754, 6, 1, 4, 1049, 0, 0, 1978, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2754 = VLD3DUPq8OddPseudo |
| 7638 | { 2753, 6, 1, 4, 1049, 0, 0, 1978, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2753 = VLD3DUPq8EvenPseudo |
| 7639 | { 2752, 7, 3, 4, 630, 0, 0, 2067, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2752 = VLD3DUPq8 |
| 7640 | { 2751, 9, 4, 4, 632, 0, 0, 2081, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2751 = VLD3DUPq32_UPD |
| 7641 | { 2750, 8, 2, 4, 1050, 0, 0, 1984, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2750 = VLD3DUPq32OddPseudo_UPD |
| 7642 | { 2749, 6, 1, 4, 1049, 0, 0, 1978, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2749 = VLD3DUPq32OddPseudo |
| 7643 | { 2748, 6, 1, 4, 1049, 0, 0, 1978, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2748 = VLD3DUPq32EvenPseudo |
| 7644 | { 2747, 7, 3, 4, 630, 0, 0, 2067, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2747 = VLD3DUPq32 |
| 7645 | { 2746, 9, 4, 4, 632, 0, 0, 2081, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2746 = VLD3DUPq16_UPD |
| 7646 | { 2745, 8, 2, 4, 1050, 0, 0, 1984, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2745 = VLD3DUPq16OddPseudo_UPD |
| 7647 | { 2744, 6, 1, 4, 1049, 0, 0, 1978, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2744 = VLD3DUPq16OddPseudo |
| 7648 | { 2743, 6, 1, 4, 1049, 0, 0, 1978, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2743 = VLD3DUPq16EvenPseudo |
| 7649 | { 2742, 7, 3, 4, 630, 0, 0, 2067, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2742 = VLD3DUPq16 |
| 7650 | { 2741, 9, 4, 4, 632, 0, 0, 2081, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2741 = VLD3DUPd8_UPD |
| 7651 | { 2740, 7, 2, 4, 634, 0, 0, 2074, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2740 = VLD3DUPd8Pseudo_UPD |
| 7652 | { 2739, 5, 1, 4, 630, 0, 0, 1960, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2739 = VLD3DUPd8Pseudo |
| 7653 | { 2738, 7, 3, 4, 630, 0, 0, 2067, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2738 = VLD3DUPd8 |
| 7654 | { 2737, 9, 4, 4, 632, 0, 0, 2081, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2737 = VLD3DUPd32_UPD |
| 7655 | { 2736, 7, 2, 4, 634, 0, 0, 2074, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2736 = VLD3DUPd32Pseudo_UPD |
| 7656 | { 2735, 5, 1, 4, 630, 0, 0, 1960, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2735 = VLD3DUPd32Pseudo |
| 7657 | { 2734, 7, 3, 4, 630, 0, 0, 2067, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2734 = VLD3DUPd32 |
| 7658 | { 2733, 9, 4, 4, 632, 0, 0, 2081, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2733 = VLD3DUPd16_UPD |
| 7659 | { 2732, 7, 2, 4, 634, 0, 0, 2074, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2732 = VLD3DUPd16Pseudo_UPD |
| 7660 | { 2731, 5, 1, 4, 630, 0, 0, 1960, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2731 = VLD3DUPd16Pseudo |
| 7661 | { 2730, 7, 3, 4, 630, 0, 0, 2067, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2730 = VLD3DUPd16 |
| 7662 | { 2729, 7, 2, 4, 609, 0, 0, 1903, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2729 = VLD2q8wb_register |
| 7663 | { 2728, 6, 2, 4, 609, 0, 0, 1897, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2728 = VLD2q8wb_fixed |
| 7664 | { 2727, 7, 2, 4, 609, 0, 0, 1971, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2727 = VLD2q8PseudoWB_register |
| 7665 | { 2726, 6, 2, 4, 609, 0, 0, 1965, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2726 = VLD2q8PseudoWB_fixed |
| 7666 | { 2725, 5, 1, 4, 607, 0, 0, 1960, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2725 = VLD2q8Pseudo |
| 7667 | { 2724, 5, 1, 4, 607, 0, 0, 385, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2724 = VLD2q8 |
| 7668 | { 2723, 7, 2, 4, 609, 0, 0, 1903, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2723 = VLD2q32wb_register |
| 7669 | { 2722, 6, 2, 4, 609, 0, 0, 1897, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2722 = VLD2q32wb_fixed |
| 7670 | { 2721, 7, 2, 4, 609, 0, 0, 1971, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2721 = VLD2q32PseudoWB_register |
| 7671 | { 2720, 6, 2, 4, 609, 0, 0, 1965, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2720 = VLD2q32PseudoWB_fixed |
| 7672 | { 2719, 5, 1, 4, 607, 0, 0, 1960, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2719 = VLD2q32Pseudo |
| 7673 | { 2718, 5, 1, 4, 607, 0, 0, 385, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2718 = VLD2q32 |
| 7674 | { 2717, 7, 2, 4, 609, 0, 0, 1903, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2717 = VLD2q16wb_register |
| 7675 | { 2716, 6, 2, 4, 609, 0, 0, 1897, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2716 = VLD2q16wb_fixed |
| 7676 | { 2715, 7, 2, 4, 609, 0, 0, 1971, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2715 = VLD2q16PseudoWB_register |
| 7677 | { 2714, 6, 2, 4, 609, 0, 0, 1965, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2714 = VLD2q16PseudoWB_fixed |
| 7678 | { 2713, 5, 1, 4, 607, 0, 0, 1960, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2713 = VLD2q16Pseudo |
| 7679 | { 2712, 5, 1, 4, 607, 0, 0, 385, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2712 = VLD2q16 |
| 7680 | { 2711, 7, 2, 4, 1003, 0, 0, 1921, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2711 = VLD2d8wb_register |
| 7681 | { 2710, 6, 2, 4, 1003, 0, 0, 1915, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2710 = VLD2d8wb_fixed |
| 7682 | { 2709, 5, 1, 4, 1002, 0, 0, 1910, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2709 = VLD2d8 |
| 7683 | { 2708, 7, 2, 4, 1003, 0, 0, 1921, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2708 = VLD2d32wb_register |
| 7684 | { 2707, 6, 2, 4, 1003, 0, 0, 1915, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2707 = VLD2d32wb_fixed |
| 7685 | { 2706, 5, 1, 4, 1002, 0, 0, 1910, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2706 = VLD2d32 |
| 7686 | { 2705, 7, 2, 4, 1003, 0, 0, 1921, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2705 = VLD2d16wb_register |
| 7687 | { 2704, 6, 2, 4, 1003, 0, 0, 1915, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2704 = VLD2d16wb_fixed |
| 7688 | { 2703, 5, 1, 4, 1002, 0, 0, 1910, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2703 = VLD2d16 |
| 7689 | { 2702, 7, 2, 4, 608, 0, 0, 1921, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2702 = VLD2b8wb_register |
| 7690 | { 2701, 6, 2, 4, 608, 0, 0, 1915, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2701 = VLD2b8wb_fixed |
| 7691 | { 2700, 5, 1, 4, 606, 0, 0, 1910, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2700 = VLD2b8 |
| 7692 | { 2699, 7, 2, 4, 608, 0, 0, 1921, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2699 = VLD2b32wb_register |
| 7693 | { 2698, 6, 2, 4, 608, 0, 0, 1915, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2698 = VLD2b32wb_fixed |
| 7694 | { 2697, 5, 1, 4, 606, 0, 0, 1910, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2697 = VLD2b32 |
| 7695 | { 2696, 7, 2, 4, 608, 0, 0, 1921, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2696 = VLD2b16wb_register |
| 7696 | { 2695, 6, 2, 4, 608, 0, 0, 1915, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2695 = VLD2b16wb_fixed |
| 7697 | { 2694, 5, 1, 4, 606, 0, 0, 1910, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2694 = VLD2b16 |
| 7698 | { 2693, 11, 3, 4, 627, 0, 0, 2040, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2693 = VLD2LNq32_UPD |
| 7699 | { 2692, 9, 2, 4, 629, 0, 0, 2058, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2692 = VLD2LNq32Pseudo_UPD |
| 7700 | { 2691, 7, 1, 4, 626, 0, 0, 2051, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2691 = VLD2LNq32Pseudo |
| 7701 | { 2690, 9, 2, 4, 626, 0, 0, 2031, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2690 = VLD2LNq32 |
| 7702 | { 2689, 11, 3, 4, 627, 0, 0, 2040, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2689 = VLD2LNq16_UPD |
| 7703 | { 2688, 9, 2, 4, 629, 0, 0, 2058, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2688 = VLD2LNq16Pseudo_UPD |
| 7704 | { 2687, 7, 1, 4, 626, 0, 0, 2051, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2687 = VLD2LNq16Pseudo |
| 7705 | { 2686, 9, 2, 4, 626, 0, 0, 2031, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2686 = VLD2LNq16 |
| 7706 | { 2685, 11, 3, 4, 627, 0, 0, 2040, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2685 = VLD2LNd8_UPD |
| 7707 | { 2684, 9, 2, 4, 629, 0, 0, 1951, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2684 = VLD2LNd8Pseudo_UPD |
| 7708 | { 2683, 7, 1, 4, 626, 0, 0, 1944, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2683 = VLD2LNd8Pseudo |
| 7709 | { 2682, 9, 2, 4, 626, 0, 0, 2031, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2682 = VLD2LNd8 |
| 7710 | { 2681, 11, 3, 4, 627, 0, 0, 2040, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2681 = VLD2LNd32_UPD |
| 7711 | { 2680, 9, 2, 4, 629, 0, 0, 1951, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2680 = VLD2LNd32Pseudo_UPD |
| 7712 | { 2679, 7, 1, 4, 626, 0, 0, 1944, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2679 = VLD2LNd32Pseudo |
| 7713 | { 2678, 9, 2, 4, 626, 0, 0, 2031, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2678 = VLD2LNd32 |
| 7714 | { 2677, 11, 3, 4, 627, 0, 0, 2040, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2677 = VLD2LNd16_UPD |
| 7715 | { 2676, 9, 2, 4, 629, 0, 0, 1951, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2676 = VLD2LNd16Pseudo_UPD |
| 7716 | { 2675, 7, 1, 4, 626, 0, 0, 1944, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2675 = VLD2LNd16Pseudo |
| 7717 | { 2674, 9, 2, 4, 626, 0, 0, 2031, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2674 = VLD2LNd16 |
| 7718 | { 2673, 8, 2, 4, 1048, 0, 0, 2023, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2673 = VLD2DUPq8OddPseudoWB_register |
| 7719 | { 2672, 7, 2, 4, 1048, 0, 0, 2016, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2672 = VLD2DUPq8OddPseudoWB_fixed |
| 7720 | { 2671, 6, 1, 4, 1048, 0, 0, 2010, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2671 = VLD2DUPq8OddPseudo |
| 7721 | { 2670, 6, 1, 4, 1048, 0, 0, 2010, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2670 = VLD2DUPq8EvenPseudo |
| 7722 | { 2669, 8, 2, 4, 1048, 0, 0, 2023, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2669 = VLD2DUPq32OddPseudoWB_register |
| 7723 | { 2668, 7, 2, 4, 1048, 0, 0, 2016, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2668 = VLD2DUPq32OddPseudoWB_fixed |
| 7724 | { 2667, 6, 1, 4, 1048, 0, 0, 2010, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2667 = VLD2DUPq32OddPseudo |
| 7725 | { 2666, 6, 1, 4, 1048, 0, 0, 2010, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2666 = VLD2DUPq32EvenPseudo |
| 7726 | { 2665, 8, 2, 4, 1048, 0, 0, 2023, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2665 = VLD2DUPq16OddPseudoWB_register |
| 7727 | { 2664, 7, 2, 4, 1048, 0, 0, 2016, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2664 = VLD2DUPq16OddPseudoWB_fixed |
| 7728 | { 2663, 6, 1, 4, 1048, 0, 0, 2010, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2663 = VLD2DUPq16OddPseudo |
| 7729 | { 2662, 6, 1, 4, 1048, 0, 0, 2010, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2662 = VLD2DUPq16EvenPseudo |
| 7730 | { 2661, 7, 2, 4, 628, 0, 0, 2003, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2661 = VLD2DUPd8x2wb_register |
| 7731 | { 2660, 6, 2, 4, 628, 0, 0, 1997, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2660 = VLD2DUPd8x2wb_fixed |
| 7732 | { 2659, 5, 1, 4, 625, 0, 0, 1992, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2659 = VLD2DUPd8x2 |
| 7733 | { 2658, 7, 2, 4, 628, 0, 0, 1921, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2658 = VLD2DUPd8wb_register |
| 7734 | { 2657, 6, 2, 4, 628, 0, 0, 1915, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2657 = VLD2DUPd8wb_fixed |
| 7735 | { 2656, 5, 1, 4, 625, 0, 0, 1910, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2656 = VLD2DUPd8 |
| 7736 | { 2655, 7, 2, 4, 628, 0, 0, 2003, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2655 = VLD2DUPd32x2wb_register |
| 7737 | { 2654, 6, 2, 4, 628, 0, 0, 1997, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2654 = VLD2DUPd32x2wb_fixed |
| 7738 | { 2653, 5, 1, 4, 625, 0, 0, 1992, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2653 = VLD2DUPd32x2 |
| 7739 | { 2652, 7, 2, 4, 628, 0, 0, 1921, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2652 = VLD2DUPd32wb_register |
| 7740 | { 2651, 6, 2, 4, 628, 0, 0, 1915, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2651 = VLD2DUPd32wb_fixed |
| 7741 | { 2650, 5, 1, 4, 625, 0, 0, 1910, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2650 = VLD2DUPd32 |
| 7742 | { 2649, 7, 2, 4, 628, 0, 0, 2003, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2649 = VLD2DUPd16x2wb_register |
| 7743 | { 2648, 6, 2, 4, 628, 0, 0, 1997, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2648 = VLD2DUPd16x2wb_fixed |
| 7744 | { 2647, 5, 1, 4, 625, 0, 0, 1992, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2647 = VLD2DUPd16x2 |
| 7745 | { 2646, 7, 2, 4, 628, 0, 0, 1921, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2646 = VLD2DUPd16wb_register |
| 7746 | { 2645, 6, 2, 4, 628, 0, 0, 1915, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2645 = VLD2DUPd16wb_fixed |
| 7747 | { 2644, 5, 1, 4, 625, 0, 0, 1910, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2644 = VLD2DUPd16 |
| 7748 | { 2643, 7, 2, 4, 601, 0, 0, 1921, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2643 = VLD1q8wb_register |
| 7749 | { 2642, 6, 2, 4, 601, 0, 0, 1915, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2642 = VLD1q8wb_fixed |
| 7750 | { 2641, 8, 2, 4, 1047, 0, 0, 1984, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2641 = VLD1q8LowTPseudo_UPD |
| 7751 | { 2640, 8, 2, 4, 1046, 0, 0, 1984, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2640 = VLD1q8LowQPseudo_UPD |
| 7752 | { 2639, 8, 2, 4, 1047, 0, 0, 1984, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2639 = VLD1q8HighTPseudo_UPD |
| 7753 | { 2638, 6, 1, 4, 1047, 0, 0, 1978, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2638 = VLD1q8HighTPseudo |
| 7754 | { 2637, 8, 2, 4, 1046, 0, 0, 1984, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2637 = VLD1q8HighQPseudo_UPD |
| 7755 | { 2636, 6, 1, 4, 1046, 0, 0, 1978, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2636 = VLD1q8HighQPseudo |
| 7756 | { 2635, 5, 1, 4, 599, 0, 0, 1910, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2635 = VLD1q8 |
| 7757 | { 2634, 7, 2, 4, 601, 0, 0, 1921, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2634 = VLD1q64wb_register |
| 7758 | { 2633, 6, 2, 4, 601, 0, 0, 1915, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2633 = VLD1q64wb_fixed |
| 7759 | { 2632, 8, 2, 4, 1047, 0, 0, 1984, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2632 = VLD1q64LowTPseudo_UPD |
| 7760 | { 2631, 8, 2, 4, 1046, 0, 0, 1984, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2631 = VLD1q64LowQPseudo_UPD |
| 7761 | { 2630, 8, 2, 4, 1047, 0, 0, 1984, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2630 = VLD1q64HighTPseudo_UPD |
| 7762 | { 2629, 6, 1, 4, 1047, 0, 0, 1978, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2629 = VLD1q64HighTPseudo |
| 7763 | { 2628, 8, 2, 4, 1046, 0, 0, 1984, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2628 = VLD1q64HighQPseudo_UPD |
| 7764 | { 2627, 6, 1, 4, 1046, 0, 0, 1978, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2627 = VLD1q64HighQPseudo |
| 7765 | { 2626, 5, 1, 4, 599, 0, 0, 1910, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2626 = VLD1q64 |
| 7766 | { 2625, 7, 2, 4, 601, 0, 0, 1921, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2625 = VLD1q32wb_register |
| 7767 | { 2624, 6, 2, 4, 601, 0, 0, 1915, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2624 = VLD1q32wb_fixed |
| 7768 | { 2623, 8, 2, 4, 1047, 0, 0, 1984, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2623 = VLD1q32LowTPseudo_UPD |
| 7769 | { 2622, 8, 2, 4, 1046, 0, 0, 1984, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2622 = VLD1q32LowQPseudo_UPD |
| 7770 | { 2621, 8, 2, 4, 1047, 0, 0, 1984, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2621 = VLD1q32HighTPseudo_UPD |
| 7771 | { 2620, 6, 1, 4, 1047, 0, 0, 1978, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2620 = VLD1q32HighTPseudo |
| 7772 | { 2619, 8, 2, 4, 1046, 0, 0, 1984, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2619 = VLD1q32HighQPseudo_UPD |
| 7773 | { 2618, 6, 1, 4, 1046, 0, 0, 1978, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2618 = VLD1q32HighQPseudo |
| 7774 | { 2617, 5, 1, 4, 599, 0, 0, 1910, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2617 = VLD1q32 |
| 7775 | { 2616, 7, 2, 4, 601, 0, 0, 1921, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2616 = VLD1q16wb_register |
| 7776 | { 2615, 6, 2, 4, 601, 0, 0, 1915, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2615 = VLD1q16wb_fixed |
| 7777 | { 2614, 8, 2, 4, 1047, 0, 0, 1984, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2614 = VLD1q16LowTPseudo_UPD |
| 7778 | { 2613, 8, 2, 4, 1046, 0, 0, 1984, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2613 = VLD1q16LowQPseudo_UPD |
| 7779 | { 2612, 8, 2, 4, 1047, 0, 0, 1984, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2612 = VLD1q16HighTPseudo_UPD |
| 7780 | { 2611, 6, 1, 4, 1047, 0, 0, 1978, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2611 = VLD1q16HighTPseudo |
| 7781 | { 2610, 8, 2, 4, 1046, 0, 0, 1984, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2610 = VLD1q16HighQPseudo_UPD |
| 7782 | { 2609, 6, 1, 4, 1046, 0, 0, 1978, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2609 = VLD1q16HighQPseudo |
| 7783 | { 2608, 5, 1, 4, 599, 0, 0, 1910, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2608 = VLD1q16 |
| 7784 | { 2607, 7, 2, 4, 600, 0, 0, 1903, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2607 = VLD1d8wb_register |
| 7785 | { 2606, 6, 2, 4, 600, 0, 0, 1897, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2606 = VLD1d8wb_fixed |
| 7786 | { 2605, 7, 2, 4, 603, 0, 0, 1903, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2605 = VLD1d8Twb_register |
| 7787 | { 2604, 6, 2, 4, 603, 0, 0, 1897, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2604 = VLD1d8Twb_fixed |
| 7788 | { 2603, 7, 2, 4, 1047, 0, 0, 1971, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2603 = VLD1d8TPseudoWB_register |
| 7789 | { 2602, 6, 2, 4, 1047, 0, 0, 1965, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2602 = VLD1d8TPseudoWB_fixed |
| 7790 | { 2601, 5, 1, 4, 1047, 0, 0, 1960, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2601 = VLD1d8TPseudo |
| 7791 | { 2600, 5, 1, 4, 602, 0, 0, 385, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2600 = VLD1d8T |
| 7792 | { 2599, 7, 2, 4, 605, 0, 0, 1903, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2599 = VLD1d8Qwb_register |
| 7793 | { 2598, 6, 2, 4, 605, 0, 0, 1897, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2598 = VLD1d8Qwb_fixed |
| 7794 | { 2597, 7, 2, 4, 1046, 0, 0, 1971, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2597 = VLD1d8QPseudoWB_register |
| 7795 | { 2596, 6, 2, 4, 1046, 0, 0, 1965, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2596 = VLD1d8QPseudoWB_fixed |
| 7796 | { 2595, 5, 1, 4, 1046, 0, 0, 1960, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2595 = VLD1d8QPseudo |
| 7797 | { 2594, 5, 1, 4, 604, 0, 0, 385, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2594 = VLD1d8Q |
| 7798 | { 2593, 5, 1, 4, 598, 0, 0, 385, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2593 = VLD1d8 |
| 7799 | { 2592, 7, 2, 4, 600, 0, 0, 1903, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2592 = VLD1d64wb_register |
| 7800 | { 2591, 6, 2, 4, 600, 0, 0, 1897, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2591 = VLD1d64wb_fixed |
| 7801 | { 2590, 7, 2, 4, 603, 0, 0, 1903, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2590 = VLD1d64Twb_register |
| 7802 | { 2589, 6, 2, 4, 603, 0, 0, 1897, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2589 = VLD1d64Twb_fixed |
| 7803 | { 2588, 7, 2, 4, 602, 0, 0, 1971, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2588 = VLD1d64TPseudoWB_register |
| 7804 | { 2587, 6, 2, 4, 602, 0, 0, 1965, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2587 = VLD1d64TPseudoWB_fixed |
| 7805 | { 2586, 5, 1, 4, 602, 0, 0, 1960, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2586 = VLD1d64TPseudo |
| 7806 | { 2585, 5, 1, 4, 602, 0, 0, 385, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2585 = VLD1d64T |
| 7807 | { 2584, 7, 2, 4, 605, 0, 0, 1903, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2584 = VLD1d64Qwb_register |
| 7808 | { 2583, 6, 2, 4, 605, 0, 0, 1897, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2583 = VLD1d64Qwb_fixed |
| 7809 | { 2582, 7, 2, 4, 604, 0, 0, 1971, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2582 = VLD1d64QPseudoWB_register |
| 7810 | { 2581, 6, 2, 4, 604, 0, 0, 1965, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2581 = VLD1d64QPseudoWB_fixed |
| 7811 | { 2580, 5, 1, 4, 604, 0, 0, 1960, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2580 = VLD1d64QPseudo |
| 7812 | { 2579, 5, 1, 4, 604, 0, 0, 385, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2579 = VLD1d64Q |
| 7813 | { 2578, 5, 1, 4, 598, 0, 0, 385, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2578 = VLD1d64 |
| 7814 | { 2577, 7, 2, 4, 600, 0, 0, 1903, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2577 = VLD1d32wb_register |
| 7815 | { 2576, 6, 2, 4, 600, 0, 0, 1897, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2576 = VLD1d32wb_fixed |
| 7816 | { 2575, 7, 2, 4, 603, 0, 0, 1903, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2575 = VLD1d32Twb_register |
| 7817 | { 2574, 6, 2, 4, 603, 0, 0, 1897, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2574 = VLD1d32Twb_fixed |
| 7818 | { 2573, 7, 2, 4, 1047, 0, 0, 1971, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2573 = VLD1d32TPseudoWB_register |
| 7819 | { 2572, 6, 2, 4, 1047, 0, 0, 1965, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2572 = VLD1d32TPseudoWB_fixed |
| 7820 | { 2571, 5, 1, 4, 1047, 0, 0, 1960, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2571 = VLD1d32TPseudo |
| 7821 | { 2570, 5, 1, 4, 602, 0, 0, 385, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2570 = VLD1d32T |
| 7822 | { 2569, 7, 2, 4, 605, 0, 0, 1903, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2569 = VLD1d32Qwb_register |
| 7823 | { 2568, 6, 2, 4, 605, 0, 0, 1897, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2568 = VLD1d32Qwb_fixed |
| 7824 | { 2567, 7, 2, 4, 1046, 0, 0, 1971, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2567 = VLD1d32QPseudoWB_register |
| 7825 | { 2566, 6, 2, 4, 1046, 0, 0, 1965, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2566 = VLD1d32QPseudoWB_fixed |
| 7826 | { 2565, 5, 1, 4, 1046, 0, 0, 1960, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2565 = VLD1d32QPseudo |
| 7827 | { 2564, 5, 1, 4, 604, 0, 0, 385, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2564 = VLD1d32Q |
| 7828 | { 2563, 5, 1, 4, 598, 0, 0, 385, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2563 = VLD1d32 |
| 7829 | { 2562, 7, 2, 4, 600, 0, 0, 1903, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2562 = VLD1d16wb_register |
| 7830 | { 2561, 6, 2, 4, 600, 0, 0, 1897, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2561 = VLD1d16wb_fixed |
| 7831 | { 2560, 7, 2, 4, 603, 0, 0, 1903, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2560 = VLD1d16Twb_register |
| 7832 | { 2559, 6, 2, 4, 603, 0, 0, 1897, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2559 = VLD1d16Twb_fixed |
| 7833 | { 2558, 7, 2, 4, 1047, 0, 0, 1971, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2558 = VLD1d16TPseudoWB_register |
| 7834 | { 2557, 6, 2, 4, 1047, 0, 0, 1965, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2557 = VLD1d16TPseudoWB_fixed |
| 7835 | { 2556, 5, 1, 4, 1047, 0, 0, 1960, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2556 = VLD1d16TPseudo |
| 7836 | { 2555, 5, 1, 4, 602, 0, 0, 385, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2555 = VLD1d16T |
| 7837 | { 2554, 7, 2, 4, 605, 0, 0, 1903, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2554 = VLD1d16Qwb_register |
| 7838 | { 2553, 6, 2, 4, 605, 0, 0, 1897, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2553 = VLD1d16Qwb_fixed |
| 7839 | { 2552, 7, 2, 4, 1046, 0, 0, 1971, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2552 = VLD1d16QPseudoWB_register |
| 7840 | { 2551, 6, 2, 4, 1046, 0, 0, 1965, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2551 = VLD1d16QPseudoWB_fixed |
| 7841 | { 2550, 5, 1, 4, 1046, 0, 0, 1960, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2550 = VLD1d16QPseudo |
| 7842 | { 2549, 5, 1, 4, 604, 0, 0, 385, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2549 = VLD1d16Q |
| 7843 | { 2548, 5, 1, 4, 598, 0, 0, 385, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2548 = VLD1d16 |
| 7844 | { 2547, 9, 2, 4, 624, 0, 0, 1951, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2547 = VLD1LNq8Pseudo_UPD |
| 7845 | { 2546, 7, 1, 4, 621, 0, 0, 1944, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x10006ULL }, // Inst #2546 = VLD1LNq8Pseudo |
| 7846 | { 2545, 9, 2, 4, 624, 0, 0, 1951, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2545 = VLD1LNq32Pseudo_UPD |
| 7847 | { 2544, 7, 1, 4, 621, 0, 0, 1944, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x10006ULL }, // Inst #2544 = VLD1LNq32Pseudo |
| 7848 | { 2543, 9, 2, 4, 624, 0, 0, 1951, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // Inst #2543 = VLD1LNq16Pseudo_UPD |
| 7849 | { 2542, 7, 1, 4, 621, 0, 0, 1944, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x10006ULL }, // Inst #2542 = VLD1LNq16Pseudo |
| 7850 | { 2541, 9, 2, 4, 624, 0, 0, 1935, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2541 = VLD1LNd8_UPD |
| 7851 | { 2540, 7, 1, 4, 620, 0, 0, 1928, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x10f06ULL }, // Inst #2540 = VLD1LNd8 |
| 7852 | { 2539, 9, 2, 4, 624, 0, 0, 1935, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2539 = VLD1LNd32_UPD |
| 7853 | { 2538, 7, 1, 4, 621, 0, 0, 1928, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x10f06ULL }, // Inst #2538 = VLD1LNd32 |
| 7854 | { 2537, 9, 2, 4, 624, 0, 0, 1935, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2537 = VLD1LNd16_UPD |
| 7855 | { 2536, 7, 1, 4, 620, 0, 0, 1928, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x10f06ULL }, // Inst #2536 = VLD1LNd16 |
| 7856 | { 2535, 7, 2, 4, 622, 0, 0, 1921, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2535 = VLD1DUPq8wb_register |
| 7857 | { 2534, 6, 2, 4, 623, 0, 0, 1915, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2534 = VLD1DUPq8wb_fixed |
| 7858 | { 2533, 5, 1, 4, 619, 0, 0, 1910, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x10f06ULL }, // Inst #2533 = VLD1DUPq8 |
| 7859 | { 2532, 7, 2, 4, 622, 0, 0, 1921, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2532 = VLD1DUPq32wb_register |
| 7860 | { 2531, 6, 2, 4, 623, 0, 0, 1915, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2531 = VLD1DUPq32wb_fixed |
| 7861 | { 2530, 5, 1, 4, 619, 0, 0, 1910, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x10f06ULL }, // Inst #2530 = VLD1DUPq32 |
| 7862 | { 2529, 7, 2, 4, 622, 0, 0, 1921, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2529 = VLD1DUPq16wb_register |
| 7863 | { 2528, 6, 2, 4, 623, 0, 0, 1915, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2528 = VLD1DUPq16wb_fixed |
| 7864 | { 2527, 5, 1, 4, 619, 0, 0, 1910, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x10f06ULL }, // Inst #2527 = VLD1DUPq16 |
| 7865 | { 2526, 7, 2, 4, 622, 0, 0, 1903, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2526 = VLD1DUPd8wb_register |
| 7866 | { 2525, 6, 2, 4, 622, 0, 0, 1897, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2525 = VLD1DUPd8wb_fixed |
| 7867 | { 2524, 5, 1, 4, 618, 0, 0, 385, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x10f06ULL }, // Inst #2524 = VLD1DUPd8 |
| 7868 | { 2523, 7, 2, 4, 622, 0, 0, 1903, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2523 = VLD1DUPd32wb_register |
| 7869 | { 2522, 6, 2, 4, 622, 0, 0, 1897, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2522 = VLD1DUPd32wb_fixed |
| 7870 | { 2521, 5, 1, 4, 618, 0, 0, 385, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x10f06ULL }, // Inst #2521 = VLD1DUPd32 |
| 7871 | { 2520, 7, 2, 4, 622, 0, 0, 1903, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2520 = VLD1DUPd16wb_register |
| 7872 | { 2519, 6, 2, 4, 622, 0, 0, 1897, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // Inst #2519 = VLD1DUPd16wb_fixed |
| 7873 | { 2518, 5, 1, 4, 618, 0, 0, 385, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x10f06ULL }, // Inst #2518 = VLD1DUPd16 |
| 7874 | { 2517, 4, 1, 4, 959, 0, 0, 1814, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x8880ULL }, // Inst #2517 = VJCVT |
| 7875 | { 2516, 3, 1, 4, 968, 0, 0, 1894, ARMImpOpBase + 0, 0, 0x8780ULL }, // Inst #2516 = VINSH |
| 7876 | { 2515, 5, 1, 4, 469, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2515 = VHSUBuv8i8 |
| 7877 | { 2514, 5, 1, 4, 468, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2514 = VHSUBuv8i16 |
| 7878 | { 2513, 5, 1, 4, 468, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2513 = VHSUBuv4i32 |
| 7879 | { 2512, 5, 1, 4, 469, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2512 = VHSUBuv4i16 |
| 7880 | { 2511, 5, 1, 4, 469, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2511 = VHSUBuv2i32 |
| 7881 | { 2510, 5, 1, 4, 468, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2510 = VHSUBuv16i8 |
| 7882 | { 2509, 5, 1, 4, 469, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2509 = VHSUBsv8i8 |
| 7883 | { 2508, 5, 1, 4, 468, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2508 = VHSUBsv8i16 |
| 7884 | { 2507, 5, 1, 4, 468, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2507 = VHSUBsv4i32 |
| 7885 | { 2506, 5, 1, 4, 469, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2506 = VHSUBsv4i16 |
| 7886 | { 2505, 5, 1, 4, 469, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2505 = VHSUBsv2i32 |
| 7887 | { 2504, 5, 1, 4, 468, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2504 = VHSUBsv16i8 |
| 7888 | { 2503, 5, 1, 4, 774, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2503 = VHADDuv8i8 |
| 7889 | { 2502, 5, 1, 4, 775, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2502 = VHADDuv8i16 |
| 7890 | { 2501, 5, 1, 4, 775, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2501 = VHADDuv4i32 |
| 7891 | { 2500, 5, 1, 4, 774, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2500 = VHADDuv4i16 |
| 7892 | { 2499, 5, 1, 4, 774, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2499 = VHADDuv2i32 |
| 7893 | { 2498, 5, 1, 4, 775, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2498 = VHADDuv16i8 |
| 7894 | { 2497, 5, 1, 4, 774, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2497 = VHADDsv8i8 |
| 7895 | { 2496, 5, 1, 4, 775, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2496 = VHADDsv8i16 |
| 7896 | { 2495, 5, 1, 4, 775, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2495 = VHADDsv4i32 |
| 7897 | { 2494, 5, 1, 4, 774, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2494 = VHADDsv4i16 |
| 7898 | { 2493, 5, 1, 4, 774, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2493 = VHADDsv2i32 |
| 7899 | { 2492, 5, 1, 4, 775, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2492 = VHADDsv16i8 |
| 7900 | { 2491, 5, 1, 4, 583, 0, 0, 1889, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x10d80ULL }, // Inst #2491 = VGETLNu8 |
| 7901 | { 2490, 5, 1, 4, 583, 0, 0, 1889, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x10d80ULL }, // Inst #2490 = VGETLNu16 |
| 7902 | { 2489, 5, 1, 4, 584, 0, 0, 1889, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x10d80ULL }, // Inst #2489 = VGETLNs8 |
| 7903 | { 2488, 5, 1, 4, 584, 0, 0, 1889, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x10d80ULL }, // Inst #2488 = VGETLNs16 |
| 7904 | { 2487, 5, 1, 4, 1044, 0, 0, 1889, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x10d80ULL }, // Inst #2487 = VGETLNi32 |
| 7905 | { 2486, 3, 1, 4, 1250, 0, 0, 1886, ARMImpOpBase + 0, 0, 0x8800ULL }, // Inst #2486 = VFP_VMINNMS |
| 7906 | { 2485, 3, 1, 4, 1210, 0, 0, 1883, ARMImpOpBase + 0, 0, 0x8800ULL }, // Inst #2485 = VFP_VMINNMH |
| 7907 | { 2484, 3, 1, 4, 1254, 0, 0, 1506, ARMImpOpBase + 0, 0, 0x8800ULL }, // Inst #2484 = VFP_VMINNMD |
| 7908 | { 2483, 3, 1, 4, 1250, 0, 0, 1886, ARMImpOpBase + 0, 0, 0x8800ULL }, // Inst #2483 = VFP_VMAXNMS |
| 7909 | { 2482, 3, 1, 4, 1210, 0, 0, 1883, ARMImpOpBase + 0, 0, 0x8800ULL }, // Inst #2482 = VFP_VMAXNMH |
| 7910 | { 2481, 3, 1, 4, 1254, 0, 0, 1506, ARMImpOpBase + 0, 0, 0x8800ULL }, // Inst #2481 = VFP_VMAXNMD |
| 7911 | { 2480, 6, 1, 4, 549, 0, 0, 1877, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x8800ULL }, // Inst #2480 = VFNMSS |
| 7912 | { 2479, 6, 1, 4, 550, 0, 0, 1857, ARMImpOpBase + 0, 0, 0x8800ULL }, // Inst #2479 = VFNMSH |
| 7913 | { 2478, 6, 1, 4, 548, 0, 0, 1662, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x8800ULL }, // Inst #2478 = VFNMSD |
| 7914 | { 2477, 6, 1, 4, 549, 0, 0, 1877, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x8800ULL }, // Inst #2477 = VFNMAS |
| 7915 | { 2476, 6, 1, 4, 550, 0, 0, 1857, ARMImpOpBase + 0, 0, 0x8800ULL }, // Inst #2476 = VFNMAH |
| 7916 | { 2475, 6, 1, 4, 548, 0, 0, 1662, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x8800ULL }, // Inst #2475 = VFNMAD |
| 7917 | { 2474, 6, 1, 4, 773, 0, 0, 1656, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2474 = VFMShq |
| 7918 | { 2473, 6, 1, 4, 772, 0, 0, 1662, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2473 = VFMShd |
| 7919 | { 2472, 6, 1, 4, 552, 0, 0, 1656, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2472 = VFMSfq |
| 7920 | { 2471, 6, 1, 4, 551, 0, 0, 1662, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2471 = VFMSfd |
| 7921 | { 2470, 6, 1, 4, 549, 0, 0, 1877, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x8800ULL }, // Inst #2470 = VFMSS |
| 7922 | { 2469, 4, 1, 4, 116, 0, 0, 1873, ARMImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x11580ULL }, // Inst #2469 = VFMSLQI |
| 7923 | { 2468, 3, 1, 4, 0, 0, 0, 1870, ARMImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x11580ULL }, // Inst #2468 = VFMSLQ |
| 7924 | { 2467, 4, 1, 4, 116, 0, 0, 1866, ARMImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x11580ULL }, // Inst #2467 = VFMSLDI |
| 7925 | { 2466, 3, 1, 4, 0, 0, 0, 1863, ARMImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x11580ULL }, // Inst #2466 = VFMSLD |
| 7926 | { 2465, 6, 1, 4, 1209, 0, 0, 1857, ARMImpOpBase + 0, 0, 0x8800ULL }, // Inst #2465 = VFMSH |
| 7927 | { 2464, 6, 1, 4, 548, 0, 0, 1662, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x8800ULL }, // Inst #2464 = VFMSD |
| 7928 | { 2463, 6, 1, 4, 773, 0, 0, 1656, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2463 = VFMAhq |
| 7929 | { 2462, 6, 1, 4, 772, 0, 0, 1662, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2462 = VFMAhd |
| 7930 | { 2461, 6, 1, 4, 552, 0, 0, 1656, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2461 = VFMAfq |
| 7931 | { 2460, 6, 1, 4, 551, 0, 0, 1662, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2460 = VFMAfd |
| 7932 | { 2459, 6, 1, 4, 549, 0, 0, 1877, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x8800ULL }, // Inst #2459 = VFMAS |
| 7933 | { 2458, 4, 1, 4, 116, 0, 0, 1873, ARMImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x11580ULL }, // Inst #2458 = VFMALQI |
| 7934 | { 2457, 3, 1, 4, 0, 0, 0, 1870, ARMImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x11580ULL }, // Inst #2457 = VFMALQ |
| 7935 | { 2456, 4, 1, 4, 116, 0, 0, 1866, ARMImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x11580ULL }, // Inst #2456 = VFMALDI |
| 7936 | { 2455, 3, 1, 4, 0, 0, 0, 1863, ARMImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x11580ULL }, // Inst #2455 = VFMALD |
| 7937 | { 2454, 6, 1, 4, 1209, 0, 0, 1857, ARMImpOpBase + 0, 0, 0x8800ULL }, // Inst #2454 = VFMAH |
| 7938 | { 2453, 6, 1, 4, 548, 0, 0, 1662, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x8800ULL }, // Inst #2453 = VFMAD |
| 7939 | { 2452, 6, 1, 4, 476, 0, 0, 1851, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11380ULL }, // Inst #2452 = VEXTq8 |
| 7940 | { 2451, 6, 1, 4, 476, 0, 0, 1851, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11380ULL }, // Inst #2451 = VEXTq64 |
| 7941 | { 2450, 6, 1, 4, 476, 0, 0, 1851, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11380ULL }, // Inst #2450 = VEXTq32 |
| 7942 | { 2449, 6, 1, 4, 476, 0, 0, 1851, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11380ULL }, // Inst #2449 = VEXTq16 |
| 7943 | { 2448, 6, 1, 4, 475, 0, 0, 1845, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11380ULL }, // Inst #2448 = VEXTd8 |
| 7944 | { 2447, 6, 1, 4, 475, 0, 0, 1845, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11380ULL }, // Inst #2447 = VEXTd32 |
| 7945 | { 2446, 6, 1, 4, 475, 0, 0, 1845, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11380ULL }, // Inst #2446 = VEXTd16 |
| 7946 | { 2445, 5, 1, 4, 760, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2445 = VEORq |
| 7947 | { 2444, 5, 1, 4, 759, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2444 = VEORd |
| 7948 | { 2443, 5, 1, 4, 575, 0, 0, 1840, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11100ULL }, // Inst #2443 = VDUPLN8q |
| 7949 | { 2442, 5, 1, 4, 574, 0, 0, 1818, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11100ULL }, // Inst #2442 = VDUPLN8d |
| 7950 | { 2441, 5, 1, 4, 575, 0, 0, 1840, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11100ULL }, // Inst #2441 = VDUPLN32q |
| 7951 | { 2440, 5, 1, 4, 574, 0, 0, 1818, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11100ULL }, // Inst #2440 = VDUPLN32d |
| 7952 | { 2439, 5, 1, 4, 575, 0, 0, 1840, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11100ULL }, // Inst #2439 = VDUPLN16q |
| 7953 | { 2438, 5, 1, 4, 574, 0, 0, 1818, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11100ULL }, // Inst #2438 = VDUPLN16d |
| 7954 | { 2437, 4, 1, 4, 576, 0, 0, 1836, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x10e80ULL }, // Inst #2437 = VDUP8q |
| 7955 | { 2436, 4, 1, 4, 770, 0, 0, 1832, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x10e80ULL }, // Inst #2436 = VDUP8d |
| 7956 | { 2435, 4, 1, 4, 576, 0, 0, 1836, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x10e80ULL }, // Inst #2435 = VDUP32q |
| 7957 | { 2434, 4, 1, 4, 770, 0, 0, 1832, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x10e80ULL }, // Inst #2434 = VDUP32d |
| 7958 | { 2433, 4, 1, 4, 576, 0, 0, 1836, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x10e80ULL }, // Inst #2433 = VDUP16q |
| 7959 | { 2432, 4, 1, 4, 770, 0, 0, 1832, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x10e80ULL }, // Inst #2432 = VDUP16d |
| 7960 | { 2431, 5, 1, 4, 675, 0, 0, 1709, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x8800ULL }, // Inst #2431 = VDIVS |
| 7961 | { 2430, 5, 1, 4, 1208, 0, 0, 1699, ARMImpOpBase + 0, 0, 0x8800ULL }, // Inst #2430 = VDIVH |
| 7962 | { 2429, 5, 1, 4, 677, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x8800ULL }, // Inst #2429 = VDIVD |
| 7963 | { 2428, 5, 1, 4, 559, 0, 0, 1823, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11080ULL }, // Inst #2428 = VCVTxu2hq |
| 7964 | { 2427, 5, 1, 4, 560, 0, 0, 1818, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11080ULL }, // Inst #2427 = VCVTxu2hd |
| 7965 | { 2426, 5, 1, 4, 995, 0, 0, 1823, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11080ULL }, // Inst #2426 = VCVTxu2fq |
| 7966 | { 2425, 5, 1, 4, 994, 0, 0, 1818, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11080ULL }, // Inst #2425 = VCVTxu2fd |
| 7967 | { 2424, 5, 1, 4, 559, 0, 0, 1823, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11080ULL }, // Inst #2424 = VCVTxs2hq |
| 7968 | { 2423, 5, 1, 4, 560, 0, 0, 1818, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11080ULL }, // Inst #2423 = VCVTxs2hd |
| 7969 | { 2422, 5, 1, 4, 995, 0, 0, 1823, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11080ULL }, // Inst #2422 = VCVTxs2fq |
| 7970 | { 2421, 5, 1, 4, 994, 0, 0, 1818, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11080ULL }, // Inst #2421 = VCVTxs2fd |
| 7971 | { 2420, 4, 1, 4, 559, 0, 0, 1695, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2420 = VCVTu2hq |
| 7972 | { 2419, 4, 1, 4, 560, 0, 0, 1683, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2419 = VCVTu2hd |
| 7973 | { 2418, 4, 1, 4, 995, 0, 0, 1695, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2418 = VCVTu2fq |
| 7974 | { 2417, 4, 1, 4, 994, 0, 0, 1683, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2417 = VCVTu2fd |
| 7975 | { 2416, 4, 1, 4, 559, 0, 0, 1695, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2416 = VCVTs2hq |
| 7976 | { 2415, 4, 1, 4, 560, 0, 0, 1683, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2415 = VCVTs2hd |
| 7977 | { 2414, 4, 1, 4, 995, 0, 0, 1695, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2414 = VCVTs2fq |
| 7978 | { 2413, 4, 1, 4, 994, 0, 0, 1683, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2413 = VCVTs2fd |
| 7979 | { 2412, 5, 1, 4, 559, 0, 0, 1823, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11080ULL }, // Inst #2412 = VCVTh2xuq |
| 7980 | { 2411, 5, 1, 4, 560, 0, 0, 1818, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11080ULL }, // Inst #2411 = VCVTh2xud |
| 7981 | { 2410, 5, 1, 4, 559, 0, 0, 1823, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11080ULL }, // Inst #2410 = VCVTh2xsq |
| 7982 | { 2409, 5, 1, 4, 560, 0, 0, 1818, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11080ULL }, // Inst #2409 = VCVTh2xsd |
| 7983 | { 2408, 4, 1, 4, 559, 0, 0, 1695, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2408 = VCVTh2uq |
| 7984 | { 2407, 4, 1, 4, 560, 0, 0, 1683, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2407 = VCVTh2ud |
| 7985 | { 2406, 4, 1, 4, 559, 0, 0, 1695, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2406 = VCVTh2sq |
| 7986 | { 2405, 4, 1, 4, 560, 0, 0, 1683, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2405 = VCVTh2sd |
| 7987 | { 2404, 4, 1, 4, 559, 0, 0, 1828, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2404 = VCVTh2f |
| 7988 | { 2403, 5, 1, 4, 995, 0, 0, 1823, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11080ULL }, // Inst #2403 = VCVTf2xuq |
| 7989 | { 2402, 5, 1, 4, 994, 0, 0, 1818, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11080ULL }, // Inst #2402 = VCVTf2xud |
| 7990 | { 2401, 5, 1, 4, 995, 0, 0, 1823, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11080ULL }, // Inst #2401 = VCVTf2xsq |
| 7991 | { 2400, 5, 1, 4, 994, 0, 0, 1818, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11080ULL }, // Inst #2400 = VCVTf2xsd |
| 7992 | { 2399, 4, 1, 4, 995, 0, 0, 1695, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2399 = VCVTf2uq |
| 7993 | { 2398, 4, 1, 4, 994, 0, 0, 1683, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2398 = VCVTf2ud |
| 7994 | { 2397, 4, 1, 4, 995, 0, 0, 1695, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2397 = VCVTf2sq |
| 7995 | { 2396, 4, 1, 4, 994, 0, 0, 1683, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2396 = VCVTf2sd |
| 7996 | { 2395, 4, 1, 4, 559, 0, 0, 645, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2395 = VCVTf2h |
| 7997 | { 2394, 5, 1, 4, 556, 0, 0, 408, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x8780ULL }, // Inst #2394 = VCVTTSH |
| 7998 | { 2393, 4, 1, 4, 555, 0, 0, 1691, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x8780ULL }, // Inst #2393 = VCVTTHS |
| 7999 | { 2392, 4, 1, 4, 1253, 0, 0, 1810, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x8780ULL }, // Inst #2392 = VCVTTHD |
| 8000 | { 2391, 5, 1, 4, 957, 0, 0, 1805, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x8780ULL }, // Inst #2391 = VCVTTDH |
| 8001 | { 2390, 4, 1, 4, 558, 0, 0, 1814, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x8780ULL }, // Inst #2390 = VCVTSD |
| 8002 | { 2389, 2, 1, 4, 1249, 0, 0, 1803, ARMImpOpBase + 0, 0, 0x8780ULL }, // Inst #2389 = VCVTPUS |
| 8003 | { 2388, 2, 1, 4, 1207, 0, 0, 1801, ARMImpOpBase + 0, 0, 0x8780ULL }, // Inst #2388 = VCVTPUH |
| 8004 | { 2387, 2, 1, 4, 1252, 0, 0, 1799, ARMImpOpBase + 0, 0, 0x8780ULL }, // Inst #2387 = VCVTPUD |
| 8005 | { 2386, 2, 1, 4, 1249, 0, 0, 1803, ARMImpOpBase + 0, 0, 0x8780ULL }, // Inst #2386 = VCVTPSS |
| 8006 | { 2385, 2, 1, 4, 1207, 0, 0, 1801, ARMImpOpBase + 0, 0, 0x8780ULL }, // Inst #2385 = VCVTPSH |
| 8007 | { 2384, 2, 1, 4, 1252, 0, 0, 1799, ARMImpOpBase + 0, 0, 0x8780ULL }, // Inst #2384 = VCVTPSD |
| 8008 | { 2383, 2, 1, 4, 553, 0, 0, 625, ARMImpOpBase + 0, 0, 0x11000ULL }, // Inst #2383 = VCVTPNUQh |
| 8009 | { 2382, 2, 1, 4, 553, 0, 0, 625, ARMImpOpBase + 0, 0, 0x11000ULL }, // Inst #2382 = VCVTPNUQf |
| 8010 | { 2381, 2, 1, 4, 553, 0, 0, 1797, ARMImpOpBase + 0, 0, 0x11000ULL }, // Inst #2381 = VCVTPNUDh |
| 8011 | { 2380, 2, 1, 4, 553, 0, 0, 1797, ARMImpOpBase + 0, 0, 0x11000ULL }, // Inst #2380 = VCVTPNUDf |
| 8012 | { 2379, 2, 1, 4, 553, 0, 0, 625, ARMImpOpBase + 0, 0, 0x11000ULL }, // Inst #2379 = VCVTPNSQh |
| 8013 | { 2378, 2, 1, 4, 553, 0, 0, 625, ARMImpOpBase + 0, 0, 0x11000ULL }, // Inst #2378 = VCVTPNSQf |
| 8014 | { 2377, 2, 1, 4, 553, 0, 0, 1797, ARMImpOpBase + 0, 0, 0x11000ULL }, // Inst #2377 = VCVTPNSDh |
| 8015 | { 2376, 2, 1, 4, 553, 0, 0, 1797, ARMImpOpBase + 0, 0, 0x11000ULL }, // Inst #2376 = VCVTPNSDf |
| 8016 | { 2375, 2, 1, 4, 1249, 0, 0, 1803, ARMImpOpBase + 0, 0, 0x8780ULL }, // Inst #2375 = VCVTNUS |
| 8017 | { 2374, 2, 1, 4, 1207, 0, 0, 1801, ARMImpOpBase + 0, 0, 0x8780ULL }, // Inst #2374 = VCVTNUH |
| 8018 | { 2373, 2, 1, 4, 1252, 0, 0, 1799, ARMImpOpBase + 0, 0, 0x8780ULL }, // Inst #2373 = VCVTNUD |
| 8019 | { 2372, 2, 1, 4, 1249, 0, 0, 1803, ARMImpOpBase + 0, 0, 0x8780ULL }, // Inst #2372 = VCVTNSS |
| 8020 | { 2371, 2, 1, 4, 1207, 0, 0, 1801, ARMImpOpBase + 0, 0, 0x8780ULL }, // Inst #2371 = VCVTNSH |
| 8021 | { 2370, 2, 1, 4, 1252, 0, 0, 1799, ARMImpOpBase + 0, 0, 0x8780ULL }, // Inst #2370 = VCVTNSD |
| 8022 | { 2369, 2, 1, 4, 553, 0, 0, 625, ARMImpOpBase + 0, 0, 0x11000ULL }, // Inst #2369 = VCVTNNUQh |
| 8023 | { 2368, 2, 1, 4, 553, 0, 0, 625, ARMImpOpBase + 0, 0, 0x11000ULL }, // Inst #2368 = VCVTNNUQf |
| 8024 | { 2367, 2, 1, 4, 553, 0, 0, 1797, ARMImpOpBase + 0, 0, 0x11000ULL }, // Inst #2367 = VCVTNNUDh |
| 8025 | { 2366, 2, 1, 4, 553, 0, 0, 1797, ARMImpOpBase + 0, 0, 0x11000ULL }, // Inst #2366 = VCVTNNUDf |
| 8026 | { 2365, 2, 1, 4, 553, 0, 0, 625, ARMImpOpBase + 0, 0, 0x11000ULL }, // Inst #2365 = VCVTNNSQh |
| 8027 | { 2364, 2, 1, 4, 553, 0, 0, 625, ARMImpOpBase + 0, 0, 0x11000ULL }, // Inst #2364 = VCVTNNSQf |
| 8028 | { 2363, 2, 1, 4, 553, 0, 0, 1797, ARMImpOpBase + 0, 0, 0x11000ULL }, // Inst #2363 = VCVTNNSDh |
| 8029 | { 2362, 2, 1, 4, 553, 0, 0, 1797, ARMImpOpBase + 0, 0, 0x11000ULL }, // Inst #2362 = VCVTNNSDf |
| 8030 | { 2361, 2, 1, 4, 1249, 0, 0, 1803, ARMImpOpBase + 0, 0, 0x8780ULL }, // Inst #2361 = VCVTMUS |
| 8031 | { 2360, 2, 1, 4, 1207, 0, 0, 1801, ARMImpOpBase + 0, 0, 0x8780ULL }, // Inst #2360 = VCVTMUH |
| 8032 | { 2359, 2, 1, 4, 1252, 0, 0, 1799, ARMImpOpBase + 0, 0, 0x8780ULL }, // Inst #2359 = VCVTMUD |
| 8033 | { 2358, 2, 1, 4, 1249, 0, 0, 1803, ARMImpOpBase + 0, 0, 0x8780ULL }, // Inst #2358 = VCVTMSS |
| 8034 | { 2357, 2, 1, 4, 1207, 0, 0, 1801, ARMImpOpBase + 0, 0, 0x8780ULL }, // Inst #2357 = VCVTMSH |
| 8035 | { 2356, 2, 1, 4, 1252, 0, 0, 1799, ARMImpOpBase + 0, 0, 0x8780ULL }, // Inst #2356 = VCVTMSD |
| 8036 | { 2355, 2, 1, 4, 553, 0, 0, 625, ARMImpOpBase + 0, 0, 0x11000ULL }, // Inst #2355 = VCVTMNUQh |
| 8037 | { 2354, 2, 1, 4, 553, 0, 0, 625, ARMImpOpBase + 0, 0, 0x11000ULL }, // Inst #2354 = VCVTMNUQf |
| 8038 | { 2353, 2, 1, 4, 553, 0, 0, 1797, ARMImpOpBase + 0, 0, 0x11000ULL }, // Inst #2353 = VCVTMNUDh |
| 8039 | { 2352, 2, 1, 4, 553, 0, 0, 1797, ARMImpOpBase + 0, 0, 0x11000ULL }, // Inst #2352 = VCVTMNUDf |
| 8040 | { 2351, 2, 1, 4, 553, 0, 0, 625, ARMImpOpBase + 0, 0, 0x11000ULL }, // Inst #2351 = VCVTMNSQh |
| 8041 | { 2350, 2, 1, 4, 553, 0, 0, 625, ARMImpOpBase + 0, 0, 0x11000ULL }, // Inst #2350 = VCVTMNSQf |
| 8042 | { 2349, 2, 1, 4, 553, 0, 0, 1797, ARMImpOpBase + 0, 0, 0x11000ULL }, // Inst #2349 = VCVTMNSDh |
| 8043 | { 2348, 2, 1, 4, 553, 0, 0, 1797, ARMImpOpBase + 0, 0, 0x11000ULL }, // Inst #2348 = VCVTMNSDf |
| 8044 | { 2347, 4, 1, 4, 557, 0, 0, 1810, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x8780ULL }, // Inst #2347 = VCVTDS |
| 8045 | { 2346, 5, 1, 4, 556, 0, 0, 408, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x8780ULL }, // Inst #2346 = VCVTBSH |
| 8046 | { 2345, 4, 1, 4, 555, 0, 0, 1691, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x8780ULL }, // Inst #2345 = VCVTBHS |
| 8047 | { 2344, 4, 1, 4, 554, 0, 0, 1810, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x8780ULL }, // Inst #2344 = VCVTBHD |
| 8048 | { 2343, 5, 1, 4, 957, 0, 0, 1805, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x8780ULL }, // Inst #2343 = VCVTBDH |
| 8049 | { 2342, 2, 1, 4, 1249, 0, 0, 1803, ARMImpOpBase + 0, 0, 0x8780ULL }, // Inst #2342 = VCVTAUS |
| 8050 | { 2341, 2, 1, 4, 1207, 0, 0, 1801, ARMImpOpBase + 0, 0, 0x8780ULL }, // Inst #2341 = VCVTAUH |
| 8051 | { 2340, 2, 1, 4, 1252, 0, 0, 1799, ARMImpOpBase + 0, 0, 0x8780ULL }, // Inst #2340 = VCVTAUD |
| 8052 | { 2339, 2, 1, 4, 1249, 0, 0, 1803, ARMImpOpBase + 0, 0, 0x8780ULL }, // Inst #2339 = VCVTASS |
| 8053 | { 2338, 2, 1, 4, 1207, 0, 0, 1801, ARMImpOpBase + 0, 0, 0x8780ULL }, // Inst #2338 = VCVTASH |
| 8054 | { 2337, 2, 1, 4, 1252, 0, 0, 1799, ARMImpOpBase + 0, 0, 0x8780ULL }, // Inst #2337 = VCVTASD |
| 8055 | { 2336, 2, 1, 4, 553, 0, 0, 625, ARMImpOpBase + 0, 0, 0x11000ULL }, // Inst #2336 = VCVTANUQh |
| 8056 | { 2335, 2, 1, 4, 553, 0, 0, 625, ARMImpOpBase + 0, 0, 0x11000ULL }, // Inst #2335 = VCVTANUQf |
| 8057 | { 2334, 2, 1, 4, 553, 0, 0, 1797, ARMImpOpBase + 0, 0, 0x11000ULL }, // Inst #2334 = VCVTANUDh |
| 8058 | { 2333, 2, 1, 4, 553, 0, 0, 1797, ARMImpOpBase + 0, 0, 0x11000ULL }, // Inst #2333 = VCVTANUDf |
| 8059 | { 2332, 2, 1, 4, 553, 0, 0, 625, ARMImpOpBase + 0, 0, 0x11000ULL }, // Inst #2332 = VCVTANSQh |
| 8060 | { 2331, 2, 1, 4, 553, 0, 0, 625, ARMImpOpBase + 0, 0, 0x11000ULL }, // Inst #2331 = VCVTANSQf |
| 8061 | { 2330, 2, 1, 4, 553, 0, 0, 1797, ARMImpOpBase + 0, 0, 0x11000ULL }, // Inst #2330 = VCVTANSDh |
| 8062 | { 2329, 2, 1, 4, 553, 0, 0, 1797, ARMImpOpBase + 0, 0, 0x11000ULL }, // Inst #2329 = VCVTANSDf |
| 8063 | { 2328, 4, 1, 4, 767, 0, 0, 1695, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2328 = VCNTq |
| 8064 | { 2327, 4, 1, 4, 768, 0, 0, 1683, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2327 = VCNTd |
| 8065 | { 2326, 3, 0, 4, 519, 0, 1, 1794, ARMImpOpBase + 70, 0|(1ULL<<MCID::Predicable), 0x28780ULL }, // Inst #2326 = VCMPZS |
| 8066 | { 2325, 3, 0, 4, 769, 0, 1, 1791, ARMImpOpBase + 70, 0, 0x8780ULL }, // Inst #2325 = VCMPZH |
| 8067 | { 2324, 3, 0, 4, 518, 0, 1, 1788, ARMImpOpBase + 70, 0|(1ULL<<MCID::Predicable), 0x8780ULL }, // Inst #2324 = VCMPZD |
| 8068 | { 2323, 4, 0, 4, 1256, 0, 1, 1691, ARMImpOpBase + 70, 0|(1ULL<<MCID::Predicable), 0x28780ULL }, // Inst #2323 = VCMPS |
| 8069 | { 2322, 4, 0, 4, 769, 0, 1, 1687, ARMImpOpBase + 70, 0, 0x8780ULL }, // Inst #2322 = VCMPH |
| 8070 | { 2321, 3, 0, 4, 519, 0, 1, 1794, ARMImpOpBase + 70, 0|(1ULL<<MCID::Predicable), 0x28780ULL }, // Inst #2321 = VCMPEZS |
| 8071 | { 2320, 3, 0, 4, 769, 0, 1, 1791, ARMImpOpBase + 70, 0, 0x8780ULL }, // Inst #2320 = VCMPEZH |
| 8072 | { 2319, 3, 0, 4, 518, 0, 1, 1788, ARMImpOpBase + 70, 0|(1ULL<<MCID::Predicable), 0x8780ULL }, // Inst #2319 = VCMPEZD |
| 8073 | { 2318, 4, 0, 4, 519, 0, 1, 1691, ARMImpOpBase + 70, 0|(1ULL<<MCID::Predicable), 0x28780ULL }, // Inst #2318 = VCMPES |
| 8074 | { 2317, 4, 0, 4, 769, 0, 1, 1687, ARMImpOpBase + 70, 0, 0x8780ULL }, // Inst #2317 = VCMPEH |
| 8075 | { 2316, 4, 0, 4, 518, 0, 1, 1683, ARMImpOpBase + 70, 0|(1ULL<<MCID::Predicable), 0x8780ULL }, // Inst #2316 = VCMPED |
| 8076 | { 2315, 4, 0, 4, 1257, 0, 1, 1683, ARMImpOpBase + 70, 0|(1ULL<<MCID::Predicable), 0x8780ULL }, // Inst #2315 = VCMPD |
| 8077 | { 2314, 6, 1, 4, 993, 0, 0, 1782, ARMImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x11580ULL }, // Inst #2314 = VCMLAv8f16_indexed |
| 8078 | { 2313, 5, 1, 4, 993, 0, 0, 1771, ARMImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x11580ULL }, // Inst #2313 = VCMLAv8f16 |
| 8079 | { 2312, 6, 1, 4, 993, 0, 0, 1776, ARMImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x11580ULL }, // Inst #2312 = VCMLAv4f32_indexed |
| 8080 | { 2311, 5, 1, 4, 993, 0, 0, 1771, ARMImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x11580ULL }, // Inst #2311 = VCMLAv4f32 |
| 8081 | { 2310, 6, 1, 4, 992, 0, 0, 1765, ARMImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x11580ULL }, // Inst #2310 = VCMLAv4f16_indexed |
| 8082 | { 2309, 5, 1, 4, 992, 0, 0, 1754, ARMImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x11580ULL }, // Inst #2309 = VCMLAv4f16 |
| 8083 | { 2308, 6, 1, 4, 992, 0, 0, 1759, ARMImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x11580ULL }, // Inst #2308 = VCMLAv2f32_indexed |
| 8084 | { 2307, 5, 1, 4, 992, 0, 0, 1754, ARMImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x11580ULL }, // Inst #2307 = VCMLAv2f32 |
| 8085 | { 2306, 4, 1, 4, 768, 0, 0, 1683, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2306 = VCLZv8i8 |
| 8086 | { 2305, 4, 1, 4, 767, 0, 0, 1695, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2305 = VCLZv8i16 |
| 8087 | { 2304, 4, 1, 4, 767, 0, 0, 1695, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2304 = VCLZv4i32 |
| 8088 | { 2303, 4, 1, 4, 768, 0, 0, 1683, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2303 = VCLZv4i16 |
| 8089 | { 2302, 4, 1, 4, 768, 0, 0, 1683, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2302 = VCLZv2i32 |
| 8090 | { 2301, 4, 1, 4, 767, 0, 0, 1695, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2301 = VCLZv16i8 |
| 8091 | { 2300, 4, 1, 4, 487, 0, 0, 1683, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2300 = VCLTzv8i8 |
| 8092 | { 2299, 4, 1, 4, 487, 0, 0, 1695, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2299 = VCLTzv8i16 |
| 8093 | { 2298, 4, 1, 4, 487, 0, 0, 1695, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2298 = VCLTzv8f16 |
| 8094 | { 2297, 4, 1, 4, 487, 0, 0, 1695, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2297 = VCLTzv4i32 |
| 8095 | { 2296, 4, 1, 4, 487, 0, 0, 1683, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2296 = VCLTzv4i16 |
| 8096 | { 2295, 4, 1, 4, 487, 0, 0, 1695, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2295 = VCLTzv4f32 |
| 8097 | { 2294, 4, 1, 4, 487, 0, 0, 1683, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2294 = VCLTzv4f16 |
| 8098 | { 2293, 4, 1, 4, 487, 0, 0, 1683, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2293 = VCLTzv2i32 |
| 8099 | { 2292, 4, 1, 4, 487, 0, 0, 1683, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2292 = VCLTzv2f32 |
| 8100 | { 2291, 4, 1, 4, 487, 0, 0, 1695, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2291 = VCLTzv16i8 |
| 8101 | { 2290, 4, 1, 4, 474, 0, 0, 1683, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2290 = VCLSv8i8 |
| 8102 | { 2289, 4, 1, 4, 473, 0, 0, 1695, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2289 = VCLSv8i16 |
| 8103 | { 2288, 4, 1, 4, 473, 0, 0, 1695, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2288 = VCLSv4i32 |
| 8104 | { 2287, 4, 1, 4, 474, 0, 0, 1683, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2287 = VCLSv4i16 |
| 8105 | { 2286, 4, 1, 4, 474, 0, 0, 1683, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2286 = VCLSv2i32 |
| 8106 | { 2285, 4, 1, 4, 473, 0, 0, 1695, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2285 = VCLSv16i8 |
| 8107 | { 2284, 4, 1, 4, 487, 0, 0, 1683, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2284 = VCLEzv8i8 |
| 8108 | { 2283, 4, 1, 4, 487, 0, 0, 1695, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2283 = VCLEzv8i16 |
| 8109 | { 2282, 4, 1, 4, 487, 0, 0, 1695, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2282 = VCLEzv8f16 |
| 8110 | { 2281, 4, 1, 4, 487, 0, 0, 1695, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2281 = VCLEzv4i32 |
| 8111 | { 2280, 4, 1, 4, 487, 0, 0, 1683, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2280 = VCLEzv4i16 |
| 8112 | { 2279, 4, 1, 4, 487, 0, 0, 1695, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2279 = VCLEzv4f32 |
| 8113 | { 2278, 4, 1, 4, 487, 0, 0, 1683, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2278 = VCLEzv4f16 |
| 8114 | { 2277, 4, 1, 4, 487, 0, 0, 1683, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2277 = VCLEzv2i32 |
| 8115 | { 2276, 4, 1, 4, 487, 0, 0, 1683, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2276 = VCLEzv2f32 |
| 8116 | { 2275, 4, 1, 4, 487, 0, 0, 1695, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2275 = VCLEzv16i8 |
| 8117 | { 2274, 4, 1, 4, 487, 0, 0, 1683, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2274 = VCGTzv8i8 |
| 8118 | { 2273, 4, 1, 4, 487, 0, 0, 1695, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2273 = VCGTzv8i16 |
| 8119 | { 2272, 4, 1, 4, 487, 0, 0, 1695, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2272 = VCGTzv8f16 |
| 8120 | { 2271, 4, 1, 4, 487, 0, 0, 1695, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2271 = VCGTzv4i32 |
| 8121 | { 2270, 4, 1, 4, 487, 0, 0, 1683, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2270 = VCGTzv4i16 |
| 8122 | { 2269, 4, 1, 4, 487, 0, 0, 1695, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2269 = VCGTzv4f32 |
| 8123 | { 2268, 4, 1, 4, 487, 0, 0, 1683, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2268 = VCGTzv4f16 |
| 8124 | { 2267, 4, 1, 4, 487, 0, 0, 1683, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2267 = VCGTzv2i32 |
| 8125 | { 2266, 4, 1, 4, 487, 0, 0, 1683, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2266 = VCGTzv2f32 |
| 8126 | { 2265, 4, 1, 4, 487, 0, 0, 1695, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2265 = VCGTzv16i8 |
| 8127 | { 2264, 5, 1, 4, 766, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2264 = VCGTuv8i8 |
| 8128 | { 2263, 5, 1, 4, 765, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2263 = VCGTuv8i16 |
| 8129 | { 2262, 5, 1, 4, 765, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2262 = VCGTuv4i32 |
| 8130 | { 2261, 5, 1, 4, 766, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2261 = VCGTuv4i16 |
| 8131 | { 2260, 5, 1, 4, 766, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2260 = VCGTuv2i32 |
| 8132 | { 2259, 5, 1, 4, 765, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2259 = VCGTuv16i8 |
| 8133 | { 2258, 5, 1, 4, 766, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2258 = VCGTsv8i8 |
| 8134 | { 2257, 5, 1, 4, 765, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2257 = VCGTsv8i16 |
| 8135 | { 2256, 5, 1, 4, 765, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2256 = VCGTsv4i32 |
| 8136 | { 2255, 5, 1, 4, 766, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2255 = VCGTsv4i16 |
| 8137 | { 2254, 5, 1, 4, 766, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2254 = VCGTsv2i32 |
| 8138 | { 2253, 5, 1, 4, 765, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2253 = VCGTsv16i8 |
| 8139 | { 2252, 5, 1, 4, 484, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2252 = VCGThq |
| 8140 | { 2251, 5, 1, 4, 483, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2251 = VCGThd |
| 8141 | { 2250, 5, 1, 4, 484, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2250 = VCGTfq |
| 8142 | { 2249, 5, 1, 4, 483, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2249 = VCGTfd |
| 8143 | { 2248, 4, 1, 4, 487, 0, 0, 1683, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2248 = VCGEzv8i8 |
| 8144 | { 2247, 4, 1, 4, 487, 0, 0, 1695, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2247 = VCGEzv8i16 |
| 8145 | { 2246, 4, 1, 4, 487, 0, 0, 1695, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2246 = VCGEzv8f16 |
| 8146 | { 2245, 4, 1, 4, 487, 0, 0, 1695, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2245 = VCGEzv4i32 |
| 8147 | { 2244, 4, 1, 4, 487, 0, 0, 1683, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2244 = VCGEzv4i16 |
| 8148 | { 2243, 4, 1, 4, 487, 0, 0, 1695, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2243 = VCGEzv4f32 |
| 8149 | { 2242, 4, 1, 4, 487, 0, 0, 1683, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2242 = VCGEzv4f16 |
| 8150 | { 2241, 4, 1, 4, 487, 0, 0, 1683, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2241 = VCGEzv2i32 |
| 8151 | { 2240, 4, 1, 4, 487, 0, 0, 1683, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2240 = VCGEzv2f32 |
| 8152 | { 2239, 4, 1, 4, 487, 0, 0, 1695, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2239 = VCGEzv16i8 |
| 8153 | { 2238, 5, 1, 4, 766, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2238 = VCGEuv8i8 |
| 8154 | { 2237, 5, 1, 4, 765, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2237 = VCGEuv8i16 |
| 8155 | { 2236, 5, 1, 4, 765, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2236 = VCGEuv4i32 |
| 8156 | { 2235, 5, 1, 4, 766, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2235 = VCGEuv4i16 |
| 8157 | { 2234, 5, 1, 4, 766, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2234 = VCGEuv2i32 |
| 8158 | { 2233, 5, 1, 4, 765, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2233 = VCGEuv16i8 |
| 8159 | { 2232, 5, 1, 4, 766, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2232 = VCGEsv8i8 |
| 8160 | { 2231, 5, 1, 4, 765, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2231 = VCGEsv8i16 |
| 8161 | { 2230, 5, 1, 4, 765, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2230 = VCGEsv4i32 |
| 8162 | { 2229, 5, 1, 4, 766, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2229 = VCGEsv4i16 |
| 8163 | { 2228, 5, 1, 4, 766, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2228 = VCGEsv2i32 |
| 8164 | { 2227, 5, 1, 4, 765, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2227 = VCGEsv16i8 |
| 8165 | { 2226, 5, 1, 4, 484, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2226 = VCGEhq |
| 8166 | { 2225, 5, 1, 4, 483, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2225 = VCGEhd |
| 8167 | { 2224, 5, 1, 4, 484, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2224 = VCGEfq |
| 8168 | { 2223, 5, 1, 4, 483, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2223 = VCGEfd |
| 8169 | { 2222, 4, 1, 4, 487, 0, 0, 1683, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2222 = VCEQzv8i8 |
| 8170 | { 2221, 4, 1, 4, 487, 0, 0, 1695, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2221 = VCEQzv8i16 |
| 8171 | { 2220, 4, 1, 4, 487, 0, 0, 1695, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2220 = VCEQzv8f16 |
| 8172 | { 2219, 4, 1, 4, 487, 0, 0, 1695, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2219 = VCEQzv4i32 |
| 8173 | { 2218, 4, 1, 4, 487, 0, 0, 1683, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2218 = VCEQzv4i16 |
| 8174 | { 2217, 4, 1, 4, 487, 0, 0, 1695, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2217 = VCEQzv4f32 |
| 8175 | { 2216, 4, 1, 4, 487, 0, 0, 1683, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2216 = VCEQzv4f16 |
| 8176 | { 2215, 4, 1, 4, 487, 0, 0, 1683, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2215 = VCEQzv2i32 |
| 8177 | { 2214, 4, 1, 4, 487, 0, 0, 1683, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2214 = VCEQzv2f32 |
| 8178 | { 2213, 4, 1, 4, 487, 0, 0, 1695, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2213 = VCEQzv16i8 |
| 8179 | { 2212, 5, 1, 4, 766, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2212 = VCEQv8i8 |
| 8180 | { 2211, 5, 1, 4, 765, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2211 = VCEQv8i16 |
| 8181 | { 2210, 5, 1, 4, 765, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2210 = VCEQv4i32 |
| 8182 | { 2209, 5, 1, 4, 766, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2209 = VCEQv4i16 |
| 8183 | { 2208, 5, 1, 4, 766, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2208 = VCEQv2i32 |
| 8184 | { 2207, 5, 1, 4, 765, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2207 = VCEQv16i8 |
| 8185 | { 2206, 5, 1, 4, 484, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2206 = VCEQhq |
| 8186 | { 2205, 5, 1, 4, 483, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2205 = VCEQhd |
| 8187 | { 2204, 5, 1, 4, 484, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2204 = VCEQfq |
| 8188 | { 2203, 5, 1, 4, 483, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2203 = VCEQfd |
| 8189 | { 2202, 4, 1, 4, 993, 0, 0, 1750, ARMImpOpBase + 0, 0, 0x11580ULL }, // Inst #2202 = VCADDv8f16 |
| 8190 | { 2201, 4, 1, 4, 993, 0, 0, 1750, ARMImpOpBase + 0, 0, 0x11580ULL }, // Inst #2201 = VCADDv4f32 |
| 8191 | { 2200, 4, 1, 4, 992, 0, 0, 1746, ARMImpOpBase + 0, 0, 0x11580ULL }, // Inst #2200 = VCADDv4f16 |
| 8192 | { 2199, 4, 1, 4, 992, 0, 0, 1746, ARMImpOpBase + 0, 0, 0x11580ULL }, // Inst #2199 = VCADDv2f32 |
| 8193 | { 2198, 6, 1, 4, 764, 0, 0, 1740, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x10000ULL }, // Inst #2198 = VBSPq |
| 8194 | { 2197, 6, 1, 4, 763, 0, 0, 1734, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x10000ULL }, // Inst #2197 = VBSPd |
| 8195 | { 2196, 6, 1, 4, 764, 0, 0, 1656, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11280ULL }, // Inst #2196 = VBSLq |
| 8196 | { 2195, 6, 1, 4, 763, 0, 0, 1662, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11280ULL }, // Inst #2195 = VBSLd |
| 8197 | { 2194, 6, 1, 4, 764, 0, 0, 1656, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11280ULL }, // Inst #2194 = VBITq |
| 8198 | { 2193, 6, 1, 4, 763, 0, 0, 1662, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11280ULL }, // Inst #2193 = VBITd |
| 8199 | { 2192, 6, 1, 4, 764, 0, 0, 1656, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11280ULL }, // Inst #2192 = VBIFq |
| 8200 | { 2191, 6, 1, 4, 763, 0, 0, 1662, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11280ULL }, // Inst #2191 = VBIFd |
| 8201 | { 2190, 5, 1, 4, 760, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2190 = VBICq |
| 8202 | { 2189, 5, 1, 4, 762, 0, 0, 1729, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x10f80ULL }, // Inst #2189 = VBICiv8i16 |
| 8203 | { 2188, 5, 1, 4, 762, 0, 0, 1729, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x10f80ULL }, // Inst #2188 = VBICiv4i32 |
| 8204 | { 2187, 5, 1, 4, 761, 0, 0, 1724, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x10f80ULL }, // Inst #2187 = VBICiv4i16 |
| 8205 | { 2186, 5, 1, 4, 761, 0, 0, 1724, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x10f80ULL }, // Inst #2186 = VBICiv2i32 |
| 8206 | { 2185, 5, 1, 4, 759, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2185 = VBICd |
| 8207 | { 2184, 5, 1, 4, 116, 0, 0, 1719, ARMImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x11580ULL }, // Inst #2184 = VBF16MALTQI |
| 8208 | { 2183, 4, 1, 4, 0, 0, 0, 641, ARMImpOpBase + 0, 0, 0x11580ULL }, // Inst #2183 = VBF16MALTQ |
| 8209 | { 2182, 5, 1, 4, 116, 0, 0, 1719, ARMImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x11580ULL }, // Inst #2182 = VBF16MALBQI |
| 8210 | { 2181, 4, 1, 4, 0, 0, 0, 641, ARMImpOpBase + 0, 0, 0x11580ULL }, // Inst #2181 = VBF16MALBQ |
| 8211 | { 2180, 5, 1, 4, 760, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2180 = VANDq |
| 8212 | { 2179, 5, 1, 4, 759, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2179 = VANDd |
| 8213 | { 2178, 5, 1, 4, 755, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2178 = VADDv8i8 |
| 8214 | { 2177, 5, 1, 4, 757, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2177 = VADDv8i16 |
| 8215 | { 2176, 5, 1, 4, 757, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2176 = VADDv4i32 |
| 8216 | { 2175, 5, 1, 4, 755, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2175 = VADDv4i16 |
| 8217 | { 2174, 5, 1, 4, 757, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2174 = VADDv2i64 |
| 8218 | { 2173, 5, 1, 4, 755, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2173 = VADDv2i32 |
| 8219 | { 2172, 5, 1, 4, 755, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2172 = VADDv1i64 |
| 8220 | { 2171, 5, 1, 4, 757, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2171 = VADDv16i8 |
| 8221 | { 2170, 5, 1, 4, 746, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2170 = VADDhq |
| 8222 | { 2169, 5, 1, 4, 744, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2169 = VADDhd |
| 8223 | { 2168, 5, 1, 4, 745, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2168 = VADDfq |
| 8224 | { 2167, 5, 1, 4, 743, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2167 = VADDfd |
| 8225 | { 2166, 5, 1, 4, 461, 0, 0, 1714, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2166 = VADDWuv8i16 |
| 8226 | { 2165, 5, 1, 4, 461, 0, 0, 1714, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2165 = VADDWuv4i32 |
| 8227 | { 2164, 5, 1, 4, 461, 0, 0, 1714, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2164 = VADDWuv2i64 |
| 8228 | { 2163, 5, 1, 4, 461, 0, 0, 1714, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2163 = VADDWsv8i16 |
| 8229 | { 2162, 5, 1, 4, 461, 0, 0, 1714, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2162 = VADDWsv4i32 |
| 8230 | { 2161, 5, 1, 4, 461, 0, 0, 1714, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2161 = VADDWsv2i64 |
| 8231 | { 2160, 5, 1, 4, 520, 0, 0, 1709, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x28800ULL }, // Inst #2160 = VADDS |
| 8232 | { 2159, 5, 1, 4, 758, 0, 0, 1668, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2159 = VADDLuv8i16 |
| 8233 | { 2158, 5, 1, 4, 758, 0, 0, 1668, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2158 = VADDLuv4i32 |
| 8234 | { 2157, 5, 1, 4, 758, 0, 0, 1668, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2157 = VADDLuv2i64 |
| 8235 | { 2156, 5, 1, 4, 758, 0, 0, 1668, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2156 = VADDLsv8i16 |
| 8236 | { 2155, 5, 1, 4, 758, 0, 0, 1668, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2155 = VADDLsv4i32 |
| 8237 | { 2154, 5, 1, 4, 758, 0, 0, 1668, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2154 = VADDLsv2i64 |
| 8238 | { 2153, 5, 1, 4, 500, 0, 0, 1704, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2153 = VADDHNv8i8 |
| 8239 | { 2152, 5, 1, 4, 500, 0, 0, 1704, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2152 = VADDHNv4i16 |
| 8240 | { 2151, 5, 1, 4, 500, 0, 0, 1704, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2151 = VADDHNv2i32 |
| 8241 | { 2150, 5, 1, 4, 742, 0, 0, 1699, ARMImpOpBase + 0, 0, 0x8800ULL }, // Inst #2150 = VADDH |
| 8242 | { 2149, 5, 1, 4, 526, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x8800ULL }, // Inst #2149 = VADDD |
| 8243 | { 2148, 5, 1, 4, 741, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2148 = VACGThq |
| 8244 | { 2147, 5, 1, 4, 740, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2147 = VACGThd |
| 8245 | { 2146, 5, 1, 4, 741, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2146 = VACGTfq |
| 8246 | { 2145, 5, 1, 4, 740, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2145 = VACGTfd |
| 8247 | { 2144, 5, 1, 4, 741, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2144 = VACGEhq |
| 8248 | { 2143, 5, 1, 4, 740, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2143 = VACGEhd |
| 8249 | { 2142, 5, 1, 4, 741, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2142 = VACGEfq |
| 8250 | { 2141, 5, 1, 4, 740, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2141 = VACGEfd |
| 8251 | { 2140, 4, 1, 4, 493, 0, 0, 1683, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2140 = VABSv8i8 |
| 8252 | { 2139, 4, 1, 4, 492, 0, 0, 1695, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2139 = VABSv8i16 |
| 8253 | { 2138, 4, 1, 4, 492, 0, 0, 1695, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2138 = VABSv4i32 |
| 8254 | { 2137, 4, 1, 4, 493, 0, 0, 1683, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2137 = VABSv4i16 |
| 8255 | { 2136, 4, 1, 4, 493, 0, 0, 1683, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2136 = VABSv2i32 |
| 8256 | { 2135, 4, 1, 4, 492, 0, 0, 1695, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2135 = VABSv16i8 |
| 8257 | { 2134, 4, 1, 4, 739, 0, 0, 1695, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2134 = VABShq |
| 8258 | { 2133, 4, 1, 4, 738, 0, 0, 1683, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2133 = VABShd |
| 8259 | { 2132, 4, 1, 4, 491, 0, 0, 1695, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2132 = VABSfq |
| 8260 | { 2131, 4, 1, 4, 490, 0, 0, 1683, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // Inst #2131 = VABSfd |
| 8261 | { 2130, 4, 1, 4, 737, 0, 0, 1691, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x28780ULL }, // Inst #2130 = VABSS |
| 8262 | { 2129, 4, 1, 4, 736, 0, 0, 1687, ARMImpOpBase + 0, 0, 0x8780ULL }, // Inst #2129 = VABSH |
| 8263 | { 2128, 4, 1, 4, 735, 0, 0, 1683, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x8780ULL }, // Inst #2128 = VABSD |
| 8264 | { 2127, 5, 1, 4, 752, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2127 = VABDuv8i8 |
| 8265 | { 2126, 5, 1, 4, 753, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2126 = VABDuv8i16 |
| 8266 | { 2125, 5, 1, 4, 753, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2125 = VABDuv4i32 |
| 8267 | { 2124, 5, 1, 4, 752, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2124 = VABDuv4i16 |
| 8268 | { 2123, 5, 1, 4, 752, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2123 = VABDuv2i32 |
| 8269 | { 2122, 5, 1, 4, 753, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2122 = VABDuv16i8 |
| 8270 | { 2121, 5, 1, 4, 752, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2121 = VABDsv8i8 |
| 8271 | { 2120, 5, 1, 4, 753, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2120 = VABDsv8i16 |
| 8272 | { 2119, 5, 1, 4, 753, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2119 = VABDsv4i32 |
| 8273 | { 2118, 5, 1, 4, 752, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2118 = VABDsv4i16 |
| 8274 | { 2117, 5, 1, 4, 752, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2117 = VABDsv2i32 |
| 8275 | { 2116, 5, 1, 4, 753, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2116 = VABDsv16i8 |
| 8276 | { 2115, 5, 1, 4, 734, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2115 = VABDhq |
| 8277 | { 2114, 5, 1, 4, 733, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2114 = VABDhd |
| 8278 | { 2113, 5, 1, 4, 734, 0, 0, 1678, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2113 = VABDfq |
| 8279 | { 2112, 5, 1, 4, 733, 0, 0, 1673, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2112 = VABDfd |
| 8280 | { 2111, 5, 1, 4, 754, 0, 0, 1668, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2111 = VABDLuv8i16 |
| 8281 | { 2110, 5, 1, 4, 754, 0, 0, 1668, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2110 = VABDLuv4i32 |
| 8282 | { 2109, 5, 1, 4, 523, 0, 0, 1668, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2109 = VABDLuv2i64 |
| 8283 | { 2108, 5, 1, 4, 754, 0, 0, 1668, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2108 = VABDLsv8i16 |
| 8284 | { 2107, 5, 1, 4, 754, 0, 0, 1668, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2107 = VABDLsv4i32 |
| 8285 | { 2106, 5, 1, 4, 523, 0, 0, 1668, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #2106 = VABDLsv2i64 |
| 8286 | { 2105, 6, 1, 4, 751, 0, 0, 1662, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2105 = VABAuv8i8 |
| 8287 | { 2104, 6, 1, 4, 480, 0, 0, 1656, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2104 = VABAuv8i16 |
| 8288 | { 2103, 6, 1, 4, 480, 0, 0, 1656, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2103 = VABAuv4i32 |
| 8289 | { 2102, 6, 1, 4, 751, 0, 0, 1662, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2102 = VABAuv4i16 |
| 8290 | { 2101, 6, 1, 4, 751, 0, 0, 1662, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2101 = VABAuv2i32 |
| 8291 | { 2100, 6, 1, 4, 480, 0, 0, 1656, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2100 = VABAuv16i8 |
| 8292 | { 2099, 6, 1, 4, 751, 0, 0, 1662, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2099 = VABAsv8i8 |
| 8293 | { 2098, 6, 1, 4, 480, 0, 0, 1656, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2098 = VABAsv8i16 |
| 8294 | { 2097, 6, 1, 4, 480, 0, 0, 1656, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2097 = VABAsv4i32 |
| 8295 | { 2096, 6, 1, 4, 751, 0, 0, 1662, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2096 = VABAsv4i16 |
| 8296 | { 2095, 6, 1, 4, 751, 0, 0, 1662, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2095 = VABAsv2i32 |
| 8297 | { 2094, 6, 1, 4, 480, 0, 0, 1656, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2094 = VABAsv16i8 |
| 8298 | { 2093, 6, 1, 4, 479, 0, 0, 1650, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2093 = VABALuv8i16 |
| 8299 | { 2092, 6, 1, 4, 479, 0, 0, 1650, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2092 = VABALuv4i32 |
| 8300 | { 2091, 6, 1, 4, 479, 0, 0, 1650, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2091 = VABALuv2i64 |
| 8301 | { 2090, 6, 1, 4, 479, 0, 0, 1650, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2090 = VABALsv8i16 |
| 8302 | { 2089, 6, 1, 4, 479, 0, 0, 1650, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2089 = VABALsv4i32 |
| 8303 | { 2088, 6, 1, 4, 479, 0, 0, 1650, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // Inst #2088 = VABALsv2i64 |
| 8304 | { 2087, 5, 1, 4, 896, 0, 0, 1637, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x700ULL }, // Inst #2087 = UXTH |
| 8305 | { 2086, 5, 1, 4, 351, 0, 0, 1637, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x700ULL }, // Inst #2086 = UXTB16 |
| 8306 | { 2085, 5, 1, 4, 896, 0, 0, 1637, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x700ULL }, // Inst #2085 = UXTB |
| 8307 | { 2084, 6, 1, 4, 899, 0, 0, 1631, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x700ULL }, // Inst #2084 = UXTAH |
| 8308 | { 2083, 6, 1, 4, 366, 0, 0, 1631, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x700ULL }, // Inst #2083 = UXTAB16 |
| 8309 | { 2082, 6, 1, 4, 899, 0, 0, 1631, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x700ULL }, // Inst #2082 = UXTAB |
| 8310 | { 2081, 5, 1, 4, 884, 0, 0, 1523, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL }, // Inst #2081 = USUB8 |
| 8311 | { 2080, 5, 1, 4, 884, 0, 0, 1523, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL }, // Inst #2080 = USUB16 |
| 8312 | { 2079, 5, 1, 4, 363, 0, 0, 1523, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL }, // Inst #2079 = USAX |
| 8313 | { 2078, 5, 1, 4, 892, 0, 0, 1570, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x680ULL }, // Inst #2078 = USAT16 |
| 8314 | { 2077, 6, 1, 4, 892, 0, 0, 1564, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x680ULL }, // Inst #2077 = USAT |
| 8315 | { 2076, 6, 1, 4, 370, 0, 0, 999, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x80ULL }, // Inst #2076 = USADA8 |
| 8316 | { 2075, 5, 1, 4, 369, 0, 0, 159, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x80ULL }, // Inst #2075 = USAD8 |
| 8317 | { 2074, 5, 1, 4, 888, 0, 0, 1523, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x200ULL }, // Inst #2074 = UQSUB8 |
| 8318 | { 2073, 5, 1, 4, 888, 0, 0, 1523, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x200ULL }, // Inst #2073 = UQSUB16 |
| 8319 | { 2072, 5, 1, 4, 890, 0, 0, 1523, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x200ULL }, // Inst #2072 = UQSAX |
| 8320 | { 2071, 5, 1, 4, 890, 0, 0, 1523, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x200ULL }, // Inst #2071 = UQASX |
| 8321 | { 2070, 5, 1, 4, 888, 0, 0, 1523, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x200ULL }, // Inst #2070 = UQADD8 |
| 8322 | { 2069, 5, 1, 4, 888, 0, 0, 1523, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x200ULL }, // Inst #2069 = UQADD16 |
| 8323 | { 2068, 7, 2, 4, 338, 0, 0, 1557, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0x80ULL }, // Inst #2068 = UMULL |
| 8324 | { 2067, 9, 2, 4, 339, 0, 0, 1540, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80ULL }, // Inst #2067 = UMLAL |
| 8325 | { 2066, 8, 2, 4, 339, 0, 0, 1642, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x80ULL }, // Inst #2066 = UMAAL |
| 8326 | { 2065, 5, 1, 4, 886, 0, 0, 1523, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x200ULL }, // Inst #2065 = UHSUB8 |
| 8327 | { 2064, 5, 1, 4, 886, 0, 0, 1523, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x200ULL }, // Inst #2064 = UHSUB16 |
| 8328 | { 2063, 5, 1, 4, 365, 0, 0, 1523, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x200ULL }, // Inst #2063 = UHSAX |
| 8329 | { 2062, 5, 1, 4, 365, 0, 0, 1523, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x200ULL }, // Inst #2062 = UHASX |
| 8330 | { 2061, 5, 1, 4, 886, 0, 0, 1523, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x200ULL }, // Inst #2061 = UHADD8 |
| 8331 | { 2060, 5, 1, 4, 886, 0, 0, 1523, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x200ULL }, // Inst #2060 = UHADD16 |
| 8332 | { 2059, 5, 1, 4, 384, 0, 0, 159, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x600ULL }, // Inst #2059 = UDIV |
| 8333 | { 2058, 1, 0, 4, 843, 0, 0, 0, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0xd00ULL }, // Inst #2058 = UDF |
| 8334 | { 2057, 6, 1, 4, 894, 0, 0, 1528, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x201ULL }, // Inst #2057 = UBFX |
| 8335 | { 2056, 5, 1, 4, 363, 0, 0, 1523, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL }, // Inst #2056 = UASX |
| 8336 | { 2055, 5, 1, 4, 884, 0, 0, 1523, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL }, // Inst #2055 = UADD8 |
| 8337 | { 2054, 5, 1, 4, 884, 0, 0, 1523, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL }, // Inst #2054 = UADD16 |
| 8338 | { 2053, 6, 0, 4, 726, 0, 1, 846, ARMImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0x281ULL }, // Inst #2053 = TSTrsr |
| 8339 | { 2052, 5, 0, 4, 725, 0, 1, 841, ARMImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0x1501ULL }, // Inst #2052 = TSTrsi |
| 8340 | { 2051, 4, 0, 4, 724, 0, 1, 837, ARMImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x201ULL }, // Inst #2051 = TSTrr |
| 8341 | { 2050, 4, 0, 4, 723, 0, 1, 243, ARMImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0x201ULL }, // Inst #2050 = TSTri |
| 8342 | { 2049, 1, 0, 4, 0, 0, 0, 0, ARMImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xd00ULL }, // Inst #2049 = TSB |
| 8343 | { 2048, 0, 0, 4, 843, 0, 0, 1, ARMImpOpBase + 0, 0|(1ULL<<MCID::Trap)|(1ULL<<MCID::UnmodeledSideEffects), 0xd00ULL }, // Inst #2048 = TRAPNaCl |
| 8344 | { 2047, 0, 0, 4, 843, 0, 0, 1, ARMImpOpBase + 0, 0|(1ULL<<MCID::Trap)|(1ULL<<MCID::UnmodeledSideEffects), 0xd00ULL }, // Inst #2047 = TRAP |
| 8345 | { 2046, 6, 0, 4, 95, 0, 1, 846, ARMImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0x281ULL }, // Inst #2046 = TEQrsr |
| 8346 | { 2045, 5, 0, 4, 94, 0, 1, 841, ARMImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0x1501ULL }, // Inst #2045 = TEQrsi |
| 8347 | { 2044, 4, 0, 4, 93, 0, 1, 837, ARMImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x201ULL }, // Inst #2044 = TEQrr |
| 8348 | { 2043, 4, 0, 4, 92, 0, 1, 243, ARMImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0x201ULL }, // Inst #2043 = TEQri |
| 8349 | { 2042, 5, 1, 4, 896, 0, 0, 1637, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x700ULL }, // Inst #2042 = SXTH |
| 8350 | { 2041, 5, 1, 4, 351, 0, 0, 1637, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x700ULL }, // Inst #2041 = SXTB16 |
| 8351 | { 2040, 5, 1, 4, 896, 0, 0, 1637, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x700ULL }, // Inst #2040 = SXTB |
| 8352 | { 2039, 6, 1, 4, 899, 0, 0, 1631, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x700ULL }, // Inst #2039 = SXTAH |
| 8353 | { 2038, 6, 1, 4, 366, 0, 0, 1631, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x700ULL }, // Inst #2038 = SXTAB16 |
| 8354 | { 2037, 6, 1, 4, 899, 0, 0, 1631, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x700ULL }, // Inst #2037 = SXTAB |
| 8355 | { 2036, 5, 1, 4, 843, 0, 0, 1626, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xd00ULL }, // Inst #2036 = SWPB |
| 8356 | { 2035, 5, 1, 4, 843, 0, 0, 1626, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xd00ULL }, // Inst #2035 = SWP |
| 8357 | { 2034, 3, 0, 4, 844, 1, 0, 858, ARMImpOpBase + 54, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // Inst #2034 = SVC |
| 8358 | { 2033, 8, 1, 4, 45, 0, 0, 614, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x281ULL }, // Inst #2033 = SUBrsr |
| 8359 | { 2032, 7, 1, 4, 3, 0, 0, 599, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x1501ULL }, // Inst #2032 = SUBrsi |
| 8360 | { 2031, 6, 1, 4, 2, 0, 0, 593, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x201ULL }, // Inst #2031 = SUBrr |
| 8361 | { 2030, 6, 1, 4, 1, 0, 0, 181, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef), 0x201ULL }, // Inst #2030 = SUBri |
| 8362 | { 2029, 6, 0, 4, 427, 0, 0, 960, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x380ULL }, // Inst #2029 = STRrs |
| 8363 | { 2028, 5, 0, 4, 425, 0, 0, 321, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x392ULL }, // Inst #2028 = STRi12 |
| 8364 | { 2027, 7, 1, 4, 947, 0, 0, 1592, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x3a2ULL }, // Inst #2027 = STR_PRE_REG |
| 8365 | { 2026, 6, 1, 4, 939, 0, 0, 1599, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x3a2ULL }, // Inst #2026 = STR_PRE_IMM |
| 8366 | { 2025, 7, 1, 4, 438, 0, 0, 1592, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x3c2ULL }, // Inst #2025 = STR_POST_REG |
| 8367 | { 2024, 7, 1, 4, 439, 0, 0, 1592, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x3c2ULL }, // Inst #2024 = STR_POST_IMM |
| 8368 | { 2023, 7, 1, 4, 438, 0, 0, 1585, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x3c2ULL }, // Inst #2023 = STRT_POST_REG |
| 8369 | { 2022, 7, 1, 4, 950, 0, 0, 1585, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x3c2ULL }, // Inst #2022 = STRT_POST_IMM |
| 8370 | { 2021, 7, 1, 4, 943, 0, 0, 1619, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x4a3ULL }, // Inst #2021 = STRH_PRE |
| 8371 | { 2020, 7, 1, 4, 436, 0, 0, 1619, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x4c3ULL }, // Inst #2020 = STRH_POST |
| 8372 | { 2019, 7, 1, 4, 436, 0, 0, 1585, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x4c3ULL }, // Inst #2019 = STRHTr |
| 8373 | { 2018, 6, 1, 4, 436, 0, 0, 1613, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x4c3ULL }, // Inst #2018 = STRHTi |
| 8374 | { 2017, 6, 0, 4, 426, 0, 0, 940, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x483ULL }, // Inst #2017 = STRH |
| 8375 | { 2016, 5, 1, 4, 429, 0, 0, 1575, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x580ULL }, // Inst #2016 = STREXH |
| 8376 | { 2015, 5, 1, 4, 429, 0, 0, 1580, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x580ULL }, // Inst #2015 = STREXD |
| 8377 | { 2014, 5, 1, 4, 429, 0, 0, 1575, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x580ULL }, // Inst #2014 = STREXB |
| 8378 | { 2013, 5, 1, 4, 429, 0, 0, 1575, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x580ULL }, // Inst #2013 = STREX |
| 8379 | { 2012, 8, 1, 4, 949, 0, 0, 1605, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4a3ULL }, // Inst #2012 = STRD_PRE |
| 8380 | { 2011, 8, 1, 4, 449, 0, 0, 1605, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4c3ULL }, // Inst #2011 = STRD_POST |
| 8381 | { 2010, 7, 0, 4, 446, 0, 0, 925, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x483ULL }, // Inst #2010 = STRD |
| 8382 | { 2009, 6, 0, 4, 428, 0, 0, 919, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x380ULL }, // Inst #2009 = STRBrs |
| 8383 | { 2008, 5, 0, 4, 937, 0, 0, 914, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x392ULL }, // Inst #2008 = STRBi12 |
| 8384 | { 2007, 7, 1, 4, 948, 0, 0, 1592, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x3a2ULL }, // Inst #2007 = STRB_PRE_REG |
| 8385 | { 2006, 6, 1, 4, 940, 0, 0, 1599, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x3a2ULL }, // Inst #2006 = STRB_PRE_IMM |
| 8386 | { 2005, 7, 1, 4, 954, 0, 0, 1592, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x3c2ULL }, // Inst #2005 = STRB_POST_REG |
| 8387 | { 2004, 7, 1, 4, 437, 0, 0, 1592, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x3c2ULL }, // Inst #2004 = STRB_POST_IMM |
| 8388 | { 2003, 7, 1, 4, 954, 0, 0, 1585, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x3c2ULL }, // Inst #2003 = STRBT_POST_REG |
| 8389 | { 2002, 7, 1, 4, 951, 0, 0, 1585, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x3c2ULL }, // Inst #2002 = STRBT_POST_IMM |
| 8390 | { 2001, 5, 1, 4, 451, 0, 0, 234, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x564ULL }, // Inst #2001 = STMIB_UPD |
| 8391 | { 2000, 4, 0, 4, 450, 0, 0, 873, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x504ULL }, // Inst #2000 = STMIB |
| 8392 | { 1999, 5, 1, 4, 451, 0, 0, 234, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x564ULL }, // Inst #1999 = STMIA_UPD |
| 8393 | { 1998, 4, 0, 4, 450, 0, 0, 873, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x504ULL }, // Inst #1998 = STMIA |
| 8394 | { 1997, 5, 1, 4, 451, 0, 0, 234, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x564ULL }, // Inst #1997 = STMDB_UPD |
| 8395 | { 1996, 4, 0, 4, 450, 0, 0, 873, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x504ULL }, // Inst #1996 = STMDB |
| 8396 | { 1995, 5, 1, 4, 451, 0, 0, 234, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x564ULL }, // Inst #1995 = STMDA_UPD |
| 8397 | { 1994, 4, 0, 4, 450, 0, 0, 873, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x504ULL }, // Inst #1994 = STMDA |
| 8398 | { 1993, 4, 0, 4, 731, 0, 0, 239, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x580ULL }, // Inst #1993 = STLH |
| 8399 | { 1992, 5, 1, 4, 731, 0, 0, 1575, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x580ULL }, // Inst #1992 = STLEXH |
| 8400 | { 1991, 5, 1, 4, 731, 0, 0, 1580, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x580ULL }, // Inst #1991 = STLEXD |
| 8401 | { 1990, 5, 1, 4, 731, 0, 0, 1575, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x580ULL }, // Inst #1990 = STLEXB |
| 8402 | { 1989, 5, 1, 4, 731, 0, 0, 1575, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x580ULL }, // Inst #1989 = STLEX |
| 8403 | { 1988, 4, 0, 4, 731, 0, 0, 239, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x580ULL }, // Inst #1988 = STLB |
| 8404 | { 1987, 4, 0, 4, 731, 0, 0, 239, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x580ULL }, // Inst #1987 = STL |
| 8405 | { 1986, 6, 0, 4, 846, 0, 0, 889, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x120ULL }, // Inst #1986 = STC_PRE |
| 8406 | { 1985, 6, 0, 4, 846, 0, 0, 889, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x140ULL }, // Inst #1985 = STC_POST |
| 8407 | { 1984, 6, 0, 4, 846, 0, 0, 895, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // Inst #1984 = STC_OPTION |
| 8408 | { 1983, 6, 0, 4, 846, 0, 0, 889, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x105ULL }, // Inst #1983 = STC_OFFSET |
| 8409 | { 1982, 6, 0, 4, 846, 0, 0, 889, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x120ULL }, // Inst #1982 = STCL_PRE |
| 8410 | { 1981, 6, 0, 4, 846, 0, 0, 889, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x140ULL }, // Inst #1981 = STCL_POST |
| 8411 | { 1980, 6, 0, 4, 846, 0, 0, 895, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // Inst #1980 = STCL_OPTION |
| 8412 | { 1979, 6, 0, 4, 846, 0, 0, 889, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x105ULL }, // Inst #1979 = STCL_OFFSET |
| 8413 | { 1978, 4, 0, 4, 846, 0, 0, 881, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x120ULL }, // Inst #1978 = STC2_PRE |
| 8414 | { 1977, 4, 0, 4, 846, 0, 0, 881, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x140ULL }, // Inst #1977 = STC2_POST |
| 8415 | { 1976, 4, 0, 4, 846, 0, 0, 885, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // Inst #1976 = STC2_OPTION |
| 8416 | { 1975, 4, 0, 4, 846, 0, 0, 881, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x105ULL }, // Inst #1975 = STC2_OFFSET |
| 8417 | { 1974, 4, 0, 4, 846, 0, 0, 881, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x120ULL }, // Inst #1974 = STC2L_PRE |
| 8418 | { 1973, 4, 0, 4, 846, 0, 0, 881, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x140ULL }, // Inst #1973 = STC2L_POST |
| 8419 | { 1972, 4, 0, 4, 846, 0, 0, 885, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // Inst #1972 = STC2L_OPTION |
| 8420 | { 1971, 4, 0, 4, 846, 0, 0, 881, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x105ULL }, // Inst #1971 = STC2L_OFFSET |
| 8421 | { 1970, 5, 1, 4, 884, 0, 0, 1523, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL }, // Inst #1970 = SSUB8 |
| 8422 | { 1969, 5, 1, 4, 884, 0, 0, 1523, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL }, // Inst #1969 = SSUB16 |
| 8423 | { 1968, 5, 1, 4, 363, 0, 0, 1523, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL }, // Inst #1968 = SSAX |
| 8424 | { 1967, 5, 1, 4, 892, 0, 0, 1570, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x680ULL }, // Inst #1967 = SSAT16 |
| 8425 | { 1966, 6, 1, 4, 892, 0, 0, 1564, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x680ULL }, // Inst #1966 = SSAT |
| 8426 | { 1965, 1, 0, 4, 729, 0, 0, 0, ARMImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // Inst #1965 = SRSIB_UPD |
| 8427 | { 1964, 1, 0, 4, 729, 0, 0, 0, ARMImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // Inst #1964 = SRSIB |
| 8428 | { 1963, 1, 0, 4, 729, 0, 0, 0, ARMImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // Inst #1963 = SRSIA_UPD |
| 8429 | { 1962, 1, 0, 4, 729, 0, 0, 0, ARMImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // Inst #1962 = SRSIA |
| 8430 | { 1961, 1, 0, 4, 729, 0, 0, 0, ARMImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // Inst #1961 = SRSDB_UPD |
| 8431 | { 1960, 1, 0, 4, 729, 0, 0, 0, ARMImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // Inst #1960 = SRSDB |
| 8432 | { 1959, 1, 0, 4, 729, 0, 0, 0, ARMImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // Inst #1959 = SRSDA_UPD |
| 8433 | { 1958, 1, 0, 4, 729, 0, 0, 0, ARMImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // Inst #1958 = SRSDA |
| 8434 | { 1957, 5, 1, 4, 371, 0, 0, 1523, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x80ULL }, // Inst #1957 = SMUSDX |
| 8435 | { 1956, 5, 1, 4, 371, 0, 0, 1523, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x80ULL }, // Inst #1956 = SMUSD |
| 8436 | { 1955, 5, 1, 4, 344, 0, 0, 159, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x80ULL }, // Inst #1955 = SMULWT |
| 8437 | { 1954, 5, 1, 4, 344, 0, 0, 159, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x80ULL }, // Inst #1954 = SMULWB |
| 8438 | { 1953, 5, 1, 4, 344, 0, 0, 159, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x80ULL }, // Inst #1953 = SMULTT |
| 8439 | { 1952, 5, 1, 4, 344, 0, 0, 159, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x80ULL }, // Inst #1952 = SMULTB |
| 8440 | { 1951, 7, 2, 4, 381, 0, 0, 1557, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0x80ULL }, // Inst #1951 = SMULL |
| 8441 | { 1950, 5, 1, 4, 344, 0, 0, 159, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x80ULL }, // Inst #1950 = SMULBT |
| 8442 | { 1949, 5, 1, 4, 344, 0, 0, 159, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x80ULL }, // Inst #1949 = SMULBB |
| 8443 | { 1948, 5, 1, 4, 343, 0, 0, 1523, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x80ULL }, // Inst #1948 = SMUADX |
| 8444 | { 1947, 5, 1, 4, 343, 0, 0, 1523, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x80ULL }, // Inst #1947 = SMUAD |
| 8445 | { 1946, 5, 1, 4, 335, 0, 0, 159, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x80ULL }, // Inst #1946 = SMMULR |
| 8446 | { 1945, 5, 1, 4, 335, 0, 0, 159, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x80ULL }, // Inst #1945 = SMMUL |
| 8447 | { 1944, 6, 1, 4, 336, 0, 0, 999, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x80ULL }, // Inst #1944 = SMMLSR |
| 8448 | { 1943, 6, 1, 4, 336, 0, 0, 999, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1943 = SMMLS |
| 8449 | { 1942, 6, 1, 4, 336, 0, 0, 999, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x80ULL }, // Inst #1942 = SMMLAR |
| 8450 | { 1941, 6, 1, 4, 336, 0, 0, 999, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x80ULL }, // Inst #1941 = SMMLA |
| 8451 | { 1940, 8, 2, 4, 342, 0, 0, 1549, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x80ULL }, // Inst #1940 = SMLSLDX |
| 8452 | { 1939, 8, 2, 4, 341, 0, 0, 1549, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x80ULL }, // Inst #1939 = SMLSLD |
| 8453 | { 1938, 6, 1, 4, 377, 0, 0, 1534, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x80ULL }, // Inst #1938 = SMLSDX |
| 8454 | { 1937, 6, 1, 4, 377, 0, 0, 1534, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x80ULL }, // Inst #1937 = SMLSD |
| 8455 | { 1936, 6, 1, 4, 345, 0, 0, 1534, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x80ULL }, // Inst #1936 = SMLAWT |
| 8456 | { 1935, 6, 1, 4, 345, 0, 0, 1534, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x80ULL }, // Inst #1935 = SMLAWB |
| 8457 | { 1934, 6, 1, 4, 345, 0, 0, 1534, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x80ULL }, // Inst #1934 = SMLATT |
| 8458 | { 1933, 6, 1, 4, 345, 0, 0, 1534, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x80ULL }, // Inst #1933 = SMLATB |
| 8459 | { 1932, 8, 2, 4, 339, 0, 0, 1549, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x80ULL }, // Inst #1932 = SMLALTT |
| 8460 | { 1931, 8, 2, 4, 339, 0, 0, 1549, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x80ULL }, // Inst #1931 = SMLALTB |
| 8461 | { 1930, 8, 2, 4, 342, 0, 0, 1549, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x80ULL }, // Inst #1930 = SMLALDX |
| 8462 | { 1929, 8, 2, 4, 341, 0, 0, 1549, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x80ULL }, // Inst #1929 = SMLALD |
| 8463 | { 1928, 8, 2, 4, 339, 0, 0, 1549, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x80ULL }, // Inst #1928 = SMLALBT |
| 8464 | { 1927, 8, 2, 4, 339, 0, 0, 1549, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x80ULL }, // Inst #1927 = SMLALBB |
| 8465 | { 1926, 9, 2, 4, 339, 0, 0, 1540, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80ULL }, // Inst #1926 = SMLAL |
| 8466 | { 1925, 6, 1, 4, 340, 0, 0, 1534, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x80ULL }, // Inst #1925 = SMLADX |
| 8467 | { 1924, 6, 1, 4, 340, 0, 0, 1534, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x80ULL }, // Inst #1924 = SMLAD |
| 8468 | { 1923, 6, 1, 4, 345, 0, 0, 1534, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x80ULL }, // Inst #1923 = SMLABT |
| 8469 | { 1922, 6, 1, 4, 345, 0, 0, 1534, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x80ULL }, // Inst #1922 = SMLABB |
| 8470 | { 1921, 3, 0, 4, 843, 0, 0, 858, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // Inst #1921 = SMC |
| 8471 | { 1920, 5, 1, 4, 886, 0, 0, 1523, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x200ULL }, // Inst #1920 = SHSUB8 |
| 8472 | { 1919, 5, 1, 4, 886, 0, 0, 1523, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x200ULL }, // Inst #1919 = SHSUB16 |
| 8473 | { 1918, 5, 1, 4, 365, 0, 0, 1523, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x200ULL }, // Inst #1918 = SHSAX |
| 8474 | { 1917, 5, 1, 4, 365, 0, 0, 1523, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x200ULL }, // Inst #1917 = SHASX |
| 8475 | { 1916, 5, 1, 4, 886, 0, 0, 1523, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x200ULL }, // Inst #1916 = SHADD8 |
| 8476 | { 1915, 5, 1, 4, 886, 0, 0, 1523, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x200ULL }, // Inst #1915 = SHADD16 |
| 8477 | { 1914, 4, 1, 4, 1015, 0, 0, 641, ARMImpOpBase + 0, 0, 0x11280ULL }, // Inst #1914 = SHA256SU1 |
| 8478 | { 1913, 3, 1, 4, 1014, 0, 0, 622, ARMImpOpBase + 0, 0, 0x11000ULL }, // Inst #1913 = SHA256SU0 |
| 8479 | { 1912, 4, 1, 4, 1015, 0, 0, 641, ARMImpOpBase + 0, 0, 0x11280ULL }, // Inst #1912 = SHA256H2 |
| 8480 | { 1911, 4, 1, 4, 1015, 0, 0, 641, ARMImpOpBase + 0, 0, 0x11280ULL }, // Inst #1911 = SHA256H |
| 8481 | { 1910, 3, 1, 4, 1012, 0, 0, 622, ARMImpOpBase + 0, 0, 0x11000ULL }, // Inst #1910 = SHA1SU1 |
| 8482 | { 1909, 4, 1, 4, 1011, 0, 0, 641, ARMImpOpBase + 0, 0, 0x11280ULL }, // Inst #1909 = SHA1SU0 |
| 8483 | { 1908, 4, 1, 4, 1013, 0, 0, 641, ARMImpOpBase + 0, 0, 0x11280ULL }, // Inst #1908 = SHA1P |
| 8484 | { 1907, 4, 1, 4, 1013, 0, 0, 641, ARMImpOpBase + 0, 0, 0x11280ULL }, // Inst #1907 = SHA1M |
| 8485 | { 1906, 2, 1, 4, 1012, 0, 0, 625, ARMImpOpBase + 0, 0, 0x11000ULL }, // Inst #1906 = SHA1H |
| 8486 | { 1905, 4, 1, 4, 1013, 0, 0, 641, ARMImpOpBase + 0, 0, 0x11280ULL }, // Inst #1905 = SHA1C |
| 8487 | { 1904, 1, 0, 4, 843, 0, 0, 0, ARMImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xd00ULL }, // Inst #1904 = SETPAN |
| 8488 | { 1903, 1, 0, 4, 843, 0, 0, 0, ARMImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xd00ULL }, // Inst #1903 = SETEND |
| 8489 | { 1902, 5, 1, 4, 333, 0, 0, 159, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x200ULL }, // Inst #1902 = SEL |
| 8490 | { 1901, 5, 1, 4, 384, 0, 0, 159, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x600ULL }, // Inst #1901 = SDIV |
| 8491 | { 1900, 6, 1, 4, 894, 0, 0, 1528, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x201ULL }, // Inst #1900 = SBFX |
| 8492 | { 1899, 8, 1, 4, 708, 1, 1, 606, ARMImpOpBase + 63, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0x281ULL }, // Inst #1899 = SBCrsr |
| 8493 | { 1898, 7, 1, 4, 702, 1, 1, 599, ARMImpOpBase + 63, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0x1501ULL }, // Inst #1898 = SBCrsi |
| 8494 | { 1897, 6, 1, 4, 699, 1, 1, 593, ARMImpOpBase + 63, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0x201ULL }, // Inst #1897 = SBCrr |
| 8495 | { 1896, 6, 1, 4, 692, 1, 1, 181, ARMImpOpBase + 63, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0x201ULL }, // Inst #1896 = SBCri |
| 8496 | { 1895, 0, 0, 4, 0, 0, 0, 1, ARMImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xd00ULL }, // Inst #1895 = SB |
| 8497 | { 1894, 5, 1, 4, 363, 0, 0, 1523, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL }, // Inst #1894 = SASX |
| 8498 | { 1893, 5, 1, 4, 884, 0, 0, 1523, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL }, // Inst #1893 = SADD8 |
| 8499 | { 1892, 5, 1, 4, 884, 0, 0, 1523, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL }, // Inst #1892 = SADD16 |
| 8500 | { 1891, 8, 1, 4, 708, 1, 1, 614, ARMImpOpBase + 63, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0x281ULL }, // Inst #1891 = RSCrsr |
| 8501 | { 1890, 7, 1, 4, 702, 1, 1, 599, ARMImpOpBase + 63, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0x1501ULL }, // Inst #1890 = RSCrsi |
| 8502 | { 1889, 6, 1, 4, 699, 1, 1, 593, ARMImpOpBase + 63, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x201ULL }, // Inst #1889 = RSCrr |
| 8503 | { 1888, 6, 1, 4, 692, 1, 1, 181, ARMImpOpBase + 63, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0x201ULL }, // Inst #1888 = RSCri |
| 8504 | { 1887, 8, 1, 4, 708, 0, 0, 614, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x281ULL }, // Inst #1887 = RSBrsr |
| 8505 | { 1886, 7, 1, 4, 702, 0, 0, 599, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x1501ULL }, // Inst #1886 = RSBrsi |
| 8506 | { 1885, 6, 1, 4, 699, 0, 0, 593, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::UnmodeledSideEffects), 0x201ULL }, // Inst #1885 = RSBrr |
| 8507 | { 1884, 6, 1, 4, 692, 0, 0, 181, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef), 0x201ULL }, // Inst #1884 = RSBri |
| 8508 | { 1883, 1, 0, 4, 729, 0, 0, 295, ARMImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // Inst #1883 = RFEIB_UPD |
| 8509 | { 1882, 1, 0, 4, 729, 0, 0, 295, ARMImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // Inst #1882 = RFEIB |
| 8510 | { 1881, 1, 0, 4, 729, 0, 0, 295, ARMImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // Inst #1881 = RFEIA_UPD |
| 8511 | { 1880, 1, 0, 4, 729, 0, 0, 295, ARMImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // Inst #1880 = RFEIA |
| 8512 | { 1879, 1, 0, 4, 729, 0, 0, 295, ARMImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // Inst #1879 = RFEDB_UPD |
| 8513 | { 1878, 1, 0, 4, 729, 0, 0, 295, ARMImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // Inst #1878 = RFEDB |
| 8514 | { 1877, 1, 0, 4, 729, 0, 0, 295, ARMImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // Inst #1877 = RFEDA_UPD |
| 8515 | { 1876, 1, 0, 4, 729, 0, 0, 295, ARMImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // Inst #1876 = RFEDA |
| 8516 | { 1875, 4, 1, 4, 721, 0, 0, 837, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x600ULL }, // Inst #1875 = REVSH |
| 8517 | { 1874, 4, 1, 4, 721, 0, 0, 837, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x600ULL }, // Inst #1874 = REV16 |
| 8518 | { 1873, 4, 1, 4, 721, 0, 0, 837, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x600ULL }, // Inst #1873 = REV |
| 8519 | { 1872, 4, 1, 4, 721, 0, 0, 837, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x600ULL }, // Inst #1872 = RBIT |
| 8520 | { 1871, 5, 1, 4, 888, 0, 0, 1523, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL }, // Inst #1871 = QSUB8 |
| 8521 | { 1870, 5, 1, 4, 888, 0, 0, 1523, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL }, // Inst #1870 = QSUB16 |
| 8522 | { 1869, 5, 1, 4, 893, 0, 0, 1523, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL }, // Inst #1869 = QSUB |
| 8523 | { 1868, 5, 1, 4, 890, 0, 0, 1523, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x200ULL }, // Inst #1868 = QSAX |
| 8524 | { 1867, 5, 1, 4, 360, 0, 0, 1523, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL }, // Inst #1867 = QDSUB |
| 8525 | { 1866, 5, 1, 4, 360, 0, 0, 1523, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL }, // Inst #1866 = QDADD |
| 8526 | { 1865, 5, 1, 4, 890, 0, 0, 1523, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x200ULL }, // Inst #1865 = QASX |
| 8527 | { 1864, 5, 1, 4, 888, 0, 0, 1523, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL }, // Inst #1864 = QADD8 |
| 8528 | { 1863, 5, 1, 4, 888, 0, 0, 1523, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL }, // Inst #1863 = QADD16 |
| 8529 | { 1862, 5, 1, 4, 893, 0, 0, 1523, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL }, // Inst #1862 = QADD |
| 8530 | { 1861, 3, 0, 4, 934, 0, 0, 1520, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0xd00ULL }, // Inst #1861 = PLIrs |
| 8531 | { 1860, 2, 0, 4, 934, 0, 0, 1518, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0xd12ULL }, // Inst #1860 = PLIi12 |
| 8532 | { 1859, 3, 0, 4, 935, 0, 0, 1520, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0xd00ULL }, // Inst #1859 = PLDrs |
| 8533 | { 1858, 2, 0, 4, 934, 0, 0, 1518, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0xd12ULL }, // Inst #1858 = PLDi12 |
| 8534 | { 1857, 3, 0, 4, 935, 0, 0, 1520, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0xd00ULL }, // Inst #1857 = PLDWrs |
| 8535 | { 1856, 2, 0, 4, 934, 0, 0, 1518, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0xd12ULL }, // Inst #1856 = PLDWi12 |
| 8536 | { 1855, 6, 1, 4, 73, 0, 0, 1512, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x600ULL }, // Inst #1855 = PKHTB |
| 8537 | { 1854, 6, 1, 4, 39, 0, 0, 1512, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x600ULL }, // Inst #1854 = PKHBT |
| 8538 | { 1853, 8, 1, 4, 324, 0, 0, 614, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x281ULL }, // Inst #1853 = ORRrsr |
| 8539 | { 1852, 7, 1, 4, 323, 0, 0, 599, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x1501ULL }, // Inst #1852 = ORRrsi |
| 8540 | { 1851, 6, 1, 4, 322, 0, 0, 593, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0x201ULL }, // Inst #1851 = ORRrr |
| 8541 | { 1850, 6, 1, 4, 321, 0, 0, 181, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef), 0x201ULL }, // Inst #1850 = ORRri |
| 8542 | { 1849, 3, 1, 4, 996, 0, 0, 1509, ARMImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #1849 = NEON_VMINNMNQh |
| 8543 | { 1848, 3, 1, 4, 996, 0, 0, 1509, ARMImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #1848 = NEON_VMINNMNQf |
| 8544 | { 1847, 3, 1, 4, 996, 0, 0, 1506, ARMImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #1847 = NEON_VMINNMNDh |
| 8545 | { 1846, 3, 1, 4, 996, 0, 0, 1506, ARMImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #1846 = NEON_VMINNMNDf |
| 8546 | { 1845, 3, 1, 4, 996, 0, 0, 1509, ARMImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #1845 = NEON_VMAXNMNQh |
| 8547 | { 1844, 3, 1, 4, 996, 0, 0, 1509, ARMImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #1844 = NEON_VMAXNMNQf |
| 8548 | { 1843, 3, 1, 4, 996, 0, 0, 1506, ARMImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #1843 = NEON_VMAXNMNDh |
| 8549 | { 1842, 3, 1, 4, 996, 0, 0, 1506, ARMImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x11280ULL }, // Inst #1842 = NEON_VMAXNMNDf |
| 8550 | { 1841, 7, 1, 4, 326, 0, 0, 1499, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x2281ULL }, // Inst #1841 = MVNsr |
| 8551 | { 1840, 6, 1, 4, 711, 0, 0, 1020, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x3501ULL }, // Inst #1840 = MVNsi |
| 8552 | { 1839, 5, 1, 4, 328, 0, 0, 326, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x2201ULL }, // Inst #1839 = MVNr |
| 8553 | { 1838, 5, 1, 4, 710, 0, 0, 1010, ARMImpOpBase + 0, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::CheapAsAMove), 0x2201ULL }, // Inst #1838 = MVNi |
| 8554 | { 1837, 3, 1, 4, 1286, 0, 0, 511, ARMImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #1837 = MVE_WLSTP_8 |
| 8555 | { 1836, 3, 1, 4, 1286, 0, 0, 511, ARMImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #1836 = MVE_WLSTP_64 |
| 8556 | { 1835, 3, 1, 4, 1286, 0, 0, 511, ARMImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #1835 = MVE_WLSTP_32 |
| 8557 | { 1834, 3, 1, 4, 1286, 0, 0, 511, ARMImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #1834 = MVE_WLSTP_16 |
| 8558 | { 1833, 7, 1, 4, 1170, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x140c80ULL }, // Inst #1833 = MVE_VSUBi8 |
| 8559 | { 1832, 7, 1, 4, 1170, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1832 = MVE_VSUBi32 |
| 8560 | { 1831, 7, 1, 4, 1170, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1831 = MVE_VSUBi16 |
| 8561 | { 1830, 7, 1, 4, 1201, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1830 = MVE_VSUBf32 |
| 8562 | { 1829, 7, 1, 4, 1201, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1829 = MVE_VSUBf16 |
| 8563 | { 1828, 7, 1, 4, 1302, 0, 0, 1163, ARMImpOpBase + 0, 0, 0x140c80ULL }, // Inst #1828 = MVE_VSUB_qr_i8 |
| 8564 | { 1827, 7, 1, 4, 1302, 0, 0, 1163, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1827 = MVE_VSUB_qr_i32 |
| 8565 | { 1826, 7, 1, 4, 1302, 0, 0, 1163, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1826 = MVE_VSUB_qr_i16 |
| 8566 | { 1825, 7, 1, 4, 1202, 0, 0, 1163, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1825 = MVE_VSUB_qr_f32 |
| 8567 | { 1824, 7, 1, 4, 1202, 0, 0, 1163, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1824 = MVE_VSUB_qr_f16 |
| 8568 | { 1823, 7, 1, 4, 1121, 0, 0, 1316, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x2140cb5ULL }, // Inst #1823 = MVE_VSTRWU32_pre |
| 8569 | { 1822, 7, 1, 4, 1121, 0, 0, 1316, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x2140cd5ULL }, // Inst #1822 = MVE_VSTRWU32_post |
| 8570 | { 1821, 6, 0, 4, 1120, 0, 0, 1310, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x2140c95ULL }, // Inst #1821 = MVE_VSTRWU32 |
| 8571 | { 1820, 6, 0, 4, 1122, 0, 0, 1480, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x2140c80ULL }, // Inst #1820 = MVE_VSTRW32_rq_u |
| 8572 | { 1819, 6, 0, 4, 1122, 0, 0, 1480, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x2140c80ULL }, // Inst #1819 = MVE_VSTRW32_rq |
| 8573 | { 1818, 7, 1, 4, 1123, 0, 0, 1492, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x2140c80ULL }, // Inst #1818 = MVE_VSTRW32_qi_pre |
| 8574 | { 1817, 6, 0, 4, 1266, 0, 0, 1486, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x2140c80ULL }, // Inst #1817 = MVE_VSTRW32_qi |
| 8575 | { 1816, 7, 1, 4, 1121, 0, 0, 1316, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x1140cb6ULL }, // Inst #1816 = MVE_VSTRHU16_pre |
| 8576 | { 1815, 7, 1, 4, 1121, 0, 0, 1316, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x1140cd6ULL }, // Inst #1815 = MVE_VSTRHU16_post |
| 8577 | { 1814, 6, 0, 4, 1120, 0, 0, 1310, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x1140c96ULL }, // Inst #1814 = MVE_VSTRHU16 |
| 8578 | { 1813, 6, 0, 4, 1122, 0, 0, 1480, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x2140c80ULL }, // Inst #1813 = MVE_VSTRH32_rq_u |
| 8579 | { 1812, 6, 0, 4, 1122, 0, 0, 1480, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x2140c80ULL }, // Inst #1812 = MVE_VSTRH32_rq |
| 8580 | { 1811, 7, 1, 4, 1121, 0, 0, 1297, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x2140cb6ULL }, // Inst #1811 = MVE_VSTRH32_pre |
| 8581 | { 1810, 7, 1, 4, 1121, 0, 0, 1297, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x2140cd6ULL }, // Inst #1810 = MVE_VSTRH32_post |
| 8582 | { 1809, 6, 0, 4, 1120, 0, 0, 1291, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x2140c96ULL }, // Inst #1809 = MVE_VSTRH32 |
| 8583 | { 1808, 6, 0, 4, 1122, 0, 0, 1480, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x1140c80ULL }, // Inst #1808 = MVE_VSTRH16_rq_u |
| 8584 | { 1807, 6, 0, 4, 1122, 0, 0, 1480, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x1140c80ULL }, // Inst #1807 = MVE_VSTRH16_rq |
| 8585 | { 1806, 6, 0, 4, 1122, 0, 0, 1480, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x3140c80ULL }, // Inst #1806 = MVE_VSTRD64_rq_u |
| 8586 | { 1805, 6, 0, 4, 1122, 0, 0, 1480, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x3140c80ULL }, // Inst #1805 = MVE_VSTRD64_rq |
| 8587 | { 1804, 7, 1, 4, 1123, 0, 0, 1492, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x3140c80ULL }, // Inst #1804 = MVE_VSTRD64_qi_pre |
| 8588 | { 1803, 6, 0, 4, 1266, 0, 0, 1486, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x3140c80ULL }, // Inst #1803 = MVE_VSTRD64_qi |
| 8589 | { 1802, 7, 1, 4, 1121, 0, 0, 1316, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x140cb7ULL }, // Inst #1802 = MVE_VSTRBU8_pre |
| 8590 | { 1801, 7, 1, 4, 1121, 0, 0, 1316, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x140cd7ULL }, // Inst #1801 = MVE_VSTRBU8_post |
| 8591 | { 1800, 6, 0, 4, 1120, 0, 0, 1310, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x140c97ULL }, // Inst #1800 = MVE_VSTRBU8 |
| 8592 | { 1799, 6, 0, 4, 1122, 0, 0, 1480, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x140c80ULL }, // Inst #1799 = MVE_VSTRB8_rq |
| 8593 | { 1798, 6, 0, 4, 1122, 0, 0, 1480, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x2140c80ULL }, // Inst #1798 = MVE_VSTRB32_rq |
| 8594 | { 1797, 7, 1, 4, 1121, 0, 0, 1297, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x2140cb7ULL }, // Inst #1797 = MVE_VSTRB32_pre |
| 8595 | { 1796, 7, 1, 4, 1121, 0, 0, 1297, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x2140cd7ULL }, // Inst #1796 = MVE_VSTRB32_post |
| 8596 | { 1795, 6, 0, 4, 1120, 0, 0, 1291, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x2140c97ULL }, // Inst #1795 = MVE_VSTRB32 |
| 8597 | { 1794, 6, 0, 4, 1122, 0, 0, 1480, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x1140c80ULL }, // Inst #1794 = MVE_VSTRB16_rq |
| 8598 | { 1793, 7, 1, 4, 1121, 0, 0, 1297, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x1140cb7ULL }, // Inst #1793 = MVE_VSTRB16_pre |
| 8599 | { 1792, 7, 1, 4, 1121, 0, 0, 1297, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x1140cd7ULL }, // Inst #1792 = MVE_VSTRB16_post |
| 8600 | { 1791, 6, 0, 4, 1120, 0, 0, 1291, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x1140c97ULL }, // Inst #1791 = MVE_VSTRB16 |
| 8601 | { 1790, 3, 1, 4, 1124, 0, 0, 1477, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x40c80ULL }, // Inst #1790 = MVE_VST43_8_wb |
| 8602 | { 1789, 2, 0, 4, 1265, 0, 0, 1475, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x40c80ULL }, // Inst #1789 = MVE_VST43_8 |
| 8603 | { 1788, 3, 1, 4, 1124, 0, 0, 1477, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x2040c80ULL }, // Inst #1788 = MVE_VST43_32_wb |
| 8604 | { 1787, 2, 0, 4, 1265, 0, 0, 1475, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x2040c80ULL }, // Inst #1787 = MVE_VST43_32 |
| 8605 | { 1786, 3, 1, 4, 1124, 0, 0, 1477, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x1040c80ULL }, // Inst #1786 = MVE_VST43_16_wb |
| 8606 | { 1785, 2, 0, 4, 1265, 0, 0, 1475, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x1040c80ULL }, // Inst #1785 = MVE_VST43_16 |
| 8607 | { 1784, 3, 1, 4, 1124, 0, 0, 1477, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x40c80ULL }, // Inst #1784 = MVE_VST42_8_wb |
| 8608 | { 1783, 2, 0, 4, 1265, 0, 0, 1475, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x40c80ULL }, // Inst #1783 = MVE_VST42_8 |
| 8609 | { 1782, 3, 1, 4, 1124, 0, 0, 1477, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x2040c80ULL }, // Inst #1782 = MVE_VST42_32_wb |
| 8610 | { 1781, 2, 0, 4, 1265, 0, 0, 1475, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x2040c80ULL }, // Inst #1781 = MVE_VST42_32 |
| 8611 | { 1780, 3, 1, 4, 1124, 0, 0, 1477, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x1040c80ULL }, // Inst #1780 = MVE_VST42_16_wb |
| 8612 | { 1779, 2, 0, 4, 1265, 0, 0, 1475, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x1040c80ULL }, // Inst #1779 = MVE_VST42_16 |
| 8613 | { 1778, 3, 1, 4, 1124, 0, 0, 1477, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x40c80ULL }, // Inst #1778 = MVE_VST41_8_wb |
| 8614 | { 1777, 2, 0, 4, 1265, 0, 0, 1475, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x40c80ULL }, // Inst #1777 = MVE_VST41_8 |
| 8615 | { 1776, 3, 1, 4, 1124, 0, 0, 1477, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x2040c80ULL }, // Inst #1776 = MVE_VST41_32_wb |
| 8616 | { 1775, 2, 0, 4, 1265, 0, 0, 1475, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x2040c80ULL }, // Inst #1775 = MVE_VST41_32 |
| 8617 | { 1774, 3, 1, 4, 1124, 0, 0, 1477, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x1040c80ULL }, // Inst #1774 = MVE_VST41_16_wb |
| 8618 | { 1773, 2, 0, 4, 1265, 0, 0, 1475, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x1040c80ULL }, // Inst #1773 = MVE_VST41_16 |
| 8619 | { 1772, 3, 1, 4, 1124, 0, 0, 1477, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x40c80ULL }, // Inst #1772 = MVE_VST40_8_wb |
| 8620 | { 1771, 2, 0, 4, 1265, 0, 0, 1475, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x40c80ULL }, // Inst #1771 = MVE_VST40_8 |
| 8621 | { 1770, 3, 1, 4, 1124, 0, 0, 1477, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x2040c80ULL }, // Inst #1770 = MVE_VST40_32_wb |
| 8622 | { 1769, 2, 0, 4, 1265, 0, 0, 1475, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x2040c80ULL }, // Inst #1769 = MVE_VST40_32 |
| 8623 | { 1768, 3, 1, 4, 1124, 0, 0, 1477, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x1040c80ULL }, // Inst #1768 = MVE_VST40_16_wb |
| 8624 | { 1767, 2, 0, 4, 1265, 0, 0, 1475, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x1040c80ULL }, // Inst #1767 = MVE_VST40_16 |
| 8625 | { 1766, 3, 1, 4, 1124, 0, 0, 1472, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x40c80ULL }, // Inst #1766 = MVE_VST21_8_wb |
| 8626 | { 1765, 2, 0, 4, 1265, 0, 0, 1470, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x40c80ULL }, // Inst #1765 = MVE_VST21_8 |
| 8627 | { 1764, 3, 1, 4, 1124, 0, 0, 1472, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x2040c80ULL }, // Inst #1764 = MVE_VST21_32_wb |
| 8628 | { 1763, 2, 0, 4, 1265, 0, 0, 1470, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x2040c80ULL }, // Inst #1763 = MVE_VST21_32 |
| 8629 | { 1762, 3, 1, 4, 1124, 0, 0, 1472, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x1040c80ULL }, // Inst #1762 = MVE_VST21_16_wb |
| 8630 | { 1761, 2, 0, 4, 1265, 0, 0, 1470, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x1040c80ULL }, // Inst #1761 = MVE_VST21_16 |
| 8631 | { 1760, 3, 1, 4, 1124, 0, 0, 1472, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x40c80ULL }, // Inst #1760 = MVE_VST20_8_wb |
| 8632 | { 1759, 2, 0, 4, 1265, 0, 0, 1470, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x40c80ULL }, // Inst #1759 = MVE_VST20_8 |
| 8633 | { 1758, 3, 1, 4, 1124, 0, 0, 1472, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x2040c80ULL }, // Inst #1758 = MVE_VST20_32_wb |
| 8634 | { 1757, 2, 0, 4, 1265, 0, 0, 1470, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x2040c80ULL }, // Inst #1757 = MVE_VST20_32 |
| 8635 | { 1756, 3, 1, 4, 1124, 0, 0, 1472, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x1040c80ULL }, // Inst #1756 = MVE_VST20_16_wb |
| 8636 | { 1755, 2, 0, 4, 1265, 0, 0, 1470, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x1040c80ULL }, // Inst #1755 = MVE_VST20_16 |
| 8637 | { 1754, 7, 1, 4, 1169, 0, 0, 1449, ARMImpOpBase + 0, 0, 0x140c80ULL }, // Inst #1754 = MVE_VSRIimm8 |
| 8638 | { 1753, 7, 1, 4, 1169, 0, 0, 1449, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1753 = MVE_VSRIimm32 |
| 8639 | { 1752, 7, 1, 4, 1169, 0, 0, 1449, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1752 = MVE_VSRIimm16 |
| 8640 | { 1751, 7, 1, 4, 1168, 0, 0, 1449, ARMImpOpBase + 0, 0, 0x140c80ULL }, // Inst #1751 = MVE_VSLIimm8 |
| 8641 | { 1750, 7, 1, 4, 1168, 0, 0, 1449, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1750 = MVE_VSLIimm32 |
| 8642 | { 1749, 7, 1, 4, 1168, 0, 0, 1449, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1749 = MVE_VSLIimm16 |
| 8643 | { 1748, 7, 1, 4, 1162, 0, 0, 1233, ARMImpOpBase + 0, 0, 0x140c80ULL }, // Inst #1748 = MVE_VSHR_immu8 |
| 8644 | { 1747, 7, 1, 4, 1162, 0, 0, 1233, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1747 = MVE_VSHR_immu32 |
| 8645 | { 1746, 7, 1, 4, 1162, 0, 0, 1233, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1746 = MVE_VSHR_immu16 |
| 8646 | { 1745, 7, 1, 4, 1162, 0, 0, 1233, ARMImpOpBase + 0, 0, 0x140c80ULL }, // Inst #1745 = MVE_VSHR_imms8 |
| 8647 | { 1744, 7, 1, 4, 1162, 0, 0, 1233, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1744 = MVE_VSHR_imms32 |
| 8648 | { 1743, 7, 1, 4, 1162, 0, 0, 1233, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1743 = MVE_VSHR_imms16 |
| 8649 | { 1742, 7, 1, 4, 1304, 0, 0, 1449, ARMImpOpBase + 0, 0, 0x2340c80ULL }, // Inst #1742 = MVE_VSHRNi32th |
| 8650 | { 1741, 7, 1, 4, 1304, 0, 0, 1449, ARMImpOpBase + 0, 0, 0x2340c80ULL }, // Inst #1741 = MVE_VSHRNi32bh |
| 8651 | { 1740, 7, 1, 4, 1304, 0, 0, 1449, ARMImpOpBase + 0, 0, 0x1340c80ULL }, // Inst #1740 = MVE_VSHRNi16th |
| 8652 | { 1739, 7, 1, 4, 1304, 0, 0, 1449, ARMImpOpBase + 0, 0, 0x1340c80ULL }, // Inst #1739 = MVE_VSHRNi16bh |
| 8653 | { 1738, 6, 1, 4, 1301, 0, 0, 1443, ARMImpOpBase + 0, 0, 0x140c80ULL }, // Inst #1738 = MVE_VSHL_qru8 |
| 8654 | { 1737, 6, 1, 4, 1301, 0, 0, 1443, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1737 = MVE_VSHL_qru32 |
| 8655 | { 1736, 6, 1, 4, 1301, 0, 0, 1443, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1736 = MVE_VSHL_qru16 |
| 8656 | { 1735, 6, 1, 4, 1301, 0, 0, 1443, ARMImpOpBase + 0, 0, 0x140c80ULL }, // Inst #1735 = MVE_VSHL_qrs8 |
| 8657 | { 1734, 6, 1, 4, 1301, 0, 0, 1443, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1734 = MVE_VSHL_qrs32 |
| 8658 | { 1733, 6, 1, 4, 1301, 0, 0, 1443, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1733 = MVE_VSHL_qrs16 |
| 8659 | { 1732, 7, 1, 4, 1303, 0, 0, 1233, ARMImpOpBase + 0, 0, 0x140c80ULL }, // Inst #1732 = MVE_VSHL_immi8 |
| 8660 | { 1731, 7, 1, 4, 1303, 0, 0, 1233, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1731 = MVE_VSHL_immi32 |
| 8661 | { 1730, 7, 1, 4, 1303, 0, 0, 1233, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1730 = MVE_VSHL_immi16 |
| 8662 | { 1729, 7, 1, 4, 1303, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x140c80ULL }, // Inst #1729 = MVE_VSHL_by_vecu8 |
| 8663 | { 1728, 7, 1, 4, 1303, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1728 = MVE_VSHL_by_vecu32 |
| 8664 | { 1727, 7, 1, 4, 1303, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1727 = MVE_VSHL_by_vecu16 |
| 8665 | { 1726, 7, 1, 4, 1303, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x140c80ULL }, // Inst #1726 = MVE_VSHL_by_vecs8 |
| 8666 | { 1725, 7, 1, 4, 1303, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1725 = MVE_VSHL_by_vecs32 |
| 8667 | { 1724, 7, 1, 4, 1303, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1724 = MVE_VSHL_by_vecs16 |
| 8668 | { 1723, 6, 1, 4, 1303, 0, 0, 1115, ARMImpOpBase + 0, 0, 0x1840c80ULL }, // Inst #1723 = MVE_VSHLL_lwu8th |
| 8669 | { 1722, 6, 1, 4, 1303, 0, 0, 1115, ARMImpOpBase + 0, 0, 0x1840c80ULL }, // Inst #1722 = MVE_VSHLL_lwu8bh |
| 8670 | { 1721, 6, 1, 4, 1303, 0, 0, 1115, ARMImpOpBase + 0, 0, 0x2840c80ULL }, // Inst #1721 = MVE_VSHLL_lwu16th |
| 8671 | { 1720, 6, 1, 4, 1303, 0, 0, 1115, ARMImpOpBase + 0, 0, 0x2840c80ULL }, // Inst #1720 = MVE_VSHLL_lwu16bh |
| 8672 | { 1719, 6, 1, 4, 1303, 0, 0, 1115, ARMImpOpBase + 0, 0, 0x1840c80ULL }, // Inst #1719 = MVE_VSHLL_lws8th |
| 8673 | { 1718, 6, 1, 4, 1303, 0, 0, 1115, ARMImpOpBase + 0, 0, 0x1840c80ULL }, // Inst #1718 = MVE_VSHLL_lws8bh |
| 8674 | { 1717, 6, 1, 4, 1303, 0, 0, 1115, ARMImpOpBase + 0, 0, 0x2840c80ULL }, // Inst #1717 = MVE_VSHLL_lws16th |
| 8675 | { 1716, 6, 1, 4, 1303, 0, 0, 1115, ARMImpOpBase + 0, 0, 0x2840c80ULL }, // Inst #1716 = MVE_VSHLL_lws16bh |
| 8676 | { 1715, 7, 1, 4, 1303, 0, 0, 1233, ARMImpOpBase + 0, 0, 0x1840c80ULL }, // Inst #1715 = MVE_VSHLL_immu8th |
| 8677 | { 1714, 7, 1, 4, 1303, 0, 0, 1233, ARMImpOpBase + 0, 0, 0x1840c80ULL }, // Inst #1714 = MVE_VSHLL_immu8bh |
| 8678 | { 1713, 7, 1, 4, 1303, 0, 0, 1233, ARMImpOpBase + 0, 0, 0x2840c80ULL }, // Inst #1713 = MVE_VSHLL_immu16th |
| 8679 | { 1712, 7, 1, 4, 1303, 0, 0, 1233, ARMImpOpBase + 0, 0, 0x2840c80ULL }, // Inst #1712 = MVE_VSHLL_immu16bh |
| 8680 | { 1711, 7, 1, 4, 1303, 0, 0, 1233, ARMImpOpBase + 0, 0, 0x1840c80ULL }, // Inst #1711 = MVE_VSHLL_imms8th |
| 8681 | { 1710, 7, 1, 4, 1303, 0, 0, 1233, ARMImpOpBase + 0, 0, 0x1840c80ULL }, // Inst #1710 = MVE_VSHLL_imms8bh |
| 8682 | { 1709, 7, 1, 4, 1303, 0, 0, 1233, ARMImpOpBase + 0, 0, 0x2840c80ULL }, // Inst #1709 = MVE_VSHLL_imms16th |
| 8683 | { 1708, 7, 1, 4, 1303, 0, 0, 1233, ARMImpOpBase + 0, 0, 0x2840c80ULL }, // Inst #1708 = MVE_VSHLL_imms16bh |
| 8684 | { 1707, 8, 2, 4, 1158, 0, 0, 1462, ARMImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x2040c80ULL }, // Inst #1707 = MVE_VSHLC |
| 8685 | { 1706, 8, 2, 4, 1167, 0, 0, 1130, ARMImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x2040c80ULL }, // Inst #1706 = MVE_VSBCI |
| 8686 | { 1705, 9, 2, 4, 1167, 0, 0, 1121, ARMImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x2040c80ULL }, // Inst #1705 = MVE_VSBC |
| 8687 | { 1704, 7, 1, 4, 1163, 0, 0, 1233, ARMImpOpBase + 0, 0, 0x140c80ULL }, // Inst #1704 = MVE_VRSHR_immu8 |
| 8688 | { 1703, 7, 1, 4, 1163, 0, 0, 1233, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1703 = MVE_VRSHR_immu32 |
| 8689 | { 1702, 7, 1, 4, 1163, 0, 0, 1233, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1702 = MVE_VRSHR_immu16 |
| 8690 | { 1701, 7, 1, 4, 1163, 0, 0, 1233, ARMImpOpBase + 0, 0, 0x140c80ULL }, // Inst #1701 = MVE_VRSHR_imms8 |
| 8691 | { 1700, 7, 1, 4, 1163, 0, 0, 1233, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1700 = MVE_VRSHR_imms32 |
| 8692 | { 1699, 7, 1, 4, 1163, 0, 0, 1233, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1699 = MVE_VRSHR_imms16 |
| 8693 | { 1698, 7, 1, 4, 1161, 0, 0, 1449, ARMImpOpBase + 0, 0, 0x2340c80ULL }, // Inst #1698 = MVE_VRSHRNi32th |
| 8694 | { 1697, 7, 1, 4, 1161, 0, 0, 1449, ARMImpOpBase + 0, 0, 0x2340c80ULL }, // Inst #1697 = MVE_VRSHRNi32bh |
| 8695 | { 1696, 7, 1, 4, 1161, 0, 0, 1449, ARMImpOpBase + 0, 0, 0x1340c80ULL }, // Inst #1696 = MVE_VRSHRNi16th |
| 8696 | { 1695, 7, 1, 4, 1161, 0, 0, 1449, ARMImpOpBase + 0, 0, 0x1340c80ULL }, // Inst #1695 = MVE_VRSHRNi16bh |
| 8697 | { 1694, 6, 1, 4, 1308, 0, 0, 1443, ARMImpOpBase + 0, 0, 0x140c80ULL }, // Inst #1694 = MVE_VRSHL_qru8 |
| 8698 | { 1693, 6, 1, 4, 1308, 0, 0, 1443, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1693 = MVE_VRSHL_qru32 |
| 8699 | { 1692, 6, 1, 4, 1308, 0, 0, 1443, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1692 = MVE_VRSHL_qru16 |
| 8700 | { 1691, 6, 1, 4, 1308, 0, 0, 1443, ARMImpOpBase + 0, 0, 0x140c80ULL }, // Inst #1691 = MVE_VRSHL_qrs8 |
| 8701 | { 1690, 6, 1, 4, 1308, 0, 0, 1443, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1690 = MVE_VRSHL_qrs32 |
| 8702 | { 1689, 6, 1, 4, 1308, 0, 0, 1443, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1689 = MVE_VRSHL_qrs16 |
| 8703 | { 1688, 7, 1, 4, 1159, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x140c80ULL }, // Inst #1688 = MVE_VRSHL_by_vecu8 |
| 8704 | { 1687, 7, 1, 4, 1159, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1687 = MVE_VRSHL_by_vecu32 |
| 8705 | { 1686, 7, 1, 4, 1159, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1686 = MVE_VRSHL_by_vecu16 |
| 8706 | { 1685, 7, 1, 4, 1159, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x140c80ULL }, // Inst #1685 = MVE_VRSHL_by_vecs8 |
| 8707 | { 1684, 7, 1, 4, 1159, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1684 = MVE_VRSHL_by_vecs32 |
| 8708 | { 1683, 7, 1, 4, 1159, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1683 = MVE_VRSHL_by_vecs16 |
| 8709 | { 1682, 7, 1, 4, 1194, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x140c80ULL }, // Inst #1682 = MVE_VRMULHu8 |
| 8710 | { 1681, 7, 1, 4, 1194, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1681 = MVE_VRMULHu32 |
| 8711 | { 1680, 7, 1, 4, 1194, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1680 = MVE_VRMULHu16 |
| 8712 | { 1679, 7, 1, 4, 1194, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x140c80ULL }, // Inst #1679 = MVE_VRMULHs8 |
| 8713 | { 1678, 7, 1, 4, 1194, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1678 = MVE_VRMULHs32 |
| 8714 | { 1677, 7, 1, 4, 1194, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1677 = MVE_VRMULHs16 |
| 8715 | { 1676, 7, 2, 4, 1198, 0, 0, 1364, ARMImpOpBase + 0, 0, 0x2440c80ULL }, // Inst #1676 = MVE_VRMLSLDAVHxs32 |
| 8716 | { 1675, 7, 2, 4, 1198, 0, 0, 1364, ARMImpOpBase + 0, 0, 0x2540c80ULL }, // Inst #1675 = MVE_VRMLSLDAVHs32 |
| 8717 | { 1674, 9, 2, 4, 1317, 0, 0, 1355, ARMImpOpBase + 0, 0, 0x2440c80ULL }, // Inst #1674 = MVE_VRMLSLDAVHaxs32 |
| 8718 | { 1673, 9, 2, 4, 1317, 0, 0, 1355, ARMImpOpBase + 0, 0, 0x2540c80ULL }, // Inst #1673 = MVE_VRMLSLDAVHas32 |
| 8719 | { 1672, 7, 2, 4, 1198, 0, 0, 1364, ARMImpOpBase + 0, 0, 0x2440c80ULL }, // Inst #1672 = MVE_VRMLALDAVHxs32 |
| 8720 | { 1671, 7, 2, 4, 1198, 0, 0, 1364, ARMImpOpBase + 0, 0, 0x2540c80ULL }, // Inst #1671 = MVE_VRMLALDAVHu32 |
| 8721 | { 1670, 7, 2, 4, 1198, 0, 0, 1364, ARMImpOpBase + 0, 0, 0x2540c80ULL }, // Inst #1670 = MVE_VRMLALDAVHs32 |
| 8722 | { 1669, 9, 2, 4, 1317, 0, 0, 1355, ARMImpOpBase + 0, 0, 0x2440c80ULL }, // Inst #1669 = MVE_VRMLALDAVHaxs32 |
| 8723 | { 1668, 9, 2, 4, 1317, 0, 0, 1355, ARMImpOpBase + 0, 0, 0x2540c80ULL }, // Inst #1668 = MVE_VRMLALDAVHau32 |
| 8724 | { 1667, 9, 2, 4, 1317, 0, 0, 1355, ARMImpOpBase + 0, 0, 0x2540c80ULL }, // Inst #1667 = MVE_VRMLALDAVHas32 |
| 8725 | { 1666, 6, 1, 4, 1200, 0, 0, 1115, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1666 = MVE_VRINTf32Z |
| 8726 | { 1665, 6, 1, 4, 1200, 0, 0, 1115, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1665 = MVE_VRINTf32X |
| 8727 | { 1664, 6, 1, 4, 1200, 0, 0, 1115, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1664 = MVE_VRINTf32P |
| 8728 | { 1663, 6, 1, 4, 1200, 0, 0, 1115, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1663 = MVE_VRINTf32N |
| 8729 | { 1662, 6, 1, 4, 1200, 0, 0, 1115, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1662 = MVE_VRINTf32M |
| 8730 | { 1661, 6, 1, 4, 1200, 0, 0, 1115, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1661 = MVE_VRINTf32A |
| 8731 | { 1660, 6, 1, 4, 1200, 0, 0, 1115, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1660 = MVE_VRINTf16Z |
| 8732 | { 1659, 6, 1, 4, 1200, 0, 0, 1115, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1659 = MVE_VRINTf16X |
| 8733 | { 1658, 6, 1, 4, 1200, 0, 0, 1115, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1658 = MVE_VRINTf16P |
| 8734 | { 1657, 6, 1, 4, 1200, 0, 0, 1115, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1657 = MVE_VRINTf16N |
| 8735 | { 1656, 6, 1, 4, 1200, 0, 0, 1115, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1656 = MVE_VRINTf16M |
| 8736 | { 1655, 6, 1, 4, 1200, 0, 0, 1115, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1655 = MVE_VRINTf16A |
| 8737 | { 1654, 7, 1, 4, 1166, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x140c80ULL }, // Inst #1654 = MVE_VRHADDu8 |
| 8738 | { 1653, 7, 1, 4, 1166, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1653 = MVE_VRHADDu32 |
| 8739 | { 1652, 7, 1, 4, 1166, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1652 = MVE_VRHADDu16 |
| 8740 | { 1651, 7, 1, 4, 1166, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x140c80ULL }, // Inst #1651 = MVE_VRHADDs8 |
| 8741 | { 1650, 7, 1, 4, 1166, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1650 = MVE_VRHADDs32 |
| 8742 | { 1649, 7, 1, 4, 1166, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1649 = MVE_VRHADDs16 |
| 8743 | { 1648, 6, 1, 4, 1165, 0, 0, 1456, ARMImpOpBase + 0, 0, 0x3040c80ULL }, // Inst #1648 = MVE_VREV64_8 |
| 8744 | { 1647, 6, 1, 4, 1165, 0, 0, 1456, ARMImpOpBase + 0, 0, 0x3040c80ULL }, // Inst #1647 = MVE_VREV64_32 |
| 8745 | { 1646, 6, 1, 4, 1165, 0, 0, 1456, ARMImpOpBase + 0, 0, 0x3040c80ULL }, // Inst #1646 = MVE_VREV64_16 |
| 8746 | { 1645, 6, 1, 4, 1165, 0, 0, 1115, ARMImpOpBase + 0, 0, 0x2040c80ULL }, // Inst #1645 = MVE_VREV32_8 |
| 8747 | { 1644, 6, 1, 4, 1165, 0, 0, 1115, ARMImpOpBase + 0, 0, 0x2040c80ULL }, // Inst #1644 = MVE_VREV32_16 |
| 8748 | { 1643, 6, 1, 4, 1165, 0, 0, 1115, ARMImpOpBase + 0, 0, 0x1040c80ULL }, // Inst #1643 = MVE_VREV16_8 |
| 8749 | { 1642, 7, 1, 4, 1164, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x140c80ULL }, // Inst #1642 = MVE_VQSUBu8 |
| 8750 | { 1641, 7, 1, 4, 1164, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1641 = MVE_VQSUBu32 |
| 8751 | { 1640, 7, 1, 4, 1164, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1640 = MVE_VQSUBu16 |
| 8752 | { 1639, 7, 1, 4, 1164, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x140c80ULL }, // Inst #1639 = MVE_VQSUBs8 |
| 8753 | { 1638, 7, 1, 4, 1164, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1638 = MVE_VQSUBs32 |
| 8754 | { 1637, 7, 1, 4, 1164, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1637 = MVE_VQSUBs16 |
| 8755 | { 1636, 7, 1, 4, 1300, 0, 0, 1163, ARMImpOpBase + 0, 0, 0x140c80ULL }, // Inst #1636 = MVE_VQSUB_qr_u8 |
| 8756 | { 1635, 7, 1, 4, 1300, 0, 0, 1163, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1635 = MVE_VQSUB_qr_u32 |
| 8757 | { 1634, 7, 1, 4, 1300, 0, 0, 1163, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1634 = MVE_VQSUB_qr_u16 |
| 8758 | { 1633, 7, 1, 4, 1300, 0, 0, 1163, ARMImpOpBase + 0, 0, 0x140c80ULL }, // Inst #1633 = MVE_VQSUB_qr_s8 |
| 8759 | { 1632, 7, 1, 4, 1300, 0, 0, 1163, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1632 = MVE_VQSUB_qr_s32 |
| 8760 | { 1631, 7, 1, 4, 1300, 0, 0, 1163, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1631 = MVE_VQSUB_qr_s16 |
| 8761 | { 1630, 7, 1, 4, 1161, 0, 0, 1449, ARMImpOpBase + 0, 0, 0x2340c80ULL }, // Inst #1630 = MVE_VQSHRUNs32th |
| 8762 | { 1629, 7, 1, 4, 1161, 0, 0, 1449, ARMImpOpBase + 0, 0, 0x2340c80ULL }, // Inst #1629 = MVE_VQSHRUNs32bh |
| 8763 | { 1628, 7, 1, 4, 1161, 0, 0, 1449, ARMImpOpBase + 0, 0, 0x1340c80ULL }, // Inst #1628 = MVE_VQSHRUNs16th |
| 8764 | { 1627, 7, 1, 4, 1161, 0, 0, 1449, ARMImpOpBase + 0, 0, 0x1340c80ULL }, // Inst #1627 = MVE_VQSHRUNs16bh |
| 8765 | { 1626, 7, 1, 4, 1161, 0, 0, 1449, ARMImpOpBase + 0, 0, 0x2340c80ULL }, // Inst #1626 = MVE_VQSHRNthu32 |
| 8766 | { 1625, 7, 1, 4, 1161, 0, 0, 1449, ARMImpOpBase + 0, 0, 0x1340c80ULL }, // Inst #1625 = MVE_VQSHRNthu16 |
| 8767 | { 1624, 7, 1, 4, 1161, 0, 0, 1449, ARMImpOpBase + 0, 0, 0x2340c80ULL }, // Inst #1624 = MVE_VQSHRNths32 |
| 8768 | { 1623, 7, 1, 4, 1161, 0, 0, 1449, ARMImpOpBase + 0, 0, 0x1340c80ULL }, // Inst #1623 = MVE_VQSHRNths16 |
| 8769 | { 1622, 7, 1, 4, 1161, 0, 0, 1449, ARMImpOpBase + 0, 0, 0x2340c80ULL }, // Inst #1622 = MVE_VQSHRNbhu32 |
| 8770 | { 1621, 7, 1, 4, 1161, 0, 0, 1449, ARMImpOpBase + 0, 0, 0x1340c80ULL }, // Inst #1621 = MVE_VQSHRNbhu16 |
| 8771 | { 1620, 7, 1, 4, 1161, 0, 0, 1449, ARMImpOpBase + 0, 0, 0x2340c80ULL }, // Inst #1620 = MVE_VQSHRNbhs32 |
| 8772 | { 1619, 7, 1, 4, 1161, 0, 0, 1449, ARMImpOpBase + 0, 0, 0x1340c80ULL }, // Inst #1619 = MVE_VQSHRNbhs16 |
| 8773 | { 1618, 7, 1, 4, 1159, 0, 0, 1233, ARMImpOpBase + 0, 0, 0x140c80ULL }, // Inst #1618 = MVE_VQSHLimmu8 |
| 8774 | { 1617, 7, 1, 4, 1159, 0, 0, 1233, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1617 = MVE_VQSHLimmu32 |
| 8775 | { 1616, 7, 1, 4, 1159, 0, 0, 1233, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1616 = MVE_VQSHLimmu16 |
| 8776 | { 1615, 7, 1, 4, 1159, 0, 0, 1233, ARMImpOpBase + 0, 0, 0x140c80ULL }, // Inst #1615 = MVE_VQSHLimms8 |
| 8777 | { 1614, 7, 1, 4, 1159, 0, 0, 1233, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1614 = MVE_VQSHLimms32 |
| 8778 | { 1613, 7, 1, 4, 1159, 0, 0, 1233, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1613 = MVE_VQSHLimms16 |
| 8779 | { 1612, 6, 1, 4, 1308, 0, 0, 1443, ARMImpOpBase + 0, 0, 0x140c80ULL }, // Inst #1612 = MVE_VQSHL_qru8 |
| 8780 | { 1611, 6, 1, 4, 1308, 0, 0, 1443, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1611 = MVE_VQSHL_qru32 |
| 8781 | { 1610, 6, 1, 4, 1308, 0, 0, 1443, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1610 = MVE_VQSHL_qru16 |
| 8782 | { 1609, 6, 1, 4, 1308, 0, 0, 1443, ARMImpOpBase + 0, 0, 0x140c80ULL }, // Inst #1609 = MVE_VQSHL_qrs8 |
| 8783 | { 1608, 6, 1, 4, 1308, 0, 0, 1443, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1608 = MVE_VQSHL_qrs32 |
| 8784 | { 1607, 6, 1, 4, 1308, 0, 0, 1443, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1607 = MVE_VQSHL_qrs16 |
| 8785 | { 1606, 7, 1, 4, 1159, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x140c80ULL }, // Inst #1606 = MVE_VQSHL_by_vecu8 |
| 8786 | { 1605, 7, 1, 4, 1159, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1605 = MVE_VQSHL_by_vecu32 |
| 8787 | { 1604, 7, 1, 4, 1159, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1604 = MVE_VQSHL_by_vecu16 |
| 8788 | { 1603, 7, 1, 4, 1159, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x140c80ULL }, // Inst #1603 = MVE_VQSHL_by_vecs8 |
| 8789 | { 1602, 7, 1, 4, 1159, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1602 = MVE_VQSHL_by_vecs32 |
| 8790 | { 1601, 7, 1, 4, 1159, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1601 = MVE_VQSHL_by_vecs16 |
| 8791 | { 1600, 7, 1, 4, 1159, 0, 0, 1233, ARMImpOpBase + 0, 0, 0x140c80ULL }, // Inst #1600 = MVE_VQSHLU_imms8 |
| 8792 | { 1599, 7, 1, 4, 1159, 0, 0, 1233, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1599 = MVE_VQSHLU_imms32 |
| 8793 | { 1598, 7, 1, 4, 1159, 0, 0, 1233, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1598 = MVE_VQSHLU_imms16 |
| 8794 | { 1597, 7, 1, 4, 1161, 0, 0, 1449, ARMImpOpBase + 0, 0, 0x2340c80ULL }, // Inst #1597 = MVE_VQRSHRUNs32th |
| 8795 | { 1596, 7, 1, 4, 1161, 0, 0, 1449, ARMImpOpBase + 0, 0, 0x2340c80ULL }, // Inst #1596 = MVE_VQRSHRUNs32bh |
| 8796 | { 1595, 7, 1, 4, 1161, 0, 0, 1449, ARMImpOpBase + 0, 0, 0x1340c80ULL }, // Inst #1595 = MVE_VQRSHRUNs16th |
| 8797 | { 1594, 7, 1, 4, 1161, 0, 0, 1449, ARMImpOpBase + 0, 0, 0x1340c80ULL }, // Inst #1594 = MVE_VQRSHRUNs16bh |
| 8798 | { 1593, 7, 1, 4, 1161, 0, 0, 1449, ARMImpOpBase + 0, 0, 0x2340c80ULL }, // Inst #1593 = MVE_VQRSHRNthu32 |
| 8799 | { 1592, 7, 1, 4, 1161, 0, 0, 1449, ARMImpOpBase + 0, 0, 0x1340c80ULL }, // Inst #1592 = MVE_VQRSHRNthu16 |
| 8800 | { 1591, 7, 1, 4, 1161, 0, 0, 1449, ARMImpOpBase + 0, 0, 0x2340c80ULL }, // Inst #1591 = MVE_VQRSHRNths32 |
| 8801 | { 1590, 7, 1, 4, 1161, 0, 0, 1449, ARMImpOpBase + 0, 0, 0x1340c80ULL }, // Inst #1590 = MVE_VQRSHRNths16 |
| 8802 | { 1589, 7, 1, 4, 1161, 0, 0, 1449, ARMImpOpBase + 0, 0, 0x2340c80ULL }, // Inst #1589 = MVE_VQRSHRNbhu32 |
| 8803 | { 1588, 7, 1, 4, 1161, 0, 0, 1449, ARMImpOpBase + 0, 0, 0x1340c80ULL }, // Inst #1588 = MVE_VQRSHRNbhu16 |
| 8804 | { 1587, 7, 1, 4, 1161, 0, 0, 1449, ARMImpOpBase + 0, 0, 0x2340c80ULL }, // Inst #1587 = MVE_VQRSHRNbhs32 |
| 8805 | { 1586, 7, 1, 4, 1161, 0, 0, 1449, ARMImpOpBase + 0, 0, 0x1340c80ULL }, // Inst #1586 = MVE_VQRSHRNbhs16 |
| 8806 | { 1585, 6, 1, 4, 1307, 0, 0, 1443, ARMImpOpBase + 0, 0, 0x140c80ULL }, // Inst #1585 = MVE_VQRSHL_qru8 |
| 8807 | { 1584, 6, 1, 4, 1307, 0, 0, 1443, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1584 = MVE_VQRSHL_qru32 |
| 8808 | { 1583, 6, 1, 4, 1307, 0, 0, 1443, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1583 = MVE_VQRSHL_qru16 |
| 8809 | { 1582, 6, 1, 4, 1307, 0, 0, 1443, ARMImpOpBase + 0, 0, 0x140c80ULL }, // Inst #1582 = MVE_VQRSHL_qrs8 |
| 8810 | { 1581, 6, 1, 4, 1307, 0, 0, 1443, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1581 = MVE_VQRSHL_qrs32 |
| 8811 | { 1580, 6, 1, 4, 1307, 0, 0, 1443, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1580 = MVE_VQRSHL_qrs16 |
| 8812 | { 1579, 7, 1, 4, 1160, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x140c80ULL }, // Inst #1579 = MVE_VQRSHL_by_vecu8 |
| 8813 | { 1578, 7, 1, 4, 1160, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1578 = MVE_VQRSHL_by_vecu32 |
| 8814 | { 1577, 7, 1, 4, 1160, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1577 = MVE_VQRSHL_by_vecu16 |
| 8815 | { 1576, 7, 1, 4, 1160, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x140c80ULL }, // Inst #1576 = MVE_VQRSHL_by_vecs8 |
| 8816 | { 1575, 7, 1, 4, 1160, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1575 = MVE_VQRSHL_by_vecs32 |
| 8817 | { 1574, 7, 1, 4, 1160, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1574 = MVE_VQRSHL_by_vecs16 |
| 8818 | { 1573, 7, 1, 4, 1194, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x140c80ULL }, // Inst #1573 = MVE_VQRDMULHi8 |
| 8819 | { 1572, 7, 1, 4, 1194, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1572 = MVE_VQRDMULHi32 |
| 8820 | { 1571, 7, 1, 4, 1194, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1571 = MVE_VQRDMULHi16 |
| 8821 | { 1570, 7, 1, 4, 1313, 0, 0, 1163, ARMImpOpBase + 0, 0, 0x140c80ULL }, // Inst #1570 = MVE_VQRDMULH_qr_s8 |
| 8822 | { 1569, 7, 1, 4, 1313, 0, 0, 1163, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1569 = MVE_VQRDMULH_qr_s32 |
| 8823 | { 1568, 7, 1, 4, 1313, 0, 0, 1163, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1568 = MVE_VQRDMULH_qr_s16 |
| 8824 | { 1567, 7, 1, 4, 1316, 0, 0, 1270, ARMImpOpBase + 0, 0, 0x40c80ULL }, // Inst #1567 = MVE_VQRDMLSDHs8 |
| 8825 | { 1566, 7, 1, 4, 1316, 0, 0, 1429, ARMImpOpBase + 0, 0, 0x2040c80ULL }, // Inst #1566 = MVE_VQRDMLSDHs32 |
| 8826 | { 1565, 7, 1, 4, 1316, 0, 0, 1270, ARMImpOpBase + 0, 0, 0x1040c80ULL }, // Inst #1565 = MVE_VQRDMLSDHs16 |
| 8827 | { 1564, 7, 1, 4, 1316, 0, 0, 1270, ARMImpOpBase + 0, 0, 0x40c80ULL }, // Inst #1564 = MVE_VQRDMLSDHXs8 |
| 8828 | { 1563, 7, 1, 4, 1316, 0, 0, 1429, ARMImpOpBase + 0, 0, 0x2040c80ULL }, // Inst #1563 = MVE_VQRDMLSDHXs32 |
| 8829 | { 1562, 7, 1, 4, 1316, 0, 0, 1270, ARMImpOpBase + 0, 0, 0x1040c80ULL }, // Inst #1562 = MVE_VQRDMLSDHXs16 |
| 8830 | { 1561, 7, 1, 4, 1315, 0, 0, 1263, ARMImpOpBase + 0, 0, 0x40c80ULL }, // Inst #1561 = MVE_VQRDMLASH_qrs8 |
| 8831 | { 1560, 7, 1, 4, 1315, 0, 0, 1263, ARMImpOpBase + 0, 0, 0x2040c80ULL }, // Inst #1560 = MVE_VQRDMLASH_qrs32 |
| 8832 | { 1559, 7, 1, 4, 1315, 0, 0, 1263, ARMImpOpBase + 0, 0, 0x1040c80ULL }, // Inst #1559 = MVE_VQRDMLASH_qrs16 |
| 8833 | { 1558, 7, 1, 4, 1315, 0, 0, 1263, ARMImpOpBase + 0, 0, 0x40c80ULL }, // Inst #1558 = MVE_VQRDMLAH_qrs8 |
| 8834 | { 1557, 7, 1, 4, 1315, 0, 0, 1263, ARMImpOpBase + 0, 0, 0x2040c80ULL }, // Inst #1557 = MVE_VQRDMLAH_qrs32 |
| 8835 | { 1556, 7, 1, 4, 1315, 0, 0, 1263, ARMImpOpBase + 0, 0, 0x1040c80ULL }, // Inst #1556 = MVE_VQRDMLAH_qrs16 |
| 8836 | { 1555, 7, 1, 4, 1316, 0, 0, 1270, ARMImpOpBase + 0, 0, 0x40c80ULL }, // Inst #1555 = MVE_VQRDMLADHs8 |
| 8837 | { 1554, 7, 1, 4, 1316, 0, 0, 1429, ARMImpOpBase + 0, 0, 0x2040c80ULL }, // Inst #1554 = MVE_VQRDMLADHs32 |
| 8838 | { 1553, 7, 1, 4, 1316, 0, 0, 1270, ARMImpOpBase + 0, 0, 0x1040c80ULL }, // Inst #1553 = MVE_VQRDMLADHs16 |
| 8839 | { 1552, 7, 1, 4, 1316, 0, 0, 1270, ARMImpOpBase + 0, 0, 0x40c80ULL }, // Inst #1552 = MVE_VQRDMLADHXs8 |
| 8840 | { 1551, 7, 1, 4, 1316, 0, 0, 1429, ARMImpOpBase + 0, 0, 0x2040c80ULL }, // Inst #1551 = MVE_VQRDMLADHXs32 |
| 8841 | { 1550, 7, 1, 4, 1316, 0, 0, 1270, ARMImpOpBase + 0, 0, 0x1040c80ULL }, // Inst #1550 = MVE_VQRDMLADHXs16 |
| 8842 | { 1549, 6, 1, 4, 1157, 0, 0, 1115, ARMImpOpBase + 0, 0, 0x140c80ULL }, // Inst #1549 = MVE_VQNEGs8 |
| 8843 | { 1548, 6, 1, 4, 1157, 0, 0, 1115, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1548 = MVE_VQNEGs32 |
| 8844 | { 1547, 6, 1, 4, 1157, 0, 0, 1115, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1547 = MVE_VQNEGs16 |
| 8845 | { 1546, 6, 1, 4, 1156, 0, 0, 1227, ARMImpOpBase + 0, 0, 0x2340c80ULL }, // Inst #1546 = MVE_VQMOVUNs32th |
| 8846 | { 1545, 6, 1, 4, 1156, 0, 0, 1227, ARMImpOpBase + 0, 0, 0x2340c80ULL }, // Inst #1545 = MVE_VQMOVUNs32bh |
| 8847 | { 1544, 6, 1, 4, 1156, 0, 0, 1227, ARMImpOpBase + 0, 0, 0x1340c80ULL }, // Inst #1544 = MVE_VQMOVUNs16th |
| 8848 | { 1543, 6, 1, 4, 1156, 0, 0, 1227, ARMImpOpBase + 0, 0, 0x1340c80ULL }, // Inst #1543 = MVE_VQMOVUNs16bh |
| 8849 | { 1542, 6, 1, 4, 1156, 0, 0, 1227, ARMImpOpBase + 0, 0, 0x2340c80ULL }, // Inst #1542 = MVE_VQMOVNu32th |
| 8850 | { 1541, 6, 1, 4, 1156, 0, 0, 1227, ARMImpOpBase + 0, 0, 0x2340c80ULL }, // Inst #1541 = MVE_VQMOVNu32bh |
| 8851 | { 1540, 6, 1, 4, 1156, 0, 0, 1227, ARMImpOpBase + 0, 0, 0x1340c80ULL }, // Inst #1540 = MVE_VQMOVNu16th |
| 8852 | { 1539, 6, 1, 4, 1156, 0, 0, 1227, ARMImpOpBase + 0, 0, 0x1340c80ULL }, // Inst #1539 = MVE_VQMOVNu16bh |
| 8853 | { 1538, 6, 1, 4, 1156, 0, 0, 1227, ARMImpOpBase + 0, 0, 0x2340c80ULL }, // Inst #1538 = MVE_VQMOVNs32th |
| 8854 | { 1537, 6, 1, 4, 1156, 0, 0, 1227, ARMImpOpBase + 0, 0, 0x2340c80ULL }, // Inst #1537 = MVE_VQMOVNs32bh |
| 8855 | { 1536, 6, 1, 4, 1156, 0, 0, 1227, ARMImpOpBase + 0, 0, 0x1340c80ULL }, // Inst #1536 = MVE_VQMOVNs16th |
| 8856 | { 1535, 6, 1, 4, 1156, 0, 0, 1227, ARMImpOpBase + 0, 0, 0x1340c80ULL }, // Inst #1535 = MVE_VQMOVNs16bh |
| 8857 | { 1534, 7, 1, 4, 1195, 0, 0, 1403, ARMImpOpBase + 0, 0, 0x2940c80ULL }, // Inst #1534 = MVE_VQDMULLs32th |
| 8858 | { 1533, 7, 1, 4, 1195, 0, 0, 1403, ARMImpOpBase + 0, 0, 0x2940c80ULL }, // Inst #1533 = MVE_VQDMULLs32bh |
| 8859 | { 1532, 7, 1, 4, 1195, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x1940c80ULL }, // Inst #1532 = MVE_VQDMULLs16th |
| 8860 | { 1531, 7, 1, 4, 1195, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x1940c80ULL }, // Inst #1531 = MVE_VQDMULLs16bh |
| 8861 | { 1530, 7, 1, 4, 1196, 0, 0, 1436, ARMImpOpBase + 0, 0, 0x2940c80ULL }, // Inst #1530 = MVE_VQDMULL_qr_s32th |
| 8862 | { 1529, 7, 1, 4, 1196, 0, 0, 1436, ARMImpOpBase + 0, 0, 0x2940c80ULL }, // Inst #1529 = MVE_VQDMULL_qr_s32bh |
| 8863 | { 1528, 7, 1, 4, 1196, 0, 0, 1163, ARMImpOpBase + 0, 0, 0x1940c80ULL }, // Inst #1528 = MVE_VQDMULL_qr_s16th |
| 8864 | { 1527, 7, 1, 4, 1196, 0, 0, 1163, ARMImpOpBase + 0, 0, 0x1940c80ULL }, // Inst #1527 = MVE_VQDMULL_qr_s16bh |
| 8865 | { 1526, 7, 1, 4, 1194, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x140c80ULL }, // Inst #1526 = MVE_VQDMULHi8 |
| 8866 | { 1525, 7, 1, 4, 1194, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1525 = MVE_VQDMULHi32 |
| 8867 | { 1524, 7, 1, 4, 1194, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1524 = MVE_VQDMULHi16 |
| 8868 | { 1523, 7, 1, 4, 1313, 0, 0, 1163, ARMImpOpBase + 0, 0, 0x140c80ULL }, // Inst #1523 = MVE_VQDMULH_qr_s8 |
| 8869 | { 1522, 7, 1, 4, 1313, 0, 0, 1163, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1522 = MVE_VQDMULH_qr_s32 |
| 8870 | { 1521, 7, 1, 4, 1313, 0, 0, 1163, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1521 = MVE_VQDMULH_qr_s16 |
| 8871 | { 1520, 7, 1, 4, 1316, 0, 0, 1270, ARMImpOpBase + 0, 0, 0x40c80ULL }, // Inst #1520 = MVE_VQDMLSDHs8 |
| 8872 | { 1519, 7, 1, 4, 1316, 0, 0, 1429, ARMImpOpBase + 0, 0, 0x2040c80ULL }, // Inst #1519 = MVE_VQDMLSDHs32 |
| 8873 | { 1518, 7, 1, 4, 1316, 0, 0, 1270, ARMImpOpBase + 0, 0, 0x1040c80ULL }, // Inst #1518 = MVE_VQDMLSDHs16 |
| 8874 | { 1517, 7, 1, 4, 1316, 0, 0, 1270, ARMImpOpBase + 0, 0, 0x40c80ULL }, // Inst #1517 = MVE_VQDMLSDHXs8 |
| 8875 | { 1516, 7, 1, 4, 1316, 0, 0, 1429, ARMImpOpBase + 0, 0, 0x2040c80ULL }, // Inst #1516 = MVE_VQDMLSDHXs32 |
| 8876 | { 1515, 7, 1, 4, 1316, 0, 0, 1270, ARMImpOpBase + 0, 0, 0x1040c80ULL }, // Inst #1515 = MVE_VQDMLSDHXs16 |
| 8877 | { 1514, 7, 1, 4, 1315, 0, 0, 1263, ARMImpOpBase + 0, 0, 0x40c80ULL }, // Inst #1514 = MVE_VQDMLASH_qrs8 |
| 8878 | { 1513, 7, 1, 4, 1315, 0, 0, 1263, ARMImpOpBase + 0, 0, 0x2040c80ULL }, // Inst #1513 = MVE_VQDMLASH_qrs32 |
| 8879 | { 1512, 7, 1, 4, 1315, 0, 0, 1263, ARMImpOpBase + 0, 0, 0x1040c80ULL }, // Inst #1512 = MVE_VQDMLASH_qrs16 |
| 8880 | { 1511, 7, 1, 4, 1315, 0, 0, 1263, ARMImpOpBase + 0, 0, 0x40c80ULL }, // Inst #1511 = MVE_VQDMLAH_qrs8 |
| 8881 | { 1510, 7, 1, 4, 1315, 0, 0, 1263, ARMImpOpBase + 0, 0, 0x2040c80ULL }, // Inst #1510 = MVE_VQDMLAH_qrs32 |
| 8882 | { 1509, 7, 1, 4, 1315, 0, 0, 1263, ARMImpOpBase + 0, 0, 0x1040c80ULL }, // Inst #1509 = MVE_VQDMLAH_qrs16 |
| 8883 | { 1508, 7, 1, 4, 1316, 0, 0, 1270, ARMImpOpBase + 0, 0, 0x40c80ULL }, // Inst #1508 = MVE_VQDMLADHs8 |
| 8884 | { 1507, 7, 1, 4, 1316, 0, 0, 1429, ARMImpOpBase + 0, 0, 0x2040c80ULL }, // Inst #1507 = MVE_VQDMLADHs32 |
| 8885 | { 1506, 7, 1, 4, 1316, 0, 0, 1270, ARMImpOpBase + 0, 0, 0x1040c80ULL }, // Inst #1506 = MVE_VQDMLADHs16 |
| 8886 | { 1505, 7, 1, 4, 1316, 0, 0, 1270, ARMImpOpBase + 0, 0, 0x40c80ULL }, // Inst #1505 = MVE_VQDMLADHXs8 |
| 8887 | { 1504, 7, 1, 4, 1316, 0, 0, 1429, ARMImpOpBase + 0, 0, 0x2040c80ULL }, // Inst #1504 = MVE_VQDMLADHXs32 |
| 8888 | { 1503, 7, 1, 4, 1316, 0, 0, 1270, ARMImpOpBase + 0, 0, 0x1040c80ULL }, // Inst #1503 = MVE_VQDMLADHXs16 |
| 8889 | { 1502, 7, 1, 4, 1155, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x140c80ULL }, // Inst #1502 = MVE_VQADDu8 |
| 8890 | { 1501, 7, 1, 4, 1155, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1501 = MVE_VQADDu32 |
| 8891 | { 1500, 7, 1, 4, 1155, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1500 = MVE_VQADDu16 |
| 8892 | { 1499, 7, 1, 4, 1155, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x140c80ULL }, // Inst #1499 = MVE_VQADDs8 |
| 8893 | { 1498, 7, 1, 4, 1155, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1498 = MVE_VQADDs32 |
| 8894 | { 1497, 7, 1, 4, 1155, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1497 = MVE_VQADDs16 |
| 8895 | { 1496, 7, 1, 4, 1299, 0, 0, 1163, ARMImpOpBase + 0, 0, 0x140c80ULL }, // Inst #1496 = MVE_VQADD_qr_u8 |
| 8896 | { 1495, 7, 1, 4, 1299, 0, 0, 1163, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1495 = MVE_VQADD_qr_u32 |
| 8897 | { 1494, 7, 1, 4, 1299, 0, 0, 1163, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1494 = MVE_VQADD_qr_u16 |
| 8898 | { 1493, 7, 1, 4, 1299, 0, 0, 1163, ARMImpOpBase + 0, 0, 0x140c80ULL }, // Inst #1493 = MVE_VQADD_qr_s8 |
| 8899 | { 1492, 7, 1, 4, 1299, 0, 0, 1163, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1492 = MVE_VQADD_qr_s32 |
| 8900 | { 1491, 7, 1, 4, 1299, 0, 0, 1163, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1491 = MVE_VQADD_qr_s16 |
| 8901 | { 1490, 6, 1, 4, 1154, 0, 0, 1115, ARMImpOpBase + 0, 0, 0x140c80ULL }, // Inst #1490 = MVE_VQABSs8 |
| 8902 | { 1489, 6, 1, 4, 1154, 0, 0, 1115, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1489 = MVE_VQABSs32 |
| 8903 | { 1488, 6, 1, 4, 1154, 0, 0, 1115, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1488 = MVE_VQABSs16 |
| 8904 | { 1487, 4, 0, 4, 1323, 0, 1, 1425, ARMImpOpBase + 69, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1140c80ULL }, // Inst #1487 = MVE_VPTv8u16r |
| 8905 | { 1486, 4, 0, 4, 1180, 0, 1, 1421, ARMImpOpBase + 69, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1140c80ULL }, // Inst #1486 = MVE_VPTv8u16 |
| 8906 | { 1485, 4, 0, 4, 1323, 0, 1, 1425, ARMImpOpBase + 69, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1140c80ULL }, // Inst #1485 = MVE_VPTv8s16r |
| 8907 | { 1484, 4, 0, 4, 1180, 0, 1, 1421, ARMImpOpBase + 69, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1140c80ULL }, // Inst #1484 = MVE_VPTv8s16 |
| 8908 | { 1483, 4, 0, 4, 1323, 0, 1, 1425, ARMImpOpBase + 69, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1140c80ULL }, // Inst #1483 = MVE_VPTv8i16r |
| 8909 | { 1482, 4, 0, 4, 1180, 0, 1, 1421, ARMImpOpBase + 69, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1140c80ULL }, // Inst #1482 = MVE_VPTv8i16 |
| 8910 | { 1481, 4, 0, 4, 1322, 0, 1, 1425, ARMImpOpBase + 69, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1140c80ULL }, // Inst #1481 = MVE_VPTv8f16r |
| 8911 | { 1480, 4, 0, 4, 1181, 0, 1, 1421, ARMImpOpBase + 69, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1140c80ULL }, // Inst #1480 = MVE_VPTv8f16 |
| 8912 | { 1479, 4, 0, 4, 1323, 0, 1, 1425, ARMImpOpBase + 69, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x2140c80ULL }, // Inst #1479 = MVE_VPTv4u32r |
| 8913 | { 1478, 4, 0, 4, 1180, 0, 1, 1421, ARMImpOpBase + 69, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x2140c80ULL }, // Inst #1478 = MVE_VPTv4u32 |
| 8914 | { 1477, 4, 0, 4, 1323, 0, 1, 1425, ARMImpOpBase + 69, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x2140c80ULL }, // Inst #1477 = MVE_VPTv4s32r |
| 8915 | { 1476, 4, 0, 4, 1180, 0, 1, 1421, ARMImpOpBase + 69, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x2140c80ULL }, // Inst #1476 = MVE_VPTv4s32 |
| 8916 | { 1475, 4, 0, 4, 1323, 0, 1, 1425, ARMImpOpBase + 69, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x2140c80ULL }, // Inst #1475 = MVE_VPTv4i32r |
| 8917 | { 1474, 4, 0, 4, 1180, 0, 1, 1421, ARMImpOpBase + 69, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x2140c80ULL }, // Inst #1474 = MVE_VPTv4i32 |
| 8918 | { 1473, 4, 0, 4, 1322, 0, 1, 1425, ARMImpOpBase + 69, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x2140c80ULL }, // Inst #1473 = MVE_VPTv4f32r |
| 8919 | { 1472, 4, 0, 4, 1181, 0, 1, 1421, ARMImpOpBase + 69, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x2140c80ULL }, // Inst #1472 = MVE_VPTv4f32 |
| 8920 | { 1471, 4, 0, 4, 1323, 0, 1, 1425, ARMImpOpBase + 69, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x140c80ULL }, // Inst #1471 = MVE_VPTv16u8r |
| 8921 | { 1470, 4, 0, 4, 1180, 0, 1, 1421, ARMImpOpBase + 69, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x140c80ULL }, // Inst #1470 = MVE_VPTv16u8 |
| 8922 | { 1469, 4, 0, 4, 1323, 0, 1, 1425, ARMImpOpBase + 69, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x140c80ULL }, // Inst #1469 = MVE_VPTv16s8r |
| 8923 | { 1468, 4, 0, 4, 1180, 0, 1, 1421, ARMImpOpBase + 69, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x140c80ULL }, // Inst #1468 = MVE_VPTv16s8 |
| 8924 | { 1467, 4, 0, 4, 1323, 0, 1, 1425, ARMImpOpBase + 69, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x140c80ULL }, // Inst #1467 = MVE_VPTv16i8r |
| 8925 | { 1466, 4, 0, 4, 1180, 0, 1, 1421, ARMImpOpBase + 69, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x140c80ULL }, // Inst #1466 = MVE_VPTv16i8 |
| 8926 | { 1465, 1, 0, 4, 1206, 1, 0, 0, ARMImpOpBase + 69, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x140c80ULL }, // Inst #1465 = MVE_VPST |
| 8927 | { 1464, 6, 1, 4, 1152, 0, 0, 1415, ARMImpOpBase + 0, 0, 0x40c80ULL }, // Inst #1464 = MVE_VPSEL |
| 8928 | { 1463, 5, 1, 4, 1205, 0, 0, 1410, ARMImpOpBase + 0, 0, 0x40c80ULL }, // Inst #1463 = MVE_VPNOT |
| 8929 | { 1462, 6, 1, 4, 1151, 0, 0, 1170, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1462 = MVE_VORRimmi32 |
| 8930 | { 1461, 6, 1, 4, 1151, 0, 0, 1170, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1461 = MVE_VORRimmi16 |
| 8931 | { 1460, 7, 1, 4, 1151, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x140c80ULL }, // Inst #1460 = MVE_VORR |
| 8932 | { 1459, 7, 1, 4, 1150, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x140c80ULL }, // Inst #1459 = MVE_VORN |
| 8933 | { 1458, 6, 1, 4, 1149, 0, 0, 1115, ARMImpOpBase + 0, 0, 0x140c80ULL }, // Inst #1458 = MVE_VNEGs8 |
| 8934 | { 1457, 6, 1, 4, 1149, 0, 0, 1115, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1457 = MVE_VNEGs32 |
| 8935 | { 1456, 6, 1, 4, 1149, 0, 0, 1115, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1456 = MVE_VNEGs16 |
| 8936 | { 1455, 6, 1, 4, 1199, 0, 0, 1115, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1455 = MVE_VNEGf32 |
| 8937 | { 1454, 6, 1, 4, 1199, 0, 0, 1115, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1454 = MVE_VNEGf16 |
| 8938 | { 1453, 6, 1, 4, 1148, 0, 0, 1397, ARMImpOpBase + 0, 0|(1ULL<<MCID::Rematerializable), 0x2140c80ULL }, // Inst #1453 = MVE_VMVNimmi32 |
| 8939 | { 1452, 6, 1, 4, 1148, 0, 0, 1397, ARMImpOpBase + 0, 0|(1ULL<<MCID::Rematerializable), 0x1140c80ULL }, // Inst #1452 = MVE_VMVNimmi16 |
| 8940 | { 1451, 6, 1, 4, 1148, 0, 0, 1115, ARMImpOpBase + 0, 0, 0x140c80ULL }, // Inst #1451 = MVE_VMVN |
| 8941 | { 1450, 7, 1, 4, 1319, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x140c80ULL }, // Inst #1450 = MVE_VMULi8 |
| 8942 | { 1449, 7, 1, 4, 1319, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1449 = MVE_VMULi32 |
| 8943 | { 1448, 7, 1, 4, 1319, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1448 = MVE_VMULi16 |
| 8944 | { 1447, 7, 1, 4, 1193, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1447 = MVE_VMULf32 |
| 8945 | { 1446, 7, 1, 4, 1193, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1446 = MVE_VMULf16 |
| 8946 | { 1445, 7, 1, 4, 1312, 0, 0, 1163, ARMImpOpBase + 0, 0, 0x140c80ULL }, // Inst #1445 = MVE_VMUL_qr_i8 |
| 8947 | { 1444, 7, 1, 4, 1312, 0, 0, 1163, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1444 = MVE_VMUL_qr_i32 |
| 8948 | { 1443, 7, 1, 4, 1312, 0, 0, 1163, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1443 = MVE_VMUL_qr_i16 |
| 8949 | { 1442, 7, 1, 4, 1320, 0, 0, 1163, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1442 = MVE_VMUL_qr_f32 |
| 8950 | { 1441, 7, 1, 4, 1320, 0, 0, 1163, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1441 = MVE_VMUL_qr_f16 |
| 8951 | { 1440, 7, 1, 4, 1195, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x1940c80ULL }, // Inst #1440 = MVE_VMULLTu8 |
| 8952 | { 1439, 7, 1, 4, 1195, 0, 0, 1403, ARMImpOpBase + 0, 0, 0x3940c80ULL }, // Inst #1439 = MVE_VMULLTu32 |
| 8953 | { 1438, 7, 1, 4, 1195, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x2940c80ULL }, // Inst #1438 = MVE_VMULLTu16 |
| 8954 | { 1437, 7, 1, 4, 1195, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x1940c80ULL }, // Inst #1437 = MVE_VMULLTs8 |
| 8955 | { 1436, 7, 1, 4, 1195, 0, 0, 1403, ARMImpOpBase + 0, 0, 0x3940c80ULL }, // Inst #1436 = MVE_VMULLTs32 |
| 8956 | { 1435, 7, 1, 4, 1195, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x2940c80ULL }, // Inst #1435 = MVE_VMULLTs16 |
| 8957 | { 1434, 7, 1, 4, 1147, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x1940c80ULL }, // Inst #1434 = MVE_VMULLTp8 |
| 8958 | { 1433, 7, 1, 4, 1147, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x2940c80ULL }, // Inst #1433 = MVE_VMULLTp16 |
| 8959 | { 1432, 7, 1, 4, 1195, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x1940c80ULL }, // Inst #1432 = MVE_VMULLBu8 |
| 8960 | { 1431, 7, 1, 4, 1195, 0, 0, 1403, ARMImpOpBase + 0, 0, 0x3940c80ULL }, // Inst #1431 = MVE_VMULLBu32 |
| 8961 | { 1430, 7, 1, 4, 1195, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x2940c80ULL }, // Inst #1430 = MVE_VMULLBu16 |
| 8962 | { 1429, 7, 1, 4, 1195, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x1940c80ULL }, // Inst #1429 = MVE_VMULLBs8 |
| 8963 | { 1428, 7, 1, 4, 1195, 0, 0, 1403, ARMImpOpBase + 0, 0, 0x3940c80ULL }, // Inst #1428 = MVE_VMULLBs32 |
| 8964 | { 1427, 7, 1, 4, 1195, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x2940c80ULL }, // Inst #1427 = MVE_VMULLBs16 |
| 8965 | { 1426, 7, 1, 4, 1147, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x1940c80ULL }, // Inst #1426 = MVE_VMULLBp8 |
| 8966 | { 1425, 7, 1, 4, 1147, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x2940c80ULL }, // Inst #1425 = MVE_VMULLBp16 |
| 8967 | { 1424, 7, 1, 4, 1194, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x140c80ULL }, // Inst #1424 = MVE_VMULHu8 |
| 8968 | { 1423, 7, 1, 4, 1194, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1423 = MVE_VMULHu32 |
| 8969 | { 1422, 7, 1, 4, 1194, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1422 = MVE_VMULHu16 |
| 8970 | { 1421, 7, 1, 4, 1194, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x140c80ULL }, // Inst #1421 = MVE_VMULHs8 |
| 8971 | { 1420, 7, 1, 4, 1194, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1420 = MVE_VMULHs32 |
| 8972 | { 1419, 7, 1, 4, 1194, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1419 = MVE_VMULHs16 |
| 8973 | { 1418, 6, 1, 4, 1192, 0, 0, 1397, ARMImpOpBase + 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x140c80ULL }, // Inst #1418 = MVE_VMOVimmi8 |
| 8974 | { 1417, 6, 1, 4, 1192, 0, 0, 1397, ARMImpOpBase + 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x3140c80ULL }, // Inst #1417 = MVE_VMOVimmi64 |
| 8975 | { 1416, 6, 1, 4, 1192, 0, 0, 1397, ARMImpOpBase + 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x2140c80ULL }, // Inst #1416 = MVE_VMOVimmi32 |
| 8976 | { 1415, 6, 1, 4, 1192, 0, 0, 1397, ARMImpOpBase + 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x1140c80ULL }, // Inst #1415 = MVE_VMOVimmi16 |
| 8977 | { 1414, 6, 1, 4, 1192, 0, 0, 1397, ARMImpOpBase + 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x2140c80ULL }, // Inst #1414 = MVE_VMOVimmf32 |
| 8978 | { 1413, 6, 1, 4, 1203, 0, 0, 1391, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x40c80ULL }, // Inst #1413 = MVE_VMOV_to_lane_8 |
| 8979 | { 1412, 6, 1, 4, 1203, 0, 0, 1391, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::InsertSubreg), 0x2040c80ULL }, // Inst #1412 = MVE_VMOV_to_lane_32 |
| 8980 | { 1411, 6, 1, 4, 1203, 0, 0, 1391, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x1040c80ULL }, // Inst #1411 = MVE_VMOV_to_lane_16 |
| 8981 | { 1410, 7, 2, 4, 1191, 0, 0, 1384, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x2040c80ULL }, // Inst #1410 = MVE_VMOV_rr_q |
| 8982 | { 1409, 8, 1, 4, 1294, 0, 0, 1376, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x2040c80ULL }, // Inst #1409 = MVE_VMOV_q_rr |
| 8983 | { 1408, 5, 1, 4, 1190, 0, 0, 1371, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x40c80ULL }, // Inst #1408 = MVE_VMOV_from_lane_u8 |
| 8984 | { 1407, 5, 1, 4, 1190, 0, 0, 1371, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x1040c80ULL }, // Inst #1407 = MVE_VMOV_from_lane_u16 |
| 8985 | { 1406, 5, 1, 4, 1190, 0, 0, 1371, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x40c80ULL }, // Inst #1406 = MVE_VMOV_from_lane_s8 |
| 8986 | { 1405, 5, 1, 4, 1190, 0, 0, 1371, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x1040c80ULL }, // Inst #1405 = MVE_VMOV_from_lane_s16 |
| 8987 | { 1404, 5, 1, 4, 1190, 0, 0, 1371, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x2040c80ULL }, // Inst #1404 = MVE_VMOV_from_lane_32 |
| 8988 | { 1403, 6, 1, 4, 1145, 0, 0, 1227, ARMImpOpBase + 0, 0, 0x2340c80ULL }, // Inst #1403 = MVE_VMOVNi32th |
| 8989 | { 1402, 6, 1, 4, 1145, 0, 0, 1227, ARMImpOpBase + 0, 0, 0x2340c80ULL }, // Inst #1402 = MVE_VMOVNi32bh |
| 8990 | { 1401, 6, 1, 4, 1145, 0, 0, 1227, ARMImpOpBase + 0, 0, 0x1340c80ULL }, // Inst #1401 = MVE_VMOVNi16th |
| 8991 | { 1400, 6, 1, 4, 1145, 0, 0, 1227, ARMImpOpBase + 0, 0, 0x1340c80ULL }, // Inst #1400 = MVE_VMOVNi16bh |
| 8992 | { 1399, 6, 1, 4, 1146, 0, 0, 1115, ARMImpOpBase + 0, 0, 0x1840c80ULL }, // Inst #1399 = MVE_VMOVLu8th |
| 8993 | { 1398, 6, 1, 4, 1146, 0, 0, 1115, ARMImpOpBase + 0, 0, 0x1840c80ULL }, // Inst #1398 = MVE_VMOVLu8bh |
| 8994 | { 1397, 6, 1, 4, 1146, 0, 0, 1115, ARMImpOpBase + 0, 0, 0x2840c80ULL }, // Inst #1397 = MVE_VMOVLu16th |
| 8995 | { 1396, 6, 1, 4, 1146, 0, 0, 1115, ARMImpOpBase + 0, 0, 0x2840c80ULL }, // Inst #1396 = MVE_VMOVLu16bh |
| 8996 | { 1395, 6, 1, 4, 1146, 0, 0, 1115, ARMImpOpBase + 0, 0, 0x1840c80ULL }, // Inst #1395 = MVE_VMOVLs8th |
| 8997 | { 1394, 6, 1, 4, 1146, 0, 0, 1115, ARMImpOpBase + 0, 0, 0x1840c80ULL }, // Inst #1394 = MVE_VMOVLs8bh |
| 8998 | { 1393, 6, 1, 4, 1146, 0, 0, 1115, ARMImpOpBase + 0, 0, 0x2840c80ULL }, // Inst #1393 = MVE_VMOVLs16th |
| 8999 | { 1392, 6, 1, 4, 1146, 0, 0, 1115, ARMImpOpBase + 0, 0, 0x2840c80ULL }, // Inst #1392 = MVE_VMOVLs16bh |
| 9000 | { 1391, 7, 2, 4, 1198, 0, 0, 1364, ARMImpOpBase + 0, 0, 0x2440c80ULL }, // Inst #1391 = MVE_VMLSLDAVxs32 |
| 9001 | { 1390, 7, 2, 4, 1198, 0, 0, 1364, ARMImpOpBase + 0, 0, 0x1440c80ULL }, // Inst #1390 = MVE_VMLSLDAVxs16 |
| 9002 | { 1389, 7, 2, 4, 1198, 0, 0, 1364, ARMImpOpBase + 0, 0, 0x2540c80ULL }, // Inst #1389 = MVE_VMLSLDAVs32 |
| 9003 | { 1388, 7, 2, 4, 1198, 0, 0, 1364, ARMImpOpBase + 0, 0, 0x1540c80ULL }, // Inst #1388 = MVE_VMLSLDAVs16 |
| 9004 | { 1387, 9, 2, 4, 1317, 0, 0, 1355, ARMImpOpBase + 0, 0, 0x2440c80ULL }, // Inst #1387 = MVE_VMLSLDAVaxs32 |
| 9005 | { 1386, 9, 2, 4, 1317, 0, 0, 1355, ARMImpOpBase + 0, 0, 0x1440c80ULL }, // Inst #1386 = MVE_VMLSLDAVaxs16 |
| 9006 | { 1385, 9, 2, 4, 1317, 0, 0, 1355, ARMImpOpBase + 0, 0, 0x2540c80ULL }, // Inst #1385 = MVE_VMLSLDAVas32 |
| 9007 | { 1384, 9, 2, 4, 1317, 0, 0, 1355, ARMImpOpBase + 0, 0, 0x1540c80ULL }, // Inst #1384 = MVE_VMLSLDAVas16 |
| 9008 | { 1383, 6, 1, 4, 1197, 0, 0, 1349, ARMImpOpBase + 0, 0, 0x440c80ULL }, // Inst #1383 = MVE_VMLSDAVxs8 |
| 9009 | { 1382, 6, 1, 4, 1197, 0, 0, 1349, ARMImpOpBase + 0, 0, 0x2440c80ULL }, // Inst #1382 = MVE_VMLSDAVxs32 |
| 9010 | { 1381, 6, 1, 4, 1197, 0, 0, 1349, ARMImpOpBase + 0, 0, 0x1440c80ULL }, // Inst #1381 = MVE_VMLSDAVxs16 |
| 9011 | { 1380, 6, 1, 4, 1197, 0, 0, 1349, ARMImpOpBase + 0, 0, 0x540c80ULL }, // Inst #1380 = MVE_VMLSDAVs8 |
| 9012 | { 1379, 6, 1, 4, 1197, 0, 0, 1349, ARMImpOpBase + 0, 0, 0x2540c80ULL }, // Inst #1379 = MVE_VMLSDAVs32 |
| 9013 | { 1378, 6, 1, 4, 1197, 0, 0, 1349, ARMImpOpBase + 0, 0, 0x1540c80ULL }, // Inst #1378 = MVE_VMLSDAVs16 |
| 9014 | { 1377, 7, 1, 4, 1318, 0, 0, 1342, ARMImpOpBase + 0, 0, 0x440c80ULL }, // Inst #1377 = MVE_VMLSDAVaxs8 |
| 9015 | { 1376, 7, 1, 4, 1318, 0, 0, 1342, ARMImpOpBase + 0, 0, 0x2440c80ULL }, // Inst #1376 = MVE_VMLSDAVaxs32 |
| 9016 | { 1375, 7, 1, 4, 1318, 0, 0, 1342, ARMImpOpBase + 0, 0, 0x1440c80ULL }, // Inst #1375 = MVE_VMLSDAVaxs16 |
| 9017 | { 1374, 7, 1, 4, 1318, 0, 0, 1342, ARMImpOpBase + 0, 0, 0x540c80ULL }, // Inst #1374 = MVE_VMLSDAVas8 |
| 9018 | { 1373, 7, 1, 4, 1318, 0, 0, 1342, ARMImpOpBase + 0, 0, 0x2540c80ULL }, // Inst #1373 = MVE_VMLSDAVas32 |
| 9019 | { 1372, 7, 1, 4, 1318, 0, 0, 1342, ARMImpOpBase + 0, 0, 0x1540c80ULL }, // Inst #1372 = MVE_VMLSDAVas16 |
| 9020 | { 1371, 7, 1, 4, 1314, 0, 0, 1263, ARMImpOpBase + 0, 0, 0x140c80ULL }, // Inst #1371 = MVE_VMLA_qr_i8 |
| 9021 | { 1370, 7, 1, 4, 1314, 0, 0, 1263, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1370 = MVE_VMLA_qr_i32 |
| 9022 | { 1369, 7, 1, 4, 1314, 0, 0, 1263, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1369 = MVE_VMLA_qr_i16 |
| 9023 | { 1368, 7, 1, 4, 1314, 0, 0, 1263, ARMImpOpBase + 0, 0, 0x140c80ULL }, // Inst #1368 = MVE_VMLAS_qr_i8 |
| 9024 | { 1367, 7, 1, 4, 1314, 0, 0, 1263, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1367 = MVE_VMLAS_qr_i32 |
| 9025 | { 1366, 7, 1, 4, 1314, 0, 0, 1263, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1366 = MVE_VMLAS_qr_i16 |
| 9026 | { 1365, 7, 2, 4, 1198, 0, 0, 1364, ARMImpOpBase + 0, 0, 0x2440c80ULL }, // Inst #1365 = MVE_VMLALDAVxs32 |
| 9027 | { 1364, 7, 2, 4, 1198, 0, 0, 1364, ARMImpOpBase + 0, 0, 0x1440c80ULL }, // Inst #1364 = MVE_VMLALDAVxs16 |
| 9028 | { 1363, 7, 2, 4, 1198, 0, 0, 1364, ARMImpOpBase + 0, 0, 0x2540c80ULL }, // Inst #1363 = MVE_VMLALDAVu32 |
| 9029 | { 1362, 7, 2, 4, 1198, 0, 0, 1364, ARMImpOpBase + 0, 0, 0x1540c80ULL }, // Inst #1362 = MVE_VMLALDAVu16 |
| 9030 | { 1361, 7, 2, 4, 1198, 0, 0, 1364, ARMImpOpBase + 0, 0, 0x2540c80ULL }, // Inst #1361 = MVE_VMLALDAVs32 |
| 9031 | { 1360, 7, 2, 4, 1198, 0, 0, 1364, ARMImpOpBase + 0, 0, 0x1540c80ULL }, // Inst #1360 = MVE_VMLALDAVs16 |
| 9032 | { 1359, 9, 2, 4, 1317, 0, 0, 1355, ARMImpOpBase + 0, 0, 0x2440c80ULL }, // Inst #1359 = MVE_VMLALDAVaxs32 |
| 9033 | { 1358, 9, 2, 4, 1317, 0, 0, 1355, ARMImpOpBase + 0, 0, 0x1440c80ULL }, // Inst #1358 = MVE_VMLALDAVaxs16 |
| 9034 | { 1357, 9, 2, 4, 1317, 0, 0, 1355, ARMImpOpBase + 0, 0, 0x2540c80ULL }, // Inst #1357 = MVE_VMLALDAVau32 |
| 9035 | { 1356, 9, 2, 4, 1317, 0, 0, 1355, ARMImpOpBase + 0, 0, 0x1540c80ULL }, // Inst #1356 = MVE_VMLALDAVau16 |
| 9036 | { 1355, 9, 2, 4, 1317, 0, 0, 1355, ARMImpOpBase + 0, 0, 0x2540c80ULL }, // Inst #1355 = MVE_VMLALDAVas32 |
| 9037 | { 1354, 9, 2, 4, 1317, 0, 0, 1355, ARMImpOpBase + 0, 0, 0x1540c80ULL }, // Inst #1354 = MVE_VMLALDAVas16 |
| 9038 | { 1353, 6, 1, 4, 1197, 0, 0, 1349, ARMImpOpBase + 0, 0, 0x440c80ULL }, // Inst #1353 = MVE_VMLADAVxs8 |
| 9039 | { 1352, 6, 1, 4, 1197, 0, 0, 1349, ARMImpOpBase + 0, 0, 0x2440c80ULL }, // Inst #1352 = MVE_VMLADAVxs32 |
| 9040 | { 1351, 6, 1, 4, 1197, 0, 0, 1349, ARMImpOpBase + 0, 0, 0x1440c80ULL }, // Inst #1351 = MVE_VMLADAVxs16 |
| 9041 | { 1350, 6, 1, 4, 1197, 0, 0, 1349, ARMImpOpBase + 0, 0, 0x540c80ULL }, // Inst #1350 = MVE_VMLADAVu8 |
| 9042 | { 1349, 6, 1, 4, 1197, 0, 0, 1349, ARMImpOpBase + 0, 0, 0x2540c80ULL }, // Inst #1349 = MVE_VMLADAVu32 |
| 9043 | { 1348, 6, 1, 4, 1197, 0, 0, 1349, ARMImpOpBase + 0, 0, 0x1540c80ULL }, // Inst #1348 = MVE_VMLADAVu16 |
| 9044 | { 1347, 6, 1, 4, 1197, 0, 0, 1349, ARMImpOpBase + 0, 0, 0x540c80ULL }, // Inst #1347 = MVE_VMLADAVs8 |
| 9045 | { 1346, 6, 1, 4, 1197, 0, 0, 1349, ARMImpOpBase + 0, 0, 0x2540c80ULL }, // Inst #1346 = MVE_VMLADAVs32 |
| 9046 | { 1345, 6, 1, 4, 1197, 0, 0, 1349, ARMImpOpBase + 0, 0, 0x1540c80ULL }, // Inst #1345 = MVE_VMLADAVs16 |
| 9047 | { 1344, 7, 1, 4, 1318, 0, 0, 1342, ARMImpOpBase + 0, 0, 0x440c80ULL }, // Inst #1344 = MVE_VMLADAVaxs8 |
| 9048 | { 1343, 7, 1, 4, 1318, 0, 0, 1342, ARMImpOpBase + 0, 0, 0x2440c80ULL }, // Inst #1343 = MVE_VMLADAVaxs32 |
| 9049 | { 1342, 7, 1, 4, 1318, 0, 0, 1342, ARMImpOpBase + 0, 0, 0x1440c80ULL }, // Inst #1342 = MVE_VMLADAVaxs16 |
| 9050 | { 1341, 7, 1, 4, 1318, 0, 0, 1342, ARMImpOpBase + 0, 0, 0x540c80ULL }, // Inst #1341 = MVE_VMLADAVau8 |
| 9051 | { 1340, 7, 1, 4, 1318, 0, 0, 1342, ARMImpOpBase + 0, 0, 0x2540c80ULL }, // Inst #1340 = MVE_VMLADAVau32 |
| 9052 | { 1339, 7, 1, 4, 1318, 0, 0, 1342, ARMImpOpBase + 0, 0, 0x1540c80ULL }, // Inst #1339 = MVE_VMLADAVau16 |
| 9053 | { 1338, 7, 1, 4, 1318, 0, 0, 1342, ARMImpOpBase + 0, 0, 0x540c80ULL }, // Inst #1338 = MVE_VMLADAVas8 |
| 9054 | { 1337, 7, 1, 4, 1318, 0, 0, 1342, ARMImpOpBase + 0, 0, 0x2540c80ULL }, // Inst #1337 = MVE_VMLADAVas32 |
| 9055 | { 1336, 7, 1, 4, 1318, 0, 0, 1342, ARMImpOpBase + 0, 0, 0x1540c80ULL }, // Inst #1336 = MVE_VMLADAVas16 |
| 9056 | { 1335, 7, 1, 4, 1141, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x140c80ULL }, // Inst #1335 = MVE_VMINu8 |
| 9057 | { 1334, 7, 1, 4, 1141, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1334 = MVE_VMINu32 |
| 9058 | { 1333, 7, 1, 4, 1141, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1333 = MVE_VMINu16 |
| 9059 | { 1332, 7, 1, 4, 1141, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x140c80ULL }, // Inst #1332 = MVE_VMINs8 |
| 9060 | { 1331, 7, 1, 4, 1141, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1331 = MVE_VMINs32 |
| 9061 | { 1330, 7, 1, 4, 1141, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1330 = MVE_VMINs16 |
| 9062 | { 1329, 6, 1, 4, 1142, 0, 0, 1336, ARMImpOpBase + 0, 0, 0x440c80ULL }, // Inst #1329 = MVE_VMINVu8 |
| 9063 | { 1328, 6, 1, 4, 1144, 0, 0, 1336, ARMImpOpBase + 0, 0, 0x2440c80ULL }, // Inst #1328 = MVE_VMINVu32 |
| 9064 | { 1327, 6, 1, 4, 1143, 0, 0, 1336, ARMImpOpBase + 0, 0, 0x1440c80ULL }, // Inst #1327 = MVE_VMINVu16 |
| 9065 | { 1326, 6, 1, 4, 1142, 0, 0, 1336, ARMImpOpBase + 0, 0, 0x440c80ULL }, // Inst #1326 = MVE_VMINVs8 |
| 9066 | { 1325, 6, 1, 4, 1144, 0, 0, 1336, ARMImpOpBase + 0, 0, 0x2440c80ULL }, // Inst #1325 = MVE_VMINVs32 |
| 9067 | { 1324, 6, 1, 4, 1143, 0, 0, 1336, ARMImpOpBase + 0, 0, 0x1440c80ULL }, // Inst #1324 = MVE_VMINVs16 |
| 9068 | { 1323, 7, 1, 4, 1309, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1323 = MVE_VMINNMf32 |
| 9069 | { 1322, 7, 1, 4, 1309, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1322 = MVE_VMINNMf16 |
| 9070 | { 1321, 6, 1, 4, 1189, 0, 0, 1336, ARMImpOpBase + 0, 0, 0x2440c80ULL }, // Inst #1321 = MVE_VMINNMVf32 |
| 9071 | { 1320, 6, 1, 4, 1189, 0, 0, 1336, ARMImpOpBase + 0, 0, 0x1440c80ULL }, // Inst #1320 = MVE_VMINNMVf16 |
| 9072 | { 1319, 6, 1, 4, 1309, 0, 0, 1227, ARMImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x2140c80ULL }, // Inst #1319 = MVE_VMINNMAf32 |
| 9073 | { 1318, 6, 1, 4, 1309, 0, 0, 1227, ARMImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x1140c80ULL }, // Inst #1318 = MVE_VMINNMAf16 |
| 9074 | { 1317, 6, 1, 4, 1189, 0, 0, 1336, ARMImpOpBase + 0, 0, 0x2440c80ULL }, // Inst #1317 = MVE_VMINNMAVf32 |
| 9075 | { 1316, 6, 1, 4, 1189, 0, 0, 1336, ARMImpOpBase + 0, 0, 0x1440c80ULL }, // Inst #1316 = MVE_VMINNMAVf16 |
| 9076 | { 1315, 6, 1, 4, 1141, 0, 0, 1227, ARMImpOpBase + 0, 0, 0x140c80ULL }, // Inst #1315 = MVE_VMINAs8 |
| 9077 | { 1314, 6, 1, 4, 1141, 0, 0, 1227, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1314 = MVE_VMINAs32 |
| 9078 | { 1313, 6, 1, 4, 1141, 0, 0, 1227, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1313 = MVE_VMINAs16 |
| 9079 | { 1312, 6, 1, 4, 1142, 0, 0, 1336, ARMImpOpBase + 0, 0, 0x440c80ULL }, // Inst #1312 = MVE_VMINAVs8 |
| 9080 | { 1311, 6, 1, 4, 1144, 0, 0, 1336, ARMImpOpBase + 0, 0, 0x2440c80ULL }, // Inst #1311 = MVE_VMINAVs32 |
| 9081 | { 1310, 6, 1, 4, 1143, 0, 0, 1336, ARMImpOpBase + 0, 0, 0x1440c80ULL }, // Inst #1310 = MVE_VMINAVs16 |
| 9082 | { 1309, 7, 1, 4, 1141, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x140c80ULL }, // Inst #1309 = MVE_VMAXu8 |
| 9083 | { 1308, 7, 1, 4, 1141, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1308 = MVE_VMAXu32 |
| 9084 | { 1307, 7, 1, 4, 1141, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1307 = MVE_VMAXu16 |
| 9085 | { 1306, 7, 1, 4, 1141, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x140c80ULL }, // Inst #1306 = MVE_VMAXs8 |
| 9086 | { 1305, 7, 1, 4, 1141, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1305 = MVE_VMAXs32 |
| 9087 | { 1304, 7, 1, 4, 1141, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1304 = MVE_VMAXs16 |
| 9088 | { 1303, 6, 1, 4, 1142, 0, 0, 1336, ARMImpOpBase + 0, 0, 0x440c80ULL }, // Inst #1303 = MVE_VMAXVu8 |
| 9089 | { 1302, 6, 1, 4, 1144, 0, 0, 1336, ARMImpOpBase + 0, 0, 0x2440c80ULL }, // Inst #1302 = MVE_VMAXVu32 |
| 9090 | { 1301, 6, 1, 4, 1143, 0, 0, 1336, ARMImpOpBase + 0, 0, 0x1440c80ULL }, // Inst #1301 = MVE_VMAXVu16 |
| 9091 | { 1300, 6, 1, 4, 1142, 0, 0, 1336, ARMImpOpBase + 0, 0, 0x440c80ULL }, // Inst #1300 = MVE_VMAXVs8 |
| 9092 | { 1299, 6, 1, 4, 1144, 0, 0, 1336, ARMImpOpBase + 0, 0, 0x2440c80ULL }, // Inst #1299 = MVE_VMAXVs32 |
| 9093 | { 1298, 6, 1, 4, 1143, 0, 0, 1336, ARMImpOpBase + 0, 0, 0x1440c80ULL }, // Inst #1298 = MVE_VMAXVs16 |
| 9094 | { 1297, 7, 1, 4, 1309, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1297 = MVE_VMAXNMf32 |
| 9095 | { 1296, 7, 1, 4, 1309, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1296 = MVE_VMAXNMf16 |
| 9096 | { 1295, 6, 1, 4, 1189, 0, 0, 1336, ARMImpOpBase + 0, 0, 0x2440c80ULL }, // Inst #1295 = MVE_VMAXNMVf32 |
| 9097 | { 1294, 6, 1, 4, 1189, 0, 0, 1336, ARMImpOpBase + 0, 0, 0x1440c80ULL }, // Inst #1294 = MVE_VMAXNMVf16 |
| 9098 | { 1293, 6, 1, 4, 1309, 0, 0, 1227, ARMImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x2140c80ULL }, // Inst #1293 = MVE_VMAXNMAf32 |
| 9099 | { 1292, 6, 1, 4, 1309, 0, 0, 1227, ARMImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x1140c80ULL }, // Inst #1292 = MVE_VMAXNMAf16 |
| 9100 | { 1291, 6, 1, 4, 1189, 0, 0, 1336, ARMImpOpBase + 0, 0, 0x2440c80ULL }, // Inst #1291 = MVE_VMAXNMAVf32 |
| 9101 | { 1290, 6, 1, 4, 1189, 0, 0, 1336, ARMImpOpBase + 0, 0, 0x1440c80ULL }, // Inst #1290 = MVE_VMAXNMAVf16 |
| 9102 | { 1289, 6, 1, 4, 1141, 0, 0, 1227, ARMImpOpBase + 0, 0, 0x140c80ULL }, // Inst #1289 = MVE_VMAXAs8 |
| 9103 | { 1288, 6, 1, 4, 1141, 0, 0, 1227, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1288 = MVE_VMAXAs32 |
| 9104 | { 1287, 6, 1, 4, 1141, 0, 0, 1227, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1287 = MVE_VMAXAs16 |
| 9105 | { 1286, 6, 1, 4, 1142, 0, 0, 1336, ARMImpOpBase + 0, 0, 0x440c80ULL }, // Inst #1286 = MVE_VMAXAVs8 |
| 9106 | { 1285, 6, 1, 4, 1144, 0, 0, 1336, ARMImpOpBase + 0, 0, 0x2440c80ULL }, // Inst #1285 = MVE_VMAXAVs32 |
| 9107 | { 1284, 6, 1, 4, 1143, 0, 0, 1336, ARMImpOpBase + 0, 0, 0x1440c80ULL }, // Inst #1284 = MVE_VMAXAVs16 |
| 9108 | { 1283, 6, 1, 4, 1115, 0, 0, 1304, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x2140c80ULL }, // Inst #1283 = MVE_VLDRWU32_rq_u |
| 9109 | { 1282, 6, 1, 4, 1115, 0, 0, 1304, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x2140c80ULL }, // Inst #1282 = MVE_VLDRWU32_rq |
| 9110 | { 1281, 7, 2, 4, 1117, 0, 0, 1329, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x2140c80ULL }, // Inst #1281 = MVE_VLDRWU32_qi_pre |
| 9111 | { 1280, 6, 1, 4, 1116, 0, 0, 1323, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x2140c80ULL }, // Inst #1280 = MVE_VLDRWU32_qi |
| 9112 | { 1279, 7, 2, 4, 1114, 0, 0, 1316, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x2140cb5ULL }, // Inst #1279 = MVE_VLDRWU32_pre |
| 9113 | { 1278, 7, 2, 4, 1114, 0, 0, 1316, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x2140cd5ULL }, // Inst #1278 = MVE_VLDRWU32_post |
| 9114 | { 1277, 6, 1, 4, 1113, 0, 0, 1310, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x2140c95ULL }, // Inst #1277 = MVE_VLDRWU32 |
| 9115 | { 1276, 6, 1, 4, 1115, 0, 0, 1304, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x2140c80ULL }, // Inst #1276 = MVE_VLDRHU32_rq_u |
| 9116 | { 1275, 6, 1, 4, 1115, 0, 0, 1304, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x2140c80ULL }, // Inst #1275 = MVE_VLDRHU32_rq |
| 9117 | { 1274, 7, 2, 4, 1114, 0, 0, 1297, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x2140cb6ULL }, // Inst #1274 = MVE_VLDRHU32_pre |
| 9118 | { 1273, 7, 2, 4, 1114, 0, 0, 1297, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x2140cd6ULL }, // Inst #1273 = MVE_VLDRHU32_post |
| 9119 | { 1272, 6, 1, 4, 1113, 0, 0, 1291, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x2140c96ULL }, // Inst #1272 = MVE_VLDRHU32 |
| 9120 | { 1271, 6, 1, 4, 1115, 0, 0, 1304, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x1140c80ULL }, // Inst #1271 = MVE_VLDRHU16_rq_u |
| 9121 | { 1270, 6, 1, 4, 1115, 0, 0, 1304, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x1140c80ULL }, // Inst #1270 = MVE_VLDRHU16_rq |
| 9122 | { 1269, 7, 2, 4, 1114, 0, 0, 1316, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x1140cb6ULL }, // Inst #1269 = MVE_VLDRHU16_pre |
| 9123 | { 1268, 7, 2, 4, 1114, 0, 0, 1316, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x1140cd6ULL }, // Inst #1268 = MVE_VLDRHU16_post |
| 9124 | { 1267, 6, 1, 4, 1113, 0, 0, 1310, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x1140c96ULL }, // Inst #1267 = MVE_VLDRHU16 |
| 9125 | { 1266, 6, 1, 4, 1115, 0, 0, 1304, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x2140c80ULL }, // Inst #1266 = MVE_VLDRHS32_rq_u |
| 9126 | { 1265, 6, 1, 4, 1115, 0, 0, 1304, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x2140c80ULL }, // Inst #1265 = MVE_VLDRHS32_rq |
| 9127 | { 1264, 7, 2, 4, 1114, 0, 0, 1297, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x2140cb6ULL }, // Inst #1264 = MVE_VLDRHS32_pre |
| 9128 | { 1263, 7, 2, 4, 1114, 0, 0, 1297, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x2140cd6ULL }, // Inst #1263 = MVE_VLDRHS32_post |
| 9129 | { 1262, 6, 1, 4, 1113, 0, 0, 1291, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x2140c96ULL }, // Inst #1262 = MVE_VLDRHS32 |
| 9130 | { 1261, 6, 1, 4, 1115, 0, 0, 1304, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x3140c80ULL }, // Inst #1261 = MVE_VLDRDU64_rq_u |
| 9131 | { 1260, 6, 1, 4, 1115, 0, 0, 1304, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x3140c80ULL }, // Inst #1260 = MVE_VLDRDU64_rq |
| 9132 | { 1259, 7, 2, 4, 1117, 0, 0, 1329, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x3140c80ULL }, // Inst #1259 = MVE_VLDRDU64_qi_pre |
| 9133 | { 1258, 6, 1, 4, 1116, 0, 0, 1323, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x3140c80ULL }, // Inst #1258 = MVE_VLDRDU64_qi |
| 9134 | { 1257, 6, 1, 4, 1115, 0, 0, 1304, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x140c80ULL }, // Inst #1257 = MVE_VLDRBU8_rq |
| 9135 | { 1256, 7, 2, 4, 1114, 0, 0, 1316, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x140cb7ULL }, // Inst #1256 = MVE_VLDRBU8_pre |
| 9136 | { 1255, 7, 2, 4, 1114, 0, 0, 1316, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x140cd7ULL }, // Inst #1255 = MVE_VLDRBU8_post |
| 9137 | { 1254, 6, 1, 4, 1113, 0, 0, 1310, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x140c97ULL }, // Inst #1254 = MVE_VLDRBU8 |
| 9138 | { 1253, 6, 1, 4, 1115, 0, 0, 1304, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x2140c80ULL }, // Inst #1253 = MVE_VLDRBU32_rq |
| 9139 | { 1252, 7, 2, 4, 1114, 0, 0, 1297, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x2140cb7ULL }, // Inst #1252 = MVE_VLDRBU32_pre |
| 9140 | { 1251, 7, 2, 4, 1114, 0, 0, 1297, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x2140cd7ULL }, // Inst #1251 = MVE_VLDRBU32_post |
| 9141 | { 1250, 6, 1, 4, 1113, 0, 0, 1291, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x2140c97ULL }, // Inst #1250 = MVE_VLDRBU32 |
| 9142 | { 1249, 6, 1, 4, 1115, 0, 0, 1304, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x1140c80ULL }, // Inst #1249 = MVE_VLDRBU16_rq |
| 9143 | { 1248, 7, 2, 4, 1114, 0, 0, 1297, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x1140cb7ULL }, // Inst #1248 = MVE_VLDRBU16_pre |
| 9144 | { 1247, 7, 2, 4, 1114, 0, 0, 1297, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x1140cd7ULL }, // Inst #1247 = MVE_VLDRBU16_post |
| 9145 | { 1246, 6, 1, 4, 1113, 0, 0, 1291, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x1140c97ULL }, // Inst #1246 = MVE_VLDRBU16 |
| 9146 | { 1245, 6, 1, 4, 1115, 0, 0, 1304, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x2140c80ULL }, // Inst #1245 = MVE_VLDRBS32_rq |
| 9147 | { 1244, 7, 2, 4, 1114, 0, 0, 1297, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x2140cb7ULL }, // Inst #1244 = MVE_VLDRBS32_pre |
| 9148 | { 1243, 7, 2, 4, 1114, 0, 0, 1297, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x2140cd7ULL }, // Inst #1243 = MVE_VLDRBS32_post |
| 9149 | { 1242, 6, 1, 4, 1113, 0, 0, 1291, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x2140c97ULL }, // Inst #1242 = MVE_VLDRBS32 |
| 9150 | { 1241, 6, 1, 4, 1115, 0, 0, 1304, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x1140c80ULL }, // Inst #1241 = MVE_VLDRBS16_rq |
| 9151 | { 1240, 7, 2, 4, 1114, 0, 0, 1297, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x1140cb7ULL }, // Inst #1240 = MVE_VLDRBS16_pre |
| 9152 | { 1239, 7, 2, 4, 1114, 0, 0, 1297, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x1140cd7ULL }, // Inst #1239 = MVE_VLDRBS16_post |
| 9153 | { 1238, 6, 1, 4, 1113, 0, 0, 1291, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x1140c97ULL }, // Inst #1238 = MVE_VLDRBS16 |
| 9154 | { 1237, 4, 2, 4, 1119, 0, 0, 1287, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x140c80ULL }, // Inst #1237 = MVE_VLD43_8_wb |
| 9155 | { 1236, 3, 1, 4, 1118, 0, 0, 1284, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x140c80ULL }, // Inst #1236 = MVE_VLD43_8 |
| 9156 | { 1235, 4, 2, 4, 1119, 0, 0, 1287, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x2140c80ULL }, // Inst #1235 = MVE_VLD43_32_wb |
| 9157 | { 1234, 3, 1, 4, 1118, 0, 0, 1284, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x2140c80ULL }, // Inst #1234 = MVE_VLD43_32 |
| 9158 | { 1233, 4, 2, 4, 1119, 0, 0, 1287, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x1140c80ULL }, // Inst #1233 = MVE_VLD43_16_wb |
| 9159 | { 1232, 3, 1, 4, 1118, 0, 0, 1284, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x1140c80ULL }, // Inst #1232 = MVE_VLD43_16 |
| 9160 | { 1231, 4, 2, 4, 1119, 0, 0, 1287, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x140c80ULL }, // Inst #1231 = MVE_VLD42_8_wb |
| 9161 | { 1230, 3, 1, 4, 1118, 0, 0, 1284, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x140c80ULL }, // Inst #1230 = MVE_VLD42_8 |
| 9162 | { 1229, 4, 2, 4, 1119, 0, 0, 1287, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x2140c80ULL }, // Inst #1229 = MVE_VLD42_32_wb |
| 9163 | { 1228, 3, 1, 4, 1118, 0, 0, 1284, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x2140c80ULL }, // Inst #1228 = MVE_VLD42_32 |
| 9164 | { 1227, 4, 2, 4, 1119, 0, 0, 1287, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x1140c80ULL }, // Inst #1227 = MVE_VLD42_16_wb |
| 9165 | { 1226, 3, 1, 4, 1118, 0, 0, 1284, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x1140c80ULL }, // Inst #1226 = MVE_VLD42_16 |
| 9166 | { 1225, 4, 2, 4, 1119, 0, 0, 1287, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x140c80ULL }, // Inst #1225 = MVE_VLD41_8_wb |
| 9167 | { 1224, 3, 1, 4, 1118, 0, 0, 1284, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x140c80ULL }, // Inst #1224 = MVE_VLD41_8 |
| 9168 | { 1223, 4, 2, 4, 1119, 0, 0, 1287, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x2140c80ULL }, // Inst #1223 = MVE_VLD41_32_wb |
| 9169 | { 1222, 3, 1, 4, 1118, 0, 0, 1284, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x2140c80ULL }, // Inst #1222 = MVE_VLD41_32 |
| 9170 | { 1221, 4, 2, 4, 1119, 0, 0, 1287, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x1140c80ULL }, // Inst #1221 = MVE_VLD41_16_wb |
| 9171 | { 1220, 3, 1, 4, 1118, 0, 0, 1284, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x1140c80ULL }, // Inst #1220 = MVE_VLD41_16 |
| 9172 | { 1219, 4, 2, 4, 1119, 0, 0, 1287, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x140c80ULL }, // Inst #1219 = MVE_VLD40_8_wb |
| 9173 | { 1218, 3, 1, 4, 1118, 0, 0, 1284, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x140c80ULL }, // Inst #1218 = MVE_VLD40_8 |
| 9174 | { 1217, 4, 2, 4, 1119, 0, 0, 1287, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x2140c80ULL }, // Inst #1217 = MVE_VLD40_32_wb |
| 9175 | { 1216, 3, 1, 4, 1118, 0, 0, 1284, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x2140c80ULL }, // Inst #1216 = MVE_VLD40_32 |
| 9176 | { 1215, 4, 2, 4, 1119, 0, 0, 1287, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x1140c80ULL }, // Inst #1215 = MVE_VLD40_16_wb |
| 9177 | { 1214, 3, 1, 4, 1118, 0, 0, 1284, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x1140c80ULL }, // Inst #1214 = MVE_VLD40_16 |
| 9178 | { 1213, 4, 2, 4, 1119, 0, 0, 1280, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x140c80ULL }, // Inst #1213 = MVE_VLD21_8_wb |
| 9179 | { 1212, 3, 1, 4, 1118, 0, 0, 1277, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x140c80ULL }, // Inst #1212 = MVE_VLD21_8 |
| 9180 | { 1211, 4, 2, 4, 1119, 0, 0, 1280, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x2140c80ULL }, // Inst #1211 = MVE_VLD21_32_wb |
| 9181 | { 1210, 3, 1, 4, 1118, 0, 0, 1277, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x2140c80ULL }, // Inst #1210 = MVE_VLD21_32 |
| 9182 | { 1209, 4, 2, 4, 1119, 0, 0, 1280, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x1140c80ULL }, // Inst #1209 = MVE_VLD21_16_wb |
| 9183 | { 1208, 3, 1, 4, 1118, 0, 0, 1277, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x1140c80ULL }, // Inst #1208 = MVE_VLD21_16 |
| 9184 | { 1207, 4, 2, 4, 1119, 0, 0, 1280, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x140c80ULL }, // Inst #1207 = MVE_VLD20_8_wb |
| 9185 | { 1206, 3, 1, 4, 1118, 0, 0, 1277, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x140c80ULL }, // Inst #1206 = MVE_VLD20_8 |
| 9186 | { 1205, 4, 2, 4, 1119, 0, 0, 1280, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x2140c80ULL }, // Inst #1205 = MVE_VLD20_32_wb |
| 9187 | { 1204, 3, 1, 4, 1118, 0, 0, 1277, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x2140c80ULL }, // Inst #1204 = MVE_VLD20_32 |
| 9188 | { 1203, 4, 2, 4, 1119, 0, 0, 1280, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x1140c80ULL }, // Inst #1203 = MVE_VLD20_16_wb |
| 9189 | { 1202, 3, 1, 4, 1118, 0, 0, 1277, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x1140c80ULL }, // Inst #1202 = MVE_VLD20_16 |
| 9190 | { 1201, 9, 2, 4, 1305, 0, 0, 1254, ARMImpOpBase + 0, 0, 0x140c80ULL }, // Inst #1201 = MVE_VIWDUPu8 |
| 9191 | { 1200, 9, 2, 4, 1305, 0, 0, 1254, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1200 = MVE_VIWDUPu32 |
| 9192 | { 1199, 9, 2, 4, 1305, 0, 0, 1254, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1199 = MVE_VIWDUPu16 |
| 9193 | { 1198, 8, 2, 4, 1306, 0, 0, 1240, ARMImpOpBase + 0, 0, 0x140c80ULL }, // Inst #1198 = MVE_VIDUPu8 |
| 9194 | { 1197, 8, 2, 4, 1306, 0, 0, 1240, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1197 = MVE_VIDUPu32 |
| 9195 | { 1196, 8, 2, 4, 1306, 0, 0, 1240, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1196 = MVE_VIDUPu16 |
| 9196 | { 1195, 7, 1, 4, 1140, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x140c80ULL }, // Inst #1195 = MVE_VHSUBu8 |
| 9197 | { 1194, 7, 1, 4, 1140, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1194 = MVE_VHSUBu32 |
| 9198 | { 1193, 7, 1, 4, 1140, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1193 = MVE_VHSUBu16 |
| 9199 | { 1192, 7, 1, 4, 1140, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x140c80ULL }, // Inst #1192 = MVE_VHSUBs8 |
| 9200 | { 1191, 7, 1, 4, 1140, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1191 = MVE_VHSUBs32 |
| 9201 | { 1190, 7, 1, 4, 1140, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1190 = MVE_VHSUBs16 |
| 9202 | { 1189, 7, 1, 4, 1298, 0, 0, 1163, ARMImpOpBase + 0, 0, 0x140c80ULL }, // Inst #1189 = MVE_VHSUB_qr_u8 |
| 9203 | { 1188, 7, 1, 4, 1298, 0, 0, 1163, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1188 = MVE_VHSUB_qr_u32 |
| 9204 | { 1187, 7, 1, 4, 1298, 0, 0, 1163, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1187 = MVE_VHSUB_qr_u16 |
| 9205 | { 1186, 7, 1, 4, 1298, 0, 0, 1163, ARMImpOpBase + 0, 0, 0x140c80ULL }, // Inst #1186 = MVE_VHSUB_qr_s8 |
| 9206 | { 1185, 7, 1, 4, 1298, 0, 0, 1163, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1185 = MVE_VHSUB_qr_s32 |
| 9207 | { 1184, 7, 1, 4, 1298, 0, 0, 1163, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1184 = MVE_VHSUB_qr_s16 |
| 9208 | { 1183, 8, 1, 4, 1139, 0, 0, 1176, ARMImpOpBase + 0, 0, 0x40c80ULL }, // Inst #1183 = MVE_VHCADDs8 |
| 9209 | { 1182, 8, 1, 4, 1139, 0, 0, 1184, ARMImpOpBase + 0, 0, 0x2040c80ULL }, // Inst #1182 = MVE_VHCADDs32 |
| 9210 | { 1181, 8, 1, 4, 1139, 0, 0, 1176, ARMImpOpBase + 0, 0, 0x1040c80ULL }, // Inst #1181 = MVE_VHCADDs16 |
| 9211 | { 1180, 7, 1, 4, 1138, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x140c80ULL }, // Inst #1180 = MVE_VHADDu8 |
| 9212 | { 1179, 7, 1, 4, 1138, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1179 = MVE_VHADDu32 |
| 9213 | { 1178, 7, 1, 4, 1138, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1178 = MVE_VHADDu16 |
| 9214 | { 1177, 7, 1, 4, 1138, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x140c80ULL }, // Inst #1177 = MVE_VHADDs8 |
| 9215 | { 1176, 7, 1, 4, 1138, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1176 = MVE_VHADDs32 |
| 9216 | { 1175, 7, 1, 4, 1138, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1175 = MVE_VHADDs16 |
| 9217 | { 1174, 7, 1, 4, 1297, 0, 0, 1163, ARMImpOpBase + 0, 0, 0x140c80ULL }, // Inst #1174 = MVE_VHADD_qr_u8 |
| 9218 | { 1173, 7, 1, 4, 1297, 0, 0, 1163, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1173 = MVE_VHADD_qr_u32 |
| 9219 | { 1172, 7, 1, 4, 1297, 0, 0, 1163, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1172 = MVE_VHADD_qr_u16 |
| 9220 | { 1171, 7, 1, 4, 1297, 0, 0, 1163, ARMImpOpBase + 0, 0, 0x140c80ULL }, // Inst #1171 = MVE_VHADD_qr_s8 |
| 9221 | { 1170, 7, 1, 4, 1297, 0, 0, 1163, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1170 = MVE_VHADD_qr_s32 |
| 9222 | { 1169, 7, 1, 4, 1297, 0, 0, 1163, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1169 = MVE_VHADD_qr_s16 |
| 9223 | { 1168, 7, 1, 4, 1188, 0, 0, 1270, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1168 = MVE_VFMSf32 |
| 9224 | { 1167, 7, 1, 4, 1188, 0, 0, 1270, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1167 = MVE_VFMSf16 |
| 9225 | { 1166, 7, 1, 4, 1188, 0, 0, 1270, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1166 = MVE_VFMAf32 |
| 9226 | { 1165, 7, 1, 4, 1188, 0, 0, 1270, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1165 = MVE_VFMAf16 |
| 9227 | { 1164, 7, 1, 4, 1321, 0, 0, 1263, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1164 = MVE_VFMA_qr_f32 |
| 9228 | { 1163, 7, 1, 4, 1321, 0, 0, 1263, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1163 = MVE_VFMA_qr_f16 |
| 9229 | { 1162, 7, 1, 4, 1321, 0, 0, 1263, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1162 = MVE_VFMA_qr_Sf32 |
| 9230 | { 1161, 7, 1, 4, 1321, 0, 0, 1263, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1161 = MVE_VFMA_qr_Sf16 |
| 9231 | { 1160, 7, 1, 4, 1137, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x140c80ULL }, // Inst #1160 = MVE_VEOR |
| 9232 | { 1159, 9, 2, 4, 1305, 0, 0, 1254, ARMImpOpBase + 0, 0, 0x140c80ULL }, // Inst #1159 = MVE_VDWDUPu8 |
| 9233 | { 1158, 9, 2, 4, 1305, 0, 0, 1254, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1158 = MVE_VDWDUPu32 |
| 9234 | { 1157, 9, 2, 4, 1305, 0, 0, 1254, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1157 = MVE_VDWDUPu16 |
| 9235 | { 1156, 6, 1, 4, 1136, 0, 0, 1248, ARMImpOpBase + 0, 0, 0x140c80ULL }, // Inst #1156 = MVE_VDUP8 |
| 9236 | { 1155, 6, 1, 4, 1136, 0, 0, 1248, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1155 = MVE_VDUP32 |
| 9237 | { 1154, 6, 1, 4, 1136, 0, 0, 1248, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1154 = MVE_VDUP16 |
| 9238 | { 1153, 8, 2, 4, 1306, 0, 0, 1240, ARMImpOpBase + 0, 0, 0x140c80ULL }, // Inst #1153 = MVE_VDDUPu8 |
| 9239 | { 1152, 8, 2, 4, 1306, 0, 0, 1240, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1152 = MVE_VDDUPu32 |
| 9240 | { 1151, 8, 2, 4, 1306, 0, 0, 1240, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1151 = MVE_VDDUPu16 |
| 9241 | { 1150, 6, 1, 4, 1185, 0, 0, 1115, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1150 = MVE_VCVTu32f32z |
| 9242 | { 1149, 6, 1, 4, 1185, 0, 0, 1115, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1149 = MVE_VCVTu32f32p |
| 9243 | { 1148, 6, 1, 4, 1185, 0, 0, 1115, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1148 = MVE_VCVTu32f32n |
| 9244 | { 1147, 6, 1, 4, 1185, 0, 0, 1115, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1147 = MVE_VCVTu32f32m |
| 9245 | { 1146, 6, 1, 4, 1185, 0, 0, 1115, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1146 = MVE_VCVTu32f32a |
| 9246 | { 1145, 7, 1, 4, 1185, 0, 0, 1233, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1145 = MVE_VCVTu32f32_fix |
| 9247 | { 1144, 6, 1, 4, 1184, 0, 0, 1115, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1144 = MVE_VCVTu16f16z |
| 9248 | { 1143, 6, 1, 4, 1184, 0, 0, 1115, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1143 = MVE_VCVTu16f16p |
| 9249 | { 1142, 6, 1, 4, 1184, 0, 0, 1115, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1142 = MVE_VCVTu16f16n |
| 9250 | { 1141, 6, 1, 4, 1184, 0, 0, 1115, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1141 = MVE_VCVTu16f16m |
| 9251 | { 1140, 6, 1, 4, 1184, 0, 0, 1115, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1140 = MVE_VCVTu16f16a |
| 9252 | { 1139, 7, 1, 4, 1184, 0, 0, 1233, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1139 = MVE_VCVTu16f16_fix |
| 9253 | { 1138, 6, 1, 4, 1185, 0, 0, 1115, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1138 = MVE_VCVTs32f32z |
| 9254 | { 1137, 6, 1, 4, 1185, 0, 0, 1115, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1137 = MVE_VCVTs32f32p |
| 9255 | { 1136, 6, 1, 4, 1185, 0, 0, 1115, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1136 = MVE_VCVTs32f32n |
| 9256 | { 1135, 6, 1, 4, 1185, 0, 0, 1115, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1135 = MVE_VCVTs32f32m |
| 9257 | { 1134, 6, 1, 4, 1185, 0, 0, 1115, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1134 = MVE_VCVTs32f32a |
| 9258 | { 1133, 7, 1, 4, 1185, 0, 0, 1233, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1133 = MVE_VCVTs32f32_fix |
| 9259 | { 1132, 6, 1, 4, 1184, 0, 0, 1115, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1132 = MVE_VCVTs16f16z |
| 9260 | { 1131, 6, 1, 4, 1184, 0, 0, 1115, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1131 = MVE_VCVTs16f16p |
| 9261 | { 1130, 6, 1, 4, 1184, 0, 0, 1115, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1130 = MVE_VCVTs16f16n |
| 9262 | { 1129, 6, 1, 4, 1184, 0, 0, 1115, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1129 = MVE_VCVTs16f16m |
| 9263 | { 1128, 6, 1, 4, 1184, 0, 0, 1115, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1128 = MVE_VCVTs16f16a |
| 9264 | { 1127, 7, 1, 4, 1184, 0, 0, 1233, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1127 = MVE_VCVTs16f16_fix |
| 9265 | { 1126, 6, 1, 4, 1183, 0, 0, 1115, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1126 = MVE_VCVTf32u32n |
| 9266 | { 1125, 7, 1, 4, 1183, 0, 0, 1233, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1125 = MVE_VCVTf32u32_fix |
| 9267 | { 1124, 6, 1, 4, 1183, 0, 0, 1115, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1124 = MVE_VCVTf32s32n |
| 9268 | { 1123, 7, 1, 4, 1183, 0, 0, 1233, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1123 = MVE_VCVTf32s32_fix |
| 9269 | { 1122, 6, 1, 4, 1187, 0, 0, 1115, ARMImpOpBase + 0, 0, 0x2240c80ULL }, // Inst #1122 = MVE_VCVTf32f16th |
| 9270 | { 1121, 6, 1, 4, 1187, 0, 0, 1115, ARMImpOpBase + 0, 0, 0x2240c80ULL }, // Inst #1121 = MVE_VCVTf32f16bh |
| 9271 | { 1120, 6, 1, 4, 1182, 0, 0, 1115, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1120 = MVE_VCVTf16u16n |
| 9272 | { 1119, 7, 1, 4, 1182, 0, 0, 1233, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1119 = MVE_VCVTf16u16_fix |
| 9273 | { 1118, 6, 1, 4, 1182, 0, 0, 1115, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1118 = MVE_VCVTf16s16n |
| 9274 | { 1117, 7, 1, 4, 1182, 0, 0, 1233, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1117 = MVE_VCVTf16s16_fix |
| 9275 | { 1116, 6, 1, 4, 1186, 0, 0, 1227, ARMImpOpBase + 0, 0, 0x2240c80ULL }, // Inst #1116 = MVE_VCVTf16f32th |
| 9276 | { 1115, 6, 1, 4, 1186, 0, 0, 1227, ARMImpOpBase + 0, 0, 0x2240c80ULL }, // Inst #1115 = MVE_VCVTf16f32bh |
| 9277 | { 1114, 5, 1, 4, 1204, 0, 0, 1222, ARMImpOpBase + 0, 0|(1ULL<<MCID::Rematerializable), 0x140c80ULL }, // Inst #1114 = MVE_VCTP8 |
| 9278 | { 1113, 5, 1, 4, 1204, 0, 0, 1222, ARMImpOpBase + 0, 0|(1ULL<<MCID::Rematerializable), 0x3140c80ULL }, // Inst #1113 = MVE_VCTP64 |
| 9279 | { 1112, 5, 1, 4, 1204, 0, 0, 1222, ARMImpOpBase + 0, 0|(1ULL<<MCID::Rematerializable), 0x2140c80ULL }, // Inst #1112 = MVE_VCTP32 |
| 9280 | { 1111, 5, 1, 4, 1204, 0, 0, 1222, ARMImpOpBase + 0, 0|(1ULL<<MCID::Rematerializable), 0x1140c80ULL }, // Inst #1111 = MVE_VCTP16 |
| 9281 | { 1110, 8, 1, 4, 1179, 0, 0, 1184, ARMImpOpBase + 0, 0, 0x2040c80ULL }, // Inst #1110 = MVE_VCMULf32 |
| 9282 | { 1109, 8, 1, 4, 1179, 0, 0, 1176, ARMImpOpBase + 0, 0, 0x1040c80ULL }, // Inst #1109 = MVE_VCMULf16 |
| 9283 | { 1108, 7, 1, 4, 1324, 0, 0, 1215, ARMImpOpBase + 0, 0, 0x140c80ULL }, // Inst #1108 = MVE_VCMPu8r |
| 9284 | { 1107, 7, 1, 4, 1180, 0, 0, 1208, ARMImpOpBase + 0, 0, 0x140c80ULL }, // Inst #1107 = MVE_VCMPu8 |
| 9285 | { 1106, 7, 1, 4, 1324, 0, 0, 1215, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1106 = MVE_VCMPu32r |
| 9286 | { 1105, 7, 1, 4, 1180, 0, 0, 1208, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1105 = MVE_VCMPu32 |
| 9287 | { 1104, 7, 1, 4, 1324, 0, 0, 1215, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1104 = MVE_VCMPu16r |
| 9288 | { 1103, 7, 1, 4, 1180, 0, 0, 1208, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1103 = MVE_VCMPu16 |
| 9289 | { 1102, 7, 1, 4, 1324, 0, 0, 1215, ARMImpOpBase + 0, 0, 0x140c80ULL }, // Inst #1102 = MVE_VCMPs8r |
| 9290 | { 1101, 7, 1, 4, 1180, 0, 0, 1208, ARMImpOpBase + 0, 0, 0x140c80ULL }, // Inst #1101 = MVE_VCMPs8 |
| 9291 | { 1100, 7, 1, 4, 1324, 0, 0, 1215, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1100 = MVE_VCMPs32r |
| 9292 | { 1099, 7, 1, 4, 1180, 0, 0, 1208, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1099 = MVE_VCMPs32 |
| 9293 | { 1098, 7, 1, 4, 1324, 0, 0, 1215, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1098 = MVE_VCMPs16r |
| 9294 | { 1097, 7, 1, 4, 1180, 0, 0, 1208, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1097 = MVE_VCMPs16 |
| 9295 | { 1096, 7, 1, 4, 1324, 0, 0, 1215, ARMImpOpBase + 0, 0, 0x140c80ULL }, // Inst #1096 = MVE_VCMPi8r |
| 9296 | { 1095, 7, 1, 4, 1180, 0, 0, 1208, ARMImpOpBase + 0, 0, 0x140c80ULL }, // Inst #1095 = MVE_VCMPi8 |
| 9297 | { 1094, 7, 1, 4, 1324, 0, 0, 1215, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1094 = MVE_VCMPi32r |
| 9298 | { 1093, 7, 1, 4, 1180, 0, 0, 1208, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1093 = MVE_VCMPi32 |
| 9299 | { 1092, 7, 1, 4, 1324, 0, 0, 1215, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1092 = MVE_VCMPi16r |
| 9300 | { 1091, 7, 1, 4, 1180, 0, 0, 1208, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1091 = MVE_VCMPi16 |
| 9301 | { 1090, 7, 1, 4, 1325, 0, 0, 1215, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1090 = MVE_VCMPf32r |
| 9302 | { 1089, 7, 1, 4, 1181, 0, 0, 1208, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1089 = MVE_VCMPf32 |
| 9303 | { 1088, 7, 1, 4, 1325, 0, 0, 1215, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1088 = MVE_VCMPf16r |
| 9304 | { 1087, 7, 1, 4, 1181, 0, 0, 1208, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1087 = MVE_VCMPf16 |
| 9305 | { 1086, 8, 1, 4, 1178, 0, 0, 1200, ARMImpOpBase + 0, 0, 0x2040c80ULL }, // Inst #1086 = MVE_VCMLAf32 |
| 9306 | { 1085, 8, 1, 4, 1178, 0, 0, 1192, ARMImpOpBase + 0, 0, 0x1040c80ULL }, // Inst #1085 = MVE_VCMLAf16 |
| 9307 | { 1084, 6, 1, 4, 1135, 0, 0, 1115, ARMImpOpBase + 0, 0, 0x140c80ULL }, // Inst #1084 = MVE_VCLZs8 |
| 9308 | { 1083, 6, 1, 4, 1135, 0, 0, 1115, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1083 = MVE_VCLZs32 |
| 9309 | { 1082, 6, 1, 4, 1135, 0, 0, 1115, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1082 = MVE_VCLZs16 |
| 9310 | { 1081, 6, 1, 4, 1134, 0, 0, 1115, ARMImpOpBase + 0, 0, 0x140c80ULL }, // Inst #1081 = MVE_VCLSs8 |
| 9311 | { 1080, 6, 1, 4, 1134, 0, 0, 1115, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1080 = MVE_VCLSs32 |
| 9312 | { 1079, 6, 1, 4, 1134, 0, 0, 1115, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1079 = MVE_VCLSs16 |
| 9313 | { 1078, 8, 1, 4, 1133, 0, 0, 1176, ARMImpOpBase + 0, 0, 0x40c80ULL }, // Inst #1078 = MVE_VCADDi8 |
| 9314 | { 1077, 8, 1, 4, 1133, 0, 0, 1184, ARMImpOpBase + 0, 0, 0x2040c80ULL }, // Inst #1077 = MVE_VCADDi32 |
| 9315 | { 1076, 8, 1, 4, 1133, 0, 0, 1176, ARMImpOpBase + 0, 0, 0x1040c80ULL }, // Inst #1076 = MVE_VCADDi16 |
| 9316 | { 1075, 8, 1, 4, 1177, 0, 0, 1184, ARMImpOpBase + 0, 0, 0x2040c80ULL }, // Inst #1075 = MVE_VCADDf32 |
| 9317 | { 1074, 8, 1, 4, 1177, 0, 0, 1176, ARMImpOpBase + 0, 0, 0x1040c80ULL }, // Inst #1074 = MVE_VCADDf16 |
| 9318 | { 1073, 7, 1, 4, 1132, 0, 0, 1163, ARMImpOpBase + 0, 0, 0x140c80ULL }, // Inst #1073 = MVE_VBRSR8 |
| 9319 | { 1072, 7, 1, 4, 1132, 0, 0, 1163, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1072 = MVE_VBRSR32 |
| 9320 | { 1071, 7, 1, 4, 1132, 0, 0, 1163, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1071 = MVE_VBRSR16 |
| 9321 | { 1070, 6, 1, 4, 1131, 0, 0, 1170, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1070 = MVE_VBICimmi32 |
| 9322 | { 1069, 6, 1, 4, 1131, 0, 0, 1170, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1069 = MVE_VBICimmi16 |
| 9323 | { 1068, 7, 1, 4, 1131, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x140c80ULL }, // Inst #1068 = MVE_VBIC |
| 9324 | { 1067, 7, 1, 4, 1130, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x140c80ULL }, // Inst #1067 = MVE_VAND |
| 9325 | { 1066, 7, 1, 4, 1129, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x140c80ULL }, // Inst #1066 = MVE_VADDi8 |
| 9326 | { 1065, 7, 1, 4, 1129, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1065 = MVE_VADDi32 |
| 9327 | { 1064, 7, 1, 4, 1129, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1064 = MVE_VADDi16 |
| 9328 | { 1063, 7, 1, 4, 1173, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1063 = MVE_VADDf32 |
| 9329 | { 1062, 7, 1, 4, 1173, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1062 = MVE_VADDf16 |
| 9330 | { 1061, 7, 1, 4, 1296, 0, 0, 1163, ARMImpOpBase + 0, 0, 0x140c80ULL }, // Inst #1061 = MVE_VADD_qr_i8 |
| 9331 | { 1060, 7, 1, 4, 1296, 0, 0, 1163, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1060 = MVE_VADD_qr_i32 |
| 9332 | { 1059, 7, 1, 4, 1296, 0, 0, 1163, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1059 = MVE_VADD_qr_i16 |
| 9333 | { 1058, 7, 1, 4, 1174, 0, 0, 1163, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1058 = MVE_VADD_qr_f32 |
| 9334 | { 1057, 7, 1, 4, 1174, 0, 0, 1163, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1057 = MVE_VADD_qr_f16 |
| 9335 | { 1056, 5, 1, 4, 1176, 0, 0, 1158, ARMImpOpBase + 0, 0, 0x540c80ULL }, // Inst #1056 = MVE_VADDVu8no_acc |
| 9336 | { 1055, 6, 1, 4, 1311, 0, 0, 1152, ARMImpOpBase + 0, 0, 0x540c80ULL }, // Inst #1055 = MVE_VADDVu8acc |
| 9337 | { 1054, 5, 1, 4, 1176, 0, 0, 1158, ARMImpOpBase + 0, 0, 0x2540c80ULL }, // Inst #1054 = MVE_VADDVu32no_acc |
| 9338 | { 1053, 6, 1, 4, 1311, 0, 0, 1152, ARMImpOpBase + 0, 0, 0x2540c80ULL }, // Inst #1053 = MVE_VADDVu32acc |
| 9339 | { 1052, 5, 1, 4, 1176, 0, 0, 1158, ARMImpOpBase + 0, 0, 0x1540c80ULL }, // Inst #1052 = MVE_VADDVu16no_acc |
| 9340 | { 1051, 6, 1, 4, 1311, 0, 0, 1152, ARMImpOpBase + 0, 0, 0x1540c80ULL }, // Inst #1051 = MVE_VADDVu16acc |
| 9341 | { 1050, 5, 1, 4, 1176, 0, 0, 1158, ARMImpOpBase + 0, 0, 0x540c80ULL }, // Inst #1050 = MVE_VADDVs8no_acc |
| 9342 | { 1049, 6, 1, 4, 1311, 0, 0, 1152, ARMImpOpBase + 0, 0, 0x540c80ULL }, // Inst #1049 = MVE_VADDVs8acc |
| 9343 | { 1048, 5, 1, 4, 1176, 0, 0, 1158, ARMImpOpBase + 0, 0, 0x2540c80ULL }, // Inst #1048 = MVE_VADDVs32no_acc |
| 9344 | { 1047, 6, 1, 4, 1311, 0, 0, 1152, ARMImpOpBase + 0, 0, 0x2540c80ULL }, // Inst #1047 = MVE_VADDVs32acc |
| 9345 | { 1046, 5, 1, 4, 1176, 0, 0, 1158, ARMImpOpBase + 0, 0, 0x1540c80ULL }, // Inst #1046 = MVE_VADDVs16no_acc |
| 9346 | { 1045, 6, 1, 4, 1311, 0, 0, 1152, ARMImpOpBase + 0, 0, 0x1540c80ULL }, // Inst #1045 = MVE_VADDVs16acc |
| 9347 | { 1044, 6, 2, 4, 1175, 0, 0, 1146, ARMImpOpBase + 0, 0, 0x2440c80ULL }, // Inst #1044 = MVE_VADDLVu32no_acc |
| 9348 | { 1043, 8, 2, 4, 1310, 0, 0, 1138, ARMImpOpBase + 0, 0, 0x2440c80ULL }, // Inst #1043 = MVE_VADDLVu32acc |
| 9349 | { 1042, 6, 2, 4, 1175, 0, 0, 1146, ARMImpOpBase + 0, 0, 0x2440c80ULL }, // Inst #1042 = MVE_VADDLVs32no_acc |
| 9350 | { 1041, 8, 2, 4, 1310, 0, 0, 1138, ARMImpOpBase + 0, 0, 0x2440c80ULL }, // Inst #1041 = MVE_VADDLVs32acc |
| 9351 | { 1040, 8, 2, 4, 1128, 0, 0, 1130, ARMImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x2040c80ULL }, // Inst #1040 = MVE_VADCI |
| 9352 | { 1039, 9, 2, 4, 1295, 0, 0, 1121, ARMImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x2040c80ULL }, // Inst #1039 = MVE_VADC |
| 9353 | { 1038, 6, 1, 4, 1127, 0, 0, 1115, ARMImpOpBase + 0, 0, 0x140c80ULL }, // Inst #1038 = MVE_VABSs8 |
| 9354 | { 1037, 6, 1, 4, 1127, 0, 0, 1115, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1037 = MVE_VABSs32 |
| 9355 | { 1036, 6, 1, 4, 1127, 0, 0, 1115, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1036 = MVE_VABSs16 |
| 9356 | { 1035, 6, 1, 4, 1172, 0, 0, 1115, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1035 = MVE_VABSf32 |
| 9357 | { 1034, 6, 1, 4, 1172, 0, 0, 1115, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1034 = MVE_VABSf16 |
| 9358 | { 1033, 7, 1, 4, 1126, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x140c80ULL }, // Inst #1033 = MVE_VABDu8 |
| 9359 | { 1032, 7, 1, 4, 1126, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1032 = MVE_VABDu32 |
| 9360 | { 1031, 7, 1, 4, 1126, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1031 = MVE_VABDu16 |
| 9361 | { 1030, 7, 1, 4, 1126, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x140c80ULL }, // Inst #1030 = MVE_VABDs8 |
| 9362 | { 1029, 7, 1, 4, 1126, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1029 = MVE_VABDs32 |
| 9363 | { 1028, 7, 1, 4, 1126, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1028 = MVE_VABDs16 |
| 9364 | { 1027, 7, 1, 4, 1171, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x2140c80ULL }, // Inst #1027 = MVE_VABDf32 |
| 9365 | { 1026, 7, 1, 4, 1171, 0, 0, 1108, ARMImpOpBase + 0, 0, 0x1140c80ULL }, // Inst #1026 = MVE_VABDf16 |
| 9366 | { 1025, 7, 1, 4, 1125, 0, 0, 1101, ARMImpOpBase + 0, 0, 0x440c80ULL }, // Inst #1025 = MVE_VABAVu8 |
| 9367 | { 1024, 7, 1, 4, 1125, 0, 0, 1101, ARMImpOpBase + 0, 0, 0x2440c80ULL }, // Inst #1024 = MVE_VABAVu32 |
| 9368 | { 1023, 7, 1, 4, 1125, 0, 0, 1101, ARMImpOpBase + 0, 0, 0x1440c80ULL }, // Inst #1023 = MVE_VABAVu16 |
| 9369 | { 1022, 7, 1, 4, 1125, 0, 0, 1101, ARMImpOpBase + 0, 0, 0x440c80ULL }, // Inst #1022 = MVE_VABAVs8 |
| 9370 | { 1021, 7, 1, 4, 1125, 0, 0, 1101, ARMImpOpBase + 0, 0, 0x2440c80ULL }, // Inst #1021 = MVE_VABAVs32 |
| 9371 | { 1020, 7, 1, 4, 1125, 0, 0, 1101, ARMImpOpBase + 0, 0, 0x1440c80ULL }, // Inst #1020 = MVE_VABAVs16 |
| 9372 | { 1019, 7, 2, 4, 1282, 0, 0, 1074, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x140c80ULL }, // Inst #1019 = MVE_URSHRL |
| 9373 | { 1018, 5, 1, 4, 1102, 0, 0, 464, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x140c80ULL }, // Inst #1018 = MVE_URSHR |
| 9374 | { 1017, 7, 2, 4, 1282, 0, 0, 1074, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x140c80ULL }, // Inst #1017 = MVE_UQSHLL |
| 9375 | { 1016, 5, 1, 4, 1102, 0, 0, 464, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x140c80ULL }, // Inst #1016 = MVE_UQSHL |
| 9376 | { 1015, 8, 2, 4, 1103, 0, 0, 1093, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x140c80ULL }, // Inst #1015 = MVE_UQRSHLL |
| 9377 | { 1014, 5, 1, 4, 1283, 0, 0, 1088, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x140c80ULL }, // Inst #1014 = MVE_UQRSHL |
| 9378 | { 1013, 7, 2, 4, 1282, 0, 0, 1074, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x140c80ULL }, // Inst #1013 = MVE_SRSHRL |
| 9379 | { 1012, 5, 1, 4, 1102, 0, 0, 464, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x140c80ULL }, // Inst #1012 = MVE_SRSHR |
| 9380 | { 1011, 7, 2, 4, 1282, 0, 0, 1074, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x140c80ULL }, // Inst #1011 = MVE_SQSHLL |
| 9381 | { 1010, 5, 1, 4, 1102, 0, 0, 464, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x140c80ULL }, // Inst #1010 = MVE_SQSHL |
| 9382 | { 1009, 8, 2, 4, 1103, 0, 0, 1093, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x140c80ULL }, // Inst #1009 = MVE_SQRSHRL |
| 9383 | { 1008, 5, 1, 4, 1283, 0, 0, 1088, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x140c80ULL }, // Inst #1008 = MVE_SQRSHR |
| 9384 | { 1007, 7, 2, 4, 1282, 0, 0, 1074, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x140c80ULL }, // Inst #1007 = MVE_LSRL |
| 9385 | { 1006, 7, 2, 4, 1103, 0, 0, 1081, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x140c80ULL }, // Inst #1006 = MVE_LSLLr |
| 9386 | { 1005, 7, 2, 4, 1282, 0, 0, 1074, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x140c80ULL }, // Inst #1005 = MVE_LSLLi |
| 9387 | { 1004, 3, 1, 4, 1288, 0, 0, 455, ARMImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #1004 = MVE_LETP |
| 9388 | { 1003, 2, 0, 4, 1285, 0, 0, 540, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #1003 = MVE_LCTP |
| 9389 | { 1002, 2, 1, 4, 1286, 0, 0, 434, ARMImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #1002 = MVE_DLSTP_8 |
| 9390 | { 1001, 2, 1, 4, 1286, 0, 0, 434, ARMImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #1001 = MVE_DLSTP_64 |
| 9391 | { 1000, 2, 1, 4, 1286, 0, 0, 434, ARMImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #1000 = MVE_DLSTP_32 |
| 9392 | { 999, 2, 1, 4, 1286, 0, 0, 434, ARMImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #999 = MVE_DLSTP_16 |
| 9393 | { 998, 7, 2, 4, 1103, 0, 0, 1081, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x140c80ULL }, // Inst #998 = MVE_ASRLr |
| 9394 | { 997, 7, 2, 4, 1282, 0, 0, 1074, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x140c80ULL }, // Inst #997 = MVE_ASRLi |
| 9395 | { 996, 6, 1, 4, 335, 0, 0, 187, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0x80ULL }, // Inst #996 = MUL |
| 9396 | { 995, 4, 0, 4, 728, 0, 1, 1070, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // Inst #995 = MSRi |
| 9397 | { 994, 4, 0, 4, 728, 0, 0, 1066, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // Inst #994 = MSRbanked |
| 9398 | { 993, 4, 0, 4, 728, 0, 1, 1062, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // Inst #993 = MSR |
| 9399 | { 992, 3, 1, 4, 727, 0, 0, 1059, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // Inst #992 = MRSsys |
| 9400 | { 991, 4, 1, 4, 727, 0, 0, 439, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // Inst #991 = MRSbanked |
| 9401 | { 990, 3, 1, 4, 727, 0, 0, 1059, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // Inst #990 = MRS |
| 9402 | { 989, 5, 2, 4, 849, 0, 0, 1054, ARMImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // Inst #989 = MRRC2 |
| 9403 | { 988, 7, 2, 4, 849, 0, 0, 1047, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // Inst #988 = MRRC |
| 9404 | { 987, 6, 1, 4, 849, 0, 0, 1041, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // Inst #987 = MRC2 |
| 9405 | { 986, 8, 1, 4, 849, 0, 0, 1033, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // Inst #986 = MRC |
| 9406 | { 985, 7, 1, 4, 689, 0, 0, 1026, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x2281ULL }, // Inst #985 = MOVsr |
| 9407 | { 984, 6, 1, 4, 325, 0, 0, 1020, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x3501ULL }, // Inst #984 = MOVsi |
| 9408 | { 983, 5, 1, 4, 867, 0, 0, 1015, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x2201ULL }, // Inst #983 = MOVr_TC |
| 9409 | { 982, 5, 1, 4, 867, 0, 0, 326, ARMImpOpBase + 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x2201ULL }, // Inst #982 = MOVr |
| 9410 | { 981, 4, 1, 4, 866, 0, 0, 243, ARMImpOpBase + 0, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x2201ULL }, // Inst #981 = MOVi16 |
| 9411 | { 980, 5, 1, 4, 866, 0, 0, 1010, ARMImpOpBase + 0, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::CheapAsAMove), 0x2201ULL }, // Inst #980 = MOVi |
| 9412 | { 979, 5, 1, 4, 691, 0, 0, 1005, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x2201ULL }, // Inst #979 = MOVTi16 |
| 9413 | { 978, 2, 0, 4, 882, 0, 0, 540, ARMImpOpBase + 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0x180ULL }, // Inst #978 = MOVPCLR |
| 9414 | { 977, 6, 1, 4, 336, 0, 0, 999, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x80ULL }, // Inst #977 = MLS |
| 9415 | { 976, 7, 1, 4, 336, 0, 0, 992, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80ULL }, // Inst #976 = MLA |
| 9416 | { 975, 5, 0, 4, 849, 0, 0, 987, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // Inst #975 = MCRR2 |
| 9417 | { 974, 7, 0, 4, 849, 0, 0, 980, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // Inst #974 = MCRR |
| 9418 | { 973, 6, 0, 4, 849, 0, 0, 974, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // Inst #973 = MCR2 |
| 9419 | { 972, 8, 0, 4, 849, 0, 0, 966, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // Inst #972 = MCR |
| 9420 | { 971, 6, 1, 4, 347, 0, 0, 960, ARMImpOpBase + 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0x300ULL }, // Inst #971 = LDRrs |
| 9421 | { 970, 5, 1, 4, 385, 0, 0, 321, ARMImpOpBase + 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0x312ULL }, // Inst #970 = LDRi12 |
| 9422 | { 969, 5, 1, 4, 397, 0, 0, 321, ARMImpOpBase + 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0x312ULL }, // Inst #969 = LDRcp |
| 9423 | { 968, 7, 2, 4, 912, 0, 0, 901, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x322ULL }, // Inst #968 = LDR_PRE_REG |
| 9424 | { 967, 6, 2, 4, 908, 0, 0, 908, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x322ULL }, // Inst #967 = LDR_PRE_IMM |
| 9425 | { 966, 7, 2, 4, 931, 0, 0, 901, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x342ULL }, // Inst #966 = LDR_POST_REG |
| 9426 | { 965, 7, 2, 4, 405, 0, 0, 901, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x342ULL }, // Inst #965 = LDR_POST_IMM |
| 9427 | { 964, 7, 2, 4, 404, 0, 0, 901, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x342ULL }, // Inst #964 = LDRT_POST_REG |
| 9428 | { 963, 7, 2, 4, 923, 0, 0, 901, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x342ULL }, // Inst #963 = LDRT_POST_IMM |
| 9429 | { 962, 7, 2, 4, 915, 0, 0, 953, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x423ULL }, // Inst #962 = LDRSH_PRE |
| 9430 | { 961, 7, 2, 4, 930, 0, 0, 953, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x443ULL }, // Inst #961 = LDRSH_POST |
| 9431 | { 960, 7, 2, 4, 350, 0, 0, 946, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x443ULL }, // Inst #960 = LDRSHTr |
| 9432 | { 959, 6, 2, 4, 926, 0, 0, 908, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x443ULL }, // Inst #959 = LDRSHTi |
| 9433 | { 958, 6, 1, 4, 348, 0, 0, 940, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x403ULL }, // Inst #958 = LDRSH |
| 9434 | { 957, 7, 2, 4, 915, 0, 0, 953, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x423ULL }, // Inst #957 = LDRSB_PRE |
| 9435 | { 956, 7, 2, 4, 930, 0, 0, 953, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x443ULL }, // Inst #956 = LDRSB_POST |
| 9436 | { 955, 7, 2, 4, 350, 0, 0, 946, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x443ULL }, // Inst #955 = LDRSBTr |
| 9437 | { 954, 6, 2, 4, 926, 0, 0, 908, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x443ULL }, // Inst #954 = LDRSBTi |
| 9438 | { 953, 6, 1, 4, 348, 0, 0, 940, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x403ULL }, // Inst #953 = LDRSB |
| 9439 | { 952, 7, 2, 4, 914, 0, 0, 953, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x423ULL }, // Inst #952 = LDRH_PRE |
| 9440 | { 951, 7, 2, 4, 929, 0, 0, 953, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x443ULL }, // Inst #951 = LDRH_POST |
| 9441 | { 950, 7, 2, 4, 406, 0, 0, 946, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x443ULL }, // Inst #950 = LDRHTr |
| 9442 | { 949, 6, 2, 4, 925, 0, 0, 908, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x443ULL }, // Inst #949 = LDRHTi |
| 9443 | { 948, 6, 1, 4, 396, 0, 0, 940, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x403ULL }, // Inst #948 = LDRH |
| 9444 | { 947, 4, 1, 4, 848, 0, 0, 239, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x580ULL }, // Inst #947 = LDREXH |
| 9445 | { 946, 4, 1, 4, 848, 0, 0, 877, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x580ULL }, // Inst #946 = LDREXD |
| 9446 | { 945, 4, 1, 4, 848, 0, 0, 239, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x580ULL }, // Inst #945 = LDREXB |
| 9447 | { 944, 4, 1, 4, 848, 0, 0, 239, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x580ULL }, // Inst #944 = LDREX |
| 9448 | { 943, 8, 3, 4, 921, 0, 0, 932, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x423ULL }, // Inst #943 = LDRD_PRE |
| 9449 | { 942, 8, 3, 4, 418, 0, 0, 932, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x443ULL }, // Inst #942 = LDRD_POST |
| 9450 | { 941, 7, 2, 4, 417, 0, 0, 925, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x403ULL }, // Inst #941 = LDRD |
| 9451 | { 940, 6, 1, 4, 387, 0, 0, 919, ARMImpOpBase + 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0x300ULL }, // Inst #940 = LDRBrs |
| 9452 | { 939, 5, 1, 4, 386, 0, 0, 914, ARMImpOpBase + 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0x312ULL }, // Inst #939 = LDRBi12 |
| 9453 | { 938, 7, 2, 4, 913, 0, 0, 901, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x322ULL }, // Inst #938 = LDRB_PRE_REG |
| 9454 | { 937, 6, 2, 4, 909, 0, 0, 908, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x322ULL }, // Inst #937 = LDRB_PRE_IMM |
| 9455 | { 936, 7, 2, 4, 932, 0, 0, 901, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x342ULL }, // Inst #936 = LDRB_POST_REG |
| 9456 | { 935, 7, 2, 4, 403, 0, 0, 901, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x342ULL }, // Inst #935 = LDRB_POST_IMM |
| 9457 | { 934, 7, 2, 4, 402, 0, 0, 901, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x342ULL }, // Inst #934 = LDRBT_POST_REG |
| 9458 | { 933, 7, 2, 4, 924, 0, 0, 901, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x342ULL }, // Inst #933 = LDRBT_POST_IMM |
| 9459 | { 932, 5, 1, 4, 421, 0, 0, 234, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x564ULL }, // Inst #932 = LDMIB_UPD |
| 9460 | { 931, 4, 0, 4, 420, 0, 0, 873, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x504ULL }, // Inst #931 = LDMIB |
| 9461 | { 930, 5, 1, 4, 421, 0, 0, 234, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x564ULL }, // Inst #930 = LDMIA_UPD |
| 9462 | { 929, 4, 0, 4, 420, 0, 0, 873, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x504ULL }, // Inst #929 = LDMIA |
| 9463 | { 928, 5, 1, 4, 421, 0, 0, 234, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x564ULL }, // Inst #928 = LDMDB_UPD |
| 9464 | { 927, 4, 0, 4, 420, 0, 0, 873, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x504ULL }, // Inst #927 = LDMDB |
| 9465 | { 926, 5, 1, 4, 421, 0, 0, 234, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x564ULL }, // Inst #926 = LDMDA_UPD |
| 9466 | { 925, 4, 0, 4, 420, 0, 0, 873, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x504ULL }, // Inst #925 = LDMDA |
| 9467 | { 924, 6, 0, 4, 846, 0, 0, 889, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x120ULL }, // Inst #924 = LDC_PRE |
| 9468 | { 923, 6, 0, 4, 846, 0, 0, 889, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x140ULL }, // Inst #923 = LDC_POST |
| 9469 | { 922, 6, 0, 4, 846, 0, 0, 895, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // Inst #922 = LDC_OPTION |
| 9470 | { 921, 6, 0, 4, 846, 0, 0, 889, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x105ULL }, // Inst #921 = LDC_OFFSET |
| 9471 | { 920, 6, 0, 4, 846, 0, 0, 889, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x120ULL }, // Inst #920 = LDCL_PRE |
| 9472 | { 919, 6, 0, 4, 846, 0, 0, 889, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x140ULL }, // Inst #919 = LDCL_POST |
| 9473 | { 918, 6, 0, 4, 846, 0, 0, 895, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // Inst #918 = LDCL_OPTION |
| 9474 | { 917, 6, 0, 4, 846, 0, 0, 889, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x105ULL }, // Inst #917 = LDCL_OFFSET |
| 9475 | { 916, 4, 0, 4, 846, 0, 0, 881, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x120ULL }, // Inst #916 = LDC2_PRE |
| 9476 | { 915, 4, 0, 4, 846, 0, 0, 881, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x140ULL }, // Inst #915 = LDC2_POST |
| 9477 | { 914, 4, 0, 4, 846, 0, 0, 885, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // Inst #914 = LDC2_OPTION |
| 9478 | { 913, 4, 0, 4, 846, 0, 0, 881, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x105ULL }, // Inst #913 = LDC2_OFFSET |
| 9479 | { 912, 4, 0, 4, 846, 0, 0, 881, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x120ULL }, // Inst #912 = LDC2L_PRE |
| 9480 | { 911, 4, 0, 4, 846, 0, 0, 881, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x140ULL }, // Inst #911 = LDC2L_POST |
| 9481 | { 910, 4, 0, 4, 846, 0, 0, 885, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // Inst #910 = LDC2L_OPTION |
| 9482 | { 909, 4, 0, 4, 846, 0, 0, 881, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x105ULL }, // Inst #909 = LDC2L_OFFSET |
| 9483 | { 908, 4, 1, 4, 687, 0, 0, 239, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x580ULL }, // Inst #908 = LDAH |
| 9484 | { 907, 4, 1, 4, 687, 0, 0, 239, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x580ULL }, // Inst #907 = LDAEXH |
| 9485 | { 906, 4, 1, 4, 687, 0, 0, 877, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x580ULL }, // Inst #906 = LDAEXD |
| 9486 | { 905, 4, 1, 4, 687, 0, 0, 239, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x580ULL }, // Inst #905 = LDAEXB |
| 9487 | { 904, 4, 1, 4, 687, 0, 0, 239, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x580ULL }, // Inst #904 = LDAEX |
| 9488 | { 903, 4, 1, 4, 687, 0, 0, 239, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x580ULL }, // Inst #903 = LDAB |
| 9489 | { 902, 4, 1, 4, 687, 0, 0, 239, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x580ULL }, // Inst #902 = LDA |
| 9490 | { 901, 1, 0, 4, 843, 0, 0, 0, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0xd00ULL }, // Inst #901 = ISB |
| 9491 | { 900, 1, 0, 4, 843, 0, 0, 0, ARMImpOpBase + 0, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // Inst #900 = HVC |
| 9492 | { 899, 1, 0, 4, 843, 0, 0, 0, ARMImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xd00ULL }, // Inst #899 = HLT |
| 9493 | { 898, 3, 0, 4, 843, 0, 0, 858, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xd00ULL }, // Inst #898 = HINT |
| 9494 | { 897, 5, 1, 4, 850, 0, 0, 234, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b64ULL }, // Inst #897 = FSTMXIA_UPD |
| 9495 | { 896, 4, 0, 4, 850, 0, 0, 873, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b04ULL }, // Inst #896 = FSTMXIA |
| 9496 | { 895, 5, 1, 4, 850, 0, 0, 234, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b64ULL }, // Inst #895 = FSTMXDB_UPD |
| 9497 | { 894, 2, 0, 4, 587, 1, 1, 540, ARMImpOpBase + 67, 0|(1ULL<<MCID::Predicable), 0x8c00ULL }, // Inst #894 = FMSTAT |
| 9498 | { 893, 5, 1, 4, 850, 0, 0, 234, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b64ULL }, // Inst #893 = FLDMXIA_UPD |
| 9499 | { 892, 4, 0, 4, 850, 0, 0, 873, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b04ULL }, // Inst #892 = FLDMXIA |
| 9500 | { 891, 5, 1, 4, 850, 0, 0, 234, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b64ULL }, // Inst #891 = FLDMXDB_UPD |
| 9501 | { 890, 4, 1, 4, 966, 0, 0, 869, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0x8c00ULL }, // Inst #890 = FCONSTS |
| 9502 | { 889, 4, 1, 4, 965, 0, 0, 865, ARMImpOpBase + 0, 0|(1ULL<<MCID::Rematerializable), 0x8c00ULL }, // Inst #889 = FCONSTH |
| 9503 | { 888, 4, 1, 4, 964, 0, 0, 861, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0x8c00ULL }, // Inst #888 = FCONSTD |
| 9504 | { 887, 2, 0, 4, 1218, 0, 1, 540, ARMImpOpBase + 66, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // Inst #887 = ERET |
| 9505 | { 886, 8, 1, 4, 324, 0, 0, 614, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x281ULL }, // Inst #886 = EORrsr |
| 9506 | { 885, 7, 1, 4, 323, 0, 0, 599, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x1501ULL }, // Inst #885 = EORrsi |
| 9507 | { 884, 6, 1, 4, 322, 0, 0, 593, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0x201ULL }, // Inst #884 = EORrr |
| 9508 | { 883, 6, 1, 4, 321, 0, 0, 181, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef), 0x201ULL }, // Inst #883 = EORri |
| 9509 | { 882, 1, 0, 4, 843, 0, 0, 0, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0xd00ULL }, // Inst #882 = DSB |
| 9510 | { 881, 1, 0, 4, 843, 0, 0, 0, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0xd00ULL }, // Inst #881 = DMB |
| 9511 | { 880, 3, 0, 4, 843, 0, 0, 858, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xd00ULL }, // Inst #880 = DBG |
| 9512 | { 879, 3, 1, 4, 700, 0, 0, 855, ARMImpOpBase + 0, 0, 0xd00ULL }, // Inst #879 = CRC32W |
| 9513 | { 878, 3, 1, 4, 700, 0, 0, 855, ARMImpOpBase + 0, 0, 0xd00ULL }, // Inst #878 = CRC32H |
| 9514 | { 877, 3, 1, 4, 700, 0, 0, 855, ARMImpOpBase + 0, 0, 0xd00ULL }, // Inst #877 = CRC32CW |
| 9515 | { 876, 3, 1, 4, 700, 0, 0, 855, ARMImpOpBase + 0, 0, 0xd00ULL }, // Inst #876 = CRC32CH |
| 9516 | { 875, 3, 1, 4, 700, 0, 0, 855, ARMImpOpBase + 0, 0, 0xd00ULL }, // Inst #875 = CRC32CB |
| 9517 | { 874, 3, 1, 4, 700, 0, 0, 855, ARMImpOpBase + 0, 0, 0xd00ULL }, // Inst #874 = CRC32B |
| 9518 | { 873, 3, 0, 4, 843, 0, 0, 852, ARMImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xd00ULL }, // Inst #873 = CPS3p |
| 9519 | { 872, 2, 0, 4, 843, 0, 0, 13, ARMImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xd00ULL }, // Inst #872 = CPS2p |
| 9520 | { 871, 1, 0, 4, 843, 0, 0, 0, ARMImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xd00ULL }, // Inst #871 = CPS1p |
| 9521 | { 870, 6, 0, 4, 719, 0, 1, 846, ARMImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0x281ULL }, // Inst #870 = CMPrsr |
| 9522 | { 869, 5, 0, 4, 718, 0, 1, 841, ARMImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0x1501ULL }, // Inst #869 = CMPrsi |
| 9523 | { 868, 4, 0, 4, 717, 0, 1, 837, ARMImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0x201ULL }, // Inst #868 = CMPrr |
| 9524 | { 867, 4, 0, 4, 716, 0, 1, 243, ARMImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0x201ULL }, // Inst #867 = CMPri |
| 9525 | { 866, 6, 0, 4, 719, 0, 1, 846, ARMImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0x281ULL }, // Inst #866 = CMNzrsr |
| 9526 | { 865, 5, 0, 4, 718, 0, 1, 841, ARMImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0x1501ULL }, // Inst #865 = CMNzrsi |
| 9527 | { 864, 4, 0, 4, 717, 0, 1, 837, ARMImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x201ULL }, // Inst #864 = CMNzrr |
| 9528 | { 863, 4, 0, 4, 716, 0, 1, 243, ARMImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0x201ULL }, // Inst #863 = CMNri |
| 9529 | { 862, 4, 1, 4, 693, 0, 0, 837, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x600ULL }, // Inst #862 = CLZ |
| 9530 | { 861, 0, 0, 4, 843, 0, 0, 1, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0xd00ULL }, // Inst #861 = CLREX |
| 9531 | { 860, 6, 0, 4, 843, 0, 0, 831, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // Inst #860 = CDP2 |
| 9532 | { 859, 8, 0, 4, 843, 0, 0, 823, ARMImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // Inst #859 = CDP |
| 9533 | { 858, 9, 1, 4, 0, 0, 0, 814, ARMImpOpBase + 0, 0, 0xc80ULL }, // Inst #858 = CDE_VCX3_vec |
| 9534 | { 857, 5, 1, 4, 0, 0, 0, 809, ARMImpOpBase + 0, 0, 0xc80ULL }, // Inst #857 = CDE_VCX3_fpsp |
| 9535 | { 856, 5, 1, 4, 0, 0, 0, 804, ARMImpOpBase + 0, 0, 0xc80ULL }, // Inst #856 = CDE_VCX3_fpdp |
| 9536 | { 855, 9, 1, 4, 0, 0, 0, 795, ARMImpOpBase + 0, 0, 0xc80ULL }, // Inst #855 = CDE_VCX3A_vec |
| 9537 | { 854, 6, 1, 4, 0, 0, 0, 789, ARMImpOpBase + 0, 0, 0xc80ULL }, // Inst #854 = CDE_VCX3A_fpsp |
| 9538 | { 853, 6, 1, 4, 0, 0, 0, 783, ARMImpOpBase + 0, 0, 0xc80ULL }, // Inst #853 = CDE_VCX3A_fpdp |
| 9539 | { 852, 8, 1, 4, 0, 0, 0, 775, ARMImpOpBase + 0, 0, 0xc80ULL }, // Inst #852 = CDE_VCX2_vec |
| 9540 | { 851, 4, 1, 4, 0, 0, 0, 771, ARMImpOpBase + 0, 0, 0xc80ULL }, // Inst #851 = CDE_VCX2_fpsp |
| 9541 | { 850, 4, 1, 4, 0, 0, 0, 767, ARMImpOpBase + 0, 0, 0xc80ULL }, // Inst #850 = CDE_VCX2_fpdp |
| 9542 | { 849, 8, 1, 4, 0, 0, 0, 759, ARMImpOpBase + 0, 0, 0xc80ULL }, // Inst #849 = CDE_VCX2A_vec |
| 9543 | { 848, 5, 1, 4, 0, 0, 0, 754, ARMImpOpBase + 0, 0, 0xc80ULL }, // Inst #848 = CDE_VCX2A_fpsp |
| 9544 | { 847, 5, 1, 4, 0, 0, 0, 749, ARMImpOpBase + 0, 0, 0xc80ULL }, // Inst #847 = CDE_VCX2A_fpdp |
| 9545 | { 846, 7, 1, 4, 0, 0, 0, 742, ARMImpOpBase + 0, 0, 0xc80ULL }, // Inst #846 = CDE_VCX1_vec |
| 9546 | { 845, 3, 1, 4, 0, 0, 0, 739, ARMImpOpBase + 0, 0, 0xc80ULL }, // Inst #845 = CDE_VCX1_fpsp |
| 9547 | { 844, 3, 1, 4, 0, 0, 0, 736, ARMImpOpBase + 0, 0, 0xc80ULL }, // Inst #844 = CDE_VCX1_fpdp |
| 9548 | { 843, 7, 1, 4, 0, 0, 0, 729, ARMImpOpBase + 0, 0, 0xc80ULL }, // Inst #843 = CDE_VCX1A_vec |
| 9549 | { 842, 4, 1, 4, 0, 0, 0, 725, ARMImpOpBase + 0, 0, 0xc80ULL }, // Inst #842 = CDE_VCX1A_fpsp |
| 9550 | { 841, 4, 1, 4, 0, 0, 0, 721, ARMImpOpBase + 0, 0, 0xc80ULL }, // Inst #841 = CDE_VCX1A_fpdp |
| 9551 | { 840, 8, 1, 4, 0, 0, 0, 713, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #840 = CDE_CX3DA |
| 9552 | { 839, 5, 1, 4, 0, 0, 0, 708, ARMImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #839 = CDE_CX3D |
| 9553 | { 838, 8, 1, 4, 0, 0, 0, 700, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #838 = CDE_CX3A |
| 9554 | { 837, 5, 1, 4, 0, 0, 0, 695, ARMImpOpBase + 0, 0, 0xc80ULL }, // Inst #837 = CDE_CX3 |
| 9555 | { 836, 7, 1, 4, 0, 0, 0, 688, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #836 = CDE_CX2DA |
| 9556 | { 835, 4, 1, 4, 0, 0, 0, 684, ARMImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #835 = CDE_CX2D |
| 9557 | { 834, 7, 1, 4, 0, 0, 0, 677, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #834 = CDE_CX2A |
| 9558 | { 833, 4, 1, 4, 0, 0, 0, 673, ARMImpOpBase + 0, 0, 0xc80ULL }, // Inst #833 = CDE_CX2 |
| 9559 | { 832, 6, 1, 4, 0, 0, 0, 667, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #832 = CDE_CX1DA |
| 9560 | { 831, 3, 1, 4, 0, 0, 0, 664, ARMImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // Inst #831 = CDE_CX1D |
| 9561 | { 830, 6, 1, 4, 0, 0, 0, 658, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // Inst #830 = CDE_CX1A |
| 9562 | { 829, 3, 1, 4, 0, 0, 0, 655, ARMImpOpBase + 0, 0, 0xc80ULL }, // Inst #829 = CDE_CX1 |
| 9563 | { 828, 3, 0, 4, 853, 0, 0, 545, ARMImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // Inst #828 = Bcc |
| 9564 | { 827, 3, 0, 4, 853, 0, 0, 535, ARMImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x180ULL }, // Inst #827 = BX_pred |
| 9565 | { 826, 2, 0, 4, 853, 0, 0, 540, ARMImpOpBase + 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0x180ULL }, // Inst #826 = BX_RET |
| 9566 | { 825, 3, 0, 4, 854, 0, 0, 535, ARMImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // Inst #825 = BXJ |
| 9567 | { 824, 1, 0, 4, 853, 0, 0, 295, ARMImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x180ULL }, // Inst #824 = BX |
| 9568 | { 823, 3, 0, 4, 856, 1, 1, 545, ARMImpOpBase + 3, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable), 0x100ULL }, // Inst #823 = BL_pred |
| 9569 | { 822, 1, 0, 4, 857, 0, 0, 193, ARMImpOpBase + 0, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x180ULL }, // Inst #822 = BLXi |
| 9570 | { 821, 3, 0, 4, 859, 1, 1, 535, ARMImpOpBase + 3, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable), 0x180ULL }, // Inst #821 = BLX_pred |
| 9571 | { 820, 1, 0, 4, 859, 1, 1, 295, ARMImpOpBase + 3, 0|(1ULL<<MCID::Call), 0x180ULL }, // Inst #820 = BLX |
| 9572 | { 819, 1, 0, 4, 856, 1, 1, 193, ARMImpOpBase + 3, 0|(1ULL<<MCID::Call), 0x100ULL }, // Inst #819 = BL |
| 9573 | { 818, 1, 0, 4, 843, 0, 0, 0, ARMImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xd00ULL }, // Inst #818 = BKPT |
| 9574 | { 817, 8, 1, 4, 324, 0, 0, 614, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x281ULL }, // Inst #817 = BICrsr |
| 9575 | { 816, 7, 1, 4, 323, 0, 0, 599, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x1501ULL }, // Inst #816 = BICrsi |
| 9576 | { 815, 6, 1, 4, 322, 0, 0, 593, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x201ULL }, // Inst #815 = BICrr |
| 9577 | { 814, 6, 1, 4, 321, 0, 0, 181, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef), 0x201ULL }, // Inst #814 = BICri |
| 9578 | { 813, 6, 1, 4, 334, 0, 0, 649, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x201ULL }, // Inst #813 = BFI |
| 9579 | { 812, 5, 1, 4, 334, 0, 0, 267, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x201ULL }, // Inst #812 = BFC |
| 9580 | { 811, 5, 1, 4, 0, 0, 0, 408, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x8780ULL }, // Inst #811 = BF16_VCVTT |
| 9581 | { 810, 5, 1, 4, 0, 0, 0, 408, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x8780ULL }, // Inst #810 = BF16_VCVTB |
| 9582 | { 809, 4, 1, 4, 0, 0, 0, 645, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11000ULL }, // Inst #809 = BF16_VCVT |
| 9583 | { 808, 4, 1, 4, 50, 0, 0, 641, ARMImpOpBase + 0, 0, 0x11280ULL }, // Inst #808 = BF16VDOTS_VDOTQ |
| 9584 | { 807, 4, 1, 4, 50, 0, 0, 637, ARMImpOpBase + 0, 0, 0x11280ULL }, // Inst #807 = BF16VDOTS_VDOTD |
| 9585 | { 806, 5, 1, 4, 50, 0, 0, 632, ARMImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x11280ULL }, // Inst #806 = BF16VDOTI_VDOTQ |
| 9586 | { 805, 5, 1, 4, 50, 0, 0, 627, ARMImpOpBase + 0, 0, 0x11280ULL }, // Inst #805 = BF16VDOTI_VDOTD |
| 9587 | { 804, 8, 1, 4, 324, 0, 0, 614, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x281ULL }, // Inst #804 = ANDrsr |
| 9588 | { 803, 7, 1, 4, 323, 0, 0, 599, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x1501ULL }, // Inst #803 = ANDrsi |
| 9589 | { 802, 6, 1, 4, 322, 0, 0, 593, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0x201ULL }, // Inst #802 = ANDrr |
| 9590 | { 801, 6, 1, 4, 321, 0, 0, 181, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef), 0x201ULL }, // Inst #801 = ANDri |
| 9591 | { 800, 2, 1, 4, 1010, 0, 0, 625, ARMImpOpBase + 0, 0, 0x11000ULL }, // Inst #800 = AESMC |
| 9592 | { 799, 2, 1, 4, 1010, 0, 0, 625, ARMImpOpBase + 0, 0, 0x11000ULL }, // Inst #799 = AESIMC |
| 9593 | { 798, 3, 1, 4, 1010, 0, 0, 622, ARMImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x11000ULL }, // Inst #798 = AESE |
| 9594 | { 797, 3, 1, 4, 1010, 0, 0, 622, ARMImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x11000ULL }, // Inst #797 = AESD |
| 9595 | { 796, 4, 1, 4, 709, 0, 0, 243, ARMImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xd01ULL }, // Inst #796 = ADR |
| 9596 | { 795, 8, 1, 4, 708, 0, 0, 614, ARMImpOpBase + 0, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x281ULL }, // Inst #795 = ADDrsr |
| 9597 | { 794, 7, 1, 4, 702, 0, 0, 599, ARMImpOpBase + 0, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x1501ULL }, // Inst #794 = ADDrsi |
| 9598 | { 793, 6, 1, 4, 699, 0, 0, 593, ARMImpOpBase + 0, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0x201ULL }, // Inst #793 = ADDrr |
| 9599 | { 792, 6, 1, 4, 692, 0, 0, 181, ARMImpOpBase + 0, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef), 0x201ULL }, // Inst #792 = ADDri |
| 9600 | { 791, 8, 1, 4, 708, 1, 1, 606, ARMImpOpBase + 63, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0x281ULL }, // Inst #791 = ADCrsr |
| 9601 | { 790, 7, 1, 4, 702, 1, 1, 599, ARMImpOpBase + 63, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0x1501ULL }, // Inst #790 = ADCrsi |
| 9602 | { 789, 6, 1, 4, 699, 1, 1, 593, ARMImpOpBase + 63, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0x201ULL }, // Inst #789 = ADCrr |
| 9603 | { 788, 6, 1, 4, 692, 1, 1, 181, ARMImpOpBase + 63, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0x201ULL }, // Inst #788 = ADCri |
| 9604 | { 787, 0, 0, 4, 858, 1, 4, 1, ARMImpOpBase + 55, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call), 0x0ULL }, // Inst #787 = tTPsoft |
| 9605 | { 786, 4, 0, 2, 6, 0, 0, 589, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #786 = tTBH_JT |
| 9606 | { 785, 4, 0, 2, 6, 0, 0, 589, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #785 = tTBB_JT |
| 9607 | { 784, 1, 0, 4, 853, 1, 0, 367, ARMImpOpBase + 54, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #784 = tTAILJMPr |
| 9608 | { 783, 3, 0, 4, 853, 1, 0, 545, ARMImpOpBase + 54, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #783 = tTAILJMPdND |
| 9609 | { 782, 3, 0, 4, 853, 1, 0, 545, ARMImpOpBase + 54, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #782 = tTAILJMPd |
| 9610 | { 781, 3, 1, 2, 41, 0, 1, 518, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook), 0x0ULL }, // Inst #781 = tSUBSrr |
| 9611 | { 780, 3, 1, 2, 42, 0, 1, 521, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook), 0x0ULL }, // Inst #780 = tSUBSi8 |
| 9612 | { 779, 3, 1, 2, 42, 0, 1, 521, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook), 0x0ULL }, // Inst #779 = tSUBSi3 |
| 9613 | { 778, 3, 1, 2, 41, 1, 1, 518, ARMImpOpBase + 63, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook), 0x0ULL }, // Inst #778 = tSBCS |
| 9614 | { 777, 2, 1, 2, 41, 0, 1, 587, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook), 0x0ULL }, // Inst #777 = tRSBS |
| 9615 | { 776, 3, 0, 2, 423, 0, 0, 584, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #776 = tPOP_RET |
| 9616 | { 775, 2, 1, 16, 871, 0, 1, 443, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable), 0x0ULL }, // Inst #775 = tMOVi32imm |
| 9617 | { 774, 5, 1, 0, 871, 0, 0, 579, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #774 = tMOVCCr_pseudo |
| 9618 | { 773, 3, 1, 2, 1274, 0, 1, 521, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook), 0x0ULL }, // Inst #773 = tLSLSri |
| 9619 | { 772, 4, 1, 2, 42, 0, 0, 575, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #772 = tLEApcrelJT |
| 9620 | { 771, 4, 1, 2, 42, 0, 0, 575, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0x0ULL }, // Inst #771 = tLEApcrel |
| 9621 | { 770, 3, 1, 0, 393, 0, 0, 572, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL }, // Inst #770 = tLDRpci_pic |
| 9622 | { 769, 5, 2, 4, 904, 0, 0, 567, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #769 = tLDR_postidx |
| 9623 | { 768, 2, 1, 0, 1023, 0, 0, 538, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #768 = tLDRLIT_ga_pcrel |
| 9624 | { 767, 2, 1, 0, 1022, 0, 0, 538, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #767 = tLDRLIT_ga_abs |
| 9625 | { 766, 4, 0, 4, 1020, 0, 0, 563, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #766 = tLDRConstPool |
| 9626 | { 765, 5, 1, 2, 1017, 0, 0, 558, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #765 = tLDMIA_UPD |
| 9627 | { 764, 5, 2, 0, 0, 0, 0, 548, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #764 = tCMP_SWAP_8 |
| 9628 | { 763, 5, 2, 0, 0, 0, 0, 553, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #763 = tCMP_SWAP_32 |
| 9629 | { 762, 5, 2, 0, 0, 0, 0, 548, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #762 = tCMP_SWAP_16 |
| 9630 | { 761, 3, 0, 4, 855, 0, 1, 545, ARMImpOpBase + 65, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #761 = tBfar |
| 9631 | { 760, 3, 0, 2, 853, 0, 0, 542, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #760 = tBX_RET_vararg |
| 9632 | { 759, 2, 0, 2, 853, 0, 0, 540, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #759 = tBX_RET |
| 9633 | { 758, 1, 0, 4, 853, 1, 1, 207, ARMImpOpBase + 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call), 0x0ULL }, // Inst #758 = tBX_CALL |
| 9634 | { 757, 0, 0, 2, 853, 0, 0, 1, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #757 = tBXNS_RET |
| 9635 | { 756, 2, 0, 2, 861, 0, 0, 538, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // Inst #756 = tBR_JTr |
| 9636 | { 755, 3, 0, 2, 862, 0, 0, 535, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #755 = tBRIND |
| 9637 | { 754, 4, 0, 4, 6, 1, 1, 531, ARMImpOpBase + 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #754 = tBL_PUSHLR |
| 9638 | { 753, 3, 0, 2, 859, 1, 1, 528, ARMImpOpBase + 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable), 0x0ULL }, // Inst #753 = tBLXr_noip |
| 9639 | { 752, 1, 0, 0, 6, 1, 1, 527, ARMImpOpBase + 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call), 0x0ULL }, // Inst #752 = tBLXNS_CALL |
| 9640 | { 751, 2, 0, 0, 1039, 1, 1, 21, ARMImpOpBase + 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #751 = tADJCALLSTACKUP |
| 9641 | { 750, 2, 0, 0, 1039, 1, 1, 21, ARMImpOpBase + 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #750 = tADJCALLSTACKDOWN |
| 9642 | { 749, 3, 1, 0, 865, 0, 1, 524, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #749 = tADDframe |
| 9643 | { 748, 3, 1, 2, 41, 0, 1, 518, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Add)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL }, // Inst #748 = tADDSrr |
| 9644 | { 747, 3, 1, 2, 42, 0, 1, 521, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Add)|(1ULL<<MCID::HasPostISelHook), 0x0ULL }, // Inst #747 = tADDSi8 |
| 9645 | { 746, 3, 1, 2, 42, 0, 1, 521, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Add)|(1ULL<<MCID::HasPostISelHook), 0x0ULL }, // Inst #746 = tADDSi3 |
| 9646 | { 745, 3, 1, 2, 41, 1, 1, 518, ARMImpOpBase + 63, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Add)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL }, // Inst #745 = tADCS |
| 9647 | { 744, 4, 1, 8, 6, 0, 1, 514, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #744 = t2WhileLoopStartTP |
| 9648 | { 743, 3, 1, 8, 6, 0, 1, 511, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #743 = t2WhileLoopStartLR |
| 9649 | { 742, 2, 0, 4, 6, 0, 1, 205, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #742 = t2WhileLoopStart |
| 9650 | { 741, 2, 1, 4, 32, 0, 0, 434, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #741 = t2WhileLoopSetup |
| 9651 | { 740, 4, 0, 4, 1234, 0, 0, 230, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #740 = t2TBH_JT |
| 9652 | { 739, 4, 0, 4, 1234, 0, 0, 230, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #739 = t2TBB_JT |
| 9653 | { 738, 0, 0, 4, 0, 0, 0, 1, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #738 = t2SpeculationBarrierSBEndBB |
| 9654 | { 737, 0, 0, 8, 0, 0, 0, 1, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #737 = t2SpeculationBarrierISBDSBEndBB |
| 9655 | { 736, 6, 1, 4, 1237, 0, 1, 425, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL }, // Inst #736 = t2SUBSrs |
| 9656 | { 735, 5, 1, 4, 1270, 0, 1, 420, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL }, // Inst #735 = t2SUBSrr |
| 9657 | { 734, 5, 1, 4, 1111, 0, 1, 415, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL }, // Inst #734 = t2SUBSri |
| 9658 | { 733, 6, 1, 4, 443, 0, 0, 505, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #733 = t2STR_preidx |
| 9659 | { 732, 5, 0, 4, 942, 0, 0, 321, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x0ULL }, // Inst #732 = t2STR_PRE_imm |
| 9660 | { 731, 5, 0, 4, 952, 0, 0, 321, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x0ULL }, // Inst #731 = t2STR_POST_imm |
| 9661 | { 730, 6, 1, 4, 443, 0, 0, 505, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #730 = t2STRH_preidx |
| 9662 | { 729, 5, 0, 4, 942, 0, 0, 321, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x0ULL }, // Inst #729 = t2STRH_PRE_imm |
| 9663 | { 728, 5, 0, 4, 440, 0, 0, 321, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x0ULL }, // Inst #728 = t2STRH_POST_imm |
| 9664 | { 727, 5, 0, 4, 0, 0, 0, 321, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x0ULL }, // Inst #727 = t2STRH_OFFSET_imm |
| 9665 | { 726, 6, 1, 4, 443, 0, 0, 505, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #726 = t2STRB_preidx |
| 9666 | { 725, 5, 0, 4, 942, 0, 0, 321, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x0ULL }, // Inst #725 = t2STRB_PRE_imm |
| 9667 | { 724, 5, 0, 4, 952, 0, 0, 321, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x0ULL }, // Inst #724 = t2STRB_POST_imm |
| 9668 | { 723, 5, 0, 4, 0, 0, 0, 321, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x0ULL }, // Inst #723 = t2STRB_OFFSET_imm |
| 9669 | { 722, 6, 1, 4, 1267, 0, 1, 499, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL }, // Inst #722 = t2RSBSrs |
| 9670 | { 721, 5, 1, 4, 1071, 0, 1, 494, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL }, // Inst #721 = t2RSBSri |
| 9671 | { 720, 5, 1, 4, 695, 0, 0, 464, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable), 0x0ULL }, // Inst #720 = t2MVNCCi |
| 9672 | { 719, 6, 0, 4, 690, 0, 0, 484, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #719 = t2MOVsr |
| 9673 | { 718, 5, 0, 4, 712, 0, 0, 479, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #718 = t2MOVsi |
| 9674 | { 717, 2, 1, 8, 354, 0, 0, 443, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable), 0x0ULL }, // Inst #717 = t2MOVi32imm |
| 9675 | { 716, 3, 1, 4, 356, 0, 0, 445, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #716 = t2MOVi16_ga_pcrel |
| 9676 | { 715, 2, 1, 0, 355, 0, 0, 443, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable), 0x0ULL }, // Inst #715 = t2MOV_ga_pcrel |
| 9677 | { 714, 4, 1, 4, 878, 0, 0, 490, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #714 = t2MOVTi16_ga_pcrel |
| 9678 | { 713, 6, 0, 4, 1097, 0, 0, 484, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #713 = t2MOVSsr |
| 9679 | { 712, 5, 0, 4, 1096, 0, 0, 479, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #712 = t2MOVSsi |
| 9680 | { 711, 6, 1, 4, 876, 0, 0, 458, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable), 0x0ULL }, // Inst #711 = t2MOVCCror |
| 9681 | { 710, 5, 1, 4, 877, 0, 0, 474, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Select)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #710 = t2MOVCCr |
| 9682 | { 709, 6, 1, 4, 876, 0, 0, 458, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable), 0x0ULL }, // Inst #709 = t2MOVCClsr |
| 9683 | { 708, 6, 1, 4, 876, 0, 0, 458, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable), 0x0ULL }, // Inst #708 = t2MOVCClsl |
| 9684 | { 707, 5, 1, 8, 353, 0, 0, 469, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable), 0x0ULL }, // Inst #707 = t2MOVCCi32imm |
| 9685 | { 706, 5, 1, 4, 681, 0, 0, 464, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable), 0x0ULL }, // Inst #706 = t2MOVCCi16 |
| 9686 | { 705, 5, 1, 4, 681, 0, 0, 464, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable), 0x0ULL }, // Inst #705 = t2MOVCCi |
| 9687 | { 704, 6, 1, 4, 876, 0, 0, 458, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable), 0x0ULL }, // Inst #704 = t2MOVCCasr |
| 9688 | { 703, 3, 1, 8, 6, 0, 1, 455, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #703 = t2LoopEndDec |
| 9689 | { 702, 2, 0, 8, 6, 0, 1, 205, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #702 = t2LoopEnd |
| 9690 | { 701, 3, 1, 4, 1112, 0, 0, 452, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // Inst #701 = t2LoopDec |
| 9691 | { 700, 4, 1, 4, 1, 0, 0, 448, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #700 = t2LEApcrelJT |
| 9692 | { 699, 4, 1, 4, 1, 0, 0, 448, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0x0ULL }, // Inst #699 = t2LEApcrel |
| 9693 | { 698, 4, 0, 4, 907, 0, 0, 243, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #698 = t2LDRpcrel |
| 9694 | { 697, 3, 1, 0, 388, 0, 0, 445, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL }, // Inst #697 = t2LDRpci_pic |
| 9695 | { 696, 5, 0, 4, 916, 0, 0, 321, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #696 = t2LDR_PRE_imm |
| 9696 | { 695, 5, 0, 4, 408, 0, 0, 321, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #695 = t2LDR_POST_imm |
| 9697 | { 694, 4, 0, 4, 398, 0, 0, 439, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #694 = t2LDRSHpcrel |
| 9698 | { 693, 5, 0, 4, 917, 0, 0, 321, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #693 = t2LDRSH_PRE_imm |
| 9699 | { 692, 5, 0, 4, 413, 0, 0, 321, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #692 = t2LDRSH_POST_imm |
| 9700 | { 691, 5, 0, 4, 1019, 0, 0, 321, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #691 = t2LDRSH_OFFSET_imm |
| 9701 | { 690, 4, 0, 4, 398, 0, 0, 439, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #690 = t2LDRSBpcrel |
| 9702 | { 689, 5, 0, 4, 917, 0, 0, 321, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #689 = t2LDRSB_PRE_imm |
| 9703 | { 688, 5, 0, 4, 413, 0, 0, 321, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #688 = t2LDRSB_POST_imm |
| 9704 | { 687, 5, 0, 4, 1019, 0, 0, 321, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #687 = t2LDRSB_OFFSET_imm |
| 9705 | { 686, 2, 1, 0, 1021, 0, 0, 443, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #686 = t2LDRLIT_ga_pcrel |
| 9706 | { 685, 4, 0, 4, 1221, 0, 0, 439, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #685 = t2LDRHpcrel |
| 9707 | { 684, 5, 0, 4, 1225, 0, 0, 321, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #684 = t2LDRH_PRE_imm |
| 9708 | { 683, 5, 0, 4, 1224, 0, 0, 321, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #683 = t2LDRH_POST_imm |
| 9709 | { 682, 5, 0, 4, 1019, 0, 0, 321, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #682 = t2LDRH_OFFSET_imm |
| 9710 | { 681, 4, 0, 4, 1020, 0, 0, 243, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #681 = t2LDRConstPool |
| 9711 | { 680, 4, 0, 4, 1221, 0, 0, 439, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #680 = t2LDRBpcrel |
| 9712 | { 679, 5, 0, 4, 910, 0, 0, 321, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #679 = t2LDRB_PRE_imm |
| 9713 | { 678, 5, 0, 4, 927, 0, 0, 321, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #678 = t2LDRB_POST_imm |
| 9714 | { 677, 5, 0, 4, 1019, 0, 0, 321, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #677 = t2LDRB_OFFSET_imm |
| 9715 | { 676, 5, 1, 4, 1016, 0, 0, 234, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #676 = t2LDMIA_RET |
| 9716 | { 675, 3, 1, 4, 32, 0, 0, 436, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #675 = t2DoLoopStartTP |
| 9717 | { 674, 2, 1, 4, 32, 0, 0, 434, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #674 = t2DoLoopStart |
| 9718 | { 673, 3, 0, 0, 7, 1, 1, 431, ARMImpOpBase + 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable), 0x0ULL }, // Inst #673 = t2CALL_BTI |
| 9719 | { 672, 3, 0, 4, 862, 0, 0, 208, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // Inst #672 = t2BR_JT |
| 9720 | { 671, 1, 0, 0, 1284, 0, 0, 0, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #671 = t2BF_LabelPseudo |
| 9721 | { 670, 6, 1, 4, 703, 0, 1, 425, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL }, // Inst #670 = t2ADDSrs |
| 9722 | { 669, 5, 1, 4, 1269, 0, 1, 420, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL }, // Inst #669 = t2ADDSrr |
| 9723 | { 668, 5, 1, 4, 1110, 0, 1, 415, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL }, // Inst #668 = t2ADDSri |
| 9724 | { 667, 2, 1, 0, 683, 0, 1, 413, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #667 = t2ABS |
| 9725 | { 666, 1, 0, 0, 851, 0, 1, 207, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #666 = WIN__DBZCHK |
| 9726 | { 665, 0, 0, 0, 851, 1, 2, 1, ARMImpOpBase + 60, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #665 = WIN__CHKSTK |
| 9727 | { 664, 6, 0, 4, 838, 0, 0, 390, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #664 = VST4qWB_register_Asm_8 |
| 9728 | { 663, 6, 0, 4, 838, 0, 0, 390, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #663 = VST4qWB_register_Asm_32 |
| 9729 | { 662, 6, 0, 4, 838, 0, 0, 390, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #662 = VST4qWB_register_Asm_16 |
| 9730 | { 661, 5, 0, 4, 838, 0, 0, 385, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #661 = VST4qWB_fixed_Asm_8 |
| 9731 | { 660, 5, 0, 4, 838, 0, 0, 385, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #660 = VST4qWB_fixed_Asm_32 |
| 9732 | { 659, 5, 0, 4, 838, 0, 0, 385, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #659 = VST4qWB_fixed_Asm_16 |
| 9733 | { 658, 5, 0, 4, 830, 0, 0, 385, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #658 = VST4qAsm_8 |
| 9734 | { 657, 5, 0, 4, 830, 0, 0, 385, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #657 = VST4qAsm_32 |
| 9735 | { 656, 5, 0, 4, 830, 0, 0, 385, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #656 = VST4qAsm_16 |
| 9736 | { 655, 6, 0, 4, 838, 0, 0, 390, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #655 = VST4dWB_register_Asm_8 |
| 9737 | { 654, 6, 0, 4, 838, 0, 0, 390, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #654 = VST4dWB_register_Asm_32 |
| 9738 | { 653, 6, 0, 4, 838, 0, 0, 390, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #653 = VST4dWB_register_Asm_16 |
| 9739 | { 652, 5, 0, 4, 838, 0, 0, 385, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #652 = VST4dWB_fixed_Asm_8 |
| 9740 | { 651, 5, 0, 4, 838, 0, 0, 385, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #651 = VST4dWB_fixed_Asm_32 |
| 9741 | { 650, 5, 0, 4, 838, 0, 0, 385, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #650 = VST4dWB_fixed_Asm_16 |
| 9742 | { 649, 5, 0, 4, 830, 0, 0, 385, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #649 = VST4dAsm_8 |
| 9743 | { 648, 5, 0, 4, 830, 0, 0, 385, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #648 = VST4dAsm_32 |
| 9744 | { 647, 5, 0, 4, 830, 0, 0, 385, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #647 = VST4dAsm_16 |
| 9745 | { 646, 7, 0, 4, 842, 0, 0, 378, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #646 = VST4LNqWB_register_Asm_32 |
| 9746 | { 645, 7, 0, 4, 842, 0, 0, 378, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #645 = VST4LNqWB_register_Asm_16 |
| 9747 | { 644, 6, 0, 4, 842, 0, 0, 372, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #644 = VST4LNqWB_fixed_Asm_32 |
| 9748 | { 643, 6, 0, 4, 842, 0, 0, 372, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #643 = VST4LNqWB_fixed_Asm_16 |
| 9749 | { 642, 6, 0, 4, 836, 0, 0, 372, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #642 = VST4LNqAsm_32 |
| 9750 | { 641, 6, 0, 4, 836, 0, 0, 372, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #641 = VST4LNqAsm_16 |
| 9751 | { 640, 7, 0, 4, 840, 0, 0, 378, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #640 = VST4LNdWB_register_Asm_8 |
| 9752 | { 639, 7, 0, 4, 840, 0, 0, 378, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #639 = VST4LNdWB_register_Asm_32 |
| 9753 | { 638, 7, 0, 4, 840, 0, 0, 378, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #638 = VST4LNdWB_register_Asm_16 |
| 9754 | { 637, 6, 0, 4, 840, 0, 0, 372, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #637 = VST4LNdWB_fixed_Asm_8 |
| 9755 | { 636, 6, 0, 4, 840, 0, 0, 372, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #636 = VST4LNdWB_fixed_Asm_32 |
| 9756 | { 635, 6, 0, 4, 840, 0, 0, 372, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #635 = VST4LNdWB_fixed_Asm_16 |
| 9757 | { 634, 6, 0, 4, 833, 0, 0, 372, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #634 = VST4LNdAsm_8 |
| 9758 | { 633, 6, 0, 4, 833, 0, 0, 372, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #633 = VST4LNdAsm_32 |
| 9759 | { 632, 6, 0, 4, 833, 0, 0, 372, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #632 = VST4LNdAsm_16 |
| 9760 | { 631, 6, 0, 4, 824, 0, 0, 390, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #631 = VST3qWB_register_Asm_8 |
| 9761 | { 630, 6, 0, 4, 824, 0, 0, 390, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #630 = VST3qWB_register_Asm_32 |
| 9762 | { 629, 6, 0, 4, 824, 0, 0, 390, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #629 = VST3qWB_register_Asm_16 |
| 9763 | { 628, 5, 0, 4, 824, 0, 0, 385, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #628 = VST3qWB_fixed_Asm_8 |
| 9764 | { 627, 5, 0, 4, 824, 0, 0, 385, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #627 = VST3qWB_fixed_Asm_32 |
| 9765 | { 626, 5, 0, 4, 824, 0, 0, 385, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #626 = VST3qWB_fixed_Asm_16 |
| 9766 | { 625, 5, 0, 4, 817, 0, 0, 385, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #625 = VST3qAsm_8 |
| 9767 | { 624, 5, 0, 4, 817, 0, 0, 385, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #624 = VST3qAsm_32 |
| 9768 | { 623, 5, 0, 4, 817, 0, 0, 385, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #623 = VST3qAsm_16 |
| 9769 | { 622, 6, 0, 4, 824, 0, 0, 390, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #622 = VST3dWB_register_Asm_8 |
| 9770 | { 621, 6, 0, 4, 824, 0, 0, 390, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #621 = VST3dWB_register_Asm_32 |
| 9771 | { 620, 6, 0, 4, 824, 0, 0, 390, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #620 = VST3dWB_register_Asm_16 |
| 9772 | { 619, 5, 0, 4, 824, 0, 0, 385, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #619 = VST3dWB_fixed_Asm_8 |
| 9773 | { 618, 5, 0, 4, 824, 0, 0, 385, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #618 = VST3dWB_fixed_Asm_32 |
| 9774 | { 617, 5, 0, 4, 824, 0, 0, 385, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #617 = VST3dWB_fixed_Asm_16 |
| 9775 | { 616, 5, 0, 4, 817, 0, 0, 385, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #616 = VST3dAsm_8 |
| 9776 | { 615, 5, 0, 4, 817, 0, 0, 385, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #615 = VST3dAsm_32 |
| 9777 | { 614, 5, 0, 4, 817, 0, 0, 385, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #614 = VST3dAsm_16 |
| 9778 | { 613, 7, 0, 4, 828, 0, 0, 378, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #613 = VST3LNqWB_register_Asm_32 |
| 9779 | { 612, 7, 0, 4, 828, 0, 0, 378, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #612 = VST3LNqWB_register_Asm_16 |
| 9780 | { 611, 6, 0, 4, 828, 0, 0, 372, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #611 = VST3LNqWB_fixed_Asm_32 |
| 9781 | { 610, 6, 0, 4, 828, 0, 0, 372, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #610 = VST3LNqWB_fixed_Asm_16 |
| 9782 | { 609, 6, 0, 4, 822, 0, 0, 372, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #609 = VST3LNqAsm_32 |
| 9783 | { 608, 6, 0, 4, 822, 0, 0, 372, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #608 = VST3LNqAsm_16 |
| 9784 | { 607, 7, 0, 4, 826, 0, 0, 378, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #607 = VST3LNdWB_register_Asm_8 |
| 9785 | { 606, 7, 0, 4, 826, 0, 0, 378, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #606 = VST3LNdWB_register_Asm_32 |
| 9786 | { 605, 7, 0, 4, 826, 0, 0, 378, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #605 = VST3LNdWB_register_Asm_16 |
| 9787 | { 604, 6, 0, 4, 826, 0, 0, 372, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #604 = VST3LNdWB_fixed_Asm_8 |
| 9788 | { 603, 6, 0, 4, 826, 0, 0, 372, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #603 = VST3LNdWB_fixed_Asm_32 |
| 9789 | { 602, 6, 0, 4, 826, 0, 0, 372, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #602 = VST3LNdWB_fixed_Asm_16 |
| 9790 | { 601, 6, 0, 4, 820, 0, 0, 372, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #601 = VST3LNdAsm_8 |
| 9791 | { 600, 6, 0, 4, 820, 0, 0, 372, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #600 = VST3LNdAsm_32 |
| 9792 | { 599, 6, 0, 4, 820, 0, 0, 372, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #599 = VST3LNdAsm_16 |
| 9793 | { 598, 7, 0, 4, 815, 0, 0, 378, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #598 = VST2LNqWB_register_Asm_32 |
| 9794 | { 597, 7, 0, 4, 815, 0, 0, 378, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #597 = VST2LNqWB_register_Asm_16 |
| 9795 | { 596, 6, 0, 4, 815, 0, 0, 372, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #596 = VST2LNqWB_fixed_Asm_32 |
| 9796 | { 595, 6, 0, 4, 815, 0, 0, 372, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #595 = VST2LNqWB_fixed_Asm_16 |
| 9797 | { 594, 6, 0, 4, 811, 0, 0, 372, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #594 = VST2LNqAsm_32 |
| 9798 | { 593, 6, 0, 4, 811, 0, 0, 372, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #593 = VST2LNqAsm_16 |
| 9799 | { 592, 7, 0, 4, 813, 0, 0, 378, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #592 = VST2LNdWB_register_Asm_8 |
| 9800 | { 591, 7, 0, 4, 813, 0, 0, 378, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #591 = VST2LNdWB_register_Asm_32 |
| 9801 | { 590, 7, 0, 4, 813, 0, 0, 378, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #590 = VST2LNdWB_register_Asm_16 |
| 9802 | { 589, 6, 0, 4, 813, 0, 0, 372, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #589 = VST2LNdWB_fixed_Asm_8 |
| 9803 | { 588, 6, 0, 4, 813, 0, 0, 372, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #588 = VST2LNdWB_fixed_Asm_32 |
| 9804 | { 587, 6, 0, 4, 813, 0, 0, 372, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #587 = VST2LNdWB_fixed_Asm_16 |
| 9805 | { 586, 6, 0, 4, 808, 0, 0, 372, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #586 = VST2LNdAsm_8 |
| 9806 | { 585, 6, 0, 4, 808, 0, 0, 372, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #585 = VST2LNdAsm_32 |
| 9807 | { 584, 6, 0, 4, 808, 0, 0, 372, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #584 = VST2LNdAsm_16 |
| 9808 | { 583, 7, 0, 4, 805, 0, 0, 378, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #583 = VST1LNdWB_register_Asm_8 |
| 9809 | { 582, 7, 0, 4, 805, 0, 0, 378, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #582 = VST1LNdWB_register_Asm_32 |
| 9810 | { 581, 7, 0, 4, 805, 0, 0, 378, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #581 = VST1LNdWB_register_Asm_16 |
| 9811 | { 580, 6, 0, 4, 805, 0, 0, 372, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #580 = VST1LNdWB_fixed_Asm_8 |
| 9812 | { 579, 6, 0, 4, 805, 0, 0, 372, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #579 = VST1LNdWB_fixed_Asm_32 |
| 9813 | { 578, 6, 0, 4, 805, 0, 0, 372, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #578 = VST1LNdWB_fixed_Asm_16 |
| 9814 | { 577, 6, 0, 4, 802, 0, 0, 372, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #577 = VST1LNdAsm_8 |
| 9815 | { 576, 6, 0, 4, 802, 0, 0, 372, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #576 = VST1LNdAsm_32 |
| 9816 | { 575, 6, 0, 4, 802, 0, 0, 372, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #575 = VST1LNdAsm_16 |
| 9817 | { 574, 5, 1, 0, 569, 0, 0, 408, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable), 0x0ULL }, // Inst #574 = VMOVScc |
| 9818 | { 573, 1, 1, 4, 1000, 0, 0, 407, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #573 = VMOVQ0 |
| 9819 | { 572, 5, 1, 0, 967, 0, 0, 402, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable), 0x0ULL }, // Inst #572 = VMOVHcc |
| 9820 | { 571, 5, 1, 0, 568, 0, 0, 397, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable), 0x0ULL }, // Inst #571 = VMOVDcc |
| 9821 | { 570, 1, 1, 4, 1056, 0, 0, 396, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #570 = VMOVD0 |
| 9822 | { 569, 6, 0, 4, 1045, 0, 0, 390, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #569 = VLD4qWB_register_Asm_8 |
| 9823 | { 568, 6, 0, 4, 1045, 0, 0, 390, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #568 = VLD4qWB_register_Asm_32 |
| 9824 | { 567, 6, 0, 4, 1045, 0, 0, 390, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #567 = VLD4qWB_register_Asm_16 |
| 9825 | { 566, 5, 0, 4, 1045, 0, 0, 385, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #566 = VLD4qWB_fixed_Asm_8 |
| 9826 | { 565, 5, 0, 4, 1045, 0, 0, 385, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #565 = VLD4qWB_fixed_Asm_32 |
| 9827 | { 564, 5, 0, 4, 1045, 0, 0, 385, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #564 = VLD4qWB_fixed_Asm_16 |
| 9828 | { 563, 5, 0, 4, 1045, 0, 0, 385, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #563 = VLD4qAsm_8 |
| 9829 | { 562, 5, 0, 4, 1045, 0, 0, 385, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #562 = VLD4qAsm_32 |
| 9830 | { 561, 5, 0, 4, 1045, 0, 0, 385, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #561 = VLD4qAsm_16 |
| 9831 | { 560, 6, 0, 4, 1045, 0, 0, 390, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #560 = VLD4dWB_register_Asm_8 |
| 9832 | { 559, 6, 0, 4, 1045, 0, 0, 390, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #559 = VLD4dWB_register_Asm_32 |
| 9833 | { 558, 6, 0, 4, 1045, 0, 0, 390, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #558 = VLD4dWB_register_Asm_16 |
| 9834 | { 557, 5, 0, 4, 1045, 0, 0, 385, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #557 = VLD4dWB_fixed_Asm_8 |
| 9835 | { 556, 5, 0, 4, 1045, 0, 0, 385, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #556 = VLD4dWB_fixed_Asm_32 |
| 9836 | { 555, 5, 0, 4, 1045, 0, 0, 385, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #555 = VLD4dWB_fixed_Asm_16 |
| 9837 | { 554, 5, 0, 4, 1045, 0, 0, 385, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #554 = VLD4dAsm_8 |
| 9838 | { 553, 5, 0, 4, 1045, 0, 0, 385, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #553 = VLD4dAsm_32 |
| 9839 | { 552, 5, 0, 4, 1045, 0, 0, 385, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #552 = VLD4dAsm_16 |
| 9840 | { 551, 7, 0, 4, 1045, 0, 0, 378, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #551 = VLD4LNqWB_register_Asm_32 |
| 9841 | { 550, 7, 0, 4, 1045, 0, 0, 378, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #550 = VLD4LNqWB_register_Asm_16 |
| 9842 | { 549, 6, 0, 4, 1045, 0, 0, 372, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #549 = VLD4LNqWB_fixed_Asm_32 |
| 9843 | { 548, 6, 0, 4, 1045, 0, 0, 372, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #548 = VLD4LNqWB_fixed_Asm_16 |
| 9844 | { 547, 6, 0, 4, 1045, 0, 0, 372, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #547 = VLD4LNqAsm_32 |
| 9845 | { 546, 6, 0, 4, 1045, 0, 0, 372, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #546 = VLD4LNqAsm_16 |
| 9846 | { 545, 7, 0, 4, 1045, 0, 0, 378, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #545 = VLD4LNdWB_register_Asm_8 |
| 9847 | { 544, 7, 0, 4, 1045, 0, 0, 378, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #544 = VLD4LNdWB_register_Asm_32 |
| 9848 | { 543, 7, 0, 4, 1045, 0, 0, 378, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #543 = VLD4LNdWB_register_Asm_16 |
| 9849 | { 542, 6, 0, 4, 1045, 0, 0, 372, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #542 = VLD4LNdWB_fixed_Asm_8 |
| 9850 | { 541, 6, 0, 4, 1045, 0, 0, 372, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #541 = VLD4LNdWB_fixed_Asm_32 |
| 9851 | { 540, 6, 0, 4, 1045, 0, 0, 372, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #540 = VLD4LNdWB_fixed_Asm_16 |
| 9852 | { 539, 6, 0, 4, 1045, 0, 0, 372, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #539 = VLD4LNdAsm_8 |
| 9853 | { 538, 6, 0, 4, 1045, 0, 0, 372, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #538 = VLD4LNdAsm_32 |
| 9854 | { 537, 6, 0, 4, 1045, 0, 0, 372, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #537 = VLD4LNdAsm_16 |
| 9855 | { 536, 6, 0, 4, 1045, 0, 0, 390, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #536 = VLD4DUPqWB_register_Asm_8 |
| 9856 | { 535, 6, 0, 4, 1045, 0, 0, 390, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #535 = VLD4DUPqWB_register_Asm_32 |
| 9857 | { 534, 6, 0, 4, 1045, 0, 0, 390, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #534 = VLD4DUPqWB_register_Asm_16 |
| 9858 | { 533, 5, 0, 4, 1045, 0, 0, 385, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #533 = VLD4DUPqWB_fixed_Asm_8 |
| 9859 | { 532, 5, 0, 4, 1045, 0, 0, 385, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #532 = VLD4DUPqWB_fixed_Asm_32 |
| 9860 | { 531, 5, 0, 4, 1045, 0, 0, 385, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #531 = VLD4DUPqWB_fixed_Asm_16 |
| 9861 | { 530, 5, 0, 4, 1045, 0, 0, 385, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #530 = VLD4DUPqAsm_8 |
| 9862 | { 529, 5, 0, 4, 1045, 0, 0, 385, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #529 = VLD4DUPqAsm_32 |
| 9863 | { 528, 5, 0, 4, 1045, 0, 0, 385, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #528 = VLD4DUPqAsm_16 |
| 9864 | { 527, 6, 0, 4, 1045, 0, 0, 390, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #527 = VLD4DUPdWB_register_Asm_8 |
| 9865 | { 526, 6, 0, 4, 1045, 0, 0, 390, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #526 = VLD4DUPdWB_register_Asm_32 |
| 9866 | { 525, 6, 0, 4, 1045, 0, 0, 390, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #525 = VLD4DUPdWB_register_Asm_16 |
| 9867 | { 524, 5, 0, 4, 1045, 0, 0, 385, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #524 = VLD4DUPdWB_fixed_Asm_8 |
| 9868 | { 523, 5, 0, 4, 1045, 0, 0, 385, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #523 = VLD4DUPdWB_fixed_Asm_32 |
| 9869 | { 522, 5, 0, 4, 1045, 0, 0, 385, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #522 = VLD4DUPdWB_fixed_Asm_16 |
| 9870 | { 521, 5, 0, 4, 1045, 0, 0, 385, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #521 = VLD4DUPdAsm_8 |
| 9871 | { 520, 5, 0, 4, 1045, 0, 0, 385, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #520 = VLD4DUPdAsm_32 |
| 9872 | { 519, 5, 0, 4, 1045, 0, 0, 385, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #519 = VLD4DUPdAsm_16 |
| 9873 | { 518, 6, 0, 4, 1045, 0, 0, 390, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #518 = VLD3qWB_register_Asm_8 |
| 9874 | { 517, 6, 0, 4, 1045, 0, 0, 390, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #517 = VLD3qWB_register_Asm_32 |
| 9875 | { 516, 6, 0, 4, 1045, 0, 0, 390, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #516 = VLD3qWB_register_Asm_16 |
| 9876 | { 515, 5, 0, 4, 1045, 0, 0, 385, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #515 = VLD3qWB_fixed_Asm_8 |
| 9877 | { 514, 5, 0, 4, 1045, 0, 0, 385, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #514 = VLD3qWB_fixed_Asm_32 |
| 9878 | { 513, 5, 0, 4, 1045, 0, 0, 385, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #513 = VLD3qWB_fixed_Asm_16 |
| 9879 | { 512, 5, 0, 4, 1045, 0, 0, 385, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #512 = VLD3qAsm_8 |
| 9880 | { 511, 5, 0, 4, 1045, 0, 0, 385, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #511 = VLD3qAsm_32 |
| 9881 | { 510, 5, 0, 4, 1045, 0, 0, 385, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #510 = VLD3qAsm_16 |
| 9882 | { 509, 6, 0, 4, 1045, 0, 0, 390, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #509 = VLD3dWB_register_Asm_8 |
| 9883 | { 508, 6, 0, 4, 1045, 0, 0, 390, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #508 = VLD3dWB_register_Asm_32 |
| 9884 | { 507, 6, 0, 4, 1045, 0, 0, 390, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #507 = VLD3dWB_register_Asm_16 |
| 9885 | { 506, 5, 0, 4, 1045, 0, 0, 385, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #506 = VLD3dWB_fixed_Asm_8 |
| 9886 | { 505, 5, 0, 4, 1045, 0, 0, 385, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #505 = VLD3dWB_fixed_Asm_32 |
| 9887 | { 504, 5, 0, 4, 1045, 0, 0, 385, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #504 = VLD3dWB_fixed_Asm_16 |
| 9888 | { 503, 5, 0, 4, 1045, 0, 0, 385, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #503 = VLD3dAsm_8 |
| 9889 | { 502, 5, 0, 4, 1045, 0, 0, 385, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #502 = VLD3dAsm_32 |
| 9890 | { 501, 5, 0, 4, 1045, 0, 0, 385, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #501 = VLD3dAsm_16 |
| 9891 | { 500, 7, 0, 4, 1045, 0, 0, 378, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #500 = VLD3LNqWB_register_Asm_32 |
| 9892 | { 499, 7, 0, 4, 1045, 0, 0, 378, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #499 = VLD3LNqWB_register_Asm_16 |
| 9893 | { 498, 6, 0, 4, 1045, 0, 0, 372, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #498 = VLD3LNqWB_fixed_Asm_32 |
| 9894 | { 497, 6, 0, 4, 1045, 0, 0, 372, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #497 = VLD3LNqWB_fixed_Asm_16 |
| 9895 | { 496, 6, 0, 4, 1045, 0, 0, 372, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #496 = VLD3LNqAsm_32 |
| 9896 | { 495, 6, 0, 4, 1045, 0, 0, 372, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #495 = VLD3LNqAsm_16 |
| 9897 | { 494, 7, 0, 4, 1045, 0, 0, 378, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #494 = VLD3LNdWB_register_Asm_8 |
| 9898 | { 493, 7, 0, 4, 1045, 0, 0, 378, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #493 = VLD3LNdWB_register_Asm_32 |
| 9899 | { 492, 7, 0, 4, 1045, 0, 0, 378, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #492 = VLD3LNdWB_register_Asm_16 |
| 9900 | { 491, 6, 0, 4, 1045, 0, 0, 372, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #491 = VLD3LNdWB_fixed_Asm_8 |
| 9901 | { 490, 6, 0, 4, 1045, 0, 0, 372, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #490 = VLD3LNdWB_fixed_Asm_32 |
| 9902 | { 489, 6, 0, 4, 1045, 0, 0, 372, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #489 = VLD3LNdWB_fixed_Asm_16 |
| 9903 | { 488, 6, 0, 4, 1045, 0, 0, 372, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #488 = VLD3LNdAsm_8 |
| 9904 | { 487, 6, 0, 4, 1045, 0, 0, 372, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #487 = VLD3LNdAsm_32 |
| 9905 | { 486, 6, 0, 4, 1045, 0, 0, 372, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #486 = VLD3LNdAsm_16 |
| 9906 | { 485, 6, 0, 4, 1045, 0, 0, 390, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #485 = VLD3DUPqWB_register_Asm_8 |
| 9907 | { 484, 6, 0, 4, 1045, 0, 0, 390, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #484 = VLD3DUPqWB_register_Asm_32 |
| 9908 | { 483, 6, 0, 4, 1045, 0, 0, 390, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #483 = VLD3DUPqWB_register_Asm_16 |
| 9909 | { 482, 5, 0, 4, 1045, 0, 0, 385, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #482 = VLD3DUPqWB_fixed_Asm_8 |
| 9910 | { 481, 5, 0, 4, 1045, 0, 0, 385, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #481 = VLD3DUPqWB_fixed_Asm_32 |
| 9911 | { 480, 5, 0, 4, 1045, 0, 0, 385, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #480 = VLD3DUPqWB_fixed_Asm_16 |
| 9912 | { 479, 5, 0, 4, 1045, 0, 0, 385, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #479 = VLD3DUPqAsm_8 |
| 9913 | { 478, 5, 0, 4, 1045, 0, 0, 385, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #478 = VLD3DUPqAsm_32 |
| 9914 | { 477, 5, 0, 4, 1045, 0, 0, 385, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #477 = VLD3DUPqAsm_16 |
| 9915 | { 476, 6, 0, 4, 1045, 0, 0, 390, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #476 = VLD3DUPdWB_register_Asm_8 |
| 9916 | { 475, 6, 0, 4, 1045, 0, 0, 390, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #475 = VLD3DUPdWB_register_Asm_32 |
| 9917 | { 474, 6, 0, 4, 1045, 0, 0, 390, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #474 = VLD3DUPdWB_register_Asm_16 |
| 9918 | { 473, 5, 0, 4, 1045, 0, 0, 385, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #473 = VLD3DUPdWB_fixed_Asm_8 |
| 9919 | { 472, 5, 0, 4, 1045, 0, 0, 385, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #472 = VLD3DUPdWB_fixed_Asm_32 |
| 9920 | { 471, 5, 0, 4, 1045, 0, 0, 385, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #471 = VLD3DUPdWB_fixed_Asm_16 |
| 9921 | { 470, 5, 0, 4, 1045, 0, 0, 385, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #470 = VLD3DUPdAsm_8 |
| 9922 | { 469, 5, 0, 4, 1045, 0, 0, 385, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #469 = VLD3DUPdAsm_32 |
| 9923 | { 468, 5, 0, 4, 1045, 0, 0, 385, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #468 = VLD3DUPdAsm_16 |
| 9924 | { 467, 7, 0, 4, 1045, 0, 0, 378, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #467 = VLD2LNqWB_register_Asm_32 |
| 9925 | { 466, 7, 0, 4, 1045, 0, 0, 378, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #466 = VLD2LNqWB_register_Asm_16 |
| 9926 | { 465, 6, 0, 4, 1045, 0, 0, 372, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #465 = VLD2LNqWB_fixed_Asm_32 |
| 9927 | { 464, 6, 0, 4, 1045, 0, 0, 372, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #464 = VLD2LNqWB_fixed_Asm_16 |
| 9928 | { 463, 6, 0, 4, 1045, 0, 0, 372, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #463 = VLD2LNqAsm_32 |
| 9929 | { 462, 6, 0, 4, 1045, 0, 0, 372, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #462 = VLD2LNqAsm_16 |
| 9930 | { 461, 7, 0, 4, 1045, 0, 0, 378, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #461 = VLD2LNdWB_register_Asm_8 |
| 9931 | { 460, 7, 0, 4, 1045, 0, 0, 378, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #460 = VLD2LNdWB_register_Asm_32 |
| 9932 | { 459, 7, 0, 4, 1045, 0, 0, 378, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #459 = VLD2LNdWB_register_Asm_16 |
| 9933 | { 458, 6, 0, 4, 1045, 0, 0, 372, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #458 = VLD2LNdWB_fixed_Asm_8 |
| 9934 | { 457, 6, 0, 4, 1045, 0, 0, 372, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #457 = VLD2LNdWB_fixed_Asm_32 |
| 9935 | { 456, 6, 0, 4, 1045, 0, 0, 372, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #456 = VLD2LNdWB_fixed_Asm_16 |
| 9936 | { 455, 6, 0, 4, 1045, 0, 0, 372, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #455 = VLD2LNdAsm_8 |
| 9937 | { 454, 6, 0, 4, 1045, 0, 0, 372, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #454 = VLD2LNdAsm_32 |
| 9938 | { 453, 6, 0, 4, 1045, 0, 0, 372, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #453 = VLD2LNdAsm_16 |
| 9939 | { 452, 7, 0, 4, 1045, 0, 0, 378, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #452 = VLD1LNdWB_register_Asm_8 |
| 9940 | { 451, 7, 0, 4, 1045, 0, 0, 378, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #451 = VLD1LNdWB_register_Asm_32 |
| 9941 | { 450, 7, 0, 4, 1045, 0, 0, 378, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #450 = VLD1LNdWB_register_Asm_16 |
| 9942 | { 449, 6, 0, 4, 1045, 0, 0, 372, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #449 = VLD1LNdWB_fixed_Asm_8 |
| 9943 | { 448, 6, 0, 4, 1045, 0, 0, 372, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #448 = VLD1LNdWB_fixed_Asm_32 |
| 9944 | { 447, 6, 0, 4, 1045, 0, 0, 372, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #447 = VLD1LNdWB_fixed_Asm_16 |
| 9945 | { 446, 6, 0, 4, 1045, 0, 0, 372, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #446 = VLD1LNdAsm_8 |
| 9946 | { 445, 6, 0, 4, 1045, 0, 0, 372, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #445 = VLD1LNdAsm_32 |
| 9947 | { 444, 6, 0, 4, 1045, 0, 0, 372, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #444 = VLD1LNdAsm_16 |
| 9948 | { 443, 7, 2, 4, 337, 0, 0, 340, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0x0ULL }, // Inst #443 = UMULLv5 |
| 9949 | { 442, 9, 2, 4, 339, 0, 0, 331, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x0ULL }, // Inst #442 = UMLALv5 |
| 9950 | { 441, 0, 0, 4, 858, 1, 4, 1, ARMImpOpBase + 55, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call), 0x0ULL }, // Inst #441 = TPsoft |
| 9951 | { 440, 2, 0, 0, 853, 1, 0, 370, ARMImpOpBase + 54, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #440 = TCRETURNrinotr12 |
| 9952 | { 439, 2, 0, 0, 853, 1, 0, 368, ARMImpOpBase + 54, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #439 = TCRETURNri |
| 9953 | { 438, 2, 0, 0, 853, 1, 0, 21, ARMImpOpBase + 54, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #438 = TCRETURNdi |
| 9954 | { 437, 1, 0, 4, 853, 1, 0, 295, ARMImpOpBase + 54, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #437 = TAILJMPr4 |
| 9955 | { 436, 1, 0, 4, 853, 1, 0, 367, ARMImpOpBase + 54, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #436 = TAILJMPr |
| 9956 | { 435, 1, 0, 4, 853, 1, 0, 193, ARMImpOpBase + 54, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #435 = TAILJMPd |
| 9957 | { 434, 0, 0, 4, 0, 0, 0, 1, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #434 = SpeculationBarrierSBEndBB |
| 9958 | { 433, 0, 0, 8, 0, 0, 0, 1, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #433 = SpeculationBarrierISBDSBEndBB |
| 9959 | { 432, 7, 1, 4, 4, 0, 1, 170, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL }, // Inst #432 = SUBSrsr |
| 9960 | { 431, 6, 1, 4, 3, 0, 1, 164, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL }, // Inst #431 = SUBSrsi |
| 9961 | { 430, 5, 1, 4, 2, 0, 1, 159, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL }, // Inst #430 = SUBSrr |
| 9962 | { 429, 5, 1, 4, 1, 0, 1, 154, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL }, // Inst #429 = SUBSri |
| 9963 | { 428, 3, 0, 4, 852, 0, 0, 364, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #428 = SUBS_PC_LR |
| 9964 | { 427, 7, 1, 4, 941, 0, 0, 350, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #427 = STRr_preidx |
| 9965 | { 426, 7, 1, 4, 941, 0, 0, 350, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #426 = STRi_preidx |
| 9966 | { 425, 4, 0, 4, 955, 0, 0, 239, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x0ULL }, // Inst #425 = STRT_POST |
| 9967 | { 424, 7, 1, 4, 941, 0, 0, 357, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #424 = STRH_preidx |
| 9968 | { 423, 7, 1, 4, 941, 0, 0, 350, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #423 = STRBr_preidx |
| 9969 | { 422, 7, 1, 4, 941, 0, 0, 350, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #422 = STRBi_preidx |
| 9970 | { 421, 4, 0, 4, 955, 0, 0, 239, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x0ULL }, // Inst #421 = STRBT_POST |
| 9971 | { 420, 4, 0, 64, 30, 0, 0, 251, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x3ULL }, // Inst #420 = STOREDUAL |
| 9972 | { 419, 3, 1, 0, 843, 0, 0, 347, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #419 = SPACE |
| 9973 | { 418, 7, 2, 4, 337, 0, 0, 340, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0x0ULL }, // Inst #418 = SMULLv5 |
| 9974 | { 417, 9, 2, 4, 339, 0, 0, 331, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x0ULL }, // Inst #417 = SMLALv5 |
| 9975 | { 416, 2, 0, 0, 0, 0, 0, 21, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #416 = SEH_StackAlloc |
| 9976 | { 415, 1, 0, 0, 0, 0, 0, 1, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #415 = SEH_SaveSP |
| 9977 | { 414, 2, 0, 0, 0, 0, 0, 21, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #414 = SEH_SaveRegs_Ret |
| 9978 | { 413, 2, 0, 0, 0, 0, 0, 21, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #413 = SEH_SaveRegs |
| 9979 | { 412, 1, 0, 0, 0, 0, 0, 1, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #412 = SEH_SaveLR |
| 9980 | { 411, 2, 0, 0, 0, 0, 0, 21, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #411 = SEH_SaveFRegs |
| 9981 | { 410, 0, 0, 0, 0, 0, 0, 1, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #410 = SEH_PrologEnd |
| 9982 | { 409, 1, 0, 0, 0, 0, 0, 1, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #409 = SEH_Nop_Ret |
| 9983 | { 408, 1, 0, 0, 0, 0, 0, 1, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #408 = SEH_Nop |
| 9984 | { 407, 0, 0, 0, 0, 0, 0, 1, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #407 = SEH_EpilogStart |
| 9985 | { 406, 0, 0, 0, 0, 0, 0, 1, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #406 = SEH_EpilogEnd |
| 9986 | { 405, 7, 1, 4, 4, 0, 1, 170, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL }, // Inst #405 = RSBSrsr |
| 9987 | { 404, 6, 1, 4, 3, 0, 1, 164, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL }, // Inst #404 = RSBSrsi |
| 9988 | { 403, 5, 1, 4, 692, 0, 1, 154, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL }, // Inst #403 = RSBSri |
| 9989 | { 402, 5, 0, 4, 720, 0, 0, 326, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #402 = RRXi |
| 9990 | { 401, 2, 1, 0, 722, 1, 0, 152, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x2000ULL }, // Inst #401 = RRX |
| 9991 | { 400, 6, 0, 4, 714, 0, 0, 187, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #400 = RORr |
| 9992 | { 399, 6, 0, 4, 713, 0, 0, 181, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #399 = RORi |
| 9993 | { 398, 5, 0, 4, 937, 0, 0, 321, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // Inst #398 = PICSTRH |
| 9994 | { 397, 5, 0, 4, 937, 0, 0, 321, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // Inst #397 = PICSTRB |
| 9995 | { 396, 5, 0, 4, 425, 0, 0, 321, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // Inst #396 = PICSTR |
| 9996 | { 395, 5, 1, 4, 903, 0, 0, 321, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // Inst #395 = PICLDRSH |
| 9997 | { 394, 5, 1, 4, 903, 0, 0, 321, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // Inst #394 = PICLDRSB |
| 9998 | { 393, 5, 1, 4, 902, 0, 0, 321, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // Inst #393 = PICLDRH |
| 9999 | { 392, 5, 1, 4, 902, 0, 0, 321, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // Inst #392 = PICLDRB |
| 10000 | { 391, 5, 1, 4, 346, 0, 0, 321, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // Inst #391 = PICLDR |
| 10001 | { 390, 5, 1, 4, 23, 0, 0, 154, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // Inst #390 = PICADD |
| 10002 | { 389, 5, 1, 4, 868, 0, 0, 267, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable), 0x0ULL }, // Inst #389 = MVNCCi |
| 10003 | { 388, 3, 0, 0, 0, 0, 1, 318, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #388 = MVE_MEMSETLOOPINST |
| 10004 | { 387, 3, 0, 0, 0, 0, 1, 315, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #387 = MVE_MEMCPYLOOPINST |
| 10005 | { 386, 6, 1, 4, 335, 0, 0, 309, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0x0ULL }, // Inst #386 = MULv5 |
| 10006 | { 385, 2, 0, 4, 0, 0, 0, 307, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4ULL }, // Inst #385 = MQQQQPRStore |
| 10007 | { 384, 2, 1, 4, 0, 0, 0, 307, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4ULL }, // Inst #384 = MQQQQPRLoad |
| 10008 | { 383, 2, 0, 4, 0, 0, 0, 305, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4ULL }, // Inst #383 = MQQPRStore |
| 10009 | { 382, 2, 1, 4, 0, 0, 0, 305, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4ULL }, // Inst #382 = MQQPRLoad |
| 10010 | { 381, 2, 1, 8, 1153, 0, 0, 303, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveReg), 0x40000ULL }, // Inst #381 = MQPRCopy |
| 10011 | { 380, 2, 1, 8, 330, 0, 0, 218, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable), 0x0ULL }, // Inst #380 = MOVi32imm |
| 10012 | { 379, 3, 1, 4, 866, 0, 0, 300, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #379 = MOVi16_ga_pcrel |
| 10013 | { 378, 2, 1, 0, 332, 0, 0, 218, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL }, // Inst #378 = MOV_ga_pcrel_ldr |
| 10014 | { 377, 2, 1, 0, 331, 0, 0, 218, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable), 0x0ULL }, // Inst #377 = MOV_ga_pcrel |
| 10015 | { 376, 4, 1, 4, 691, 0, 0, 296, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #376 = MOVTi16_ga_pcrel |
| 10016 | { 375, 1, 0, 4, 882, 0, 0, 295, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #375 = MOVPCRX |
| 10017 | { 374, 7, 1, 4, 327, 0, 0, 288, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable), 0x0ULL }, // Inst #374 = MOVCCsr |
| 10018 | { 373, 6, 1, 4, 873, 0, 0, 282, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable), 0x0ULL }, // Inst #373 = MOVCCsi |
| 10019 | { 372, 5, 1, 4, 870, 0, 0, 277, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Select)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #372 = MOVCCr |
| 10020 | { 371, 5, 1, 8, 329, 0, 0, 272, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable), 0x0ULL }, // Inst #371 = MOVCCi32imm |
| 10021 | { 370, 5, 1, 4, 866, 0, 0, 267, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable), 0x0ULL }, // Inst #370 = MOVCCi16 |
| 10022 | { 369, 5, 1, 4, 868, 0, 0, 267, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable), 0x0ULL }, // Inst #369 = MOVCCi |
| 10023 | { 368, 7, 1, 4, 336, 0, 0, 260, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x0ULL }, // Inst #368 = MLAv5 |
| 10024 | { 367, 5, 2, 0, 1042, 0, 0, 255, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #367 = MEMCPY |
| 10025 | { 366, 2, 1, 0, 715, 0, 1, 152, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x2000ULL }, // Inst #366 = LSRs1 |
| 10026 | { 365, 6, 0, 4, 714, 0, 0, 187, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #365 = LSRr |
| 10027 | { 364, 6, 0, 4, 875, 0, 0, 181, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #364 = LSRi |
| 10028 | { 363, 6, 0, 4, 714, 0, 0, 187, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #363 = LSLr |
| 10029 | { 362, 6, 0, 4, 875, 0, 0, 181, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #362 = LSLi |
| 10030 | { 361, 4, 1, 64, 12, 0, 0, 251, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x3ULL }, // Inst #361 = LOADDUAL |
| 10031 | { 360, 4, 1, 4, 1, 0, 0, 247, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #360 = LEApcrelJT |
| 10032 | { 359, 4, 1, 4, 1, 0, 0, 247, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #359 = LEApcrel |
| 10033 | { 358, 4, 1, 4, 933, 0, 0, 239, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #358 = LDRT_POST |
| 10034 | { 357, 4, 1, 4, 349, 0, 0, 239, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x0ULL }, // Inst #357 = LDRSHTii |
| 10035 | { 356, 4, 1, 4, 349, 0, 0, 239, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x0ULL }, // Inst #356 = LDRSBTii |
| 10036 | { 355, 2, 1, 0, 455, 0, 0, 218, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL }, // Inst #355 = LDRLIT_ga_pcrel_ldr |
| 10037 | { 354, 2, 1, 0, 454, 0, 0, 218, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable), 0x0ULL }, // Inst #354 = LDRLIT_ga_pcrel |
| 10038 | { 353, 2, 1, 0, 453, 0, 0, 218, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #353 = LDRLIT_ga_abs |
| 10039 | { 352, 4, 1, 4, 407, 0, 0, 239, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x0ULL }, // Inst #352 = LDRHTii |
| 10040 | { 351, 4, 1, 4, 901, 0, 0, 243, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #351 = LDRConstPool |
| 10041 | { 350, 4, 1, 4, 688, 0, 0, 239, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #350 = LDRBT_POST |
| 10042 | { 349, 5, 1, 4, 422, 0, 0, 234, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #349 = LDMIA_RET |
| 10043 | { 348, 3, 0, 0, 1041, 0, 0, 2, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #348 = JUMPTABLE_TBH |
| 10044 | { 347, 3, 0, 0, 1041, 0, 0, 2, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #347 = JUMPTABLE_TBB |
| 10045 | { 346, 3, 0, 0, 1041, 0, 0, 2, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #346 = JUMPTABLE_INSTS |
| 10046 | { 345, 3, 0, 0, 1041, 0, 0, 2, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #345 = JUMPTABLE_ADDRS |
| 10047 | { 344, 0, 0, 0, 1039, 0, 0, 1, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #344 = Int_eh_sjlj_setup_dispatch |
| 10048 | { 343, 2, 0, 20, 1039, 0, 15, 152, ARMImpOpBase + 39, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #343 = Int_eh_sjlj_setjmp_nofp |
| 10049 | { 342, 2, 0, 20, 1039, 0, 31, 152, ARMImpOpBase + 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #342 = Int_eh_sjlj_setjmp |
| 10050 | { 341, 2, 0, 16, 1039, 0, 3, 152, ARMImpOpBase + 5, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #341 = Int_eh_sjlj_longjmp |
| 10051 | { 340, 0, 0, 0, 1039, 0, 0, 1, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #340 = Int_eh_sjlj_dispatchsetup |
| 10052 | { 339, 2, 0, 4, 457, 0, 0, 13, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #339 = ITasm |
| 10053 | { 338, 4, 0, 0, 1061, 0, 1, 230, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #338 = COPY_STRUCT_BYVAL_I32 |
| 10054 | { 337, 3, 0, 0, 843, 0, 0, 2, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // Inst #337 = CONSTPOOL_ENTRY |
| 10055 | { 336, 5, 2, 0, 1040, 0, 0, 220, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #336 = CMP_SWAP_8 |
| 10056 | { 335, 5, 2, 0, 1040, 0, 0, 225, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #335 = CMP_SWAP_64 |
| 10057 | { 334, 5, 2, 0, 1040, 0, 0, 220, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #334 = CMP_SWAP_32 |
| 10058 | { 333, 5, 2, 0, 1040, 0, 0, 220, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #333 = CMP_SWAP_16 |
| 10059 | { 332, 1, 0, 8, 853, 1, 1, 207, ARMImpOpBase + 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call), 0x0ULL }, // Inst #332 = BX_CALL |
| 10060 | { 331, 2, 0, 4, 862, 0, 0, 218, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // Inst #331 = BR_JTr |
| 10061 | { 330, 4, 0, 4, 864, 0, 0, 214, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // Inst #330 = BR_JTm_rs |
| 10062 | { 329, 3, 0, 4, 864, 0, 0, 211, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // Inst #329 = BR_JTm_i12 |
| 10063 | { 328, 3, 0, 4, 861, 0, 0, 208, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // Inst #328 = BR_JTadd |
| 10064 | { 327, 1, 0, 8, 869, 1, 1, 207, ARMImpOpBase + 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call), 0x0ULL }, // Inst #327 = BMOVPCRX_CALL |
| 10065 | { 326, 1, 0, 8, 869, 1, 1, 193, ARMImpOpBase + 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call), 0x0ULL }, // Inst #326 = BMOVPCB_CALL |
| 10066 | { 325, 2, 0, 4, 6, 1, 1, 205, ARMImpOpBase + 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #325 = BL_PUSHLR |
| 10067 | { 324, 1, 0, 4, 859, 1, 1, 204, ARMImpOpBase + 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call), 0x0ULL }, // Inst #324 = BLX_pred_noip |
| 10068 | { 323, 1, 0, 4, 859, 1, 1, 204, ARMImpOpBase + 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call), 0x0ULL }, // Inst #323 = BLX_noip |
| 10069 | { 322, 6, 0, 0, 860, 0, 1, 198, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #322 = BCCi64 |
| 10070 | { 321, 4, 0, 0, 860, 0, 1, 194, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #321 = BCCZi64 |
| 10071 | { 320, 1, 0, 4, 853, 0, 0, 193, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #320 = B |
| 10072 | { 319, 2, 1, 0, 5, 0, 1, 152, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x2000ULL }, // Inst #319 = ASRs1 |
| 10073 | { 318, 6, 0, 4, 714, 0, 0, 187, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #318 = ASRr |
| 10074 | { 317, 6, 0, 4, 713, 0, 0, 181, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #317 = ASRi |
| 10075 | { 316, 4, 0, 0, 1039, 1, 1, 177, ARMImpOpBase + 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #316 = ADJCALLSTACKUP |
| 10076 | { 315, 4, 0, 0, 1039, 1, 1, 177, ARMImpOpBase + 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #315 = ADJCALLSTACKDOWN |
| 10077 | { 314, 7, 1, 4, 707, 0, 1, 170, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL }, // Inst #314 = ADDSrsr |
| 10078 | { 313, 6, 1, 4, 702, 0, 1, 164, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL }, // Inst #313 = ADDSrsi |
| 10079 | { 312, 5, 1, 4, 699, 0, 1, 159, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL }, // Inst #312 = ADDSrr |
| 10080 | { 311, 5, 1, 4, 692, 0, 1, 154, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL }, // Inst #311 = ADDSri |
| 10081 | { 310, 2, 1, 8, 679, 0, 1, 152, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #310 = ABS |
| 10082 | { 309, 4, 1, 0, 0, 0, 0, 148, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #309 = G_UBFX |
| 10083 | { 308, 4, 1, 0, 0, 0, 0, 148, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #308 = G_SBFX |
| 10084 | { 307, 2, 1, 0, 0, 0, 0, 61, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #307 = G_VECREDUCE_UMIN |
| 10085 | { 306, 2, 1, 0, 0, 0, 0, 61, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #306 = G_VECREDUCE_UMAX |
| 10086 | { 305, 2, 1, 0, 0, 0, 0, 61, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #305 = G_VECREDUCE_SMIN |
| 10087 | { 304, 2, 1, 0, 0, 0, 0, 61, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #304 = G_VECREDUCE_SMAX |
| 10088 | { 303, 2, 1, 0, 0, 0, 0, 61, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #303 = G_VECREDUCE_XOR |
| 10089 | { 302, 2, 1, 0, 0, 0, 0, 61, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #302 = G_VECREDUCE_OR |
| 10090 | { 301, 2, 1, 0, 0, 0, 0, 61, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #301 = G_VECREDUCE_AND |
| 10091 | { 300, 2, 1, 0, 0, 0, 0, 61, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #300 = G_VECREDUCE_MUL |
| 10092 | { 299, 2, 1, 0, 0, 0, 0, 61, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #299 = G_VECREDUCE_ADD |
| 10093 | { 298, 2, 1, 0, 0, 0, 0, 61, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #298 = G_VECREDUCE_FMINIMUM |
| 10094 | { 297, 2, 1, 0, 0, 0, 0, 61, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #297 = G_VECREDUCE_FMAXIMUM |
| 10095 | { 296, 2, 1, 0, 0, 0, 0, 61, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #296 = G_VECREDUCE_FMIN |
| 10096 | { 295, 2, 1, 0, 0, 0, 0, 61, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #295 = G_VECREDUCE_FMAX |
| 10097 | { 294, 2, 1, 0, 0, 0, 0, 61, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #294 = G_VECREDUCE_FMUL |
| 10098 | { 293, 2, 1, 0, 0, 0, 0, 61, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #293 = G_VECREDUCE_FADD |
| 10099 | { 292, 3, 1, 0, 0, 0, 0, 131, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #292 = G_VECREDUCE_SEQ_FMUL |
| 10100 | { 291, 3, 1, 0, 0, 0, 0, 131, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #291 = G_VECREDUCE_SEQ_FADD |
| 10101 | { 290, 1, 0, 0, 0, 0, 0, 1, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #290 = G_UBSANTRAP |
| 10102 | { 289, 0, 0, 0, 0, 0, 0, 1, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #289 = G_DEBUGTRAP |
| 10103 | { 288, 0, 0, 0, 0, 0, 0, 1, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #288 = G_TRAP |
| 10104 | { 287, 3, 0, 0, 0, 0, 0, 58, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #287 = G_BZERO |
| 10105 | { 286, 4, 0, 0, 0, 0, 0, 144, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #286 = G_MEMSET |
| 10106 | { 285, 4, 0, 0, 0, 0, 0, 144, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #285 = G_MEMMOVE |
| 10107 | { 284, 3, 0, 0, 0, 0, 0, 131, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #284 = G_MEMCPY_INLINE |
| 10108 | { 283, 4, 0, 0, 0, 0, 0, 144, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #283 = G_MEMCPY |
| 10109 | { 282, 2, 0, 0, 0, 0, 0, 142, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #282 = G_WRITE_REGISTER |
| 10110 | { 281, 2, 1, 0, 0, 0, 0, 51, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #281 = G_READ_REGISTER |
| 10111 | { 280, 3, 1, 0, 0, 0, 0, 101, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #280 = G_STRICT_FLDEXP |
| 10112 | { 279, 2, 1, 0, 0, 0, 0, 67, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #279 = G_STRICT_FSQRT |
| 10113 | { 278, 4, 1, 0, 0, 0, 0, 46, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #278 = G_STRICT_FMA |
| 10114 | { 277, 3, 1, 0, 0, 0, 0, 43, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #277 = G_STRICT_FREM |
| 10115 | { 276, 3, 1, 0, 0, 0, 0, 43, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #276 = G_STRICT_FDIV |
| 10116 | { 275, 3, 1, 0, 0, 0, 0, 43, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #275 = G_STRICT_FMUL |
| 10117 | { 274, 3, 1, 0, 0, 0, 0, 43, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #274 = G_STRICT_FSUB |
| 10118 | { 273, 3, 1, 0, 0, 0, 0, 43, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #273 = G_STRICT_FADD |
| 10119 | { 272, 1, 0, 0, 0, 0, 0, 50, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #272 = G_STACKRESTORE |
| 10120 | { 271, 1, 1, 0, 0, 0, 0, 50, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #271 = G_STACKSAVE |
| 10121 | { 270, 3, 1, 0, 0, 0, 0, 69, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #270 = G_DYN_STACKALLOC |
| 10122 | { 269, 2, 1, 0, 0, 0, 0, 51, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #269 = G_JUMP_TABLE |
| 10123 | { 268, 2, 1, 0, 0, 0, 0, 51, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #268 = G_BLOCK_ADDR |
| 10124 | { 267, 2, 1, 0, 0, 0, 0, 61, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #267 = G_ADDRSPACE_CAST |
| 10125 | { 266, 2, 1, 0, 0, 0, 0, 67, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #266 = G_FNEARBYINT |
| 10126 | { 265, 2, 1, 0, 0, 0, 0, 67, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #265 = G_FRINT |
| 10127 | { 264, 2, 1, 0, 0, 0, 0, 67, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #264 = G_FFLOOR |
| 10128 | { 263, 2, 1, 0, 0, 0, 0, 67, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #263 = G_FSQRT |
| 10129 | { 262, 2, 1, 0, 0, 0, 0, 67, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #262 = G_FTANH |
| 10130 | { 261, 2, 1, 0, 0, 0, 0, 67, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #261 = G_FSINH |
| 10131 | { 260, 2, 1, 0, 0, 0, 0, 67, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #260 = G_FCOSH |
| 10132 | { 259, 3, 1, 0, 0, 0, 0, 43, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #259 = G_FATAN2 |
| 10133 | { 258, 2, 1, 0, 0, 0, 0, 67, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #258 = G_FATAN |
| 10134 | { 257, 2, 1, 0, 0, 0, 0, 67, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #257 = G_FASIN |
| 10135 | { 256, 2, 1, 0, 0, 0, 0, 67, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #256 = G_FACOS |
| 10136 | { 255, 2, 1, 0, 0, 0, 0, 67, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #255 = G_FTAN |
| 10137 | { 254, 3, 2, 0, 0, 0, 0, 43, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #254 = G_FSINCOS |
| 10138 | { 253, 2, 1, 0, 0, 0, 0, 67, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #253 = G_FSIN |
| 10139 | { 252, 2, 1, 0, 0, 0, 0, 67, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #252 = G_FCOS |
| 10140 | { 251, 2, 1, 0, 0, 0, 0, 67, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #251 = G_FCEIL |
| 10141 | { 250, 2, 1, 0, 0, 0, 0, 67, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #250 = G_BITREVERSE |
| 10142 | { 249, 2, 1, 0, 0, 0, 0, 67, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #249 = G_BSWAP |
| 10143 | { 248, 2, 1, 0, 0, 0, 0, 61, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #248 = G_CTPOP |
| 10144 | { 247, 2, 1, 0, 0, 0, 0, 61, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #247 = G_CTLZ_ZERO_UNDEF |
| 10145 | { 246, 2, 1, 0, 0, 0, 0, 61, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #246 = G_CTLZ |
| 10146 | { 245, 2, 1, 0, 0, 0, 0, 61, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #245 = G_CTTZ_ZERO_UNDEF |
| 10147 | { 244, 2, 1, 0, 0, 0, 0, 61, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #244 = G_CTTZ |
| 10148 | { 243, 4, 1, 0, 0, 0, 0, 138, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #243 = G_VECTOR_COMPRESS |
| 10149 | { 242, 2, 1, 0, 0, 0, 0, 51, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #242 = G_STEP_VECTOR |
| 10150 | { 241, 2, 1, 0, 0, 0, 0, 61, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #241 = G_SPLAT_VECTOR |
| 10151 | { 240, 4, 1, 0, 0, 0, 0, 134, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #240 = G_SHUFFLE_VECTOR |
| 10152 | { 239, 3, 1, 0, 0, 0, 0, 131, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #239 = G_EXTRACT_VECTOR_ELT |
| 10153 | { 238, 4, 1, 0, 0, 0, 0, 127, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #238 = G_INSERT_VECTOR_ELT |
| 10154 | { 237, 3, 1, 0, 0, 0, 0, 58, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #237 = G_EXTRACT_SUBVECTOR |
| 10155 | { 236, 4, 1, 0, 0, 0, 0, 63, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #236 = G_INSERT_SUBVECTOR |
| 10156 | { 235, 2, 1, 0, 0, 0, 0, 51, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #235 = G_VSCALE |
| 10157 | { 234, 3, 0, 0, 0, 0, 0, 124, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #234 = G_BRJT |
| 10158 | { 233, 1, 0, 0, 0, 0, 0, 0, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #233 = G_BR |
| 10159 | { 232, 2, 1, 0, 0, 0, 0, 61, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #232 = G_LLROUND |
| 10160 | { 231, 2, 1, 0, 0, 0, 0, 61, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #231 = G_LROUND |
| 10161 | { 230, 2, 1, 0, 0, 0, 0, 67, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #230 = G_ABS |
| 10162 | { 229, 3, 1, 0, 0, 0, 0, 43, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #229 = G_UMAX |
| 10163 | { 228, 3, 1, 0, 0, 0, 0, 43, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #228 = G_UMIN |
| 10164 | { 227, 3, 1, 0, 0, 0, 0, 43, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #227 = G_SMAX |
| 10165 | { 226, 3, 1, 0, 0, 0, 0, 43, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #226 = G_SMIN |
| 10166 | { 225, 3, 1, 0, 0, 0, 0, 101, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #225 = G_PTRMASK |
| 10167 | { 224, 3, 1, 0, 0, 0, 0, 101, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #224 = G_PTR_ADD |
| 10168 | { 223, 0, 0, 0, 0, 0, 0, 1, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #223 = G_RESET_FPMODE |
| 10169 | { 222, 1, 0, 0, 0, 0, 0, 50, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #222 = G_SET_FPMODE |
| 10170 | { 221, 1, 1, 0, 0, 0, 0, 50, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #221 = G_GET_FPMODE |
| 10171 | { 220, 0, 0, 0, 0, 0, 0, 1, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #220 = G_RESET_FPENV |
| 10172 | { 219, 1, 0, 0, 0, 0, 0, 50, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #219 = G_SET_FPENV |
| 10173 | { 218, 1, 1, 0, 0, 0, 0, 50, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #218 = G_GET_FPENV |
| 10174 | { 217, 3, 1, 0, 0, 0, 0, 43, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #217 = G_FMAXIMUMNUM |
| 10175 | { 216, 3, 1, 0, 0, 0, 0, 43, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #216 = G_FMINIMUMNUM |
| 10176 | { 215, 3, 1, 0, 0, 0, 0, 43, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #215 = G_FMAXIMUM |
| 10177 | { 214, 3, 1, 0, 0, 0, 0, 43, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #214 = G_FMINIMUM |
| 10178 | { 213, 3, 1, 0, 0, 0, 0, 43, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #213 = G_FMAXNUM_IEEE |
| 10179 | { 212, 3, 1, 0, 0, 0, 0, 43, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #212 = G_FMINNUM_IEEE |
| 10180 | { 211, 3, 1, 0, 0, 0, 0, 43, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #211 = G_FMAXNUM |
| 10181 | { 210, 3, 1, 0, 0, 0, 0, 43, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #210 = G_FMINNUM |
| 10182 | { 209, 2, 1, 0, 0, 0, 0, 67, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #209 = G_FCANONICALIZE |
| 10183 | { 208, 3, 1, 0, 0, 0, 0, 98, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #208 = G_IS_FPCLASS |
| 10184 | { 207, 3, 1, 0, 0, 0, 0, 101, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #207 = G_FCOPYSIGN |
| 10185 | { 206, 2, 1, 0, 0, 0, 0, 67, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #206 = G_FABS |
| 10186 | { 205, 2, 1, 0, 0, 0, 0, 61, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #205 = G_FPTOUI_SAT |
| 10187 | { 204, 2, 1, 0, 0, 0, 0, 61, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #204 = G_FPTOSI_SAT |
| 10188 | { 203, 2, 1, 0, 0, 0, 0, 61, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #203 = G_UITOFP |
| 10189 | { 202, 2, 1, 0, 0, 0, 0, 61, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #202 = G_SITOFP |
| 10190 | { 201, 2, 1, 0, 0, 0, 0, 61, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #201 = G_FPTOUI |
| 10191 | { 200, 2, 1, 0, 0, 0, 0, 61, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #200 = G_FPTOSI |
| 10192 | { 199, 2, 1, 0, 0, 0, 0, 61, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #199 = G_FPTRUNC |
| 10193 | { 198, 2, 1, 0, 0, 0, 0, 61, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #198 = G_FPEXT |
| 10194 | { 197, 2, 1, 0, 0, 0, 0, 67, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #197 = G_FNEG |
| 10195 | { 196, 3, 2, 0, 0, 0, 0, 91, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #196 = G_FFREXP |
| 10196 | { 195, 3, 1, 0, 0, 0, 0, 101, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #195 = G_FLDEXP |
| 10197 | { 194, 2, 1, 0, 0, 0, 0, 67, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #194 = G_FLOG10 |
| 10198 | { 193, 2, 1, 0, 0, 0, 0, 67, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #193 = G_FLOG2 |
| 10199 | { 192, 2, 1, 0, 0, 0, 0, 67, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #192 = G_FLOG |
| 10200 | { 191, 2, 1, 0, 0, 0, 0, 67, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #191 = G_FEXP10 |
| 10201 | { 190, 2, 1, 0, 0, 0, 0, 67, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #190 = G_FEXP2 |
| 10202 | { 189, 2, 1, 0, 0, 0, 0, 67, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #189 = G_FEXP |
| 10203 | { 188, 3, 1, 0, 0, 0, 0, 101, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #188 = G_FPOWI |
| 10204 | { 187, 3, 1, 0, 0, 0, 0, 43, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #187 = G_FPOW |
| 10205 | { 186, 3, 1, 0, 0, 0, 0, 43, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #186 = G_FREM |
| 10206 | { 185, 3, 1, 0, 0, 0, 0, 43, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #185 = G_FDIV |
| 10207 | { 184, 4, 1, 0, 0, 0, 0, 46, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #184 = G_FMAD |
| 10208 | { 183, 4, 1, 0, 0, 0, 0, 46, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #183 = G_FMA |
| 10209 | { 182, 3, 1, 0, 0, 0, 0, 43, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #182 = G_FMUL |
| 10210 | { 181, 3, 1, 0, 0, 0, 0, 43, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #181 = G_FSUB |
| 10211 | { 180, 3, 1, 0, 0, 0, 0, 43, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #180 = G_FADD |
| 10212 | { 179, 4, 1, 0, 0, 0, 0, 120, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #179 = G_UDIVFIXSAT |
| 10213 | { 178, 4, 1, 0, 0, 0, 0, 120, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #178 = G_SDIVFIXSAT |
| 10214 | { 177, 4, 1, 0, 0, 0, 0, 120, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #177 = G_UDIVFIX |
| 10215 | { 176, 4, 1, 0, 0, 0, 0, 120, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #176 = G_SDIVFIX |
| 10216 | { 175, 4, 1, 0, 0, 0, 0, 120, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #175 = G_UMULFIXSAT |
| 10217 | { 174, 4, 1, 0, 0, 0, 0, 120, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #174 = G_SMULFIXSAT |
| 10218 | { 173, 4, 1, 0, 0, 0, 0, 120, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #173 = G_UMULFIX |
| 10219 | { 172, 4, 1, 0, 0, 0, 0, 120, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #172 = G_SMULFIX |
| 10220 | { 171, 3, 1, 0, 0, 0, 0, 101, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #171 = G_SSHLSAT |
| 10221 | { 170, 3, 1, 0, 0, 0, 0, 101, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #170 = G_USHLSAT |
| 10222 | { 169, 3, 1, 0, 0, 0, 0, 43, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #169 = G_SSUBSAT |
| 10223 | { 168, 3, 1, 0, 0, 0, 0, 43, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #168 = G_USUBSAT |
| 10224 | { 167, 3, 1, 0, 0, 0, 0, 43, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #167 = G_SADDSAT |
| 10225 | { 166, 3, 1, 0, 0, 0, 0, 43, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #166 = G_UADDSAT |
| 10226 | { 165, 3, 1, 0, 0, 0, 0, 43, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #165 = G_SMULH |
| 10227 | { 164, 3, 1, 0, 0, 0, 0, 43, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #164 = G_UMULH |
| 10228 | { 163, 4, 2, 0, 0, 0, 0, 87, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #163 = G_SMULO |
| 10229 | { 162, 4, 2, 0, 0, 0, 0, 87, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #162 = G_UMULO |
| 10230 | { 161, 5, 2, 0, 0, 0, 0, 115, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #161 = G_SSUBE |
| 10231 | { 160, 4, 2, 0, 0, 0, 0, 87, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #160 = G_SSUBO |
| 10232 | { 159, 5, 2, 0, 0, 0, 0, 115, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #159 = G_SADDE |
| 10233 | { 158, 4, 2, 0, 0, 0, 0, 87, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #158 = G_SADDO |
| 10234 | { 157, 5, 2, 0, 0, 0, 0, 115, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #157 = G_USUBE |
| 10235 | { 156, 4, 2, 0, 0, 0, 0, 87, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #156 = G_USUBO |
| 10236 | { 155, 5, 2, 0, 0, 0, 0, 115, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #155 = G_UADDE |
| 10237 | { 154, 4, 2, 0, 0, 0, 0, 87, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #154 = G_UADDO |
| 10238 | { 153, 4, 1, 0, 0, 0, 0, 87, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #153 = G_SELECT |
| 10239 | { 152, 3, 1, 0, 0, 0, 0, 112, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #152 = G_UCMP |
| 10240 | { 151, 3, 1, 0, 0, 0, 0, 112, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #151 = G_SCMP |
| 10241 | { 150, 4, 1, 0, 0, 0, 0, 108, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #150 = G_FCMP |
| 10242 | { 149, 4, 1, 0, 0, 0, 0, 108, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #149 = G_ICMP |
| 10243 | { 148, 3, 1, 0, 0, 0, 0, 101, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #148 = G_ROTL |
| 10244 | { 147, 3, 1, 0, 0, 0, 0, 101, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #147 = G_ROTR |
| 10245 | { 146, 4, 1, 0, 0, 0, 0, 104, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #146 = G_FSHR |
| 10246 | { 145, 4, 1, 0, 0, 0, 0, 104, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #145 = G_FSHL |
| 10247 | { 144, 3, 1, 0, 0, 0, 0, 101, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #144 = G_ASHR |
| 10248 | { 143, 3, 1, 0, 0, 0, 0, 101, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #143 = G_LSHR |
| 10249 | { 142, 3, 1, 0, 0, 0, 0, 101, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #142 = G_SHL |
| 10250 | { 141, 2, 1, 0, 0, 0, 0, 61, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #141 = G_ZEXT |
| 10251 | { 140, 3, 1, 0, 0, 0, 0, 40, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #140 = G_SEXT_INREG |
| 10252 | { 139, 2, 1, 0, 0, 0, 0, 61, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #139 = G_SEXT |
| 10253 | { 138, 3, 1, 0, 0, 0, 0, 98, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #138 = G_VAARG |
| 10254 | { 137, 1, 0, 0, 0, 0, 0, 50, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #137 = G_VASTART |
| 10255 | { 136, 2, 1, 0, 0, 0, 0, 51, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #136 = G_FCONSTANT |
| 10256 | { 135, 2, 1, 0, 0, 0, 0, 51, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #135 = G_CONSTANT |
| 10257 | { 134, 2, 1, 0, 0, 0, 0, 61, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #134 = G_TRUNC |
| 10258 | { 133, 2, 1, 0, 0, 0, 0, 61, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #133 = G_ANYEXT |
| 10259 | { 132, 1, 0, 0, 0, 0, 0, 0, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #132 = G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS |
| 10260 | { 131, 1, 0, 0, 0, 0, 0, 0, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #131 = G_INTRINSIC_CONVERGENT |
| 10261 | { 130, 1, 0, 0, 0, 0, 0, 0, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #130 = G_INTRINSIC_W_SIDE_EFFECTS |
| 10262 | { 129, 1, 0, 0, 0, 0, 0, 0, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #129 = G_INTRINSIC |
| 10263 | { 128, 0, 0, 0, 0, 0, 0, 1, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #128 = G_INVOKE_REGION_START |
| 10264 | { 127, 1, 0, 0, 0, 0, 0, 50, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #127 = G_BRINDIRECT |
| 10265 | { 126, 2, 0, 0, 0, 0, 0, 51, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #126 = G_BRCOND |
| 10266 | { 125, 4, 0, 0, 0, 0, 0, 94, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #125 = G_PREFETCH |
| 10267 | { 124, 2, 0, 0, 0, 0, 0, 21, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #124 = G_FENCE |
| 10268 | { 123, 3, 1, 0, 0, 0, 0, 91, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #123 = G_ATOMICRMW_USUB_SAT |
| 10269 | { 122, 3, 1, 0, 0, 0, 0, 91, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #122 = G_ATOMICRMW_USUB_COND |
| 10270 | { 121, 3, 1, 0, 0, 0, 0, 91, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #121 = G_ATOMICRMW_UDEC_WRAP |
| 10271 | { 120, 3, 1, 0, 0, 0, 0, 91, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #120 = G_ATOMICRMW_UINC_WRAP |
| 10272 | { 119, 3, 1, 0, 0, 0, 0, 91, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #119 = G_ATOMICRMW_FMINIMUM |
| 10273 | { 118, 3, 1, 0, 0, 0, 0, 91, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #118 = G_ATOMICRMW_FMAXIMUM |
| 10274 | { 117, 3, 1, 0, 0, 0, 0, 91, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #117 = G_ATOMICRMW_FMIN |
| 10275 | { 116, 3, 1, 0, 0, 0, 0, 91, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #116 = G_ATOMICRMW_FMAX |
| 10276 | { 115, 3, 1, 0, 0, 0, 0, 91, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #115 = G_ATOMICRMW_FSUB |
| 10277 | { 114, 3, 1, 0, 0, 0, 0, 91, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #114 = G_ATOMICRMW_FADD |
| 10278 | { 113, 3, 1, 0, 0, 0, 0, 91, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #113 = G_ATOMICRMW_UMIN |
| 10279 | { 112, 3, 1, 0, 0, 0, 0, 91, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #112 = G_ATOMICRMW_UMAX |
| 10280 | { 111, 3, 1, 0, 0, 0, 0, 91, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #111 = G_ATOMICRMW_MIN |
| 10281 | { 110, 3, 1, 0, 0, 0, 0, 91, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #110 = G_ATOMICRMW_MAX |
| 10282 | { 109, 3, 1, 0, 0, 0, 0, 91, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #109 = G_ATOMICRMW_XOR |
| 10283 | { 108, 3, 1, 0, 0, 0, 0, 91, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #108 = G_ATOMICRMW_OR |
| 10284 | { 107, 3, 1, 0, 0, 0, 0, 91, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #107 = G_ATOMICRMW_NAND |
| 10285 | { 106, 3, 1, 0, 0, 0, 0, 91, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #106 = G_ATOMICRMW_AND |
| 10286 | { 105, 3, 1, 0, 0, 0, 0, 91, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #105 = G_ATOMICRMW_SUB |
| 10287 | { 104, 3, 1, 0, 0, 0, 0, 91, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #104 = G_ATOMICRMW_ADD |
| 10288 | { 103, 3, 1, 0, 0, 0, 0, 91, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #103 = G_ATOMICRMW_XCHG |
| 10289 | { 102, 4, 1, 0, 0, 0, 0, 87, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #102 = G_ATOMIC_CMPXCHG |
| 10290 | { 101, 5, 2, 0, 0, 0, 0, 82, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #101 = G_ATOMIC_CMPXCHG_WITH_SUCCESS |
| 10291 | { 100, 5, 1, 0, 0, 0, 0, 77, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #100 = G_INDEXED_STORE |
| 10292 | { 99, 2, 0, 0, 0, 0, 0, 61, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #99 = G_STORE |
| 10293 | { 98, 5, 2, 0, 0, 0, 0, 72, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #98 = G_INDEXED_ZEXTLOAD |
| 10294 | { 97, 5, 2, 0, 0, 0, 0, 72, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #97 = G_INDEXED_SEXTLOAD |
| 10295 | { 96, 5, 2, 0, 0, 0, 0, 72, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #96 = G_INDEXED_LOAD |
| 10296 | { 95, 2, 1, 0, 0, 0, 0, 61, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #95 = G_ZEXTLOAD |
| 10297 | { 94, 2, 1, 0, 0, 0, 0, 61, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #94 = G_SEXTLOAD |
| 10298 | { 93, 2, 1, 0, 0, 0, 0, 61, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #93 = G_LOAD |
| 10299 | { 92, 1, 1, 0, 0, 0, 0, 50, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #92 = G_READSTEADYCOUNTER |
| 10300 | { 91, 1, 1, 0, 0, 0, 0, 50, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #91 = G_READCYCLECOUNTER |
| 10301 | { 90, 2, 1, 0, 0, 0, 0, 67, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #90 = G_INTRINSIC_ROUNDEVEN |
| 10302 | { 89, 2, 1, 0, 0, 0, 0, 61, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #89 = G_INTRINSIC_LLRINT |
| 10303 | { 88, 2, 1, 0, 0, 0, 0, 61, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #88 = G_INTRINSIC_LRINT |
| 10304 | { 87, 2, 1, 0, 0, 0, 0, 67, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #87 = G_INTRINSIC_ROUND |
| 10305 | { 86, 2, 1, 0, 0, 0, 0, 67, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #86 = G_INTRINSIC_TRUNC |
| 10306 | { 85, 3, 1, 0, 0, 0, 0, 69, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #85 = G_INTRINSIC_FPTRUNC_ROUND |
| 10307 | { 84, 2, 1, 0, 0, 0, 0, 67, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #84 = G_CONSTANT_FOLD_BARRIER |
| 10308 | { 83, 2, 1, 0, 0, 0, 0, 67, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #83 = G_FREEZE |
| 10309 | { 82, 2, 1, 0, 0, 0, 0, 61, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #82 = G_BITCAST |
| 10310 | { 81, 2, 1, 0, 0, 0, 0, 61, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #81 = G_INTTOPTR |
| 10311 | { 80, 2, 1, 0, 0, 0, 0, 61, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #80 = G_PTRTOINT |
| 10312 | { 79, 2, 1, 0, 0, 0, 0, 61, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #79 = G_CONCAT_VECTORS |
| 10313 | { 78, 2, 1, 0, 0, 0, 0, 61, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #78 = G_BUILD_VECTOR_TRUNC |
| 10314 | { 77, 2, 1, 0, 0, 0, 0, 61, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #77 = G_BUILD_VECTOR |
| 10315 | { 76, 2, 1, 0, 0, 0, 0, 61, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #76 = G_MERGE_VALUES |
| 10316 | { 75, 4, 1, 0, 0, 0, 0, 63, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #75 = G_INSERT |
| 10317 | { 74, 2, 1, 0, 0, 0, 0, 61, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #74 = G_UNMERGE_VALUES |
| 10318 | { 73, 3, 1, 0, 0, 0, 0, 58, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #73 = G_EXTRACT |
| 10319 | { 72, 2, 1, 0, 0, 0, 0, 51, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #72 = G_CONSTANT_POOL |
| 10320 | { 71, 5, 1, 0, 0, 0, 0, 53, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #71 = G_PTRAUTH_GLOBAL_VALUE |
| 10321 | { 70, 2, 1, 0, 0, 0, 0, 51, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #70 = G_GLOBAL_VALUE |
| 10322 | { 69, 2, 1, 0, 0, 0, 0, 51, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #69 = G_FRAME_INDEX |
| 10323 | { 68, 1, 1, 0, 0, 0, 0, 50, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #68 = G_PHI |
| 10324 | { 67, 1, 1, 0, 0, 0, 0, 50, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #67 = G_IMPLICIT_DEF |
| 10325 | { 66, 3, 1, 0, 0, 0, 0, 43, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #66 = G_ABDU |
| 10326 | { 65, 3, 1, 0, 0, 0, 0, 43, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #65 = G_ABDS |
| 10327 | { 64, 3, 1, 0, 0, 0, 0, 43, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #64 = G_XOR |
| 10328 | { 63, 3, 1, 0, 0, 0, 0, 43, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #63 = G_OR |
| 10329 | { 62, 3, 1, 0, 0, 0, 0, 43, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #62 = G_AND |
| 10330 | { 61, 4, 2, 0, 0, 0, 0, 46, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #61 = G_UDIVREM |
| 10331 | { 60, 4, 2, 0, 0, 0, 0, 46, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #60 = G_SDIVREM |
| 10332 | { 59, 3, 1, 0, 0, 0, 0, 43, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #59 = G_UREM |
| 10333 | { 58, 3, 1, 0, 0, 0, 0, 43, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #58 = G_SREM |
| 10334 | { 57, 3, 1, 0, 0, 0, 0, 43, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #57 = G_UDIV |
| 10335 | { 56, 3, 1, 0, 0, 0, 0, 43, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #56 = G_SDIV |
| 10336 | { 55, 3, 1, 0, 0, 0, 0, 43, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #55 = G_MUL |
| 10337 | { 54, 3, 1, 0, 0, 0, 0, 43, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #54 = G_SUB |
| 10338 | { 53, 3, 1, 0, 0, 0, 0, 43, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #53 = G_ADD |
| 10339 | { 52, 3, 1, 0, 0, 0, 0, 40, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #52 = G_ASSERT_ALIGN |
| 10340 | { 51, 3, 1, 0, 0, 0, 0, 40, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #51 = G_ASSERT_ZEXT |
| 10341 | { 50, 3, 1, 0, 0, 0, 0, 40, ARMImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #50 = G_ASSERT_SEXT |
| 10342 | { 49, 1, 0, 0, 0, 0, 0, 0, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #49 = CONVERGENCECTRL_GLUE |
| 10343 | { 48, 2, 1, 0, 0, 0, 0, 13, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #48 = CONVERGENCECTRL_LOOP |
| 10344 | { 47, 1, 1, 0, 0, 0, 0, 0, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #47 = CONVERGENCECTRL_ANCHOR |
| 10345 | { 46, 1, 1, 0, 0, 0, 0, 0, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #46 = CONVERGENCECTRL_ENTRY |
| 10346 | { 45, 1, 0, 0, 0, 0, 0, 1, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // Inst #45 = JUMP_TABLE_DEBUG_INFO |
| 10347 | { 44, 0, 0, 0, 0, 0, 0, 1, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #44 = MEMBARRIER |
| 10348 | { 43, 0, 0, 0, 0, 0, 0, 1, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #43 = FAKE_USE |
| 10349 | { 42, 0, 0, 0, 0, 0, 0, 1, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #42 = ICALL_BRANCH_FUNNEL |
| 10350 | { 41, 3, 0, 0, 0, 0, 0, 37, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #41 = PATCHABLE_TYPED_EVENT_CALL |
| 10351 | { 40, 2, 0, 0, 0, 0, 0, 35, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #40 = PATCHABLE_EVENT_CALL |
| 10352 | { 39, 0, 0, 0, 0, 0, 0, 1, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #39 = PATCHABLE_TAIL_CALL |
| 10353 | { 38, 0, 0, 0, 0, 0, 0, 1, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #38 = PATCHABLE_FUNCTION_EXIT |
| 10354 | { 37, 0, 0, 0, 0, 0, 0, 1, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #37 = PATCHABLE_RET |
| 10355 | { 36, 0, 0, 0, 0, 0, 0, 1, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #36 = PATCHABLE_FUNCTION_ENTER |
| 10356 | { 35, 0, 0, 0, 0, 0, 0, 1, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #35 = PATCHABLE_OP |
| 10357 | { 34, 1, 1, 0, 0, 0, 0, 0, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #34 = FAULTING_OP |
| 10358 | { 33, 2, 0, 0, 0, 0, 0, 33, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #33 = LOCAL_ESCAPE |
| 10359 | { 32, 0, 0, 0, 0, 0, 0, 1, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #32 = STATEPOINT |
| 10360 | { 31, 3, 1, 0, 0, 0, 0, 30, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #31 = PREALLOCATED_ARG |
| 10361 | { 30, 1, 0, 0, 0, 0, 0, 1, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #30 = PREALLOCATED_SETUP |
| 10362 | { 29, 1, 1, 0, 0, 0, 0, 29, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL }, // Inst #29 = LOAD_STACK_GUARD |
| 10363 | { 28, 6, 1, 0, 0, 0, 0, 23, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #28 = PATCHPOINT |
| 10364 | { 27, 0, 0, 0, 0, 0, 0, 1, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #27 = FENTRY_CALL |
| 10365 | { 26, 2, 0, 0, 0, 0, 0, 21, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #26 = STACKMAP |
| 10366 | { 25, 2, 1, 0, 0, 0, 0, 19, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // Inst #25 = ARITH_FENCE |
| 10367 | { 24, 4, 0, 0, 0, 0, 0, 15, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #24 = PSEUDO_PROBE |
| 10368 | { 23, 1, 0, 0, 0, 0, 0, 1, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // Inst #23 = LIFETIME_END |
| 10369 | { 22, 1, 0, 0, 0, 0, 0, 1, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // Inst #22 = LIFETIME_START |
| 10370 | { 21, 0, 0, 0, 1220, 0, 0, 1, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #21 = BUNDLE |
| 10371 | { 20, 2, 1, 0, 680, 0, 0, 13, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #20 = COPY |
| 10372 | { 19, 2, 1, 0, 0, 0, 0, 13, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #19 = REG_SEQUENCE |
| 10373 | { 18, 1, 0, 0, 0, 0, 0, 0, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // Inst #18 = DBG_LABEL |
| 10374 | { 17, 0, 0, 0, 0, 0, 0, 1, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #17 = DBG_PHI |
| 10375 | { 16, 0, 0, 0, 0, 0, 0, 1, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #16 = DBG_INSTR_REF |
| 10376 | { 15, 0, 0, 0, 0, 0, 0, 1, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #15 = DBG_VALUE_LIST |
| 10377 | { 14, 0, 0, 0, 0, 0, 0, 1, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #14 = DBG_VALUE |
| 10378 | { 13, 3, 1, 0, 1060, 0, 0, 2, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #13 = COPY_TO_REGCLASS |
| 10379 | { 12, 4, 1, 0, 0, 0, 0, 9, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #12 = SUBREG_TO_REG |
| 10380 | { 11, 1, 1, 0, 0, 0, 0, 0, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #11 = INIT_UNDEF |
| 10381 | { 10, 1, 1, 0, 0, 0, 0, 0, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #10 = IMPLICIT_DEF |
| 10382 | { 9, 4, 1, 0, 0, 0, 0, 5, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #9 = INSERT_SUBREG |
| 10383 | { 8, 3, 1, 0, 0, 0, 0, 2, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #8 = EXTRACT_SUBREG |
| 10384 | { 7, 0, 0, 0, 0, 0, 0, 1, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #7 = KILL |
| 10385 | { 6, 1, 0, 0, 0, 0, 0, 1, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // Inst #6 = ANNOTATION_LABEL |
| 10386 | { 5, 1, 0, 0, 0, 0, 0, 1, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // Inst #5 = GC_LABEL |
| 10387 | { 4, 1, 0, 0, 0, 0, 0, 1, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // Inst #4 = EH_LABEL |
| 10388 | { 3, 1, 0, 0, 0, 0, 0, 1, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // Inst #3 = CFI_INSTRUCTION |
| 10389 | { 2, 0, 0, 0, 0, 0, 0, 1, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2 = INLINEASM_BR |
| 10390 | { 1, 0, 0, 0, 0, 0, 0, 1, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #1 = INLINEASM |
| 10391 | { 0, 1, 1, 0, 0, 0, 0, 0, ARMImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #0 = PHI |
| 10392 | }, { |
| 10393 | /* 0 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10394 | /* 1 */ |
| 10395 | /* 1 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 10396 | /* 2 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 10397 | /* 5 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 10398 | /* 9 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 10399 | /* 13 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10400 | /* 15 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 10401 | /* 19 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, |
| 10402 | /* 21 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 10403 | /* 23 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 10404 | /* 29 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10405 | /* 30 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 10406 | /* 33 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 10407 | /* 35 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10408 | /* 37 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10409 | /* 40 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, |
| 10410 | /* 43 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, |
| 10411 | /* 46 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, |
| 10412 | /* 50 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, |
| 10413 | /* 51 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10414 | /* 53 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 10415 | /* 58 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, |
| 10416 | /* 61 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, |
| 10417 | /* 63 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, |
| 10418 | /* 67 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, |
| 10419 | /* 69 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 10420 | /* 72 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10421 | /* 77 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10422 | /* 82 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, |
| 10423 | /* 87 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, |
| 10424 | /* 91 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, |
| 10425 | /* 94 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 10426 | /* 98 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10427 | /* 101 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, |
| 10428 | /* 104 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, |
| 10429 | /* 108 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, |
| 10430 | /* 112 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, |
| 10431 | /* 115 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, |
| 10432 | /* 120 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, |
| 10433 | /* 124 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, |
| 10434 | /* 127 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, |
| 10435 | /* 131 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, |
| 10436 | /* 134 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10437 | /* 138 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, |
| 10438 | /* 142 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, |
| 10439 | /* 144 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, |
| 10440 | /* 148 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, |
| 10441 | /* 152 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10442 | /* 154 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10443 | /* 159 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10444 | /* 164 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10445 | /* 170 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10446 | /* 177 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10447 | /* 181 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10448 | /* 187 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10449 | /* 193 */ { -1, 0, MCOI::OPERAND_PCREL, 0 }, |
| 10450 | /* 194 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, |
| 10451 | /* 198 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, |
| 10452 | /* 204 */ { ARM::GPRnoipRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10453 | /* 205 */ { ARM::GPRlrRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, |
| 10454 | /* 207 */ { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10455 | /* 208 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 10456 | /* 211 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 10457 | /* 214 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 10458 | /* 218 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 10459 | /* 220 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10460 | /* 225 */ { ARM::GPRPairRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::GPRPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRPairRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { ARM::GPRPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10461 | /* 230 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 10462 | /* 234 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10463 | /* 239 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10464 | /* 243 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10465 | /* 247 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10466 | /* 251 */ { ARM::GPRPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, |
| 10467 | /* 255 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 10468 | /* 260 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10469 | /* 267 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10470 | /* 272 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10471 | /* 277 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10472 | /* 282 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10473 | /* 288 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10474 | /* 295 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10475 | /* 296 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10476 | /* 300 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10477 | /* 303 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10478 | /* 305 */ { ARM::MQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10479 | /* 307 */ { ARM::MQQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10480 | /* 309 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10481 | /* 315 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10482 | /* 318 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10483 | /* 321 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10484 | /* 326 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10485 | /* 331 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10486 | /* 340 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10487 | /* 347 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10488 | /* 350 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10489 | /* 357 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10490 | /* 364 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10491 | /* 367 */ { ARM::tcGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10492 | /* 368 */ { ARM::tcGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 10493 | /* 370 */ { ARM::tcGPRnotr12RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 10494 | /* 372 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10495 | /* 378 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10496 | /* 385 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10497 | /* 390 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10498 | /* 396 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10499 | /* 397 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10500 | /* 402 */ { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10501 | /* 407 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10502 | /* 408 */ { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10503 | /* 413 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10504 | /* 415 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10505 | /* 420 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10506 | /* 425 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10507 | /* 431 */ { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, |
| 10508 | /* 434 */ { ARM::GPRlrRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10509 | /* 436 */ { ARM::GPRlrRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10510 | /* 439 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10511 | /* 443 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 10512 | /* 445 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10513 | /* 448 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10514 | /* 452 */ { ARM::GPRlrRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRlrRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10515 | /* 455 */ { ARM::GPRlrRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRlrRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, |
| 10516 | /* 458 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10517 | /* 464 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10518 | /* 469 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10519 | /* 474 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10520 | /* 479 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10521 | /* 484 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10522 | /* 490 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10523 | /* 494 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10524 | /* 499 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10525 | /* 505 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10526 | /* 511 */ { ARM::GPRlrRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, |
| 10527 | /* 514 */ { ARM::GPRlrRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, |
| 10528 | /* 518 */ { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10529 | /* 521 */ { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10530 | /* 524 */ { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 10531 | /* 527 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10532 | /* 528 */ { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnoipRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10533 | /* 531 */ { ARM::GPRlrRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, |
| 10534 | /* 535 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10535 | /* 538 */ { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 10536 | /* 540 */ { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10537 | /* 542 */ { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10538 | /* 545 */ { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10539 | /* 548 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10540 | /* 553 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10541 | /* 558 */ { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10542 | /* 563 */ { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10543 | /* 567 */ { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10544 | /* 572 */ { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10545 | /* 575 */ { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10546 | /* 579 */ { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10547 | /* 584 */ { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10548 | /* 587 */ { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10549 | /* 589 */ { ARM::tGPRwithpcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 10550 | /* 593 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10551 | /* 599 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10552 | /* 606 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10553 | /* 614 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10554 | /* 622 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10555 | /* 625 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10556 | /* 627 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10557 | /* 632 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10558 | /* 637 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10559 | /* 641 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10560 | /* 645 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10561 | /* 649 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10562 | /* 655 */ { ARM::GPRwithAPSR_NZCVnospRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10563 | /* 658 */ { ARM::GPRwithAPSR_NZCVnospRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRwithAPSR_NZCVnospRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10564 | /* 664 */ { ARM::GPRPairnospRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10565 | /* 667 */ { ARM::GPRPairnospRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRPairnospRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10566 | /* 673 */ { ARM::GPRwithAPSR_NZCVnospRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRwithAPSR_NZCVnospRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10567 | /* 677 */ { ARM::GPRwithAPSR_NZCVnospRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRwithAPSR_NZCVnospRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::GPRwithAPSR_NZCVnospRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10568 | /* 684 */ { ARM::GPRPairnospRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRwithAPSR_NZCVnospRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10569 | /* 688 */ { ARM::GPRPairnospRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRPairnospRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::GPRwithAPSR_NZCVnospRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10570 | /* 695 */ { ARM::GPRwithAPSR_NZCVnospRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRwithAPSR_NZCVnospRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRwithAPSR_NZCVnospRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10571 | /* 700 */ { ARM::GPRwithAPSR_NZCVnospRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRwithAPSR_NZCVnospRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::GPRwithAPSR_NZCVnospRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRwithAPSR_NZCVnospRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10572 | /* 708 */ { ARM::GPRPairnospRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRwithAPSR_NZCVnospRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRwithAPSR_NZCVnospRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10573 | /* 713 */ { ARM::GPRPairnospRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRPairnospRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::GPRwithAPSR_NZCVnospRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRwithAPSR_NZCVnospRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10574 | /* 721 */ { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10575 | /* 725 */ { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10576 | /* 729 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, |
| 10577 | /* 736 */ { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10578 | /* 739 */ { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10579 | /* 742 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, MCOI_TIED_TO(0) }, |
| 10580 | /* 749 */ { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10581 | /* 754 */ { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10582 | /* 759 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, |
| 10583 | /* 767 */ { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10584 | /* 771 */ { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10585 | /* 775 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, MCOI_TIED_TO(0) }, |
| 10586 | /* 783 */ { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10587 | /* 789 */ { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10588 | /* 795 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, |
| 10589 | /* 804 */ { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10590 | /* 809 */ { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10591 | /* 814 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, MCOI_TIED_TO(0) }, |
| 10592 | /* 823 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10593 | /* 831 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10594 | /* 837 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10595 | /* 841 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10596 | /* 846 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10597 | /* 852 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10598 | /* 855 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10599 | /* 858 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10600 | /* 861 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10601 | /* 865 */ { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10602 | /* 869 */ { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10603 | /* 873 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10604 | /* 877 */ { ARM::GPRPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10605 | /* 881 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, |
| 10606 | /* 885 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10607 | /* 889 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10608 | /* 895 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10609 | /* 901 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(1) }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10610 | /* 908 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10611 | /* 914 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10612 | /* 919 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10613 | /* 925 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10614 | /* 932 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(2) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10615 | /* 940 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10616 | /* 946 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(1) }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10617 | /* 953 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(1) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10618 | /* 960 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10619 | /* 966 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10620 | /* 974 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10621 | /* 980 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10622 | /* 987 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10623 | /* 992 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10624 | /* 999 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10625 | /* 1005 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10626 | /* 1010 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10627 | /* 1015 */ { ARM::tcGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tcGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10628 | /* 1020 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10629 | /* 1026 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10630 | /* 1033 */ { ARM::GPRwithAPSRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10631 | /* 1041 */ { ARM::GPRwithAPSRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10632 | /* 1047 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10633 | /* 1054 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10634 | /* 1059 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10635 | /* 1062 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10636 | /* 1066 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10637 | /* 1070 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10638 | /* 1074 */ { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPROddRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::tGPROddRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10639 | /* 1081 */ { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::tGPROddRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::tGPROddRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10640 | /* 1088 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10641 | /* 1093 */ { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::tGPROddRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::tGPROddRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10642 | /* 1101 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, |
| 10643 | /* 1108 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, MCOI_TIED_TO(0) }, |
| 10644 | /* 1115 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, MCOI_TIED_TO(0) }, |
| 10645 | /* 1121 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::cl_FPSCR_NZCVRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::cl_FPSCR_NZCVRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, MCOI_TIED_TO(0) }, |
| 10646 | /* 1130 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::cl_FPSCR_NZCVRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, MCOI_TIED_TO(0) }, |
| 10647 | /* 1138 */ { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPROddRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::tGPROddRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, |
| 10648 | /* 1146 */ { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPROddRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, |
| 10649 | /* 1152 */ { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, |
| 10650 | /* 1158 */ { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, |
| 10651 | /* 1163 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, MCOI_TIED_TO(0) }, |
| 10652 | /* 1170 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, |
| 10653 | /* 1176 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, MCOI_TIED_TO(0) }, |
| 10654 | /* 1184 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, MCOI_TIED_TO(0) }, |
| 10655 | /* 1192 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, |
| 10656 | /* 1200 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, |
| 10657 | /* 1208 */ { ARM::VCCRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, |
| 10658 | /* 1215 */ { ARM::VCCRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRwithZRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, |
| 10659 | /* 1222 */ { ARM::VCCRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, |
| 10660 | /* 1227 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, |
| 10661 | /* 1233 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, MCOI_TIED_TO(0) }, |
| 10662 | /* 1240 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, MCOI_TIED_TO(0) }, |
| 10663 | /* 1248 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, MCOI_TIED_TO(0) }, |
| 10664 | /* 1254 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { ARM::tGPROddRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, MCOI_TIED_TO(0) }, |
| 10665 | /* 1263 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, |
| 10666 | /* 1270 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, |
| 10667 | /* 1277 */ { ARM::MQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, |
| 10668 | /* 1280 */ { ARM::MQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(1) }, |
| 10669 | /* 1284 */ { ARM::MQQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, |
| 10670 | /* 1287 */ { ARM::MQQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(1) }, |
| 10671 | /* 1291 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, |
| 10672 | /* 1297 */ { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, |
| 10673 | /* 1304 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, |
| 10674 | /* 1310 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, |
| 10675 | /* 1316 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, |
| 10676 | /* 1323 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, |
| 10677 | /* 1329 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, |
| 10678 | /* 1336 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, |
| 10679 | /* 1342 */ { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, |
| 10680 | /* 1349 */ { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, |
| 10681 | /* 1355 */ { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPROddRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::tGPROddRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, |
| 10682 | /* 1364 */ { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPROddRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, |
| 10683 | /* 1371 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10684 | /* 1376 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10685 | /* 1384 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10686 | /* 1391 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10687 | /* 1397 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, MCOI_TIED_TO(0) }, |
| 10688 | /* 1403 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, MCOI_TIED_TO(0) }, |
| 10689 | /* 1410 */ { ARM::VCCRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::VCCRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, |
| 10690 | /* 1415 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, |
| 10691 | /* 1421 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10692 | /* 1425 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRwithZRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10693 | /* 1429 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, |
| 10694 | /* 1436 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, MCOI_TIED_TO(0) }, |
| 10695 | /* 1443 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, |
| 10696 | /* 1449 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, |
| 10697 | /* 1456 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, MCOI_TIED_TO(0) }, |
| 10698 | /* 1462 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, |
| 10699 | /* 1470 */ { ARM::MQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, |
| 10700 | /* 1472 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, |
| 10701 | /* 1475 */ { ARM::MQQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, |
| 10702 | /* 1477 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, |
| 10703 | /* 1480 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, |
| 10704 | /* 1486 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, |
| 10705 | /* 1492 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, |
| 10706 | /* 1499 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10707 | /* 1506 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10708 | /* 1509 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10709 | /* 1512 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10710 | /* 1518 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, |
| 10711 | /* 1520 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, |
| 10712 | /* 1523 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10713 | /* 1528 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10714 | /* 1534 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10715 | /* 1540 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10716 | /* 1549 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10717 | /* 1557 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10718 | /* 1564 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10719 | /* 1570 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10720 | /* 1575 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10721 | /* 1580 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::GPRPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10722 | /* 1585 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10723 | /* 1592 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10724 | /* 1599 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10725 | /* 1605 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10726 | /* 1613 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10727 | /* 1619 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10728 | /* 1626 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10729 | /* 1631 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10730 | /* 1637 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10731 | /* 1642 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10732 | /* 1650 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10733 | /* 1656 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10734 | /* 1662 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10735 | /* 1668 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10736 | /* 1673 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10737 | /* 1678 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10738 | /* 1683 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10739 | /* 1687 */ { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10740 | /* 1691 */ { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10741 | /* 1695 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10742 | /* 1699 */ { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10743 | /* 1704 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10744 | /* 1709 */ { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10745 | /* 1714 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10746 | /* 1719 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10747 | /* 1724 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10748 | /* 1729 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10749 | /* 1734 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10750 | /* 1740 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10751 | /* 1746 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10752 | /* 1750 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10753 | /* 1754 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10754 | /* 1759 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10755 | /* 1765 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10756 | /* 1771 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10757 | /* 1776 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10758 | /* 1782 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10759 | /* 1788 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10760 | /* 1791 */ { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10761 | /* 1794 */ { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10762 | /* 1797 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10763 | /* 1799 */ { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10764 | /* 1801 */ { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10765 | /* 1803 */ { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10766 | /* 1805 */ { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10767 | /* 1810 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10768 | /* 1814 */ { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10769 | /* 1818 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10770 | /* 1823 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10771 | /* 1828 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10772 | /* 1832 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10773 | /* 1836 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10774 | /* 1840 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10775 | /* 1845 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10776 | /* 1851 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10777 | /* 1857 */ { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10778 | /* 1863 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10779 | /* 1866 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPR_8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10780 | /* 1870 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10781 | /* 1873 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10782 | /* 1877 */ { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10783 | /* 1883 */ { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10784 | /* 1886 */ { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10785 | /* 1889 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10786 | /* 1894 */ { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10787 | /* 1897 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10788 | /* 1903 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10789 | /* 1910 */ { ARM::DPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10790 | /* 1915 */ { ARM::DPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10791 | /* 1921 */ { ARM::DPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10792 | /* 1928 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10793 | /* 1935 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10794 | /* 1944 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10795 | /* 1951 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10796 | /* 1960 */ { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10797 | /* 1965 */ { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10798 | /* 1971 */ { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10799 | /* 1978 */ { ARM::QQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10800 | /* 1984 */ { ARM::QQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10801 | /* 1992 */ { ARM::DPairSpcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10802 | /* 1997 */ { ARM::DPairSpcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10803 | /* 2003 */ { ARM::DPairSpcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10804 | /* 2010 */ { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10805 | /* 2016 */ { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10806 | /* 2023 */ { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10807 | /* 2031 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10808 | /* 2040 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(2) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10809 | /* 2051 */ { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10810 | /* 2058 */ { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10811 | /* 2067 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10812 | /* 2074 */ { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10813 | /* 2081 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(3) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10814 | /* 2090 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(2) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10815 | /* 2101 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(3) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(2) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10816 | /* 2114 */ { ARM::QQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10817 | /* 2121 */ { ARM::QQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10818 | /* 2130 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10819 | /* 2138 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(4) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10820 | /* 2148 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(2) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(3) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10821 | /* 2161 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(4) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(2) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(3) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10822 | /* 2176 */ { ARM::DPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10823 | /* 2180 */ { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10824 | /* 2185 */ { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10825 | /* 2190 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10826 | /* 2194 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10827 | /* 2199 */ { ARM::cl_FPSCR_NZCVRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10828 | /* 2204 */ { ARM::cl_FPSCR_NZCVRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10829 | /* 2210 */ { ARM::VCCRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10830 | /* 2215 */ { ARM::VCCRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10831 | /* 2221 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10832 | /* 2225 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10833 | /* 2232 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10834 | /* 2239 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10835 | /* 2246 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10836 | /* 2253 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10837 | /* 2260 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10838 | /* 2267 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10839 | /* 2272 */ { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10840 | /* 2276 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10841 | /* 2280 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10842 | /* 2285 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10843 | /* 2291 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10844 | /* 2295 */ { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10845 | /* 2299 */ { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10846 | /* 2305 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10847 | /* 2309 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::cl_FPSCR_NZCVRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10848 | /* 2313 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::VCCRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10849 | /* 2317 */ { ARM::cl_FPSCR_NZCVRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10850 | /* 2321 */ { ARM::VCCRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10851 | /* 2325 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10852 | /* 2331 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10853 | /* 2337 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10854 | /* 2343 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10855 | /* 2349 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10856 | /* 2355 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10857 | /* 2361 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10858 | /* 2366 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10859 | /* 2371 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10860 | /* 2376 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10861 | /* 2381 */ { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10862 | /* 2383 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10863 | /* 2389 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10864 | /* 2395 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10865 | /* 2401 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10866 | /* 2406 */ { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10867 | /* 2411 */ { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10868 | /* 2415 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10869 | /* 2421 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10870 | /* 2427 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10871 | /* 2433 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10872 | /* 2441 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10873 | /* 2447 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10874 | /* 2455 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10875 | /* 2460 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10876 | /* 2465 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10877 | /* 2471 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10878 | /* 2478 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10879 | /* 2484 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10880 | /* 2491 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10881 | /* 2496 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10882 | /* 2501 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10883 | /* 2508 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10884 | /* 2514 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10885 | /* 2521 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10886 | /* 2528 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10887 | /* 2537 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10888 | /* 2543 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10889 | /* 2551 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10890 | /* 2558 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10891 | /* 2566 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10892 | /* 2576 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10893 | /* 2582 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10894 | /* 2590 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10895 | /* 2597 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10896 | /* 2606 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10897 | /* 2615 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10898 | /* 2626 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10899 | /* 2634 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10900 | /* 2644 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::cl_FPSCR_NZCVRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10901 | /* 2650 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::VCCRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10902 | /* 2656 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10903 | /* 2662 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10904 | /* 2668 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10905 | /* 2673 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10906 | /* 2678 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::DPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10907 | /* 2684 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10908 | /* 2690 */ { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10909 | /* 2694 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10910 | /* 2700 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10911 | /* 2706 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10912 | /* 2713 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10913 | /* 2719 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10914 | /* 2724 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10915 | /* 2730 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10916 | /* 2737 */ { ARM::GPRspRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRspRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10917 | /* 2743 */ { ARM::GPRspRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRspRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10918 | /* 2748 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10919 | /* 2752 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10920 | /* 2756 */ { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnospRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10921 | /* 2761 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10922 | /* 2767 */ { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10923 | /* 2771 */ { -1, 0, MCOI::OPERAND_PCREL, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10924 | /* 2775 */ { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10925 | /* 2779 */ { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnospRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10926 | /* 2784 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10927 | /* 2788 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10928 | /* 2793 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRwithZRnospRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRwithZRnospRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10929 | /* 2797 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10930 | /* 2801 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10931 | /* 2806 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10932 | /* 2811 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10933 | /* 2815 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10934 | /* 2821 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(2) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10935 | /* 2828 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10936 | /* 2834 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10937 | /* 2839 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10938 | /* 2843 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10939 | /* 2849 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10940 | /* 2856 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10941 | /* 2862 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10942 | /* 2867 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10943 | /* 2872 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10944 | /* 2879 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10945 | /* 2883 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10946 | /* 2888 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10947 | /* 2893 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10948 | /* 2899 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10949 | /* 2904 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10950 | /* 2910 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10951 | /* 2914 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10952 | /* 2919 */ { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10953 | /* 2922 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10954 | /* 2928 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10955 | /* 2936 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10956 | /* 2942 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10957 | /* 2947 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10958 | /* 2952 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10959 | /* 2958 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10960 | /* 2964 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10961 | /* 2970 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10962 | /* 2977 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10963 | /* 2983 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10964 | /* 2989 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10965 | /* 2993 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10966 | /* 2997 */ { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10967 | /* 3003 */ { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10968 | /* 3009 */ { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10969 | /* 3015 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRspRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10970 | /* 3020 */ { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRspRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10971 | /* 3025 */ { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10972 | /* 3031 */ { ARM::GPRspRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRspRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10973 | /* 3036 */ { ARM::GPRspRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRspRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10974 | /* 3041 */ { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10975 | /* 3045 */ { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10976 | /* 3048 */ { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10977 | /* 3051 */ { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, |
| 10978 | /* 3053 */ { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10979 | /* 3057 */ { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10980 | /* 3061 */ { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10981 | /* 3066 */ { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10982 | /* 3071 */ { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10983 | /* 3075 */ { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10984 | /* 3080 */ { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10985 | /* 3085 */ { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10986 | /* 3091 */ { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10987 | /* 3096 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10988 | }, { |
| 10989 | /* 0 */ |
| 10990 | /* 0 */ ARM::CPSR, |
| 10991 | /* 1 */ ARM::SP, ARM::SP, |
| 10992 | /* 3 */ ARM::SP, ARM::LR, |
| 10993 | /* 5 */ ARM::R7, ARM::LR, ARM::SP, |
| 10994 | /* 8 */ ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::LR, ARM::CPSR, ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15, |
| 10995 | /* 39 */ ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::LR, ARM::CPSR, |
| 10996 | /* 54 */ ARM::SP, |
| 10997 | /* 55 */ ARM::SP, ARM::R0, ARM::R12, ARM::LR, ARM::CPSR, |
| 10998 | /* 60 */ ARM::R4, ARM::R4, ARM::SP, |
| 10999 | /* 63 */ ARM::CPSR, ARM::CPSR, |
| 11000 | /* 65 */ ARM::LR, |
| 11001 | /* 66 */ ARM::PC, |
| 11002 | /* 67 */ ARM::FPSCR_NZCV, ARM::CPSR, |
| 11003 | /* 69 */ ARM::VPR, |
| 11004 | /* 70 */ ARM::FPSCR_NZCV, |
| 11005 | /* 71 */ ARM::FPSCR, |
| 11006 | /* 72 */ ARM::VPR, ARM::FPSCR, ARM::FPSCR_NZCV, ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7, ARM::D8, ARM::D9, ARM::D10, ARM::D11, ARM::D12, ARM::D13, ARM::D14, ARM::D15, |
| 11007 | /* 91 */ ARM::VPR, ARM::FPSCR, ARM::FPSCR_NZCV, ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7, ARM::D8, ARM::D9, ARM::D10, ARM::D11, ARM::D12, ARM::D13, ARM::D14, ARM::D15, ARM::D16, ARM::D17, ARM::D18, ARM::D19, ARM::D20, ARM::D21, ARM::D22, ARM::D23, ARM::D24, ARM::D25, ARM::D26, ARM::D27, ARM::D28, ARM::D29, ARM::D30, ARM::D31, |
| 11008 | /* 126 */ ARM::VPR, ARM::FPSCR, ARM::FPSCR_NZCV, ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7, ARM::D8, ARM::D9, ARM::D10, ARM::D11, ARM::D12, ARM::D13, ARM::D14, ARM::D15, ARM::VPR, ARM::FPSCR, ARM::FPSCR_NZCV, |
| 11009 | /* 148 */ ARM::VPR, ARM::FPSCR, ARM::FPSCR_NZCV, ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7, ARM::D8, ARM::D9, ARM::D10, ARM::D11, ARM::D12, ARM::D13, ARM::D14, ARM::D15, ARM::D16, ARM::D17, ARM::D18, ARM::D19, ARM::D20, ARM::D21, ARM::D22, ARM::D23, ARM::D24, ARM::D25, ARM::D26, ARM::D27, ARM::D28, ARM::D29, ARM::D30, ARM::D31, ARM::VPR, ARM::FPSCR, ARM::FPSCR_NZCV, |
| 11010 | /* 186 */ ARM::R12, ARM::LR, ARM::SP, |
| 11011 | /* 189 */ ARM::ITSTATE, |
| 11012 | /* 190 */ ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::LR, ARM::CPSR, ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15, |
| 11013 | /* 217 */ ARM::LR, ARM::SP, ARM::R12, |
| 11014 | /* 220 */ ARM::R11, ARM::LR, ARM::SP, |
| 11015 | /* 223 */ ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R12, ARM::CPSR, |
| 11016 | } |
| 11017 | }; |
| 11018 | |
| 11019 | |
| 11020 | #ifdef __GNUC__ |
| 11021 | #pragma GCC diagnostic push |
| 11022 | #pragma GCC diagnostic ignored "-Woverlength-strings" |
| 11023 | #endif |
| 11024 | extern const char ARMInstrNameData[] = { |
| 11025 | /* 0 */ "G_FLOG10\000" |
| 11026 | /* 9 */ "G_FEXP10\000" |
| 11027 | /* 18 */ "VMOVD0\000" |
| 11028 | /* 25 */ "VMSR_P0\000" |
| 11029 | /* 33 */ "VMRS_P0\000" |
| 11030 | /* 41 */ "VMOVQ0\000" |
| 11031 | /* 48 */ "VMRS_MVFR0\000" |
| 11032 | /* 59 */ "SHA1SU0\000" |
| 11033 | /* 67 */ "SHA256SU0\000" |
| 11034 | /* 77 */ "t__brkdiv0\000" |
| 11035 | /* 88 */ "VTBL1\000" |
| 11036 | /* 94 */ "VMRS_MVFR1\000" |
| 11037 | /* 105 */ "t2DCPS1\000" |
| 11038 | /* 113 */ "SHA1SU1\000" |
| 11039 | /* 121 */ "SHA256SU1\000" |
| 11040 | /* 131 */ "VTBX1\000" |
| 11041 | /* 137 */ "CDE_CX1\000" |
| 11042 | /* 145 */ "t2ASRs1\000" |
| 11043 | /* 153 */ "t2LSRs1\000" |
| 11044 | /* 161 */ "t2LDRBi12\000" |
| 11045 | /* 171 */ "t2STRBi12\000" |
| 11046 | /* 181 */ "t2LDRSBi12\000" |
| 11047 | /* 192 */ "t2PLDi12\000" |
| 11048 | /* 201 */ "t2LDRHi12\000" |
| 11049 | /* 211 */ "t2STRHi12\000" |
| 11050 | /* 221 */ "t2LDRSHi12\000" |
| 11051 | /* 232 */ "t2PLIi12\000" |
| 11052 | /* 241 */ "t2LDRi12\000" |
| 11053 | /* 250 */ "t2STRi12\000" |
| 11054 | /* 259 */ "t2PLDWi12\000" |
| 11055 | /* 269 */ "BR_JTm_i12\000" |
| 11056 | /* 280 */ "t2SUBri12\000" |
| 11057 | /* 290 */ "t2ADDri12\000" |
| 11058 | /* 300 */ "t2SUBspImm12\000" |
| 11059 | /* 313 */ "t2ADDspImm12\000" |
| 11060 | /* 326 */ "TCRETURNrinotr12\000" |
| 11061 | /* 343 */ "MVE_VSTRB32\000" |
| 11062 | /* 355 */ "MVE_VSTRH32\000" |
| 11063 | /* 367 */ "COPY_STRUCT_BYVAL_I32\000" |
| 11064 | /* 389 */ "MVE_VCTP32\000" |
| 11065 | /* 400 */ "MVE_VDUP32\000" |
| 11066 | /* 411 */ "MVE_VBRSR32\000" |
| 11067 | /* 423 */ "MVE_VLDRBS32\000" |
| 11068 | /* 436 */ "MVE_VLDRHS32\000" |
| 11069 | /* 449 */ "MVE_VLDRBU32\000" |
| 11070 | /* 462 */ "MVE_VLDRHU32\000" |
| 11071 | /* 475 */ "MVE_VLDRWU32\000" |
| 11072 | /* 488 */ "MVE_VSTRWU32\000" |
| 11073 | /* 501 */ "MVE_VLD20_32\000" |
| 11074 | /* 514 */ "MVE_VST20_32\000" |
| 11075 | /* 527 */ "MVE_VLD40_32\000" |
| 11076 | /* 540 */ "MVE_VST40_32\000" |
| 11077 | /* 553 */ "MVE_VLD21_32\000" |
| 11078 | /* 566 */ "MVE_VST21_32\000" |
| 11079 | /* 579 */ "MVE_VLD41_32\000" |
| 11080 | /* 592 */ "MVE_VST41_32\000" |
| 11081 | /* 605 */ "MVE_VLD42_32\000" |
| 11082 | /* 618 */ "MVE_VST42_32\000" |
| 11083 | /* 631 */ "MVE_VLD43_32\000" |
| 11084 | /* 644 */ "MVE_VST43_32\000" |
| 11085 | /* 657 */ "MVE_VREV64_32\000" |
| 11086 | /* 671 */ "tCMP_SWAP_32\000" |
| 11087 | /* 684 */ "MVE_DLSTP_32\000" |
| 11088 | /* 697 */ "MVE_WLSTP_32\000" |
| 11089 | /* 710 */ "MVE_VMOV_from_lane_32\000" |
| 11090 | /* 732 */ "MVE_VMOV_to_lane_32\000" |
| 11091 | /* 752 */ "VLD3dWB_fixed_Asm_32\000" |
| 11092 | /* 773 */ "VST3dWB_fixed_Asm_32\000" |
| 11093 | /* 794 */ "VLD4dWB_fixed_Asm_32\000" |
| 11094 | /* 815 */ "VST4dWB_fixed_Asm_32\000" |
| 11095 | /* 836 */ "VLD1LNdWB_fixed_Asm_32\000" |
| 11096 | /* 859 */ "VST1LNdWB_fixed_Asm_32\000" |
| 11097 | /* 882 */ "VLD2LNdWB_fixed_Asm_32\000" |
| 11098 | /* 905 */ "VST2LNdWB_fixed_Asm_32\000" |
| 11099 | /* 928 */ "VLD3LNdWB_fixed_Asm_32\000" |
| 11100 | /* 951 */ "VST3LNdWB_fixed_Asm_32\000" |
| 11101 | /* 974 */ "VLD4LNdWB_fixed_Asm_32\000" |
| 11102 | /* 997 */ "VST4LNdWB_fixed_Asm_32\000" |
| 11103 | /* 1020 */ "VLD3DUPdWB_fixed_Asm_32\000" |
| 11104 | /* 1044 */ "VLD4DUPdWB_fixed_Asm_32\000" |
| 11105 | /* 1068 */ "VLD3qWB_fixed_Asm_32\000" |
| 11106 | /* 1089 */ "VST3qWB_fixed_Asm_32\000" |
| 11107 | /* 1110 */ "VLD4qWB_fixed_Asm_32\000" |
| 11108 | /* 1131 */ "VST4qWB_fixed_Asm_32\000" |
| 11109 | /* 1152 */ "VLD2LNqWB_fixed_Asm_32\000" |
| 11110 | /* 1175 */ "VST2LNqWB_fixed_Asm_32\000" |
| 11111 | /* 1198 */ "VLD3LNqWB_fixed_Asm_32\000" |
| 11112 | /* 1221 */ "VST3LNqWB_fixed_Asm_32\000" |
| 11113 | /* 1244 */ "VLD4LNqWB_fixed_Asm_32\000" |
| 11114 | /* 1267 */ "VST4LNqWB_fixed_Asm_32\000" |
| 11115 | /* 1290 */ "VLD3DUPqWB_fixed_Asm_32\000" |
| 11116 | /* 1314 */ "VLD4DUPqWB_fixed_Asm_32\000" |
| 11117 | /* 1338 */ "VLD3dWB_register_Asm_32\000" |
| 11118 | /* 1362 */ "VST3dWB_register_Asm_32\000" |
| 11119 | /* 1386 */ "VLD4dWB_register_Asm_32\000" |
| 11120 | /* 1410 */ "VST4dWB_register_Asm_32\000" |
| 11121 | /* 1434 */ "VLD1LNdWB_register_Asm_32\000" |
| 11122 | /* 1460 */ "VST1LNdWB_register_Asm_32\000" |
| 11123 | /* 1486 */ "VLD2LNdWB_register_Asm_32\000" |
| 11124 | /* 1512 */ "VST2LNdWB_register_Asm_32\000" |
| 11125 | /* 1538 */ "VLD3LNdWB_register_Asm_32\000" |
| 11126 | /* 1564 */ "VST3LNdWB_register_Asm_32\000" |
| 11127 | /* 1590 */ "VLD4LNdWB_register_Asm_32\000" |
| 11128 | /* 1616 */ "VST4LNdWB_register_Asm_32\000" |
| 11129 | /* 1642 */ "VLD3DUPdWB_register_Asm_32\000" |
| 11130 | /* 1669 */ "VLD4DUPdWB_register_Asm_32\000" |
| 11131 | /* 1696 */ "VLD3qWB_register_Asm_32\000" |
| 11132 | /* 1720 */ "VST3qWB_register_Asm_32\000" |
| 11133 | /* 1744 */ "VLD4qWB_register_Asm_32\000" |
| 11134 | /* 1768 */ "VST4qWB_register_Asm_32\000" |
| 11135 | /* 1792 */ "VLD2LNqWB_register_Asm_32\000" |
| 11136 | /* 1818 */ "VST2LNqWB_register_Asm_32\000" |
| 11137 | /* 1844 */ "VLD3LNqWB_register_Asm_32\000" |
| 11138 | /* 1870 */ "VST3LNqWB_register_Asm_32\000" |
| 11139 | /* 1896 */ "VLD4LNqWB_register_Asm_32\000" |
| 11140 | /* 1922 */ "VST4LNqWB_register_Asm_32\000" |
| 11141 | /* 1948 */ "VLD3DUPqWB_register_Asm_32\000" |
| 11142 | /* 1975 */ "VLD4DUPqWB_register_Asm_32\000" |
| 11143 | /* 2002 */ "VLD3dAsm_32\000" |
| 11144 | /* 2014 */ "VST3dAsm_32\000" |
| 11145 | /* 2026 */ "VLD4dAsm_32\000" |
| 11146 | /* 2038 */ "VST4dAsm_32\000" |
| 11147 | /* 2050 */ "VLD1LNdAsm_32\000" |
| 11148 | /* 2064 */ "VST1LNdAsm_32\000" |
| 11149 | /* 2078 */ "VLD2LNdAsm_32\000" |
| 11150 | /* 2092 */ "VST2LNdAsm_32\000" |
| 11151 | /* 2106 */ "VLD3LNdAsm_32\000" |
| 11152 | /* 2120 */ "VST3LNdAsm_32\000" |
| 11153 | /* 2134 */ "VLD4LNdAsm_32\000" |
| 11154 | /* 2148 */ "VST4LNdAsm_32\000" |
| 11155 | /* 2162 */ "VLD3DUPdAsm_32\000" |
| 11156 | /* 2177 */ "VLD4DUPdAsm_32\000" |
| 11157 | /* 2192 */ "VLD3qAsm_32\000" |
| 11158 | /* 2204 */ "VST3qAsm_32\000" |
| 11159 | /* 2216 */ "VLD4qAsm_32\000" |
| 11160 | /* 2228 */ "VST4qAsm_32\000" |
| 11161 | /* 2240 */ "VLD2LNqAsm_32\000" |
| 11162 | /* 2254 */ "VST2LNqAsm_32\000" |
| 11163 | /* 2268 */ "VLD3LNqAsm_32\000" |
| 11164 | /* 2282 */ "VST3LNqAsm_32\000" |
| 11165 | /* 2296 */ "VLD4LNqAsm_32\000" |
| 11166 | /* 2310 */ "VST4LNqAsm_32\000" |
| 11167 | /* 2324 */ "VLD3DUPqAsm_32\000" |
| 11168 | /* 2339 */ "VLD4DUPqAsm_32\000" |
| 11169 | /* 2354 */ "VLD2b32\000" |
| 11170 | /* 2362 */ "VST2b32\000" |
| 11171 | /* 2370 */ "VLD1d32\000" |
| 11172 | /* 2378 */ "VST1d32\000" |
| 11173 | /* 2386 */ "VLD2d32\000" |
| 11174 | /* 2394 */ "VST2d32\000" |
| 11175 | /* 2402 */ "VLD3d32\000" |
| 11176 | /* 2410 */ "VST3d32\000" |
| 11177 | /* 2418 */ "VREV64d32\000" |
| 11178 | /* 2428 */ "VLD4d32\000" |
| 11179 | /* 2436 */ "VST4d32\000" |
| 11180 | /* 2444 */ "VLD1LNd32\000" |
| 11181 | /* 2454 */ "VST1LNd32\000" |
| 11182 | /* 2464 */ "VLD2LNd32\000" |
| 11183 | /* 2474 */ "VST2LNd32\000" |
| 11184 | /* 2484 */ "VLD3LNd32\000" |
| 11185 | /* 2494 */ "VST3LNd32\000" |
| 11186 | /* 2504 */ "VLD4LNd32\000" |
| 11187 | /* 2514 */ "VST4LNd32\000" |
| 11188 | /* 2524 */ "VTRNd32\000" |
| 11189 | /* 2532 */ "VLD1DUPd32\000" |
| 11190 | /* 2543 */ "VLD2DUPd32\000" |
| 11191 | /* 2554 */ "VLD3DUPd32\000" |
| 11192 | /* 2565 */ "VLD4DUPd32\000" |
| 11193 | /* 2576 */ "VEXTd32\000" |
| 11194 | /* 2584 */ "VCMLAv2f32\000" |
| 11195 | /* 2595 */ "VCADDv2f32\000" |
| 11196 | /* 2606 */ "VMOVv2f32\000" |
| 11197 | /* 2616 */ "VCGEzv2f32\000" |
| 11198 | /* 2627 */ "VCLEzv2f32\000" |
| 11199 | /* 2638 */ "VCEQzv2f32\000" |
| 11200 | /* 2649 */ "VCGTzv2f32\000" |
| 11201 | /* 2660 */ "VCLTzv2f32\000" |
| 11202 | /* 2671 */ "VCMLAv4f32\000" |
| 11203 | /* 2682 */ "VCADDv4f32\000" |
| 11204 | /* 2693 */ "MVE_VPTv4f32\000" |
| 11205 | /* 2706 */ "VMOVv4f32\000" |
| 11206 | /* 2716 */ "VCGEzv4f32\000" |
| 11207 | /* 2727 */ "VCLEzv4f32\000" |
| 11208 | /* 2738 */ "VCEQzv4f32\000" |
| 11209 | /* 2749 */ "VCGTzv4f32\000" |
| 11210 | /* 2760 */ "VCLTzv4f32\000" |
| 11211 | /* 2771 */ "MVE_VCMLAf32\000" |
| 11212 | /* 2784 */ "MVE_VFMAf32\000" |
| 11213 | /* 2796 */ "MVE_VMINNMAf32\000" |
| 11214 | /* 2811 */ "MVE_VMAXNMAf32\000" |
| 11215 | /* 2826 */ "MVE_VSUBf32\000" |
| 11216 | /* 2838 */ "MVE_VABDf32\000" |
| 11217 | /* 2850 */ "MVE_VCADDf32\000" |
| 11218 | /* 2863 */ "MVE_VADDf32\000" |
| 11219 | /* 2875 */ "MVE_VNEGf32\000" |
| 11220 | /* 2887 */ "MVE_VCMULf32\000" |
| 11221 | /* 2900 */ "MVE_VMULf32\000" |
| 11222 | /* 2912 */ "MVE_VMINNMf32\000" |
| 11223 | /* 2926 */ "MVE_VMAXNMf32\000" |
| 11224 | /* 2940 */ "MVE_VCMPf32\000" |
| 11225 | /* 2952 */ "MVE_VABSf32\000" |
| 11226 | /* 2964 */ "MVE_VFMSf32\000" |
| 11227 | /* 2976 */ "MVE_VFMA_qr_Sf32\000" |
| 11228 | /* 2993 */ "MVE_VMINNMAVf32\000" |
| 11229 | /* 3009 */ "MVE_VMAXNMAVf32\000" |
| 11230 | /* 3025 */ "MVE_VMINNMVf32\000" |
| 11231 | /* 3040 */ "MVE_VMAXNMVf32\000" |
| 11232 | /* 3055 */ "MVE_VFMA_qr_f32\000" |
| 11233 | /* 3071 */ "MVE_VSUB_qr_f32\000" |
| 11234 | /* 3087 */ "MVE_VADD_qr_f32\000" |
| 11235 | /* 3103 */ "MVE_VMUL_qr_f32\000" |
| 11236 | /* 3119 */ "MVE_VMOVimmf32\000" |
| 11237 | /* 3134 */ "VMLAv2i32\000" |
| 11238 | /* 3144 */ "VSUBv2i32\000" |
| 11239 | /* 3154 */ "VADDv2i32\000" |
| 11240 | /* 3164 */ "VQNEGv2i32\000" |
| 11241 | /* 3175 */ "VQRDMLAHv2i32\000" |
| 11242 | /* 3189 */ "VQDMULHv2i32\000" |
| 11243 | /* 3202 */ "VQRDMULHv2i32\000" |
| 11244 | /* 3216 */ "VQRDMLSHv2i32\000" |
| 11245 | /* 3230 */ "VSLIv2i32\000" |
| 11246 | /* 3240 */ "VSRIv2i32\000" |
| 11247 | /* 3250 */ "VMULv2i32\000" |
| 11248 | /* 3260 */ "VRSUBHNv2i32\000" |
| 11249 | /* 3273 */ "VSUBHNv2i32\000" |
| 11250 | /* 3285 */ "VRADDHNv2i32\000" |
| 11251 | /* 3298 */ "VADDHNv2i32\000" |
| 11252 | /* 3310 */ "VRSHRNv2i32\000" |
| 11253 | /* 3322 */ "VSHRNv2i32\000" |
| 11254 | /* 3333 */ "VQSHRUNv2i32\000" |
| 11255 | /* 3346 */ "VQRSHRUNv2i32\000" |
| 11256 | /* 3360 */ "VMVNv2i32\000" |
| 11257 | /* 3370 */ "VMOVNv2i32\000" |
| 11258 | /* 3381 */ "VCEQv2i32\000" |
| 11259 | /* 3391 */ "VQABSv2i32\000" |
| 11260 | /* 3402 */ "VABSv2i32\000" |
| 11261 | /* 3412 */ "VCLSv2i32\000" |
| 11262 | /* 3422 */ "VMLSv2i32\000" |
| 11263 | /* 3432 */ "VTSTv2i32\000" |
| 11264 | /* 3442 */ "VMOVv2i32\000" |
| 11265 | /* 3452 */ "VCLZv2i32\000" |
| 11266 | /* 3462 */ "VBICiv2i32\000" |
| 11267 | /* 3473 */ "VSHLiv2i32\000" |
| 11268 | /* 3484 */ "VORRiv2i32\000" |
| 11269 | /* 3495 */ "VQSHLsiv2i32\000" |
| 11270 | /* 3508 */ "VQSHLuiv2i32\000" |
| 11271 | /* 3521 */ "VMLAslv2i32\000" |
| 11272 | /* 3533 */ "VQRDMLAHslv2i32\000" |
| 11273 | /* 3549 */ "VQDMULHslv2i32\000" |
| 11274 | /* 3564 */ "VQRDMULHslv2i32\000" |
| 11275 | /* 3580 */ "VQRDMLSHslv2i32\000" |
| 11276 | /* 3596 */ "VQDMLALslv2i32\000" |
| 11277 | /* 3611 */ "VQDMULLslv2i32\000" |
| 11278 | /* 3626 */ "VQDMLSLslv2i32\000" |
| 11279 | /* 3641 */ "VMULslv2i32\000" |
| 11280 | /* 3653 */ "VMLSslv2i32\000" |
| 11281 | /* 3665 */ "VABAsv2i32\000" |
| 11282 | /* 3676 */ "VRSRAsv2i32\000" |
| 11283 | /* 3688 */ "VSRAsv2i32\000" |
| 11284 | /* 3699 */ "VHSUBsv2i32\000" |
| 11285 | /* 3711 */ "VQSUBsv2i32\000" |
| 11286 | /* 3723 */ "VABDsv2i32\000" |
| 11287 | /* 3734 */ "VRHADDsv2i32\000" |
| 11288 | /* 3747 */ "VHADDsv2i32\000" |
| 11289 | /* 3759 */ "VQADDsv2i32\000" |
| 11290 | /* 3771 */ "VCGEsv2i32\000" |
| 11291 | /* 3782 */ "VPADALsv2i32\000" |
| 11292 | /* 3795 */ "VPADDLsv2i32\000" |
| 11293 | /* 3808 */ "VQSHLsv2i32\000" |
| 11294 | /* 3820 */ "VQRSHLsv2i32\000" |
| 11295 | /* 3833 */ "VRSHLsv2i32\000" |
| 11296 | /* 3845 */ "VSHLsv2i32\000" |
| 11297 | /* 3856 */ "VMINsv2i32\000" |
| 11298 | /* 3867 */ "VQSHRNsv2i32\000" |
| 11299 | /* 3880 */ "VQRSHRNsv2i32\000" |
| 11300 | /* 3894 */ "VQMOVNsv2i32\000" |
| 11301 | /* 3907 */ "VRSHRsv2i32\000" |
| 11302 | /* 3919 */ "VSHRsv2i32\000" |
| 11303 | /* 3930 */ "VCGTsv2i32\000" |
| 11304 | /* 3941 */ "VMAXsv2i32\000" |
| 11305 | /* 3952 */ "VMLALslsv2i32\000" |
| 11306 | /* 3966 */ "VMULLslsv2i32\000" |
| 11307 | /* 3980 */ "VMLSLslsv2i32\000" |
| 11308 | /* 3994 */ "VABAuv2i32\000" |
| 11309 | /* 4005 */ "VRSRAuv2i32\000" |
| 11310 | /* 4017 */ "VSRAuv2i32\000" |
| 11311 | /* 4028 */ "VHSUBuv2i32\000" |
| 11312 | /* 4040 */ "VQSUBuv2i32\000" |
| 11313 | /* 4052 */ "VABDuv2i32\000" |
| 11314 | /* 4063 */ "VRHADDuv2i32\000" |
| 11315 | /* 4076 */ "VHADDuv2i32\000" |
| 11316 | /* 4088 */ "VQADDuv2i32\000" |
| 11317 | /* 4100 */ "VCGEuv2i32\000" |
| 11318 | /* 4111 */ "VPADALuv2i32\000" |
| 11319 | /* 4124 */ "VPADDLuv2i32\000" |
| 11320 | /* 4137 */ "VQSHLuv2i32\000" |
| 11321 | /* 4149 */ "VQRSHLuv2i32\000" |
| 11322 | /* 4162 */ "VRSHLuv2i32\000" |
| 11323 | /* 4174 */ "VSHLuv2i32\000" |
| 11324 | /* 4185 */ "VMINuv2i32\000" |
| 11325 | /* 4196 */ "VQSHRNuv2i32\000" |
| 11326 | /* 4209 */ "VQRSHRNuv2i32\000" |
| 11327 | /* 4223 */ "VQMOVNuv2i32\000" |
| 11328 | /* 4236 */ "VRSHRuv2i32\000" |
| 11329 | /* 4248 */ "VSHRuv2i32\000" |
| 11330 | /* 4259 */ "VCGTuv2i32\000" |
| 11331 | /* 4270 */ "VMAXuv2i32\000" |
| 11332 | /* 4281 */ "VMLALsluv2i32\000" |
| 11333 | /* 4295 */ "VMULLsluv2i32\000" |
| 11334 | /* 4309 */ "VMLSLsluv2i32\000" |
| 11335 | /* 4323 */ "VQSHLsuv2i32\000" |
| 11336 | /* 4336 */ "VQMOVNsuv2i32\000" |
| 11337 | /* 4350 */ "VCGEzv2i32\000" |
| 11338 | /* 4361 */ "VCLEzv2i32\000" |
| 11339 | /* 4372 */ "VCEQzv2i32\000" |
| 11340 | /* 4383 */ "VCGTzv2i32\000" |
| 11341 | /* 4394 */ "VCLTzv2i32\000" |
| 11342 | /* 4405 */ "VMLAv4i32\000" |
| 11343 | /* 4415 */ "VSUBv4i32\000" |
| 11344 | /* 4425 */ "VADDv4i32\000" |
| 11345 | /* 4435 */ "VQNEGv4i32\000" |
| 11346 | /* 4446 */ "VQRDMLAHv4i32\000" |
| 11347 | /* 4460 */ "VQDMULHv4i32\000" |
| 11348 | /* 4473 */ "VQRDMULHv4i32\000" |
| 11349 | /* 4487 */ "VQRDMLSHv4i32\000" |
| 11350 | /* 4501 */ "VSLIv4i32\000" |
| 11351 | /* 4511 */ "VSRIv4i32\000" |
| 11352 | /* 4521 */ "VQDMLALv4i32\000" |
| 11353 | /* 4534 */ "VQDMULLv4i32\000" |
| 11354 | /* 4547 */ "VQDMLSLv4i32\000" |
| 11355 | /* 4560 */ "VMULv4i32\000" |
| 11356 | /* 4570 */ "VMVNv4i32\000" |
| 11357 | /* 4580 */ "VCEQv4i32\000" |
| 11358 | /* 4590 */ "VQABSv4i32\000" |
| 11359 | /* 4601 */ "VABSv4i32\000" |
| 11360 | /* 4611 */ "VCLSv4i32\000" |
| 11361 | /* 4621 */ "VMLSv4i32\000" |
| 11362 | /* 4631 */ "MVE_VPTv4i32\000" |
| 11363 | /* 4644 */ "VTSTv4i32\000" |
| 11364 | /* 4654 */ "VMOVv4i32\000" |
| 11365 | /* 4664 */ "VCLZv4i32\000" |
| 11366 | /* 4674 */ "VBICiv4i32\000" |
| 11367 | /* 4685 */ "VSHLiv4i32\000" |
| 11368 | /* 4696 */ "VORRiv4i32\000" |
| 11369 | /* 4707 */ "VQSHLsiv4i32\000" |
| 11370 | /* 4720 */ "VQSHLuiv4i32\000" |
| 11371 | /* 4733 */ "VMLAslv4i32\000" |
| 11372 | /* 4745 */ "VQRDMLAHslv4i32\000" |
| 11373 | /* 4761 */ "VQDMULHslv4i32\000" |
| 11374 | /* 4776 */ "VQRDMULHslv4i32\000" |
| 11375 | /* 4792 */ "VQRDMLSHslv4i32\000" |
| 11376 | /* 4808 */ "VMULslv4i32\000" |
| 11377 | /* 4820 */ "VMLSslv4i32\000" |
| 11378 | /* 4832 */ "VABAsv4i32\000" |
| 11379 | /* 4843 */ "VRSRAsv4i32\000" |
| 11380 | /* 4855 */ "VSRAsv4i32\000" |
| 11381 | /* 4866 */ "VHSUBsv4i32\000" |
| 11382 | /* 4878 */ "VQSUBsv4i32\000" |
| 11383 | /* 4890 */ "VABDsv4i32\000" |
| 11384 | /* 4901 */ "VRHADDsv4i32\000" |
| 11385 | /* 4914 */ "VHADDsv4i32\000" |
| 11386 | /* 4926 */ "VQADDsv4i32\000" |
| 11387 | /* 4938 */ "VCGEsv4i32\000" |
| 11388 | /* 4949 */ "VABALsv4i32\000" |
| 11389 | /* 4961 */ "VPADALsv4i32\000" |
| 11390 | /* 4974 */ "VMLALsv4i32\000" |
| 11391 | /* 4986 */ "VSUBLsv4i32\000" |
| 11392 | /* 4998 */ "VABDLsv4i32\000" |
| 11393 | /* 5010 */ "VPADDLsv4i32\000" |
| 11394 | /* 5023 */ "VADDLsv4i32\000" |
| 11395 | /* 5035 */ "VQSHLsv4i32\000" |
| 11396 | /* 5047 */ "VQRSHLsv4i32\000" |
| 11397 | /* 5060 */ "VRSHLsv4i32\000" |
| 11398 | /* 5072 */ "VSHLsv4i32\000" |
| 11399 | /* 5083 */ "VSHLLsv4i32\000" |
| 11400 | /* 5095 */ "VMULLsv4i32\000" |
| 11401 | /* 5107 */ "VMLSLsv4i32\000" |
| 11402 | /* 5119 */ "VMOVLsv4i32\000" |
| 11403 | /* 5131 */ "VMINsv4i32\000" |
| 11404 | /* 5142 */ "VRSHRsv4i32\000" |
| 11405 | /* 5154 */ "VSHRsv4i32\000" |
| 11406 | /* 5165 */ "VCGTsv4i32\000" |
| 11407 | /* 5176 */ "VSUBWsv4i32\000" |
| 11408 | /* 5188 */ "VADDWsv4i32\000" |
| 11409 | /* 5200 */ "VMAXsv4i32\000" |
| 11410 | /* 5211 */ "VABAuv4i32\000" |
| 11411 | /* 5222 */ "VRSRAuv4i32\000" |
| 11412 | /* 5234 */ "VSRAuv4i32\000" |
| 11413 | /* 5245 */ "VHSUBuv4i32\000" |
| 11414 | /* 5257 */ "VQSUBuv4i32\000" |
| 11415 | /* 5269 */ "VABDuv4i32\000" |
| 11416 | /* 5280 */ "VRHADDuv4i32\000" |
| 11417 | /* 5293 */ "VHADDuv4i32\000" |
| 11418 | /* 5305 */ "VQADDuv4i32\000" |
| 11419 | /* 5317 */ "VCGEuv4i32\000" |
| 11420 | /* 5328 */ "VABALuv4i32\000" |
| 11421 | /* 5340 */ "VPADALuv4i32\000" |
| 11422 | /* 5353 */ "VMLALuv4i32\000" |
| 11423 | /* 5365 */ "VSUBLuv4i32\000" |
| 11424 | /* 5377 */ "VABDLuv4i32\000" |
| 11425 | /* 5389 */ "VPADDLuv4i32\000" |
| 11426 | /* 5402 */ "VADDLuv4i32\000" |
| 11427 | /* 5414 */ "VQSHLuv4i32\000" |
| 11428 | /* 5426 */ "VQRSHLuv4i32\000" |
| 11429 | /* 5439 */ "VRSHLuv4i32\000" |
| 11430 | /* 5451 */ "VSHLuv4i32\000" |
| 11431 | /* 5462 */ "VSHLLuv4i32\000" |
| 11432 | /* 5474 */ "VMULLuv4i32\000" |
| 11433 | /* 5486 */ "VMLSLuv4i32\000" |
| 11434 | /* 5498 */ "VMOVLuv4i32\000" |
| 11435 | /* 5510 */ "VMINuv4i32\000" |
| 11436 | /* 5521 */ "VRSHRuv4i32\000" |
| 11437 | /* 5533 */ "VSHRuv4i32\000" |
| 11438 | /* 5544 */ "VCGTuv4i32\000" |
| 11439 | /* 5555 */ "VSUBWuv4i32\000" |
| 11440 | /* 5567 */ "VADDWuv4i32\000" |
| 11441 | /* 5579 */ "VMAXuv4i32\000" |
| 11442 | /* 5590 */ "VQSHLsuv4i32\000" |
| 11443 | /* 5603 */ "VCGEzv4i32\000" |
| 11444 | /* 5614 */ "VCLEzv4i32\000" |
| 11445 | /* 5625 */ "VCEQzv4i32\000" |
| 11446 | /* 5636 */ "VCGTzv4i32\000" |
| 11447 | /* 5647 */ "VCLTzv4i32\000" |
| 11448 | /* 5658 */ "MVE_VSUBi32\000" |
| 11449 | /* 5670 */ "MVE_VCADDi32\000" |
| 11450 | /* 5683 */ "VPADDi32\000" |
| 11451 | /* 5692 */ "MVE_VADDi32\000" |
| 11452 | /* 5704 */ "MVE_VQDMULHi32\000" |
| 11453 | /* 5719 */ "MVE_VQRDMULHi32\000" |
| 11454 | /* 5735 */ "VSHLLi32\000" |
| 11455 | /* 5744 */ "MVE_VMULi32\000" |
| 11456 | /* 5756 */ "VGETLNi32\000" |
| 11457 | /* 5766 */ "VSETLNi32\000" |
| 11458 | /* 5776 */ "MVE_VCMPi32\000" |
| 11459 | /* 5788 */ "MVE_VMLA_qr_i32\000" |
| 11460 | /* 5804 */ "MVE_VSUB_qr_i32\000" |
| 11461 | /* 5820 */ "MVE_VADD_qr_i32\000" |
| 11462 | /* 5836 */ "MVE_VMUL_qr_i32\000" |
| 11463 | /* 5852 */ "MVE_VMLAS_qr_i32\000" |
| 11464 | /* 5869 */ "MVE_VBICimmi32\000" |
| 11465 | /* 5884 */ "MVE_VMVNimmi32\000" |
| 11466 | /* 5899 */ "MVE_VORRimmi32\000" |
| 11467 | /* 5914 */ "MVE_VMOVimmi32\000" |
| 11468 | /* 5929 */ "MVE_VSHL_immi32\000" |
| 11469 | /* 5945 */ "MVE_VSLIimm32\000" |
| 11470 | /* 5959 */ "MVE_VSRIimm32\000" |
| 11471 | /* 5973 */ "VLD1q32\000" |
| 11472 | /* 5981 */ "VST1q32\000" |
| 11473 | /* 5989 */ "VLD2q32\000" |
| 11474 | /* 5997 */ "VST2q32\000" |
| 11475 | /* 6005 */ "VLD3q32\000" |
| 11476 | /* 6013 */ "VST3q32\000" |
| 11477 | /* 6021 */ "VREV64q32\000" |
| 11478 | /* 6031 */ "VLD4q32\000" |
| 11479 | /* 6039 */ "VST4q32\000" |
| 11480 | /* 6047 */ "VLD2LNq32\000" |
| 11481 | /* 6057 */ "VST2LNq32\000" |
| 11482 | /* 6067 */ "VLD3LNq32\000" |
| 11483 | /* 6077 */ "VST3LNq32\000" |
| 11484 | /* 6087 */ "VLD4LNq32\000" |
| 11485 | /* 6097 */ "VST4LNq32\000" |
| 11486 | /* 6107 */ "VTRNq32\000" |
| 11487 | /* 6115 */ "VZIPq32\000" |
| 11488 | /* 6123 */ "VLD1DUPq32\000" |
| 11489 | /* 6134 */ "VLD3DUPq32\000" |
| 11490 | /* 6145 */ "VLD4DUPq32\000" |
| 11491 | /* 6156 */ "VUZPq32\000" |
| 11492 | /* 6164 */ "VEXTq32\000" |
| 11493 | /* 6172 */ "MVE_VPTv4s32\000" |
| 11494 | /* 6185 */ "MVE_VMINAs32\000" |
| 11495 | /* 6198 */ "MVE_VMAXAs32\000" |
| 11496 | /* 6211 */ "MVE_VMULLBs32\000" |
| 11497 | /* 6225 */ "MVE_VHSUBs32\000" |
| 11498 | /* 6238 */ "MVE_VQSUBs32\000" |
| 11499 | /* 6251 */ "MVE_VABDs32\000" |
| 11500 | /* 6263 */ "MVE_VHCADDs32\000" |
| 11501 | /* 6277 */ "MVE_VRHADDs32\000" |
| 11502 | /* 6291 */ "MVE_VHADDs32\000" |
| 11503 | /* 6304 */ "MVE_VQADDs32\000" |
| 11504 | /* 6317 */ "MVE_VQNEGs32\000" |
| 11505 | /* 6330 */ "MVE_VNEGs32\000" |
| 11506 | /* 6342 */ "MVE_VQDMLADHs32\000" |
| 11507 | /* 6358 */ "MVE_VQRDMLADHs32\000" |
| 11508 | /* 6375 */ "MVE_VQDMLSDHs32\000" |
| 11509 | /* 6391 */ "MVE_VQRDMLSDHs32\000" |
| 11510 | /* 6408 */ "MVE_VRMULHs32\000" |
| 11511 | /* 6422 */ "MVE_VMULHs32\000" |
| 11512 | /* 6435 */ "MVE_VRMLALDAVHs32\000" |
| 11513 | /* 6453 */ "MVE_VRMLSLDAVHs32\000" |
| 11514 | /* 6471 */ "VPMINs32\000" |
| 11515 | /* 6480 */ "MVE_VMINs32\000" |
| 11516 | /* 6492 */ "MVE_VCMPs32\000" |
| 11517 | /* 6504 */ "MVE_VQABSs32\000" |
| 11518 | /* 6517 */ "MVE_VABSs32\000" |
| 11519 | /* 6529 */ "MVE_VCLSs32\000" |
| 11520 | /* 6541 */ "MVE_VMULLTs32\000" |
| 11521 | /* 6555 */ "MVE_VABAVs32\000" |
| 11522 | /* 6568 */ "MVE_VMLADAVs32\000" |
| 11523 | /* 6583 */ "MVE_VMLALDAVs32\000" |
| 11524 | /* 6599 */ "MVE_VMLSLDAVs32\000" |
| 11525 | /* 6615 */ "MVE_VMLSDAVs32\000" |
| 11526 | /* 6630 */ "MVE_VMINAVs32\000" |
| 11527 | /* 6644 */ "MVE_VMAXAVs32\000" |
| 11528 | /* 6658 */ "MVE_VMINVs32\000" |
| 11529 | /* 6671 */ "MVE_VMAXVs32\000" |
| 11530 | /* 6684 */ "VPMAXs32\000" |
| 11531 | /* 6693 */ "MVE_VMAXs32\000" |
| 11532 | /* 6705 */ "MVE_VQDMLADHXs32\000" |
| 11533 | /* 6722 */ "MVE_VQRDMLADHXs32\000" |
| 11534 | /* 6740 */ "MVE_VQDMLSDHXs32\000" |
| 11535 | /* 6757 */ "MVE_VQRDMLSDHXs32\000" |
| 11536 | /* 6775 */ "MVE_VCLZs32\000" |
| 11537 | /* 6787 */ "MVE_VHSUB_qr_s32\000" |
| 11538 | /* 6804 */ "MVE_VQSUB_qr_s32\000" |
| 11539 | /* 6821 */ "MVE_VHADD_qr_s32\000" |
| 11540 | /* 6838 */ "MVE_VQADD_qr_s32\000" |
| 11541 | /* 6855 */ "MVE_VQDMULH_qr_s32\000" |
| 11542 | /* 6874 */ "MVE_VQRDMULH_qr_s32\000" |
| 11543 | /* 6894 */ "MVE_VRMLALDAVHas32\000" |
| 11544 | /* 6913 */ "MVE_VRMLSLDAVHas32\000" |
| 11545 | /* 6932 */ "MVE_VMLADAVas32\000" |
| 11546 | /* 6948 */ "MVE_VMLALDAVas32\000" |
| 11547 | /* 6965 */ "MVE_VMLSLDAVas32\000" |
| 11548 | /* 6982 */ "MVE_VMLSDAVas32\000" |
| 11549 | /* 6998 */ "MVE_VQSHL_by_vecs32\000" |
| 11550 | /* 7018 */ "MVE_VQRSHL_by_vecs32\000" |
| 11551 | /* 7039 */ "MVE_VRSHL_by_vecs32\000" |
| 11552 | /* 7059 */ "MVE_VSHL_by_vecs32\000" |
| 11553 | /* 7078 */ "MVE_VQSHRNbhs32\000" |
| 11554 | /* 7094 */ "MVE_VQRSHRNbhs32\000" |
| 11555 | /* 7111 */ "MVE_VQSHRNths32\000" |
| 11556 | /* 7127 */ "MVE_VQRSHRNths32\000" |
| 11557 | /* 7144 */ "MVE_VQSHLimms32\000" |
| 11558 | /* 7160 */ "MVE_VRSHR_imms32\000" |
| 11559 | /* 7177 */ "MVE_VSHR_imms32\000" |
| 11560 | /* 7193 */ "MVE_VQSHLU_imms32\000" |
| 11561 | /* 7211 */ "MVE_VQDMLAH_qrs32\000" |
| 11562 | /* 7229 */ "MVE_VQRDMLAH_qrs32\000" |
| 11563 | /* 7248 */ "MVE_VQDMLASH_qrs32\000" |
| 11564 | /* 7267 */ "MVE_VQRDMLASH_qrs32\000" |
| 11565 | /* 7287 */ "MVE_VQSHL_qrs32\000" |
| 11566 | /* 7303 */ "MVE_VQRSHL_qrs32\000" |
| 11567 | /* 7320 */ "MVE_VRSHL_qrs32\000" |
| 11568 | /* 7336 */ "MVE_VSHL_qrs32\000" |
| 11569 | /* 7351 */ "MVE_VRMLALDAVHxs32\000" |
| 11570 | /* 7370 */ "MVE_VRMLSLDAVHxs32\000" |
| 11571 | /* 7389 */ "MVE_VMLADAVxs32\000" |
| 11572 | /* 7405 */ "MVE_VMLALDAVxs32\000" |
| 11573 | /* 7422 */ "MVE_VMLSLDAVxs32\000" |
| 11574 | /* 7439 */ "MVE_VMLSDAVxs32\000" |
| 11575 | /* 7455 */ "MVE_VRMLALDAVHaxs32\000" |
| 11576 | /* 7475 */ "MVE_VRMLSLDAVHaxs32\000" |
| 11577 | /* 7495 */ "MVE_VMLADAVaxs32\000" |
| 11578 | /* 7512 */ "MVE_VMLALDAVaxs32\000" |
| 11579 | /* 7530 */ "MVE_VMLSLDAVaxs32\000" |
| 11580 | /* 7548 */ "MVE_VMLSDAVaxs32\000" |
| 11581 | /* 7565 */ "MVE_VPTv4u32\000" |
| 11582 | /* 7578 */ "MVE_VMULLBu32\000" |
| 11583 | /* 7592 */ "MVE_VHSUBu32\000" |
| 11584 | /* 7605 */ "MVE_VQSUBu32\000" |
| 11585 | /* 7618 */ "MVE_VABDu32\000" |
| 11586 | /* 7630 */ "MVE_VRHADDu32\000" |
| 11587 | /* 7644 */ "MVE_VHADDu32\000" |
| 11588 | /* 7657 */ "MVE_VQADDu32\000" |
| 11589 | /* 7670 */ "MVE_VRMULHu32\000" |
| 11590 | /* 7684 */ "MVE_VMULHu32\000" |
| 11591 | /* 7697 */ "MVE_VRMLALDAVHu32\000" |
| 11592 | /* 7715 */ "VPMINu32\000" |
| 11593 | /* 7724 */ "MVE_VMINu32\000" |
| 11594 | /* 7736 */ "MVE_VCMPu32\000" |
| 11595 | /* 7748 */ "MVE_VDDUPu32\000" |
| 11596 | /* 7761 */ "MVE_VIDUPu32\000" |
| 11597 | /* 7774 */ "MVE_VDWDUPu32\000" |
| 11598 | /* 7788 */ "MVE_VIWDUPu32\000" |
| 11599 | /* 7802 */ "MVE_VMULLTu32\000" |
| 11600 | /* 7816 */ "MVE_VABAVu32\000" |
| 11601 | /* 7829 */ "MVE_VMLADAVu32\000" |
| 11602 | /* 7844 */ "MVE_VMLALDAVu32\000" |
| 11603 | /* 7860 */ "MVE_VMINVu32\000" |
| 11604 | /* 7873 */ "MVE_VMAXVu32\000" |
| 11605 | /* 7886 */ "VPMAXu32\000" |
| 11606 | /* 7895 */ "MVE_VMAXu32\000" |
| 11607 | /* 7907 */ "MVE_VHSUB_qr_u32\000" |
| 11608 | /* 7924 */ "MVE_VQSUB_qr_u32\000" |
| 11609 | /* 7941 */ "MVE_VHADD_qr_u32\000" |
| 11610 | /* 7958 */ "MVE_VQADD_qr_u32\000" |
| 11611 | /* 7975 */ "MVE_VRMLALDAVHau32\000" |
| 11612 | /* 7994 */ "MVE_VMLADAVau32\000" |
| 11613 | /* 8010 */ "MVE_VMLALDAVau32\000" |
| 11614 | /* 8027 */ "MVE_VQSHL_by_vecu32\000" |
| 11615 | /* 8047 */ "MVE_VQRSHL_by_vecu32\000" |
| 11616 | /* 8068 */ "MVE_VRSHL_by_vecu32\000" |
| 11617 | /* 8088 */ "MVE_VSHL_by_vecu32\000" |
| 11618 | /* 8107 */ "MVE_VQSHRNbhu32\000" |
| 11619 | /* 8123 */ "MVE_VQRSHRNbhu32\000" |
| 11620 | /* 8140 */ "MVE_VQSHRNthu32\000" |
| 11621 | /* 8156 */ "MVE_VQRSHRNthu32\000" |
| 11622 | /* 8173 */ "MVE_VQSHLimmu32\000" |
| 11623 | /* 8189 */ "MVE_VRSHR_immu32\000" |
| 11624 | /* 8206 */ "MVE_VSHR_immu32\000" |
| 11625 | /* 8222 */ "MVE_VQSHL_qru32\000" |
| 11626 | /* 8238 */ "MVE_VQRSHL_qru32\000" |
| 11627 | /* 8255 */ "MVE_VRSHL_qru32\000" |
| 11628 | /* 8271 */ "MVE_VSHL_qru32\000" |
| 11629 | /* 8286 */ "t2MRC2\000" |
| 11630 | /* 8293 */ "t2MRRC2\000" |
| 11631 | /* 8301 */ "G_FLOG2\000" |
| 11632 | /* 8309 */ "SHA256H2\000" |
| 11633 | /* 8318 */ "VTBL2\000" |
| 11634 | /* 8324 */ "G_FATAN2\000" |
| 11635 | /* 8333 */ "t2CDP2\000" |
| 11636 | /* 8340 */ "G_FEXP2\000" |
| 11637 | /* 8348 */ "t2MCR2\000" |
| 11638 | /* 8355 */ "VMRS_MVFR2\000" |
| 11639 | /* 8366 */ "t2MCRR2\000" |
| 11640 | /* 8374 */ "t2DCPS2\000" |
| 11641 | /* 8382 */ "VMSR_FPINST2\000" |
| 11642 | /* 8395 */ "VMRS_FPINST2\000" |
| 11643 | /* 8408 */ "VLLDM_T2\000" |
| 11644 | /* 8417 */ "VLSTM_T2\000" |
| 11645 | /* 8426 */ "VTBX2\000" |
| 11646 | /* 8432 */ "CDE_CX2\000" |
| 11647 | /* 8440 */ "VLD2DUPd32x2\000" |
| 11648 | /* 8453 */ "VLD2DUPd16x2\000" |
| 11649 | /* 8466 */ "VLD2DUPd8x2\000" |
| 11650 | /* 8478 */ "VTBL3\000" |
| 11651 | /* 8484 */ "t2DCPS3\000" |
| 11652 | /* 8492 */ "VTBX3\000" |
| 11653 | /* 8498 */ "CDE_CX3\000" |
| 11654 | /* 8506 */ "tSUBi3\000" |
| 11655 | /* 8513 */ "tADDi3\000" |
| 11656 | /* 8520 */ "tSUBSi3\000" |
| 11657 | /* 8528 */ "tADDSi3\000" |
| 11658 | /* 8536 */ "MVE_VCTP64\000" |
| 11659 | /* 8547 */ "CMP_SWAP_64\000" |
| 11660 | /* 8559 */ "MVE_DLSTP_64\000" |
| 11661 | /* 8572 */ "MVE_WLSTP_64\000" |
| 11662 | /* 8585 */ "VLD1d64\000" |
| 11663 | /* 8593 */ "VST1d64\000" |
| 11664 | /* 8601 */ "VSUBv1i64\000" |
| 11665 | /* 8611 */ "VADDv1i64\000" |
| 11666 | /* 8621 */ "VSLIv1i64\000" |
| 11667 | /* 8631 */ "VSRIv1i64\000" |
| 11668 | /* 8641 */ "VMOVv1i64\000" |
| 11669 | /* 8651 */ "VSHLiv1i64\000" |
| 11670 | /* 8662 */ "VQSHLsiv1i64\000" |
| 11671 | /* 8675 */ "VQSHLuiv1i64\000" |
| 11672 | /* 8688 */ "VRSRAsv1i64\000" |
| 11673 | /* 8700 */ "VSRAsv1i64\000" |
| 11674 | /* 8711 */ "VQSUBsv1i64\000" |
| 11675 | /* 8723 */ "VQADDsv1i64\000" |
| 11676 | /* 8735 */ "VQSHLsv1i64\000" |
| 11677 | /* 8747 */ "VQRSHLsv1i64\000" |
| 11678 | /* 8760 */ "VRSHLsv1i64\000" |
| 11679 | /* 8772 */ "VSHLsv1i64\000" |
| 11680 | /* 8783 */ "VRSHRsv1i64\000" |
| 11681 | /* 8795 */ "VSHRsv1i64\000" |
| 11682 | /* 8806 */ "VRSRAuv1i64\000" |
| 11683 | /* 8818 */ "VSRAuv1i64\000" |
| 11684 | /* 8829 */ "VQSUBuv1i64\000" |
| 11685 | /* 8841 */ "VQADDuv1i64\000" |
| 11686 | /* 8853 */ "VQSHLuv1i64\000" |
| 11687 | /* 8865 */ "VQRSHLuv1i64\000" |
| 11688 | /* 8878 */ "VRSHLuv1i64\000" |
| 11689 | /* 8890 */ "VSHLuv1i64\000" |
| 11690 | /* 8901 */ "VRSHRuv1i64\000" |
| 11691 | /* 8913 */ "VSHRuv1i64\000" |
| 11692 | /* 8924 */ "VQSHLsuv1i64\000" |
| 11693 | /* 8937 */ "VSUBv2i64\000" |
| 11694 | /* 8947 */ "VADDv2i64\000" |
| 11695 | /* 8957 */ "VSLIv2i64\000" |
| 11696 | /* 8967 */ "VSRIv2i64\000" |
| 11697 | /* 8977 */ "VQDMLALv2i64\000" |
| 11698 | /* 8990 */ "VQDMULLv2i64\000" |
| 11699 | /* 9003 */ "VQDMLSLv2i64\000" |
| 11700 | /* 9016 */ "VMOVv2i64\000" |
| 11701 | /* 9026 */ "VSHLiv2i64\000" |
| 11702 | /* 9037 */ "VQSHLsiv2i64\000" |
| 11703 | /* 9050 */ "VQSHLuiv2i64\000" |
| 11704 | /* 9063 */ "VRSRAsv2i64\000" |
| 11705 | /* 9075 */ "VSRAsv2i64\000" |
| 11706 | /* 9086 */ "VQSUBsv2i64\000" |
| 11707 | /* 9098 */ "VQADDsv2i64\000" |
| 11708 | /* 9110 */ "VABALsv2i64\000" |
| 11709 | /* 9122 */ "VMLALsv2i64\000" |
| 11710 | /* 9134 */ "VSUBLsv2i64\000" |
| 11711 | /* 9146 */ "VABDLsv2i64\000" |
| 11712 | /* 9158 */ "VADDLsv2i64\000" |
| 11713 | /* 9170 */ "VQSHLsv2i64\000" |
| 11714 | /* 9182 */ "VQRSHLsv2i64\000" |
| 11715 | /* 9195 */ "VRSHLsv2i64\000" |
| 11716 | /* 9207 */ "VSHLsv2i64\000" |
| 11717 | /* 9218 */ "VSHLLsv2i64\000" |
| 11718 | /* 9230 */ "VMULLsv2i64\000" |
| 11719 | /* 9242 */ "VMLSLsv2i64\000" |
| 11720 | /* 9254 */ "VMOVLsv2i64\000" |
| 11721 | /* 9266 */ "VRSHRsv2i64\000" |
| 11722 | /* 9278 */ "VSHRsv2i64\000" |
| 11723 | /* 9289 */ "VSUBWsv2i64\000" |
| 11724 | /* 9301 */ "VADDWsv2i64\000" |
| 11725 | /* 9313 */ "VRSRAuv2i64\000" |
| 11726 | /* 9325 */ "VSRAuv2i64\000" |
| 11727 | /* 9336 */ "VQSUBuv2i64\000" |
| 11728 | /* 9348 */ "VQADDuv2i64\000" |
| 11729 | /* 9360 */ "VABALuv2i64\000" |
| 11730 | /* 9372 */ "VMLALuv2i64\000" |
| 11731 | /* 9384 */ "VSUBLuv2i64\000" |
| 11732 | /* 9396 */ "VABDLuv2i64\000" |
| 11733 | /* 9408 */ "VADDLuv2i64\000" |
| 11734 | /* 9420 */ "VQSHLuv2i64\000" |
| 11735 | /* 9432 */ "VQRSHLuv2i64\000" |
| 11736 | /* 9445 */ "VRSHLuv2i64\000" |
| 11737 | /* 9457 */ "VSHLuv2i64\000" |
| 11738 | /* 9468 */ "VSHLLuv2i64\000" |
| 11739 | /* 9480 */ "VMULLuv2i64\000" |
| 11740 | /* 9492 */ "VMLSLuv2i64\000" |
| 11741 | /* 9504 */ "VMOVLuv2i64\000" |
| 11742 | /* 9516 */ "VRSHRuv2i64\000" |
| 11743 | /* 9528 */ "VSHRuv2i64\000" |
| 11744 | /* 9539 */ "VSUBWuv2i64\000" |
| 11745 | /* 9551 */ "VADDWuv2i64\000" |
| 11746 | /* 9563 */ "VQSHLsuv2i64\000" |
| 11747 | /* 9576 */ "BCCi64\000" |
| 11748 | /* 9583 */ "BCCZi64\000" |
| 11749 | /* 9591 */ "MVE_VMOVimmi64\000" |
| 11750 | /* 9606 */ "VMULLp64\000" |
| 11751 | /* 9615 */ "VLD1q64\000" |
| 11752 | /* 9623 */ "VST1q64\000" |
| 11753 | /* 9631 */ "VEXTq64\000" |
| 11754 | /* 9639 */ "VTBL4\000" |
| 11755 | /* 9645 */ "VTBX4\000" |
| 11756 | /* 9651 */ "TAILJMPr4\000" |
| 11757 | /* 9661 */ "MLAv5\000" |
| 11758 | /* 9667 */ "SMLALv5\000" |
| 11759 | /* 9675 */ "UMLALv5\000" |
| 11760 | /* 9683 */ "SMULLv5\000" |
| 11761 | /* 9691 */ "UMULLv5\000" |
| 11762 | /* 9699 */ "MULv5\000" |
| 11763 | /* 9705 */ "t2SXTAB16\000" |
| 11764 | /* 9715 */ "t2UXTAB16\000" |
| 11765 | /* 9725 */ "MVE_VSTRB16\000" |
| 11766 | /* 9737 */ "t2SXTB16\000" |
| 11767 | /* 9746 */ "t2UXTB16\000" |
| 11768 | /* 9755 */ "t2SHSUB16\000" |
| 11769 | /* 9765 */ "t2UHSUB16\000" |
| 11770 | /* 9775 */ "t2QSUB16\000" |
| 11771 | /* 9784 */ "t2UQSUB16\000" |
| 11772 | /* 9794 */ "t2SSUB16\000" |
| 11773 | /* 9803 */ "t2USUB16\000" |
| 11774 | /* 9812 */ "t2SHADD16\000" |
| 11775 | /* 9822 */ "t2UHADD16\000" |
| 11776 | /* 9832 */ "t2QADD16\000" |
| 11777 | /* 9841 */ "t2UQADD16\000" |
| 11778 | /* 9851 */ "t2SADD16\000" |
| 11779 | /* 9860 */ "t2UADD16\000" |
| 11780 | /* 9869 */ "MVE_VCTP16\000" |
| 11781 | /* 9880 */ "MVE_VDUP16\000" |
| 11782 | /* 9891 */ "MVE_VBRSR16\000" |
| 11783 | /* 9903 */ "MVE_VLDRBS16\000" |
| 11784 | /* 9916 */ "t2SSAT16\000" |
| 11785 | /* 9925 */ "t2USAT16\000" |
| 11786 | /* 9934 */ "MVE_VLDRBU16\000" |
| 11787 | /* 9947 */ "MVE_VLDRHU16\000" |
| 11788 | /* 9960 */ "MVE_VSTRHU16\000" |
| 11789 | /* 9973 */ "t2REV16\000" |
| 11790 | /* 9981 */ "tREV16\000" |
| 11791 | /* 9988 */ "MVE_VLD20_16\000" |
| 11792 | /* 10001 */ "MVE_VST20_16\000" |
| 11793 | /* 10014 */ "MVE_VLD40_16\000" |
| 11794 | /* 10027 */ "MVE_VST40_16\000" |
| 11795 | /* 10040 */ "MVE_VLD21_16\000" |
| 11796 | /* 10053 */ "MVE_VST21_16\000" |
| 11797 | /* 10066 */ "MVE_VLD41_16\000" |
| 11798 | /* 10079 */ "MVE_VST41_16\000" |
| 11799 | /* 10092 */ "MVE_VREV32_16\000" |
| 11800 | /* 10106 */ "MVE_VLD42_16\000" |
| 11801 | /* 10119 */ "MVE_VST42_16\000" |
| 11802 | /* 10132 */ "MVE_VLD43_16\000" |
| 11803 | /* 10145 */ "MVE_VST43_16\000" |
| 11804 | /* 10158 */ "MVE_VREV64_16\000" |
| 11805 | /* 10172 */ "tCMP_SWAP_16\000" |
| 11806 | /* 10185 */ "MVE_DLSTP_16\000" |
| 11807 | /* 10198 */ "MVE_WLSTP_16\000" |
| 11808 | /* 10211 */ "MVE_VMOV_to_lane_16\000" |
| 11809 | /* 10231 */ "VLD3dWB_fixed_Asm_16\000" |
| 11810 | /* 10252 */ "VST3dWB_fixed_Asm_16\000" |
| 11811 | /* 10273 */ "VLD4dWB_fixed_Asm_16\000" |
| 11812 | /* 10294 */ "VST4dWB_fixed_Asm_16\000" |
| 11813 | /* 10315 */ "VLD1LNdWB_fixed_Asm_16\000" |
| 11814 | /* 10338 */ "VST1LNdWB_fixed_Asm_16\000" |
| 11815 | /* 10361 */ "VLD2LNdWB_fixed_Asm_16\000" |
| 11816 | /* 10384 */ "VST2LNdWB_fixed_Asm_16\000" |
| 11817 | /* 10407 */ "VLD3LNdWB_fixed_Asm_16\000" |
| 11818 | /* 10430 */ "VST3LNdWB_fixed_Asm_16\000" |
| 11819 | /* 10453 */ "VLD4LNdWB_fixed_Asm_16\000" |
| 11820 | /* 10476 */ "VST4LNdWB_fixed_Asm_16\000" |
| 11821 | /* 10499 */ "VLD3DUPdWB_fixed_Asm_16\000" |
| 11822 | /* 10523 */ "VLD4DUPdWB_fixed_Asm_16\000" |
| 11823 | /* 10547 */ "VLD3qWB_fixed_Asm_16\000" |
| 11824 | /* 10568 */ "VST3qWB_fixed_Asm_16\000" |
| 11825 | /* 10589 */ "VLD4qWB_fixed_Asm_16\000" |
| 11826 | /* 10610 */ "VST4qWB_fixed_Asm_16\000" |
| 11827 | /* 10631 */ "VLD2LNqWB_fixed_Asm_16\000" |
| 11828 | /* 10654 */ "VST2LNqWB_fixed_Asm_16\000" |
| 11829 | /* 10677 */ "VLD3LNqWB_fixed_Asm_16\000" |
| 11830 | /* 10700 */ "VST3LNqWB_fixed_Asm_16\000" |
| 11831 | /* 10723 */ "VLD4LNqWB_fixed_Asm_16\000" |
| 11832 | /* 10746 */ "VST4LNqWB_fixed_Asm_16\000" |
| 11833 | /* 10769 */ "VLD3DUPqWB_fixed_Asm_16\000" |
| 11834 | /* 10793 */ "VLD4DUPqWB_fixed_Asm_16\000" |
| 11835 | /* 10817 */ "VLD3dWB_register_Asm_16\000" |
| 11836 | /* 10841 */ "VST3dWB_register_Asm_16\000" |
| 11837 | /* 10865 */ "VLD4dWB_register_Asm_16\000" |
| 11838 | /* 10889 */ "VST4dWB_register_Asm_16\000" |
| 11839 | /* 10913 */ "VLD1LNdWB_register_Asm_16\000" |
| 11840 | /* 10939 */ "VST1LNdWB_register_Asm_16\000" |
| 11841 | /* 10965 */ "VLD2LNdWB_register_Asm_16\000" |
| 11842 | /* 10991 */ "VST2LNdWB_register_Asm_16\000" |
| 11843 | /* 11017 */ "VLD3LNdWB_register_Asm_16\000" |
| 11844 | /* 11043 */ "VST3LNdWB_register_Asm_16\000" |
| 11845 | /* 11069 */ "VLD4LNdWB_register_Asm_16\000" |
| 11846 | /* 11095 */ "VST4LNdWB_register_Asm_16\000" |
| 11847 | /* 11121 */ "VLD3DUPdWB_register_Asm_16\000" |
| 11848 | /* 11148 */ "VLD4DUPdWB_register_Asm_16\000" |
| 11849 | /* 11175 */ "VLD3qWB_register_Asm_16\000" |
| 11850 | /* 11199 */ "VST3qWB_register_Asm_16\000" |
| 11851 | /* 11223 */ "VLD4qWB_register_Asm_16\000" |
| 11852 | /* 11247 */ "VST4qWB_register_Asm_16\000" |
| 11853 | /* 11271 */ "VLD2LNqWB_register_Asm_16\000" |
| 11854 | /* 11297 */ "VST2LNqWB_register_Asm_16\000" |
| 11855 | /* 11323 */ "VLD3LNqWB_register_Asm_16\000" |
| 11856 | /* 11349 */ "VST3LNqWB_register_Asm_16\000" |
| 11857 | /* 11375 */ "VLD4LNqWB_register_Asm_16\000" |
| 11858 | /* 11401 */ "VST4LNqWB_register_Asm_16\000" |
| 11859 | /* 11427 */ "VLD3DUPqWB_register_Asm_16\000" |
| 11860 | /* 11454 */ "VLD4DUPqWB_register_Asm_16\000" |
| 11861 | /* 11481 */ "VLD3dAsm_16\000" |
| 11862 | /* 11493 */ "VST3dAsm_16\000" |
| 11863 | /* 11505 */ "VLD4dAsm_16\000" |
| 11864 | /* 11517 */ "VST4dAsm_16\000" |
| 11865 | /* 11529 */ "VLD1LNdAsm_16\000" |
| 11866 | /* 11543 */ "VST1LNdAsm_16\000" |
| 11867 | /* 11557 */ "VLD2LNdAsm_16\000" |
| 11868 | /* 11571 */ "VST2LNdAsm_16\000" |
| 11869 | /* 11585 */ "VLD3LNdAsm_16\000" |
| 11870 | /* 11599 */ "VST3LNdAsm_16\000" |
| 11871 | /* 11613 */ "VLD4LNdAsm_16\000" |
| 11872 | /* 11627 */ "VST4LNdAsm_16\000" |
| 11873 | /* 11641 */ "VLD3DUPdAsm_16\000" |
| 11874 | /* 11656 */ "VLD4DUPdAsm_16\000" |
| 11875 | /* 11671 */ "VLD3qAsm_16\000" |
| 11876 | /* 11683 */ "VST3qAsm_16\000" |
| 11877 | /* 11695 */ "VLD4qAsm_16\000" |
| 11878 | /* 11707 */ "VST4qAsm_16\000" |
| 11879 | /* 11719 */ "VLD2LNqAsm_16\000" |
| 11880 | /* 11733 */ "VST2LNqAsm_16\000" |
| 11881 | /* 11747 */ "VLD3LNqAsm_16\000" |
| 11882 | /* 11761 */ "VST3LNqAsm_16\000" |
| 11883 | /* 11775 */ "VLD4LNqAsm_16\000" |
| 11884 | /* 11789 */ "VST4LNqAsm_16\000" |
| 11885 | /* 11803 */ "VLD3DUPqAsm_16\000" |
| 11886 | /* 11818 */ "VLD4DUPqAsm_16\000" |
| 11887 | /* 11833 */ "VLD2b16\000" |
| 11888 | /* 11841 */ "VST2b16\000" |
| 11889 | /* 11849 */ "VLD1d16\000" |
| 11890 | /* 11857 */ "VST1d16\000" |
| 11891 | /* 11865 */ "VREV32d16\000" |
| 11892 | /* 11875 */ "VLD2d16\000" |
| 11893 | /* 11883 */ "VST2d16\000" |
| 11894 | /* 11891 */ "VLD3d16\000" |
| 11895 | /* 11899 */ "VST3d16\000" |
| 11896 | /* 11907 */ "VREV64d16\000" |
| 11897 | /* 11917 */ "VLD4d16\000" |
| 11898 | /* 11925 */ "VST4d16\000" |
| 11899 | /* 11933 */ "VLD1LNd16\000" |
| 11900 | /* 11943 */ "VST1LNd16\000" |
| 11901 | /* 11953 */ "VLD2LNd16\000" |
| 11902 | /* 11963 */ "VST2LNd16\000" |
| 11903 | /* 11973 */ "VLD3LNd16\000" |
| 11904 | /* 11983 */ "VST3LNd16\000" |
| 11905 | /* 11993 */ "VLD4LNd16\000" |
| 11906 | /* 12003 */ "VST4LNd16\000" |
| 11907 | /* 12013 */ "VTRNd16\000" |
| 11908 | /* 12021 */ "VZIPd16\000" |
| 11909 | /* 12029 */ "VLD1DUPd16\000" |
| 11910 | /* 12040 */ "VLD2DUPd16\000" |
| 11911 | /* 12051 */ "VLD3DUPd16\000" |
| 11912 | /* 12062 */ "VLD4DUPd16\000" |
| 11913 | /* 12073 */ "VUZPd16\000" |
| 11914 | /* 12081 */ "VEXTd16\000" |
| 11915 | /* 12089 */ "VCMLAv4f16\000" |
| 11916 | /* 12100 */ "VCADDv4f16\000" |
| 11917 | /* 12111 */ "VCGEzv4f16\000" |
| 11918 | /* 12122 */ "VCLEzv4f16\000" |
| 11919 | /* 12133 */ "VCEQzv4f16\000" |
| 11920 | /* 12144 */ "VCGTzv4f16\000" |
| 11921 | /* 12155 */ "VCLTzv4f16\000" |
| 11922 | /* 12166 */ "VCMLAv8f16\000" |
| 11923 | /* 12177 */ "VCADDv8f16\000" |
| 11924 | /* 12188 */ "MVE_VPTv8f16\000" |
| 11925 | /* 12201 */ "VCGEzv8f16\000" |
| 11926 | /* 12212 */ "VCLEzv8f16\000" |
| 11927 | /* 12223 */ "VCEQzv8f16\000" |
| 11928 | /* 12234 */ "VCGTzv8f16\000" |
| 11929 | /* 12245 */ "VCLTzv8f16\000" |
| 11930 | /* 12256 */ "MVE_VCMLAf16\000" |
| 11931 | /* 12269 */ "MVE_VFMAf16\000" |
| 11932 | /* 12281 */ "MVE_VMINNMAf16\000" |
| 11933 | /* 12296 */ "MVE_VMAXNMAf16\000" |
| 11934 | /* 12311 */ "MVE_VSUBf16\000" |
| 11935 | /* 12323 */ "MVE_VABDf16\000" |
| 11936 | /* 12335 */ "MVE_VCADDf16\000" |
| 11937 | /* 12348 */ "MVE_VADDf16\000" |
| 11938 | /* 12360 */ "MVE_VNEGf16\000" |
| 11939 | /* 12372 */ "MVE_VCMULf16\000" |
| 11940 | /* 12385 */ "MVE_VMULf16\000" |
| 11941 | /* 12397 */ "MVE_VMINNMf16\000" |
| 11942 | /* 12411 */ "MVE_VMAXNMf16\000" |
| 11943 | /* 12425 */ "MVE_VCMPf16\000" |
| 11944 | /* 12437 */ "MVE_VABSf16\000" |
| 11945 | /* 12449 */ "MVE_VFMSf16\000" |
| 11946 | /* 12461 */ "MVE_VFMA_qr_Sf16\000" |
| 11947 | /* 12478 */ "MVE_VMINNMAVf16\000" |
| 11948 | /* 12494 */ "MVE_VMAXNMAVf16\000" |
| 11949 | /* 12510 */ "MVE_VMINNMVf16\000" |
| 11950 | /* 12525 */ "MVE_VMAXNMVf16\000" |
| 11951 | /* 12540 */ "MVE_VFMA_qr_f16\000" |
| 11952 | /* 12556 */ "MVE_VSUB_qr_f16\000" |
| 11953 | /* 12572 */ "MVE_VADD_qr_f16\000" |
| 11954 | /* 12588 */ "MVE_VMUL_qr_f16\000" |
| 11955 | /* 12604 */ "VMLAv4i16\000" |
| 11956 | /* 12614 */ "VSUBv4i16\000" |
| 11957 | /* 12624 */ "VADDv4i16\000" |
| 11958 | /* 12634 */ "VQNEGv4i16\000" |
| 11959 | /* 12645 */ "VQRDMLAHv4i16\000" |
| 11960 | /* 12659 */ "VQDMULHv4i16\000" |
| 11961 | /* 12672 */ "VQRDMULHv4i16\000" |
| 11962 | /* 12686 */ "VQRDMLSHv4i16\000" |
| 11963 | /* 12700 */ "VSLIv4i16\000" |
| 11964 | /* 12710 */ "VSRIv4i16\000" |
| 11965 | /* 12720 */ "VMULv4i16\000" |
| 11966 | /* 12730 */ "VRSUBHNv4i16\000" |
| 11967 | /* 12743 */ "VSUBHNv4i16\000" |
| 11968 | /* 12755 */ "VRADDHNv4i16\000" |
| 11969 | /* 12768 */ "VADDHNv4i16\000" |
| 11970 | /* 12780 */ "VRSHRNv4i16\000" |
| 11971 | /* 12792 */ "VSHRNv4i16\000" |
| 11972 | /* 12803 */ "VQSHRUNv4i16\000" |
| 11973 | /* 12816 */ "VQRSHRUNv4i16\000" |
| 11974 | /* 12830 */ "VMVNv4i16\000" |
| 11975 | /* 12840 */ "VMOVNv4i16\000" |
| 11976 | /* 12851 */ "VCEQv4i16\000" |
| 11977 | /* 12861 */ "VQABSv4i16\000" |
| 11978 | /* 12872 */ "VABSv4i16\000" |
| 11979 | /* 12882 */ "VCLSv4i16\000" |
| 11980 | /* 12892 */ "VMLSv4i16\000" |
| 11981 | /* 12902 */ "VTSTv4i16\000" |
| 11982 | /* 12912 */ "VMOVv4i16\000" |
| 11983 | /* 12922 */ "VCLZv4i16\000" |
| 11984 | /* 12932 */ "VBICiv4i16\000" |
| 11985 | /* 12943 */ "VSHLiv4i16\000" |
| 11986 | /* 12954 */ "VORRiv4i16\000" |
| 11987 | /* 12965 */ "VQSHLsiv4i16\000" |
| 11988 | /* 12978 */ "VQSHLuiv4i16\000" |
| 11989 | /* 12991 */ "VMLAslv4i16\000" |
| 11990 | /* 13003 */ "VQRDMLAHslv4i16\000" |
| 11991 | /* 13019 */ "VQDMULHslv4i16\000" |
| 11992 | /* 13034 */ "VQRDMULHslv4i16\000" |
| 11993 | /* 13050 */ "VQRDMLSHslv4i16\000" |
| 11994 | /* 13066 */ "VQDMLALslv4i16\000" |
| 11995 | /* 13081 */ "VQDMULLslv4i16\000" |
| 11996 | /* 13096 */ "VQDMLSLslv4i16\000" |
| 11997 | /* 13111 */ "VMULslv4i16\000" |
| 11998 | /* 13123 */ "VMLSslv4i16\000" |
| 11999 | /* 13135 */ "VABAsv4i16\000" |
| 12000 | /* 13146 */ "VRSRAsv4i16\000" |
| 12001 | /* 13158 */ "VSRAsv4i16\000" |
| 12002 | /* 13169 */ "VHSUBsv4i16\000" |
| 12003 | /* 13181 */ "VQSUBsv4i16\000" |
| 12004 | /* 13193 */ "VABDsv4i16\000" |
| 12005 | /* 13204 */ "VRHADDsv4i16\000" |
| 12006 | /* 13217 */ "VHADDsv4i16\000" |
| 12007 | /* 13229 */ "VQADDsv4i16\000" |
| 12008 | /* 13241 */ "VCGEsv4i16\000" |
| 12009 | /* 13252 */ "VPADALsv4i16\000" |
| 12010 | /* 13265 */ "VPADDLsv4i16\000" |
| 12011 | /* 13278 */ "VQSHLsv4i16\000" |
| 12012 | /* 13290 */ "VQRSHLsv4i16\000" |
| 12013 | /* 13303 */ "VRSHLsv4i16\000" |
| 12014 | /* 13315 */ "VSHLsv4i16\000" |
| 12015 | /* 13326 */ "VMINsv4i16\000" |
| 12016 | /* 13337 */ "VQSHRNsv4i16\000" |
| 12017 | /* 13350 */ "VQRSHRNsv4i16\000" |
| 12018 | /* 13364 */ "VQMOVNsv4i16\000" |
| 12019 | /* 13377 */ "VRSHRsv4i16\000" |
| 12020 | /* 13389 */ "VSHRsv4i16\000" |
| 12021 | /* 13400 */ "VCGTsv4i16\000" |
| 12022 | /* 13411 */ "VMAXsv4i16\000" |
| 12023 | /* 13422 */ "VMLALslsv4i16\000" |
| 12024 | /* 13436 */ "VMULLslsv4i16\000" |
| 12025 | /* 13450 */ "VMLSLslsv4i16\000" |
| 12026 | /* 13464 */ "VABAuv4i16\000" |
| 12027 | /* 13475 */ "VRSRAuv4i16\000" |
| 12028 | /* 13487 */ "VSRAuv4i16\000" |
| 12029 | /* 13498 */ "VHSUBuv4i16\000" |
| 12030 | /* 13510 */ "VQSUBuv4i16\000" |
| 12031 | /* 13522 */ "VABDuv4i16\000" |
| 12032 | /* 13533 */ "VRHADDuv4i16\000" |
| 12033 | /* 13546 */ "VHADDuv4i16\000" |
| 12034 | /* 13558 */ "VQADDuv4i16\000" |
| 12035 | /* 13570 */ "VCGEuv4i16\000" |
| 12036 | /* 13581 */ "VPADALuv4i16\000" |
| 12037 | /* 13594 */ "VPADDLuv4i16\000" |
| 12038 | /* 13607 */ "VQSHLuv4i16\000" |
| 12039 | /* 13619 */ "VQRSHLuv4i16\000" |
| 12040 | /* 13632 */ "VRSHLuv4i16\000" |
| 12041 | /* 13644 */ "VSHLuv4i16\000" |
| 12042 | /* 13655 */ "VMINuv4i16\000" |
| 12043 | /* 13666 */ "VQSHRNuv4i16\000" |
| 12044 | /* 13679 */ "VQRSHRNuv4i16\000" |
| 12045 | /* 13693 */ "VQMOVNuv4i16\000" |
| 12046 | /* 13706 */ "VRSHRuv4i16\000" |
| 12047 | /* 13718 */ "VSHRuv4i16\000" |
| 12048 | /* 13729 */ "VCGTuv4i16\000" |
| 12049 | /* 13740 */ "VMAXuv4i16\000" |
| 12050 | /* 13751 */ "VMLALsluv4i16\000" |
| 12051 | /* 13765 */ "VMULLsluv4i16\000" |
| 12052 | /* 13779 */ "VMLSLsluv4i16\000" |
| 12053 | /* 13793 */ "VQSHLsuv4i16\000" |
| 12054 | /* 13806 */ "VQMOVNsuv4i16\000" |
| 12055 | /* 13820 */ "VCGEzv4i16\000" |
| 12056 | /* 13831 */ "VCLEzv4i16\000" |
| 12057 | /* 13842 */ "VCEQzv4i16\000" |
| 12058 | /* 13853 */ "VCGTzv4i16\000" |
| 12059 | /* 13864 */ "VCLTzv4i16\000" |
| 12060 | /* 13875 */ "VMLAv8i16\000" |
| 12061 | /* 13885 */ "VSUBv8i16\000" |
| 12062 | /* 13895 */ "VADDv8i16\000" |
| 12063 | /* 13905 */ "VQNEGv8i16\000" |
| 12064 | /* 13916 */ "VQRDMLAHv8i16\000" |
| 12065 | /* 13930 */ "VQDMULHv8i16\000" |
| 12066 | /* 13943 */ "VQRDMULHv8i16\000" |
| 12067 | /* 13957 */ "VQRDMLSHv8i16\000" |
| 12068 | /* 13971 */ "VSLIv8i16\000" |
| 12069 | /* 13981 */ "VSRIv8i16\000" |
| 12070 | /* 13991 */ "VMULv8i16\000" |
| 12071 | /* 14001 */ "VMVNv8i16\000" |
| 12072 | /* 14011 */ "VCEQv8i16\000" |
| 12073 | /* 14021 */ "VQABSv8i16\000" |
| 12074 | /* 14032 */ "VABSv8i16\000" |
| 12075 | /* 14042 */ "VCLSv8i16\000" |
| 12076 | /* 14052 */ "VMLSv8i16\000" |
| 12077 | /* 14062 */ "MVE_VPTv8i16\000" |
| 12078 | /* 14075 */ "VTSTv8i16\000" |
| 12079 | /* 14085 */ "VMOVv8i16\000" |
| 12080 | /* 14095 */ "VCLZv8i16\000" |
| 12081 | /* 14105 */ "VBICiv8i16\000" |
| 12082 | /* 14116 */ "VSHLiv8i16\000" |
| 12083 | /* 14127 */ "VORRiv8i16\000" |
| 12084 | /* 14138 */ "VQSHLsiv8i16\000" |
| 12085 | /* 14151 */ "VQSHLuiv8i16\000" |
| 12086 | /* 14164 */ "VMLAslv8i16\000" |
| 12087 | /* 14176 */ "VQRDMLAHslv8i16\000" |
| 12088 | /* 14192 */ "VQDMULHslv8i16\000" |
| 12089 | /* 14207 */ "VQRDMULHslv8i16\000" |
| 12090 | /* 14223 */ "VQRDMLSHslv8i16\000" |
| 12091 | /* 14239 */ "VMULslv8i16\000" |
| 12092 | /* 14251 */ "VMLSslv8i16\000" |
| 12093 | /* 14263 */ "VABAsv8i16\000" |
| 12094 | /* 14274 */ "VRSRAsv8i16\000" |
| 12095 | /* 14286 */ "VSRAsv8i16\000" |
| 12096 | /* 14297 */ "VHSUBsv8i16\000" |
| 12097 | /* 14309 */ "VQSUBsv8i16\000" |
| 12098 | /* 14321 */ "VABDsv8i16\000" |
| 12099 | /* 14332 */ "VRHADDsv8i16\000" |
| 12100 | /* 14345 */ "VHADDsv8i16\000" |
| 12101 | /* 14357 */ "VQADDsv8i16\000" |
| 12102 | /* 14369 */ "VCGEsv8i16\000" |
| 12103 | /* 14380 */ "VABALsv8i16\000" |
| 12104 | /* 14392 */ "VPADALsv8i16\000" |
| 12105 | /* 14405 */ "VMLALsv8i16\000" |
| 12106 | /* 14417 */ "VSUBLsv8i16\000" |
| 12107 | /* 14429 */ "VABDLsv8i16\000" |
| 12108 | /* 14441 */ "VPADDLsv8i16\000" |
| 12109 | /* 14454 */ "VADDLsv8i16\000" |
| 12110 | /* 14466 */ "VQSHLsv8i16\000" |
| 12111 | /* 14478 */ "VQRSHLsv8i16\000" |
| 12112 | /* 14491 */ "VRSHLsv8i16\000" |
| 12113 | /* 14503 */ "VSHLsv8i16\000" |
| 12114 | /* 14514 */ "VSHLLsv8i16\000" |
| 12115 | /* 14526 */ "VMULLsv8i16\000" |
| 12116 | /* 14538 */ "VMLSLsv8i16\000" |
| 12117 | /* 14550 */ "VMOVLsv8i16\000" |
| 12118 | /* 14562 */ "VMINsv8i16\000" |
| 12119 | /* 14573 */ "VRSHRsv8i16\000" |
| 12120 | /* 14585 */ "VSHRsv8i16\000" |
| 12121 | /* 14596 */ "VCGTsv8i16\000" |
| 12122 | /* 14607 */ "VSUBWsv8i16\000" |
| 12123 | /* 14619 */ "VADDWsv8i16\000" |
| 12124 | /* 14631 */ "VMAXsv8i16\000" |
| 12125 | /* 14642 */ "VABAuv8i16\000" |
| 12126 | /* 14653 */ "VRSRAuv8i16\000" |
| 12127 | /* 14665 */ "VSRAuv8i16\000" |
| 12128 | /* 14676 */ "VHSUBuv8i16\000" |
| 12129 | /* 14688 */ "VQSUBuv8i16\000" |
| 12130 | /* 14700 */ "VABDuv8i16\000" |
| 12131 | /* 14711 */ "VRHADDuv8i16\000" |
| 12132 | /* 14724 */ "VHADDuv8i16\000" |
| 12133 | /* 14736 */ "VQADDuv8i16\000" |
| 12134 | /* 14748 */ "VCGEuv8i16\000" |
| 12135 | /* 14759 */ "VABALuv8i16\000" |
| 12136 | /* 14771 */ "VPADALuv8i16\000" |
| 12137 | /* 14784 */ "VMLALuv8i16\000" |
| 12138 | /* 14796 */ "VSUBLuv8i16\000" |
| 12139 | /* 14808 */ "VABDLuv8i16\000" |
| 12140 | /* 14820 */ "VPADDLuv8i16\000" |
| 12141 | /* 14833 */ "VADDLuv8i16\000" |
| 12142 | /* 14845 */ "VQSHLuv8i16\000" |
| 12143 | /* 14857 */ "VQRSHLuv8i16\000" |
| 12144 | /* 14870 */ "VRSHLuv8i16\000" |
| 12145 | /* 14882 */ "VSHLuv8i16\000" |
| 12146 | /* 14893 */ "VSHLLuv8i16\000" |
| 12147 | /* 14905 */ "VMULLuv8i16\000" |
| 12148 | /* 14917 */ "VMLSLuv8i16\000" |
| 12149 | /* 14929 */ "VMOVLuv8i16\000" |
| 12150 | /* 14941 */ "VMINuv8i16\000" |
| 12151 | /* 14952 */ "VRSHRuv8i16\000" |
| 12152 | /* 14964 */ "VSHRuv8i16\000" |
| 12153 | /* 14975 */ "VCGTuv8i16\000" |
| 12154 | /* 14986 */ "VSUBWuv8i16\000" |
| 12155 | /* 14998 */ "VADDWuv8i16\000" |
| 12156 | /* 15010 */ "VMAXuv8i16\000" |
| 12157 | /* 15021 */ "VQSHLsuv8i16\000" |
| 12158 | /* 15034 */ "VCGEzv8i16\000" |
| 12159 | /* 15045 */ "VCLEzv8i16\000" |
| 12160 | /* 15056 */ "VCEQzv8i16\000" |
| 12161 | /* 15067 */ "VCGTzv8i16\000" |
| 12162 | /* 15078 */ "VCLTzv8i16\000" |
| 12163 | /* 15089 */ "MVE_VSUBi16\000" |
| 12164 | /* 15101 */ "t2MOVCCi16\000" |
| 12165 | /* 15112 */ "MVE_VCADDi16\000" |
| 12166 | /* 15125 */ "VPADDi16\000" |
| 12167 | /* 15134 */ "MVE_VADDi16\000" |
| 12168 | /* 15146 */ "MVE_VQDMULHi16\000" |
| 12169 | /* 15161 */ "MVE_VQRDMULHi16\000" |
| 12170 | /* 15177 */ "VSHLLi16\000" |
| 12171 | /* 15186 */ "MVE_VMULi16\000" |
| 12172 | /* 15198 */ "VSETLNi16\000" |
| 12173 | /* 15208 */ "MVE_VCMPi16\000" |
| 12174 | /* 15220 */ "t2MOVTi16\000" |
| 12175 | /* 15230 */ "t2MOVi16\000" |
| 12176 | /* 15239 */ "MVE_VMLA_qr_i16\000" |
| 12177 | /* 15255 */ "MVE_VSUB_qr_i16\000" |
| 12178 | /* 15271 */ "MVE_VADD_qr_i16\000" |
| 12179 | /* 15287 */ "MVE_VMUL_qr_i16\000" |
| 12180 | /* 15303 */ "MVE_VMLAS_qr_i16\000" |
| 12181 | /* 15320 */ "MVE_VBICimmi16\000" |
| 12182 | /* 15335 */ "MVE_VMVNimmi16\000" |
| 12183 | /* 15350 */ "MVE_VORRimmi16\000" |
| 12184 | /* 15365 */ "MVE_VMOVimmi16\000" |
| 12185 | /* 15380 */ "MVE_VSHL_immi16\000" |
| 12186 | /* 15396 */ "MVE_VSLIimm16\000" |
| 12187 | /* 15410 */ "MVE_VSRIimm16\000" |
| 12188 | /* 15424 */ "MVE_VMULLBp16\000" |
| 12189 | /* 15438 */ "MVE_VMULLTp16\000" |
| 12190 | /* 15452 */ "VLD1q16\000" |
| 12191 | /* 15460 */ "VST1q16\000" |
| 12192 | /* 15468 */ "VREV32q16\000" |
| 12193 | /* 15478 */ "VLD2q16\000" |
| 12194 | /* 15486 */ "VST2q16\000" |
| 12195 | /* 15494 */ "VLD3q16\000" |
| 12196 | /* 15502 */ "VST3q16\000" |
| 12197 | /* 15510 */ "VREV64q16\000" |
| 12198 | /* 15520 */ "VLD4q16\000" |
| 12199 | /* 15528 */ "VST4q16\000" |
| 12200 | /* 15536 */ "VLD2LNq16\000" |
| 12201 | /* 15546 */ "VST2LNq16\000" |
| 12202 | /* 15556 */ "VLD3LNq16\000" |
| 12203 | /* 15566 */ "VST3LNq16\000" |
| 12204 | /* 15576 */ "VLD4LNq16\000" |
| 12205 | /* 15586 */ "VST4LNq16\000" |
| 12206 | /* 15596 */ "VTRNq16\000" |
| 12207 | /* 15604 */ "VZIPq16\000" |
| 12208 | /* 15612 */ "VLD1DUPq16\000" |
| 12209 | /* 15623 */ "VLD3DUPq16\000" |
| 12210 | /* 15634 */ "VLD4DUPq16\000" |
| 12211 | /* 15645 */ "VUZPq16\000" |
| 12212 | /* 15653 */ "VEXTq16\000" |
| 12213 | /* 15661 */ "MVE_VPTv8s16\000" |
| 12214 | /* 15674 */ "MVE_VMINAs16\000" |
| 12215 | /* 15687 */ "MVE_VMAXAs16\000" |
| 12216 | /* 15700 */ "MVE_VMULLBs16\000" |
| 12217 | /* 15714 */ "MVE_VHSUBs16\000" |
| 12218 | /* 15727 */ "MVE_VQSUBs16\000" |
| 12219 | /* 15740 */ "MVE_VABDs16\000" |
| 12220 | /* 15752 */ "MVE_VHCADDs16\000" |
| 12221 | /* 15766 */ "MVE_VRHADDs16\000" |
| 12222 | /* 15780 */ "MVE_VHADDs16\000" |
| 12223 | /* 15793 */ "MVE_VQADDs16\000" |
| 12224 | /* 15806 */ "MVE_VQNEGs16\000" |
| 12225 | /* 15819 */ "MVE_VNEGs16\000" |
| 12226 | /* 15831 */ "MVE_VQDMLADHs16\000" |
| 12227 | /* 15847 */ "MVE_VQRDMLADHs16\000" |
| 12228 | /* 15864 */ "MVE_VQDMLSDHs16\000" |
| 12229 | /* 15880 */ "MVE_VQRDMLSDHs16\000" |
| 12230 | /* 15897 */ "MVE_VRMULHs16\000" |
| 12231 | /* 15911 */ "MVE_VMULHs16\000" |
| 12232 | /* 15924 */ "VPMINs16\000" |
| 12233 | /* 15933 */ "MVE_VMINs16\000" |
| 12234 | /* 15945 */ "VGETLNs16\000" |
| 12235 | /* 15955 */ "MVE_VCMPs16\000" |
| 12236 | /* 15967 */ "MVE_VQABSs16\000" |
| 12237 | /* 15980 */ "MVE_VABSs16\000" |
| 12238 | /* 15992 */ "MVE_VCLSs16\000" |
| 12239 | /* 16004 */ "MVE_VMULLTs16\000" |
| 12240 | /* 16018 */ "MVE_VABAVs16\000" |
| 12241 | /* 16031 */ "MVE_VMLADAVs16\000" |
| 12242 | /* 16046 */ "MVE_VMLALDAVs16\000" |
| 12243 | /* 16062 */ "MVE_VMLSLDAVs16\000" |
| 12244 | /* 16078 */ "MVE_VMLSDAVs16\000" |
| 12245 | /* 16093 */ "MVE_VMINAVs16\000" |
| 12246 | /* 16107 */ "MVE_VMAXAVs16\000" |
| 12247 | /* 16121 */ "MVE_VMINVs16\000" |
| 12248 | /* 16134 */ "MVE_VMAXVs16\000" |
| 12249 | /* 16147 */ "VPMAXs16\000" |
| 12250 | /* 16156 */ "MVE_VMAXs16\000" |
| 12251 | /* 16168 */ "MVE_VQDMLADHXs16\000" |
| 12252 | /* 16185 */ "MVE_VQRDMLADHXs16\000" |
| 12253 | /* 16203 */ "MVE_VQDMLSDHXs16\000" |
| 12254 | /* 16220 */ "MVE_VQRDMLSDHXs16\000" |
| 12255 | /* 16238 */ "MVE_VCLZs16\000" |
| 12256 | /* 16250 */ "MVE_VMOV_from_lane_s16\000" |
| 12257 | /* 16273 */ "MVE_VHSUB_qr_s16\000" |
| 12258 | /* 16290 */ "MVE_VQSUB_qr_s16\000" |
| 12259 | /* 16307 */ "MVE_VHADD_qr_s16\000" |
| 12260 | /* 16324 */ "MVE_VQADD_qr_s16\000" |
| 12261 | /* 16341 */ "MVE_VQDMULH_qr_s16\000" |
| 12262 | /* 16360 */ "MVE_VQRDMULH_qr_s16\000" |
| 12263 | /* 16380 */ "MVE_VMLADAVas16\000" |
| 12264 | /* 16396 */ "MVE_VMLALDAVas16\000" |
| 12265 | /* 16413 */ "MVE_VMLSLDAVas16\000" |
| 12266 | /* 16430 */ "MVE_VMLSDAVas16\000" |
| 12267 | /* 16446 */ "MVE_VQSHL_by_vecs16\000" |
| 12268 | /* 16466 */ "MVE_VQRSHL_by_vecs16\000" |
| 12269 | /* 16487 */ "MVE_VRSHL_by_vecs16\000" |
| 12270 | /* 16507 */ "MVE_VSHL_by_vecs16\000" |
| 12271 | /* 16526 */ "MVE_VQSHRNbhs16\000" |
| 12272 | /* 16542 */ "MVE_VQRSHRNbhs16\000" |
| 12273 | /* 16559 */ "MVE_VQSHRNths16\000" |
| 12274 | /* 16575 */ "MVE_VQRSHRNths16\000" |
| 12275 | /* 16592 */ "MVE_VQSHLimms16\000" |
| 12276 | /* 16608 */ "MVE_VRSHR_imms16\000" |
| 12277 | /* 16625 */ "MVE_VSHR_imms16\000" |
| 12278 | /* 16641 */ "MVE_VQSHLU_imms16\000" |
| 12279 | /* 16659 */ "MVE_VQDMLAH_qrs16\000" |
| 12280 | /* 16677 */ "MVE_VQRDMLAH_qrs16\000" |
| 12281 | /* 16696 */ "MVE_VQDMLASH_qrs16\000" |
| 12282 | /* 16715 */ "MVE_VQRDMLASH_qrs16\000" |
| 12283 | /* 16735 */ "MVE_VQSHL_qrs16\000" |
| 12284 | /* 16751 */ "MVE_VQRSHL_qrs16\000" |
| 12285 | /* 16768 */ "MVE_VRSHL_qrs16\000" |
| 12286 | /* 16784 */ "MVE_VSHL_qrs16\000" |
| 12287 | /* 16799 */ "MVE_VMLADAVxs16\000" |
| 12288 | /* 16815 */ "MVE_VMLALDAVxs16\000" |
| 12289 | /* 16832 */ "MVE_VMLSLDAVxs16\000" |
| 12290 | /* 16849 */ "MVE_VMLSDAVxs16\000" |
| 12291 | /* 16865 */ "MVE_VMLADAVaxs16\000" |
| 12292 | /* 16882 */ "MVE_VMLALDAVaxs16\000" |
| 12293 | /* 16900 */ "MVE_VMLSLDAVaxs16\000" |
| 12294 | /* 16918 */ "MVE_VMLSDAVaxs16\000" |
| 12295 | /* 16935 */ "MVE_VPTv8u16\000" |
| 12296 | /* 16948 */ "MVE_VMULLBu16\000" |
| 12297 | /* 16962 */ "MVE_VHSUBu16\000" |
| 12298 | /* 16975 */ "MVE_VQSUBu16\000" |
| 12299 | /* 16988 */ "MVE_VABDu16\000" |
| 12300 | /* 17000 */ "MVE_VRHADDu16\000" |
| 12301 | /* 17014 */ "MVE_VHADDu16\000" |
| 12302 | /* 17027 */ "MVE_VQADDu16\000" |
| 12303 | /* 17040 */ "MVE_VRMULHu16\000" |
| 12304 | /* 17054 */ "MVE_VMULHu16\000" |
| 12305 | /* 17067 */ "VPMINu16\000" |
| 12306 | /* 17076 */ "MVE_VMINu16\000" |
| 12307 | /* 17088 */ "VGETLNu16\000" |
| 12308 | /* 17098 */ "MVE_VCMPu16\000" |
| 12309 | /* 17110 */ "MVE_VDDUPu16\000" |
| 12310 | /* 17123 */ "MVE_VIDUPu16\000" |
| 12311 | /* 17136 */ "MVE_VDWDUPu16\000" |
| 12312 | /* 17150 */ "MVE_VIWDUPu16\000" |
| 12313 | /* 17164 */ "MVE_VMULLTu16\000" |
| 12314 | /* 17178 */ "MVE_VABAVu16\000" |
| 12315 | /* 17191 */ "MVE_VMLADAVu16\000" |
| 12316 | /* 17206 */ "MVE_VMLALDAVu16\000" |
| 12317 | /* 17222 */ "MVE_VMINVu16\000" |
| 12318 | /* 17235 */ "MVE_VMAXVu16\000" |
| 12319 | /* 17248 */ "VPMAXu16\000" |
| 12320 | /* 17257 */ "MVE_VMAXu16\000" |
| 12321 | /* 17269 */ "MVE_VMOV_from_lane_u16\000" |
| 12322 | /* 17292 */ "MVE_VHSUB_qr_u16\000" |
| 12323 | /* 17309 */ "MVE_VQSUB_qr_u16\000" |
| 12324 | /* 17326 */ "MVE_VHADD_qr_u16\000" |
| 12325 | /* 17343 */ "MVE_VQADD_qr_u16\000" |
| 12326 | /* 17360 */ "MVE_VMLADAVau16\000" |
| 12327 | /* 17376 */ "MVE_VMLALDAVau16\000" |
| 12328 | /* 17393 */ "MVE_VQSHL_by_vecu16\000" |
| 12329 | /* 17413 */ "MVE_VQRSHL_by_vecu16\000" |
| 12330 | /* 17434 */ "MVE_VRSHL_by_vecu16\000" |
| 12331 | /* 17454 */ "MVE_VSHL_by_vecu16\000" |
| 12332 | /* 17473 */ "MVE_VQSHRNbhu16\000" |
| 12333 | /* 17489 */ "MVE_VQRSHRNbhu16\000" |
| 12334 | /* 17506 */ "MVE_VQSHRNthu16\000" |
| 12335 | /* 17522 */ "MVE_VQRSHRNthu16\000" |
| 12336 | /* 17539 */ "MVE_VQSHLimmu16\000" |
| 12337 | /* 17555 */ "MVE_VRSHR_immu16\000" |
| 12338 | /* 17572 */ "MVE_VSHR_immu16\000" |
| 12339 | /* 17588 */ "MVE_VQSHL_qru16\000" |
| 12340 | /* 17604 */ "MVE_VQRSHL_qru16\000" |
| 12341 | /* 17621 */ "MVE_VRSHL_qru16\000" |
| 12342 | /* 17637 */ "MVE_VSHL_qru16\000" |
| 12343 | /* 17652 */ "t2USADA8\000" |
| 12344 | /* 17661 */ "t2SHSUB8\000" |
| 12345 | /* 17670 */ "t2UHSUB8\000" |
| 12346 | /* 17679 */ "t2QSUB8\000" |
| 12347 | /* 17687 */ "t2UQSUB8\000" |
| 12348 | /* 17696 */ "t2SSUB8\000" |
| 12349 | /* 17704 */ "t2USUB8\000" |
| 12350 | /* 17712 */ "t2USAD8\000" |
| 12351 | /* 17720 */ "t2SHADD8\000" |
| 12352 | /* 17729 */ "t2UHADD8\000" |
| 12353 | /* 17738 */ "t2QADD8\000" |
| 12354 | /* 17746 */ "t2UQADD8\000" |
| 12355 | /* 17755 */ "t2SADD8\000" |
| 12356 | /* 17763 */ "t2UADD8\000" |
| 12357 | /* 17771 */ "MVE_VCTP8\000" |
| 12358 | /* 17781 */ "MVE_VDUP8\000" |
| 12359 | /* 17791 */ "MVE_VBRSR8\000" |
| 12360 | /* 17802 */ "MVE_VLDRBU8\000" |
| 12361 | /* 17814 */ "MVE_VSTRBU8\000" |
| 12362 | /* 17826 */ "MVE_VLD20_8\000" |
| 12363 | /* 17838 */ "MVE_VST20_8\000" |
| 12364 | /* 17850 */ "MVE_VLD40_8\000" |
| 12365 | /* 17862 */ "MVE_VST40_8\000" |
| 12366 | /* 17874 */ "MVE_VLD21_8\000" |
| 12367 | /* 17886 */ "MVE_VST21_8\000" |
| 12368 | /* 17898 */ "MVE_VLD41_8\000" |
| 12369 | /* 17910 */ "MVE_VST41_8\000" |
| 12370 | /* 17922 */ "MVE_VREV32_8\000" |
| 12371 | /* 17935 */ "MVE_VLD42_8\000" |
| 12372 | /* 17947 */ "MVE_VST42_8\000" |
| 12373 | /* 17959 */ "MVE_VLD43_8\000" |
| 12374 | /* 17971 */ "MVE_VST43_8\000" |
| 12375 | /* 17983 */ "MVE_VREV64_8\000" |
| 12376 | /* 17996 */ "MVE_VREV16_8\000" |
| 12377 | /* 18009 */ "tCMP_SWAP_8\000" |
| 12378 | /* 18021 */ "MVE_DLSTP_8\000" |
| 12379 | /* 18033 */ "MVE_WLSTP_8\000" |
| 12380 | /* 18045 */ "MVE_VMOV_to_lane_8\000" |
| 12381 | /* 18064 */ "VLD3dWB_fixed_Asm_8\000" |
| 12382 | /* 18084 */ "VST3dWB_fixed_Asm_8\000" |
| 12383 | /* 18104 */ "VLD4dWB_fixed_Asm_8\000" |
| 12384 | /* 18124 */ "VST4dWB_fixed_Asm_8\000" |
| 12385 | /* 18144 */ "VLD1LNdWB_fixed_Asm_8\000" |
| 12386 | /* 18166 */ "VST1LNdWB_fixed_Asm_8\000" |
| 12387 | /* 18188 */ "VLD2LNdWB_fixed_Asm_8\000" |
| 12388 | /* 18210 */ "VST2LNdWB_fixed_Asm_8\000" |
| 12389 | /* 18232 */ "VLD3LNdWB_fixed_Asm_8\000" |
| 12390 | /* 18254 */ "VST3LNdWB_fixed_Asm_8\000" |
| 12391 | /* 18276 */ "VLD4LNdWB_fixed_Asm_8\000" |
| 12392 | /* 18298 */ "VST4LNdWB_fixed_Asm_8\000" |
| 12393 | /* 18320 */ "VLD3DUPdWB_fixed_Asm_8\000" |
| 12394 | /* 18343 */ "VLD4DUPdWB_fixed_Asm_8\000" |
| 12395 | /* 18366 */ "VLD3qWB_fixed_Asm_8\000" |
| 12396 | /* 18386 */ "VST3qWB_fixed_Asm_8\000" |
| 12397 | /* 18406 */ "VLD4qWB_fixed_Asm_8\000" |
| 12398 | /* 18426 */ "VST4qWB_fixed_Asm_8\000" |
| 12399 | /* 18446 */ "VLD3DUPqWB_fixed_Asm_8\000" |
| 12400 | /* 18469 */ "VLD4DUPqWB_fixed_Asm_8\000" |
| 12401 | /* 18492 */ "VLD3dWB_register_Asm_8\000" |
| 12402 | /* 18515 */ "VST3dWB_register_Asm_8\000" |
| 12403 | /* 18538 */ "VLD4dWB_register_Asm_8\000" |
| 12404 | /* 18561 */ "VST4dWB_register_Asm_8\000" |
| 12405 | /* 18584 */ "VLD1LNdWB_register_Asm_8\000" |
| 12406 | /* 18609 */ "VST1LNdWB_register_Asm_8\000" |
| 12407 | /* 18634 */ "VLD2LNdWB_register_Asm_8\000" |
| 12408 | /* 18659 */ "VST2LNdWB_register_Asm_8\000" |
| 12409 | /* 18684 */ "VLD3LNdWB_register_Asm_8\000" |
| 12410 | /* 18709 */ "VST3LNdWB_register_Asm_8\000" |
| 12411 | /* 18734 */ "VLD4LNdWB_register_Asm_8\000" |
| 12412 | /* 18759 */ "VST4LNdWB_register_Asm_8\000" |
| 12413 | /* 18784 */ "VLD3DUPdWB_register_Asm_8\000" |
| 12414 | /* 18810 */ "VLD4DUPdWB_register_Asm_8\000" |
| 12415 | /* 18836 */ "VLD3qWB_register_Asm_8\000" |
| 12416 | /* 18859 */ "VST3qWB_register_Asm_8\000" |
| 12417 | /* 18882 */ "VLD4qWB_register_Asm_8\000" |
| 12418 | /* 18905 */ "VST4qWB_register_Asm_8\000" |
| 12419 | /* 18928 */ "VLD3DUPqWB_register_Asm_8\000" |
| 12420 | /* 18954 */ "VLD4DUPqWB_register_Asm_8\000" |
| 12421 | /* 18980 */ "VLD3dAsm_8\000" |
| 12422 | /* 18991 */ "VST3dAsm_8\000" |
| 12423 | /* 19002 */ "VLD4dAsm_8\000" |
| 12424 | /* 19013 */ "VST4dAsm_8\000" |
| 12425 | /* 19024 */ "VLD1LNdAsm_8\000" |
| 12426 | /* 19037 */ "VST1LNdAsm_8\000" |
| 12427 | /* 19050 */ "VLD2LNdAsm_8\000" |
| 12428 | /* 19063 */ "VST2LNdAsm_8\000" |
| 12429 | /* 19076 */ "VLD3LNdAsm_8\000" |
| 12430 | /* 19089 */ "VST3LNdAsm_8\000" |
| 12431 | /* 19102 */ "VLD4LNdAsm_8\000" |
| 12432 | /* 19115 */ "VST4LNdAsm_8\000" |
| 12433 | /* 19128 */ "VLD3DUPdAsm_8\000" |
| 12434 | /* 19142 */ "VLD4DUPdAsm_8\000" |
| 12435 | /* 19156 */ "VLD3qAsm_8\000" |
| 12436 | /* 19167 */ "VST3qAsm_8\000" |
| 12437 | /* 19178 */ "VLD4qAsm_8\000" |
| 12438 | /* 19189 */ "VST4qAsm_8\000" |
| 12439 | /* 19200 */ "VLD3DUPqAsm_8\000" |
| 12440 | /* 19214 */ "VLD4DUPqAsm_8\000" |
| 12441 | /* 19228 */ "VLD2b8\000" |
| 12442 | /* 19235 */ "VST2b8\000" |
| 12443 | /* 19242 */ "VLD1d8\000" |
| 12444 | /* 19249 */ "VST1d8\000" |
| 12445 | /* 19256 */ "VREV32d8\000" |
| 12446 | /* 19265 */ "VLD2d8\000" |
| 12447 | /* 19272 */ "VST2d8\000" |
| 12448 | /* 19279 */ "VLD3d8\000" |
| 12449 | /* 19286 */ "VST3d8\000" |
| 12450 | /* 19293 */ "VREV64d8\000" |
| 12451 | /* 19302 */ "VLD4d8\000" |
| 12452 | /* 19309 */ "VST4d8\000" |
| 12453 | /* 19316 */ "VREV16d8\000" |
| 12454 | /* 19325 */ "VLD1LNd8\000" |
| 12455 | /* 19334 */ "VST1LNd8\000" |
| 12456 | /* 19343 */ "VLD2LNd8\000" |
| 12457 | /* 19352 */ "VST2LNd8\000" |
| 12458 | /* 19361 */ "VLD3LNd8\000" |
| 12459 | /* 19370 */ "VST3LNd8\000" |
| 12460 | /* 19379 */ "VLD4LNd8\000" |
| 12461 | /* 19388 */ "VST4LNd8\000" |
| 12462 | /* 19397 */ "VTRNd8\000" |
| 12463 | /* 19404 */ "VZIPd8\000" |
| 12464 | /* 19411 */ "VLD1DUPd8\000" |
| 12465 | /* 19421 */ "VLD2DUPd8\000" |
| 12466 | /* 19431 */ "VLD3DUPd8\000" |
| 12467 | /* 19441 */ "VLD4DUPd8\000" |
| 12468 | /* 19451 */ "VUZPd8\000" |
| 12469 | /* 19458 */ "VEXTd8\000" |
| 12470 | /* 19465 */ "VMLAv16i8\000" |
| 12471 | /* 19475 */ "VSUBv16i8\000" |
| 12472 | /* 19485 */ "VADDv16i8\000" |
| 12473 | /* 19495 */ "VQNEGv16i8\000" |
| 12474 | /* 19506 */ "VSLIv16i8\000" |
| 12475 | /* 19516 */ "VSRIv16i8\000" |
| 12476 | /* 19526 */ "VMULv16i8\000" |
| 12477 | /* 19536 */ "VCEQv16i8\000" |
| 12478 | /* 19546 */ "VQABSv16i8\000" |
| 12479 | /* 19557 */ "VABSv16i8\000" |
| 12480 | /* 19567 */ "VCLSv16i8\000" |
| 12481 | /* 19577 */ "VMLSv16i8\000" |
| 12482 | /* 19587 */ "MVE_VPTv16i8\000" |
| 12483 | /* 19600 */ "VTSTv16i8\000" |
| 12484 | /* 19610 */ "VMOVv16i8\000" |
| 12485 | /* 19620 */ "VCLZv16i8\000" |
| 12486 | /* 19630 */ "VSHLiv16i8\000" |
| 12487 | /* 19641 */ "VQSHLsiv16i8\000" |
| 12488 | /* 19654 */ "VQSHLuiv16i8\000" |
| 12489 | /* 19667 */ "VABAsv16i8\000" |
| 12490 | /* 19678 */ "VRSRAsv16i8\000" |
| 12491 | /* 19690 */ "VSRAsv16i8\000" |
| 12492 | /* 19701 */ "VHSUBsv16i8\000" |
| 12493 | /* 19713 */ "VQSUBsv16i8\000" |
| 12494 | /* 19725 */ "VABDsv16i8\000" |
| 12495 | /* 19736 */ "VRHADDsv16i8\000" |
| 12496 | /* 19749 */ "VHADDsv16i8\000" |
| 12497 | /* 19761 */ "VQADDsv16i8\000" |
| 12498 | /* 19773 */ "VCGEsv16i8\000" |
| 12499 | /* 19784 */ "VPADALsv16i8\000" |
| 12500 | /* 19797 */ "VPADDLsv16i8\000" |
| 12501 | /* 19810 */ "VQSHLsv16i8\000" |
| 12502 | /* 19822 */ "VQRSHLsv16i8\000" |
| 12503 | /* 19835 */ "VRSHLsv16i8\000" |
| 12504 | /* 19847 */ "VSHLsv16i8\000" |
| 12505 | /* 19858 */ "VMINsv16i8\000" |
| 12506 | /* 19869 */ "VRSHRsv16i8\000" |
| 12507 | /* 19881 */ "VSHRsv16i8\000" |
| 12508 | /* 19892 */ "VCGTsv16i8\000" |
| 12509 | /* 19903 */ "VMAXsv16i8\000" |
| 12510 | /* 19914 */ "VABAuv16i8\000" |
| 12511 | /* 19925 */ "VRSRAuv16i8\000" |
| 12512 | /* 19937 */ "VSRAuv16i8\000" |
| 12513 | /* 19948 */ "VHSUBuv16i8\000" |
| 12514 | /* 19960 */ "VQSUBuv16i8\000" |
| 12515 | /* 19972 */ "VABDuv16i8\000" |
| 12516 | /* 19983 */ "VRHADDuv16i8\000" |
| 12517 | /* 19996 */ "VHADDuv16i8\000" |
| 12518 | /* 20008 */ "VQADDuv16i8\000" |
| 12519 | /* 20020 */ "VCGEuv16i8\000" |
| 12520 | /* 20031 */ "VPADALuv16i8\000" |
| 12521 | /* 20044 */ "VPADDLuv16i8\000" |
| 12522 | /* 20057 */ "VQSHLuv16i8\000" |
| 12523 | /* 20069 */ "VQRSHLuv16i8\000" |
| 12524 | /* 20082 */ "VRSHLuv16i8\000" |
| 12525 | /* 20094 */ "VSHLuv16i8\000" |
| 12526 | /* 20105 */ "VMINuv16i8\000" |
| 12527 | /* 20116 */ "VRSHRuv16i8\000" |
| 12528 | /* 20128 */ "VSHRuv16i8\000" |
| 12529 | /* 20139 */ "VCGTuv16i8\000" |
| 12530 | /* 20150 */ "VMAXuv16i8\000" |
| 12531 | /* 20161 */ "VQSHLsuv16i8\000" |
| 12532 | /* 20174 */ "VCGEzv16i8\000" |
| 12533 | /* 20185 */ "VCLEzv16i8\000" |
| 12534 | /* 20196 */ "VCEQzv16i8\000" |
| 12535 | /* 20207 */ "VCGTzv16i8\000" |
| 12536 | /* 20218 */ "VCLTzv16i8\000" |
| 12537 | /* 20229 */ "VMLAv8i8\000" |
| 12538 | /* 20238 */ "VSUBv8i8\000" |
| 12539 | /* 20247 */ "VADDv8i8\000" |
| 12540 | /* 20256 */ "VQNEGv8i8\000" |
| 12541 | /* 20266 */ "VSLIv8i8\000" |
| 12542 | /* 20275 */ "VSRIv8i8\000" |
| 12543 | /* 20284 */ "VMULv8i8\000" |
| 12544 | /* 20293 */ "VRSUBHNv8i8\000" |
| 12545 | /* 20305 */ "VSUBHNv8i8\000" |
| 12546 | /* 20316 */ "VRADDHNv8i8\000" |
| 12547 | /* 20328 */ "VADDHNv8i8\000" |
| 12548 | /* 20339 */ "VRSHRNv8i8\000" |
| 12549 | /* 20350 */ "VSHRNv8i8\000" |
| 12550 | /* 20360 */ "VQSHRUNv8i8\000" |
| 12551 | /* 20372 */ "VQRSHRUNv8i8\000" |
| 12552 | /* 20385 */ "VMOVNv8i8\000" |
| 12553 | /* 20395 */ "VCEQv8i8\000" |
| 12554 | /* 20404 */ "VQABSv8i8\000" |
| 12555 | /* 20414 */ "VABSv8i8\000" |
| 12556 | /* 20423 */ "VCLSv8i8\000" |
| 12557 | /* 20432 */ "VMLSv8i8\000" |
| 12558 | /* 20441 */ "VTSTv8i8\000" |
| 12559 | /* 20450 */ "VMOVv8i8\000" |
| 12560 | /* 20459 */ "VCLZv8i8\000" |
| 12561 | /* 20468 */ "VSHLiv8i8\000" |
| 12562 | /* 20478 */ "VQSHLsiv8i8\000" |
| 12563 | /* 20490 */ "VQSHLuiv8i8\000" |
| 12564 | /* 20502 */ "VABAsv8i8\000" |
| 12565 | /* 20512 */ "VRSRAsv8i8\000" |
| 12566 | /* 20523 */ "VSRAsv8i8\000" |
| 12567 | /* 20533 */ "VHSUBsv8i8\000" |
| 12568 | /* 20544 */ "VQSUBsv8i8\000" |
| 12569 | /* 20555 */ "VABDsv8i8\000" |
| 12570 | /* 20565 */ "VRHADDsv8i8\000" |
| 12571 | /* 20577 */ "VHADDsv8i8\000" |
| 12572 | /* 20588 */ "VQADDsv8i8\000" |
| 12573 | /* 20599 */ "VCGEsv8i8\000" |
| 12574 | /* 20609 */ "VPADALsv8i8\000" |
| 12575 | /* 20621 */ "VPADDLsv8i8\000" |
| 12576 | /* 20633 */ "VQSHLsv8i8\000" |
| 12577 | /* 20644 */ "VQRSHLsv8i8\000" |
| 12578 | /* 20656 */ "VRSHLsv8i8\000" |
| 12579 | /* 20667 */ "VSHLsv8i8\000" |
| 12580 | /* 20677 */ "VMINsv8i8\000" |
| 12581 | /* 20687 */ "VQSHRNsv8i8\000" |
| 12582 | /* 20699 */ "VQRSHRNsv8i8\000" |
| 12583 | /* 20712 */ "VQMOVNsv8i8\000" |
| 12584 | /* 20724 */ "VRSHRsv8i8\000" |
| 12585 | /* 20735 */ "VSHRsv8i8\000" |
| 12586 | /* 20745 */ "VCGTsv8i8\000" |
| 12587 | /* 20755 */ "VMAXsv8i8\000" |
| 12588 | /* 20765 */ "VABAuv8i8\000" |
| 12589 | /* 20775 */ "VRSRAuv8i8\000" |
| 12590 | /* 20786 */ "VSRAuv8i8\000" |
| 12591 | /* 20796 */ "VHSUBuv8i8\000" |
| 12592 | /* 20807 */ "VQSUBuv8i8\000" |
| 12593 | /* 20818 */ "VABDuv8i8\000" |
| 12594 | /* 20828 */ "VRHADDuv8i8\000" |
| 12595 | /* 20840 */ "VHADDuv8i8\000" |
| 12596 | /* 20851 */ "VQADDuv8i8\000" |
| 12597 | /* 20862 */ "VCGEuv8i8\000" |
| 12598 | /* 20872 */ "VPADALuv8i8\000" |
| 12599 | /* 20884 */ "VPADDLuv8i8\000" |
| 12600 | /* 20896 */ "VQSHLuv8i8\000" |
| 12601 | /* 20907 */ "VQRSHLuv8i8\000" |
| 12602 | /* 20919 */ "VRSHLuv8i8\000" |
| 12603 | /* 20930 */ "VSHLuv8i8\000" |
| 12604 | /* 20940 */ "VMINuv8i8\000" |
| 12605 | /* 20950 */ "VQSHRNuv8i8\000" |
| 12606 | /* 20962 */ "VQRSHRNuv8i8\000" |
| 12607 | /* 20975 */ "VQMOVNuv8i8\000" |
| 12608 | /* 20987 */ "VRSHRuv8i8\000" |
| 12609 | /* 20998 */ "VSHRuv8i8\000" |
| 12610 | /* 21008 */ "VCGTuv8i8\000" |
| 12611 | /* 21018 */ "VMAXuv8i8\000" |
| 12612 | /* 21028 */ "VQSHLsuv8i8\000" |
| 12613 | /* 21040 */ "VQMOVNsuv8i8\000" |
| 12614 | /* 21053 */ "VCGEzv8i8\000" |
| 12615 | /* 21063 */ "VCLEzv8i8\000" |
| 12616 | /* 21073 */ "VCEQzv8i8\000" |
| 12617 | /* 21083 */ "VCGTzv8i8\000" |
| 12618 | /* 21093 */ "VCLTzv8i8\000" |
| 12619 | /* 21103 */ "t2LDRBi8\000" |
| 12620 | /* 21112 */ "t2STRBi8\000" |
| 12621 | /* 21121 */ "t2LDRSBi8\000" |
| 12622 | /* 21131 */ "MVE_VSUBi8\000" |
| 12623 | /* 21142 */ "tSUBi8\000" |
| 12624 | /* 21149 */ "MVE_VCADDi8\000" |
| 12625 | /* 21161 */ "VPADDi8\000" |
| 12626 | /* 21169 */ "MVE_VADDi8\000" |
| 12627 | /* 21180 */ "tADDi8\000" |
| 12628 | /* 21187 */ "t2PLDi8\000" |
| 12629 | /* 21195 */ "t2LDRDi8\000" |
| 12630 | /* 21204 */ "t2STRDi8\000" |
| 12631 | /* 21213 */ "MVE_VQDMULHi8\000" |
| 12632 | /* 21227 */ "MVE_VQRDMULHi8\000" |
| 12633 | /* 21242 */ "t2LDRHi8\000" |
| 12634 | /* 21251 */ "t2STRHi8\000" |
| 12635 | /* 21260 */ "t2LDRSHi8\000" |
| 12636 | /* 21270 */ "t2PLIi8\000" |
| 12637 | /* 21278 */ "VSHLLi8\000" |
| 12638 | /* 21286 */ "MVE_VMULi8\000" |
| 12639 | /* 21297 */ "VSETLNi8\000" |
| 12640 | /* 21306 */ "MVE_VCMPi8\000" |
| 12641 | /* 21317 */ "tCMPi8\000" |
| 12642 | /* 21324 */ "t2LDRi8\000" |
| 12643 | /* 21332 */ "t2STRi8\000" |
| 12644 | /* 21340 */ "tSUBSi8\000" |
| 12645 | /* 21348 */ "tADDSi8\000" |
| 12646 | /* 21356 */ "tMOVi8\000" |
| 12647 | /* 21363 */ "t2PLDWi8\000" |
| 12648 | /* 21372 */ "MVE_VMLA_qr_i8\000" |
| 12649 | /* 21387 */ "MVE_VSUB_qr_i8\000" |
| 12650 | /* 21402 */ "MVE_VADD_qr_i8\000" |
| 12651 | /* 21417 */ "MVE_VMUL_qr_i8\000" |
| 12652 | /* 21432 */ "MVE_VMLAS_qr_i8\000" |
| 12653 | /* 21448 */ "MVE_VMOVimmi8\000" |
| 12654 | /* 21462 */ "MVE_VSHL_immi8\000" |
| 12655 | /* 21477 */ "MVE_VSLIimm8\000" |
| 12656 | /* 21490 */ "MVE_VSRIimm8\000" |
| 12657 | /* 21503 */ "MVE_VMULLBp8\000" |
| 12658 | /* 21516 */ "VMULLp8\000" |
| 12659 | /* 21524 */ "MVE_VMULLTp8\000" |
| 12660 | /* 21537 */ "VLD1q8\000" |
| 12661 | /* 21544 */ "VST1q8\000" |
| 12662 | /* 21551 */ "VREV32q8\000" |
| 12663 | /* 21560 */ "VLD2q8\000" |
| 12664 | /* 21567 */ "VST2q8\000" |
| 12665 | /* 21574 */ "VLD3q8\000" |
| 12666 | /* 21581 */ "VST3q8\000" |
| 12667 | /* 21588 */ "VREV64q8\000" |
| 12668 | /* 21597 */ "VLD4q8\000" |
| 12669 | /* 21604 */ "VST4q8\000" |
| 12670 | /* 21611 */ "VREV16q8\000" |
| 12671 | /* 21620 */ "VTRNq8\000" |
| 12672 | /* 21627 */ "VZIPq8\000" |
| 12673 | /* 21634 */ "VLD1DUPq8\000" |
| 12674 | /* 21644 */ "VLD3DUPq8\000" |
| 12675 | /* 21654 */ "VLD4DUPq8\000" |
| 12676 | /* 21664 */ "VUZPq8\000" |
| 12677 | /* 21671 */ "VEXTq8\000" |
| 12678 | /* 21678 */ "MVE_VPTv16s8\000" |
| 12679 | /* 21691 */ "MVE_VMINAs8\000" |
| 12680 | /* 21703 */ "MVE_VMAXAs8\000" |
| 12681 | /* 21715 */ "MVE_VMULLBs8\000" |
| 12682 | /* 21728 */ "MVE_VHSUBs8\000" |
| 12683 | /* 21740 */ "MVE_VQSUBs8\000" |
| 12684 | /* 21752 */ "MVE_VABDs8\000" |
| 12685 | /* 21763 */ "MVE_VHCADDs8\000" |
| 12686 | /* 21776 */ "MVE_VRHADDs8\000" |
| 12687 | /* 21789 */ "MVE_VHADDs8\000" |
| 12688 | /* 21801 */ "MVE_VQADDs8\000" |
| 12689 | /* 21813 */ "MVE_VQNEGs8\000" |
| 12690 | /* 21825 */ "MVE_VNEGs8\000" |
| 12691 | /* 21836 */ "MVE_VQDMLADHs8\000" |
| 12692 | /* 21851 */ "MVE_VQRDMLADHs8\000" |
| 12693 | /* 21867 */ "MVE_VQDMLSDHs8\000" |
| 12694 | /* 21882 */ "MVE_VQRDMLSDHs8\000" |
| 12695 | /* 21898 */ "MVE_VRMULHs8\000" |
| 12696 | /* 21911 */ "MVE_VMULHs8\000" |
| 12697 | /* 21923 */ "VPMINs8\000" |
| 12698 | /* 21931 */ "MVE_VMINs8\000" |
| 12699 | /* 21942 */ "VGETLNs8\000" |
| 12700 | /* 21951 */ "MVE_VCMPs8\000" |
| 12701 | /* 21962 */ "MVE_VQABSs8\000" |
| 12702 | /* 21974 */ "MVE_VABSs8\000" |
| 12703 | /* 21985 */ "MVE_VCLSs8\000" |
| 12704 | /* 21996 */ "MVE_VMULLTs8\000" |
| 12705 | /* 22009 */ "MVE_VABAVs8\000" |
| 12706 | /* 22021 */ "MVE_VMLADAVs8\000" |
| 12707 | /* 22035 */ "MVE_VMLSDAVs8\000" |
| 12708 | /* 22049 */ "MVE_VMINAVs8\000" |
| 12709 | /* 22062 */ "MVE_VMAXAVs8\000" |
| 12710 | /* 22075 */ "MVE_VMINVs8\000" |
| 12711 | /* 22087 */ "MVE_VMAXVs8\000" |
| 12712 | /* 22099 */ "VPMAXs8\000" |
| 12713 | /* 22107 */ "MVE_VMAXs8\000" |
| 12714 | /* 22118 */ "MVE_VQDMLADHXs8\000" |
| 12715 | /* 22134 */ "MVE_VQRDMLADHXs8\000" |
| 12716 | /* 22151 */ "MVE_VQDMLSDHXs8\000" |
| 12717 | /* 22167 */ "MVE_VQRDMLSDHXs8\000" |
| 12718 | /* 22184 */ "MVE_VCLZs8\000" |
| 12719 | /* 22195 */ "MVE_VMOV_from_lane_s8\000" |
| 12720 | /* 22217 */ "MVE_VHSUB_qr_s8\000" |
| 12721 | /* 22233 */ "MVE_VQSUB_qr_s8\000" |
| 12722 | /* 22249 */ "MVE_VHADD_qr_s8\000" |
| 12723 | /* 22265 */ "MVE_VQADD_qr_s8\000" |
| 12724 | /* 22281 */ "MVE_VQDMULH_qr_s8\000" |
| 12725 | /* 22299 */ "MVE_VQRDMULH_qr_s8\000" |
| 12726 | /* 22318 */ "MVE_VMLADAVas8\000" |
| 12727 | /* 22333 */ "MVE_VMLSDAVas8\000" |
| 12728 | /* 22348 */ "MVE_VQSHL_by_vecs8\000" |
| 12729 | /* 22367 */ "MVE_VQRSHL_by_vecs8\000" |
| 12730 | /* 22387 */ "MVE_VRSHL_by_vecs8\000" |
| 12731 | /* 22406 */ "MVE_VSHL_by_vecs8\000" |
| 12732 | /* 22424 */ "MVE_VQSHLimms8\000" |
| 12733 | /* 22439 */ "MVE_VRSHR_imms8\000" |
| 12734 | /* 22455 */ "MVE_VSHR_imms8\000" |
| 12735 | /* 22470 */ "MVE_VQSHLU_imms8\000" |
| 12736 | /* 22487 */ "MVE_VQDMLAH_qrs8\000" |
| 12737 | /* 22504 */ "MVE_VQRDMLAH_qrs8\000" |
| 12738 | /* 22522 */ "MVE_VQDMLASH_qrs8\000" |
| 12739 | /* 22540 */ "MVE_VQRDMLASH_qrs8\000" |
| 12740 | /* 22559 */ "MVE_VQSHL_qrs8\000" |
| 12741 | /* 22574 */ "MVE_VQRSHL_qrs8\000" |
| 12742 | /* 22590 */ "MVE_VRSHL_qrs8\000" |
| 12743 | /* 22605 */ "MVE_VSHL_qrs8\000" |
| 12744 | /* 22619 */ "MVE_VMLADAVxs8\000" |
| 12745 | /* 22634 */ "MVE_VMLSDAVxs8\000" |
| 12746 | /* 22649 */ "MVE_VMLADAVaxs8\000" |
| 12747 | /* 22665 */ "MVE_VMLSDAVaxs8\000" |
| 12748 | /* 22681 */ "MVE_VPTv16u8\000" |
| 12749 | /* 22694 */ "MVE_VMULLBu8\000" |
| 12750 | /* 22707 */ "MVE_VHSUBu8\000" |
| 12751 | /* 22719 */ "MVE_VQSUBu8\000" |
| 12752 | /* 22731 */ "MVE_VABDu8\000" |
| 12753 | /* 22742 */ "MVE_VRHADDu8\000" |
| 12754 | /* 22755 */ "MVE_VHADDu8\000" |
| 12755 | /* 22767 */ "MVE_VQADDu8\000" |
| 12756 | /* 22779 */ "MVE_VRMULHu8\000" |
| 12757 | /* 22792 */ "MVE_VMULHu8\000" |
| 12758 | /* 22804 */ "VPMINu8\000" |
| 12759 | /* 22812 */ "MVE_VMINu8\000" |
| 12760 | /* 22823 */ "VGETLNu8\000" |
| 12761 | /* 22832 */ "MVE_VCMPu8\000" |
| 12762 | /* 22843 */ "MVE_VDDUPu8\000" |
| 12763 | /* 22855 */ "MVE_VIDUPu8\000" |
| 12764 | /* 22867 */ "MVE_VDWDUPu8\000" |
| 12765 | /* 22880 */ "MVE_VIWDUPu8\000" |
| 12766 | /* 22893 */ "MVE_VMULLTu8\000" |
| 12767 | /* 22906 */ "MVE_VABAVu8\000" |
| 12768 | /* 22918 */ "MVE_VMLADAVu8\000" |
| 12769 | /* 22932 */ "MVE_VMINVu8\000" |
| 12770 | /* 22944 */ "MVE_VMAXVu8\000" |
| 12771 | /* 22956 */ "VPMAXu8\000" |
| 12772 | /* 22964 */ "MVE_VMAXu8\000" |
| 12773 | /* 22975 */ "MVE_VMOV_from_lane_u8\000" |
| 12774 | /* 22997 */ "MVE_VHSUB_qr_u8\000" |
| 12775 | /* 23013 */ "MVE_VQSUB_qr_u8\000" |
| 12776 | /* 23029 */ "MVE_VHADD_qr_u8\000" |
| 12777 | /* 23045 */ "MVE_VQADD_qr_u8\000" |
| 12778 | /* 23061 */ "MVE_VMLADAVau8\000" |
| 12779 | /* 23076 */ "MVE_VQSHL_by_vecu8\000" |
| 12780 | /* 23095 */ "MVE_VQRSHL_by_vecu8\000" |
| 12781 | /* 23115 */ "MVE_VRSHL_by_vecu8\000" |
| 12782 | /* 23134 */ "MVE_VSHL_by_vecu8\000" |
| 12783 | /* 23152 */ "MVE_VQSHLimmu8\000" |
| 12784 | /* 23167 */ "MVE_VRSHR_immu8\000" |
| 12785 | /* 23183 */ "MVE_VSHR_immu8\000" |
| 12786 | /* 23198 */ "MVE_VQSHL_qru8\000" |
| 12787 | /* 23213 */ "MVE_VQRSHL_qru8\000" |
| 12788 | /* 23229 */ "MVE_VRSHL_qru8\000" |
| 12789 | /* 23244 */ "MVE_VSHL_qru8\000" |
| 12790 | /* 23258 */ "CDE_CX1A\000" |
| 12791 | /* 23267 */ "MVE_VRINTf32A\000" |
| 12792 | /* 23281 */ "CDE_CX2A\000" |
| 12793 | /* 23290 */ "CDE_CX3A\000" |
| 12794 | /* 23299 */ "MVE_VRINTf16A\000" |
| 12795 | /* 23313 */ "CDE_CX1DA\000" |
| 12796 | /* 23323 */ "CDE_CX2DA\000" |
| 12797 | /* 23333 */ "CDE_CX3DA\000" |
| 12798 | /* 23343 */ "RFEDA\000" |
| 12799 | /* 23349 */ "t2LDA\000" |
| 12800 | /* 23355 */ "sysLDMDA\000" |
| 12801 | /* 23364 */ "sysSTMDA\000" |
| 12802 | /* 23373 */ "SRSDA\000" |
| 12803 | /* 23379 */ "VLDMDIA\000" |
| 12804 | /* 23387 */ "VSTMDIA\000" |
| 12805 | /* 23395 */ "t2RFEIA\000" |
| 12806 | /* 23403 */ "t2LDMIA\000" |
| 12807 | /* 23411 */ "sysLDMIA\000" |
| 12808 | /* 23420 */ "tLDMIA\000" |
| 12809 | /* 23427 */ "t2STMIA\000" |
| 12810 | /* 23435 */ "sysSTMIA\000" |
| 12811 | /* 23444 */ "VLDMQIA\000" |
| 12812 | /* 23452 */ "VSTMQIA\000" |
| 12813 | /* 23460 */ "VLDMSIA\000" |
| 12814 | /* 23468 */ "VSTMSIA\000" |
| 12815 | /* 23476 */ "t2SRSIA\000" |
| 12816 | /* 23484 */ "FLDMXIA\000" |
| 12817 | /* 23492 */ "FSTMXIA\000" |
| 12818 | /* 23500 */ "t2MLA\000" |
| 12819 | /* 23506 */ "t2SMMLA\000" |
| 12820 | /* 23514 */ "VUSMMLA\000" |
| 12821 | /* 23522 */ "VSMMLA\000" |
| 12822 | /* 23529 */ "VUMMLA\000" |
| 12823 | /* 23536 */ "VMMLA\000" |
| 12824 | /* 23542 */ "G_FMA\000" |
| 12825 | /* 23548 */ "G_STRICT_FMA\000" |
| 12826 | /* 23561 */ "t2TTA\000" |
| 12827 | /* 23567 */ "t2CRC32B\000" |
| 12828 | /* 23576 */ "t2B\000" |
| 12829 | /* 23580 */ "t2LDAB\000" |
| 12830 | /* 23587 */ "t2SXTAB\000" |
| 12831 | /* 23595 */ "t2UXTAB\000" |
| 12832 | /* 23603 */ "t2SMLABB\000" |
| 12833 | /* 23612 */ "t2SMLALBB\000" |
| 12834 | /* 23622 */ "t2SMULBB\000" |
| 12835 | /* 23631 */ "t2TBB\000" |
| 12836 | /* 23637 */ "JUMPTABLE_TBB\000" |
| 12837 | /* 23651 */ "t2SpeculationBarrierISBDSBEndBB\000" |
| 12838 | /* 23683 */ "t2SpeculationBarrierSBEndBB\000" |
| 12839 | /* 23711 */ "t2CRC32CB\000" |
| 12840 | /* 23721 */ "t2RFEDB\000" |
| 12841 | /* 23729 */ "t2LDMDB\000" |
| 12842 | /* 23737 */ "sysLDMDB\000" |
| 12843 | /* 23746 */ "t2STMDB\000" |
| 12844 | /* 23754 */ "sysSTMDB\000" |
| 12845 | /* 23763 */ "t2SRSDB\000" |
| 12846 | /* 23771 */ "RFEIB\000" |
| 12847 | /* 23777 */ "sysLDMIB\000" |
| 12848 | /* 23786 */ "sysSTMIB\000" |
| 12849 | /* 23795 */ "SRSIB\000" |
| 12850 | /* 23801 */ "t2STLB\000" |
| 12851 | /* 23808 */ "t2DMB\000" |
| 12852 | /* 23814 */ "SWPB\000" |
| 12853 | /* 23819 */ "PICLDRB\000" |
| 12854 | /* 23827 */ "PICSTRB\000" |
| 12855 | /* 23835 */ "t2SB\000" |
| 12856 | /* 23840 */ "t2DSB\000" |
| 12857 | /* 23846 */ "t2ISB\000" |
| 12858 | /* 23852 */ "PICLDRSB\000" |
| 12859 | /* 23861 */ "tLDRSB\000" |
| 12860 | /* 23868 */ "tRSB\000" |
| 12861 | /* 23873 */ "t2TSB\000" |
| 12862 | /* 23879 */ "t2SMLATB\000" |
| 12863 | /* 23888 */ "t2PKHTB\000" |
| 12864 | /* 23896 */ "t2SMLALTB\000" |
| 12865 | /* 23906 */ "t2SMULTB\000" |
| 12866 | /* 23915 */ "BF16_VCVTB\000" |
| 12867 | /* 23926 */ "t2SXTB\000" |
| 12868 | /* 23933 */ "tSXTB\000" |
| 12869 | /* 23939 */ "t2UXTB\000" |
| 12870 | /* 23946 */ "tUXTB\000" |
| 12871 | /* 23952 */ "t2QDSUB\000" |
| 12872 | /* 23960 */ "G_FSUB\000" |
| 12873 | /* 23967 */ "G_STRICT_FSUB\000" |
| 12874 | /* 23981 */ "G_ATOMICRMW_FSUB\000" |
| 12875 | /* 23998 */ "t2QSUB\000" |
| 12876 | /* 24005 */ "G_SUB\000" |
| 12877 | /* 24011 */ "G_ATOMICRMW_SUB\000" |
| 12878 | /* 24027 */ "t2SMLAWB\000" |
| 12879 | /* 24036 */ "t2SMULWB\000" |
| 12880 | /* 24045 */ "t2LDAEXB\000" |
| 12881 | /* 24054 */ "t2STLEXB\000" |
| 12882 | /* 24063 */ "t2LDREXB\000" |
| 12883 | /* 24072 */ "t2STREXB\000" |
| 12884 | /* 24081 */ "tB\000" |
| 12885 | /* 24084 */ "SHA1C\000" |
| 12886 | /* 24090 */ "t2PAC\000" |
| 12887 | /* 24096 */ "MVE_VSBC\000" |
| 12888 | /* 24105 */ "tSBC\000" |
| 12889 | /* 24110 */ "MVE_VADC\000" |
| 12890 | /* 24119 */ "tADC\000" |
| 12891 | /* 24124 */ "t2BFC\000" |
| 12892 | /* 24130 */ "MVE_VBIC\000" |
| 12893 | /* 24139 */ "tBIC\000" |
| 12894 | /* 24144 */ "G_INTRINSIC\000" |
| 12895 | /* 24156 */ "MVE_VSHLC\000" |
| 12896 | /* 24166 */ "AESIMC\000" |
| 12897 | /* 24173 */ "t2SMC\000" |
| 12898 | /* 24179 */ "AESMC\000" |
| 12899 | /* 24185 */ "t2CSINC\000" |
| 12900 | /* 24193 */ "G_FPTRUNC\000" |
| 12901 | /* 24203 */ "G_INTRINSIC_TRUNC\000" |
| 12902 | /* 24221 */ "G_TRUNC\000" |
| 12903 | /* 24229 */ "G_BUILD_VECTOR_TRUNC\000" |
| 12904 | /* 24250 */ "G_DYN_STACKALLOC\000" |
| 12905 | /* 24267 */ "VMSR_FPSCR_NZCVQC\000" |
| 12906 | /* 24285 */ "VMRS_FPSCR_NZCVQC\000" |
| 12907 | /* 24303 */ "t2MRC\000" |
| 12908 | /* 24309 */ "t2MRRC\000" |
| 12909 | /* 24316 */ "MOVr_TC\000" |
| 12910 | /* 24324 */ "t2HVC\000" |
| 12911 | /* 24330 */ "tSVC\000" |
| 12912 | /* 24335 */ "VMSR_FPEXC\000" |
| 12913 | /* 24346 */ "VMRS_FPEXC\000" |
| 12914 | /* 24357 */ "CDE_CX1D\000" |
| 12915 | /* 24366 */ "CDE_CX2D\000" |
| 12916 | /* 24375 */ "CDE_CX3D\000" |
| 12917 | /* 24384 */ "VNMLAD\000" |
| 12918 | /* 24391 */ "t2SMLAD\000" |
| 12919 | /* 24399 */ "VMLAD\000" |
| 12920 | /* 24405 */ "VFMAD\000" |
| 12921 | /* 24411 */ "G_FMAD\000" |
| 12922 | /* 24418 */ "VFNMAD\000" |
| 12923 | /* 24425 */ "G_INDEXED_SEXTLOAD\000" |
| 12924 | /* 24444 */ "G_SEXTLOAD\000" |
| 12925 | /* 24455 */ "G_INDEXED_ZEXTLOAD\000" |
| 12926 | /* 24474 */ "G_ZEXTLOAD\000" |
| 12927 | /* 24485 */ "G_INDEXED_LOAD\000" |
| 12928 | /* 24500 */ "G_LOAD\000" |
| 12929 | /* 24507 */ "VRINTAD\000" |
| 12930 | /* 24515 */ "t2SMUAD\000" |
| 12931 | /* 24523 */ "VSUBD\000" |
| 12932 | /* 24529 */ "tPICADD\000" |
| 12933 | /* 24537 */ "t2QDADD\000" |
| 12934 | /* 24545 */ "G_VECREDUCE_FADD\000" |
| 12935 | /* 24562 */ "G_FADD\000" |
| 12936 | /* 24569 */ "G_VECREDUCE_SEQ_FADD\000" |
| 12937 | /* 24590 */ "G_STRICT_FADD\000" |
| 12938 | /* 24604 */ "G_ATOMICRMW_FADD\000" |
| 12939 | /* 24621 */ "t2QADD\000" |
| 12940 | /* 24628 */ "G_VECREDUCE_ADD\000" |
| 12941 | /* 24644 */ "G_ADD\000" |
| 12942 | /* 24650 */ "G_PTR_ADD\000" |
| 12943 | /* 24660 */ "G_ATOMICRMW_ADD\000" |
| 12944 | /* 24676 */ "VADDD\000" |
| 12945 | /* 24682 */ "VSELGED\000" |
| 12946 | /* 24690 */ "VCMPED\000" |
| 12947 | /* 24697 */ "VNEGD\000" |
| 12948 | /* 24703 */ "VCVTBHD\000" |
| 12949 | /* 24711 */ "VTOSHD\000" |
| 12950 | /* 24718 */ "VCVTTHD\000" |
| 12951 | /* 24726 */ "VTOUHD\000" |
| 12952 | /* 24733 */ "VMSR_FPSID\000" |
| 12953 | /* 24744 */ "VMRS_FPSID\000" |
| 12954 | /* 24755 */ "t2SMLALD\000" |
| 12955 | /* 24764 */ "VFMALD\000" |
| 12956 | /* 24771 */ "t2SMLSLD\000" |
| 12957 | /* 24780 */ "VFMSLD\000" |
| 12958 | /* 24787 */ "VTOSLD\000" |
| 12959 | /* 24794 */ "VNMULD\000" |
| 12960 | /* 24801 */ "VMULD\000" |
| 12961 | /* 24807 */ "VTOULD\000" |
| 12962 | /* 24814 */ "VFP_VMINNMD\000" |
| 12963 | /* 24826 */ "VFP_VMAXNMD\000" |
| 12964 | /* 24838 */ "VSCCLRMD\000" |
| 12965 | /* 24847 */ "VRINTMD\000" |
| 12966 | /* 24855 */ "G_ATOMICRMW_NAND\000" |
| 12967 | /* 24872 */ "MVE_VAND\000" |
| 12968 | /* 24881 */ "G_VECREDUCE_AND\000" |
| 12969 | /* 24897 */ "G_AND\000" |
| 12970 | /* 24903 */ "G_ATOMICRMW_AND\000" |
| 12971 | /* 24919 */ "tAND\000" |
| 12972 | /* 24924 */ "tSETEND\000" |
| 12973 | /* 24932 */ "LIFETIME_END\000" |
| 12974 | /* 24945 */ "tBRIND\000" |
| 12975 | /* 24952 */ "G_BRCOND\000" |
| 12976 | /* 24961 */ "G_ATOMICRMW_USUB_COND\000" |
| 12977 | /* 24983 */ "VRINTND\000" |
| 12978 | /* 24991 */ "G_LLROUND\000" |
| 12979 | /* 25001 */ "G_LROUND\000" |
| 12980 | /* 25010 */ "G_INTRINSIC_ROUND\000" |
| 12981 | /* 25028 */ "G_INTRINSIC_FPTRUNC_ROUND\000" |
| 12982 | /* 25054 */ "tTAILJMPdND\000" |
| 12983 | /* 25066 */ "VSHTOD\000" |
| 12984 | /* 25073 */ "VUHTOD\000" |
| 12985 | /* 25080 */ "VSITOD\000" |
| 12986 | /* 25087 */ "VUITOD\000" |
| 12987 | /* 25094 */ "VSLTOD\000" |
| 12988 | /* 25101 */ "VULTOD\000" |
| 12989 | /* 25108 */ "VCMPD\000" |
| 12990 | /* 25114 */ "VRINTPD\000" |
| 12991 | /* 25122 */ "VLD3d32_UPD\000" |
| 12992 | /* 25134 */ "VST3d32_UPD\000" |
| 12993 | /* 25146 */ "VLD4d32_UPD\000" |
| 12994 | /* 25158 */ "VST4d32_UPD\000" |
| 12995 | /* 25170 */ "VLD1LNd32_UPD\000" |
| 12996 | /* 25184 */ "VST1LNd32_UPD\000" |
| 12997 | /* 25198 */ "VLD2LNd32_UPD\000" |
| 12998 | /* 25212 */ "VST2LNd32_UPD\000" |
| 12999 | /* 25226 */ "VLD3LNd32_UPD\000" |
| 13000 | /* 25240 */ "VST3LNd32_UPD\000" |
| 13001 | /* 25254 */ "VLD4LNd32_UPD\000" |
| 13002 | /* 25268 */ "VST4LNd32_UPD\000" |
| 13003 | /* 25282 */ "VLD3DUPd32_UPD\000" |
| 13004 | /* 25297 */ "VLD4DUPd32_UPD\000" |
| 13005 | /* 25312 */ "VLD3q32_UPD\000" |
| 13006 | /* 25324 */ "VST3q32_UPD\000" |
| 13007 | /* 25336 */ "VLD4q32_UPD\000" |
| 13008 | /* 25348 */ "VST4q32_UPD\000" |
| 13009 | /* 25360 */ "VLD2LNq32_UPD\000" |
| 13010 | /* 25374 */ "VST2LNq32_UPD\000" |
| 13011 | /* 25388 */ "VLD3LNq32_UPD\000" |
| 13012 | /* 25402 */ "VST3LNq32_UPD\000" |
| 13013 | /* 25416 */ "VLD4LNq32_UPD\000" |
| 13014 | /* 25430 */ "VST4LNq32_UPD\000" |
| 13015 | /* 25444 */ "VLD3DUPq32_UPD\000" |
| 13016 | /* 25459 */ "VLD4DUPq32_UPD\000" |
| 13017 | /* 25474 */ "VLD3d16_UPD\000" |
| 13018 | /* 25486 */ "VST3d16_UPD\000" |
| 13019 | /* 25498 */ "VLD4d16_UPD\000" |
| 13020 | /* 25510 */ "VST4d16_UPD\000" |
| 13021 | /* 25522 */ "VLD1LNd16_UPD\000" |
| 13022 | /* 25536 */ "VST1LNd16_UPD\000" |
| 13023 | /* 25550 */ "VLD2LNd16_UPD\000" |
| 13024 | /* 25564 */ "VST2LNd16_UPD\000" |
| 13025 | /* 25578 */ "VLD3LNd16_UPD\000" |
| 13026 | /* 25592 */ "VST3LNd16_UPD\000" |
| 13027 | /* 25606 */ "VLD4LNd16_UPD\000" |
| 13028 | /* 25620 */ "VST4LNd16_UPD\000" |
| 13029 | /* 25634 */ "VLD3DUPd16_UPD\000" |
| 13030 | /* 25649 */ "VLD4DUPd16_UPD\000" |
| 13031 | /* 25664 */ "VLD3q16_UPD\000" |
| 13032 | /* 25676 */ "VST3q16_UPD\000" |
| 13033 | /* 25688 */ "VLD4q16_UPD\000" |
| 13034 | /* 25700 */ "VST4q16_UPD\000" |
| 13035 | /* 25712 */ "VLD2LNq16_UPD\000" |
| 13036 | /* 25726 */ "VST2LNq16_UPD\000" |
| 13037 | /* 25740 */ "VLD3LNq16_UPD\000" |
| 13038 | /* 25754 */ "VST3LNq16_UPD\000" |
| 13039 | /* 25768 */ "VLD4LNq16_UPD\000" |
| 13040 | /* 25782 */ "VST4LNq16_UPD\000" |
| 13041 | /* 25796 */ "VLD3DUPq16_UPD\000" |
| 13042 | /* 25811 */ "VLD4DUPq16_UPD\000" |
| 13043 | /* 25826 */ "VLD3d8_UPD\000" |
| 13044 | /* 25837 */ "VST3d8_UPD\000" |
| 13045 | /* 25848 */ "VLD4d8_UPD\000" |
| 13046 | /* 25859 */ "VST4d8_UPD\000" |
| 13047 | /* 25870 */ "VLD1LNd8_UPD\000" |
| 13048 | /* 25883 */ "VST1LNd8_UPD\000" |
| 13049 | /* 25896 */ "VLD2LNd8_UPD\000" |
| 13050 | /* 25909 */ "VST2LNd8_UPD\000" |
| 13051 | /* 25922 */ "VLD3LNd8_UPD\000" |
| 13052 | /* 25935 */ "VST3LNd8_UPD\000" |
| 13053 | /* 25948 */ "VLD4LNd8_UPD\000" |
| 13054 | /* 25961 */ "VST4LNd8_UPD\000" |
| 13055 | /* 25974 */ "VLD3DUPd8_UPD\000" |
| 13056 | /* 25988 */ "VLD4DUPd8_UPD\000" |
| 13057 | /* 26002 */ "VLD3q8_UPD\000" |
| 13058 | /* 26013 */ "VST3q8_UPD\000" |
| 13059 | /* 26024 */ "VLD4q8_UPD\000" |
| 13060 | /* 26035 */ "VST4q8_UPD\000" |
| 13061 | /* 26046 */ "VLD3DUPq8_UPD\000" |
| 13062 | /* 26060 */ "VLD4DUPq8_UPD\000" |
| 13063 | /* 26074 */ "RFEDA_UPD\000" |
| 13064 | /* 26084 */ "sysLDMDA_UPD\000" |
| 13065 | /* 26097 */ "sysSTMDA_UPD\000" |
| 13066 | /* 26110 */ "SRSDA_UPD\000" |
| 13067 | /* 26120 */ "VLDMDIA_UPD\000" |
| 13068 | /* 26132 */ "VSTMDIA_UPD\000" |
| 13069 | /* 26144 */ "RFEIA_UPD\000" |
| 13070 | /* 26154 */ "t2LDMIA_UPD\000" |
| 13071 | /* 26166 */ "sysLDMIA_UPD\000" |
| 13072 | /* 26179 */ "tLDMIA_UPD\000" |
| 13073 | /* 26190 */ "t2STMIA_UPD\000" |
| 13074 | /* 26202 */ "sysSTMIA_UPD\000" |
| 13075 | /* 26215 */ "tSTMIA_UPD\000" |
| 13076 | /* 26226 */ "VLDMSIA_UPD\000" |
| 13077 | /* 26238 */ "VSTMSIA_UPD\000" |
| 13078 | /* 26250 */ "t2SRSIA_UPD\000" |
| 13079 | /* 26262 */ "FLDMXIA_UPD\000" |
| 13080 | /* 26274 */ "FSTMXIA_UPD\000" |
| 13081 | /* 26286 */ "VLDMDDB_UPD\000" |
| 13082 | /* 26298 */ "VSTMDDB_UPD\000" |
| 13083 | /* 26310 */ "RFEDB_UPD\000" |
| 13084 | /* 26320 */ "t2LDMDB_UPD\000" |
| 13085 | /* 26332 */ "sysLDMDB_UPD\000" |
| 13086 | /* 26345 */ "t2STMDB_UPD\000" |
| 13087 | /* 26357 */ "sysSTMDB_UPD\000" |
| 13088 | /* 26370 */ "VLDMSDB_UPD\000" |
| 13089 | /* 26382 */ "VSTMSDB_UPD\000" |
| 13090 | /* 26394 */ "t2SRSDB_UPD\000" |
| 13091 | /* 26406 */ "FLDMXDB_UPD\000" |
| 13092 | /* 26418 */ "FSTMXDB_UPD\000" |
| 13093 | /* 26430 */ "RFEIB_UPD\000" |
| 13094 | /* 26440 */ "sysLDMIB_UPD\000" |
| 13095 | /* 26453 */ "sysSTMIB_UPD\000" |
| 13096 | /* 26466 */ "SRSIB_UPD\000" |
| 13097 | /* 26476 */ "VLD3d32Pseudo_UPD\000" |
| 13098 | /* 26494 */ "VST3d32Pseudo_UPD\000" |
| 13099 | /* 26512 */ "VLD4d32Pseudo_UPD\000" |
| 13100 | /* 26530 */ "VST4d32Pseudo_UPD\000" |
| 13101 | /* 26548 */ "VLD2LNd32Pseudo_UPD\000" |
| 13102 | /* 26568 */ "VST2LNd32Pseudo_UPD\000" |
| 13103 | /* 26588 */ "VLD3LNd32Pseudo_UPD\000" |
| 13104 | /* 26608 */ "VST3LNd32Pseudo_UPD\000" |
| 13105 | /* 26628 */ "VLD4LNd32Pseudo_UPD\000" |
| 13106 | /* 26648 */ "VST4LNd32Pseudo_UPD\000" |
| 13107 | /* 26668 */ "VLD3DUPd32Pseudo_UPD\000" |
| 13108 | /* 26689 */ "VLD4DUPd32Pseudo_UPD\000" |
| 13109 | /* 26710 */ "VLD3q32Pseudo_UPD\000" |
| 13110 | /* 26728 */ "VST3q32Pseudo_UPD\000" |
| 13111 | /* 26746 */ "VLD4q32Pseudo_UPD\000" |
| 13112 | /* 26764 */ "VST4q32Pseudo_UPD\000" |
| 13113 | /* 26782 */ "VLD1LNq32Pseudo_UPD\000" |
| 13114 | /* 26802 */ "VST1LNq32Pseudo_UPD\000" |
| 13115 | /* 26822 */ "VLD2LNq32Pseudo_UPD\000" |
| 13116 | /* 26842 */ "VST2LNq32Pseudo_UPD\000" |
| 13117 | /* 26862 */ "VLD3LNq32Pseudo_UPD\000" |
| 13118 | /* 26882 */ "VST3LNq32Pseudo_UPD\000" |
| 13119 | /* 26902 */ "VLD4LNq32Pseudo_UPD\000" |
| 13120 | /* 26922 */ "VST4LNq32Pseudo_UPD\000" |
| 13121 | /* 26942 */ "VLD3d16Pseudo_UPD\000" |
| 13122 | /* 26960 */ "VST3d16Pseudo_UPD\000" |
| 13123 | /* 26978 */ "VLD4d16Pseudo_UPD\000" |
| 13124 | /* 26996 */ "VST4d16Pseudo_UPD\000" |
| 13125 | /* 27014 */ "VLD2LNd16Pseudo_UPD\000" |
| 13126 | /* 27034 */ "VST2LNd16Pseudo_UPD\000" |
| 13127 | /* 27054 */ "VLD3LNd16Pseudo_UPD\000" |
| 13128 | /* 27074 */ "VST3LNd16Pseudo_UPD\000" |
| 13129 | /* 27094 */ "VLD4LNd16Pseudo_UPD\000" |
| 13130 | /* 27114 */ "VST4LNd16Pseudo_UPD\000" |
| 13131 | /* 27134 */ "VLD3DUPd16Pseudo_UPD\000" |
| 13132 | /* 27155 */ "VLD4DUPd16Pseudo_UPD\000" |
| 13133 | /* 27176 */ "VLD3q16Pseudo_UPD\000" |
| 13134 | /* 27194 */ "VST3q16Pseudo_UPD\000" |
| 13135 | /* 27212 */ "VLD4q16Pseudo_UPD\000" |
| 13136 | /* 27230 */ "VST4q16Pseudo_UPD\000" |
| 13137 | /* 27248 */ "VLD1LNq16Pseudo_UPD\000" |
| 13138 | /* 27268 */ "VST1LNq16Pseudo_UPD\000" |
| 13139 | /* 27288 */ "VLD2LNq16Pseudo_UPD\000" |
| 13140 | /* 27308 */ "VST2LNq16Pseudo_UPD\000" |
| 13141 | /* 27328 */ "VLD3LNq16Pseudo_UPD\000" |
| 13142 | /* 27348 */ "VST3LNq16Pseudo_UPD\000" |
| 13143 | /* 27368 */ "VLD4LNq16Pseudo_UPD\000" |
| 13144 | /* 27388 */ "VST4LNq16Pseudo_UPD\000" |
| 13145 | /* 27408 */ "VLD3d8Pseudo_UPD\000" |
| 13146 | /* 27425 */ "VST3d8Pseudo_UPD\000" |
| 13147 | /* 27442 */ "VLD4d8Pseudo_UPD\000" |
| 13148 | /* 27459 */ "VST4d8Pseudo_UPD\000" |
| 13149 | /* 27476 */ "VLD2LNd8Pseudo_UPD\000" |
| 13150 | /* 27495 */ "VST2LNd8Pseudo_UPD\000" |
| 13151 | /* 27514 */ "VLD3LNd8Pseudo_UPD\000" |
| 13152 | /* 27533 */ "VST3LNd8Pseudo_UPD\000" |
| 13153 | /* 27552 */ "VLD4LNd8Pseudo_UPD\000" |
| 13154 | /* 27571 */ "VST4LNd8Pseudo_UPD\000" |
| 13155 | /* 27590 */ "VLD3DUPd8Pseudo_UPD\000" |
| 13156 | /* 27610 */ "VLD4DUPd8Pseudo_UPD\000" |
| 13157 | /* 27630 */ "VLD3q8Pseudo_UPD\000" |
| 13158 | /* 27647 */ "VST3q8Pseudo_UPD\000" |
| 13159 | /* 27664 */ "VLD4q8Pseudo_UPD\000" |
| 13160 | /* 27681 */ "VST4q8Pseudo_UPD\000" |
| 13161 | /* 27698 */ "VLD1LNq8Pseudo_UPD\000" |
| 13162 | /* 27717 */ "VST1LNq8Pseudo_UPD\000" |
| 13163 | /* 27736 */ "VLD1q32HighQPseudo_UPD\000" |
| 13164 | /* 27759 */ "VST1q32HighQPseudo_UPD\000" |
| 13165 | /* 27782 */ "VLD1q64HighQPseudo_UPD\000" |
| 13166 | /* 27805 */ "VST1q64HighQPseudo_UPD\000" |
| 13167 | /* 27828 */ "VLD1q16HighQPseudo_UPD\000" |
| 13168 | /* 27851 */ "VST1q16HighQPseudo_UPD\000" |
| 13169 | /* 27874 */ "VLD1q8HighQPseudo_UPD\000" |
| 13170 | /* 27896 */ "VST1q8HighQPseudo_UPD\000" |
| 13171 | /* 27918 */ "VLD1q32LowQPseudo_UPD\000" |
| 13172 | /* 27940 */ "VST1q32LowQPseudo_UPD\000" |
| 13173 | /* 27962 */ "VLD1q64LowQPseudo_UPD\000" |
| 13174 | /* 27984 */ "VST1q64LowQPseudo_UPD\000" |
| 13175 | /* 28006 */ "VLD1q16LowQPseudo_UPD\000" |
| 13176 | /* 28028 */ "VST1q16LowQPseudo_UPD\000" |
| 13177 | /* 28050 */ "VLD1q8LowQPseudo_UPD\000" |
| 13178 | /* 28071 */ "VST1q8LowQPseudo_UPD\000" |
| 13179 | /* 28092 */ "VLD1q32HighTPseudo_UPD\000" |
| 13180 | /* 28115 */ "VST1q32HighTPseudo_UPD\000" |
| 13181 | /* 28138 */ "VLD1q64HighTPseudo_UPD\000" |
| 13182 | /* 28161 */ "VST1q64HighTPseudo_UPD\000" |
| 13183 | /* 28184 */ "VLD1q16HighTPseudo_UPD\000" |
| 13184 | /* 28207 */ "VST1q16HighTPseudo_UPD\000" |
| 13185 | /* 28230 */ "VLD1q8HighTPseudo_UPD\000" |
| 13186 | /* 28252 */ "VST1q8HighTPseudo_UPD\000" |
| 13187 | /* 28274 */ "VLD1q32LowTPseudo_UPD\000" |
| 13188 | /* 28296 */ "VST1q32LowTPseudo_UPD\000" |
| 13189 | /* 28318 */ "VLD1q64LowTPseudo_UPD\000" |
| 13190 | /* 28340 */ "VST1q64LowTPseudo_UPD\000" |
| 13191 | /* 28362 */ "VLD1q16LowTPseudo_UPD\000" |
| 13192 | /* 28384 */ "VST1q16LowTPseudo_UPD\000" |
| 13193 | /* 28406 */ "VLD1q8LowTPseudo_UPD\000" |
| 13194 | /* 28427 */ "VST1q8LowTPseudo_UPD\000" |
| 13195 | /* 28448 */ "VLD3DUPq32OddPseudo_UPD\000" |
| 13196 | /* 28472 */ "VLD4DUPq32OddPseudo_UPD\000" |
| 13197 | /* 28496 */ "VLD3DUPq16OddPseudo_UPD\000" |
| 13198 | /* 28520 */ "VLD4DUPq16OddPseudo_UPD\000" |
| 13199 | /* 28544 */ "VLD3DUPq8OddPseudo_UPD\000" |
| 13200 | /* 28567 */ "VLD4DUPq8OddPseudo_UPD\000" |
| 13201 | /* 28590 */ "VLD3q32oddPseudo_UPD\000" |
| 13202 | /* 28611 */ "VST3q32oddPseudo_UPD\000" |
| 13203 | /* 28632 */ "VLD4q32oddPseudo_UPD\000" |
| 13204 | /* 28653 */ "VST4q32oddPseudo_UPD\000" |
| 13205 | /* 28674 */ "VLD3q16oddPseudo_UPD\000" |
| 13206 | /* 28695 */ "VST3q16oddPseudo_UPD\000" |
| 13207 | /* 28716 */ "VLD4q16oddPseudo_UPD\000" |
| 13208 | /* 28737 */ "VST4q16oddPseudo_UPD\000" |
| 13209 | /* 28758 */ "VLD3q8oddPseudo_UPD\000" |
| 13210 | /* 28778 */ "VST3q8oddPseudo_UPD\000" |
| 13211 | /* 28798 */ "VLD4q8oddPseudo_UPD\000" |
| 13212 | /* 28818 */ "VST4q8oddPseudo_UPD\000" |
| 13213 | /* 28838 */ "VSELEQD\000" |
| 13214 | /* 28846 */ "LOAD_STACK_GUARD\000" |
| 13215 | /* 28863 */ "VLDRD\000" |
| 13216 | /* 28869 */ "VTOSIRD\000" |
| 13217 | /* 28877 */ "VTOUIRD\000" |
| 13218 | /* 28885 */ "VMOVRRD\000" |
| 13219 | /* 28893 */ "VRINTRD\000" |
| 13220 | /* 28901 */ "VSTRD\000" |
| 13221 | /* 28907 */ "VCVTASD\000" |
| 13222 | /* 28915 */ "VABSD\000" |
| 13223 | /* 28921 */ "AESD\000" |
| 13224 | /* 28926 */ "VNMLSD\000" |
| 13225 | /* 28933 */ "t2SMLSD\000" |
| 13226 | /* 28941 */ "VMLSD\000" |
| 13227 | /* 28947 */ "VFMSD\000" |
| 13228 | /* 28953 */ "VFNMSD\000" |
| 13229 | /* 28960 */ "VCVTMSD\000" |
| 13230 | /* 28968 */ "VCVTNSD\000" |
| 13231 | /* 28976 */ "VCVTPSD\000" |
| 13232 | /* 28984 */ "VCVTSD\000" |
| 13233 | /* 28991 */ "t2SMUSD\000" |
| 13234 | /* 28999 */ "VSELVSD\000" |
| 13235 | /* 29007 */ "VSELGTD\000" |
| 13236 | /* 29015 */ "VUSDOTD\000" |
| 13237 | /* 29023 */ "VSDOTD\000" |
| 13238 | /* 29030 */ "VUDOTD\000" |
| 13239 | /* 29037 */ "BF16VDOTI_VDOTD\000" |
| 13240 | /* 29053 */ "BF16VDOTS_VDOTD\000" |
| 13241 | /* 29069 */ "VSQRTD\000" |
| 13242 | /* 29076 */ "FCONSTD\000" |
| 13243 | /* 29084 */ "VCVTAUD\000" |
| 13244 | /* 29092 */ "VCVTMUD\000" |
| 13245 | /* 29100 */ "VCVTNUD\000" |
| 13246 | /* 29108 */ "VCVTPUD\000" |
| 13247 | /* 29116 */ "VDIVD\000" |
| 13248 | /* 29122 */ "VMOVD\000" |
| 13249 | /* 29128 */ "t2LDAEXD\000" |
| 13250 | /* 29137 */ "t2STLEXD\000" |
| 13251 | /* 29146 */ "t2LDREXD\000" |
| 13252 | /* 29155 */ "t2STREXD\000" |
| 13253 | /* 29164 */ "VRINTXD\000" |
| 13254 | /* 29172 */ "VCMPEZD\000" |
| 13255 | /* 29180 */ "VTOSIZD\000" |
| 13256 | /* 29188 */ "VTOUIZD\000" |
| 13257 | /* 29196 */ "VCMPZD\000" |
| 13258 | /* 29203 */ "VRINTZD\000" |
| 13259 | /* 29211 */ "PSEUDO_PROBE\000" |
| 13260 | /* 29224 */ "G_SSUBE\000" |
| 13261 | /* 29232 */ "G_USUBE\000" |
| 13262 | /* 29240 */ "SPACE\000" |
| 13263 | /* 29246 */ "G_FENCE\000" |
| 13264 | /* 29254 */ "ARITH_FENCE\000" |
| 13265 | /* 29266 */ "REG_SEQUENCE\000" |
| 13266 | /* 29279 */ "G_SADDE\000" |
| 13267 | /* 29287 */ "G_UADDE\000" |
| 13268 | /* 29295 */ "G_GET_FPMODE\000" |
| 13269 | /* 29308 */ "G_RESET_FPMODE\000" |
| 13270 | /* 29323 */ "G_SET_FPMODE\000" |
| 13271 | /* 29336 */ "G_FMINNUM_IEEE\000" |
| 13272 | /* 29351 */ "G_FMAXNUM_IEEE\000" |
| 13273 | /* 29366 */ "t2LE\000" |
| 13274 | /* 29371 */ "G_VSCALE\000" |
| 13275 | /* 29380 */ "G_JUMP_TABLE\000" |
| 13276 | /* 29393 */ "BUNDLE\000" |
| 13277 | /* 29400 */ "G_MEMCPY_INLINE\000" |
| 13278 | /* 29416 */ "LOCAL_ESCAPE\000" |
| 13279 | /* 29429 */ "G_STACKRESTORE\000" |
| 13280 | /* 29444 */ "G_INDEXED_STORE\000" |
| 13281 | /* 29460 */ "G_STORE\000" |
| 13282 | /* 29468 */ "t2LDC2_PRE\000" |
| 13283 | /* 29479 */ "t2STC2_PRE\000" |
| 13284 | /* 29490 */ "t2LDRB_PRE\000" |
| 13285 | /* 29501 */ "t2STRB_PRE\000" |
| 13286 | /* 29512 */ "t2LDRSB_PRE\000" |
| 13287 | /* 29524 */ "t2LDC_PRE\000" |
| 13288 | /* 29534 */ "t2STC_PRE\000" |
| 13289 | /* 29544 */ "t2LDRD_PRE\000" |
| 13290 | /* 29555 */ "t2STRD_PRE\000" |
| 13291 | /* 29566 */ "t2LDRH_PRE\000" |
| 13292 | /* 29577 */ "t2STRH_PRE\000" |
| 13293 | /* 29588 */ "t2LDRSH_PRE\000" |
| 13294 | /* 29600 */ "t2LDC2L_PRE\000" |
| 13295 | /* 29612 */ "t2STC2L_PRE\000" |
| 13296 | /* 29624 */ "t2LDCL_PRE\000" |
| 13297 | /* 29635 */ "t2STCL_PRE\000" |
| 13298 | /* 29646 */ "t2LDR_PRE\000" |
| 13299 | /* 29656 */ "t2STR_PRE\000" |
| 13300 | /* 29666 */ "AESE\000" |
| 13301 | /* 29671 */ "G_BITREVERSE\000" |
| 13302 | /* 29684 */ "FAKE_USE\000" |
| 13303 | /* 29693 */ "DBG_VALUE\000" |
| 13304 | /* 29703 */ "G_GLOBAL_VALUE\000" |
| 13305 | /* 29718 */ "G_PTRAUTH_GLOBAL_VALUE\000" |
| 13306 | /* 29741 */ "CONVERGENCECTRL_GLUE\000" |
| 13307 | /* 29762 */ "G_STACKSAVE\000" |
| 13308 | /* 29774 */ "G_MEMMOVE\000" |
| 13309 | /* 29784 */ "G_FREEZE\000" |
| 13310 | /* 29793 */ "G_FCANONICALIZE\000" |
| 13311 | /* 29809 */ "t2UDF\000" |
| 13312 | /* 29815 */ "tUDF\000" |
| 13313 | /* 29820 */ "G_CTLZ_ZERO_UNDEF\000" |
| 13314 | /* 29838 */ "G_CTTZ_ZERO_UNDEF\000" |
| 13315 | /* 29856 */ "INIT_UNDEF\000" |
| 13316 | /* 29867 */ "G_IMPLICIT_DEF\000" |
| 13317 | /* 29882 */ "DBG_INSTR_REF\000" |
| 13318 | /* 29896 */ "t2DBG\000" |
| 13319 | /* 29902 */ "t2PACG\000" |
| 13320 | /* 29909 */ "G_FNEG\000" |
| 13321 | /* 29916 */ "t2CSNEG\000" |
| 13322 | /* 29924 */ "EXTRACT_SUBREG\000" |
| 13323 | /* 29939 */ "INSERT_SUBREG\000" |
| 13324 | /* 29953 */ "G_SEXT_INREG\000" |
| 13325 | /* 29966 */ "LDRB_PRE_REG\000" |
| 13326 | /* 29979 */ "STRB_PRE_REG\000" |
| 13327 | /* 29992 */ "LDR_PRE_REG\000" |
| 13328 | /* 30004 */ "STR_PRE_REG\000" |
| 13329 | /* 30016 */ "SUBREG_TO_REG\000" |
| 13330 | /* 30030 */ "LDRB_POST_REG\000" |
| 13331 | /* 30044 */ "STRB_POST_REG\000" |
| 13332 | /* 30058 */ "LDR_POST_REG\000" |
| 13333 | /* 30071 */ "STR_POST_REG\000" |
| 13334 | /* 30084 */ "LDRBT_POST_REG\000" |
| 13335 | /* 30099 */ "STRBT_POST_REG\000" |
| 13336 | /* 30114 */ "LDRT_POST_REG\000" |
| 13337 | /* 30128 */ "STRT_POST_REG\000" |
| 13338 | /* 30142 */ "G_ATOMIC_CMPXCHG\000" |
| 13339 | /* 30159 */ "G_ATOMICRMW_XCHG\000" |
| 13340 | /* 30176 */ "G_FLOG\000" |
| 13341 | /* 30183 */ "G_VAARG\000" |
| 13342 | /* 30191 */ "PREALLOCATED_ARG\000" |
| 13343 | /* 30208 */ "t2SG\000" |
| 13344 | /* 30213 */ "t2AUTG\000" |
| 13345 | /* 30220 */ "SHA1H\000" |
| 13346 | /* 30226 */ "t2CRC32H\000" |
| 13347 | /* 30235 */ "SHA256H\000" |
| 13348 | /* 30243 */ "t2LDAH\000" |
| 13349 | /* 30250 */ "VNMLAH\000" |
| 13350 | /* 30257 */ "VMLAH\000" |
| 13351 | /* 30263 */ "VFMAH\000" |
| 13352 | /* 30269 */ "VFNMAH\000" |
| 13353 | /* 30276 */ "VRINTAH\000" |
| 13354 | /* 30284 */ "t2SXTAH\000" |
| 13355 | /* 30292 */ "t2UXTAH\000" |
| 13356 | /* 30300 */ "t2TBH\000" |
| 13357 | /* 30306 */ "JUMPTABLE_TBH\000" |
| 13358 | /* 30320 */ "VSUBH\000" |
| 13359 | /* 30326 */ "t2CRC32CH\000" |
| 13360 | /* 30336 */ "G_PREFETCH\000" |
| 13361 | /* 30347 */ "VCVTBDH\000" |
| 13362 | /* 30355 */ "VADDH\000" |
| 13363 | /* 30361 */ "VCVTTDH\000" |
| 13364 | /* 30369 */ "VSELGEH\000" |
| 13365 | /* 30377 */ "VCMPEH\000" |
| 13366 | /* 30384 */ "VNEGH\000" |
| 13367 | /* 30390 */ "VTOSHH\000" |
| 13368 | /* 30397 */ "VTOUHH\000" |
| 13369 | /* 30404 */ "VTOSLH\000" |
| 13370 | /* 30411 */ "t2STLH\000" |
| 13371 | /* 30418 */ "VNMULH\000" |
| 13372 | /* 30425 */ "G_SMULH\000" |
| 13373 | /* 30433 */ "G_UMULH\000" |
| 13374 | /* 30441 */ "VMULH\000" |
| 13375 | /* 30447 */ "VTOULH\000" |
| 13376 | /* 30454 */ "VFP_VMINNMH\000" |
| 13377 | /* 30466 */ "VFP_VMAXNMH\000" |
| 13378 | /* 30478 */ "VRINTMH\000" |
| 13379 | /* 30486 */ "G_FTANH\000" |
| 13380 | /* 30494 */ "G_FSINH\000" |
| 13381 | /* 30502 */ "VRINTNH\000" |
| 13382 | /* 30510 */ "VSHTOH\000" |
| 13383 | /* 30517 */ "VUHTOH\000" |
| 13384 | /* 30524 */ "VSITOH\000" |
| 13385 | /* 30531 */ "VUITOH\000" |
| 13386 | /* 30538 */ "VSLTOH\000" |
| 13387 | /* 30545 */ "VULTOH\000" |
| 13388 | /* 30552 */ "VCMPH\000" |
| 13389 | /* 30558 */ "VRINTPH\000" |
| 13390 | /* 30566 */ "VSELEQH\000" |
| 13391 | /* 30574 */ "PICLDRH\000" |
| 13392 | /* 30582 */ "VLDRH\000" |
| 13393 | /* 30588 */ "VTOSIRH\000" |
| 13394 | /* 30596 */ "VTOUIRH\000" |
| 13395 | /* 30604 */ "VRINTRH\000" |
| 13396 | /* 30612 */ "PICSTRH\000" |
| 13397 | /* 30620 */ "VSTRH\000" |
| 13398 | /* 30626 */ "VMOVRH\000" |
| 13399 | /* 30633 */ "VCVTASH\000" |
| 13400 | /* 30641 */ "VABSH\000" |
| 13401 | /* 30647 */ "VCVTBSH\000" |
| 13402 | /* 30655 */ "VNMLSH\000" |
| 13403 | /* 30662 */ "VMLSH\000" |
| 13404 | /* 30668 */ "VFMSH\000" |
| 13405 | /* 30674 */ "VFNMSH\000" |
| 13406 | /* 30681 */ "VCVTMSH\000" |
| 13407 | /* 30689 */ "VINSH\000" |
| 13408 | /* 30695 */ "VCVTNSH\000" |
| 13409 | /* 30703 */ "G_FCOSH\000" |
| 13410 | /* 30711 */ "VCVTPSH\000" |
| 13411 | /* 30719 */ "PICLDRSH\000" |
| 13412 | /* 30728 */ "tLDRSH\000" |
| 13413 | /* 30735 */ "VCVTTSH\000" |
| 13414 | /* 30743 */ "tPUSH\000" |
| 13415 | /* 30749 */ "t2REVSH\000" |
| 13416 | /* 30757 */ "tREVSH\000" |
| 13417 | /* 30764 */ "VSELVSH\000" |
| 13418 | /* 30772 */ "VSELGTH\000" |
| 13419 | /* 30780 */ "VSQRTH\000" |
| 13420 | /* 30787 */ "FCONSTH\000" |
| 13421 | /* 30795 */ "t2SXTH\000" |
| 13422 | /* 30802 */ "tSXTH\000" |
| 13423 | /* 30808 */ "t2UXTH\000" |
| 13424 | /* 30815 */ "tUXTH\000" |
| 13425 | /* 30821 */ "VCVTAUH\000" |
| 13426 | /* 30829 */ "VCVTMUH\000" |
| 13427 | /* 30837 */ "VCVTNUH\000" |
| 13428 | /* 30845 */ "VCVTPUH\000" |
| 13429 | /* 30853 */ "VDIVH\000" |
| 13430 | /* 30859 */ "VMOVH\000" |
| 13431 | /* 30865 */ "t2LDAEXH\000" |
| 13432 | /* 30874 */ "t2STLEXH\000" |
| 13433 | /* 30883 */ "t2LDREXH\000" |
| 13434 | /* 30892 */ "t2STREXH\000" |
| 13435 | /* 30901 */ "VRINTXH\000" |
| 13436 | /* 30909 */ "VCMPEZH\000" |
| 13437 | /* 30917 */ "VTOSIZH\000" |
| 13438 | /* 30925 */ "VTOUIZH\000" |
| 13439 | /* 30933 */ "VCMPZH\000" |
| 13440 | /* 30940 */ "VRINTZH\000" |
| 13441 | /* 30948 */ "MVE_VSBCI\000" |
| 13442 | /* 30958 */ "MVE_VADCI\000" |
| 13443 | /* 30968 */ "VFMALDI\000" |
| 13444 | /* 30976 */ "VFMSLDI\000" |
| 13445 | /* 30984 */ "VUSDOTDI\000" |
| 13446 | /* 30993 */ "VSDOTDI\000" |
| 13447 | /* 31001 */ "VSUDOTDI\000" |
| 13448 | /* 31010 */ "VUDOTDI\000" |
| 13449 | /* 31018 */ "t2BFI\000" |
| 13450 | /* 31024 */ "DBG_PHI\000" |
| 13451 | /* 31032 */ "VBF16MALBQI\000" |
| 13452 | /* 31044 */ "VFMALQI\000" |
| 13453 | /* 31052 */ "VFMSLQI\000" |
| 13454 | /* 31060 */ "VBF16MALTQI\000" |
| 13455 | /* 31072 */ "VUSDOTQI\000" |
| 13456 | /* 31081 */ "VSDOTQI\000" |
| 13457 | /* 31089 */ "VSUDOTQI\000" |
| 13458 | /* 31098 */ "VUDOTQI\000" |
| 13459 | /* 31106 */ "G_FPTOSI\000" |
| 13460 | /* 31115 */ "t2BTI\000" |
| 13461 | /* 31121 */ "t2PACBTI\000" |
| 13462 | /* 31130 */ "t2CALL_BTI\000" |
| 13463 | /* 31141 */ "G_FPTOUI\000" |
| 13464 | /* 31150 */ "G_FPOWI\000" |
| 13465 | /* 31158 */ "t2BXJ\000" |
| 13466 | /* 31164 */ "WIN__DBZCHK\000" |
| 13467 | /* 31176 */ "G_PTRMASK\000" |
| 13468 | /* 31186 */ "WIN__CHKSTK\000" |
| 13469 | /* 31198 */ "t2UMAAL\000" |
| 13470 | /* 31206 */ "t2SMLAL\000" |
| 13471 | /* 31214 */ "t2UMLAL\000" |
| 13472 | /* 31222 */ "LOADDUAL\000" |
| 13473 | /* 31231 */ "STOREDUAL\000" |
| 13474 | /* 31241 */ "tBL\000" |
| 13475 | /* 31245 */ "GC_LABEL\000" |
| 13476 | /* 31254 */ "DBG_LABEL\000" |
| 13477 | /* 31264 */ "EH_LABEL\000" |
| 13478 | /* 31273 */ "ANNOTATION_LABEL\000" |
| 13479 | /* 31290 */ "ICALL_BRANCH_FUNNEL\000" |
| 13480 | /* 31310 */ "t2SEL\000" |
| 13481 | /* 31316 */ "t2CSEL\000" |
| 13482 | /* 31323 */ "MVE_VPSEL\000" |
| 13483 | /* 31333 */ "G_FSHL\000" |
| 13484 | /* 31340 */ "MVE_SQSHL\000" |
| 13485 | /* 31350 */ "MVE_UQSHL\000" |
| 13486 | /* 31360 */ "MVE_UQRSHL\000" |
| 13487 | /* 31371 */ "G_SHL\000" |
| 13488 | /* 31377 */ "G_FCEIL\000" |
| 13489 | /* 31385 */ "BMOVPCB_CALL\000" |
| 13490 | /* 31398 */ "PATCHABLE_TAIL_CALL\000" |
| 13491 | /* 31418 */ "tBLXNS_CALL\000" |
| 13492 | /* 31430 */ "PATCHABLE_TYPED_EVENT_CALL\000" |
| 13493 | /* 31457 */ "PATCHABLE_EVENT_CALL\000" |
| 13494 | /* 31478 */ "tBX_CALL\000" |
| 13495 | /* 31487 */ "BMOVPCRX_CALL\000" |
| 13496 | /* 31501 */ "FENTRY_CALL\000" |
| 13497 | /* 31513 */ "MVE_SQSHLL\000" |
| 13498 | /* 31524 */ "MVE_UQSHLL\000" |
| 13499 | /* 31535 */ "MVE_UQRSHLL\000" |
| 13500 | /* 31547 */ "KILL\000" |
| 13501 | /* 31552 */ "t2SMULL\000" |
| 13502 | /* 31560 */ "t2UMULL\000" |
| 13503 | /* 31568 */ "G_CONSTANT_POOL\000" |
| 13504 | /* 31584 */ "MVE_SQRSHRL\000" |
| 13505 | /* 31596 */ "MVE_SRSHRL\000" |
| 13506 | /* 31607 */ "MVE_URSHRL\000" |
| 13507 | /* 31618 */ "MVE_LSRL\000" |
| 13508 | /* 31627 */ "G_ROTL\000" |
| 13509 | /* 31634 */ "t2STL\000" |
| 13510 | /* 31640 */ "t2MUL\000" |
| 13511 | /* 31646 */ "G_VECREDUCE_FMUL\000" |
| 13512 | /* 31663 */ "G_FMUL\000" |
| 13513 | /* 31670 */ "G_VECREDUCE_SEQ_FMUL\000" |
| 13514 | /* 31691 */ "G_STRICT_FMUL\000" |
| 13515 | /* 31705 */ "t2SMMUL\000" |
| 13516 | /* 31713 */ "G_VECREDUCE_MUL\000" |
| 13517 | /* 31729 */ "G_MUL\000" |
| 13518 | /* 31735 */ "tMUL\000" |
| 13519 | /* 31740 */ "SHA1M\000" |
| 13520 | /* 31746 */ "MVE_VRINTf32M\000" |
| 13521 | /* 31760 */ "MVE_VRINTf16M\000" |
| 13522 | /* 31774 */ "VLLDM\000" |
| 13523 | /* 31780 */ "G_FREM\000" |
| 13524 | /* 31787 */ "G_STRICT_FREM\000" |
| 13525 | /* 31801 */ "G_SREM\000" |
| 13526 | /* 31808 */ "G_UREM\000" |
| 13527 | /* 31815 */ "G_SDIVREM\000" |
| 13528 | /* 31825 */ "G_UDIVREM\000" |
| 13529 | /* 31835 */ "LDRB_PRE_IMM\000" |
| 13530 | /* 31848 */ "STRB_PRE_IMM\000" |
| 13531 | /* 31861 */ "LDR_PRE_IMM\000" |
| 13532 | /* 31873 */ "STR_PRE_IMM\000" |
| 13533 | /* 31885 */ "LDRB_POST_IMM\000" |
| 13534 | /* 31899 */ "STRB_POST_IMM\000" |
| 13535 | /* 31913 */ "LDR_POST_IMM\000" |
| 13536 | /* 31926 */ "STR_POST_IMM\000" |
| 13537 | /* 31939 */ "LDRBT_POST_IMM\000" |
| 13538 | /* 31954 */ "STRBT_POST_IMM\000" |
| 13539 | /* 31969 */ "LDRT_POST_IMM\000" |
| 13540 | /* 31983 */ "STRT_POST_IMM\000" |
| 13541 | /* 31997 */ "t2CLRM\000" |
| 13542 | /* 32004 */ "INLINEASM\000" |
| 13543 | /* 32014 */ "VLSTM\000" |
| 13544 | /* 32020 */ "G_VECREDUCE_FMINIMUM\000" |
| 13545 | /* 32041 */ "G_FMINIMUM\000" |
| 13546 | /* 32052 */ "G_ATOMICRMW_FMINIMUM\000" |
| 13547 | /* 32073 */ "G_VECREDUCE_FMAXIMUM\000" |
| 13548 | /* 32094 */ "G_FMAXIMUM\000" |
| 13549 | /* 32105 */ "G_ATOMICRMW_FMAXIMUM\000" |
| 13550 | /* 32126 */ "G_FMINIMUMNUM\000" |
| 13551 | /* 32140 */ "G_FMAXIMUMNUM\000" |
| 13552 | /* 32154 */ "G_FMINNUM\000" |
| 13553 | /* 32164 */ "G_FMAXNUM\000" |
| 13554 | /* 32174 */ "t2MSR_M\000" |
| 13555 | /* 32182 */ "t2MRS_M\000" |
| 13556 | /* 32190 */ "MVE_VRINTf32N\000" |
| 13557 | /* 32204 */ "MVE_VRINTf16N\000" |
| 13558 | /* 32218 */ "t2SETPAN\000" |
| 13559 | /* 32227 */ "G_FATAN\000" |
| 13560 | /* 32235 */ "G_FTAN\000" |
| 13561 | /* 32242 */ "G_INTRINSIC_ROUNDEVEN\000" |
| 13562 | /* 32264 */ "G_ASSERT_ALIGN\000" |
| 13563 | /* 32279 */ "G_FCOPYSIGN\000" |
| 13564 | /* 32291 */ "G_VECREDUCE_FMIN\000" |
| 13565 | /* 32308 */ "G_ATOMICRMW_FMIN\000" |
| 13566 | /* 32325 */ "G_VECREDUCE_SMIN\000" |
| 13567 | /* 32342 */ "G_SMIN\000" |
| 13568 | /* 32349 */ "G_VECREDUCE_UMIN\000" |
| 13569 | /* 32366 */ "G_UMIN\000" |
| 13570 | /* 32373 */ "G_ATOMICRMW_UMIN\000" |
| 13571 | /* 32390 */ "G_ATOMICRMW_MIN\000" |
| 13572 | /* 32406 */ "G_FASIN\000" |
| 13573 | /* 32414 */ "G_FSIN\000" |
| 13574 | /* 32421 */ "CFI_INSTRUCTION\000" |
| 13575 | /* 32437 */ "t2LDC2_OPTION\000" |
| 13576 | /* 32451 */ "t2STC2_OPTION\000" |
| 13577 | /* 32465 */ "t2LDC_OPTION\000" |
| 13578 | /* 32478 */ "t2STC_OPTION\000" |
| 13579 | /* 32491 */ "t2LDC2L_OPTION\000" |
| 13580 | /* 32506 */ "t2STC2L_OPTION\000" |
| 13581 | /* 32521 */ "t2LDCL_OPTION\000" |
| 13582 | /* 32535 */ "t2STCL_OPTION\000" |
| 13583 | /* 32549 */ "MVE_VORN\000" |
| 13584 | /* 32558 */ "MVE_VMVN\000" |
| 13585 | /* 32567 */ "tMVN\000" |
| 13586 | /* 32572 */ "tADJCALLSTACKDOWN\000" |
| 13587 | /* 32590 */ "G_SSUBO\000" |
| 13588 | /* 32598 */ "G_USUBO\000" |
| 13589 | /* 32606 */ "G_SADDO\000" |
| 13590 | /* 32614 */ "G_UADDO\000" |
| 13591 | /* 32622 */ "JUMP_TABLE_DEBUG_INFO\000" |
| 13592 | /* 32644 */ "G_SMULO\000" |
| 13593 | /* 32652 */ "G_UMULO\000" |
| 13594 | /* 32660 */ "G_BZERO\000" |
| 13595 | /* 32668 */ "SHA1P\000" |
| 13596 | /* 32674 */ "MVE_VRINTf32P\000" |
| 13597 | /* 32688 */ "MVE_VRINTf16P\000" |
| 13598 | /* 32702 */ "STACKMAP\000" |
| 13599 | /* 32711 */ "G_DEBUGTRAP\000" |
| 13600 | /* 32723 */ "G_UBSANTRAP\000" |
| 13601 | /* 32735 */ "G_TRAP\000" |
| 13602 | /* 32742 */ "tTRAP\000" |
| 13603 | /* 32748 */ "G_ATOMICRMW_UDEC_WRAP\000" |
| 13604 | /* 32770 */ "G_ATOMICRMW_UINC_WRAP\000" |
| 13605 | /* 32792 */ "G_BSWAP\000" |
| 13606 | /* 32800 */ "t2CDP\000" |
| 13607 | /* 32806 */ "G_SITOFP\000" |
| 13608 | /* 32815 */ "G_UITOFP\000" |
| 13609 | /* 32824 */ "G_FCMP\000" |
| 13610 | /* 32831 */ "G_ICMP\000" |
| 13611 | /* 32838 */ "G_SCMP\000" |
| 13612 | /* 32845 */ "G_UCMP\000" |
| 13613 | /* 32852 */ "CONVERGENCECTRL_LOOP\000" |
| 13614 | /* 32873 */ "G_CTPOP\000" |
| 13615 | /* 32881 */ "tPOP\000" |
| 13616 | /* 32886 */ "PATCHABLE_OP\000" |
| 13617 | /* 32899 */ "FAULTING_OP\000" |
| 13618 | /* 32911 */ "SEH_SaveSP\000" |
| 13619 | /* 32922 */ "tADDrSP\000" |
| 13620 | /* 32930 */ "MVE_LCTP\000" |
| 13621 | /* 32939 */ "MVE_LETP\000" |
| 13622 | /* 32948 */ "t2WhileLoopStartTP\000" |
| 13623 | /* 32967 */ "t2DoLoopStartTP\000" |
| 13624 | /* 32983 */ "tADJCALLSTACKUP\000" |
| 13625 | /* 32999 */ "PREALLOCATED_SETUP\000" |
| 13626 | /* 33018 */ "SWP\000" |
| 13627 | /* 33022 */ "G_FLDEXP\000" |
| 13628 | /* 33031 */ "G_STRICT_FLDEXP\000" |
| 13629 | /* 33047 */ "G_FEXP\000" |
| 13630 | /* 33054 */ "G_FFREXP\000" |
| 13631 | /* 33063 */ "VLD1d32Q\000" |
| 13632 | /* 33072 */ "VST1d32Q\000" |
| 13633 | /* 33081 */ "VLD1d64Q\000" |
| 13634 | /* 33090 */ "VST1d64Q\000" |
| 13635 | /* 33099 */ "VLD1d16Q\000" |
| 13636 | /* 33108 */ "VST1d16Q\000" |
| 13637 | /* 33117 */ "VLD1d8Q\000" |
| 13638 | /* 33125 */ "VST1d8Q\000" |
| 13639 | /* 33133 */ "VBF16MALBQ\000" |
| 13640 | /* 33144 */ "VFMALQ\000" |
| 13641 | /* 33151 */ "VFMSLQ\000" |
| 13642 | /* 33158 */ "VBF16MALTQ\000" |
| 13643 | /* 33169 */ "VUSDOTQ\000" |
| 13644 | /* 33177 */ "VSDOTQ\000" |
| 13645 | /* 33184 */ "VUDOTQ\000" |
| 13646 | /* 33191 */ "BF16VDOTI_VDOTQ\000" |
| 13647 | /* 33207 */ "BF16VDOTS_VDOTQ\000" |
| 13648 | /* 33223 */ "t2SMMLAR\000" |
| 13649 | /* 33232 */ "t2MSR_AR\000" |
| 13650 | /* 33241 */ "t2MRS_AR\000" |
| 13651 | /* 33250 */ "t2MRSsys_AR\000" |
| 13652 | /* 33262 */ "G_BR\000" |
| 13653 | /* 33267 */ "INLINEASM_BR\000" |
| 13654 | /* 33280 */ "t2MCR\000" |
| 13655 | /* 33286 */ "t2ADR\000" |
| 13656 | /* 33292 */ "tADR\000" |
| 13657 | /* 33297 */ "G_BLOCK_ADDR\000" |
| 13658 | /* 33310 */ "PICLDR\000" |
| 13659 | /* 33317 */ "MEMBARRIER\000" |
| 13660 | /* 33328 */ "G_CONSTANT_FOLD_BARRIER\000" |
| 13661 | /* 33352 */ "PATCHABLE_FUNCTION_ENTER\000" |
| 13662 | /* 33377 */ "G_READCYCLECOUNTER\000" |
| 13663 | /* 33396 */ "G_READSTEADYCOUNTER\000" |
| 13664 | /* 33416 */ "G_READ_REGISTER\000" |
| 13665 | /* 33432 */ "G_WRITE_REGISTER\000" |
| 13666 | /* 33449 */ "G_ASHR\000" |
| 13667 | /* 33456 */ "G_FSHR\000" |
| 13668 | /* 33463 */ "G_LSHR\000" |
| 13669 | /* 33470 */ "MVE_SQRSHR\000" |
| 13670 | /* 33481 */ "MVE_SRSHR\000" |
| 13671 | /* 33491 */ "MVE_URSHR\000" |
| 13672 | /* 33501 */ "VMOVHR\000" |
| 13673 | /* 33508 */ "MOVPCLR\000" |
| 13674 | /* 33516 */ "tBL_PUSHLR\000" |
| 13675 | /* 33527 */ "t2SMMULR\000" |
| 13676 | /* 33536 */ "t2SUBS_PC_LR\000" |
| 13677 | /* 33549 */ "SEH_SaveLR\000" |
| 13678 | /* 33560 */ "t2WhileLoopStartLR\000" |
| 13679 | /* 33579 */ "MVE_VEOR\000" |
| 13680 | /* 33588 */ "tEOR\000" |
| 13681 | /* 33593 */ "CONVERGENCECTRL_ANCHOR\000" |
| 13682 | /* 33616 */ "G_FFLOOR\000" |
| 13683 | /* 33625 */ "tROR\000" |
| 13684 | /* 33630 */ "G_EXTRACT_SUBVECTOR\000" |
| 13685 | /* 33650 */ "G_INSERT_SUBVECTOR\000" |
| 13686 | /* 33669 */ "G_BUILD_VECTOR\000" |
| 13687 | /* 33684 */ "G_SHUFFLE_VECTOR\000" |
| 13688 | /* 33701 */ "G_STEP_VECTOR\000" |
| 13689 | /* 33715 */ "G_SPLAT_VECTOR\000" |
| 13690 | /* 33730 */ "G_VECREDUCE_XOR\000" |
| 13691 | /* 33746 */ "G_XOR\000" |
| 13692 | /* 33752 */ "G_ATOMICRMW_XOR\000" |
| 13693 | /* 33768 */ "G_VECREDUCE_OR\000" |
| 13694 | /* 33783 */ "G_OR\000" |
| 13695 | /* 33788 */ "G_ATOMICRMW_OR\000" |
| 13696 | /* 33803 */ "VMSR_VPR\000" |
| 13697 | /* 33812 */ "VMRS_VPR\000" |
| 13698 | /* 33821 */ "t2MCRR\000" |
| 13699 | /* 33828 */ "VMOVDRR\000" |
| 13700 | /* 33836 */ "MVE_VORR\000" |
| 13701 | /* 33845 */ "tORR\000" |
| 13702 | /* 33850 */ "VMOVSRR\000" |
| 13703 | /* 33858 */ "t2SMMLSR\000" |
| 13704 | /* 33867 */ "VMSR\000" |
| 13705 | /* 33872 */ "VMOVSR\000" |
| 13706 | /* 33879 */ "G_ROTR\000" |
| 13707 | /* 33886 */ "G_INTTOPTR\000" |
| 13708 | /* 33897 */ "PICSTR\000" |
| 13709 | /* 33904 */ "VNMLAS\000" |
| 13710 | /* 33911 */ "VMLAS\000" |
| 13711 | /* 33917 */ "VFMAS\000" |
| 13712 | /* 33923 */ "VFNMAS\000" |
| 13713 | /* 33930 */ "VRINTAS\000" |
| 13714 | /* 33938 */ "t2ABS\000" |
| 13715 | /* 33944 */ "G_FABS\000" |
| 13716 | /* 33951 */ "G_ABS\000" |
| 13717 | /* 33957 */ "tRSBS\000" |
| 13718 | /* 33963 */ "VSUBS\000" |
| 13719 | /* 33969 */ "tSBCS\000" |
| 13720 | /* 33975 */ "tADCS\000" |
| 13721 | /* 33981 */ "G_ABDS\000" |
| 13722 | /* 33988 */ "VADDS\000" |
| 13723 | /* 33994 */ "VCVTDS\000" |
| 13724 | /* 34001 */ "VSELGES\000" |
| 13725 | /* 34009 */ "VCMPES\000" |
| 13726 | /* 34016 */ "G_UNMERGE_VALUES\000" |
| 13727 | /* 34033 */ "G_MERGE_VALUES\000" |
| 13728 | /* 34048 */ "VNEGS\000" |
| 13729 | /* 34054 */ "VCVTBHS\000" |
| 13730 | /* 34062 */ "VTOSHS\000" |
| 13731 | /* 34069 */ "VCVTTHS\000" |
| 13732 | /* 34077 */ "VTOUHS\000" |
| 13733 | /* 34084 */ "t2DLS\000" |
| 13734 | /* 34090 */ "t2MLS\000" |
| 13735 | /* 34096 */ "t2SMMLS\000" |
| 13736 | /* 34104 */ "VTOSLS\000" |
| 13737 | /* 34111 */ "VNMULS\000" |
| 13738 | /* 34118 */ "VMULS\000" |
| 13739 | /* 34124 */ "VTOULS\000" |
| 13740 | /* 34131 */ "t2WLS\000" |
| 13741 | /* 34137 */ "VFP_VMINNMS\000" |
| 13742 | /* 34149 */ "VFP_VMAXNMS\000" |
| 13743 | /* 34161 */ "VSCCLRMS\000" |
| 13744 | /* 34170 */ "VRINTMS\000" |
| 13745 | /* 34178 */ "VRINTNS\000" |
| 13746 | /* 34186 */ "VMSR_FPCXTNS\000" |
| 13747 | /* 34199 */ "VMRS_FPCXTNS\000" |
| 13748 | /* 34212 */ "tBXNS\000" |
| 13749 | /* 34218 */ "G_FACOS\000" |
| 13750 | /* 34226 */ "G_FCOS\000" |
| 13751 | /* 34233 */ "G_FSINCOS\000" |
| 13752 | /* 34243 */ "VSHTOS\000" |
| 13753 | /* 34250 */ "VUHTOS\000" |
| 13754 | /* 34257 */ "VSITOS\000" |
| 13755 | /* 34264 */ "VUITOS\000" |
| 13756 | /* 34271 */ "VSLTOS\000" |
| 13757 | /* 34278 */ "VULTOS\000" |
| 13758 | /* 34285 */ "tCPS\000" |
| 13759 | /* 34290 */ "VCMPS\000" |
| 13760 | /* 34296 */ "VRINTPS\000" |
| 13761 | /* 34304 */ "VSELEQS\000" |
| 13762 | /* 34312 */ "JUMPTABLE_ADDRS\000" |
| 13763 | /* 34328 */ "VLDRS\000" |
| 13764 | /* 34334 */ "VTOSIRS\000" |
| 13765 | /* 34342 */ "VTOUIRS\000" |
| 13766 | /* 34350 */ "VMRS\000" |
| 13767 | /* 34355 */ "G_CONCAT_VECTORS\000" |
| 13768 | /* 34372 */ "VMOVRRS\000" |
| 13769 | /* 34380 */ "VRINTRS\000" |
| 13770 | /* 34388 */ "VSTRS\000" |
| 13771 | /* 34394 */ "VMOVRS\000" |
| 13772 | /* 34401 */ "COPY_TO_REGCLASS\000" |
| 13773 | /* 34418 */ "G_IS_FPCLASS\000" |
| 13774 | /* 34431 */ "VCVTASS\000" |
| 13775 | /* 34439 */ "VABSS\000" |
| 13776 | /* 34445 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\000" |
| 13777 | /* 34475 */ "G_VECTOR_COMPRESS\000" |
| 13778 | /* 34493 */ "VNMLSS\000" |
| 13779 | /* 34500 */ "VMLSS\000" |
| 13780 | /* 34506 */ "VFMSS\000" |
| 13781 | /* 34512 */ "VFNMSS\000" |
| 13782 | /* 34519 */ "VCVTMSS\000" |
| 13783 | /* 34527 */ "VCVTNSS\000" |
| 13784 | /* 34535 */ "VCVTPSS\000" |
| 13785 | /* 34543 */ "VSELVSS\000" |
| 13786 | /* 34551 */ "G_INTRINSIC_W_SIDE_EFFECTS\000" |
| 13787 | /* 34578 */ "G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS\000" |
| 13788 | /* 34616 */ "VSELGTS\000" |
| 13789 | /* 34624 */ "VSQRTS\000" |
| 13790 | /* 34631 */ "JUMPTABLE_INSTS\000" |
| 13791 | /* 34647 */ "FCONSTS\000" |
| 13792 | /* 34655 */ "VMSR_FPCXTS\000" |
| 13793 | /* 34667 */ "VMRS_FPCXTS\000" |
| 13794 | /* 34679 */ "VCVTAUS\000" |
| 13795 | /* 34687 */ "VCVTMUS\000" |
| 13796 | /* 34695 */ "VCVTNUS\000" |
| 13797 | /* 34703 */ "VCVTPUS\000" |
| 13798 | /* 34711 */ "VDIVS\000" |
| 13799 | /* 34717 */ "VMOVS\000" |
| 13800 | /* 34723 */ "VRINTXS\000" |
| 13801 | /* 34731 */ "VCMPEZS\000" |
| 13802 | /* 34739 */ "VTOSIZS\000" |
| 13803 | /* 34747 */ "VTOUIZS\000" |
| 13804 | /* 34755 */ "VCMPZS\000" |
| 13805 | /* 34762 */ "VRINTZS\000" |
| 13806 | /* 34770 */ "VLD1d32T\000" |
| 13807 | /* 34779 */ "VST1d32T\000" |
| 13808 | /* 34788 */ "VLD1d64T\000" |
| 13809 | /* 34797 */ "VST1d64T\000" |
| 13810 | /* 34806 */ "VLD1d16T\000" |
| 13811 | /* 34815 */ "VST1d16T\000" |
| 13812 | /* 34824 */ "VLD1d8T\000" |
| 13813 | /* 34832 */ "VST1d8T\000" |
| 13814 | /* 34840 */ "G_SSUBSAT\000" |
| 13815 | /* 34850 */ "G_USUBSAT\000" |
| 13816 | /* 34860 */ "G_SADDSAT\000" |
| 13817 | /* 34870 */ "G_UADDSAT\000" |
| 13818 | /* 34880 */ "G_SSHLSAT\000" |
| 13819 | /* 34890 */ "G_USHLSAT\000" |
| 13820 | /* 34900 */ "t2SSAT\000" |
| 13821 | /* 34907 */ "t2USAT\000" |
| 13822 | /* 34914 */ "G_SMULFIXSAT\000" |
| 13823 | /* 34927 */ "G_UMULFIXSAT\000" |
| 13824 | /* 34940 */ "G_SDIVFIXSAT\000" |
| 13825 | /* 34953 */ "G_UDIVFIXSAT\000" |
| 13826 | /* 34966 */ "G_ATOMICRMW_USUB_SAT\000" |
| 13827 | /* 34987 */ "G_FPTOSI_SAT\000" |
| 13828 | /* 35000 */ "G_FPTOUI_SAT\000" |
| 13829 | /* 35013 */ "FMSTAT\000" |
| 13830 | /* 35020 */ "t2TTAT\000" |
| 13831 | /* 35027 */ "t2SMLABT\000" |
| 13832 | /* 35036 */ "t2PKHBT\000" |
| 13833 | /* 35044 */ "t2SMLALBT\000" |
| 13834 | /* 35054 */ "t2SMULBT\000" |
| 13835 | /* 35063 */ "t2LDRBT\000" |
| 13836 | /* 35071 */ "t2STRBT\000" |
| 13837 | /* 35079 */ "t2LDRSBT\000" |
| 13838 | /* 35088 */ "G_EXTRACT\000" |
| 13839 | /* 35098 */ "G_SELECT\000" |
| 13840 | /* 35107 */ "G_BRINDIRECT\000" |
| 13841 | /* 35120 */ "ERET\000" |
| 13842 | /* 35125 */ "t2LDMIA_RET\000" |
| 13843 | /* 35137 */ "PATCHABLE_RET\000" |
| 13844 | /* 35151 */ "tPOP_RET\000" |
| 13845 | /* 35160 */ "tBXNS_RET\000" |
| 13846 | /* 35170 */ "tBX_RET\000" |
| 13847 | /* 35178 */ "t2LDC2_OFFSET\000" |
| 13848 | /* 35192 */ "t2STC2_OFFSET\000" |
| 13849 | /* 35206 */ "t2LDC_OFFSET\000" |
| 13850 | /* 35219 */ "t2STC_OFFSET\000" |
| 13851 | /* 35232 */ "t2LDC2L_OFFSET\000" |
| 13852 | /* 35247 */ "t2STC2L_OFFSET\000" |
| 13853 | /* 35262 */ "t2LDCL_OFFSET\000" |
| 13854 | /* 35276 */ "t2STCL_OFFSET\000" |
| 13855 | /* 35290 */ "G_MEMSET\000" |
| 13856 | /* 35299 */ "t2LDRHT\000" |
| 13857 | /* 35307 */ "t2STRHT\000" |
| 13858 | /* 35315 */ "t2LDRSHT\000" |
| 13859 | /* 35324 */ "t2IT\000" |
| 13860 | /* 35329 */ "t2RBIT\000" |
| 13861 | /* 35336 */ "PATCHABLE_FUNCTION_EXIT\000" |
| 13862 | /* 35360 */ "G_BRJT\000" |
| 13863 | /* 35367 */ "t2TBB_JT\000" |
| 13864 | /* 35376 */ "tTBB_JT\000" |
| 13865 | /* 35384 */ "t2TBH_JT\000" |
| 13866 | /* 35393 */ "tTBH_JT\000" |
| 13867 | /* 35401 */ "t2BR_JT\000" |
| 13868 | /* 35409 */ "t2LEApcrelJT\000" |
| 13869 | /* 35422 */ "tLEApcrelJT\000" |
| 13870 | /* 35434 */ "G_EXTRACT_VECTOR_ELT\000" |
| 13871 | /* 35455 */ "G_INSERT_VECTOR_ELT\000" |
| 13872 | /* 35475 */ "tHLT\000" |
| 13873 | /* 35480 */ "G_FCONSTANT\000" |
| 13874 | /* 35492 */ "G_CONSTANT\000" |
| 13875 | /* 35503 */ "G_INTRINSIC_CONVERGENT\000" |
| 13876 | /* 35526 */ "t2HINT\000" |
| 13877 | /* 35533 */ "tHINT\000" |
| 13878 | /* 35539 */ "STATEPOINT\000" |
| 13879 | /* 35550 */ "PATCHPOINT\000" |
| 13880 | /* 35561 */ "G_PTRTOINT\000" |
| 13881 | /* 35572 */ "G_FRINT\000" |
| 13882 | /* 35580 */ "G_INTRINSIC_LLRINT\000" |
| 13883 | /* 35599 */ "G_INTRINSIC_LRINT\000" |
| 13884 | /* 35617 */ "G_FNEARBYINT\000" |
| 13885 | /* 35630 */ "MVE_VPNOT\000" |
| 13886 | /* 35640 */ "tBKPT\000" |
| 13887 | /* 35646 */ "G_VASTART\000" |
| 13888 | /* 35656 */ "LIFETIME_START\000" |
| 13889 | /* 35671 */ "G_INVOKE_REGION_START\000" |
| 13890 | /* 35693 */ "t2LDRT\000" |
| 13891 | /* 35700 */ "G_INSERT\000" |
| 13892 | /* 35709 */ "G_FSQRT\000" |
| 13893 | /* 35717 */ "G_STRICT_FSQRT\000" |
| 13894 | /* 35732 */ "t2STRT\000" |
| 13895 | /* 35739 */ "G_BITCAST\000" |
| 13896 | /* 35749 */ "G_ADDRSPACE_CAST\000" |
| 13897 | /* 35766 */ "DBG_VALUE_LIST\000" |
| 13898 | /* 35781 */ "VMSR_FPINST\000" |
| 13899 | /* 35793 */ "VMRS_FPINST\000" |
| 13900 | /* 35805 */ "MVE_MEMSETLOOPINST\000" |
| 13901 | /* 35824 */ "MVE_MEMCPYLOOPINST\000" |
| 13902 | /* 35843 */ "t2LDC2_POST\000" |
| 13903 | /* 35855 */ "t2STC2_POST\000" |
| 13904 | /* 35867 */ "t2LDRB_POST\000" |
| 13905 | /* 35879 */ "t2STRB_POST\000" |
| 13906 | /* 35891 */ "t2LDRSB_POST\000" |
| 13907 | /* 35904 */ "t2LDC_POST\000" |
| 13908 | /* 35915 */ "t2STC_POST\000" |
| 13909 | /* 35926 */ "t2LDRD_POST\000" |
| 13910 | /* 35938 */ "t2STRD_POST\000" |
| 13911 | /* 35950 */ "t2LDRH_POST\000" |
| 13912 | /* 35962 */ "t2STRH_POST\000" |
| 13913 | /* 35974 */ "t2LDRSH_POST\000" |
| 13914 | /* 35987 */ "t2LDC2L_POST\000" |
| 13915 | /* 36000 */ "t2STC2L_POST\000" |
| 13916 | /* 36013 */ "t2LDCL_POST\000" |
| 13917 | /* 36025 */ "t2STCL_POST\000" |
| 13918 | /* 36037 */ "t2LDR_POST\000" |
| 13919 | /* 36048 */ "t2STR_POST\000" |
| 13920 | /* 36059 */ "LDRBT_POST\000" |
| 13921 | /* 36070 */ "STRBT_POST\000" |
| 13922 | /* 36081 */ "LDRT_POST\000" |
| 13923 | /* 36091 */ "STRT_POST\000" |
| 13924 | /* 36101 */ "MVE_VPST\000" |
| 13925 | /* 36110 */ "tTST\000" |
| 13926 | /* 36115 */ "t2TT\000" |
| 13927 | /* 36120 */ "t2SMLATT\000" |
| 13928 | /* 36129 */ "t2SMLALTT\000" |
| 13929 | /* 36139 */ "t2SMULTT\000" |
| 13930 | /* 36148 */ "t2TTT\000" |
| 13931 | /* 36154 */ "BF16_VCVTT\000" |
| 13932 | /* 36165 */ "t2AUT\000" |
| 13933 | /* 36171 */ "t2BXAUT\000" |
| 13934 | /* 36179 */ "VJCVT\000" |
| 13935 | /* 36185 */ "BF16_VCVT\000" |
| 13936 | /* 36195 */ "t2SMLAWT\000" |
| 13937 | /* 36204 */ "t2SMULWT\000" |
| 13938 | /* 36213 */ "G_FPEXT\000" |
| 13939 | /* 36221 */ "G_SEXT\000" |
| 13940 | /* 36228 */ "G_ASSERT_SEXT\000" |
| 13941 | /* 36242 */ "G_ANYEXT\000" |
| 13942 | /* 36251 */ "G_ZEXT\000" |
| 13943 | /* 36258 */ "G_ASSERT_ZEXT\000" |
| 13944 | /* 36272 */ "G_ABDU\000" |
| 13945 | /* 36279 */ "t2REV\000" |
| 13946 | /* 36285 */ "tREV\000" |
| 13947 | /* 36290 */ "G_FDIV\000" |
| 13948 | /* 36297 */ "G_STRICT_FDIV\000" |
| 13949 | /* 36311 */ "t2SDIV\000" |
| 13950 | /* 36318 */ "G_SDIV\000" |
| 13951 | /* 36325 */ "t2UDIV\000" |
| 13952 | /* 36332 */ "G_UDIV\000" |
| 13953 | /* 36339 */ "G_GET_FPENV\000" |
| 13954 | /* 36351 */ "G_RESET_FPENV\000" |
| 13955 | /* 36365 */ "G_SET_FPENV\000" |
| 13956 | /* 36377 */ "t2CSINV\000" |
| 13957 | /* 36385 */ "t2CRC32W\000" |
| 13958 | /* 36394 */ "t2RFEIAW\000" |
| 13959 | /* 36403 */ "t2RFEDBW\000" |
| 13960 | /* 36412 */ "t2CRC32CW\000" |
| 13961 | /* 36422 */ "G_FPOW\000" |
| 13962 | /* 36429 */ "MVE_VRINTf32X\000" |
| 13963 | /* 36443 */ "MVE_VRINTf16X\000" |
| 13964 | /* 36457 */ "G_VECREDUCE_FMAX\000" |
| 13965 | /* 36474 */ "G_ATOMICRMW_FMAX\000" |
| 13966 | /* 36491 */ "G_VECREDUCE_SMAX\000" |
| 13967 | /* 36508 */ "G_SMAX\000" |
| 13968 | /* 36515 */ "G_VECREDUCE_UMAX\000" |
| 13969 | /* 36532 */ "G_UMAX\000" |
| 13970 | /* 36539 */ "G_ATOMICRMW_UMAX\000" |
| 13971 | /* 36556 */ "G_ATOMICRMW_MAX\000" |
| 13972 | /* 36572 */ "t2SHSAX\000" |
| 13973 | /* 36580 */ "t2UHSAX\000" |
| 13974 | /* 36588 */ "t2QSAX\000" |
| 13975 | /* 36595 */ "t2UQSAX\000" |
| 13976 | /* 36603 */ "t2SSAX\000" |
| 13977 | /* 36610 */ "t2USAX\000" |
| 13978 | /* 36617 */ "tBX\000" |
| 13979 | /* 36621 */ "t2SMLADX\000" |
| 13980 | /* 36630 */ "t2SMUADX\000" |
| 13981 | /* 36639 */ "t2SMLALDX\000" |
| 13982 | /* 36649 */ "t2SMLSLDX\000" |
| 13983 | /* 36659 */ "t2SMLSDX\000" |
| 13984 | /* 36668 */ "t2SMUSDX\000" |
| 13985 | /* 36677 */ "t2LDAEX\000" |
| 13986 | /* 36685 */ "G_FRAME_INDEX\000" |
| 13987 | /* 36699 */ "t2STLEX\000" |
| 13988 | /* 36707 */ "t2LDREX\000" |
| 13989 | /* 36715 */ "t2CLREX\000" |
| 13990 | /* 36723 */ "t2STREX\000" |
| 13991 | /* 36731 */ "t2SBFX\000" |
| 13992 | /* 36738 */ "G_SBFX\000" |
| 13993 | /* 36745 */ "t2UBFX\000" |
| 13994 | /* 36752 */ "G_UBFX\000" |
| 13995 | /* 36759 */ "G_SMULFIX\000" |
| 13996 | /* 36769 */ "G_UMULFIX\000" |
| 13997 | /* 36779 */ "G_SDIVFIX\000" |
| 13998 | /* 36789 */ "G_UDIVFIX\000" |
| 13999 | /* 36799 */ "BLX\000" |
| 14000 | /* 36803 */ "MOVPCRX\000" |
| 14001 | /* 36811 */ "t2RRX\000" |
| 14002 | /* 36817 */ "t2SHASX\000" |
| 14003 | /* 36825 */ "t2UHASX\000" |
| 14004 | /* 36833 */ "t2QASX\000" |
| 14005 | /* 36840 */ "t2UQASX\000" |
| 14006 | /* 36848 */ "t2SASX\000" |
| 14007 | /* 36855 */ "t2UASX\000" |
| 14008 | /* 36862 */ "G_MEMCPY\000" |
| 14009 | /* 36871 */ "COPY\000" |
| 14010 | /* 36876 */ "CONSTPOOL_ENTRY\000" |
| 14011 | /* 36892 */ "CONVERGENCECTRL_ENTRY\000" |
| 14012 | /* 36914 */ "MVE_VRINTf32Z\000" |
| 14013 | /* 36928 */ "MVE_VRINTf16Z\000" |
| 14014 | /* 36942 */ "tCBZ\000" |
| 14015 | /* 36947 */ "t2CLZ\000" |
| 14016 | /* 36953 */ "G_CTLZ\000" |
| 14017 | /* 36960 */ "tCBNZ\000" |
| 14018 | /* 36966 */ "G_CTTZ\000" |
| 14019 | /* 36973 */ "MVE_VCVTs32f32a\000" |
| 14020 | /* 36989 */ "MVE_VCVTu32f32a\000" |
| 14021 | /* 37005 */ "MVE_VCVTs16f16a\000" |
| 14022 | /* 37021 */ "MVE_VCVTu16f16a\000" |
| 14023 | /* 37037 */ "MVE_VLD20_32_wb\000" |
| 14024 | /* 37053 */ "MVE_VST20_32_wb\000" |
| 14025 | /* 37069 */ "MVE_VLD40_32_wb\000" |
| 14026 | /* 37085 */ "MVE_VST40_32_wb\000" |
| 14027 | /* 37101 */ "MVE_VLD21_32_wb\000" |
| 14028 | /* 37117 */ "MVE_VST21_32_wb\000" |
| 14029 | /* 37133 */ "MVE_VLD41_32_wb\000" |
| 14030 | /* 37149 */ "MVE_VST41_32_wb\000" |
| 14031 | /* 37165 */ "MVE_VLD42_32_wb\000" |
| 14032 | /* 37181 */ "MVE_VST42_32_wb\000" |
| 14033 | /* 37197 */ "MVE_VLD43_32_wb\000" |
| 14034 | /* 37213 */ "MVE_VST43_32_wb\000" |
| 14035 | /* 37229 */ "MVE_VLD20_16_wb\000" |
| 14036 | /* 37245 */ "MVE_VST20_16_wb\000" |
| 14037 | /* 37261 */ "MVE_VLD40_16_wb\000" |
| 14038 | /* 37277 */ "MVE_VST40_16_wb\000" |
| 14039 | /* 37293 */ "MVE_VLD21_16_wb\000" |
| 14040 | /* 37309 */ "MVE_VST21_16_wb\000" |
| 14041 | /* 37325 */ "MVE_VLD41_16_wb\000" |
| 14042 | /* 37341 */ "MVE_VST41_16_wb\000" |
| 14043 | /* 37357 */ "MVE_VLD42_16_wb\000" |
| 14044 | /* 37373 */ "MVE_VST42_16_wb\000" |
| 14045 | /* 37389 */ "MVE_VLD43_16_wb\000" |
| 14046 | /* 37405 */ "MVE_VST43_16_wb\000" |
| 14047 | /* 37421 */ "MVE_VLD20_8_wb\000" |
| 14048 | /* 37436 */ "MVE_VST20_8_wb\000" |
| 14049 | /* 37451 */ "MVE_VLD40_8_wb\000" |
| 14050 | /* 37466 */ "MVE_VST40_8_wb\000" |
| 14051 | /* 37481 */ "MVE_VLD21_8_wb\000" |
| 14052 | /* 37496 */ "MVE_VST21_8_wb\000" |
| 14053 | /* 37511 */ "MVE_VLD41_8_wb\000" |
| 14054 | /* 37526 */ "MVE_VST41_8_wb\000" |
| 14055 | /* 37541 */ "MVE_VLD42_8_wb\000" |
| 14056 | /* 37556 */ "MVE_VST42_8_wb\000" |
| 14057 | /* 37571 */ "MVE_VLD43_8_wb\000" |
| 14058 | /* 37586 */ "MVE_VST43_8_wb\000" |
| 14059 | /* 37601 */ "t2Bcc\000" |
| 14060 | /* 37607 */ "tBcc\000" |
| 14061 | /* 37612 */ "VMOVDcc\000" |
| 14062 | /* 37620 */ "VMOVHcc\000" |
| 14063 | /* 37628 */ "VMOVScc\000" |
| 14064 | /* 37636 */ "MVE_VADDVs32acc\000" |
| 14065 | /* 37652 */ "MVE_VADDLVs32acc\000" |
| 14066 | /* 37669 */ "MVE_VADDVu32acc\000" |
| 14067 | /* 37685 */ "MVE_VADDLVu32acc\000" |
| 14068 | /* 37702 */ "MVE_VADDVs16acc\000" |
| 14069 | /* 37718 */ "MVE_VADDVu16acc\000" |
| 14070 | /* 37734 */ "MVE_VADDVs8acc\000" |
| 14071 | /* 37749 */ "MVE_VADDVu8acc\000" |
| 14072 | /* 37764 */ "MVE_VADDVs32no_acc\000" |
| 14073 | /* 37783 */ "MVE_VADDLVs32no_acc\000" |
| 14074 | /* 37803 */ "MVE_VADDVu32no_acc\000" |
| 14075 | /* 37822 */ "MVE_VADDLVu32no_acc\000" |
| 14076 | /* 37842 */ "MVE_VADDVs16no_acc\000" |
| 14077 | /* 37861 */ "MVE_VADDVu16no_acc\000" |
| 14078 | /* 37880 */ "MVE_VADDVs8no_acc\000" |
| 14079 | /* 37898 */ "MVE_VADDVu8no_acc\000" |
| 14080 | /* 37916 */ "t2LoopEndDec\000" |
| 14081 | /* 37929 */ "t2LoopDec\000" |
| 14082 | /* 37939 */ "CDE_VCX1_vec\000" |
| 14083 | /* 37952 */ "CDE_VCX2_vec\000" |
| 14084 | /* 37965 */ "CDE_VCX3_vec\000" |
| 14085 | /* 37978 */ "CDE_VCX1A_vec\000" |
| 14086 | /* 37992 */ "CDE_VCX2A_vec\000" |
| 14087 | /* 38006 */ "CDE_VCX3A_vec\000" |
| 14088 | /* 38020 */ "t2BFic\000" |
| 14089 | /* 38027 */ "t2LDRpci_pic\000" |
| 14090 | /* 38040 */ "tLDRpci_pic\000" |
| 14091 | /* 38052 */ "SEH_StackAlloc\000" |
| 14092 | /* 38067 */ "VDUPLN32d\000" |
| 14093 | /* 38077 */ "VDUP32d\000" |
| 14094 | /* 38085 */ "VNEGs32d\000" |
| 14095 | /* 38094 */ "VDUPLN16d\000" |
| 14096 | /* 38104 */ "VDUP16d\000" |
| 14097 | /* 38112 */ "VNEGs16d\000" |
| 14098 | /* 38121 */ "VDUPLN8d\000" |
| 14099 | /* 38130 */ "VDUP8d\000" |
| 14100 | /* 38137 */ "VNEGs8d\000" |
| 14101 | /* 38145 */ "VBICd\000" |
| 14102 | /* 38151 */ "VANDd\000" |
| 14103 | /* 38157 */ "VRECPEd\000" |
| 14104 | /* 38165 */ "VRSQRTEd\000" |
| 14105 | /* 38174 */ "VBIFd\000" |
| 14106 | /* 38180 */ "VBSLd\000" |
| 14107 | /* 38186 */ "VORNd\000" |
| 14108 | /* 38192 */ "VMVNd\000" |
| 14109 | /* 38198 */ "tTAILJMPd\000" |
| 14110 | /* 38208 */ "VBSPd\000" |
| 14111 | /* 38214 */ "VSWPd\000" |
| 14112 | /* 38220 */ "VEORd\000" |
| 14113 | /* 38226 */ "VORRd\000" |
| 14114 | /* 38232 */ "VBITd\000" |
| 14115 | /* 38238 */ "VCNTd\000" |
| 14116 | /* 38244 */ "MQQPRLoad\000" |
| 14117 | /* 38254 */ "MQQQQPRLoad\000" |
| 14118 | /* 38266 */ "BR_JTadd\000" |
| 14119 | /* 38275 */ "t2MSRbanked\000" |
| 14120 | /* 38287 */ "t2MRSbanked\000" |
| 14121 | /* 38299 */ "BL_pred\000" |
| 14122 | /* 38307 */ "BX_pred\000" |
| 14123 | /* 38315 */ "BLX_pred\000" |
| 14124 | /* 38324 */ "VCMLAv2f32_indexed\000" |
| 14125 | /* 38343 */ "VCMLAv4f32_indexed\000" |
| 14126 | /* 38362 */ "VCMLAv4f16_indexed\000" |
| 14127 | /* 38381 */ "VCMLAv8f16_indexed\000" |
| 14128 | /* 38400 */ "VLD2q32PseudoWB_fixed\000" |
| 14129 | /* 38422 */ "VST2q32PseudoWB_fixed\000" |
| 14130 | /* 38444 */ "VLD2q16PseudoWB_fixed\000" |
| 14131 | /* 38466 */ "VST2q16PseudoWB_fixed\000" |
| 14132 | /* 38488 */ "VLD2q8PseudoWB_fixed\000" |
| 14133 | /* 38509 */ "VST2q8PseudoWB_fixed\000" |
| 14134 | /* 38530 */ "VLD1d32QPseudoWB_fixed\000" |
| 14135 | /* 38553 */ "VST1d32QPseudoWB_fixed\000" |
| 14136 | /* 38576 */ "VLD1d64QPseudoWB_fixed\000" |
| 14137 | /* 38599 */ "VST1d64QPseudoWB_fixed\000" |
| 14138 | /* 38622 */ "VLD1d16QPseudoWB_fixed\000" |
| 14139 | /* 38645 */ "VST1d16QPseudoWB_fixed\000" |
| 14140 | /* 38668 */ "VLD1d8QPseudoWB_fixed\000" |
| 14141 | /* 38690 */ "VST1d8QPseudoWB_fixed\000" |
| 14142 | /* 38712 */ "VLD1d32TPseudoWB_fixed\000" |
| 14143 | /* 38735 */ "VST1d32TPseudoWB_fixed\000" |
| 14144 | /* 38758 */ "VLD1d64TPseudoWB_fixed\000" |
| 14145 | /* 38781 */ "VST1d64TPseudoWB_fixed\000" |
| 14146 | /* 38804 */ "VLD1d16TPseudoWB_fixed\000" |
| 14147 | /* 38827 */ "VST1d16TPseudoWB_fixed\000" |
| 14148 | /* 38850 */ "VLD1d8TPseudoWB_fixed\000" |
| 14149 | /* 38872 */ "VST1d8TPseudoWB_fixed\000" |
| 14150 | /* 38894 */ "VLD2DUPq32OddPseudoWB_fixed\000" |
| 14151 | /* 38922 */ "VLD2DUPq16OddPseudoWB_fixed\000" |
| 14152 | /* 38950 */ "VLD2DUPq8OddPseudoWB_fixed\000" |
| 14153 | /* 38977 */ "VLD2b32wb_fixed\000" |
| 14154 | /* 38993 */ "VST2b32wb_fixed\000" |
| 14155 | /* 39009 */ "VLD1d32wb_fixed\000" |
| 14156 | /* 39025 */ "VST1d32wb_fixed\000" |
| 14157 | /* 39041 */ "VLD2d32wb_fixed\000" |
| 14158 | /* 39057 */ "VST2d32wb_fixed\000" |
| 14159 | /* 39073 */ "VLD1DUPd32wb_fixed\000" |
| 14160 | /* 39092 */ "VLD2DUPd32wb_fixed\000" |
| 14161 | /* 39111 */ "VLD1q32wb_fixed\000" |
| 14162 | /* 39127 */ "VST1q32wb_fixed\000" |
| 14163 | /* 39143 */ "VLD2q32wb_fixed\000" |
| 14164 | /* 39159 */ "VST2q32wb_fixed\000" |
| 14165 | /* 39175 */ "VLD1DUPq32wb_fixed\000" |
| 14166 | /* 39194 */ "VLD2DUPd32x2wb_fixed\000" |
| 14167 | /* 39215 */ "VLD2DUPd16x2wb_fixed\000" |
| 14168 | /* 39236 */ "VLD2DUPd8x2wb_fixed\000" |
| 14169 | /* 39256 */ "VLD1d64wb_fixed\000" |
| 14170 | /* 39272 */ "VST1d64wb_fixed\000" |
| 14171 | /* 39288 */ "VLD1q64wb_fixed\000" |
| 14172 | /* 39304 */ "VST1q64wb_fixed\000" |
| 14173 | /* 39320 */ "VLD2b16wb_fixed\000" |
| 14174 | /* 39336 */ "VST2b16wb_fixed\000" |
| 14175 | /* 39352 */ "VLD1d16wb_fixed\000" |
| 14176 | /* 39368 */ "VST1d16wb_fixed\000" |
| 14177 | /* 39384 */ "VLD2d16wb_fixed\000" |
| 14178 | /* 39400 */ "VST2d16wb_fixed\000" |
| 14179 | /* 39416 */ "VLD1DUPd16wb_fixed\000" |
| 14180 | /* 39435 */ "VLD2DUPd16wb_fixed\000" |
| 14181 | /* 39454 */ "VLD1q16wb_fixed\000" |
| 14182 | /* 39470 */ "VST1q16wb_fixed\000" |
| 14183 | /* 39486 */ "VLD2q16wb_fixed\000" |
| 14184 | /* 39502 */ "VST2q16wb_fixed\000" |
| 14185 | /* 39518 */ "VLD1DUPq16wb_fixed\000" |
| 14186 | /* 39537 */ "VLD2b8wb_fixed\000" |
| 14187 | /* 39552 */ "VST2b8wb_fixed\000" |
| 14188 | /* 39567 */ "VLD1d8wb_fixed\000" |
| 14189 | /* 39582 */ "VST1d8wb_fixed\000" |
| 14190 | /* 39597 */ "VLD2d8wb_fixed\000" |
| 14191 | /* 39612 */ "VST2d8wb_fixed\000" |
| 14192 | /* 39627 */ "VLD1DUPd8wb_fixed\000" |
| 14193 | /* 39645 */ "VLD2DUPd8wb_fixed\000" |
| 14194 | /* 39663 */ "VLD1q8wb_fixed\000" |
| 14195 | /* 39678 */ "VST1q8wb_fixed\000" |
| 14196 | /* 39693 */ "VLD2q8wb_fixed\000" |
| 14197 | /* 39708 */ "VST2q8wb_fixed\000" |
| 14198 | /* 39723 */ "VLD1DUPq8wb_fixed\000" |
| 14199 | /* 39741 */ "VLD1d32Qwb_fixed\000" |
| 14200 | /* 39758 */ "VST1d32Qwb_fixed\000" |
| 14201 | /* 39775 */ "VLD1d64Qwb_fixed\000" |
| 14202 | /* 39792 */ "VST1d64Qwb_fixed\000" |
| 14203 | /* 39809 */ "VLD1d16Qwb_fixed\000" |
| 14204 | /* 39826 */ "VST1d16Qwb_fixed\000" |
| 14205 | /* 39843 */ "VLD1d8Qwb_fixed\000" |
| 14206 | /* 39859 */ "VST1d8Qwb_fixed\000" |
| 14207 | /* 39875 */ "VLD1d32Twb_fixed\000" |
| 14208 | /* 39892 */ "VST1d32Twb_fixed\000" |
| 14209 | /* 39909 */ "VLD1d64Twb_fixed\000" |
| 14210 | /* 39926 */ "VST1d64Twb_fixed\000" |
| 14211 | /* 39943 */ "VLD1d16Twb_fixed\000" |
| 14212 | /* 39960 */ "VST1d16Twb_fixed\000" |
| 14213 | /* 39977 */ "VLD1d8Twb_fixed\000" |
| 14214 | /* 39993 */ "VST1d8Twb_fixed\000" |
| 14215 | /* 40009 */ "VCVTs2fd\000" |
| 14216 | /* 40018 */ "VCVTxs2fd\000" |
| 14217 | /* 40028 */ "VCVTu2fd\000" |
| 14218 | /* 40037 */ "VCVTxu2fd\000" |
| 14219 | /* 40047 */ "VMLAfd\000" |
| 14220 | /* 40054 */ "VFMAfd\000" |
| 14221 | /* 40061 */ "VSUBfd\000" |
| 14222 | /* 40068 */ "VABDfd\000" |
| 14223 | /* 40075 */ "VADDfd\000" |
| 14224 | /* 40082 */ "VACGEfd\000" |
| 14225 | /* 40090 */ "VCGEfd\000" |
| 14226 | /* 40097 */ "VRECPEfd\000" |
| 14227 | /* 40106 */ "VRSQRTEfd\000" |
| 14228 | /* 40116 */ "VNEGfd\000" |
| 14229 | /* 40123 */ "VMULfd\000" |
| 14230 | /* 40130 */ "VMINfd\000" |
| 14231 | /* 40137 */ "VCEQfd\000" |
| 14232 | /* 40144 */ "VABSfd\000" |
| 14233 | /* 40151 */ "VMLSfd\000" |
| 14234 | /* 40158 */ "VFMSfd\000" |
| 14235 | /* 40165 */ "VRECPSfd\000" |
| 14236 | /* 40174 */ "VRSQRTSfd\000" |
| 14237 | /* 40184 */ "VACGTfd\000" |
| 14238 | /* 40192 */ "VCGTfd\000" |
| 14239 | /* 40199 */ "VMAXfd\000" |
| 14240 | /* 40206 */ "VMLAslfd\000" |
| 14241 | /* 40215 */ "VMULslfd\000" |
| 14242 | /* 40224 */ "VMLSslfd\000" |
| 14243 | /* 40233 */ "VCVTs2hd\000" |
| 14244 | /* 40242 */ "VCVTxs2hd\000" |
| 14245 | /* 40252 */ "VCVTu2hd\000" |
| 14246 | /* 40261 */ "VCVTxu2hd\000" |
| 14247 | /* 40271 */ "VMLAhd\000" |
| 14248 | /* 40278 */ "VFMAhd\000" |
| 14249 | /* 40285 */ "VSUBhd\000" |
| 14250 | /* 40292 */ "VABDhd\000" |
| 14251 | /* 40299 */ "VADDhd\000" |
| 14252 | /* 40306 */ "VACGEhd\000" |
| 14253 | /* 40314 */ "VCGEhd\000" |
| 14254 | /* 40321 */ "VRECPEhd\000" |
| 14255 | /* 40330 */ "VRSQRTEhd\000" |
| 14256 | /* 40340 */ "VNEGhd\000" |
| 14257 | /* 40347 */ "VMULhd\000" |
| 14258 | /* 40354 */ "VMINhd\000" |
| 14259 | /* 40361 */ "VCEQhd\000" |
| 14260 | /* 40368 */ "VABShd\000" |
| 14261 | /* 40375 */ "VMLShd\000" |
| 14262 | /* 40382 */ "VFMShd\000" |
| 14263 | /* 40389 */ "VRECPShd\000" |
| 14264 | /* 40398 */ "VRSQRTShd\000" |
| 14265 | /* 40408 */ "VACGThd\000" |
| 14266 | /* 40416 */ "VCGThd\000" |
| 14267 | /* 40423 */ "VMAXhd\000" |
| 14268 | /* 40430 */ "VMLAslhd\000" |
| 14269 | /* 40439 */ "VMULslhd\000" |
| 14270 | /* 40448 */ "VMLSslhd\000" |
| 14271 | /* 40457 */ "SEH_EpilogEnd\000" |
| 14272 | /* 40471 */ "SEH_PrologEnd\000" |
| 14273 | /* 40485 */ "t2LoopEnd\000" |
| 14274 | /* 40495 */ "VMULpd\000" |
| 14275 | /* 40502 */ "VCVTf2sd\000" |
| 14276 | /* 40511 */ "VCVTh2sd\000" |
| 14277 | /* 40520 */ "VCVTf2xsd\000" |
| 14278 | /* 40530 */ "VCVTh2xsd\000" |
| 14279 | /* 40540 */ "VCVTf2ud\000" |
| 14280 | /* 40549 */ "VCVTh2ud\000" |
| 14281 | /* 40558 */ "VCVTf2xud\000" |
| 14282 | /* 40568 */ "VCVTh2xud\000" |
| 14283 | /* 40578 */ "tADDframe\000" |
| 14284 | /* 40588 */ "MQQPRStore\000" |
| 14285 | /* 40599 */ "MQQQQPRStore\000" |
| 14286 | /* 40612 */ "VLDR_P0_pre\000" |
| 14287 | /* 40624 */ "VSTR_P0_pre\000" |
| 14288 | /* 40636 */ "MVE_VSTRB32_pre\000" |
| 14289 | /* 40652 */ "MVE_VSTRH32_pre\000" |
| 14290 | /* 40668 */ "MVE_VLDRBS32_pre\000" |
| 14291 | /* 40685 */ "MVE_VLDRHS32_pre\000" |
| 14292 | /* 40702 */ "MVE_VLDRBU32_pre\000" |
| 14293 | /* 40719 */ "MVE_VLDRHU32_pre\000" |
| 14294 | /* 40736 */ "MVE_VLDRWU32_pre\000" |
| 14295 | /* 40753 */ "MVE_VSTRWU32_pre\000" |
| 14296 | /* 40770 */ "MVE_VSTRB16_pre\000" |
| 14297 | /* 40786 */ "MVE_VLDRBS16_pre\000" |
| 14298 | /* 40803 */ "MVE_VLDRBU16_pre\000" |
| 14299 | /* 40820 */ "MVE_VLDRHU16_pre\000" |
| 14300 | /* 40837 */ "MVE_VSTRHU16_pre\000" |
| 14301 | /* 40854 */ "MVE_VLDRBU8_pre\000" |
| 14302 | /* 40870 */ "MVE_VSTRBU8_pre\000" |
| 14303 | /* 40886 */ "VLDR_FPSCR_NZCVQC_pre\000" |
| 14304 | /* 40908 */ "VSTR_FPSCR_NZCVQC_pre\000" |
| 14305 | /* 40930 */ "VLDR_FPSCR_pre\000" |
| 14306 | /* 40945 */ "VSTR_FPSCR_pre\000" |
| 14307 | /* 40960 */ "VLDR_VPR_pre\000" |
| 14308 | /* 40973 */ "VSTR_VPR_pre\000" |
| 14309 | /* 40986 */ "VLDR_FPCXTNS_pre\000" |
| 14310 | /* 41003 */ "VSTR_FPCXTNS_pre\000" |
| 14311 | /* 41020 */ "VLDR_FPCXTS_pre\000" |
| 14312 | /* 41036 */ "VSTR_FPCXTS_pre\000" |
| 14313 | /* 41052 */ "MVE_VLDRWU32_qi_pre\000" |
| 14314 | /* 41072 */ "MVE_VSTRW32_qi_pre\000" |
| 14315 | /* 41091 */ "MVE_VSTRD64_qi_pre\000" |
| 14316 | /* 41110 */ "MVE_VLDRDU64_qi_pre\000" |
| 14317 | /* 41130 */ "t2LEUpdate\000" |
| 14318 | /* 41141 */ "VCVTh2f\000" |
| 14319 | /* 41149 */ "VPADDf\000" |
| 14320 | /* 41156 */ "VRINTANDf\000" |
| 14321 | /* 41166 */ "NEON_VMINNMNDf\000" |
| 14322 | /* 41181 */ "NEON_VMAXNMNDf\000" |
| 14323 | /* 41196 */ "VRINTMNDf\000" |
| 14324 | /* 41206 */ "VRINTNNDf\000" |
| 14325 | /* 41216 */ "VRINTPNDf\000" |
| 14326 | /* 41226 */ "VRINTXNDf\000" |
| 14327 | /* 41236 */ "VRINTZNDf\000" |
| 14328 | /* 41246 */ "VCVTANSDf\000" |
| 14329 | /* 41256 */ "VCVTMNSDf\000" |
| 14330 | /* 41266 */ "VCVTNNSDf\000" |
| 14331 | /* 41276 */ "VCVTPNSDf\000" |
| 14332 | /* 41286 */ "VCVTANUDf\000" |
| 14333 | /* 41296 */ "VCVTMNUDf\000" |
| 14334 | /* 41306 */ "VCVTNNUDf\000" |
| 14335 | /* 41316 */ "VCVTPNUDf\000" |
| 14336 | /* 41326 */ "VPMINf\000" |
| 14337 | /* 41333 */ "VRINTANQf\000" |
| 14338 | /* 41343 */ "NEON_VMINNMNQf\000" |
| 14339 | /* 41358 */ "NEON_VMAXNMNQf\000" |
| 14340 | /* 41373 */ "VRINTMNQf\000" |
| 14341 | /* 41383 */ "VRINTNNQf\000" |
| 14342 | /* 41393 */ "VRINTPNQf\000" |
| 14343 | /* 41403 */ "VRINTXNQf\000" |
| 14344 | /* 41413 */ "VRINTZNQf\000" |
| 14345 | /* 41423 */ "VCVTANSQf\000" |
| 14346 | /* 41433 */ "VCVTMNSQf\000" |
| 14347 | /* 41443 */ "VCVTNNSQf\000" |
| 14348 | /* 41453 */ "VCVTPNSQf\000" |
| 14349 | /* 41463 */ "VCVTANUQf\000" |
| 14350 | /* 41473 */ "VCVTMNUQf\000" |
| 14351 | /* 41483 */ "VCVTNNUQf\000" |
| 14352 | /* 41493 */ "VCVTPNUQf\000" |
| 14353 | /* 41503 */ "VPMAXf\000" |
| 14354 | /* 41510 */ "VLDR_P0_off\000" |
| 14355 | /* 41522 */ "VSTR_P0_off\000" |
| 14356 | /* 41534 */ "VLDR_FPSCR_NZCVQC_off\000" |
| 14357 | /* 41556 */ "VSTR_FPSCR_NZCVQC_off\000" |
| 14358 | /* 41578 */ "VLDR_FPSCR_off\000" |
| 14359 | /* 41593 */ "VSTR_FPSCR_off\000" |
| 14360 | /* 41608 */ "VLDR_VPR_off\000" |
| 14361 | /* 41621 */ "VSTR_VPR_off\000" |
| 14362 | /* 41634 */ "VLDR_FPCXTNS_off\000" |
| 14363 | /* 41651 */ "VSTR_FPCXTNS_off\000" |
| 14364 | /* 41668 */ "VLDR_FPCXTS_off\000" |
| 14365 | /* 41684 */ "VSTR_FPCXTS_off\000" |
| 14366 | /* 41700 */ "tBX_RET_vararg\000" |
| 14367 | /* 41715 */ "VCVTf2h\000" |
| 14368 | /* 41723 */ "VPADDh\000" |
| 14369 | /* 41730 */ "VRINTANDh\000" |
| 14370 | /* 41740 */ "NEON_VMINNMNDh\000" |
| 14371 | /* 41755 */ "NEON_VMAXNMNDh\000" |
| 14372 | /* 41770 */ "VRINTMNDh\000" |
| 14373 | /* 41780 */ "VRINTNNDh\000" |
| 14374 | /* 41790 */ "VRINTPNDh\000" |
| 14375 | /* 41800 */ "VRINTXNDh\000" |
| 14376 | /* 41810 */ "VRINTZNDh\000" |
| 14377 | /* 41820 */ "VCVTANSDh\000" |
| 14378 | /* 41830 */ "VCVTMNSDh\000" |
| 14379 | /* 41840 */ "VCVTNNSDh\000" |
| 14380 | /* 41850 */ "VCVTPNSDh\000" |
| 14381 | /* 41860 */ "VCVTANUDh\000" |
| 14382 | /* 41870 */ "VCVTMNUDh\000" |
| 14383 | /* 41880 */ "VCVTNNUDh\000" |
| 14384 | /* 41890 */ "VCVTPNUDh\000" |
| 14385 | /* 41900 */ "VPMINh\000" |
| 14386 | /* 41907 */ "VRINTANQh\000" |
| 14387 | /* 41917 */ "NEON_VMINNMNQh\000" |
| 14388 | /* 41932 */ "NEON_VMAXNMNQh\000" |
| 14389 | /* 41947 */ "VRINTMNQh\000" |
| 14390 | /* 41957 */ "VRINTNNQh\000" |
| 14391 | /* 41967 */ "VRINTPNQh\000" |
| 14392 | /* 41977 */ "VRINTXNQh\000" |
| 14393 | /* 41987 */ "VRINTZNQh\000" |
| 14394 | /* 41997 */ "VCVTANSQh\000" |
| 14395 | /* 42007 */ "VCVTMNSQh\000" |
| 14396 | /* 42017 */ "VCVTNNSQh\000" |
| 14397 | /* 42027 */ "VCVTPNSQh\000" |
| 14398 | /* 42037 */ "VCVTANUQh\000" |
| 14399 | /* 42047 */ "VCVTMNUQh\000" |
| 14400 | /* 42057 */ "VCVTNNUQh\000" |
| 14401 | /* 42067 */ "VCVTPNUQh\000" |
| 14402 | /* 42077 */ "VPMAXh\000" |
| 14403 | /* 42084 */ "MVE_VCVTf16f32bh\000" |
| 14404 | /* 42101 */ "MVE_VRSHRNi32bh\000" |
| 14405 | /* 42117 */ "MVE_VSHRNi32bh\000" |
| 14406 | /* 42132 */ "MVE_VMOVNi32bh\000" |
| 14407 | /* 42147 */ "MVE_VQDMULLs32bh\000" |
| 14408 | /* 42164 */ "MVE_VQSHRUNs32bh\000" |
| 14409 | /* 42181 */ "MVE_VQRSHRUNs32bh\000" |
| 14410 | /* 42199 */ "MVE_VQMOVUNs32bh\000" |
| 14411 | /* 42216 */ "MVE_VQMOVNs32bh\000" |
| 14412 | /* 42232 */ "MVE_VQDMULL_qr_s32bh\000" |
| 14413 | /* 42253 */ "MVE_VQMOVNu32bh\000" |
| 14414 | /* 42269 */ "MVE_VCVTf32f16bh\000" |
| 14415 | /* 42286 */ "MVE_VRSHRNi16bh\000" |
| 14416 | /* 42302 */ "MVE_VSHRNi16bh\000" |
| 14417 | /* 42317 */ "MVE_VMOVNi16bh\000" |
| 14418 | /* 42332 */ "MVE_VQDMULLs16bh\000" |
| 14419 | /* 42349 */ "MVE_VMOVLs16bh\000" |
| 14420 | /* 42364 */ "MVE_VQSHRUNs16bh\000" |
| 14421 | /* 42381 */ "MVE_VQRSHRUNs16bh\000" |
| 14422 | /* 42399 */ "MVE_VQMOVUNs16bh\000" |
| 14423 | /* 42416 */ "MVE_VQMOVNs16bh\000" |
| 14424 | /* 42432 */ "MVE_VQDMULL_qr_s16bh\000" |
| 14425 | /* 42453 */ "MVE_VSHLL_imms16bh\000" |
| 14426 | /* 42472 */ "MVE_VSHLL_lws16bh\000" |
| 14427 | /* 42490 */ "MVE_VMOVLu16bh\000" |
| 14428 | /* 42505 */ "MVE_VQMOVNu16bh\000" |
| 14429 | /* 42521 */ "MVE_VSHLL_immu16bh\000" |
| 14430 | /* 42540 */ "MVE_VSHLL_lwu16bh\000" |
| 14431 | /* 42558 */ "MVE_VMOVLs8bh\000" |
| 14432 | /* 42572 */ "MVE_VSHLL_imms8bh\000" |
| 14433 | /* 42590 */ "MVE_VSHLL_lws8bh\000" |
| 14434 | /* 42607 */ "MVE_VMOVLu8bh\000" |
| 14435 | /* 42621 */ "MVE_VSHLL_immu8bh\000" |
| 14436 | /* 42639 */ "MVE_VSHLL_lwu8bh\000" |
| 14437 | /* 42656 */ "Int_eh_sjlj_setup_dispatch\000" |
| 14438 | /* 42683 */ "MVE_VCVTf16f32th\000" |
| 14439 | /* 42700 */ "MVE_VRSHRNi32th\000" |
| 14440 | /* 42716 */ "MVE_VSHRNi32th\000" |
| 14441 | /* 42731 */ "MVE_VMOVNi32th\000" |
| 14442 | /* 42746 */ "MVE_VQDMULLs32th\000" |
| 14443 | /* 42763 */ "MVE_VQSHRUNs32th\000" |
| 14444 | /* 42780 */ "MVE_VQRSHRUNs32th\000" |
| 14445 | /* 42798 */ "MVE_VQMOVUNs32th\000" |
| 14446 | /* 42815 */ "MVE_VQMOVNs32th\000" |
| 14447 | /* 42831 */ "MVE_VQDMULL_qr_s32th\000" |
| 14448 | /* 42852 */ "MVE_VQMOVNu32th\000" |
| 14449 | /* 42868 */ "MVE_VCVTf32f16th\000" |
| 14450 | /* 42885 */ "MVE_VRSHRNi16th\000" |
| 14451 | /* 42901 */ "MVE_VSHRNi16th\000" |
| 14452 | /* 42916 */ "MVE_VMOVNi16th\000" |
| 14453 | /* 42931 */ "MVE_VQDMULLs16th\000" |
| 14454 | /* 42948 */ "MVE_VMOVLs16th\000" |
| 14455 | /* 42963 */ "MVE_VQSHRUNs16th\000" |
| 14456 | /* 42980 */ "MVE_VQRSHRUNs16th\000" |
| 14457 | /* 42998 */ "MVE_VQMOVUNs16th\000" |
| 14458 | /* 43015 */ "MVE_VQMOVNs16th\000" |
| 14459 | /* 43031 */ "MVE_VQDMULL_qr_s16th\000" |
| 14460 | /* 43052 */ "MVE_VSHLL_imms16th\000" |
| 14461 | /* 43071 */ "MVE_VSHLL_lws16th\000" |
| 14462 | /* 43089 */ "MVE_VMOVLu16th\000" |
| 14463 | /* 43104 */ "MVE_VQMOVNu16th\000" |
| 14464 | /* 43120 */ "MVE_VSHLL_immu16th\000" |
| 14465 | /* 43139 */ "MVE_VSHLL_lwu16th\000" |
| 14466 | /* 43157 */ "MVE_VMOVLs8th\000" |
| 14467 | /* 43171 */ "MVE_VSHLL_imms8th\000" |
| 14468 | /* 43189 */ "MVE_VSHLL_lws8th\000" |
| 14469 | /* 43206 */ "MVE_VMOVLu8th\000" |
| 14470 | /* 43220 */ "MVE_VSHLL_immu8th\000" |
| 14471 | /* 43238 */ "MVE_VSHLL_lwu8th\000" |
| 14472 | /* 43255 */ "tLDRBi\000" |
| 14473 | /* 43262 */ "tSTRBi\000" |
| 14474 | /* 43269 */ "t2MVNCCi\000" |
| 14475 | /* 43278 */ "t2MOVCCi\000" |
| 14476 | /* 43287 */ "t2BFi\000" |
| 14477 | /* 43293 */ "tLDRHi\000" |
| 14478 | /* 43300 */ "tSTRHi\000" |
| 14479 | /* 43307 */ "t2BFLi\000" |
| 14480 | /* 43314 */ "MVE_LSLLi\000" |
| 14481 | /* 43324 */ "MVE_ASRLi\000" |
| 14482 | /* 43334 */ "LSLi\000" |
| 14483 | /* 43339 */ "t2MVNi\000" |
| 14484 | /* 43346 */ "tADDrSPi\000" |
| 14485 | /* 43355 */ "tLDRi\000" |
| 14486 | /* 43361 */ "RORi\000" |
| 14487 | /* 43366 */ "ASRi\000" |
| 14488 | /* 43371 */ "LSRi\000" |
| 14489 | /* 43376 */ "MSRi\000" |
| 14490 | /* 43381 */ "tSTRi\000" |
| 14491 | /* 43387 */ "LDRSBTi\000" |
| 14492 | /* 43395 */ "LDRHTi\000" |
| 14493 | /* 43402 */ "STRHTi\000" |
| 14494 | /* 43409 */ "LDRSHTi\000" |
| 14495 | /* 43417 */ "t2MOVi\000" |
| 14496 | /* 43424 */ "tBLXi\000" |
| 14497 | /* 43430 */ "RRXi\000" |
| 14498 | /* 43435 */ "t2LDRBpci\000" |
| 14499 | /* 43445 */ "t2LDRSBpci\000" |
| 14500 | /* 43456 */ "t2PLDpci\000" |
| 14501 | /* 43465 */ "t2LDRHpci\000" |
| 14502 | /* 43475 */ "t2LDRSHpci\000" |
| 14503 | /* 43486 */ "t2PLIpci\000" |
| 14504 | /* 43495 */ "t2LDRpci\000" |
| 14505 | /* 43504 */ "tLDRpci\000" |
| 14506 | /* 43512 */ "TCRETURNdi\000" |
| 14507 | /* 43523 */ "LDRSBTii\000" |
| 14508 | /* 43532 */ "LDRHTii\000" |
| 14509 | /* 43540 */ "LDRSHTii\000" |
| 14510 | /* 43549 */ "tSUBspi\000" |
| 14511 | /* 43557 */ "tADDspi\000" |
| 14512 | /* 43565 */ "tLDRspi\000" |
| 14513 | /* 43573 */ "tSTRspi\000" |
| 14514 | /* 43581 */ "MVE_VLDRWU32_qi\000" |
| 14515 | /* 43597 */ "MVE_VSTRW32_qi\000" |
| 14516 | /* 43612 */ "MVE_VSTRD64_qi\000" |
| 14517 | /* 43627 */ "MVE_VLDRDU64_qi\000" |
| 14518 | /* 43643 */ "t2RSBri\000" |
| 14519 | /* 43651 */ "t2SUBri\000" |
| 14520 | /* 43659 */ "t2SBCri\000" |
| 14521 | /* 43667 */ "t2ADCri\000" |
| 14522 | /* 43675 */ "t2BICri\000" |
| 14523 | /* 43683 */ "RSCri\000" |
| 14524 | /* 43689 */ "t2ADDri\000" |
| 14525 | /* 43697 */ "t2ANDri\000" |
| 14526 | /* 43705 */ "t2LSLri\000" |
| 14527 | /* 43713 */ "tLSLri\000" |
| 14528 | /* 43720 */ "t2CMNri\000" |
| 14529 | /* 43728 */ "t2ORNri\000" |
| 14530 | /* 43736 */ "TCRETURNri\000" |
| 14531 | /* 43747 */ "t2CMPri\000" |
| 14532 | /* 43755 */ "t2TEQri\000" |
| 14533 | /* 43763 */ "t2EORri\000" |
| 14534 | /* 43771 */ "t2RORri\000" |
| 14535 | /* 43779 */ "t2ORRri\000" |
| 14536 | /* 43787 */ "t2ASRri\000" |
| 14537 | /* 43795 */ "tASRri\000" |
| 14538 | /* 43802 */ "t2LSRri\000" |
| 14539 | /* 43810 */ "tLSRri\000" |
| 14540 | /* 43817 */ "t2RSBSri\000" |
| 14541 | /* 43826 */ "t2SUBSri\000" |
| 14542 | /* 43835 */ "t2ADDSri\000" |
| 14543 | /* 43844 */ "tLSLSri\000" |
| 14544 | /* 43852 */ "t2TSTri\000" |
| 14545 | /* 43860 */ "MOVCCsi\000" |
| 14546 | /* 43868 */ "MVNsi\000" |
| 14547 | /* 43874 */ "t2MOVSsi\000" |
| 14548 | /* 43883 */ "t2MOVsi\000" |
| 14549 | /* 43891 */ "RSBrsi\000" |
| 14550 | /* 43898 */ "SUBrsi\000" |
| 14551 | /* 43905 */ "SBCrsi\000" |
| 14552 | /* 43912 */ "ADCrsi\000" |
| 14553 | /* 43919 */ "BICrsi\000" |
| 14554 | /* 43926 */ "RSCrsi\000" |
| 14555 | /* 43933 */ "ADDrsi\000" |
| 14556 | /* 43940 */ "ANDrsi\000" |
| 14557 | /* 43947 */ "CMPrsi\000" |
| 14558 | /* 43954 */ "TEQrsi\000" |
| 14559 | /* 43961 */ "EORrsi\000" |
| 14560 | /* 43968 */ "ORRrsi\000" |
| 14561 | /* 43975 */ "RSBSrsi\000" |
| 14562 | /* 43983 */ "SUBSrsi\000" |
| 14563 | /* 43991 */ "ADDSrsi\000" |
| 14564 | /* 43999 */ "TSTrsi\000" |
| 14565 | /* 44006 */ "CMNzrsi\000" |
| 14566 | /* 44014 */ "TRAPNaCl\000" |
| 14567 | /* 44023 */ "t2LEApcrel\000" |
| 14568 | /* 44034 */ "tLEApcrel\000" |
| 14569 | /* 44044 */ "t2LDRBpcrel\000" |
| 14570 | /* 44056 */ "t2LDRSBpcrel\000" |
| 14571 | /* 44069 */ "t2LDRHpcrel\000" |
| 14572 | /* 44081 */ "t2LDRSHpcrel\000" |
| 14573 | /* 44094 */ "t2LDRpcrel\000" |
| 14574 | /* 44105 */ "t2MOVTi16_ga_pcrel\000" |
| 14575 | /* 44124 */ "t2MOVi16_ga_pcrel\000" |
| 14576 | /* 44142 */ "t2LDRLIT_ga_pcrel\000" |
| 14577 | /* 44160 */ "tLDRLIT_ga_pcrel\000" |
| 14578 | /* 44177 */ "t2MOV_ga_pcrel\000" |
| 14579 | /* 44192 */ "t2LDRConstPool\000" |
| 14580 | /* 44207 */ "tLDRConstPool\000" |
| 14581 | /* 44221 */ "t2MOVCClsl\000" |
| 14582 | /* 44232 */ "MVE_VCVTs32f32m\000" |
| 14583 | /* 44248 */ "MVE_VCVTu32f32m\000" |
| 14584 | /* 44264 */ "MVE_VCVTs16f16m\000" |
| 14585 | /* 44280 */ "MVE_VCVTu16f16m\000" |
| 14586 | /* 44296 */ "t2SUBspImm\000" |
| 14587 | /* 44307 */ "t2ADDspImm\000" |
| 14588 | /* 44318 */ "t2MOVCCi32imm\000" |
| 14589 | /* 44332 */ "t2MOVi32imm\000" |
| 14590 | /* 44344 */ "tMOVi32imm\000" |
| 14591 | /* 44355 */ "t2LDRB_PRE_imm\000" |
| 14592 | /* 44370 */ "t2STRB_PRE_imm\000" |
| 14593 | /* 44385 */ "t2LDRSB_PRE_imm\000" |
| 14594 | /* 44401 */ "t2LDRH_PRE_imm\000" |
| 14595 | /* 44416 */ "t2STRH_PRE_imm\000" |
| 14596 | /* 44431 */ "t2LDRSH_PRE_imm\000" |
| 14597 | /* 44447 */ "t2LDR_PRE_imm\000" |
| 14598 | /* 44461 */ "t2STR_PRE_imm\000" |
| 14599 | /* 44475 */ "t2LDRB_OFFSET_imm\000" |
| 14600 | /* 44493 */ "t2STRB_OFFSET_imm\000" |
| 14601 | /* 44511 */ "t2LDRSB_OFFSET_imm\000" |
| 14602 | /* 44530 */ "t2LDRH_OFFSET_imm\000" |
| 14603 | /* 44548 */ "t2STRH_OFFSET_imm\000" |
| 14604 | /* 44566 */ "t2LDRSH_OFFSET_imm\000" |
| 14605 | /* 44585 */ "t2LDRB_POST_imm\000" |
| 14606 | /* 44601 */ "t2STRB_POST_imm\000" |
| 14607 | /* 44617 */ "t2LDRSB_POST_imm\000" |
| 14608 | /* 44634 */ "t2LDRH_POST_imm\000" |
| 14609 | /* 44650 */ "t2STRH_POST_imm\000" |
| 14610 | /* 44666 */ "t2LDRSH_POST_imm\000" |
| 14611 | /* 44683 */ "t2LDR_POST_imm\000" |
| 14612 | /* 44698 */ "t2STR_POST_imm\000" |
| 14613 | /* 44713 */ "ITasm\000" |
| 14614 | /* 44719 */ "MVE_VCVTs32f32n\000" |
| 14615 | /* 44735 */ "MVE_VCVTu32f32n\000" |
| 14616 | /* 44751 */ "MVE_VCVTf32s32n\000" |
| 14617 | /* 44767 */ "MVE_VCVTf32u32n\000" |
| 14618 | /* 44783 */ "MVE_VCVTs16f16n\000" |
| 14619 | /* 44799 */ "MVE_VCVTu16f16n\000" |
| 14620 | /* 44815 */ "MVE_VCVTf16s16n\000" |
| 14621 | /* 44831 */ "MVE_VCVTf16u16n\000" |
| 14622 | /* 44847 */ "VLD3d32Pseudo\000" |
| 14623 | /* 44861 */ "VST3d32Pseudo\000" |
| 14624 | /* 44875 */ "VLD4d32Pseudo\000" |
| 14625 | /* 44889 */ "VST4d32Pseudo\000" |
| 14626 | /* 44903 */ "VLD2LNd32Pseudo\000" |
| 14627 | /* 44919 */ "VST2LNd32Pseudo\000" |
| 14628 | /* 44935 */ "VLD3LNd32Pseudo\000" |
| 14629 | /* 44951 */ "VST3LNd32Pseudo\000" |
| 14630 | /* 44967 */ "VLD4LNd32Pseudo\000" |
| 14631 | /* 44983 */ "VST4LNd32Pseudo\000" |
| 14632 | /* 44999 */ "VLD3DUPd32Pseudo\000" |
| 14633 | /* 45016 */ "VLD4DUPd32Pseudo\000" |
| 14634 | /* 45033 */ "VLD2q32Pseudo\000" |
| 14635 | /* 45047 */ "VST2q32Pseudo\000" |
| 14636 | /* 45061 */ "VLD1LNq32Pseudo\000" |
| 14637 | /* 45077 */ "VST1LNq32Pseudo\000" |
| 14638 | /* 45093 */ "VLD2LNq32Pseudo\000" |
| 14639 | /* 45109 */ "VST2LNq32Pseudo\000" |
| 14640 | /* 45125 */ "VLD3LNq32Pseudo\000" |
| 14641 | /* 45141 */ "VST3LNq32Pseudo\000" |
| 14642 | /* 45157 */ "VLD4LNq32Pseudo\000" |
| 14643 | /* 45173 */ "VST4LNq32Pseudo\000" |
| 14644 | /* 45189 */ "VTBL3Pseudo\000" |
| 14645 | /* 45201 */ "VTBX3Pseudo\000" |
| 14646 | /* 45213 */ "VTBL4Pseudo\000" |
| 14647 | /* 45225 */ "VTBX4Pseudo\000" |
| 14648 | /* 45237 */ "VLD3d16Pseudo\000" |
| 14649 | /* 45251 */ "VST3d16Pseudo\000" |
| 14650 | /* 45265 */ "VLD4d16Pseudo\000" |
| 14651 | /* 45279 */ "VST4d16Pseudo\000" |
| 14652 | /* 45293 */ "VLD2LNd16Pseudo\000" |
| 14653 | /* 45309 */ "VST2LNd16Pseudo\000" |
| 14654 | /* 45325 */ "VLD3LNd16Pseudo\000" |
| 14655 | /* 45341 */ "VST3LNd16Pseudo\000" |
| 14656 | /* 45357 */ "VLD4LNd16Pseudo\000" |
| 14657 | /* 45373 */ "VST4LNd16Pseudo\000" |
| 14658 | /* 45389 */ "VLD3DUPd16Pseudo\000" |
| 14659 | /* 45406 */ "VLD4DUPd16Pseudo\000" |
| 14660 | /* 45423 */ "VLD2q16Pseudo\000" |
| 14661 | /* 45437 */ "VST2q16Pseudo\000" |
| 14662 | /* 45451 */ "VLD1LNq16Pseudo\000" |
| 14663 | /* 45467 */ "VST1LNq16Pseudo\000" |
| 14664 | /* 45483 */ "VLD2LNq16Pseudo\000" |
| 14665 | /* 45499 */ "VST2LNq16Pseudo\000" |
| 14666 | /* 45515 */ "VLD3LNq16Pseudo\000" |
| 14667 | /* 45531 */ "VST3LNq16Pseudo\000" |
| 14668 | /* 45547 */ "VLD4LNq16Pseudo\000" |
| 14669 | /* 45563 */ "VST4LNq16Pseudo\000" |
| 14670 | /* 45579 */ "VLD3d8Pseudo\000" |
| 14671 | /* 45592 */ "VST3d8Pseudo\000" |
| 14672 | /* 45605 */ "VLD4d8Pseudo\000" |
| 14673 | /* 45618 */ "VST4d8Pseudo\000" |
| 14674 | /* 45631 */ "VLD2LNd8Pseudo\000" |
| 14675 | /* 45646 */ "VST2LNd8Pseudo\000" |
| 14676 | /* 45661 */ "VLD3LNd8Pseudo\000" |
| 14677 | /* 45676 */ "VST3LNd8Pseudo\000" |
| 14678 | /* 45691 */ "VLD4LNd8Pseudo\000" |
| 14679 | /* 45706 */ "VST4LNd8Pseudo\000" |
| 14680 | /* 45721 */ "VLD3DUPd8Pseudo\000" |
| 14681 | /* 45737 */ "VLD4DUPd8Pseudo\000" |
| 14682 | /* 45753 */ "VLD2q8Pseudo\000" |
| 14683 | /* 45766 */ "VST2q8Pseudo\000" |
| 14684 | /* 45779 */ "VLD1LNq8Pseudo\000" |
| 14685 | /* 45794 */ "VST1LNq8Pseudo\000" |
| 14686 | /* 45809 */ "VLD1d32QPseudo\000" |
| 14687 | /* 45824 */ "VST1d32QPseudo\000" |
| 14688 | /* 45839 */ "VLD1d64QPseudo\000" |
| 14689 | /* 45854 */ "VST1d64QPseudo\000" |
| 14690 | /* 45869 */ "VLD1d16QPseudo\000" |
| 14691 | /* 45884 */ "VST1d16QPseudo\000" |
| 14692 | /* 45899 */ "VLD1d8QPseudo\000" |
| 14693 | /* 45913 */ "VST1d8QPseudo\000" |
| 14694 | /* 45927 */ "VLD1q32HighQPseudo\000" |
| 14695 | /* 45946 */ "VST1q32HighQPseudo\000" |
| 14696 | /* 45965 */ "VLD1q64HighQPseudo\000" |
| 14697 | /* 45984 */ "VST1q64HighQPseudo\000" |
| 14698 | /* 46003 */ "VLD1q16HighQPseudo\000" |
| 14699 | /* 46022 */ "VST1q16HighQPseudo\000" |
| 14700 | /* 46041 */ "VLD1q8HighQPseudo\000" |
| 14701 | /* 46059 */ "VST1q8HighQPseudo\000" |
| 14702 | /* 46077 */ "VLD1d32TPseudo\000" |
| 14703 | /* 46092 */ "VST1d32TPseudo\000" |
| 14704 | /* 46107 */ "VLD1d64TPseudo\000" |
| 14705 | /* 46122 */ "VST1d64TPseudo\000" |
| 14706 | /* 46137 */ "VLD1d16TPseudo\000" |
| 14707 | /* 46152 */ "VST1d16TPseudo\000" |
| 14708 | /* 46167 */ "VLD1d8TPseudo\000" |
| 14709 | /* 46181 */ "VST1d8TPseudo\000" |
| 14710 | /* 46195 */ "VLD1q32HighTPseudo\000" |
| 14711 | /* 46214 */ "VST1q32HighTPseudo\000" |
| 14712 | /* 46233 */ "VLD1q64HighTPseudo\000" |
| 14713 | /* 46252 */ "VST1q64HighTPseudo\000" |
| 14714 | /* 46271 */ "VLD1q16HighTPseudo\000" |
| 14715 | /* 46290 */ "VST1q16HighTPseudo\000" |
| 14716 | /* 46309 */ "VLD1q8HighTPseudo\000" |
| 14717 | /* 46327 */ "VST1q8HighTPseudo\000" |
| 14718 | /* 46345 */ "VLD2DUPq32OddPseudo\000" |
| 14719 | /* 46365 */ "VLD3DUPq32OddPseudo\000" |
| 14720 | /* 46385 */ "VLD4DUPq32OddPseudo\000" |
| 14721 | /* 46405 */ "VLD2DUPq16OddPseudo\000" |
| 14722 | /* 46425 */ "VLD3DUPq16OddPseudo\000" |
| 14723 | /* 46445 */ "VLD4DUPq16OddPseudo\000" |
| 14724 | /* 46465 */ "VLD2DUPq8OddPseudo\000" |
| 14725 | /* 46484 */ "VLD3DUPq8OddPseudo\000" |
| 14726 | /* 46503 */ "VLD4DUPq8OddPseudo\000" |
| 14727 | /* 46522 */ "VLD3q32oddPseudo\000" |
| 14728 | /* 46539 */ "VST3q32oddPseudo\000" |
| 14729 | /* 46556 */ "VLD4q32oddPseudo\000" |
| 14730 | /* 46573 */ "VST4q32oddPseudo\000" |
| 14731 | /* 46590 */ "VLD3q16oddPseudo\000" |
| 14732 | /* 46607 */ "VST3q16oddPseudo\000" |
| 14733 | /* 46624 */ "VLD4q16oddPseudo\000" |
| 14734 | /* 46641 */ "VST4q16oddPseudo\000" |
| 14735 | /* 46658 */ "VLD3q8oddPseudo\000" |
| 14736 | /* 46674 */ "VST3q8oddPseudo\000" |
| 14737 | /* 46690 */ "VLD4q8oddPseudo\000" |
| 14738 | /* 46706 */ "VST4q8oddPseudo\000" |
| 14739 | /* 46722 */ "t2BF_LabelPseudo\000" |
| 14740 | /* 46739 */ "VLD2DUPq32EvenPseudo\000" |
| 14741 | /* 46760 */ "VLD3DUPq32EvenPseudo\000" |
| 14742 | /* 46781 */ "VLD4DUPq32EvenPseudo\000" |
| 14743 | /* 46802 */ "VLD2DUPq16EvenPseudo\000" |
| 14744 | /* 46823 */ "VLD3DUPq16EvenPseudo\000" |
| 14745 | /* 46844 */ "VLD4DUPq16EvenPseudo\000" |
| 14746 | /* 46865 */ "VLD2DUPq8EvenPseudo\000" |
| 14747 | /* 46885 */ "VLD3DUPq8EvenPseudo\000" |
| 14748 | /* 46905 */ "VLD4DUPq8EvenPseudo\000" |
| 14749 | /* 46925 */ "tMOVCCr_pseudo\000" |
| 14750 | /* 46940 */ "t2CPS1p\000" |
| 14751 | /* 46948 */ "MVE_VCVTs32f32p\000" |
| 14752 | /* 46964 */ "MVE_VCVTu32f32p\000" |
| 14753 | /* 46980 */ "t2CPS2p\000" |
| 14754 | /* 46988 */ "t2CPS3p\000" |
| 14755 | /* 46996 */ "MVE_VCVTs16f16p\000" |
| 14756 | /* 47012 */ "MVE_VCVTu16f16p\000" |
| 14757 | /* 47028 */ "LDRcp\000" |
| 14758 | /* 47034 */ "CDE_VCX1_fpdp\000" |
| 14759 | /* 47048 */ "CDE_VCX2_fpdp\000" |
| 14760 | /* 47062 */ "CDE_VCX3_fpdp\000" |
| 14761 | /* 47076 */ "CDE_VCX1A_fpdp\000" |
| 14762 | /* 47091 */ "CDE_VCX2A_fpdp\000" |
| 14763 | /* 47106 */ "CDE_VCX3A_fpdp\000" |
| 14764 | /* 47121 */ "t2Int_eh_sjlj_setjmp_nofp\000" |
| 14765 | /* 47147 */ "BLX_noip\000" |
| 14766 | /* 47156 */ "BLX_pred_noip\000" |
| 14767 | /* 47170 */ "tBLXr_noip\000" |
| 14768 | /* 47181 */ "tInt_WIN_eh_sjlj_longjmp\000" |
| 14769 | /* 47206 */ "tInt_eh_sjlj_longjmp\000" |
| 14770 | /* 47227 */ "t2Int_eh_sjlj_setjmp\000" |
| 14771 | /* 47248 */ "tInt_eh_sjlj_setjmp\000" |
| 14772 | /* 47268 */ "SEH_Nop\000" |
| 14773 | /* 47276 */ "CDE_VCX1_fpsp\000" |
| 14774 | /* 47290 */ "CDE_VCX2_fpsp\000" |
| 14775 | /* 47304 */ "CDE_VCX3_fpsp\000" |
| 14776 | /* 47318 */ "CDE_VCX1A_fpsp\000" |
| 14777 | /* 47333 */ "CDE_VCX2A_fpsp\000" |
| 14778 | /* 47348 */ "CDE_VCX3A_fpsp\000" |
| 14779 | /* 47363 */ "t2WhileLoopSetup\000" |
| 14780 | /* 47380 */ "Int_eh_sjlj_dispatchsetup\000" |
| 14781 | /* 47406 */ "VDUPLN32q\000" |
| 14782 | /* 47416 */ "VDUP32q\000" |
| 14783 | /* 47424 */ "VNEGf32q\000" |
| 14784 | /* 47433 */ "VNEGs32q\000" |
| 14785 | /* 47442 */ "VDUPLN16q\000" |
| 14786 | /* 47452 */ "VDUP16q\000" |
| 14787 | /* 47460 */ "VNEGs16q\000" |
| 14788 | /* 47469 */ "VDUPLN8q\000" |
| 14789 | /* 47478 */ "VDUP8q\000" |
| 14790 | /* 47485 */ "VNEGs8q\000" |
| 14791 | /* 47493 */ "VBICq\000" |
| 14792 | /* 47499 */ "VANDq\000" |
| 14793 | /* 47505 */ "VRECPEq\000" |
| 14794 | /* 47513 */ "VRSQRTEq\000" |
| 14795 | /* 47522 */ "VBIFq\000" |
| 14796 | /* 47528 */ "VBSLq\000" |
| 14797 | /* 47534 */ "VORNq\000" |
| 14798 | /* 47540 */ "VMVNq\000" |
| 14799 | /* 47546 */ "VBSPq\000" |
| 14800 | /* 47552 */ "VSWPq\000" |
| 14801 | /* 47558 */ "VEORq\000" |
| 14802 | /* 47564 */ "VORRq\000" |
| 14803 | /* 47570 */ "VBITq\000" |
| 14804 | /* 47576 */ "VCNTq\000" |
| 14805 | /* 47582 */ "MVE_VMOV_rr_q\000" |
| 14806 | /* 47596 */ "VCVTs2fq\000" |
| 14807 | /* 47605 */ "VCVTxs2fq\000" |
| 14808 | /* 47615 */ "VCVTu2fq\000" |
| 14809 | /* 47624 */ "VCVTxu2fq\000" |
| 14810 | /* 47634 */ "VMLAfq\000" |
| 14811 | /* 47641 */ "VFMAfq\000" |
| 14812 | /* 47648 */ "VSUBfq\000" |
| 14813 | /* 47655 */ "VABDfq\000" |
| 14814 | /* 47662 */ "VADDfq\000" |
| 14815 | /* 47669 */ "VACGEfq\000" |
| 14816 | /* 47677 */ "VCGEfq\000" |
| 14817 | /* 47684 */ "VRECPEfq\000" |
| 14818 | /* 47693 */ "VRSQRTEfq\000" |
| 14819 | /* 47703 */ "VMULfq\000" |
| 14820 | /* 47710 */ "VMINfq\000" |
| 14821 | /* 47717 */ "VCEQfq\000" |
| 14822 | /* 47724 */ "VABSfq\000" |
| 14823 | /* 47731 */ "VMLSfq\000" |
| 14824 | /* 47738 */ "VFMSfq\000" |
| 14825 | /* 47745 */ "VRECPSfq\000" |
| 14826 | /* 47754 */ "VRSQRTSfq\000" |
| 14827 | /* 47764 */ "VACGTfq\000" |
| 14828 | /* 47772 */ "VCGTfq\000" |
| 14829 | /* 47779 */ "VMAXfq\000" |
| 14830 | /* 47786 */ "VMLAslfq\000" |
| 14831 | /* 47795 */ "VMULslfq\000" |
| 14832 | /* 47804 */ "VMLSslfq\000" |
| 14833 | /* 47813 */ "VCVTs2hq\000" |
| 14834 | /* 47822 */ "VCVTxs2hq\000" |
| 14835 | /* 47832 */ "VCVTu2hq\000" |
| 14836 | /* 47841 */ "VCVTxu2hq\000" |
| 14837 | /* 47851 */ "VMLAhq\000" |
| 14838 | /* 47858 */ "VFMAhq\000" |
| 14839 | /* 47865 */ "VSUBhq\000" |
| 14840 | /* 47872 */ "VABDhq\000" |
| 14841 | /* 47879 */ "VADDhq\000" |
| 14842 | /* 47886 */ "VACGEhq\000" |
| 14843 | /* 47894 */ "VCGEhq\000" |
| 14844 | /* 47901 */ "VRECPEhq\000" |
| 14845 | /* 47910 */ "VRSQRTEhq\000" |
| 14846 | /* 47920 */ "VNEGhq\000" |
| 14847 | /* 47927 */ "VMULhq\000" |
| 14848 | /* 47934 */ "VMINhq\000" |
| 14849 | /* 47941 */ "VCEQhq\000" |
| 14850 | /* 47948 */ "VABShq\000" |
| 14851 | /* 47955 */ "VMLShq\000" |
| 14852 | /* 47962 */ "VFMShq\000" |
| 14853 | /* 47969 */ "VRECPShq\000" |
| 14854 | /* 47978 */ "VRSQRTShq\000" |
| 14855 | /* 47988 */ "VACGThq\000" |
| 14856 | /* 47996 */ "VCGThq\000" |
| 14857 | /* 48003 */ "VMAXhq\000" |
| 14858 | /* 48010 */ "VMLAslhq\000" |
| 14859 | /* 48019 */ "VMULslhq\000" |
| 14860 | /* 48028 */ "VMLSslhq\000" |
| 14861 | /* 48037 */ "VMULpq\000" |
| 14862 | /* 48044 */ "MVE_VSTRB32_rq\000" |
| 14863 | /* 48059 */ "MVE_VSTRH32_rq\000" |
| 14864 | /* 48074 */ "MVE_VLDRBS32_rq\000" |
| 14865 | /* 48090 */ "MVE_VLDRHS32_rq\000" |
| 14866 | /* 48106 */ "MVE_VLDRBU32_rq\000" |
| 14867 | /* 48122 */ "MVE_VLDRHU32_rq\000" |
| 14868 | /* 48138 */ "MVE_VLDRWU32_rq\000" |
| 14869 | /* 48154 */ "MVE_VSTRW32_rq\000" |
| 14870 | /* 48169 */ "MVE_VSTRD64_rq\000" |
| 14871 | /* 48184 */ "MVE_VLDRDU64_rq\000" |
| 14872 | /* 48200 */ "MVE_VSTRB16_rq\000" |
| 14873 | /* 48215 */ "MVE_VSTRH16_rq\000" |
| 14874 | /* 48230 */ "MVE_VLDRBS16_rq\000" |
| 14875 | /* 48246 */ "MVE_VLDRBU16_rq\000" |
| 14876 | /* 48262 */ "MVE_VLDRHU16_rq\000" |
| 14877 | /* 48278 */ "MVE_VSTRB8_rq\000" |
| 14878 | /* 48292 */ "MVE_VLDRBU8_rq\000" |
| 14879 | /* 48307 */ "VCVTf2sq\000" |
| 14880 | /* 48316 */ "VCVTh2sq\000" |
| 14881 | /* 48325 */ "VCVTf2xsq\000" |
| 14882 | /* 48335 */ "VCVTh2xsq\000" |
| 14883 | /* 48345 */ "VCVTf2uq\000" |
| 14884 | /* 48354 */ "VCVTh2uq\000" |
| 14885 | /* 48363 */ "VCVTf2xuq\000" |
| 14886 | /* 48373 */ "VCVTh2xuq\000" |
| 14887 | /* 48383 */ "MVE_VPTv4f32r\000" |
| 14888 | /* 48397 */ "MVE_VCMPf32r\000" |
| 14889 | /* 48410 */ "MVE_VPTv4i32r\000" |
| 14890 | /* 48424 */ "MVE_VCMPi32r\000" |
| 14891 | /* 48437 */ "MVE_VPTv4s32r\000" |
| 14892 | /* 48451 */ "MVE_VCMPs32r\000" |
| 14893 | /* 48464 */ "MVE_VPTv4u32r\000" |
| 14894 | /* 48478 */ "MVE_VCMPu32r\000" |
| 14895 | /* 48491 */ "MVE_VPTv8f16r\000" |
| 14896 | /* 48505 */ "MVE_VCMPf16r\000" |
| 14897 | /* 48518 */ "MVE_VPTv8i16r\000" |
| 14898 | /* 48532 */ "MVE_VCMPi16r\000" |
| 14899 | /* 48545 */ "MVE_VPTv8s16r\000" |
| 14900 | /* 48559 */ "MVE_VCMPs16r\000" |
| 14901 | /* 48572 */ "MVE_VPTv8u16r\000" |
| 14902 | /* 48586 */ "MVE_VCMPu16r\000" |
| 14903 | /* 48599 */ "MVE_VPTv16i8r\000" |
| 14904 | /* 48613 */ "MVE_VCMPi8r\000" |
| 14905 | /* 48625 */ "MVE_VPTv16s8r\000" |
| 14906 | /* 48639 */ "MVE_VCMPs8r\000" |
| 14907 | /* 48651 */ "MVE_VPTv16u8r\000" |
| 14908 | /* 48665 */ "MVE_VCMPu8r\000" |
| 14909 | /* 48677 */ "tLDRBr\000" |
| 14910 | /* 48684 */ "tSTRBr\000" |
| 14911 | /* 48691 */ "t2MOVCCr\000" |
| 14912 | /* 48700 */ "t2BFr\000" |
| 14913 | /* 48706 */ "tLDRHr\000" |
| 14914 | /* 48713 */ "tSTRHr\000" |
| 14915 | /* 48720 */ "t2BFLr\000" |
| 14916 | /* 48727 */ "MVE_LSLLr\000" |
| 14917 | /* 48737 */ "MVE_ASRLr\000" |
| 14918 | /* 48747 */ "LSLr\000" |
| 14919 | /* 48752 */ "t2MVNr\000" |
| 14920 | /* 48759 */ "tCMPr\000" |
| 14921 | /* 48765 */ "tTAILJMPr\000" |
| 14922 | /* 48775 */ "tLDRr\000" |
| 14923 | /* 48781 */ "RORr\000" |
| 14924 | /* 48786 */ "ASRr\000" |
| 14925 | /* 48791 */ "LSRr\000" |
| 14926 | /* 48796 */ "tSTRr\000" |
| 14927 | /* 48802 */ "tBLXNSr\000" |
| 14928 | /* 48810 */ "tMOVSr\000" |
| 14929 | /* 48817 */ "LDRSBTr\000" |
| 14930 | /* 48825 */ "LDRHTr\000" |
| 14931 | /* 48832 */ "STRHTr\000" |
| 14932 | /* 48839 */ "LDRSHTr\000" |
| 14933 | /* 48847 */ "tBR_JTr\000" |
| 14934 | /* 48855 */ "t2MOVr\000" |
| 14935 | /* 48862 */ "tMOVr\000" |
| 14936 | /* 48868 */ "tBLXr\000" |
| 14937 | /* 48874 */ "tBfar\000" |
| 14938 | /* 48880 */ "LDRLIT_ga_pcrel_ldr\000" |
| 14939 | /* 48900 */ "MOV_ga_pcrel_ldr\000" |
| 14940 | /* 48917 */ "VLD2q32PseudoWB_register\000" |
| 14941 | /* 48942 */ "VST2q32PseudoWB_register\000" |
| 14942 | /* 48967 */ "VLD2q16PseudoWB_register\000" |
| 14943 | /* 48992 */ "VST2q16PseudoWB_register\000" |
| 14944 | /* 49017 */ "VLD2q8PseudoWB_register\000" |
| 14945 | /* 49041 */ "VST2q8PseudoWB_register\000" |
| 14946 | /* 49065 */ "VLD1d32QPseudoWB_register\000" |
| 14947 | /* 49091 */ "VST1d32QPseudoWB_register\000" |
| 14948 | /* 49117 */ "VLD1d64QPseudoWB_register\000" |
| 14949 | /* 49143 */ "VST1d64QPseudoWB_register\000" |
| 14950 | /* 49169 */ "VLD1d16QPseudoWB_register\000" |
| 14951 | /* 49195 */ "VST1d16QPseudoWB_register\000" |
| 14952 | /* 49221 */ "VLD1d8QPseudoWB_register\000" |
| 14953 | /* 49246 */ "VST1d8QPseudoWB_register\000" |
| 14954 | /* 49271 */ "VLD1d32TPseudoWB_register\000" |
| 14955 | /* 49297 */ "VST1d32TPseudoWB_register\000" |
| 14956 | /* 49323 */ "VLD1d64TPseudoWB_register\000" |
| 14957 | /* 49349 */ "VST1d64TPseudoWB_register\000" |
| 14958 | /* 49375 */ "VLD1d16TPseudoWB_register\000" |
| 14959 | /* 49401 */ "VST1d16TPseudoWB_register\000" |
| 14960 | /* 49427 */ "VLD1d8TPseudoWB_register\000" |
| 14961 | /* 49452 */ "VST1d8TPseudoWB_register\000" |
| 14962 | /* 49477 */ "VLD2DUPq32OddPseudoWB_register\000" |
| 14963 | /* 49508 */ "VLD2DUPq16OddPseudoWB_register\000" |
| 14964 | /* 49539 */ "VLD2DUPq8OddPseudoWB_register\000" |
| 14965 | /* 49569 */ "VLD2b32wb_register\000" |
| 14966 | /* 49588 */ "VST2b32wb_register\000" |
| 14967 | /* 49607 */ "VLD1d32wb_register\000" |
| 14968 | /* 49626 */ "VST1d32wb_register\000" |
| 14969 | /* 49645 */ "VLD2d32wb_register\000" |
| 14970 | /* 49664 */ "VST2d32wb_register\000" |
| 14971 | /* 49683 */ "VLD1DUPd32wb_register\000" |
| 14972 | /* 49705 */ "VLD2DUPd32wb_register\000" |
| 14973 | /* 49727 */ "VLD1q32wb_register\000" |
| 14974 | /* 49746 */ "VST1q32wb_register\000" |
| 14975 | /* 49765 */ "VLD2q32wb_register\000" |
| 14976 | /* 49784 */ "VST2q32wb_register\000" |
| 14977 | /* 49803 */ "VLD1DUPq32wb_register\000" |
| 14978 | /* 49825 */ "VLD2DUPd32x2wb_register\000" |
| 14979 | /* 49849 */ "VLD2DUPd16x2wb_register\000" |
| 14980 | /* 49873 */ "VLD2DUPd8x2wb_register\000" |
| 14981 | /* 49896 */ "VLD1d64wb_register\000" |
| 14982 | /* 49915 */ "VST1d64wb_register\000" |
| 14983 | /* 49934 */ "VLD1q64wb_register\000" |
| 14984 | /* 49953 */ "VST1q64wb_register\000" |
| 14985 | /* 49972 */ "VLD2b16wb_register\000" |
| 14986 | /* 49991 */ "VST2b16wb_register\000" |
| 14987 | /* 50010 */ "VLD1d16wb_register\000" |
| 14988 | /* 50029 */ "VST1d16wb_register\000" |
| 14989 | /* 50048 */ "VLD2d16wb_register\000" |
| 14990 | /* 50067 */ "VST2d16wb_register\000" |
| 14991 | /* 50086 */ "VLD1DUPd16wb_register\000" |
| 14992 | /* 50108 */ "VLD2DUPd16wb_register\000" |
| 14993 | /* 50130 */ "VLD1q16wb_register\000" |
| 14994 | /* 50149 */ "VST1q16wb_register\000" |
| 14995 | /* 50168 */ "VLD2q16wb_register\000" |
| 14996 | /* 50187 */ "VST2q16wb_register\000" |
| 14997 | /* 50206 */ "VLD1DUPq16wb_register\000" |
| 14998 | /* 50228 */ "VLD2b8wb_register\000" |
| 14999 | /* 50246 */ "VST2b8wb_register\000" |
| 15000 | /* 50264 */ "VLD1d8wb_register\000" |
| 15001 | /* 50282 */ "VST1d8wb_register\000" |
| 15002 | /* 50300 */ "VLD2d8wb_register\000" |
| 15003 | /* 50318 */ "VST2d8wb_register\000" |
| 15004 | /* 50336 */ "VLD1DUPd8wb_register\000" |
| 15005 | /* 50357 */ "VLD2DUPd8wb_register\000" |
| 15006 | /* 50378 */ "VLD1q8wb_register\000" |
| 15007 | /* 50396 */ "VST1q8wb_register\000" |
| 15008 | /* 50414 */ "VLD2q8wb_register\000" |
| 15009 | /* 50432 */ "VST2q8wb_register\000" |
| 15010 | /* 50450 */ "VLD1DUPq8wb_register\000" |
| 15011 | /* 50471 */ "VLD1d32Qwb_register\000" |
| 15012 | /* 50491 */ "VST1d32Qwb_register\000" |
| 15013 | /* 50511 */ "VLD1d64Qwb_register\000" |
| 15014 | /* 50531 */ "VST1d64Qwb_register\000" |
| 15015 | /* 50551 */ "VLD1d16Qwb_register\000" |
| 15016 | /* 50571 */ "VST1d16Qwb_register\000" |
| 15017 | /* 50591 */ "VLD1d8Qwb_register\000" |
| 15018 | /* 50610 */ "VST1d8Qwb_register\000" |
| 15019 | /* 50629 */ "VLD1d32Twb_register\000" |
| 15020 | /* 50649 */ "VST1d32Twb_register\000" |
| 15021 | /* 50669 */ "VLD1d64Twb_register\000" |
| 15022 | /* 50689 */ "VST1d64Twb_register\000" |
| 15023 | /* 50709 */ "VLD1d16Twb_register\000" |
| 15024 | /* 50729 */ "VST1d16Twb_register\000" |
| 15025 | /* 50749 */ "VLD1d8Twb_register\000" |
| 15026 | /* 50768 */ "VST1d8Twb_register\000" |
| 15027 | /* 50787 */ "tCMPhir\000" |
| 15028 | /* 50795 */ "t2MOVCCror\000" |
| 15029 | /* 50806 */ "tADDspr\000" |
| 15030 | /* 50814 */ "t2RSBrr\000" |
| 15031 | /* 50822 */ "t2SUBrr\000" |
| 15032 | /* 50830 */ "tSUBrr\000" |
| 15033 | /* 50837 */ "t2SBCrr\000" |
| 15034 | /* 50845 */ "t2ADCrr\000" |
| 15035 | /* 50853 */ "t2BICrr\000" |
| 15036 | /* 50861 */ "RSCrr\000" |
| 15037 | /* 50867 */ "t2ADDrr\000" |
| 15038 | /* 50875 */ "tADDrr\000" |
| 15039 | /* 50882 */ "t2ANDrr\000" |
| 15040 | /* 50890 */ "t2LSLrr\000" |
| 15041 | /* 50898 */ "tLSLrr\000" |
| 15042 | /* 50905 */ "t2ORNrr\000" |
| 15043 | /* 50913 */ "t2CMPrr\000" |
| 15044 | /* 50921 */ "t2TEQrr\000" |
| 15045 | /* 50929 */ "t2EORrr\000" |
| 15046 | /* 50937 */ "t2RORrr\000" |
| 15047 | /* 50945 */ "t2ORRrr\000" |
| 15048 | /* 50953 */ "t2ASRrr\000" |
| 15049 | /* 50961 */ "tASRrr\000" |
| 15050 | /* 50968 */ "t2LSRrr\000" |
| 15051 | /* 50976 */ "tLSRrr\000" |
| 15052 | /* 50983 */ "t2SUBSrr\000" |
| 15053 | /* 50992 */ "tSUBSrr\000" |
| 15054 | /* 51000 */ "t2ADDSrr\000" |
| 15055 | /* 51009 */ "tADDSrr\000" |
| 15056 | /* 51017 */ "t2TSTrr\000" |
| 15057 | /* 51025 */ "MVE_VMOV_q_rr\000" |
| 15058 | /* 51039 */ "tADDhirr\000" |
| 15059 | /* 51048 */ "t2CMNzrr\000" |
| 15060 | /* 51057 */ "MOVCCsr\000" |
| 15061 | /* 51065 */ "MVNsr\000" |
| 15062 | /* 51071 */ "t2MOVSsr\000" |
| 15063 | /* 51080 */ "t2MOVsr\000" |
| 15064 | /* 51088 */ "t2MOVCCasr\000" |
| 15065 | /* 51099 */ "t2MOVCClsr\000" |
| 15066 | /* 51110 */ "RSBrsr\000" |
| 15067 | /* 51117 */ "SUBrsr\000" |
| 15068 | /* 51124 */ "SBCrsr\000" |
| 15069 | /* 51131 */ "ADCrsr\000" |
| 15070 | /* 51138 */ "BICrsr\000" |
| 15071 | /* 51145 */ "RSCrsr\000" |
| 15072 | /* 51152 */ "ADDrsr\000" |
| 15073 | /* 51159 */ "ANDrsr\000" |
| 15074 | /* 51166 */ "CMPrsr\000" |
| 15075 | /* 51173 */ "TEQrsr\000" |
| 15076 | /* 51180 */ "EORrsr\000" |
| 15077 | /* 51187 */ "ORRrsr\000" |
| 15078 | /* 51194 */ "RSBSrsr\000" |
| 15079 | /* 51202 */ "SUBSrsr\000" |
| 15080 | /* 51210 */ "ADDSrsr\000" |
| 15081 | /* 51218 */ "TSTrsr\000" |
| 15082 | /* 51225 */ "CMNzrsr\000" |
| 15083 | /* 51233 */ "t2LDRBs\000" |
| 15084 | /* 51241 */ "t2STRBs\000" |
| 15085 | /* 51249 */ "t2LDRSBs\000" |
| 15086 | /* 51258 */ "t2PLDs\000" |
| 15087 | /* 51265 */ "t2LDRHs\000" |
| 15088 | /* 51273 */ "t2STRHs\000" |
| 15089 | /* 51281 */ "t2LDRSHs\000" |
| 15090 | /* 51290 */ "t2PLIs\000" |
| 15091 | /* 51297 */ "t2MVNs\000" |
| 15092 | /* 51304 */ "t2LDRs\000" |
| 15093 | /* 51311 */ "t2STRs\000" |
| 15094 | /* 51318 */ "t2PLDWs\000" |
| 15095 | /* 51326 */ "tLDRLIT_ga_abs\000" |
| 15096 | /* 51341 */ "SEH_SaveFRegs\000" |
| 15097 | /* 51355 */ "SEH_SaveRegs\000" |
| 15098 | /* 51368 */ "LDRBrs\000" |
| 15099 | /* 51375 */ "STRBrs\000" |
| 15100 | /* 51382 */ "t2RSBrs\000" |
| 15101 | /* 51390 */ "t2SUBrs\000" |
| 15102 | /* 51398 */ "t2SBCrs\000" |
| 15103 | /* 51406 */ "t2ADCrs\000" |
| 15104 | /* 51414 */ "t2BICrs\000" |
| 15105 | /* 51422 */ "t2ADDrs\000" |
| 15106 | /* 51430 */ "PLDrs\000" |
| 15107 | /* 51436 */ "t2ANDrs\000" |
| 15108 | /* 51444 */ "PLIrs\000" |
| 15109 | /* 51450 */ "t2ORNrs\000" |
| 15110 | /* 51458 */ "t2CMPrs\000" |
| 15111 | /* 51466 */ "t2TEQrs\000" |
| 15112 | /* 51474 */ "LDRrs\000" |
| 15113 | /* 51480 */ "t2EORrs\000" |
| 15114 | /* 51488 */ "t2ORRrs\000" |
| 15115 | /* 51496 */ "STRrs\000" |
| 15116 | /* 51502 */ "t2RSBSrs\000" |
| 15117 | /* 51511 */ "t2SUBSrs\000" |
| 15118 | /* 51520 */ "t2ADDSrs\000" |
| 15119 | /* 51529 */ "t2TSTrs\000" |
| 15120 | /* 51537 */ "PLDWrs\000" |
| 15121 | /* 51544 */ "BR_JTm_rs\000" |
| 15122 | /* 51554 */ "t2CMNzrs\000" |
| 15123 | /* 51563 */ "MRSsys\000" |
| 15124 | /* 51570 */ "SEH_Nop_Ret\000" |
| 15125 | /* 51582 */ "SEH_SaveRegs_Ret\000" |
| 15126 | /* 51599 */ "tTPsoft\000" |
| 15127 | /* 51607 */ "SEH_EpilogStart\000" |
| 15128 | /* 51623 */ "t2WhileLoopStart\000" |
| 15129 | /* 51640 */ "t2DoLoopStart\000" |
| 15130 | /* 51654 */ "VLDR_P0_post\000" |
| 15131 | /* 51667 */ "VSTR_P0_post\000" |
| 15132 | /* 51680 */ "MVE_VSTRB32_post\000" |
| 15133 | /* 51697 */ "MVE_VSTRH32_post\000" |
| 15134 | /* 51714 */ "MVE_VLDRBS32_post\000" |
| 15135 | /* 51732 */ "MVE_VLDRHS32_post\000" |
| 15136 | /* 51750 */ "MVE_VLDRBU32_post\000" |
| 15137 | /* 51768 */ "MVE_VLDRHU32_post\000" |
| 15138 | /* 51786 */ "MVE_VLDRWU32_post\000" |
| 15139 | /* 51804 */ "MVE_VSTRWU32_post\000" |
| 15140 | /* 51822 */ "MVE_VSTRB16_post\000" |
| 15141 | /* 51839 */ "MVE_VLDRBS16_post\000" |
| 15142 | /* 51857 */ "MVE_VLDRBU16_post\000" |
| 15143 | /* 51875 */ "MVE_VLDRHU16_post\000" |
| 15144 | /* 51893 */ "MVE_VSTRHU16_post\000" |
| 15145 | /* 51911 */ "MVE_VLDRBU8_post\000" |
| 15146 | /* 51928 */ "MVE_VSTRBU8_post\000" |
| 15147 | /* 51945 */ "VLDR_FPSCR_NZCVQC_post\000" |
| 15148 | /* 51968 */ "VSTR_FPSCR_NZCVQC_post\000" |
| 15149 | /* 51991 */ "VLDR_FPSCR_post\000" |
| 15150 | /* 52007 */ "VSTR_FPSCR_post\000" |
| 15151 | /* 52023 */ "VLDR_VPR_post\000" |
| 15152 | /* 52037 */ "VSTR_VPR_post\000" |
| 15153 | /* 52051 */ "VLDR_FPCXTNS_post\000" |
| 15154 | /* 52069 */ "VSTR_FPCXTNS_post\000" |
| 15155 | /* 52087 */ "VLDR_FPCXTS_post\000" |
| 15156 | /* 52104 */ "VSTR_FPCXTS_post\000" |
| 15157 | /* 52121 */ "MVE_VSTRH32_rq_u\000" |
| 15158 | /* 52138 */ "MVE_VLDRHS32_rq_u\000" |
| 15159 | /* 52156 */ "MVE_VLDRHU32_rq_u\000" |
| 15160 | /* 52174 */ "MVE_VLDRWU32_rq_u\000" |
| 15161 | /* 52192 */ "MVE_VSTRW32_rq_u\000" |
| 15162 | /* 52209 */ "MVE_VSTRD64_rq_u\000" |
| 15163 | /* 52226 */ "MVE_VLDRDU64_rq_u\000" |
| 15164 | /* 52244 */ "MVE_VSTRH16_rq_u\000" |
| 15165 | /* 52261 */ "MVE_VLDRHU16_rq_u\000" |
| 15166 | /* 52279 */ "t2STRB_preidx\000" |
| 15167 | /* 52293 */ "t2STRH_preidx\000" |
| 15168 | /* 52307 */ "t2STR_preidx\000" |
| 15169 | /* 52320 */ "STRBi_preidx\000" |
| 15170 | /* 52333 */ "STRi_preidx\000" |
| 15171 | /* 52345 */ "STRBr_preidx\000" |
| 15172 | /* 52358 */ "STRr_preidx\000" |
| 15173 | /* 52370 */ "tLDR_postidx\000" |
| 15174 | /* 52383 */ "MVE_VCVTs32f32_fix\000" |
| 15175 | /* 52402 */ "MVE_VCVTu32f32_fix\000" |
| 15176 | /* 52421 */ "MVE_VCVTf32s32_fix\000" |
| 15177 | /* 52440 */ "MVE_VCVTf32u32_fix\000" |
| 15178 | /* 52459 */ "MVE_VCVTs16f16_fix\000" |
| 15179 | /* 52478 */ "MVE_VCVTu16f16_fix\000" |
| 15180 | /* 52497 */ "MVE_VCVTf16s16_fix\000" |
| 15181 | /* 52516 */ "MVE_VCVTf16u16_fix\000" |
| 15182 | /* 52535 */ "MQPRCopy\000" |
| 15183 | /* 52544 */ "MVE_VCVTs32f32z\000" |
| 15184 | /* 52560 */ "MVE_VCVTu32f32z\000" |
| 15185 | /* 52576 */ "MVE_VCVTs16f16z\000" |
| 15186 | /* 52592 */ "MVE_VCVTu16f16z\000" |
| 15187 | /* 52608 */ "tCMNz\000" |
| 15188 | }; |
| 15189 | #ifdef __GNUC__ |
| 15190 | #pragma GCC diagnostic pop |
| 15191 | #endif |
| 15192 | |
| 15193 | extern const unsigned ARMInstrNameIndices[] = { |
| 15194 | 31028U, 32004U, 33267U, 32421U, 31264U, 31245U, 31273U, 31547U, |
| 15195 | 29924U, 29939U, 29869U, 29856U, 30016U, 34401U, 29693U, 35766U, |
| 15196 | 29882U, 31024U, 31254U, 29266U, 36871U, 29393U, 35656U, 24932U, |
| 15197 | 29211U, 29254U, 32702U, 31501U, 35550U, 28846U, 32999U, 30191U, |
| 15198 | 35539U, 29416U, 32899U, 32886U, 33352U, 35137U, 35336U, 31398U, |
| 15199 | 31457U, 31430U, 31290U, 29684U, 33317U, 32622U, 36892U, 33593U, |
| 15200 | 32852U, 29741U, 36228U, 36258U, 32264U, 24644U, 24005U, 31729U, |
| 15201 | 36318U, 36332U, 31801U, 31808U, 31815U, 31825U, 24897U, 33783U, |
| 15202 | 33746U, 33981U, 36272U, 29867U, 31026U, 36685U, 29703U, 29718U, |
| 15203 | 31568U, 35088U, 34016U, 35700U, 34033U, 33669U, 24229U, 34355U, |
| 15204 | 35561U, 33886U, 35739U, 29784U, 33328U, 25028U, 24203U, 25010U, |
| 15205 | 35599U, 35580U, 32242U, 33377U, 33396U, 24500U, 24444U, 24474U, |
| 15206 | 24485U, 24425U, 24455U, 29460U, 29444U, 34445U, 30142U, 30159U, |
| 15207 | 24660U, 24011U, 24903U, 24855U, 33788U, 33752U, 36556U, 32390U, |
| 15208 | 36539U, 32373U, 24604U, 23981U, 36474U, 32308U, 32105U, 32052U, |
| 15209 | 32770U, 32748U, 24961U, 34966U, 29246U, 30336U, 24952U, 35107U, |
| 15210 | 35671U, 24144U, 34551U, 35503U, 34578U, 36242U, 24221U, 35492U, |
| 15211 | 35480U, 35646U, 30183U, 36221U, 29953U, 36251U, 31371U, 33463U, |
| 15212 | 33449U, 31333U, 33456U, 33879U, 31627U, 32831U, 32824U, 32838U, |
| 15213 | 32845U, 35098U, 32614U, 29287U, 32598U, 29232U, 32606U, 29279U, |
| 15214 | 32590U, 29224U, 32652U, 32644U, 30433U, 30425U, 34870U, 34860U, |
| 15215 | 34850U, 34840U, 34890U, 34880U, 36759U, 36769U, 34914U, 34927U, |
| 15216 | 36779U, 36789U, 34940U, 34953U, 24562U, 23960U, 31663U, 23542U, |
| 15217 | 24411U, 36290U, 31780U, 36422U, 31150U, 33047U, 8340U, 9U, |
| 15218 | 30176U, 8301U, 0U, 33022U, 33054U, 29909U, 36213U, 24193U, |
| 15219 | 31106U, 31141U, 32806U, 32815U, 34987U, 35000U, 33944U, 32279U, |
| 15220 | 34418U, 29793U, 32154U, 32164U, 29336U, 29351U, 32041U, 32094U, |
| 15221 | 32126U, 32140U, 36339U, 36365U, 36351U, 29295U, 29323U, 29308U, |
| 15222 | 24650U, 31176U, 32342U, 36508U, 32366U, 36532U, 33951U, 25001U, |
| 15223 | 24991U, 33262U, 35360U, 29371U, 33650U, 33630U, 35455U, 35434U, |
| 15224 | 33684U, 33715U, 33701U, 34475U, 36966U, 29838U, 36953U, 29820U, |
| 15225 | 32873U, 32792U, 29671U, 31377U, 34226U, 32414U, 34233U, 32235U, |
| 15226 | 34218U, 32406U, 32227U, 8324U, 30703U, 30494U, 30486U, 35709U, |
| 15227 | 33616U, 35572U, 35617U, 35749U, 33297U, 29380U, 24250U, 29762U, |
| 15228 | 29429U, 24590U, 23967U, 31691U, 36297U, 31787U, 23548U, 35717U, |
| 15229 | 33031U, 33416U, 33432U, 36862U, 29400U, 29774U, 35290U, 32660U, |
| 15230 | 32735U, 32711U, 32723U, 24569U, 31670U, 24545U, 31646U, 36457U, |
| 15231 | 32291U, 32073U, 32020U, 24628U, 31713U, 24881U, 33768U, 33730U, |
| 15232 | 36491U, 32325U, 36515U, 32349U, 36738U, 36752U, 33940U, 43837U, |
| 15233 | 51002U, 43991U, 51210U, 32573U, 32984U, 43366U, 48786U, 147U, |
| 15234 | 23574U, 9583U, 9576U, 47147U, 47156U, 33517U, 31385U, 31487U, |
| 15235 | 38266U, 269U, 51544U, 48848U, 31479U, 10173U, 672U, 8547U, |
| 15236 | 18010U, 36876U, 367U, 44713U, 47380U, 47207U, 47229U, 47123U, |
| 15237 | 42656U, 34312U, 34631U, 23637U, 30306U, 35127U, 36059U, 44194U, |
| 15238 | 43532U, 51327U, 44144U, 48880U, 43523U, 43540U, 36081U, 44025U, |
| 15239 | 35411U, 31222U, 43334U, 48747U, 43371U, 48791U, 155U, 36864U, |
| 15240 | 9661U, 43280U, 15103U, 44320U, 48693U, 43860U, 51057U, 36803U, |
| 15241 | 44107U, 44179U, 48900U, 44126U, 44334U, 52535U, 38244U, 40588U, |
| 15242 | 38254U, 40599U, 9699U, 35824U, 35805U, 43271U, 24530U, 33310U, |
| 15243 | 23819U, 30574U, 23852U, 30719U, 33897U, 23827U, 30612U, 43361U, |
| 15244 | 48781U, 36813U, 43430U, 43819U, 43975U, 51194U, 40457U, 51607U, |
| 15245 | 47268U, 51570U, 40471U, 51341U, 33549U, 51355U, 51582U, 32911U, |
| 15246 | 38052U, 9667U, 9683U, 29240U, 31231U, 36070U, 52320U, 52345U, |
| 15247 | 52295U, 36091U, 52333U, 52358U, 33538U, 43828U, 50985U, 43983U, |
| 15248 | 51202U, 23653U, 23685U, 38199U, 48766U, 9651U, 43512U, 43736U, |
| 15249 | 326U, 51600U, 9675U, 9691U, 11529U, 2050U, 19024U, 10315U, |
| 15250 | 836U, 18144U, 10913U, 1434U, 18584U, 11557U, 2078U, 19050U, |
| 15251 | 10361U, 882U, 18188U, 10965U, 1486U, 18634U, 11719U, 2240U, |
| 15252 | 10631U, 1152U, 11271U, 1792U, 11641U, 2162U, 19128U, 10499U, |
| 15253 | 1020U, 18320U, 11121U, 1642U, 18784U, 11803U, 2324U, 19200U, |
| 15254 | 10769U, 1290U, 18446U, 11427U, 1948U, 18928U, 11585U, 2106U, |
| 15255 | 19076U, 10407U, 928U, 18232U, 11017U, 1538U, 18684U, 11747U, |
| 15256 | 2268U, 10677U, 1198U, 11323U, 1844U, 11481U, 2002U, 18980U, |
| 15257 | 10231U, 752U, 18064U, 10817U, 1338U, 18492U, 11671U, 2192U, |
| 15258 | 19156U, 10547U, 1068U, 18366U, 11175U, 1696U, 18836U, 11656U, |
| 15259 | 2177U, 19142U, 10523U, 1044U, 18343U, 11148U, 1669U, 18810U, |
| 15260 | 11818U, 2339U, 19214U, 10793U, 1314U, 18469U, 11454U, 1975U, |
| 15261 | 18954U, 11613U, 2134U, 19102U, 10453U, 974U, 18276U, 11069U, |
| 15262 | 1590U, 18734U, 11775U, 2296U, 10723U, 1244U, 11375U, 1896U, |
| 15263 | 11505U, 2026U, 19002U, 10273U, 794U, 18104U, 10865U, 1386U, |
| 15264 | 18538U, 11695U, 2216U, 19178U, 10589U, 1110U, 18406U, 11223U, |
| 15265 | 1744U, 18882U, 18U, 37612U, 37620U, 41U, 37628U, 11543U, |
| 15266 | 2064U, 19037U, 10338U, 859U, 18166U, 10939U, 1460U, 18609U, |
| 15267 | 11571U, 2092U, 19063U, 10384U, 905U, 18210U, 10991U, 1512U, |
| 15268 | 18659U, 11733U, 2254U, 10654U, 1175U, 11297U, 1818U, 11599U, |
| 15269 | 2120U, 19089U, 10430U, 951U, 18254U, 11043U, 1564U, 18709U, |
| 15270 | 11761U, 2282U, 10700U, 1221U, 11349U, 1870U, 11493U, 2014U, |
| 15271 | 18991U, 10252U, 773U, 18084U, 10841U, 1362U, 18515U, 11683U, |
| 15272 | 2204U, 19167U, 10568U, 1089U, 18386U, 11199U, 1720U, 18859U, |
| 15273 | 11627U, 2148U, 19115U, 10476U, 997U, 18298U, 11095U, 1616U, |
| 15274 | 18759U, 11789U, 2310U, 10746U, 1267U, 11401U, 1922U, 11517U, |
| 15275 | 2038U, 19013U, 10294U, 815U, 18124U, 10889U, 1410U, 18561U, |
| 15276 | 11707U, 2228U, 19189U, 10610U, 1131U, 18426U, 11247U, 1768U, |
| 15277 | 18905U, 31186U, 31164U, 33938U, 43835U, 51000U, 51520U, 46722U, |
| 15278 | 35401U, 31130U, 51640U, 32967U, 35125U, 44475U, 44585U, 44355U, |
| 15279 | 44044U, 44192U, 44530U, 44634U, 44401U, 44069U, 44142U, 44511U, |
| 15280 | 44617U, 44385U, 44056U, 44566U, 44666U, 44431U, 44081U, 44683U, |
| 15281 | 44447U, 38027U, 44094U, 44023U, 35409U, 37929U, 40485U, 37916U, |
| 15282 | 51088U, 43278U, 15101U, 44318U, 44221U, 51099U, 48691U, 50795U, |
| 15283 | 43874U, 51071U, 44105U, 44177U, 44124U, 44332U, 43883U, 51080U, |
| 15284 | 43269U, 43817U, 51502U, 44493U, 44601U, 44370U, 52279U, 44548U, |
| 15285 | 44650U, 44416U, 52293U, 44698U, 44461U, 52307U, 43826U, 50983U, |
| 15286 | 51511U, 23651U, 23683U, 35367U, 35384U, 47363U, 51623U, 33560U, |
| 15287 | 32948U, 33975U, 8528U, 21348U, 51009U, 40578U, 32572U, 32983U, |
| 15288 | 31418U, 47170U, 33516U, 24945U, 48847U, 35160U, 31478U, 35170U, |
| 15289 | 41700U, 48874U, 10172U, 671U, 18009U, 26179U, 44207U, 51326U, |
| 15290 | 44160U, 52370U, 38040U, 44034U, 35422U, 43844U, 46925U, 44344U, |
| 15291 | 35151U, 33957U, 33969U, 8520U, 21340U, 50992U, 38198U, 25054U, |
| 15292 | 48765U, 35376U, 35393U, 51599U, 43669U, 50847U, 43912U, 51131U, |
| 15293 | 43691U, 50869U, 43933U, 51152U, 33288U, 28921U, 29666U, 24166U, |
| 15294 | 24179U, 43699U, 50884U, 43940U, 51159U, 29037U, 33191U, 29053U, |
| 15295 | 33207U, 36185U, 23915U, 36154U, 24126U, 31020U, 43677U, 50855U, |
| 15296 | 43919U, 51138U, 35641U, 31242U, 36799U, 38315U, 43425U, 38299U, |
| 15297 | 36618U, 31160U, 35171U, 38307U, 37603U, 137U, 23258U, 24357U, |
| 15298 | 23313U, 8432U, 23281U, 24366U, 23323U, 8498U, 23290U, 24375U, |
| 15299 | 23333U, 47076U, 47318U, 37978U, 47034U, 47276U, 37939U, 47091U, |
| 15300 | 47333U, 37992U, 47048U, 47290U, 37952U, 47106U, 47348U, 38006U, |
| 15301 | 47062U, 47304U, 37965U, 32802U, 8335U, 36717U, 36949U, 43722U, |
| 15302 | 51050U, 44006U, 51225U, 43749U, 50915U, 43947U, 51166U, 46942U, |
| 15303 | 46982U, 46990U, 23569U, 23713U, 30328U, 36414U, 30228U, 36387U, |
| 15304 | 29898U, 23810U, 23842U, 43765U, 50931U, 43961U, 51180U, 35120U, |
| 15305 | 29076U, 30787U, 34647U, 26406U, 23484U, 26262U, 35013U, 26418U, |
| 15306 | 23492U, 26274U, 35528U, 35476U, 24326U, 23848U, 23351U, 23582U, |
| 15307 | 36679U, 24047U, 29130U, 30867U, 30245U, 35234U, 32493U, 35989U, |
| 15308 | 29602U, 35180U, 32439U, 35845U, 29470U, 35264U, 32523U, 36015U, |
| 15309 | 29626U, 35208U, 32467U, 35906U, 29526U, 23358U, 26087U, 23731U, |
| 15310 | 26322U, 23405U, 26156U, 23780U, 26443U, 31939U, 30084U, 31885U, |
| 15311 | 30030U, 31835U, 29966U, 163U, 51368U, 28864U, 35928U, 29546U, |
| 15312 | 36709U, 24065U, 29148U, 30885U, 30577U, 43395U, 48825U, 35952U, |
| 15313 | 29568U, 23855U, 43387U, 48817U, 35893U, 29514U, 30722U, 43409U, |
| 15314 | 48839U, 35976U, 29590U, 31969U, 30114U, 31913U, 30058U, 31861U, |
| 15315 | 29992U, 47028U, 243U, 51474U, 33282U, 8350U, 33823U, 8368U, |
| 15316 | 23502U, 34092U, 33508U, 15222U, 43419U, 15232U, 48857U, 24316U, |
| 15317 | 43885U, 51082U, 24305U, 8288U, 24311U, 8295U, 34351U, 38289U, |
| 15318 | 51563U, 33868U, 38277U, 43376U, 31642U, 43324U, 48737U, 10185U, |
| 15319 | 684U, 8559U, 18021U, 32930U, 32939U, 43314U, 48727U, 31618U, |
| 15320 | 33470U, 31584U, 31340U, 31513U, 33481U, 31596U, 31360U, 31535U, |
| 15321 | 31350U, 31524U, 33491U, 31607U, 16018U, 6555U, 22009U, 17178U, |
| 15322 | 7816U, 22906U, 12323U, 2838U, 15740U, 6251U, 21752U, 16988U, |
| 15323 | 7618U, 22731U, 12437U, 2952U, 15980U, 6517U, 21974U, 24110U, |
| 15324 | 30958U, 37652U, 37783U, 37685U, 37822U, 37702U, 37842U, 37636U, |
| 15325 | 37764U, 37734U, 37880U, 37718U, 37861U, 37669U, 37803U, 37749U, |
| 15326 | 37898U, 12572U, 3087U, 15271U, 5820U, 21402U, 12348U, 2863U, |
| 15327 | 15134U, 5692U, 21169U, 24872U, 24130U, 15320U, 5869U, 9891U, |
| 15328 | 411U, 17791U, 12335U, 2850U, 15112U, 5670U, 21149U, 15992U, |
| 15329 | 6529U, 21985U, 16238U, 6775U, 22184U, 12256U, 2771U, 12425U, |
| 15330 | 48505U, 2940U, 48397U, 15208U, 48532U, 5776U, 48424U, 21306U, |
| 15331 | 48613U, 15955U, 48559U, 6492U, 48451U, 21951U, 48639U, 17098U, |
| 15332 | 48586U, 7736U, 48478U, 22832U, 48665U, 12372U, 2887U, 9869U, |
| 15333 | 389U, 8536U, 17771U, 42084U, 42683U, 52497U, 44815U, 52516U, |
| 15334 | 44831U, 42269U, 42868U, 52421U, 44751U, 52440U, 44767U, 52459U, |
| 15335 | 37005U, 44264U, 44783U, 46996U, 52576U, 52383U, 36973U, 44232U, |
| 15336 | 44719U, 46948U, 52544U, 52478U, 37021U, 44280U, 44799U, 47012U, |
| 15337 | 52592U, 52402U, 36989U, 44248U, 44735U, 46964U, 52560U, 17110U, |
| 15338 | 7748U, 22843U, 9880U, 400U, 17781U, 17136U, 7774U, 22867U, |
| 15339 | 33579U, 12461U, 2976U, 12540U, 3055U, 12269U, 2784U, 12449U, |
| 15340 | 2964U, 16307U, 6821U, 22249U, 17326U, 7941U, 23029U, 15780U, |
| 15341 | 6291U, 21789U, 17014U, 7644U, 22755U, 15752U, 6263U, 21763U, |
| 15342 | 16273U, 6787U, 22217U, 17292U, 7907U, 22997U, 15714U, 6225U, |
| 15343 | 21728U, 16962U, 7592U, 22707U, 17123U, 7761U, 22855U, 17150U, |
| 15344 | 7788U, 22880U, 9988U, 37229U, 501U, 37037U, 17826U, 37421U, |
| 15345 | 10040U, 37293U, 553U, 37101U, 17874U, 37481U, 10014U, 37261U, |
| 15346 | 527U, 37069U, 17850U, 37451U, 10066U, 37325U, 579U, 37133U, |
| 15347 | 17898U, 37511U, 10106U, 37357U, 605U, 37165U, 17935U, 37541U, |
| 15348 | 10132U, 37389U, 631U, 37197U, 17959U, 37571U, 9903U, 51839U, |
| 15349 | 40786U, 48230U, 423U, 51714U, 40668U, 48074U, 9934U, 51857U, |
| 15350 | 40803U, 48246U, 449U, 51750U, 40702U, 48106U, 17802U, 51911U, |
| 15351 | 40854U, 48292U, 43627U, 41110U, 48184U, 52226U, 436U, 51732U, |
| 15352 | 40685U, 48090U, 52138U, 9947U, 51875U, 40820U, 48262U, 52261U, |
| 15353 | 462U, 51768U, 40719U, 48122U, 52156U, 475U, 51786U, 40736U, |
| 15354 | 43581U, 41052U, 48138U, 52174U, 16107U, 6644U, 22062U, 15687U, |
| 15355 | 6198U, 21703U, 12494U, 3009U, 12296U, 2811U, 12525U, 3040U, |
| 15356 | 12411U, 2926U, 16134U, 6671U, 22087U, 17235U, 7873U, 22944U, |
| 15357 | 16156U, 6693U, 22107U, 17257U, 7895U, 22964U, 16093U, 6630U, |
| 15358 | 22049U, 15674U, 6185U, 21691U, 12478U, 2993U, 12281U, 2796U, |
| 15359 | 12510U, 3025U, 12397U, 2912U, 16121U, 6658U, 22075U, 17222U, |
| 15360 | 7860U, 22932U, 15933U, 6480U, 21931U, 17076U, 7724U, 22812U, |
| 15361 | 16380U, 6932U, 22318U, 17360U, 7994U, 23061U, 16865U, 7495U, |
| 15362 | 22649U, 16031U, 6568U, 22021U, 17191U, 7829U, 22918U, 16799U, |
| 15363 | 7389U, 22619U, 16396U, 6948U, 17376U, 8010U, 16882U, 7512U, |
| 15364 | 16046U, 6583U, 17206U, 7844U, 16815U, 7405U, 15303U, 5852U, |
| 15365 | 21432U, 15239U, 5788U, 21372U, 16430U, 6982U, 22333U, 16918U, |
| 15366 | 7548U, 22665U, 16078U, 6615U, 22035U, 16849U, 7439U, 22634U, |
| 15367 | 16413U, 6965U, 16900U, 7530U, 16062U, 6599U, 16832U, 7422U, |
| 15368 | 42349U, 42948U, 42558U, 43157U, 42490U, 43089U, 42607U, 43206U, |
| 15369 | 42317U, 42916U, 42132U, 42731U, 710U, 16250U, 22195U, 17269U, |
| 15370 | 22975U, 51025U, 47582U, 10211U, 732U, 18045U, 3119U, 15365U, |
| 15371 | 5914U, 9591U, 21448U, 15911U, 6422U, 21911U, 17054U, 7684U, |
| 15372 | 22792U, 15424U, 21503U, 15700U, 6211U, 21715U, 16948U, 7578U, |
| 15373 | 22694U, 15438U, 21524U, 16004U, 6541U, 21996U, 17164U, 7802U, |
| 15374 | 22893U, 12588U, 3103U, 15287U, 5836U, 21417U, 12385U, 2900U, |
| 15375 | 15186U, 5744U, 21286U, 32558U, 15335U, 5884U, 12360U, 2875U, |
| 15376 | 15819U, 6330U, 21825U, 32549U, 33836U, 15350U, 5899U, 35630U, |
| 15377 | 31323U, 36101U, 19587U, 48599U, 21678U, 48625U, 22681U, 48651U, |
| 15378 | 2693U, 48383U, 4631U, 48410U, 6172U, 48437U, 7565U, 48464U, |
| 15379 | 12188U, 48491U, 14062U, 48518U, 15661U, 48545U, 16935U, 48572U, |
| 15380 | 15967U, 6504U, 21962U, 16324U, 6838U, 22265U, 17343U, 7958U, |
| 15381 | 23045U, 15793U, 6304U, 21801U, 17027U, 7657U, 22767U, 16168U, |
| 15382 | 6705U, 22118U, 15831U, 6342U, 21836U, 16659U, 7211U, 22487U, |
| 15383 | 16696U, 7248U, 22522U, 16203U, 6740U, 22151U, 15864U, 6375U, |
| 15384 | 21867U, 16341U, 6855U, 22281U, 15146U, 5704U, 21213U, 42432U, |
| 15385 | 43031U, 42232U, 42831U, 42332U, 42931U, 42147U, 42746U, 42416U, |
| 15386 | 43015U, 42216U, 42815U, 42505U, 43104U, 42253U, 42852U, 42399U, |
| 15387 | 42998U, 42199U, 42798U, 15806U, 6317U, 21813U, 16185U, 6722U, |
| 15388 | 22134U, 15847U, 6358U, 21851U, 16677U, 7229U, 22504U, 16715U, |
| 15389 | 7267U, 22540U, 16220U, 6757U, 22167U, 15880U, 6391U, 21882U, |
| 15390 | 16360U, 6874U, 22299U, 15161U, 5719U, 21227U, 16466U, 7018U, |
| 15391 | 22367U, 17413U, 8047U, 23095U, 16751U, 7303U, 22574U, 17604U, |
| 15392 | 8238U, 23213U, 16542U, 7094U, 17489U, 8123U, 16575U, 7127U, |
| 15393 | 17522U, 8156U, 42381U, 42980U, 42181U, 42780U, 16641U, 7193U, |
| 15394 | 22470U, 16446U, 6998U, 22348U, 17393U, 8027U, 23076U, 16735U, |
| 15395 | 7287U, 22559U, 17588U, 8222U, 23198U, 16592U, 7144U, 22424U, |
| 15396 | 17539U, 8173U, 23152U, 16526U, 7078U, 17473U, 8107U, 16559U, |
| 15397 | 7111U, 17506U, 8140U, 42364U, 42963U, 42164U, 42763U, 16290U, |
| 15398 | 6804U, 22233U, 17309U, 7924U, 23013U, 15727U, 6238U, 21740U, |
| 15399 | 16975U, 7605U, 22719U, 17996U, 10092U, 17922U, 10158U, 657U, |
| 15400 | 17983U, 15766U, 6277U, 21776U, 17000U, 7630U, 22742U, 23299U, |
| 15401 | 31760U, 32204U, 32688U, 36443U, 36928U, 23267U, 31746U, 32190U, |
| 15402 | 32674U, 36429U, 36914U, 6894U, 7975U, 7455U, 6435U, 7697U, |
| 15403 | 7351U, 6913U, 7475U, 6453U, 7370U, 15897U, 6408U, 21898U, |
| 15404 | 17040U, 7670U, 22779U, 16487U, 7039U, 22387U, 17434U, 8068U, |
| 15405 | 23115U, 16768U, 7320U, 22590U, 17621U, 8255U, 23229U, 42286U, |
| 15406 | 42885U, 42101U, 42700U, 16608U, 7160U, 22439U, 17555U, 8189U, |
| 15407 | 23167U, 24096U, 30948U, 24156U, 42453U, 43052U, 42572U, 43171U, |
| 15408 | 42521U, 43120U, 42621U, 43220U, 42472U, 43071U, 42590U, 43189U, |
| 15409 | 42540U, 43139U, 42639U, 43238U, 16507U, 7059U, 22406U, 17454U, |
| 15410 | 8088U, 23134U, 15380U, 5929U, 21462U, 16784U, 7336U, 22605U, |
| 15411 | 17637U, 8271U, 23244U, 42302U, 42901U, 42117U, 42716U, 16625U, |
| 15412 | 7177U, 22455U, 17572U, 8206U, 23183U, 15396U, 5945U, 21477U, |
| 15413 | 15410U, 5959U, 21490U, 10001U, 37245U, 514U, 37053U, 17838U, |
| 15414 | 37436U, 10053U, 37309U, 566U, 37117U, 17886U, 37496U, 10027U, |
| 15415 | 37277U, 540U, 37085U, 17862U, 37466U, 10079U, 37341U, 592U, |
| 15416 | 37149U, 17910U, 37526U, 10119U, 37373U, 618U, 37181U, 17947U, |
| 15417 | 37556U, 10145U, 37405U, 644U, 37213U, 17971U, 37586U, 9725U, |
| 15418 | 51822U, 40770U, 48200U, 343U, 51680U, 40636U, 48044U, 48278U, |
| 15419 | 17814U, 51928U, 40870U, 43612U, 41091U, 48169U, 52209U, 48215U, |
| 15420 | 52244U, 355U, 51697U, 40652U, 48059U, 52121U, 9960U, 51893U, |
| 15421 | 40837U, 43597U, 41072U, 48154U, 52192U, 488U, 51804U, 40753U, |
| 15422 | 12556U, 3071U, 15255U, 5804U, 21387U, 12311U, 2826U, 15089U, |
| 15423 | 5658U, 21131U, 10198U, 697U, 8572U, 18033U, 43341U, 48754U, |
| 15424 | 43868U, 51065U, 41181U, 41755U, 41358U, 41932U, 41166U, 41740U, |
| 15425 | 41343U, 41917U, 43781U, 50947U, 43968U, 51187U, 35038U, 23890U, |
| 15426 | 261U, 51537U, 194U, 51430U, 234U, 51444U, 24623U, 9834U, |
| 15427 | 17740U, 36835U, 24539U, 23954U, 36590U, 24000U, 9777U, 17681U, |
| 15428 | 35331U, 36281U, 9975U, 30751U, 23343U, 26074U, 23723U, 26310U, |
| 15429 | 23397U, 26144U, 23771U, 26430U, 43645U, 50816U, 43891U, 51110U, |
| 15430 | 43683U, 50861U, 43926U, 51145U, 9853U, 17757U, 36850U, 23837U, |
| 15431 | 43661U, 50839U, 43905U, 51124U, 36733U, 36313U, 31312U, 24925U, |
| 15432 | 32220U, 24084U, 30220U, 31740U, 32668U, 59U, 113U, 30235U, |
| 15433 | 8309U, 67U, 121U, 9814U, 17722U, 36819U, 36574U, 9757U, |
| 15434 | 17663U, 24175U, 23605U, 35029U, 24393U, 36623U, 31208U, 23614U, |
| 15435 | 35046U, 24757U, 36641U, 23898U, 36131U, 23881U, 36122U, 24029U, |
| 15436 | 36197U, 28935U, 36661U, 24773U, 36651U, 23508U, 33225U, 34098U, |
| 15437 | 33860U, 31707U, 33529U, 24517U, 36632U, 23624U, 35056U, 31554U, |
| 15438 | 23908U, 36141U, 24038U, 36206U, 28993U, 36670U, 23373U, 26110U, |
| 15439 | 23765U, 26396U, 23478U, 26252U, 23795U, 26466U, 34902U, 9918U, |
| 15440 | 36605U, 9796U, 17698U, 35249U, 32508U, 36002U, 29614U, 35194U, |
| 15441 | 32453U, 35857U, 29481U, 35278U, 32537U, 36027U, 29637U, 35221U, |
| 15442 | 32480U, 35917U, 29536U, 31636U, 23803U, 36701U, 24056U, 29139U, |
| 15443 | 30876U, 30413U, 23367U, 26100U, 23748U, 26347U, 23429U, 26192U, |
| 15444 | 23789U, 26456U, 31954U, 30099U, 31899U, 30044U, 31848U, 29979U, |
| 15445 | 173U, 51375U, 28902U, 35940U, 29557U, 36725U, 24074U, 29157U, |
| 15446 | 30894U, 30615U, 43402U, 48832U, 35964U, 29579U, 31983U, 30128U, |
| 15447 | 31926U, 30071U, 31873U, 30004U, 252U, 51496U, 43653U, 50824U, |
| 15448 | 43898U, 51117U, 24331U, 33018U, 23814U, 23589U, 9707U, 30286U, |
| 15449 | 23928U, 9739U, 30797U, 43757U, 50923U, 43954U, 51173U, 32718U, |
| 15450 | 44014U, 23875U, 43854U, 51019U, 43999U, 51218U, 9862U, 17765U, |
| 15451 | 36857U, 36747U, 29811U, 36327U, 9824U, 17731U, 36827U, 36582U, |
| 15452 | 9767U, 17672U, 31200U, 31216U, 31562U, 9843U, 17748U, 36842U, |
| 15453 | 36597U, 9786U, 17689U, 17714U, 17654U, 34909U, 9927U, 36612U, |
| 15454 | 9805U, 17706U, 23597U, 9717U, 30294U, 23941U, 9748U, 30810U, |
| 15455 | 9110U, 4949U, 14380U, 9360U, 5328U, 14759U, 19667U, 3665U, |
| 15456 | 13135U, 4832U, 14263U, 20502U, 19914U, 3994U, 13464U, 5211U, |
| 15457 | 14642U, 20765U, 9146U, 4998U, 14429U, 9396U, 5377U, 14808U, |
| 15458 | 40068U, 47655U, 40292U, 47872U, 19725U, 3723U, 13193U, 4890U, |
| 15459 | 14321U, 20555U, 19972U, 4052U, 13522U, 5269U, 14700U, 20818U, |
| 15460 | 28915U, 30641U, 34439U, 40144U, 47724U, 40368U, 47948U, 19557U, |
| 15461 | 3402U, 12872U, 4601U, 14032U, 20414U, 40082U, 47669U, 40306U, |
| 15462 | 47886U, 40184U, 47764U, 40408U, 47988U, 24676U, 30355U, 3298U, |
| 15463 | 12768U, 20328U, 9158U, 5023U, 14454U, 9408U, 5402U, 14833U, |
| 15464 | 33988U, 9301U, 5188U, 14619U, 9551U, 5567U, 14998U, 40075U, |
| 15465 | 47662U, 40299U, 47879U, 19485U, 8611U, 3154U, 8947U, 12624U, |
| 15466 | 4425U, 13895U, 20247U, 38151U, 47499U, 33133U, 31032U, 33158U, |
| 15467 | 31060U, 38145U, 3462U, 12932U, 4674U, 14105U, 47493U, 38174U, |
| 15468 | 47522U, 38232U, 47570U, 38180U, 47528U, 38208U, 47546U, 2595U, |
| 15469 | 12100U, 2682U, 12177U, 40137U, 47717U, 40361U, 47941U, 19536U, |
| 15470 | 3381U, 12851U, 4580U, 14011U, 20395U, 20196U, 2638U, 4372U, |
| 15471 | 12133U, 2738U, 13842U, 5625U, 12223U, 15056U, 21073U, 40090U, |
| 15472 | 47677U, 40314U, 47894U, 19773U, 3771U, 13241U, 4938U, 14369U, |
| 15473 | 20599U, 20020U, 4100U, 13570U, 5317U, 14748U, 20862U, 20174U, |
| 15474 | 2616U, 4350U, 12111U, 2716U, 13820U, 5603U, 12201U, 15034U, |
| 15475 | 21053U, 40192U, 47772U, 40416U, 47996U, 19892U, 3930U, 13400U, |
| 15476 | 5165U, 14596U, 20745U, 20139U, 4259U, 13729U, 5544U, 14975U, |
| 15477 | 21008U, 20207U, 2649U, 4383U, 12144U, 2749U, 13853U, 5636U, |
| 15478 | 12234U, 15067U, 21083U, 20185U, 2627U, 4361U, 12122U, 2727U, |
| 15479 | 13831U, 5614U, 12212U, 15045U, 21063U, 19567U, 3412U, 12882U, |
| 15480 | 4611U, 14042U, 20423U, 20218U, 2660U, 4394U, 12155U, 2760U, |
| 15481 | 13864U, 5647U, 12245U, 15078U, 21093U, 19620U, 3452U, 12922U, |
| 15482 | 4664U, 14095U, 20459U, 2584U, 38324U, 12089U, 38362U, 2671U, |
| 15483 | 38343U, 12166U, 38381U, 25108U, 24690U, 30377U, 34009U, 29172U, |
| 15484 | 30909U, 34731U, 30552U, 34290U, 29196U, 30933U, 34755U, 38238U, |
| 15485 | 47576U, 41246U, 41820U, 41423U, 41997U, 41286U, 41860U, 41463U, |
| 15486 | 42037U, 28907U, 30633U, 34431U, 29084U, 30821U, 34679U, 30347U, |
| 15487 | 24703U, 34054U, 30647U, 33994U, 41256U, 41830U, 41433U, 42007U, |
| 15488 | 41296U, 41870U, 41473U, 42047U, 28960U, 30681U, 34519U, 29092U, |
| 15489 | 30829U, 34687U, 41266U, 41840U, 41443U, 42017U, 41306U, 41880U, |
| 15490 | 41483U, 42057U, 28968U, 30695U, 34527U, 29100U, 30837U, 34695U, |
| 15491 | 41276U, 41850U, 41453U, 42027U, 41316U, 41890U, 41493U, 42067U, |
| 15492 | 28976U, 30711U, 34535U, 29108U, 30845U, 34703U, 28984U, 30361U, |
| 15493 | 24718U, 34069U, 30735U, 41715U, 40502U, 48307U, 40540U, 48345U, |
| 15494 | 40520U, 48325U, 40558U, 48363U, 41141U, 40511U, 48316U, 40549U, |
| 15495 | 48354U, 40530U, 48335U, 40568U, 48373U, 40009U, 47596U, 40233U, |
| 15496 | 47813U, 40028U, 47615U, 40252U, 47832U, 40018U, 47605U, 40242U, |
| 15497 | 47822U, 40037U, 47624U, 40261U, 47841U, 29116U, 30853U, 34711U, |
| 15498 | 38104U, 47452U, 38077U, 47416U, 38130U, 47478U, 38094U, 47442U, |
| 15499 | 38067U, 47406U, 38121U, 47469U, 38220U, 47558U, 12081U, 2576U, |
| 15500 | 19458U, 15653U, 6164U, 9631U, 21671U, 24405U, 30263U, 24764U, |
| 15501 | 30968U, 33144U, 31044U, 33917U, 40054U, 47641U, 40278U, 47858U, |
| 15502 | 28947U, 30668U, 24780U, 30976U, 33151U, 31052U, 34506U, 40158U, |
| 15503 | 47738U, 40382U, 47962U, 24418U, 30269U, 33923U, 28953U, 30674U, |
| 15504 | 34512U, 24826U, 30466U, 34149U, 24814U, 30454U, 34137U, 5756U, |
| 15505 | 15945U, 21942U, 17088U, 22823U, 19749U, 3747U, 13217U, 4914U, |
| 15506 | 14345U, 20577U, 19996U, 4076U, 13546U, 5293U, 14724U, 20840U, |
| 15507 | 19701U, 3699U, 13169U, 4866U, 14297U, 20533U, 19948U, 4028U, |
| 15508 | 13498U, 5245U, 14676U, 20796U, 30689U, 36179U, 12029U, 39416U, |
| 15509 | 50086U, 2532U, 39073U, 49683U, 19411U, 39627U, 50336U, 15612U, |
| 15510 | 39518U, 50206U, 6123U, 39175U, 49803U, 21634U, 39723U, 50450U, |
| 15511 | 11933U, 25522U, 2444U, 25170U, 19325U, 25870U, 45451U, 27248U, |
| 15512 | 45061U, 26782U, 45779U, 27698U, 11849U, 33099U, 45869U, 38622U, |
| 15513 | 49169U, 39809U, 50551U, 34806U, 46137U, 38804U, 49375U, 39943U, |
| 15514 | 50709U, 39352U, 50010U, 2370U, 33063U, 45809U, 38530U, 49065U, |
| 15515 | 39741U, 50471U, 34770U, 46077U, 38712U, 49271U, 39875U, 50629U, |
| 15516 | 39009U, 49607U, 8585U, 33081U, 45839U, 38576U, 49117U, 39775U, |
| 15517 | 50511U, 34788U, 46107U, 38758U, 49323U, 39909U, 50669U, 39256U, |
| 15518 | 49896U, 19242U, 33117U, 45899U, 38668U, 49221U, 39843U, 50591U, |
| 15519 | 34824U, 46167U, 38850U, 49427U, 39977U, 50749U, 39567U, 50264U, |
| 15520 | 15452U, 46003U, 27828U, 46271U, 28184U, 28006U, 28362U, 39454U, |
| 15521 | 50130U, 5973U, 45927U, 27736U, 46195U, 28092U, 27918U, 28274U, |
| 15522 | 39111U, 49727U, 9615U, 45965U, 27782U, 46233U, 28138U, 27962U, |
| 15523 | 28318U, 39288U, 49934U, 21537U, 46041U, 27874U, 46309U, 28230U, |
| 15524 | 28050U, 28406U, 39663U, 50378U, 12040U, 39435U, 50108U, 8453U, |
| 15525 | 39215U, 49849U, 2543U, 39092U, 49705U, 8440U, 39194U, 49825U, |
| 15526 | 19421U, 39645U, 50357U, 8466U, 39236U, 49873U, 46802U, 46405U, |
| 15527 | 38922U, 49508U, 46739U, 46345U, 38894U, 49477U, 46865U, 46465U, |
| 15528 | 38950U, 49539U, 11953U, 45293U, 27014U, 25550U, 2464U, 44903U, |
| 15529 | 26548U, 25198U, 19343U, 45631U, 27476U, 25896U, 15536U, 45483U, |
| 15530 | 27288U, 25712U, 6047U, 45093U, 26822U, 25360U, 11833U, 39320U, |
| 15531 | 49972U, 2354U, 38977U, 49569U, 19228U, 39537U, 50228U, 11875U, |
| 15532 | 39384U, 50048U, 2386U, 39041U, 49645U, 19265U, 39597U, 50300U, |
| 15533 | 15478U, 45423U, 38444U, 48967U, 39486U, 50168U, 5989U, 45033U, |
| 15534 | 38400U, 48917U, 39143U, 49765U, 21560U, 45753U, 38488U, 49017U, |
| 15535 | 39693U, 50414U, 12051U, 45389U, 27134U, 25634U, 2554U, 44999U, |
| 15536 | 26668U, 25282U, 19431U, 45721U, 27590U, 25974U, 15623U, 46823U, |
| 15537 | 46425U, 28496U, 25796U, 6134U, 46760U, 46365U, 28448U, 25444U, |
| 15538 | 21644U, 46885U, 46484U, 28544U, 26046U, 11973U, 45325U, 27054U, |
| 15539 | 25578U, 2484U, 44935U, 26588U, 25226U, 19361U, 45661U, 27514U, |
| 15540 | 25922U, 15556U, 45515U, 27328U, 25740U, 6067U, 45125U, 26862U, |
| 15541 | 25388U, 11891U, 45237U, 26942U, 25474U, 2402U, 44847U, 26476U, |
| 15542 | 25122U, 19279U, 45579U, 27408U, 25826U, 15494U, 27176U, 25664U, |
| 15543 | 46590U, 28674U, 6005U, 26710U, 25312U, 46522U, 28590U, 21574U, |
| 15544 | 27630U, 26002U, 46658U, 28758U, 12062U, 45406U, 27155U, 25649U, |
| 15545 | 2565U, 45016U, 26689U, 25297U, 19441U, 45737U, 27610U, 25988U, |
| 15546 | 15634U, 46844U, 46445U, 28520U, 25811U, 6145U, 46781U, 46385U, |
| 15547 | 28472U, 25459U, 21654U, 46905U, 46503U, 28567U, 26060U, 11993U, |
| 15548 | 45357U, 27094U, 25606U, 2504U, 44967U, 26628U, 25254U, 19379U, |
| 15549 | 45691U, 27552U, 25948U, 15576U, 45547U, 27368U, 25768U, 6087U, |
| 15550 | 45157U, 26902U, 25416U, 11917U, 45265U, 26978U, 25498U, 2428U, |
| 15551 | 44875U, 26512U, 25146U, 19302U, 45605U, 27442U, 25848U, 15520U, |
| 15552 | 27212U, 25688U, 46624U, 28716U, 6031U, 26746U, 25336U, 46556U, |
| 15553 | 28632U, 21597U, 27664U, 26024U, 46690U, 28798U, 26286U, 23379U, |
| 15554 | 26120U, 23444U, 26370U, 23460U, 26226U, 28863U, 30582U, 34328U, |
| 15555 | 41634U, 52051U, 40986U, 41668U, 52087U, 41020U, 41534U, 51945U, |
| 15556 | 40886U, 41578U, 51991U, 40930U, 41510U, 51654U, 40612U, 41608U, |
| 15557 | 52023U, 40960U, 31774U, 8408U, 32014U, 8417U, 40199U, 47779U, |
| 15558 | 40423U, 48003U, 19903U, 3941U, 13411U, 5200U, 14631U, 20755U, |
| 15559 | 20150U, 4270U, 13740U, 5579U, 15010U, 21018U, 40130U, 47710U, |
| 15560 | 40354U, 47934U, 19858U, 3856U, 13326U, 5131U, 14562U, 20677U, |
| 15561 | 20105U, 4185U, 13655U, 5510U, 14941U, 20940U, 24399U, 30257U, |
| 15562 | 3952U, 13422U, 4281U, 13751U, 9122U, 4974U, 14405U, 9372U, |
| 15563 | 5353U, 14784U, 33911U, 40047U, 47634U, 40271U, 47851U, 40206U, |
| 15564 | 47786U, 40430U, 48010U, 3521U, 12991U, 4733U, 14164U, 19465U, |
| 15565 | 3134U, 12604U, 4405U, 13875U, 20229U, 28941U, 30662U, 3980U, |
| 15566 | 13450U, 4309U, 13779U, 9242U, 5107U, 14538U, 9492U, 5486U, |
| 15567 | 14917U, 34500U, 40151U, 47731U, 40375U, 47955U, 40224U, 47804U, |
| 15568 | 40448U, 48028U, 3653U, 13123U, 4820U, 14251U, 19577U, 3422U, |
| 15569 | 12892U, 4621U, 14052U, 20432U, 23536U, 29122U, 33828U, 30859U, |
| 15570 | 33501U, 9254U, 5119U, 14550U, 9504U, 5498U, 14929U, 3370U, |
| 15571 | 12840U, 20385U, 30626U, 28885U, 34372U, 34394U, 34717U, 33872U, |
| 15572 | 33850U, 19610U, 8641U, 2606U, 3442U, 9016U, 2706U, 12912U, |
| 15573 | 4654U, 14085U, 20450U, 34350U, 34199U, 34667U, 24346U, 35793U, |
| 15574 | 8395U, 24285U, 24744U, 48U, 94U, 8355U, 33U, 33812U, |
| 15575 | 33867U, 34186U, 34655U, 24335U, 35781U, 8382U, 24267U, 24733U, |
| 15576 | 25U, 33803U, 24801U, 30441U, 9606U, 21516U, 3966U, 13436U, |
| 15577 | 4295U, 13765U, 9230U, 5095U, 14526U, 9480U, 5474U, 14905U, |
| 15578 | 34118U, 40123U, 47703U, 40347U, 47927U, 40495U, 48037U, 40215U, |
| 15579 | 47795U, 40439U, 48019U, 3641U, 13111U, 4808U, 14239U, 19526U, |
| 15580 | 3250U, 12720U, 4560U, 13991U, 20284U, 38192U, 47540U, 3360U, |
| 15581 | 12830U, 4570U, 14001U, 24697U, 30384U, 34048U, 47424U, 40116U, |
| 15582 | 40340U, 47920U, 38112U, 47460U, 38085U, 47433U, 38137U, 47485U, |
| 15583 | 24384U, 30250U, 33904U, 28926U, 30655U, 34493U, 24794U, 30418U, |
| 15584 | 34111U, 38186U, 47534U, 38226U, 3484U, 12954U, 4696U, 14127U, |
| 15585 | 47564U, 19784U, 3782U, 13252U, 4961U, 14392U, 20609U, 20031U, |
| 15586 | 4111U, 13581U, 5340U, 14771U, 20872U, 19797U, 3795U, 13265U, |
| 15587 | 5010U, 14441U, 20621U, 20044U, 4124U, 13594U, 5389U, 14820U, |
| 15588 | 20884U, 41149U, 41723U, 15125U, 5683U, 21161U, 41503U, 42077U, |
| 15589 | 16147U, 6684U, 22099U, 17248U, 7886U, 22956U, 41326U, 41900U, |
| 15590 | 15924U, 6471U, 21923U, 17067U, 7715U, 22804U, 19546U, 3391U, |
| 15591 | 12861U, 4590U, 14021U, 20404U, 19761U, 8723U, 3759U, 9098U, |
| 15592 | 13229U, 4926U, 14357U, 20588U, 20008U, 8841U, 4088U, 9348U, |
| 15593 | 13558U, 5305U, 14736U, 20851U, 3596U, 13066U, 8977U, 4521U, |
| 15594 | 3626U, 13096U, 9003U, 4547U, 3549U, 13019U, 4761U, 14192U, |
| 15595 | 3189U, 12659U, 4460U, 13930U, 3611U, 13081U, 8990U, 4534U, |
| 15596 | 4336U, 13806U, 21040U, 3894U, 13364U, 20712U, 4223U, 13693U, |
| 15597 | 20975U, 19495U, 3164U, 12634U, 4435U, 13905U, 20256U, 3533U, |
| 15598 | 13003U, 4745U, 14176U, 3175U, 12645U, 4446U, 13916U, 3580U, |
| 15599 | 13050U, 4792U, 14223U, 3216U, 12686U, 4487U, 13957U, 3564U, |
| 15600 | 13034U, 4776U, 14207U, 3202U, 12672U, 4473U, 13943U, 19822U, |
| 15601 | 8747U, 3820U, 9182U, 13290U, 5047U, 14478U, 20644U, 20069U, |
| 15602 | 8865U, 4149U, 9432U, 13619U, 5426U, 14857U, 20907U, 3880U, |
| 15603 | 13350U, 20699U, 4209U, 13679U, 20962U, 3346U, 12816U, 20372U, |
| 15604 | 19641U, 8662U, 3495U, 9037U, 12965U, 4707U, 14138U, 20478U, |
| 15605 | 20161U, 8924U, 4323U, 9563U, 13793U, 5590U, 15021U, 21028U, |
| 15606 | 19810U, 8735U, 3808U, 9170U, 13278U, 5035U, 14466U, 20633U, |
| 15607 | 19654U, 8675U, 3508U, 9050U, 12978U, 4720U, 14151U, 20490U, |
| 15608 | 20057U, 8853U, 4137U, 9420U, 13607U, 5414U, 14845U, 20896U, |
| 15609 | 3867U, 13337U, 20687U, 4196U, 13666U, 20950U, 3333U, 12803U, |
| 15610 | 20360U, 19713U, 8711U, 3711U, 9086U, 13181U, 4878U, 14309U, |
| 15611 | 20544U, 19960U, 8829U, 4040U, 9336U, 13510U, 5257U, 14688U, |
| 15612 | 20807U, 3285U, 12755U, 20316U, 38157U, 40097U, 47684U, 40321U, |
| 15613 | 47901U, 47505U, 40165U, 47745U, 40389U, 47969U, 19316U, 21611U, |
| 15614 | 11865U, 19256U, 15468U, 21551U, 11907U, 2418U, 19293U, 15510U, |
| 15615 | 6021U, 21588U, 19736U, 3734U, 13204U, 4901U, 14332U, 20565U, |
| 15616 | 19983U, 4063U, 13533U, 5280U, 14711U, 20828U, 24507U, 30276U, |
| 15617 | 41156U, 41730U, 41333U, 41907U, 33930U, 24847U, 30478U, 41196U, |
| 15618 | 41770U, 41373U, 41947U, 34170U, 24983U, 30502U, 41206U, 41780U, |
| 15619 | 41383U, 41957U, 34178U, 25114U, 30558U, 41216U, 41790U, 41393U, |
| 15620 | 41967U, 34296U, 28893U, 30604U, 34380U, 29164U, 30901U, 41226U, |
| 15621 | 41800U, 41403U, 41977U, 34723U, 29203U, 30940U, 41236U, 41810U, |
| 15622 | 41413U, 41987U, 34762U, 19835U, 8760U, 3833U, 9195U, 13303U, |
| 15623 | 5060U, 14491U, 20656U, 20082U, 8878U, 4162U, 9445U, 13632U, |
| 15624 | 5439U, 14870U, 20919U, 3310U, 12780U, 20339U, 19869U, 8783U, |
| 15625 | 3907U, 9266U, 13377U, 5142U, 14573U, 20724U, 20116U, 8901U, |
| 15626 | 4236U, 9516U, 13706U, 5521U, 14952U, 20987U, 38165U, 40106U, |
| 15627 | 47693U, 40330U, 47910U, 47513U, 40174U, 47754U, 40398U, 47978U, |
| 15628 | 19678U, 8688U, 3676U, 9063U, 13146U, 4843U, 14274U, 20512U, |
| 15629 | 19925U, 8806U, 4005U, 9313U, 13475U, 5222U, 14653U, 20775U, |
| 15630 | 3260U, 12730U, 20293U, 24838U, 34161U, 29023U, 30993U, 33177U, |
| 15631 | 31081U, 28838U, 30566U, 34304U, 24682U, 30369U, 34001U, 29007U, |
| 15632 | 30772U, 34616U, 28999U, 30764U, 34543U, 15198U, 5766U, 21297U, |
| 15633 | 15177U, 5735U, 21278U, 9218U, 5083U, 14514U, 9468U, 5462U, |
| 15634 | 14893U, 19630U, 8651U, 3473U, 9026U, 12943U, 4685U, 14116U, |
| 15635 | 20468U, 19847U, 8772U, 3845U, 9207U, 13315U, 5072U, 14503U, |
| 15636 | 20667U, 20094U, 8890U, 4174U, 9457U, 13644U, 5451U, 14882U, |
| 15637 | 20930U, 3322U, 12792U, 20350U, 19881U, 8795U, 3919U, 9278U, |
| 15638 | 13389U, 5154U, 14585U, 20735U, 20128U, 8913U, 4248U, 9528U, |
| 15639 | 13718U, 5533U, 14964U, 20998U, 25066U, 30510U, 34243U, 25080U, |
| 15640 | 30524U, 34257U, 19506U, 8621U, 3230U, 8957U, 12700U, 4501U, |
| 15641 | 13971U, 20266U, 25094U, 30538U, 34271U, 23522U, 29069U, 30780U, |
| 15642 | 34624U, 19690U, 8700U, 3688U, 9075U, 13158U, 4855U, 14286U, |
| 15643 | 20523U, 19937U, 8818U, 4017U, 9325U, 13487U, 5234U, 14665U, |
| 15644 | 20786U, 19516U, 8631U, 3240U, 8967U, 12710U, 4511U, 13981U, |
| 15645 | 20275U, 11943U, 25536U, 2454U, 25184U, 19334U, 25883U, 45467U, |
| 15646 | 27268U, 45077U, 26802U, 45794U, 27717U, 11857U, 33108U, 45884U, |
| 15647 | 38645U, 49195U, 39826U, 50571U, 34815U, 46152U, 38827U, 49401U, |
| 15648 | 39960U, 50729U, 39368U, 50029U, 2378U, 33072U, 45824U, 38553U, |
| 15649 | 49091U, 39758U, 50491U, 34779U, 46092U, 38735U, 49297U, 39892U, |
| 15650 | 50649U, 39025U, 49626U, 8593U, 33090U, 45854U, 38599U, 49143U, |
| 15651 | 39792U, 50531U, 34797U, 46122U, 38781U, 49349U, 39926U, 50689U, |
| 15652 | 39272U, 49915U, 19249U, 33125U, 45913U, 38690U, 49246U, 39859U, |
| 15653 | 50610U, 34832U, 46181U, 38872U, 49452U, 39993U, 50768U, 39582U, |
| 15654 | 50282U, 15460U, 46022U, 27851U, 46290U, 28207U, 28028U, 28384U, |
| 15655 | 39470U, 50149U, 5981U, 45946U, 27759U, 46214U, 28115U, 27940U, |
| 15656 | 28296U, 39127U, 49746U, 9623U, 45984U, 27805U, 46252U, 28161U, |
| 15657 | 27984U, 28340U, 39304U, 49953U, 21544U, 46059U, 27896U, 46327U, |
| 15658 | 28252U, 28071U, 28427U, 39678U, 50396U, 11963U, 45309U, 27034U, |
| 15659 | 25564U, 2474U, 44919U, 26568U, 25212U, 19352U, 45646U, 27495U, |
| 15660 | 25909U, 15546U, 45499U, 27308U, 25726U, 6057U, 45109U, 26842U, |
| 15661 | 25374U, 11841U, 39336U, 49991U, 2362U, 38993U, 49588U, 19235U, |
| 15662 | 39552U, 50246U, 11883U, 39400U, 50067U, 2394U, 39057U, 49664U, |
| 15663 | 19272U, 39612U, 50318U, 15486U, 45437U, 38466U, 48992U, 39502U, |
| 15664 | 50187U, 5997U, 45047U, 38422U, 48942U, 39159U, 49784U, 21567U, |
| 15665 | 45766U, 38509U, 49041U, 39708U, 50432U, 11983U, 45341U, 27074U, |
| 15666 | 25592U, 2494U, 44951U, 26608U, 25240U, 19370U, 45676U, 27533U, |
| 15667 | 25935U, 15566U, 45531U, 27348U, 25754U, 6077U, 45141U, 26882U, |
| 15668 | 25402U, 11899U, 45251U, 26960U, 25486U, 2410U, 44861U, 26494U, |
| 15669 | 25134U, 19286U, 45592U, 27425U, 25837U, 15502U, 27194U, 25676U, |
| 15670 | 46607U, 28695U, 6013U, 26728U, 25324U, 46539U, 28611U, 21581U, |
| 15671 | 27647U, 26013U, 46674U, 28778U, 12003U, 45373U, 27114U, 25620U, |
| 15672 | 2514U, 44983U, 26648U, 25268U, 19388U, 45706U, 27571U, 25961U, |
| 15673 | 15586U, 45563U, 27388U, 25782U, 6097U, 45173U, 26922U, 25430U, |
| 15674 | 11925U, 45279U, 26996U, 25510U, 2436U, 44889U, 26530U, 25158U, |
| 15675 | 19309U, 45618U, 27459U, 25859U, 15528U, 27230U, 25700U, 46641U, |
| 15676 | 28737U, 6039U, 26764U, 25348U, 46573U, 28653U, 21604U, 27681U, |
| 15677 | 26035U, 46706U, 28818U, 26298U, 23387U, 26132U, 23452U, 26382U, |
| 15678 | 23468U, 26238U, 28901U, 30620U, 34388U, 41651U, 52069U, 41003U, |
| 15679 | 41684U, 52104U, 41036U, 41556U, 51968U, 40908U, 41593U, 52007U, |
| 15680 | 40945U, 41522U, 51667U, 40624U, 41621U, 52037U, 40973U, 24523U, |
| 15681 | 30320U, 3273U, 12743U, 20305U, 9134U, 4986U, 14417U, 9384U, |
| 15682 | 5365U, 14796U, 33963U, 9289U, 5176U, 14607U, 9539U, 5555U, |
| 15683 | 14986U, 40061U, 47648U, 40285U, 47865U, 19475U, 8601U, 3144U, |
| 15684 | 8937U, 12614U, 4415U, 13885U, 20238U, 31001U, 31089U, 38214U, |
| 15685 | 47552U, 88U, 8318U, 8478U, 45189U, 9639U, 45213U, 131U, |
| 15686 | 8426U, 8492U, 45201U, 9645U, 45225U, 24711U, 30390U, 34062U, |
| 15687 | 28869U, 30588U, 34334U, 29180U, 30917U, 34739U, 24787U, 30404U, |
| 15688 | 34104U, 24726U, 30397U, 34077U, 28877U, 30596U, 34342U, 29188U, |
| 15689 | 30925U, 34747U, 24807U, 30447U, 34124U, 12013U, 2524U, 19397U, |
| 15690 | 15596U, 6107U, 21620U, 19600U, 3432U, 12902U, 4644U, 14075U, |
| 15691 | 20441U, 29030U, 31010U, 33184U, 31098U, 25073U, 30517U, 34250U, |
| 15692 | 25087U, 30531U, 34264U, 25101U, 30545U, 34278U, 23529U, 29015U, |
| 15693 | 30984U, 33169U, 31072U, 23514U, 12073U, 19451U, 15645U, 6156U, |
| 15694 | 21664U, 12021U, 19404U, 15604U, 6115U, 21627U, 23355U, 26084U, |
| 15695 | 23737U, 26332U, 23411U, 26166U, 23777U, 26440U, 23364U, 26097U, |
| 15696 | 23754U, 26357U, 23435U, 26202U, 23786U, 26453U, 43667U, 50845U, |
| 15697 | 51406U, 43689U, 290U, 50867U, 51422U, 44307U, 313U, 33286U, |
| 15698 | 43697U, 50882U, 51436U, 43787U, 50953U, 145U, 36165U, 30213U, |
| 15699 | 23576U, 24124U, 31018U, 43307U, 48720U, 43287U, 38020U, 48700U, |
| 15700 | 43675U, 50853U, 51414U, 31115U, 36171U, 31158U, 37601U, 32800U, |
| 15701 | 8333U, 36715U, 31997U, 36947U, 43720U, 51048U, 51554U, 43747U, |
| 15702 | 50913U, 51458U, 46940U, 46980U, 46988U, 23567U, 23711U, 30326U, |
| 15703 | 36412U, 30226U, 36385U, 31316U, 24185U, 36377U, 29916U, 29896U, |
| 15704 | 105U, 8374U, 8484U, 34084U, 23808U, 23840U, 43763U, 50929U, |
| 15705 | 51480U, 35526U, 24324U, 23846U, 35324U, 47227U, 47121U, 23349U, |
| 15706 | 23580U, 36677U, 24045U, 29128U, 30865U, 30243U, 35232U, 32491U, |
| 15707 | 35987U, 29600U, 35178U, 32437U, 35843U, 29468U, 35262U, 32521U, |
| 15708 | 36013U, 29624U, 35206U, 32465U, 35904U, 29524U, 23729U, 26320U, |
| 15709 | 23403U, 26154U, 35063U, 35867U, 29490U, 161U, 21103U, 43435U, |
| 15710 | 51233U, 35926U, 29544U, 21195U, 36707U, 24063U, 29146U, 30883U, |
| 15711 | 35299U, 35950U, 29566U, 201U, 21242U, 43465U, 51265U, 35079U, |
| 15712 | 35891U, 29512U, 181U, 21121U, 43445U, 51249U, 35315U, 35974U, |
| 15713 | 29588U, 221U, 21260U, 43475U, 51281U, 35693U, 36037U, 29646U, |
| 15714 | 241U, 21324U, 43495U, 51304U, 29366U, 41130U, 43705U, 50890U, |
| 15715 | 43802U, 50968U, 153U, 33280U, 8348U, 33821U, 8366U, 23500U, |
| 15716 | 34090U, 15220U, 43417U, 15230U, 48855U, 24303U, 8286U, 24309U, |
| 15717 | 8293U, 33241U, 32182U, 38287U, 33250U, 33232U, 32174U, 38275U, |
| 15718 | 31640U, 43339U, 48752U, 51297U, 43728U, 50905U, 51450U, 43779U, |
| 15719 | 50945U, 51488U, 24090U, 31121U, 29902U, 35036U, 23888U, 259U, |
| 15720 | 21363U, 51318U, 192U, 21187U, 43456U, 51258U, 232U, 21270U, |
| 15721 | 43486U, 51290U, 24621U, 9832U, 17738U, 36833U, 24537U, 23952U, |
| 15722 | 36588U, 23998U, 9775U, 17679U, 35329U, 36279U, 9973U, 30749U, |
| 15723 | 23721U, 36403U, 23395U, 36394U, 43771U, 50937U, 36811U, 43643U, |
| 15724 | 50814U, 51382U, 9851U, 17755U, 36848U, 23835U, 43659U, 50837U, |
| 15725 | 51398U, 36731U, 36311U, 31310U, 32218U, 30208U, 9812U, 17720U, |
| 15726 | 36817U, 36572U, 9755U, 17661U, 24173U, 23603U, 35027U, 24391U, |
| 15727 | 36621U, 31206U, 23612U, 35044U, 24755U, 36639U, 23896U, 36129U, |
| 15728 | 23879U, 36120U, 24027U, 36195U, 28933U, 36659U, 24771U, 36649U, |
| 15729 | 23506U, 33223U, 34096U, 33858U, 31705U, 33527U, 24515U, 36630U, |
| 15730 | 23622U, 35054U, 31552U, 23906U, 36139U, 24036U, 36204U, 28991U, |
| 15731 | 36668U, 23763U, 26394U, 23476U, 26250U, 34900U, 9916U, 36603U, |
| 15732 | 9794U, 17696U, 35247U, 32506U, 36000U, 29612U, 35192U, 32451U, |
| 15733 | 35855U, 29479U, 35276U, 32535U, 36025U, 29635U, 35219U, 32478U, |
| 15734 | 35915U, 29534U, 31634U, 23801U, 36699U, 24054U, 29137U, 30874U, |
| 15735 | 30411U, 23746U, 26345U, 23427U, 26190U, 35071U, 35879U, 29501U, |
| 15736 | 171U, 21112U, 51241U, 35938U, 29555U, 21204U, 36723U, 24072U, |
| 15737 | 29155U, 30892U, 35307U, 35962U, 29577U, 211U, 21251U, 51273U, |
| 15738 | 35732U, 36048U, 29656U, 250U, 21332U, 51311U, 33536U, 43651U, |
| 15739 | 280U, 50822U, 51390U, 44296U, 300U, 23587U, 9705U, 30284U, |
| 15740 | 23926U, 9737U, 30795U, 23631U, 30300U, 43755U, 50921U, 51466U, |
| 15741 | 23873U, 43852U, 51017U, 51529U, 36115U, 23561U, 35020U, 36148U, |
| 15742 | 9860U, 17763U, 36855U, 36745U, 29809U, 36325U, 9822U, 17729U, |
| 15743 | 36825U, 36580U, 9765U, 17670U, 31198U, 31214U, 31560U, 9841U, |
| 15744 | 17746U, 36840U, 36595U, 9784U, 17687U, 17712U, 17652U, 34907U, |
| 15745 | 9925U, 36610U, 9803U, 17704U, 23595U, 9715U, 30292U, 23939U, |
| 15746 | 9746U, 30808U, 34131U, 24119U, 51039U, 8513U, 21180U, 32922U, |
| 15747 | 43346U, 50875U, 43557U, 50806U, 33292U, 24919U, 43795U, 50961U, |
| 15748 | 24081U, 24139U, 35640U, 31241U, 48802U, 43424U, 48868U, 36617U, |
| 15749 | 34212U, 37607U, 36960U, 36942U, 52608U, 50787U, 21317U, 48759U, |
| 15750 | 34285U, 33588U, 35533U, 35475U, 47181U, 47206U, 47248U, 23420U, |
| 15751 | 43255U, 48677U, 43293U, 48706U, 23861U, 30728U, 43355U, 43504U, |
| 15752 | 48775U, 43565U, 43713U, 50898U, 43810U, 50976U, 48810U, 21356U, |
| 15753 | 48862U, 31735U, 32567U, 33845U, 24529U, 32881U, 30743U, 36285U, |
| 15754 | 9981U, 30757U, 33625U, 23868U, 24105U, 24924U, 26215U, 43262U, |
| 15755 | 48684U, 43300U, 48713U, 43381U, 48796U, 43573U, 8506U, 21142U, |
| 15756 | 50830U, 43549U, 24330U, 23933U, 30802U, 32742U, 36110U, 29815U, |
| 15757 | 23946U, 30815U, 77U, |
| 15758 | }; |
| 15759 | |
| 15760 | extern const uint8_t ARMInstrDeprecationFeatures[] = { |
| 15761 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15762 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15763 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15764 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15765 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15766 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15767 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15768 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15769 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15770 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15771 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15772 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15773 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15774 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15775 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15776 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15777 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15778 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15779 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15780 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15781 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15782 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15783 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15784 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15785 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15786 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15787 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15788 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15789 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15790 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15791 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15792 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15793 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15794 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15795 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15796 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15797 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15798 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15799 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15800 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15801 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15802 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15803 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15804 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15805 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15806 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15807 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15808 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15809 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15810 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15811 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15812 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15813 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15814 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15815 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15816 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15817 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15818 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15819 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15820 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15821 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15822 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15823 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15824 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15825 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15826 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15827 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15828 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15829 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15830 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15831 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15832 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15833 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15834 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15835 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15836 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15837 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15838 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15839 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15840 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15841 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15842 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15843 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15844 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15845 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15846 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15847 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15848 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15849 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15850 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15851 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15852 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15853 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15854 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15855 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15856 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15857 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15858 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15859 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15860 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15861 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15862 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15863 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15864 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15865 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15866 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15867 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15868 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15869 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15870 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15871 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15872 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15873 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15874 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15875 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15876 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15877 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15878 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15879 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15880 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15881 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15882 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15883 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15884 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15885 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15886 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15887 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15888 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15889 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15890 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15891 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15892 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15893 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15894 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15895 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15896 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15897 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15898 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15899 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15900 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15901 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15902 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15903 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15904 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15905 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15906 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15907 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15908 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15909 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15910 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15911 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15912 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15913 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15914 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15915 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15916 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15917 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15918 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15919 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15920 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15921 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15922 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15923 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15924 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15925 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15926 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15927 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15928 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15929 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15930 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15931 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15932 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15933 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15934 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15935 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15936 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15937 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15938 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15939 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15940 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15941 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15942 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15943 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15944 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15945 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15946 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15947 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15948 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15949 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15950 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15951 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15952 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15953 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15954 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15955 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15956 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15957 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15958 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15959 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15960 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15961 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15962 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15963 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15964 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15965 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15966 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15967 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15968 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15969 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15970 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15971 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15972 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15973 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15974 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15975 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15976 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15977 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15978 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15979 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15980 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15981 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15982 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15983 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15984 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15985 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15986 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15987 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15988 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15989 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15990 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15991 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15992 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15993 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15994 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15995 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15996 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15997 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15998 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), ARM::HasV8Ops, |
| 15999 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16000 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16001 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16002 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16003 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16004 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16005 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16006 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16007 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16008 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16009 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16010 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16011 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16012 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16013 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16014 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16015 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16016 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16017 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16018 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16019 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16020 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16021 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16022 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16023 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16024 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16025 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16026 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16027 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16028 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16029 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16030 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16031 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16032 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16033 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16034 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16035 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16036 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16037 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16038 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16039 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16040 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16041 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16042 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16043 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16044 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16045 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16046 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16047 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16048 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16049 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16050 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16051 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16052 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16053 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16054 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16055 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16056 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16057 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16058 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16059 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16060 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16061 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16062 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16063 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16064 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16065 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16066 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16067 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16068 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16069 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16070 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16071 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16072 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16073 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16074 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16075 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16076 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16077 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16078 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16079 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16080 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16081 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16082 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16083 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16084 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16085 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16086 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16087 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16088 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16089 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16090 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16091 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16092 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16093 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16094 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16095 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16096 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16097 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16098 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16099 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16100 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16101 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16102 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16103 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16104 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16105 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16106 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16107 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16108 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16109 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16110 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16111 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16112 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16113 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16114 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16115 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16116 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16117 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16118 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16119 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16120 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16121 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16122 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16123 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16124 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16125 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16126 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16127 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16128 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16129 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16130 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16131 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16132 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16133 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16134 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16135 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16136 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16137 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16138 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16139 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16140 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16141 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16142 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16143 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16144 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16145 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16146 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16147 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16148 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16149 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16150 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16151 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16152 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16153 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16154 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16155 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16156 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16157 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16158 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16159 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16160 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16161 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16162 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16163 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16164 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16165 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16166 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16167 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16168 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16169 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16170 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16171 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16172 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16173 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16174 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16175 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16176 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16177 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16178 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16179 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16180 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16181 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16182 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16183 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16184 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16185 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16186 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16187 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16188 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16189 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16190 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16191 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16192 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16193 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16194 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16195 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16196 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16197 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16198 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16199 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16200 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16201 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16202 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16203 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16204 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16205 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16206 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16207 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16208 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16209 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16210 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16211 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16212 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16213 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16214 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16215 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16216 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16217 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16218 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16219 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16220 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16221 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16222 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16223 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16224 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16225 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16226 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16227 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16228 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16229 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16230 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16231 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16232 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16233 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16234 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16235 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16236 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16237 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16238 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16239 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16240 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16241 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16242 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16243 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16244 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16245 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16246 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16247 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16248 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16249 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16250 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16251 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16252 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16253 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16254 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16255 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16256 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16257 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16258 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16259 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16260 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16261 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16262 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16263 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16264 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16265 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16266 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16267 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16268 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16269 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16270 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16271 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16272 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16273 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16274 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16275 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16276 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16277 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16278 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16279 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16280 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16281 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16282 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16283 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16284 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16285 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16286 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16287 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16288 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16289 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16290 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16291 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16292 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16293 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16294 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16295 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16296 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16297 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16298 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16299 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16300 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16301 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16302 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16303 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16304 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16305 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16306 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16307 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16308 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16309 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16310 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16311 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16312 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16313 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16314 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16315 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16316 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16317 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16318 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16319 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16320 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16321 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), ARM::HasV8Ops, uint8_t(-1), uint8_t(-1), |
| 16322 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16323 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16324 | uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16325 | }; |
| 16326 | |
| 16327 | extern const MCInstrInfo::ComplexDeprecationPredicate ARMInstrComplexDeprecationInfos[] = { |
| 16328 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16329 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16330 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16331 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16332 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16333 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16334 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16335 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16336 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16337 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16338 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16339 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16340 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16341 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16342 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16343 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16344 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16345 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16346 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16347 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16348 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16349 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16350 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16351 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16352 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16353 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16354 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16355 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16356 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16357 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16358 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16359 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16360 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16361 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16362 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16363 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16364 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16365 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16366 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16367 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16368 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16369 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16370 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16371 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16372 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16373 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16374 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16375 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16376 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16377 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16378 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16379 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16380 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16381 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16382 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16383 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16384 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16385 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16386 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16387 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16388 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16389 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16390 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16391 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16392 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16393 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16394 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16395 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16396 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16397 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16398 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16399 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16400 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16401 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16402 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16403 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16404 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16405 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16406 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16407 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16408 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16409 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16410 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16411 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16412 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16413 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16414 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16415 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16416 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16417 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16418 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16419 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16420 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16421 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16422 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16423 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16424 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16425 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16426 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16427 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16428 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16429 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16430 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16431 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16432 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16433 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16434 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16435 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16436 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16437 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16438 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16439 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16440 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16441 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16442 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16443 | nullptr, nullptr, nullptr, nullptr, nullptr, &getARMLoadDeprecationInfo, &getARMLoadDeprecationInfo, &getARMLoadDeprecationInfo, |
| 16444 | &getARMLoadDeprecationInfo, &getARMLoadDeprecationInfo, &getARMLoadDeprecationInfo, &getARMLoadDeprecationInfo, &getARMLoadDeprecationInfo, nullptr, nullptr, nullptr, |
| 16445 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16446 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16447 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16448 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16449 | nullptr, nullptr, nullptr, nullptr, &getMCRDeprecationInfo, nullptr, nullptr, nullptr, |
| 16450 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16451 | nullptr, nullptr, &getMRCDeprecationInfo, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16452 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16453 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16454 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16455 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16456 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16457 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16458 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16459 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16460 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16461 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16462 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16463 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16464 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16465 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16466 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16467 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16468 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16469 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16470 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16471 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16472 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16473 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16474 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16475 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16476 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16477 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16478 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16479 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16480 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16481 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16482 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16483 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16484 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16485 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16486 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16487 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16488 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16489 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16490 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16491 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16492 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16493 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16494 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16495 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16496 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16497 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16498 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16499 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16500 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16501 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16502 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16503 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16504 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16505 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16506 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16507 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16508 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16509 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16510 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16511 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16512 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16513 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16514 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16515 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16516 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16517 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16518 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16519 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16520 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16521 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16522 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16523 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16524 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16525 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16526 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16527 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16528 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16529 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16530 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16531 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16532 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16533 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16534 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16535 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16536 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16537 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16538 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16539 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16540 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16541 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16542 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16543 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16544 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16545 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16546 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16547 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16548 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16549 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16550 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16551 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16552 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16553 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16554 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16555 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16556 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16557 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16558 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16559 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16560 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16561 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16562 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16563 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16564 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16565 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16566 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16567 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16568 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16569 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16570 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16571 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16572 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16573 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16574 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16575 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16576 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16577 | nullptr, nullptr, &getARMStoreDeprecationInfo, &getARMStoreDeprecationInfo, &getARMStoreDeprecationInfo, &getARMStoreDeprecationInfo, &getARMStoreDeprecationInfo, &getARMStoreDeprecationInfo, |
| 16578 | &getARMStoreDeprecationInfo, &getARMStoreDeprecationInfo, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16579 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16580 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16581 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16582 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16583 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16584 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16585 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16586 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16587 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16588 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16589 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16590 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16591 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16592 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16593 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16594 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16595 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16596 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16597 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16598 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16599 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16600 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16601 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16602 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16603 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16604 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16605 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16606 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16607 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16608 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16609 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16610 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16611 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16612 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16613 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16614 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16615 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16616 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16617 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16618 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16619 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16620 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16621 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16622 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16623 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16624 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16625 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16626 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16627 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16628 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16629 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16630 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16631 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16632 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16633 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16634 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16635 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16636 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16637 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16638 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16639 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16640 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16641 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16642 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16643 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16644 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16645 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16646 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16647 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16648 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16649 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16650 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16651 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16652 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16653 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16654 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16655 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16656 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16657 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16658 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16659 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16660 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16661 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16662 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16663 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16664 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16665 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16666 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16667 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16668 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16669 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16670 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16671 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16672 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16673 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16674 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16675 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16676 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16677 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16678 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16679 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16680 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16681 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16682 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16683 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16684 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16685 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16686 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16687 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16688 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16689 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16690 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16691 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16692 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16693 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16694 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16695 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16696 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16697 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16698 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16699 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16700 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16701 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16702 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16703 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16704 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16705 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16706 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16707 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16708 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16709 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16710 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16711 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16712 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16713 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16714 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16715 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16716 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16717 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16718 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16719 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16720 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16721 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16722 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16723 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16724 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16725 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16726 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16727 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16728 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16729 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16730 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16731 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16732 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16733 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16734 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16735 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16736 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16737 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16738 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16739 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16740 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16741 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16742 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16743 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16744 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16745 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16746 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16747 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16748 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16749 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16750 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16751 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16752 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16753 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16754 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16755 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16756 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16757 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16758 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16759 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16760 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16761 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16762 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16763 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16764 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16765 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16766 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16767 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16768 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16769 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16770 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16771 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16772 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16773 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16774 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16775 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16776 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16777 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16778 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16779 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16780 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16781 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16782 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16783 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16784 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16785 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16786 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16787 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16788 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16789 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16790 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16791 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16792 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16793 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16794 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16795 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16796 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16797 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16798 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16799 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16800 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16801 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16802 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16803 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16804 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16805 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16806 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16807 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16808 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16809 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16810 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16811 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16812 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16813 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16814 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16815 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16816 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16817 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16818 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16819 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16820 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16821 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16822 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16823 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16824 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16825 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16826 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16827 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16828 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16829 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16830 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16831 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16832 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16833 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16834 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16835 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16836 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16837 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16838 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16839 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16840 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16841 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16842 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16843 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16844 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16845 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16846 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16847 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16848 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16849 | nullptr, nullptr, nullptr, &getMCRDeprecationInfo, nullptr, nullptr, nullptr, nullptr, |
| 16850 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16851 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16852 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16853 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16854 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16855 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16856 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16857 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16858 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16859 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16860 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16861 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16862 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16863 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16864 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16865 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16866 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16867 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16868 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16869 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16870 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16871 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16872 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16873 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16874 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16875 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16876 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16877 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16878 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16879 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16880 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16881 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16882 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16883 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16884 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16885 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16886 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16887 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16888 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16889 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16890 | nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, |
| 16891 | nullptr, nullptr, nullptr, |
| 16892 | }; |
| 16893 | |
| 16894 | static inline void InitARMMCInstrInfo(MCInstrInfo *II) { |
| 16895 | II->InitMCInstrInfo(ARMDescs.Insts, ARMInstrNameIndices, ARMInstrNameData, ARMInstrDeprecationFeatures, ARMInstrComplexDeprecationInfos, 4507); |
| 16896 | } |
| 16897 | |
| 16898 | } // end namespace llvm |
| 16899 | #endif // GET_INSTRINFO_MC_DESC |
| 16900 | |
| 16901 | #ifdef GET_INSTRINFO_HEADER |
| 16902 | #undef GET_INSTRINFO_HEADER |
| 16903 | namespace llvm { |
| 16904 | struct ARMGenInstrInfo : public TargetInstrInfo { |
| 16905 | explicit ARMGenInstrInfo(unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u); |
| 16906 | ~ARMGenInstrInfo() override = default; |
| 16907 | |
| 16908 | }; |
| 16909 | } // end namespace llvm |
| 16910 | #endif // GET_INSTRINFO_HEADER |
| 16911 | |
| 16912 | #ifdef GET_INSTRINFO_HELPER_DECLS |
| 16913 | #undef GET_INSTRINFO_HELPER_DECLS |
| 16914 | |
| 16915 | |
| 16916 | #endif // GET_INSTRINFO_HELPER_DECLS |
| 16917 | |
| 16918 | #ifdef GET_INSTRINFO_HELPERS |
| 16919 | #undef GET_INSTRINFO_HELPERS |
| 16920 | |
| 16921 | #endif // GET_INSTRINFO_HELPERS |
| 16922 | |
| 16923 | #ifdef GET_INSTRINFO_CTOR_DTOR |
| 16924 | #undef GET_INSTRINFO_CTOR_DTOR |
| 16925 | namespace llvm { |
| 16926 | extern const ARMInstrTable ARMDescs; |
| 16927 | extern const unsigned ARMInstrNameIndices[]; |
| 16928 | extern const char ARMInstrNameData[]; |
| 16929 | extern const uint8_t ARMInstrDeprecationFeatures[]; |
| 16930 | extern const MCInstrInfo::ComplexDeprecationPredicate ARMInstrComplexDeprecationInfos[]; |
| 16931 | ARMGenInstrInfo::ARMGenInstrInfo(unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode) |
| 16932 | : TargetInstrInfo(CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) { |
| 16933 | InitMCInstrInfo(ARMDescs.Insts, ARMInstrNameIndices, ARMInstrNameData, ARMInstrDeprecationFeatures, ARMInstrComplexDeprecationInfos, 4507); |
| 16934 | } |
| 16935 | } // end namespace llvm |
| 16936 | #endif // GET_INSTRINFO_CTOR_DTOR |
| 16937 | |
| 16938 | #ifdef GET_INSTRINFO_MC_HELPER_DECLS |
| 16939 | #undef GET_INSTRINFO_MC_HELPER_DECLS |
| 16940 | |
| 16941 | namespace llvm { |
| 16942 | class MCInst; |
| 16943 | class FeatureBitset; |
| 16944 | |
| 16945 | namespace ARM_MC { |
| 16946 | |
| 16947 | void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features); |
| 16948 | |
| 16949 | } // end namespace ARM_MC |
| 16950 | } // end namespace llvm |
| 16951 | |
| 16952 | #endif // GET_INSTRINFO_MC_HELPER_DECLS |
| 16953 | |
| 16954 | #ifdef GET_INSTRINFO_MC_HELPERS |
| 16955 | #undef GET_INSTRINFO_MC_HELPERS |
| 16956 | |
| 16957 | namespace llvm::ARM_MC { |
| 16958 | } // end namespace llvm::ARM_MC |
| 16959 | #endif // GET_GENISTRINFO_MC_HELPERS |
| 16960 | |
| 16961 | #if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) ||\ |
| 16962 | defined(GET_AVAILABLE_OPCODE_CHECKER) |
| 16963 | #define GET_COMPUTE_FEATURES |
| 16964 | #endif |
| 16965 | #ifdef GET_COMPUTE_FEATURES |
| 16966 | #undef GET_COMPUTE_FEATURES |
| 16967 | namespace llvm::ARM_MC { |
| 16968 | // Bits for subtarget features that participate in instruction matching. |
| 16969 | enum SubtargetFeatureBits : uint8_t { |
| 16970 | Feature_HasV4TBit = 35, |
| 16971 | Feature_HasV5TBit = 36, |
| 16972 | Feature_HasV5TEBit = 37, |
| 16973 | Feature_HasV6Bit = 38, |
| 16974 | Feature_HasV6MBit = 40, |
| 16975 | Feature_HasV8MBaselineBit = 45, |
| 16976 | Feature_HasV8MMainlineBit = 46, |
| 16977 | Feature_HasV8_1MMainlineBit = 47, |
| 16978 | Feature_HasMVEIntBit = 26, |
| 16979 | Feature_HasMVEFloatBit = 25, |
| 16980 | Feature_HasCDEBit = 4, |
| 16981 | Feature_HasFPRegsBit = 18, |
| 16982 | Feature_HasFPRegs16Bit = 19, |
| 16983 | Feature_HasNoFPRegs16Bit = 29, |
| 16984 | Feature_HasFPRegs64Bit = 20, |
| 16985 | Feature_HasFPRegsV8_1MBit = 21, |
| 16986 | Feature_HasV6T2Bit = 41, |
| 16987 | Feature_HasV6KBit = 39, |
| 16988 | Feature_HasV7Bit = 42, |
| 16989 | Feature_HasV8Bit = 44, |
| 16990 | Feature_PreV8Bit = 64, |
| 16991 | Feature_HasV8_1aBit = 48, |
| 16992 | Feature_HasV8_2aBit = 49, |
| 16993 | Feature_HasV8_3aBit = 50, |
| 16994 | Feature_HasV8_4aBit = 51, |
| 16995 | Feature_HasV8_5aBit = 52, |
| 16996 | Feature_HasV8_6aBit = 53, |
| 16997 | Feature_HasV8_7aBit = 54, |
| 16998 | Feature_HasVFP2Bit = 55, |
| 16999 | Feature_HasVFP3Bit = 56, |
| 17000 | Feature_HasVFP4Bit = 57, |
| 17001 | Feature_HasDPVFPBit = 10, |
| 17002 | Feature_HasFPARMv8Bit = 17, |
| 17003 | Feature_HasNEONBit = 28, |
| 17004 | Feature_HasSHA2Bit = 33, |
| 17005 | Feature_HasAESBit = 1, |
| 17006 | Feature_HasCryptoBit = 7, |
| 17007 | Feature_HasDotProdBit = 14, |
| 17008 | Feature_HasCRCBit = 6, |
| 17009 | Feature_HasRASBit = 31, |
| 17010 | Feature_HasLOBBit = 23, |
| 17011 | Feature_HasPACBTIBit = 30, |
| 17012 | Feature_HasFP16Bit = 15, |
| 17013 | Feature_HasFullFP16Bit = 22, |
| 17014 | Feature_HasFP16FMLBit = 16, |
| 17015 | Feature_HasBF16Bit = 3, |
| 17016 | Feature_HasMatMulInt8Bit = 27, |
| 17017 | Feature_HasDivideInThumbBit = 13, |
| 17018 | Feature_HasDivideInARMBit = 12, |
| 17019 | Feature_HasDSPBit = 11, |
| 17020 | Feature_HasDBBit = 8, |
| 17021 | Feature_HasDFBBit = 9, |
| 17022 | Feature_HasV7ClrexBit = 43, |
| 17023 | Feature_HasAcquireReleaseBit = 2, |
| 17024 | Feature_HasMPBit = 24, |
| 17025 | Feature_HasVirtualizationBit = 58, |
| 17026 | Feature_HasTrustZoneBit = 34, |
| 17027 | Feature_Has8MSecExtBit = 0, |
| 17028 | Feature_IsThumbBit = 62, |
| 17029 | Feature_IsThumb2Bit = 63, |
| 17030 | Feature_IsMClassBit = 60, |
| 17031 | Feature_IsNotMClassBit = 61, |
| 17032 | Feature_IsARMBit = 59, |
| 17033 | Feature_UseNaClTrapBit = 65, |
| 17034 | Feature_UseNegativeImmediatesBit = 66, |
| 17035 | Feature_HasSBBit = 32, |
| 17036 | Feature_HasCLRBHBBit = 5, |
| 17037 | }; |
| 17038 | |
| 17039 | inline FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) { |
| 17040 | FeatureBitset Features; |
| 17041 | if (FB[ARM::HasV4TOps]) |
| 17042 | Features.set(Feature_HasV4TBit); |
| 17043 | if (FB[ARM::HasV5TOps]) |
| 17044 | Features.set(Feature_HasV5TBit); |
| 17045 | if (FB[ARM::HasV5TEOps]) |
| 17046 | Features.set(Feature_HasV5TEBit); |
| 17047 | if (FB[ARM::HasV6Ops]) |
| 17048 | Features.set(Feature_HasV6Bit); |
| 17049 | if (FB[ARM::HasV6MOps]) |
| 17050 | Features.set(Feature_HasV6MBit); |
| 17051 | if (FB[ARM::HasV8MBaselineOps]) |
| 17052 | Features.set(Feature_HasV8MBaselineBit); |
| 17053 | if (FB[ARM::HasV8MMainlineOps]) |
| 17054 | Features.set(Feature_HasV8MMainlineBit); |
| 17055 | if (FB[ARM::HasV8_1MMainlineOps]) |
| 17056 | Features.set(Feature_HasV8_1MMainlineBit); |
| 17057 | if (FB[ARM::HasMVEIntegerOps]) |
| 17058 | Features.set(Feature_HasMVEIntBit); |
| 17059 | if (FB[ARM::HasMVEFloatOps]) |
| 17060 | Features.set(Feature_HasMVEFloatBit); |
| 17061 | if (FB[ARM::HasCDEOps]) |
| 17062 | Features.set(Feature_HasCDEBit); |
| 17063 | if (FB[ARM::FeatureFPRegs]) |
| 17064 | Features.set(Feature_HasFPRegsBit); |
| 17065 | if (FB[ARM::FeatureFPRegs16]) |
| 17066 | Features.set(Feature_HasFPRegs16Bit); |
| 17067 | if (!FB[ARM::FeatureFPRegs16]) |
| 17068 | Features.set(Feature_HasNoFPRegs16Bit); |
| 17069 | if (FB[ARM::FeatureFPRegs64]) |
| 17070 | Features.set(Feature_HasFPRegs64Bit); |
| 17071 | if (FB[ARM::FeatureFPRegs] && FB[ARM::HasV8_1MMainlineOps]) |
| 17072 | Features.set(Feature_HasFPRegsV8_1MBit); |
| 17073 | if (FB[ARM::HasV6T2Ops]) |
| 17074 | Features.set(Feature_HasV6T2Bit); |
| 17075 | if (FB[ARM::HasV6KOps]) |
| 17076 | Features.set(Feature_HasV6KBit); |
| 17077 | if (FB[ARM::HasV7Ops]) |
| 17078 | Features.set(Feature_HasV7Bit); |
| 17079 | if (FB[ARM::HasV8Ops]) |
| 17080 | Features.set(Feature_HasV8Bit); |
| 17081 | if (!FB[ARM::HasV8Ops]) |
| 17082 | Features.set(Feature_PreV8Bit); |
| 17083 | if (FB[ARM::HasV8_1aOps]) |
| 17084 | Features.set(Feature_HasV8_1aBit); |
| 17085 | if (FB[ARM::HasV8_2aOps]) |
| 17086 | Features.set(Feature_HasV8_2aBit); |
| 17087 | if (FB[ARM::HasV8_3aOps]) |
| 17088 | Features.set(Feature_HasV8_3aBit); |
| 17089 | if (FB[ARM::HasV8_4aOps]) |
| 17090 | Features.set(Feature_HasV8_4aBit); |
| 17091 | if (FB[ARM::HasV8_5aOps]) |
| 17092 | Features.set(Feature_HasV8_5aBit); |
| 17093 | if (FB[ARM::HasV8_6aOps]) |
| 17094 | Features.set(Feature_HasV8_6aBit); |
| 17095 | if (FB[ARM::HasV8_7aOps]) |
| 17096 | Features.set(Feature_HasV8_7aBit); |
| 17097 | if (FB[ARM::FeatureVFP2_SP]) |
| 17098 | Features.set(Feature_HasVFP2Bit); |
| 17099 | if (FB[ARM::FeatureVFP3_D16_SP]) |
| 17100 | Features.set(Feature_HasVFP3Bit); |
| 17101 | if (FB[ARM::FeatureVFP4_D16_SP]) |
| 17102 | Features.set(Feature_HasVFP4Bit); |
| 17103 | if (FB[ARM::FeatureFP64]) |
| 17104 | Features.set(Feature_HasDPVFPBit); |
| 17105 | if (FB[ARM::FeatureFPARMv8_D16_SP]) |
| 17106 | Features.set(Feature_HasFPARMv8Bit); |
| 17107 | if (FB[ARM::FeatureNEON]) |
| 17108 | Features.set(Feature_HasNEONBit); |
| 17109 | if (FB[ARM::FeatureSHA2]) |
| 17110 | Features.set(Feature_HasSHA2Bit); |
| 17111 | if (FB[ARM::FeatureAES]) |
| 17112 | Features.set(Feature_HasAESBit); |
| 17113 | if (FB[ARM::FeatureCrypto]) |
| 17114 | Features.set(Feature_HasCryptoBit); |
| 17115 | if (FB[ARM::FeatureDotProd]) |
| 17116 | Features.set(Feature_HasDotProdBit); |
| 17117 | if (FB[ARM::FeatureCRC]) |
| 17118 | Features.set(Feature_HasCRCBit); |
| 17119 | if (FB[ARM::FeatureRAS]) |
| 17120 | Features.set(Feature_HasRASBit); |
| 17121 | if (FB[ARM::FeatureLOB]) |
| 17122 | Features.set(Feature_HasLOBBit); |
| 17123 | if (FB[ARM::FeaturePACBTI]) |
| 17124 | Features.set(Feature_HasPACBTIBit); |
| 17125 | if (FB[ARM::FeatureFP16]) |
| 17126 | Features.set(Feature_HasFP16Bit); |
| 17127 | if (FB[ARM::FeatureFullFP16]) |
| 17128 | Features.set(Feature_HasFullFP16Bit); |
| 17129 | if (FB[ARM::FeatureFP16FML]) |
| 17130 | Features.set(Feature_HasFP16FMLBit); |
| 17131 | if (FB[ARM::FeatureBF16]) |
| 17132 | Features.set(Feature_HasBF16Bit); |
| 17133 | if (FB[ARM::FeatureMatMulInt8]) |
| 17134 | Features.set(Feature_HasMatMulInt8Bit); |
| 17135 | if (FB[ARM::FeatureHWDivThumb]) |
| 17136 | Features.set(Feature_HasDivideInThumbBit); |
| 17137 | if (FB[ARM::FeatureHWDivARM]) |
| 17138 | Features.set(Feature_HasDivideInARMBit); |
| 17139 | if (FB[ARM::FeatureDSP]) |
| 17140 | Features.set(Feature_HasDSPBit); |
| 17141 | if (FB[ARM::FeatureDB]) |
| 17142 | Features.set(Feature_HasDBBit); |
| 17143 | if (FB[ARM::FeatureDFB]) |
| 17144 | Features.set(Feature_HasDFBBit); |
| 17145 | if (FB[ARM::FeatureV7Clrex]) |
| 17146 | Features.set(Feature_HasV7ClrexBit); |
| 17147 | if (FB[ARM::FeatureAcquireRelease]) |
| 17148 | Features.set(Feature_HasAcquireReleaseBit); |
| 17149 | if (FB[ARM::FeatureMP]) |
| 17150 | Features.set(Feature_HasMPBit); |
| 17151 | if (FB[ARM::FeatureVirtualization]) |
| 17152 | Features.set(Feature_HasVirtualizationBit); |
| 17153 | if (FB[ARM::FeatureTrustZone]) |
| 17154 | Features.set(Feature_HasTrustZoneBit); |
| 17155 | if (FB[ARM::Feature8MSecExt]) |
| 17156 | Features.set(Feature_Has8MSecExtBit); |
| 17157 | if (FB[ARM::ModeThumb]) |
| 17158 | Features.set(Feature_IsThumbBit); |
| 17159 | if (FB[ARM::ModeThumb] && FB[ARM::FeatureThumb2]) |
| 17160 | Features.set(Feature_IsThumb2Bit); |
| 17161 | if (FB[ARM::FeatureMClass]) |
| 17162 | Features.set(Feature_IsMClassBit); |
| 17163 | if (!FB[ARM::FeatureMClass]) |
| 17164 | Features.set(Feature_IsNotMClassBit); |
| 17165 | if (!FB[ARM::ModeThumb]) |
| 17166 | Features.set(Feature_IsARMBit); |
| 17167 | if (FB[ARM::FeatureNaClTrap]) |
| 17168 | Features.set(Feature_UseNaClTrapBit); |
| 17169 | if (!FB[ARM::FeatureNoNegativeImmediates]) |
| 17170 | Features.set(Feature_UseNegativeImmediatesBit); |
| 17171 | if (FB[ARM::FeatureSB]) |
| 17172 | Features.set(Feature_HasSBBit); |
| 17173 | if (FB[ARM::FeatureCLRBHB]) |
| 17174 | Features.set(Feature_HasCLRBHBBit); |
| 17175 | return Features; |
| 17176 | } |
| 17177 | |
| 17178 | inline FeatureBitset computeRequiredFeatures(unsigned Opcode) { |
| 17179 | enum : uint8_t { |
| 17180 | CEFBS_None, |
| 17181 | CEFBS_Has8MSecExt, |
| 17182 | CEFBS_HasBF16, |
| 17183 | CEFBS_HasCDE, |
| 17184 | CEFBS_HasDotProd, |
| 17185 | CEFBS_HasFP16, |
| 17186 | CEFBS_HasFPARMv8, |
| 17187 | CEFBS_HasFPRegs, |
| 17188 | CEFBS_HasFPRegs16, |
| 17189 | CEFBS_HasFPRegs64, |
| 17190 | CEFBS_HasFPRegsV8_1M, |
| 17191 | CEFBS_HasFullFP16, |
| 17192 | CEFBS_HasMVEFloat, |
| 17193 | CEFBS_HasMVEInt, |
| 17194 | CEFBS_HasMatMulInt8, |
| 17195 | CEFBS_HasNEON, |
| 17196 | CEFBS_HasV8_1MMainline, |
| 17197 | CEFBS_HasVFP2, |
| 17198 | CEFBS_HasVFP3, |
| 17199 | CEFBS_HasVFP4, |
| 17200 | CEFBS_IsARM, |
| 17201 | CEFBS_IsThumb, |
| 17202 | CEFBS_IsThumb2, |
| 17203 | CEFBS_HasBF16_HasNEON, |
| 17204 | CEFBS_HasCDE_HasFPRegs, |
| 17205 | CEFBS_HasCDE_HasMVEInt, |
| 17206 | CEFBS_HasDSP_IsThumb2, |
| 17207 | CEFBS_HasFPARMv8_HasDPVFP, |
| 17208 | CEFBS_HasFPARMv8_HasNEON, |
| 17209 | CEFBS_HasFPARMv8_HasV8_3a, |
| 17210 | CEFBS_HasFPRegs_HasV8_1MMainline, |
| 17211 | CEFBS_HasNEON_HasFP16, |
| 17212 | CEFBS_HasNEON_HasFP16FML, |
| 17213 | CEFBS_HasNEON_HasFullFP16, |
| 17214 | CEFBS_HasNEON_HasV8_1a, |
| 17215 | CEFBS_HasNEON_HasV8_3a, |
| 17216 | CEFBS_HasNEON_HasVFP4, |
| 17217 | CEFBS_HasV7_IsMClass, |
| 17218 | CEFBS_HasV8_HasAES, |
| 17219 | CEFBS_HasV8_HasNEON, |
| 17220 | CEFBS_HasV8_HasSHA2, |
| 17221 | CEFBS_HasV8MMainline_Has8MSecExt, |
| 17222 | CEFBS_HasV8_1MMainline_Has8MSecExt, |
| 17223 | CEFBS_HasV8_1MMainline_HasFPRegs, |
| 17224 | CEFBS_HasV8_1MMainline_HasMVEInt, |
| 17225 | CEFBS_HasVFP2_HasDPVFP, |
| 17226 | CEFBS_HasVFP3_HasDPVFP, |
| 17227 | CEFBS_HasVFP4_HasDPVFP, |
| 17228 | CEFBS_IsARM_HasAcquireRelease, |
| 17229 | CEFBS_IsARM_HasCRC, |
| 17230 | CEFBS_IsARM_HasDB, |
| 17231 | CEFBS_IsARM_HasDivideInARM, |
| 17232 | CEFBS_IsARM_HasSB, |
| 17233 | CEFBS_IsARM_HasTrustZone, |
| 17234 | CEFBS_IsARM_HasV4T, |
| 17235 | CEFBS_IsARM_HasV5T, |
| 17236 | CEFBS_IsARM_HasV5TE, |
| 17237 | CEFBS_IsARM_HasV6, |
| 17238 | CEFBS_IsARM_HasV6K, |
| 17239 | CEFBS_IsARM_HasV6T2, |
| 17240 | CEFBS_IsARM_HasV7, |
| 17241 | CEFBS_IsARM_HasV8, |
| 17242 | CEFBS_IsARM_HasV8_4a, |
| 17243 | CEFBS_IsARM_HasVFP2, |
| 17244 | CEFBS_IsARM_HasVirtualization, |
| 17245 | CEFBS_IsARM_PreV8, |
| 17246 | CEFBS_IsARM_UseNaClTrap, |
| 17247 | CEFBS_IsThumb_Has8MSecExt, |
| 17248 | CEFBS_IsThumb_HasAcquireRelease, |
| 17249 | CEFBS_IsThumb_HasDB, |
| 17250 | CEFBS_IsThumb_HasV5T, |
| 17251 | CEFBS_IsThumb_HasV6, |
| 17252 | CEFBS_IsThumb_HasV6M, |
| 17253 | CEFBS_IsThumb_HasV7Clrex, |
| 17254 | CEFBS_IsThumb_HasV8, |
| 17255 | CEFBS_IsThumb_HasV8MBaseline, |
| 17256 | CEFBS_IsThumb_HasV8_4a, |
| 17257 | CEFBS_IsThumb_HasVirtualization, |
| 17258 | CEFBS_IsThumb_IsMClass, |
| 17259 | CEFBS_IsThumb_IsNotMClass, |
| 17260 | CEFBS_IsThumb2_HasCRC, |
| 17261 | CEFBS_IsThumb2_HasDSP, |
| 17262 | CEFBS_IsThumb2_HasSB, |
| 17263 | CEFBS_IsThumb2_HasTrustZone, |
| 17264 | CEFBS_IsThumb2_HasV7, |
| 17265 | CEFBS_IsThumb2_HasV8, |
| 17266 | CEFBS_IsThumb2_HasVFP2, |
| 17267 | CEFBS_IsThumb2_HasVirtualization, |
| 17268 | CEFBS_IsThumb2_IsNotMClass, |
| 17269 | CEFBS_IsThumb2_PreV8, |
| 17270 | CEFBS_PreV8_IsThumb2, |
| 17271 | CEFBS_HasDivideInThumb_IsThumb_HasV8MBaseline, |
| 17272 | CEFBS_HasFPARMv8_HasNEON_HasFullFP16, |
| 17273 | CEFBS_HasNEON_HasV8_3a_HasFullFP16, |
| 17274 | CEFBS_HasV8_HasNEON_HasFullFP16, |
| 17275 | CEFBS_IsARM_HasAcquireRelease_HasV7Clrex, |
| 17276 | CEFBS_IsARM_HasV7_HasMP, |
| 17277 | CEFBS_IsARM_HasV8_HasV8_1a, |
| 17278 | CEFBS_IsThumb_HasAcquireRelease_HasV7Clrex, |
| 17279 | CEFBS_IsThumb_HasV5T_IsNotMClass, |
| 17280 | CEFBS_IsThumb2_HasV7_HasMP, |
| 17281 | CEFBS_IsThumb2_HasV8_HasV8_1a, |
| 17282 | CEFBS_IsThumb2_HasV8_1MMainline_HasLOB, |
| 17283 | CEFBS_IsThumb2_HasV8_1MMainline_HasPACBTI, |
| 17284 | CEFBS_IsThumb_HasAcquireRelease_HasV7Clrex_IsNotMClass, |
| 17285 | }; |
| 17286 | |
| 17287 | static constexpr FeatureBitset FeatureBitsets[] = { |
| 17288 | {}, // CEFBS_None |
| 17289 | {Feature_Has8MSecExtBit, }, |
| 17290 | {Feature_HasBF16Bit, }, |
| 17291 | {Feature_HasCDEBit, }, |
| 17292 | {Feature_HasDotProdBit, }, |
| 17293 | {Feature_HasFP16Bit, }, |
| 17294 | {Feature_HasFPARMv8Bit, }, |
| 17295 | {Feature_HasFPRegsBit, }, |
| 17296 | {Feature_HasFPRegs16Bit, }, |
| 17297 | {Feature_HasFPRegs64Bit, }, |
| 17298 | {Feature_HasFPRegsV8_1MBit, }, |
| 17299 | {Feature_HasFullFP16Bit, }, |
| 17300 | {Feature_HasMVEFloatBit, }, |
| 17301 | {Feature_HasMVEIntBit, }, |
| 17302 | {Feature_HasMatMulInt8Bit, }, |
| 17303 | {Feature_HasNEONBit, }, |
| 17304 | {Feature_HasV8_1MMainlineBit, }, |
| 17305 | {Feature_HasVFP2Bit, }, |
| 17306 | {Feature_HasVFP3Bit, }, |
| 17307 | {Feature_HasVFP4Bit, }, |
| 17308 | {Feature_IsARMBit, }, |
| 17309 | {Feature_IsThumbBit, }, |
| 17310 | {Feature_IsThumb2Bit, }, |
| 17311 | {Feature_HasBF16Bit, Feature_HasNEONBit, }, |
| 17312 | {Feature_HasCDEBit, Feature_HasFPRegsBit, }, |
| 17313 | {Feature_HasCDEBit, Feature_HasMVEIntBit, }, |
| 17314 | {Feature_HasDSPBit, Feature_IsThumb2Bit, }, |
| 17315 | {Feature_HasFPARMv8Bit, Feature_HasDPVFPBit, }, |
| 17316 | {Feature_HasFPARMv8Bit, Feature_HasNEONBit, }, |
| 17317 | {Feature_HasFPARMv8Bit, Feature_HasV8_3aBit, }, |
| 17318 | {Feature_HasFPRegsBit, Feature_HasV8_1MMainlineBit, }, |
| 17319 | {Feature_HasNEONBit, Feature_HasFP16Bit, }, |
| 17320 | {Feature_HasNEONBit, Feature_HasFP16FMLBit, }, |
| 17321 | {Feature_HasNEONBit, Feature_HasFullFP16Bit, }, |
| 17322 | {Feature_HasNEONBit, Feature_HasV8_1aBit, }, |
| 17323 | {Feature_HasNEONBit, Feature_HasV8_3aBit, }, |
| 17324 | {Feature_HasNEONBit, Feature_HasVFP4Bit, }, |
| 17325 | {Feature_HasV7Bit, Feature_IsMClassBit, }, |
| 17326 | {Feature_HasV8Bit, Feature_HasAESBit, }, |
| 17327 | {Feature_HasV8Bit, Feature_HasNEONBit, }, |
| 17328 | {Feature_HasV8Bit, Feature_HasSHA2Bit, }, |
| 17329 | {Feature_HasV8MMainlineBit, Feature_Has8MSecExtBit, }, |
| 17330 | {Feature_HasV8_1MMainlineBit, Feature_Has8MSecExtBit, }, |
| 17331 | {Feature_HasV8_1MMainlineBit, Feature_HasFPRegsBit, }, |
| 17332 | {Feature_HasV8_1MMainlineBit, Feature_HasMVEIntBit, }, |
| 17333 | {Feature_HasVFP2Bit, Feature_HasDPVFPBit, }, |
| 17334 | {Feature_HasVFP3Bit, Feature_HasDPVFPBit, }, |
| 17335 | {Feature_HasVFP4Bit, Feature_HasDPVFPBit, }, |
| 17336 | {Feature_IsARMBit, Feature_HasAcquireReleaseBit, }, |
| 17337 | {Feature_IsARMBit, Feature_HasCRCBit, }, |
| 17338 | {Feature_IsARMBit, Feature_HasDBBit, }, |
| 17339 | {Feature_IsARMBit, Feature_HasDivideInARMBit, }, |
| 17340 | {Feature_IsARMBit, Feature_HasSBBit, }, |
| 17341 | {Feature_IsARMBit, Feature_HasTrustZoneBit, }, |
| 17342 | {Feature_IsARMBit, Feature_HasV4TBit, }, |
| 17343 | {Feature_IsARMBit, Feature_HasV5TBit, }, |
| 17344 | {Feature_IsARMBit, Feature_HasV5TEBit, }, |
| 17345 | {Feature_IsARMBit, Feature_HasV6Bit, }, |
| 17346 | {Feature_IsARMBit, Feature_HasV6KBit, }, |
| 17347 | {Feature_IsARMBit, Feature_HasV6T2Bit, }, |
| 17348 | {Feature_IsARMBit, Feature_HasV7Bit, }, |
| 17349 | {Feature_IsARMBit, Feature_HasV8Bit, }, |
| 17350 | {Feature_IsARMBit, Feature_HasV8_4aBit, }, |
| 17351 | {Feature_IsARMBit, Feature_HasVFP2Bit, }, |
| 17352 | {Feature_IsARMBit, Feature_HasVirtualizationBit, }, |
| 17353 | {Feature_IsARMBit, Feature_PreV8Bit, }, |
| 17354 | {Feature_IsARMBit, Feature_UseNaClTrapBit, }, |
| 17355 | {Feature_IsThumbBit, Feature_Has8MSecExtBit, }, |
| 17356 | {Feature_IsThumbBit, Feature_HasAcquireReleaseBit, }, |
| 17357 | {Feature_IsThumbBit, Feature_HasDBBit, }, |
| 17358 | {Feature_IsThumbBit, Feature_HasV5TBit, }, |
| 17359 | {Feature_IsThumbBit, Feature_HasV6Bit, }, |
| 17360 | {Feature_IsThumbBit, Feature_HasV6MBit, }, |
| 17361 | {Feature_IsThumbBit, Feature_HasV7ClrexBit, }, |
| 17362 | {Feature_IsThumbBit, Feature_HasV8Bit, }, |
| 17363 | {Feature_IsThumbBit, Feature_HasV8MBaselineBit, }, |
| 17364 | {Feature_IsThumbBit, Feature_HasV8_4aBit, }, |
| 17365 | {Feature_IsThumbBit, Feature_HasVirtualizationBit, }, |
| 17366 | {Feature_IsThumbBit, Feature_IsMClassBit, }, |
| 17367 | {Feature_IsThumbBit, Feature_IsNotMClassBit, }, |
| 17368 | {Feature_IsThumb2Bit, Feature_HasCRCBit, }, |
| 17369 | {Feature_IsThumb2Bit, Feature_HasDSPBit, }, |
| 17370 | {Feature_IsThumb2Bit, Feature_HasSBBit, }, |
| 17371 | {Feature_IsThumb2Bit, Feature_HasTrustZoneBit, }, |
| 17372 | {Feature_IsThumb2Bit, Feature_HasV7Bit, }, |
| 17373 | {Feature_IsThumb2Bit, Feature_HasV8Bit, }, |
| 17374 | {Feature_IsThumb2Bit, Feature_HasVFP2Bit, }, |
| 17375 | {Feature_IsThumb2Bit, Feature_HasVirtualizationBit, }, |
| 17376 | {Feature_IsThumb2Bit, Feature_IsNotMClassBit, }, |
| 17377 | {Feature_IsThumb2Bit, Feature_PreV8Bit, }, |
| 17378 | {Feature_PreV8Bit, Feature_IsThumb2Bit, }, |
| 17379 | {Feature_HasDivideInThumbBit, Feature_IsThumbBit, Feature_HasV8MBaselineBit, }, |
| 17380 | {Feature_HasFPARMv8Bit, Feature_HasNEONBit, Feature_HasFullFP16Bit, }, |
| 17381 | {Feature_HasNEONBit, Feature_HasV8_3aBit, Feature_HasFullFP16Bit, }, |
| 17382 | {Feature_HasV8Bit, Feature_HasNEONBit, Feature_HasFullFP16Bit, }, |
| 17383 | {Feature_IsARMBit, Feature_HasAcquireReleaseBit, Feature_HasV7ClrexBit, }, |
| 17384 | {Feature_IsARMBit, Feature_HasV7Bit, Feature_HasMPBit, }, |
| 17385 | {Feature_IsARMBit, Feature_HasV8Bit, Feature_HasV8_1aBit, }, |
| 17386 | {Feature_IsThumbBit, Feature_HasAcquireReleaseBit, Feature_HasV7ClrexBit, }, |
| 17387 | {Feature_IsThumbBit, Feature_HasV5TBit, Feature_IsNotMClassBit, }, |
| 17388 | {Feature_IsThumb2Bit, Feature_HasV7Bit, Feature_HasMPBit, }, |
| 17389 | {Feature_IsThumb2Bit, Feature_HasV8Bit, Feature_HasV8_1aBit, }, |
| 17390 | {Feature_IsThumb2Bit, Feature_HasV8_1MMainlineBit, Feature_HasLOBBit, }, |
| 17391 | {Feature_IsThumb2Bit, Feature_HasV8_1MMainlineBit, Feature_HasPACBTIBit, }, |
| 17392 | {Feature_IsThumbBit, Feature_HasAcquireReleaseBit, Feature_HasV7ClrexBit, Feature_IsNotMClassBit, }, |
| 17393 | }; |
| 17394 | static constexpr uint8_t RequiredFeaturesRefs[] = { |
| 17395 | CEFBS_None, // PHI = 0 |
| 17396 | CEFBS_None, // INLINEASM = 1 |
| 17397 | CEFBS_None, // INLINEASM_BR = 2 |
| 17398 | CEFBS_None, // CFI_INSTRUCTION = 3 |
| 17399 | CEFBS_None, // EH_LABEL = 4 |
| 17400 | CEFBS_None, // GC_LABEL = 5 |
| 17401 | CEFBS_None, // ANNOTATION_LABEL = 6 |
| 17402 | CEFBS_None, // KILL = 7 |
| 17403 | CEFBS_None, // EXTRACT_SUBREG = 8 |
| 17404 | CEFBS_None, // INSERT_SUBREG = 9 |
| 17405 | CEFBS_None, // IMPLICIT_DEF = 10 |
| 17406 | CEFBS_None, // INIT_UNDEF = 11 |
| 17407 | CEFBS_None, // SUBREG_TO_REG = 12 |
| 17408 | CEFBS_None, // COPY_TO_REGCLASS = 13 |
| 17409 | CEFBS_None, // DBG_VALUE = 14 |
| 17410 | CEFBS_None, // DBG_VALUE_LIST = 15 |
| 17411 | CEFBS_None, // DBG_INSTR_REF = 16 |
| 17412 | CEFBS_None, // DBG_PHI = 17 |
| 17413 | CEFBS_None, // DBG_LABEL = 18 |
| 17414 | CEFBS_None, // REG_SEQUENCE = 19 |
| 17415 | CEFBS_None, // COPY = 20 |
| 17416 | CEFBS_None, // BUNDLE = 21 |
| 17417 | CEFBS_None, // LIFETIME_START = 22 |
| 17418 | CEFBS_None, // LIFETIME_END = 23 |
| 17419 | CEFBS_None, // PSEUDO_PROBE = 24 |
| 17420 | CEFBS_None, // ARITH_FENCE = 25 |
| 17421 | CEFBS_None, // STACKMAP = 26 |
| 17422 | CEFBS_None, // FENTRY_CALL = 27 |
| 17423 | CEFBS_None, // PATCHPOINT = 28 |
| 17424 | CEFBS_None, // LOAD_STACK_GUARD = 29 |
| 17425 | CEFBS_None, // PREALLOCATED_SETUP = 30 |
| 17426 | CEFBS_None, // PREALLOCATED_ARG = 31 |
| 17427 | CEFBS_None, // STATEPOINT = 32 |
| 17428 | CEFBS_None, // LOCAL_ESCAPE = 33 |
| 17429 | CEFBS_None, // FAULTING_OP = 34 |
| 17430 | CEFBS_None, // PATCHABLE_OP = 35 |
| 17431 | CEFBS_None, // PATCHABLE_FUNCTION_ENTER = 36 |
| 17432 | CEFBS_None, // PATCHABLE_RET = 37 |
| 17433 | CEFBS_None, // PATCHABLE_FUNCTION_EXIT = 38 |
| 17434 | CEFBS_None, // PATCHABLE_TAIL_CALL = 39 |
| 17435 | CEFBS_None, // PATCHABLE_EVENT_CALL = 40 |
| 17436 | CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL = 41 |
| 17437 | CEFBS_None, // ICALL_BRANCH_FUNNEL = 42 |
| 17438 | CEFBS_None, // FAKE_USE = 43 |
| 17439 | CEFBS_None, // MEMBARRIER = 44 |
| 17440 | CEFBS_None, // JUMP_TABLE_DEBUG_INFO = 45 |
| 17441 | CEFBS_None, // CONVERGENCECTRL_ENTRY = 46 |
| 17442 | CEFBS_None, // CONVERGENCECTRL_ANCHOR = 47 |
| 17443 | CEFBS_None, // CONVERGENCECTRL_LOOP = 48 |
| 17444 | CEFBS_None, // CONVERGENCECTRL_GLUE = 49 |
| 17445 | CEFBS_None, // G_ASSERT_SEXT = 50 |
| 17446 | CEFBS_None, // G_ASSERT_ZEXT = 51 |
| 17447 | CEFBS_None, // G_ASSERT_ALIGN = 52 |
| 17448 | CEFBS_None, // G_ADD = 53 |
| 17449 | CEFBS_None, // G_SUB = 54 |
| 17450 | CEFBS_None, // G_MUL = 55 |
| 17451 | CEFBS_None, // G_SDIV = 56 |
| 17452 | CEFBS_None, // G_UDIV = 57 |
| 17453 | CEFBS_None, // G_SREM = 58 |
| 17454 | CEFBS_None, // G_UREM = 59 |
| 17455 | CEFBS_None, // G_SDIVREM = 60 |
| 17456 | CEFBS_None, // G_UDIVREM = 61 |
| 17457 | CEFBS_None, // G_AND = 62 |
| 17458 | CEFBS_None, // G_OR = 63 |
| 17459 | CEFBS_None, // G_XOR = 64 |
| 17460 | CEFBS_None, // G_ABDS = 65 |
| 17461 | CEFBS_None, // G_ABDU = 66 |
| 17462 | CEFBS_None, // G_IMPLICIT_DEF = 67 |
| 17463 | CEFBS_None, // G_PHI = 68 |
| 17464 | CEFBS_None, // G_FRAME_INDEX = 69 |
| 17465 | CEFBS_None, // G_GLOBAL_VALUE = 70 |
| 17466 | CEFBS_None, // G_PTRAUTH_GLOBAL_VALUE = 71 |
| 17467 | CEFBS_None, // G_CONSTANT_POOL = 72 |
| 17468 | CEFBS_None, // G_EXTRACT = 73 |
| 17469 | CEFBS_None, // G_UNMERGE_VALUES = 74 |
| 17470 | CEFBS_None, // G_INSERT = 75 |
| 17471 | CEFBS_None, // G_MERGE_VALUES = 76 |
| 17472 | CEFBS_None, // G_BUILD_VECTOR = 77 |
| 17473 | CEFBS_None, // G_BUILD_VECTOR_TRUNC = 78 |
| 17474 | CEFBS_None, // G_CONCAT_VECTORS = 79 |
| 17475 | CEFBS_None, // G_PTRTOINT = 80 |
| 17476 | CEFBS_None, // G_INTTOPTR = 81 |
| 17477 | CEFBS_None, // G_BITCAST = 82 |
| 17478 | CEFBS_None, // G_FREEZE = 83 |
| 17479 | CEFBS_None, // G_CONSTANT_FOLD_BARRIER = 84 |
| 17480 | CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND = 85 |
| 17481 | CEFBS_None, // G_INTRINSIC_TRUNC = 86 |
| 17482 | CEFBS_None, // G_INTRINSIC_ROUND = 87 |
| 17483 | CEFBS_None, // G_INTRINSIC_LRINT = 88 |
| 17484 | CEFBS_None, // G_INTRINSIC_LLRINT = 89 |
| 17485 | CEFBS_None, // G_INTRINSIC_ROUNDEVEN = 90 |
| 17486 | CEFBS_None, // G_READCYCLECOUNTER = 91 |
| 17487 | CEFBS_None, // G_READSTEADYCOUNTER = 92 |
| 17488 | CEFBS_None, // G_LOAD = 93 |
| 17489 | CEFBS_None, // G_SEXTLOAD = 94 |
| 17490 | CEFBS_None, // G_ZEXTLOAD = 95 |
| 17491 | CEFBS_None, // G_INDEXED_LOAD = 96 |
| 17492 | CEFBS_None, // G_INDEXED_SEXTLOAD = 97 |
| 17493 | CEFBS_None, // G_INDEXED_ZEXTLOAD = 98 |
| 17494 | CEFBS_None, // G_STORE = 99 |
| 17495 | CEFBS_None, // G_INDEXED_STORE = 100 |
| 17496 | CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS = 101 |
| 17497 | CEFBS_None, // G_ATOMIC_CMPXCHG = 102 |
| 17498 | CEFBS_None, // G_ATOMICRMW_XCHG = 103 |
| 17499 | CEFBS_None, // G_ATOMICRMW_ADD = 104 |
| 17500 | CEFBS_None, // G_ATOMICRMW_SUB = 105 |
| 17501 | CEFBS_None, // G_ATOMICRMW_AND = 106 |
| 17502 | CEFBS_None, // G_ATOMICRMW_NAND = 107 |
| 17503 | CEFBS_None, // G_ATOMICRMW_OR = 108 |
| 17504 | CEFBS_None, // G_ATOMICRMW_XOR = 109 |
| 17505 | CEFBS_None, // G_ATOMICRMW_MAX = 110 |
| 17506 | CEFBS_None, // G_ATOMICRMW_MIN = 111 |
| 17507 | CEFBS_None, // G_ATOMICRMW_UMAX = 112 |
| 17508 | CEFBS_None, // G_ATOMICRMW_UMIN = 113 |
| 17509 | CEFBS_None, // G_ATOMICRMW_FADD = 114 |
| 17510 | CEFBS_None, // G_ATOMICRMW_FSUB = 115 |
| 17511 | CEFBS_None, // G_ATOMICRMW_FMAX = 116 |
| 17512 | CEFBS_None, // G_ATOMICRMW_FMIN = 117 |
| 17513 | CEFBS_None, // G_ATOMICRMW_FMAXIMUM = 118 |
| 17514 | CEFBS_None, // G_ATOMICRMW_FMINIMUM = 119 |
| 17515 | CEFBS_None, // G_ATOMICRMW_UINC_WRAP = 120 |
| 17516 | CEFBS_None, // G_ATOMICRMW_UDEC_WRAP = 121 |
| 17517 | CEFBS_None, // G_ATOMICRMW_USUB_COND = 122 |
| 17518 | CEFBS_None, // G_ATOMICRMW_USUB_SAT = 123 |
| 17519 | CEFBS_None, // G_FENCE = 124 |
| 17520 | CEFBS_None, // G_PREFETCH = 125 |
| 17521 | CEFBS_None, // G_BRCOND = 126 |
| 17522 | CEFBS_None, // G_BRINDIRECT = 127 |
| 17523 | CEFBS_None, // G_INVOKE_REGION_START = 128 |
| 17524 | CEFBS_None, // G_INTRINSIC = 129 |
| 17525 | CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS = 130 |
| 17526 | CEFBS_None, // G_INTRINSIC_CONVERGENT = 131 |
| 17527 | CEFBS_None, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 132 |
| 17528 | CEFBS_None, // G_ANYEXT = 133 |
| 17529 | CEFBS_None, // G_TRUNC = 134 |
| 17530 | CEFBS_None, // G_CONSTANT = 135 |
| 17531 | CEFBS_None, // G_FCONSTANT = 136 |
| 17532 | CEFBS_None, // G_VASTART = 137 |
| 17533 | CEFBS_None, // G_VAARG = 138 |
| 17534 | CEFBS_None, // G_SEXT = 139 |
| 17535 | CEFBS_None, // G_SEXT_INREG = 140 |
| 17536 | CEFBS_None, // G_ZEXT = 141 |
| 17537 | CEFBS_None, // G_SHL = 142 |
| 17538 | CEFBS_None, // G_LSHR = 143 |
| 17539 | CEFBS_None, // G_ASHR = 144 |
| 17540 | CEFBS_None, // G_FSHL = 145 |
| 17541 | CEFBS_None, // G_FSHR = 146 |
| 17542 | CEFBS_None, // G_ROTR = 147 |
| 17543 | CEFBS_None, // G_ROTL = 148 |
| 17544 | CEFBS_None, // G_ICMP = 149 |
| 17545 | CEFBS_None, // G_FCMP = 150 |
| 17546 | CEFBS_None, // G_SCMP = 151 |
| 17547 | CEFBS_None, // G_UCMP = 152 |
| 17548 | CEFBS_None, // G_SELECT = 153 |
| 17549 | CEFBS_None, // G_UADDO = 154 |
| 17550 | CEFBS_None, // G_UADDE = 155 |
| 17551 | CEFBS_None, // G_USUBO = 156 |
| 17552 | CEFBS_None, // G_USUBE = 157 |
| 17553 | CEFBS_None, // G_SADDO = 158 |
| 17554 | CEFBS_None, // G_SADDE = 159 |
| 17555 | CEFBS_None, // G_SSUBO = 160 |
| 17556 | CEFBS_None, // G_SSUBE = 161 |
| 17557 | CEFBS_None, // G_UMULO = 162 |
| 17558 | CEFBS_None, // G_SMULO = 163 |
| 17559 | CEFBS_None, // G_UMULH = 164 |
| 17560 | CEFBS_None, // G_SMULH = 165 |
| 17561 | CEFBS_None, // G_UADDSAT = 166 |
| 17562 | CEFBS_None, // G_SADDSAT = 167 |
| 17563 | CEFBS_None, // G_USUBSAT = 168 |
| 17564 | CEFBS_None, // G_SSUBSAT = 169 |
| 17565 | CEFBS_None, // G_USHLSAT = 170 |
| 17566 | CEFBS_None, // G_SSHLSAT = 171 |
| 17567 | CEFBS_None, // G_SMULFIX = 172 |
| 17568 | CEFBS_None, // G_UMULFIX = 173 |
| 17569 | CEFBS_None, // G_SMULFIXSAT = 174 |
| 17570 | CEFBS_None, // G_UMULFIXSAT = 175 |
| 17571 | CEFBS_None, // G_SDIVFIX = 176 |
| 17572 | CEFBS_None, // G_UDIVFIX = 177 |
| 17573 | CEFBS_None, // G_SDIVFIXSAT = 178 |
| 17574 | CEFBS_None, // G_UDIVFIXSAT = 179 |
| 17575 | CEFBS_None, // G_FADD = 180 |
| 17576 | CEFBS_None, // G_FSUB = 181 |
| 17577 | CEFBS_None, // G_FMUL = 182 |
| 17578 | CEFBS_None, // G_FMA = 183 |
| 17579 | CEFBS_None, // G_FMAD = 184 |
| 17580 | CEFBS_None, // G_FDIV = 185 |
| 17581 | CEFBS_None, // G_FREM = 186 |
| 17582 | CEFBS_None, // G_FPOW = 187 |
| 17583 | CEFBS_None, // G_FPOWI = 188 |
| 17584 | CEFBS_None, // G_FEXP = 189 |
| 17585 | CEFBS_None, // G_FEXP2 = 190 |
| 17586 | CEFBS_None, // G_FEXP10 = 191 |
| 17587 | CEFBS_None, // G_FLOG = 192 |
| 17588 | CEFBS_None, // G_FLOG2 = 193 |
| 17589 | CEFBS_None, // G_FLOG10 = 194 |
| 17590 | CEFBS_None, // G_FLDEXP = 195 |
| 17591 | CEFBS_None, // G_FFREXP = 196 |
| 17592 | CEFBS_None, // G_FNEG = 197 |
| 17593 | CEFBS_None, // G_FPEXT = 198 |
| 17594 | CEFBS_None, // G_FPTRUNC = 199 |
| 17595 | CEFBS_None, // G_FPTOSI = 200 |
| 17596 | CEFBS_None, // G_FPTOUI = 201 |
| 17597 | CEFBS_None, // G_SITOFP = 202 |
| 17598 | CEFBS_None, // G_UITOFP = 203 |
| 17599 | CEFBS_None, // G_FPTOSI_SAT = 204 |
| 17600 | CEFBS_None, // G_FPTOUI_SAT = 205 |
| 17601 | CEFBS_None, // G_FABS = 206 |
| 17602 | CEFBS_None, // G_FCOPYSIGN = 207 |
| 17603 | CEFBS_None, // G_IS_FPCLASS = 208 |
| 17604 | CEFBS_None, // G_FCANONICALIZE = 209 |
| 17605 | CEFBS_None, // G_FMINNUM = 210 |
| 17606 | CEFBS_None, // G_FMAXNUM = 211 |
| 17607 | CEFBS_None, // G_FMINNUM_IEEE = 212 |
| 17608 | CEFBS_None, // G_FMAXNUM_IEEE = 213 |
| 17609 | CEFBS_None, // G_FMINIMUM = 214 |
| 17610 | CEFBS_None, // G_FMAXIMUM = 215 |
| 17611 | CEFBS_None, // G_FMINIMUMNUM = 216 |
| 17612 | CEFBS_None, // G_FMAXIMUMNUM = 217 |
| 17613 | CEFBS_None, // G_GET_FPENV = 218 |
| 17614 | CEFBS_None, // G_SET_FPENV = 219 |
| 17615 | CEFBS_None, // G_RESET_FPENV = 220 |
| 17616 | CEFBS_None, // G_GET_FPMODE = 221 |
| 17617 | CEFBS_None, // G_SET_FPMODE = 222 |
| 17618 | CEFBS_None, // G_RESET_FPMODE = 223 |
| 17619 | CEFBS_None, // G_PTR_ADD = 224 |
| 17620 | CEFBS_None, // G_PTRMASK = 225 |
| 17621 | CEFBS_None, // G_SMIN = 226 |
| 17622 | CEFBS_None, // G_SMAX = 227 |
| 17623 | CEFBS_None, // G_UMIN = 228 |
| 17624 | CEFBS_None, // G_UMAX = 229 |
| 17625 | CEFBS_None, // G_ABS = 230 |
| 17626 | CEFBS_None, // G_LROUND = 231 |
| 17627 | CEFBS_None, // G_LLROUND = 232 |
| 17628 | CEFBS_None, // G_BR = 233 |
| 17629 | CEFBS_None, // G_BRJT = 234 |
| 17630 | CEFBS_None, // G_VSCALE = 235 |
| 17631 | CEFBS_None, // G_INSERT_SUBVECTOR = 236 |
| 17632 | CEFBS_None, // G_EXTRACT_SUBVECTOR = 237 |
| 17633 | CEFBS_None, // G_INSERT_VECTOR_ELT = 238 |
| 17634 | CEFBS_None, // G_EXTRACT_VECTOR_ELT = 239 |
| 17635 | CEFBS_None, // G_SHUFFLE_VECTOR = 240 |
| 17636 | CEFBS_None, // G_SPLAT_VECTOR = 241 |
| 17637 | CEFBS_None, // G_STEP_VECTOR = 242 |
| 17638 | CEFBS_None, // G_VECTOR_COMPRESS = 243 |
| 17639 | CEFBS_None, // G_CTTZ = 244 |
| 17640 | CEFBS_None, // G_CTTZ_ZERO_UNDEF = 245 |
| 17641 | CEFBS_None, // G_CTLZ = 246 |
| 17642 | CEFBS_None, // G_CTLZ_ZERO_UNDEF = 247 |
| 17643 | CEFBS_None, // G_CTPOP = 248 |
| 17644 | CEFBS_None, // G_BSWAP = 249 |
| 17645 | CEFBS_None, // G_BITREVERSE = 250 |
| 17646 | CEFBS_None, // G_FCEIL = 251 |
| 17647 | CEFBS_None, // G_FCOS = 252 |
| 17648 | CEFBS_None, // G_FSIN = 253 |
| 17649 | CEFBS_None, // G_FSINCOS = 254 |
| 17650 | CEFBS_None, // G_FTAN = 255 |
| 17651 | CEFBS_None, // G_FACOS = 256 |
| 17652 | CEFBS_None, // G_FASIN = 257 |
| 17653 | CEFBS_None, // G_FATAN = 258 |
| 17654 | CEFBS_None, // G_FATAN2 = 259 |
| 17655 | CEFBS_None, // G_FCOSH = 260 |
| 17656 | CEFBS_None, // G_FSINH = 261 |
| 17657 | CEFBS_None, // G_FTANH = 262 |
| 17658 | CEFBS_None, // G_FSQRT = 263 |
| 17659 | CEFBS_None, // G_FFLOOR = 264 |
| 17660 | CEFBS_None, // G_FRINT = 265 |
| 17661 | CEFBS_None, // G_FNEARBYINT = 266 |
| 17662 | CEFBS_None, // G_ADDRSPACE_CAST = 267 |
| 17663 | CEFBS_None, // G_BLOCK_ADDR = 268 |
| 17664 | CEFBS_None, // G_JUMP_TABLE = 269 |
| 17665 | CEFBS_None, // G_DYN_STACKALLOC = 270 |
| 17666 | CEFBS_None, // G_STACKSAVE = 271 |
| 17667 | CEFBS_None, // G_STACKRESTORE = 272 |
| 17668 | CEFBS_None, // G_STRICT_FADD = 273 |
| 17669 | CEFBS_None, // G_STRICT_FSUB = 274 |
| 17670 | CEFBS_None, // G_STRICT_FMUL = 275 |
| 17671 | CEFBS_None, // G_STRICT_FDIV = 276 |
| 17672 | CEFBS_None, // G_STRICT_FREM = 277 |
| 17673 | CEFBS_None, // G_STRICT_FMA = 278 |
| 17674 | CEFBS_None, // G_STRICT_FSQRT = 279 |
| 17675 | CEFBS_None, // G_STRICT_FLDEXP = 280 |
| 17676 | CEFBS_None, // G_READ_REGISTER = 281 |
| 17677 | CEFBS_None, // G_WRITE_REGISTER = 282 |
| 17678 | CEFBS_None, // G_MEMCPY = 283 |
| 17679 | CEFBS_None, // G_MEMCPY_INLINE = 284 |
| 17680 | CEFBS_None, // G_MEMMOVE = 285 |
| 17681 | CEFBS_None, // G_MEMSET = 286 |
| 17682 | CEFBS_None, // G_BZERO = 287 |
| 17683 | CEFBS_None, // G_TRAP = 288 |
| 17684 | CEFBS_None, // G_DEBUGTRAP = 289 |
| 17685 | CEFBS_None, // G_UBSANTRAP = 290 |
| 17686 | CEFBS_None, // G_VECREDUCE_SEQ_FADD = 291 |
| 17687 | CEFBS_None, // G_VECREDUCE_SEQ_FMUL = 292 |
| 17688 | CEFBS_None, // G_VECREDUCE_FADD = 293 |
| 17689 | CEFBS_None, // G_VECREDUCE_FMUL = 294 |
| 17690 | CEFBS_None, // G_VECREDUCE_FMAX = 295 |
| 17691 | CEFBS_None, // G_VECREDUCE_FMIN = 296 |
| 17692 | CEFBS_None, // G_VECREDUCE_FMAXIMUM = 297 |
| 17693 | CEFBS_None, // G_VECREDUCE_FMINIMUM = 298 |
| 17694 | CEFBS_None, // G_VECREDUCE_ADD = 299 |
| 17695 | CEFBS_None, // G_VECREDUCE_MUL = 300 |
| 17696 | CEFBS_None, // G_VECREDUCE_AND = 301 |
| 17697 | CEFBS_None, // G_VECREDUCE_OR = 302 |
| 17698 | CEFBS_None, // G_VECREDUCE_XOR = 303 |
| 17699 | CEFBS_None, // G_VECREDUCE_SMAX = 304 |
| 17700 | CEFBS_None, // G_VECREDUCE_SMIN = 305 |
| 17701 | CEFBS_None, // G_VECREDUCE_UMAX = 306 |
| 17702 | CEFBS_None, // G_VECREDUCE_UMIN = 307 |
| 17703 | CEFBS_None, // G_SBFX = 308 |
| 17704 | CEFBS_None, // G_UBFX = 309 |
| 17705 | CEFBS_IsARM, // ABS = 310 |
| 17706 | CEFBS_IsARM, // ADDSri = 311 |
| 17707 | CEFBS_IsARM, // ADDSrr = 312 |
| 17708 | CEFBS_IsARM, // ADDSrsi = 313 |
| 17709 | CEFBS_IsARM, // ADDSrsr = 314 |
| 17710 | CEFBS_None, // ADJCALLSTACKDOWN = 315 |
| 17711 | CEFBS_None, // ADJCALLSTACKUP = 316 |
| 17712 | CEFBS_IsARM, // ASRi = 317 |
| 17713 | CEFBS_IsARM, // ASRr = 318 |
| 17714 | CEFBS_IsARM, // ASRs1 = 319 |
| 17715 | CEFBS_IsARM, // B = 320 |
| 17716 | CEFBS_None, // BCCZi64 = 321 |
| 17717 | CEFBS_None, // BCCi64 = 322 |
| 17718 | CEFBS_IsARM_HasV5T, // BLX_noip = 323 |
| 17719 | CEFBS_IsARM_HasV5T, // BLX_pred_noip = 324 |
| 17720 | CEFBS_IsARM, // BL_PUSHLR = 325 |
| 17721 | CEFBS_IsARM, // BMOVPCB_CALL = 326 |
| 17722 | CEFBS_IsARM, // BMOVPCRX_CALL = 327 |
| 17723 | CEFBS_IsARM, // BR_JTadd = 328 |
| 17724 | CEFBS_IsARM, // BR_JTm_i12 = 329 |
| 17725 | CEFBS_IsARM, // BR_JTm_rs = 330 |
| 17726 | CEFBS_IsARM, // BR_JTr = 331 |
| 17727 | CEFBS_IsARM_HasV4T, // BX_CALL = 332 |
| 17728 | CEFBS_None, // CMP_SWAP_16 = 333 |
| 17729 | CEFBS_None, // CMP_SWAP_32 = 334 |
| 17730 | CEFBS_None, // CMP_SWAP_64 = 335 |
| 17731 | CEFBS_None, // CMP_SWAP_8 = 336 |
| 17732 | CEFBS_None, // CONSTPOOL_ENTRY = 337 |
| 17733 | CEFBS_None, // COPY_STRUCT_BYVAL_I32 = 338 |
| 17734 | CEFBS_IsARM, // ITasm = 339 |
| 17735 | CEFBS_None, // Int_eh_sjlj_dispatchsetup = 340 |
| 17736 | CEFBS_IsARM, // Int_eh_sjlj_longjmp = 341 |
| 17737 | CEFBS_IsARM_HasVFP2, // Int_eh_sjlj_setjmp = 342 |
| 17738 | CEFBS_IsARM, // Int_eh_sjlj_setjmp_nofp = 343 |
| 17739 | CEFBS_None, // Int_eh_sjlj_setup_dispatch = 344 |
| 17740 | CEFBS_None, // JUMPTABLE_ADDRS = 345 |
| 17741 | CEFBS_None, // JUMPTABLE_INSTS = 346 |
| 17742 | CEFBS_None, // JUMPTABLE_TBB = 347 |
| 17743 | CEFBS_None, // JUMPTABLE_TBH = 348 |
| 17744 | CEFBS_IsARM, // LDMIA_RET = 349 |
| 17745 | CEFBS_IsARM, // LDRBT_POST = 350 |
| 17746 | CEFBS_IsARM, // LDRConstPool = 351 |
| 17747 | CEFBS_IsARM, // LDRHTii = 352 |
| 17748 | CEFBS_IsARM, // LDRLIT_ga_abs = 353 |
| 17749 | CEFBS_IsARM, // LDRLIT_ga_pcrel = 354 |
| 17750 | CEFBS_IsARM, // LDRLIT_ga_pcrel_ldr = 355 |
| 17751 | CEFBS_IsARM, // LDRSBTii = 356 |
| 17752 | CEFBS_IsARM, // LDRSHTii = 357 |
| 17753 | CEFBS_IsARM, // LDRT_POST = 358 |
| 17754 | CEFBS_IsARM, // LEApcrel = 359 |
| 17755 | CEFBS_IsARM, // LEApcrelJT = 360 |
| 17756 | CEFBS_IsARM_HasV5TE, // LOADDUAL = 361 |
| 17757 | CEFBS_IsARM, // LSLi = 362 |
| 17758 | CEFBS_IsARM, // LSLr = 363 |
| 17759 | CEFBS_IsARM, // LSRi = 364 |
| 17760 | CEFBS_IsARM, // LSRr = 365 |
| 17761 | CEFBS_IsARM, // LSRs1 = 366 |
| 17762 | CEFBS_None, // MEMCPY = 367 |
| 17763 | CEFBS_IsARM, // MLAv5 = 368 |
| 17764 | CEFBS_IsARM, // MOVCCi = 369 |
| 17765 | CEFBS_IsARM_HasV6T2, // MOVCCi16 = 370 |
| 17766 | CEFBS_IsARM_HasV6T2, // MOVCCi32imm = 371 |
| 17767 | CEFBS_IsARM, // MOVCCr = 372 |
| 17768 | CEFBS_IsARM, // MOVCCsi = 373 |
| 17769 | CEFBS_IsARM, // MOVCCsr = 374 |
| 17770 | CEFBS_IsARM, // MOVPCRX = 375 |
| 17771 | CEFBS_None, // MOVTi16_ga_pcrel = 376 |
| 17772 | CEFBS_IsARM, // MOV_ga_pcrel = 377 |
| 17773 | CEFBS_IsARM, // MOV_ga_pcrel_ldr = 378 |
| 17774 | CEFBS_None, // MOVi16_ga_pcrel = 379 |
| 17775 | CEFBS_IsARM, // MOVi32imm = 380 |
| 17776 | CEFBS_HasMVEInt, // MQPRCopy = 381 |
| 17777 | CEFBS_HasMVEInt, // MQQPRLoad = 382 |
| 17778 | CEFBS_HasMVEInt, // MQQPRStore = 383 |
| 17779 | CEFBS_HasMVEInt, // MQQQQPRLoad = 384 |
| 17780 | CEFBS_HasMVEInt, // MQQQQPRStore = 385 |
| 17781 | CEFBS_IsARM, // MULv5 = 386 |
| 17782 | CEFBS_None, // MVE_MEMCPYLOOPINST = 387 |
| 17783 | CEFBS_None, // MVE_MEMSETLOOPINST = 388 |
| 17784 | CEFBS_IsARM, // MVNCCi = 389 |
| 17785 | CEFBS_IsARM, // PICADD = 390 |
| 17786 | CEFBS_IsARM, // PICLDR = 391 |
| 17787 | CEFBS_IsARM, // PICLDRB = 392 |
| 17788 | CEFBS_IsARM, // PICLDRH = 393 |
| 17789 | CEFBS_IsARM, // PICLDRSB = 394 |
| 17790 | CEFBS_IsARM, // PICLDRSH = 395 |
| 17791 | CEFBS_IsARM, // PICSTR = 396 |
| 17792 | CEFBS_IsARM, // PICSTRB = 397 |
| 17793 | CEFBS_IsARM, // PICSTRH = 398 |
| 17794 | CEFBS_IsARM, // RORi = 399 |
| 17795 | CEFBS_IsARM, // RORr = 400 |
| 17796 | CEFBS_IsARM, // RRX = 401 |
| 17797 | CEFBS_IsARM, // RRXi = 402 |
| 17798 | CEFBS_IsARM, // RSBSri = 403 |
| 17799 | CEFBS_IsARM, // RSBSrsi = 404 |
| 17800 | CEFBS_IsARM, // RSBSrsr = 405 |
| 17801 | CEFBS_None, // SEH_EpilogEnd = 406 |
| 17802 | CEFBS_None, // SEH_EpilogStart = 407 |
| 17803 | CEFBS_None, // SEH_Nop = 408 |
| 17804 | CEFBS_None, // SEH_Nop_Ret = 409 |
| 17805 | CEFBS_None, // SEH_PrologEnd = 410 |
| 17806 | CEFBS_None, // SEH_SaveFRegs = 411 |
| 17807 | CEFBS_None, // SEH_SaveLR = 412 |
| 17808 | CEFBS_None, // SEH_SaveRegs = 413 |
| 17809 | CEFBS_None, // SEH_SaveRegs_Ret = 414 |
| 17810 | CEFBS_None, // SEH_SaveSP = 415 |
| 17811 | CEFBS_None, // SEH_StackAlloc = 416 |
| 17812 | CEFBS_IsARM, // SMLALv5 = 417 |
| 17813 | CEFBS_IsARM, // SMULLv5 = 418 |
| 17814 | CEFBS_None, // SPACE = 419 |
| 17815 | CEFBS_IsARM_HasV5TE, // STOREDUAL = 420 |
| 17816 | CEFBS_IsARM, // STRBT_POST = 421 |
| 17817 | CEFBS_IsARM, // STRBi_preidx = 422 |
| 17818 | CEFBS_IsARM, // STRBr_preidx = 423 |
| 17819 | CEFBS_IsARM, // STRH_preidx = 424 |
| 17820 | CEFBS_IsARM, // STRT_POST = 425 |
| 17821 | CEFBS_IsARM, // STRi_preidx = 426 |
| 17822 | CEFBS_IsARM, // STRr_preidx = 427 |
| 17823 | CEFBS_IsARM, // SUBS_PC_LR = 428 |
| 17824 | CEFBS_IsARM, // SUBSri = 429 |
| 17825 | CEFBS_IsARM, // SUBSrr = 430 |
| 17826 | CEFBS_IsARM, // SUBSrsi = 431 |
| 17827 | CEFBS_IsARM, // SUBSrsr = 432 |
| 17828 | CEFBS_None, // SpeculationBarrierISBDSBEndBB = 433 |
| 17829 | CEFBS_None, // SpeculationBarrierSBEndBB = 434 |
| 17830 | CEFBS_IsARM, // TAILJMPd = 435 |
| 17831 | CEFBS_IsARM_HasV4T, // TAILJMPr = 436 |
| 17832 | CEFBS_IsARM, // TAILJMPr4 = 437 |
| 17833 | CEFBS_None, // TCRETURNdi = 438 |
| 17834 | CEFBS_None, // TCRETURNri = 439 |
| 17835 | CEFBS_None, // TCRETURNrinotr12 = 440 |
| 17836 | CEFBS_IsARM, // TPsoft = 441 |
| 17837 | CEFBS_IsARM, // UMLALv5 = 442 |
| 17838 | CEFBS_IsARM, // UMULLv5 = 443 |
| 17839 | CEFBS_HasNEON, // VLD1LNdAsm_16 = 444 |
| 17840 | CEFBS_HasNEON, // VLD1LNdAsm_32 = 445 |
| 17841 | CEFBS_HasNEON, // VLD1LNdAsm_8 = 446 |
| 17842 | CEFBS_HasNEON, // VLD1LNdWB_fixed_Asm_16 = 447 |
| 17843 | CEFBS_HasNEON, // VLD1LNdWB_fixed_Asm_32 = 448 |
| 17844 | CEFBS_HasNEON, // VLD1LNdWB_fixed_Asm_8 = 449 |
| 17845 | CEFBS_HasNEON, // VLD1LNdWB_register_Asm_16 = 450 |
| 17846 | CEFBS_HasNEON, // VLD1LNdWB_register_Asm_32 = 451 |
| 17847 | CEFBS_HasNEON, // VLD1LNdWB_register_Asm_8 = 452 |
| 17848 | CEFBS_HasNEON, // VLD2LNdAsm_16 = 453 |
| 17849 | CEFBS_HasNEON, // VLD2LNdAsm_32 = 454 |
| 17850 | CEFBS_HasNEON, // VLD2LNdAsm_8 = 455 |
| 17851 | CEFBS_HasNEON, // VLD2LNdWB_fixed_Asm_16 = 456 |
| 17852 | CEFBS_HasNEON, // VLD2LNdWB_fixed_Asm_32 = 457 |
| 17853 | CEFBS_HasNEON, // VLD2LNdWB_fixed_Asm_8 = 458 |
| 17854 | CEFBS_HasNEON, // VLD2LNdWB_register_Asm_16 = 459 |
| 17855 | CEFBS_HasNEON, // VLD2LNdWB_register_Asm_32 = 460 |
| 17856 | CEFBS_HasNEON, // VLD2LNdWB_register_Asm_8 = 461 |
| 17857 | CEFBS_HasNEON, // VLD2LNqAsm_16 = 462 |
| 17858 | CEFBS_HasNEON, // VLD2LNqAsm_32 = 463 |
| 17859 | CEFBS_HasNEON, // VLD2LNqWB_fixed_Asm_16 = 464 |
| 17860 | CEFBS_HasNEON, // VLD2LNqWB_fixed_Asm_32 = 465 |
| 17861 | CEFBS_HasNEON, // VLD2LNqWB_register_Asm_16 = 466 |
| 17862 | CEFBS_HasNEON, // VLD2LNqWB_register_Asm_32 = 467 |
| 17863 | CEFBS_HasNEON, // VLD3DUPdAsm_16 = 468 |
| 17864 | CEFBS_HasNEON, // VLD3DUPdAsm_32 = 469 |
| 17865 | CEFBS_HasNEON, // VLD3DUPdAsm_8 = 470 |
| 17866 | CEFBS_HasNEON, // VLD3DUPdWB_fixed_Asm_16 = 471 |
| 17867 | CEFBS_HasNEON, // VLD3DUPdWB_fixed_Asm_32 = 472 |
| 17868 | CEFBS_HasNEON, // VLD3DUPdWB_fixed_Asm_8 = 473 |
| 17869 | CEFBS_HasNEON, // VLD3DUPdWB_register_Asm_16 = 474 |
| 17870 | CEFBS_HasNEON, // VLD3DUPdWB_register_Asm_32 = 475 |
| 17871 | CEFBS_HasNEON, // VLD3DUPdWB_register_Asm_8 = 476 |
| 17872 | CEFBS_HasNEON, // VLD3DUPqAsm_16 = 477 |
| 17873 | CEFBS_HasNEON, // VLD3DUPqAsm_32 = 478 |
| 17874 | CEFBS_HasNEON, // VLD3DUPqAsm_8 = 479 |
| 17875 | CEFBS_HasNEON, // VLD3DUPqWB_fixed_Asm_16 = 480 |
| 17876 | CEFBS_HasNEON, // VLD3DUPqWB_fixed_Asm_32 = 481 |
| 17877 | CEFBS_HasNEON, // VLD3DUPqWB_fixed_Asm_8 = 482 |
| 17878 | CEFBS_HasNEON, // VLD3DUPqWB_register_Asm_16 = 483 |
| 17879 | CEFBS_HasNEON, // VLD3DUPqWB_register_Asm_32 = 484 |
| 17880 | CEFBS_HasNEON, // VLD3DUPqWB_register_Asm_8 = 485 |
| 17881 | CEFBS_HasNEON, // VLD3LNdAsm_16 = 486 |
| 17882 | CEFBS_HasNEON, // VLD3LNdAsm_32 = 487 |
| 17883 | CEFBS_HasNEON, // VLD3LNdAsm_8 = 488 |
| 17884 | CEFBS_HasNEON, // VLD3LNdWB_fixed_Asm_16 = 489 |
| 17885 | CEFBS_HasNEON, // VLD3LNdWB_fixed_Asm_32 = 490 |
| 17886 | CEFBS_HasNEON, // VLD3LNdWB_fixed_Asm_8 = 491 |
| 17887 | CEFBS_HasNEON, // VLD3LNdWB_register_Asm_16 = 492 |
| 17888 | CEFBS_HasNEON, // VLD3LNdWB_register_Asm_32 = 493 |
| 17889 | CEFBS_HasNEON, // VLD3LNdWB_register_Asm_8 = 494 |
| 17890 | CEFBS_HasNEON, // VLD3LNqAsm_16 = 495 |
| 17891 | CEFBS_HasNEON, // VLD3LNqAsm_32 = 496 |
| 17892 | CEFBS_HasNEON, // VLD3LNqWB_fixed_Asm_16 = 497 |
| 17893 | CEFBS_HasNEON, // VLD3LNqWB_fixed_Asm_32 = 498 |
| 17894 | CEFBS_HasNEON, // VLD3LNqWB_register_Asm_16 = 499 |
| 17895 | CEFBS_HasNEON, // VLD3LNqWB_register_Asm_32 = 500 |
| 17896 | CEFBS_HasNEON, // VLD3dAsm_16 = 501 |
| 17897 | CEFBS_HasNEON, // VLD3dAsm_32 = 502 |
| 17898 | CEFBS_HasNEON, // VLD3dAsm_8 = 503 |
| 17899 | CEFBS_HasNEON, // VLD3dWB_fixed_Asm_16 = 504 |
| 17900 | CEFBS_HasNEON, // VLD3dWB_fixed_Asm_32 = 505 |
| 17901 | CEFBS_HasNEON, // VLD3dWB_fixed_Asm_8 = 506 |
| 17902 | CEFBS_HasNEON, // VLD3dWB_register_Asm_16 = 507 |
| 17903 | CEFBS_HasNEON, // VLD3dWB_register_Asm_32 = 508 |
| 17904 | CEFBS_HasNEON, // VLD3dWB_register_Asm_8 = 509 |
| 17905 | CEFBS_HasNEON, // VLD3qAsm_16 = 510 |
| 17906 | CEFBS_HasNEON, // VLD3qAsm_32 = 511 |
| 17907 | CEFBS_HasNEON, // VLD3qAsm_8 = 512 |
| 17908 | CEFBS_HasNEON, // VLD3qWB_fixed_Asm_16 = 513 |
| 17909 | CEFBS_HasNEON, // VLD3qWB_fixed_Asm_32 = 514 |
| 17910 | CEFBS_HasNEON, // VLD3qWB_fixed_Asm_8 = 515 |
| 17911 | CEFBS_HasNEON, // VLD3qWB_register_Asm_16 = 516 |
| 17912 | CEFBS_HasNEON, // VLD3qWB_register_Asm_32 = 517 |
| 17913 | CEFBS_HasNEON, // VLD3qWB_register_Asm_8 = 518 |
| 17914 | CEFBS_HasNEON, // VLD4DUPdAsm_16 = 519 |
| 17915 | CEFBS_HasNEON, // VLD4DUPdAsm_32 = 520 |
| 17916 | CEFBS_HasNEON, // VLD4DUPdAsm_8 = 521 |
| 17917 | CEFBS_HasNEON, // VLD4DUPdWB_fixed_Asm_16 = 522 |
| 17918 | CEFBS_HasNEON, // VLD4DUPdWB_fixed_Asm_32 = 523 |
| 17919 | CEFBS_HasNEON, // VLD4DUPdWB_fixed_Asm_8 = 524 |
| 17920 | CEFBS_HasNEON, // VLD4DUPdWB_register_Asm_16 = 525 |
| 17921 | CEFBS_HasNEON, // VLD4DUPdWB_register_Asm_32 = 526 |
| 17922 | CEFBS_HasNEON, // VLD4DUPdWB_register_Asm_8 = 527 |
| 17923 | CEFBS_HasNEON, // VLD4DUPqAsm_16 = 528 |
| 17924 | CEFBS_HasNEON, // VLD4DUPqAsm_32 = 529 |
| 17925 | CEFBS_HasNEON, // VLD4DUPqAsm_8 = 530 |
| 17926 | CEFBS_HasNEON, // VLD4DUPqWB_fixed_Asm_16 = 531 |
| 17927 | CEFBS_HasNEON, // VLD4DUPqWB_fixed_Asm_32 = 532 |
| 17928 | CEFBS_HasNEON, // VLD4DUPqWB_fixed_Asm_8 = 533 |
| 17929 | CEFBS_HasNEON, // VLD4DUPqWB_register_Asm_16 = 534 |
| 17930 | CEFBS_HasNEON, // VLD4DUPqWB_register_Asm_32 = 535 |
| 17931 | CEFBS_HasNEON, // VLD4DUPqWB_register_Asm_8 = 536 |
| 17932 | CEFBS_HasNEON, // VLD4LNdAsm_16 = 537 |
| 17933 | CEFBS_HasNEON, // VLD4LNdAsm_32 = 538 |
| 17934 | CEFBS_HasNEON, // VLD4LNdAsm_8 = 539 |
| 17935 | CEFBS_HasNEON, // VLD4LNdWB_fixed_Asm_16 = 540 |
| 17936 | CEFBS_HasNEON, // VLD4LNdWB_fixed_Asm_32 = 541 |
| 17937 | CEFBS_HasNEON, // VLD4LNdWB_fixed_Asm_8 = 542 |
| 17938 | CEFBS_HasNEON, // VLD4LNdWB_register_Asm_16 = 543 |
| 17939 | CEFBS_HasNEON, // VLD4LNdWB_register_Asm_32 = 544 |
| 17940 | CEFBS_HasNEON, // VLD4LNdWB_register_Asm_8 = 545 |
| 17941 | CEFBS_HasNEON, // VLD4LNqAsm_16 = 546 |
| 17942 | CEFBS_HasNEON, // VLD4LNqAsm_32 = 547 |
| 17943 | CEFBS_HasNEON, // VLD4LNqWB_fixed_Asm_16 = 548 |
| 17944 | CEFBS_HasNEON, // VLD4LNqWB_fixed_Asm_32 = 549 |
| 17945 | CEFBS_HasNEON, // VLD4LNqWB_register_Asm_16 = 550 |
| 17946 | CEFBS_HasNEON, // VLD4LNqWB_register_Asm_32 = 551 |
| 17947 | CEFBS_HasNEON, // VLD4dAsm_16 = 552 |
| 17948 | CEFBS_HasNEON, // VLD4dAsm_32 = 553 |
| 17949 | CEFBS_HasNEON, // VLD4dAsm_8 = 554 |
| 17950 | CEFBS_HasNEON, // VLD4dWB_fixed_Asm_16 = 555 |
| 17951 | CEFBS_HasNEON, // VLD4dWB_fixed_Asm_32 = 556 |
| 17952 | CEFBS_HasNEON, // VLD4dWB_fixed_Asm_8 = 557 |
| 17953 | CEFBS_HasNEON, // VLD4dWB_register_Asm_16 = 558 |
| 17954 | CEFBS_HasNEON, // VLD4dWB_register_Asm_32 = 559 |
| 17955 | CEFBS_HasNEON, // VLD4dWB_register_Asm_8 = 560 |
| 17956 | CEFBS_HasNEON, // VLD4qAsm_16 = 561 |
| 17957 | CEFBS_HasNEON, // VLD4qAsm_32 = 562 |
| 17958 | CEFBS_HasNEON, // VLD4qAsm_8 = 563 |
| 17959 | CEFBS_HasNEON, // VLD4qWB_fixed_Asm_16 = 564 |
| 17960 | CEFBS_HasNEON, // VLD4qWB_fixed_Asm_32 = 565 |
| 17961 | CEFBS_HasNEON, // VLD4qWB_fixed_Asm_8 = 566 |
| 17962 | CEFBS_HasNEON, // VLD4qWB_register_Asm_16 = 567 |
| 17963 | CEFBS_HasNEON, // VLD4qWB_register_Asm_32 = 568 |
| 17964 | CEFBS_HasNEON, // VLD4qWB_register_Asm_8 = 569 |
| 17965 | CEFBS_None, // VMOVD0 = 570 |
| 17966 | CEFBS_HasFPRegs64, // VMOVDcc = 571 |
| 17967 | CEFBS_HasFPRegs, // VMOVHcc = 572 |
| 17968 | CEFBS_None, // VMOVQ0 = 573 |
| 17969 | CEFBS_HasFPRegs, // VMOVScc = 574 |
| 17970 | CEFBS_HasNEON, // VST1LNdAsm_16 = 575 |
| 17971 | CEFBS_HasNEON, // VST1LNdAsm_32 = 576 |
| 17972 | CEFBS_HasNEON, // VST1LNdAsm_8 = 577 |
| 17973 | CEFBS_HasNEON, // VST1LNdWB_fixed_Asm_16 = 578 |
| 17974 | CEFBS_HasNEON, // VST1LNdWB_fixed_Asm_32 = 579 |
| 17975 | CEFBS_HasNEON, // VST1LNdWB_fixed_Asm_8 = 580 |
| 17976 | CEFBS_HasNEON, // VST1LNdWB_register_Asm_16 = 581 |
| 17977 | CEFBS_HasNEON, // VST1LNdWB_register_Asm_32 = 582 |
| 17978 | CEFBS_HasNEON, // VST1LNdWB_register_Asm_8 = 583 |
| 17979 | CEFBS_HasNEON, // VST2LNdAsm_16 = 584 |
| 17980 | CEFBS_HasNEON, // VST2LNdAsm_32 = 585 |
| 17981 | CEFBS_HasNEON, // VST2LNdAsm_8 = 586 |
| 17982 | CEFBS_HasNEON, // VST2LNdWB_fixed_Asm_16 = 587 |
| 17983 | CEFBS_HasNEON, // VST2LNdWB_fixed_Asm_32 = 588 |
| 17984 | CEFBS_HasNEON, // VST2LNdWB_fixed_Asm_8 = 589 |
| 17985 | CEFBS_HasNEON, // VST2LNdWB_register_Asm_16 = 590 |
| 17986 | CEFBS_HasNEON, // VST2LNdWB_register_Asm_32 = 591 |
| 17987 | CEFBS_HasNEON, // VST2LNdWB_register_Asm_8 = 592 |
| 17988 | CEFBS_HasNEON, // VST2LNqAsm_16 = 593 |
| 17989 | CEFBS_HasNEON, // VST2LNqAsm_32 = 594 |
| 17990 | CEFBS_HasNEON, // VST2LNqWB_fixed_Asm_16 = 595 |
| 17991 | CEFBS_HasNEON, // VST2LNqWB_fixed_Asm_32 = 596 |
| 17992 | CEFBS_HasNEON, // VST2LNqWB_register_Asm_16 = 597 |
| 17993 | CEFBS_HasNEON, // VST2LNqWB_register_Asm_32 = 598 |
| 17994 | CEFBS_HasNEON, // VST3LNdAsm_16 = 599 |
| 17995 | CEFBS_HasNEON, // VST3LNdAsm_32 = 600 |
| 17996 | CEFBS_HasNEON, // VST3LNdAsm_8 = 601 |
| 17997 | CEFBS_HasNEON, // VST3LNdWB_fixed_Asm_16 = 602 |
| 17998 | CEFBS_HasNEON, // VST3LNdWB_fixed_Asm_32 = 603 |
| 17999 | CEFBS_HasNEON, // VST3LNdWB_fixed_Asm_8 = 604 |
| 18000 | CEFBS_HasNEON, // VST3LNdWB_register_Asm_16 = 605 |
| 18001 | CEFBS_HasNEON, // VST3LNdWB_register_Asm_32 = 606 |
| 18002 | CEFBS_HasNEON, // VST3LNdWB_register_Asm_8 = 607 |
| 18003 | CEFBS_HasNEON, // VST3LNqAsm_16 = 608 |
| 18004 | CEFBS_HasNEON, // VST3LNqAsm_32 = 609 |
| 18005 | CEFBS_HasNEON, // VST3LNqWB_fixed_Asm_16 = 610 |
| 18006 | CEFBS_HasNEON, // VST3LNqWB_fixed_Asm_32 = 611 |
| 18007 | CEFBS_HasNEON, // VST3LNqWB_register_Asm_16 = 612 |
| 18008 | CEFBS_HasNEON, // VST3LNqWB_register_Asm_32 = 613 |
| 18009 | CEFBS_HasNEON, // VST3dAsm_16 = 614 |
| 18010 | CEFBS_HasNEON, // VST3dAsm_32 = 615 |
| 18011 | CEFBS_HasNEON, // VST3dAsm_8 = 616 |
| 18012 | CEFBS_HasNEON, // VST3dWB_fixed_Asm_16 = 617 |
| 18013 | CEFBS_HasNEON, // VST3dWB_fixed_Asm_32 = 618 |
| 18014 | CEFBS_HasNEON, // VST3dWB_fixed_Asm_8 = 619 |
| 18015 | CEFBS_HasNEON, // VST3dWB_register_Asm_16 = 620 |
| 18016 | CEFBS_HasNEON, // VST3dWB_register_Asm_32 = 621 |
| 18017 | CEFBS_HasNEON, // VST3dWB_register_Asm_8 = 622 |
| 18018 | CEFBS_HasNEON, // VST3qAsm_16 = 623 |
| 18019 | CEFBS_HasNEON, // VST3qAsm_32 = 624 |
| 18020 | CEFBS_HasNEON, // VST3qAsm_8 = 625 |
| 18021 | CEFBS_HasNEON, // VST3qWB_fixed_Asm_16 = 626 |
| 18022 | CEFBS_HasNEON, // VST3qWB_fixed_Asm_32 = 627 |
| 18023 | CEFBS_HasNEON, // VST3qWB_fixed_Asm_8 = 628 |
| 18024 | CEFBS_HasNEON, // VST3qWB_register_Asm_16 = 629 |
| 18025 | CEFBS_HasNEON, // VST3qWB_register_Asm_32 = 630 |
| 18026 | CEFBS_HasNEON, // VST3qWB_register_Asm_8 = 631 |
| 18027 | CEFBS_HasNEON, // VST4LNdAsm_16 = 632 |
| 18028 | CEFBS_HasNEON, // VST4LNdAsm_32 = 633 |
| 18029 | CEFBS_HasNEON, // VST4LNdAsm_8 = 634 |
| 18030 | CEFBS_HasNEON, // VST4LNdWB_fixed_Asm_16 = 635 |
| 18031 | CEFBS_HasNEON, // VST4LNdWB_fixed_Asm_32 = 636 |
| 18032 | CEFBS_HasNEON, // VST4LNdWB_fixed_Asm_8 = 637 |
| 18033 | CEFBS_HasNEON, // VST4LNdWB_register_Asm_16 = 638 |
| 18034 | CEFBS_HasNEON, // VST4LNdWB_register_Asm_32 = 639 |
| 18035 | CEFBS_HasNEON, // VST4LNdWB_register_Asm_8 = 640 |
| 18036 | CEFBS_HasNEON, // VST4LNqAsm_16 = 641 |
| 18037 | CEFBS_HasNEON, // VST4LNqAsm_32 = 642 |
| 18038 | CEFBS_HasNEON, // VST4LNqWB_fixed_Asm_16 = 643 |
| 18039 | CEFBS_HasNEON, // VST4LNqWB_fixed_Asm_32 = 644 |
| 18040 | CEFBS_HasNEON, // VST4LNqWB_register_Asm_16 = 645 |
| 18041 | CEFBS_HasNEON, // VST4LNqWB_register_Asm_32 = 646 |
| 18042 | CEFBS_HasNEON, // VST4dAsm_16 = 647 |
| 18043 | CEFBS_HasNEON, // VST4dAsm_32 = 648 |
| 18044 | CEFBS_HasNEON, // VST4dAsm_8 = 649 |
| 18045 | CEFBS_HasNEON, // VST4dWB_fixed_Asm_16 = 650 |
| 18046 | CEFBS_HasNEON, // VST4dWB_fixed_Asm_32 = 651 |
| 18047 | CEFBS_HasNEON, // VST4dWB_fixed_Asm_8 = 652 |
| 18048 | CEFBS_HasNEON, // VST4dWB_register_Asm_16 = 653 |
| 18049 | CEFBS_HasNEON, // VST4dWB_register_Asm_32 = 654 |
| 18050 | CEFBS_HasNEON, // VST4dWB_register_Asm_8 = 655 |
| 18051 | CEFBS_HasNEON, // VST4qAsm_16 = 656 |
| 18052 | CEFBS_HasNEON, // VST4qAsm_32 = 657 |
| 18053 | CEFBS_HasNEON, // VST4qAsm_8 = 658 |
| 18054 | CEFBS_HasNEON, // VST4qWB_fixed_Asm_16 = 659 |
| 18055 | CEFBS_HasNEON, // VST4qWB_fixed_Asm_32 = 660 |
| 18056 | CEFBS_HasNEON, // VST4qWB_fixed_Asm_8 = 661 |
| 18057 | CEFBS_HasNEON, // VST4qWB_register_Asm_16 = 662 |
| 18058 | CEFBS_HasNEON, // VST4qWB_register_Asm_32 = 663 |
| 18059 | CEFBS_HasNEON, // VST4qWB_register_Asm_8 = 664 |
| 18060 | CEFBS_None, // WIN__CHKSTK = 665 |
| 18061 | CEFBS_None, // WIN__DBZCHK = 666 |
| 18062 | CEFBS_IsThumb2, // t2ABS = 667 |
| 18063 | CEFBS_IsThumb2, // t2ADDSri = 668 |
| 18064 | CEFBS_IsThumb2, // t2ADDSrr = 669 |
| 18065 | CEFBS_IsThumb2, // t2ADDSrs = 670 |
| 18066 | CEFBS_IsThumb2_HasV8_1MMainline_HasLOB, // t2BF_LabelPseudo = 671 |
| 18067 | CEFBS_IsThumb_HasV8MBaseline, // t2BR_JT = 672 |
| 18068 | CEFBS_IsThumb2, // t2CALL_BTI = 673 |
| 18069 | CEFBS_IsThumb2_HasV8_1MMainline_HasLOB, // t2DoLoopStart = 674 |
| 18070 | CEFBS_IsThumb2_HasV8_1MMainline_HasLOB, // t2DoLoopStartTP = 675 |
| 18071 | CEFBS_IsThumb2, // t2LDMIA_RET = 676 |
| 18072 | CEFBS_IsThumb2, // t2LDRB_OFFSET_imm = 677 |
| 18073 | CEFBS_IsThumb2, // t2LDRB_POST_imm = 678 |
| 18074 | CEFBS_IsThumb2, // t2LDRB_PRE_imm = 679 |
| 18075 | CEFBS_IsThumb2, // t2LDRBpcrel = 680 |
| 18076 | CEFBS_IsThumb2, // t2LDRConstPool = 681 |
| 18077 | CEFBS_IsThumb2, // t2LDRH_OFFSET_imm = 682 |
| 18078 | CEFBS_IsThumb2, // t2LDRH_POST_imm = 683 |
| 18079 | CEFBS_IsThumb2, // t2LDRH_PRE_imm = 684 |
| 18080 | CEFBS_IsThumb2, // t2LDRHpcrel = 685 |
| 18081 | CEFBS_IsThumb_HasV8MBaseline, // t2LDRLIT_ga_pcrel = 686 |
| 18082 | CEFBS_IsThumb2, // t2LDRSB_OFFSET_imm = 687 |
| 18083 | CEFBS_IsThumb2, // t2LDRSB_POST_imm = 688 |
| 18084 | CEFBS_IsThumb2, // t2LDRSB_PRE_imm = 689 |
| 18085 | CEFBS_IsThumb2, // t2LDRSBpcrel = 690 |
| 18086 | CEFBS_IsThumb2, // t2LDRSH_OFFSET_imm = 691 |
| 18087 | CEFBS_IsThumb2, // t2LDRSH_POST_imm = 692 |
| 18088 | CEFBS_IsThumb2, // t2LDRSH_PRE_imm = 693 |
| 18089 | CEFBS_IsThumb2, // t2LDRSHpcrel = 694 |
| 18090 | CEFBS_IsThumb2, // t2LDR_POST_imm = 695 |
| 18091 | CEFBS_IsThumb2, // t2LDR_PRE_imm = 696 |
| 18092 | CEFBS_IsThumb2, // t2LDRpci_pic = 697 |
| 18093 | CEFBS_IsThumb2, // t2LDRpcrel = 698 |
| 18094 | CEFBS_IsThumb2, // t2LEApcrel = 699 |
| 18095 | CEFBS_IsThumb2, // t2LEApcrelJT = 700 |
| 18096 | CEFBS_IsThumb2_HasV8_1MMainline_HasLOB, // t2LoopDec = 701 |
| 18097 | CEFBS_IsThumb2_HasV8_1MMainline_HasLOB, // t2LoopEnd = 702 |
| 18098 | CEFBS_IsThumb2_HasV8_1MMainline_HasLOB, // t2LoopEndDec = 703 |
| 18099 | CEFBS_IsThumb2, // t2MOVCCasr = 704 |
| 18100 | CEFBS_IsThumb2, // t2MOVCCi = 705 |
| 18101 | CEFBS_IsThumb2, // t2MOVCCi16 = 706 |
| 18102 | CEFBS_IsThumb2, // t2MOVCCi32imm = 707 |
| 18103 | CEFBS_IsThumb2, // t2MOVCClsl = 708 |
| 18104 | CEFBS_IsThumb2, // t2MOVCClsr = 709 |
| 18105 | CEFBS_IsThumb2, // t2MOVCCr = 710 |
| 18106 | CEFBS_IsThumb2, // t2MOVCCror = 711 |
| 18107 | CEFBS_IsThumb2, // t2MOVSsi = 712 |
| 18108 | CEFBS_IsThumb2, // t2MOVSsr = 713 |
| 18109 | CEFBS_IsThumb_HasV8MBaseline, // t2MOVTi16_ga_pcrel = 714 |
| 18110 | CEFBS_IsThumb_HasV8MBaseline, // t2MOV_ga_pcrel = 715 |
| 18111 | CEFBS_None, // t2MOVi16_ga_pcrel = 716 |
| 18112 | CEFBS_IsThumb, // t2MOVi32imm = 717 |
| 18113 | CEFBS_IsThumb2, // t2MOVsi = 718 |
| 18114 | CEFBS_IsThumb2, // t2MOVsr = 719 |
| 18115 | CEFBS_IsThumb2, // t2MVNCCi = 720 |
| 18116 | CEFBS_IsThumb2, // t2RSBSri = 721 |
| 18117 | CEFBS_IsThumb2, // t2RSBSrs = 722 |
| 18118 | CEFBS_IsThumb2, // t2STRB_OFFSET_imm = 723 |
| 18119 | CEFBS_IsThumb2, // t2STRB_POST_imm = 724 |
| 18120 | CEFBS_IsThumb2, // t2STRB_PRE_imm = 725 |
| 18121 | CEFBS_IsThumb2, // t2STRB_preidx = 726 |
| 18122 | CEFBS_IsThumb2, // t2STRH_OFFSET_imm = 727 |
| 18123 | CEFBS_IsThumb2, // t2STRH_POST_imm = 728 |
| 18124 | CEFBS_IsThumb2, // t2STRH_PRE_imm = 729 |
| 18125 | CEFBS_IsThumb2, // t2STRH_preidx = 730 |
| 18126 | CEFBS_IsThumb2, // t2STR_POST_imm = 731 |
| 18127 | CEFBS_IsThumb2, // t2STR_PRE_imm = 732 |
| 18128 | CEFBS_IsThumb2, // t2STR_preidx = 733 |
| 18129 | CEFBS_IsThumb2, // t2SUBSri = 734 |
| 18130 | CEFBS_IsThumb2, // t2SUBSrr = 735 |
| 18131 | CEFBS_IsThumb2, // t2SUBSrs = 736 |
| 18132 | CEFBS_None, // t2SpeculationBarrierISBDSBEndBB = 737 |
| 18133 | CEFBS_None, // t2SpeculationBarrierSBEndBB = 738 |
| 18134 | CEFBS_IsThumb2, // t2TBB_JT = 739 |
| 18135 | CEFBS_IsThumb2, // t2TBH_JT = 740 |
| 18136 | CEFBS_IsThumb2_HasV8_1MMainline_HasLOB, // t2WhileLoopSetup = 741 |
| 18137 | CEFBS_IsThumb2_HasV8_1MMainline_HasLOB, // t2WhileLoopStart = 742 |
| 18138 | CEFBS_IsThumb2_HasV8_1MMainline_HasLOB, // t2WhileLoopStartLR = 743 |
| 18139 | CEFBS_IsThumb2_HasV8_1MMainline_HasLOB, // t2WhileLoopStartTP = 744 |
| 18140 | CEFBS_None, // tADCS = 745 |
| 18141 | CEFBS_None, // tADDSi3 = 746 |
| 18142 | CEFBS_None, // tADDSi8 = 747 |
| 18143 | CEFBS_None, // tADDSrr = 748 |
| 18144 | CEFBS_IsThumb, // tADDframe = 749 |
| 18145 | CEFBS_IsThumb, // tADJCALLSTACKDOWN = 750 |
| 18146 | CEFBS_IsThumb, // tADJCALLSTACKUP = 751 |
| 18147 | CEFBS_IsThumb_Has8MSecExt, // tBLXNS_CALL = 752 |
| 18148 | CEFBS_IsThumb_HasV5T, // tBLXr_noip = 753 |
| 18149 | CEFBS_IsThumb, // tBL_PUSHLR = 754 |
| 18150 | CEFBS_IsThumb, // tBRIND = 755 |
| 18151 | CEFBS_IsThumb, // tBR_JTr = 756 |
| 18152 | CEFBS_IsThumb, // tBXNS_RET = 757 |
| 18153 | CEFBS_IsThumb, // tBX_CALL = 758 |
| 18154 | CEFBS_IsThumb, // tBX_RET = 759 |
| 18155 | CEFBS_IsThumb, // tBX_RET_vararg = 760 |
| 18156 | CEFBS_IsThumb, // tBfar = 761 |
| 18157 | CEFBS_None, // tCMP_SWAP_16 = 762 |
| 18158 | CEFBS_None, // tCMP_SWAP_32 = 763 |
| 18159 | CEFBS_None, // tCMP_SWAP_8 = 764 |
| 18160 | CEFBS_IsThumb, // tLDMIA_UPD = 765 |
| 18161 | CEFBS_IsThumb, // tLDRConstPool = 766 |
| 18162 | CEFBS_IsThumb, // tLDRLIT_ga_abs = 767 |
| 18163 | CEFBS_IsThumb, // tLDRLIT_ga_pcrel = 768 |
| 18164 | CEFBS_IsThumb, // tLDR_postidx = 769 |
| 18165 | CEFBS_IsThumb, // tLDRpci_pic = 770 |
| 18166 | CEFBS_IsThumb, // tLEApcrel = 771 |
| 18167 | CEFBS_IsThumb, // tLEApcrelJT = 772 |
| 18168 | CEFBS_None, // tLSLSri = 773 |
| 18169 | CEFBS_None, // tMOVCCr_pseudo = 774 |
| 18170 | CEFBS_None, // tMOVi32imm = 775 |
| 18171 | CEFBS_IsThumb, // tPOP_RET = 776 |
| 18172 | CEFBS_None, // tRSBS = 777 |
| 18173 | CEFBS_None, // tSBCS = 778 |
| 18174 | CEFBS_None, // tSUBSi3 = 779 |
| 18175 | CEFBS_None, // tSUBSi8 = 780 |
| 18176 | CEFBS_None, // tSUBSrr = 781 |
| 18177 | CEFBS_IsThumb2, // tTAILJMPd = 782 |
| 18178 | CEFBS_IsThumb, // tTAILJMPdND = 783 |
| 18179 | CEFBS_IsThumb, // tTAILJMPr = 784 |
| 18180 | CEFBS_IsThumb, // tTBB_JT = 785 |
| 18181 | CEFBS_IsThumb, // tTBH_JT = 786 |
| 18182 | CEFBS_IsThumb, // tTPsoft = 787 |
| 18183 | CEFBS_IsARM, // ADCri = 788 |
| 18184 | CEFBS_IsARM, // ADCrr = 789 |
| 18185 | CEFBS_IsARM, // ADCrsi = 790 |
| 18186 | CEFBS_IsARM, // ADCrsr = 791 |
| 18187 | CEFBS_IsARM, // ADDri = 792 |
| 18188 | CEFBS_IsARM, // ADDrr = 793 |
| 18189 | CEFBS_IsARM, // ADDrsi = 794 |
| 18190 | CEFBS_IsARM, // ADDrsr = 795 |
| 18191 | CEFBS_IsARM, // ADR = 796 |
| 18192 | CEFBS_HasV8_HasAES, // AESD = 797 |
| 18193 | CEFBS_HasV8_HasAES, // AESE = 798 |
| 18194 | CEFBS_HasV8_HasAES, // AESIMC = 799 |
| 18195 | CEFBS_HasV8_HasAES, // AESMC = 800 |
| 18196 | CEFBS_IsARM, // ANDri = 801 |
| 18197 | CEFBS_IsARM, // ANDrr = 802 |
| 18198 | CEFBS_IsARM, // ANDrsi = 803 |
| 18199 | CEFBS_IsARM, // ANDrsr = 804 |
| 18200 | CEFBS_HasBF16_HasNEON, // BF16VDOTI_VDOTD = 805 |
| 18201 | CEFBS_HasBF16_HasNEON, // BF16VDOTI_VDOTQ = 806 |
| 18202 | CEFBS_HasBF16_HasNEON, // BF16VDOTS_VDOTD = 807 |
| 18203 | CEFBS_HasBF16_HasNEON, // BF16VDOTS_VDOTQ = 808 |
| 18204 | CEFBS_HasBF16_HasNEON, // BF16_VCVT = 809 |
| 18205 | CEFBS_HasBF16, // BF16_VCVTB = 810 |
| 18206 | CEFBS_HasBF16, // BF16_VCVTT = 811 |
| 18207 | CEFBS_IsARM_HasV6T2, // BFC = 812 |
| 18208 | CEFBS_IsARM_HasV6T2, // BFI = 813 |
| 18209 | CEFBS_IsARM, // BICri = 814 |
| 18210 | CEFBS_IsARM, // BICrr = 815 |
| 18211 | CEFBS_IsARM, // BICrsi = 816 |
| 18212 | CEFBS_IsARM, // BICrsr = 817 |
| 18213 | CEFBS_IsARM, // BKPT = 818 |
| 18214 | CEFBS_IsARM, // BL = 819 |
| 18215 | CEFBS_IsARM_HasV5T, // BLX = 820 |
| 18216 | CEFBS_IsARM_HasV5T, // BLX_pred = 821 |
| 18217 | CEFBS_IsARM_HasV5T, // BLXi = 822 |
| 18218 | CEFBS_IsARM, // BL_pred = 823 |
| 18219 | CEFBS_IsARM_HasV4T, // BX = 824 |
| 18220 | CEFBS_IsARM, // BXJ = 825 |
| 18221 | CEFBS_IsARM_HasV4T, // BX_RET = 826 |
| 18222 | CEFBS_IsARM_HasV4T, // BX_pred = 827 |
| 18223 | CEFBS_IsARM, // Bcc = 828 |
| 18224 | CEFBS_HasCDE, // CDE_CX1 = 829 |
| 18225 | CEFBS_HasCDE, // CDE_CX1A = 830 |
| 18226 | CEFBS_HasCDE, // CDE_CX1D = 831 |
| 18227 | CEFBS_HasCDE, // CDE_CX1DA = 832 |
| 18228 | CEFBS_HasCDE, // CDE_CX2 = 833 |
| 18229 | CEFBS_HasCDE, // CDE_CX2A = 834 |
| 18230 | CEFBS_HasCDE, // CDE_CX2D = 835 |
| 18231 | CEFBS_HasCDE, // CDE_CX2DA = 836 |
| 18232 | CEFBS_HasCDE, // CDE_CX3 = 837 |
| 18233 | CEFBS_HasCDE, // CDE_CX3A = 838 |
| 18234 | CEFBS_HasCDE, // CDE_CX3D = 839 |
| 18235 | CEFBS_HasCDE, // CDE_CX3DA = 840 |
| 18236 | CEFBS_HasCDE_HasFPRegs, // CDE_VCX1A_fpdp = 841 |
| 18237 | CEFBS_HasCDE_HasFPRegs, // CDE_VCX1A_fpsp = 842 |
| 18238 | CEFBS_HasCDE_HasMVEInt, // CDE_VCX1A_vec = 843 |
| 18239 | CEFBS_HasCDE_HasFPRegs, // CDE_VCX1_fpdp = 844 |
| 18240 | CEFBS_HasCDE_HasFPRegs, // CDE_VCX1_fpsp = 845 |
| 18241 | CEFBS_HasCDE_HasMVEInt, // CDE_VCX1_vec = 846 |
| 18242 | CEFBS_HasCDE_HasFPRegs, // CDE_VCX2A_fpdp = 847 |
| 18243 | CEFBS_HasCDE_HasFPRegs, // CDE_VCX2A_fpsp = 848 |
| 18244 | CEFBS_HasCDE_HasMVEInt, // CDE_VCX2A_vec = 849 |
| 18245 | CEFBS_HasCDE_HasFPRegs, // CDE_VCX2_fpdp = 850 |
| 18246 | CEFBS_HasCDE_HasFPRegs, // CDE_VCX2_fpsp = 851 |
| 18247 | CEFBS_HasCDE_HasMVEInt, // CDE_VCX2_vec = 852 |
| 18248 | CEFBS_HasCDE_HasFPRegs, // CDE_VCX3A_fpdp = 853 |
| 18249 | CEFBS_HasCDE_HasFPRegs, // CDE_VCX3A_fpsp = 854 |
| 18250 | CEFBS_HasCDE_HasMVEInt, // CDE_VCX3A_vec = 855 |
| 18251 | CEFBS_HasCDE_HasFPRegs, // CDE_VCX3_fpdp = 856 |
| 18252 | CEFBS_HasCDE_HasFPRegs, // CDE_VCX3_fpsp = 857 |
| 18253 | CEFBS_HasCDE_HasMVEInt, // CDE_VCX3_vec = 858 |
| 18254 | CEFBS_IsARM_PreV8, // CDP = 859 |
| 18255 | CEFBS_IsARM_PreV8, // CDP2 = 860 |
| 18256 | CEFBS_IsARM_HasV6K, // CLREX = 861 |
| 18257 | CEFBS_IsARM_HasV5T, // CLZ = 862 |
| 18258 | CEFBS_IsARM, // CMNri = 863 |
| 18259 | CEFBS_IsARM, // CMNzrr = 864 |
| 18260 | CEFBS_IsARM, // CMNzrsi = 865 |
| 18261 | CEFBS_IsARM, // CMNzrsr = 866 |
| 18262 | CEFBS_IsARM, // CMPri = 867 |
| 18263 | CEFBS_IsARM, // CMPrr = 868 |
| 18264 | CEFBS_IsARM, // CMPrsi = 869 |
| 18265 | CEFBS_IsARM, // CMPrsr = 870 |
| 18266 | CEFBS_IsARM, // CPS1p = 871 |
| 18267 | CEFBS_IsARM, // CPS2p = 872 |
| 18268 | CEFBS_IsARM, // CPS3p = 873 |
| 18269 | CEFBS_IsARM_HasCRC, // CRC32B = 874 |
| 18270 | CEFBS_IsARM_HasCRC, // CRC32CB = 875 |
| 18271 | CEFBS_IsARM_HasCRC, // CRC32CH = 876 |
| 18272 | CEFBS_IsARM_HasCRC, // CRC32CW = 877 |
| 18273 | CEFBS_IsARM_HasCRC, // CRC32H = 878 |
| 18274 | CEFBS_IsARM_HasCRC, // CRC32W = 879 |
| 18275 | CEFBS_IsARM_HasV7, // DBG = 880 |
| 18276 | CEFBS_IsARM_HasDB, // DMB = 881 |
| 18277 | CEFBS_IsARM_HasDB, // DSB = 882 |
| 18278 | CEFBS_IsARM, // EORri = 883 |
| 18279 | CEFBS_IsARM, // EORrr = 884 |
| 18280 | CEFBS_IsARM, // EORrsi = 885 |
| 18281 | CEFBS_IsARM, // EORrsr = 886 |
| 18282 | CEFBS_IsARM_HasVirtualization, // ERET = 887 |
| 18283 | CEFBS_HasVFP3_HasDPVFP, // FCONSTD = 888 |
| 18284 | CEFBS_HasFullFP16, // FCONSTH = 889 |
| 18285 | CEFBS_HasVFP3, // FCONSTS = 890 |
| 18286 | CEFBS_HasFPRegs, // FLDMXDB_UPD = 891 |
| 18287 | CEFBS_HasFPRegs, // FLDMXIA = 892 |
| 18288 | CEFBS_HasFPRegs, // FLDMXIA_UPD = 893 |
| 18289 | CEFBS_HasFPRegs, // FMSTAT = 894 |
| 18290 | CEFBS_HasFPRegs, // FSTMXDB_UPD = 895 |
| 18291 | CEFBS_HasFPRegs, // FSTMXIA = 896 |
| 18292 | CEFBS_HasFPRegs, // FSTMXIA_UPD = 897 |
| 18293 | CEFBS_IsARM_HasV6, // HINT = 898 |
| 18294 | CEFBS_IsARM_HasV8, // HLT = 899 |
| 18295 | CEFBS_IsARM_HasVirtualization, // HVC = 900 |
| 18296 | CEFBS_IsARM_HasDB, // ISB = 901 |
| 18297 | CEFBS_IsARM_HasAcquireRelease, // LDA = 902 |
| 18298 | CEFBS_IsARM_HasAcquireRelease, // LDAB = 903 |
| 18299 | CEFBS_IsARM_HasAcquireRelease_HasV7Clrex, // LDAEX = 904 |
| 18300 | CEFBS_IsARM_HasAcquireRelease_HasV7Clrex, // LDAEXB = 905 |
| 18301 | CEFBS_IsARM_HasAcquireRelease_HasV7Clrex, // LDAEXD = 906 |
| 18302 | CEFBS_IsARM_HasAcquireRelease_HasV7Clrex, // LDAEXH = 907 |
| 18303 | CEFBS_IsARM_HasAcquireRelease, // LDAH = 908 |
| 18304 | CEFBS_IsARM_PreV8, // LDC2L_OFFSET = 909 |
| 18305 | CEFBS_IsARM_PreV8, // LDC2L_OPTION = 910 |
| 18306 | CEFBS_IsARM_PreV8, // LDC2L_POST = 911 |
| 18307 | CEFBS_IsARM_PreV8, // LDC2L_PRE = 912 |
| 18308 | CEFBS_IsARM_PreV8, // LDC2_OFFSET = 913 |
| 18309 | CEFBS_IsARM_PreV8, // LDC2_OPTION = 914 |
| 18310 | CEFBS_IsARM_PreV8, // LDC2_POST = 915 |
| 18311 | CEFBS_IsARM_PreV8, // LDC2_PRE = 916 |
| 18312 | CEFBS_IsARM, // LDCL_OFFSET = 917 |
| 18313 | CEFBS_IsARM, // LDCL_OPTION = 918 |
| 18314 | CEFBS_IsARM, // LDCL_POST = 919 |
| 18315 | CEFBS_IsARM, // LDCL_PRE = 920 |
| 18316 | CEFBS_IsARM, // LDC_OFFSET = 921 |
| 18317 | CEFBS_IsARM, // LDC_OPTION = 922 |
| 18318 | CEFBS_IsARM, // LDC_POST = 923 |
| 18319 | CEFBS_IsARM, // LDC_PRE = 924 |
| 18320 | CEFBS_IsARM, // LDMDA = 925 |
| 18321 | CEFBS_IsARM, // LDMDA_UPD = 926 |
| 18322 | CEFBS_IsARM, // LDMDB = 927 |
| 18323 | CEFBS_IsARM, // LDMDB_UPD = 928 |
| 18324 | CEFBS_IsARM, // LDMIA = 929 |
| 18325 | CEFBS_IsARM, // LDMIA_UPD = 930 |
| 18326 | CEFBS_IsARM, // LDMIB = 931 |
| 18327 | CEFBS_IsARM, // LDMIB_UPD = 932 |
| 18328 | CEFBS_IsARM, // LDRBT_POST_IMM = 933 |
| 18329 | CEFBS_IsARM, // LDRBT_POST_REG = 934 |
| 18330 | CEFBS_IsARM, // LDRB_POST_IMM = 935 |
| 18331 | CEFBS_IsARM, // LDRB_POST_REG = 936 |
| 18332 | CEFBS_IsARM, // LDRB_PRE_IMM = 937 |
| 18333 | CEFBS_IsARM, // LDRB_PRE_REG = 938 |
| 18334 | CEFBS_IsARM, // LDRBi12 = 939 |
| 18335 | CEFBS_IsARM, // LDRBrs = 940 |
| 18336 | CEFBS_IsARM_HasV5TE, // LDRD = 941 |
| 18337 | CEFBS_IsARM, // LDRD_POST = 942 |
| 18338 | CEFBS_IsARM, // LDRD_PRE = 943 |
| 18339 | CEFBS_IsARM, // LDREX = 944 |
| 18340 | CEFBS_IsARM, // LDREXB = 945 |
| 18341 | CEFBS_IsARM, // LDREXD = 946 |
| 18342 | CEFBS_IsARM, // LDREXH = 947 |
| 18343 | CEFBS_IsARM, // LDRH = 948 |
| 18344 | CEFBS_IsARM, // LDRHTi = 949 |
| 18345 | CEFBS_IsARM, // LDRHTr = 950 |
| 18346 | CEFBS_IsARM, // LDRH_POST = 951 |
| 18347 | CEFBS_IsARM, // LDRH_PRE = 952 |
| 18348 | CEFBS_IsARM, // LDRSB = 953 |
| 18349 | CEFBS_IsARM, // LDRSBTi = 954 |
| 18350 | CEFBS_IsARM, // LDRSBTr = 955 |
| 18351 | CEFBS_IsARM, // LDRSB_POST = 956 |
| 18352 | CEFBS_IsARM, // LDRSB_PRE = 957 |
| 18353 | CEFBS_IsARM, // LDRSH = 958 |
| 18354 | CEFBS_IsARM, // LDRSHTi = 959 |
| 18355 | CEFBS_IsARM, // LDRSHTr = 960 |
| 18356 | CEFBS_IsARM, // LDRSH_POST = 961 |
| 18357 | CEFBS_IsARM, // LDRSH_PRE = 962 |
| 18358 | CEFBS_IsARM, // LDRT_POST_IMM = 963 |
| 18359 | CEFBS_IsARM, // LDRT_POST_REG = 964 |
| 18360 | CEFBS_IsARM, // LDR_POST_IMM = 965 |
| 18361 | CEFBS_IsARM, // LDR_POST_REG = 966 |
| 18362 | CEFBS_IsARM, // LDR_PRE_IMM = 967 |
| 18363 | CEFBS_IsARM, // LDR_PRE_REG = 968 |
| 18364 | CEFBS_IsARM, // LDRcp = 969 |
| 18365 | CEFBS_IsARM, // LDRi12 = 970 |
| 18366 | CEFBS_IsARM, // LDRrs = 971 |
| 18367 | CEFBS_IsARM, // MCR = 972 |
| 18368 | CEFBS_IsARM_PreV8, // MCR2 = 973 |
| 18369 | CEFBS_IsARM, // MCRR = 974 |
| 18370 | CEFBS_IsARM_PreV8, // MCRR2 = 975 |
| 18371 | CEFBS_IsARM_HasV6, // MLA = 976 |
| 18372 | CEFBS_IsARM_HasV6T2, // MLS = 977 |
| 18373 | CEFBS_IsARM, // MOVPCLR = 978 |
| 18374 | CEFBS_IsARM_HasV6T2, // MOVTi16 = 979 |
| 18375 | CEFBS_IsARM, // MOVi = 980 |
| 18376 | CEFBS_IsARM_HasV6T2, // MOVi16 = 981 |
| 18377 | CEFBS_IsARM, // MOVr = 982 |
| 18378 | CEFBS_IsARM, // MOVr_TC = 983 |
| 18379 | CEFBS_IsARM, // MOVsi = 984 |
| 18380 | CEFBS_IsARM, // MOVsr = 985 |
| 18381 | CEFBS_IsARM, // MRC = 986 |
| 18382 | CEFBS_IsARM_PreV8, // MRC2 = 987 |
| 18383 | CEFBS_IsARM, // MRRC = 988 |
| 18384 | CEFBS_IsARM_PreV8, // MRRC2 = 989 |
| 18385 | CEFBS_IsARM, // MRS = 990 |
| 18386 | CEFBS_IsARM_HasVirtualization, // MRSbanked = 991 |
| 18387 | CEFBS_IsARM, // MRSsys = 992 |
| 18388 | CEFBS_IsARM, // MSR = 993 |
| 18389 | CEFBS_IsARM_HasVirtualization, // MSRbanked = 994 |
| 18390 | CEFBS_IsARM, // MSRi = 995 |
| 18391 | CEFBS_IsARM_HasV6, // MUL = 996 |
| 18392 | CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_ASRLi = 997 |
| 18393 | CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_ASRLr = 998 |
| 18394 | CEFBS_HasMVEInt, // MVE_DLSTP_16 = 999 |
| 18395 | CEFBS_HasMVEInt, // MVE_DLSTP_32 = 1000 |
| 18396 | CEFBS_HasMVEInt, // MVE_DLSTP_64 = 1001 |
| 18397 | CEFBS_HasMVEInt, // MVE_DLSTP_8 = 1002 |
| 18398 | CEFBS_HasMVEInt, // MVE_LCTP = 1003 |
| 18399 | CEFBS_HasMVEInt, // MVE_LETP = 1004 |
| 18400 | CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_LSLLi = 1005 |
| 18401 | CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_LSLLr = 1006 |
| 18402 | CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_LSRL = 1007 |
| 18403 | CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_SQRSHR = 1008 |
| 18404 | CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_SQRSHRL = 1009 |
| 18405 | CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_SQSHL = 1010 |
| 18406 | CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_SQSHLL = 1011 |
| 18407 | CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_SRSHR = 1012 |
| 18408 | CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_SRSHRL = 1013 |
| 18409 | CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_UQRSHL = 1014 |
| 18410 | CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_UQRSHLL = 1015 |
| 18411 | CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_UQSHL = 1016 |
| 18412 | CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_UQSHLL = 1017 |
| 18413 | CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_URSHR = 1018 |
| 18414 | CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_URSHRL = 1019 |
| 18415 | CEFBS_HasMVEInt, // MVE_VABAVs16 = 1020 |
| 18416 | CEFBS_HasMVEInt, // MVE_VABAVs32 = 1021 |
| 18417 | CEFBS_HasMVEInt, // MVE_VABAVs8 = 1022 |
| 18418 | CEFBS_HasMVEInt, // MVE_VABAVu16 = 1023 |
| 18419 | CEFBS_HasMVEInt, // MVE_VABAVu32 = 1024 |
| 18420 | CEFBS_HasMVEInt, // MVE_VABAVu8 = 1025 |
| 18421 | CEFBS_HasMVEFloat, // MVE_VABDf16 = 1026 |
| 18422 | CEFBS_HasMVEFloat, // MVE_VABDf32 = 1027 |
| 18423 | CEFBS_HasMVEInt, // MVE_VABDs16 = 1028 |
| 18424 | CEFBS_HasMVEInt, // MVE_VABDs32 = 1029 |
| 18425 | CEFBS_HasMVEInt, // MVE_VABDs8 = 1030 |
| 18426 | CEFBS_HasMVEInt, // MVE_VABDu16 = 1031 |
| 18427 | CEFBS_HasMVEInt, // MVE_VABDu32 = 1032 |
| 18428 | CEFBS_HasMVEInt, // MVE_VABDu8 = 1033 |
| 18429 | CEFBS_HasMVEFloat, // MVE_VABSf16 = 1034 |
| 18430 | CEFBS_HasMVEFloat, // MVE_VABSf32 = 1035 |
| 18431 | CEFBS_HasMVEInt, // MVE_VABSs16 = 1036 |
| 18432 | CEFBS_HasMVEInt, // MVE_VABSs32 = 1037 |
| 18433 | CEFBS_HasMVEInt, // MVE_VABSs8 = 1038 |
| 18434 | CEFBS_HasMVEInt, // MVE_VADC = 1039 |
| 18435 | CEFBS_HasMVEInt, // MVE_VADCI = 1040 |
| 18436 | CEFBS_HasMVEInt, // MVE_VADDLVs32acc = 1041 |
| 18437 | CEFBS_HasMVEInt, // MVE_VADDLVs32no_acc = 1042 |
| 18438 | CEFBS_HasMVEInt, // MVE_VADDLVu32acc = 1043 |
| 18439 | CEFBS_HasMVEInt, // MVE_VADDLVu32no_acc = 1044 |
| 18440 | CEFBS_HasMVEInt, // MVE_VADDVs16acc = 1045 |
| 18441 | CEFBS_HasMVEInt, // MVE_VADDVs16no_acc = 1046 |
| 18442 | CEFBS_HasMVEInt, // MVE_VADDVs32acc = 1047 |
| 18443 | CEFBS_HasMVEInt, // MVE_VADDVs32no_acc = 1048 |
| 18444 | CEFBS_HasMVEInt, // MVE_VADDVs8acc = 1049 |
| 18445 | CEFBS_HasMVEInt, // MVE_VADDVs8no_acc = 1050 |
| 18446 | CEFBS_HasMVEInt, // MVE_VADDVu16acc = 1051 |
| 18447 | CEFBS_HasMVEInt, // MVE_VADDVu16no_acc = 1052 |
| 18448 | CEFBS_HasMVEInt, // MVE_VADDVu32acc = 1053 |
| 18449 | CEFBS_HasMVEInt, // MVE_VADDVu32no_acc = 1054 |
| 18450 | CEFBS_HasMVEInt, // MVE_VADDVu8acc = 1055 |
| 18451 | CEFBS_HasMVEInt, // MVE_VADDVu8no_acc = 1056 |
| 18452 | CEFBS_HasMVEFloat, // MVE_VADD_qr_f16 = 1057 |
| 18453 | CEFBS_HasMVEFloat, // MVE_VADD_qr_f32 = 1058 |
| 18454 | CEFBS_HasMVEInt, // MVE_VADD_qr_i16 = 1059 |
| 18455 | CEFBS_HasMVEInt, // MVE_VADD_qr_i32 = 1060 |
| 18456 | CEFBS_HasMVEInt, // MVE_VADD_qr_i8 = 1061 |
| 18457 | CEFBS_HasMVEFloat, // MVE_VADDf16 = 1062 |
| 18458 | CEFBS_HasMVEFloat, // MVE_VADDf32 = 1063 |
| 18459 | CEFBS_HasMVEInt, // MVE_VADDi16 = 1064 |
| 18460 | CEFBS_HasMVEInt, // MVE_VADDi32 = 1065 |
| 18461 | CEFBS_HasMVEInt, // MVE_VADDi8 = 1066 |
| 18462 | CEFBS_HasMVEInt, // MVE_VAND = 1067 |
| 18463 | CEFBS_HasMVEInt, // MVE_VBIC = 1068 |
| 18464 | CEFBS_HasMVEInt, // MVE_VBICimmi16 = 1069 |
| 18465 | CEFBS_HasMVEInt, // MVE_VBICimmi32 = 1070 |
| 18466 | CEFBS_HasMVEInt, // MVE_VBRSR16 = 1071 |
| 18467 | CEFBS_HasMVEInt, // MVE_VBRSR32 = 1072 |
| 18468 | CEFBS_HasMVEInt, // MVE_VBRSR8 = 1073 |
| 18469 | CEFBS_HasMVEFloat, // MVE_VCADDf16 = 1074 |
| 18470 | CEFBS_HasMVEFloat, // MVE_VCADDf32 = 1075 |
| 18471 | CEFBS_HasMVEInt, // MVE_VCADDi16 = 1076 |
| 18472 | CEFBS_HasMVEInt, // MVE_VCADDi32 = 1077 |
| 18473 | CEFBS_HasMVEInt, // MVE_VCADDi8 = 1078 |
| 18474 | CEFBS_HasMVEInt, // MVE_VCLSs16 = 1079 |
| 18475 | CEFBS_HasMVEInt, // MVE_VCLSs32 = 1080 |
| 18476 | CEFBS_HasMVEInt, // MVE_VCLSs8 = 1081 |
| 18477 | CEFBS_HasMVEInt, // MVE_VCLZs16 = 1082 |
| 18478 | CEFBS_HasMVEInt, // MVE_VCLZs32 = 1083 |
| 18479 | CEFBS_HasMVEInt, // MVE_VCLZs8 = 1084 |
| 18480 | CEFBS_HasMVEFloat, // MVE_VCMLAf16 = 1085 |
| 18481 | CEFBS_HasMVEFloat, // MVE_VCMLAf32 = 1086 |
| 18482 | CEFBS_HasMVEFloat, // MVE_VCMPf16 = 1087 |
| 18483 | CEFBS_HasMVEFloat, // MVE_VCMPf16r = 1088 |
| 18484 | CEFBS_HasMVEFloat, // MVE_VCMPf32 = 1089 |
| 18485 | CEFBS_HasMVEFloat, // MVE_VCMPf32r = 1090 |
| 18486 | CEFBS_HasMVEInt, // MVE_VCMPi16 = 1091 |
| 18487 | CEFBS_HasMVEInt, // MVE_VCMPi16r = 1092 |
| 18488 | CEFBS_HasMVEInt, // MVE_VCMPi32 = 1093 |
| 18489 | CEFBS_HasMVEInt, // MVE_VCMPi32r = 1094 |
| 18490 | CEFBS_HasMVEInt, // MVE_VCMPi8 = 1095 |
| 18491 | CEFBS_HasMVEInt, // MVE_VCMPi8r = 1096 |
| 18492 | CEFBS_HasMVEInt, // MVE_VCMPs16 = 1097 |
| 18493 | CEFBS_HasMVEInt, // MVE_VCMPs16r = 1098 |
| 18494 | CEFBS_HasMVEInt, // MVE_VCMPs32 = 1099 |
| 18495 | CEFBS_HasMVEInt, // MVE_VCMPs32r = 1100 |
| 18496 | CEFBS_HasMVEInt, // MVE_VCMPs8 = 1101 |
| 18497 | CEFBS_HasMVEInt, // MVE_VCMPs8r = 1102 |
| 18498 | CEFBS_HasMVEInt, // MVE_VCMPu16 = 1103 |
| 18499 | CEFBS_HasMVEInt, // MVE_VCMPu16r = 1104 |
| 18500 | CEFBS_HasMVEInt, // MVE_VCMPu32 = 1105 |
| 18501 | CEFBS_HasMVEInt, // MVE_VCMPu32r = 1106 |
| 18502 | CEFBS_HasMVEInt, // MVE_VCMPu8 = 1107 |
| 18503 | CEFBS_HasMVEInt, // MVE_VCMPu8r = 1108 |
| 18504 | CEFBS_HasMVEFloat, // MVE_VCMULf16 = 1109 |
| 18505 | CEFBS_HasMVEFloat, // MVE_VCMULf32 = 1110 |
| 18506 | CEFBS_HasMVEInt, // MVE_VCTP16 = 1111 |
| 18507 | CEFBS_HasMVEInt, // MVE_VCTP32 = 1112 |
| 18508 | CEFBS_HasMVEInt, // MVE_VCTP64 = 1113 |
| 18509 | CEFBS_HasMVEInt, // MVE_VCTP8 = 1114 |
| 18510 | CEFBS_HasMVEFloat, // MVE_VCVTf16f32bh = 1115 |
| 18511 | CEFBS_HasMVEFloat, // MVE_VCVTf16f32th = 1116 |
| 18512 | CEFBS_HasMVEFloat, // MVE_VCVTf16s16_fix = 1117 |
| 18513 | CEFBS_HasMVEFloat, // MVE_VCVTf16s16n = 1118 |
| 18514 | CEFBS_HasMVEFloat, // MVE_VCVTf16u16_fix = 1119 |
| 18515 | CEFBS_HasMVEFloat, // MVE_VCVTf16u16n = 1120 |
| 18516 | CEFBS_HasMVEFloat, // MVE_VCVTf32f16bh = 1121 |
| 18517 | CEFBS_HasMVEFloat, // MVE_VCVTf32f16th = 1122 |
| 18518 | CEFBS_HasMVEFloat, // MVE_VCVTf32s32_fix = 1123 |
| 18519 | CEFBS_HasMVEFloat, // MVE_VCVTf32s32n = 1124 |
| 18520 | CEFBS_HasMVEFloat, // MVE_VCVTf32u32_fix = 1125 |
| 18521 | CEFBS_HasMVEFloat, // MVE_VCVTf32u32n = 1126 |
| 18522 | CEFBS_HasMVEFloat, // MVE_VCVTs16f16_fix = 1127 |
| 18523 | CEFBS_HasMVEFloat, // MVE_VCVTs16f16a = 1128 |
| 18524 | CEFBS_HasMVEFloat, // MVE_VCVTs16f16m = 1129 |
| 18525 | CEFBS_HasMVEFloat, // MVE_VCVTs16f16n = 1130 |
| 18526 | CEFBS_HasMVEFloat, // MVE_VCVTs16f16p = 1131 |
| 18527 | CEFBS_HasMVEFloat, // MVE_VCVTs16f16z = 1132 |
| 18528 | CEFBS_HasMVEFloat, // MVE_VCVTs32f32_fix = 1133 |
| 18529 | CEFBS_HasMVEFloat, // MVE_VCVTs32f32a = 1134 |
| 18530 | CEFBS_HasMVEFloat, // MVE_VCVTs32f32m = 1135 |
| 18531 | CEFBS_HasMVEFloat, // MVE_VCVTs32f32n = 1136 |
| 18532 | CEFBS_HasMVEFloat, // MVE_VCVTs32f32p = 1137 |
| 18533 | CEFBS_HasMVEFloat, // MVE_VCVTs32f32z = 1138 |
| 18534 | CEFBS_HasMVEFloat, // MVE_VCVTu16f16_fix = 1139 |
| 18535 | CEFBS_HasMVEFloat, // MVE_VCVTu16f16a = 1140 |
| 18536 | CEFBS_HasMVEFloat, // MVE_VCVTu16f16m = 1141 |
| 18537 | CEFBS_HasMVEFloat, // MVE_VCVTu16f16n = 1142 |
| 18538 | CEFBS_HasMVEFloat, // MVE_VCVTu16f16p = 1143 |
| 18539 | CEFBS_HasMVEFloat, // MVE_VCVTu16f16z = 1144 |
| 18540 | CEFBS_HasMVEFloat, // MVE_VCVTu32f32_fix = 1145 |
| 18541 | CEFBS_HasMVEFloat, // MVE_VCVTu32f32a = 1146 |
| 18542 | CEFBS_HasMVEFloat, // MVE_VCVTu32f32m = 1147 |
| 18543 | CEFBS_HasMVEFloat, // MVE_VCVTu32f32n = 1148 |
| 18544 | CEFBS_HasMVEFloat, // MVE_VCVTu32f32p = 1149 |
| 18545 | CEFBS_HasMVEFloat, // MVE_VCVTu32f32z = 1150 |
| 18546 | CEFBS_HasMVEInt, // MVE_VDDUPu16 = 1151 |
| 18547 | CEFBS_HasMVEInt, // MVE_VDDUPu32 = 1152 |
| 18548 | CEFBS_HasMVEInt, // MVE_VDDUPu8 = 1153 |
| 18549 | CEFBS_HasMVEInt, // MVE_VDUP16 = 1154 |
| 18550 | CEFBS_HasMVEInt, // MVE_VDUP32 = 1155 |
| 18551 | CEFBS_HasMVEInt, // MVE_VDUP8 = 1156 |
| 18552 | CEFBS_HasMVEInt, // MVE_VDWDUPu16 = 1157 |
| 18553 | CEFBS_HasMVEInt, // MVE_VDWDUPu32 = 1158 |
| 18554 | CEFBS_HasMVEInt, // MVE_VDWDUPu8 = 1159 |
| 18555 | CEFBS_HasMVEInt, // MVE_VEOR = 1160 |
| 18556 | CEFBS_HasMVEFloat, // MVE_VFMA_qr_Sf16 = 1161 |
| 18557 | CEFBS_HasMVEFloat, // MVE_VFMA_qr_Sf32 = 1162 |
| 18558 | CEFBS_HasMVEFloat, // MVE_VFMA_qr_f16 = 1163 |
| 18559 | CEFBS_HasMVEFloat, // MVE_VFMA_qr_f32 = 1164 |
| 18560 | CEFBS_HasMVEFloat, // MVE_VFMAf16 = 1165 |
| 18561 | CEFBS_HasMVEFloat, // MVE_VFMAf32 = 1166 |
| 18562 | CEFBS_HasMVEFloat, // MVE_VFMSf16 = 1167 |
| 18563 | CEFBS_HasMVEFloat, // MVE_VFMSf32 = 1168 |
| 18564 | CEFBS_HasMVEInt, // MVE_VHADD_qr_s16 = 1169 |
| 18565 | CEFBS_HasMVEInt, // MVE_VHADD_qr_s32 = 1170 |
| 18566 | CEFBS_HasMVEInt, // MVE_VHADD_qr_s8 = 1171 |
| 18567 | CEFBS_HasMVEInt, // MVE_VHADD_qr_u16 = 1172 |
| 18568 | CEFBS_HasMVEInt, // MVE_VHADD_qr_u32 = 1173 |
| 18569 | CEFBS_HasMVEInt, // MVE_VHADD_qr_u8 = 1174 |
| 18570 | CEFBS_HasMVEInt, // MVE_VHADDs16 = 1175 |
| 18571 | CEFBS_HasMVEInt, // MVE_VHADDs32 = 1176 |
| 18572 | CEFBS_HasMVEInt, // MVE_VHADDs8 = 1177 |
| 18573 | CEFBS_HasMVEInt, // MVE_VHADDu16 = 1178 |
| 18574 | CEFBS_HasMVEInt, // MVE_VHADDu32 = 1179 |
| 18575 | CEFBS_HasMVEInt, // MVE_VHADDu8 = 1180 |
| 18576 | CEFBS_HasMVEInt, // MVE_VHCADDs16 = 1181 |
| 18577 | CEFBS_HasMVEInt, // MVE_VHCADDs32 = 1182 |
| 18578 | CEFBS_HasMVEInt, // MVE_VHCADDs8 = 1183 |
| 18579 | CEFBS_HasMVEInt, // MVE_VHSUB_qr_s16 = 1184 |
| 18580 | CEFBS_HasMVEInt, // MVE_VHSUB_qr_s32 = 1185 |
| 18581 | CEFBS_HasMVEInt, // MVE_VHSUB_qr_s8 = 1186 |
| 18582 | CEFBS_HasMVEInt, // MVE_VHSUB_qr_u16 = 1187 |
| 18583 | CEFBS_HasMVEInt, // MVE_VHSUB_qr_u32 = 1188 |
| 18584 | CEFBS_HasMVEInt, // MVE_VHSUB_qr_u8 = 1189 |
| 18585 | CEFBS_HasMVEInt, // MVE_VHSUBs16 = 1190 |
| 18586 | CEFBS_HasMVEInt, // MVE_VHSUBs32 = 1191 |
| 18587 | CEFBS_HasMVEInt, // MVE_VHSUBs8 = 1192 |
| 18588 | CEFBS_HasMVEInt, // MVE_VHSUBu16 = 1193 |
| 18589 | CEFBS_HasMVEInt, // MVE_VHSUBu32 = 1194 |
| 18590 | CEFBS_HasMVEInt, // MVE_VHSUBu8 = 1195 |
| 18591 | CEFBS_HasMVEInt, // MVE_VIDUPu16 = 1196 |
| 18592 | CEFBS_HasMVEInt, // MVE_VIDUPu32 = 1197 |
| 18593 | CEFBS_HasMVEInt, // MVE_VIDUPu8 = 1198 |
| 18594 | CEFBS_HasMVEInt, // MVE_VIWDUPu16 = 1199 |
| 18595 | CEFBS_HasMVEInt, // MVE_VIWDUPu32 = 1200 |
| 18596 | CEFBS_HasMVEInt, // MVE_VIWDUPu8 = 1201 |
| 18597 | CEFBS_HasMVEInt, // MVE_VLD20_16 = 1202 |
| 18598 | CEFBS_HasMVEInt, // MVE_VLD20_16_wb = 1203 |
| 18599 | CEFBS_HasMVEInt, // MVE_VLD20_32 = 1204 |
| 18600 | CEFBS_HasMVEInt, // MVE_VLD20_32_wb = 1205 |
| 18601 | CEFBS_HasMVEInt, // MVE_VLD20_8 = 1206 |
| 18602 | CEFBS_HasMVEInt, // MVE_VLD20_8_wb = 1207 |
| 18603 | CEFBS_HasMVEInt, // MVE_VLD21_16 = 1208 |
| 18604 | CEFBS_HasMVEInt, // MVE_VLD21_16_wb = 1209 |
| 18605 | CEFBS_HasMVEInt, // MVE_VLD21_32 = 1210 |
| 18606 | CEFBS_HasMVEInt, // MVE_VLD21_32_wb = 1211 |
| 18607 | CEFBS_HasMVEInt, // MVE_VLD21_8 = 1212 |
| 18608 | CEFBS_HasMVEInt, // MVE_VLD21_8_wb = 1213 |
| 18609 | CEFBS_HasMVEInt, // MVE_VLD40_16 = 1214 |
| 18610 | CEFBS_HasMVEInt, // MVE_VLD40_16_wb = 1215 |
| 18611 | CEFBS_HasMVEInt, // MVE_VLD40_32 = 1216 |
| 18612 | CEFBS_HasMVEInt, // MVE_VLD40_32_wb = 1217 |
| 18613 | CEFBS_HasMVEInt, // MVE_VLD40_8 = 1218 |
| 18614 | CEFBS_HasMVEInt, // MVE_VLD40_8_wb = 1219 |
| 18615 | CEFBS_HasMVEInt, // MVE_VLD41_16 = 1220 |
| 18616 | CEFBS_HasMVEInt, // MVE_VLD41_16_wb = 1221 |
| 18617 | CEFBS_HasMVEInt, // MVE_VLD41_32 = 1222 |
| 18618 | CEFBS_HasMVEInt, // MVE_VLD41_32_wb = 1223 |
| 18619 | CEFBS_HasMVEInt, // MVE_VLD41_8 = 1224 |
| 18620 | CEFBS_HasMVEInt, // MVE_VLD41_8_wb = 1225 |
| 18621 | CEFBS_HasMVEInt, // MVE_VLD42_16 = 1226 |
| 18622 | CEFBS_HasMVEInt, // MVE_VLD42_16_wb = 1227 |
| 18623 | CEFBS_HasMVEInt, // MVE_VLD42_32 = 1228 |
| 18624 | CEFBS_HasMVEInt, // MVE_VLD42_32_wb = 1229 |
| 18625 | CEFBS_HasMVEInt, // MVE_VLD42_8 = 1230 |
| 18626 | CEFBS_HasMVEInt, // MVE_VLD42_8_wb = 1231 |
| 18627 | CEFBS_HasMVEInt, // MVE_VLD43_16 = 1232 |
| 18628 | CEFBS_HasMVEInt, // MVE_VLD43_16_wb = 1233 |
| 18629 | CEFBS_HasMVEInt, // MVE_VLD43_32 = 1234 |
| 18630 | CEFBS_HasMVEInt, // MVE_VLD43_32_wb = 1235 |
| 18631 | CEFBS_HasMVEInt, // MVE_VLD43_8 = 1236 |
| 18632 | CEFBS_HasMVEInt, // MVE_VLD43_8_wb = 1237 |
| 18633 | CEFBS_HasMVEInt, // MVE_VLDRBS16 = 1238 |
| 18634 | CEFBS_HasMVEInt, // MVE_VLDRBS16_post = 1239 |
| 18635 | CEFBS_HasMVEInt, // MVE_VLDRBS16_pre = 1240 |
| 18636 | CEFBS_HasMVEInt, // MVE_VLDRBS16_rq = 1241 |
| 18637 | CEFBS_HasMVEInt, // MVE_VLDRBS32 = 1242 |
| 18638 | CEFBS_HasMVEInt, // MVE_VLDRBS32_post = 1243 |
| 18639 | CEFBS_HasMVEInt, // MVE_VLDRBS32_pre = 1244 |
| 18640 | CEFBS_HasMVEInt, // MVE_VLDRBS32_rq = 1245 |
| 18641 | CEFBS_HasMVEInt, // MVE_VLDRBU16 = 1246 |
| 18642 | CEFBS_HasMVEInt, // MVE_VLDRBU16_post = 1247 |
| 18643 | CEFBS_HasMVEInt, // MVE_VLDRBU16_pre = 1248 |
| 18644 | CEFBS_HasMVEInt, // MVE_VLDRBU16_rq = 1249 |
| 18645 | CEFBS_HasMVEInt, // MVE_VLDRBU32 = 1250 |
| 18646 | CEFBS_HasMVEInt, // MVE_VLDRBU32_post = 1251 |
| 18647 | CEFBS_HasMVEInt, // MVE_VLDRBU32_pre = 1252 |
| 18648 | CEFBS_HasMVEInt, // MVE_VLDRBU32_rq = 1253 |
| 18649 | CEFBS_HasMVEInt, // MVE_VLDRBU8 = 1254 |
| 18650 | CEFBS_HasMVEInt, // MVE_VLDRBU8_post = 1255 |
| 18651 | CEFBS_HasMVEInt, // MVE_VLDRBU8_pre = 1256 |
| 18652 | CEFBS_HasMVEInt, // MVE_VLDRBU8_rq = 1257 |
| 18653 | CEFBS_HasMVEInt, // MVE_VLDRDU64_qi = 1258 |
| 18654 | CEFBS_HasMVEInt, // MVE_VLDRDU64_qi_pre = 1259 |
| 18655 | CEFBS_HasMVEInt, // MVE_VLDRDU64_rq = 1260 |
| 18656 | CEFBS_HasMVEInt, // MVE_VLDRDU64_rq_u = 1261 |
| 18657 | CEFBS_HasMVEInt, // MVE_VLDRHS32 = 1262 |
| 18658 | CEFBS_HasMVEInt, // MVE_VLDRHS32_post = 1263 |
| 18659 | CEFBS_HasMVEInt, // MVE_VLDRHS32_pre = 1264 |
| 18660 | CEFBS_HasMVEInt, // MVE_VLDRHS32_rq = 1265 |
| 18661 | CEFBS_HasMVEInt, // MVE_VLDRHS32_rq_u = 1266 |
| 18662 | CEFBS_HasMVEInt, // MVE_VLDRHU16 = 1267 |
| 18663 | CEFBS_HasMVEInt, // MVE_VLDRHU16_post = 1268 |
| 18664 | CEFBS_HasMVEInt, // MVE_VLDRHU16_pre = 1269 |
| 18665 | CEFBS_HasMVEInt, // MVE_VLDRHU16_rq = 1270 |
| 18666 | CEFBS_HasMVEInt, // MVE_VLDRHU16_rq_u = 1271 |
| 18667 | CEFBS_HasMVEInt, // MVE_VLDRHU32 = 1272 |
| 18668 | CEFBS_HasMVEInt, // MVE_VLDRHU32_post = 1273 |
| 18669 | CEFBS_HasMVEInt, // MVE_VLDRHU32_pre = 1274 |
| 18670 | CEFBS_HasMVEInt, // MVE_VLDRHU32_rq = 1275 |
| 18671 | CEFBS_HasMVEInt, // MVE_VLDRHU32_rq_u = 1276 |
| 18672 | CEFBS_HasMVEInt, // MVE_VLDRWU32 = 1277 |
| 18673 | CEFBS_HasMVEInt, // MVE_VLDRWU32_post = 1278 |
| 18674 | CEFBS_HasMVEInt, // MVE_VLDRWU32_pre = 1279 |
| 18675 | CEFBS_HasMVEInt, // MVE_VLDRWU32_qi = 1280 |
| 18676 | CEFBS_HasMVEInt, // MVE_VLDRWU32_qi_pre = 1281 |
| 18677 | CEFBS_HasMVEInt, // MVE_VLDRWU32_rq = 1282 |
| 18678 | CEFBS_HasMVEInt, // MVE_VLDRWU32_rq_u = 1283 |
| 18679 | CEFBS_HasMVEInt, // MVE_VMAXAVs16 = 1284 |
| 18680 | CEFBS_HasMVEInt, // MVE_VMAXAVs32 = 1285 |
| 18681 | CEFBS_HasMVEInt, // MVE_VMAXAVs8 = 1286 |
| 18682 | CEFBS_HasMVEInt, // MVE_VMAXAs16 = 1287 |
| 18683 | CEFBS_HasMVEInt, // MVE_VMAXAs32 = 1288 |
| 18684 | CEFBS_HasMVEInt, // MVE_VMAXAs8 = 1289 |
| 18685 | CEFBS_HasMVEFloat, // MVE_VMAXNMAVf16 = 1290 |
| 18686 | CEFBS_HasMVEFloat, // MVE_VMAXNMAVf32 = 1291 |
| 18687 | CEFBS_HasMVEFloat, // MVE_VMAXNMAf16 = 1292 |
| 18688 | CEFBS_HasMVEFloat, // MVE_VMAXNMAf32 = 1293 |
| 18689 | CEFBS_HasMVEFloat, // MVE_VMAXNMVf16 = 1294 |
| 18690 | CEFBS_HasMVEFloat, // MVE_VMAXNMVf32 = 1295 |
| 18691 | CEFBS_HasMVEFloat, // MVE_VMAXNMf16 = 1296 |
| 18692 | CEFBS_HasMVEFloat, // MVE_VMAXNMf32 = 1297 |
| 18693 | CEFBS_HasMVEInt, // MVE_VMAXVs16 = 1298 |
| 18694 | CEFBS_HasMVEInt, // MVE_VMAXVs32 = 1299 |
| 18695 | CEFBS_HasMVEInt, // MVE_VMAXVs8 = 1300 |
| 18696 | CEFBS_HasMVEInt, // MVE_VMAXVu16 = 1301 |
| 18697 | CEFBS_HasMVEInt, // MVE_VMAXVu32 = 1302 |
| 18698 | CEFBS_HasMVEInt, // MVE_VMAXVu8 = 1303 |
| 18699 | CEFBS_HasMVEInt, // MVE_VMAXs16 = 1304 |
| 18700 | CEFBS_HasMVEInt, // MVE_VMAXs32 = 1305 |
| 18701 | CEFBS_HasMVEInt, // MVE_VMAXs8 = 1306 |
| 18702 | CEFBS_HasMVEInt, // MVE_VMAXu16 = 1307 |
| 18703 | CEFBS_HasMVEInt, // MVE_VMAXu32 = 1308 |
| 18704 | CEFBS_HasMVEInt, // MVE_VMAXu8 = 1309 |
| 18705 | CEFBS_HasMVEInt, // MVE_VMINAVs16 = 1310 |
| 18706 | CEFBS_HasMVEInt, // MVE_VMINAVs32 = 1311 |
| 18707 | CEFBS_HasMVEInt, // MVE_VMINAVs8 = 1312 |
| 18708 | CEFBS_HasMVEInt, // MVE_VMINAs16 = 1313 |
| 18709 | CEFBS_HasMVEInt, // MVE_VMINAs32 = 1314 |
| 18710 | CEFBS_HasMVEInt, // MVE_VMINAs8 = 1315 |
| 18711 | CEFBS_HasMVEFloat, // MVE_VMINNMAVf16 = 1316 |
| 18712 | CEFBS_HasMVEFloat, // MVE_VMINNMAVf32 = 1317 |
| 18713 | CEFBS_HasMVEFloat, // MVE_VMINNMAf16 = 1318 |
| 18714 | CEFBS_HasMVEFloat, // MVE_VMINNMAf32 = 1319 |
| 18715 | CEFBS_HasMVEFloat, // MVE_VMINNMVf16 = 1320 |
| 18716 | CEFBS_HasMVEFloat, // MVE_VMINNMVf32 = 1321 |
| 18717 | CEFBS_HasMVEFloat, // MVE_VMINNMf16 = 1322 |
| 18718 | CEFBS_HasMVEFloat, // MVE_VMINNMf32 = 1323 |
| 18719 | CEFBS_HasMVEInt, // MVE_VMINVs16 = 1324 |
| 18720 | CEFBS_HasMVEInt, // MVE_VMINVs32 = 1325 |
| 18721 | CEFBS_HasMVEInt, // MVE_VMINVs8 = 1326 |
| 18722 | CEFBS_HasMVEInt, // MVE_VMINVu16 = 1327 |
| 18723 | CEFBS_HasMVEInt, // MVE_VMINVu32 = 1328 |
| 18724 | CEFBS_HasMVEInt, // MVE_VMINVu8 = 1329 |
| 18725 | CEFBS_HasMVEInt, // MVE_VMINs16 = 1330 |
| 18726 | CEFBS_HasMVEInt, // MVE_VMINs32 = 1331 |
| 18727 | CEFBS_HasMVEInt, // MVE_VMINs8 = 1332 |
| 18728 | CEFBS_HasMVEInt, // MVE_VMINu16 = 1333 |
| 18729 | CEFBS_HasMVEInt, // MVE_VMINu32 = 1334 |
| 18730 | CEFBS_HasMVEInt, // MVE_VMINu8 = 1335 |
| 18731 | CEFBS_HasMVEInt, // MVE_VMLADAVas16 = 1336 |
| 18732 | CEFBS_HasMVEInt, // MVE_VMLADAVas32 = 1337 |
| 18733 | CEFBS_HasMVEInt, // MVE_VMLADAVas8 = 1338 |
| 18734 | CEFBS_HasMVEInt, // MVE_VMLADAVau16 = 1339 |
| 18735 | CEFBS_HasMVEInt, // MVE_VMLADAVau32 = 1340 |
| 18736 | CEFBS_HasMVEInt, // MVE_VMLADAVau8 = 1341 |
| 18737 | CEFBS_HasMVEInt, // MVE_VMLADAVaxs16 = 1342 |
| 18738 | CEFBS_HasMVEInt, // MVE_VMLADAVaxs32 = 1343 |
| 18739 | CEFBS_HasMVEInt, // MVE_VMLADAVaxs8 = 1344 |
| 18740 | CEFBS_HasMVEInt, // MVE_VMLADAVs16 = 1345 |
| 18741 | CEFBS_HasMVEInt, // MVE_VMLADAVs32 = 1346 |
| 18742 | CEFBS_HasMVEInt, // MVE_VMLADAVs8 = 1347 |
| 18743 | CEFBS_HasMVEInt, // MVE_VMLADAVu16 = 1348 |
| 18744 | CEFBS_HasMVEInt, // MVE_VMLADAVu32 = 1349 |
| 18745 | CEFBS_HasMVEInt, // MVE_VMLADAVu8 = 1350 |
| 18746 | CEFBS_HasMVEInt, // MVE_VMLADAVxs16 = 1351 |
| 18747 | CEFBS_HasMVEInt, // MVE_VMLADAVxs32 = 1352 |
| 18748 | CEFBS_HasMVEInt, // MVE_VMLADAVxs8 = 1353 |
| 18749 | CEFBS_HasMVEInt, // MVE_VMLALDAVas16 = 1354 |
| 18750 | CEFBS_HasMVEInt, // MVE_VMLALDAVas32 = 1355 |
| 18751 | CEFBS_HasMVEInt, // MVE_VMLALDAVau16 = 1356 |
| 18752 | CEFBS_HasMVEInt, // MVE_VMLALDAVau32 = 1357 |
| 18753 | CEFBS_HasMVEInt, // MVE_VMLALDAVaxs16 = 1358 |
| 18754 | CEFBS_HasMVEInt, // MVE_VMLALDAVaxs32 = 1359 |
| 18755 | CEFBS_HasMVEInt, // MVE_VMLALDAVs16 = 1360 |
| 18756 | CEFBS_HasMVEInt, // MVE_VMLALDAVs32 = 1361 |
| 18757 | CEFBS_HasMVEInt, // MVE_VMLALDAVu16 = 1362 |
| 18758 | CEFBS_HasMVEInt, // MVE_VMLALDAVu32 = 1363 |
| 18759 | CEFBS_HasMVEInt, // MVE_VMLALDAVxs16 = 1364 |
| 18760 | CEFBS_HasMVEInt, // MVE_VMLALDAVxs32 = 1365 |
| 18761 | CEFBS_HasMVEInt, // MVE_VMLAS_qr_i16 = 1366 |
| 18762 | CEFBS_HasMVEInt, // MVE_VMLAS_qr_i32 = 1367 |
| 18763 | CEFBS_HasMVEInt, // MVE_VMLAS_qr_i8 = 1368 |
| 18764 | CEFBS_HasMVEInt, // MVE_VMLA_qr_i16 = 1369 |
| 18765 | CEFBS_HasMVEInt, // MVE_VMLA_qr_i32 = 1370 |
| 18766 | CEFBS_HasMVEInt, // MVE_VMLA_qr_i8 = 1371 |
| 18767 | CEFBS_HasMVEInt, // MVE_VMLSDAVas16 = 1372 |
| 18768 | CEFBS_HasMVEInt, // MVE_VMLSDAVas32 = 1373 |
| 18769 | CEFBS_HasMVEInt, // MVE_VMLSDAVas8 = 1374 |
| 18770 | CEFBS_HasMVEInt, // MVE_VMLSDAVaxs16 = 1375 |
| 18771 | CEFBS_HasMVEInt, // MVE_VMLSDAVaxs32 = 1376 |
| 18772 | CEFBS_HasMVEInt, // MVE_VMLSDAVaxs8 = 1377 |
| 18773 | CEFBS_HasMVEInt, // MVE_VMLSDAVs16 = 1378 |
| 18774 | CEFBS_HasMVEInt, // MVE_VMLSDAVs32 = 1379 |
| 18775 | CEFBS_HasMVEInt, // MVE_VMLSDAVs8 = 1380 |
| 18776 | CEFBS_HasMVEInt, // MVE_VMLSDAVxs16 = 1381 |
| 18777 | CEFBS_HasMVEInt, // MVE_VMLSDAVxs32 = 1382 |
| 18778 | CEFBS_HasMVEInt, // MVE_VMLSDAVxs8 = 1383 |
| 18779 | CEFBS_HasMVEInt, // MVE_VMLSLDAVas16 = 1384 |
| 18780 | CEFBS_HasMVEInt, // MVE_VMLSLDAVas32 = 1385 |
| 18781 | CEFBS_HasMVEInt, // MVE_VMLSLDAVaxs16 = 1386 |
| 18782 | CEFBS_HasMVEInt, // MVE_VMLSLDAVaxs32 = 1387 |
| 18783 | CEFBS_HasMVEInt, // MVE_VMLSLDAVs16 = 1388 |
| 18784 | CEFBS_HasMVEInt, // MVE_VMLSLDAVs32 = 1389 |
| 18785 | CEFBS_HasMVEInt, // MVE_VMLSLDAVxs16 = 1390 |
| 18786 | CEFBS_HasMVEInt, // MVE_VMLSLDAVxs32 = 1391 |
| 18787 | CEFBS_HasMVEInt, // MVE_VMOVLs16bh = 1392 |
| 18788 | CEFBS_HasMVEInt, // MVE_VMOVLs16th = 1393 |
| 18789 | CEFBS_HasMVEInt, // MVE_VMOVLs8bh = 1394 |
| 18790 | CEFBS_HasMVEInt, // MVE_VMOVLs8th = 1395 |
| 18791 | CEFBS_HasMVEInt, // MVE_VMOVLu16bh = 1396 |
| 18792 | CEFBS_HasMVEInt, // MVE_VMOVLu16th = 1397 |
| 18793 | CEFBS_HasMVEInt, // MVE_VMOVLu8bh = 1398 |
| 18794 | CEFBS_HasMVEInt, // MVE_VMOVLu8th = 1399 |
| 18795 | CEFBS_HasMVEInt, // MVE_VMOVNi16bh = 1400 |
| 18796 | CEFBS_HasMVEInt, // MVE_VMOVNi16th = 1401 |
| 18797 | CEFBS_HasMVEInt, // MVE_VMOVNi32bh = 1402 |
| 18798 | CEFBS_HasMVEInt, // MVE_VMOVNi32th = 1403 |
| 18799 | CEFBS_HasFPRegsV8_1M, // MVE_VMOV_from_lane_32 = 1404 |
| 18800 | CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_VMOV_from_lane_s16 = 1405 |
| 18801 | CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_VMOV_from_lane_s8 = 1406 |
| 18802 | CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_VMOV_from_lane_u16 = 1407 |
| 18803 | CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_VMOV_from_lane_u8 = 1408 |
| 18804 | CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_VMOV_q_rr = 1409 |
| 18805 | CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_VMOV_rr_q = 1410 |
| 18806 | CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_VMOV_to_lane_16 = 1411 |
| 18807 | CEFBS_HasFPRegsV8_1M, // MVE_VMOV_to_lane_32 = 1412 |
| 18808 | CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_VMOV_to_lane_8 = 1413 |
| 18809 | CEFBS_HasMVEInt, // MVE_VMOVimmf32 = 1414 |
| 18810 | CEFBS_HasMVEInt, // MVE_VMOVimmi16 = 1415 |
| 18811 | CEFBS_HasMVEInt, // MVE_VMOVimmi32 = 1416 |
| 18812 | CEFBS_HasMVEInt, // MVE_VMOVimmi64 = 1417 |
| 18813 | CEFBS_HasMVEInt, // MVE_VMOVimmi8 = 1418 |
| 18814 | CEFBS_HasMVEInt, // MVE_VMULHs16 = 1419 |
| 18815 | CEFBS_HasMVEInt, // MVE_VMULHs32 = 1420 |
| 18816 | CEFBS_HasMVEInt, // MVE_VMULHs8 = 1421 |
| 18817 | CEFBS_HasMVEInt, // MVE_VMULHu16 = 1422 |
| 18818 | CEFBS_HasMVEInt, // MVE_VMULHu32 = 1423 |
| 18819 | CEFBS_HasMVEInt, // MVE_VMULHu8 = 1424 |
| 18820 | CEFBS_HasMVEInt, // MVE_VMULLBp16 = 1425 |
| 18821 | CEFBS_HasMVEInt, // MVE_VMULLBp8 = 1426 |
| 18822 | CEFBS_HasMVEInt, // MVE_VMULLBs16 = 1427 |
| 18823 | CEFBS_HasMVEInt, // MVE_VMULLBs32 = 1428 |
| 18824 | CEFBS_HasMVEInt, // MVE_VMULLBs8 = 1429 |
| 18825 | CEFBS_HasMVEInt, // MVE_VMULLBu16 = 1430 |
| 18826 | CEFBS_HasMVEInt, // MVE_VMULLBu32 = 1431 |
| 18827 | CEFBS_HasMVEInt, // MVE_VMULLBu8 = 1432 |
| 18828 | CEFBS_HasMVEInt, // MVE_VMULLTp16 = 1433 |
| 18829 | CEFBS_HasMVEInt, // MVE_VMULLTp8 = 1434 |
| 18830 | CEFBS_HasMVEInt, // MVE_VMULLTs16 = 1435 |
| 18831 | CEFBS_HasMVEInt, // MVE_VMULLTs32 = 1436 |
| 18832 | CEFBS_HasMVEInt, // MVE_VMULLTs8 = 1437 |
| 18833 | CEFBS_HasMVEInt, // MVE_VMULLTu16 = 1438 |
| 18834 | CEFBS_HasMVEInt, // MVE_VMULLTu32 = 1439 |
| 18835 | CEFBS_HasMVEInt, // MVE_VMULLTu8 = 1440 |
| 18836 | CEFBS_HasMVEFloat, // MVE_VMUL_qr_f16 = 1441 |
| 18837 | CEFBS_HasMVEFloat, // MVE_VMUL_qr_f32 = 1442 |
| 18838 | CEFBS_HasMVEInt, // MVE_VMUL_qr_i16 = 1443 |
| 18839 | CEFBS_HasMVEInt, // MVE_VMUL_qr_i32 = 1444 |
| 18840 | CEFBS_HasMVEInt, // MVE_VMUL_qr_i8 = 1445 |
| 18841 | CEFBS_HasMVEFloat, // MVE_VMULf16 = 1446 |
| 18842 | CEFBS_HasMVEFloat, // MVE_VMULf32 = 1447 |
| 18843 | CEFBS_HasMVEInt, // MVE_VMULi16 = 1448 |
| 18844 | CEFBS_HasMVEInt, // MVE_VMULi32 = 1449 |
| 18845 | CEFBS_HasMVEInt, // MVE_VMULi8 = 1450 |
| 18846 | CEFBS_HasMVEInt, // MVE_VMVN = 1451 |
| 18847 | CEFBS_HasMVEInt, // MVE_VMVNimmi16 = 1452 |
| 18848 | CEFBS_HasMVEInt, // MVE_VMVNimmi32 = 1453 |
| 18849 | CEFBS_HasMVEFloat, // MVE_VNEGf16 = 1454 |
| 18850 | CEFBS_HasMVEFloat, // MVE_VNEGf32 = 1455 |
| 18851 | CEFBS_HasMVEInt, // MVE_VNEGs16 = 1456 |
| 18852 | CEFBS_HasMVEInt, // MVE_VNEGs32 = 1457 |
| 18853 | CEFBS_HasMVEInt, // MVE_VNEGs8 = 1458 |
| 18854 | CEFBS_HasMVEInt, // MVE_VORN = 1459 |
| 18855 | CEFBS_HasMVEInt, // MVE_VORR = 1460 |
| 18856 | CEFBS_HasMVEInt, // MVE_VORRimmi16 = 1461 |
| 18857 | CEFBS_HasMVEInt, // MVE_VORRimmi32 = 1462 |
| 18858 | CEFBS_HasMVEInt, // MVE_VPNOT = 1463 |
| 18859 | CEFBS_HasMVEInt, // MVE_VPSEL = 1464 |
| 18860 | CEFBS_HasMVEInt, // MVE_VPST = 1465 |
| 18861 | CEFBS_HasMVEInt, // MVE_VPTv16i8 = 1466 |
| 18862 | CEFBS_HasMVEInt, // MVE_VPTv16i8r = 1467 |
| 18863 | CEFBS_HasMVEInt, // MVE_VPTv16s8 = 1468 |
| 18864 | CEFBS_HasMVEInt, // MVE_VPTv16s8r = 1469 |
| 18865 | CEFBS_HasMVEInt, // MVE_VPTv16u8 = 1470 |
| 18866 | CEFBS_HasMVEInt, // MVE_VPTv16u8r = 1471 |
| 18867 | CEFBS_HasMVEFloat, // MVE_VPTv4f32 = 1472 |
| 18868 | CEFBS_HasMVEFloat, // MVE_VPTv4f32r = 1473 |
| 18869 | CEFBS_HasMVEInt, // MVE_VPTv4i32 = 1474 |
| 18870 | CEFBS_HasMVEInt, // MVE_VPTv4i32r = 1475 |
| 18871 | CEFBS_HasMVEInt, // MVE_VPTv4s32 = 1476 |
| 18872 | CEFBS_HasMVEInt, // MVE_VPTv4s32r = 1477 |
| 18873 | CEFBS_HasMVEInt, // MVE_VPTv4u32 = 1478 |
| 18874 | CEFBS_HasMVEInt, // MVE_VPTv4u32r = 1479 |
| 18875 | CEFBS_HasMVEFloat, // MVE_VPTv8f16 = 1480 |
| 18876 | CEFBS_HasMVEFloat, // MVE_VPTv8f16r = 1481 |
| 18877 | CEFBS_HasMVEInt, // MVE_VPTv8i16 = 1482 |
| 18878 | CEFBS_HasMVEInt, // MVE_VPTv8i16r = 1483 |
| 18879 | CEFBS_HasMVEInt, // MVE_VPTv8s16 = 1484 |
| 18880 | CEFBS_HasMVEInt, // MVE_VPTv8s16r = 1485 |
| 18881 | CEFBS_HasMVEInt, // MVE_VPTv8u16 = 1486 |
| 18882 | CEFBS_HasMVEInt, // MVE_VPTv8u16r = 1487 |
| 18883 | CEFBS_HasMVEInt, // MVE_VQABSs16 = 1488 |
| 18884 | CEFBS_HasMVEInt, // MVE_VQABSs32 = 1489 |
| 18885 | CEFBS_HasMVEInt, // MVE_VQABSs8 = 1490 |
| 18886 | CEFBS_HasMVEInt, // MVE_VQADD_qr_s16 = 1491 |
| 18887 | CEFBS_HasMVEInt, // MVE_VQADD_qr_s32 = 1492 |
| 18888 | CEFBS_HasMVEInt, // MVE_VQADD_qr_s8 = 1493 |
| 18889 | CEFBS_HasMVEInt, // MVE_VQADD_qr_u16 = 1494 |
| 18890 | CEFBS_HasMVEInt, // MVE_VQADD_qr_u32 = 1495 |
| 18891 | CEFBS_HasMVEInt, // MVE_VQADD_qr_u8 = 1496 |
| 18892 | CEFBS_HasMVEInt, // MVE_VQADDs16 = 1497 |
| 18893 | CEFBS_HasMVEInt, // MVE_VQADDs32 = 1498 |
| 18894 | CEFBS_HasMVEInt, // MVE_VQADDs8 = 1499 |
| 18895 | CEFBS_HasMVEInt, // MVE_VQADDu16 = 1500 |
| 18896 | CEFBS_HasMVEInt, // MVE_VQADDu32 = 1501 |
| 18897 | CEFBS_HasMVEInt, // MVE_VQADDu8 = 1502 |
| 18898 | CEFBS_HasMVEInt, // MVE_VQDMLADHXs16 = 1503 |
| 18899 | CEFBS_HasMVEInt, // MVE_VQDMLADHXs32 = 1504 |
| 18900 | CEFBS_HasMVEInt, // MVE_VQDMLADHXs8 = 1505 |
| 18901 | CEFBS_HasMVEInt, // MVE_VQDMLADHs16 = 1506 |
| 18902 | CEFBS_HasMVEInt, // MVE_VQDMLADHs32 = 1507 |
| 18903 | CEFBS_HasMVEInt, // MVE_VQDMLADHs8 = 1508 |
| 18904 | CEFBS_HasMVEInt, // MVE_VQDMLAH_qrs16 = 1509 |
| 18905 | CEFBS_HasMVEInt, // MVE_VQDMLAH_qrs32 = 1510 |
| 18906 | CEFBS_HasMVEInt, // MVE_VQDMLAH_qrs8 = 1511 |
| 18907 | CEFBS_HasMVEInt, // MVE_VQDMLASH_qrs16 = 1512 |
| 18908 | CEFBS_HasMVEInt, // MVE_VQDMLASH_qrs32 = 1513 |
| 18909 | CEFBS_HasMVEInt, // MVE_VQDMLASH_qrs8 = 1514 |
| 18910 | CEFBS_HasMVEInt, // MVE_VQDMLSDHXs16 = 1515 |
| 18911 | CEFBS_HasMVEInt, // MVE_VQDMLSDHXs32 = 1516 |
| 18912 | CEFBS_HasMVEInt, // MVE_VQDMLSDHXs8 = 1517 |
| 18913 | CEFBS_HasMVEInt, // MVE_VQDMLSDHs16 = 1518 |
| 18914 | CEFBS_HasMVEInt, // MVE_VQDMLSDHs32 = 1519 |
| 18915 | CEFBS_HasMVEInt, // MVE_VQDMLSDHs8 = 1520 |
| 18916 | CEFBS_HasMVEInt, // MVE_VQDMULH_qr_s16 = 1521 |
| 18917 | CEFBS_HasMVEInt, // MVE_VQDMULH_qr_s32 = 1522 |
| 18918 | CEFBS_HasMVEInt, // MVE_VQDMULH_qr_s8 = 1523 |
| 18919 | CEFBS_HasMVEInt, // MVE_VQDMULHi16 = 1524 |
| 18920 | CEFBS_HasMVEInt, // MVE_VQDMULHi32 = 1525 |
| 18921 | CEFBS_HasMVEInt, // MVE_VQDMULHi8 = 1526 |
| 18922 | CEFBS_HasMVEInt, // MVE_VQDMULL_qr_s16bh = 1527 |
| 18923 | CEFBS_HasMVEInt, // MVE_VQDMULL_qr_s16th = 1528 |
| 18924 | CEFBS_HasMVEInt, // MVE_VQDMULL_qr_s32bh = 1529 |
| 18925 | CEFBS_HasMVEInt, // MVE_VQDMULL_qr_s32th = 1530 |
| 18926 | CEFBS_HasMVEInt, // MVE_VQDMULLs16bh = 1531 |
| 18927 | CEFBS_HasMVEInt, // MVE_VQDMULLs16th = 1532 |
| 18928 | CEFBS_HasMVEInt, // MVE_VQDMULLs32bh = 1533 |
| 18929 | CEFBS_HasMVEInt, // MVE_VQDMULLs32th = 1534 |
| 18930 | CEFBS_HasMVEInt, // MVE_VQMOVNs16bh = 1535 |
| 18931 | CEFBS_HasMVEInt, // MVE_VQMOVNs16th = 1536 |
| 18932 | CEFBS_HasMVEInt, // MVE_VQMOVNs32bh = 1537 |
| 18933 | CEFBS_HasMVEInt, // MVE_VQMOVNs32th = 1538 |
| 18934 | CEFBS_HasMVEInt, // MVE_VQMOVNu16bh = 1539 |
| 18935 | CEFBS_HasMVEInt, // MVE_VQMOVNu16th = 1540 |
| 18936 | CEFBS_HasMVEInt, // MVE_VQMOVNu32bh = 1541 |
| 18937 | CEFBS_HasMVEInt, // MVE_VQMOVNu32th = 1542 |
| 18938 | CEFBS_HasMVEInt, // MVE_VQMOVUNs16bh = 1543 |
| 18939 | CEFBS_HasMVEInt, // MVE_VQMOVUNs16th = 1544 |
| 18940 | CEFBS_HasMVEInt, // MVE_VQMOVUNs32bh = 1545 |
| 18941 | CEFBS_HasMVEInt, // MVE_VQMOVUNs32th = 1546 |
| 18942 | CEFBS_HasMVEInt, // MVE_VQNEGs16 = 1547 |
| 18943 | CEFBS_HasMVEInt, // MVE_VQNEGs32 = 1548 |
| 18944 | CEFBS_HasMVEInt, // MVE_VQNEGs8 = 1549 |
| 18945 | CEFBS_HasMVEInt, // MVE_VQRDMLADHXs16 = 1550 |
| 18946 | CEFBS_HasMVEInt, // MVE_VQRDMLADHXs32 = 1551 |
| 18947 | CEFBS_HasMVEInt, // MVE_VQRDMLADHXs8 = 1552 |
| 18948 | CEFBS_HasMVEInt, // MVE_VQRDMLADHs16 = 1553 |
| 18949 | CEFBS_HasMVEInt, // MVE_VQRDMLADHs32 = 1554 |
| 18950 | CEFBS_HasMVEInt, // MVE_VQRDMLADHs8 = 1555 |
| 18951 | CEFBS_HasMVEInt, // MVE_VQRDMLAH_qrs16 = 1556 |
| 18952 | CEFBS_HasMVEInt, // MVE_VQRDMLAH_qrs32 = 1557 |
| 18953 | CEFBS_HasMVEInt, // MVE_VQRDMLAH_qrs8 = 1558 |
| 18954 | CEFBS_HasMVEInt, // MVE_VQRDMLASH_qrs16 = 1559 |
| 18955 | CEFBS_HasMVEInt, // MVE_VQRDMLASH_qrs32 = 1560 |
| 18956 | CEFBS_HasMVEInt, // MVE_VQRDMLASH_qrs8 = 1561 |
| 18957 | CEFBS_HasMVEInt, // MVE_VQRDMLSDHXs16 = 1562 |
| 18958 | CEFBS_HasMVEInt, // MVE_VQRDMLSDHXs32 = 1563 |
| 18959 | CEFBS_HasMVEInt, // MVE_VQRDMLSDHXs8 = 1564 |
| 18960 | CEFBS_HasMVEInt, // MVE_VQRDMLSDHs16 = 1565 |
| 18961 | CEFBS_HasMVEInt, // MVE_VQRDMLSDHs32 = 1566 |
| 18962 | CEFBS_HasMVEInt, // MVE_VQRDMLSDHs8 = 1567 |
| 18963 | CEFBS_HasMVEInt, // MVE_VQRDMULH_qr_s16 = 1568 |
| 18964 | CEFBS_HasMVEInt, // MVE_VQRDMULH_qr_s32 = 1569 |
| 18965 | CEFBS_HasMVEInt, // MVE_VQRDMULH_qr_s8 = 1570 |
| 18966 | CEFBS_HasMVEInt, // MVE_VQRDMULHi16 = 1571 |
| 18967 | CEFBS_HasMVEInt, // MVE_VQRDMULHi32 = 1572 |
| 18968 | CEFBS_HasMVEInt, // MVE_VQRDMULHi8 = 1573 |
| 18969 | CEFBS_HasMVEInt, // MVE_VQRSHL_by_vecs16 = 1574 |
| 18970 | CEFBS_HasMVEInt, // MVE_VQRSHL_by_vecs32 = 1575 |
| 18971 | CEFBS_HasMVEInt, // MVE_VQRSHL_by_vecs8 = 1576 |
| 18972 | CEFBS_HasMVEInt, // MVE_VQRSHL_by_vecu16 = 1577 |
| 18973 | CEFBS_HasMVEInt, // MVE_VQRSHL_by_vecu32 = 1578 |
| 18974 | CEFBS_HasMVEInt, // MVE_VQRSHL_by_vecu8 = 1579 |
| 18975 | CEFBS_HasMVEInt, // MVE_VQRSHL_qrs16 = 1580 |
| 18976 | CEFBS_HasMVEInt, // MVE_VQRSHL_qrs32 = 1581 |
| 18977 | CEFBS_HasMVEInt, // MVE_VQRSHL_qrs8 = 1582 |
| 18978 | CEFBS_HasMVEInt, // MVE_VQRSHL_qru16 = 1583 |
| 18979 | CEFBS_HasMVEInt, // MVE_VQRSHL_qru32 = 1584 |
| 18980 | CEFBS_HasMVEInt, // MVE_VQRSHL_qru8 = 1585 |
| 18981 | CEFBS_HasMVEInt, // MVE_VQRSHRNbhs16 = 1586 |
| 18982 | CEFBS_HasMVEInt, // MVE_VQRSHRNbhs32 = 1587 |
| 18983 | CEFBS_HasMVEInt, // MVE_VQRSHRNbhu16 = 1588 |
| 18984 | CEFBS_HasMVEInt, // MVE_VQRSHRNbhu32 = 1589 |
| 18985 | CEFBS_HasMVEInt, // MVE_VQRSHRNths16 = 1590 |
| 18986 | CEFBS_HasMVEInt, // MVE_VQRSHRNths32 = 1591 |
| 18987 | CEFBS_HasMVEInt, // MVE_VQRSHRNthu16 = 1592 |
| 18988 | CEFBS_HasMVEInt, // MVE_VQRSHRNthu32 = 1593 |
| 18989 | CEFBS_HasMVEInt, // MVE_VQRSHRUNs16bh = 1594 |
| 18990 | CEFBS_HasMVEInt, // MVE_VQRSHRUNs16th = 1595 |
| 18991 | CEFBS_HasMVEInt, // MVE_VQRSHRUNs32bh = 1596 |
| 18992 | CEFBS_HasMVEInt, // MVE_VQRSHRUNs32th = 1597 |
| 18993 | CEFBS_HasMVEInt, // MVE_VQSHLU_imms16 = 1598 |
| 18994 | CEFBS_HasMVEInt, // MVE_VQSHLU_imms32 = 1599 |
| 18995 | CEFBS_HasMVEInt, // MVE_VQSHLU_imms8 = 1600 |
| 18996 | CEFBS_HasMVEInt, // MVE_VQSHL_by_vecs16 = 1601 |
| 18997 | CEFBS_HasMVEInt, // MVE_VQSHL_by_vecs32 = 1602 |
| 18998 | CEFBS_HasMVEInt, // MVE_VQSHL_by_vecs8 = 1603 |
| 18999 | CEFBS_HasMVEInt, // MVE_VQSHL_by_vecu16 = 1604 |
| 19000 | CEFBS_HasMVEInt, // MVE_VQSHL_by_vecu32 = 1605 |
| 19001 | CEFBS_HasMVEInt, // MVE_VQSHL_by_vecu8 = 1606 |
| 19002 | CEFBS_HasMVEInt, // MVE_VQSHL_qrs16 = 1607 |
| 19003 | CEFBS_HasMVEInt, // MVE_VQSHL_qrs32 = 1608 |
| 19004 | CEFBS_HasMVEInt, // MVE_VQSHL_qrs8 = 1609 |
| 19005 | CEFBS_HasMVEInt, // MVE_VQSHL_qru16 = 1610 |
| 19006 | CEFBS_HasMVEInt, // MVE_VQSHL_qru32 = 1611 |
| 19007 | CEFBS_HasMVEInt, // MVE_VQSHL_qru8 = 1612 |
| 19008 | CEFBS_HasMVEInt, // MVE_VQSHLimms16 = 1613 |
| 19009 | CEFBS_HasMVEInt, // MVE_VQSHLimms32 = 1614 |
| 19010 | CEFBS_HasMVEInt, // MVE_VQSHLimms8 = 1615 |
| 19011 | CEFBS_HasMVEInt, // MVE_VQSHLimmu16 = 1616 |
| 19012 | CEFBS_HasMVEInt, // MVE_VQSHLimmu32 = 1617 |
| 19013 | CEFBS_HasMVEInt, // MVE_VQSHLimmu8 = 1618 |
| 19014 | CEFBS_HasMVEInt, // MVE_VQSHRNbhs16 = 1619 |
| 19015 | CEFBS_HasMVEInt, // MVE_VQSHRNbhs32 = 1620 |
| 19016 | CEFBS_HasMVEInt, // MVE_VQSHRNbhu16 = 1621 |
| 19017 | CEFBS_HasMVEInt, // MVE_VQSHRNbhu32 = 1622 |
| 19018 | CEFBS_HasMVEInt, // MVE_VQSHRNths16 = 1623 |
| 19019 | CEFBS_HasMVEInt, // MVE_VQSHRNths32 = 1624 |
| 19020 | CEFBS_HasMVEInt, // MVE_VQSHRNthu16 = 1625 |
| 19021 | CEFBS_HasMVEInt, // MVE_VQSHRNthu32 = 1626 |
| 19022 | CEFBS_HasMVEInt, // MVE_VQSHRUNs16bh = 1627 |
| 19023 | CEFBS_HasMVEInt, // MVE_VQSHRUNs16th = 1628 |
| 19024 | CEFBS_HasMVEInt, // MVE_VQSHRUNs32bh = 1629 |
| 19025 | CEFBS_HasMVEInt, // MVE_VQSHRUNs32th = 1630 |
| 19026 | CEFBS_HasMVEInt, // MVE_VQSUB_qr_s16 = 1631 |
| 19027 | CEFBS_HasMVEInt, // MVE_VQSUB_qr_s32 = 1632 |
| 19028 | CEFBS_HasMVEInt, // MVE_VQSUB_qr_s8 = 1633 |
| 19029 | CEFBS_HasMVEInt, // MVE_VQSUB_qr_u16 = 1634 |
| 19030 | CEFBS_HasMVEInt, // MVE_VQSUB_qr_u32 = 1635 |
| 19031 | CEFBS_HasMVEInt, // MVE_VQSUB_qr_u8 = 1636 |
| 19032 | CEFBS_HasMVEInt, // MVE_VQSUBs16 = 1637 |
| 19033 | CEFBS_HasMVEInt, // MVE_VQSUBs32 = 1638 |
| 19034 | CEFBS_HasMVEInt, // MVE_VQSUBs8 = 1639 |
| 19035 | CEFBS_HasMVEInt, // MVE_VQSUBu16 = 1640 |
| 19036 | CEFBS_HasMVEInt, // MVE_VQSUBu32 = 1641 |
| 19037 | CEFBS_HasMVEInt, // MVE_VQSUBu8 = 1642 |
| 19038 | CEFBS_HasMVEInt, // MVE_VREV16_8 = 1643 |
| 19039 | CEFBS_HasMVEInt, // MVE_VREV32_16 = 1644 |
| 19040 | CEFBS_HasMVEInt, // MVE_VREV32_8 = 1645 |
| 19041 | CEFBS_HasMVEInt, // MVE_VREV64_16 = 1646 |
| 19042 | CEFBS_HasMVEInt, // MVE_VREV64_32 = 1647 |
| 19043 | CEFBS_HasMVEInt, // MVE_VREV64_8 = 1648 |
| 19044 | CEFBS_HasMVEInt, // MVE_VRHADDs16 = 1649 |
| 19045 | CEFBS_HasMVEInt, // MVE_VRHADDs32 = 1650 |
| 19046 | CEFBS_HasMVEInt, // MVE_VRHADDs8 = 1651 |
| 19047 | CEFBS_HasMVEInt, // MVE_VRHADDu16 = 1652 |
| 19048 | CEFBS_HasMVEInt, // MVE_VRHADDu32 = 1653 |
| 19049 | CEFBS_HasMVEInt, // MVE_VRHADDu8 = 1654 |
| 19050 | CEFBS_HasMVEFloat, // MVE_VRINTf16A = 1655 |
| 19051 | CEFBS_HasMVEFloat, // MVE_VRINTf16M = 1656 |
| 19052 | CEFBS_HasMVEFloat, // MVE_VRINTf16N = 1657 |
| 19053 | CEFBS_HasMVEFloat, // MVE_VRINTf16P = 1658 |
| 19054 | CEFBS_HasMVEFloat, // MVE_VRINTf16X = 1659 |
| 19055 | CEFBS_HasMVEFloat, // MVE_VRINTf16Z = 1660 |
| 19056 | CEFBS_HasMVEFloat, // MVE_VRINTf32A = 1661 |
| 19057 | CEFBS_HasMVEFloat, // MVE_VRINTf32M = 1662 |
| 19058 | CEFBS_HasMVEFloat, // MVE_VRINTf32N = 1663 |
| 19059 | CEFBS_HasMVEFloat, // MVE_VRINTf32P = 1664 |
| 19060 | CEFBS_HasMVEFloat, // MVE_VRINTf32X = 1665 |
| 19061 | CEFBS_HasMVEFloat, // MVE_VRINTf32Z = 1666 |
| 19062 | CEFBS_HasMVEInt, // MVE_VRMLALDAVHas32 = 1667 |
| 19063 | CEFBS_HasMVEInt, // MVE_VRMLALDAVHau32 = 1668 |
| 19064 | CEFBS_HasMVEInt, // MVE_VRMLALDAVHaxs32 = 1669 |
| 19065 | CEFBS_HasMVEInt, // MVE_VRMLALDAVHs32 = 1670 |
| 19066 | CEFBS_HasMVEInt, // MVE_VRMLALDAVHu32 = 1671 |
| 19067 | CEFBS_HasMVEInt, // MVE_VRMLALDAVHxs32 = 1672 |
| 19068 | CEFBS_HasMVEInt, // MVE_VRMLSLDAVHas32 = 1673 |
| 19069 | CEFBS_HasMVEInt, // MVE_VRMLSLDAVHaxs32 = 1674 |
| 19070 | CEFBS_HasMVEInt, // MVE_VRMLSLDAVHs32 = 1675 |
| 19071 | CEFBS_HasMVEInt, // MVE_VRMLSLDAVHxs32 = 1676 |
| 19072 | CEFBS_HasMVEInt, // MVE_VRMULHs16 = 1677 |
| 19073 | CEFBS_HasMVEInt, // MVE_VRMULHs32 = 1678 |
| 19074 | CEFBS_HasMVEInt, // MVE_VRMULHs8 = 1679 |
| 19075 | CEFBS_HasMVEInt, // MVE_VRMULHu16 = 1680 |
| 19076 | CEFBS_HasMVEInt, // MVE_VRMULHu32 = 1681 |
| 19077 | CEFBS_HasMVEInt, // MVE_VRMULHu8 = 1682 |
| 19078 | CEFBS_HasMVEInt, // MVE_VRSHL_by_vecs16 = 1683 |
| 19079 | CEFBS_HasMVEInt, // MVE_VRSHL_by_vecs32 = 1684 |
| 19080 | CEFBS_HasMVEInt, // MVE_VRSHL_by_vecs8 = 1685 |
| 19081 | CEFBS_HasMVEInt, // MVE_VRSHL_by_vecu16 = 1686 |
| 19082 | CEFBS_HasMVEInt, // MVE_VRSHL_by_vecu32 = 1687 |
| 19083 | CEFBS_HasMVEInt, // MVE_VRSHL_by_vecu8 = 1688 |
| 19084 | CEFBS_HasMVEInt, // MVE_VRSHL_qrs16 = 1689 |
| 19085 | CEFBS_HasMVEInt, // MVE_VRSHL_qrs32 = 1690 |
| 19086 | CEFBS_HasMVEInt, // MVE_VRSHL_qrs8 = 1691 |
| 19087 | CEFBS_HasMVEInt, // MVE_VRSHL_qru16 = 1692 |
| 19088 | CEFBS_HasMVEInt, // MVE_VRSHL_qru32 = 1693 |
| 19089 | CEFBS_HasMVEInt, // MVE_VRSHL_qru8 = 1694 |
| 19090 | CEFBS_HasMVEInt, // MVE_VRSHRNi16bh = 1695 |
| 19091 | CEFBS_HasMVEInt, // MVE_VRSHRNi16th = 1696 |
| 19092 | CEFBS_HasMVEInt, // MVE_VRSHRNi32bh = 1697 |
| 19093 | CEFBS_HasMVEInt, // MVE_VRSHRNi32th = 1698 |
| 19094 | CEFBS_HasMVEInt, // MVE_VRSHR_imms16 = 1699 |
| 19095 | CEFBS_HasMVEInt, // MVE_VRSHR_imms32 = 1700 |
| 19096 | CEFBS_HasMVEInt, // MVE_VRSHR_imms8 = 1701 |
| 19097 | CEFBS_HasMVEInt, // MVE_VRSHR_immu16 = 1702 |
| 19098 | CEFBS_HasMVEInt, // MVE_VRSHR_immu32 = 1703 |
| 19099 | CEFBS_HasMVEInt, // MVE_VRSHR_immu8 = 1704 |
| 19100 | CEFBS_HasMVEInt, // MVE_VSBC = 1705 |
| 19101 | CEFBS_HasMVEInt, // MVE_VSBCI = 1706 |
| 19102 | CEFBS_HasMVEInt, // MVE_VSHLC = 1707 |
| 19103 | CEFBS_HasMVEInt, // MVE_VSHLL_imms16bh = 1708 |
| 19104 | CEFBS_HasMVEInt, // MVE_VSHLL_imms16th = 1709 |
| 19105 | CEFBS_HasMVEInt, // MVE_VSHLL_imms8bh = 1710 |
| 19106 | CEFBS_HasMVEInt, // MVE_VSHLL_imms8th = 1711 |
| 19107 | CEFBS_HasMVEInt, // MVE_VSHLL_immu16bh = 1712 |
| 19108 | CEFBS_HasMVEInt, // MVE_VSHLL_immu16th = 1713 |
| 19109 | CEFBS_HasMVEInt, // MVE_VSHLL_immu8bh = 1714 |
| 19110 | CEFBS_HasMVEInt, // MVE_VSHLL_immu8th = 1715 |
| 19111 | CEFBS_HasMVEInt, // MVE_VSHLL_lws16bh = 1716 |
| 19112 | CEFBS_HasMVEInt, // MVE_VSHLL_lws16th = 1717 |
| 19113 | CEFBS_HasMVEInt, // MVE_VSHLL_lws8bh = 1718 |
| 19114 | CEFBS_HasMVEInt, // MVE_VSHLL_lws8th = 1719 |
| 19115 | CEFBS_HasMVEInt, // MVE_VSHLL_lwu16bh = 1720 |
| 19116 | CEFBS_HasMVEInt, // MVE_VSHLL_lwu16th = 1721 |
| 19117 | CEFBS_HasMVEInt, // MVE_VSHLL_lwu8bh = 1722 |
| 19118 | CEFBS_HasMVEInt, // MVE_VSHLL_lwu8th = 1723 |
| 19119 | CEFBS_HasMVEInt, // MVE_VSHL_by_vecs16 = 1724 |
| 19120 | CEFBS_HasMVEInt, // MVE_VSHL_by_vecs32 = 1725 |
| 19121 | CEFBS_HasMVEInt, // MVE_VSHL_by_vecs8 = 1726 |
| 19122 | CEFBS_HasMVEInt, // MVE_VSHL_by_vecu16 = 1727 |
| 19123 | CEFBS_HasMVEInt, // MVE_VSHL_by_vecu32 = 1728 |
| 19124 | CEFBS_HasMVEInt, // MVE_VSHL_by_vecu8 = 1729 |
| 19125 | CEFBS_HasMVEInt, // MVE_VSHL_immi16 = 1730 |
| 19126 | CEFBS_HasMVEInt, // MVE_VSHL_immi32 = 1731 |
| 19127 | CEFBS_HasMVEInt, // MVE_VSHL_immi8 = 1732 |
| 19128 | CEFBS_HasMVEInt, // MVE_VSHL_qrs16 = 1733 |
| 19129 | CEFBS_HasMVEInt, // MVE_VSHL_qrs32 = 1734 |
| 19130 | CEFBS_HasMVEInt, // MVE_VSHL_qrs8 = 1735 |
| 19131 | CEFBS_HasMVEInt, // MVE_VSHL_qru16 = 1736 |
| 19132 | CEFBS_HasMVEInt, // MVE_VSHL_qru32 = 1737 |
| 19133 | CEFBS_HasMVEInt, // MVE_VSHL_qru8 = 1738 |
| 19134 | CEFBS_HasMVEInt, // MVE_VSHRNi16bh = 1739 |
| 19135 | CEFBS_HasMVEInt, // MVE_VSHRNi16th = 1740 |
| 19136 | CEFBS_HasMVEInt, // MVE_VSHRNi32bh = 1741 |
| 19137 | CEFBS_HasMVEInt, // MVE_VSHRNi32th = 1742 |
| 19138 | CEFBS_HasMVEInt, // MVE_VSHR_imms16 = 1743 |
| 19139 | CEFBS_HasMVEInt, // MVE_VSHR_imms32 = 1744 |
| 19140 | CEFBS_HasMVEInt, // MVE_VSHR_imms8 = 1745 |
| 19141 | CEFBS_HasMVEInt, // MVE_VSHR_immu16 = 1746 |
| 19142 | CEFBS_HasMVEInt, // MVE_VSHR_immu32 = 1747 |
| 19143 | CEFBS_HasMVEInt, // MVE_VSHR_immu8 = 1748 |
| 19144 | CEFBS_HasMVEInt, // MVE_VSLIimm16 = 1749 |
| 19145 | CEFBS_HasMVEInt, // MVE_VSLIimm32 = 1750 |
| 19146 | CEFBS_HasMVEInt, // MVE_VSLIimm8 = 1751 |
| 19147 | CEFBS_HasMVEInt, // MVE_VSRIimm16 = 1752 |
| 19148 | CEFBS_HasMVEInt, // MVE_VSRIimm32 = 1753 |
| 19149 | CEFBS_HasMVEInt, // MVE_VSRIimm8 = 1754 |
| 19150 | CEFBS_HasMVEInt, // MVE_VST20_16 = 1755 |
| 19151 | CEFBS_HasMVEInt, // MVE_VST20_16_wb = 1756 |
| 19152 | CEFBS_HasMVEInt, // MVE_VST20_32 = 1757 |
| 19153 | CEFBS_HasMVEInt, // MVE_VST20_32_wb = 1758 |
| 19154 | CEFBS_HasMVEInt, // MVE_VST20_8 = 1759 |
| 19155 | CEFBS_HasMVEInt, // MVE_VST20_8_wb = 1760 |
| 19156 | CEFBS_HasMVEInt, // MVE_VST21_16 = 1761 |
| 19157 | CEFBS_HasMVEInt, // MVE_VST21_16_wb = 1762 |
| 19158 | CEFBS_HasMVEInt, // MVE_VST21_32 = 1763 |
| 19159 | CEFBS_HasMVEInt, // MVE_VST21_32_wb = 1764 |
| 19160 | CEFBS_HasMVEInt, // MVE_VST21_8 = 1765 |
| 19161 | CEFBS_HasMVEInt, // MVE_VST21_8_wb = 1766 |
| 19162 | CEFBS_HasMVEInt, // MVE_VST40_16 = 1767 |
| 19163 | CEFBS_HasMVEInt, // MVE_VST40_16_wb = 1768 |
| 19164 | CEFBS_HasMVEInt, // MVE_VST40_32 = 1769 |
| 19165 | CEFBS_HasMVEInt, // MVE_VST40_32_wb = 1770 |
| 19166 | CEFBS_HasMVEInt, // MVE_VST40_8 = 1771 |
| 19167 | CEFBS_HasMVEInt, // MVE_VST40_8_wb = 1772 |
| 19168 | CEFBS_HasMVEInt, // MVE_VST41_16 = 1773 |
| 19169 | CEFBS_HasMVEInt, // MVE_VST41_16_wb = 1774 |
| 19170 | CEFBS_HasMVEInt, // MVE_VST41_32 = 1775 |
| 19171 | CEFBS_HasMVEInt, // MVE_VST41_32_wb = 1776 |
| 19172 | CEFBS_HasMVEInt, // MVE_VST41_8 = 1777 |
| 19173 | CEFBS_HasMVEInt, // MVE_VST41_8_wb = 1778 |
| 19174 | CEFBS_HasMVEInt, // MVE_VST42_16 = 1779 |
| 19175 | CEFBS_HasMVEInt, // MVE_VST42_16_wb = 1780 |
| 19176 | CEFBS_HasMVEInt, // MVE_VST42_32 = 1781 |
| 19177 | CEFBS_HasMVEInt, // MVE_VST42_32_wb = 1782 |
| 19178 | CEFBS_HasMVEInt, // MVE_VST42_8 = 1783 |
| 19179 | CEFBS_HasMVEInt, // MVE_VST42_8_wb = 1784 |
| 19180 | CEFBS_HasMVEInt, // MVE_VST43_16 = 1785 |
| 19181 | CEFBS_HasMVEInt, // MVE_VST43_16_wb = 1786 |
| 19182 | CEFBS_HasMVEInt, // MVE_VST43_32 = 1787 |
| 19183 | CEFBS_HasMVEInt, // MVE_VST43_32_wb = 1788 |
| 19184 | CEFBS_HasMVEInt, // MVE_VST43_8 = 1789 |
| 19185 | CEFBS_HasMVEInt, // MVE_VST43_8_wb = 1790 |
| 19186 | CEFBS_HasMVEInt, // MVE_VSTRB16 = 1791 |
| 19187 | CEFBS_HasMVEInt, // MVE_VSTRB16_post = 1792 |
| 19188 | CEFBS_HasMVEInt, // MVE_VSTRB16_pre = 1793 |
| 19189 | CEFBS_HasMVEInt, // MVE_VSTRB16_rq = 1794 |
| 19190 | CEFBS_HasMVEInt, // MVE_VSTRB32 = 1795 |
| 19191 | CEFBS_HasMVEInt, // MVE_VSTRB32_post = 1796 |
| 19192 | CEFBS_HasMVEInt, // MVE_VSTRB32_pre = 1797 |
| 19193 | CEFBS_HasMVEInt, // MVE_VSTRB32_rq = 1798 |
| 19194 | CEFBS_HasMVEInt, // MVE_VSTRB8_rq = 1799 |
| 19195 | CEFBS_HasMVEInt, // MVE_VSTRBU8 = 1800 |
| 19196 | CEFBS_HasMVEInt, // MVE_VSTRBU8_post = 1801 |
| 19197 | CEFBS_HasMVEInt, // MVE_VSTRBU8_pre = 1802 |
| 19198 | CEFBS_HasMVEInt, // MVE_VSTRD64_qi = 1803 |
| 19199 | CEFBS_HasMVEInt, // MVE_VSTRD64_qi_pre = 1804 |
| 19200 | CEFBS_HasMVEInt, // MVE_VSTRD64_rq = 1805 |
| 19201 | CEFBS_HasMVEInt, // MVE_VSTRD64_rq_u = 1806 |
| 19202 | CEFBS_HasMVEInt, // MVE_VSTRH16_rq = 1807 |
| 19203 | CEFBS_HasMVEInt, // MVE_VSTRH16_rq_u = 1808 |
| 19204 | CEFBS_HasMVEInt, // MVE_VSTRH32 = 1809 |
| 19205 | CEFBS_HasMVEInt, // MVE_VSTRH32_post = 1810 |
| 19206 | CEFBS_HasMVEInt, // MVE_VSTRH32_pre = 1811 |
| 19207 | CEFBS_HasMVEInt, // MVE_VSTRH32_rq = 1812 |
| 19208 | CEFBS_HasMVEInt, // MVE_VSTRH32_rq_u = 1813 |
| 19209 | CEFBS_HasMVEInt, // MVE_VSTRHU16 = 1814 |
| 19210 | CEFBS_HasMVEInt, // MVE_VSTRHU16_post = 1815 |
| 19211 | CEFBS_HasMVEInt, // MVE_VSTRHU16_pre = 1816 |
| 19212 | CEFBS_HasMVEInt, // MVE_VSTRW32_qi = 1817 |
| 19213 | CEFBS_HasMVEInt, // MVE_VSTRW32_qi_pre = 1818 |
| 19214 | CEFBS_HasMVEInt, // MVE_VSTRW32_rq = 1819 |
| 19215 | CEFBS_HasMVEInt, // MVE_VSTRW32_rq_u = 1820 |
| 19216 | CEFBS_HasMVEInt, // MVE_VSTRWU32 = 1821 |
| 19217 | CEFBS_HasMVEInt, // MVE_VSTRWU32_post = 1822 |
| 19218 | CEFBS_HasMVEInt, // MVE_VSTRWU32_pre = 1823 |
| 19219 | CEFBS_HasMVEFloat, // MVE_VSUB_qr_f16 = 1824 |
| 19220 | CEFBS_HasMVEFloat, // MVE_VSUB_qr_f32 = 1825 |
| 19221 | CEFBS_HasMVEInt, // MVE_VSUB_qr_i16 = 1826 |
| 19222 | CEFBS_HasMVEInt, // MVE_VSUB_qr_i32 = 1827 |
| 19223 | CEFBS_HasMVEInt, // MVE_VSUB_qr_i8 = 1828 |
| 19224 | CEFBS_HasMVEFloat, // MVE_VSUBf16 = 1829 |
| 19225 | CEFBS_HasMVEFloat, // MVE_VSUBf32 = 1830 |
| 19226 | CEFBS_HasMVEInt, // MVE_VSUBi16 = 1831 |
| 19227 | CEFBS_HasMVEInt, // MVE_VSUBi32 = 1832 |
| 19228 | CEFBS_HasMVEInt, // MVE_VSUBi8 = 1833 |
| 19229 | CEFBS_HasMVEInt, // MVE_WLSTP_16 = 1834 |
| 19230 | CEFBS_HasMVEInt, // MVE_WLSTP_32 = 1835 |
| 19231 | CEFBS_HasMVEInt, // MVE_WLSTP_64 = 1836 |
| 19232 | CEFBS_HasMVEInt, // MVE_WLSTP_8 = 1837 |
| 19233 | CEFBS_IsARM, // MVNi = 1838 |
| 19234 | CEFBS_IsARM, // MVNr = 1839 |
| 19235 | CEFBS_IsARM, // MVNsi = 1840 |
| 19236 | CEFBS_IsARM, // MVNsr = 1841 |
| 19237 | CEFBS_HasFPARMv8_HasNEON, // NEON_VMAXNMNDf = 1842 |
| 19238 | CEFBS_HasFPARMv8_HasNEON_HasFullFP16, // NEON_VMAXNMNDh = 1843 |
| 19239 | CEFBS_HasFPARMv8_HasNEON, // NEON_VMAXNMNQf = 1844 |
| 19240 | CEFBS_HasFPARMv8_HasNEON_HasFullFP16, // NEON_VMAXNMNQh = 1845 |
| 19241 | CEFBS_HasFPARMv8_HasNEON, // NEON_VMINNMNDf = 1846 |
| 19242 | CEFBS_HasFPARMv8_HasNEON_HasFullFP16, // NEON_VMINNMNDh = 1847 |
| 19243 | CEFBS_HasFPARMv8_HasNEON, // NEON_VMINNMNQf = 1848 |
| 19244 | CEFBS_HasFPARMv8_HasNEON_HasFullFP16, // NEON_VMINNMNQh = 1849 |
| 19245 | CEFBS_IsARM, // ORRri = 1850 |
| 19246 | CEFBS_IsARM, // ORRrr = 1851 |
| 19247 | CEFBS_IsARM, // ORRrsi = 1852 |
| 19248 | CEFBS_IsARM, // ORRrsr = 1853 |
| 19249 | CEFBS_IsARM_HasV6, // PKHBT = 1854 |
| 19250 | CEFBS_IsARM_HasV6, // PKHTB = 1855 |
| 19251 | CEFBS_IsARM_HasV7_HasMP, // PLDWi12 = 1856 |
| 19252 | CEFBS_IsARM_HasV7_HasMP, // PLDWrs = 1857 |
| 19253 | CEFBS_IsARM, // PLDi12 = 1858 |
| 19254 | CEFBS_IsARM, // PLDrs = 1859 |
| 19255 | CEFBS_IsARM_HasV7, // PLIi12 = 1860 |
| 19256 | CEFBS_IsARM_HasV7, // PLIrs = 1861 |
| 19257 | CEFBS_IsARM, // QADD = 1862 |
| 19258 | CEFBS_IsARM, // QADD16 = 1863 |
| 19259 | CEFBS_IsARM, // QADD8 = 1864 |
| 19260 | CEFBS_IsARM, // QASX = 1865 |
| 19261 | CEFBS_IsARM, // QDADD = 1866 |
| 19262 | CEFBS_IsARM, // QDSUB = 1867 |
| 19263 | CEFBS_IsARM, // QSAX = 1868 |
| 19264 | CEFBS_IsARM, // QSUB = 1869 |
| 19265 | CEFBS_IsARM, // QSUB16 = 1870 |
| 19266 | CEFBS_IsARM, // QSUB8 = 1871 |
| 19267 | CEFBS_IsARM_HasV6T2, // RBIT = 1872 |
| 19268 | CEFBS_IsARM_HasV6, // REV = 1873 |
| 19269 | CEFBS_IsARM_HasV6, // REV16 = 1874 |
| 19270 | CEFBS_IsARM_HasV6, // REVSH = 1875 |
| 19271 | CEFBS_IsARM, // RFEDA = 1876 |
| 19272 | CEFBS_IsARM, // RFEDA_UPD = 1877 |
| 19273 | CEFBS_IsARM, // RFEDB = 1878 |
| 19274 | CEFBS_IsARM, // RFEDB_UPD = 1879 |
| 19275 | CEFBS_IsARM, // RFEIA = 1880 |
| 19276 | CEFBS_IsARM, // RFEIA_UPD = 1881 |
| 19277 | CEFBS_IsARM, // RFEIB = 1882 |
| 19278 | CEFBS_IsARM, // RFEIB_UPD = 1883 |
| 19279 | CEFBS_IsARM, // RSBri = 1884 |
| 19280 | CEFBS_IsARM, // RSBrr = 1885 |
| 19281 | CEFBS_IsARM, // RSBrsi = 1886 |
| 19282 | CEFBS_IsARM, // RSBrsr = 1887 |
| 19283 | CEFBS_IsARM, // RSCri = 1888 |
| 19284 | CEFBS_IsARM, // RSCrr = 1889 |
| 19285 | CEFBS_IsARM, // RSCrsi = 1890 |
| 19286 | CEFBS_IsARM, // RSCrsr = 1891 |
| 19287 | CEFBS_IsARM, // SADD16 = 1892 |
| 19288 | CEFBS_IsARM, // SADD8 = 1893 |
| 19289 | CEFBS_IsARM, // SASX = 1894 |
| 19290 | CEFBS_IsARM_HasSB, // SB = 1895 |
| 19291 | CEFBS_IsARM, // SBCri = 1896 |
| 19292 | CEFBS_IsARM, // SBCrr = 1897 |
| 19293 | CEFBS_IsARM, // SBCrsi = 1898 |
| 19294 | CEFBS_IsARM, // SBCrsr = 1899 |
| 19295 | CEFBS_IsARM_HasV6T2, // SBFX = 1900 |
| 19296 | CEFBS_IsARM_HasDivideInARM, // SDIV = 1901 |
| 19297 | CEFBS_IsARM_HasV6, // SEL = 1902 |
| 19298 | CEFBS_IsARM, // SETEND = 1903 |
| 19299 | CEFBS_IsARM_HasV8_HasV8_1a, // SETPAN = 1904 |
| 19300 | CEFBS_HasV8_HasSHA2, // SHA1C = 1905 |
| 19301 | CEFBS_HasV8_HasSHA2, // SHA1H = 1906 |
| 19302 | CEFBS_HasV8_HasSHA2, // SHA1M = 1907 |
| 19303 | CEFBS_HasV8_HasSHA2, // SHA1P = 1908 |
| 19304 | CEFBS_HasV8_HasSHA2, // SHA1SU0 = 1909 |
| 19305 | CEFBS_HasV8_HasSHA2, // SHA1SU1 = 1910 |
| 19306 | CEFBS_HasV8_HasSHA2, // SHA256H = 1911 |
| 19307 | CEFBS_HasV8_HasSHA2, // SHA256H2 = 1912 |
| 19308 | CEFBS_HasV8_HasSHA2, // SHA256SU0 = 1913 |
| 19309 | CEFBS_HasV8_HasSHA2, // SHA256SU1 = 1914 |
| 19310 | CEFBS_IsARM, // SHADD16 = 1915 |
| 19311 | CEFBS_IsARM, // SHADD8 = 1916 |
| 19312 | CEFBS_IsARM, // SHASX = 1917 |
| 19313 | CEFBS_IsARM, // SHSAX = 1918 |
| 19314 | CEFBS_IsARM, // SHSUB16 = 1919 |
| 19315 | CEFBS_IsARM, // SHSUB8 = 1920 |
| 19316 | CEFBS_IsARM_HasTrustZone, // SMC = 1921 |
| 19317 | CEFBS_IsARM_HasV5TE, // SMLABB = 1922 |
| 19318 | CEFBS_IsARM_HasV5TE, // SMLABT = 1923 |
| 19319 | CEFBS_IsARM_HasV6, // SMLAD = 1924 |
| 19320 | CEFBS_IsARM_HasV6, // SMLADX = 1925 |
| 19321 | CEFBS_IsARM_HasV6, // SMLAL = 1926 |
| 19322 | CEFBS_IsARM_HasV5TE, // SMLALBB = 1927 |
| 19323 | CEFBS_IsARM_HasV5TE, // SMLALBT = 1928 |
| 19324 | CEFBS_IsARM_HasV6, // SMLALD = 1929 |
| 19325 | CEFBS_IsARM_HasV6, // SMLALDX = 1930 |
| 19326 | CEFBS_IsARM_HasV5TE, // SMLALTB = 1931 |
| 19327 | CEFBS_IsARM_HasV5TE, // SMLALTT = 1932 |
| 19328 | CEFBS_IsARM_HasV5TE, // SMLATB = 1933 |
| 19329 | CEFBS_IsARM_HasV5TE, // SMLATT = 1934 |
| 19330 | CEFBS_IsARM_HasV5TE, // SMLAWB = 1935 |
| 19331 | CEFBS_IsARM_HasV5TE, // SMLAWT = 1936 |
| 19332 | CEFBS_IsARM_HasV6, // SMLSD = 1937 |
| 19333 | CEFBS_IsARM_HasV6, // SMLSDX = 1938 |
| 19334 | CEFBS_IsARM_HasV6, // SMLSLD = 1939 |
| 19335 | CEFBS_IsARM_HasV6, // SMLSLDX = 1940 |
| 19336 | CEFBS_IsARM_HasV6, // SMMLA = 1941 |
| 19337 | CEFBS_IsARM_HasV6, // SMMLAR = 1942 |
| 19338 | CEFBS_IsARM_HasV6, // SMMLS = 1943 |
| 19339 | CEFBS_IsARM_HasV6, // SMMLSR = 1944 |
| 19340 | CEFBS_IsARM_HasV6, // SMMUL = 1945 |
| 19341 | CEFBS_IsARM_HasV6, // SMMULR = 1946 |
| 19342 | CEFBS_IsARM_HasV6, // SMUAD = 1947 |
| 19343 | CEFBS_IsARM_HasV6, // SMUADX = 1948 |
| 19344 | CEFBS_IsARM_HasV5TE, // SMULBB = 1949 |
| 19345 | CEFBS_IsARM_HasV5TE, // SMULBT = 1950 |
| 19346 | CEFBS_IsARM_HasV6, // SMULL = 1951 |
| 19347 | CEFBS_IsARM_HasV5TE, // SMULTB = 1952 |
| 19348 | CEFBS_IsARM_HasV5TE, // SMULTT = 1953 |
| 19349 | CEFBS_IsARM_HasV5TE, // SMULWB = 1954 |
| 19350 | CEFBS_IsARM_HasV5TE, // SMULWT = 1955 |
| 19351 | CEFBS_IsARM_HasV6, // SMUSD = 1956 |
| 19352 | CEFBS_IsARM_HasV6, // SMUSDX = 1957 |
| 19353 | CEFBS_IsARM, // SRSDA = 1958 |
| 19354 | CEFBS_IsARM, // SRSDA_UPD = 1959 |
| 19355 | CEFBS_IsARM, // SRSDB = 1960 |
| 19356 | CEFBS_IsARM, // SRSDB_UPD = 1961 |
| 19357 | CEFBS_IsARM, // SRSIA = 1962 |
| 19358 | CEFBS_IsARM, // SRSIA_UPD = 1963 |
| 19359 | CEFBS_IsARM, // SRSIB = 1964 |
| 19360 | CEFBS_IsARM, // SRSIB_UPD = 1965 |
| 19361 | CEFBS_IsARM_HasV6, // SSAT = 1966 |
| 19362 | CEFBS_IsARM_HasV6, // SSAT16 = 1967 |
| 19363 | CEFBS_IsARM, // SSAX = 1968 |
| 19364 | CEFBS_IsARM, // SSUB16 = 1969 |
| 19365 | CEFBS_IsARM, // SSUB8 = 1970 |
| 19366 | CEFBS_IsARM_PreV8, // STC2L_OFFSET = 1971 |
| 19367 | CEFBS_IsARM_PreV8, // STC2L_OPTION = 1972 |
| 19368 | CEFBS_IsARM_PreV8, // STC2L_POST = 1973 |
| 19369 | CEFBS_IsARM_PreV8, // STC2L_PRE = 1974 |
| 19370 | CEFBS_IsARM_PreV8, // STC2_OFFSET = 1975 |
| 19371 | CEFBS_IsARM_PreV8, // STC2_OPTION = 1976 |
| 19372 | CEFBS_IsARM_PreV8, // STC2_POST = 1977 |
| 19373 | CEFBS_IsARM_PreV8, // STC2_PRE = 1978 |
| 19374 | CEFBS_IsARM, // STCL_OFFSET = 1979 |
| 19375 | CEFBS_IsARM, // STCL_OPTION = 1980 |
| 19376 | CEFBS_IsARM, // STCL_POST = 1981 |
| 19377 | CEFBS_IsARM, // STCL_PRE = 1982 |
| 19378 | CEFBS_IsARM, // STC_OFFSET = 1983 |
| 19379 | CEFBS_IsARM, // STC_OPTION = 1984 |
| 19380 | CEFBS_IsARM, // STC_POST = 1985 |
| 19381 | CEFBS_IsARM, // STC_PRE = 1986 |
| 19382 | CEFBS_IsARM_HasAcquireRelease, // STL = 1987 |
| 19383 | CEFBS_IsARM_HasAcquireRelease, // STLB = 1988 |
| 19384 | CEFBS_IsARM_HasAcquireRelease_HasV7Clrex, // STLEX = 1989 |
| 19385 | CEFBS_IsARM_HasAcquireRelease_HasV7Clrex, // STLEXB = 1990 |
| 19386 | CEFBS_IsARM_HasAcquireRelease_HasV7Clrex, // STLEXD = 1991 |
| 19387 | CEFBS_IsARM_HasAcquireRelease_HasV7Clrex, // STLEXH = 1992 |
| 19388 | CEFBS_IsARM_HasAcquireRelease, // STLH = 1993 |
| 19389 | CEFBS_IsARM, // STMDA = 1994 |
| 19390 | CEFBS_IsARM, // STMDA_UPD = 1995 |
| 19391 | CEFBS_IsARM, // STMDB = 1996 |
| 19392 | CEFBS_IsARM, // STMDB_UPD = 1997 |
| 19393 | CEFBS_IsARM, // STMIA = 1998 |
| 19394 | CEFBS_IsARM, // STMIA_UPD = 1999 |
| 19395 | CEFBS_IsARM, // STMIB = 2000 |
| 19396 | CEFBS_IsARM, // STMIB_UPD = 2001 |
| 19397 | CEFBS_IsARM, // STRBT_POST_IMM = 2002 |
| 19398 | CEFBS_IsARM, // STRBT_POST_REG = 2003 |
| 19399 | CEFBS_IsARM, // STRB_POST_IMM = 2004 |
| 19400 | CEFBS_IsARM, // STRB_POST_REG = 2005 |
| 19401 | CEFBS_IsARM, // STRB_PRE_IMM = 2006 |
| 19402 | CEFBS_IsARM, // STRB_PRE_REG = 2007 |
| 19403 | CEFBS_IsARM, // STRBi12 = 2008 |
| 19404 | CEFBS_IsARM, // STRBrs = 2009 |
| 19405 | CEFBS_IsARM_HasV5TE, // STRD = 2010 |
| 19406 | CEFBS_IsARM, // STRD_POST = 2011 |
| 19407 | CEFBS_IsARM, // STRD_PRE = 2012 |
| 19408 | CEFBS_IsARM, // STREX = 2013 |
| 19409 | CEFBS_IsARM, // STREXB = 2014 |
| 19410 | CEFBS_IsARM, // STREXD = 2015 |
| 19411 | CEFBS_IsARM, // STREXH = 2016 |
| 19412 | CEFBS_IsARM, // STRH = 2017 |
| 19413 | CEFBS_IsARM, // STRHTi = 2018 |
| 19414 | CEFBS_IsARM, // STRHTr = 2019 |
| 19415 | CEFBS_IsARM, // STRH_POST = 2020 |
| 19416 | CEFBS_IsARM, // STRH_PRE = 2021 |
| 19417 | CEFBS_IsARM, // STRT_POST_IMM = 2022 |
| 19418 | CEFBS_IsARM, // STRT_POST_REG = 2023 |
| 19419 | CEFBS_IsARM, // STR_POST_IMM = 2024 |
| 19420 | CEFBS_IsARM, // STR_POST_REG = 2025 |
| 19421 | CEFBS_IsARM, // STR_PRE_IMM = 2026 |
| 19422 | CEFBS_IsARM, // STR_PRE_REG = 2027 |
| 19423 | CEFBS_IsARM, // STRi12 = 2028 |
| 19424 | CEFBS_IsARM, // STRrs = 2029 |
| 19425 | CEFBS_IsARM, // SUBri = 2030 |
| 19426 | CEFBS_IsARM, // SUBrr = 2031 |
| 19427 | CEFBS_IsARM, // SUBrsi = 2032 |
| 19428 | CEFBS_IsARM, // SUBrsr = 2033 |
| 19429 | CEFBS_IsARM, // SVC = 2034 |
| 19430 | CEFBS_IsARM_PreV8, // SWP = 2035 |
| 19431 | CEFBS_IsARM_PreV8, // SWPB = 2036 |
| 19432 | CEFBS_IsARM_HasV6, // SXTAB = 2037 |
| 19433 | CEFBS_IsARM_HasV6, // SXTAB16 = 2038 |
| 19434 | CEFBS_IsARM_HasV6, // SXTAH = 2039 |
| 19435 | CEFBS_IsARM_HasV6, // SXTB = 2040 |
| 19436 | CEFBS_IsARM_HasV6, // SXTB16 = 2041 |
| 19437 | CEFBS_IsARM_HasV6, // SXTH = 2042 |
| 19438 | CEFBS_IsARM, // TEQri = 2043 |
| 19439 | CEFBS_IsARM, // TEQrr = 2044 |
| 19440 | CEFBS_IsARM, // TEQrsi = 2045 |
| 19441 | CEFBS_IsARM, // TEQrsr = 2046 |
| 19442 | CEFBS_IsARM, // TRAP = 2047 |
| 19443 | CEFBS_IsARM_UseNaClTrap, // TRAPNaCl = 2048 |
| 19444 | CEFBS_IsARM_HasV8_4a, // TSB = 2049 |
| 19445 | CEFBS_IsARM, // TSTri = 2050 |
| 19446 | CEFBS_IsARM, // TSTrr = 2051 |
| 19447 | CEFBS_IsARM, // TSTrsi = 2052 |
| 19448 | CEFBS_IsARM, // TSTrsr = 2053 |
| 19449 | CEFBS_IsARM, // UADD16 = 2054 |
| 19450 | CEFBS_IsARM, // UADD8 = 2055 |
| 19451 | CEFBS_IsARM, // UASX = 2056 |
| 19452 | CEFBS_IsARM_HasV6T2, // UBFX = 2057 |
| 19453 | CEFBS_IsARM, // UDF = 2058 |
| 19454 | CEFBS_IsARM_HasDivideInARM, // UDIV = 2059 |
| 19455 | CEFBS_IsARM, // UHADD16 = 2060 |
| 19456 | CEFBS_IsARM, // UHADD8 = 2061 |
| 19457 | CEFBS_IsARM, // UHASX = 2062 |
| 19458 | CEFBS_IsARM, // UHSAX = 2063 |
| 19459 | CEFBS_IsARM, // UHSUB16 = 2064 |
| 19460 | CEFBS_IsARM, // UHSUB8 = 2065 |
| 19461 | CEFBS_IsARM_HasV6, // UMAAL = 2066 |
| 19462 | CEFBS_IsARM_HasV6, // UMLAL = 2067 |
| 19463 | CEFBS_IsARM_HasV6, // UMULL = 2068 |
| 19464 | CEFBS_IsARM, // UQADD16 = 2069 |
| 19465 | CEFBS_IsARM, // UQADD8 = 2070 |
| 19466 | CEFBS_IsARM, // UQASX = 2071 |
| 19467 | CEFBS_IsARM, // UQSAX = 2072 |
| 19468 | CEFBS_IsARM, // UQSUB16 = 2073 |
| 19469 | CEFBS_IsARM, // UQSUB8 = 2074 |
| 19470 | CEFBS_IsARM_HasV6, // USAD8 = 2075 |
| 19471 | CEFBS_IsARM_HasV6, // USADA8 = 2076 |
| 19472 | CEFBS_IsARM_HasV6, // USAT = 2077 |
| 19473 | CEFBS_IsARM_HasV6, // USAT16 = 2078 |
| 19474 | CEFBS_IsARM, // USAX = 2079 |
| 19475 | CEFBS_IsARM, // USUB16 = 2080 |
| 19476 | CEFBS_IsARM, // USUB8 = 2081 |
| 19477 | CEFBS_IsARM_HasV6, // UXTAB = 2082 |
| 19478 | CEFBS_IsARM_HasV6, // UXTAB16 = 2083 |
| 19479 | CEFBS_IsARM_HasV6, // UXTAH = 2084 |
| 19480 | CEFBS_IsARM_HasV6, // UXTB = 2085 |
| 19481 | CEFBS_IsARM_HasV6, // UXTB16 = 2086 |
| 19482 | CEFBS_IsARM_HasV6, // UXTH = 2087 |
| 19483 | CEFBS_HasNEON, // VABALsv2i64 = 2088 |
| 19484 | CEFBS_HasNEON, // VABALsv4i32 = 2089 |
| 19485 | CEFBS_HasNEON, // VABALsv8i16 = 2090 |
| 19486 | CEFBS_HasNEON, // VABALuv2i64 = 2091 |
| 19487 | CEFBS_HasNEON, // VABALuv4i32 = 2092 |
| 19488 | CEFBS_HasNEON, // VABALuv8i16 = 2093 |
| 19489 | CEFBS_HasNEON, // VABAsv16i8 = 2094 |
| 19490 | CEFBS_HasNEON, // VABAsv2i32 = 2095 |
| 19491 | CEFBS_HasNEON, // VABAsv4i16 = 2096 |
| 19492 | CEFBS_HasNEON, // VABAsv4i32 = 2097 |
| 19493 | CEFBS_HasNEON, // VABAsv8i16 = 2098 |
| 19494 | CEFBS_HasNEON, // VABAsv8i8 = 2099 |
| 19495 | CEFBS_HasNEON, // VABAuv16i8 = 2100 |
| 19496 | CEFBS_HasNEON, // VABAuv2i32 = 2101 |
| 19497 | CEFBS_HasNEON, // VABAuv4i16 = 2102 |
| 19498 | CEFBS_HasNEON, // VABAuv4i32 = 2103 |
| 19499 | CEFBS_HasNEON, // VABAuv8i16 = 2104 |
| 19500 | CEFBS_HasNEON, // VABAuv8i8 = 2105 |
| 19501 | CEFBS_HasNEON, // VABDLsv2i64 = 2106 |
| 19502 | CEFBS_HasNEON, // VABDLsv4i32 = 2107 |
| 19503 | CEFBS_HasNEON, // VABDLsv8i16 = 2108 |
| 19504 | CEFBS_HasNEON, // VABDLuv2i64 = 2109 |
| 19505 | CEFBS_HasNEON, // VABDLuv4i32 = 2110 |
| 19506 | CEFBS_HasNEON, // VABDLuv8i16 = 2111 |
| 19507 | CEFBS_HasNEON, // VABDfd = 2112 |
| 19508 | CEFBS_HasNEON, // VABDfq = 2113 |
| 19509 | CEFBS_HasNEON_HasFullFP16, // VABDhd = 2114 |
| 19510 | CEFBS_HasNEON_HasFullFP16, // VABDhq = 2115 |
| 19511 | CEFBS_HasNEON, // VABDsv16i8 = 2116 |
| 19512 | CEFBS_HasNEON, // VABDsv2i32 = 2117 |
| 19513 | CEFBS_HasNEON, // VABDsv4i16 = 2118 |
| 19514 | CEFBS_HasNEON, // VABDsv4i32 = 2119 |
| 19515 | CEFBS_HasNEON, // VABDsv8i16 = 2120 |
| 19516 | CEFBS_HasNEON, // VABDsv8i8 = 2121 |
| 19517 | CEFBS_HasNEON, // VABDuv16i8 = 2122 |
| 19518 | CEFBS_HasNEON, // VABDuv2i32 = 2123 |
| 19519 | CEFBS_HasNEON, // VABDuv4i16 = 2124 |
| 19520 | CEFBS_HasNEON, // VABDuv4i32 = 2125 |
| 19521 | CEFBS_HasNEON, // VABDuv8i16 = 2126 |
| 19522 | CEFBS_HasNEON, // VABDuv8i8 = 2127 |
| 19523 | CEFBS_HasVFP2_HasDPVFP, // VABSD = 2128 |
| 19524 | CEFBS_HasFullFP16, // VABSH = 2129 |
| 19525 | CEFBS_HasVFP2, // VABSS = 2130 |
| 19526 | CEFBS_HasNEON, // VABSfd = 2131 |
| 19527 | CEFBS_HasNEON, // VABSfq = 2132 |
| 19528 | CEFBS_HasNEON_HasFullFP16, // VABShd = 2133 |
| 19529 | CEFBS_HasNEON_HasFullFP16, // VABShq = 2134 |
| 19530 | CEFBS_HasNEON, // VABSv16i8 = 2135 |
| 19531 | CEFBS_HasNEON, // VABSv2i32 = 2136 |
| 19532 | CEFBS_HasNEON, // VABSv4i16 = 2137 |
| 19533 | CEFBS_HasNEON, // VABSv4i32 = 2138 |
| 19534 | CEFBS_HasNEON, // VABSv8i16 = 2139 |
| 19535 | CEFBS_HasNEON, // VABSv8i8 = 2140 |
| 19536 | CEFBS_HasNEON, // VACGEfd = 2141 |
| 19537 | CEFBS_HasNEON, // VACGEfq = 2142 |
| 19538 | CEFBS_HasNEON_HasFullFP16, // VACGEhd = 2143 |
| 19539 | CEFBS_HasNEON_HasFullFP16, // VACGEhq = 2144 |
| 19540 | CEFBS_HasNEON, // VACGTfd = 2145 |
| 19541 | CEFBS_HasNEON, // VACGTfq = 2146 |
| 19542 | CEFBS_HasNEON_HasFullFP16, // VACGThd = 2147 |
| 19543 | CEFBS_HasNEON_HasFullFP16, // VACGThq = 2148 |
| 19544 | CEFBS_HasVFP2_HasDPVFP, // VADDD = 2149 |
| 19545 | CEFBS_HasFullFP16, // VADDH = 2150 |
| 19546 | CEFBS_HasNEON, // VADDHNv2i32 = 2151 |
| 19547 | CEFBS_HasNEON, // VADDHNv4i16 = 2152 |
| 19548 | CEFBS_HasNEON, // VADDHNv8i8 = 2153 |
| 19549 | CEFBS_HasNEON, // VADDLsv2i64 = 2154 |
| 19550 | CEFBS_HasNEON, // VADDLsv4i32 = 2155 |
| 19551 | CEFBS_HasNEON, // VADDLsv8i16 = 2156 |
| 19552 | CEFBS_HasNEON, // VADDLuv2i64 = 2157 |
| 19553 | CEFBS_HasNEON, // VADDLuv4i32 = 2158 |
| 19554 | CEFBS_HasNEON, // VADDLuv8i16 = 2159 |
| 19555 | CEFBS_HasVFP2, // VADDS = 2160 |
| 19556 | CEFBS_HasNEON, // VADDWsv2i64 = 2161 |
| 19557 | CEFBS_HasNEON, // VADDWsv4i32 = 2162 |
| 19558 | CEFBS_HasNEON, // VADDWsv8i16 = 2163 |
| 19559 | CEFBS_HasNEON, // VADDWuv2i64 = 2164 |
| 19560 | CEFBS_HasNEON, // VADDWuv4i32 = 2165 |
| 19561 | CEFBS_HasNEON, // VADDWuv8i16 = 2166 |
| 19562 | CEFBS_HasNEON, // VADDfd = 2167 |
| 19563 | CEFBS_HasNEON, // VADDfq = 2168 |
| 19564 | CEFBS_HasNEON_HasFullFP16, // VADDhd = 2169 |
| 19565 | CEFBS_HasNEON_HasFullFP16, // VADDhq = 2170 |
| 19566 | CEFBS_HasNEON, // VADDv16i8 = 2171 |
| 19567 | CEFBS_HasNEON, // VADDv1i64 = 2172 |
| 19568 | CEFBS_HasNEON, // VADDv2i32 = 2173 |
| 19569 | CEFBS_HasNEON, // VADDv2i64 = 2174 |
| 19570 | CEFBS_HasNEON, // VADDv4i16 = 2175 |
| 19571 | CEFBS_HasNEON, // VADDv4i32 = 2176 |
| 19572 | CEFBS_HasNEON, // VADDv8i16 = 2177 |
| 19573 | CEFBS_HasNEON, // VADDv8i8 = 2178 |
| 19574 | CEFBS_HasNEON, // VANDd = 2179 |
| 19575 | CEFBS_HasNEON, // VANDq = 2180 |
| 19576 | CEFBS_HasBF16_HasNEON, // VBF16MALBQ = 2181 |
| 19577 | CEFBS_HasBF16_HasNEON, // VBF16MALBQI = 2182 |
| 19578 | CEFBS_HasBF16_HasNEON, // VBF16MALTQ = 2183 |
| 19579 | CEFBS_HasBF16_HasNEON, // VBF16MALTQI = 2184 |
| 19580 | CEFBS_HasNEON, // VBICd = 2185 |
| 19581 | CEFBS_HasNEON, // VBICiv2i32 = 2186 |
| 19582 | CEFBS_HasNEON, // VBICiv4i16 = 2187 |
| 19583 | CEFBS_HasNEON, // VBICiv4i32 = 2188 |
| 19584 | CEFBS_HasNEON, // VBICiv8i16 = 2189 |
| 19585 | CEFBS_HasNEON, // VBICq = 2190 |
| 19586 | CEFBS_HasNEON, // VBIFd = 2191 |
| 19587 | CEFBS_HasNEON, // VBIFq = 2192 |
| 19588 | CEFBS_HasNEON, // VBITd = 2193 |
| 19589 | CEFBS_HasNEON, // VBITq = 2194 |
| 19590 | CEFBS_HasNEON, // VBSLd = 2195 |
| 19591 | CEFBS_HasNEON, // VBSLq = 2196 |
| 19592 | CEFBS_HasNEON, // VBSPd = 2197 |
| 19593 | CEFBS_HasNEON, // VBSPq = 2198 |
| 19594 | CEFBS_HasNEON_HasV8_3a, // VCADDv2f32 = 2199 |
| 19595 | CEFBS_HasNEON_HasV8_3a_HasFullFP16, // VCADDv4f16 = 2200 |
| 19596 | CEFBS_HasNEON_HasV8_3a, // VCADDv4f32 = 2201 |
| 19597 | CEFBS_HasNEON_HasV8_3a_HasFullFP16, // VCADDv8f16 = 2202 |
| 19598 | CEFBS_HasNEON, // VCEQfd = 2203 |
| 19599 | CEFBS_HasNEON, // VCEQfq = 2204 |
| 19600 | CEFBS_HasNEON_HasFullFP16, // VCEQhd = 2205 |
| 19601 | CEFBS_HasNEON_HasFullFP16, // VCEQhq = 2206 |
| 19602 | CEFBS_HasNEON, // VCEQv16i8 = 2207 |
| 19603 | CEFBS_HasNEON, // VCEQv2i32 = 2208 |
| 19604 | CEFBS_HasNEON, // VCEQv4i16 = 2209 |
| 19605 | CEFBS_HasNEON, // VCEQv4i32 = 2210 |
| 19606 | CEFBS_HasNEON, // VCEQv8i16 = 2211 |
| 19607 | CEFBS_HasNEON, // VCEQv8i8 = 2212 |
| 19608 | CEFBS_HasNEON, // VCEQzv16i8 = 2213 |
| 19609 | CEFBS_HasNEON, // VCEQzv2f32 = 2214 |
| 19610 | CEFBS_HasNEON, // VCEQzv2i32 = 2215 |
| 19611 | CEFBS_HasNEON_HasFullFP16, // VCEQzv4f16 = 2216 |
| 19612 | CEFBS_HasNEON, // VCEQzv4f32 = 2217 |
| 19613 | CEFBS_HasNEON, // VCEQzv4i16 = 2218 |
| 19614 | CEFBS_HasNEON, // VCEQzv4i32 = 2219 |
| 19615 | CEFBS_HasNEON_HasFullFP16, // VCEQzv8f16 = 2220 |
| 19616 | CEFBS_HasNEON, // VCEQzv8i16 = 2221 |
| 19617 | CEFBS_HasNEON, // VCEQzv8i8 = 2222 |
| 19618 | CEFBS_HasNEON, // VCGEfd = 2223 |
| 19619 | CEFBS_HasNEON, // VCGEfq = 2224 |
| 19620 | CEFBS_HasNEON_HasFullFP16, // VCGEhd = 2225 |
| 19621 | CEFBS_HasNEON_HasFullFP16, // VCGEhq = 2226 |
| 19622 | CEFBS_HasNEON, // VCGEsv16i8 = 2227 |
| 19623 | CEFBS_HasNEON, // VCGEsv2i32 = 2228 |
| 19624 | CEFBS_HasNEON, // VCGEsv4i16 = 2229 |
| 19625 | CEFBS_HasNEON, // VCGEsv4i32 = 2230 |
| 19626 | CEFBS_HasNEON, // VCGEsv8i16 = 2231 |
| 19627 | CEFBS_HasNEON, // VCGEsv8i8 = 2232 |
| 19628 | CEFBS_HasNEON, // VCGEuv16i8 = 2233 |
| 19629 | CEFBS_HasNEON, // VCGEuv2i32 = 2234 |
| 19630 | CEFBS_HasNEON, // VCGEuv4i16 = 2235 |
| 19631 | CEFBS_HasNEON, // VCGEuv4i32 = 2236 |
| 19632 | CEFBS_HasNEON, // VCGEuv8i16 = 2237 |
| 19633 | CEFBS_HasNEON, // VCGEuv8i8 = 2238 |
| 19634 | CEFBS_HasNEON, // VCGEzv16i8 = 2239 |
| 19635 | CEFBS_HasNEON, // VCGEzv2f32 = 2240 |
| 19636 | CEFBS_HasNEON, // VCGEzv2i32 = 2241 |
| 19637 | CEFBS_HasNEON_HasFullFP16, // VCGEzv4f16 = 2242 |
| 19638 | CEFBS_HasNEON, // VCGEzv4f32 = 2243 |
| 19639 | CEFBS_HasNEON, // VCGEzv4i16 = 2244 |
| 19640 | CEFBS_HasNEON, // VCGEzv4i32 = 2245 |
| 19641 | CEFBS_HasNEON_HasFullFP16, // VCGEzv8f16 = 2246 |
| 19642 | CEFBS_HasNEON, // VCGEzv8i16 = 2247 |
| 19643 | CEFBS_HasNEON, // VCGEzv8i8 = 2248 |
| 19644 | CEFBS_HasNEON, // VCGTfd = 2249 |
| 19645 | CEFBS_HasNEON, // VCGTfq = 2250 |
| 19646 | CEFBS_HasNEON_HasFullFP16, // VCGThd = 2251 |
| 19647 | CEFBS_HasNEON_HasFullFP16, // VCGThq = 2252 |
| 19648 | CEFBS_HasNEON, // VCGTsv16i8 = 2253 |
| 19649 | CEFBS_HasNEON, // VCGTsv2i32 = 2254 |
| 19650 | CEFBS_HasNEON, // VCGTsv4i16 = 2255 |
| 19651 | CEFBS_HasNEON, // VCGTsv4i32 = 2256 |
| 19652 | CEFBS_HasNEON, // VCGTsv8i16 = 2257 |
| 19653 | CEFBS_HasNEON, // VCGTsv8i8 = 2258 |
| 19654 | CEFBS_HasNEON, // VCGTuv16i8 = 2259 |
| 19655 | CEFBS_HasNEON, // VCGTuv2i32 = 2260 |
| 19656 | CEFBS_HasNEON, // VCGTuv4i16 = 2261 |
| 19657 | CEFBS_HasNEON, // VCGTuv4i32 = 2262 |
| 19658 | CEFBS_HasNEON, // VCGTuv8i16 = 2263 |
| 19659 | CEFBS_HasNEON, // VCGTuv8i8 = 2264 |
| 19660 | CEFBS_HasNEON, // VCGTzv16i8 = 2265 |
| 19661 | CEFBS_HasNEON, // VCGTzv2f32 = 2266 |
| 19662 | CEFBS_HasNEON, // VCGTzv2i32 = 2267 |
| 19663 | CEFBS_HasNEON_HasFullFP16, // VCGTzv4f16 = 2268 |
| 19664 | CEFBS_HasNEON, // VCGTzv4f32 = 2269 |
| 19665 | CEFBS_HasNEON, // VCGTzv4i16 = 2270 |
| 19666 | CEFBS_HasNEON, // VCGTzv4i32 = 2271 |
| 19667 | CEFBS_HasNEON_HasFullFP16, // VCGTzv8f16 = 2272 |
| 19668 | CEFBS_HasNEON, // VCGTzv8i16 = 2273 |
| 19669 | CEFBS_HasNEON, // VCGTzv8i8 = 2274 |
| 19670 | CEFBS_HasNEON, // VCLEzv16i8 = 2275 |
| 19671 | CEFBS_HasNEON, // VCLEzv2f32 = 2276 |
| 19672 | CEFBS_HasNEON, // VCLEzv2i32 = 2277 |
| 19673 | CEFBS_HasNEON_HasFullFP16, // VCLEzv4f16 = 2278 |
| 19674 | CEFBS_HasNEON, // VCLEzv4f32 = 2279 |
| 19675 | CEFBS_HasNEON, // VCLEzv4i16 = 2280 |
| 19676 | CEFBS_HasNEON, // VCLEzv4i32 = 2281 |
| 19677 | CEFBS_HasNEON_HasFullFP16, // VCLEzv8f16 = 2282 |
| 19678 | CEFBS_HasNEON, // VCLEzv8i16 = 2283 |
| 19679 | CEFBS_HasNEON, // VCLEzv8i8 = 2284 |
| 19680 | CEFBS_HasNEON, // VCLSv16i8 = 2285 |
| 19681 | CEFBS_HasNEON, // VCLSv2i32 = 2286 |
| 19682 | CEFBS_HasNEON, // VCLSv4i16 = 2287 |
| 19683 | CEFBS_HasNEON, // VCLSv4i32 = 2288 |
| 19684 | CEFBS_HasNEON, // VCLSv8i16 = 2289 |
| 19685 | CEFBS_HasNEON, // VCLSv8i8 = 2290 |
| 19686 | CEFBS_HasNEON, // VCLTzv16i8 = 2291 |
| 19687 | CEFBS_HasNEON, // VCLTzv2f32 = 2292 |
| 19688 | CEFBS_HasNEON, // VCLTzv2i32 = 2293 |
| 19689 | CEFBS_HasNEON_HasFullFP16, // VCLTzv4f16 = 2294 |
| 19690 | CEFBS_HasNEON, // VCLTzv4f32 = 2295 |
| 19691 | CEFBS_HasNEON, // VCLTzv4i16 = 2296 |
| 19692 | CEFBS_HasNEON, // VCLTzv4i32 = 2297 |
| 19693 | CEFBS_HasNEON_HasFullFP16, // VCLTzv8f16 = 2298 |
| 19694 | CEFBS_HasNEON, // VCLTzv8i16 = 2299 |
| 19695 | CEFBS_HasNEON, // VCLTzv8i8 = 2300 |
| 19696 | CEFBS_HasNEON, // VCLZv16i8 = 2301 |
| 19697 | CEFBS_HasNEON, // VCLZv2i32 = 2302 |
| 19698 | CEFBS_HasNEON, // VCLZv4i16 = 2303 |
| 19699 | CEFBS_HasNEON, // VCLZv4i32 = 2304 |
| 19700 | CEFBS_HasNEON, // VCLZv8i16 = 2305 |
| 19701 | CEFBS_HasNEON, // VCLZv8i8 = 2306 |
| 19702 | CEFBS_HasNEON_HasV8_3a, // VCMLAv2f32 = 2307 |
| 19703 | CEFBS_HasNEON_HasV8_3a, // VCMLAv2f32_indexed = 2308 |
| 19704 | CEFBS_HasNEON_HasV8_3a_HasFullFP16, // VCMLAv4f16 = 2309 |
| 19705 | CEFBS_HasNEON_HasV8_3a_HasFullFP16, // VCMLAv4f16_indexed = 2310 |
| 19706 | CEFBS_HasNEON_HasV8_3a, // VCMLAv4f32 = 2311 |
| 19707 | CEFBS_HasNEON_HasV8_3a, // VCMLAv4f32_indexed = 2312 |
| 19708 | CEFBS_HasNEON_HasV8_3a_HasFullFP16, // VCMLAv8f16 = 2313 |
| 19709 | CEFBS_HasNEON_HasV8_3a_HasFullFP16, // VCMLAv8f16_indexed = 2314 |
| 19710 | CEFBS_HasVFP2_HasDPVFP, // VCMPD = 2315 |
| 19711 | CEFBS_HasVFP2_HasDPVFP, // VCMPED = 2316 |
| 19712 | CEFBS_HasFullFP16, // VCMPEH = 2317 |
| 19713 | CEFBS_HasVFP2, // VCMPES = 2318 |
| 19714 | CEFBS_HasVFP2_HasDPVFP, // VCMPEZD = 2319 |
| 19715 | CEFBS_HasFullFP16, // VCMPEZH = 2320 |
| 19716 | CEFBS_HasVFP2, // VCMPEZS = 2321 |
| 19717 | CEFBS_HasFullFP16, // VCMPH = 2322 |
| 19718 | CEFBS_HasVFP2, // VCMPS = 2323 |
| 19719 | CEFBS_HasVFP2_HasDPVFP, // VCMPZD = 2324 |
| 19720 | CEFBS_HasFullFP16, // VCMPZH = 2325 |
| 19721 | CEFBS_HasVFP2, // VCMPZS = 2326 |
| 19722 | CEFBS_HasNEON, // VCNTd = 2327 |
| 19723 | CEFBS_HasNEON, // VCNTq = 2328 |
| 19724 | CEFBS_HasV8_HasNEON, // VCVTANSDf = 2329 |
| 19725 | CEFBS_HasV8_HasNEON_HasFullFP16, // VCVTANSDh = 2330 |
| 19726 | CEFBS_HasV8_HasNEON, // VCVTANSQf = 2331 |
| 19727 | CEFBS_HasV8_HasNEON_HasFullFP16, // VCVTANSQh = 2332 |
| 19728 | CEFBS_HasV8_HasNEON, // VCVTANUDf = 2333 |
| 19729 | CEFBS_HasV8_HasNEON_HasFullFP16, // VCVTANUDh = 2334 |
| 19730 | CEFBS_HasV8_HasNEON, // VCVTANUQf = 2335 |
| 19731 | CEFBS_HasV8_HasNEON_HasFullFP16, // VCVTANUQh = 2336 |
| 19732 | CEFBS_HasFPARMv8_HasDPVFP, // VCVTASD = 2337 |
| 19733 | CEFBS_HasFullFP16, // VCVTASH = 2338 |
| 19734 | CEFBS_HasFPARMv8, // VCVTASS = 2339 |
| 19735 | CEFBS_HasFPARMv8_HasDPVFP, // VCVTAUD = 2340 |
| 19736 | CEFBS_HasFullFP16, // VCVTAUH = 2341 |
| 19737 | CEFBS_HasFPARMv8, // VCVTAUS = 2342 |
| 19738 | CEFBS_HasFPARMv8_HasDPVFP, // VCVTBDH = 2343 |
| 19739 | CEFBS_HasFPARMv8_HasDPVFP, // VCVTBHD = 2344 |
| 19740 | CEFBS_HasFP16, // VCVTBHS = 2345 |
| 19741 | CEFBS_HasFP16, // VCVTBSH = 2346 |
| 19742 | CEFBS_HasVFP2_HasDPVFP, // VCVTDS = 2347 |
| 19743 | CEFBS_HasV8_HasNEON, // VCVTMNSDf = 2348 |
| 19744 | CEFBS_HasV8_HasNEON_HasFullFP16, // VCVTMNSDh = 2349 |
| 19745 | CEFBS_HasV8_HasNEON, // VCVTMNSQf = 2350 |
| 19746 | CEFBS_HasV8_HasNEON_HasFullFP16, // VCVTMNSQh = 2351 |
| 19747 | CEFBS_HasV8_HasNEON, // VCVTMNUDf = 2352 |
| 19748 | CEFBS_HasV8_HasNEON_HasFullFP16, // VCVTMNUDh = 2353 |
| 19749 | CEFBS_HasV8_HasNEON, // VCVTMNUQf = 2354 |
| 19750 | CEFBS_HasV8_HasNEON_HasFullFP16, // VCVTMNUQh = 2355 |
| 19751 | CEFBS_HasFPARMv8_HasDPVFP, // VCVTMSD = 2356 |
| 19752 | CEFBS_HasFullFP16, // VCVTMSH = 2357 |
| 19753 | CEFBS_HasFPARMv8, // VCVTMSS = 2358 |
| 19754 | CEFBS_HasFPARMv8_HasDPVFP, // VCVTMUD = 2359 |
| 19755 | CEFBS_HasFullFP16, // VCVTMUH = 2360 |
| 19756 | CEFBS_HasFPARMv8, // VCVTMUS = 2361 |
| 19757 | CEFBS_HasV8_HasNEON, // VCVTNNSDf = 2362 |
| 19758 | CEFBS_HasV8_HasNEON_HasFullFP16, // VCVTNNSDh = 2363 |
| 19759 | CEFBS_HasV8_HasNEON, // VCVTNNSQf = 2364 |
| 19760 | CEFBS_HasV8_HasNEON_HasFullFP16, // VCVTNNSQh = 2365 |
| 19761 | CEFBS_HasV8_HasNEON, // VCVTNNUDf = 2366 |
| 19762 | CEFBS_HasV8_HasNEON_HasFullFP16, // VCVTNNUDh = 2367 |
| 19763 | CEFBS_HasV8_HasNEON, // VCVTNNUQf = 2368 |
| 19764 | CEFBS_HasV8_HasNEON_HasFullFP16, // VCVTNNUQh = 2369 |
| 19765 | CEFBS_HasFPARMv8_HasDPVFP, // VCVTNSD = 2370 |
| 19766 | CEFBS_HasFullFP16, // VCVTNSH = 2371 |
| 19767 | CEFBS_HasFPARMv8, // VCVTNSS = 2372 |
| 19768 | CEFBS_HasFPARMv8_HasDPVFP, // VCVTNUD = 2373 |
| 19769 | CEFBS_HasFullFP16, // VCVTNUH = 2374 |
| 19770 | CEFBS_HasFPARMv8, // VCVTNUS = 2375 |
| 19771 | CEFBS_HasV8_HasNEON, // VCVTPNSDf = 2376 |
| 19772 | CEFBS_HasV8_HasNEON_HasFullFP16, // VCVTPNSDh = 2377 |
| 19773 | CEFBS_HasV8_HasNEON, // VCVTPNSQf = 2378 |
| 19774 | CEFBS_HasV8_HasNEON_HasFullFP16, // VCVTPNSQh = 2379 |
| 19775 | CEFBS_HasV8_HasNEON, // VCVTPNUDf = 2380 |
| 19776 | CEFBS_HasV8_HasNEON_HasFullFP16, // VCVTPNUDh = 2381 |
| 19777 | CEFBS_HasV8_HasNEON, // VCVTPNUQf = 2382 |
| 19778 | CEFBS_HasV8_HasNEON_HasFullFP16, // VCVTPNUQh = 2383 |
| 19779 | CEFBS_HasFPARMv8_HasDPVFP, // VCVTPSD = 2384 |
| 19780 | CEFBS_HasFullFP16, // VCVTPSH = 2385 |
| 19781 | CEFBS_HasFPARMv8, // VCVTPSS = 2386 |
| 19782 | CEFBS_HasFPARMv8_HasDPVFP, // VCVTPUD = 2387 |
| 19783 | CEFBS_HasFullFP16, // VCVTPUH = 2388 |
| 19784 | CEFBS_HasFPARMv8, // VCVTPUS = 2389 |
| 19785 | CEFBS_HasVFP2_HasDPVFP, // VCVTSD = 2390 |
| 19786 | CEFBS_HasFPARMv8_HasDPVFP, // VCVTTDH = 2391 |
| 19787 | CEFBS_HasFPARMv8_HasDPVFP, // VCVTTHD = 2392 |
| 19788 | CEFBS_HasFP16, // VCVTTHS = 2393 |
| 19789 | CEFBS_HasFP16, // VCVTTSH = 2394 |
| 19790 | CEFBS_HasNEON_HasFP16, // VCVTf2h = 2395 |
| 19791 | CEFBS_HasNEON, // VCVTf2sd = 2396 |
| 19792 | CEFBS_HasNEON, // VCVTf2sq = 2397 |
| 19793 | CEFBS_HasNEON, // VCVTf2ud = 2398 |
| 19794 | CEFBS_HasNEON, // VCVTf2uq = 2399 |
| 19795 | CEFBS_HasNEON, // VCVTf2xsd = 2400 |
| 19796 | CEFBS_HasNEON, // VCVTf2xsq = 2401 |
| 19797 | CEFBS_HasNEON, // VCVTf2xud = 2402 |
| 19798 | CEFBS_HasNEON, // VCVTf2xuq = 2403 |
| 19799 | CEFBS_HasNEON_HasFP16, // VCVTh2f = 2404 |
| 19800 | CEFBS_HasNEON_HasFullFP16, // VCVTh2sd = 2405 |
| 19801 | CEFBS_HasNEON_HasFullFP16, // VCVTh2sq = 2406 |
| 19802 | CEFBS_HasNEON_HasFullFP16, // VCVTh2ud = 2407 |
| 19803 | CEFBS_HasNEON_HasFullFP16, // VCVTh2uq = 2408 |
| 19804 | CEFBS_HasNEON_HasFullFP16, // VCVTh2xsd = 2409 |
| 19805 | CEFBS_HasNEON_HasFullFP16, // VCVTh2xsq = 2410 |
| 19806 | CEFBS_HasNEON_HasFullFP16, // VCVTh2xud = 2411 |
| 19807 | CEFBS_HasNEON_HasFullFP16, // VCVTh2xuq = 2412 |
| 19808 | CEFBS_HasNEON, // VCVTs2fd = 2413 |
| 19809 | CEFBS_HasNEON, // VCVTs2fq = 2414 |
| 19810 | CEFBS_HasNEON_HasFullFP16, // VCVTs2hd = 2415 |
| 19811 | CEFBS_HasNEON_HasFullFP16, // VCVTs2hq = 2416 |
| 19812 | CEFBS_HasNEON, // VCVTu2fd = 2417 |
| 19813 | CEFBS_HasNEON, // VCVTu2fq = 2418 |
| 19814 | CEFBS_HasNEON_HasFullFP16, // VCVTu2hd = 2419 |
| 19815 | CEFBS_HasNEON_HasFullFP16, // VCVTu2hq = 2420 |
| 19816 | CEFBS_HasNEON, // VCVTxs2fd = 2421 |
| 19817 | CEFBS_HasNEON, // VCVTxs2fq = 2422 |
| 19818 | CEFBS_HasNEON_HasFullFP16, // VCVTxs2hd = 2423 |
| 19819 | CEFBS_HasNEON_HasFullFP16, // VCVTxs2hq = 2424 |
| 19820 | CEFBS_HasNEON, // VCVTxu2fd = 2425 |
| 19821 | CEFBS_HasNEON, // VCVTxu2fq = 2426 |
| 19822 | CEFBS_HasNEON_HasFullFP16, // VCVTxu2hd = 2427 |
| 19823 | CEFBS_HasNEON_HasFullFP16, // VCVTxu2hq = 2428 |
| 19824 | CEFBS_HasVFP2_HasDPVFP, // VDIVD = 2429 |
| 19825 | CEFBS_HasFullFP16, // VDIVH = 2430 |
| 19826 | CEFBS_HasVFP2, // VDIVS = 2431 |
| 19827 | CEFBS_HasNEON, // VDUP16d = 2432 |
| 19828 | CEFBS_HasNEON, // VDUP16q = 2433 |
| 19829 | CEFBS_HasNEON, // VDUP32d = 2434 |
| 19830 | CEFBS_HasNEON, // VDUP32q = 2435 |
| 19831 | CEFBS_HasNEON, // VDUP8d = 2436 |
| 19832 | CEFBS_HasNEON, // VDUP8q = 2437 |
| 19833 | CEFBS_HasNEON, // VDUPLN16d = 2438 |
| 19834 | CEFBS_HasNEON, // VDUPLN16q = 2439 |
| 19835 | CEFBS_HasNEON, // VDUPLN32d = 2440 |
| 19836 | CEFBS_HasNEON, // VDUPLN32q = 2441 |
| 19837 | CEFBS_HasNEON, // VDUPLN8d = 2442 |
| 19838 | CEFBS_HasNEON, // VDUPLN8q = 2443 |
| 19839 | CEFBS_HasNEON, // VEORd = 2444 |
| 19840 | CEFBS_HasNEON, // VEORq = 2445 |
| 19841 | CEFBS_HasNEON, // VEXTd16 = 2446 |
| 19842 | CEFBS_HasNEON, // VEXTd32 = 2447 |
| 19843 | CEFBS_HasNEON, // VEXTd8 = 2448 |
| 19844 | CEFBS_HasNEON, // VEXTq16 = 2449 |
| 19845 | CEFBS_HasNEON, // VEXTq32 = 2450 |
| 19846 | CEFBS_HasNEON, // VEXTq64 = 2451 |
| 19847 | CEFBS_HasNEON, // VEXTq8 = 2452 |
| 19848 | CEFBS_HasVFP4_HasDPVFP, // VFMAD = 2453 |
| 19849 | CEFBS_HasFullFP16, // VFMAH = 2454 |
| 19850 | CEFBS_HasNEON_HasFP16FML, // VFMALD = 2455 |
| 19851 | CEFBS_HasNEON_HasFP16FML, // VFMALDI = 2456 |
| 19852 | CEFBS_HasNEON_HasFP16FML, // VFMALQ = 2457 |
| 19853 | CEFBS_HasNEON_HasFP16FML, // VFMALQI = 2458 |
| 19854 | CEFBS_HasVFP4, // VFMAS = 2459 |
| 19855 | CEFBS_HasNEON_HasVFP4, // VFMAfd = 2460 |
| 19856 | CEFBS_HasNEON_HasVFP4, // VFMAfq = 2461 |
| 19857 | CEFBS_HasNEON_HasFullFP16, // VFMAhd = 2462 |
| 19858 | CEFBS_HasNEON_HasFullFP16, // VFMAhq = 2463 |
| 19859 | CEFBS_HasVFP4_HasDPVFP, // VFMSD = 2464 |
| 19860 | CEFBS_HasFullFP16, // VFMSH = 2465 |
| 19861 | CEFBS_HasNEON_HasFP16FML, // VFMSLD = 2466 |
| 19862 | CEFBS_HasNEON_HasFP16FML, // VFMSLDI = 2467 |
| 19863 | CEFBS_HasNEON_HasFP16FML, // VFMSLQ = 2468 |
| 19864 | CEFBS_HasNEON_HasFP16FML, // VFMSLQI = 2469 |
| 19865 | CEFBS_HasVFP4, // VFMSS = 2470 |
| 19866 | CEFBS_HasNEON_HasVFP4, // VFMSfd = 2471 |
| 19867 | CEFBS_HasNEON_HasVFP4, // VFMSfq = 2472 |
| 19868 | CEFBS_HasNEON_HasFullFP16, // VFMShd = 2473 |
| 19869 | CEFBS_HasNEON_HasFullFP16, // VFMShq = 2474 |
| 19870 | CEFBS_HasVFP4_HasDPVFP, // VFNMAD = 2475 |
| 19871 | CEFBS_HasFullFP16, // VFNMAH = 2476 |
| 19872 | CEFBS_HasVFP4, // VFNMAS = 2477 |
| 19873 | CEFBS_HasVFP4_HasDPVFP, // VFNMSD = 2478 |
| 19874 | CEFBS_HasFullFP16, // VFNMSH = 2479 |
| 19875 | CEFBS_HasVFP4, // VFNMSS = 2480 |
| 19876 | CEFBS_HasFPARMv8_HasDPVFP, // VFP_VMAXNMD = 2481 |
| 19877 | CEFBS_HasFullFP16, // VFP_VMAXNMH = 2482 |
| 19878 | CEFBS_HasFPARMv8, // VFP_VMAXNMS = 2483 |
| 19879 | CEFBS_HasFPARMv8_HasDPVFP, // VFP_VMINNMD = 2484 |
| 19880 | CEFBS_HasFullFP16, // VFP_VMINNMH = 2485 |
| 19881 | CEFBS_HasFPARMv8, // VFP_VMINNMS = 2486 |
| 19882 | CEFBS_HasFPRegs, // VGETLNi32 = 2487 |
| 19883 | CEFBS_HasNEON, // VGETLNs16 = 2488 |
| 19884 | CEFBS_HasNEON, // VGETLNs8 = 2489 |
| 19885 | CEFBS_HasNEON, // VGETLNu16 = 2490 |
| 19886 | CEFBS_HasNEON, // VGETLNu8 = 2491 |
| 19887 | CEFBS_HasNEON, // VHADDsv16i8 = 2492 |
| 19888 | CEFBS_HasNEON, // VHADDsv2i32 = 2493 |
| 19889 | CEFBS_HasNEON, // VHADDsv4i16 = 2494 |
| 19890 | CEFBS_HasNEON, // VHADDsv4i32 = 2495 |
| 19891 | CEFBS_HasNEON, // VHADDsv8i16 = 2496 |
| 19892 | CEFBS_HasNEON, // VHADDsv8i8 = 2497 |
| 19893 | CEFBS_HasNEON, // VHADDuv16i8 = 2498 |
| 19894 | CEFBS_HasNEON, // VHADDuv2i32 = 2499 |
| 19895 | CEFBS_HasNEON, // VHADDuv4i16 = 2500 |
| 19896 | CEFBS_HasNEON, // VHADDuv4i32 = 2501 |
| 19897 | CEFBS_HasNEON, // VHADDuv8i16 = 2502 |
| 19898 | CEFBS_HasNEON, // VHADDuv8i8 = 2503 |
| 19899 | CEFBS_HasNEON, // VHSUBsv16i8 = 2504 |
| 19900 | CEFBS_HasNEON, // VHSUBsv2i32 = 2505 |
| 19901 | CEFBS_HasNEON, // VHSUBsv4i16 = 2506 |
| 19902 | CEFBS_HasNEON, // VHSUBsv4i32 = 2507 |
| 19903 | CEFBS_HasNEON, // VHSUBsv8i16 = 2508 |
| 19904 | CEFBS_HasNEON, // VHSUBsv8i8 = 2509 |
| 19905 | CEFBS_HasNEON, // VHSUBuv16i8 = 2510 |
| 19906 | CEFBS_HasNEON, // VHSUBuv2i32 = 2511 |
| 19907 | CEFBS_HasNEON, // VHSUBuv4i16 = 2512 |
| 19908 | CEFBS_HasNEON, // VHSUBuv4i32 = 2513 |
| 19909 | CEFBS_HasNEON, // VHSUBuv8i16 = 2514 |
| 19910 | CEFBS_HasNEON, // VHSUBuv8i8 = 2515 |
| 19911 | CEFBS_HasFullFP16, // VINSH = 2516 |
| 19912 | CEFBS_HasFPARMv8_HasV8_3a, // VJCVT = 2517 |
| 19913 | CEFBS_HasNEON, // VLD1DUPd16 = 2518 |
| 19914 | CEFBS_HasNEON, // VLD1DUPd16wb_fixed = 2519 |
| 19915 | CEFBS_HasNEON, // VLD1DUPd16wb_register = 2520 |
| 19916 | CEFBS_HasNEON, // VLD1DUPd32 = 2521 |
| 19917 | CEFBS_HasNEON, // VLD1DUPd32wb_fixed = 2522 |
| 19918 | CEFBS_HasNEON, // VLD1DUPd32wb_register = 2523 |
| 19919 | CEFBS_HasNEON, // VLD1DUPd8 = 2524 |
| 19920 | CEFBS_HasNEON, // VLD1DUPd8wb_fixed = 2525 |
| 19921 | CEFBS_HasNEON, // VLD1DUPd8wb_register = 2526 |
| 19922 | CEFBS_HasNEON, // VLD1DUPq16 = 2527 |
| 19923 | CEFBS_HasNEON, // VLD1DUPq16wb_fixed = 2528 |
| 19924 | CEFBS_HasNEON, // VLD1DUPq16wb_register = 2529 |
| 19925 | CEFBS_HasNEON, // VLD1DUPq32 = 2530 |
| 19926 | CEFBS_HasNEON, // VLD1DUPq32wb_fixed = 2531 |
| 19927 | CEFBS_HasNEON, // VLD1DUPq32wb_register = 2532 |
| 19928 | CEFBS_HasNEON, // VLD1DUPq8 = 2533 |
| 19929 | CEFBS_HasNEON, // VLD1DUPq8wb_fixed = 2534 |
| 19930 | CEFBS_HasNEON, // VLD1DUPq8wb_register = 2535 |
| 19931 | CEFBS_HasNEON, // VLD1LNd16 = 2536 |
| 19932 | CEFBS_HasNEON, // VLD1LNd16_UPD = 2537 |
| 19933 | CEFBS_HasNEON, // VLD1LNd32 = 2538 |
| 19934 | CEFBS_HasNEON, // VLD1LNd32_UPD = 2539 |
| 19935 | CEFBS_HasNEON, // VLD1LNd8 = 2540 |
| 19936 | CEFBS_HasNEON, // VLD1LNd8_UPD = 2541 |
| 19937 | CEFBS_HasNEON, // VLD1LNq16Pseudo = 2542 |
| 19938 | CEFBS_HasNEON, // VLD1LNq16Pseudo_UPD = 2543 |
| 19939 | CEFBS_HasNEON, // VLD1LNq32Pseudo = 2544 |
| 19940 | CEFBS_HasNEON, // VLD1LNq32Pseudo_UPD = 2545 |
| 19941 | CEFBS_HasNEON, // VLD1LNq8Pseudo = 2546 |
| 19942 | CEFBS_HasNEON, // VLD1LNq8Pseudo_UPD = 2547 |
| 19943 | CEFBS_HasNEON, // VLD1d16 = 2548 |
| 19944 | CEFBS_HasNEON, // VLD1d16Q = 2549 |
| 19945 | CEFBS_HasNEON, // VLD1d16QPseudo = 2550 |
| 19946 | CEFBS_HasNEON, // VLD1d16QPseudoWB_fixed = 2551 |
| 19947 | CEFBS_HasNEON, // VLD1d16QPseudoWB_register = 2552 |
| 19948 | CEFBS_HasNEON, // VLD1d16Qwb_fixed = 2553 |
| 19949 | CEFBS_HasNEON, // VLD1d16Qwb_register = 2554 |
| 19950 | CEFBS_HasNEON, // VLD1d16T = 2555 |
| 19951 | CEFBS_HasNEON, // VLD1d16TPseudo = 2556 |
| 19952 | CEFBS_HasNEON, // VLD1d16TPseudoWB_fixed = 2557 |
| 19953 | CEFBS_HasNEON, // VLD1d16TPseudoWB_register = 2558 |
| 19954 | CEFBS_HasNEON, // VLD1d16Twb_fixed = 2559 |
| 19955 | CEFBS_HasNEON, // VLD1d16Twb_register = 2560 |
| 19956 | CEFBS_HasNEON, // VLD1d16wb_fixed = 2561 |
| 19957 | CEFBS_HasNEON, // VLD1d16wb_register = 2562 |
| 19958 | CEFBS_HasNEON, // VLD1d32 = 2563 |
| 19959 | CEFBS_HasNEON, // VLD1d32Q = 2564 |
| 19960 | CEFBS_HasNEON, // VLD1d32QPseudo = 2565 |
| 19961 | CEFBS_HasNEON, // VLD1d32QPseudoWB_fixed = 2566 |
| 19962 | CEFBS_HasNEON, // VLD1d32QPseudoWB_register = 2567 |
| 19963 | CEFBS_HasNEON, // VLD1d32Qwb_fixed = 2568 |
| 19964 | CEFBS_HasNEON, // VLD1d32Qwb_register = 2569 |
| 19965 | CEFBS_HasNEON, // VLD1d32T = 2570 |
| 19966 | CEFBS_HasNEON, // VLD1d32TPseudo = 2571 |
| 19967 | CEFBS_HasNEON, // VLD1d32TPseudoWB_fixed = 2572 |
| 19968 | CEFBS_HasNEON, // VLD1d32TPseudoWB_register = 2573 |
| 19969 | CEFBS_HasNEON, // VLD1d32Twb_fixed = 2574 |
| 19970 | CEFBS_HasNEON, // VLD1d32Twb_register = 2575 |
| 19971 | CEFBS_HasNEON, // VLD1d32wb_fixed = 2576 |
| 19972 | CEFBS_HasNEON, // VLD1d32wb_register = 2577 |
| 19973 | CEFBS_HasNEON, // VLD1d64 = 2578 |
| 19974 | CEFBS_HasNEON, // VLD1d64Q = 2579 |
| 19975 | CEFBS_HasNEON, // VLD1d64QPseudo = 2580 |
| 19976 | CEFBS_HasNEON, // VLD1d64QPseudoWB_fixed = 2581 |
| 19977 | CEFBS_HasNEON, // VLD1d64QPseudoWB_register = 2582 |
| 19978 | CEFBS_HasNEON, // VLD1d64Qwb_fixed = 2583 |
| 19979 | CEFBS_HasNEON, // VLD1d64Qwb_register = 2584 |
| 19980 | CEFBS_HasNEON, // VLD1d64T = 2585 |
| 19981 | CEFBS_HasNEON, // VLD1d64TPseudo = 2586 |
| 19982 | CEFBS_HasNEON, // VLD1d64TPseudoWB_fixed = 2587 |
| 19983 | CEFBS_HasNEON, // VLD1d64TPseudoWB_register = 2588 |
| 19984 | CEFBS_HasNEON, // VLD1d64Twb_fixed = 2589 |
| 19985 | CEFBS_HasNEON, // VLD1d64Twb_register = 2590 |
| 19986 | CEFBS_HasNEON, // VLD1d64wb_fixed = 2591 |
| 19987 | CEFBS_HasNEON, // VLD1d64wb_register = 2592 |
| 19988 | CEFBS_HasNEON, // VLD1d8 = 2593 |
| 19989 | CEFBS_HasNEON, // VLD1d8Q = 2594 |
| 19990 | CEFBS_HasNEON, // VLD1d8QPseudo = 2595 |
| 19991 | CEFBS_HasNEON, // VLD1d8QPseudoWB_fixed = 2596 |
| 19992 | CEFBS_HasNEON, // VLD1d8QPseudoWB_register = 2597 |
| 19993 | CEFBS_HasNEON, // VLD1d8Qwb_fixed = 2598 |
| 19994 | CEFBS_HasNEON, // VLD1d8Qwb_register = 2599 |
| 19995 | CEFBS_HasNEON, // VLD1d8T = 2600 |
| 19996 | CEFBS_HasNEON, // VLD1d8TPseudo = 2601 |
| 19997 | CEFBS_HasNEON, // VLD1d8TPseudoWB_fixed = 2602 |
| 19998 | CEFBS_HasNEON, // VLD1d8TPseudoWB_register = 2603 |
| 19999 | CEFBS_HasNEON, // VLD1d8Twb_fixed = 2604 |
| 20000 | CEFBS_HasNEON, // VLD1d8Twb_register = 2605 |
| 20001 | CEFBS_HasNEON, // VLD1d8wb_fixed = 2606 |
| 20002 | CEFBS_HasNEON, // VLD1d8wb_register = 2607 |
| 20003 | CEFBS_HasNEON, // VLD1q16 = 2608 |
| 20004 | CEFBS_HasNEON, // VLD1q16HighQPseudo = 2609 |
| 20005 | CEFBS_HasNEON, // VLD1q16HighQPseudo_UPD = 2610 |
| 20006 | CEFBS_HasNEON, // VLD1q16HighTPseudo = 2611 |
| 20007 | CEFBS_HasNEON, // VLD1q16HighTPseudo_UPD = 2612 |
| 20008 | CEFBS_HasNEON, // VLD1q16LowQPseudo_UPD = 2613 |
| 20009 | CEFBS_HasNEON, // VLD1q16LowTPseudo_UPD = 2614 |
| 20010 | CEFBS_HasNEON, // VLD1q16wb_fixed = 2615 |
| 20011 | CEFBS_HasNEON, // VLD1q16wb_register = 2616 |
| 20012 | CEFBS_HasNEON, // VLD1q32 = 2617 |
| 20013 | CEFBS_HasNEON, // VLD1q32HighQPseudo = 2618 |
| 20014 | CEFBS_HasNEON, // VLD1q32HighQPseudo_UPD = 2619 |
| 20015 | CEFBS_HasNEON, // VLD1q32HighTPseudo = 2620 |
| 20016 | CEFBS_HasNEON, // VLD1q32HighTPseudo_UPD = 2621 |
| 20017 | CEFBS_HasNEON, // VLD1q32LowQPseudo_UPD = 2622 |
| 20018 | CEFBS_HasNEON, // VLD1q32LowTPseudo_UPD = 2623 |
| 20019 | CEFBS_HasNEON, // VLD1q32wb_fixed = 2624 |
| 20020 | CEFBS_HasNEON, // VLD1q32wb_register = 2625 |
| 20021 | CEFBS_HasNEON, // VLD1q64 = 2626 |
| 20022 | CEFBS_HasNEON, // VLD1q64HighQPseudo = 2627 |
| 20023 | CEFBS_HasNEON, // VLD1q64HighQPseudo_UPD = 2628 |
| 20024 | CEFBS_HasNEON, // VLD1q64HighTPseudo = 2629 |
| 20025 | CEFBS_HasNEON, // VLD1q64HighTPseudo_UPD = 2630 |
| 20026 | CEFBS_HasNEON, // VLD1q64LowQPseudo_UPD = 2631 |
| 20027 | CEFBS_HasNEON, // VLD1q64LowTPseudo_UPD = 2632 |
| 20028 | CEFBS_HasNEON, // VLD1q64wb_fixed = 2633 |
| 20029 | CEFBS_HasNEON, // VLD1q64wb_register = 2634 |
| 20030 | CEFBS_HasNEON, // VLD1q8 = 2635 |
| 20031 | CEFBS_HasNEON, // VLD1q8HighQPseudo = 2636 |
| 20032 | CEFBS_HasNEON, // VLD1q8HighQPseudo_UPD = 2637 |
| 20033 | CEFBS_HasNEON, // VLD1q8HighTPseudo = 2638 |
| 20034 | CEFBS_HasNEON, // VLD1q8HighTPseudo_UPD = 2639 |
| 20035 | CEFBS_HasNEON, // VLD1q8LowQPseudo_UPD = 2640 |
| 20036 | CEFBS_HasNEON, // VLD1q8LowTPseudo_UPD = 2641 |
| 20037 | CEFBS_HasNEON, // VLD1q8wb_fixed = 2642 |
| 20038 | CEFBS_HasNEON, // VLD1q8wb_register = 2643 |
| 20039 | CEFBS_HasNEON, // VLD2DUPd16 = 2644 |
| 20040 | CEFBS_HasNEON, // VLD2DUPd16wb_fixed = 2645 |
| 20041 | CEFBS_HasNEON, // VLD2DUPd16wb_register = 2646 |
| 20042 | CEFBS_HasNEON, // VLD2DUPd16x2 = 2647 |
| 20043 | CEFBS_HasNEON, // VLD2DUPd16x2wb_fixed = 2648 |
| 20044 | CEFBS_HasNEON, // VLD2DUPd16x2wb_register = 2649 |
| 20045 | CEFBS_HasNEON, // VLD2DUPd32 = 2650 |
| 20046 | CEFBS_HasNEON, // VLD2DUPd32wb_fixed = 2651 |
| 20047 | CEFBS_HasNEON, // VLD2DUPd32wb_register = 2652 |
| 20048 | CEFBS_HasNEON, // VLD2DUPd32x2 = 2653 |
| 20049 | CEFBS_HasNEON, // VLD2DUPd32x2wb_fixed = 2654 |
| 20050 | CEFBS_HasNEON, // VLD2DUPd32x2wb_register = 2655 |
| 20051 | CEFBS_HasNEON, // VLD2DUPd8 = 2656 |
| 20052 | CEFBS_HasNEON, // VLD2DUPd8wb_fixed = 2657 |
| 20053 | CEFBS_HasNEON, // VLD2DUPd8wb_register = 2658 |
| 20054 | CEFBS_HasNEON, // VLD2DUPd8x2 = 2659 |
| 20055 | CEFBS_HasNEON, // VLD2DUPd8x2wb_fixed = 2660 |
| 20056 | CEFBS_HasNEON, // VLD2DUPd8x2wb_register = 2661 |
| 20057 | CEFBS_HasNEON, // VLD2DUPq16EvenPseudo = 2662 |
| 20058 | CEFBS_HasNEON, // VLD2DUPq16OddPseudo = 2663 |
| 20059 | CEFBS_HasNEON, // VLD2DUPq16OddPseudoWB_fixed = 2664 |
| 20060 | CEFBS_HasNEON, // VLD2DUPq16OddPseudoWB_register = 2665 |
| 20061 | CEFBS_HasNEON, // VLD2DUPq32EvenPseudo = 2666 |
| 20062 | CEFBS_HasNEON, // VLD2DUPq32OddPseudo = 2667 |
| 20063 | CEFBS_HasNEON, // VLD2DUPq32OddPseudoWB_fixed = 2668 |
| 20064 | CEFBS_HasNEON, // VLD2DUPq32OddPseudoWB_register = 2669 |
| 20065 | CEFBS_HasNEON, // VLD2DUPq8EvenPseudo = 2670 |
| 20066 | CEFBS_HasNEON, // VLD2DUPq8OddPseudo = 2671 |
| 20067 | CEFBS_HasNEON, // VLD2DUPq8OddPseudoWB_fixed = 2672 |
| 20068 | CEFBS_HasNEON, // VLD2DUPq8OddPseudoWB_register = 2673 |
| 20069 | CEFBS_HasNEON, // VLD2LNd16 = 2674 |
| 20070 | CEFBS_HasNEON, // VLD2LNd16Pseudo = 2675 |
| 20071 | CEFBS_HasNEON, // VLD2LNd16Pseudo_UPD = 2676 |
| 20072 | CEFBS_HasNEON, // VLD2LNd16_UPD = 2677 |
| 20073 | CEFBS_HasNEON, // VLD2LNd32 = 2678 |
| 20074 | CEFBS_HasNEON, // VLD2LNd32Pseudo = 2679 |
| 20075 | CEFBS_HasNEON, // VLD2LNd32Pseudo_UPD = 2680 |
| 20076 | CEFBS_HasNEON, // VLD2LNd32_UPD = 2681 |
| 20077 | CEFBS_HasNEON, // VLD2LNd8 = 2682 |
| 20078 | CEFBS_HasNEON, // VLD2LNd8Pseudo = 2683 |
| 20079 | CEFBS_HasNEON, // VLD2LNd8Pseudo_UPD = 2684 |
| 20080 | CEFBS_HasNEON, // VLD2LNd8_UPD = 2685 |
| 20081 | CEFBS_HasNEON, // VLD2LNq16 = 2686 |
| 20082 | CEFBS_HasNEON, // VLD2LNq16Pseudo = 2687 |
| 20083 | CEFBS_HasNEON, // VLD2LNq16Pseudo_UPD = 2688 |
| 20084 | CEFBS_HasNEON, // VLD2LNq16_UPD = 2689 |
| 20085 | CEFBS_HasNEON, // VLD2LNq32 = 2690 |
| 20086 | CEFBS_HasNEON, // VLD2LNq32Pseudo = 2691 |
| 20087 | CEFBS_HasNEON, // VLD2LNq32Pseudo_UPD = 2692 |
| 20088 | CEFBS_HasNEON, // VLD2LNq32_UPD = 2693 |
| 20089 | CEFBS_HasNEON, // VLD2b16 = 2694 |
| 20090 | CEFBS_HasNEON, // VLD2b16wb_fixed = 2695 |
| 20091 | CEFBS_HasNEON, // VLD2b16wb_register = 2696 |
| 20092 | CEFBS_HasNEON, // VLD2b32 = 2697 |
| 20093 | CEFBS_HasNEON, // VLD2b32wb_fixed = 2698 |
| 20094 | CEFBS_HasNEON, // VLD2b32wb_register = 2699 |
| 20095 | CEFBS_HasNEON, // VLD2b8 = 2700 |
| 20096 | CEFBS_HasNEON, // VLD2b8wb_fixed = 2701 |
| 20097 | CEFBS_HasNEON, // VLD2b8wb_register = 2702 |
| 20098 | CEFBS_HasNEON, // VLD2d16 = 2703 |
| 20099 | CEFBS_HasNEON, // VLD2d16wb_fixed = 2704 |
| 20100 | CEFBS_HasNEON, // VLD2d16wb_register = 2705 |
| 20101 | CEFBS_HasNEON, // VLD2d32 = 2706 |
| 20102 | CEFBS_HasNEON, // VLD2d32wb_fixed = 2707 |
| 20103 | CEFBS_HasNEON, // VLD2d32wb_register = 2708 |
| 20104 | CEFBS_HasNEON, // VLD2d8 = 2709 |
| 20105 | CEFBS_HasNEON, // VLD2d8wb_fixed = 2710 |
| 20106 | CEFBS_HasNEON, // VLD2d8wb_register = 2711 |
| 20107 | CEFBS_HasNEON, // VLD2q16 = 2712 |
| 20108 | CEFBS_HasNEON, // VLD2q16Pseudo = 2713 |
| 20109 | CEFBS_HasNEON, // VLD2q16PseudoWB_fixed = 2714 |
| 20110 | CEFBS_HasNEON, // VLD2q16PseudoWB_register = 2715 |
| 20111 | CEFBS_HasNEON, // VLD2q16wb_fixed = 2716 |
| 20112 | CEFBS_HasNEON, // VLD2q16wb_register = 2717 |
| 20113 | CEFBS_HasNEON, // VLD2q32 = 2718 |
| 20114 | CEFBS_HasNEON, // VLD2q32Pseudo = 2719 |
| 20115 | CEFBS_HasNEON, // VLD2q32PseudoWB_fixed = 2720 |
| 20116 | CEFBS_HasNEON, // VLD2q32PseudoWB_register = 2721 |
| 20117 | CEFBS_HasNEON, // VLD2q32wb_fixed = 2722 |
| 20118 | CEFBS_HasNEON, // VLD2q32wb_register = 2723 |
| 20119 | CEFBS_HasNEON, // VLD2q8 = 2724 |
| 20120 | CEFBS_HasNEON, // VLD2q8Pseudo = 2725 |
| 20121 | CEFBS_HasNEON, // VLD2q8PseudoWB_fixed = 2726 |
| 20122 | CEFBS_HasNEON, // VLD2q8PseudoWB_register = 2727 |
| 20123 | CEFBS_HasNEON, // VLD2q8wb_fixed = 2728 |
| 20124 | CEFBS_HasNEON, // VLD2q8wb_register = 2729 |
| 20125 | CEFBS_HasNEON, // VLD3DUPd16 = 2730 |
| 20126 | CEFBS_HasNEON, // VLD3DUPd16Pseudo = 2731 |
| 20127 | CEFBS_HasNEON, // VLD3DUPd16Pseudo_UPD = 2732 |
| 20128 | CEFBS_HasNEON, // VLD3DUPd16_UPD = 2733 |
| 20129 | CEFBS_HasNEON, // VLD3DUPd32 = 2734 |
| 20130 | CEFBS_HasNEON, // VLD3DUPd32Pseudo = 2735 |
| 20131 | CEFBS_HasNEON, // VLD3DUPd32Pseudo_UPD = 2736 |
| 20132 | CEFBS_HasNEON, // VLD3DUPd32_UPD = 2737 |
| 20133 | CEFBS_HasNEON, // VLD3DUPd8 = 2738 |
| 20134 | CEFBS_HasNEON, // VLD3DUPd8Pseudo = 2739 |
| 20135 | CEFBS_HasNEON, // VLD3DUPd8Pseudo_UPD = 2740 |
| 20136 | CEFBS_HasNEON, // VLD3DUPd8_UPD = 2741 |
| 20137 | CEFBS_HasNEON, // VLD3DUPq16 = 2742 |
| 20138 | CEFBS_HasNEON, // VLD3DUPq16EvenPseudo = 2743 |
| 20139 | CEFBS_HasNEON, // VLD3DUPq16OddPseudo = 2744 |
| 20140 | CEFBS_HasNEON, // VLD3DUPq16OddPseudo_UPD = 2745 |
| 20141 | CEFBS_HasNEON, // VLD3DUPq16_UPD = 2746 |
| 20142 | CEFBS_HasNEON, // VLD3DUPq32 = 2747 |
| 20143 | CEFBS_HasNEON, // VLD3DUPq32EvenPseudo = 2748 |
| 20144 | CEFBS_HasNEON, // VLD3DUPq32OddPseudo = 2749 |
| 20145 | CEFBS_HasNEON, // VLD3DUPq32OddPseudo_UPD = 2750 |
| 20146 | CEFBS_HasNEON, // VLD3DUPq32_UPD = 2751 |
| 20147 | CEFBS_HasNEON, // VLD3DUPq8 = 2752 |
| 20148 | CEFBS_HasNEON, // VLD3DUPq8EvenPseudo = 2753 |
| 20149 | CEFBS_HasNEON, // VLD3DUPq8OddPseudo = 2754 |
| 20150 | CEFBS_HasNEON, // VLD3DUPq8OddPseudo_UPD = 2755 |
| 20151 | CEFBS_HasNEON, // VLD3DUPq8_UPD = 2756 |
| 20152 | CEFBS_HasNEON, // VLD3LNd16 = 2757 |
| 20153 | CEFBS_HasNEON, // VLD3LNd16Pseudo = 2758 |
| 20154 | CEFBS_HasNEON, // VLD3LNd16Pseudo_UPD = 2759 |
| 20155 | CEFBS_HasNEON, // VLD3LNd16_UPD = 2760 |
| 20156 | CEFBS_HasNEON, // VLD3LNd32 = 2761 |
| 20157 | CEFBS_HasNEON, // VLD3LNd32Pseudo = 2762 |
| 20158 | CEFBS_HasNEON, // VLD3LNd32Pseudo_UPD = 2763 |
| 20159 | CEFBS_HasNEON, // VLD3LNd32_UPD = 2764 |
| 20160 | CEFBS_HasNEON, // VLD3LNd8 = 2765 |
| 20161 | CEFBS_HasNEON, // VLD3LNd8Pseudo = 2766 |
| 20162 | CEFBS_HasNEON, // VLD3LNd8Pseudo_UPD = 2767 |
| 20163 | CEFBS_HasNEON, // VLD3LNd8_UPD = 2768 |
| 20164 | CEFBS_HasNEON, // VLD3LNq16 = 2769 |
| 20165 | CEFBS_HasNEON, // VLD3LNq16Pseudo = 2770 |
| 20166 | CEFBS_HasNEON, // VLD3LNq16Pseudo_UPD = 2771 |
| 20167 | CEFBS_HasNEON, // VLD3LNq16_UPD = 2772 |
| 20168 | CEFBS_HasNEON, // VLD3LNq32 = 2773 |
| 20169 | CEFBS_HasNEON, // VLD3LNq32Pseudo = 2774 |
| 20170 | CEFBS_HasNEON, // VLD3LNq32Pseudo_UPD = 2775 |
| 20171 | CEFBS_HasNEON, // VLD3LNq32_UPD = 2776 |
| 20172 | CEFBS_HasNEON, // VLD3d16 = 2777 |
| 20173 | CEFBS_HasNEON, // VLD3d16Pseudo = 2778 |
| 20174 | CEFBS_HasNEON, // VLD3d16Pseudo_UPD = 2779 |
| 20175 | CEFBS_HasNEON, // VLD3d16_UPD = 2780 |
| 20176 | CEFBS_HasNEON, // VLD3d32 = 2781 |
| 20177 | CEFBS_HasNEON, // VLD3d32Pseudo = 2782 |
| 20178 | CEFBS_HasNEON, // VLD3d32Pseudo_UPD = 2783 |
| 20179 | CEFBS_HasNEON, // VLD3d32_UPD = 2784 |
| 20180 | CEFBS_HasNEON, // VLD3d8 = 2785 |
| 20181 | CEFBS_HasNEON, // VLD3d8Pseudo = 2786 |
| 20182 | CEFBS_HasNEON, // VLD3d8Pseudo_UPD = 2787 |
| 20183 | CEFBS_HasNEON, // VLD3d8_UPD = 2788 |
| 20184 | CEFBS_HasNEON, // VLD3q16 = 2789 |
| 20185 | CEFBS_HasNEON, // VLD3q16Pseudo_UPD = 2790 |
| 20186 | CEFBS_HasNEON, // VLD3q16_UPD = 2791 |
| 20187 | CEFBS_HasNEON, // VLD3q16oddPseudo = 2792 |
| 20188 | CEFBS_HasNEON, // VLD3q16oddPseudo_UPD = 2793 |
| 20189 | CEFBS_HasNEON, // VLD3q32 = 2794 |
| 20190 | CEFBS_HasNEON, // VLD3q32Pseudo_UPD = 2795 |
| 20191 | CEFBS_HasNEON, // VLD3q32_UPD = 2796 |
| 20192 | CEFBS_HasNEON, // VLD3q32oddPseudo = 2797 |
| 20193 | CEFBS_HasNEON, // VLD3q32oddPseudo_UPD = 2798 |
| 20194 | CEFBS_HasNEON, // VLD3q8 = 2799 |
| 20195 | CEFBS_HasNEON, // VLD3q8Pseudo_UPD = 2800 |
| 20196 | CEFBS_HasNEON, // VLD3q8_UPD = 2801 |
| 20197 | CEFBS_HasNEON, // VLD3q8oddPseudo = 2802 |
| 20198 | CEFBS_HasNEON, // VLD3q8oddPseudo_UPD = 2803 |
| 20199 | CEFBS_HasNEON, // VLD4DUPd16 = 2804 |
| 20200 | CEFBS_HasNEON, // VLD4DUPd16Pseudo = 2805 |
| 20201 | CEFBS_HasNEON, // VLD4DUPd16Pseudo_UPD = 2806 |
| 20202 | CEFBS_HasNEON, // VLD4DUPd16_UPD = 2807 |
| 20203 | CEFBS_HasNEON, // VLD4DUPd32 = 2808 |
| 20204 | CEFBS_HasNEON, // VLD4DUPd32Pseudo = 2809 |
| 20205 | CEFBS_HasNEON, // VLD4DUPd32Pseudo_UPD = 2810 |
| 20206 | CEFBS_HasNEON, // VLD4DUPd32_UPD = 2811 |
| 20207 | CEFBS_HasNEON, // VLD4DUPd8 = 2812 |
| 20208 | CEFBS_HasNEON, // VLD4DUPd8Pseudo = 2813 |
| 20209 | CEFBS_HasNEON, // VLD4DUPd8Pseudo_UPD = 2814 |
| 20210 | CEFBS_HasNEON, // VLD4DUPd8_UPD = 2815 |
| 20211 | CEFBS_HasNEON, // VLD4DUPq16 = 2816 |
| 20212 | CEFBS_HasNEON, // VLD4DUPq16EvenPseudo = 2817 |
| 20213 | CEFBS_HasNEON, // VLD4DUPq16OddPseudo = 2818 |
| 20214 | CEFBS_HasNEON, // VLD4DUPq16OddPseudo_UPD = 2819 |
| 20215 | CEFBS_HasNEON, // VLD4DUPq16_UPD = 2820 |
| 20216 | CEFBS_HasNEON, // VLD4DUPq32 = 2821 |
| 20217 | CEFBS_HasNEON, // VLD4DUPq32EvenPseudo = 2822 |
| 20218 | CEFBS_HasNEON, // VLD4DUPq32OddPseudo = 2823 |
| 20219 | CEFBS_HasNEON, // VLD4DUPq32OddPseudo_UPD = 2824 |
| 20220 | CEFBS_HasNEON, // VLD4DUPq32_UPD = 2825 |
| 20221 | CEFBS_HasNEON, // VLD4DUPq8 = 2826 |
| 20222 | CEFBS_HasNEON, // VLD4DUPq8EvenPseudo = 2827 |
| 20223 | CEFBS_HasNEON, // VLD4DUPq8OddPseudo = 2828 |
| 20224 | CEFBS_HasNEON, // VLD4DUPq8OddPseudo_UPD = 2829 |
| 20225 | CEFBS_HasNEON, // VLD4DUPq8_UPD = 2830 |
| 20226 | CEFBS_HasNEON, // VLD4LNd16 = 2831 |
| 20227 | CEFBS_HasNEON, // VLD4LNd16Pseudo = 2832 |
| 20228 | CEFBS_HasNEON, // VLD4LNd16Pseudo_UPD = 2833 |
| 20229 | CEFBS_HasNEON, // VLD4LNd16_UPD = 2834 |
| 20230 | CEFBS_HasNEON, // VLD4LNd32 = 2835 |
| 20231 | CEFBS_HasNEON, // VLD4LNd32Pseudo = 2836 |
| 20232 | CEFBS_HasNEON, // VLD4LNd32Pseudo_UPD = 2837 |
| 20233 | CEFBS_HasNEON, // VLD4LNd32_UPD = 2838 |
| 20234 | CEFBS_HasNEON, // VLD4LNd8 = 2839 |
| 20235 | CEFBS_HasNEON, // VLD4LNd8Pseudo = 2840 |
| 20236 | CEFBS_HasNEON, // VLD4LNd8Pseudo_UPD = 2841 |
| 20237 | CEFBS_HasNEON, // VLD4LNd8_UPD = 2842 |
| 20238 | CEFBS_HasNEON, // VLD4LNq16 = 2843 |
| 20239 | CEFBS_HasNEON, // VLD4LNq16Pseudo = 2844 |
| 20240 | CEFBS_HasNEON, // VLD4LNq16Pseudo_UPD = 2845 |
| 20241 | CEFBS_HasNEON, // VLD4LNq16_UPD = 2846 |
| 20242 | CEFBS_HasNEON, // VLD4LNq32 = 2847 |
| 20243 | CEFBS_HasNEON, // VLD4LNq32Pseudo = 2848 |
| 20244 | CEFBS_HasNEON, // VLD4LNq32Pseudo_UPD = 2849 |
| 20245 | CEFBS_HasNEON, // VLD4LNq32_UPD = 2850 |
| 20246 | CEFBS_HasNEON, // VLD4d16 = 2851 |
| 20247 | CEFBS_HasNEON, // VLD4d16Pseudo = 2852 |
| 20248 | CEFBS_HasNEON, // VLD4d16Pseudo_UPD = 2853 |
| 20249 | CEFBS_HasNEON, // VLD4d16_UPD = 2854 |
| 20250 | CEFBS_HasNEON, // VLD4d32 = 2855 |
| 20251 | CEFBS_HasNEON, // VLD4d32Pseudo = 2856 |
| 20252 | CEFBS_HasNEON, // VLD4d32Pseudo_UPD = 2857 |
| 20253 | CEFBS_HasNEON, // VLD4d32_UPD = 2858 |
| 20254 | CEFBS_HasNEON, // VLD4d8 = 2859 |
| 20255 | CEFBS_HasNEON, // VLD4d8Pseudo = 2860 |
| 20256 | CEFBS_HasNEON, // VLD4d8Pseudo_UPD = 2861 |
| 20257 | CEFBS_HasNEON, // VLD4d8_UPD = 2862 |
| 20258 | CEFBS_HasNEON, // VLD4q16 = 2863 |
| 20259 | CEFBS_HasNEON, // VLD4q16Pseudo_UPD = 2864 |
| 20260 | CEFBS_HasNEON, // VLD4q16_UPD = 2865 |
| 20261 | CEFBS_HasNEON, // VLD4q16oddPseudo = 2866 |
| 20262 | CEFBS_HasNEON, // VLD4q16oddPseudo_UPD = 2867 |
| 20263 | CEFBS_HasNEON, // VLD4q32 = 2868 |
| 20264 | CEFBS_HasNEON, // VLD4q32Pseudo_UPD = 2869 |
| 20265 | CEFBS_HasNEON, // VLD4q32_UPD = 2870 |
| 20266 | CEFBS_HasNEON, // VLD4q32oddPseudo = 2871 |
| 20267 | CEFBS_HasNEON, // VLD4q32oddPseudo_UPD = 2872 |
| 20268 | CEFBS_HasNEON, // VLD4q8 = 2873 |
| 20269 | CEFBS_HasNEON, // VLD4q8Pseudo_UPD = 2874 |
| 20270 | CEFBS_HasNEON, // VLD4q8_UPD = 2875 |
| 20271 | CEFBS_HasNEON, // VLD4q8oddPseudo = 2876 |
| 20272 | CEFBS_HasNEON, // VLD4q8oddPseudo_UPD = 2877 |
| 20273 | CEFBS_HasFPRegs, // VLDMDDB_UPD = 2878 |
| 20274 | CEFBS_HasFPRegs, // VLDMDIA = 2879 |
| 20275 | CEFBS_HasFPRegs, // VLDMDIA_UPD = 2880 |
| 20276 | CEFBS_HasVFP2, // VLDMQIA = 2881 |
| 20277 | CEFBS_HasFPRegs, // VLDMSDB_UPD = 2882 |
| 20278 | CEFBS_HasFPRegs, // VLDMSIA = 2883 |
| 20279 | CEFBS_HasFPRegs, // VLDMSIA_UPD = 2884 |
| 20280 | CEFBS_HasFPRegs, // VLDRD = 2885 |
| 20281 | CEFBS_HasFPRegs16, // VLDRH = 2886 |
| 20282 | CEFBS_HasFPRegs, // VLDRS = 2887 |
| 20283 | CEFBS_HasV8_1MMainline_Has8MSecExt, // VLDR_FPCXTNS_off = 2888 |
| 20284 | CEFBS_HasV8_1MMainline_Has8MSecExt, // VLDR_FPCXTNS_post = 2889 |
| 20285 | CEFBS_HasV8_1MMainline_Has8MSecExt, // VLDR_FPCXTNS_pre = 2890 |
| 20286 | CEFBS_HasV8_1MMainline_Has8MSecExt, // VLDR_FPCXTS_off = 2891 |
| 20287 | CEFBS_HasV8_1MMainline_Has8MSecExt, // VLDR_FPCXTS_post = 2892 |
| 20288 | CEFBS_HasV8_1MMainline_Has8MSecExt, // VLDR_FPCXTS_pre = 2893 |
| 20289 | CEFBS_HasFPRegs_HasV8_1MMainline, // VLDR_FPSCR_NZCVQC_off = 2894 |
| 20290 | CEFBS_HasFPRegs_HasV8_1MMainline, // VLDR_FPSCR_NZCVQC_post = 2895 |
| 20291 | CEFBS_HasFPRegs_HasV8_1MMainline, // VLDR_FPSCR_NZCVQC_pre = 2896 |
| 20292 | CEFBS_HasFPRegs_HasV8_1MMainline, // VLDR_FPSCR_off = 2897 |
| 20293 | CEFBS_HasFPRegs_HasV8_1MMainline, // VLDR_FPSCR_post = 2898 |
| 20294 | CEFBS_HasFPRegs_HasV8_1MMainline, // VLDR_FPSCR_pre = 2899 |
| 20295 | CEFBS_HasV8_1MMainline_HasMVEInt, // VLDR_P0_off = 2900 |
| 20296 | CEFBS_HasV8_1MMainline_HasMVEInt, // VLDR_P0_post = 2901 |
| 20297 | CEFBS_HasV8_1MMainline_HasMVEInt, // VLDR_P0_pre = 2902 |
| 20298 | CEFBS_HasV8_1MMainline_HasMVEInt, // VLDR_VPR_off = 2903 |
| 20299 | CEFBS_HasV8_1MMainline_HasMVEInt, // VLDR_VPR_post = 2904 |
| 20300 | CEFBS_HasV8_1MMainline_HasMVEInt, // VLDR_VPR_pre = 2905 |
| 20301 | CEFBS_HasV8MMainline_Has8MSecExt, // VLLDM = 2906 |
| 20302 | CEFBS_HasV8_1MMainline_Has8MSecExt, // VLLDM_T2 = 2907 |
| 20303 | CEFBS_HasV8MMainline_Has8MSecExt, // VLSTM = 2908 |
| 20304 | CEFBS_HasV8_1MMainline_Has8MSecExt, // VLSTM_T2 = 2909 |
| 20305 | CEFBS_HasNEON, // VMAXfd = 2910 |
| 20306 | CEFBS_HasNEON, // VMAXfq = 2911 |
| 20307 | CEFBS_HasNEON_HasFullFP16, // VMAXhd = 2912 |
| 20308 | CEFBS_HasNEON_HasFullFP16, // VMAXhq = 2913 |
| 20309 | CEFBS_HasNEON, // VMAXsv16i8 = 2914 |
| 20310 | CEFBS_HasNEON, // VMAXsv2i32 = 2915 |
| 20311 | CEFBS_HasNEON, // VMAXsv4i16 = 2916 |
| 20312 | CEFBS_HasNEON, // VMAXsv4i32 = 2917 |
| 20313 | CEFBS_HasNEON, // VMAXsv8i16 = 2918 |
| 20314 | CEFBS_HasNEON, // VMAXsv8i8 = 2919 |
| 20315 | CEFBS_HasNEON, // VMAXuv16i8 = 2920 |
| 20316 | CEFBS_HasNEON, // VMAXuv2i32 = 2921 |
| 20317 | CEFBS_HasNEON, // VMAXuv4i16 = 2922 |
| 20318 | CEFBS_HasNEON, // VMAXuv4i32 = 2923 |
| 20319 | CEFBS_HasNEON, // VMAXuv8i16 = 2924 |
| 20320 | CEFBS_HasNEON, // VMAXuv8i8 = 2925 |
| 20321 | CEFBS_HasNEON, // VMINfd = 2926 |
| 20322 | CEFBS_HasNEON, // VMINfq = 2927 |
| 20323 | CEFBS_HasNEON_HasFullFP16, // VMINhd = 2928 |
| 20324 | CEFBS_HasNEON_HasFullFP16, // VMINhq = 2929 |
| 20325 | CEFBS_HasNEON, // VMINsv16i8 = 2930 |
| 20326 | CEFBS_HasNEON, // VMINsv2i32 = 2931 |
| 20327 | CEFBS_HasNEON, // VMINsv4i16 = 2932 |
| 20328 | CEFBS_HasNEON, // VMINsv4i32 = 2933 |
| 20329 | CEFBS_HasNEON, // VMINsv8i16 = 2934 |
| 20330 | CEFBS_HasNEON, // VMINsv8i8 = 2935 |
| 20331 | CEFBS_HasNEON, // VMINuv16i8 = 2936 |
| 20332 | CEFBS_HasNEON, // VMINuv2i32 = 2937 |
| 20333 | CEFBS_HasNEON, // VMINuv4i16 = 2938 |
| 20334 | CEFBS_HasNEON, // VMINuv4i32 = 2939 |
| 20335 | CEFBS_HasNEON, // VMINuv8i16 = 2940 |
| 20336 | CEFBS_HasNEON, // VMINuv8i8 = 2941 |
| 20337 | CEFBS_HasVFP2_HasDPVFP, // VMLAD = 2942 |
| 20338 | CEFBS_HasFullFP16, // VMLAH = 2943 |
| 20339 | CEFBS_HasNEON, // VMLALslsv2i32 = 2944 |
| 20340 | CEFBS_HasNEON, // VMLALslsv4i16 = 2945 |
| 20341 | CEFBS_HasNEON, // VMLALsluv2i32 = 2946 |
| 20342 | CEFBS_HasNEON, // VMLALsluv4i16 = 2947 |
| 20343 | CEFBS_HasNEON, // VMLALsv2i64 = 2948 |
| 20344 | CEFBS_HasNEON, // VMLALsv4i32 = 2949 |
| 20345 | CEFBS_HasNEON, // VMLALsv8i16 = 2950 |
| 20346 | CEFBS_HasNEON, // VMLALuv2i64 = 2951 |
| 20347 | CEFBS_HasNEON, // VMLALuv4i32 = 2952 |
| 20348 | CEFBS_HasNEON, // VMLALuv8i16 = 2953 |
| 20349 | CEFBS_HasVFP2, // VMLAS = 2954 |
| 20350 | CEFBS_HasNEON, // VMLAfd = 2955 |
| 20351 | CEFBS_HasNEON, // VMLAfq = 2956 |
| 20352 | CEFBS_HasNEON_HasFullFP16, // VMLAhd = 2957 |
| 20353 | CEFBS_HasNEON_HasFullFP16, // VMLAhq = 2958 |
| 20354 | CEFBS_HasNEON, // VMLAslfd = 2959 |
| 20355 | CEFBS_HasNEON, // VMLAslfq = 2960 |
| 20356 | CEFBS_HasNEON_HasFullFP16, // VMLAslhd = 2961 |
| 20357 | CEFBS_HasNEON_HasFullFP16, // VMLAslhq = 2962 |
| 20358 | CEFBS_HasNEON, // VMLAslv2i32 = 2963 |
| 20359 | CEFBS_HasNEON, // VMLAslv4i16 = 2964 |
| 20360 | CEFBS_HasNEON, // VMLAslv4i32 = 2965 |
| 20361 | CEFBS_HasNEON, // VMLAslv8i16 = 2966 |
| 20362 | CEFBS_HasNEON, // VMLAv16i8 = 2967 |
| 20363 | CEFBS_HasNEON, // VMLAv2i32 = 2968 |
| 20364 | CEFBS_HasNEON, // VMLAv4i16 = 2969 |
| 20365 | CEFBS_HasNEON, // VMLAv4i32 = 2970 |
| 20366 | CEFBS_HasNEON, // VMLAv8i16 = 2971 |
| 20367 | CEFBS_HasNEON, // VMLAv8i8 = 2972 |
| 20368 | CEFBS_HasVFP2_HasDPVFP, // VMLSD = 2973 |
| 20369 | CEFBS_HasFullFP16, // VMLSH = 2974 |
| 20370 | CEFBS_HasNEON, // VMLSLslsv2i32 = 2975 |
| 20371 | CEFBS_HasNEON, // VMLSLslsv4i16 = 2976 |
| 20372 | CEFBS_HasNEON, // VMLSLsluv2i32 = 2977 |
| 20373 | CEFBS_HasNEON, // VMLSLsluv4i16 = 2978 |
| 20374 | CEFBS_HasNEON, // VMLSLsv2i64 = 2979 |
| 20375 | CEFBS_HasNEON, // VMLSLsv4i32 = 2980 |
| 20376 | CEFBS_HasNEON, // VMLSLsv8i16 = 2981 |
| 20377 | CEFBS_HasNEON, // VMLSLuv2i64 = 2982 |
| 20378 | CEFBS_HasNEON, // VMLSLuv4i32 = 2983 |
| 20379 | CEFBS_HasNEON, // VMLSLuv8i16 = 2984 |
| 20380 | CEFBS_HasVFP2, // VMLSS = 2985 |
| 20381 | CEFBS_HasNEON, // VMLSfd = 2986 |
| 20382 | CEFBS_HasNEON, // VMLSfq = 2987 |
| 20383 | CEFBS_HasNEON_HasFullFP16, // VMLShd = 2988 |
| 20384 | CEFBS_HasNEON_HasFullFP16, // VMLShq = 2989 |
| 20385 | CEFBS_HasNEON, // VMLSslfd = 2990 |
| 20386 | CEFBS_HasNEON, // VMLSslfq = 2991 |
| 20387 | CEFBS_HasNEON_HasFullFP16, // VMLSslhd = 2992 |
| 20388 | CEFBS_HasNEON_HasFullFP16, // VMLSslhq = 2993 |
| 20389 | CEFBS_HasNEON, // VMLSslv2i32 = 2994 |
| 20390 | CEFBS_HasNEON, // VMLSslv4i16 = 2995 |
| 20391 | CEFBS_HasNEON, // VMLSslv4i32 = 2996 |
| 20392 | CEFBS_HasNEON, // VMLSslv8i16 = 2997 |
| 20393 | CEFBS_HasNEON, // VMLSv16i8 = 2998 |
| 20394 | CEFBS_HasNEON, // VMLSv2i32 = 2999 |
| 20395 | CEFBS_HasNEON, // VMLSv4i16 = 3000 |
| 20396 | CEFBS_HasNEON, // VMLSv4i32 = 3001 |
| 20397 | CEFBS_HasNEON, // VMLSv8i16 = 3002 |
| 20398 | CEFBS_HasNEON, // VMLSv8i8 = 3003 |
| 20399 | CEFBS_HasBF16_HasNEON, // VMMLA = 3004 |
| 20400 | CEFBS_HasFPRegs64, // VMOVD = 3005 |
| 20401 | CEFBS_HasFPRegs, // VMOVDRR = 3006 |
| 20402 | CEFBS_HasFullFP16, // VMOVH = 3007 |
| 20403 | CEFBS_HasFPRegs16, // VMOVHR = 3008 |
| 20404 | CEFBS_HasNEON, // VMOVLsv2i64 = 3009 |
| 20405 | CEFBS_HasNEON, // VMOVLsv4i32 = 3010 |
| 20406 | CEFBS_HasNEON, // VMOVLsv8i16 = 3011 |
| 20407 | CEFBS_HasNEON, // VMOVLuv2i64 = 3012 |
| 20408 | CEFBS_HasNEON, // VMOVLuv4i32 = 3013 |
| 20409 | CEFBS_HasNEON, // VMOVLuv8i16 = 3014 |
| 20410 | CEFBS_HasNEON, // VMOVNv2i32 = 3015 |
| 20411 | CEFBS_HasNEON, // VMOVNv4i16 = 3016 |
| 20412 | CEFBS_HasNEON, // VMOVNv8i8 = 3017 |
| 20413 | CEFBS_HasFPRegs16, // VMOVRH = 3018 |
| 20414 | CEFBS_HasFPRegs, // VMOVRRD = 3019 |
| 20415 | CEFBS_HasFPRegs, // VMOVRRS = 3020 |
| 20416 | CEFBS_HasFPRegs, // VMOVRS = 3021 |
| 20417 | CEFBS_HasFPRegs, // VMOVS = 3022 |
| 20418 | CEFBS_HasFPRegs, // VMOVSR = 3023 |
| 20419 | CEFBS_HasFPRegs, // VMOVSRR = 3024 |
| 20420 | CEFBS_HasNEON, // VMOVv16i8 = 3025 |
| 20421 | CEFBS_HasNEON, // VMOVv1i64 = 3026 |
| 20422 | CEFBS_HasNEON, // VMOVv2f32 = 3027 |
| 20423 | CEFBS_HasNEON, // VMOVv2i32 = 3028 |
| 20424 | CEFBS_HasNEON, // VMOVv2i64 = 3029 |
| 20425 | CEFBS_HasNEON, // VMOVv4f32 = 3030 |
| 20426 | CEFBS_HasNEON, // VMOVv4i16 = 3031 |
| 20427 | CEFBS_HasNEON, // VMOVv4i32 = 3032 |
| 20428 | CEFBS_HasNEON, // VMOVv8i16 = 3033 |
| 20429 | CEFBS_HasNEON, // VMOVv8i8 = 3034 |
| 20430 | CEFBS_HasFPRegs, // VMRS = 3035 |
| 20431 | CEFBS_HasV8_1MMainline_Has8MSecExt, // VMRS_FPCXTNS = 3036 |
| 20432 | CEFBS_HasV8_1MMainline_Has8MSecExt, // VMRS_FPCXTS = 3037 |
| 20433 | CEFBS_HasVFP2, // VMRS_FPEXC = 3038 |
| 20434 | CEFBS_HasVFP2, // VMRS_FPINST = 3039 |
| 20435 | CEFBS_HasVFP2, // VMRS_FPINST2 = 3040 |
| 20436 | CEFBS_HasV8_1MMainline_HasFPRegs, // VMRS_FPSCR_NZCVQC = 3041 |
| 20437 | CEFBS_HasVFP2, // VMRS_FPSID = 3042 |
| 20438 | CEFBS_HasVFP2, // VMRS_MVFR0 = 3043 |
| 20439 | CEFBS_HasVFP2, // VMRS_MVFR1 = 3044 |
| 20440 | CEFBS_HasFPARMv8, // VMRS_MVFR2 = 3045 |
| 20441 | CEFBS_HasV8_1MMainline_HasMVEInt, // VMRS_P0 = 3046 |
| 20442 | CEFBS_HasV8_1MMainline_HasMVEInt, // VMRS_VPR = 3047 |
| 20443 | CEFBS_HasFPRegs, // VMSR = 3048 |
| 20444 | CEFBS_HasV8_1MMainline_Has8MSecExt, // VMSR_FPCXTNS = 3049 |
| 20445 | CEFBS_HasV8_1MMainline_Has8MSecExt, // VMSR_FPCXTS = 3050 |
| 20446 | CEFBS_HasVFP2, // VMSR_FPEXC = 3051 |
| 20447 | CEFBS_HasVFP2, // VMSR_FPINST = 3052 |
| 20448 | CEFBS_HasVFP2, // VMSR_FPINST2 = 3053 |
| 20449 | CEFBS_HasV8_1MMainline_HasFPRegs, // VMSR_FPSCR_NZCVQC = 3054 |
| 20450 | CEFBS_HasVFP2, // VMSR_FPSID = 3055 |
| 20451 | CEFBS_HasV8_1MMainline_HasMVEInt, // VMSR_P0 = 3056 |
| 20452 | CEFBS_HasV8_1MMainline_HasMVEInt, // VMSR_VPR = 3057 |
| 20453 | CEFBS_HasVFP2_HasDPVFP, // VMULD = 3058 |
| 20454 | CEFBS_HasFullFP16, // VMULH = 3059 |
| 20455 | CEFBS_HasV8_HasAES, // VMULLp64 = 3060 |
| 20456 | CEFBS_HasNEON, // VMULLp8 = 3061 |
| 20457 | CEFBS_HasNEON, // VMULLslsv2i32 = 3062 |
| 20458 | CEFBS_HasNEON, // VMULLslsv4i16 = 3063 |
| 20459 | CEFBS_HasNEON, // VMULLsluv2i32 = 3064 |
| 20460 | CEFBS_HasNEON, // VMULLsluv4i16 = 3065 |
| 20461 | CEFBS_HasNEON, // VMULLsv2i64 = 3066 |
| 20462 | CEFBS_HasNEON, // VMULLsv4i32 = 3067 |
| 20463 | CEFBS_HasNEON, // VMULLsv8i16 = 3068 |
| 20464 | CEFBS_HasNEON, // VMULLuv2i64 = 3069 |
| 20465 | CEFBS_HasNEON, // VMULLuv4i32 = 3070 |
| 20466 | CEFBS_HasNEON, // VMULLuv8i16 = 3071 |
| 20467 | CEFBS_HasVFP2, // VMULS = 3072 |
| 20468 | CEFBS_HasNEON, // VMULfd = 3073 |
| 20469 | CEFBS_HasNEON, // VMULfq = 3074 |
| 20470 | CEFBS_HasNEON_HasFullFP16, // VMULhd = 3075 |
| 20471 | CEFBS_HasNEON_HasFullFP16, // VMULhq = 3076 |
| 20472 | CEFBS_HasNEON, // VMULpd = 3077 |
| 20473 | CEFBS_HasNEON, // VMULpq = 3078 |
| 20474 | CEFBS_HasNEON, // VMULslfd = 3079 |
| 20475 | CEFBS_HasNEON, // VMULslfq = 3080 |
| 20476 | CEFBS_HasNEON_HasFullFP16, // VMULslhd = 3081 |
| 20477 | CEFBS_HasNEON_HasFullFP16, // VMULslhq = 3082 |
| 20478 | CEFBS_HasNEON, // VMULslv2i32 = 3083 |
| 20479 | CEFBS_HasNEON, // VMULslv4i16 = 3084 |
| 20480 | CEFBS_HasNEON, // VMULslv4i32 = 3085 |
| 20481 | CEFBS_HasNEON, // VMULslv8i16 = 3086 |
| 20482 | CEFBS_HasNEON, // VMULv16i8 = 3087 |
| 20483 | CEFBS_HasNEON, // VMULv2i32 = 3088 |
| 20484 | CEFBS_HasNEON, // VMULv4i16 = 3089 |
| 20485 | CEFBS_HasNEON, // VMULv4i32 = 3090 |
| 20486 | CEFBS_HasNEON, // VMULv8i16 = 3091 |
| 20487 | CEFBS_HasNEON, // VMULv8i8 = 3092 |
| 20488 | CEFBS_HasNEON, // VMVNd = 3093 |
| 20489 | CEFBS_HasNEON, // VMVNq = 3094 |
| 20490 | CEFBS_HasNEON, // VMVNv2i32 = 3095 |
| 20491 | CEFBS_HasNEON, // VMVNv4i16 = 3096 |
| 20492 | CEFBS_HasNEON, // VMVNv4i32 = 3097 |
| 20493 | CEFBS_HasNEON, // VMVNv8i16 = 3098 |
| 20494 | CEFBS_HasVFP2_HasDPVFP, // VNEGD = 3099 |
| 20495 | CEFBS_HasFullFP16, // VNEGH = 3100 |
| 20496 | CEFBS_HasVFP2, // VNEGS = 3101 |
| 20497 | CEFBS_HasNEON, // VNEGf32q = 3102 |
| 20498 | CEFBS_HasNEON, // VNEGfd = 3103 |
| 20499 | CEFBS_HasNEON_HasFullFP16, // VNEGhd = 3104 |
| 20500 | CEFBS_HasNEON_HasFullFP16, // VNEGhq = 3105 |
| 20501 | CEFBS_HasNEON, // VNEGs16d = 3106 |
| 20502 | CEFBS_HasNEON, // VNEGs16q = 3107 |
| 20503 | CEFBS_HasNEON, // VNEGs32d = 3108 |
| 20504 | CEFBS_HasNEON, // VNEGs32q = 3109 |
| 20505 | CEFBS_HasNEON, // VNEGs8d = 3110 |
| 20506 | CEFBS_HasNEON, // VNEGs8q = 3111 |
| 20507 | CEFBS_HasVFP2_HasDPVFP, // VNMLAD = 3112 |
| 20508 | CEFBS_HasFullFP16, // VNMLAH = 3113 |
| 20509 | CEFBS_HasVFP2, // VNMLAS = 3114 |
| 20510 | CEFBS_HasVFP2_HasDPVFP, // VNMLSD = 3115 |
| 20511 | CEFBS_HasFullFP16, // VNMLSH = 3116 |
| 20512 | CEFBS_HasVFP2, // VNMLSS = 3117 |
| 20513 | CEFBS_HasVFP2_HasDPVFP, // VNMULD = 3118 |
| 20514 | CEFBS_HasFullFP16, // VNMULH = 3119 |
| 20515 | CEFBS_HasVFP2, // VNMULS = 3120 |
| 20516 | CEFBS_HasNEON, // VORNd = 3121 |
| 20517 | CEFBS_HasNEON, // VORNq = 3122 |
| 20518 | CEFBS_HasNEON, // VORRd = 3123 |
| 20519 | CEFBS_HasNEON, // VORRiv2i32 = 3124 |
| 20520 | CEFBS_HasNEON, // VORRiv4i16 = 3125 |
| 20521 | CEFBS_HasNEON, // VORRiv4i32 = 3126 |
| 20522 | CEFBS_HasNEON, // VORRiv8i16 = 3127 |
| 20523 | CEFBS_HasNEON, // VORRq = 3128 |
| 20524 | CEFBS_HasNEON, // VPADALsv16i8 = 3129 |
| 20525 | CEFBS_HasNEON, // VPADALsv2i32 = 3130 |
| 20526 | CEFBS_HasNEON, // VPADALsv4i16 = 3131 |
| 20527 | CEFBS_HasNEON, // VPADALsv4i32 = 3132 |
| 20528 | CEFBS_HasNEON, // VPADALsv8i16 = 3133 |
| 20529 | CEFBS_HasNEON, // VPADALsv8i8 = 3134 |
| 20530 | CEFBS_HasNEON, // VPADALuv16i8 = 3135 |
| 20531 | CEFBS_HasNEON, // VPADALuv2i32 = 3136 |
| 20532 | CEFBS_HasNEON, // VPADALuv4i16 = 3137 |
| 20533 | CEFBS_HasNEON, // VPADALuv4i32 = 3138 |
| 20534 | CEFBS_HasNEON, // VPADALuv8i16 = 3139 |
| 20535 | CEFBS_HasNEON, // VPADALuv8i8 = 3140 |
| 20536 | CEFBS_HasNEON, // VPADDLsv16i8 = 3141 |
| 20537 | CEFBS_HasNEON, // VPADDLsv2i32 = 3142 |
| 20538 | CEFBS_HasNEON, // VPADDLsv4i16 = 3143 |
| 20539 | CEFBS_HasNEON, // VPADDLsv4i32 = 3144 |
| 20540 | CEFBS_HasNEON, // VPADDLsv8i16 = 3145 |
| 20541 | CEFBS_HasNEON, // VPADDLsv8i8 = 3146 |
| 20542 | CEFBS_HasNEON, // VPADDLuv16i8 = 3147 |
| 20543 | CEFBS_HasNEON, // VPADDLuv2i32 = 3148 |
| 20544 | CEFBS_HasNEON, // VPADDLuv4i16 = 3149 |
| 20545 | CEFBS_HasNEON, // VPADDLuv4i32 = 3150 |
| 20546 | CEFBS_HasNEON, // VPADDLuv8i16 = 3151 |
| 20547 | CEFBS_HasNEON, // VPADDLuv8i8 = 3152 |
| 20548 | CEFBS_HasNEON, // VPADDf = 3153 |
| 20549 | CEFBS_HasNEON_HasFullFP16, // VPADDh = 3154 |
| 20550 | CEFBS_HasNEON, // VPADDi16 = 3155 |
| 20551 | CEFBS_HasNEON, // VPADDi32 = 3156 |
| 20552 | CEFBS_HasNEON, // VPADDi8 = 3157 |
| 20553 | CEFBS_HasNEON, // VPMAXf = 3158 |
| 20554 | CEFBS_HasNEON_HasFullFP16, // VPMAXh = 3159 |
| 20555 | CEFBS_HasNEON, // VPMAXs16 = 3160 |
| 20556 | CEFBS_HasNEON, // VPMAXs32 = 3161 |
| 20557 | CEFBS_HasNEON, // VPMAXs8 = 3162 |
| 20558 | CEFBS_HasNEON, // VPMAXu16 = 3163 |
| 20559 | CEFBS_HasNEON, // VPMAXu32 = 3164 |
| 20560 | CEFBS_HasNEON, // VPMAXu8 = 3165 |
| 20561 | CEFBS_HasNEON, // VPMINf = 3166 |
| 20562 | CEFBS_HasNEON_HasFullFP16, // VPMINh = 3167 |
| 20563 | CEFBS_HasNEON, // VPMINs16 = 3168 |
| 20564 | CEFBS_HasNEON, // VPMINs32 = 3169 |
| 20565 | CEFBS_HasNEON, // VPMINs8 = 3170 |
| 20566 | CEFBS_HasNEON, // VPMINu16 = 3171 |
| 20567 | CEFBS_HasNEON, // VPMINu32 = 3172 |
| 20568 | CEFBS_HasNEON, // VPMINu8 = 3173 |
| 20569 | CEFBS_HasNEON, // VQABSv16i8 = 3174 |
| 20570 | CEFBS_HasNEON, // VQABSv2i32 = 3175 |
| 20571 | CEFBS_HasNEON, // VQABSv4i16 = 3176 |
| 20572 | CEFBS_HasNEON, // VQABSv4i32 = 3177 |
| 20573 | CEFBS_HasNEON, // VQABSv8i16 = 3178 |
| 20574 | CEFBS_HasNEON, // VQABSv8i8 = 3179 |
| 20575 | CEFBS_HasNEON, // VQADDsv16i8 = 3180 |
| 20576 | CEFBS_HasNEON, // VQADDsv1i64 = 3181 |
| 20577 | CEFBS_HasNEON, // VQADDsv2i32 = 3182 |
| 20578 | CEFBS_HasNEON, // VQADDsv2i64 = 3183 |
| 20579 | CEFBS_HasNEON, // VQADDsv4i16 = 3184 |
| 20580 | CEFBS_HasNEON, // VQADDsv4i32 = 3185 |
| 20581 | CEFBS_HasNEON, // VQADDsv8i16 = 3186 |
| 20582 | CEFBS_HasNEON, // VQADDsv8i8 = 3187 |
| 20583 | CEFBS_HasNEON, // VQADDuv16i8 = 3188 |
| 20584 | CEFBS_HasNEON, // VQADDuv1i64 = 3189 |
| 20585 | CEFBS_HasNEON, // VQADDuv2i32 = 3190 |
| 20586 | CEFBS_HasNEON, // VQADDuv2i64 = 3191 |
| 20587 | CEFBS_HasNEON, // VQADDuv4i16 = 3192 |
| 20588 | CEFBS_HasNEON, // VQADDuv4i32 = 3193 |
| 20589 | CEFBS_HasNEON, // VQADDuv8i16 = 3194 |
| 20590 | CEFBS_HasNEON, // VQADDuv8i8 = 3195 |
| 20591 | CEFBS_HasNEON, // VQDMLALslv2i32 = 3196 |
| 20592 | CEFBS_HasNEON, // VQDMLALslv4i16 = 3197 |
| 20593 | CEFBS_HasNEON, // VQDMLALv2i64 = 3198 |
| 20594 | CEFBS_HasNEON, // VQDMLALv4i32 = 3199 |
| 20595 | CEFBS_HasNEON, // VQDMLSLslv2i32 = 3200 |
| 20596 | CEFBS_HasNEON, // VQDMLSLslv4i16 = 3201 |
| 20597 | CEFBS_HasNEON, // VQDMLSLv2i64 = 3202 |
| 20598 | CEFBS_HasNEON, // VQDMLSLv4i32 = 3203 |
| 20599 | CEFBS_HasNEON, // VQDMULHslv2i32 = 3204 |
| 20600 | CEFBS_HasNEON, // VQDMULHslv4i16 = 3205 |
| 20601 | CEFBS_HasNEON, // VQDMULHslv4i32 = 3206 |
| 20602 | CEFBS_HasNEON, // VQDMULHslv8i16 = 3207 |
| 20603 | CEFBS_HasNEON, // VQDMULHv2i32 = 3208 |
| 20604 | CEFBS_HasNEON, // VQDMULHv4i16 = 3209 |
| 20605 | CEFBS_HasNEON, // VQDMULHv4i32 = 3210 |
| 20606 | CEFBS_HasNEON, // VQDMULHv8i16 = 3211 |
| 20607 | CEFBS_HasNEON, // VQDMULLslv2i32 = 3212 |
| 20608 | CEFBS_HasNEON, // VQDMULLslv4i16 = 3213 |
| 20609 | CEFBS_HasNEON, // VQDMULLv2i64 = 3214 |
| 20610 | CEFBS_HasNEON, // VQDMULLv4i32 = 3215 |
| 20611 | CEFBS_HasNEON, // VQMOVNsuv2i32 = 3216 |
| 20612 | CEFBS_HasNEON, // VQMOVNsuv4i16 = 3217 |
| 20613 | CEFBS_HasNEON, // VQMOVNsuv8i8 = 3218 |
| 20614 | CEFBS_HasNEON, // VQMOVNsv2i32 = 3219 |
| 20615 | CEFBS_HasNEON, // VQMOVNsv4i16 = 3220 |
| 20616 | CEFBS_HasNEON, // VQMOVNsv8i8 = 3221 |
| 20617 | CEFBS_HasNEON, // VQMOVNuv2i32 = 3222 |
| 20618 | CEFBS_HasNEON, // VQMOVNuv4i16 = 3223 |
| 20619 | CEFBS_HasNEON, // VQMOVNuv8i8 = 3224 |
| 20620 | CEFBS_HasNEON, // VQNEGv16i8 = 3225 |
| 20621 | CEFBS_HasNEON, // VQNEGv2i32 = 3226 |
| 20622 | CEFBS_HasNEON, // VQNEGv4i16 = 3227 |
| 20623 | CEFBS_HasNEON, // VQNEGv4i32 = 3228 |
| 20624 | CEFBS_HasNEON, // VQNEGv8i16 = 3229 |
| 20625 | CEFBS_HasNEON, // VQNEGv8i8 = 3230 |
| 20626 | CEFBS_HasNEON_HasV8_1a, // VQRDMLAHslv2i32 = 3231 |
| 20627 | CEFBS_HasNEON_HasV8_1a, // VQRDMLAHslv4i16 = 3232 |
| 20628 | CEFBS_HasNEON_HasV8_1a, // VQRDMLAHslv4i32 = 3233 |
| 20629 | CEFBS_HasNEON_HasV8_1a, // VQRDMLAHslv8i16 = 3234 |
| 20630 | CEFBS_HasNEON_HasV8_1a, // VQRDMLAHv2i32 = 3235 |
| 20631 | CEFBS_HasNEON_HasV8_1a, // VQRDMLAHv4i16 = 3236 |
| 20632 | CEFBS_HasNEON_HasV8_1a, // VQRDMLAHv4i32 = 3237 |
| 20633 | CEFBS_HasNEON_HasV8_1a, // VQRDMLAHv8i16 = 3238 |
| 20634 | CEFBS_HasNEON_HasV8_1a, // VQRDMLSHslv2i32 = 3239 |
| 20635 | CEFBS_HasNEON_HasV8_1a, // VQRDMLSHslv4i16 = 3240 |
| 20636 | CEFBS_HasNEON_HasV8_1a, // VQRDMLSHslv4i32 = 3241 |
| 20637 | CEFBS_HasNEON_HasV8_1a, // VQRDMLSHslv8i16 = 3242 |
| 20638 | CEFBS_HasNEON_HasV8_1a, // VQRDMLSHv2i32 = 3243 |
| 20639 | CEFBS_HasNEON_HasV8_1a, // VQRDMLSHv4i16 = 3244 |
| 20640 | CEFBS_HasNEON_HasV8_1a, // VQRDMLSHv4i32 = 3245 |
| 20641 | CEFBS_HasNEON_HasV8_1a, // VQRDMLSHv8i16 = 3246 |
| 20642 | CEFBS_HasNEON, // VQRDMULHslv2i32 = 3247 |
| 20643 | CEFBS_HasNEON, // VQRDMULHslv4i16 = 3248 |
| 20644 | CEFBS_HasNEON, // VQRDMULHslv4i32 = 3249 |
| 20645 | CEFBS_HasNEON, // VQRDMULHslv8i16 = 3250 |
| 20646 | CEFBS_HasNEON, // VQRDMULHv2i32 = 3251 |
| 20647 | CEFBS_HasNEON, // VQRDMULHv4i16 = 3252 |
| 20648 | CEFBS_HasNEON, // VQRDMULHv4i32 = 3253 |
| 20649 | CEFBS_HasNEON, // VQRDMULHv8i16 = 3254 |
| 20650 | CEFBS_HasNEON, // VQRSHLsv16i8 = 3255 |
| 20651 | CEFBS_HasNEON, // VQRSHLsv1i64 = 3256 |
| 20652 | CEFBS_HasNEON, // VQRSHLsv2i32 = 3257 |
| 20653 | CEFBS_HasNEON, // VQRSHLsv2i64 = 3258 |
| 20654 | CEFBS_HasNEON, // VQRSHLsv4i16 = 3259 |
| 20655 | CEFBS_HasNEON, // VQRSHLsv4i32 = 3260 |
| 20656 | CEFBS_HasNEON, // VQRSHLsv8i16 = 3261 |
| 20657 | CEFBS_HasNEON, // VQRSHLsv8i8 = 3262 |
| 20658 | CEFBS_HasNEON, // VQRSHLuv16i8 = 3263 |
| 20659 | CEFBS_HasNEON, // VQRSHLuv1i64 = 3264 |
| 20660 | CEFBS_HasNEON, // VQRSHLuv2i32 = 3265 |
| 20661 | CEFBS_HasNEON, // VQRSHLuv2i64 = 3266 |
| 20662 | CEFBS_HasNEON, // VQRSHLuv4i16 = 3267 |
| 20663 | CEFBS_HasNEON, // VQRSHLuv4i32 = 3268 |
| 20664 | CEFBS_HasNEON, // VQRSHLuv8i16 = 3269 |
| 20665 | CEFBS_HasNEON, // VQRSHLuv8i8 = 3270 |
| 20666 | CEFBS_HasNEON, // VQRSHRNsv2i32 = 3271 |
| 20667 | CEFBS_HasNEON, // VQRSHRNsv4i16 = 3272 |
| 20668 | CEFBS_HasNEON, // VQRSHRNsv8i8 = 3273 |
| 20669 | CEFBS_HasNEON, // VQRSHRNuv2i32 = 3274 |
| 20670 | CEFBS_HasNEON, // VQRSHRNuv4i16 = 3275 |
| 20671 | CEFBS_HasNEON, // VQRSHRNuv8i8 = 3276 |
| 20672 | CEFBS_HasNEON, // VQRSHRUNv2i32 = 3277 |
| 20673 | CEFBS_HasNEON, // VQRSHRUNv4i16 = 3278 |
| 20674 | CEFBS_HasNEON, // VQRSHRUNv8i8 = 3279 |
| 20675 | CEFBS_HasNEON, // VQSHLsiv16i8 = 3280 |
| 20676 | CEFBS_HasNEON, // VQSHLsiv1i64 = 3281 |
| 20677 | CEFBS_HasNEON, // VQSHLsiv2i32 = 3282 |
| 20678 | CEFBS_HasNEON, // VQSHLsiv2i64 = 3283 |
| 20679 | CEFBS_HasNEON, // VQSHLsiv4i16 = 3284 |
| 20680 | CEFBS_HasNEON, // VQSHLsiv4i32 = 3285 |
| 20681 | CEFBS_HasNEON, // VQSHLsiv8i16 = 3286 |
| 20682 | CEFBS_HasNEON, // VQSHLsiv8i8 = 3287 |
| 20683 | CEFBS_HasNEON, // VQSHLsuv16i8 = 3288 |
| 20684 | CEFBS_HasNEON, // VQSHLsuv1i64 = 3289 |
| 20685 | CEFBS_HasNEON, // VQSHLsuv2i32 = 3290 |
| 20686 | CEFBS_HasNEON, // VQSHLsuv2i64 = 3291 |
| 20687 | CEFBS_HasNEON, // VQSHLsuv4i16 = 3292 |
| 20688 | CEFBS_HasNEON, // VQSHLsuv4i32 = 3293 |
| 20689 | CEFBS_HasNEON, // VQSHLsuv8i16 = 3294 |
| 20690 | CEFBS_HasNEON, // VQSHLsuv8i8 = 3295 |
| 20691 | CEFBS_HasNEON, // VQSHLsv16i8 = 3296 |
| 20692 | CEFBS_HasNEON, // VQSHLsv1i64 = 3297 |
| 20693 | CEFBS_HasNEON, // VQSHLsv2i32 = 3298 |
| 20694 | CEFBS_HasNEON, // VQSHLsv2i64 = 3299 |
| 20695 | CEFBS_HasNEON, // VQSHLsv4i16 = 3300 |
| 20696 | CEFBS_HasNEON, // VQSHLsv4i32 = 3301 |
| 20697 | CEFBS_HasNEON, // VQSHLsv8i16 = 3302 |
| 20698 | CEFBS_HasNEON, // VQSHLsv8i8 = 3303 |
| 20699 | CEFBS_HasNEON, // VQSHLuiv16i8 = 3304 |
| 20700 | CEFBS_HasNEON, // VQSHLuiv1i64 = 3305 |
| 20701 | CEFBS_HasNEON, // VQSHLuiv2i32 = 3306 |
| 20702 | CEFBS_HasNEON, // VQSHLuiv2i64 = 3307 |
| 20703 | CEFBS_HasNEON, // VQSHLuiv4i16 = 3308 |
| 20704 | CEFBS_HasNEON, // VQSHLuiv4i32 = 3309 |
| 20705 | CEFBS_HasNEON, // VQSHLuiv8i16 = 3310 |
| 20706 | CEFBS_HasNEON, // VQSHLuiv8i8 = 3311 |
| 20707 | CEFBS_HasNEON, // VQSHLuv16i8 = 3312 |
| 20708 | CEFBS_HasNEON, // VQSHLuv1i64 = 3313 |
| 20709 | CEFBS_HasNEON, // VQSHLuv2i32 = 3314 |
| 20710 | CEFBS_HasNEON, // VQSHLuv2i64 = 3315 |
| 20711 | CEFBS_HasNEON, // VQSHLuv4i16 = 3316 |
| 20712 | CEFBS_HasNEON, // VQSHLuv4i32 = 3317 |
| 20713 | CEFBS_HasNEON, // VQSHLuv8i16 = 3318 |
| 20714 | CEFBS_HasNEON, // VQSHLuv8i8 = 3319 |
| 20715 | CEFBS_HasNEON, // VQSHRNsv2i32 = 3320 |
| 20716 | CEFBS_HasNEON, // VQSHRNsv4i16 = 3321 |
| 20717 | CEFBS_HasNEON, // VQSHRNsv8i8 = 3322 |
| 20718 | CEFBS_HasNEON, // VQSHRNuv2i32 = 3323 |
| 20719 | CEFBS_HasNEON, // VQSHRNuv4i16 = 3324 |
| 20720 | CEFBS_HasNEON, // VQSHRNuv8i8 = 3325 |
| 20721 | CEFBS_HasNEON, // VQSHRUNv2i32 = 3326 |
| 20722 | CEFBS_HasNEON, // VQSHRUNv4i16 = 3327 |
| 20723 | CEFBS_HasNEON, // VQSHRUNv8i8 = 3328 |
| 20724 | CEFBS_HasNEON, // VQSUBsv16i8 = 3329 |
| 20725 | CEFBS_HasNEON, // VQSUBsv1i64 = 3330 |
| 20726 | CEFBS_HasNEON, // VQSUBsv2i32 = 3331 |
| 20727 | CEFBS_HasNEON, // VQSUBsv2i64 = 3332 |
| 20728 | CEFBS_HasNEON, // VQSUBsv4i16 = 3333 |
| 20729 | CEFBS_HasNEON, // VQSUBsv4i32 = 3334 |
| 20730 | CEFBS_HasNEON, // VQSUBsv8i16 = 3335 |
| 20731 | CEFBS_HasNEON, // VQSUBsv8i8 = 3336 |
| 20732 | CEFBS_HasNEON, // VQSUBuv16i8 = 3337 |
| 20733 | CEFBS_HasNEON, // VQSUBuv1i64 = 3338 |
| 20734 | CEFBS_HasNEON, // VQSUBuv2i32 = 3339 |
| 20735 | CEFBS_HasNEON, // VQSUBuv2i64 = 3340 |
| 20736 | CEFBS_HasNEON, // VQSUBuv4i16 = 3341 |
| 20737 | CEFBS_HasNEON, // VQSUBuv4i32 = 3342 |
| 20738 | CEFBS_HasNEON, // VQSUBuv8i16 = 3343 |
| 20739 | CEFBS_HasNEON, // VQSUBuv8i8 = 3344 |
| 20740 | CEFBS_HasNEON, // VRADDHNv2i32 = 3345 |
| 20741 | CEFBS_HasNEON, // VRADDHNv4i16 = 3346 |
| 20742 | CEFBS_HasNEON, // VRADDHNv8i8 = 3347 |
| 20743 | CEFBS_HasNEON, // VRECPEd = 3348 |
| 20744 | CEFBS_HasNEON, // VRECPEfd = 3349 |
| 20745 | CEFBS_HasNEON, // VRECPEfq = 3350 |
| 20746 | CEFBS_HasNEON_HasFullFP16, // VRECPEhd = 3351 |
| 20747 | CEFBS_HasNEON_HasFullFP16, // VRECPEhq = 3352 |
| 20748 | CEFBS_HasNEON, // VRECPEq = 3353 |
| 20749 | CEFBS_HasNEON, // VRECPSfd = 3354 |
| 20750 | CEFBS_HasNEON, // VRECPSfq = 3355 |
| 20751 | CEFBS_HasNEON_HasFullFP16, // VRECPShd = 3356 |
| 20752 | CEFBS_HasNEON_HasFullFP16, // VRECPShq = 3357 |
| 20753 | CEFBS_HasNEON, // VREV16d8 = 3358 |
| 20754 | CEFBS_HasNEON, // VREV16q8 = 3359 |
| 20755 | CEFBS_HasNEON, // VREV32d16 = 3360 |
| 20756 | CEFBS_HasNEON, // VREV32d8 = 3361 |
| 20757 | CEFBS_HasNEON, // VREV32q16 = 3362 |
| 20758 | CEFBS_HasNEON, // VREV32q8 = 3363 |
| 20759 | CEFBS_HasNEON, // VREV64d16 = 3364 |
| 20760 | CEFBS_HasNEON, // VREV64d32 = 3365 |
| 20761 | CEFBS_HasNEON, // VREV64d8 = 3366 |
| 20762 | CEFBS_HasNEON, // VREV64q16 = 3367 |
| 20763 | CEFBS_HasNEON, // VREV64q32 = 3368 |
| 20764 | CEFBS_HasNEON, // VREV64q8 = 3369 |
| 20765 | CEFBS_HasNEON, // VRHADDsv16i8 = 3370 |
| 20766 | CEFBS_HasNEON, // VRHADDsv2i32 = 3371 |
| 20767 | CEFBS_HasNEON, // VRHADDsv4i16 = 3372 |
| 20768 | CEFBS_HasNEON, // VRHADDsv4i32 = 3373 |
| 20769 | CEFBS_HasNEON, // VRHADDsv8i16 = 3374 |
| 20770 | CEFBS_HasNEON, // VRHADDsv8i8 = 3375 |
| 20771 | CEFBS_HasNEON, // VRHADDuv16i8 = 3376 |
| 20772 | CEFBS_HasNEON, // VRHADDuv2i32 = 3377 |
| 20773 | CEFBS_HasNEON, // VRHADDuv4i16 = 3378 |
| 20774 | CEFBS_HasNEON, // VRHADDuv4i32 = 3379 |
| 20775 | CEFBS_HasNEON, // VRHADDuv8i16 = 3380 |
| 20776 | CEFBS_HasNEON, // VRHADDuv8i8 = 3381 |
| 20777 | CEFBS_HasFPARMv8_HasDPVFP, // VRINTAD = 3382 |
| 20778 | CEFBS_HasFullFP16, // VRINTAH = 3383 |
| 20779 | CEFBS_HasV8_HasNEON, // VRINTANDf = 3384 |
| 20780 | CEFBS_HasV8_HasNEON_HasFullFP16, // VRINTANDh = 3385 |
| 20781 | CEFBS_HasV8_HasNEON, // VRINTANQf = 3386 |
| 20782 | CEFBS_HasV8_HasNEON_HasFullFP16, // VRINTANQh = 3387 |
| 20783 | CEFBS_HasFPARMv8, // VRINTAS = 3388 |
| 20784 | CEFBS_HasFPARMv8_HasDPVFP, // VRINTMD = 3389 |
| 20785 | CEFBS_HasFullFP16, // VRINTMH = 3390 |
| 20786 | CEFBS_HasV8_HasNEON, // VRINTMNDf = 3391 |
| 20787 | CEFBS_HasV8_HasNEON_HasFullFP16, // VRINTMNDh = 3392 |
| 20788 | CEFBS_HasV8_HasNEON, // VRINTMNQf = 3393 |
| 20789 | CEFBS_HasV8_HasNEON_HasFullFP16, // VRINTMNQh = 3394 |
| 20790 | CEFBS_HasFPARMv8, // VRINTMS = 3395 |
| 20791 | CEFBS_HasFPARMv8_HasDPVFP, // VRINTND = 3396 |
| 20792 | CEFBS_HasFullFP16, // VRINTNH = 3397 |
| 20793 | CEFBS_HasV8_HasNEON, // VRINTNNDf = 3398 |
| 20794 | CEFBS_HasV8_HasNEON_HasFullFP16, // VRINTNNDh = 3399 |
| 20795 | CEFBS_HasV8_HasNEON, // VRINTNNQf = 3400 |
| 20796 | CEFBS_HasV8_HasNEON_HasFullFP16, // VRINTNNQh = 3401 |
| 20797 | CEFBS_HasFPARMv8, // VRINTNS = 3402 |
| 20798 | CEFBS_HasFPARMv8_HasDPVFP, // VRINTPD = 3403 |
| 20799 | CEFBS_HasFullFP16, // VRINTPH = 3404 |
| 20800 | CEFBS_HasV8_HasNEON, // VRINTPNDf = 3405 |
| 20801 | CEFBS_HasV8_HasNEON_HasFullFP16, // VRINTPNDh = 3406 |
| 20802 | CEFBS_HasV8_HasNEON, // VRINTPNQf = 3407 |
| 20803 | CEFBS_HasV8_HasNEON_HasFullFP16, // VRINTPNQh = 3408 |
| 20804 | CEFBS_HasFPARMv8, // VRINTPS = 3409 |
| 20805 | CEFBS_HasFPARMv8_HasDPVFP, // VRINTRD = 3410 |
| 20806 | CEFBS_HasFullFP16, // VRINTRH = 3411 |
| 20807 | CEFBS_HasFPARMv8, // VRINTRS = 3412 |
| 20808 | CEFBS_HasFPARMv8_HasDPVFP, // VRINTXD = 3413 |
| 20809 | CEFBS_HasFullFP16, // VRINTXH = 3414 |
| 20810 | CEFBS_HasV8_HasNEON, // VRINTXNDf = 3415 |
| 20811 | CEFBS_HasV8_HasNEON_HasFullFP16, // VRINTXNDh = 3416 |
| 20812 | CEFBS_HasV8_HasNEON, // VRINTXNQf = 3417 |
| 20813 | CEFBS_HasV8_HasNEON_HasFullFP16, // VRINTXNQh = 3418 |
| 20814 | CEFBS_HasFPARMv8, // VRINTXS = 3419 |
| 20815 | CEFBS_HasFPARMv8_HasDPVFP, // VRINTZD = 3420 |
| 20816 | CEFBS_HasFullFP16, // VRINTZH = 3421 |
| 20817 | CEFBS_HasV8_HasNEON, // VRINTZNDf = 3422 |
| 20818 | CEFBS_HasV8_HasNEON_HasFullFP16, // VRINTZNDh = 3423 |
| 20819 | CEFBS_HasV8_HasNEON, // VRINTZNQf = 3424 |
| 20820 | CEFBS_HasV8_HasNEON_HasFullFP16, // VRINTZNQh = 3425 |
| 20821 | CEFBS_HasFPARMv8, // VRINTZS = 3426 |
| 20822 | CEFBS_HasNEON, // VRSHLsv16i8 = 3427 |
| 20823 | CEFBS_HasNEON, // VRSHLsv1i64 = 3428 |
| 20824 | CEFBS_HasNEON, // VRSHLsv2i32 = 3429 |
| 20825 | CEFBS_HasNEON, // VRSHLsv2i64 = 3430 |
| 20826 | CEFBS_HasNEON, // VRSHLsv4i16 = 3431 |
| 20827 | CEFBS_HasNEON, // VRSHLsv4i32 = 3432 |
| 20828 | CEFBS_HasNEON, // VRSHLsv8i16 = 3433 |
| 20829 | CEFBS_HasNEON, // VRSHLsv8i8 = 3434 |
| 20830 | CEFBS_HasNEON, // VRSHLuv16i8 = 3435 |
| 20831 | CEFBS_HasNEON, // VRSHLuv1i64 = 3436 |
| 20832 | CEFBS_HasNEON, // VRSHLuv2i32 = 3437 |
| 20833 | CEFBS_HasNEON, // VRSHLuv2i64 = 3438 |
| 20834 | CEFBS_HasNEON, // VRSHLuv4i16 = 3439 |
| 20835 | CEFBS_HasNEON, // VRSHLuv4i32 = 3440 |
| 20836 | CEFBS_HasNEON, // VRSHLuv8i16 = 3441 |
| 20837 | CEFBS_HasNEON, // VRSHLuv8i8 = 3442 |
| 20838 | CEFBS_HasNEON, // VRSHRNv2i32 = 3443 |
| 20839 | CEFBS_HasNEON, // VRSHRNv4i16 = 3444 |
| 20840 | CEFBS_HasNEON, // VRSHRNv8i8 = 3445 |
| 20841 | CEFBS_HasNEON, // VRSHRsv16i8 = 3446 |
| 20842 | CEFBS_HasNEON, // VRSHRsv1i64 = 3447 |
| 20843 | CEFBS_HasNEON, // VRSHRsv2i32 = 3448 |
| 20844 | CEFBS_HasNEON, // VRSHRsv2i64 = 3449 |
| 20845 | CEFBS_HasNEON, // VRSHRsv4i16 = 3450 |
| 20846 | CEFBS_HasNEON, // VRSHRsv4i32 = 3451 |
| 20847 | CEFBS_HasNEON, // VRSHRsv8i16 = 3452 |
| 20848 | CEFBS_HasNEON, // VRSHRsv8i8 = 3453 |
| 20849 | CEFBS_HasNEON, // VRSHRuv16i8 = 3454 |
| 20850 | CEFBS_HasNEON, // VRSHRuv1i64 = 3455 |
| 20851 | CEFBS_HasNEON, // VRSHRuv2i32 = 3456 |
| 20852 | CEFBS_HasNEON, // VRSHRuv2i64 = 3457 |
| 20853 | CEFBS_HasNEON, // VRSHRuv4i16 = 3458 |
| 20854 | CEFBS_HasNEON, // VRSHRuv4i32 = 3459 |
| 20855 | CEFBS_HasNEON, // VRSHRuv8i16 = 3460 |
| 20856 | CEFBS_HasNEON, // VRSHRuv8i8 = 3461 |
| 20857 | CEFBS_HasNEON, // VRSQRTEd = 3462 |
| 20858 | CEFBS_HasNEON, // VRSQRTEfd = 3463 |
| 20859 | CEFBS_HasNEON, // VRSQRTEfq = 3464 |
| 20860 | CEFBS_HasNEON_HasFullFP16, // VRSQRTEhd = 3465 |
| 20861 | CEFBS_HasNEON_HasFullFP16, // VRSQRTEhq = 3466 |
| 20862 | CEFBS_HasNEON, // VRSQRTEq = 3467 |
| 20863 | CEFBS_HasNEON, // VRSQRTSfd = 3468 |
| 20864 | CEFBS_HasNEON, // VRSQRTSfq = 3469 |
| 20865 | CEFBS_HasNEON_HasFullFP16, // VRSQRTShd = 3470 |
| 20866 | CEFBS_HasNEON_HasFullFP16, // VRSQRTShq = 3471 |
| 20867 | CEFBS_HasNEON, // VRSRAsv16i8 = 3472 |
| 20868 | CEFBS_HasNEON, // VRSRAsv1i64 = 3473 |
| 20869 | CEFBS_HasNEON, // VRSRAsv2i32 = 3474 |
| 20870 | CEFBS_HasNEON, // VRSRAsv2i64 = 3475 |
| 20871 | CEFBS_HasNEON, // VRSRAsv4i16 = 3476 |
| 20872 | CEFBS_HasNEON, // VRSRAsv4i32 = 3477 |
| 20873 | CEFBS_HasNEON, // VRSRAsv8i16 = 3478 |
| 20874 | CEFBS_HasNEON, // VRSRAsv8i8 = 3479 |
| 20875 | CEFBS_HasNEON, // VRSRAuv16i8 = 3480 |
| 20876 | CEFBS_HasNEON, // VRSRAuv1i64 = 3481 |
| 20877 | CEFBS_HasNEON, // VRSRAuv2i32 = 3482 |
| 20878 | CEFBS_HasNEON, // VRSRAuv2i64 = 3483 |
| 20879 | CEFBS_HasNEON, // VRSRAuv4i16 = 3484 |
| 20880 | CEFBS_HasNEON, // VRSRAuv4i32 = 3485 |
| 20881 | CEFBS_HasNEON, // VRSRAuv8i16 = 3486 |
| 20882 | CEFBS_HasNEON, // VRSRAuv8i8 = 3487 |
| 20883 | CEFBS_HasNEON, // VRSUBHNv2i32 = 3488 |
| 20884 | CEFBS_HasNEON, // VRSUBHNv4i16 = 3489 |
| 20885 | CEFBS_HasNEON, // VRSUBHNv8i8 = 3490 |
| 20886 | CEFBS_HasV8_1MMainline_Has8MSecExt, // VSCCLRMD = 3491 |
| 20887 | CEFBS_HasV8_1MMainline_Has8MSecExt, // VSCCLRMS = 3492 |
| 20888 | CEFBS_HasDotProd, // VSDOTD = 3493 |
| 20889 | CEFBS_HasDotProd, // VSDOTDI = 3494 |
| 20890 | CEFBS_HasDotProd, // VSDOTQ = 3495 |
| 20891 | CEFBS_HasDotProd, // VSDOTQI = 3496 |
| 20892 | CEFBS_HasFPARMv8_HasDPVFP, // VSELEQD = 3497 |
| 20893 | CEFBS_HasFullFP16, // VSELEQH = 3498 |
| 20894 | CEFBS_HasFPARMv8, // VSELEQS = 3499 |
| 20895 | CEFBS_HasFPARMv8_HasDPVFP, // VSELGED = 3500 |
| 20896 | CEFBS_HasFullFP16, // VSELGEH = 3501 |
| 20897 | CEFBS_HasFPARMv8, // VSELGES = 3502 |
| 20898 | CEFBS_HasFPARMv8_HasDPVFP, // VSELGTD = 3503 |
| 20899 | CEFBS_HasFullFP16, // VSELGTH = 3504 |
| 20900 | CEFBS_HasFPARMv8, // VSELGTS = 3505 |
| 20901 | CEFBS_HasFPARMv8_HasDPVFP, // VSELVSD = 3506 |
| 20902 | CEFBS_HasFullFP16, // VSELVSH = 3507 |
| 20903 | CEFBS_HasFPARMv8, // VSELVSS = 3508 |
| 20904 | CEFBS_HasNEON, // VSETLNi16 = 3509 |
| 20905 | CEFBS_HasVFP2, // VSETLNi32 = 3510 |
| 20906 | CEFBS_HasNEON, // VSETLNi8 = 3511 |
| 20907 | CEFBS_HasNEON, // VSHLLi16 = 3512 |
| 20908 | CEFBS_HasNEON, // VSHLLi32 = 3513 |
| 20909 | CEFBS_HasNEON, // VSHLLi8 = 3514 |
| 20910 | CEFBS_HasNEON, // VSHLLsv2i64 = 3515 |
| 20911 | CEFBS_HasNEON, // VSHLLsv4i32 = 3516 |
| 20912 | CEFBS_HasNEON, // VSHLLsv8i16 = 3517 |
| 20913 | CEFBS_HasNEON, // VSHLLuv2i64 = 3518 |
| 20914 | CEFBS_HasNEON, // VSHLLuv4i32 = 3519 |
| 20915 | CEFBS_HasNEON, // VSHLLuv8i16 = 3520 |
| 20916 | CEFBS_HasNEON, // VSHLiv16i8 = 3521 |
| 20917 | CEFBS_HasNEON, // VSHLiv1i64 = 3522 |
| 20918 | CEFBS_HasNEON, // VSHLiv2i32 = 3523 |
| 20919 | CEFBS_HasNEON, // VSHLiv2i64 = 3524 |
| 20920 | CEFBS_HasNEON, // VSHLiv4i16 = 3525 |
| 20921 | CEFBS_HasNEON, // VSHLiv4i32 = 3526 |
| 20922 | CEFBS_HasNEON, // VSHLiv8i16 = 3527 |
| 20923 | CEFBS_HasNEON, // VSHLiv8i8 = 3528 |
| 20924 | CEFBS_HasNEON, // VSHLsv16i8 = 3529 |
| 20925 | CEFBS_HasNEON, // VSHLsv1i64 = 3530 |
| 20926 | CEFBS_HasNEON, // VSHLsv2i32 = 3531 |
| 20927 | CEFBS_HasNEON, // VSHLsv2i64 = 3532 |
| 20928 | CEFBS_HasNEON, // VSHLsv4i16 = 3533 |
| 20929 | CEFBS_HasNEON, // VSHLsv4i32 = 3534 |
| 20930 | CEFBS_HasNEON, // VSHLsv8i16 = 3535 |
| 20931 | CEFBS_HasNEON, // VSHLsv8i8 = 3536 |
| 20932 | CEFBS_HasNEON, // VSHLuv16i8 = 3537 |
| 20933 | CEFBS_HasNEON, // VSHLuv1i64 = 3538 |
| 20934 | CEFBS_HasNEON, // VSHLuv2i32 = 3539 |
| 20935 | CEFBS_HasNEON, // VSHLuv2i64 = 3540 |
| 20936 | CEFBS_HasNEON, // VSHLuv4i16 = 3541 |
| 20937 | CEFBS_HasNEON, // VSHLuv4i32 = 3542 |
| 20938 | CEFBS_HasNEON, // VSHLuv8i16 = 3543 |
| 20939 | CEFBS_HasNEON, // VSHLuv8i8 = 3544 |
| 20940 | CEFBS_HasNEON, // VSHRNv2i32 = 3545 |
| 20941 | CEFBS_HasNEON, // VSHRNv4i16 = 3546 |
| 20942 | CEFBS_HasNEON, // VSHRNv8i8 = 3547 |
| 20943 | CEFBS_HasNEON, // VSHRsv16i8 = 3548 |
| 20944 | CEFBS_HasNEON, // VSHRsv1i64 = 3549 |
| 20945 | CEFBS_HasNEON, // VSHRsv2i32 = 3550 |
| 20946 | CEFBS_HasNEON, // VSHRsv2i64 = 3551 |
| 20947 | CEFBS_HasNEON, // VSHRsv4i16 = 3552 |
| 20948 | CEFBS_HasNEON, // VSHRsv4i32 = 3553 |
| 20949 | CEFBS_HasNEON, // VSHRsv8i16 = 3554 |
| 20950 | CEFBS_HasNEON, // VSHRsv8i8 = 3555 |
| 20951 | CEFBS_HasNEON, // VSHRuv16i8 = 3556 |
| 20952 | CEFBS_HasNEON, // VSHRuv1i64 = 3557 |
| 20953 | CEFBS_HasNEON, // VSHRuv2i32 = 3558 |
| 20954 | CEFBS_HasNEON, // VSHRuv2i64 = 3559 |
| 20955 | CEFBS_HasNEON, // VSHRuv4i16 = 3560 |
| 20956 | CEFBS_HasNEON, // VSHRuv4i32 = 3561 |
| 20957 | CEFBS_HasNEON, // VSHRuv8i16 = 3562 |
| 20958 | CEFBS_HasNEON, // VSHRuv8i8 = 3563 |
| 20959 | CEFBS_HasVFP2_HasDPVFP, // VSHTOD = 3564 |
| 20960 | CEFBS_HasFullFP16, // VSHTOH = 3565 |
| 20961 | CEFBS_HasVFP2, // VSHTOS = 3566 |
| 20962 | CEFBS_HasVFP2_HasDPVFP, // VSITOD = 3567 |
| 20963 | CEFBS_HasFullFP16, // VSITOH = 3568 |
| 20964 | CEFBS_HasVFP2, // VSITOS = 3569 |
| 20965 | CEFBS_HasNEON, // VSLIv16i8 = 3570 |
| 20966 | CEFBS_HasNEON, // VSLIv1i64 = 3571 |
| 20967 | CEFBS_HasNEON, // VSLIv2i32 = 3572 |
| 20968 | CEFBS_HasNEON, // VSLIv2i64 = 3573 |
| 20969 | CEFBS_HasNEON, // VSLIv4i16 = 3574 |
| 20970 | CEFBS_HasNEON, // VSLIv4i32 = 3575 |
| 20971 | CEFBS_HasNEON, // VSLIv8i16 = 3576 |
| 20972 | CEFBS_HasNEON, // VSLIv8i8 = 3577 |
| 20973 | CEFBS_HasVFP2_HasDPVFP, // VSLTOD = 3578 |
| 20974 | CEFBS_HasFullFP16, // VSLTOH = 3579 |
| 20975 | CEFBS_HasVFP2, // VSLTOS = 3580 |
| 20976 | CEFBS_HasMatMulInt8, // VSMMLA = 3581 |
| 20977 | CEFBS_HasVFP2_HasDPVFP, // VSQRTD = 3582 |
| 20978 | CEFBS_HasFullFP16, // VSQRTH = 3583 |
| 20979 | CEFBS_HasVFP2, // VSQRTS = 3584 |
| 20980 | CEFBS_HasNEON, // VSRAsv16i8 = 3585 |
| 20981 | CEFBS_HasNEON, // VSRAsv1i64 = 3586 |
| 20982 | CEFBS_HasNEON, // VSRAsv2i32 = 3587 |
| 20983 | CEFBS_HasNEON, // VSRAsv2i64 = 3588 |
| 20984 | CEFBS_HasNEON, // VSRAsv4i16 = 3589 |
| 20985 | CEFBS_HasNEON, // VSRAsv4i32 = 3590 |
| 20986 | CEFBS_HasNEON, // VSRAsv8i16 = 3591 |
| 20987 | CEFBS_HasNEON, // VSRAsv8i8 = 3592 |
| 20988 | CEFBS_HasNEON, // VSRAuv16i8 = 3593 |
| 20989 | CEFBS_HasNEON, // VSRAuv1i64 = 3594 |
| 20990 | CEFBS_HasNEON, // VSRAuv2i32 = 3595 |
| 20991 | CEFBS_HasNEON, // VSRAuv2i64 = 3596 |
| 20992 | CEFBS_HasNEON, // VSRAuv4i16 = 3597 |
| 20993 | CEFBS_HasNEON, // VSRAuv4i32 = 3598 |
| 20994 | CEFBS_HasNEON, // VSRAuv8i16 = 3599 |
| 20995 | CEFBS_HasNEON, // VSRAuv8i8 = 3600 |
| 20996 | CEFBS_HasNEON, // VSRIv16i8 = 3601 |
| 20997 | CEFBS_HasNEON, // VSRIv1i64 = 3602 |
| 20998 | CEFBS_HasNEON, // VSRIv2i32 = 3603 |
| 20999 | CEFBS_HasNEON, // VSRIv2i64 = 3604 |
| 21000 | CEFBS_HasNEON, // VSRIv4i16 = 3605 |
| 21001 | CEFBS_HasNEON, // VSRIv4i32 = 3606 |
| 21002 | CEFBS_HasNEON, // VSRIv8i16 = 3607 |
| 21003 | CEFBS_HasNEON, // VSRIv8i8 = 3608 |
| 21004 | CEFBS_HasNEON, // VST1LNd16 = 3609 |
| 21005 | CEFBS_HasNEON, // VST1LNd16_UPD = 3610 |
| 21006 | CEFBS_HasNEON, // VST1LNd32 = 3611 |
| 21007 | CEFBS_HasNEON, // VST1LNd32_UPD = 3612 |
| 21008 | CEFBS_HasNEON, // VST1LNd8 = 3613 |
| 21009 | CEFBS_HasNEON, // VST1LNd8_UPD = 3614 |
| 21010 | CEFBS_HasNEON, // VST1LNq16Pseudo = 3615 |
| 21011 | CEFBS_HasNEON, // VST1LNq16Pseudo_UPD = 3616 |
| 21012 | CEFBS_HasNEON, // VST1LNq32Pseudo = 3617 |
| 21013 | CEFBS_HasNEON, // VST1LNq32Pseudo_UPD = 3618 |
| 21014 | CEFBS_HasNEON, // VST1LNq8Pseudo = 3619 |
| 21015 | CEFBS_HasNEON, // VST1LNq8Pseudo_UPD = 3620 |
| 21016 | CEFBS_HasNEON, // VST1d16 = 3621 |
| 21017 | CEFBS_HasNEON, // VST1d16Q = 3622 |
| 21018 | CEFBS_HasNEON, // VST1d16QPseudo = 3623 |
| 21019 | CEFBS_HasNEON, // VST1d16QPseudoWB_fixed = 3624 |
| 21020 | CEFBS_HasNEON, // VST1d16QPseudoWB_register = 3625 |
| 21021 | CEFBS_HasNEON, // VST1d16Qwb_fixed = 3626 |
| 21022 | CEFBS_HasNEON, // VST1d16Qwb_register = 3627 |
| 21023 | CEFBS_HasNEON, // VST1d16T = 3628 |
| 21024 | CEFBS_HasNEON, // VST1d16TPseudo = 3629 |
| 21025 | CEFBS_HasNEON, // VST1d16TPseudoWB_fixed = 3630 |
| 21026 | CEFBS_HasNEON, // VST1d16TPseudoWB_register = 3631 |
| 21027 | CEFBS_HasNEON, // VST1d16Twb_fixed = 3632 |
| 21028 | CEFBS_HasNEON, // VST1d16Twb_register = 3633 |
| 21029 | CEFBS_HasNEON, // VST1d16wb_fixed = 3634 |
| 21030 | CEFBS_HasNEON, // VST1d16wb_register = 3635 |
| 21031 | CEFBS_HasNEON, // VST1d32 = 3636 |
| 21032 | CEFBS_HasNEON, // VST1d32Q = 3637 |
| 21033 | CEFBS_HasNEON, // VST1d32QPseudo = 3638 |
| 21034 | CEFBS_HasNEON, // VST1d32QPseudoWB_fixed = 3639 |
| 21035 | CEFBS_HasNEON, // VST1d32QPseudoWB_register = 3640 |
| 21036 | CEFBS_HasNEON, // VST1d32Qwb_fixed = 3641 |
| 21037 | CEFBS_HasNEON, // VST1d32Qwb_register = 3642 |
| 21038 | CEFBS_HasNEON, // VST1d32T = 3643 |
| 21039 | CEFBS_HasNEON, // VST1d32TPseudo = 3644 |
| 21040 | CEFBS_HasNEON, // VST1d32TPseudoWB_fixed = 3645 |
| 21041 | CEFBS_HasNEON, // VST1d32TPseudoWB_register = 3646 |
| 21042 | CEFBS_HasNEON, // VST1d32Twb_fixed = 3647 |
| 21043 | CEFBS_HasNEON, // VST1d32Twb_register = 3648 |
| 21044 | CEFBS_HasNEON, // VST1d32wb_fixed = 3649 |
| 21045 | CEFBS_HasNEON, // VST1d32wb_register = 3650 |
| 21046 | CEFBS_HasNEON, // VST1d64 = 3651 |
| 21047 | CEFBS_HasNEON, // VST1d64Q = 3652 |
| 21048 | CEFBS_HasNEON, // VST1d64QPseudo = 3653 |
| 21049 | CEFBS_HasNEON, // VST1d64QPseudoWB_fixed = 3654 |
| 21050 | CEFBS_HasNEON, // VST1d64QPseudoWB_register = 3655 |
| 21051 | CEFBS_HasNEON, // VST1d64Qwb_fixed = 3656 |
| 21052 | CEFBS_HasNEON, // VST1d64Qwb_register = 3657 |
| 21053 | CEFBS_HasNEON, // VST1d64T = 3658 |
| 21054 | CEFBS_HasNEON, // VST1d64TPseudo = 3659 |
| 21055 | CEFBS_HasNEON, // VST1d64TPseudoWB_fixed = 3660 |
| 21056 | CEFBS_HasNEON, // VST1d64TPseudoWB_register = 3661 |
| 21057 | CEFBS_HasNEON, // VST1d64Twb_fixed = 3662 |
| 21058 | CEFBS_HasNEON, // VST1d64Twb_register = 3663 |
| 21059 | CEFBS_HasNEON, // VST1d64wb_fixed = 3664 |
| 21060 | CEFBS_HasNEON, // VST1d64wb_register = 3665 |
| 21061 | CEFBS_HasNEON, // VST1d8 = 3666 |
| 21062 | CEFBS_HasNEON, // VST1d8Q = 3667 |
| 21063 | CEFBS_HasNEON, // VST1d8QPseudo = 3668 |
| 21064 | CEFBS_HasNEON, // VST1d8QPseudoWB_fixed = 3669 |
| 21065 | CEFBS_HasNEON, // VST1d8QPseudoWB_register = 3670 |
| 21066 | CEFBS_HasNEON, // VST1d8Qwb_fixed = 3671 |
| 21067 | CEFBS_HasNEON, // VST1d8Qwb_register = 3672 |
| 21068 | CEFBS_HasNEON, // VST1d8T = 3673 |
| 21069 | CEFBS_HasNEON, // VST1d8TPseudo = 3674 |
| 21070 | CEFBS_HasNEON, // VST1d8TPseudoWB_fixed = 3675 |
| 21071 | CEFBS_HasNEON, // VST1d8TPseudoWB_register = 3676 |
| 21072 | CEFBS_HasNEON, // VST1d8Twb_fixed = 3677 |
| 21073 | CEFBS_HasNEON, // VST1d8Twb_register = 3678 |
| 21074 | CEFBS_HasNEON, // VST1d8wb_fixed = 3679 |
| 21075 | CEFBS_HasNEON, // VST1d8wb_register = 3680 |
| 21076 | CEFBS_HasNEON, // VST1q16 = 3681 |
| 21077 | CEFBS_HasNEON, // VST1q16HighQPseudo = 3682 |
| 21078 | CEFBS_HasNEON, // VST1q16HighQPseudo_UPD = 3683 |
| 21079 | CEFBS_HasNEON, // VST1q16HighTPseudo = 3684 |
| 21080 | CEFBS_HasNEON, // VST1q16HighTPseudo_UPD = 3685 |
| 21081 | CEFBS_HasNEON, // VST1q16LowQPseudo_UPD = 3686 |
| 21082 | CEFBS_HasNEON, // VST1q16LowTPseudo_UPD = 3687 |
| 21083 | CEFBS_HasNEON, // VST1q16wb_fixed = 3688 |
| 21084 | CEFBS_HasNEON, // VST1q16wb_register = 3689 |
| 21085 | CEFBS_HasNEON, // VST1q32 = 3690 |
| 21086 | CEFBS_HasNEON, // VST1q32HighQPseudo = 3691 |
| 21087 | CEFBS_HasNEON, // VST1q32HighQPseudo_UPD = 3692 |
| 21088 | CEFBS_HasNEON, // VST1q32HighTPseudo = 3693 |
| 21089 | CEFBS_HasNEON, // VST1q32HighTPseudo_UPD = 3694 |
| 21090 | CEFBS_HasNEON, // VST1q32LowQPseudo_UPD = 3695 |
| 21091 | CEFBS_HasNEON, // VST1q32LowTPseudo_UPD = 3696 |
| 21092 | CEFBS_HasNEON, // VST1q32wb_fixed = 3697 |
| 21093 | CEFBS_HasNEON, // VST1q32wb_register = 3698 |
| 21094 | CEFBS_HasNEON, // VST1q64 = 3699 |
| 21095 | CEFBS_HasNEON, // VST1q64HighQPseudo = 3700 |
| 21096 | CEFBS_HasNEON, // VST1q64HighQPseudo_UPD = 3701 |
| 21097 | CEFBS_HasNEON, // VST1q64HighTPseudo = 3702 |
| 21098 | CEFBS_HasNEON, // VST1q64HighTPseudo_UPD = 3703 |
| 21099 | CEFBS_HasNEON, // VST1q64LowQPseudo_UPD = 3704 |
| 21100 | CEFBS_HasNEON, // VST1q64LowTPseudo_UPD = 3705 |
| 21101 | CEFBS_HasNEON, // VST1q64wb_fixed = 3706 |
| 21102 | CEFBS_HasNEON, // VST1q64wb_register = 3707 |
| 21103 | CEFBS_HasNEON, // VST1q8 = 3708 |
| 21104 | CEFBS_HasNEON, // VST1q8HighQPseudo = 3709 |
| 21105 | CEFBS_HasNEON, // VST1q8HighQPseudo_UPD = 3710 |
| 21106 | CEFBS_HasNEON, // VST1q8HighTPseudo = 3711 |
| 21107 | CEFBS_HasNEON, // VST1q8HighTPseudo_UPD = 3712 |
| 21108 | CEFBS_HasNEON, // VST1q8LowQPseudo_UPD = 3713 |
| 21109 | CEFBS_HasNEON, // VST1q8LowTPseudo_UPD = 3714 |
| 21110 | CEFBS_HasNEON, // VST1q8wb_fixed = 3715 |
| 21111 | CEFBS_HasNEON, // VST1q8wb_register = 3716 |
| 21112 | CEFBS_HasNEON, // VST2LNd16 = 3717 |
| 21113 | CEFBS_HasNEON, // VST2LNd16Pseudo = 3718 |
| 21114 | CEFBS_HasNEON, // VST2LNd16Pseudo_UPD = 3719 |
| 21115 | CEFBS_HasNEON, // VST2LNd16_UPD = 3720 |
| 21116 | CEFBS_HasNEON, // VST2LNd32 = 3721 |
| 21117 | CEFBS_HasNEON, // VST2LNd32Pseudo = 3722 |
| 21118 | CEFBS_HasNEON, // VST2LNd32Pseudo_UPD = 3723 |
| 21119 | CEFBS_HasNEON, // VST2LNd32_UPD = 3724 |
| 21120 | CEFBS_HasNEON, // VST2LNd8 = 3725 |
| 21121 | CEFBS_HasNEON, // VST2LNd8Pseudo = 3726 |
| 21122 | CEFBS_HasNEON, // VST2LNd8Pseudo_UPD = 3727 |
| 21123 | CEFBS_HasNEON, // VST2LNd8_UPD = 3728 |
| 21124 | CEFBS_HasNEON, // VST2LNq16 = 3729 |
| 21125 | CEFBS_HasNEON, // VST2LNq16Pseudo = 3730 |
| 21126 | CEFBS_HasNEON, // VST2LNq16Pseudo_UPD = 3731 |
| 21127 | CEFBS_HasNEON, // VST2LNq16_UPD = 3732 |
| 21128 | CEFBS_HasNEON, // VST2LNq32 = 3733 |
| 21129 | CEFBS_HasNEON, // VST2LNq32Pseudo = 3734 |
| 21130 | CEFBS_HasNEON, // VST2LNq32Pseudo_UPD = 3735 |
| 21131 | CEFBS_HasNEON, // VST2LNq32_UPD = 3736 |
| 21132 | CEFBS_HasNEON, // VST2b16 = 3737 |
| 21133 | CEFBS_HasNEON, // VST2b16wb_fixed = 3738 |
| 21134 | CEFBS_HasNEON, // VST2b16wb_register = 3739 |
| 21135 | CEFBS_HasNEON, // VST2b32 = 3740 |
| 21136 | CEFBS_HasNEON, // VST2b32wb_fixed = 3741 |
| 21137 | CEFBS_HasNEON, // VST2b32wb_register = 3742 |
| 21138 | CEFBS_HasNEON, // VST2b8 = 3743 |
| 21139 | CEFBS_HasNEON, // VST2b8wb_fixed = 3744 |
| 21140 | CEFBS_HasNEON, // VST2b8wb_register = 3745 |
| 21141 | CEFBS_HasNEON, // VST2d16 = 3746 |
| 21142 | CEFBS_HasNEON, // VST2d16wb_fixed = 3747 |
| 21143 | CEFBS_HasNEON, // VST2d16wb_register = 3748 |
| 21144 | CEFBS_HasNEON, // VST2d32 = 3749 |
| 21145 | CEFBS_HasNEON, // VST2d32wb_fixed = 3750 |
| 21146 | CEFBS_HasNEON, // VST2d32wb_register = 3751 |
| 21147 | CEFBS_HasNEON, // VST2d8 = 3752 |
| 21148 | CEFBS_HasNEON, // VST2d8wb_fixed = 3753 |
| 21149 | CEFBS_HasNEON, // VST2d8wb_register = 3754 |
| 21150 | CEFBS_HasNEON, // VST2q16 = 3755 |
| 21151 | CEFBS_HasNEON, // VST2q16Pseudo = 3756 |
| 21152 | CEFBS_HasNEON, // VST2q16PseudoWB_fixed = 3757 |
| 21153 | CEFBS_HasNEON, // VST2q16PseudoWB_register = 3758 |
| 21154 | CEFBS_HasNEON, // VST2q16wb_fixed = 3759 |
| 21155 | CEFBS_HasNEON, // VST2q16wb_register = 3760 |
| 21156 | CEFBS_HasNEON, // VST2q32 = 3761 |
| 21157 | CEFBS_HasNEON, // VST2q32Pseudo = 3762 |
| 21158 | CEFBS_HasNEON, // VST2q32PseudoWB_fixed = 3763 |
| 21159 | CEFBS_HasNEON, // VST2q32PseudoWB_register = 3764 |
| 21160 | CEFBS_HasNEON, // VST2q32wb_fixed = 3765 |
| 21161 | CEFBS_HasNEON, // VST2q32wb_register = 3766 |
| 21162 | CEFBS_HasNEON, // VST2q8 = 3767 |
| 21163 | CEFBS_HasNEON, // VST2q8Pseudo = 3768 |
| 21164 | CEFBS_HasNEON, // VST2q8PseudoWB_fixed = 3769 |
| 21165 | CEFBS_HasNEON, // VST2q8PseudoWB_register = 3770 |
| 21166 | CEFBS_HasNEON, // VST2q8wb_fixed = 3771 |
| 21167 | CEFBS_HasNEON, // VST2q8wb_register = 3772 |
| 21168 | CEFBS_HasNEON, // VST3LNd16 = 3773 |
| 21169 | CEFBS_HasNEON, // VST3LNd16Pseudo = 3774 |
| 21170 | CEFBS_HasNEON, // VST3LNd16Pseudo_UPD = 3775 |
| 21171 | CEFBS_HasNEON, // VST3LNd16_UPD = 3776 |
| 21172 | CEFBS_HasNEON, // VST3LNd32 = 3777 |
| 21173 | CEFBS_HasNEON, // VST3LNd32Pseudo = 3778 |
| 21174 | CEFBS_HasNEON, // VST3LNd32Pseudo_UPD = 3779 |
| 21175 | CEFBS_HasNEON, // VST3LNd32_UPD = 3780 |
| 21176 | CEFBS_HasNEON, // VST3LNd8 = 3781 |
| 21177 | CEFBS_HasNEON, // VST3LNd8Pseudo = 3782 |
| 21178 | CEFBS_HasNEON, // VST3LNd8Pseudo_UPD = 3783 |
| 21179 | CEFBS_HasNEON, // VST3LNd8_UPD = 3784 |
| 21180 | CEFBS_HasNEON, // VST3LNq16 = 3785 |
| 21181 | CEFBS_HasNEON, // VST3LNq16Pseudo = 3786 |
| 21182 | CEFBS_HasNEON, // VST3LNq16Pseudo_UPD = 3787 |
| 21183 | CEFBS_HasNEON, // VST3LNq16_UPD = 3788 |
| 21184 | CEFBS_HasNEON, // VST3LNq32 = 3789 |
| 21185 | CEFBS_HasNEON, // VST3LNq32Pseudo = 3790 |
| 21186 | CEFBS_HasNEON, // VST3LNq32Pseudo_UPD = 3791 |
| 21187 | CEFBS_HasNEON, // VST3LNq32_UPD = 3792 |
| 21188 | CEFBS_HasNEON, // VST3d16 = 3793 |
| 21189 | CEFBS_HasNEON, // VST3d16Pseudo = 3794 |
| 21190 | CEFBS_HasNEON, // VST3d16Pseudo_UPD = 3795 |
| 21191 | CEFBS_HasNEON, // VST3d16_UPD = 3796 |
| 21192 | CEFBS_HasNEON, // VST3d32 = 3797 |
| 21193 | CEFBS_HasNEON, // VST3d32Pseudo = 3798 |
| 21194 | CEFBS_HasNEON, // VST3d32Pseudo_UPD = 3799 |
| 21195 | CEFBS_HasNEON, // VST3d32_UPD = 3800 |
| 21196 | CEFBS_HasNEON, // VST3d8 = 3801 |
| 21197 | CEFBS_HasNEON, // VST3d8Pseudo = 3802 |
| 21198 | CEFBS_HasNEON, // VST3d8Pseudo_UPD = 3803 |
| 21199 | CEFBS_HasNEON, // VST3d8_UPD = 3804 |
| 21200 | CEFBS_HasNEON, // VST3q16 = 3805 |
| 21201 | CEFBS_HasNEON, // VST3q16Pseudo_UPD = 3806 |
| 21202 | CEFBS_HasNEON, // VST3q16_UPD = 3807 |
| 21203 | CEFBS_HasNEON, // VST3q16oddPseudo = 3808 |
| 21204 | CEFBS_HasNEON, // VST3q16oddPseudo_UPD = 3809 |
| 21205 | CEFBS_HasNEON, // VST3q32 = 3810 |
| 21206 | CEFBS_HasNEON, // VST3q32Pseudo_UPD = 3811 |
| 21207 | CEFBS_HasNEON, // VST3q32_UPD = 3812 |
| 21208 | CEFBS_HasNEON, // VST3q32oddPseudo = 3813 |
| 21209 | CEFBS_HasNEON, // VST3q32oddPseudo_UPD = 3814 |
| 21210 | CEFBS_HasNEON, // VST3q8 = 3815 |
| 21211 | CEFBS_HasNEON, // VST3q8Pseudo_UPD = 3816 |
| 21212 | CEFBS_HasNEON, // VST3q8_UPD = 3817 |
| 21213 | CEFBS_HasNEON, // VST3q8oddPseudo = 3818 |
| 21214 | CEFBS_HasNEON, // VST3q8oddPseudo_UPD = 3819 |
| 21215 | CEFBS_HasNEON, // VST4LNd16 = 3820 |
| 21216 | CEFBS_HasNEON, // VST4LNd16Pseudo = 3821 |
| 21217 | CEFBS_HasNEON, // VST4LNd16Pseudo_UPD = 3822 |
| 21218 | CEFBS_HasNEON, // VST4LNd16_UPD = 3823 |
| 21219 | CEFBS_HasNEON, // VST4LNd32 = 3824 |
| 21220 | CEFBS_HasNEON, // VST4LNd32Pseudo = 3825 |
| 21221 | CEFBS_HasNEON, // VST4LNd32Pseudo_UPD = 3826 |
| 21222 | CEFBS_HasNEON, // VST4LNd32_UPD = 3827 |
| 21223 | CEFBS_HasNEON, // VST4LNd8 = 3828 |
| 21224 | CEFBS_HasNEON, // VST4LNd8Pseudo = 3829 |
| 21225 | CEFBS_HasNEON, // VST4LNd8Pseudo_UPD = 3830 |
| 21226 | CEFBS_HasNEON, // VST4LNd8_UPD = 3831 |
| 21227 | CEFBS_HasNEON, // VST4LNq16 = 3832 |
| 21228 | CEFBS_HasNEON, // VST4LNq16Pseudo = 3833 |
| 21229 | CEFBS_HasNEON, // VST4LNq16Pseudo_UPD = 3834 |
| 21230 | CEFBS_HasNEON, // VST4LNq16_UPD = 3835 |
| 21231 | CEFBS_HasNEON, // VST4LNq32 = 3836 |
| 21232 | CEFBS_HasNEON, // VST4LNq32Pseudo = 3837 |
| 21233 | CEFBS_HasNEON, // VST4LNq32Pseudo_UPD = 3838 |
| 21234 | CEFBS_HasNEON, // VST4LNq32_UPD = 3839 |
| 21235 | CEFBS_HasNEON, // VST4d16 = 3840 |
| 21236 | CEFBS_HasNEON, // VST4d16Pseudo = 3841 |
| 21237 | CEFBS_HasNEON, // VST4d16Pseudo_UPD = 3842 |
| 21238 | CEFBS_HasNEON, // VST4d16_UPD = 3843 |
| 21239 | CEFBS_HasNEON, // VST4d32 = 3844 |
| 21240 | CEFBS_HasNEON, // VST4d32Pseudo = 3845 |
| 21241 | CEFBS_HasNEON, // VST4d32Pseudo_UPD = 3846 |
| 21242 | CEFBS_HasNEON, // VST4d32_UPD = 3847 |
| 21243 | CEFBS_HasNEON, // VST4d8 = 3848 |
| 21244 | CEFBS_HasNEON, // VST4d8Pseudo = 3849 |
| 21245 | CEFBS_HasNEON, // VST4d8Pseudo_UPD = 3850 |
| 21246 | CEFBS_HasNEON, // VST4d8_UPD = 3851 |
| 21247 | CEFBS_HasNEON, // VST4q16 = 3852 |
| 21248 | CEFBS_HasNEON, // VST4q16Pseudo_UPD = 3853 |
| 21249 | CEFBS_HasNEON, // VST4q16_UPD = 3854 |
| 21250 | CEFBS_HasNEON, // VST4q16oddPseudo = 3855 |
| 21251 | CEFBS_HasNEON, // VST4q16oddPseudo_UPD = 3856 |
| 21252 | CEFBS_HasNEON, // VST4q32 = 3857 |
| 21253 | CEFBS_HasNEON, // VST4q32Pseudo_UPD = 3858 |
| 21254 | CEFBS_HasNEON, // VST4q32_UPD = 3859 |
| 21255 | CEFBS_HasNEON, // VST4q32oddPseudo = 3860 |
| 21256 | CEFBS_HasNEON, // VST4q32oddPseudo_UPD = 3861 |
| 21257 | CEFBS_HasNEON, // VST4q8 = 3862 |
| 21258 | CEFBS_HasNEON, // VST4q8Pseudo_UPD = 3863 |
| 21259 | CEFBS_HasNEON, // VST4q8_UPD = 3864 |
| 21260 | CEFBS_HasNEON, // VST4q8oddPseudo = 3865 |
| 21261 | CEFBS_HasNEON, // VST4q8oddPseudo_UPD = 3866 |
| 21262 | CEFBS_HasFPRegs, // VSTMDDB_UPD = 3867 |
| 21263 | CEFBS_HasFPRegs, // VSTMDIA = 3868 |
| 21264 | CEFBS_HasFPRegs, // VSTMDIA_UPD = 3869 |
| 21265 | CEFBS_HasVFP2, // VSTMQIA = 3870 |
| 21266 | CEFBS_HasFPRegs, // VSTMSDB_UPD = 3871 |
| 21267 | CEFBS_HasFPRegs, // VSTMSIA = 3872 |
| 21268 | CEFBS_HasFPRegs, // VSTMSIA_UPD = 3873 |
| 21269 | CEFBS_HasFPRegs, // VSTRD = 3874 |
| 21270 | CEFBS_HasFPRegs16, // VSTRH = 3875 |
| 21271 | CEFBS_HasFPRegs, // VSTRS = 3876 |
| 21272 | CEFBS_HasV8_1MMainline_Has8MSecExt, // VSTR_FPCXTNS_off = 3877 |
| 21273 | CEFBS_HasV8_1MMainline_Has8MSecExt, // VSTR_FPCXTNS_post = 3878 |
| 21274 | CEFBS_HasV8_1MMainline_Has8MSecExt, // VSTR_FPCXTNS_pre = 3879 |
| 21275 | CEFBS_HasV8_1MMainline_Has8MSecExt, // VSTR_FPCXTS_off = 3880 |
| 21276 | CEFBS_HasV8_1MMainline_Has8MSecExt, // VSTR_FPCXTS_post = 3881 |
| 21277 | CEFBS_HasV8_1MMainline_Has8MSecExt, // VSTR_FPCXTS_pre = 3882 |
| 21278 | CEFBS_HasFPRegs_HasV8_1MMainline, // VSTR_FPSCR_NZCVQC_off = 3883 |
| 21279 | CEFBS_HasFPRegs_HasV8_1MMainline, // VSTR_FPSCR_NZCVQC_post = 3884 |
| 21280 | CEFBS_HasFPRegs_HasV8_1MMainline, // VSTR_FPSCR_NZCVQC_pre = 3885 |
| 21281 | CEFBS_HasFPRegs_HasV8_1MMainline, // VSTR_FPSCR_off = 3886 |
| 21282 | CEFBS_HasFPRegs_HasV8_1MMainline, // VSTR_FPSCR_post = 3887 |
| 21283 | CEFBS_HasFPRegs_HasV8_1MMainline, // VSTR_FPSCR_pre = 3888 |
| 21284 | CEFBS_HasV8_1MMainline_HasMVEInt, // VSTR_P0_off = 3889 |
| 21285 | CEFBS_HasV8_1MMainline_HasMVEInt, // VSTR_P0_post = 3890 |
| 21286 | CEFBS_HasV8_1MMainline_HasMVEInt, // VSTR_P0_pre = 3891 |
| 21287 | CEFBS_HasV8_1MMainline_HasMVEInt, // VSTR_VPR_off = 3892 |
| 21288 | CEFBS_HasV8_1MMainline_HasMVEInt, // VSTR_VPR_post = 3893 |
| 21289 | CEFBS_HasV8_1MMainline_HasMVEInt, // VSTR_VPR_pre = 3894 |
| 21290 | CEFBS_HasVFP2_HasDPVFP, // VSUBD = 3895 |
| 21291 | CEFBS_HasFullFP16, // VSUBH = 3896 |
| 21292 | CEFBS_HasNEON, // VSUBHNv2i32 = 3897 |
| 21293 | CEFBS_HasNEON, // VSUBHNv4i16 = 3898 |
| 21294 | CEFBS_HasNEON, // VSUBHNv8i8 = 3899 |
| 21295 | CEFBS_HasNEON, // VSUBLsv2i64 = 3900 |
| 21296 | CEFBS_HasNEON, // VSUBLsv4i32 = 3901 |
| 21297 | CEFBS_HasNEON, // VSUBLsv8i16 = 3902 |
| 21298 | CEFBS_HasNEON, // VSUBLuv2i64 = 3903 |
| 21299 | CEFBS_HasNEON, // VSUBLuv4i32 = 3904 |
| 21300 | CEFBS_HasNEON, // VSUBLuv8i16 = 3905 |
| 21301 | CEFBS_HasVFP2, // VSUBS = 3906 |
| 21302 | CEFBS_HasNEON, // VSUBWsv2i64 = 3907 |
| 21303 | CEFBS_HasNEON, // VSUBWsv4i32 = 3908 |
| 21304 | CEFBS_HasNEON, // VSUBWsv8i16 = 3909 |
| 21305 | CEFBS_HasNEON, // VSUBWuv2i64 = 3910 |
| 21306 | CEFBS_HasNEON, // VSUBWuv4i32 = 3911 |
| 21307 | CEFBS_HasNEON, // VSUBWuv8i16 = 3912 |
| 21308 | CEFBS_HasNEON, // VSUBfd = 3913 |
| 21309 | CEFBS_HasNEON, // VSUBfq = 3914 |
| 21310 | CEFBS_HasNEON_HasFullFP16, // VSUBhd = 3915 |
| 21311 | CEFBS_HasNEON_HasFullFP16, // VSUBhq = 3916 |
| 21312 | CEFBS_HasNEON, // VSUBv16i8 = 3917 |
| 21313 | CEFBS_HasNEON, // VSUBv1i64 = 3918 |
| 21314 | CEFBS_HasNEON, // VSUBv2i32 = 3919 |
| 21315 | CEFBS_HasNEON, // VSUBv2i64 = 3920 |
| 21316 | CEFBS_HasNEON, // VSUBv4i16 = 3921 |
| 21317 | CEFBS_HasNEON, // VSUBv4i32 = 3922 |
| 21318 | CEFBS_HasNEON, // VSUBv8i16 = 3923 |
| 21319 | CEFBS_HasNEON, // VSUBv8i8 = 3924 |
| 21320 | CEFBS_HasMatMulInt8, // VSUDOTDI = 3925 |
| 21321 | CEFBS_HasMatMulInt8, // VSUDOTQI = 3926 |
| 21322 | CEFBS_HasNEON, // VSWPd = 3927 |
| 21323 | CEFBS_HasNEON, // VSWPq = 3928 |
| 21324 | CEFBS_HasNEON, // VTBL1 = 3929 |
| 21325 | CEFBS_HasNEON, // VTBL2 = 3930 |
| 21326 | CEFBS_HasNEON, // VTBL3 = 3931 |
| 21327 | CEFBS_HasNEON, // VTBL3Pseudo = 3932 |
| 21328 | CEFBS_HasNEON, // VTBL4 = 3933 |
| 21329 | CEFBS_HasNEON, // VTBL4Pseudo = 3934 |
| 21330 | CEFBS_HasNEON, // VTBX1 = 3935 |
| 21331 | CEFBS_HasNEON, // VTBX2 = 3936 |
| 21332 | CEFBS_HasNEON, // VTBX3 = 3937 |
| 21333 | CEFBS_HasNEON, // VTBX3Pseudo = 3938 |
| 21334 | CEFBS_HasNEON, // VTBX4 = 3939 |
| 21335 | CEFBS_HasNEON, // VTBX4Pseudo = 3940 |
| 21336 | CEFBS_HasVFP2_HasDPVFP, // VTOSHD = 3941 |
| 21337 | CEFBS_HasFullFP16, // VTOSHH = 3942 |
| 21338 | CEFBS_HasVFP2, // VTOSHS = 3943 |
| 21339 | CEFBS_HasVFP2_HasDPVFP, // VTOSIRD = 3944 |
| 21340 | CEFBS_HasFullFP16, // VTOSIRH = 3945 |
| 21341 | CEFBS_HasVFP2, // VTOSIRS = 3946 |
| 21342 | CEFBS_HasVFP2_HasDPVFP, // VTOSIZD = 3947 |
| 21343 | CEFBS_HasFullFP16, // VTOSIZH = 3948 |
| 21344 | CEFBS_HasVFP2, // VTOSIZS = 3949 |
| 21345 | CEFBS_HasVFP2_HasDPVFP, // VTOSLD = 3950 |
| 21346 | CEFBS_HasFullFP16, // VTOSLH = 3951 |
| 21347 | CEFBS_HasVFP2, // VTOSLS = 3952 |
| 21348 | CEFBS_HasVFP2_HasDPVFP, // VTOUHD = 3953 |
| 21349 | CEFBS_HasFullFP16, // VTOUHH = 3954 |
| 21350 | CEFBS_HasVFP2, // VTOUHS = 3955 |
| 21351 | CEFBS_HasVFP2_HasDPVFP, // VTOUIRD = 3956 |
| 21352 | CEFBS_HasFullFP16, // VTOUIRH = 3957 |
| 21353 | CEFBS_HasVFP2, // VTOUIRS = 3958 |
| 21354 | CEFBS_HasVFP2_HasDPVFP, // VTOUIZD = 3959 |
| 21355 | CEFBS_HasFullFP16, // VTOUIZH = 3960 |
| 21356 | CEFBS_HasVFP2, // VTOUIZS = 3961 |
| 21357 | CEFBS_HasVFP2_HasDPVFP, // VTOULD = 3962 |
| 21358 | CEFBS_HasFullFP16, // VTOULH = 3963 |
| 21359 | CEFBS_HasVFP2, // VTOULS = 3964 |
| 21360 | CEFBS_HasNEON, // VTRNd16 = 3965 |
| 21361 | CEFBS_HasNEON, // VTRNd32 = 3966 |
| 21362 | CEFBS_HasNEON, // VTRNd8 = 3967 |
| 21363 | CEFBS_HasNEON, // VTRNq16 = 3968 |
| 21364 | CEFBS_HasNEON, // VTRNq32 = 3969 |
| 21365 | CEFBS_HasNEON, // VTRNq8 = 3970 |
| 21366 | CEFBS_HasNEON, // VTSTv16i8 = 3971 |
| 21367 | CEFBS_HasNEON, // VTSTv2i32 = 3972 |
| 21368 | CEFBS_HasNEON, // VTSTv4i16 = 3973 |
| 21369 | CEFBS_HasNEON, // VTSTv4i32 = 3974 |
| 21370 | CEFBS_HasNEON, // VTSTv8i16 = 3975 |
| 21371 | CEFBS_HasNEON, // VTSTv8i8 = 3976 |
| 21372 | CEFBS_HasDotProd, // VUDOTD = 3977 |
| 21373 | CEFBS_HasDotProd, // VUDOTDI = 3978 |
| 21374 | CEFBS_HasDotProd, // VUDOTQ = 3979 |
| 21375 | CEFBS_HasDotProd, // VUDOTQI = 3980 |
| 21376 | CEFBS_HasVFP2_HasDPVFP, // VUHTOD = 3981 |
| 21377 | CEFBS_HasFullFP16, // VUHTOH = 3982 |
| 21378 | CEFBS_HasVFP2, // VUHTOS = 3983 |
| 21379 | CEFBS_HasVFP2_HasDPVFP, // VUITOD = 3984 |
| 21380 | CEFBS_HasFullFP16, // VUITOH = 3985 |
| 21381 | CEFBS_HasVFP2, // VUITOS = 3986 |
| 21382 | CEFBS_HasVFP2_HasDPVFP, // VULTOD = 3987 |
| 21383 | CEFBS_HasFullFP16, // VULTOH = 3988 |
| 21384 | CEFBS_HasVFP2, // VULTOS = 3989 |
| 21385 | CEFBS_HasMatMulInt8, // VUMMLA = 3990 |
| 21386 | CEFBS_HasMatMulInt8, // VUSDOTD = 3991 |
| 21387 | CEFBS_HasMatMulInt8, // VUSDOTDI = 3992 |
| 21388 | CEFBS_HasMatMulInt8, // VUSDOTQ = 3993 |
| 21389 | CEFBS_HasMatMulInt8, // VUSDOTQI = 3994 |
| 21390 | CEFBS_HasMatMulInt8, // VUSMMLA = 3995 |
| 21391 | CEFBS_HasNEON, // VUZPd16 = 3996 |
| 21392 | CEFBS_HasNEON, // VUZPd8 = 3997 |
| 21393 | CEFBS_HasNEON, // VUZPq16 = 3998 |
| 21394 | CEFBS_HasNEON, // VUZPq32 = 3999 |
| 21395 | CEFBS_HasNEON, // VUZPq8 = 4000 |
| 21396 | CEFBS_HasNEON, // VZIPd16 = 4001 |
| 21397 | CEFBS_HasNEON, // VZIPd8 = 4002 |
| 21398 | CEFBS_HasNEON, // VZIPq16 = 4003 |
| 21399 | CEFBS_HasNEON, // VZIPq32 = 4004 |
| 21400 | CEFBS_HasNEON, // VZIPq8 = 4005 |
| 21401 | CEFBS_IsARM, // sysLDMDA = 4006 |
| 21402 | CEFBS_IsARM, // sysLDMDA_UPD = 4007 |
| 21403 | CEFBS_IsARM, // sysLDMDB = 4008 |
| 21404 | CEFBS_IsARM, // sysLDMDB_UPD = 4009 |
| 21405 | CEFBS_IsARM, // sysLDMIA = 4010 |
| 21406 | CEFBS_IsARM, // sysLDMIA_UPD = 4011 |
| 21407 | CEFBS_IsARM, // sysLDMIB = 4012 |
| 21408 | CEFBS_IsARM, // sysLDMIB_UPD = 4013 |
| 21409 | CEFBS_IsARM, // sysSTMDA = 4014 |
| 21410 | CEFBS_IsARM, // sysSTMDA_UPD = 4015 |
| 21411 | CEFBS_IsARM, // sysSTMDB = 4016 |
| 21412 | CEFBS_IsARM, // sysSTMDB_UPD = 4017 |
| 21413 | CEFBS_IsARM, // sysSTMIA = 4018 |
| 21414 | CEFBS_IsARM, // sysSTMIA_UPD = 4019 |
| 21415 | CEFBS_IsARM, // sysSTMIB = 4020 |
| 21416 | CEFBS_IsARM, // sysSTMIB_UPD = 4021 |
| 21417 | CEFBS_IsThumb2, // t2ADCri = 4022 |
| 21418 | CEFBS_IsThumb2, // t2ADCrr = 4023 |
| 21419 | CEFBS_IsThumb2, // t2ADCrs = 4024 |
| 21420 | CEFBS_IsThumb2, // t2ADDri = 4025 |
| 21421 | CEFBS_IsThumb2, // t2ADDri12 = 4026 |
| 21422 | CEFBS_IsThumb2, // t2ADDrr = 4027 |
| 21423 | CEFBS_IsThumb2, // t2ADDrs = 4028 |
| 21424 | CEFBS_IsThumb2, // t2ADDspImm = 4029 |
| 21425 | CEFBS_IsThumb2, // t2ADDspImm12 = 4030 |
| 21426 | CEFBS_IsThumb2, // t2ADR = 4031 |
| 21427 | CEFBS_IsThumb2, // t2ANDri = 4032 |
| 21428 | CEFBS_IsThumb2, // t2ANDrr = 4033 |
| 21429 | CEFBS_IsThumb2, // t2ANDrs = 4034 |
| 21430 | CEFBS_IsThumb2, // t2ASRri = 4035 |
| 21431 | CEFBS_IsThumb2, // t2ASRrr = 4036 |
| 21432 | CEFBS_IsThumb2, // t2ASRs1 = 4037 |
| 21433 | CEFBS_HasV7_IsMClass, // t2AUT = 4038 |
| 21434 | CEFBS_IsThumb2_HasV8_1MMainline_HasPACBTI, // t2AUTG = 4039 |
| 21435 | CEFBS_IsThumb_HasV8MBaseline, // t2B = 4040 |
| 21436 | CEFBS_IsThumb2, // t2BFC = 4041 |
| 21437 | CEFBS_IsThumb2, // t2BFI = 4042 |
| 21438 | CEFBS_IsThumb2_HasV8_1MMainline_HasLOB, // t2BFLi = 4043 |
| 21439 | CEFBS_IsThumb2_HasV8_1MMainline_HasLOB, // t2BFLr = 4044 |
| 21440 | CEFBS_IsThumb2_HasV8_1MMainline_HasLOB, // t2BFi = 4045 |
| 21441 | CEFBS_IsThumb2_HasV8_1MMainline_HasLOB, // t2BFic = 4046 |
| 21442 | CEFBS_IsThumb2_HasV8_1MMainline_HasLOB, // t2BFr = 4047 |
| 21443 | CEFBS_IsThumb2, // t2BICri = 4048 |
| 21444 | CEFBS_IsThumb2, // t2BICrr = 4049 |
| 21445 | CEFBS_IsThumb2, // t2BICrs = 4050 |
| 21446 | CEFBS_HasV7_IsMClass, // t2BTI = 4051 |
| 21447 | CEFBS_IsThumb2_HasV8_1MMainline_HasPACBTI, // t2BXAUT = 4052 |
| 21448 | CEFBS_IsThumb2_IsNotMClass, // t2BXJ = 4053 |
| 21449 | CEFBS_IsThumb2, // t2Bcc = 4054 |
| 21450 | CEFBS_IsThumb2_PreV8, // t2CDP = 4055 |
| 21451 | CEFBS_IsThumb2_PreV8, // t2CDP2 = 4056 |
| 21452 | CEFBS_IsThumb_HasV7Clrex, // t2CLREX = 4057 |
| 21453 | CEFBS_HasV8_1MMainline, // t2CLRM = 4058 |
| 21454 | CEFBS_IsThumb2, // t2CLZ = 4059 |
| 21455 | CEFBS_IsThumb2, // t2CMNri = 4060 |
| 21456 | CEFBS_IsThumb2, // t2CMNzrr = 4061 |
| 21457 | CEFBS_IsThumb2, // t2CMNzrs = 4062 |
| 21458 | CEFBS_IsThumb2, // t2CMPri = 4063 |
| 21459 | CEFBS_IsThumb2, // t2CMPrr = 4064 |
| 21460 | CEFBS_IsThumb2, // t2CMPrs = 4065 |
| 21461 | CEFBS_IsThumb2_IsNotMClass, // t2CPS1p = 4066 |
| 21462 | CEFBS_IsThumb2_IsNotMClass, // t2CPS2p = 4067 |
| 21463 | CEFBS_IsThumb2_IsNotMClass, // t2CPS3p = 4068 |
| 21464 | CEFBS_IsThumb2_HasCRC, // t2CRC32B = 4069 |
| 21465 | CEFBS_IsThumb2_HasCRC, // t2CRC32CB = 4070 |
| 21466 | CEFBS_IsThumb2_HasCRC, // t2CRC32CH = 4071 |
| 21467 | CEFBS_IsThumb2_HasCRC, // t2CRC32CW = 4072 |
| 21468 | CEFBS_IsThumb2_HasCRC, // t2CRC32H = 4073 |
| 21469 | CEFBS_IsThumb2_HasCRC, // t2CRC32W = 4074 |
| 21470 | CEFBS_HasV8_1MMainline, // t2CSEL = 4075 |
| 21471 | CEFBS_HasV8_1MMainline, // t2CSINC = 4076 |
| 21472 | CEFBS_HasV8_1MMainline, // t2CSINV = 4077 |
| 21473 | CEFBS_HasV8_1MMainline, // t2CSNEG = 4078 |
| 21474 | CEFBS_IsThumb2, // t2DBG = 4079 |
| 21475 | CEFBS_IsThumb2_HasV8, // t2DCPS1 = 4080 |
| 21476 | CEFBS_IsThumb2_HasV8, // t2DCPS2 = 4081 |
| 21477 | CEFBS_IsThumb2_HasV8, // t2DCPS3 = 4082 |
| 21478 | CEFBS_IsThumb2_HasV8_1MMainline_HasLOB, // t2DLS = 4083 |
| 21479 | CEFBS_IsThumb_HasDB, // t2DMB = 4084 |
| 21480 | CEFBS_IsThumb_HasDB, // t2DSB = 4085 |
| 21481 | CEFBS_IsThumb2, // t2EORri = 4086 |
| 21482 | CEFBS_IsThumb2, // t2EORrr = 4087 |
| 21483 | CEFBS_IsThumb2, // t2EORrs = 4088 |
| 21484 | CEFBS_IsThumb2, // t2HINT = 4089 |
| 21485 | CEFBS_IsThumb2_HasVirtualization, // t2HVC = 4090 |
| 21486 | CEFBS_IsThumb_HasDB, // t2ISB = 4091 |
| 21487 | CEFBS_IsThumb2, // t2IT = 4092 |
| 21488 | CEFBS_IsThumb2_HasVFP2, // t2Int_eh_sjlj_setjmp = 4093 |
| 21489 | CEFBS_IsThumb2, // t2Int_eh_sjlj_setjmp_nofp = 4094 |
| 21490 | CEFBS_IsThumb_HasAcquireRelease, // t2LDA = 4095 |
| 21491 | CEFBS_IsThumb_HasAcquireRelease, // t2LDAB = 4096 |
| 21492 | CEFBS_IsThumb_HasAcquireRelease_HasV7Clrex, // t2LDAEX = 4097 |
| 21493 | CEFBS_IsThumb_HasAcquireRelease_HasV7Clrex, // t2LDAEXB = 4098 |
| 21494 | CEFBS_IsThumb_HasAcquireRelease_HasV7Clrex_IsNotMClass, // t2LDAEXD = 4099 |
| 21495 | CEFBS_IsThumb_HasAcquireRelease_HasV7Clrex, // t2LDAEXH = 4100 |
| 21496 | CEFBS_IsThumb_HasAcquireRelease, // t2LDAH = 4101 |
| 21497 | CEFBS_PreV8_IsThumb2, // t2LDC2L_OFFSET = 4102 |
| 21498 | CEFBS_PreV8_IsThumb2, // t2LDC2L_OPTION = 4103 |
| 21499 | CEFBS_PreV8_IsThumb2, // t2LDC2L_POST = 4104 |
| 21500 | CEFBS_PreV8_IsThumb2, // t2LDC2L_PRE = 4105 |
| 21501 | CEFBS_PreV8_IsThumb2, // t2LDC2_OFFSET = 4106 |
| 21502 | CEFBS_PreV8_IsThumb2, // t2LDC2_OPTION = 4107 |
| 21503 | CEFBS_PreV8_IsThumb2, // t2LDC2_POST = 4108 |
| 21504 | CEFBS_PreV8_IsThumb2, // t2LDC2_PRE = 4109 |
| 21505 | CEFBS_IsThumb2, // t2LDCL_OFFSET = 4110 |
| 21506 | CEFBS_IsThumb2, // t2LDCL_OPTION = 4111 |
| 21507 | CEFBS_IsThumb2, // t2LDCL_POST = 4112 |
| 21508 | CEFBS_IsThumb2, // t2LDCL_PRE = 4113 |
| 21509 | CEFBS_IsThumb2, // t2LDC_OFFSET = 4114 |
| 21510 | CEFBS_IsThumb2, // t2LDC_OPTION = 4115 |
| 21511 | CEFBS_IsThumb2, // t2LDC_POST = 4116 |
| 21512 | CEFBS_IsThumb2, // t2LDC_PRE = 4117 |
| 21513 | CEFBS_IsThumb2, // t2LDMDB = 4118 |
| 21514 | CEFBS_IsThumb2, // t2LDMDB_UPD = 4119 |
| 21515 | CEFBS_IsThumb2, // t2LDMIA = 4120 |
| 21516 | CEFBS_IsThumb2, // t2LDMIA_UPD = 4121 |
| 21517 | CEFBS_IsThumb2, // t2LDRBT = 4122 |
| 21518 | CEFBS_IsThumb2, // t2LDRB_POST = 4123 |
| 21519 | CEFBS_IsThumb2, // t2LDRB_PRE = 4124 |
| 21520 | CEFBS_IsThumb2, // t2LDRBi12 = 4125 |
| 21521 | CEFBS_IsThumb2, // t2LDRBi8 = 4126 |
| 21522 | CEFBS_IsThumb2, // t2LDRBpci = 4127 |
| 21523 | CEFBS_IsThumb2, // t2LDRBs = 4128 |
| 21524 | CEFBS_IsThumb2, // t2LDRD_POST = 4129 |
| 21525 | CEFBS_IsThumb2, // t2LDRD_PRE = 4130 |
| 21526 | CEFBS_IsThumb2, // t2LDRDi8 = 4131 |
| 21527 | CEFBS_IsThumb_HasV8MBaseline, // t2LDREX = 4132 |
| 21528 | CEFBS_IsThumb_HasV8MBaseline, // t2LDREXB = 4133 |
| 21529 | CEFBS_IsThumb2_IsNotMClass, // t2LDREXD = 4134 |
| 21530 | CEFBS_IsThumb_HasV8MBaseline, // t2LDREXH = 4135 |
| 21531 | CEFBS_IsThumb2, // t2LDRHT = 4136 |
| 21532 | CEFBS_IsThumb2, // t2LDRH_POST = 4137 |
| 21533 | CEFBS_IsThumb2, // t2LDRH_PRE = 4138 |
| 21534 | CEFBS_IsThumb2, // t2LDRHi12 = 4139 |
| 21535 | CEFBS_IsThumb2, // t2LDRHi8 = 4140 |
| 21536 | CEFBS_IsThumb2, // t2LDRHpci = 4141 |
| 21537 | CEFBS_IsThumb2, // t2LDRHs = 4142 |
| 21538 | CEFBS_IsThumb2, // t2LDRSBT = 4143 |
| 21539 | CEFBS_IsThumb2, // t2LDRSB_POST = 4144 |
| 21540 | CEFBS_IsThumb2, // t2LDRSB_PRE = 4145 |
| 21541 | CEFBS_IsThumb2, // t2LDRSBi12 = 4146 |
| 21542 | CEFBS_IsThumb2, // t2LDRSBi8 = 4147 |
| 21543 | CEFBS_IsThumb2, // t2LDRSBpci = 4148 |
| 21544 | CEFBS_IsThumb2, // t2LDRSBs = 4149 |
| 21545 | CEFBS_IsThumb2, // t2LDRSHT = 4150 |
| 21546 | CEFBS_IsThumb2, // t2LDRSH_POST = 4151 |
| 21547 | CEFBS_IsThumb2, // t2LDRSH_PRE = 4152 |
| 21548 | CEFBS_IsThumb2, // t2LDRSHi12 = 4153 |
| 21549 | CEFBS_IsThumb2, // t2LDRSHi8 = 4154 |
| 21550 | CEFBS_IsThumb2, // t2LDRSHpci = 4155 |
| 21551 | CEFBS_IsThumb2, // t2LDRSHs = 4156 |
| 21552 | CEFBS_IsThumb2, // t2LDRT = 4157 |
| 21553 | CEFBS_IsThumb2, // t2LDR_POST = 4158 |
| 21554 | CEFBS_IsThumb2, // t2LDR_PRE = 4159 |
| 21555 | CEFBS_IsThumb2, // t2LDRi12 = 4160 |
| 21556 | CEFBS_IsThumb2, // t2LDRi8 = 4161 |
| 21557 | CEFBS_IsThumb2, // t2LDRpci = 4162 |
| 21558 | CEFBS_IsThumb2, // t2LDRs = 4163 |
| 21559 | CEFBS_IsThumb2_HasV8_1MMainline_HasLOB, // t2LE = 4164 |
| 21560 | CEFBS_IsThumb2_HasV8_1MMainline_HasLOB, // t2LEUpdate = 4165 |
| 21561 | CEFBS_IsThumb2, // t2LSLri = 4166 |
| 21562 | CEFBS_IsThumb2, // t2LSLrr = 4167 |
| 21563 | CEFBS_IsThumb2, // t2LSRri = 4168 |
| 21564 | CEFBS_IsThumb2, // t2LSRrr = 4169 |
| 21565 | CEFBS_IsThumb2, // t2LSRs1 = 4170 |
| 21566 | CEFBS_IsThumb2, // t2MCR = 4171 |
| 21567 | CEFBS_IsThumb2_PreV8, // t2MCR2 = 4172 |
| 21568 | CEFBS_IsThumb2, // t2MCRR = 4173 |
| 21569 | CEFBS_IsThumb2_PreV8, // t2MCRR2 = 4174 |
| 21570 | CEFBS_IsThumb2, // t2MLA = 4175 |
| 21571 | CEFBS_IsThumb2, // t2MLS = 4176 |
| 21572 | CEFBS_IsThumb_HasV8MBaseline, // t2MOVTi16 = 4177 |
| 21573 | CEFBS_IsThumb2, // t2MOVi = 4178 |
| 21574 | CEFBS_IsThumb_HasV8MBaseline, // t2MOVi16 = 4179 |
| 21575 | CEFBS_IsThumb2, // t2MOVr = 4180 |
| 21576 | CEFBS_IsThumb2, // t2MRC = 4181 |
| 21577 | CEFBS_IsThumb2_PreV8, // t2MRC2 = 4182 |
| 21578 | CEFBS_IsThumb2, // t2MRRC = 4183 |
| 21579 | CEFBS_IsThumb2_PreV8, // t2MRRC2 = 4184 |
| 21580 | CEFBS_IsThumb2_IsNotMClass, // t2MRS_AR = 4185 |
| 21581 | CEFBS_IsThumb_IsMClass, // t2MRS_M = 4186 |
| 21582 | CEFBS_IsThumb_HasVirtualization, // t2MRSbanked = 4187 |
| 21583 | CEFBS_IsThumb2_IsNotMClass, // t2MRSsys_AR = 4188 |
| 21584 | CEFBS_IsThumb2_IsNotMClass, // t2MSR_AR = 4189 |
| 21585 | CEFBS_IsThumb_IsMClass, // t2MSR_M = 4190 |
| 21586 | CEFBS_IsThumb_HasVirtualization, // t2MSRbanked = 4191 |
| 21587 | CEFBS_IsThumb2, // t2MUL = 4192 |
| 21588 | CEFBS_IsThumb2, // t2MVNi = 4193 |
| 21589 | CEFBS_IsThumb2, // t2MVNr = 4194 |
| 21590 | CEFBS_IsThumb2, // t2MVNs = 4195 |
| 21591 | CEFBS_IsThumb2, // t2ORNri = 4196 |
| 21592 | CEFBS_IsThumb2, // t2ORNrr = 4197 |
| 21593 | CEFBS_IsThumb2, // t2ORNrs = 4198 |
| 21594 | CEFBS_IsThumb2, // t2ORRri = 4199 |
| 21595 | CEFBS_IsThumb2, // t2ORRrr = 4200 |
| 21596 | CEFBS_IsThumb2, // t2ORRrs = 4201 |
| 21597 | CEFBS_HasV7_IsMClass, // t2PAC = 4202 |
| 21598 | CEFBS_HasV7_IsMClass, // t2PACBTI = 4203 |
| 21599 | CEFBS_IsThumb2_HasV8_1MMainline_HasPACBTI, // t2PACG = 4204 |
| 21600 | CEFBS_HasDSP_IsThumb2, // t2PKHBT = 4205 |
| 21601 | CEFBS_HasDSP_IsThumb2, // t2PKHTB = 4206 |
| 21602 | CEFBS_IsThumb2_HasV7_HasMP, // t2PLDWi12 = 4207 |
| 21603 | CEFBS_IsThumb2_HasV7_HasMP, // t2PLDWi8 = 4208 |
| 21604 | CEFBS_IsThumb2_HasV7_HasMP, // t2PLDWs = 4209 |
| 21605 | CEFBS_IsThumb2, // t2PLDi12 = 4210 |
| 21606 | CEFBS_IsThumb2, // t2PLDi8 = 4211 |
| 21607 | CEFBS_IsThumb2, // t2PLDpci = 4212 |
| 21608 | CEFBS_IsThumb2, // t2PLDs = 4213 |
| 21609 | CEFBS_IsThumb2_HasV7, // t2PLIi12 = 4214 |
| 21610 | CEFBS_IsThumb2_HasV7, // t2PLIi8 = 4215 |
| 21611 | CEFBS_IsThumb2_HasV7, // t2PLIpci = 4216 |
| 21612 | CEFBS_IsThumb2_HasV7, // t2PLIs = 4217 |
| 21613 | CEFBS_IsThumb2_HasDSP, // t2QADD = 4218 |
| 21614 | CEFBS_IsThumb2_HasDSP, // t2QADD16 = 4219 |
| 21615 | CEFBS_IsThumb2_HasDSP, // t2QADD8 = 4220 |
| 21616 | CEFBS_IsThumb2_HasDSP, // t2QASX = 4221 |
| 21617 | CEFBS_IsThumb2_HasDSP, // t2QDADD = 4222 |
| 21618 | CEFBS_IsThumb2_HasDSP, // t2QDSUB = 4223 |
| 21619 | CEFBS_IsThumb2_HasDSP, // t2QSAX = 4224 |
| 21620 | CEFBS_IsThumb2_HasDSP, // t2QSUB = 4225 |
| 21621 | CEFBS_IsThumb2_HasDSP, // t2QSUB16 = 4226 |
| 21622 | CEFBS_IsThumb2_HasDSP, // t2QSUB8 = 4227 |
| 21623 | CEFBS_IsThumb2, // t2RBIT = 4228 |
| 21624 | CEFBS_IsThumb2, // t2REV = 4229 |
| 21625 | CEFBS_IsThumb2, // t2REV16 = 4230 |
| 21626 | CEFBS_IsThumb2, // t2REVSH = 4231 |
| 21627 | CEFBS_IsThumb2_IsNotMClass, // t2RFEDB = 4232 |
| 21628 | CEFBS_IsThumb2_IsNotMClass, // t2RFEDBW = 4233 |
| 21629 | CEFBS_IsThumb2_IsNotMClass, // t2RFEIA = 4234 |
| 21630 | CEFBS_IsThumb2_IsNotMClass, // t2RFEIAW = 4235 |
| 21631 | CEFBS_IsThumb2, // t2RORri = 4236 |
| 21632 | CEFBS_IsThumb2, // t2RORrr = 4237 |
| 21633 | CEFBS_IsThumb2, // t2RRX = 4238 |
| 21634 | CEFBS_IsThumb2, // t2RSBri = 4239 |
| 21635 | CEFBS_IsThumb2, // t2RSBrr = 4240 |
| 21636 | CEFBS_IsThumb2, // t2RSBrs = 4241 |
| 21637 | CEFBS_IsThumb2_HasDSP, // t2SADD16 = 4242 |
| 21638 | CEFBS_IsThumb2_HasDSP, // t2SADD8 = 4243 |
| 21639 | CEFBS_IsThumb2_HasDSP, // t2SASX = 4244 |
| 21640 | CEFBS_IsThumb2_HasSB, // t2SB = 4245 |
| 21641 | CEFBS_IsThumb2, // t2SBCri = 4246 |
| 21642 | CEFBS_IsThumb2, // t2SBCrr = 4247 |
| 21643 | CEFBS_IsThumb2, // t2SBCrs = 4248 |
| 21644 | CEFBS_IsThumb2, // t2SBFX = 4249 |
| 21645 | CEFBS_HasDivideInThumb_IsThumb_HasV8MBaseline, // t2SDIV = 4250 |
| 21646 | CEFBS_IsThumb2_HasDSP, // t2SEL = 4251 |
| 21647 | CEFBS_IsThumb2_HasV8_HasV8_1a, // t2SETPAN = 4252 |
| 21648 | CEFBS_Has8MSecExt, // t2SG = 4253 |
| 21649 | CEFBS_IsThumb2_HasDSP, // t2SHADD16 = 4254 |
| 21650 | CEFBS_IsThumb2_HasDSP, // t2SHADD8 = 4255 |
| 21651 | CEFBS_IsThumb2_HasDSP, // t2SHASX = 4256 |
| 21652 | CEFBS_IsThumb2_HasDSP, // t2SHSAX = 4257 |
| 21653 | CEFBS_IsThumb2_HasDSP, // t2SHSUB16 = 4258 |
| 21654 | CEFBS_IsThumb2_HasDSP, // t2SHSUB8 = 4259 |
| 21655 | CEFBS_IsThumb2_HasTrustZone, // t2SMC = 4260 |
| 21656 | CEFBS_IsThumb2_HasDSP, // t2SMLABB = 4261 |
| 21657 | CEFBS_IsThumb2_HasDSP, // t2SMLABT = 4262 |
| 21658 | CEFBS_IsThumb2_HasDSP, // t2SMLAD = 4263 |
| 21659 | CEFBS_IsThumb2_HasDSP, // t2SMLADX = 4264 |
| 21660 | CEFBS_IsThumb2, // t2SMLAL = 4265 |
| 21661 | CEFBS_IsThumb2_HasDSP, // t2SMLALBB = 4266 |
| 21662 | CEFBS_IsThumb2_HasDSP, // t2SMLALBT = 4267 |
| 21663 | CEFBS_IsThumb2_HasDSP, // t2SMLALD = 4268 |
| 21664 | CEFBS_IsThumb2_HasDSP, // t2SMLALDX = 4269 |
| 21665 | CEFBS_IsThumb2_HasDSP, // t2SMLALTB = 4270 |
| 21666 | CEFBS_IsThumb2_HasDSP, // t2SMLALTT = 4271 |
| 21667 | CEFBS_IsThumb2_HasDSP, // t2SMLATB = 4272 |
| 21668 | CEFBS_IsThumb2_HasDSP, // t2SMLATT = 4273 |
| 21669 | CEFBS_IsThumb2_HasDSP, // t2SMLAWB = 4274 |
| 21670 | CEFBS_IsThumb2_HasDSP, // t2SMLAWT = 4275 |
| 21671 | CEFBS_IsThumb2_HasDSP, // t2SMLSD = 4276 |
| 21672 | CEFBS_IsThumb2_HasDSP, // t2SMLSDX = 4277 |
| 21673 | CEFBS_IsThumb2_HasDSP, // t2SMLSLD = 4278 |
| 21674 | CEFBS_IsThumb2_HasDSP, // t2SMLSLDX = 4279 |
| 21675 | CEFBS_IsThumb2_HasDSP, // t2SMMLA = 4280 |
| 21676 | CEFBS_IsThumb2_HasDSP, // t2SMMLAR = 4281 |
| 21677 | CEFBS_IsThumb2_HasDSP, // t2SMMLS = 4282 |
| 21678 | CEFBS_IsThumb2_HasDSP, // t2SMMLSR = 4283 |
| 21679 | CEFBS_IsThumb2_HasDSP, // t2SMMUL = 4284 |
| 21680 | CEFBS_IsThumb2_HasDSP, // t2SMMULR = 4285 |
| 21681 | CEFBS_IsThumb2_HasDSP, // t2SMUAD = 4286 |
| 21682 | CEFBS_IsThumb2_HasDSP, // t2SMUADX = 4287 |
| 21683 | CEFBS_IsThumb2_HasDSP, // t2SMULBB = 4288 |
| 21684 | CEFBS_IsThumb2_HasDSP, // t2SMULBT = 4289 |
| 21685 | CEFBS_IsThumb2, // t2SMULL = 4290 |
| 21686 | CEFBS_IsThumb2_HasDSP, // t2SMULTB = 4291 |
| 21687 | CEFBS_IsThumb2_HasDSP, // t2SMULTT = 4292 |
| 21688 | CEFBS_IsThumb2_HasDSP, // t2SMULWB = 4293 |
| 21689 | CEFBS_IsThumb2_HasDSP, // t2SMULWT = 4294 |
| 21690 | CEFBS_IsThumb2_HasDSP, // t2SMUSD = 4295 |
| 21691 | CEFBS_IsThumb2_HasDSP, // t2SMUSDX = 4296 |
| 21692 | CEFBS_IsThumb2_IsNotMClass, // t2SRSDB = 4297 |
| 21693 | CEFBS_IsThumb2_IsNotMClass, // t2SRSDB_UPD = 4298 |
| 21694 | CEFBS_IsThumb2_IsNotMClass, // t2SRSIA = 4299 |
| 21695 | CEFBS_IsThumb2_IsNotMClass, // t2SRSIA_UPD = 4300 |
| 21696 | CEFBS_IsThumb2, // t2SSAT = 4301 |
| 21697 | CEFBS_IsThumb2_HasDSP, // t2SSAT16 = 4302 |
| 21698 | CEFBS_IsThumb2_HasDSP, // t2SSAX = 4303 |
| 21699 | CEFBS_IsThumb2_HasDSP, // t2SSUB16 = 4304 |
| 21700 | CEFBS_IsThumb2_HasDSP, // t2SSUB8 = 4305 |
| 21701 | CEFBS_PreV8_IsThumb2, // t2STC2L_OFFSET = 4306 |
| 21702 | CEFBS_PreV8_IsThumb2, // t2STC2L_OPTION = 4307 |
| 21703 | CEFBS_PreV8_IsThumb2, // t2STC2L_POST = 4308 |
| 21704 | CEFBS_PreV8_IsThumb2, // t2STC2L_PRE = 4309 |
| 21705 | CEFBS_PreV8_IsThumb2, // t2STC2_OFFSET = 4310 |
| 21706 | CEFBS_PreV8_IsThumb2, // t2STC2_OPTION = 4311 |
| 21707 | CEFBS_PreV8_IsThumb2, // t2STC2_POST = 4312 |
| 21708 | CEFBS_PreV8_IsThumb2, // t2STC2_PRE = 4313 |
| 21709 | CEFBS_IsThumb2, // t2STCL_OFFSET = 4314 |
| 21710 | CEFBS_IsThumb2, // t2STCL_OPTION = 4315 |
| 21711 | CEFBS_IsThumb2, // t2STCL_POST = 4316 |
| 21712 | CEFBS_IsThumb2, // t2STCL_PRE = 4317 |
| 21713 | CEFBS_IsThumb2, // t2STC_OFFSET = 4318 |
| 21714 | CEFBS_IsThumb2, // t2STC_OPTION = 4319 |
| 21715 | CEFBS_IsThumb2, // t2STC_POST = 4320 |
| 21716 | CEFBS_IsThumb2, // t2STC_PRE = 4321 |
| 21717 | CEFBS_IsThumb_HasAcquireRelease, // t2STL = 4322 |
| 21718 | CEFBS_IsThumb_HasAcquireRelease, // t2STLB = 4323 |
| 21719 | CEFBS_IsThumb_HasAcquireRelease_HasV7Clrex, // t2STLEX = 4324 |
| 21720 | CEFBS_IsThumb_HasAcquireRelease_HasV7Clrex, // t2STLEXB = 4325 |
| 21721 | CEFBS_IsThumb_HasAcquireRelease_HasV7Clrex_IsNotMClass, // t2STLEXD = 4326 |
| 21722 | CEFBS_IsThumb_HasAcquireRelease_HasV7Clrex, // t2STLEXH = 4327 |
| 21723 | CEFBS_IsThumb_HasAcquireRelease, // t2STLH = 4328 |
| 21724 | CEFBS_IsThumb2, // t2STMDB = 4329 |
| 21725 | CEFBS_IsThumb2, // t2STMDB_UPD = 4330 |
| 21726 | CEFBS_IsThumb2, // t2STMIA = 4331 |
| 21727 | CEFBS_IsThumb2, // t2STMIA_UPD = 4332 |
| 21728 | CEFBS_IsThumb2, // t2STRBT = 4333 |
| 21729 | CEFBS_IsThumb2, // t2STRB_POST = 4334 |
| 21730 | CEFBS_IsThumb2, // t2STRB_PRE = 4335 |
| 21731 | CEFBS_IsThumb2, // t2STRBi12 = 4336 |
| 21732 | CEFBS_IsThumb2, // t2STRBi8 = 4337 |
| 21733 | CEFBS_IsThumb2, // t2STRBs = 4338 |
| 21734 | CEFBS_IsThumb2, // t2STRD_POST = 4339 |
| 21735 | CEFBS_IsThumb2, // t2STRD_PRE = 4340 |
| 21736 | CEFBS_IsThumb2, // t2STRDi8 = 4341 |
| 21737 | CEFBS_IsThumb_HasV8MBaseline, // t2STREX = 4342 |
| 21738 | CEFBS_IsThumb_HasV8MBaseline, // t2STREXB = 4343 |
| 21739 | CEFBS_IsThumb2_IsNotMClass, // t2STREXD = 4344 |
| 21740 | CEFBS_IsThumb_HasV8MBaseline, // t2STREXH = 4345 |
| 21741 | CEFBS_IsThumb2, // t2STRHT = 4346 |
| 21742 | CEFBS_IsThumb2, // t2STRH_POST = 4347 |
| 21743 | CEFBS_IsThumb2, // t2STRH_PRE = 4348 |
| 21744 | CEFBS_IsThumb2, // t2STRHi12 = 4349 |
| 21745 | CEFBS_IsThumb2, // t2STRHi8 = 4350 |
| 21746 | CEFBS_IsThumb2, // t2STRHs = 4351 |
| 21747 | CEFBS_IsThumb2, // t2STRT = 4352 |
| 21748 | CEFBS_IsThumb2, // t2STR_POST = 4353 |
| 21749 | CEFBS_IsThumb2, // t2STR_PRE = 4354 |
| 21750 | CEFBS_IsThumb2, // t2STRi12 = 4355 |
| 21751 | CEFBS_IsThumb2, // t2STRi8 = 4356 |
| 21752 | CEFBS_IsThumb2, // t2STRs = 4357 |
| 21753 | CEFBS_IsThumb2_IsNotMClass, // t2SUBS_PC_LR = 4358 |
| 21754 | CEFBS_IsThumb2, // t2SUBri = 4359 |
| 21755 | CEFBS_IsThumb2, // t2SUBri12 = 4360 |
| 21756 | CEFBS_IsThumb2, // t2SUBrr = 4361 |
| 21757 | CEFBS_IsThumb2, // t2SUBrs = 4362 |
| 21758 | CEFBS_IsThumb2, // t2SUBspImm = 4363 |
| 21759 | CEFBS_IsThumb2, // t2SUBspImm12 = 4364 |
| 21760 | CEFBS_HasDSP_IsThumb2, // t2SXTAB = 4365 |
| 21761 | CEFBS_HasDSP_IsThumb2, // t2SXTAB16 = 4366 |
| 21762 | CEFBS_HasDSP_IsThumb2, // t2SXTAH = 4367 |
| 21763 | CEFBS_IsThumb2, // t2SXTB = 4368 |
| 21764 | CEFBS_HasDSP_IsThumb2, // t2SXTB16 = 4369 |
| 21765 | CEFBS_IsThumb2, // t2SXTH = 4370 |
| 21766 | CEFBS_IsThumb2, // t2TBB = 4371 |
| 21767 | CEFBS_IsThumb2, // t2TBH = 4372 |
| 21768 | CEFBS_IsThumb2, // t2TEQri = 4373 |
| 21769 | CEFBS_IsThumb2, // t2TEQrr = 4374 |
| 21770 | CEFBS_IsThumb2, // t2TEQrs = 4375 |
| 21771 | CEFBS_IsThumb_HasV8_4a, // t2TSB = 4376 |
| 21772 | CEFBS_IsThumb2, // t2TSTri = 4377 |
| 21773 | CEFBS_IsThumb2, // t2TSTrr = 4378 |
| 21774 | CEFBS_IsThumb2, // t2TSTrs = 4379 |
| 21775 | CEFBS_IsThumb_Has8MSecExt, // t2TT = 4380 |
| 21776 | CEFBS_IsThumb_Has8MSecExt, // t2TTA = 4381 |
| 21777 | CEFBS_IsThumb_Has8MSecExt, // t2TTAT = 4382 |
| 21778 | CEFBS_IsThumb_Has8MSecExt, // t2TTT = 4383 |
| 21779 | CEFBS_IsThumb2_HasDSP, // t2UADD16 = 4384 |
| 21780 | CEFBS_IsThumb2_HasDSP, // t2UADD8 = 4385 |
| 21781 | CEFBS_IsThumb2_HasDSP, // t2UASX = 4386 |
| 21782 | CEFBS_IsThumb2, // t2UBFX = 4387 |
| 21783 | CEFBS_IsThumb2, // t2UDF = 4388 |
| 21784 | CEFBS_HasDivideInThumb_IsThumb_HasV8MBaseline, // t2UDIV = 4389 |
| 21785 | CEFBS_IsThumb2_HasDSP, // t2UHADD16 = 4390 |
| 21786 | CEFBS_IsThumb2_HasDSP, // t2UHADD8 = 4391 |
| 21787 | CEFBS_IsThumb2_HasDSP, // t2UHASX = 4392 |
| 21788 | CEFBS_IsThumb2_HasDSP, // t2UHSAX = 4393 |
| 21789 | CEFBS_IsThumb2_HasDSP, // t2UHSUB16 = 4394 |
| 21790 | CEFBS_IsThumb2_HasDSP, // t2UHSUB8 = 4395 |
| 21791 | CEFBS_IsThumb2_HasDSP, // t2UMAAL = 4396 |
| 21792 | CEFBS_IsThumb2, // t2UMLAL = 4397 |
| 21793 | CEFBS_IsThumb2, // t2UMULL = 4398 |
| 21794 | CEFBS_IsThumb2_HasDSP, // t2UQADD16 = 4399 |
| 21795 | CEFBS_IsThumb2_HasDSP, // t2UQADD8 = 4400 |
| 21796 | CEFBS_IsThumb2_HasDSP, // t2UQASX = 4401 |
| 21797 | CEFBS_IsThumb2_HasDSP, // t2UQSAX = 4402 |
| 21798 | CEFBS_IsThumb2_HasDSP, // t2UQSUB16 = 4403 |
| 21799 | CEFBS_IsThumb2_HasDSP, // t2UQSUB8 = 4404 |
| 21800 | CEFBS_IsThumb2_HasDSP, // t2USAD8 = 4405 |
| 21801 | CEFBS_IsThumb2_HasDSP, // t2USADA8 = 4406 |
| 21802 | CEFBS_IsThumb2, // t2USAT = 4407 |
| 21803 | CEFBS_IsThumb2_HasDSP, // t2USAT16 = 4408 |
| 21804 | CEFBS_IsThumb2_HasDSP, // t2USAX = 4409 |
| 21805 | CEFBS_IsThumb2_HasDSP, // t2USUB16 = 4410 |
| 21806 | CEFBS_IsThumb2_HasDSP, // t2USUB8 = 4411 |
| 21807 | CEFBS_HasDSP_IsThumb2, // t2UXTAB = 4412 |
| 21808 | CEFBS_HasDSP_IsThumb2, // t2UXTAB16 = 4413 |
| 21809 | CEFBS_HasDSP_IsThumb2, // t2UXTAH = 4414 |
| 21810 | CEFBS_IsThumb2, // t2UXTB = 4415 |
| 21811 | CEFBS_HasDSP_IsThumb2, // t2UXTB16 = 4416 |
| 21812 | CEFBS_IsThumb2, // t2UXTH = 4417 |
| 21813 | CEFBS_IsThumb2_HasV8_1MMainline_HasLOB, // t2WLS = 4418 |
| 21814 | CEFBS_IsThumb, // tADC = 4419 |
| 21815 | CEFBS_IsThumb, // tADDhirr = 4420 |
| 21816 | CEFBS_IsThumb, // tADDi3 = 4421 |
| 21817 | CEFBS_IsThumb, // tADDi8 = 4422 |
| 21818 | CEFBS_IsThumb, // tADDrSP = 4423 |
| 21819 | CEFBS_IsThumb, // tADDrSPi = 4424 |
| 21820 | CEFBS_IsThumb, // tADDrr = 4425 |
| 21821 | CEFBS_IsThumb, // tADDspi = 4426 |
| 21822 | CEFBS_IsThumb, // tADDspr = 4427 |
| 21823 | CEFBS_IsThumb, // tADR = 4428 |
| 21824 | CEFBS_IsThumb, // tAND = 4429 |
| 21825 | CEFBS_IsThumb, // tASRri = 4430 |
| 21826 | CEFBS_IsThumb, // tASRrr = 4431 |
| 21827 | CEFBS_IsThumb, // tB = 4432 |
| 21828 | CEFBS_IsThumb, // tBIC = 4433 |
| 21829 | CEFBS_IsThumb, // tBKPT = 4434 |
| 21830 | CEFBS_IsThumb, // tBL = 4435 |
| 21831 | CEFBS_IsThumb_Has8MSecExt, // tBLXNSr = 4436 |
| 21832 | CEFBS_IsThumb_HasV5T_IsNotMClass, // tBLXi = 4437 |
| 21833 | CEFBS_IsThumb_HasV5T, // tBLXr = 4438 |
| 21834 | CEFBS_IsThumb, // tBX = 4439 |
| 21835 | CEFBS_IsThumb_Has8MSecExt, // tBXNS = 4440 |
| 21836 | CEFBS_IsThumb, // tBcc = 4441 |
| 21837 | CEFBS_IsThumb_HasV8MBaseline, // tCBNZ = 4442 |
| 21838 | CEFBS_IsThumb_HasV8MBaseline, // tCBZ = 4443 |
| 21839 | CEFBS_IsThumb, // tCMNz = 4444 |
| 21840 | CEFBS_IsThumb, // tCMPhir = 4445 |
| 21841 | CEFBS_IsThumb, // tCMPi8 = 4446 |
| 21842 | CEFBS_IsThumb, // tCMPr = 4447 |
| 21843 | CEFBS_IsThumb, // tCPS = 4448 |
| 21844 | CEFBS_IsThumb, // tEOR = 4449 |
| 21845 | CEFBS_IsThumb_HasV6M, // tHINT = 4450 |
| 21846 | CEFBS_IsThumb_HasV8, // tHLT = 4451 |
| 21847 | CEFBS_IsThumb, // tInt_WIN_eh_sjlj_longjmp = 4452 |
| 21848 | CEFBS_IsThumb, // tInt_eh_sjlj_longjmp = 4453 |
| 21849 | CEFBS_IsThumb, // tInt_eh_sjlj_setjmp = 4454 |
| 21850 | CEFBS_IsThumb, // tLDMIA = 4455 |
| 21851 | CEFBS_IsThumb, // tLDRBi = 4456 |
| 21852 | CEFBS_IsThumb, // tLDRBr = 4457 |
| 21853 | CEFBS_IsThumb, // tLDRHi = 4458 |
| 21854 | CEFBS_IsThumb, // tLDRHr = 4459 |
| 21855 | CEFBS_IsThumb, // tLDRSB = 4460 |
| 21856 | CEFBS_IsThumb, // tLDRSH = 4461 |
| 21857 | CEFBS_IsThumb, // tLDRi = 4462 |
| 21858 | CEFBS_IsThumb, // tLDRpci = 4463 |
| 21859 | CEFBS_IsThumb, // tLDRr = 4464 |
| 21860 | CEFBS_IsThumb, // tLDRspi = 4465 |
| 21861 | CEFBS_IsThumb, // tLSLri = 4466 |
| 21862 | CEFBS_IsThumb, // tLSLrr = 4467 |
| 21863 | CEFBS_IsThumb, // tLSRri = 4468 |
| 21864 | CEFBS_IsThumb, // tLSRrr = 4469 |
| 21865 | CEFBS_IsThumb, // tMOVSr = 4470 |
| 21866 | CEFBS_IsThumb, // tMOVi8 = 4471 |
| 21867 | CEFBS_IsThumb, // tMOVr = 4472 |
| 21868 | CEFBS_IsThumb, // tMUL = 4473 |
| 21869 | CEFBS_IsThumb, // tMVN = 4474 |
| 21870 | CEFBS_IsThumb, // tORR = 4475 |
| 21871 | CEFBS_IsThumb, // tPICADD = 4476 |
| 21872 | CEFBS_IsThumb, // tPOP = 4477 |
| 21873 | CEFBS_IsThumb, // tPUSH = 4478 |
| 21874 | CEFBS_IsThumb_HasV6, // tREV = 4479 |
| 21875 | CEFBS_IsThumb_HasV6, // tREV16 = 4480 |
| 21876 | CEFBS_IsThumb_HasV6, // tREVSH = 4481 |
| 21877 | CEFBS_IsThumb, // tROR = 4482 |
| 21878 | CEFBS_IsThumb, // tRSB = 4483 |
| 21879 | CEFBS_IsThumb, // tSBC = 4484 |
| 21880 | CEFBS_IsThumb_IsNotMClass, // tSETEND = 4485 |
| 21881 | CEFBS_IsThumb, // tSTMIA_UPD = 4486 |
| 21882 | CEFBS_IsThumb, // tSTRBi = 4487 |
| 21883 | CEFBS_IsThumb, // tSTRBr = 4488 |
| 21884 | CEFBS_IsThumb, // tSTRHi = 4489 |
| 21885 | CEFBS_IsThumb, // tSTRHr = 4490 |
| 21886 | CEFBS_IsThumb, // tSTRi = 4491 |
| 21887 | CEFBS_IsThumb, // tSTRr = 4492 |
| 21888 | CEFBS_IsThumb, // tSTRspi = 4493 |
| 21889 | CEFBS_IsThumb, // tSUBi3 = 4494 |
| 21890 | CEFBS_IsThumb, // tSUBi8 = 4495 |
| 21891 | CEFBS_IsThumb, // tSUBrr = 4496 |
| 21892 | CEFBS_IsThumb, // tSUBspi = 4497 |
| 21893 | CEFBS_IsThumb, // tSVC = 4498 |
| 21894 | CEFBS_IsThumb_HasV6, // tSXTB = 4499 |
| 21895 | CEFBS_IsThumb_HasV6, // tSXTH = 4500 |
| 21896 | CEFBS_IsThumb, // tTRAP = 4501 |
| 21897 | CEFBS_IsThumb, // tTST = 4502 |
| 21898 | CEFBS_IsThumb, // tUDF = 4503 |
| 21899 | CEFBS_IsThumb_HasV6, // tUXTB = 4504 |
| 21900 | CEFBS_IsThumb_HasV6, // tUXTH = 4505 |
| 21901 | CEFBS_IsThumb, // t__brkdiv0 = 4506 |
| 21902 | }; |
| 21903 | |
| 21904 | assert(Opcode < 4507); |
| 21905 | return FeatureBitsets[RequiredFeaturesRefs[Opcode]]; |
| 21906 | } |
| 21907 | |
| 21908 | } // end namespace llvm::ARM_MC |
| 21909 | #endif // GET_COMPUTE_FEATURES |
| 21910 | |
| 21911 | #ifdef GET_AVAILABLE_OPCODE_CHECKER |
| 21912 | #undef GET_AVAILABLE_OPCODE_CHECKER |
| 21913 | namespace llvm::ARM_MC { |
| 21914 | bool isOpcodeAvailable(unsigned Opcode, const FeatureBitset &Features) { |
| 21915 | FeatureBitset AvailableFeatures = computeAvailableFeatures(Features); |
| 21916 | FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode); |
| 21917 | FeatureBitset MissingFeatures = |
| 21918 | (AvailableFeatures & RequiredFeatures) ^ |
| 21919 | RequiredFeatures; |
| 21920 | return !MissingFeatures.any(); |
| 21921 | } |
| 21922 | } // end namespace llvm::ARM_MC |
| 21923 | #endif // GET_AVAILABLE_OPCODE_CHECKER |
| 21924 | |
| 21925 | #ifdef ENABLE_INSTR_PREDICATE_VERIFIER |
| 21926 | #undef ENABLE_INSTR_PREDICATE_VERIFIER |
| 21927 | #include <sstream> |
| 21928 | |
| 21929 | namespace llvm::ARM_MC { |
| 21930 | #ifndef NDEBUG |
| 21931 | static const char *SubtargetFeatureNames[] = { |
| 21932 | "Feature_Has8MSecExt", |
| 21933 | "Feature_HasAES", |
| 21934 | "Feature_HasAcquireRelease", |
| 21935 | "Feature_HasBF16", |
| 21936 | "Feature_HasCDE", |
| 21937 | "Feature_HasCLRBHB", |
| 21938 | "Feature_HasCRC", |
| 21939 | "Feature_HasCrypto", |
| 21940 | "Feature_HasDB", |
| 21941 | "Feature_HasDFB", |
| 21942 | "Feature_HasDPVFP", |
| 21943 | "Feature_HasDSP", |
| 21944 | "Feature_HasDivideInARM", |
| 21945 | "Feature_HasDivideInThumb", |
| 21946 | "Feature_HasDotProd", |
| 21947 | "Feature_HasFP16", |
| 21948 | "Feature_HasFP16FML", |
| 21949 | "Feature_HasFPARMv8", |
| 21950 | "Feature_HasFPRegs", |
| 21951 | "Feature_HasFPRegs16", |
| 21952 | "Feature_HasFPRegs64", |
| 21953 | "Feature_HasFPRegsV8_1M", |
| 21954 | "Feature_HasFullFP16", |
| 21955 | "Feature_HasLOB", |
| 21956 | "Feature_HasMP", |
| 21957 | "Feature_HasMVEFloat", |
| 21958 | "Feature_HasMVEInt", |
| 21959 | "Feature_HasMatMulInt8", |
| 21960 | "Feature_HasNEON", |
| 21961 | "Feature_HasNoFPRegs16", |
| 21962 | "Feature_HasPACBTI", |
| 21963 | "Feature_HasRAS", |
| 21964 | "Feature_HasSB", |
| 21965 | "Feature_HasSHA2", |
| 21966 | "Feature_HasTrustZone", |
| 21967 | "Feature_HasV4T", |
| 21968 | "Feature_HasV5T", |
| 21969 | "Feature_HasV5TE", |
| 21970 | "Feature_HasV6", |
| 21971 | "Feature_HasV6K", |
| 21972 | "Feature_HasV6M", |
| 21973 | "Feature_HasV6T2", |
| 21974 | "Feature_HasV7", |
| 21975 | "Feature_HasV7Clrex", |
| 21976 | "Feature_HasV8", |
| 21977 | "Feature_HasV8MBaseline", |
| 21978 | "Feature_HasV8MMainline", |
| 21979 | "Feature_HasV8_1MMainline", |
| 21980 | "Feature_HasV8_1a", |
| 21981 | "Feature_HasV8_2a", |
| 21982 | "Feature_HasV8_3a", |
| 21983 | "Feature_HasV8_4a", |
| 21984 | "Feature_HasV8_5a", |
| 21985 | "Feature_HasV8_6a", |
| 21986 | "Feature_HasV8_7a", |
| 21987 | "Feature_HasVFP2", |
| 21988 | "Feature_HasVFP3", |
| 21989 | "Feature_HasVFP4", |
| 21990 | "Feature_HasVirtualization", |
| 21991 | "Feature_IsARM", |
| 21992 | "Feature_IsMClass", |
| 21993 | "Feature_IsNotMClass", |
| 21994 | "Feature_IsThumb", |
| 21995 | "Feature_IsThumb2", |
| 21996 | "Feature_PreV8", |
| 21997 | "Feature_UseNaClTrap", |
| 21998 | "Feature_UseNegativeImmediates", |
| 21999 | nullptr |
| 22000 | }; |
| 22001 | |
| 22002 | #endif // NDEBUG |
| 22003 | |
| 22004 | void verifyInstructionPredicates( |
| 22005 | unsigned Opcode, const FeatureBitset &Features) { |
| 22006 | #ifndef NDEBUG |
| 22007 | FeatureBitset AvailableFeatures = computeAvailableFeatures(Features); |
| 22008 | FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode); |
| 22009 | FeatureBitset MissingFeatures = |
| 22010 | (AvailableFeatures & RequiredFeatures) ^ |
| 22011 | RequiredFeatures; |
| 22012 | if (MissingFeatures.any()) { |
| 22013 | std::ostringstream Msg; |
| 22014 | Msg << "Attempting to emit "<< &ARMInstrNameData[ARMInstrNameIndices[Opcode]] |
| 22015 | << " instruction but the "; |
| 22016 | for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i) |
| 22017 | if (MissingFeatures.test(i)) |
| 22018 | Msg << SubtargetFeatureNames[i] << " "; |
| 22019 | Msg << "predicate(s) are not met"; |
| 22020 | report_fatal_error(Msg.str().c_str()); |
| 22021 | } |
| 22022 | #endif // NDEBUG |
| 22023 | } |
| 22024 | } // end namespace llvm::ARM_MC |
| 22025 | #endif // ENABLE_INSTR_PREDICATE_VERIFIER |
| 22026 | |
| 22027 |
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