1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Register Bank Source Fragments *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_REGBANK_DECLARATIONS
10#undef GET_REGBANK_DECLARATIONS
11namespace llvm {
12namespace ARM {
13enum : unsigned {
14 InvalidRegBankID = ~0u,
15 FPRRegBankID = 0,
16 GPRRegBankID = 1,
17 NumRegisterBanks,
18};
19} // end namespace ARM
20} // end namespace llvm
21#endif // GET_REGBANK_DECLARATIONS
22
23#ifdef GET_TARGET_REGBANK_CLASS
24#undef GET_TARGET_REGBANK_CLASS
25private:
26 static const RegisterBank *RegBanks[];
27 static const unsigned Sizes[];
28
29public:
30 const RegisterBank &getRegBankFromRegClass(const TargetRegisterClass &RC, LLT Ty) const override;
31protected:
32 ARMGenRegisterBankInfo(unsigned HwMode = 0);
33
34#endif // GET_TARGET_REGBANK_CLASS
35
36#ifdef GET_TARGET_REGBANK_IMPL
37#undef GET_TARGET_REGBANK_IMPL
38namespace llvm {
39namespace ARM {
40const uint32_t FPRRegBankCoverageData[] = {
41 // 0-31
42 (1u << (ARM::HPRRegClassID - 0)) |
43 (1u << (ARM::SPRRegClassID - 0)) |
44 (1u << (ARM::SPR_8RegClassID - 0)) |
45 (1u << (ARM::FPWithVPRRegClassID - 0)) |
46 (1u << (ARM::FPWithVPR_with_ssub_0RegClassID - 0)) |
47 (1u << (ARM::FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8RegClassID - 0)) |
48 0,
49 // 32-63
50 (1u << (ARM::DPRRegClassID - 32)) |
51 (1u << (ARM::DPR_VFP2RegClassID - 32)) |
52 (1u << (ARM::DPR_8RegClassID - 32)) |
53 0,
54 // 64-95
55 (1u << (ARM::QPRRegClassID - 64)) |
56 (1u << (ARM::MQPRRegClassID - 64)) |
57 (1u << (ARM::QPR_VFP2RegClassID - 64)) |
58 (1u << (ARM::QPR_8RegClassID - 64)) |
59 0,
60 // 96-127
61 0,
62 // 128-159
63 0,
64};
65const uint32_t GPRRegBankCoverageData[] = {
66 // 0-31
67 (1u << (ARM::GPRRegClassID - 0)) |
68 (1u << (ARM::GPRnopcRegClassID - 0)) |
69 (1u << (ARM::rGPRRegClassID - 0)) |
70 (1u << (ARM::GPRnoip_and_GPRwithAPSR_NZCVnospRegClassID - 0)) |
71 (1u << (ARM::tGPRRegClassID - 0)) |
72 (1u << (ARM::GPRnoip_and_tGPREvenRegClassID - 0)) |
73 (1u << (ARM::tGPROddRegClassID - 0)) |
74 (1u << (ARM::tGPREvenRegClassID - 0)) |
75 (1u << (ARM::GPRnosp_and_GPRnopc_and_hGPRRegClassID - 0)) |
76 (1u << (ARM::tcGPRRegClassID - 0)) |
77 (1u << (ARM::GPRnoip_and_GPRnopcRegClassID - 0)) |
78 (1u << (ARM::GPRnopc_and_GPRnoip_and_hGPRRegClassID - 0)) |
79 (1u << (ARM::GPRnopc_and_hGPRRegClassID - 0)) |
80 (1u << (ARM::GPRnospRegClassID - 0)) |
81 (1u << (ARM::GPRnoip_and_GPRnospRegClassID - 0)) |
82 (1u << (ARM::tGPRwithpcRegClassID - 0)) |
83 (1u << (ARM::GPRnosp_and_GPRnoip_and_hGPRRegClassID - 0)) |
84 (1u << (ARM::GPRnosp_and_hGPRRegClassID - 0)) |
85 (1u << (ARM::GPRnoipRegClassID - 0)) |
86 (1u << (ARM::GPRnoip_and_hGPRRegClassID - 0)) |
87 (1u << (ARM::hGPRRegClassID - 0)) |
88 (1u << (ARM::GPRwithAPSRRegClassID - 0)) |
89 (1u << (ARM::GPRwithAPSR_NZCVnospRegClassID - 0)) |
90 0,
91 // 32-63
92 (1u << (ARM::tGPR_and_tGPREvenRegClassID - 32)) |
93 (1u << (ARM::tGPREven_and_tcGPRnotr12RegClassID - 32)) |
94 (1u << (ARM::tGPR_and_tGPROddRegClassID - 32)) |
95 (1u << (ARM::tGPROdd_and_tcGPRRegClassID - 32)) |
96 (1u << (ARM::tcGPRnotr12RegClassID - 32)) |
97 (1u << (ARM::hGPR_and_GPRnoip_and_tGPREvenRegClassID - 32)) |
98 (1u << (ARM::hGPR_and_tGPROddRegClassID - 32)) |
99 (1u << (ARM::GPRnosp_and_GPRnopc_and_GPRnoip_and_hGPRRegClassID - 32)) |
100 (1u << (ARM::hGPR_and_tGPREvenRegClassID - 32)) |
101 (1u << (ARM::GPRlrRegClassID - 32)) |
102 (1u << (ARM::hGPR_and_tcGPRRegClassID - 32)) |
103 (1u << (ARM::tGPREven_and_tcGPRRegClassID - 32)) |
104 (1u << (ARM::GPRspRegClassID - 32)) |
105 (1u << (ARM::hGPR_and_tGPRwithpcRegClassID - 32)) |
106 0,
107 // 64-95
108 0,
109 // 96-127
110 0,
111 // 128-159
112 0,
113};
114
115constexpr RegisterBank FPRRegBank(/* ID */ ARM::FPRRegBankID, /* Name */ "FPRB", /* CoveredRegClasses */ FPRRegBankCoverageData, /* NumRegClasses */ 137);
116constexpr RegisterBank GPRRegBank(/* ID */ ARM::GPRRegBankID, /* Name */ "GPRB", /* CoveredRegClasses */ GPRRegBankCoverageData, /* NumRegClasses */ 137);
117} // end namespace ARM
118
119const RegisterBank *ARMGenRegisterBankInfo::RegBanks[] = {
120 &ARM::FPRRegBank,
121 &ARM::GPRRegBank,
122};
123
124const unsigned ARMGenRegisterBankInfo::Sizes[] = {
125 // Mode = 0 (Default)
126 128,
127 32,
128};
129
130ARMGenRegisterBankInfo::ARMGenRegisterBankInfo(unsigned HwMode)
131 : RegisterBankInfo(RegBanks, ARM::NumRegisterBanks, Sizes, HwMode) {
132 // Assert that RegBank indices match their ID's
133#ifndef NDEBUG
134 for (auto RB : enumerate(RegBanks))
135 assert(RB.index() == RB.value()->getID() && "Index != ID");
136#endif // NDEBUG
137}
138const RegisterBank &
139ARMGenRegisterBankInfo::getRegBankFromRegClass(const TargetRegisterClass &RC, LLT) const {
140 constexpr uint32_t InvalidRegBankID = uint32_t(ARM::InvalidRegBankID) & 3;
141 static const uint32_t RegClass2RegBank[5] = {
142 (uint32_t(ARM::FPRRegBankID) << 0) | // HPRRegClassID
143 (uint32_t(ARM::FPRRegBankID) << 2) | // FPWithVPRRegClassID
144 (uint32_t(ARM::FPRRegBankID) << 4) | // SPRRegClassID
145 (uint32_t(ARM::FPRRegBankID) << 6) | // FPWithVPR_with_ssub_0RegClassID
146 (uint32_t(ARM::GPRRegBankID) << 8) | // GPRRegClassID
147 (uint32_t(ARM::GPRRegBankID) << 10) | // GPRwithAPSRRegClassID
148 (uint32_t(InvalidRegBankID) << 12) |
149 (uint32_t(ARM::FPRRegBankID) << 14) | // SPR_8RegClassID
150 (uint32_t(ARM::GPRRegBankID) << 16) | // GPRnopcRegClassID
151 (uint32_t(ARM::GPRRegBankID) << 18) | // GPRnospRegClassID
152 (uint32_t(ARM::GPRRegBankID) << 20) | // GPRwithAPSR_NZCVnospRegClassID
153 (uint32_t(InvalidRegBankID) << 22) |
154 (uint32_t(InvalidRegBankID) << 24) |
155 (uint32_t(ARM::GPRRegBankID) << 26) | // GPRnoipRegClassID
156 (uint32_t(ARM::GPRRegBankID) << 28) | // rGPRRegClassID
157 (uint32_t(ARM::GPRRegBankID) << 30), // GPRnoip_and_GPRnopcRegClassID
158 (uint32_t(ARM::GPRRegBankID) << 0) | // GPRnoip_and_GPRnospRegClassID
159 (uint32_t(ARM::GPRRegBankID) << 2) | // GPRnoip_and_GPRwithAPSR_NZCVnospRegClassID
160 (uint32_t(ARM::GPRRegBankID) << 4) | // tGPRwithpcRegClassID
161 (uint32_t(ARM::FPRRegBankID) << 6) | // FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8RegClassID
162 (uint32_t(ARM::GPRRegBankID) << 8) | // hGPRRegClassID
163 (uint32_t(ARM::GPRRegBankID) << 10) | // tGPRRegClassID
164 (uint32_t(ARM::GPRRegBankID) << 12) | // tGPREvenRegClassID
165 (uint32_t(ARM::GPRRegBankID) << 14) | // GPRnopc_and_hGPRRegClassID
166 (uint32_t(ARM::GPRRegBankID) << 16) | // GPRnosp_and_hGPRRegClassID
167 (uint32_t(ARM::GPRRegBankID) << 18) | // GPRnoip_and_hGPRRegClassID
168 (uint32_t(ARM::GPRRegBankID) << 20) | // GPRnoip_and_tGPREvenRegClassID
169 (uint32_t(ARM::GPRRegBankID) << 22) | // GPRnosp_and_GPRnopc_and_hGPRRegClassID
170 (uint32_t(ARM::GPRRegBankID) << 24) | // tGPROddRegClassID
171 (uint32_t(ARM::GPRRegBankID) << 26) | // GPRnopc_and_GPRnoip_and_hGPRRegClassID
172 (uint32_t(ARM::GPRRegBankID) << 28) | // GPRnosp_and_GPRnoip_and_hGPRRegClassID
173 (uint32_t(ARM::GPRRegBankID) << 30), // tcGPRRegClassID
174 (uint32_t(ARM::GPRRegBankID) << 0) | // GPRnosp_and_GPRnopc_and_GPRnoip_and_hGPRRegClassID
175 (uint32_t(ARM::GPRRegBankID) << 2) | // hGPR_and_tGPREvenRegClassID
176 (uint32_t(ARM::GPRRegBankID) << 4) | // tGPR_and_tGPREvenRegClassID
177 (uint32_t(ARM::GPRRegBankID) << 6) | // tGPR_and_tGPROddRegClassID
178 (uint32_t(ARM::GPRRegBankID) << 8) | // tcGPRnotr12RegClassID
179 (uint32_t(ARM::GPRRegBankID) << 10) | // tGPREven_and_tcGPRRegClassID
180 (uint32_t(InvalidRegBankID) << 12) |
181 (uint32_t(ARM::GPRRegBankID) << 14) | // hGPR_and_GPRnoip_and_tGPREvenRegClassID
182 (uint32_t(ARM::GPRRegBankID) << 16) | // hGPR_and_tGPROddRegClassID
183 (uint32_t(ARM::GPRRegBankID) << 18) | // tGPREven_and_tcGPRnotr12RegClassID
184 (uint32_t(ARM::GPRRegBankID) << 20) | // tGPROdd_and_tcGPRRegClassID
185 (uint32_t(InvalidRegBankID) << 22) |
186 (uint32_t(InvalidRegBankID) << 24) |
187 (uint32_t(ARM::GPRRegBankID) << 26) | // GPRlrRegClassID
188 (uint32_t(ARM::GPRRegBankID) << 28) | // GPRspRegClassID
189 (uint32_t(InvalidRegBankID) << 30),
190 (uint32_t(InvalidRegBankID) << 0) |
191 (uint32_t(ARM::GPRRegBankID) << 2) | // hGPR_and_tGPRwithpcRegClassID
192 (uint32_t(ARM::GPRRegBankID) << 4) | // hGPR_and_tcGPRRegClassID
193 (uint32_t(ARM::FPRRegBankID) << 6) | // DPRRegClassID
194 (uint32_t(ARM::FPRRegBankID) << 8) | // DPR_VFP2RegClassID
195 (uint32_t(ARM::FPRRegBankID) << 10) | // DPR_8RegClassID
196 (uint32_t(InvalidRegBankID) << 12) |
197 (uint32_t(InvalidRegBankID) << 14) |
198 (uint32_t(InvalidRegBankID) << 16) |
199 (uint32_t(InvalidRegBankID) << 18) |
200 (uint32_t(InvalidRegBankID) << 20) |
201 (uint32_t(InvalidRegBankID) << 22) |
202 (uint32_t(InvalidRegBankID) << 24) |
203 (uint32_t(InvalidRegBankID) << 26) |
204 (uint32_t(InvalidRegBankID) << 28) |
205 (uint32_t(InvalidRegBankID) << 30),
206 (uint32_t(InvalidRegBankID) << 0) |
207 (uint32_t(InvalidRegBankID) << 2) |
208 (uint32_t(InvalidRegBankID) << 4) |
209 (uint32_t(InvalidRegBankID) << 6) |
210 (uint32_t(InvalidRegBankID) << 8) |
211 (uint32_t(ARM::FPRRegBankID) << 10) | // QPRRegClassID
212 (uint32_t(InvalidRegBankID) << 12) |
213 (uint32_t(InvalidRegBankID) << 14) |
214 (uint32_t(ARM::FPRRegBankID) << 16) | // MQPRRegClassID
215 (uint32_t(ARM::FPRRegBankID) << 18) | // QPR_VFP2RegClassID
216 (uint32_t(InvalidRegBankID) << 20) |
217 (uint32_t(ARM::FPRRegBankID) << 22) // QPR_8RegClassID
218 };
219 const unsigned RegClassID = RC.getID();
220 if (LLVM_LIKELY(RegClassID < 76)) {
221 unsigned RegBankID = (RegClass2RegBank[RegClassID / 16] >> ((RegClassID % 16) * 2)) & 3;
222 if (RegBankID != InvalidRegBankID)
223 return getRegBank(RegBankID);
224 }
225 llvm_unreachable(llvm::Twine("Target needs to handle register class ID 0x").concat(llvm::Twine::utohexstr(RegClassID)).str().c_str());
226}
227} // end namespace llvm
228#endif // GET_TARGET_REGBANK_IMPL
229