1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Assembly Matcher Source Fragment *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* From: AVR.td *|
7|* *|
8\*===----------------------------------------------------------------------===*/
9
10
11#ifdef GET_ASSEMBLER_HEADER
12#undef GET_ASSEMBLER_HEADER
13 // This should be included into the middle of the declaration of
14 // your subclasses implementation of MCTargetAsmParser.
15 FeatureBitset ComputeAvailableFeatures(const FeatureBitset &FB) const;
16 void convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
17 const OperandVector &Operands);
18 void convertToMapAndConstraints(unsigned Kind,
19 const OperandVector &Operands) override;
20 unsigned MatchInstructionImpl(const OperandVector &Operands,
21 MCInst &Inst,
22 uint64_t &ErrorInfo,
23 FeatureBitset &MissingFeatures,
24 bool matchingInlineAsm,
25 unsigned VariantID = 0);
26 unsigned MatchInstructionImpl(const OperandVector &Operands,
27 MCInst &Inst,
28 uint64_t &ErrorInfo,
29 bool matchingInlineAsm,
30 unsigned VariantID = 0) {
31 FeatureBitset MissingFeatures;
32 return MatchInstructionImpl(Operands, Inst, ErrorInfo, MissingFeatures,
33 matchingInlineAsm, VariantID);
34 }
35
36 ParseStatus MatchOperandParserImpl(
37 OperandVector &Operands,
38 StringRef Mnemonic,
39 bool ParseForAllFeatures = false);
40 ParseStatus tryCustomParseOperand(
41 OperandVector &Operands,
42 unsigned MCK);
43
44#endif // GET_ASSEMBLER_HEADER
45
46
47#ifdef GET_OPERAND_DIAGNOSTIC_TYPES
48#undef GET_OPERAND_DIAGNOSTIC_TYPES
49
50#endif // GET_OPERAND_DIAGNOSTIC_TYPES
51
52
53#ifdef GET_REGISTER_MATCHER
54#undef GET_REGISTER_MATCHER
55
56// Bits for subtarget features that participate in instruction matching.
57enum SubtargetFeatureBits : uint8_t {
58 Feature_HasSRAMBit = 14,
59 Feature_HasJMPCALLBit = 7,
60 Feature_HasIJMPCALLBit = 6,
61 Feature_HasEIJMPCALLBit = 3,
62 Feature_HasADDSUBIWBit = 0,
63 Feature_HasSmallStackBit = 15,
64 Feature_HasMOVWBit = 10,
65 Feature_HasLPMBit = 8,
66 Feature_HasLPMXBit = 9,
67 Feature_HasELPMBit = 4,
68 Feature_HasELPMXBit = 5,
69 Feature_HasSPMBit = 12,
70 Feature_HasSPMXBit = 13,
71 Feature_HasDESBit = 2,
72 Feature_SupportsRMWBit = 18,
73 Feature_SupportsMultiplicationBit = 17,
74 Feature_HasBREAKBit = 1,
75 Feature_HasTinyEncodingBit = 16,
76 Feature_HasNonTinyEncodingBit = 11,
77};
78
79static MCRegister MatchRegisterName(StringRef Name) {
80 switch (Name.size()) {
81 default: break;
82 case 2: // 11 strings to match.
83 switch (Name[0]) {
84 default: break;
85 case 'S': // 1 string to match.
86 if (Name[1] != 'P')
87 break;
88 return AVR::SP; // "SP"
89 case 'r': // 10 strings to match.
90 switch (Name[1]) {
91 default: break;
92 case '0': // 1 string to match.
93 return AVR::R0; // "r0"
94 case '1': // 1 string to match.
95 return AVR::R1; // "r1"
96 case '2': // 1 string to match.
97 return AVR::R2; // "r2"
98 case '3': // 1 string to match.
99 return AVR::R3; // "r3"
100 case '4': // 1 string to match.
101 return AVR::R4; // "r4"
102 case '5': // 1 string to match.
103 return AVR::R5; // "r5"
104 case '6': // 1 string to match.
105 return AVR::R6; // "r6"
106 case '7': // 1 string to match.
107 return AVR::R7; // "r7"
108 case '8': // 1 string to match.
109 return AVR::R8; // "r8"
110 case '9': // 1 string to match.
111 return AVR::R9; // "r9"
112 }
113 break;
114 }
115 break;
116 case 3: // 24 strings to match.
117 switch (Name[0]) {
118 default: break;
119 case 'S': // 2 strings to match.
120 if (Name[1] != 'P')
121 break;
122 switch (Name[2]) {
123 default: break;
124 case 'H': // 1 string to match.
125 return AVR::SPH; // "SPH"
126 case 'L': // 1 string to match.
127 return AVR::SPL; // "SPL"
128 }
129 break;
130 case 'r': // 22 strings to match.
131 switch (Name[1]) {
132 default: break;
133 case '1': // 10 strings to match.
134 switch (Name[2]) {
135 default: break;
136 case '0': // 1 string to match.
137 return AVR::R10; // "r10"
138 case '1': // 1 string to match.
139 return AVR::R11; // "r11"
140 case '2': // 1 string to match.
141 return AVR::R12; // "r12"
142 case '3': // 1 string to match.
143 return AVR::R13; // "r13"
144 case '4': // 1 string to match.
145 return AVR::R14; // "r14"
146 case '5': // 1 string to match.
147 return AVR::R15; // "r15"
148 case '6': // 1 string to match.
149 return AVR::R16; // "r16"
150 case '7': // 1 string to match.
151 return AVR::R17; // "r17"
152 case '8': // 1 string to match.
153 return AVR::R18; // "r18"
154 case '9': // 1 string to match.
155 return AVR::R19; // "r19"
156 }
157 break;
158 case '2': // 10 strings to match.
159 switch (Name[2]) {
160 default: break;
161 case '0': // 1 string to match.
162 return AVR::R20; // "r20"
163 case '1': // 1 string to match.
164 return AVR::R21; // "r21"
165 case '2': // 1 string to match.
166 return AVR::R22; // "r22"
167 case '3': // 1 string to match.
168 return AVR::R23; // "r23"
169 case '4': // 1 string to match.
170 return AVR::R24; // "r24"
171 case '5': // 1 string to match.
172 return AVR::R25; // "r25"
173 case '6': // 1 string to match.
174 return AVR::R26; // "r26"
175 case '7': // 1 string to match.
176 return AVR::R27; // "r27"
177 case '8': // 1 string to match.
178 return AVR::R28; // "r28"
179 case '9': // 1 string to match.
180 return AVR::R29; // "r29"
181 }
182 break;
183 case '3': // 2 strings to match.
184 switch (Name[2]) {
185 default: break;
186 case '0': // 1 string to match.
187 return AVR::R30; // "r30"
188 case '1': // 1 string to match.
189 return AVR::R31; // "r31"
190 }
191 break;
192 }
193 break;
194 }
195 break;
196 case 5: // 6 strings to match.
197 switch (Name[0]) {
198 default: break;
199 case 'F': // 1 string to match.
200 if (memcmp(Name.data()+1, "LAGS", 4) != 0)
201 break;
202 return AVR::SREG; // "FLAGS"
203 case 'r': // 5 strings to match.
204 switch (Name[1]) {
205 default: break;
206 case '1': // 1 string to match.
207 if (memcmp(Name.data()+2, ":r0", 3) != 0)
208 break;
209 return AVR::R1R0; // "r1:r0"
210 case '3': // 1 string to match.
211 if (memcmp(Name.data()+2, ":r2", 3) != 0)
212 break;
213 return AVR::R3R2; // "r3:r2"
214 case '5': // 1 string to match.
215 if (memcmp(Name.data()+2, ":r4", 3) != 0)
216 break;
217 return AVR::R5R4; // "r5:r4"
218 case '7': // 1 string to match.
219 if (memcmp(Name.data()+2, ":r6", 3) != 0)
220 break;
221 return AVR::R7R6; // "r7:r6"
222 case '9': // 1 string to match.
223 if (memcmp(Name.data()+2, ":r8", 3) != 0)
224 break;
225 return AVR::R9R8; // "r9:r8"
226 }
227 break;
228 }
229 break;
230 case 6: // 1 string to match.
231 if (memcmp(Name.data()+0, "r10:r9", 6) != 0)
232 break;
233 return AVR::R10R9; // "r10:r9"
234 case 7: // 19 strings to match.
235 if (Name[0] != 'r')
236 break;
237 switch (Name[1]) {
238 default: break;
239 case '1': // 9 strings to match.
240 switch (Name[2]) {
241 default: break;
242 case '1': // 1 string to match.
243 if (memcmp(Name.data()+3, ":r10", 4) != 0)
244 break;
245 return AVR::R11R10; // "r11:r10"
246 case '2': // 1 string to match.
247 if (memcmp(Name.data()+3, ":r11", 4) != 0)
248 break;
249 return AVR::R12R11; // "r12:r11"
250 case '3': // 1 string to match.
251 if (memcmp(Name.data()+3, ":r12", 4) != 0)
252 break;
253 return AVR::R13R12; // "r13:r12"
254 case '4': // 1 string to match.
255 if (memcmp(Name.data()+3, ":r13", 4) != 0)
256 break;
257 return AVR::R14R13; // "r14:r13"
258 case '5': // 1 string to match.
259 if (memcmp(Name.data()+3, ":r14", 4) != 0)
260 break;
261 return AVR::R15R14; // "r15:r14"
262 case '6': // 1 string to match.
263 if (memcmp(Name.data()+3, ":r15", 4) != 0)
264 break;
265 return AVR::R16R15; // "r16:r15"
266 case '7': // 1 string to match.
267 if (memcmp(Name.data()+3, ":r16", 4) != 0)
268 break;
269 return AVR::R17R16; // "r17:r16"
270 case '8': // 1 string to match.
271 if (memcmp(Name.data()+3, ":r17", 4) != 0)
272 break;
273 return AVR::R18R17; // "r18:r17"
274 case '9': // 1 string to match.
275 if (memcmp(Name.data()+3, ":r18", 4) != 0)
276 break;
277 return AVR::R19R18; // "r19:r18"
278 }
279 break;
280 case '2': // 9 strings to match.
281 switch (Name[2]) {
282 default: break;
283 case '0': // 1 string to match.
284 if (memcmp(Name.data()+3, ":r19", 4) != 0)
285 break;
286 return AVR::R20R19; // "r20:r19"
287 case '1': // 1 string to match.
288 if (memcmp(Name.data()+3, ":r20", 4) != 0)
289 break;
290 return AVR::R21R20; // "r21:r20"
291 case '2': // 1 string to match.
292 if (memcmp(Name.data()+3, ":r21", 4) != 0)
293 break;
294 return AVR::R22R21; // "r22:r21"
295 case '3': // 1 string to match.
296 if (memcmp(Name.data()+3, ":r22", 4) != 0)
297 break;
298 return AVR::R23R22; // "r23:r22"
299 case '4': // 1 string to match.
300 if (memcmp(Name.data()+3, ":r23", 4) != 0)
301 break;
302 return AVR::R24R23; // "r24:r23"
303 case '5': // 1 string to match.
304 if (memcmp(Name.data()+3, ":r24", 4) != 0)
305 break;
306 return AVR::R25R24; // "r25:r24"
307 case '6': // 1 string to match.
308 if (memcmp(Name.data()+3, ":r25", 4) != 0)
309 break;
310 return AVR::R26R25; // "r26:r25"
311 case '7': // 1 string to match.
312 if (memcmp(Name.data()+3, ":r26", 4) != 0)
313 break;
314 return AVR::R27R26; // "r27:r26"
315 case '9': // 1 string to match.
316 if (memcmp(Name.data()+3, ":r28", 4) != 0)
317 break;
318 return AVR::R29R28; // "r29:r28"
319 }
320 break;
321 case '3': // 1 string to match.
322 if (memcmp(Name.data()+2, "1:r30", 5) != 0)
323 break;
324 return AVR::R31R30; // "r31:r30"
325 }
326 break;
327 }
328 return AVR::NoRegister;
329}
330
331static MCRegister MatchRegisterAltName(StringRef Name) {
332 switch (Name.size()) {
333 default: break;
334 case 1: // 3 strings to match.
335 switch (Name[0]) {
336 default: break;
337 case 'X': // 1 string to match.
338 return AVR::R27R26; // "X"
339 case 'Y': // 1 string to match.
340 return AVR::R29R28; // "Y"
341 case 'Z': // 1 string to match.
342 return AVR::R31R30; // "Z"
343 }
344 break;
345 case 2: // 6 strings to match.
346 switch (Name[0]) {
347 default: break;
348 case 'x': // 2 strings to match.
349 switch (Name[1]) {
350 default: break;
351 case 'h': // 1 string to match.
352 return AVR::R27; // "xh"
353 case 'l': // 1 string to match.
354 return AVR::R26; // "xl"
355 }
356 break;
357 case 'y': // 2 strings to match.
358 switch (Name[1]) {
359 default: break;
360 case 'h': // 1 string to match.
361 return AVR::R29; // "yh"
362 case 'l': // 1 string to match.
363 return AVR::R28; // "yl"
364 }
365 break;
366 case 'z': // 2 strings to match.
367 switch (Name[1]) {
368 default: break;
369 case 'h': // 1 string to match.
370 return AVR::R31; // "zh"
371 case 'l': // 1 string to match.
372 return AVR::R30; // "zl"
373 }
374 break;
375 }
376 break;
377 }
378 return AVR::NoRegister;
379}
380
381#endif // GET_REGISTER_MATCHER
382
383
384#ifdef GET_SUBTARGET_FEATURE_NAME
385#undef GET_SUBTARGET_FEATURE_NAME
386
387// User-level names for subtarget features that participate in
388// instruction matching.
389static const char *getSubtargetFeatureName(uint64_t Val) {
390 switch(Val) {
391 case Feature_HasSRAMBit: return "";
392 case Feature_HasJMPCALLBit: return "";
393 case Feature_HasIJMPCALLBit: return "";
394 case Feature_HasEIJMPCALLBit: return "";
395 case Feature_HasADDSUBIWBit: return "";
396 case Feature_HasSmallStackBit: return "";
397 case Feature_HasMOVWBit: return "";
398 case Feature_HasLPMBit: return "";
399 case Feature_HasLPMXBit: return "";
400 case Feature_HasELPMBit: return "";
401 case Feature_HasELPMXBit: return "";
402 case Feature_HasSPMBit: return "";
403 case Feature_HasSPMXBit: return "";
404 case Feature_HasDESBit: return "";
405 case Feature_SupportsRMWBit: return "";
406 case Feature_SupportsMultiplicationBit: return "";
407 case Feature_HasBREAKBit: return "";
408 case Feature_HasTinyEncodingBit: return "";
409 case Feature_HasNonTinyEncodingBit: return "";
410 default: return "(unknown)";
411 }
412}
413
414#endif // GET_SUBTARGET_FEATURE_NAME
415
416
417#ifdef GET_MATCHER_IMPLEMENTATION
418#undef GET_MATCHER_IMPLEMENTATION
419
420enum {
421 Tie0_1_1,
422 Tie0_2_2,
423 Tie1_2_2,
424 Tie1_3_3,
425};
426
427static const uint8_t TiedAsmOperandTable[][3] = {
428 /* Tie0_1_1 */ { 0, 1, 1 },
429 /* Tie0_2_2 */ { 0, 2, 2 },
430 /* Tie1_2_2 */ { 1, 2, 2 },
431 /* Tie1_3_3 */ { 1, 3, 3 },
432};
433
434namespace {
435enum OperatorConversionKind {
436 CVT_Done,
437 CVT_Reg,
438 CVT_Tied,
439 CVT_95_Reg,
440 CVT_95_addImmOperands,
441 CVT_imm_95_0,
442 CVT_imm_95_5,
443 CVT_imm_95_7,
444 CVT_imm_95_6,
445 CVT_imm_95_3,
446 CVT_95_addImmCom8Operands,
447 CVT_imm_95_2,
448 CVT_imm_95_4,
449 CVT_imm_95_1,
450 CVT_95_addMemriOperands,
451 CVT_imm_95_255,
452 CVT_NUM_CONVERTERS
453};
454
455enum InstructionConversionKind {
456 Convert__Reg1_0__Tie0_1_1__Reg1_1,
457 Convert__Reg1_0__Tie0_1_1__Imm1_1,
458 Convert__Reg1_0__Tie0_1_1,
459 Convert__Imm1_0,
460 Convert__Imm1_0__Imm1_1,
461 Convert__imm_95_0__Imm1_0,
462 Convert_NoOperands,
463 Convert__imm_95_5__Imm1_0,
464 Convert__imm_95_7__Imm1_0,
465 Convert__imm_95_6__Imm1_0,
466 Convert__imm_95_3__Imm1_0,
467 Convert__Reg1_0__Imm1_1,
468 Convert__Reg1_0__Tie0_1_1__ImmCom81_1,
469 Convert__imm_95_0,
470 Convert__imm_95_5,
471 Convert__imm_95_7,
472 Convert__imm_95_2,
473 Convert__Reg1_0__Tie0_1_1__Reg1_0,
474 Convert__imm_95_4,
475 Convert__imm_95_6,
476 Convert__imm_95_3,
477 Convert__imm_95_1,
478 Convert__Reg1_0__Reg1_1,
479 Convert__Reg1_1__Reg1_0,
480 Convert__Reg1_0__Reg1_2__Tie1_3_3,
481 Convert__Reg1_0__Reg1_1__Tie1_2_2,
482 Convert__Reg1_0__Memri2_1,
483 Convert__Imm1_0__Reg1_1,
484 Convert__Reg1_0,
485 Convert__Reg1_0__imm_95_255,
486 Convert__Reg1_1__Tie0_2_2__Reg1_2__imm_95_0,
487 Convert__Reg1_0__Tie0_1_1__Reg1_2__imm_95_0,
488 Convert__Memri2_0__Reg1_1,
489 CVT_NUM_SIGNATURES
490};
491
492} // end anonymous namespace
493
494static const uint8_t ConversionTable[CVT_NUM_SIGNATURES][9] = {
495 // Convert__Reg1_0__Tie0_1_1__Reg1_1
496 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_Done },
497 // Convert__Reg1_0__Tie0_1_1__Imm1_1
498 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_Done },
499 // Convert__Reg1_0__Tie0_1_1
500 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_Done },
501 // Convert__Imm1_0
502 { CVT_95_addImmOperands, 1, CVT_Done },
503 // Convert__Imm1_0__Imm1_1
504 { CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
505 // Convert__imm_95_0__Imm1_0
506 { CVT_imm_95_0, 0, CVT_95_addImmOperands, 1, CVT_Done },
507 // Convert_NoOperands
508 { CVT_Done },
509 // Convert__imm_95_5__Imm1_0
510 { CVT_imm_95_5, 0, CVT_95_addImmOperands, 1, CVT_Done },
511 // Convert__imm_95_7__Imm1_0
512 { CVT_imm_95_7, 0, CVT_95_addImmOperands, 1, CVT_Done },
513 // Convert__imm_95_6__Imm1_0
514 { CVT_imm_95_6, 0, CVT_95_addImmOperands, 1, CVT_Done },
515 // Convert__imm_95_3__Imm1_0
516 { CVT_imm_95_3, 0, CVT_95_addImmOperands, 1, CVT_Done },
517 // Convert__Reg1_0__Imm1_1
518 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
519 // Convert__Reg1_0__Tie0_1_1__ImmCom81_1
520 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmCom8Operands, 2, CVT_Done },
521 // Convert__imm_95_0
522 { CVT_imm_95_0, 0, CVT_Done },
523 // Convert__imm_95_5
524 { CVT_imm_95_5, 0, CVT_Done },
525 // Convert__imm_95_7
526 { CVT_imm_95_7, 0, CVT_Done },
527 // Convert__imm_95_2
528 { CVT_imm_95_2, 0, CVT_Done },
529 // Convert__Reg1_0__Tie0_1_1__Reg1_0
530 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 1, CVT_Done },
531 // Convert__imm_95_4
532 { CVT_imm_95_4, 0, CVT_Done },
533 // Convert__imm_95_6
534 { CVT_imm_95_6, 0, CVT_Done },
535 // Convert__imm_95_3
536 { CVT_imm_95_3, 0, CVT_Done },
537 // Convert__imm_95_1
538 { CVT_imm_95_1, 0, CVT_Done },
539 // Convert__Reg1_0__Reg1_1
540 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Done },
541 // Convert__Reg1_1__Reg1_0
542 { CVT_95_Reg, 2, CVT_95_Reg, 1, CVT_Done },
543 // Convert__Reg1_0__Reg1_2__Tie1_3_3
544 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_Tied, Tie1_3_3, CVT_Done },
545 // Convert__Reg1_0__Reg1_1__Tie1_2_2
546 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Tied, Tie1_2_2, CVT_Done },
547 // Convert__Reg1_0__Memri2_1
548 { CVT_95_Reg, 1, CVT_95_addMemriOperands, 2, CVT_Done },
549 // Convert__Imm1_0__Reg1_1
550 { CVT_95_addImmOperands, 1, CVT_95_Reg, 2, CVT_Done },
551 // Convert__Reg1_0
552 { CVT_95_Reg, 1, CVT_Done },
553 // Convert__Reg1_0__imm_95_255
554 { CVT_95_Reg, 1, CVT_imm_95_255, 0, CVT_Done },
555 // Convert__Reg1_1__Tie0_2_2__Reg1_2__imm_95_0
556 { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_Done },
557 // Convert__Reg1_0__Tie0_1_1__Reg1_2__imm_95_0
558 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_Done },
559 // Convert__Memri2_0__Reg1_1
560 { CVT_95_addMemriOperands, 1, CVT_95_Reg, 2, CVT_Done },
561};
562
563void AVRAsmParser::
564convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
565 const OperandVector &Operands) {
566 assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
567 const uint8_t *Converter = ConversionTable[Kind];
568 Inst.setOpcode(Opcode);
569 for (const uint8_t *p = Converter; *p; p += 2) {
570 unsigned OpIdx = *(p + 1);
571 switch (*p) {
572 default: llvm_unreachable("invalid conversion entry!");
573 case CVT_Reg:
574 static_cast<AVROperand &>(*Operands[OpIdx]).addRegOperands(Inst, 1);
575 break;
576 case CVT_Tied: {
577 assert(*(p + 1) < (size_t)(std::end(TiedAsmOperandTable) -
578 std::begin(TiedAsmOperandTable)) &&
579 "Tied operand not found");
580 unsigned TiedResOpnd = TiedAsmOperandTable[*(p + 1)][0];
581 if (TiedResOpnd != (uint8_t)-1)
582 Inst.addOperand(Inst.getOperand(TiedResOpnd));
583 break;
584 }
585 case CVT_95_Reg:
586 static_cast<AVROperand &>(*Operands[OpIdx]).addRegOperands(Inst, 1);
587 break;
588 case CVT_95_addImmOperands:
589 static_cast<AVROperand &>(*Operands[OpIdx]).addImmOperands(Inst, 1);
590 break;
591 case CVT_imm_95_0:
592 Inst.addOperand(MCOperand::createImm(0));
593 break;
594 case CVT_imm_95_5:
595 Inst.addOperand(MCOperand::createImm(5));
596 break;
597 case CVT_imm_95_7:
598 Inst.addOperand(MCOperand::createImm(7));
599 break;
600 case CVT_imm_95_6:
601 Inst.addOperand(MCOperand::createImm(6));
602 break;
603 case CVT_imm_95_3:
604 Inst.addOperand(MCOperand::createImm(3));
605 break;
606 case CVT_95_addImmCom8Operands:
607 static_cast<AVROperand &>(*Operands[OpIdx]).addImmCom8Operands(Inst, 1);
608 break;
609 case CVT_imm_95_2:
610 Inst.addOperand(MCOperand::createImm(2));
611 break;
612 case CVT_imm_95_4:
613 Inst.addOperand(MCOperand::createImm(4));
614 break;
615 case CVT_imm_95_1:
616 Inst.addOperand(MCOperand::createImm(1));
617 break;
618 case CVT_95_addMemriOperands:
619 static_cast<AVROperand &>(*Operands[OpIdx]).addMemriOperands(Inst, 2);
620 break;
621 case CVT_imm_95_255:
622 Inst.addOperand(MCOperand::createImm(255));
623 break;
624 }
625 }
626}
627
628void AVRAsmParser::
629convertToMapAndConstraints(unsigned Kind,
630 const OperandVector &Operands) {
631 assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
632 unsigned NumMCOperands = 0;
633 const uint8_t *Converter = ConversionTable[Kind];
634 for (const uint8_t *p = Converter; *p; p += 2) {
635 switch (*p) {
636 default: llvm_unreachable("invalid conversion entry!");
637 case CVT_Reg:
638 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
639 Operands[*(p + 1)]->setConstraint("r");
640 ++NumMCOperands;
641 break;
642 case CVT_Tied:
643 ++NumMCOperands;
644 break;
645 case CVT_95_Reg:
646 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
647 Operands[*(p + 1)]->setConstraint("r");
648 NumMCOperands += 1;
649 break;
650 case CVT_95_addImmOperands:
651 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
652 Operands[*(p + 1)]->setConstraint("m");
653 NumMCOperands += 1;
654 break;
655 case CVT_imm_95_0:
656 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
657 Operands[*(p + 1)]->setConstraint("");
658 ++NumMCOperands;
659 break;
660 case CVT_imm_95_5:
661 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
662 Operands[*(p + 1)]->setConstraint("");
663 ++NumMCOperands;
664 break;
665 case CVT_imm_95_7:
666 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
667 Operands[*(p + 1)]->setConstraint("");
668 ++NumMCOperands;
669 break;
670 case CVT_imm_95_6:
671 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
672 Operands[*(p + 1)]->setConstraint("");
673 ++NumMCOperands;
674 break;
675 case CVT_imm_95_3:
676 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
677 Operands[*(p + 1)]->setConstraint("");
678 ++NumMCOperands;
679 break;
680 case CVT_95_addImmCom8Operands:
681 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
682 Operands[*(p + 1)]->setConstraint("m");
683 NumMCOperands += 1;
684 break;
685 case CVT_imm_95_2:
686 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
687 Operands[*(p + 1)]->setConstraint("");
688 ++NumMCOperands;
689 break;
690 case CVT_imm_95_4:
691 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
692 Operands[*(p + 1)]->setConstraint("");
693 ++NumMCOperands;
694 break;
695 case CVT_imm_95_1:
696 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
697 Operands[*(p + 1)]->setConstraint("");
698 ++NumMCOperands;
699 break;
700 case CVT_95_addMemriOperands:
701 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
702 Operands[*(p + 1)]->setConstraint("m");
703 NumMCOperands += 2;
704 break;
705 case CVT_imm_95_255:
706 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
707 Operands[*(p + 1)]->setConstraint("");
708 ++NumMCOperands;
709 break;
710 }
711 }
712}
713
714namespace {
715
716/// MatchClassKind - The kinds of classes which participate in
717/// instruction matching.
718enum MatchClassKind {
719 InvalidMatchClass = 0,
720 OptionalMatchClass = 1,
721 MCK__43_, // '+'
722 MCK__MINUS_, // '-'
723 MCK_LAST_TOKEN = MCK__MINUS_,
724 MCK_Reg21, // derived register class
725 MCK_CCR, // register class 'CCR'
726 MCK_GPRSP, // register class 'GPRSP'
727 MCK_ZREG, // register class 'ZREG'
728 MCK_PTRDISPREGS, // register class 'PTRDISPREGS'
729 MCK_PTRREGS, // register class 'PTRREGS'
730 MCK_DREGSLD8lo, // register class 'DREGSLD8lo'
731 MCK_IWREGS, // register class 'IWREGS'
732 MCK_Reg16, // derived register class
733 MCK_Reg17, // derived register class
734 MCK_Reg15, // derived register class
735 MCK_DLDREGS, // register class 'DLDREGS'
736 MCK_DREGSlo, // register class 'DREGSlo'
737 MCK_LD8lo, // register class 'LD8lo'
738 MCK_Reg20, // derived register class
739 MCK_Reg19, // derived register class
740 MCK_Reg12, // derived register class
741 MCK_Reg13, // derived register class
742 MCK_DREGSMOVW, // register class 'DREGSMOVW'
743 MCK_GPR8lo, // register class 'GPR8lo'
744 MCK_LD8, // register class 'LD8'
745 MCK_DREGS, // register class 'DREGS'
746 MCK_GPR8, // register class 'GPR8'
747 MCK_LAST_REGISTER = MCK_GPR8,
748 MCK_Imm, // user defined class 'ImmAsmOperand'
749 MCK_Memri, // user defined class 'MemriAsmOperand'
750 MCK_ImmCom8, // user defined class 'imm_com8_asmoperand'
751 NumMatchClassKinds
752};
753
754} // end anonymous namespace
755
756static unsigned getDiagKindFromRegisterClass(MatchClassKind RegisterClass) {
757 return MCTargetAsmParser::Match_InvalidOperand;
758}
759
760static MatchClassKind matchTokenString(StringRef Name) {
761 switch (Name.size()) {
762 default: break;
763 case 1: // 2 strings to match.
764 switch (Name[0]) {
765 default: break;
766 case '+': // 1 string to match.
767 return MCK__43_; // "+"
768 case '-': // 1 string to match.
769 return MCK__MINUS_; // "-"
770 }
771 break;
772 }
773 return InvalidMatchClass;
774}
775
776/// isSubclass - Compute whether \p A is a subclass of \p B.
777static bool isSubclass(MatchClassKind A, MatchClassKind B) {
778 if (A == B)
779 return true;
780
781 [[maybe_unused]] static constexpr struct {
782 uint32_t Offset;
783 uint16_t Start;
784 uint16_t Length;
785 } Table[] = {
786 {0, 0, 0},
787 {0, 0, 0},
788 {0, 0, 0},
789 {0, 0, 0},
790 {0, 13, 13},
791 {13, 0, 0},
792 {13, 0, 0},
793 {13, 8, 18},
794 {31, 9, 17},
795 {48, 11, 15},
796 {63, 12, 14},
797 {77, 15, 11},
798 {88, 13, 13},
799 {101, 21, 5},
800 {106, 20, 6},
801 {112, 20, 6},
802 {118, 18, 8},
803 {126, 24, 3},
804 {129, 19, 7},
805 {136, 25, 1},
806 {137, 21, 5},
807 {142, 25, 1},
808 {143, 25, 1},
809 {144, 26, 1},
810 {145, 26, 1},
811 {146, 0, 0},
812 {146, 0, 0},
813 {146, 0, 0},
814 {146, 0, 0},
815 {146, 0, 0},
816 };
817
818 static constexpr uint8_t Data[] = {
819 0x41,
820 0x71,
821 0x11,
822 0xCE,
823 0x22,
824 0x9C,
825 0x11,
826 0xCE,
827 0x87,
828 0x33,
829 0x9C,
830 0x83,
831 0x31,
832 0x8E,
833 0xE7,
834 0x64,
835 0x83,
836 0xE3,
837 0x03,
838 };
839
840 auto &Entry = Table[A];
841 unsigned Idx = B - Entry.Start;
842 if (Idx >= Entry.Length)
843 return false;
844 Idx += Entry.Offset;
845 return (Data[Idx / 8] >> (Idx % 8)) & 1;
846}
847
848static unsigned validateOperandClass(MCParsedAsmOperand &GOp, MatchClassKind Kind) {
849 AVROperand &Operand = (AVROperand &)GOp;
850 if (Kind == InvalidMatchClass)
851 return MCTargetAsmParser::Match_InvalidOperand;
852
853 if (Operand.isToken() && Kind <= MCK_LAST_TOKEN)
854 return isSubclass(matchTokenString(Operand.getToken()), Kind) ?
855 MCTargetAsmParser::Match_Success :
856 MCTargetAsmParser::Match_InvalidOperand;
857
858 switch (Kind) {
859 default: break;
860 case MCK_Imm: {
861 DiagnosticPredicate DP(Operand.isImm());
862 if (DP.isMatch())
863 return MCTargetAsmParser::Match_Success;
864 break;
865 }
866 case MCK_Memri: {
867 DiagnosticPredicate DP(Operand.isMemri());
868 if (DP.isMatch())
869 return MCTargetAsmParser::Match_Success;
870 break;
871 }
872 case MCK_ImmCom8: {
873 DiagnosticPredicate DP(Operand.isImmCom8());
874 if (DP.isMatch())
875 return MCTargetAsmParser::Match_Success;
876 break;
877 }
878 } // end switch (Kind)
879
880 if (Operand.isReg()) {
881 static constexpr uint16_t Table[AVR::NUM_TARGET_REGS] = {
882 InvalidMatchClass,
883 MCK_GPRSP,
884 InvalidMatchClass,
885 InvalidMatchClass,
886 MCK_CCR,
887 MCK_GPR8lo,
888 MCK_GPR8lo,
889 MCK_GPR8lo,
890 MCK_GPR8lo,
891 MCK_GPR8lo,
892 MCK_GPR8lo,
893 MCK_GPR8lo,
894 MCK_GPR8lo,
895 MCK_GPR8lo,
896 MCK_GPR8lo,
897 MCK_GPR8lo,
898 MCK_GPR8lo,
899 MCK_GPR8lo,
900 MCK_GPR8lo,
901 MCK_GPR8lo,
902 MCK_GPR8lo,
903 MCK_LD8lo,
904 MCK_LD8lo,
905 MCK_LD8lo,
906 MCK_LD8lo,
907 MCK_LD8lo,
908 MCK_LD8lo,
909 MCK_LD8lo,
910 MCK_LD8lo,
911 MCK_LD8,
912 MCK_LD8,
913 MCK_LD8,
914 MCK_LD8,
915 MCK_LD8,
916 MCK_LD8,
917 MCK_LD8,
918 MCK_LD8,
919 MCK_DREGSlo,
920 MCK_DREGSlo,
921 MCK_DREGSlo,
922 MCK_DREGSlo,
923 MCK_DREGSlo,
924 MCK_Reg20,
925 MCK_DREGSlo,
926 MCK_Reg20,
927 MCK_DREGSlo,
928 MCK_Reg20,
929 MCK_DREGSlo,
930 MCK_Reg21,
931 MCK_DREGSLD8lo,
932 MCK_Reg16,
933 MCK_DREGSLD8lo,
934 MCK_Reg16,
935 MCK_DREGSLD8lo,
936 MCK_Reg16,
937 MCK_DREGSLD8lo,
938 MCK_Reg15,
939 MCK_IWREGS,
940 MCK_Reg12,
941 MCK_PTRREGS,
942 MCK_PTRDISPREGS,
943 MCK_ZREG,
944 };
945
946 MCRegister Reg = Operand.getReg();
947 MatchClassKind OpKind = Reg.isPhysical() ? (MatchClassKind)Table[Reg.id()] : InvalidMatchClass;
948 return isSubclass(OpKind, Kind) ? (unsigned)MCTargetAsmParser::Match_Success :
949 getDiagKindFromRegisterClass(Kind);
950 }
951
952 if (Kind > MCK_LAST_TOKEN && Kind <= MCK_LAST_REGISTER)
953 return getDiagKindFromRegisterClass(Kind);
954
955 return MCTargetAsmParser::Match_InvalidOperand;
956}
957
958#ifndef NDEBUG
959const char *getMatchClassName(MatchClassKind Kind) {
960 switch (Kind) {
961 case InvalidMatchClass: return "InvalidMatchClass";
962 case OptionalMatchClass: return "OptionalMatchClass";
963 case MCK__43_: return "MCK__43_";
964 case MCK__MINUS_: return "MCK__MINUS_";
965 case MCK_Reg21: return "MCK_Reg21";
966 case MCK_CCR: return "MCK_CCR";
967 case MCK_GPRSP: return "MCK_GPRSP";
968 case MCK_ZREG: return "MCK_ZREG";
969 case MCK_PTRDISPREGS: return "MCK_PTRDISPREGS";
970 case MCK_PTRREGS: return "MCK_PTRREGS";
971 case MCK_DREGSLD8lo: return "MCK_DREGSLD8lo";
972 case MCK_IWREGS: return "MCK_IWREGS";
973 case MCK_Reg16: return "MCK_Reg16";
974 case MCK_Reg17: return "MCK_Reg17";
975 case MCK_Reg15: return "MCK_Reg15";
976 case MCK_DLDREGS: return "MCK_DLDREGS";
977 case MCK_DREGSlo: return "MCK_DREGSlo";
978 case MCK_LD8lo: return "MCK_LD8lo";
979 case MCK_Reg20: return "MCK_Reg20";
980 case MCK_Reg19: return "MCK_Reg19";
981 case MCK_Reg12: return "MCK_Reg12";
982 case MCK_Reg13: return "MCK_Reg13";
983 case MCK_DREGSMOVW: return "MCK_DREGSMOVW";
984 case MCK_GPR8lo: return "MCK_GPR8lo";
985 case MCK_LD8: return "MCK_LD8";
986 case MCK_DREGS: return "MCK_DREGS";
987 case MCK_GPR8: return "MCK_GPR8";
988 case MCK_Imm: return "MCK_Imm";
989 case MCK_Memri: return "MCK_Memri";
990 case MCK_ImmCom8: return "MCK_ImmCom8";
991 case NumMatchClassKinds: return "NumMatchClassKinds";
992 }
993 llvm_unreachable("unhandled MatchClassKind!");
994}
995
996#endif // NDEBUG
997FeatureBitset AVRAsmParser::
998ComputeAvailableFeatures(const FeatureBitset &FB) const {
999 FeatureBitset Features;
1000 if (FB[AVR::FeatureSRAM])
1001 Features.set(Feature_HasSRAMBit);
1002 if (FB[AVR::FeatureJMPCALL])
1003 Features.set(Feature_HasJMPCALLBit);
1004 if (FB[AVR::FeatureIJMPCALL])
1005 Features.set(Feature_HasIJMPCALLBit);
1006 if (FB[AVR::FeatureEIJMPCALL])
1007 Features.set(Feature_HasEIJMPCALLBit);
1008 if (FB[AVR::FeatureADDSUBIW])
1009 Features.set(Feature_HasADDSUBIWBit);
1010 if (FB[AVR::FeatureSmallStack])
1011 Features.set(Feature_HasSmallStackBit);
1012 if (FB[AVR::FeatureMOVW])
1013 Features.set(Feature_HasMOVWBit);
1014 if (FB[AVR::FeatureLPM])
1015 Features.set(Feature_HasLPMBit);
1016 if (FB[AVR::FeatureLPMX])
1017 Features.set(Feature_HasLPMXBit);
1018 if (FB[AVR::FeatureELPM])
1019 Features.set(Feature_HasELPMBit);
1020 if (FB[AVR::FeatureELPMX])
1021 Features.set(Feature_HasELPMXBit);
1022 if (FB[AVR::FeatureSPM])
1023 Features.set(Feature_HasSPMBit);
1024 if (FB[AVR::FeatureSPMX])
1025 Features.set(Feature_HasSPMXBit);
1026 if (FB[AVR::FeatureDES])
1027 Features.set(Feature_HasDESBit);
1028 if (FB[AVR::FeatureRMW])
1029 Features.set(Feature_SupportsRMWBit);
1030 if (FB[AVR::FeatureMultiplication])
1031 Features.set(Feature_SupportsMultiplicationBit);
1032 if (FB[AVR::FeatureBREAK])
1033 Features.set(Feature_HasBREAKBit);
1034 if (FB[AVR::FeatureTinyEncoding])
1035 Features.set(Feature_HasTinyEncodingBit);
1036 if (!FB[AVR::FeatureTinyEncoding])
1037 Features.set(Feature_HasNonTinyEncodingBit);
1038 return Features;
1039}
1040
1041static bool checkAsmTiedOperandConstraints(const AVRAsmParser&AsmParser,
1042 unsigned Kind, const OperandVector &Operands,
1043 uint64_t &ErrorInfo) {
1044 assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
1045 const uint8_t *Converter = ConversionTable[Kind];
1046 for (const uint8_t *p = Converter; *p; p += 2) {
1047 switch (*p) {
1048 case CVT_Tied: {
1049 unsigned OpIdx = *(p + 1);
1050 assert(OpIdx < (size_t)(std::end(TiedAsmOperandTable) -
1051 std::begin(TiedAsmOperandTable)) &&
1052 "Tied operand not found");
1053 unsigned OpndNum1 = TiedAsmOperandTable[OpIdx][1];
1054 unsigned OpndNum2 = TiedAsmOperandTable[OpIdx][2];
1055 if (OpndNum1 != OpndNum2) {
1056 auto &SrcOp1 = Operands[OpndNum1];
1057 auto &SrcOp2 = Operands[OpndNum2];
1058 if (!AsmParser.areEqualRegs(*SrcOp1, *SrcOp2)) {
1059 ErrorInfo = OpndNum2;
1060 return false;
1061 }
1062 }
1063 break;
1064 }
1065 default:
1066 break;
1067 }
1068 }
1069 return true;
1070}
1071
1072static const char MnemonicTable[] =
1073 "\000\003adc\003add\004adiw\003and\004andi\003asr\004bclr\003bld\004brbc"
1074 "\004brbs\004brcc\004brcs\005break\004breq\004brge\004brhc\004brhs\004br"
1075 "id\004brie\004brlo\004brlt\004brmi\004brne\004brpl\004brsh\004brtc\004b"
1076 "rts\004brvc\004brvs\004bset\003bst\004call\003cbi\003cbr\003clc\003clh\003"
1077 "cli\003cln\003clr\003cls\003clt\003clv\003clz\003com\002cp\003cpc\003cp"
1078 "i\004cpse\003dec\003des\006eicall\005eijmp\004elpm\003eor\004fmul\005fm"
1079 "uls\006fmulsu\005icall\004ijmp\002in\003inc\003jmp\003lac\003las\003lat"
1080 "\002ld\003ldd\003ldi\003lds\003lpm\003lsl\003lsr\003mov\004movw\003mul\004"
1081 "muls\005mulsu\003neg\003nop\002or\003ori\003out\003pop\004push\005rcall"
1082 "\003ret\004reti\004rjmp\003rol\003ror\003sbc\004sbci\003sbi\004sbic\004"
1083 "sbis\004sbiw\003sbr\004sbrc\004sbrs\003sec\003seh\003sei\003sen\003ser\003"
1084 "ses\003set\003sev\003sez\005sleep\003spm\002st\003std\003sts\003sub\004"
1085 "subi\004swap\003tst\003wdr\003xch";
1086
1087// Feature bitsets.
1088enum : uint8_t {
1089 AMFBS_None,
1090 AMFBS_HasADDSUBIW,
1091 AMFBS_HasBREAK,
1092 AMFBS_HasDES,
1093 AMFBS_HasEIJMPCALL,
1094 AMFBS_HasELPM,
1095 AMFBS_HasELPMX,
1096 AMFBS_HasIJMPCALL,
1097 AMFBS_HasJMPCALL,
1098 AMFBS_HasLPM,
1099 AMFBS_HasLPMX,
1100 AMFBS_HasMOVW,
1101 AMFBS_HasSPM,
1102 AMFBS_HasSPMX,
1103 AMFBS_HasSRAM,
1104 AMFBS_SupportsMultiplication,
1105 AMFBS_SupportsRMW,
1106 AMFBS_HasSRAM_HasNonTinyEncoding,
1107 AMFBS_HasSRAM_HasTinyEncoding,
1108};
1109
1110static constexpr FeatureBitset FeatureBitsets[] = {
1111 {}, // AMFBS_None
1112 {Feature_HasADDSUBIWBit, },
1113 {Feature_HasBREAKBit, },
1114 {Feature_HasDESBit, },
1115 {Feature_HasEIJMPCALLBit, },
1116 {Feature_HasELPMBit, },
1117 {Feature_HasELPMXBit, },
1118 {Feature_HasIJMPCALLBit, },
1119 {Feature_HasJMPCALLBit, },
1120 {Feature_HasLPMBit, },
1121 {Feature_HasLPMXBit, },
1122 {Feature_HasMOVWBit, },
1123 {Feature_HasSPMBit, },
1124 {Feature_HasSPMXBit, },
1125 {Feature_HasSRAMBit, },
1126 {Feature_SupportsMultiplicationBit, },
1127 {Feature_SupportsRMWBit, },
1128 {Feature_HasSRAMBit, Feature_HasNonTinyEncodingBit, },
1129 {Feature_HasSRAMBit, Feature_HasTinyEncodingBit, },
1130};
1131
1132namespace {
1133 struct MatchEntry {
1134 uint16_t Mnemonic;
1135 uint16_t Opcode;
1136 uint8_t ConvertFn;
1137 uint8_t RequiredFeaturesIdx;
1138 uint8_t Classes[3];
1139 StringRef getMnemonic() const {
1140 return StringRef(MnemonicTable + Mnemonic + 1,
1141 MnemonicTable[Mnemonic]);
1142 }
1143 };
1144
1145 // Predicate for searching for an opcode.
1146 struct LessOpcode {
1147 bool operator()(const MatchEntry &LHS, StringRef RHS) {
1148 return LHS.getMnemonic() < RHS;
1149 }
1150 bool operator()(StringRef LHS, const MatchEntry &RHS) {
1151 return LHS < RHS.getMnemonic();
1152 }
1153 bool operator()(const MatchEntry &LHS, const MatchEntry &RHS) {
1154 return LHS.getMnemonic() < RHS.getMnemonic();
1155 }
1156 };
1157} // end anonymous namespace
1158
1159static const MatchEntry MatchTable0[] = {
1160 { 1 /* adc */, AVR::ADCRdRr, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_None, { MCK_GPR8, MCK_GPR8 }, },
1161 { 5 /* add */, AVR::ADDRdRr, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_None, { MCK_GPR8, MCK_GPR8 }, },
1162 { 9 /* adiw */, AVR::ADIWRdK, Convert__Reg1_0__Tie0_1_1__Imm1_1, AMFBS_HasADDSUBIW, { MCK_IWREGS, MCK_Imm }, },
1163 { 14 /* and */, AVR::ANDRdRr, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_None, { MCK_GPR8, MCK_GPR8 }, },
1164 { 18 /* andi */, AVR::ANDIRdK, Convert__Reg1_0__Tie0_1_1__Imm1_1, AMFBS_None, { MCK_LD8, MCK_Imm }, },
1165 { 23 /* asr */, AVR::ASRRd, Convert__Reg1_0__Tie0_1_1, AMFBS_None, { MCK_GPR8 }, },
1166 { 27 /* bclr */, AVR::BCLRs, Convert__Imm1_0, AMFBS_None, { MCK_Imm }, },
1167 { 32 /* bld */, AVR::BLD, Convert__Reg1_0__Tie0_1_1__Imm1_1, AMFBS_None, { MCK_GPR8, MCK_Imm }, },
1168 { 36 /* brbc */, AVR::BRBCsk, Convert__Imm1_0__Imm1_1, AMFBS_None, { MCK_Imm, MCK_Imm }, },
1169 { 41 /* brbs */, AVR::BRBSsk, Convert__Imm1_0__Imm1_1, AMFBS_None, { MCK_Imm, MCK_Imm }, },
1170 { 46 /* brcc */, AVR::BRBCsk, Convert__imm_95_0__Imm1_0, AMFBS_None, { MCK_Imm }, },
1171 { 51 /* brcs */, AVR::BRBSsk, Convert__imm_95_0__Imm1_0, AMFBS_None, { MCK_Imm }, },
1172 { 56 /* break */, AVR::BREAK, Convert_NoOperands, AMFBS_HasBREAK, { }, },
1173 { 62 /* breq */, AVR::BREQk, Convert__Imm1_0, AMFBS_None, { MCK_Imm }, },
1174 { 67 /* brge */, AVR::BRGEk, Convert__Imm1_0, AMFBS_None, { MCK_Imm }, },
1175 { 72 /* brhc */, AVR::BRBCsk, Convert__imm_95_5__Imm1_0, AMFBS_None, { MCK_Imm }, },
1176 { 77 /* brhs */, AVR::BRBSsk, Convert__imm_95_5__Imm1_0, AMFBS_None, { MCK_Imm }, },
1177 { 82 /* brid */, AVR::BRBCsk, Convert__imm_95_7__Imm1_0, AMFBS_None, { MCK_Imm }, },
1178 { 87 /* brie */, AVR::BRBSsk, Convert__imm_95_7__Imm1_0, AMFBS_None, { MCK_Imm }, },
1179 { 92 /* brlo */, AVR::BRLOk, Convert__Imm1_0, AMFBS_None, { MCK_Imm }, },
1180 { 97 /* brlt */, AVR::BRLTk, Convert__Imm1_0, AMFBS_None, { MCK_Imm }, },
1181 { 102 /* brmi */, AVR::BRMIk, Convert__Imm1_0, AMFBS_None, { MCK_Imm }, },
1182 { 107 /* brne */, AVR::BRNEk, Convert__Imm1_0, AMFBS_None, { MCK_Imm }, },
1183 { 112 /* brpl */, AVR::BRPLk, Convert__Imm1_0, AMFBS_None, { MCK_Imm }, },
1184 { 117 /* brsh */, AVR::BRSHk, Convert__Imm1_0, AMFBS_None, { MCK_Imm }, },
1185 { 122 /* brtc */, AVR::BRBCsk, Convert__imm_95_6__Imm1_0, AMFBS_None, { MCK_Imm }, },
1186 { 127 /* brts */, AVR::BRBSsk, Convert__imm_95_6__Imm1_0, AMFBS_None, { MCK_Imm }, },
1187 { 132 /* brvc */, AVR::BRBCsk, Convert__imm_95_3__Imm1_0, AMFBS_None, { MCK_Imm }, },
1188 { 137 /* brvs */, AVR::BRBSsk, Convert__imm_95_3__Imm1_0, AMFBS_None, { MCK_Imm }, },
1189 { 142 /* bset */, AVR::BSETs, Convert__Imm1_0, AMFBS_None, { MCK_Imm }, },
1190 { 147 /* bst */, AVR::BST, Convert__Reg1_0__Imm1_1, AMFBS_None, { MCK_GPR8, MCK_Imm }, },
1191 { 151 /* call */, AVR::CALLk, Convert__Imm1_0, AMFBS_HasJMPCALL, { MCK_Imm }, },
1192 { 156 /* cbi */, AVR::CBIAb, Convert__Imm1_0__Imm1_1, AMFBS_None, { MCK_Imm, MCK_Imm }, },
1193 { 160 /* cbr */, AVR::ANDIRdK, Convert__Reg1_0__Tie0_1_1__ImmCom81_1, AMFBS_None, { MCK_LD8, MCK_ImmCom8 }, },
1194 { 164 /* clc */, AVR::BCLRs, Convert__imm_95_0, AMFBS_None, { }, },
1195 { 168 /* clh */, AVR::BCLRs, Convert__imm_95_5, AMFBS_None, { }, },
1196 { 172 /* cli */, AVR::BCLRs, Convert__imm_95_7, AMFBS_None, { }, },
1197 { 176 /* cln */, AVR::BCLRs, Convert__imm_95_2, AMFBS_None, { }, },
1198 { 180 /* clr */, AVR::EORRdRr, Convert__Reg1_0__Tie0_1_1__Reg1_0, AMFBS_None, { MCK_GPR8 }, },
1199 { 184 /* cls */, AVR::BCLRs, Convert__imm_95_4, AMFBS_None, { }, },
1200 { 188 /* clt */, AVR::BCLRs, Convert__imm_95_6, AMFBS_None, { }, },
1201 { 192 /* clv */, AVR::BCLRs, Convert__imm_95_3, AMFBS_None, { }, },
1202 { 196 /* clz */, AVR::BCLRs, Convert__imm_95_1, AMFBS_None, { }, },
1203 { 200 /* com */, AVR::COMRd, Convert__Reg1_0__Tie0_1_1, AMFBS_None, { MCK_GPR8 }, },
1204 { 204 /* cp */, AVR::CPRdRr, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_GPR8, MCK_GPR8 }, },
1205 { 207 /* cpc */, AVR::CPCRdRr, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_GPR8, MCK_GPR8 }, },
1206 { 211 /* cpi */, AVR::CPIRdK, Convert__Reg1_0__Imm1_1, AMFBS_None, { MCK_LD8, MCK_Imm }, },
1207 { 215 /* cpse */, AVR::CPSE, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_GPR8, MCK_GPR8 }, },
1208 { 220 /* dec */, AVR::DECRd, Convert__Reg1_0__Tie0_1_1, AMFBS_None, { MCK_GPR8 }, },
1209 { 224 /* des */, AVR::DESK, Convert__Imm1_0, AMFBS_HasDES, { MCK_Imm }, },
1210 { 228 /* eicall */, AVR::EICALL, Convert_NoOperands, AMFBS_HasEIJMPCALL, { }, },
1211 { 235 /* eijmp */, AVR::EIJMP, Convert_NoOperands, AMFBS_HasEIJMPCALL, { }, },
1212 { 241 /* elpm */, AVR::ELPM, Convert_NoOperands, AMFBS_HasELPM, { }, },
1213 { 241 /* elpm */, AVR::ELPMRdZ, Convert__Reg1_0__Reg1_1, AMFBS_HasELPMX, { MCK_GPR8, MCK_ZREG }, },
1214 { 241 /* elpm */, AVR::ELPMRdZPi, Convert__Reg1_0__Reg1_1, AMFBS_HasELPMX, { MCK_GPR8, MCK_ZREG, MCK__43_ }, },
1215 { 246 /* eor */, AVR::EORRdRr, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_None, { MCK_GPR8, MCK_GPR8 }, },
1216 { 250 /* fmul */, AVR::FMUL, Convert__Reg1_0__Reg1_1, AMFBS_SupportsMultiplication, { MCK_LD8lo, MCK_LD8lo }, },
1217 { 255 /* fmuls */, AVR::FMULS, Convert__Reg1_0__Reg1_1, AMFBS_SupportsMultiplication, { MCK_LD8lo, MCK_LD8lo }, },
1218 { 261 /* fmulsu */, AVR::FMULSU, Convert__Reg1_0__Reg1_1, AMFBS_SupportsMultiplication, { MCK_LD8lo, MCK_LD8lo }, },
1219 { 268 /* icall */, AVR::ICALL, Convert_NoOperands, AMFBS_HasIJMPCALL, { }, },
1220 { 274 /* ijmp */, AVR::IJMP, Convert_NoOperands, AMFBS_HasIJMPCALL, { }, },
1221 { 279 /* in */, AVR::INRdA, Convert__Reg1_0__Imm1_1, AMFBS_None, { MCK_GPR8, MCK_Imm }, },
1222 { 282 /* inc */, AVR::INCRd, Convert__Reg1_0__Tie0_1_1, AMFBS_None, { MCK_GPR8 }, },
1223 { 286 /* jmp */, AVR::JMPk, Convert__Imm1_0, AMFBS_HasJMPCALL, { MCK_Imm }, },
1224 { 290 /* lac */, AVR::LACZRd, Convert__Reg1_1__Reg1_0, AMFBS_SupportsRMW, { MCK_ZREG, MCK_GPR8 }, },
1225 { 294 /* las */, AVR::LASZRd, Convert__Reg1_1__Reg1_0, AMFBS_SupportsRMW, { MCK_ZREG, MCK_GPR8 }, },
1226 { 298 /* lat */, AVR::LATZRd, Convert__Reg1_1__Reg1_0, AMFBS_SupportsRMW, { MCK_ZREG, MCK_GPR8 }, },
1227 { 302 /* ld */, AVR::LDRdPtr, Convert__Reg1_0__Reg1_1, AMFBS_HasSRAM, { MCK_GPR8, MCK_PTRREGS }, },
1228 { 302 /* ld */, AVR::LDRdPtrPd, Convert__Reg1_0__Reg1_2__Tie1_3_3, AMFBS_HasSRAM, { MCK_GPR8, MCK__MINUS_, MCK_PTRREGS }, },
1229 { 302 /* ld */, AVR::LDRdPtrPi, Convert__Reg1_0__Reg1_1__Tie1_2_2, AMFBS_HasSRAM, { MCK_GPR8, MCK_PTRREGS, MCK__43_ }, },
1230 { 305 /* ldd */, AVR::LDDRdPtrQ, Convert__Reg1_0__Memri2_1, AMFBS_HasSRAM_HasNonTinyEncoding, { MCK_GPR8, MCK_Memri }, },
1231 { 309 /* ldi */, AVR::LDIRdK, Convert__Reg1_0__Imm1_1, AMFBS_None, { MCK_LD8, MCK_Imm }, },
1232 { 313 /* lds */, AVR::LDSRdKTiny, Convert__Reg1_0__Imm1_1, AMFBS_HasSRAM_HasTinyEncoding, { MCK_LD8, MCK_Imm }, },
1233 { 313 /* lds */, AVR::LDSRdK, Convert__Reg1_0__Imm1_1, AMFBS_HasSRAM_HasNonTinyEncoding, { MCK_GPR8, MCK_Imm }, },
1234 { 317 /* lpm */, AVR::LPM, Convert_NoOperands, AMFBS_HasLPM, { }, },
1235 { 317 /* lpm */, AVR::LPMRdZ, Convert__Reg1_0__Reg1_1, AMFBS_HasLPMX, { MCK_GPR8, MCK_ZREG }, },
1236 { 317 /* lpm */, AVR::LPMRdZPi, Convert__Reg1_0__Reg1_1, AMFBS_HasLPMX, { MCK_GPR8, MCK_ZREG, MCK__43_ }, },
1237 { 321 /* lsl */, AVR::ADDRdRr, Convert__Reg1_0__Tie0_1_1__Reg1_0, AMFBS_None, { MCK_GPR8 }, },
1238 { 325 /* lsr */, AVR::LSRRd, Convert__Reg1_0__Tie0_1_1, AMFBS_None, { MCK_GPR8 }, },
1239 { 329 /* mov */, AVR::MOVRdRr, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_GPR8, MCK_GPR8 }, },
1240 { 333 /* movw */, AVR::MOVWRdRr, Convert__Reg1_0__Reg1_1, AMFBS_HasMOVW, { MCK_DREGS, MCK_DREGS }, },
1241 { 338 /* mul */, AVR::MULRdRr, Convert__Reg1_0__Reg1_1, AMFBS_SupportsMultiplication, { MCK_GPR8, MCK_GPR8 }, },
1242 { 342 /* muls */, AVR::MULSRdRr, Convert__Reg1_0__Reg1_1, AMFBS_SupportsMultiplication, { MCK_LD8, MCK_LD8 }, },
1243 { 347 /* mulsu */, AVR::MULSURdRr, Convert__Reg1_0__Reg1_1, AMFBS_SupportsMultiplication, { MCK_LD8lo, MCK_LD8lo }, },
1244 { 353 /* neg */, AVR::NEGRd, Convert__Reg1_0__Tie0_1_1, AMFBS_None, { MCK_GPR8 }, },
1245 { 357 /* nop */, AVR::NOP, Convert_NoOperands, AMFBS_None, { }, },
1246 { 361 /* or */, AVR::ORRdRr, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_None, { MCK_GPR8, MCK_GPR8 }, },
1247 { 364 /* ori */, AVR::ORIRdK, Convert__Reg1_0__Tie0_1_1__Imm1_1, AMFBS_None, { MCK_LD8, MCK_Imm }, },
1248 { 368 /* out */, AVR::OUTARr, Convert__Imm1_0__Reg1_1, AMFBS_None, { MCK_Imm, MCK_GPR8 }, },
1249 { 372 /* pop */, AVR::POPRd, Convert__Reg1_0, AMFBS_HasSRAM, { MCK_GPR8 }, },
1250 { 376 /* push */, AVR::PUSHRr, Convert__Reg1_0, AMFBS_HasSRAM, { MCK_GPR8 }, },
1251 { 381 /* rcall */, AVR::RCALLk, Convert__Imm1_0, AMFBS_None, { MCK_Imm }, },
1252 { 387 /* ret */, AVR::RET, Convert_NoOperands, AMFBS_None, { }, },
1253 { 391 /* reti */, AVR::RETI, Convert_NoOperands, AMFBS_None, { }, },
1254 { 396 /* rjmp */, AVR::RJMPk, Convert__Imm1_0, AMFBS_None, { MCK_Imm }, },
1255 { 401 /* rol */, AVR::ADCRdRr, Convert__Reg1_0__Tie0_1_1__Reg1_0, AMFBS_None, { MCK_GPR8 }, },
1256 { 405 /* ror */, AVR::RORRd, Convert__Reg1_0__Tie0_1_1, AMFBS_None, { MCK_GPR8 }, },
1257 { 409 /* sbc */, AVR::SBCRdRr, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_None, { MCK_GPR8, MCK_GPR8 }, },
1258 { 413 /* sbci */, AVR::SBCIRdK, Convert__Reg1_0__Tie0_1_1__Imm1_1, AMFBS_None, { MCK_LD8, MCK_Imm }, },
1259 { 418 /* sbi */, AVR::SBIAb, Convert__Imm1_0__Imm1_1, AMFBS_None, { MCK_Imm, MCK_Imm }, },
1260 { 422 /* sbic */, AVR::SBICAb, Convert__Imm1_0__Imm1_1, AMFBS_None, { MCK_Imm, MCK_Imm }, },
1261 { 427 /* sbis */, AVR::SBISAb, Convert__Imm1_0__Imm1_1, AMFBS_None, { MCK_Imm, MCK_Imm }, },
1262 { 432 /* sbiw */, AVR::SBIWRdK, Convert__Reg1_0__Tie0_1_1__Imm1_1, AMFBS_HasADDSUBIW, { MCK_IWREGS, MCK_Imm }, },
1263 { 437 /* sbr */, AVR::ORIRdK, Convert__Reg1_0__Tie0_1_1__Imm1_1, AMFBS_None, { MCK_LD8, MCK_Imm }, },
1264 { 441 /* sbrc */, AVR::SBRCRrB, Convert__Reg1_0__Imm1_1, AMFBS_None, { MCK_GPR8, MCK_Imm }, },
1265 { 446 /* sbrs */, AVR::SBRSRrB, Convert__Reg1_0__Imm1_1, AMFBS_None, { MCK_GPR8, MCK_Imm }, },
1266 { 451 /* sec */, AVR::BSETs, Convert__imm_95_0, AMFBS_None, { }, },
1267 { 455 /* seh */, AVR::BSETs, Convert__imm_95_5, AMFBS_None, { }, },
1268 { 459 /* sei */, AVR::BSETs, Convert__imm_95_7, AMFBS_None, { }, },
1269 { 463 /* sen */, AVR::BSETs, Convert__imm_95_2, AMFBS_None, { }, },
1270 { 467 /* ser */, AVR::LDIRdK, Convert__Reg1_0__imm_95_255, AMFBS_None, { MCK_LD8 }, },
1271 { 471 /* ses */, AVR::BSETs, Convert__imm_95_4, AMFBS_None, { }, },
1272 { 475 /* set */, AVR::BSETs, Convert__imm_95_6, AMFBS_None, { }, },
1273 { 479 /* sev */, AVR::BSETs, Convert__imm_95_3, AMFBS_None, { }, },
1274 { 483 /* sez */, AVR::BSETs, Convert__imm_95_1, AMFBS_None, { }, },
1275 { 487 /* sleep */, AVR::SLEEP, Convert_NoOperands, AMFBS_None, { }, },
1276 { 493 /* spm */, AVR::SPM, Convert_NoOperands, AMFBS_HasSPM, { }, },
1277 { 493 /* spm */, AVR::SPMZPi, Convert__Reg1_0, AMFBS_HasSPMX, { MCK_ZREG, MCK__43_ }, },
1278 { 497 /* st */, AVR::STPtrRr, Convert__Reg1_0__Reg1_1, AMFBS_HasSRAM, { MCK_PTRREGS, MCK_GPR8 }, },
1279 { 497 /* st */, AVR::STPtrPdRr, Convert__Reg1_1__Tie0_2_2__Reg1_2__imm_95_0, AMFBS_HasSRAM, { MCK__MINUS_, MCK_PTRREGS, MCK_GPR8 }, },
1280 { 497 /* st */, AVR::STPtrPiRr, Convert__Reg1_0__Tie0_1_1__Reg1_2__imm_95_0, AMFBS_HasSRAM, { MCK_PTRREGS, MCK__43_, MCK_GPR8 }, },
1281 { 500 /* std */, AVR::STDPtrQRr, Convert__Memri2_0__Reg1_1, AMFBS_HasSRAM_HasNonTinyEncoding, { MCK_Memri, MCK_GPR8 }, },
1282 { 504 /* sts */, AVR::STSKRrTiny, Convert__Imm1_0__Reg1_1, AMFBS_HasSRAM_HasTinyEncoding, { MCK_Imm, MCK_LD8 }, },
1283 { 504 /* sts */, AVR::STSKRr, Convert__Imm1_0__Reg1_1, AMFBS_HasSRAM_HasNonTinyEncoding, { MCK_Imm, MCK_GPR8 }, },
1284 { 508 /* sub */, AVR::SUBRdRr, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_None, { MCK_GPR8, MCK_GPR8 }, },
1285 { 512 /* subi */, AVR::SUBIRdK, Convert__Reg1_0__Tie0_1_1__Imm1_1, AMFBS_None, { MCK_LD8, MCK_Imm }, },
1286 { 517 /* swap */, AVR::SWAPRd, Convert__Reg1_0__Tie0_1_1, AMFBS_None, { MCK_GPR8 }, },
1287 { 522 /* tst */, AVR::ANDRdRr, Convert__Reg1_0__Tie0_1_1__Reg1_0, AMFBS_None, { MCK_GPR8 }, },
1288 { 526 /* wdr */, AVR::WDR, Convert_NoOperands, AMFBS_None, { }, },
1289 { 530 /* xch */, AVR::XCHZRd, Convert__Reg1_1__Reg1_0, AMFBS_SupportsRMW, { MCK_ZREG, MCK_GPR8 }, },
1290};
1291
1292#include "llvm/Support/Debug.h"
1293#include "llvm/Support/Format.h"
1294
1295unsigned AVRAsmParser::
1296MatchInstructionImpl(const OperandVector &Operands,
1297 MCInst &Inst,
1298 uint64_t &ErrorInfo,
1299 FeatureBitset &MissingFeatures,
1300 bool matchingInlineAsm, unsigned VariantID) {
1301 // Eliminate obvious mismatches.
1302 if (Operands.size() > 4) {
1303 ErrorInfo = 4;
1304 return Match_InvalidOperand;
1305 }
1306
1307 // Get the current feature set.
1308 const FeatureBitset &AvailableFeatures = getAvailableFeatures();
1309
1310 // Get the instruction mnemonic, which is the first token.
1311 StringRef Mnemonic = ((AVROperand &)*Operands[0]).getToken();
1312
1313 // Some state to try to produce better error messages.
1314 bool HadMatchOtherThanFeatures = false;
1315 bool HadMatchOtherThanPredicate = false;
1316 unsigned RetCode = Match_InvalidOperand;
1317 MissingFeatures.set();
1318 // Set ErrorInfo to the operand that mismatches if it is
1319 // wrong for all instances of the instruction.
1320 ErrorInfo = ~0ULL;
1321 // Find the appropriate table for this asm variant.
1322 const MatchEntry *Start, *End;
1323 switch (VariantID) {
1324 default: llvm_unreachable("invalid variant!");
1325 case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break;
1326 }
1327 // Search the table.
1328 auto MnemonicRange = std::equal_range(Start, End, Mnemonic, LessOpcode());
1329
1330 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "AsmMatcher: found " <<
1331 std::distance(MnemonicRange.first, MnemonicRange.second) <<
1332 " encodings with mnemonic '" << Mnemonic << "'\n");
1333
1334 // Return a more specific error code if no mnemonics match.
1335 if (MnemonicRange.first == MnemonicRange.second)
1336 return Match_MnemonicFail;
1337
1338 for (const MatchEntry *it = MnemonicRange.first, *ie = MnemonicRange.second;
1339 it != ie; ++it) {
1340 const FeatureBitset &RequiredFeatures = FeatureBitsets[it->RequiredFeaturesIdx];
1341 bool HasRequiredFeatures =
1342 (AvailableFeatures & RequiredFeatures) == RequiredFeatures;
1343 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Trying to match opcode "
1344 << MII.getName(it->Opcode) << "\n");
1345 // equal_range guarantees that instruction mnemonic matches.
1346 assert(Mnemonic == it->getMnemonic());
1347 bool OperandsValid = true;
1348 for (unsigned FormalIdx = 0, ActualIdx = 1; FormalIdx != 3; ++FormalIdx) {
1349 auto Formal = static_cast<MatchClassKind>(it->Classes[FormalIdx]);
1350 DEBUG_WITH_TYPE("asm-matcher",
1351 dbgs() << " Matching formal operand class " << getMatchClassName(Formal)
1352 << " against actual operand at index " << ActualIdx);
1353 if (ActualIdx < Operands.size())
1354 DEBUG_WITH_TYPE("asm-matcher", dbgs() << " (";
1355 Operands[ActualIdx]->print(dbgs(), *getContext().getAsmInfo()); dbgs() << "): ");
1356 else
1357 DEBUG_WITH_TYPE("asm-matcher", dbgs() << ": ");
1358 if (ActualIdx >= Operands.size()) {
1359 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "actual operand index out of range\n");
1360 if (Formal == InvalidMatchClass) {
1361 break;
1362 }
1363 if (isSubclass(Formal, OptionalMatchClass)) {
1364 continue;
1365 }
1366 OperandsValid = false;
1367 ErrorInfo = ActualIdx;
1368 break;
1369 }
1370 MCParsedAsmOperand &Actual = *Operands[ActualIdx];
1371 unsigned Diag = validateOperandClass(Actual, Formal);
1372 if (Diag == Match_Success) {
1373 DEBUG_WITH_TYPE("asm-matcher",
1374 dbgs() << "match success using generic matcher\n");
1375 ++ActualIdx;
1376 continue;
1377 }
1378 // If the generic handler indicates an invalid operand
1379 // failure, check for a special case.
1380 if (Diag != Match_Success) {
1381 unsigned TargetDiag = validateTargetOperandClass(Actual, Formal);
1382 if (TargetDiag == Match_Success) {
1383 DEBUG_WITH_TYPE("asm-matcher",
1384 dbgs() << "match success using target matcher\n");
1385 ++ActualIdx;
1386 continue;
1387 }
1388 // If the target matcher returned a specific error code use
1389 // that, else use the one from the generic matcher.
1390 if (TargetDiag != Match_InvalidOperand && HasRequiredFeatures)
1391 Diag = TargetDiag;
1392 }
1393 // If current formal operand wasn't matched and it is optional
1394 // then try to match next formal operand
1395 if (Diag == Match_InvalidOperand && isSubclass(Formal, OptionalMatchClass)) {
1396 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "ignoring optional operand\n");
1397 continue;
1398 }
1399 // If this operand is broken for all of the instances of this
1400 // mnemonic, keep track of it so we can report loc info.
1401 // If we already had a match that only failed due to a
1402 // target predicate, that diagnostic is preferred.
1403 if (!HadMatchOtherThanPredicate &&
1404 (it == MnemonicRange.first || ErrorInfo <= ActualIdx)) {
1405 if (HasRequiredFeatures && (ErrorInfo != ActualIdx || Diag != Match_InvalidOperand))
1406 RetCode = Diag;
1407 ErrorInfo = ActualIdx;
1408 }
1409 // Otherwise, just reject this instance of the mnemonic.
1410 OperandsValid = false;
1411 break;
1412 }
1413
1414 if (!OperandsValid) {
1415 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Opcode result: multiple "
1416 "operand mismatches, ignoring "
1417 "this opcode\n");
1418 continue;
1419 }
1420 if (!HasRequiredFeatures) {
1421 HadMatchOtherThanFeatures = true;
1422 FeatureBitset NewMissingFeatures = RequiredFeatures & ~AvailableFeatures;
1423 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Missing target features:";
1424 for (unsigned I = 0, E = NewMissingFeatures.size(); I != E; ++I)
1425 if (NewMissingFeatures[I])
1426 dbgs() << ' ' << I;
1427 dbgs() << "\n");
1428 if (NewMissingFeatures.count() <=
1429 MissingFeatures.count())
1430 MissingFeatures = NewMissingFeatures;
1431 continue;
1432 }
1433
1434 Inst.clear();
1435
1436 Inst.setOpcode(it->Opcode);
1437 // We have a potential match but have not rendered the operands.
1438 // Check the target predicate to handle any context sensitive
1439 // constraints.
1440 // For example, Ties that are referenced multiple times must be
1441 // checked here to ensure the input is the same for each match
1442 // constraints. If we leave it any later the ties will have been
1443 // canonicalized
1444 unsigned MatchResult;
1445 if ((MatchResult = checkEarlyTargetMatchPredicate(Inst, Operands)) != Match_Success) {
1446 Inst.clear();
1447 DEBUG_WITH_TYPE(
1448 "asm-matcher",
1449 dbgs() << "Early target match predicate failed with diag code "
1450 << MatchResult << "\n");
1451 RetCode = MatchResult;
1452 HadMatchOtherThanPredicate = true;
1453 continue;
1454 }
1455
1456 if (matchingInlineAsm) {
1457 convertToMapAndConstraints(it->ConvertFn, Operands);
1458 if (!checkAsmTiedOperandConstraints(*this, it->ConvertFn, Operands,
1459 ErrorInfo))
1460 return Match_InvalidTiedOperand;
1461
1462 return Match_Success;
1463 }
1464
1465 // We have selected a definite instruction, convert the parsed
1466 // operands into the appropriate MCInst.
1467 convertToMCInst(it->ConvertFn, Inst, it->Opcode, Operands);
1468
1469 // We have a potential match. Check the target predicate to
1470 // handle any context sensitive constraints.
1471 if ((MatchResult = checkTargetMatchPredicate(Inst)) != Match_Success) {
1472 DEBUG_WITH_TYPE("asm-matcher",
1473 dbgs() << "Target match predicate failed with diag code "
1474 << MatchResult << "\n");
1475 Inst.clear();
1476 RetCode = MatchResult;
1477 HadMatchOtherThanPredicate = true;
1478 continue;
1479 }
1480
1481 if (!checkAsmTiedOperandConstraints(*this, it->ConvertFn, Operands,
1482 ErrorInfo))
1483 return Match_InvalidTiedOperand;
1484
1485 DEBUG_WITH_TYPE(
1486 "asm-matcher",
1487 dbgs() << "Opcode result: complete match, selecting this opcode\n");
1488 return Match_Success;
1489 }
1490
1491 // Okay, we had no match. Try to return a useful error code.
1492 if (HadMatchOtherThanPredicate || !HadMatchOtherThanFeatures)
1493 return RetCode;
1494
1495 ErrorInfo = 0;
1496 return Match_MissingFeature;
1497}
1498
1499namespace {
1500 struct OperandMatchEntry {
1501 uint16_t Mnemonic;
1502 uint8_t OperandMask;
1503 uint8_t Class;
1504 uint8_t RequiredFeaturesIdx;
1505
1506 StringRef getMnemonic() const {
1507 return StringRef(MnemonicTable + Mnemonic + 1,
1508 MnemonicTable[Mnemonic]);
1509 }
1510 };
1511
1512 // Predicate for searching for an opcode.
1513 struct LessOpcodeOperand {
1514 bool operator()(const OperandMatchEntry &LHS, StringRef RHS) {
1515 return LHS.getMnemonic() < RHS;
1516 }
1517 bool operator()(StringRef LHS, const OperandMatchEntry &RHS) {
1518 return LHS < RHS.getMnemonic();
1519 }
1520 bool operator()(const OperandMatchEntry &LHS, const OperandMatchEntry &RHS) {
1521 return LHS.getMnemonic() < RHS.getMnemonic();
1522 }
1523 };
1524} // end anonymous namespace
1525
1526static const OperandMatchEntry OperandMatchTable[2] = {
1527 /* Operand List Mnemonic, Mask, Operand Class, Features */
1528 { 305 /* ldd */, 2 /* 1 */, MCK_Memri, AMFBS_HasSRAM_HasNonTinyEncoding },
1529 { 500 /* std */, 1 /* 0 */, MCK_Memri, AMFBS_HasSRAM_HasNonTinyEncoding },
1530};
1531
1532ParseStatus AVRAsmParser::
1533tryCustomParseOperand(OperandVector &Operands,
1534 unsigned MCK) {
1535
1536 switch(MCK) {
1537 case MCK_Memri:
1538 return parseMemriOperand(Operands);
1539 default:
1540 return ParseStatus::NoMatch;
1541 }
1542 return ParseStatus::NoMatch;
1543}
1544
1545ParseStatus AVRAsmParser::
1546MatchOperandParserImpl(OperandVector &Operands,
1547 StringRef Mnemonic,
1548 bool ParseForAllFeatures) {
1549 // Get the current feature set.
1550 const FeatureBitset &AvailableFeatures = getAvailableFeatures();
1551
1552 // Get the next operand index.
1553 unsigned NextOpNum = Operands.size() - 1;
1554 // Search the table.
1555 auto MnemonicRange =
1556 std::equal_range(std::begin(OperandMatchTable), std::end(OperandMatchTable),
1557 Mnemonic, LessOpcodeOperand());
1558
1559 if (MnemonicRange.first == MnemonicRange.second)
1560 return ParseStatus::NoMatch;
1561
1562 for (const OperandMatchEntry *it = MnemonicRange.first,
1563 *ie = MnemonicRange.second; it != ie; ++it) {
1564 // equal_range guarantees that instruction mnemonic matches.
1565 assert(Mnemonic == it->getMnemonic());
1566
1567 // check if the available features match
1568 const FeatureBitset &RequiredFeatures = FeatureBitsets[it->RequiredFeaturesIdx];
1569 if (!ParseForAllFeatures && (AvailableFeatures & RequiredFeatures) != RequiredFeatures)
1570 continue;
1571
1572 // check if the operand in question has a custom parser.
1573 if (!(it->OperandMask & (1 << NextOpNum)))
1574 continue;
1575
1576 // call custom parse method to handle the operand
1577 ParseStatus Result = tryCustomParseOperand(Operands, it->Class);
1578 if (!Result.isNoMatch())
1579 return Result;
1580 }
1581
1582 // Okay, we had no match.
1583 return ParseStatus::NoMatch;
1584}
1585
1586#endif // GET_MATCHER_IMPLEMENTATION
1587
1588
1589#ifdef GET_MNEMONIC_SPELL_CHECKER
1590#undef GET_MNEMONIC_SPELL_CHECKER
1591
1592static std::string AVRMnemonicSpellCheck(StringRef S, const FeatureBitset &FBS, unsigned VariantID) {
1593 const unsigned MaxEditDist = 2;
1594 std::vector<StringRef> Candidates;
1595 StringRef Prev = "";
1596
1597 // Find the appropriate table for this asm variant.
1598 const MatchEntry *Start, *End;
1599 switch (VariantID) {
1600 default: llvm_unreachable("invalid variant!");
1601 case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break;
1602 }
1603
1604 for (auto I = Start; I < End; I++) {
1605 // Ignore unsupported instructions.
1606 const FeatureBitset &RequiredFeatures = FeatureBitsets[I->RequiredFeaturesIdx];
1607 if ((FBS & RequiredFeatures) != RequiredFeatures)
1608 continue;
1609
1610 StringRef T = I->getMnemonic();
1611 // Avoid recomputing the edit distance for the same string.
1612 if (T == Prev)
1613 continue;
1614
1615 Prev = T;
1616 unsigned Dist = S.edit_distance(T, false, MaxEditDist);
1617 if (Dist <= MaxEditDist)
1618 Candidates.push_back(T);
1619 }
1620
1621 if (Candidates.empty())
1622 return "";
1623
1624 std::string Res = ", did you mean: ";
1625 unsigned i = 0;
1626 for (; i < Candidates.size() - 1; i++)
1627 Res += Candidates[i].str() + ", ";
1628 return Res + Candidates[i].str() + "?";
1629}
1630
1631#endif // GET_MNEMONIC_SPELL_CHECKER
1632
1633
1634#ifdef GET_MNEMONIC_CHECKER
1635#undef GET_MNEMONIC_CHECKER
1636
1637static bool AVRCheckMnemonic(StringRef Mnemonic,
1638 const FeatureBitset &AvailableFeatures,
1639 unsigned VariantID) {
1640 // Find the appropriate table for this asm variant.
1641 const MatchEntry *Start, *End;
1642 switch (VariantID) {
1643 default: llvm_unreachable("invalid variant!");
1644 case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break;
1645 }
1646
1647 // Search the table.
1648 auto MnemonicRange = std::equal_range(Start, End, Mnemonic, LessOpcode());
1649
1650 if (MnemonicRange.first == MnemonicRange.second)
1651 return false;
1652
1653 for (const MatchEntry *it = MnemonicRange.first, *ie = MnemonicRange.second;
1654 it != ie; ++it) {
1655 const FeatureBitset &RequiredFeatures =
1656 FeatureBitsets[it->RequiredFeaturesIdx];
1657 if ((AvailableFeatures & RequiredFeatures) == RequiredFeatures)
1658 return true;
1659 }
1660 return false;
1661}
1662
1663#endif // GET_MNEMONIC_CHECKER
1664
1665