1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Instruction Enum Values and Descriptors *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_INSTRINFO_ENUM
10#undef GET_INSTRINFO_ENUM
11namespace llvm::BPF {
12 enum {
13 PHI = 0,
14 INLINEASM = 1,
15 INLINEASM_BR = 2,
16 CFI_INSTRUCTION = 3,
17 EH_LABEL = 4,
18 GC_LABEL = 5,
19 ANNOTATION_LABEL = 6,
20 KILL = 7,
21 EXTRACT_SUBREG = 8,
22 INSERT_SUBREG = 9,
23 IMPLICIT_DEF = 10,
24 INIT_UNDEF = 11,
25 SUBREG_TO_REG = 12,
26 COPY_TO_REGCLASS = 13,
27 DBG_VALUE = 14,
28 DBG_VALUE_LIST = 15,
29 DBG_INSTR_REF = 16,
30 DBG_PHI = 17,
31 DBG_LABEL = 18,
32 REG_SEQUENCE = 19,
33 COPY = 20,
34 BUNDLE = 21,
35 LIFETIME_START = 22,
36 LIFETIME_END = 23,
37 PSEUDO_PROBE = 24,
38 ARITH_FENCE = 25,
39 STACKMAP = 26,
40 FENTRY_CALL = 27,
41 PATCHPOINT = 28,
42 LOAD_STACK_GUARD = 29,
43 PREALLOCATED_SETUP = 30,
44 PREALLOCATED_ARG = 31,
45 STATEPOINT = 32,
46 LOCAL_ESCAPE = 33,
47 FAULTING_OP = 34,
48 PATCHABLE_OP = 35,
49 PATCHABLE_FUNCTION_ENTER = 36,
50 PATCHABLE_RET = 37,
51 PATCHABLE_FUNCTION_EXIT = 38,
52 PATCHABLE_TAIL_CALL = 39,
53 PATCHABLE_EVENT_CALL = 40,
54 PATCHABLE_TYPED_EVENT_CALL = 41,
55 ICALL_BRANCH_FUNNEL = 42,
56 FAKE_USE = 43,
57 MEMBARRIER = 44,
58 JUMP_TABLE_DEBUG_INFO = 45,
59 CONVERGENCECTRL_ENTRY = 46,
60 CONVERGENCECTRL_ANCHOR = 47,
61 CONVERGENCECTRL_LOOP = 48,
62 CONVERGENCECTRL_GLUE = 49,
63 G_ASSERT_SEXT = 50,
64 G_ASSERT_ZEXT = 51,
65 G_ASSERT_ALIGN = 52,
66 G_ADD = 53,
67 G_SUB = 54,
68 G_MUL = 55,
69 G_SDIV = 56,
70 G_UDIV = 57,
71 G_SREM = 58,
72 G_UREM = 59,
73 G_SDIVREM = 60,
74 G_UDIVREM = 61,
75 G_AND = 62,
76 G_OR = 63,
77 G_XOR = 64,
78 G_ABDS = 65,
79 G_ABDU = 66,
80 G_IMPLICIT_DEF = 67,
81 G_PHI = 68,
82 G_FRAME_INDEX = 69,
83 G_GLOBAL_VALUE = 70,
84 G_PTRAUTH_GLOBAL_VALUE = 71,
85 G_CONSTANT_POOL = 72,
86 G_EXTRACT = 73,
87 G_UNMERGE_VALUES = 74,
88 G_INSERT = 75,
89 G_MERGE_VALUES = 76,
90 G_BUILD_VECTOR = 77,
91 G_BUILD_VECTOR_TRUNC = 78,
92 G_CONCAT_VECTORS = 79,
93 G_PTRTOINT = 80,
94 G_INTTOPTR = 81,
95 G_BITCAST = 82,
96 G_FREEZE = 83,
97 G_CONSTANT_FOLD_BARRIER = 84,
98 G_INTRINSIC_FPTRUNC_ROUND = 85,
99 G_INTRINSIC_TRUNC = 86,
100 G_INTRINSIC_ROUND = 87,
101 G_INTRINSIC_LRINT = 88,
102 G_INTRINSIC_LLRINT = 89,
103 G_INTRINSIC_ROUNDEVEN = 90,
104 G_READCYCLECOUNTER = 91,
105 G_READSTEADYCOUNTER = 92,
106 G_LOAD = 93,
107 G_SEXTLOAD = 94,
108 G_ZEXTLOAD = 95,
109 G_INDEXED_LOAD = 96,
110 G_INDEXED_SEXTLOAD = 97,
111 G_INDEXED_ZEXTLOAD = 98,
112 G_STORE = 99,
113 G_INDEXED_STORE = 100,
114 G_ATOMIC_CMPXCHG_WITH_SUCCESS = 101,
115 G_ATOMIC_CMPXCHG = 102,
116 G_ATOMICRMW_XCHG = 103,
117 G_ATOMICRMW_ADD = 104,
118 G_ATOMICRMW_SUB = 105,
119 G_ATOMICRMW_AND = 106,
120 G_ATOMICRMW_NAND = 107,
121 G_ATOMICRMW_OR = 108,
122 G_ATOMICRMW_XOR = 109,
123 G_ATOMICRMW_MAX = 110,
124 G_ATOMICRMW_MIN = 111,
125 G_ATOMICRMW_UMAX = 112,
126 G_ATOMICRMW_UMIN = 113,
127 G_ATOMICRMW_FADD = 114,
128 G_ATOMICRMW_FSUB = 115,
129 G_ATOMICRMW_FMAX = 116,
130 G_ATOMICRMW_FMIN = 117,
131 G_ATOMICRMW_FMAXIMUM = 118,
132 G_ATOMICRMW_FMINIMUM = 119,
133 G_ATOMICRMW_UINC_WRAP = 120,
134 G_ATOMICRMW_UDEC_WRAP = 121,
135 G_ATOMICRMW_USUB_COND = 122,
136 G_ATOMICRMW_USUB_SAT = 123,
137 G_FENCE = 124,
138 G_PREFETCH = 125,
139 G_BRCOND = 126,
140 G_BRINDIRECT = 127,
141 G_INVOKE_REGION_START = 128,
142 G_INTRINSIC = 129,
143 G_INTRINSIC_W_SIDE_EFFECTS = 130,
144 G_INTRINSIC_CONVERGENT = 131,
145 G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 132,
146 G_ANYEXT = 133,
147 G_TRUNC = 134,
148 G_CONSTANT = 135,
149 G_FCONSTANT = 136,
150 G_VASTART = 137,
151 G_VAARG = 138,
152 G_SEXT = 139,
153 G_SEXT_INREG = 140,
154 G_ZEXT = 141,
155 G_SHL = 142,
156 G_LSHR = 143,
157 G_ASHR = 144,
158 G_FSHL = 145,
159 G_FSHR = 146,
160 G_ROTR = 147,
161 G_ROTL = 148,
162 G_ICMP = 149,
163 G_FCMP = 150,
164 G_SCMP = 151,
165 G_UCMP = 152,
166 G_SELECT = 153,
167 G_UADDO = 154,
168 G_UADDE = 155,
169 G_USUBO = 156,
170 G_USUBE = 157,
171 G_SADDO = 158,
172 G_SADDE = 159,
173 G_SSUBO = 160,
174 G_SSUBE = 161,
175 G_UMULO = 162,
176 G_SMULO = 163,
177 G_UMULH = 164,
178 G_SMULH = 165,
179 G_UADDSAT = 166,
180 G_SADDSAT = 167,
181 G_USUBSAT = 168,
182 G_SSUBSAT = 169,
183 G_USHLSAT = 170,
184 G_SSHLSAT = 171,
185 G_SMULFIX = 172,
186 G_UMULFIX = 173,
187 G_SMULFIXSAT = 174,
188 G_UMULFIXSAT = 175,
189 G_SDIVFIX = 176,
190 G_UDIVFIX = 177,
191 G_SDIVFIXSAT = 178,
192 G_UDIVFIXSAT = 179,
193 G_FADD = 180,
194 G_FSUB = 181,
195 G_FMUL = 182,
196 G_FMA = 183,
197 G_FMAD = 184,
198 G_FDIV = 185,
199 G_FREM = 186,
200 G_FPOW = 187,
201 G_FPOWI = 188,
202 G_FEXP = 189,
203 G_FEXP2 = 190,
204 G_FEXP10 = 191,
205 G_FLOG = 192,
206 G_FLOG2 = 193,
207 G_FLOG10 = 194,
208 G_FLDEXP = 195,
209 G_FFREXP = 196,
210 G_FNEG = 197,
211 G_FPEXT = 198,
212 G_FPTRUNC = 199,
213 G_FPTOSI = 200,
214 G_FPTOUI = 201,
215 G_SITOFP = 202,
216 G_UITOFP = 203,
217 G_FPTOSI_SAT = 204,
218 G_FPTOUI_SAT = 205,
219 G_FABS = 206,
220 G_FCOPYSIGN = 207,
221 G_IS_FPCLASS = 208,
222 G_FCANONICALIZE = 209,
223 G_FMINNUM = 210,
224 G_FMAXNUM = 211,
225 G_FMINNUM_IEEE = 212,
226 G_FMAXNUM_IEEE = 213,
227 G_FMINIMUM = 214,
228 G_FMAXIMUM = 215,
229 G_FMINIMUMNUM = 216,
230 G_FMAXIMUMNUM = 217,
231 G_GET_FPENV = 218,
232 G_SET_FPENV = 219,
233 G_RESET_FPENV = 220,
234 G_GET_FPMODE = 221,
235 G_SET_FPMODE = 222,
236 G_RESET_FPMODE = 223,
237 G_PTR_ADD = 224,
238 G_PTRMASK = 225,
239 G_SMIN = 226,
240 G_SMAX = 227,
241 G_UMIN = 228,
242 G_UMAX = 229,
243 G_ABS = 230,
244 G_LROUND = 231,
245 G_LLROUND = 232,
246 G_BR = 233,
247 G_BRJT = 234,
248 G_VSCALE = 235,
249 G_INSERT_SUBVECTOR = 236,
250 G_EXTRACT_SUBVECTOR = 237,
251 G_INSERT_VECTOR_ELT = 238,
252 G_EXTRACT_VECTOR_ELT = 239,
253 G_SHUFFLE_VECTOR = 240,
254 G_SPLAT_VECTOR = 241,
255 G_STEP_VECTOR = 242,
256 G_VECTOR_COMPRESS = 243,
257 G_CTTZ = 244,
258 G_CTTZ_ZERO_UNDEF = 245,
259 G_CTLZ = 246,
260 G_CTLZ_ZERO_UNDEF = 247,
261 G_CTPOP = 248,
262 G_BSWAP = 249,
263 G_BITREVERSE = 250,
264 G_FCEIL = 251,
265 G_FCOS = 252,
266 G_FSIN = 253,
267 G_FSINCOS = 254,
268 G_FTAN = 255,
269 G_FACOS = 256,
270 G_FASIN = 257,
271 G_FATAN = 258,
272 G_FATAN2 = 259,
273 G_FCOSH = 260,
274 G_FSINH = 261,
275 G_FTANH = 262,
276 G_FSQRT = 263,
277 G_FFLOOR = 264,
278 G_FRINT = 265,
279 G_FNEARBYINT = 266,
280 G_ADDRSPACE_CAST = 267,
281 G_BLOCK_ADDR = 268,
282 G_JUMP_TABLE = 269,
283 G_DYN_STACKALLOC = 270,
284 G_STACKSAVE = 271,
285 G_STACKRESTORE = 272,
286 G_STRICT_FADD = 273,
287 G_STRICT_FSUB = 274,
288 G_STRICT_FMUL = 275,
289 G_STRICT_FDIV = 276,
290 G_STRICT_FREM = 277,
291 G_STRICT_FMA = 278,
292 G_STRICT_FSQRT = 279,
293 G_STRICT_FLDEXP = 280,
294 G_READ_REGISTER = 281,
295 G_WRITE_REGISTER = 282,
296 G_MEMCPY = 283,
297 G_MEMCPY_INLINE = 284,
298 G_MEMMOVE = 285,
299 G_MEMSET = 286,
300 G_BZERO = 287,
301 G_TRAP = 288,
302 G_DEBUGTRAP = 289,
303 G_UBSANTRAP = 290,
304 G_VECREDUCE_SEQ_FADD = 291,
305 G_VECREDUCE_SEQ_FMUL = 292,
306 G_VECREDUCE_FADD = 293,
307 G_VECREDUCE_FMUL = 294,
308 G_VECREDUCE_FMAX = 295,
309 G_VECREDUCE_FMIN = 296,
310 G_VECREDUCE_FMAXIMUM = 297,
311 G_VECREDUCE_FMINIMUM = 298,
312 G_VECREDUCE_ADD = 299,
313 G_VECREDUCE_MUL = 300,
314 G_VECREDUCE_AND = 301,
315 G_VECREDUCE_OR = 302,
316 G_VECREDUCE_XOR = 303,
317 G_VECREDUCE_SMAX = 304,
318 G_VECREDUCE_SMIN = 305,
319 G_VECREDUCE_UMAX = 306,
320 G_VECREDUCE_UMIN = 307,
321 G_SBFX = 308,
322 G_UBFX = 309,
323 ADJCALLSTACKDOWN = 310,
324 ADJCALLSTACKUP = 311,
325 FI_ri = 312,
326 MEMCPY = 313,
327 Select = 314,
328 Select_32 = 315,
329 Select_32_64 = 316,
330 Select_64_32 = 317,
331 Select_Ri = 318,
332 Select_Ri_32 = 319,
333 Select_Ri_32_64 = 320,
334 Select_Ri_64_32 = 321,
335 ADDR_SPACE_CAST = 322,
336 ADD_ri = 323,
337 ADD_ri_32 = 324,
338 ADD_rr = 325,
339 ADD_rr_32 = 326,
340 AND_ri = 327,
341 AND_ri_32 = 328,
342 AND_rr = 329,
343 AND_rr_32 = 330,
344 BE16 = 331,
345 BE32 = 332,
346 BE64 = 333,
347 BSWAP16 = 334,
348 BSWAP32 = 335,
349 BSWAP64 = 336,
350 CMPXCHGD = 337,
351 CMPXCHGW32 = 338,
352 CORE_LD32 = 339,
353 CORE_LD64 = 340,
354 CORE_SHIFT = 341,
355 CORE_ST = 342,
356 DIV_ri = 343,
357 DIV_ri_32 = 344,
358 DIV_rr = 345,
359 DIV_rr_32 = 346,
360 JAL = 347,
361 JALX = 348,
362 JCOND = 349,
363 JEQ_ri = 350,
364 JEQ_ri_32 = 351,
365 JEQ_rr = 352,
366 JEQ_rr_32 = 353,
367 JMP = 354,
368 JMPL = 355,
369 JNE_ri = 356,
370 JNE_ri_32 = 357,
371 JNE_rr = 358,
372 JNE_rr_32 = 359,
373 JSET_ri = 360,
374 JSET_ri_32 = 361,
375 JSET_rr = 362,
376 JSET_rr_32 = 363,
377 JSGE_ri = 364,
378 JSGE_ri_32 = 365,
379 JSGE_rr = 366,
380 JSGE_rr_32 = 367,
381 JSGT_ri = 368,
382 JSGT_ri_32 = 369,
383 JSGT_rr = 370,
384 JSGT_rr_32 = 371,
385 JSLE_ri = 372,
386 JSLE_ri_32 = 373,
387 JSLE_rr = 374,
388 JSLE_rr_32 = 375,
389 JSLT_ri = 376,
390 JSLT_ri_32 = 377,
391 JSLT_rr = 378,
392 JSLT_rr_32 = 379,
393 JUGE_ri = 380,
394 JUGE_ri_32 = 381,
395 JUGE_rr = 382,
396 JUGE_rr_32 = 383,
397 JUGT_ri = 384,
398 JUGT_ri_32 = 385,
399 JUGT_rr = 386,
400 JUGT_rr_32 = 387,
401 JULE_ri = 388,
402 JULE_ri_32 = 389,
403 JULE_rr = 390,
404 JULE_rr_32 = 391,
405 JULT_ri = 392,
406 JULT_ri_32 = 393,
407 JULT_rr = 394,
408 JULT_rr_32 = 395,
409 LDB = 396,
410 LDB32 = 397,
411 LDBACQ32 = 398,
412 LDBSX = 399,
413 LDD = 400,
414 LDDACQ = 401,
415 LDH = 402,
416 LDH32 = 403,
417 LDHACQ32 = 404,
418 LDHSX = 405,
419 LDW = 406,
420 LDW32 = 407,
421 LDWACQ32 = 408,
422 LDWSX = 409,
423 LD_ABS_B = 410,
424 LD_ABS_H = 411,
425 LD_ABS_W = 412,
426 LD_IND_B = 413,
427 LD_IND_H = 414,
428 LD_IND_W = 415,
429 LD_imm64 = 416,
430 LD_pseudo = 417,
431 LE16 = 418,
432 LE32 = 419,
433 LE64 = 420,
434 MOD_ri = 421,
435 MOD_ri_32 = 422,
436 MOD_rr = 423,
437 MOD_rr_32 = 424,
438 MOVSX_rr_16 = 425,
439 MOVSX_rr_32 = 426,
440 MOVSX_rr_32_16 = 427,
441 MOVSX_rr_32_8 = 428,
442 MOVSX_rr_8 = 429,
443 MOV_32_64 = 430,
444 MOV_ri = 431,
445 MOV_ri_32 = 432,
446 MOV_rr = 433,
447 MOV_rr_32 = 434,
448 MUL_ri = 435,
449 MUL_ri_32 = 436,
450 MUL_rr = 437,
451 MUL_rr_32 = 438,
452 NEG_32 = 439,
453 NEG_64 = 440,
454 NOP = 441,
455 OR_ri = 442,
456 OR_ri_32 = 443,
457 OR_rr = 444,
458 OR_rr_32 = 445,
459 RET = 446,
460 SDIV_ri = 447,
461 SDIV_ri_32 = 448,
462 SDIV_rr = 449,
463 SDIV_rr_32 = 450,
464 SLL_ri = 451,
465 SLL_ri_32 = 452,
466 SLL_rr = 453,
467 SLL_rr_32 = 454,
468 SMOD_ri = 455,
469 SMOD_ri_32 = 456,
470 SMOD_rr = 457,
471 SMOD_rr_32 = 458,
472 SRA_ri = 459,
473 SRA_ri_32 = 460,
474 SRA_rr = 461,
475 SRA_rr_32 = 462,
476 SRL_ri = 463,
477 SRL_ri_32 = 464,
478 SRL_rr = 465,
479 SRL_rr_32 = 466,
480 STB = 467,
481 STB32 = 468,
482 STBREL32 = 469,
483 STB_imm = 470,
484 STD = 471,
485 STDREL = 472,
486 STD_imm = 473,
487 STH = 474,
488 STH32 = 475,
489 STHREL32 = 476,
490 STH_imm = 477,
491 STW = 478,
492 STW32 = 479,
493 STWREL32 = 480,
494 STW_imm = 481,
495 SUB_ri = 482,
496 SUB_ri_32 = 483,
497 SUB_rr = 484,
498 SUB_rr_32 = 485,
499 XADDD = 486,
500 XADDW = 487,
501 XADDW32 = 488,
502 XANDD = 489,
503 XANDW32 = 490,
504 XCHGD = 491,
505 XCHGW32 = 492,
506 XFADDD = 493,
507 XFADDW32 = 494,
508 XFANDD = 495,
509 XFANDW32 = 496,
510 XFORD = 497,
511 XFORW32 = 498,
512 XFXORD = 499,
513 XFXORW32 = 500,
514 XORD = 501,
515 XORW32 = 502,
516 XOR_ri = 503,
517 XOR_ri_32 = 504,
518 XOR_rr = 505,
519 XOR_rr_32 = 506,
520 XXORD = 507,
521 XXORW32 = 508,
522 INSTRUCTION_LIST_END = 509
523 };
524
525} // end namespace llvm::BPF
526#endif // GET_INSTRINFO_ENUM
527
528#ifdef GET_INSTRINFO_SCHED_ENUM
529#undef GET_INSTRINFO_SCHED_ENUM
530namespace llvm::BPF::Sched {
531
532 enum {
533 NoInstrModel = 0,
534 SCHED_LIST_END = 1
535 };
536} // end namespace llvm::BPF::Sched
537#endif // GET_INSTRINFO_SCHED_ENUM
538
539#if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
540namespace llvm {
541
542struct BPFInstrTable {
543 MCInstrDesc Insts[509];
544 static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo");
545 MCOperandInfo OperandInfo[284];
546 static_assert(alignof(MCOperandInfo) >= alignof(MCPhysReg), "Unwanted padding between OperandInfo and ImplicitOps");
547 MCPhysReg ImplicitOps[14];
548};
549
550} // end namespace llvm
551#endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
552
553#ifdef GET_INSTRINFO_MC_DESC
554#undef GET_INSTRINFO_MC_DESC
555namespace llvm {
556
557static_assert(sizeof(MCOperandInfo) % sizeof(MCPhysReg) == 0);
558static constexpr unsigned BPFImpOpBase = sizeof BPFInstrTable::OperandInfo / (sizeof(MCPhysReg));
559
560extern const BPFInstrTable BPFDescs = {
561 {
562 { 508, 4, 1, 8, 0, 0, 0, 280, BPFImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #508 = XXORW32
563 { 507, 4, 1, 8, 0, 0, 0, 276, BPFImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #507 = XXORD
564 { 506, 3, 1, 8, 0, 0, 0, 216, BPFImpOpBase + 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #506 = XOR_rr_32
565 { 505, 3, 1, 8, 0, 0, 0, 213, BPFImpOpBase + 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #505 = XOR_rr
566 { 504, 3, 1, 8, 0, 0, 0, 210, BPFImpOpBase + 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #504 = XOR_ri_32
567 { 503, 3, 1, 8, 0, 0, 0, 207, BPFImpOpBase + 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #503 = XOR_ri
568 { 502, 4, 1, 8, 0, 0, 0, 280, BPFImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #502 = XORW32
569 { 501, 4, 1, 8, 0, 0, 0, 276, BPFImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #501 = XORD
570 { 500, 4, 1, 8, 0, 0, 0, 280, BPFImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #500 = XFXORW32
571 { 499, 4, 1, 8, 0, 0, 0, 276, BPFImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #499 = XFXORD
572 { 498, 4, 1, 8, 0, 0, 0, 280, BPFImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #498 = XFORW32
573 { 497, 4, 1, 8, 0, 0, 0, 276, BPFImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #497 = XFORD
574 { 496, 4, 1, 8, 0, 0, 0, 280, BPFImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #496 = XFANDW32
575 { 495, 4, 1, 8, 0, 0, 0, 276, BPFImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #495 = XFANDD
576 { 494, 4, 1, 8, 0, 0, 0, 280, BPFImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #494 = XFADDW32
577 { 493, 4, 1, 8, 0, 0, 0, 276, BPFImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #493 = XFADDD
578 { 492, 4, 1, 8, 0, 0, 0, 280, BPFImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #492 = XCHGW32
579 { 491, 4, 1, 8, 0, 0, 0, 276, BPFImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #491 = XCHGD
580 { 490, 4, 1, 8, 0, 0, 0, 280, BPFImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #490 = XANDW32
581 { 489, 4, 1, 8, 0, 0, 0, 276, BPFImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #489 = XANDD
582 { 488, 4, 1, 8, 0, 0, 0, 280, BPFImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #488 = XADDW32
583 { 487, 4, 1, 8, 0, 0, 0, 276, BPFImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #487 = XADDW
584 { 486, 4, 1, 8, 0, 0, 0, 276, BPFImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #486 = XADDD
585 { 485, 3, 1, 8, 0, 0, 0, 216, BPFImpOpBase + 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #485 = SUB_rr_32
586 { 484, 3, 1, 8, 0, 0, 0, 213, BPFImpOpBase + 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #484 = SUB_rr
587 { 483, 3, 1, 8, 0, 0, 0, 210, BPFImpOpBase + 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #483 = SUB_ri_32
588 { 482, 3, 1, 8, 0, 0, 0, 207, BPFImpOpBase + 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #482 = SUB_ri
589 { 481, 3, 0, 8, 0, 0, 0, 273, BPFImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #481 = STW_imm
590 { 480, 3, 0, 8, 0, 0, 0, 256, BPFImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #480 = STWREL32
591 { 479, 3, 0, 8, 0, 0, 0, 256, BPFImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #479 = STW32
592 { 478, 3, 0, 8, 0, 0, 0, 152, BPFImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #478 = STW
593 { 477, 3, 0, 8, 0, 0, 0, 273, BPFImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #477 = STH_imm
594 { 476, 3, 0, 8, 0, 0, 0, 256, BPFImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #476 = STHREL32
595 { 475, 3, 0, 8, 0, 0, 0, 256, BPFImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #475 = STH32
596 { 474, 3, 0, 8, 0, 0, 0, 152, BPFImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #474 = STH
597 { 473, 3, 0, 8, 0, 0, 0, 273, BPFImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #473 = STD_imm
598 { 472, 3, 0, 8, 0, 0, 0, 152, BPFImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #472 = STDREL
599 { 471, 3, 0, 8, 0, 0, 0, 152, BPFImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #471 = STD
600 { 470, 3, 0, 8, 0, 0, 0, 273, BPFImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #470 = STB_imm
601 { 469, 3, 0, 8, 0, 0, 0, 256, BPFImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #469 = STBREL32
602 { 468, 3, 0, 8, 0, 0, 0, 256, BPFImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #468 = STB32
603 { 467, 3, 0, 8, 0, 0, 0, 152, BPFImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #467 = STB
604 { 466, 3, 1, 8, 0, 0, 0, 216, BPFImpOpBase + 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #466 = SRL_rr_32
605 { 465, 3, 1, 8, 0, 0, 0, 213, BPFImpOpBase + 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #465 = SRL_rr
606 { 464, 3, 1, 8, 0, 0, 0, 210, BPFImpOpBase + 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #464 = SRL_ri_32
607 { 463, 3, 1, 8, 0, 0, 0, 207, BPFImpOpBase + 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #463 = SRL_ri
608 { 462, 3, 1, 8, 0, 0, 0, 216, BPFImpOpBase + 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #462 = SRA_rr_32
609 { 461, 3, 1, 8, 0, 0, 0, 213, BPFImpOpBase + 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #461 = SRA_rr
610 { 460, 3, 1, 8, 0, 0, 0, 210, BPFImpOpBase + 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #460 = SRA_ri_32
611 { 459, 3, 1, 8, 0, 0, 0, 207, BPFImpOpBase + 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #459 = SRA_ri
612 { 458, 3, 1, 8, 0, 0, 0, 216, BPFImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #458 = SMOD_rr_32
613 { 457, 3, 1, 8, 0, 0, 0, 213, BPFImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #457 = SMOD_rr
614 { 456, 3, 1, 8, 0, 0, 0, 210, BPFImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #456 = SMOD_ri_32
615 { 455, 3, 1, 8, 0, 0, 0, 207, BPFImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #455 = SMOD_ri
616 { 454, 3, 1, 8, 0, 0, 0, 216, BPFImpOpBase + 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #454 = SLL_rr_32
617 { 453, 3, 1, 8, 0, 0, 0, 213, BPFImpOpBase + 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #453 = SLL_rr
618 { 452, 3, 1, 8, 0, 0, 0, 210, BPFImpOpBase + 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #452 = SLL_ri_32
619 { 451, 3, 1, 8, 0, 0, 0, 207, BPFImpOpBase + 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #451 = SLL_ri
620 { 450, 3, 1, 8, 0, 0, 0, 216, BPFImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #450 = SDIV_rr_32
621 { 449, 3, 1, 8, 0, 0, 0, 213, BPFImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #449 = SDIV_rr
622 { 448, 3, 1, 8, 0, 0, 0, 210, BPFImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #448 = SDIV_ri_32
623 { 447, 3, 1, 8, 0, 0, 0, 207, BPFImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #447 = SDIV_ri
624 { 446, 0, 0, 8, 0, 0, 0, 1, BPFImpOpBase + 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #446 = RET
625 { 445, 3, 1, 8, 0, 0, 0, 216, BPFImpOpBase + 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #445 = OR_rr_32
626 { 444, 3, 1, 8, 0, 0, 0, 213, BPFImpOpBase + 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #444 = OR_rr
627 { 443, 3, 1, 8, 0, 0, 0, 210, BPFImpOpBase + 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #443 = OR_ri_32
628 { 442, 3, 1, 8, 0, 0, 0, 207, BPFImpOpBase + 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #442 = OR_ri
629 { 441, 1, 0, 8, 0, 0, 0, 1, BPFImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #441 = NOP
630 { 440, 2, 1, 8, 0, 0, 0, 219, BPFImpOpBase + 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #440 = NEG_64
631 { 439, 2, 1, 8, 0, 0, 0, 271, BPFImpOpBase + 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #439 = NEG_32
632 { 438, 3, 1, 8, 0, 0, 0, 216, BPFImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #438 = MUL_rr_32
633 { 437, 3, 1, 8, 0, 0, 0, 213, BPFImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #437 = MUL_rr
634 { 436, 3, 1, 8, 0, 0, 0, 210, BPFImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #436 = MUL_ri_32
635 { 435, 3, 1, 8, 0, 0, 0, 207, BPFImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #435 = MUL_ri
636 { 434, 2, 1, 8, 0, 0, 0, 265, BPFImpOpBase + 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #434 = MOV_rr_32
637 { 433, 2, 1, 8, 0, 0, 0, 261, BPFImpOpBase + 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #433 = MOV_rr
638 { 432, 2, 1, 8, 0, 0, 0, 269, BPFImpOpBase + 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #432 = MOV_ri_32
639 { 431, 2, 1, 8, 0, 0, 0, 259, BPFImpOpBase + 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #431 = MOV_ri
640 { 430, 2, 1, 8, 0, 0, 0, 267, BPFImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #430 = MOV_32_64
641 { 429, 2, 1, 8, 0, 0, 0, 261, BPFImpOpBase + 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #429 = MOVSX_rr_8
642 { 428, 2, 1, 8, 0, 0, 0, 265, BPFImpOpBase + 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #428 = MOVSX_rr_32_8
643 { 427, 2, 1, 8, 0, 0, 0, 265, BPFImpOpBase + 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #427 = MOVSX_rr_32_16
644 { 426, 2, 1, 8, 0, 0, 0, 261, BPFImpOpBase + 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #426 = MOVSX_rr_32
645 { 425, 2, 1, 8, 0, 0, 0, 261, BPFImpOpBase + 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #425 = MOVSX_rr_16
646 { 424, 3, 1, 8, 0, 0, 0, 216, BPFImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #424 = MOD_rr_32
647 { 423, 3, 1, 8, 0, 0, 0, 213, BPFImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #423 = MOD_rr
648 { 422, 3, 1, 8, 0, 0, 0, 210, BPFImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #422 = MOD_ri_32
649 { 421, 3, 1, 8, 0, 0, 0, 207, BPFImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #421 = MOD_ri
650 { 420, 2, 1, 8, 0, 0, 0, 219, BPFImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #420 = LE64
651 { 419, 2, 1, 8, 0, 0, 0, 219, BPFImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #419 = LE32
652 { 418, 2, 1, 8, 0, 0, 0, 219, BPFImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #418 = LE16
653 { 417, 3, 1, 8, 0, 0, 0, 244, BPFImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #417 = LD_pseudo
654 { 416, 2, 1, 8, 0, 0, 0, 263, BPFImpOpBase + 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #416 = LD_imm64
655 { 415, 2, 0, 8, 0, 1, 6, 261, BPFImpOpBase + 7, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #415 = LD_IND_W
656 { 414, 2, 0, 8, 0, 1, 6, 261, BPFImpOpBase + 7, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #414 = LD_IND_H
657 { 413, 2, 0, 8, 0, 1, 6, 261, BPFImpOpBase + 7, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #413 = LD_IND_B
658 { 412, 2, 0, 8, 0, 1, 6, 259, BPFImpOpBase + 7, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #412 = LD_ABS_W
659 { 411, 2, 0, 8, 0, 1, 6, 259, BPFImpOpBase + 7, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #411 = LD_ABS_H
660 { 410, 2, 0, 8, 0, 1, 6, 259, BPFImpOpBase + 7, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #410 = LD_ABS_B
661 { 409, 3, 1, 8, 0, 0, 0, 152, BPFImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #409 = LDWSX
662 { 408, 3, 1, 8, 0, 0, 0, 256, BPFImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #408 = LDWACQ32
663 { 407, 3, 1, 8, 0, 0, 0, 256, BPFImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #407 = LDW32
664 { 406, 3, 1, 8, 0, 0, 0, 152, BPFImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #406 = LDW
665 { 405, 3, 1, 8, 0, 0, 0, 152, BPFImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #405 = LDHSX
666 { 404, 3, 1, 8, 0, 0, 0, 256, BPFImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #404 = LDHACQ32
667 { 403, 3, 1, 8, 0, 0, 0, 256, BPFImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #403 = LDH32
668 { 402, 3, 1, 8, 0, 0, 0, 152, BPFImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #402 = LDH
669 { 401, 3, 1, 8, 0, 0, 0, 152, BPFImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #401 = LDDACQ
670 { 400, 3, 1, 8, 0, 0, 0, 152, BPFImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #400 = LDD
671 { 399, 3, 1, 8, 0, 0, 0, 152, BPFImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #399 = LDBSX
672 { 398, 3, 1, 8, 0, 0, 0, 256, BPFImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #398 = LDBACQ32
673 { 397, 3, 1, 8, 0, 0, 0, 256, BPFImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #397 = LDB32
674 { 396, 3, 1, 8, 0, 0, 0, 152, BPFImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #396 = LDB
675 { 395, 3, 0, 8, 0, 0, 0, 253, BPFImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #395 = JULT_rr_32
676 { 394, 3, 0, 8, 0, 0, 0, 250, BPFImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #394 = JULT_rr
677 { 393, 3, 0, 8, 0, 0, 0, 247, BPFImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #393 = JULT_ri_32
678 { 392, 3, 0, 8, 0, 0, 0, 244, BPFImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #392 = JULT_ri
679 { 391, 3, 0, 8, 0, 0, 0, 253, BPFImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #391 = JULE_rr_32
680 { 390, 3, 0, 8, 0, 0, 0, 250, BPFImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #390 = JULE_rr
681 { 389, 3, 0, 8, 0, 0, 0, 247, BPFImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #389 = JULE_ri_32
682 { 388, 3, 0, 8, 0, 0, 0, 244, BPFImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #388 = JULE_ri
683 { 387, 3, 0, 8, 0, 0, 0, 253, BPFImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #387 = JUGT_rr_32
684 { 386, 3, 0, 8, 0, 0, 0, 250, BPFImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #386 = JUGT_rr
685 { 385, 3, 0, 8, 0, 0, 0, 247, BPFImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #385 = JUGT_ri_32
686 { 384, 3, 0, 8, 0, 0, 0, 244, BPFImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #384 = JUGT_ri
687 { 383, 3, 0, 8, 0, 0, 0, 253, BPFImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #383 = JUGE_rr_32
688 { 382, 3, 0, 8, 0, 0, 0, 250, BPFImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #382 = JUGE_rr
689 { 381, 3, 0, 8, 0, 0, 0, 247, BPFImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #381 = JUGE_ri_32
690 { 380, 3, 0, 8, 0, 0, 0, 244, BPFImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #380 = JUGE_ri
691 { 379, 3, 0, 8, 0, 0, 0, 253, BPFImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #379 = JSLT_rr_32
692 { 378, 3, 0, 8, 0, 0, 0, 250, BPFImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #378 = JSLT_rr
693 { 377, 3, 0, 8, 0, 0, 0, 247, BPFImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #377 = JSLT_ri_32
694 { 376, 3, 0, 8, 0, 0, 0, 244, BPFImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #376 = JSLT_ri
695 { 375, 3, 0, 8, 0, 0, 0, 253, BPFImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #375 = JSLE_rr_32
696 { 374, 3, 0, 8, 0, 0, 0, 250, BPFImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #374 = JSLE_rr
697 { 373, 3, 0, 8, 0, 0, 0, 247, BPFImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #373 = JSLE_ri_32
698 { 372, 3, 0, 8, 0, 0, 0, 244, BPFImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #372 = JSLE_ri
699 { 371, 3, 0, 8, 0, 0, 0, 253, BPFImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #371 = JSGT_rr_32
700 { 370, 3, 0, 8, 0, 0, 0, 250, BPFImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #370 = JSGT_rr
701 { 369, 3, 0, 8, 0, 0, 0, 247, BPFImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #369 = JSGT_ri_32
702 { 368, 3, 0, 8, 0, 0, 0, 244, BPFImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #368 = JSGT_ri
703 { 367, 3, 0, 8, 0, 0, 0, 253, BPFImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #367 = JSGE_rr_32
704 { 366, 3, 0, 8, 0, 0, 0, 250, BPFImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #366 = JSGE_rr
705 { 365, 3, 0, 8, 0, 0, 0, 247, BPFImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #365 = JSGE_ri_32
706 { 364, 3, 0, 8, 0, 0, 0, 244, BPFImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #364 = JSGE_ri
707 { 363, 3, 0, 8, 0, 0, 0, 253, BPFImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #363 = JSET_rr_32
708 { 362, 3, 0, 8, 0, 0, 0, 250, BPFImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #362 = JSET_rr
709 { 361, 3, 0, 8, 0, 0, 0, 247, BPFImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #361 = JSET_ri_32
710 { 360, 3, 0, 8, 0, 0, 0, 244, BPFImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #360 = JSET_ri
711 { 359, 3, 0, 8, 0, 0, 0, 253, BPFImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #359 = JNE_rr_32
712 { 358, 3, 0, 8, 0, 0, 0, 250, BPFImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #358 = JNE_rr
713 { 357, 3, 0, 8, 0, 0, 0, 247, BPFImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #357 = JNE_ri_32
714 { 356, 3, 0, 8, 0, 0, 0, 244, BPFImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #356 = JNE_ri
715 { 355, 1, 0, 8, 0, 0, 0, 0, BPFImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #355 = JMPL
716 { 354, 1, 0, 8, 0, 0, 0, 0, BPFImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #354 = JMP
717 { 353, 3, 0, 8, 0, 0, 0, 253, BPFImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #353 = JEQ_rr_32
718 { 352, 3, 0, 8, 0, 0, 0, 250, BPFImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #352 = JEQ_rr
719 { 351, 3, 0, 8, 0, 0, 0, 247, BPFImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #351 = JEQ_ri_32
720 { 350, 3, 0, 8, 0, 0, 0, 244, BPFImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #350 = JEQ_ri
721 { 349, 1, 0, 8, 0, 0, 0, 0, BPFImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #349 = JCOND
722 { 348, 1, 0, 8, 0, 1, 0, 243, BPFImpOpBase + 6, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #348 = JALX
723 { 347, 1, 0, 8, 0, 1, 0, 0, BPFImpOpBase + 6, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #347 = JAL
724 { 346, 3, 1, 8, 0, 0, 0, 216, BPFImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #346 = DIV_rr_32
725 { 345, 3, 1, 8, 0, 0, 0, 213, BPFImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #345 = DIV_rr
726 { 344, 3, 1, 8, 0, 0, 0, 210, BPFImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #344 = DIV_ri_32
727 { 343, 3, 1, 8, 0, 0, 0, 207, BPFImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #343 = DIV_ri
728 { 342, 4, 0, 8, 0, 0, 0, 239, BPFImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #342 = CORE_ST
729 { 341, 4, 1, 8, 0, 0, 0, 235, BPFImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #341 = CORE_SHIFT
730 { 340, 4, 1, 8, 0, 0, 0, 231, BPFImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #340 = CORE_LD64
731 { 339, 4, 1, 8, 0, 0, 0, 227, BPFImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #339 = CORE_LD32
732 { 338, 3, 0, 8, 0, 1, 1, 224, BPFImpOpBase + 4, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #338 = CMPXCHGW32
733 { 337, 3, 0, 8, 0, 1, 1, 221, BPFImpOpBase + 2, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #337 = CMPXCHGD
734 { 336, 2, 1, 8, 0, 0, 0, 219, BPFImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #336 = BSWAP64
735 { 335, 2, 1, 8, 0, 0, 0, 219, BPFImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #335 = BSWAP32
736 { 334, 2, 1, 8, 0, 0, 0, 219, BPFImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #334 = BSWAP16
737 { 333, 2, 1, 8, 0, 0, 0, 219, BPFImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #333 = BE64
738 { 332, 2, 1, 8, 0, 0, 0, 219, BPFImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #332 = BE32
739 { 331, 2, 1, 8, 0, 0, 0, 219, BPFImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #331 = BE16
740 { 330, 3, 1, 8, 0, 0, 0, 216, BPFImpOpBase + 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #330 = AND_rr_32
741 { 329, 3, 1, 8, 0, 0, 0, 213, BPFImpOpBase + 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #329 = AND_rr
742 { 328, 3, 1, 8, 0, 0, 0, 210, BPFImpOpBase + 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #328 = AND_ri_32
743 { 327, 3, 1, 8, 0, 0, 0, 207, BPFImpOpBase + 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #327 = AND_ri
744 { 326, 3, 1, 8, 0, 0, 0, 216, BPFImpOpBase + 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #326 = ADD_rr_32
745 { 325, 3, 1, 8, 0, 0, 0, 213, BPFImpOpBase + 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #325 = ADD_rr
746 { 324, 3, 1, 8, 0, 0, 0, 210, BPFImpOpBase + 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #324 = ADD_ri_32
747 { 323, 3, 1, 8, 0, 0, 0, 207, BPFImpOpBase + 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #323 = ADD_ri
748 { 322, 4, 1, 8, 0, 0, 0, 155, BPFImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #322 = ADDR_SPACE_CAST
749 { 321, 6, 1, 8, 0, 0, 0, 201, BPFImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #321 = Select_Ri_64_32
750 { 320, 6, 1, 8, 0, 0, 0, 195, BPFImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #320 = Select_Ri_32_64
751 { 319, 6, 1, 8, 0, 0, 0, 189, BPFImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #319 = Select_Ri_32
752 { 318, 6, 1, 8, 0, 0, 0, 183, BPFImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #318 = Select_Ri
753 { 317, 6, 1, 8, 0, 0, 0, 177, BPFImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #317 = Select_64_32
754 { 316, 6, 1, 8, 0, 0, 0, 171, BPFImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #316 = Select_32_64
755 { 315, 6, 1, 8, 0, 0, 0, 165, BPFImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #315 = Select_32
756 { 314, 6, 1, 8, 0, 0, 0, 159, BPFImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #314 = Select
757 { 313, 4, 0, 8, 0, 0, 0, 155, BPFImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #313 = MEMCPY
758 { 312, 3, 1, 8, 0, 0, 0, 152, BPFImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #312 = FI_ri
759 { 311, 2, 0, 8, 0, 1, 1, 21, BPFImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #311 = ADJCALLSTACKUP
760 { 310, 2, 0, 8, 0, 1, 1, 21, BPFImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #310 = ADJCALLSTACKDOWN
761 { 309, 4, 1, 0, 0, 0, 0, 148, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #309 = G_UBFX
762 { 308, 4, 1, 0, 0, 0, 0, 148, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #308 = G_SBFX
763 { 307, 2, 1, 0, 0, 0, 0, 61, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #307 = G_VECREDUCE_UMIN
764 { 306, 2, 1, 0, 0, 0, 0, 61, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #306 = G_VECREDUCE_UMAX
765 { 305, 2, 1, 0, 0, 0, 0, 61, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #305 = G_VECREDUCE_SMIN
766 { 304, 2, 1, 0, 0, 0, 0, 61, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #304 = G_VECREDUCE_SMAX
767 { 303, 2, 1, 0, 0, 0, 0, 61, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #303 = G_VECREDUCE_XOR
768 { 302, 2, 1, 0, 0, 0, 0, 61, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #302 = G_VECREDUCE_OR
769 { 301, 2, 1, 0, 0, 0, 0, 61, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #301 = G_VECREDUCE_AND
770 { 300, 2, 1, 0, 0, 0, 0, 61, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #300 = G_VECREDUCE_MUL
771 { 299, 2, 1, 0, 0, 0, 0, 61, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #299 = G_VECREDUCE_ADD
772 { 298, 2, 1, 0, 0, 0, 0, 61, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #298 = G_VECREDUCE_FMINIMUM
773 { 297, 2, 1, 0, 0, 0, 0, 61, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #297 = G_VECREDUCE_FMAXIMUM
774 { 296, 2, 1, 0, 0, 0, 0, 61, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #296 = G_VECREDUCE_FMIN
775 { 295, 2, 1, 0, 0, 0, 0, 61, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #295 = G_VECREDUCE_FMAX
776 { 294, 2, 1, 0, 0, 0, 0, 61, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #294 = G_VECREDUCE_FMUL
777 { 293, 2, 1, 0, 0, 0, 0, 61, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #293 = G_VECREDUCE_FADD
778 { 292, 3, 1, 0, 0, 0, 0, 131, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #292 = G_VECREDUCE_SEQ_FMUL
779 { 291, 3, 1, 0, 0, 0, 0, 131, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #291 = G_VECREDUCE_SEQ_FADD
780 { 290, 1, 0, 0, 0, 0, 0, 1, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #290 = G_UBSANTRAP
781 { 289, 0, 0, 0, 0, 0, 0, 1, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #289 = G_DEBUGTRAP
782 { 288, 0, 0, 0, 0, 0, 0, 1, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #288 = G_TRAP
783 { 287, 3, 0, 0, 0, 0, 0, 58, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #287 = G_BZERO
784 { 286, 4, 0, 0, 0, 0, 0, 144, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #286 = G_MEMSET
785 { 285, 4, 0, 0, 0, 0, 0, 144, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #285 = G_MEMMOVE
786 { 284, 3, 0, 0, 0, 0, 0, 131, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #284 = G_MEMCPY_INLINE
787 { 283, 4, 0, 0, 0, 0, 0, 144, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #283 = G_MEMCPY
788 { 282, 2, 0, 0, 0, 0, 0, 142, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #282 = G_WRITE_REGISTER
789 { 281, 2, 1, 0, 0, 0, 0, 51, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #281 = G_READ_REGISTER
790 { 280, 3, 1, 0, 0, 0, 0, 101, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #280 = G_STRICT_FLDEXP
791 { 279, 2, 1, 0, 0, 0, 0, 67, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #279 = G_STRICT_FSQRT
792 { 278, 4, 1, 0, 0, 0, 0, 46, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #278 = G_STRICT_FMA
793 { 277, 3, 1, 0, 0, 0, 0, 43, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #277 = G_STRICT_FREM
794 { 276, 3, 1, 0, 0, 0, 0, 43, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #276 = G_STRICT_FDIV
795 { 275, 3, 1, 0, 0, 0, 0, 43, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #275 = G_STRICT_FMUL
796 { 274, 3, 1, 0, 0, 0, 0, 43, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #274 = G_STRICT_FSUB
797 { 273, 3, 1, 0, 0, 0, 0, 43, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #273 = G_STRICT_FADD
798 { 272, 1, 0, 0, 0, 0, 0, 50, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #272 = G_STACKRESTORE
799 { 271, 1, 1, 0, 0, 0, 0, 50, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #271 = G_STACKSAVE
800 { 270, 3, 1, 0, 0, 0, 0, 69, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #270 = G_DYN_STACKALLOC
801 { 269, 2, 1, 0, 0, 0, 0, 51, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #269 = G_JUMP_TABLE
802 { 268, 2, 1, 0, 0, 0, 0, 51, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #268 = G_BLOCK_ADDR
803 { 267, 2, 1, 0, 0, 0, 0, 61, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #267 = G_ADDRSPACE_CAST
804 { 266, 2, 1, 0, 0, 0, 0, 67, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #266 = G_FNEARBYINT
805 { 265, 2, 1, 0, 0, 0, 0, 67, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #265 = G_FRINT
806 { 264, 2, 1, 0, 0, 0, 0, 67, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #264 = G_FFLOOR
807 { 263, 2, 1, 0, 0, 0, 0, 67, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #263 = G_FSQRT
808 { 262, 2, 1, 0, 0, 0, 0, 67, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #262 = G_FTANH
809 { 261, 2, 1, 0, 0, 0, 0, 67, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #261 = G_FSINH
810 { 260, 2, 1, 0, 0, 0, 0, 67, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #260 = G_FCOSH
811 { 259, 3, 1, 0, 0, 0, 0, 43, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #259 = G_FATAN2
812 { 258, 2, 1, 0, 0, 0, 0, 67, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #258 = G_FATAN
813 { 257, 2, 1, 0, 0, 0, 0, 67, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #257 = G_FASIN
814 { 256, 2, 1, 0, 0, 0, 0, 67, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #256 = G_FACOS
815 { 255, 2, 1, 0, 0, 0, 0, 67, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #255 = G_FTAN
816 { 254, 3, 2, 0, 0, 0, 0, 43, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #254 = G_FSINCOS
817 { 253, 2, 1, 0, 0, 0, 0, 67, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #253 = G_FSIN
818 { 252, 2, 1, 0, 0, 0, 0, 67, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #252 = G_FCOS
819 { 251, 2, 1, 0, 0, 0, 0, 67, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #251 = G_FCEIL
820 { 250, 2, 1, 0, 0, 0, 0, 67, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #250 = G_BITREVERSE
821 { 249, 2, 1, 0, 0, 0, 0, 67, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #249 = G_BSWAP
822 { 248, 2, 1, 0, 0, 0, 0, 61, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #248 = G_CTPOP
823 { 247, 2, 1, 0, 0, 0, 0, 61, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #247 = G_CTLZ_ZERO_UNDEF
824 { 246, 2, 1, 0, 0, 0, 0, 61, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #246 = G_CTLZ
825 { 245, 2, 1, 0, 0, 0, 0, 61, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #245 = G_CTTZ_ZERO_UNDEF
826 { 244, 2, 1, 0, 0, 0, 0, 61, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #244 = G_CTTZ
827 { 243, 4, 1, 0, 0, 0, 0, 138, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #243 = G_VECTOR_COMPRESS
828 { 242, 2, 1, 0, 0, 0, 0, 51, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #242 = G_STEP_VECTOR
829 { 241, 2, 1, 0, 0, 0, 0, 61, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #241 = G_SPLAT_VECTOR
830 { 240, 4, 1, 0, 0, 0, 0, 134, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #240 = G_SHUFFLE_VECTOR
831 { 239, 3, 1, 0, 0, 0, 0, 131, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #239 = G_EXTRACT_VECTOR_ELT
832 { 238, 4, 1, 0, 0, 0, 0, 127, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #238 = G_INSERT_VECTOR_ELT
833 { 237, 3, 1, 0, 0, 0, 0, 58, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #237 = G_EXTRACT_SUBVECTOR
834 { 236, 4, 1, 0, 0, 0, 0, 63, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #236 = G_INSERT_SUBVECTOR
835 { 235, 2, 1, 0, 0, 0, 0, 51, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #235 = G_VSCALE
836 { 234, 3, 0, 0, 0, 0, 0, 124, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #234 = G_BRJT
837 { 233, 1, 0, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #233 = G_BR
838 { 232, 2, 1, 0, 0, 0, 0, 61, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #232 = G_LLROUND
839 { 231, 2, 1, 0, 0, 0, 0, 61, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #231 = G_LROUND
840 { 230, 2, 1, 0, 0, 0, 0, 67, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #230 = G_ABS
841 { 229, 3, 1, 0, 0, 0, 0, 43, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #229 = G_UMAX
842 { 228, 3, 1, 0, 0, 0, 0, 43, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #228 = G_UMIN
843 { 227, 3, 1, 0, 0, 0, 0, 43, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #227 = G_SMAX
844 { 226, 3, 1, 0, 0, 0, 0, 43, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #226 = G_SMIN
845 { 225, 3, 1, 0, 0, 0, 0, 101, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #225 = G_PTRMASK
846 { 224, 3, 1, 0, 0, 0, 0, 101, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #224 = G_PTR_ADD
847 { 223, 0, 0, 0, 0, 0, 0, 1, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #223 = G_RESET_FPMODE
848 { 222, 1, 0, 0, 0, 0, 0, 50, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #222 = G_SET_FPMODE
849 { 221, 1, 1, 0, 0, 0, 0, 50, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #221 = G_GET_FPMODE
850 { 220, 0, 0, 0, 0, 0, 0, 1, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #220 = G_RESET_FPENV
851 { 219, 1, 0, 0, 0, 0, 0, 50, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #219 = G_SET_FPENV
852 { 218, 1, 1, 0, 0, 0, 0, 50, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #218 = G_GET_FPENV
853 { 217, 3, 1, 0, 0, 0, 0, 43, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #217 = G_FMAXIMUMNUM
854 { 216, 3, 1, 0, 0, 0, 0, 43, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #216 = G_FMINIMUMNUM
855 { 215, 3, 1, 0, 0, 0, 0, 43, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #215 = G_FMAXIMUM
856 { 214, 3, 1, 0, 0, 0, 0, 43, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #214 = G_FMINIMUM
857 { 213, 3, 1, 0, 0, 0, 0, 43, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #213 = G_FMAXNUM_IEEE
858 { 212, 3, 1, 0, 0, 0, 0, 43, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #212 = G_FMINNUM_IEEE
859 { 211, 3, 1, 0, 0, 0, 0, 43, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #211 = G_FMAXNUM
860 { 210, 3, 1, 0, 0, 0, 0, 43, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #210 = G_FMINNUM
861 { 209, 2, 1, 0, 0, 0, 0, 67, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #209 = G_FCANONICALIZE
862 { 208, 3, 1, 0, 0, 0, 0, 98, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #208 = G_IS_FPCLASS
863 { 207, 3, 1, 0, 0, 0, 0, 101, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #207 = G_FCOPYSIGN
864 { 206, 2, 1, 0, 0, 0, 0, 67, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #206 = G_FABS
865 { 205, 2, 1, 0, 0, 0, 0, 61, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #205 = G_FPTOUI_SAT
866 { 204, 2, 1, 0, 0, 0, 0, 61, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #204 = G_FPTOSI_SAT
867 { 203, 2, 1, 0, 0, 0, 0, 61, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #203 = G_UITOFP
868 { 202, 2, 1, 0, 0, 0, 0, 61, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #202 = G_SITOFP
869 { 201, 2, 1, 0, 0, 0, 0, 61, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #201 = G_FPTOUI
870 { 200, 2, 1, 0, 0, 0, 0, 61, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #200 = G_FPTOSI
871 { 199, 2, 1, 0, 0, 0, 0, 61, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #199 = G_FPTRUNC
872 { 198, 2, 1, 0, 0, 0, 0, 61, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #198 = G_FPEXT
873 { 197, 2, 1, 0, 0, 0, 0, 67, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #197 = G_FNEG
874 { 196, 3, 2, 0, 0, 0, 0, 91, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #196 = G_FFREXP
875 { 195, 3, 1, 0, 0, 0, 0, 101, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #195 = G_FLDEXP
876 { 194, 2, 1, 0, 0, 0, 0, 67, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #194 = G_FLOG10
877 { 193, 2, 1, 0, 0, 0, 0, 67, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #193 = G_FLOG2
878 { 192, 2, 1, 0, 0, 0, 0, 67, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #192 = G_FLOG
879 { 191, 2, 1, 0, 0, 0, 0, 67, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #191 = G_FEXP10
880 { 190, 2, 1, 0, 0, 0, 0, 67, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #190 = G_FEXP2
881 { 189, 2, 1, 0, 0, 0, 0, 67, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #189 = G_FEXP
882 { 188, 3, 1, 0, 0, 0, 0, 101, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #188 = G_FPOWI
883 { 187, 3, 1, 0, 0, 0, 0, 43, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #187 = G_FPOW
884 { 186, 3, 1, 0, 0, 0, 0, 43, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #186 = G_FREM
885 { 185, 3, 1, 0, 0, 0, 0, 43, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #185 = G_FDIV
886 { 184, 4, 1, 0, 0, 0, 0, 46, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #184 = G_FMAD
887 { 183, 4, 1, 0, 0, 0, 0, 46, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #183 = G_FMA
888 { 182, 3, 1, 0, 0, 0, 0, 43, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #182 = G_FMUL
889 { 181, 3, 1, 0, 0, 0, 0, 43, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #181 = G_FSUB
890 { 180, 3, 1, 0, 0, 0, 0, 43, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #180 = G_FADD
891 { 179, 4, 1, 0, 0, 0, 0, 120, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #179 = G_UDIVFIXSAT
892 { 178, 4, 1, 0, 0, 0, 0, 120, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #178 = G_SDIVFIXSAT
893 { 177, 4, 1, 0, 0, 0, 0, 120, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #177 = G_UDIVFIX
894 { 176, 4, 1, 0, 0, 0, 0, 120, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #176 = G_SDIVFIX
895 { 175, 4, 1, 0, 0, 0, 0, 120, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #175 = G_UMULFIXSAT
896 { 174, 4, 1, 0, 0, 0, 0, 120, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #174 = G_SMULFIXSAT
897 { 173, 4, 1, 0, 0, 0, 0, 120, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #173 = G_UMULFIX
898 { 172, 4, 1, 0, 0, 0, 0, 120, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #172 = G_SMULFIX
899 { 171, 3, 1, 0, 0, 0, 0, 101, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #171 = G_SSHLSAT
900 { 170, 3, 1, 0, 0, 0, 0, 101, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #170 = G_USHLSAT
901 { 169, 3, 1, 0, 0, 0, 0, 43, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #169 = G_SSUBSAT
902 { 168, 3, 1, 0, 0, 0, 0, 43, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #168 = G_USUBSAT
903 { 167, 3, 1, 0, 0, 0, 0, 43, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #167 = G_SADDSAT
904 { 166, 3, 1, 0, 0, 0, 0, 43, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #166 = G_UADDSAT
905 { 165, 3, 1, 0, 0, 0, 0, 43, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #165 = G_SMULH
906 { 164, 3, 1, 0, 0, 0, 0, 43, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #164 = G_UMULH
907 { 163, 4, 2, 0, 0, 0, 0, 87, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #163 = G_SMULO
908 { 162, 4, 2, 0, 0, 0, 0, 87, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #162 = G_UMULO
909 { 161, 5, 2, 0, 0, 0, 0, 115, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #161 = G_SSUBE
910 { 160, 4, 2, 0, 0, 0, 0, 87, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #160 = G_SSUBO
911 { 159, 5, 2, 0, 0, 0, 0, 115, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #159 = G_SADDE
912 { 158, 4, 2, 0, 0, 0, 0, 87, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #158 = G_SADDO
913 { 157, 5, 2, 0, 0, 0, 0, 115, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #157 = G_USUBE
914 { 156, 4, 2, 0, 0, 0, 0, 87, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #156 = G_USUBO
915 { 155, 5, 2, 0, 0, 0, 0, 115, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #155 = G_UADDE
916 { 154, 4, 2, 0, 0, 0, 0, 87, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #154 = G_UADDO
917 { 153, 4, 1, 0, 0, 0, 0, 87, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #153 = G_SELECT
918 { 152, 3, 1, 0, 0, 0, 0, 112, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #152 = G_UCMP
919 { 151, 3, 1, 0, 0, 0, 0, 112, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #151 = G_SCMP
920 { 150, 4, 1, 0, 0, 0, 0, 108, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #150 = G_FCMP
921 { 149, 4, 1, 0, 0, 0, 0, 108, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #149 = G_ICMP
922 { 148, 3, 1, 0, 0, 0, 0, 101, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #148 = G_ROTL
923 { 147, 3, 1, 0, 0, 0, 0, 101, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #147 = G_ROTR
924 { 146, 4, 1, 0, 0, 0, 0, 104, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #146 = G_FSHR
925 { 145, 4, 1, 0, 0, 0, 0, 104, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #145 = G_FSHL
926 { 144, 3, 1, 0, 0, 0, 0, 101, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #144 = G_ASHR
927 { 143, 3, 1, 0, 0, 0, 0, 101, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #143 = G_LSHR
928 { 142, 3, 1, 0, 0, 0, 0, 101, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #142 = G_SHL
929 { 141, 2, 1, 0, 0, 0, 0, 61, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #141 = G_ZEXT
930 { 140, 3, 1, 0, 0, 0, 0, 40, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #140 = G_SEXT_INREG
931 { 139, 2, 1, 0, 0, 0, 0, 61, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #139 = G_SEXT
932 { 138, 3, 1, 0, 0, 0, 0, 98, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #138 = G_VAARG
933 { 137, 1, 0, 0, 0, 0, 0, 50, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #137 = G_VASTART
934 { 136, 2, 1, 0, 0, 0, 0, 51, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #136 = G_FCONSTANT
935 { 135, 2, 1, 0, 0, 0, 0, 51, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #135 = G_CONSTANT
936 { 134, 2, 1, 0, 0, 0, 0, 61, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #134 = G_TRUNC
937 { 133, 2, 1, 0, 0, 0, 0, 61, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #133 = G_ANYEXT
938 { 132, 1, 0, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #132 = G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
939 { 131, 1, 0, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #131 = G_INTRINSIC_CONVERGENT
940 { 130, 1, 0, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #130 = G_INTRINSIC_W_SIDE_EFFECTS
941 { 129, 1, 0, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #129 = G_INTRINSIC
942 { 128, 0, 0, 0, 0, 0, 0, 1, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #128 = G_INVOKE_REGION_START
943 { 127, 1, 0, 0, 0, 0, 0, 50, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #127 = G_BRINDIRECT
944 { 126, 2, 0, 0, 0, 0, 0, 51, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #126 = G_BRCOND
945 { 125, 4, 0, 0, 0, 0, 0, 94, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #125 = G_PREFETCH
946 { 124, 2, 0, 0, 0, 0, 0, 21, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #124 = G_FENCE
947 { 123, 3, 1, 0, 0, 0, 0, 91, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #123 = G_ATOMICRMW_USUB_SAT
948 { 122, 3, 1, 0, 0, 0, 0, 91, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #122 = G_ATOMICRMW_USUB_COND
949 { 121, 3, 1, 0, 0, 0, 0, 91, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #121 = G_ATOMICRMW_UDEC_WRAP
950 { 120, 3, 1, 0, 0, 0, 0, 91, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #120 = G_ATOMICRMW_UINC_WRAP
951 { 119, 3, 1, 0, 0, 0, 0, 91, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #119 = G_ATOMICRMW_FMINIMUM
952 { 118, 3, 1, 0, 0, 0, 0, 91, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #118 = G_ATOMICRMW_FMAXIMUM
953 { 117, 3, 1, 0, 0, 0, 0, 91, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #117 = G_ATOMICRMW_FMIN
954 { 116, 3, 1, 0, 0, 0, 0, 91, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #116 = G_ATOMICRMW_FMAX
955 { 115, 3, 1, 0, 0, 0, 0, 91, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #115 = G_ATOMICRMW_FSUB
956 { 114, 3, 1, 0, 0, 0, 0, 91, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #114 = G_ATOMICRMW_FADD
957 { 113, 3, 1, 0, 0, 0, 0, 91, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #113 = G_ATOMICRMW_UMIN
958 { 112, 3, 1, 0, 0, 0, 0, 91, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #112 = G_ATOMICRMW_UMAX
959 { 111, 3, 1, 0, 0, 0, 0, 91, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #111 = G_ATOMICRMW_MIN
960 { 110, 3, 1, 0, 0, 0, 0, 91, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #110 = G_ATOMICRMW_MAX
961 { 109, 3, 1, 0, 0, 0, 0, 91, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #109 = G_ATOMICRMW_XOR
962 { 108, 3, 1, 0, 0, 0, 0, 91, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #108 = G_ATOMICRMW_OR
963 { 107, 3, 1, 0, 0, 0, 0, 91, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #107 = G_ATOMICRMW_NAND
964 { 106, 3, 1, 0, 0, 0, 0, 91, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #106 = G_ATOMICRMW_AND
965 { 105, 3, 1, 0, 0, 0, 0, 91, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #105 = G_ATOMICRMW_SUB
966 { 104, 3, 1, 0, 0, 0, 0, 91, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #104 = G_ATOMICRMW_ADD
967 { 103, 3, 1, 0, 0, 0, 0, 91, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #103 = G_ATOMICRMW_XCHG
968 { 102, 4, 1, 0, 0, 0, 0, 87, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #102 = G_ATOMIC_CMPXCHG
969 { 101, 5, 2, 0, 0, 0, 0, 82, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #101 = G_ATOMIC_CMPXCHG_WITH_SUCCESS
970 { 100, 5, 1, 0, 0, 0, 0, 77, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #100 = G_INDEXED_STORE
971 { 99, 2, 0, 0, 0, 0, 0, 61, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #99 = G_STORE
972 { 98, 5, 2, 0, 0, 0, 0, 72, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #98 = G_INDEXED_ZEXTLOAD
973 { 97, 5, 2, 0, 0, 0, 0, 72, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #97 = G_INDEXED_SEXTLOAD
974 { 96, 5, 2, 0, 0, 0, 0, 72, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #96 = G_INDEXED_LOAD
975 { 95, 2, 1, 0, 0, 0, 0, 61, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #95 = G_ZEXTLOAD
976 { 94, 2, 1, 0, 0, 0, 0, 61, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #94 = G_SEXTLOAD
977 { 93, 2, 1, 0, 0, 0, 0, 61, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #93 = G_LOAD
978 { 92, 1, 1, 0, 0, 0, 0, 50, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #92 = G_READSTEADYCOUNTER
979 { 91, 1, 1, 0, 0, 0, 0, 50, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #91 = G_READCYCLECOUNTER
980 { 90, 2, 1, 0, 0, 0, 0, 67, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #90 = G_INTRINSIC_ROUNDEVEN
981 { 89, 2, 1, 0, 0, 0, 0, 61, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #89 = G_INTRINSIC_LLRINT
982 { 88, 2, 1, 0, 0, 0, 0, 61, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #88 = G_INTRINSIC_LRINT
983 { 87, 2, 1, 0, 0, 0, 0, 67, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #87 = G_INTRINSIC_ROUND
984 { 86, 2, 1, 0, 0, 0, 0, 67, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #86 = G_INTRINSIC_TRUNC
985 { 85, 3, 1, 0, 0, 0, 0, 69, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #85 = G_INTRINSIC_FPTRUNC_ROUND
986 { 84, 2, 1, 0, 0, 0, 0, 67, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #84 = G_CONSTANT_FOLD_BARRIER
987 { 83, 2, 1, 0, 0, 0, 0, 67, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #83 = G_FREEZE
988 { 82, 2, 1, 0, 0, 0, 0, 61, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #82 = G_BITCAST
989 { 81, 2, 1, 0, 0, 0, 0, 61, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #81 = G_INTTOPTR
990 { 80, 2, 1, 0, 0, 0, 0, 61, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #80 = G_PTRTOINT
991 { 79, 2, 1, 0, 0, 0, 0, 61, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #79 = G_CONCAT_VECTORS
992 { 78, 2, 1, 0, 0, 0, 0, 61, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #78 = G_BUILD_VECTOR_TRUNC
993 { 77, 2, 1, 0, 0, 0, 0, 61, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #77 = G_BUILD_VECTOR
994 { 76, 2, 1, 0, 0, 0, 0, 61, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #76 = G_MERGE_VALUES
995 { 75, 4, 1, 0, 0, 0, 0, 63, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #75 = G_INSERT
996 { 74, 2, 1, 0, 0, 0, 0, 61, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #74 = G_UNMERGE_VALUES
997 { 73, 3, 1, 0, 0, 0, 0, 58, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #73 = G_EXTRACT
998 { 72, 2, 1, 0, 0, 0, 0, 51, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #72 = G_CONSTANT_POOL
999 { 71, 5, 1, 0, 0, 0, 0, 53, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #71 = G_PTRAUTH_GLOBAL_VALUE
1000 { 70, 2, 1, 0, 0, 0, 0, 51, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #70 = G_GLOBAL_VALUE
1001 { 69, 2, 1, 0, 0, 0, 0, 51, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #69 = G_FRAME_INDEX
1002 { 68, 1, 1, 0, 0, 0, 0, 50, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #68 = G_PHI
1003 { 67, 1, 1, 0, 0, 0, 0, 50, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #67 = G_IMPLICIT_DEF
1004 { 66, 3, 1, 0, 0, 0, 0, 43, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #66 = G_ABDU
1005 { 65, 3, 1, 0, 0, 0, 0, 43, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #65 = G_ABDS
1006 { 64, 3, 1, 0, 0, 0, 0, 43, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #64 = G_XOR
1007 { 63, 3, 1, 0, 0, 0, 0, 43, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #63 = G_OR
1008 { 62, 3, 1, 0, 0, 0, 0, 43, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #62 = G_AND
1009 { 61, 4, 2, 0, 0, 0, 0, 46, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #61 = G_UDIVREM
1010 { 60, 4, 2, 0, 0, 0, 0, 46, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #60 = G_SDIVREM
1011 { 59, 3, 1, 0, 0, 0, 0, 43, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #59 = G_UREM
1012 { 58, 3, 1, 0, 0, 0, 0, 43, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #58 = G_SREM
1013 { 57, 3, 1, 0, 0, 0, 0, 43, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #57 = G_UDIV
1014 { 56, 3, 1, 0, 0, 0, 0, 43, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #56 = G_SDIV
1015 { 55, 3, 1, 0, 0, 0, 0, 43, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #55 = G_MUL
1016 { 54, 3, 1, 0, 0, 0, 0, 43, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #54 = G_SUB
1017 { 53, 3, 1, 0, 0, 0, 0, 43, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #53 = G_ADD
1018 { 52, 3, 1, 0, 0, 0, 0, 40, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #52 = G_ASSERT_ALIGN
1019 { 51, 3, 1, 0, 0, 0, 0, 40, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #51 = G_ASSERT_ZEXT
1020 { 50, 3, 1, 0, 0, 0, 0, 40, BPFImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #50 = G_ASSERT_SEXT
1021 { 49, 1, 0, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #49 = CONVERGENCECTRL_GLUE
1022 { 48, 2, 1, 0, 0, 0, 0, 13, BPFImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #48 = CONVERGENCECTRL_LOOP
1023 { 47, 1, 1, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #47 = CONVERGENCECTRL_ANCHOR
1024 { 46, 1, 1, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #46 = CONVERGENCECTRL_ENTRY
1025 { 45, 1, 0, 0, 0, 0, 0, 1, BPFImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #45 = JUMP_TABLE_DEBUG_INFO
1026 { 44, 0, 0, 0, 0, 0, 0, 1, BPFImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #44 = MEMBARRIER
1027 { 43, 0, 0, 0, 0, 0, 0, 1, BPFImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #43 = FAKE_USE
1028 { 42, 0, 0, 0, 0, 0, 0, 1, BPFImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #42 = ICALL_BRANCH_FUNNEL
1029 { 41, 3, 0, 0, 0, 0, 0, 37, BPFImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #41 = PATCHABLE_TYPED_EVENT_CALL
1030 { 40, 2, 0, 0, 0, 0, 0, 35, BPFImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #40 = PATCHABLE_EVENT_CALL
1031 { 39, 0, 0, 0, 0, 0, 0, 1, BPFImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #39 = PATCHABLE_TAIL_CALL
1032 { 38, 0, 0, 0, 0, 0, 0, 1, BPFImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #38 = PATCHABLE_FUNCTION_EXIT
1033 { 37, 0, 0, 0, 0, 0, 0, 1, BPFImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #37 = PATCHABLE_RET
1034 { 36, 0, 0, 0, 0, 0, 0, 1, BPFImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #36 = PATCHABLE_FUNCTION_ENTER
1035 { 35, 0, 0, 0, 0, 0, 0, 1, BPFImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #35 = PATCHABLE_OP
1036 { 34, 1, 1, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #34 = FAULTING_OP
1037 { 33, 2, 0, 0, 0, 0, 0, 33, BPFImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #33 = LOCAL_ESCAPE
1038 { 32, 0, 0, 0, 0, 0, 0, 1, BPFImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #32 = STATEPOINT
1039 { 31, 3, 1, 0, 0, 0, 0, 30, BPFImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #31 = PREALLOCATED_ARG
1040 { 30, 1, 0, 0, 0, 0, 0, 1, BPFImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #30 = PREALLOCATED_SETUP
1041 { 29, 1, 1, 0, 0, 0, 0, 29, BPFImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #29 = LOAD_STACK_GUARD
1042 { 28, 6, 1, 0, 0, 0, 0, 23, BPFImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #28 = PATCHPOINT
1043 { 27, 0, 0, 0, 0, 0, 0, 1, BPFImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #27 = FENTRY_CALL
1044 { 26, 2, 0, 0, 0, 0, 0, 21, BPFImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #26 = STACKMAP
1045 { 25, 2, 1, 0, 0, 0, 0, 19, BPFImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #25 = ARITH_FENCE
1046 { 24, 4, 0, 0, 0, 0, 0, 15, BPFImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #24 = PSEUDO_PROBE
1047 { 23, 1, 0, 0, 0, 0, 0, 1, BPFImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #23 = LIFETIME_END
1048 { 22, 1, 0, 0, 0, 0, 0, 1, BPFImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #22 = LIFETIME_START
1049 { 21, 0, 0, 0, 0, 0, 0, 1, BPFImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #21 = BUNDLE
1050 { 20, 2, 1, 0, 0, 0, 0, 13, BPFImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #20 = COPY
1051 { 19, 2, 1, 0, 0, 0, 0, 13, BPFImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #19 = REG_SEQUENCE
1052 { 18, 1, 0, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #18 = DBG_LABEL
1053 { 17, 0, 0, 0, 0, 0, 0, 1, BPFImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #17 = DBG_PHI
1054 { 16, 0, 0, 0, 0, 0, 0, 1, BPFImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #16 = DBG_INSTR_REF
1055 { 15, 0, 0, 0, 0, 0, 0, 1, BPFImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #15 = DBG_VALUE_LIST
1056 { 14, 0, 0, 0, 0, 0, 0, 1, BPFImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #14 = DBG_VALUE
1057 { 13, 3, 1, 0, 0, 0, 0, 2, BPFImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #13 = COPY_TO_REGCLASS
1058 { 12, 4, 1, 0, 0, 0, 0, 9, BPFImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #12 = SUBREG_TO_REG
1059 { 11, 1, 1, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #11 = INIT_UNDEF
1060 { 10, 1, 1, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #10 = IMPLICIT_DEF
1061 { 9, 4, 1, 0, 0, 0, 0, 5, BPFImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #9 = INSERT_SUBREG
1062 { 8, 3, 1, 0, 0, 0, 0, 2, BPFImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #8 = EXTRACT_SUBREG
1063 { 7, 0, 0, 0, 0, 0, 0, 1, BPFImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #7 = KILL
1064 { 6, 1, 0, 0, 0, 0, 0, 1, BPFImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #6 = ANNOTATION_LABEL
1065 { 5, 1, 0, 0, 0, 0, 0, 1, BPFImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #5 = GC_LABEL
1066 { 4, 1, 0, 0, 0, 0, 0, 1, BPFImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #4 = EH_LABEL
1067 { 3, 1, 0, 0, 0, 0, 0, 1, BPFImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #3 = CFI_INSTRUCTION
1068 { 2, 0, 0, 0, 0, 0, 0, 1, BPFImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #2 = INLINEASM_BR
1069 { 1, 0, 0, 0, 0, 0, 0, 1, BPFImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1 = INLINEASM
1070 { 0, 1, 1, 0, 0, 0, 0, 0, BPFImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #0 = PHI
1071 }, {
1072 /* 0 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1073 /* 1 */
1074 /* 1 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1075 /* 2 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1076 /* 5 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1077 /* 9 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1078 /* 13 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1079 /* 15 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1080 /* 19 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) },
1081 /* 21 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1082 /* 23 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1083 /* 29 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 },
1084 /* 30 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1085 /* 33 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1086 /* 35 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1087 /* 37 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1088 /* 40 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1089 /* 43 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1090 /* 46 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1091 /* 50 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1092 /* 51 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1093 /* 53 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1094 /* 58 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1095 /* 61 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1096 /* 63 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1097 /* 67 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1098 /* 69 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1099 /* 72 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1100 /* 77 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1101 /* 82 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1102 /* 87 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1103 /* 91 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1104 /* 94 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1105 /* 98 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1106 /* 101 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1107 /* 104 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1108 /* 108 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1109 /* 112 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1110 /* 115 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1111 /* 120 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1112 /* 124 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1113 /* 127 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
1114 /* 131 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
1115 /* 134 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1116 /* 138 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1117 /* 142 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1118 /* 144 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1119 /* 148 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1120 /* 152 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1121 /* 155 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1122 /* 159 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1123 /* 165 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1124 /* 171 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1125 /* 177 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1126 /* 183 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1127 /* 189 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1128 /* 195 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1129 /* 201 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1130 /* 207 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1131 /* 210 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1132 /* 213 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1133 /* 216 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1134 /* 219 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
1135 /* 221 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1136 /* 224 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1137 /* 227 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1138 /* 231 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1139 /* 235 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1140 /* 239 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1141 /* 243 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1142 /* 244 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1143 /* 247 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1144 /* 250 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1145 /* 253 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1146 /* 256 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1147 /* 259 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1148 /* 261 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1149 /* 263 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1150 /* 265 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1151 /* 267 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1152 /* 269 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1153 /* 271 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
1154 /* 273 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1155 /* 276 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
1156 /* 280 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
1157 }, {
1158 /* 0 */
1159 /* 0 */ BPF::R11, BPF::R11,
1160 /* 2 */ BPF::R0, BPF::R0,
1161 /* 4 */ BPF::W0, BPF::W0,
1162 /* 6 */ BPF::R11,
1163 /* 7 */ BPF::R6, BPF::R0, BPF::R1, BPF::R2, BPF::R3, BPF::R4, BPF::R5,
1164 }
1165};
1166
1167
1168#ifdef __GNUC__
1169#pragma GCC diagnostic push
1170#pragma GCC diagnostic ignored "-Woverlength-strings"
1171#endif
1172extern const char BPFInstrNameData[] = {
1173 /* 0 */ "G_FLOG10\000"
1174 /* 9 */ "G_FEXP10\000"
1175 /* 18 */ "LDB32\000"
1176 /* 24 */ "STB32\000"
1177 /* 30 */ "CORE_LD32\000"
1178 /* 40 */ "BE32\000"
1179 /* 45 */ "LE32\000"
1180 /* 50 */ "LDH32\000"
1181 /* 56 */ "STH32\000"
1182 /* 62 */ "STBREL32\000"
1183 /* 71 */ "STHREL32\000"
1184 /* 80 */ "STWREL32\000"
1185 /* 89 */ "BSWAP32\000"
1186 /* 97 */ "LDBACQ32\000"
1187 /* 106 */ "LDHACQ32\000"
1188 /* 115 */ "LDWACQ32\000"
1189 /* 124 */ "XFADDW32\000"
1190 /* 133 */ "XADDW32\000"
1191 /* 141 */ "LDW32\000"
1192 /* 147 */ "XFANDW32\000"
1193 /* 156 */ "XANDW32\000"
1194 /* 164 */ "CMPXCHGW32\000"
1195 /* 175 */ "XFORW32\000"
1196 /* 183 */ "XFXORW32\000"
1197 /* 192 */ "XXORW32\000"
1198 /* 200 */ "STW32\000"
1199 /* 206 */ "Select_Ri_64_32\000"
1200 /* 222 */ "Select_64_32\000"
1201 /* 235 */ "NEG_32\000"
1202 /* 242 */ "Select_Ri_32\000"
1203 /* 255 */ "SRA_ri_32\000"
1204 /* 265 */ "SUB_ri_32\000"
1205 /* 275 */ "ADD_ri_32\000"
1206 /* 285 */ "AND_ri_32\000"
1207 /* 295 */ "SMOD_ri_32\000"
1208 /* 306 */ "JSGE_ri_32\000"
1209 /* 317 */ "JUGE_ri_32\000"
1210 /* 328 */ "JSLE_ri_32\000"
1211 /* 339 */ "JULE_ri_32\000"
1212 /* 350 */ "JNE_ri_32\000"
1213 /* 360 */ "SLL_ri_32\000"
1214 /* 370 */ "SRL_ri_32\000"
1215 /* 380 */ "MUL_ri_32\000"
1216 /* 390 */ "JEQ_ri_32\000"
1217 /* 400 */ "XOR_ri_32\000"
1218 /* 410 */ "JSET_ri_32\000"
1219 /* 421 */ "JSGT_ri_32\000"
1220 /* 432 */ "JUGT_ri_32\000"
1221 /* 443 */ "JSLT_ri_32\000"
1222 /* 454 */ "JULT_ri_32\000"
1223 /* 465 */ "SDIV_ri_32\000"
1224 /* 476 */ "MOV_ri_32\000"
1225 /* 486 */ "SRA_rr_32\000"
1226 /* 496 */ "SUB_rr_32\000"
1227 /* 506 */ "ADD_rr_32\000"
1228 /* 516 */ "AND_rr_32\000"
1229 /* 526 */ "SMOD_rr_32\000"
1230 /* 537 */ "JSGE_rr_32\000"
1231 /* 548 */ "JUGE_rr_32\000"
1232 /* 559 */ "JSLE_rr_32\000"
1233 /* 570 */ "JULE_rr_32\000"
1234 /* 581 */ "JNE_rr_32\000"
1235 /* 591 */ "SLL_rr_32\000"
1236 /* 601 */ "SRL_rr_32\000"
1237 /* 611 */ "MUL_rr_32\000"
1238 /* 621 */ "JEQ_rr_32\000"
1239 /* 631 */ "XOR_rr_32\000"
1240 /* 641 */ "JSET_rr_32\000"
1241 /* 652 */ "JSGT_rr_32\000"
1242 /* 663 */ "JUGT_rr_32\000"
1243 /* 674 */ "JSLT_rr_32\000"
1244 /* 685 */ "JULT_rr_32\000"
1245 /* 696 */ "SDIV_rr_32\000"
1246 /* 707 */ "MOV_rr_32\000"
1247 /* 717 */ "MOVSX_rr_32\000"
1248 /* 729 */ "Select_32\000"
1249 /* 739 */ "G_FLOG2\000"
1250 /* 747 */ "G_FATAN2\000"
1251 /* 756 */ "G_FEXP2\000"
1252 /* 764 */ "CORE_LD64\000"
1253 /* 774 */ "BE64\000"
1254 /* 779 */ "LE64\000"
1255 /* 784 */ "BSWAP64\000"
1256 /* 792 */ "MOV_32_64\000"
1257 /* 802 */ "Select_Ri_32_64\000"
1258 /* 818 */ "Select_32_64\000"
1259 /* 831 */ "NEG_64\000"
1260 /* 838 */ "LD_imm64\000"
1261 /* 847 */ "BE16\000"
1262 /* 852 */ "LE16\000"
1263 /* 857 */ "BSWAP16\000"
1264 /* 865 */ "MOVSX_rr_32_16\000"
1265 /* 880 */ "MOVSX_rr_16\000"
1266 /* 892 */ "MOVSX_rr_32_8\000"
1267 /* 906 */ "MOVSX_rr_8\000"
1268 /* 917 */ "G_FMA\000"
1269 /* 923 */ "G_STRICT_FMA\000"
1270 /* 936 */ "LDB\000"
1271 /* 940 */ "STB\000"
1272 /* 944 */ "G_FSUB\000"
1273 /* 951 */ "G_STRICT_FSUB\000"
1274 /* 965 */ "G_ATOMICRMW_FSUB\000"
1275 /* 982 */ "G_SUB\000"
1276 /* 988 */ "G_ATOMICRMW_SUB\000"
1277 /* 1004 */ "LD_IND_B\000"
1278 /* 1013 */ "LD_ABS_B\000"
1279 /* 1022 */ "G_INTRINSIC\000"
1280 /* 1034 */ "G_FPTRUNC\000"
1281 /* 1044 */ "G_INTRINSIC_TRUNC\000"
1282 /* 1062 */ "G_TRUNC\000"
1283 /* 1070 */ "G_BUILD_VECTOR_TRUNC\000"
1284 /* 1091 */ "G_DYN_STACKALLOC\000"
1285 /* 1108 */ "G_FMAD\000"
1286 /* 1115 */ "G_INDEXED_SEXTLOAD\000"
1287 /* 1134 */ "G_SEXTLOAD\000"
1288 /* 1145 */ "G_INDEXED_ZEXTLOAD\000"
1289 /* 1164 */ "G_ZEXTLOAD\000"
1290 /* 1175 */ "G_INDEXED_LOAD\000"
1291 /* 1190 */ "G_LOAD\000"
1292 /* 1197 */ "G_VECREDUCE_FADD\000"
1293 /* 1214 */ "G_FADD\000"
1294 /* 1221 */ "G_VECREDUCE_SEQ_FADD\000"
1295 /* 1242 */ "G_STRICT_FADD\000"
1296 /* 1256 */ "G_ATOMICRMW_FADD\000"
1297 /* 1273 */ "G_VECREDUCE_ADD\000"
1298 /* 1289 */ "G_ADD\000"
1299 /* 1295 */ "G_PTR_ADD\000"
1300 /* 1305 */ "G_ATOMICRMW_ADD\000"
1301 /* 1321 */ "XFADDD\000"
1302 /* 1328 */ "XADDD\000"
1303 /* 1334 */ "LDD\000"
1304 /* 1338 */ "XFANDD\000"
1305 /* 1345 */ "XANDD\000"
1306 /* 1351 */ "CMPXCHGD\000"
1307 /* 1360 */ "G_ATOMICRMW_NAND\000"
1308 /* 1377 */ "G_VECREDUCE_AND\000"
1309 /* 1393 */ "G_AND\000"
1310 /* 1399 */ "G_ATOMICRMW_AND\000"
1311 /* 1415 */ "LIFETIME_END\000"
1312 /* 1428 */ "JCOND\000"
1313 /* 1434 */ "G_BRCOND\000"
1314 /* 1443 */ "G_ATOMICRMW_USUB_COND\000"
1315 /* 1465 */ "G_LLROUND\000"
1316 /* 1475 */ "G_LROUND\000"
1317 /* 1484 */ "G_INTRINSIC_ROUND\000"
1318 /* 1502 */ "G_INTRINSIC_FPTRUNC_ROUND\000"
1319 /* 1528 */ "LOAD_STACK_GUARD\000"
1320 /* 1545 */ "XFORD\000"
1321 /* 1551 */ "XFXORD\000"
1322 /* 1558 */ "XXORD\000"
1323 /* 1564 */ "STD\000"
1324 /* 1568 */ "PSEUDO_PROBE\000"
1325 /* 1581 */ "G_SSUBE\000"
1326 /* 1589 */ "G_USUBE\000"
1327 /* 1597 */ "G_FENCE\000"
1328 /* 1605 */ "ARITH_FENCE\000"
1329 /* 1617 */ "REG_SEQUENCE\000"
1330 /* 1630 */ "G_SADDE\000"
1331 /* 1638 */ "G_UADDE\000"
1332 /* 1646 */ "G_GET_FPMODE\000"
1333 /* 1659 */ "G_RESET_FPMODE\000"
1334 /* 1674 */ "G_SET_FPMODE\000"
1335 /* 1687 */ "G_FMINNUM_IEEE\000"
1336 /* 1702 */ "G_FMAXNUM_IEEE\000"
1337 /* 1717 */ "G_VSCALE\000"
1338 /* 1726 */ "G_JUMP_TABLE\000"
1339 /* 1739 */ "BUNDLE\000"
1340 /* 1746 */ "G_MEMCPY_INLINE\000"
1341 /* 1762 */ "LOCAL_ESCAPE\000"
1342 /* 1775 */ "G_STACKRESTORE\000"
1343 /* 1790 */ "G_INDEXED_STORE\000"
1344 /* 1806 */ "G_STORE\000"
1345 /* 1814 */ "G_BITREVERSE\000"
1346 /* 1827 */ "FAKE_USE\000"
1347 /* 1836 */ "DBG_VALUE\000"
1348 /* 1846 */ "G_GLOBAL_VALUE\000"
1349 /* 1861 */ "G_PTRAUTH_GLOBAL_VALUE\000"
1350 /* 1884 */ "CONVERGENCECTRL_GLUE\000"
1351 /* 1905 */ "G_STACKSAVE\000"
1352 /* 1917 */ "G_MEMMOVE\000"
1353 /* 1927 */ "G_FREEZE\000"
1354 /* 1936 */ "G_FCANONICALIZE\000"
1355 /* 1952 */ "G_CTLZ_ZERO_UNDEF\000"
1356 /* 1970 */ "G_CTTZ_ZERO_UNDEF\000"
1357 /* 1988 */ "INIT_UNDEF\000"
1358 /* 1999 */ "G_IMPLICIT_DEF\000"
1359 /* 2014 */ "DBG_INSTR_REF\000"
1360 /* 2028 */ "G_FNEG\000"
1361 /* 2035 */ "EXTRACT_SUBREG\000"
1362 /* 2050 */ "INSERT_SUBREG\000"
1363 /* 2064 */ "G_SEXT_INREG\000"
1364 /* 2077 */ "SUBREG_TO_REG\000"
1365 /* 2091 */ "G_ATOMIC_CMPXCHG\000"
1366 /* 2108 */ "G_ATOMICRMW_XCHG\000"
1367 /* 2125 */ "G_FLOG\000"
1368 /* 2132 */ "G_VAARG\000"
1369 /* 2140 */ "PREALLOCATED_ARG\000"
1370 /* 2157 */ "G_PREFETCH\000"
1371 /* 2168 */ "LDH\000"
1372 /* 2172 */ "G_SMULH\000"
1373 /* 2180 */ "G_UMULH\000"
1374 /* 2188 */ "G_FTANH\000"
1375 /* 2196 */ "G_FSINH\000"
1376 /* 2204 */ "G_FCOSH\000"
1377 /* 2212 */ "STH\000"
1378 /* 2216 */ "LD_IND_H\000"
1379 /* 2225 */ "LD_ABS_H\000"
1380 /* 2234 */ "DBG_PHI\000"
1381 /* 2242 */ "G_FPTOSI\000"
1382 /* 2251 */ "G_FPTOUI\000"
1383 /* 2260 */ "G_FPOWI\000"
1384 /* 2268 */ "G_PTRMASK\000"
1385 /* 2278 */ "JAL\000"
1386 /* 2282 */ "GC_LABEL\000"
1387 /* 2291 */ "DBG_LABEL\000"
1388 /* 2301 */ "EH_LABEL\000"
1389 /* 2310 */ "ANNOTATION_LABEL\000"
1390 /* 2327 */ "ICALL_BRANCH_FUNNEL\000"
1391 /* 2347 */ "STDREL\000"
1392 /* 2354 */ "G_FSHL\000"
1393 /* 2361 */ "G_SHL\000"
1394 /* 2367 */ "G_FCEIL\000"
1395 /* 2375 */ "PATCHABLE_TAIL_CALL\000"
1396 /* 2395 */ "PATCHABLE_TYPED_EVENT_CALL\000"
1397 /* 2422 */ "PATCHABLE_EVENT_CALL\000"
1398 /* 2443 */ "FENTRY_CALL\000"
1399 /* 2455 */ "KILL\000"
1400 /* 2460 */ "G_CONSTANT_POOL\000"
1401 /* 2476 */ "JMPL\000"
1402 /* 2481 */ "G_ROTL\000"
1403 /* 2488 */ "G_VECREDUCE_FMUL\000"
1404 /* 2505 */ "G_FMUL\000"
1405 /* 2512 */ "G_VECREDUCE_SEQ_FMUL\000"
1406 /* 2533 */ "G_STRICT_FMUL\000"
1407 /* 2547 */ "G_VECREDUCE_MUL\000"
1408 /* 2563 */ "G_MUL\000"
1409 /* 2569 */ "G_FREM\000"
1410 /* 2576 */ "G_STRICT_FREM\000"
1411 /* 2590 */ "G_SREM\000"
1412 /* 2597 */ "G_UREM\000"
1413 /* 2604 */ "G_SDIVREM\000"
1414 /* 2614 */ "G_UDIVREM\000"
1415 /* 2624 */ "INLINEASM\000"
1416 /* 2634 */ "G_VECREDUCE_FMINIMUM\000"
1417 /* 2655 */ "G_FMINIMUM\000"
1418 /* 2666 */ "G_ATOMICRMW_FMINIMUM\000"
1419 /* 2687 */ "G_VECREDUCE_FMAXIMUM\000"
1420 /* 2708 */ "G_FMAXIMUM\000"
1421 /* 2719 */ "G_ATOMICRMW_FMAXIMUM\000"
1422 /* 2740 */ "G_FMINIMUMNUM\000"
1423 /* 2754 */ "G_FMAXIMUMNUM\000"
1424 /* 2768 */ "G_FMINNUM\000"
1425 /* 2778 */ "G_FMAXNUM\000"
1426 /* 2788 */ "G_FATAN\000"
1427 /* 2796 */ "G_FTAN\000"
1428 /* 2803 */ "G_INTRINSIC_ROUNDEVEN\000"
1429 /* 2825 */ "G_ASSERT_ALIGN\000"
1430 /* 2840 */ "G_FCOPYSIGN\000"
1431 /* 2852 */ "G_VECREDUCE_FMIN\000"
1432 /* 2869 */ "G_ATOMICRMW_FMIN\000"
1433 /* 2886 */ "G_VECREDUCE_SMIN\000"
1434 /* 2903 */ "G_SMIN\000"
1435 /* 2910 */ "G_VECREDUCE_UMIN\000"
1436 /* 2927 */ "G_UMIN\000"
1437 /* 2934 */ "G_ATOMICRMW_UMIN\000"
1438 /* 2951 */ "G_ATOMICRMW_MIN\000"
1439 /* 2967 */ "G_FASIN\000"
1440 /* 2975 */ "G_FSIN\000"
1441 /* 2982 */ "CFI_INSTRUCTION\000"
1442 /* 2998 */ "ADJCALLSTACKDOWN\000"
1443 /* 3015 */ "G_SSUBO\000"
1444 /* 3023 */ "G_USUBO\000"
1445 /* 3031 */ "G_SADDO\000"
1446 /* 3039 */ "G_UADDO\000"
1447 /* 3047 */ "JUMP_TABLE_DEBUG_INFO\000"
1448 /* 3069 */ "G_SMULO\000"
1449 /* 3077 */ "G_UMULO\000"
1450 /* 3085 */ "G_BZERO\000"
1451 /* 3093 */ "STACKMAP\000"
1452 /* 3102 */ "G_DEBUGTRAP\000"
1453 /* 3114 */ "G_UBSANTRAP\000"
1454 /* 3126 */ "G_TRAP\000"
1455 /* 3133 */ "G_ATOMICRMW_UDEC_WRAP\000"
1456 /* 3155 */ "G_ATOMICRMW_UINC_WRAP\000"
1457 /* 3177 */ "G_BSWAP\000"
1458 /* 3185 */ "G_SITOFP\000"
1459 /* 3194 */ "G_UITOFP\000"
1460 /* 3203 */ "G_FCMP\000"
1461 /* 3210 */ "G_ICMP\000"
1462 /* 3217 */ "G_SCMP\000"
1463 /* 3224 */ "G_UCMP\000"
1464 /* 3231 */ "JMP\000"
1465 /* 3235 */ "NOP\000"
1466 /* 3239 */ "CONVERGENCECTRL_LOOP\000"
1467 /* 3260 */ "G_CTPOP\000"
1468 /* 3268 */ "PATCHABLE_OP\000"
1469 /* 3281 */ "FAULTING_OP\000"
1470 /* 3293 */ "ADJCALLSTACKUP\000"
1471 /* 3308 */ "PREALLOCATED_SETUP\000"
1472 /* 3327 */ "G_FLDEXP\000"
1473 /* 3336 */ "G_STRICT_FLDEXP\000"
1474 /* 3352 */ "G_FEXP\000"
1475 /* 3359 */ "G_FFREXP\000"
1476 /* 3368 */ "LDDACQ\000"
1477 /* 3375 */ "G_BR\000"
1478 /* 3380 */ "INLINEASM_BR\000"
1479 /* 3393 */ "G_BLOCK_ADDR\000"
1480 /* 3406 */ "MEMBARRIER\000"
1481 /* 3417 */ "G_CONSTANT_FOLD_BARRIER\000"
1482 /* 3441 */ "PATCHABLE_FUNCTION_ENTER\000"
1483 /* 3466 */ "G_READCYCLECOUNTER\000"
1484 /* 3485 */ "G_READSTEADYCOUNTER\000"
1485 /* 3505 */ "G_READ_REGISTER\000"
1486 /* 3521 */ "G_WRITE_REGISTER\000"
1487 /* 3538 */ "G_ASHR\000"
1488 /* 3545 */ "G_FSHR\000"
1489 /* 3552 */ "G_LSHR\000"
1490 /* 3559 */ "CONVERGENCECTRL_ANCHOR\000"
1491 /* 3582 */ "G_FFLOOR\000"
1492 /* 3591 */ "G_EXTRACT_SUBVECTOR\000"
1493 /* 3611 */ "G_INSERT_SUBVECTOR\000"
1494 /* 3630 */ "G_BUILD_VECTOR\000"
1495 /* 3645 */ "G_SHUFFLE_VECTOR\000"
1496 /* 3662 */ "G_STEP_VECTOR\000"
1497 /* 3676 */ "G_SPLAT_VECTOR\000"
1498 /* 3691 */ "G_VECREDUCE_XOR\000"
1499 /* 3707 */ "G_XOR\000"
1500 /* 3713 */ "G_ATOMICRMW_XOR\000"
1501 /* 3729 */ "G_VECREDUCE_OR\000"
1502 /* 3744 */ "G_OR\000"
1503 /* 3749 */ "G_ATOMICRMW_OR\000"
1504 /* 3764 */ "G_ROTR\000"
1505 /* 3771 */ "G_INTTOPTR\000"
1506 /* 3782 */ "G_FABS\000"
1507 /* 3789 */ "G_ABS\000"
1508 /* 3795 */ "G_ABDS\000"
1509 /* 3802 */ "G_UNMERGE_VALUES\000"
1510 /* 3819 */ "G_MERGE_VALUES\000"
1511 /* 3834 */ "G_FACOS\000"
1512 /* 3842 */ "G_FCOS\000"
1513 /* 3849 */ "G_FSINCOS\000"
1514 /* 3859 */ "G_CONCAT_VECTORS\000"
1515 /* 3876 */ "COPY_TO_REGCLASS\000"
1516 /* 3893 */ "G_IS_FPCLASS\000"
1517 /* 3906 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\000"
1518 /* 3936 */ "G_VECTOR_COMPRESS\000"
1519 /* 3954 */ "G_INTRINSIC_W_SIDE_EFFECTS\000"
1520 /* 3981 */ "G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS\000"
1521 /* 4019 */ "G_SSUBSAT\000"
1522 /* 4029 */ "G_USUBSAT\000"
1523 /* 4039 */ "G_SADDSAT\000"
1524 /* 4049 */ "G_UADDSAT\000"
1525 /* 4059 */ "G_SSHLSAT\000"
1526 /* 4069 */ "G_USHLSAT\000"
1527 /* 4079 */ "G_SMULFIXSAT\000"
1528 /* 4092 */ "G_UMULFIXSAT\000"
1529 /* 4105 */ "G_SDIVFIXSAT\000"
1530 /* 4118 */ "G_UDIVFIXSAT\000"
1531 /* 4131 */ "G_ATOMICRMW_USUB_SAT\000"
1532 /* 4152 */ "G_FPTOSI_SAT\000"
1533 /* 4165 */ "G_FPTOUI_SAT\000"
1534 /* 4178 */ "G_EXTRACT\000"
1535 /* 4188 */ "G_SELECT\000"
1536 /* 4197 */ "G_BRINDIRECT\000"
1537 /* 4210 */ "PATCHABLE_RET\000"
1538 /* 4224 */ "G_MEMSET\000"
1539 /* 4233 */ "CORE_SHIFT\000"
1540 /* 4244 */ "PATCHABLE_FUNCTION_EXIT\000"
1541 /* 4268 */ "G_BRJT\000"
1542 /* 4275 */ "G_EXTRACT_VECTOR_ELT\000"
1543 /* 4296 */ "G_INSERT_VECTOR_ELT\000"
1544 /* 4316 */ "G_FCONSTANT\000"
1545 /* 4328 */ "G_CONSTANT\000"
1546 /* 4339 */ "G_INTRINSIC_CONVERGENT\000"
1547 /* 4362 */ "STATEPOINT\000"
1548 /* 4373 */ "PATCHPOINT\000"
1549 /* 4384 */ "G_PTRTOINT\000"
1550 /* 4395 */ "G_FRINT\000"
1551 /* 4403 */ "G_INTRINSIC_LLRINT\000"
1552 /* 4422 */ "G_INTRINSIC_LRINT\000"
1553 /* 4440 */ "G_FNEARBYINT\000"
1554 /* 4453 */ "G_VASTART\000"
1555 /* 4463 */ "LIFETIME_START\000"
1556 /* 4478 */ "G_INVOKE_REGION_START\000"
1557 /* 4500 */ "G_INSERT\000"
1558 /* 4509 */ "G_FSQRT\000"
1559 /* 4517 */ "G_STRICT_FSQRT\000"
1560 /* 4532 */ "G_BITCAST\000"
1561 /* 4542 */ "G_ADDRSPACE_CAST\000"
1562 /* 4559 */ "ADDR_SPACE_CAST\000"
1563 /* 4575 */ "DBG_VALUE_LIST\000"
1564 /* 4590 */ "CORE_ST\000"
1565 /* 4598 */ "G_FPEXT\000"
1566 /* 4606 */ "G_SEXT\000"
1567 /* 4613 */ "G_ASSERT_SEXT\000"
1568 /* 4627 */ "G_ANYEXT\000"
1569 /* 4636 */ "G_ZEXT\000"
1570 /* 4643 */ "G_ASSERT_ZEXT\000"
1571 /* 4657 */ "G_ABDU\000"
1572 /* 4664 */ "G_FDIV\000"
1573 /* 4671 */ "G_STRICT_FDIV\000"
1574 /* 4685 */ "G_SDIV\000"
1575 /* 4692 */ "G_UDIV\000"
1576 /* 4699 */ "G_GET_FPENV\000"
1577 /* 4711 */ "G_RESET_FPENV\000"
1578 /* 4725 */ "G_SET_FPENV\000"
1579 /* 4737 */ "XADDW\000"
1580 /* 4743 */ "LDW\000"
1581 /* 4747 */ "G_FPOW\000"
1582 /* 4754 */ "STW\000"
1583 /* 4758 */ "LD_IND_W\000"
1584 /* 4767 */ "LD_ABS_W\000"
1585 /* 4776 */ "G_VECREDUCE_FMAX\000"
1586 /* 4793 */ "G_ATOMICRMW_FMAX\000"
1587 /* 4810 */ "G_VECREDUCE_SMAX\000"
1588 /* 4827 */ "G_SMAX\000"
1589 /* 4834 */ "G_VECREDUCE_UMAX\000"
1590 /* 4851 */ "G_UMAX\000"
1591 /* 4858 */ "G_ATOMICRMW_UMAX\000"
1592 /* 4875 */ "G_ATOMICRMW_MAX\000"
1593 /* 4891 */ "G_FRAME_INDEX\000"
1594 /* 4905 */ "G_SBFX\000"
1595 /* 4912 */ "G_UBFX\000"
1596 /* 4919 */ "G_SMULFIX\000"
1597 /* 4929 */ "G_UMULFIX\000"
1598 /* 4939 */ "G_SDIVFIX\000"
1599 /* 4949 */ "G_UDIVFIX\000"
1600 /* 4959 */ "JALX\000"
1601 /* 4964 */ "LDBSX\000"
1602 /* 4970 */ "LDHSX\000"
1603 /* 4976 */ "LDWSX\000"
1604 /* 4982 */ "G_MEMCPY\000"
1605 /* 4991 */ "COPY\000"
1606 /* 4996 */ "CONVERGENCECTRL_ENTRY\000"
1607 /* 5018 */ "G_CTLZ\000"
1608 /* 5025 */ "G_CTTZ\000"
1609 /* 5032 */ "Select_Ri\000"
1610 /* 5042 */ "SRA_ri\000"
1611 /* 5049 */ "SUB_ri\000"
1612 /* 5056 */ "ADD_ri\000"
1613 /* 5063 */ "AND_ri\000"
1614 /* 5070 */ "SMOD_ri\000"
1615 /* 5078 */ "JSGE_ri\000"
1616 /* 5086 */ "JUGE_ri\000"
1617 /* 5094 */ "JSLE_ri\000"
1618 /* 5102 */ "JULE_ri\000"
1619 /* 5110 */ "JNE_ri\000"
1620 /* 5117 */ "FI_ri\000"
1621 /* 5123 */ "SLL_ri\000"
1622 /* 5130 */ "SRL_ri\000"
1623 /* 5137 */ "MUL_ri\000"
1624 /* 5144 */ "JEQ_ri\000"
1625 /* 5151 */ "XOR_ri\000"
1626 /* 5158 */ "JSET_ri\000"
1627 /* 5166 */ "JSGT_ri\000"
1628 /* 5174 */ "JUGT_ri\000"
1629 /* 5182 */ "JSLT_ri\000"
1630 /* 5190 */ "JULT_ri\000"
1631 /* 5198 */ "SDIV_ri\000"
1632 /* 5206 */ "MOV_ri\000"
1633 /* 5213 */ "STB_imm\000"
1634 /* 5221 */ "STD_imm\000"
1635 /* 5229 */ "STH_imm\000"
1636 /* 5237 */ "STW_imm\000"
1637 /* 5245 */ "LD_pseudo\000"
1638 /* 5255 */ "SRA_rr\000"
1639 /* 5262 */ "SUB_rr\000"
1640 /* 5269 */ "ADD_rr\000"
1641 /* 5276 */ "AND_rr\000"
1642 /* 5283 */ "SMOD_rr\000"
1643 /* 5291 */ "JSGE_rr\000"
1644 /* 5299 */ "JUGE_rr\000"
1645 /* 5307 */ "JSLE_rr\000"
1646 /* 5315 */ "JULE_rr\000"
1647 /* 5323 */ "JNE_rr\000"
1648 /* 5330 */ "SLL_rr\000"
1649 /* 5337 */ "SRL_rr\000"
1650 /* 5344 */ "MUL_rr\000"
1651 /* 5351 */ "JEQ_rr\000"
1652 /* 5358 */ "XOR_rr\000"
1653 /* 5365 */ "JSET_rr\000"
1654 /* 5373 */ "JSGT_rr\000"
1655 /* 5381 */ "JUGT_rr\000"
1656 /* 5389 */ "JSLT_rr\000"
1657 /* 5397 */ "JULT_rr\000"
1658 /* 5405 */ "SDIV_rr\000"
1659 /* 5413 */ "MOV_rr\000"
1660 /* 5420 */ "Select\000"
1661};
1662#ifdef __GNUC__
1663#pragma GCC diagnostic pop
1664#endif
1665
1666extern const unsigned BPFInstrNameIndices[] = {
1667 2238U, 2624U, 3380U, 2982U, 2301U, 2282U, 2310U, 2455U,
1668 2035U, 2050U, 2001U, 1988U, 2077U, 3876U, 1836U, 4575U,
1669 2014U, 2234U, 2291U, 1617U, 4991U, 1739U, 4463U, 1415U,
1670 1568U, 1605U, 3093U, 2443U, 4373U, 1528U, 3308U, 2140U,
1671 4362U, 1762U, 3281U, 3268U, 3441U, 4210U, 4244U, 2375U,
1672 2422U, 2395U, 2327U, 1827U, 3406U, 3047U, 4996U, 3559U,
1673 3239U, 1884U, 4613U, 4643U, 2825U, 1289U, 982U, 2563U,
1674 4685U, 4692U, 2590U, 2597U, 2604U, 2614U, 1393U, 3744U,
1675 3707U, 3795U, 4657U, 1999U, 2236U, 4891U, 1846U, 1861U,
1676 2460U, 4178U, 3802U, 4500U, 3819U, 3630U, 1070U, 3859U,
1677 4384U, 3771U, 4532U, 1927U, 3417U, 1502U, 1044U, 1484U,
1678 4422U, 4403U, 2803U, 3466U, 3485U, 1190U, 1134U, 1164U,
1679 1175U, 1115U, 1145U, 1806U, 1790U, 3906U, 2091U, 2108U,
1680 1305U, 988U, 1399U, 1360U, 3749U, 3713U, 4875U, 2951U,
1681 4858U, 2934U, 1256U, 965U, 4793U, 2869U, 2719U, 2666U,
1682 3155U, 3133U, 1443U, 4131U, 1597U, 2157U, 1434U, 4197U,
1683 4478U, 1022U, 3954U, 4339U, 3981U, 4627U, 1062U, 4328U,
1684 4316U, 4453U, 2132U, 4606U, 2064U, 4636U, 2361U, 3552U,
1685 3538U, 2354U, 3545U, 3764U, 2481U, 3210U, 3203U, 3217U,
1686 3224U, 4188U, 3039U, 1638U, 3023U, 1589U, 3031U, 1630U,
1687 3015U, 1581U, 3077U, 3069U, 2180U, 2172U, 4049U, 4039U,
1688 4029U, 4019U, 4069U, 4059U, 4919U, 4929U, 4079U, 4092U,
1689 4939U, 4949U, 4105U, 4118U, 1214U, 944U, 2505U, 917U,
1690 1108U, 4664U, 2569U, 4747U, 2260U, 3352U, 756U, 9U,
1691 2125U, 739U, 0U, 3327U, 3359U, 2028U, 4598U, 1034U,
1692 2242U, 2251U, 3185U, 3194U, 4152U, 4165U, 3782U, 2840U,
1693 3893U, 1936U, 2768U, 2778U, 1687U, 1702U, 2655U, 2708U,
1694 2740U, 2754U, 4699U, 4725U, 4711U, 1646U, 1674U, 1659U,
1695 1295U, 2268U, 2903U, 4827U, 2927U, 4851U, 3789U, 1475U,
1696 1465U, 3375U, 4268U, 1717U, 3611U, 3591U, 4296U, 4275U,
1697 3645U, 3676U, 3662U, 3936U, 5025U, 1970U, 5018U, 1952U,
1698 3260U, 3177U, 1814U, 2367U, 3842U, 2975U, 3849U, 2796U,
1699 3834U, 2967U, 2788U, 747U, 2204U, 2196U, 2188U, 4509U,
1700 3582U, 4395U, 4440U, 4542U, 3393U, 1726U, 1091U, 1905U,
1701 1775U, 1242U, 951U, 2533U, 4671U, 2576U, 923U, 4517U,
1702 3336U, 3505U, 3521U, 4982U, 1746U, 1917U, 4224U, 3085U,
1703 3126U, 3102U, 3114U, 1221U, 2512U, 1197U, 2488U, 4776U,
1704 2852U, 2687U, 2634U, 1273U, 2547U, 1377U, 3729U, 3691U,
1705 4810U, 2886U, 4834U, 2910U, 4905U, 4912U, 2998U, 3293U,
1706 5117U, 4984U, 5420U, 729U, 818U, 222U, 5032U, 242U,
1707 802U, 206U, 4559U, 5056U, 275U, 5269U, 506U, 5063U,
1708 285U, 5276U, 516U, 847U, 40U, 774U, 857U, 89U,
1709 784U, 1351U, 164U, 30U, 764U, 4233U, 4590U, 5199U,
1710 466U, 5406U, 697U, 2278U, 4959U, 1428U, 5144U, 390U,
1711 5351U, 621U, 3231U, 2476U, 5110U, 350U, 5323U, 581U,
1712 5158U, 410U, 5365U, 641U, 5078U, 306U, 5291U, 537U,
1713 5166U, 421U, 5373U, 652U, 5094U, 328U, 5307U, 559U,
1714 5182U, 443U, 5389U, 674U, 5086U, 317U, 5299U, 548U,
1715 5174U, 432U, 5381U, 663U, 5102U, 339U, 5315U, 570U,
1716 5190U, 454U, 5397U, 685U, 936U, 18U, 97U, 4964U,
1717 1334U, 3368U, 2168U, 50U, 106U, 4970U, 4743U, 141U,
1718 115U, 4976U, 1013U, 2225U, 4767U, 1004U, 2216U, 4758U,
1719 838U, 5245U, 852U, 45U, 779U, 5071U, 296U, 5284U,
1720 527U, 880U, 717U, 865U, 892U, 906U, 792U, 5206U,
1721 476U, 5413U, 707U, 5137U, 380U, 5344U, 611U, 235U,
1722 831U, 3235U, 5152U, 401U, 5359U, 632U, 4220U, 5198U,
1723 465U, 5405U, 696U, 5123U, 360U, 5330U, 591U, 5070U,
1724 295U, 5283U, 526U, 5042U, 255U, 5255U, 486U, 5130U,
1725 370U, 5337U, 601U, 940U, 24U, 62U, 5213U, 1564U,
1726 2347U, 5221U, 2212U, 56U, 71U, 5229U, 4754U, 200U,
1727 80U, 5237U, 5049U, 265U, 5262U, 496U, 1328U, 4737U,
1728 133U, 1345U, 156U, 1354U, 167U, 1321U, 124U, 1338U,
1729 147U, 1545U, 175U, 1551U, 183U, 1553U, 185U, 5151U,
1730 400U, 5358U, 631U, 1558U, 192U,
1731};
1732
1733static inline void InitBPFMCInstrInfo(MCInstrInfo *II) {
1734 II->InitMCInstrInfo(BPFDescs.Insts, BPFInstrNameIndices, BPFInstrNameData, nullptr, nullptr, 509);
1735}
1736
1737} // end namespace llvm
1738#endif // GET_INSTRINFO_MC_DESC
1739
1740#ifdef GET_INSTRINFO_HEADER
1741#undef GET_INSTRINFO_HEADER
1742namespace llvm {
1743struct BPFGenInstrInfo : public TargetInstrInfo {
1744 explicit BPFGenInstrInfo(unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u);
1745 ~BPFGenInstrInfo() override = default;
1746
1747};
1748} // end namespace llvm
1749#endif // GET_INSTRINFO_HEADER
1750
1751#ifdef GET_INSTRINFO_HELPER_DECLS
1752#undef GET_INSTRINFO_HELPER_DECLS
1753
1754
1755#endif // GET_INSTRINFO_HELPER_DECLS
1756
1757#ifdef GET_INSTRINFO_HELPERS
1758#undef GET_INSTRINFO_HELPERS
1759
1760#endif // GET_INSTRINFO_HELPERS
1761
1762#ifdef GET_INSTRINFO_CTOR_DTOR
1763#undef GET_INSTRINFO_CTOR_DTOR
1764namespace llvm {
1765extern const BPFInstrTable BPFDescs;
1766extern const unsigned BPFInstrNameIndices[];
1767extern const char BPFInstrNameData[];
1768BPFGenInstrInfo::BPFGenInstrInfo(unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode)
1769 : TargetInstrInfo(CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {
1770 InitMCInstrInfo(BPFDescs.Insts, BPFInstrNameIndices, BPFInstrNameData, nullptr, nullptr, 509);
1771}
1772} // end namespace llvm
1773#endif // GET_INSTRINFO_CTOR_DTOR
1774
1775#ifdef GET_INSTRINFO_MC_HELPER_DECLS
1776#undef GET_INSTRINFO_MC_HELPER_DECLS
1777
1778namespace llvm {
1779class MCInst;
1780class FeatureBitset;
1781
1782namespace BPF_MC {
1783
1784void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features);
1785
1786} // end namespace BPF_MC
1787} // end namespace llvm
1788
1789#endif // GET_INSTRINFO_MC_HELPER_DECLS
1790
1791#ifdef GET_INSTRINFO_MC_HELPERS
1792#undef GET_INSTRINFO_MC_HELPERS
1793
1794namespace llvm::BPF_MC {
1795} // end namespace llvm::BPF_MC
1796#endif // GET_GENISTRINFO_MC_HELPERS
1797
1798#if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) ||\
1799 defined(GET_AVAILABLE_OPCODE_CHECKER)
1800#define GET_COMPUTE_FEATURES
1801#endif
1802#ifdef GET_COMPUTE_FEATURES
1803#undef GET_COMPUTE_FEATURES
1804namespace llvm::BPF_MC {
1805// Bits for subtarget features that participate in instruction matching.
1806enum SubtargetFeatureBits : uint8_t {
1807};
1808
1809inline FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) {
1810 FeatureBitset Features;
1811 return Features;
1812}
1813
1814inline FeatureBitset computeRequiredFeatures(unsigned Opcode) {
1815 enum : uint8_t {
1816 CEFBS_None,
1817 };
1818
1819 static constexpr FeatureBitset FeatureBitsets[] = {
1820 {}, // CEFBS_None
1821 };
1822 static constexpr uint8_t RequiredFeaturesRefs[] = {
1823 CEFBS_None, // PHI = 0
1824 CEFBS_None, // INLINEASM = 1
1825 CEFBS_None, // INLINEASM_BR = 2
1826 CEFBS_None, // CFI_INSTRUCTION = 3
1827 CEFBS_None, // EH_LABEL = 4
1828 CEFBS_None, // GC_LABEL = 5
1829 CEFBS_None, // ANNOTATION_LABEL = 6
1830 CEFBS_None, // KILL = 7
1831 CEFBS_None, // EXTRACT_SUBREG = 8
1832 CEFBS_None, // INSERT_SUBREG = 9
1833 CEFBS_None, // IMPLICIT_DEF = 10
1834 CEFBS_None, // INIT_UNDEF = 11
1835 CEFBS_None, // SUBREG_TO_REG = 12
1836 CEFBS_None, // COPY_TO_REGCLASS = 13
1837 CEFBS_None, // DBG_VALUE = 14
1838 CEFBS_None, // DBG_VALUE_LIST = 15
1839 CEFBS_None, // DBG_INSTR_REF = 16
1840 CEFBS_None, // DBG_PHI = 17
1841 CEFBS_None, // DBG_LABEL = 18
1842 CEFBS_None, // REG_SEQUENCE = 19
1843 CEFBS_None, // COPY = 20
1844 CEFBS_None, // BUNDLE = 21
1845 CEFBS_None, // LIFETIME_START = 22
1846 CEFBS_None, // LIFETIME_END = 23
1847 CEFBS_None, // PSEUDO_PROBE = 24
1848 CEFBS_None, // ARITH_FENCE = 25
1849 CEFBS_None, // STACKMAP = 26
1850 CEFBS_None, // FENTRY_CALL = 27
1851 CEFBS_None, // PATCHPOINT = 28
1852 CEFBS_None, // LOAD_STACK_GUARD = 29
1853 CEFBS_None, // PREALLOCATED_SETUP = 30
1854 CEFBS_None, // PREALLOCATED_ARG = 31
1855 CEFBS_None, // STATEPOINT = 32
1856 CEFBS_None, // LOCAL_ESCAPE = 33
1857 CEFBS_None, // FAULTING_OP = 34
1858 CEFBS_None, // PATCHABLE_OP = 35
1859 CEFBS_None, // PATCHABLE_FUNCTION_ENTER = 36
1860 CEFBS_None, // PATCHABLE_RET = 37
1861 CEFBS_None, // PATCHABLE_FUNCTION_EXIT = 38
1862 CEFBS_None, // PATCHABLE_TAIL_CALL = 39
1863 CEFBS_None, // PATCHABLE_EVENT_CALL = 40
1864 CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL = 41
1865 CEFBS_None, // ICALL_BRANCH_FUNNEL = 42
1866 CEFBS_None, // FAKE_USE = 43
1867 CEFBS_None, // MEMBARRIER = 44
1868 CEFBS_None, // JUMP_TABLE_DEBUG_INFO = 45
1869 CEFBS_None, // CONVERGENCECTRL_ENTRY = 46
1870 CEFBS_None, // CONVERGENCECTRL_ANCHOR = 47
1871 CEFBS_None, // CONVERGENCECTRL_LOOP = 48
1872 CEFBS_None, // CONVERGENCECTRL_GLUE = 49
1873 CEFBS_None, // G_ASSERT_SEXT = 50
1874 CEFBS_None, // G_ASSERT_ZEXT = 51
1875 CEFBS_None, // G_ASSERT_ALIGN = 52
1876 CEFBS_None, // G_ADD = 53
1877 CEFBS_None, // G_SUB = 54
1878 CEFBS_None, // G_MUL = 55
1879 CEFBS_None, // G_SDIV = 56
1880 CEFBS_None, // G_UDIV = 57
1881 CEFBS_None, // G_SREM = 58
1882 CEFBS_None, // G_UREM = 59
1883 CEFBS_None, // G_SDIVREM = 60
1884 CEFBS_None, // G_UDIVREM = 61
1885 CEFBS_None, // G_AND = 62
1886 CEFBS_None, // G_OR = 63
1887 CEFBS_None, // G_XOR = 64
1888 CEFBS_None, // G_ABDS = 65
1889 CEFBS_None, // G_ABDU = 66
1890 CEFBS_None, // G_IMPLICIT_DEF = 67
1891 CEFBS_None, // G_PHI = 68
1892 CEFBS_None, // G_FRAME_INDEX = 69
1893 CEFBS_None, // G_GLOBAL_VALUE = 70
1894 CEFBS_None, // G_PTRAUTH_GLOBAL_VALUE = 71
1895 CEFBS_None, // G_CONSTANT_POOL = 72
1896 CEFBS_None, // G_EXTRACT = 73
1897 CEFBS_None, // G_UNMERGE_VALUES = 74
1898 CEFBS_None, // G_INSERT = 75
1899 CEFBS_None, // G_MERGE_VALUES = 76
1900 CEFBS_None, // G_BUILD_VECTOR = 77
1901 CEFBS_None, // G_BUILD_VECTOR_TRUNC = 78
1902 CEFBS_None, // G_CONCAT_VECTORS = 79
1903 CEFBS_None, // G_PTRTOINT = 80
1904 CEFBS_None, // G_INTTOPTR = 81
1905 CEFBS_None, // G_BITCAST = 82
1906 CEFBS_None, // G_FREEZE = 83
1907 CEFBS_None, // G_CONSTANT_FOLD_BARRIER = 84
1908 CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND = 85
1909 CEFBS_None, // G_INTRINSIC_TRUNC = 86
1910 CEFBS_None, // G_INTRINSIC_ROUND = 87
1911 CEFBS_None, // G_INTRINSIC_LRINT = 88
1912 CEFBS_None, // G_INTRINSIC_LLRINT = 89
1913 CEFBS_None, // G_INTRINSIC_ROUNDEVEN = 90
1914 CEFBS_None, // G_READCYCLECOUNTER = 91
1915 CEFBS_None, // G_READSTEADYCOUNTER = 92
1916 CEFBS_None, // G_LOAD = 93
1917 CEFBS_None, // G_SEXTLOAD = 94
1918 CEFBS_None, // G_ZEXTLOAD = 95
1919 CEFBS_None, // G_INDEXED_LOAD = 96
1920 CEFBS_None, // G_INDEXED_SEXTLOAD = 97
1921 CEFBS_None, // G_INDEXED_ZEXTLOAD = 98
1922 CEFBS_None, // G_STORE = 99
1923 CEFBS_None, // G_INDEXED_STORE = 100
1924 CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS = 101
1925 CEFBS_None, // G_ATOMIC_CMPXCHG = 102
1926 CEFBS_None, // G_ATOMICRMW_XCHG = 103
1927 CEFBS_None, // G_ATOMICRMW_ADD = 104
1928 CEFBS_None, // G_ATOMICRMW_SUB = 105
1929 CEFBS_None, // G_ATOMICRMW_AND = 106
1930 CEFBS_None, // G_ATOMICRMW_NAND = 107
1931 CEFBS_None, // G_ATOMICRMW_OR = 108
1932 CEFBS_None, // G_ATOMICRMW_XOR = 109
1933 CEFBS_None, // G_ATOMICRMW_MAX = 110
1934 CEFBS_None, // G_ATOMICRMW_MIN = 111
1935 CEFBS_None, // G_ATOMICRMW_UMAX = 112
1936 CEFBS_None, // G_ATOMICRMW_UMIN = 113
1937 CEFBS_None, // G_ATOMICRMW_FADD = 114
1938 CEFBS_None, // G_ATOMICRMW_FSUB = 115
1939 CEFBS_None, // G_ATOMICRMW_FMAX = 116
1940 CEFBS_None, // G_ATOMICRMW_FMIN = 117
1941 CEFBS_None, // G_ATOMICRMW_FMAXIMUM = 118
1942 CEFBS_None, // G_ATOMICRMW_FMINIMUM = 119
1943 CEFBS_None, // G_ATOMICRMW_UINC_WRAP = 120
1944 CEFBS_None, // G_ATOMICRMW_UDEC_WRAP = 121
1945 CEFBS_None, // G_ATOMICRMW_USUB_COND = 122
1946 CEFBS_None, // G_ATOMICRMW_USUB_SAT = 123
1947 CEFBS_None, // G_FENCE = 124
1948 CEFBS_None, // G_PREFETCH = 125
1949 CEFBS_None, // G_BRCOND = 126
1950 CEFBS_None, // G_BRINDIRECT = 127
1951 CEFBS_None, // G_INVOKE_REGION_START = 128
1952 CEFBS_None, // G_INTRINSIC = 129
1953 CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS = 130
1954 CEFBS_None, // G_INTRINSIC_CONVERGENT = 131
1955 CEFBS_None, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 132
1956 CEFBS_None, // G_ANYEXT = 133
1957 CEFBS_None, // G_TRUNC = 134
1958 CEFBS_None, // G_CONSTANT = 135
1959 CEFBS_None, // G_FCONSTANT = 136
1960 CEFBS_None, // G_VASTART = 137
1961 CEFBS_None, // G_VAARG = 138
1962 CEFBS_None, // G_SEXT = 139
1963 CEFBS_None, // G_SEXT_INREG = 140
1964 CEFBS_None, // G_ZEXT = 141
1965 CEFBS_None, // G_SHL = 142
1966 CEFBS_None, // G_LSHR = 143
1967 CEFBS_None, // G_ASHR = 144
1968 CEFBS_None, // G_FSHL = 145
1969 CEFBS_None, // G_FSHR = 146
1970 CEFBS_None, // G_ROTR = 147
1971 CEFBS_None, // G_ROTL = 148
1972 CEFBS_None, // G_ICMP = 149
1973 CEFBS_None, // G_FCMP = 150
1974 CEFBS_None, // G_SCMP = 151
1975 CEFBS_None, // G_UCMP = 152
1976 CEFBS_None, // G_SELECT = 153
1977 CEFBS_None, // G_UADDO = 154
1978 CEFBS_None, // G_UADDE = 155
1979 CEFBS_None, // G_USUBO = 156
1980 CEFBS_None, // G_USUBE = 157
1981 CEFBS_None, // G_SADDO = 158
1982 CEFBS_None, // G_SADDE = 159
1983 CEFBS_None, // G_SSUBO = 160
1984 CEFBS_None, // G_SSUBE = 161
1985 CEFBS_None, // G_UMULO = 162
1986 CEFBS_None, // G_SMULO = 163
1987 CEFBS_None, // G_UMULH = 164
1988 CEFBS_None, // G_SMULH = 165
1989 CEFBS_None, // G_UADDSAT = 166
1990 CEFBS_None, // G_SADDSAT = 167
1991 CEFBS_None, // G_USUBSAT = 168
1992 CEFBS_None, // G_SSUBSAT = 169
1993 CEFBS_None, // G_USHLSAT = 170
1994 CEFBS_None, // G_SSHLSAT = 171
1995 CEFBS_None, // G_SMULFIX = 172
1996 CEFBS_None, // G_UMULFIX = 173
1997 CEFBS_None, // G_SMULFIXSAT = 174
1998 CEFBS_None, // G_UMULFIXSAT = 175
1999 CEFBS_None, // G_SDIVFIX = 176
2000 CEFBS_None, // G_UDIVFIX = 177
2001 CEFBS_None, // G_SDIVFIXSAT = 178
2002 CEFBS_None, // G_UDIVFIXSAT = 179
2003 CEFBS_None, // G_FADD = 180
2004 CEFBS_None, // G_FSUB = 181
2005 CEFBS_None, // G_FMUL = 182
2006 CEFBS_None, // G_FMA = 183
2007 CEFBS_None, // G_FMAD = 184
2008 CEFBS_None, // G_FDIV = 185
2009 CEFBS_None, // G_FREM = 186
2010 CEFBS_None, // G_FPOW = 187
2011 CEFBS_None, // G_FPOWI = 188
2012 CEFBS_None, // G_FEXP = 189
2013 CEFBS_None, // G_FEXP2 = 190
2014 CEFBS_None, // G_FEXP10 = 191
2015 CEFBS_None, // G_FLOG = 192
2016 CEFBS_None, // G_FLOG2 = 193
2017 CEFBS_None, // G_FLOG10 = 194
2018 CEFBS_None, // G_FLDEXP = 195
2019 CEFBS_None, // G_FFREXP = 196
2020 CEFBS_None, // G_FNEG = 197
2021 CEFBS_None, // G_FPEXT = 198
2022 CEFBS_None, // G_FPTRUNC = 199
2023 CEFBS_None, // G_FPTOSI = 200
2024 CEFBS_None, // G_FPTOUI = 201
2025 CEFBS_None, // G_SITOFP = 202
2026 CEFBS_None, // G_UITOFP = 203
2027 CEFBS_None, // G_FPTOSI_SAT = 204
2028 CEFBS_None, // G_FPTOUI_SAT = 205
2029 CEFBS_None, // G_FABS = 206
2030 CEFBS_None, // G_FCOPYSIGN = 207
2031 CEFBS_None, // G_IS_FPCLASS = 208
2032 CEFBS_None, // G_FCANONICALIZE = 209
2033 CEFBS_None, // G_FMINNUM = 210
2034 CEFBS_None, // G_FMAXNUM = 211
2035 CEFBS_None, // G_FMINNUM_IEEE = 212
2036 CEFBS_None, // G_FMAXNUM_IEEE = 213
2037 CEFBS_None, // G_FMINIMUM = 214
2038 CEFBS_None, // G_FMAXIMUM = 215
2039 CEFBS_None, // G_FMINIMUMNUM = 216
2040 CEFBS_None, // G_FMAXIMUMNUM = 217
2041 CEFBS_None, // G_GET_FPENV = 218
2042 CEFBS_None, // G_SET_FPENV = 219
2043 CEFBS_None, // G_RESET_FPENV = 220
2044 CEFBS_None, // G_GET_FPMODE = 221
2045 CEFBS_None, // G_SET_FPMODE = 222
2046 CEFBS_None, // G_RESET_FPMODE = 223
2047 CEFBS_None, // G_PTR_ADD = 224
2048 CEFBS_None, // G_PTRMASK = 225
2049 CEFBS_None, // G_SMIN = 226
2050 CEFBS_None, // G_SMAX = 227
2051 CEFBS_None, // G_UMIN = 228
2052 CEFBS_None, // G_UMAX = 229
2053 CEFBS_None, // G_ABS = 230
2054 CEFBS_None, // G_LROUND = 231
2055 CEFBS_None, // G_LLROUND = 232
2056 CEFBS_None, // G_BR = 233
2057 CEFBS_None, // G_BRJT = 234
2058 CEFBS_None, // G_VSCALE = 235
2059 CEFBS_None, // G_INSERT_SUBVECTOR = 236
2060 CEFBS_None, // G_EXTRACT_SUBVECTOR = 237
2061 CEFBS_None, // G_INSERT_VECTOR_ELT = 238
2062 CEFBS_None, // G_EXTRACT_VECTOR_ELT = 239
2063 CEFBS_None, // G_SHUFFLE_VECTOR = 240
2064 CEFBS_None, // G_SPLAT_VECTOR = 241
2065 CEFBS_None, // G_STEP_VECTOR = 242
2066 CEFBS_None, // G_VECTOR_COMPRESS = 243
2067 CEFBS_None, // G_CTTZ = 244
2068 CEFBS_None, // G_CTTZ_ZERO_UNDEF = 245
2069 CEFBS_None, // G_CTLZ = 246
2070 CEFBS_None, // G_CTLZ_ZERO_UNDEF = 247
2071 CEFBS_None, // G_CTPOP = 248
2072 CEFBS_None, // G_BSWAP = 249
2073 CEFBS_None, // G_BITREVERSE = 250
2074 CEFBS_None, // G_FCEIL = 251
2075 CEFBS_None, // G_FCOS = 252
2076 CEFBS_None, // G_FSIN = 253
2077 CEFBS_None, // G_FSINCOS = 254
2078 CEFBS_None, // G_FTAN = 255
2079 CEFBS_None, // G_FACOS = 256
2080 CEFBS_None, // G_FASIN = 257
2081 CEFBS_None, // G_FATAN = 258
2082 CEFBS_None, // G_FATAN2 = 259
2083 CEFBS_None, // G_FCOSH = 260
2084 CEFBS_None, // G_FSINH = 261
2085 CEFBS_None, // G_FTANH = 262
2086 CEFBS_None, // G_FSQRT = 263
2087 CEFBS_None, // G_FFLOOR = 264
2088 CEFBS_None, // G_FRINT = 265
2089 CEFBS_None, // G_FNEARBYINT = 266
2090 CEFBS_None, // G_ADDRSPACE_CAST = 267
2091 CEFBS_None, // G_BLOCK_ADDR = 268
2092 CEFBS_None, // G_JUMP_TABLE = 269
2093 CEFBS_None, // G_DYN_STACKALLOC = 270
2094 CEFBS_None, // G_STACKSAVE = 271
2095 CEFBS_None, // G_STACKRESTORE = 272
2096 CEFBS_None, // G_STRICT_FADD = 273
2097 CEFBS_None, // G_STRICT_FSUB = 274
2098 CEFBS_None, // G_STRICT_FMUL = 275
2099 CEFBS_None, // G_STRICT_FDIV = 276
2100 CEFBS_None, // G_STRICT_FREM = 277
2101 CEFBS_None, // G_STRICT_FMA = 278
2102 CEFBS_None, // G_STRICT_FSQRT = 279
2103 CEFBS_None, // G_STRICT_FLDEXP = 280
2104 CEFBS_None, // G_READ_REGISTER = 281
2105 CEFBS_None, // G_WRITE_REGISTER = 282
2106 CEFBS_None, // G_MEMCPY = 283
2107 CEFBS_None, // G_MEMCPY_INLINE = 284
2108 CEFBS_None, // G_MEMMOVE = 285
2109 CEFBS_None, // G_MEMSET = 286
2110 CEFBS_None, // G_BZERO = 287
2111 CEFBS_None, // G_TRAP = 288
2112 CEFBS_None, // G_DEBUGTRAP = 289
2113 CEFBS_None, // G_UBSANTRAP = 290
2114 CEFBS_None, // G_VECREDUCE_SEQ_FADD = 291
2115 CEFBS_None, // G_VECREDUCE_SEQ_FMUL = 292
2116 CEFBS_None, // G_VECREDUCE_FADD = 293
2117 CEFBS_None, // G_VECREDUCE_FMUL = 294
2118 CEFBS_None, // G_VECREDUCE_FMAX = 295
2119 CEFBS_None, // G_VECREDUCE_FMIN = 296
2120 CEFBS_None, // G_VECREDUCE_FMAXIMUM = 297
2121 CEFBS_None, // G_VECREDUCE_FMINIMUM = 298
2122 CEFBS_None, // G_VECREDUCE_ADD = 299
2123 CEFBS_None, // G_VECREDUCE_MUL = 300
2124 CEFBS_None, // G_VECREDUCE_AND = 301
2125 CEFBS_None, // G_VECREDUCE_OR = 302
2126 CEFBS_None, // G_VECREDUCE_XOR = 303
2127 CEFBS_None, // G_VECREDUCE_SMAX = 304
2128 CEFBS_None, // G_VECREDUCE_SMIN = 305
2129 CEFBS_None, // G_VECREDUCE_UMAX = 306
2130 CEFBS_None, // G_VECREDUCE_UMIN = 307
2131 CEFBS_None, // G_SBFX = 308
2132 CEFBS_None, // G_UBFX = 309
2133 CEFBS_None, // ADJCALLSTACKDOWN = 310
2134 CEFBS_None, // ADJCALLSTACKUP = 311
2135 CEFBS_None, // FI_ri = 312
2136 CEFBS_None, // MEMCPY = 313
2137 CEFBS_None, // Select = 314
2138 CEFBS_None, // Select_32 = 315
2139 CEFBS_None, // Select_32_64 = 316
2140 CEFBS_None, // Select_64_32 = 317
2141 CEFBS_None, // Select_Ri = 318
2142 CEFBS_None, // Select_Ri_32 = 319
2143 CEFBS_None, // Select_Ri_32_64 = 320
2144 CEFBS_None, // Select_Ri_64_32 = 321
2145 CEFBS_None, // ADDR_SPACE_CAST = 322
2146 CEFBS_None, // ADD_ri = 323
2147 CEFBS_None, // ADD_ri_32 = 324
2148 CEFBS_None, // ADD_rr = 325
2149 CEFBS_None, // ADD_rr_32 = 326
2150 CEFBS_None, // AND_ri = 327
2151 CEFBS_None, // AND_ri_32 = 328
2152 CEFBS_None, // AND_rr = 329
2153 CEFBS_None, // AND_rr_32 = 330
2154 CEFBS_None, // BE16 = 331
2155 CEFBS_None, // BE32 = 332
2156 CEFBS_None, // BE64 = 333
2157 CEFBS_None, // BSWAP16 = 334
2158 CEFBS_None, // BSWAP32 = 335
2159 CEFBS_None, // BSWAP64 = 336
2160 CEFBS_None, // CMPXCHGD = 337
2161 CEFBS_None, // CMPXCHGW32 = 338
2162 CEFBS_None, // CORE_LD32 = 339
2163 CEFBS_None, // CORE_LD64 = 340
2164 CEFBS_None, // CORE_SHIFT = 341
2165 CEFBS_None, // CORE_ST = 342
2166 CEFBS_None, // DIV_ri = 343
2167 CEFBS_None, // DIV_ri_32 = 344
2168 CEFBS_None, // DIV_rr = 345
2169 CEFBS_None, // DIV_rr_32 = 346
2170 CEFBS_None, // JAL = 347
2171 CEFBS_None, // JALX = 348
2172 CEFBS_None, // JCOND = 349
2173 CEFBS_None, // JEQ_ri = 350
2174 CEFBS_None, // JEQ_ri_32 = 351
2175 CEFBS_None, // JEQ_rr = 352
2176 CEFBS_None, // JEQ_rr_32 = 353
2177 CEFBS_None, // JMP = 354
2178 CEFBS_None, // JMPL = 355
2179 CEFBS_None, // JNE_ri = 356
2180 CEFBS_None, // JNE_ri_32 = 357
2181 CEFBS_None, // JNE_rr = 358
2182 CEFBS_None, // JNE_rr_32 = 359
2183 CEFBS_None, // JSET_ri = 360
2184 CEFBS_None, // JSET_ri_32 = 361
2185 CEFBS_None, // JSET_rr = 362
2186 CEFBS_None, // JSET_rr_32 = 363
2187 CEFBS_None, // JSGE_ri = 364
2188 CEFBS_None, // JSGE_ri_32 = 365
2189 CEFBS_None, // JSGE_rr = 366
2190 CEFBS_None, // JSGE_rr_32 = 367
2191 CEFBS_None, // JSGT_ri = 368
2192 CEFBS_None, // JSGT_ri_32 = 369
2193 CEFBS_None, // JSGT_rr = 370
2194 CEFBS_None, // JSGT_rr_32 = 371
2195 CEFBS_None, // JSLE_ri = 372
2196 CEFBS_None, // JSLE_ri_32 = 373
2197 CEFBS_None, // JSLE_rr = 374
2198 CEFBS_None, // JSLE_rr_32 = 375
2199 CEFBS_None, // JSLT_ri = 376
2200 CEFBS_None, // JSLT_ri_32 = 377
2201 CEFBS_None, // JSLT_rr = 378
2202 CEFBS_None, // JSLT_rr_32 = 379
2203 CEFBS_None, // JUGE_ri = 380
2204 CEFBS_None, // JUGE_ri_32 = 381
2205 CEFBS_None, // JUGE_rr = 382
2206 CEFBS_None, // JUGE_rr_32 = 383
2207 CEFBS_None, // JUGT_ri = 384
2208 CEFBS_None, // JUGT_ri_32 = 385
2209 CEFBS_None, // JUGT_rr = 386
2210 CEFBS_None, // JUGT_rr_32 = 387
2211 CEFBS_None, // JULE_ri = 388
2212 CEFBS_None, // JULE_ri_32 = 389
2213 CEFBS_None, // JULE_rr = 390
2214 CEFBS_None, // JULE_rr_32 = 391
2215 CEFBS_None, // JULT_ri = 392
2216 CEFBS_None, // JULT_ri_32 = 393
2217 CEFBS_None, // JULT_rr = 394
2218 CEFBS_None, // JULT_rr_32 = 395
2219 CEFBS_None, // LDB = 396
2220 CEFBS_None, // LDB32 = 397
2221 CEFBS_None, // LDBACQ32 = 398
2222 CEFBS_None, // LDBSX = 399
2223 CEFBS_None, // LDD = 400
2224 CEFBS_None, // LDDACQ = 401
2225 CEFBS_None, // LDH = 402
2226 CEFBS_None, // LDH32 = 403
2227 CEFBS_None, // LDHACQ32 = 404
2228 CEFBS_None, // LDHSX = 405
2229 CEFBS_None, // LDW = 406
2230 CEFBS_None, // LDW32 = 407
2231 CEFBS_None, // LDWACQ32 = 408
2232 CEFBS_None, // LDWSX = 409
2233 CEFBS_None, // LD_ABS_B = 410
2234 CEFBS_None, // LD_ABS_H = 411
2235 CEFBS_None, // LD_ABS_W = 412
2236 CEFBS_None, // LD_IND_B = 413
2237 CEFBS_None, // LD_IND_H = 414
2238 CEFBS_None, // LD_IND_W = 415
2239 CEFBS_None, // LD_imm64 = 416
2240 CEFBS_None, // LD_pseudo = 417
2241 CEFBS_None, // LE16 = 418
2242 CEFBS_None, // LE32 = 419
2243 CEFBS_None, // LE64 = 420
2244 CEFBS_None, // MOD_ri = 421
2245 CEFBS_None, // MOD_ri_32 = 422
2246 CEFBS_None, // MOD_rr = 423
2247 CEFBS_None, // MOD_rr_32 = 424
2248 CEFBS_None, // MOVSX_rr_16 = 425
2249 CEFBS_None, // MOVSX_rr_32 = 426
2250 CEFBS_None, // MOVSX_rr_32_16 = 427
2251 CEFBS_None, // MOVSX_rr_32_8 = 428
2252 CEFBS_None, // MOVSX_rr_8 = 429
2253 CEFBS_None, // MOV_32_64 = 430
2254 CEFBS_None, // MOV_ri = 431
2255 CEFBS_None, // MOV_ri_32 = 432
2256 CEFBS_None, // MOV_rr = 433
2257 CEFBS_None, // MOV_rr_32 = 434
2258 CEFBS_None, // MUL_ri = 435
2259 CEFBS_None, // MUL_ri_32 = 436
2260 CEFBS_None, // MUL_rr = 437
2261 CEFBS_None, // MUL_rr_32 = 438
2262 CEFBS_None, // NEG_32 = 439
2263 CEFBS_None, // NEG_64 = 440
2264 CEFBS_None, // NOP = 441
2265 CEFBS_None, // OR_ri = 442
2266 CEFBS_None, // OR_ri_32 = 443
2267 CEFBS_None, // OR_rr = 444
2268 CEFBS_None, // OR_rr_32 = 445
2269 CEFBS_None, // RET = 446
2270 CEFBS_None, // SDIV_ri = 447
2271 CEFBS_None, // SDIV_ri_32 = 448
2272 CEFBS_None, // SDIV_rr = 449
2273 CEFBS_None, // SDIV_rr_32 = 450
2274 CEFBS_None, // SLL_ri = 451
2275 CEFBS_None, // SLL_ri_32 = 452
2276 CEFBS_None, // SLL_rr = 453
2277 CEFBS_None, // SLL_rr_32 = 454
2278 CEFBS_None, // SMOD_ri = 455
2279 CEFBS_None, // SMOD_ri_32 = 456
2280 CEFBS_None, // SMOD_rr = 457
2281 CEFBS_None, // SMOD_rr_32 = 458
2282 CEFBS_None, // SRA_ri = 459
2283 CEFBS_None, // SRA_ri_32 = 460
2284 CEFBS_None, // SRA_rr = 461
2285 CEFBS_None, // SRA_rr_32 = 462
2286 CEFBS_None, // SRL_ri = 463
2287 CEFBS_None, // SRL_ri_32 = 464
2288 CEFBS_None, // SRL_rr = 465
2289 CEFBS_None, // SRL_rr_32 = 466
2290 CEFBS_None, // STB = 467
2291 CEFBS_None, // STB32 = 468
2292 CEFBS_None, // STBREL32 = 469
2293 CEFBS_None, // STB_imm = 470
2294 CEFBS_None, // STD = 471
2295 CEFBS_None, // STDREL = 472
2296 CEFBS_None, // STD_imm = 473
2297 CEFBS_None, // STH = 474
2298 CEFBS_None, // STH32 = 475
2299 CEFBS_None, // STHREL32 = 476
2300 CEFBS_None, // STH_imm = 477
2301 CEFBS_None, // STW = 478
2302 CEFBS_None, // STW32 = 479
2303 CEFBS_None, // STWREL32 = 480
2304 CEFBS_None, // STW_imm = 481
2305 CEFBS_None, // SUB_ri = 482
2306 CEFBS_None, // SUB_ri_32 = 483
2307 CEFBS_None, // SUB_rr = 484
2308 CEFBS_None, // SUB_rr_32 = 485
2309 CEFBS_None, // XADDD = 486
2310 CEFBS_None, // XADDW = 487
2311 CEFBS_None, // XADDW32 = 488
2312 CEFBS_None, // XANDD = 489
2313 CEFBS_None, // XANDW32 = 490
2314 CEFBS_None, // XCHGD = 491
2315 CEFBS_None, // XCHGW32 = 492
2316 CEFBS_None, // XFADDD = 493
2317 CEFBS_None, // XFADDW32 = 494
2318 CEFBS_None, // XFANDD = 495
2319 CEFBS_None, // XFANDW32 = 496
2320 CEFBS_None, // XFORD = 497
2321 CEFBS_None, // XFORW32 = 498
2322 CEFBS_None, // XFXORD = 499
2323 CEFBS_None, // XFXORW32 = 500
2324 CEFBS_None, // XORD = 501
2325 CEFBS_None, // XORW32 = 502
2326 CEFBS_None, // XOR_ri = 503
2327 CEFBS_None, // XOR_ri_32 = 504
2328 CEFBS_None, // XOR_rr = 505
2329 CEFBS_None, // XOR_rr_32 = 506
2330 CEFBS_None, // XXORD = 507
2331 CEFBS_None, // XXORW32 = 508
2332 };
2333
2334 assert(Opcode < 509);
2335 return FeatureBitsets[RequiredFeaturesRefs[Opcode]];
2336}
2337
2338} // end namespace llvm::BPF_MC
2339#endif // GET_COMPUTE_FEATURES
2340
2341#ifdef GET_AVAILABLE_OPCODE_CHECKER
2342#undef GET_AVAILABLE_OPCODE_CHECKER
2343namespace llvm::BPF_MC {
2344bool isOpcodeAvailable(unsigned Opcode, const FeatureBitset &Features) {
2345 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
2346 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
2347 FeatureBitset MissingFeatures =
2348 (AvailableFeatures & RequiredFeatures) ^
2349 RequiredFeatures;
2350 return !MissingFeatures.any();
2351}
2352} // end namespace llvm::BPF_MC
2353#endif // GET_AVAILABLE_OPCODE_CHECKER
2354
2355#ifdef ENABLE_INSTR_PREDICATE_VERIFIER
2356#undef ENABLE_INSTR_PREDICATE_VERIFIER
2357#include <sstream>
2358
2359namespace llvm::BPF_MC {
2360#ifndef NDEBUG
2361static const char *SubtargetFeatureNames[] = {
2362 nullptr
2363};
2364
2365#endif // NDEBUG
2366
2367void verifyInstructionPredicates(
2368 unsigned Opcode, const FeatureBitset &Features) {
2369#ifndef NDEBUG
2370 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
2371 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
2372 FeatureBitset MissingFeatures =
2373 (AvailableFeatures & RequiredFeatures) ^
2374 RequiredFeatures;
2375 if (MissingFeatures.any()) {
2376 std::ostringstream Msg;
2377 Msg << "Attempting to emit " << &BPFInstrNameData[BPFInstrNameIndices[Opcode]]
2378 << " instruction but the ";
2379 for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i)
2380 if (MissingFeatures.test(i))
2381 Msg << SubtargetFeatureNames[i] << " ";
2382 Msg << "predicate(s) are not met";
2383 report_fatal_error(Msg.str().c_str());
2384 }
2385#endif // NDEBUG
2386}
2387} // end namespace llvm::BPF_MC
2388#endif // ENABLE_INSTR_PREDICATE_VERIFIER
2389
2390