1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register Enum Values *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9
10#ifdef GET_REGINFO_ENUM
11#undef GET_REGINFO_ENUM
12
13namespace llvm {
14
15class MCRegisterClass;
16extern const MCRegisterClass BPFMCRegisterClasses[];
17
18namespace BPF {
19enum : unsigned {
20 NoRegister,
21 R0 = 1,
22 R1 = 2,
23 R2 = 3,
24 R3 = 4,
25 R4 = 5,
26 R5 = 6,
27 R6 = 7,
28 R7 = 8,
29 R8 = 9,
30 R9 = 10,
31 R10 = 11,
32 R11 = 12,
33 W0 = 13,
34 W1 = 14,
35 W2 = 15,
36 W3 = 16,
37 W4 = 17,
38 W5 = 18,
39 W6 = 19,
40 W7 = 20,
41 W8 = 21,
42 W9 = 22,
43 W10 = 23,
44 W11 = 24,
45 NUM_TARGET_REGS // 25
46};
47} // end namespace BPF
48
49// Register classes
50
51namespace BPF {
52enum {
53 GPR32RegClassID = 0,
54 GPRRegClassID = 1,
55
56};
57} // end namespace BPF
58
59
60// Subregister indices
61
62namespace BPF {
63enum : uint16_t {
64 NoSubRegister,
65 sub_32, // 1
66 NUM_TARGET_SUBREGS
67};
68} // end namespace BPF
69
70// Register pressure sets enum.
71namespace BPF {
72enum RegisterPressureSets {
73 GPR32 = 0,
74};
75} // end namespace BPF
76
77} // end namespace llvm
78
79#endif // GET_REGINFO_ENUM
80
81/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
82|* *|
83|* MC Register Information *|
84|* *|
85|* Automatically generated file, do not edit! *|
86|* *|
87\*===----------------------------------------------------------------------===*/
88
89
90#ifdef GET_REGINFO_MC_DESC
91#undef GET_REGINFO_MC_DESC
92
93namespace llvm {
94
95extern const int16_t BPFRegDiffLists[] = {
96 /* 0 */ -12, 0,
97 /* 2 */ 12, 0,
98};
99
100extern const LaneBitmask BPFLaneMaskLists[] = {
101 /* 0 */ LaneBitmask(0x0000000000000001),
102 /* 1 */ LaneBitmask(0xFFFFFFFFFFFFFFFF),
103};
104
105extern const uint16_t BPFSubRegIdxLists[] = {
106 /* 0 */ 1,
107};
108
109
110#ifdef __GNUC__
111#pragma GCC diagnostic push
112#pragma GCC diagnostic ignored "-Woverlength-strings"
113#endif
114extern const char BPFRegStrings[] = {
115 /* 0 */ "R10\000"
116 /* 4 */ "W10\000"
117 /* 8 */ "R0\000"
118 /* 11 */ "W0\000"
119 /* 14 */ "R11\000"
120 /* 18 */ "W11\000"
121 /* 22 */ "R1\000"
122 /* 25 */ "W1\000"
123 /* 28 */ "R2\000"
124 /* 31 */ "W2\000"
125 /* 34 */ "R3\000"
126 /* 37 */ "W3\000"
127 /* 40 */ "R4\000"
128 /* 43 */ "W4\000"
129 /* 46 */ "R5\000"
130 /* 49 */ "W5\000"
131 /* 52 */ "R6\000"
132 /* 55 */ "W6\000"
133 /* 58 */ "R7\000"
134 /* 61 */ "W7\000"
135 /* 64 */ "R8\000"
136 /* 67 */ "W8\000"
137 /* 70 */ "R9\000"
138 /* 73 */ "W9\000"
139};
140#ifdef __GNUC__
141#pragma GCC diagnostic pop
142#endif
143
144extern const MCRegisterDesc BPFRegDesc[] = { // Descriptors
145 { 3, 0, 0, 0, 0, 0, 0, 0 },
146 { 8, 2, 1, 0, 4096, 0, 0, 0 },
147 { 22, 2, 1, 0, 4097, 0, 0, 0 },
148 { 28, 2, 1, 0, 4098, 0, 0, 0 },
149 { 34, 2, 1, 0, 4099, 0, 0, 0 },
150 { 40, 2, 1, 0, 4100, 0, 0, 0 },
151 { 46, 2, 1, 0, 4101, 0, 0, 0 },
152 { 52, 2, 1, 0, 4102, 0, 0, 0 },
153 { 58, 2, 1, 0, 4103, 0, 0, 0 },
154 { 64, 2, 1, 0, 4104, 0, 0, 0 },
155 { 70, 2, 1, 0, 4105, 0, 0, 0 },
156 { 0, 2, 1, 0, 4106, 0, 0, 0 },
157 { 14, 2, 1, 0, 4107, 0, 0, 0 },
158 { 11, 1, 0, 1, 4096, 1, 0, 0 },
159 { 25, 1, 0, 1, 4097, 1, 0, 0 },
160 { 31, 1, 0, 1, 4098, 1, 0, 0 },
161 { 37, 1, 0, 1, 4099, 1, 0, 0 },
162 { 43, 1, 0, 1, 4100, 1, 0, 0 },
163 { 49, 1, 0, 1, 4101, 1, 0, 0 },
164 { 55, 1, 0, 1, 4102, 1, 0, 0 },
165 { 61, 1, 0, 1, 4103, 1, 0, 0 },
166 { 67, 1, 0, 1, 4104, 1, 0, 0 },
167 { 73, 1, 0, 1, 4105, 1, 0, 0 },
168 { 4, 1, 0, 1, 4106, 1, 0, 0 },
169 { 18, 1, 0, 1, 4107, 1, 0, 0 },
170};
171
172extern const MCPhysReg BPFRegUnitRoots[][2] = {
173 { BPF::W0 },
174 { BPF::W1 },
175 { BPF::W2 },
176 { BPF::W3 },
177 { BPF::W4 },
178 { BPF::W5 },
179 { BPF::W6 },
180 { BPF::W7 },
181 { BPF::W8 },
182 { BPF::W9 },
183 { BPF::W10 },
184 { BPF::W11 },
185};
186
187namespace { // Register classes...
188 // GPR32 Register Class...
189 const MCPhysReg GPR32[] = {
190 BPF::W1, BPF::W2, BPF::W3, BPF::W4, BPF::W5, BPF::W6, BPF::W7, BPF::W8, BPF::W9, BPF::W0, BPF::W11, BPF::W10,
191 };
192
193 // GPR32 Bit set.
194 const uint8_t GPR32Bits[] = {
195 0x00, 0xe0, 0xff, 0x01,
196 };
197
198 // GPR Register Class...
199 const MCPhysReg GPR[] = {
200 BPF::R1, BPF::R2, BPF::R3, BPF::R4, BPF::R5, BPF::R6, BPF::R7, BPF::R8, BPF::R9, BPF::R0, BPF::R11, BPF::R10,
201 };
202
203 // GPR Bit set.
204 const uint8_t GPRBits[] = {
205 0xfe, 0x1f,
206 };
207
208} // end anonymous namespace
209
210
211#ifdef __GNUC__
212#pragma GCC diagnostic push
213#pragma GCC diagnostic ignored "-Woverlength-strings"
214#endif
215extern const char BPFRegClassStrings[] = {
216 /* 0 */ "GPR32\000"
217 /* 6 */ "GPR\000"
218};
219#ifdef __GNUC__
220#pragma GCC diagnostic pop
221#endif
222
223extern const MCRegisterClass BPFMCRegisterClasses[] = {
224 { GPR32, GPR32Bits, 0, 12, sizeof(GPR32Bits), BPF::GPR32RegClassID, 32, 1, true, false },
225 { GPR, GPRBits, 6, 12, sizeof(GPRBits), BPF::GPRRegClassID, 64, 1, true, false },
226};
227
228// BPF Dwarf<->LLVM register mappings.
229extern const MCRegisterInfo::DwarfLLVMRegPair BPFDwarfFlavour0Dwarf2L[] = {
230 { 0U, BPF::W0 },
231 { 1U, BPF::W1 },
232 { 2U, BPF::W2 },
233 { 3U, BPF::W3 },
234 { 4U, BPF::W4 },
235 { 5U, BPF::W5 },
236 { 6U, BPF::W6 },
237 { 7U, BPF::W7 },
238 { 8U, BPF::W8 },
239 { 9U, BPF::W9 },
240 { 10U, BPF::W10 },
241 { 11U, BPF::W11 },
242};
243extern const unsigned BPFDwarfFlavour0Dwarf2LSize = std::size(BPFDwarfFlavour0Dwarf2L);
244
245extern const MCRegisterInfo::DwarfLLVMRegPair BPFEHFlavour0Dwarf2L[] = {
246 { 0U, BPF::W0 },
247 { 1U, BPF::W1 },
248 { 2U, BPF::W2 },
249 { 3U, BPF::W3 },
250 { 4U, BPF::W4 },
251 { 5U, BPF::W5 },
252 { 6U, BPF::W6 },
253 { 7U, BPF::W7 },
254 { 8U, BPF::W8 },
255 { 9U, BPF::W9 },
256 { 10U, BPF::W10 },
257 { 11U, BPF::W11 },
258};
259extern const unsigned BPFEHFlavour0Dwarf2LSize = std::size(BPFEHFlavour0Dwarf2L);
260
261extern const MCRegisterInfo::DwarfLLVMRegPair BPFDwarfFlavour0L2Dwarf[] = {
262 { BPF::R0, 0U },
263 { BPF::R1, 1U },
264 { BPF::R2, 2U },
265 { BPF::R3, 3U },
266 { BPF::R4, 4U },
267 { BPF::R5, 5U },
268 { BPF::R6, 6U },
269 { BPF::R7, 7U },
270 { BPF::R8, 8U },
271 { BPF::R9, 9U },
272 { BPF::R10, 10U },
273 { BPF::R11, 11U },
274 { BPF::W0, 0U },
275 { BPF::W1, 1U },
276 { BPF::W2, 2U },
277 { BPF::W3, 3U },
278 { BPF::W4, 4U },
279 { BPF::W5, 5U },
280 { BPF::W6, 6U },
281 { BPF::W7, 7U },
282 { BPF::W8, 8U },
283 { BPF::W9, 9U },
284 { BPF::W10, 10U },
285 { BPF::W11, 11U },
286};
287extern const unsigned BPFDwarfFlavour0L2DwarfSize = std::size(BPFDwarfFlavour0L2Dwarf);
288
289extern const MCRegisterInfo::DwarfLLVMRegPair BPFEHFlavour0L2Dwarf[] = {
290 { BPF::R0, 0U },
291 { BPF::R1, 1U },
292 { BPF::R2, 2U },
293 { BPF::R3, 3U },
294 { BPF::R4, 4U },
295 { BPF::R5, 5U },
296 { BPF::R6, 6U },
297 { BPF::R7, 7U },
298 { BPF::R8, 8U },
299 { BPF::R9, 9U },
300 { BPF::R10, 10U },
301 { BPF::R11, 11U },
302 { BPF::W0, 0U },
303 { BPF::W1, 1U },
304 { BPF::W2, 2U },
305 { BPF::W3, 3U },
306 { BPF::W4, 4U },
307 { BPF::W5, 5U },
308 { BPF::W6, 6U },
309 { BPF::W7, 7U },
310 { BPF::W8, 8U },
311 { BPF::W9, 9U },
312 { BPF::W10, 10U },
313 { BPF::W11, 11U },
314};
315extern const unsigned BPFEHFlavour0L2DwarfSize = std::size(BPFEHFlavour0L2Dwarf);
316
317extern const uint16_t BPFRegEncodingTable[] = {
318 0,
319 0,
320 1,
321 2,
322 3,
323 4,
324 5,
325 6,
326 7,
327 8,
328 9,
329 10,
330 11,
331 0,
332 1,
333 2,
334 3,
335 4,
336 5,
337 6,
338 7,
339 8,
340 9,
341 10,
342 11,
343};
344static inline void InitBPFMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
345 RI->InitMCRegisterInfo(BPFRegDesc, 25, RA, PC, BPFMCRegisterClasses, 2, BPFRegUnitRoots, 12, BPFRegDiffLists, BPFLaneMaskLists, BPFRegStrings, BPFRegClassStrings, BPFSubRegIdxLists, 2,
346BPFRegEncodingTable);
347
348 switch (DwarfFlavour) {
349 default:
350 llvm_unreachable("Unknown DWARF flavour");
351 case 0:
352 RI->mapDwarfRegsToLLVMRegs(BPFDwarfFlavour0Dwarf2L, BPFDwarfFlavour0Dwarf2LSize, false);
353 break;
354 }
355 switch (EHFlavour) {
356 default:
357 llvm_unreachable("Unknown DWARF flavour");
358 case 0:
359 RI->mapDwarfRegsToLLVMRegs(BPFEHFlavour0Dwarf2L, BPFEHFlavour0Dwarf2LSize, true);
360 break;
361 }
362 switch (DwarfFlavour) {
363 default:
364 llvm_unreachable("Unknown DWARF flavour");
365 case 0:
366 RI->mapLLVMRegsToDwarfRegs(BPFDwarfFlavour0L2Dwarf, BPFDwarfFlavour0L2DwarfSize, false);
367 break;
368 }
369 switch (EHFlavour) {
370 default:
371 llvm_unreachable("Unknown DWARF flavour");
372 case 0:
373 RI->mapLLVMRegsToDwarfRegs(BPFEHFlavour0L2Dwarf, BPFEHFlavour0L2DwarfSize, true);
374 break;
375 }
376}
377
378} // end namespace llvm
379
380#endif // GET_REGINFO_MC_DESC
381
382/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
383|* *|
384|* Register Information Header Fragment *|
385|* *|
386|* Automatically generated file, do not edit! *|
387|* *|
388\*===----------------------------------------------------------------------===*/
389
390
391#ifdef GET_REGINFO_HEADER
392#undef GET_REGINFO_HEADER
393
394#include "llvm/CodeGen/TargetRegisterInfo.h"
395
396namespace llvm {
397
398class BPFFrameLowering;
399
400struct BPFGenRegisterInfo : public TargetRegisterInfo {
401 explicit BPFGenRegisterInfo(unsigned RA, unsigned D = 0, unsigned E = 0,
402 unsigned PC = 0, unsigned HwMode = 0);
403 unsigned composeSubRegIndicesImpl(unsigned, unsigned) const override;
404 unsigned reverseComposeSubRegIndicesImpl(unsigned, unsigned) const override;
405 LaneBitmask composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
406 LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
407 const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass *, unsigned) const override;
408 const TargetRegisterClass *getSubRegisterClass(const TargetRegisterClass *, unsigned) const override;
409 const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override;
410 unsigned getRegUnitWeight(unsigned RegUnit) const override;
411 unsigned getNumRegPressureSets() const override;
412 const char *getRegPressureSetName(unsigned Idx) const override;
413 unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override;
414 const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override;
415 const int *getRegUnitPressureSets(unsigned RegUnit) const override;
416 ArrayRef<const char *> getRegMaskNames() const override;
417 ArrayRef<const uint32_t *> getRegMasks() const override;
418 bool isGeneralPurposeRegister(const MachineFunction &, MCRegister) const override;
419 bool isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const override;
420 bool isFixedRegister(const MachineFunction &, MCRegister) const override;
421 bool isArgumentRegister(const MachineFunction &, MCRegister) const override;
422 bool isConstantPhysReg(MCRegister PhysReg) const override final;
423 /// Devirtualized TargetFrameLowering.
424 static const BPFFrameLowering *getFrameLowering(
425 const MachineFunction &MF);
426};
427
428namespace BPF { // Register classes
429 extern const TargetRegisterClass GPR32RegClass;
430 extern const TargetRegisterClass GPRRegClass;
431} // end namespace BPF
432
433} // end namespace llvm
434
435#endif // GET_REGINFO_HEADER
436
437/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
438|* *|
439|* Target Register and Register Classes Information *|
440|* *|
441|* Automatically generated file, do not edit! *|
442|* *|
443\*===----------------------------------------------------------------------===*/
444
445
446#ifdef GET_REGINFO_TARGET_DESC
447#undef GET_REGINFO_TARGET_DESC
448
449namespace llvm {
450
451extern const MCRegisterClass BPFMCRegisterClasses[];
452
453static const MVT::SimpleValueType VTLists[] = {
454 /* 0 */ MVT::i32, MVT::Other,
455 /* 2 */ MVT::i64, MVT::Other,
456};
457
458static const char *SubRegIndexNameTable[] = { "sub_32", "" };
459
460static const TargetRegisterInfo::SubRegCoveredBits SubRegIdxRangeTable[] = {
461 { 65535, 65535 },
462 { 0, 32 }, // sub_32
463};
464
465
466static const LaneBitmask SubRegIndexLaneMaskTable[] = {
467 LaneBitmask::getAll(),
468 LaneBitmask(0x0000000000000001), // sub_32
469 };
470
471
472
473static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
474 // Mode = 0 (Default)
475 { 32, 32, 64, /*VTLists+*/0 }, // GPR32
476 { 64, 64, 64, /*VTLists+*/2 }, // GPR
477};
478static const uint32_t GPR32SubClassMask[] = {
479 0x00000001,
480 0x00000002, // sub_32
481};
482
483static const uint32_t GPRSubClassMask[] = {
484 0x00000002,
485};
486
487static const uint16_t SuperRegIdxSeqs[] = {
488 /* 0 */ 1, 0,
489};
490
491
492namespace BPF { // Register class instances
493 extern const TargetRegisterClass GPR32RegClass = {
494 &BPFMCRegisterClasses[GPR32RegClassID],
495 GPR32SubClassMask,
496 SuperRegIdxSeqs + 0,
497 LaneBitmask(0x0000000000000001),
498 0,
499 false,
500 0x00, /* TSFlags */
501 false, /* HasDisjunctSubRegs */
502 false, /* CoveredBySubRegs */
503 nullptr, 0,
504 nullptr
505 };
506
507 extern const TargetRegisterClass GPRRegClass = {
508 &BPFMCRegisterClasses[GPRRegClassID],
509 GPRSubClassMask,
510 SuperRegIdxSeqs + 1,
511 LaneBitmask(0x0000000000000001),
512 0,
513 false,
514 0x00, /* TSFlags */
515 false, /* HasDisjunctSubRegs */
516 false, /* CoveredBySubRegs */
517 nullptr, 0,
518 nullptr
519 };
520
521} // end namespace BPF
522
523namespace {
524 const TargetRegisterClass *const RegisterClasses[] = {
525 &BPF::GPR32RegClass,
526 &BPF::GPRRegClass,
527 };
528} // end anonymous namespace
529
530static const uint8_t CostPerUseTable[] = {
5310, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
532
533
534static const bool InAllocatableClassTable[] = {
535false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, };
536
537
538static const TargetRegisterInfoDesc BPFRegInfoDesc = { // Extra Descriptors
539CostPerUseTable, 1, InAllocatableClassTable};
540
541unsigned BPFGenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
542 static const uint8_t Rows[1][1] = {
543 { 0, },
544 };
545
546 --IdxA; assert(IdxA < 1); (void) IdxA;
547 --IdxB; assert(IdxB < 1);
548 return Rows[0][IdxB];
549}
550
551unsigned BPFGenRegisterInfo::reverseComposeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
552 static const uint8_t Table[1][1] = {
553 { 0, },
554 };
555
556 --IdxA; assert(IdxA < 1);
557 --IdxB; assert(IdxB < 1);
558 return Table[IdxA][IdxB];
559 }
560
561 struct MaskRolOp {
562 LaneBitmask Mask;
563 uint8_t RotateLeft;
564 };
565 static const MaskRolOp LaneMaskComposeSequences[] = {
566 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 0 }, { LaneBitmask::getNone(), 0 } // Sequence 0
567 };
568 static const uint8_t CompositeSequences[] = {
569 0 // to sub_32
570 };
571
572LaneBitmask BPFGenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
573 --IdxA; assert(IdxA < 1 && "Subregister index out of bounds");
574 LaneBitmask Result;
575 for (const MaskRolOp *Ops =
576 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
577 Ops->Mask.any(); ++Ops) {
578 LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
579 if (unsigned S = Ops->RotateLeft)
580 Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));
581 else
582 Result |= LaneBitmask(M);
583 }
584 return Result;
585}
586
587LaneBitmask BPFGenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
588 LaneMask &= getSubRegIndexLaneMask(IdxA);
589 --IdxA; assert(IdxA < 1 && "Subregister index out of bounds");
590 LaneBitmask Result;
591 for (const MaskRolOp *Ops =
592 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
593 Ops->Mask.any(); ++Ops) {
594 LaneBitmask::Type M = LaneMask.getAsInteger();
595 if (unsigned S = Ops->RotateLeft)
596 Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));
597 else
598 Result |= LaneBitmask(M);
599 }
600 return Result;
601}
602
603const TargetRegisterClass *BPFGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
604 static const uint8_t Table[2][1] = {
605 { // GPR32
606 0, // sub_32
607 },
608 { // GPR
609 2, // sub_32 -> GPR
610 },
611 };
612 assert(RC && "Missing regclass");
613 if (!Idx) return RC;
614 --Idx;
615 assert(Idx < 1 && "Bad subreg");
616 unsigned TV = Table[RC->getID()][Idx];
617 return TV ? getRegClass(TV - 1) : nullptr;
618}
619
620const TargetRegisterClass *BPFGenRegisterInfo::getSubRegisterClass(const TargetRegisterClass *RC, unsigned Idx) const {
621 static const uint8_t Table[2][1] = {
622 { // GPR32
623 0, // GPR32:sub_32
624 },
625 { // GPR
626 1, // GPR:sub_32 -> GPR32
627 },
628 };
629 assert(RC && "Missing regclass");
630 if (!Idx) return RC;
631 --Idx;
632 assert(Idx < 1 && "Bad subreg");
633 unsigned TV = Table[RC->getID()][Idx];
634 return TV ? getRegClass(TV - 1) : nullptr;
635}
636
637/// Get the weight in units of pressure for this register class.
638const RegClassWeight &BPFGenRegisterInfo::
639getRegClassWeight(const TargetRegisterClass *RC) const {
640 static const RegClassWeight RCWeightTable[] = {
641 {1, 12}, // GPR32
642 {1, 12}, // GPR
643 };
644 return RCWeightTable[RC->getID()];
645}
646
647/// Get the weight in units of pressure for this register unit.
648unsigned BPFGenRegisterInfo::
649getRegUnitWeight(unsigned RegUnit) const {
650 assert(RegUnit < 12 && "invalid register unit");
651 // All register units have unit weight.
652 return 1;
653}
654
655
656// Get the number of dimensions of register pressure.
657unsigned BPFGenRegisterInfo::getNumRegPressureSets() const {
658 return 1;
659}
660
661// Get the name of this register unit pressure set.
662const char *BPFGenRegisterInfo::
663getRegPressureSetName(unsigned Idx) const {
664 static const char *PressureNameTable[] = {
665 "GPR32",
666 };
667 return PressureNameTable[Idx];
668}
669
670// Get the register unit pressure limit for this dimension.
671// This limit must be adjusted dynamically for reserved registers.
672unsigned BPFGenRegisterInfo::
673getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
674 static const uint8_t PressureLimitTable[] = {
675 12, // 0: GPR32
676 };
677 return PressureLimitTable[Idx];
678}
679
680/// Table of pressure sets per register class or unit.
681static const int RCSetsTable[] = {
682 /* 0 */ 0, -1,
683};
684
685/// Get the dimensions of register pressure impacted by this register class.
686/// Returns a -1 terminated array of pressure set IDs
687const int *BPFGenRegisterInfo::
688getRegClassPressureSets(const TargetRegisterClass *RC) const {
689 static const uint8_t RCSetStartTable[] = {
690 0,0,};
691 return &RCSetsTable[RCSetStartTable[RC->getID()]];
692}
693
694/// Get the dimensions of register pressure impacted by this register unit.
695/// Returns a -1 terminated array of pressure set IDs
696const int *BPFGenRegisterInfo::
697getRegUnitPressureSets(unsigned RegUnit) const {
698 assert(RegUnit < 12 && "invalid register unit");
699 static const uint8_t RUSetStartTable[] = {
700 0,0,0,0,0,0,0,0,0,0,0,0,};
701 return &RCSetsTable[RUSetStartTable[RegUnit]];
702}
703
704extern const MCRegisterDesc BPFRegDesc[];
705extern const int16_t BPFRegDiffLists[];
706extern const LaneBitmask BPFLaneMaskLists[];
707extern const char BPFRegStrings[];
708extern const char BPFRegClassStrings[];
709extern const MCPhysReg BPFRegUnitRoots[][2];
710extern const uint16_t BPFSubRegIdxLists[];
711extern const uint16_t BPFRegEncodingTable[];
712// BPF Dwarf<->LLVM register mappings.
713extern const MCRegisterInfo::DwarfLLVMRegPair BPFDwarfFlavour0Dwarf2L[];
714extern const unsigned BPFDwarfFlavour0Dwarf2LSize;
715
716extern const MCRegisterInfo::DwarfLLVMRegPair BPFEHFlavour0Dwarf2L[];
717extern const unsigned BPFEHFlavour0Dwarf2LSize;
718
719extern const MCRegisterInfo::DwarfLLVMRegPair BPFDwarfFlavour0L2Dwarf[];
720extern const unsigned BPFDwarfFlavour0L2DwarfSize;
721
722extern const MCRegisterInfo::DwarfLLVMRegPair BPFEHFlavour0L2Dwarf[];
723extern const unsigned BPFEHFlavour0L2DwarfSize;
724
725BPFGenRegisterInfo::
726BPFGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
727 unsigned PC, unsigned HwMode)
728 : TargetRegisterInfo(&BPFRegInfoDesc, RegisterClasses, RegisterClasses+2,
729 SubRegIndexNameTable, SubRegIdxRangeTable, SubRegIndexLaneMaskTable,
730 LaneBitmask(0xFFFFFFFFFFFFFFFE), RegClassInfos, VTLists, HwMode) {
731 InitMCRegisterInfo(BPFRegDesc, 25, RA, PC,
732 BPFMCRegisterClasses, 2,
733 BPFRegUnitRoots,
734 12,
735 BPFRegDiffLists,
736 BPFLaneMaskLists,
737 BPFRegStrings,
738 BPFRegClassStrings,
739 BPFSubRegIdxLists,
740 2,
741 BPFRegEncodingTable);
742
743 switch (DwarfFlavour) {
744 default:
745 llvm_unreachable("Unknown DWARF flavour");
746 case 0:
747 mapDwarfRegsToLLVMRegs(BPFDwarfFlavour0Dwarf2L, BPFDwarfFlavour0Dwarf2LSize, false);
748 break;
749 }
750 switch (EHFlavour) {
751 default:
752 llvm_unreachable("Unknown DWARF flavour");
753 case 0:
754 mapDwarfRegsToLLVMRegs(BPFEHFlavour0Dwarf2L, BPFEHFlavour0Dwarf2LSize, true);
755 break;
756 }
757 switch (DwarfFlavour) {
758 default:
759 llvm_unreachable("Unknown DWARF flavour");
760 case 0:
761 mapLLVMRegsToDwarfRegs(BPFDwarfFlavour0L2Dwarf, BPFDwarfFlavour0L2DwarfSize, false);
762 break;
763 }
764 switch (EHFlavour) {
765 default:
766 llvm_unreachable("Unknown DWARF flavour");
767 case 0:
768 mapLLVMRegsToDwarfRegs(BPFEHFlavour0L2Dwarf, BPFEHFlavour0L2DwarfSize, true);
769 break;
770 }
771}
772
773static const MCPhysReg CSR_SaveList[] = { BPF::R6, BPF::R7, BPF::R8, BPF::R9, BPF::R10, 0 };
774static const uint32_t CSR_RegMask[] = { 0x00f80f80, };
775static const MCPhysReg CSR_PreserveAll_SaveList[] = { BPF::R0, BPF::R1, BPF::R2, BPF::R3, BPF::R4, BPF::R5, BPF::R6, BPF::R7, BPF::R8, BPF::R9, BPF::R10, 0 };
776static const uint32_t CSR_PreserveAll_RegMask[] = { 0x00ffeffe, };
777
778
779ArrayRef<const uint32_t *> BPFGenRegisterInfo::getRegMasks() const {
780 static const uint32_t *const Masks[] = {
781 CSR_RegMask,
782 CSR_PreserveAll_RegMask,
783 };
784 return ArrayRef(Masks);
785}
786
787bool BPFGenRegisterInfo::
788isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
789 return
790 false;
791}
792
793bool BPFGenRegisterInfo::
794isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const {
795 return
796 false;
797}
798
799bool BPFGenRegisterInfo::
800isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
801 return
802 false;
803}
804
805bool BPFGenRegisterInfo::
806isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
807 return
808 false;
809}
810
811bool BPFGenRegisterInfo::
812isConstantPhysReg(MCRegister PhysReg) const {
813 return
814 false;
815}
816
817ArrayRef<const char *> BPFGenRegisterInfo::getRegMaskNames() const {
818 static const char *Names[] = {
819 "CSR",
820 "CSR_PreserveAll",
821 };
822 return ArrayRef(Names);
823}
824
825const BPFFrameLowering *
826BPFGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
827 return static_cast<const BPFFrameLowering *>(
828 MF.getSubtarget().getFrameLowering());
829}
830
831} // end namespace llvm
832
833#endif // GET_REGINFO_TARGET_DESC
834
835