1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Subtarget Enumeration Source Fragment *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9
10#ifdef GET_SUBTARGETINFO_ENUM
11#undef GET_SUBTARGETINFO_ENUM
12
13namespace llvm {
14namespace BPF {
15enum {
16 ALU32 = 0,
17 DummyFeature = 1,
18 DwarfRIS = 2,
19 NumSubtargetFeatures = 3
20};
21} // end namespace BPF
22} // end namespace llvm
23
24#endif // GET_SUBTARGETINFO_ENUM
25
26
27#ifdef GET_SUBTARGETINFO_MACRO
28GET_SUBTARGETINFO_MACRO(HasAlu32, false, hasAlu32)
29GET_SUBTARGETINFO_MACRO(UseDwarfRIS, false, useDwarfRIS)
30GET_SUBTARGETINFO_MACRO(isDummyMode, false, isDummyMode)
31#undef GET_SUBTARGETINFO_MACRO
32#endif // GET_SUBTARGETINFO_MACRO
33
34
35#ifdef GET_SUBTARGETINFO_MC_DESC
36#undef GET_SUBTARGETINFO_MC_DESC
37
38namespace llvm {
39// Sorted (by key) array of values for CPU features.
40extern const llvm::SubtargetFeatureKV BPFFeatureKV[] = {
41 { "alu32", "Enable ALU32 instructions", BPF::ALU32, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
42 { "dummy", "unused feature", BPF::DummyFeature, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
43 { "dwarfris", "Disable MCAsmInfo DwarfUsesRelocationsAcrossSections", BPF::DwarfRIS, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
44};
45
46#ifdef DBGFIELD
47#error "<target>GenSubtargetInfo.inc requires a DBGFIELD macro"
48#endif
49#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
50#define DBGFIELD(x) x,
51#define DBGVAL_OR_NULLPTR(x) x
52#else
53#define DBGFIELD(x)
54#define DBGVAL_OR_NULLPTR(x) nullptr
55#endif
56
57// ===============================================================
58// Data tables for the new per-operand machine model.
59
60// {ProcResourceIdx, ReleaseAtCycle, AcquireAtCycle}
61extern const llvm::MCWriteProcResEntry BPFWriteProcResTable[] = {
62 { 0, 0, 0 }, // Invalid
63}; // BPFWriteProcResTable
64
65// {Cycles, WriteResourceID}
66extern const llvm::MCWriteLatencyEntry BPFWriteLatencyTable[] = {
67 { 0, 0}, // Invalid
68}; // BPFWriteLatencyTable
69
70// {UseIdx, WriteResourceID, Cycles}
71extern const llvm::MCReadAdvanceEntry BPFReadAdvanceTable[] = {
72 {0, 0, 0}, // Invalid
73}; // BPFReadAdvanceTable
74
75#ifdef __GNUC__
76#pragma GCC diagnostic push
77#pragma GCC diagnostic ignored "-Woverlength-strings"
78#endif
79static constexpr char BPFSchedClassNamesStorage[] =
80 "\0"
81 "InvalidSchedClass\0"
82 ;
83#ifdef __GNUC__
84#pragma GCC diagnostic pop
85#endif
86
87static constexpr llvm::StringTable BPFSchedClassNames =
88 BPFSchedClassNamesStorage;
89
90static const llvm::MCSchedModel NoSchedModel = {
91 MCSchedModel::DefaultIssueWidth,
92 MCSchedModel::DefaultMicroOpBufferSize,
93 MCSchedModel::DefaultLoopMicroOpBufferSize,
94 MCSchedModel::DefaultLoadLatency,
95 MCSchedModel::DefaultHighLatency,
96 MCSchedModel::DefaultMispredictPenalty,
97 false, // PostRAScheduler
98 false, // CompleteModel
99 false, // EnableIntervals
100 0, // Processor ID
101 nullptr, nullptr, 0, 0, // No instruction-level machine model.
102 DBGVAL_OR_NULLPTR(&BPFSchedClassNames), // SchedClassNames
103 nullptr, // No Itinerary
104 nullptr // No extra processor descriptor
105};
106
107#undef DBGFIELD
108
109#undef DBGVAL_OR_NULLPTR
110
111// Sorted (by key) array of values for CPU subtype.
112extern const llvm::SubtargetSubTypeKV BPFSubTypeKV[] = {
113 { "generic", { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
114 { "probe", { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
115 { "v1", { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
116 { "v2", { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
117 { "v3", { { { 0x1ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
118 { "v4", { { { 0x1ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
119};
120
121// Sorted array of names of CPU subtypes, including aliases.
122extern const llvm::StringRef BPFNames[] = {
123"generic",
124"probe",
125"v1",
126"v2",
127"v3",
128"v4"};
129
130namespace BPF_MC {
131unsigned resolveVariantSchedClassImpl(unsigned SchedClass,
132 const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) {
133 // Don't know how to resolve this scheduling class.
134 return 0;
135}
136} // end namespace BPF_MC
137
138struct BPFGenMCSubtargetInfo : public MCSubtargetInfo {
139 BPFGenMCSubtargetInfo(const Triple &TT,
140 StringRef CPU, StringRef TuneCPU, StringRef FS,
141 ArrayRef<StringRef> PN,
142 ArrayRef<SubtargetFeatureKV> PF,
143 ArrayRef<SubtargetSubTypeKV> PD,
144 const MCWriteProcResEntry *WPR,
145 const MCWriteLatencyEntry *WL,
146 const MCReadAdvanceEntry *RA, const InstrStage *IS,
147 const unsigned *OC, const unsigned *FP) :
148 MCSubtargetInfo(TT, CPU, TuneCPU, FS, PN, PF, PD,
149 WPR, WL, RA, IS, OC, FP) { }
150
151 unsigned resolveVariantSchedClass(unsigned SchedClass,
152 const MCInst *MI, const MCInstrInfo *MCII,
153 unsigned CPUID) const override {
154 return BPF_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, CPUID);
155 }
156};
157
158static inline MCSubtargetInfo *createBPFMCSubtargetInfoImpl(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS) {
159 return new BPFGenMCSubtargetInfo(TT, CPU, TuneCPU, FS, BPFNames, BPFFeatureKV, BPFSubTypeKV,
160 BPFWriteProcResTable, BPFWriteLatencyTable, BPFReadAdvanceTable,
161 nullptr, nullptr, nullptr);
162}
163
164} // end namespace llvm
165
166#endif // GET_SUBTARGETINFO_MC_DESC
167
168
169#ifdef GET_SUBTARGETINFO_TARGET_DESC
170#undef GET_SUBTARGETINFO_TARGET_DESC
171
172#include "llvm/ADT/BitmaskEnum.h"
173#include "llvm/Support/Debug.h"
174#include "llvm/Support/raw_ostream.h"
175
176// ParseSubtargetFeatures - Parses features string setting specified
177// subtarget options.
178void llvm::BPFSubtarget::ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS) {
179 LLVM_DEBUG(dbgs() << "\nFeatures:" << FS);
180 LLVM_DEBUG(dbgs() << "\nCPU:" << CPU);
181 LLVM_DEBUG(dbgs() << "\nTuneCPU:" << TuneCPU << "\n\n");
182 InitMCProcessorInfo(CPU, TuneCPU, FS);
183 const FeatureBitset &Bits = getFeatureBits();
184 if (Bits[BPF::ALU32]) HasAlu32 = true;
185 if (Bits[BPF::DummyFeature]) isDummyMode = true;
186 if (Bits[BPF::DwarfRIS]) UseDwarfRIS = true;
187}
188#endif // GET_SUBTARGETINFO_TARGET_DESC
189
190
191#ifdef GET_SUBTARGETINFO_HEADER
192#undef GET_SUBTARGETINFO_HEADER
193
194namespace llvm {
195class DFAPacketizer;
196namespace BPF_MC {
197unsigned resolveVariantSchedClassImpl(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID);
198} // end namespace BPF_MC
199
200struct BPFGenSubtargetInfo : public TargetSubtargetInfo {
201 explicit BPFGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS);
202public:
203 unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const override;
204 unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const override;
205 DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID) const;
206};
207} // end namespace llvm
208
209#endif // GET_SUBTARGETINFO_HEADER
210
211
212#ifdef GET_SUBTARGETINFO_CTOR
213#undef GET_SUBTARGETINFO_CTOR
214
215#include "llvm/CodeGen/TargetSchedule.h"
216
217namespace llvm {
218extern const llvm::StringRef BPFNames[];
219extern const llvm::SubtargetFeatureKV BPFFeatureKV[];
220extern const llvm::SubtargetSubTypeKV BPFSubTypeKV[];
221extern const llvm::MCWriteProcResEntry BPFWriteProcResTable[];
222extern const llvm::MCWriteLatencyEntry BPFWriteLatencyTable[];
223extern const llvm::MCReadAdvanceEntry BPFReadAdvanceTable[];
224BPFGenSubtargetInfo::BPFGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS)
225 : TargetSubtargetInfo(TT, CPU, TuneCPU, FS, ArrayRef(BPFNames, 6), ArrayRef(BPFFeatureKV, 3), ArrayRef(BPFSubTypeKV, 6),
226 BPFWriteProcResTable, BPFWriteLatencyTable, BPFReadAdvanceTable,
227 nullptr, nullptr, nullptr) {}
228
229unsigned BPFGenSubtargetInfo
230::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {
231 report_fatal_error("Expected a variant SchedClass");
232} // BPFGenSubtargetInfo::resolveSchedClass
233
234unsigned BPFGenSubtargetInfo
235::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const {
236 return BPF_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, CPUID);
237} // BPFGenSubtargetInfo::resolveVariantSchedClass
238
239} // end namespace llvm
240
241#endif // GET_SUBTARGETINFO_CTOR
242
243
244#ifdef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
245#undef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
246
247#endif // GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
248
249
250#ifdef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
251#undef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
252
253#endif // GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
254
255