1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Instruction Enum Values and Descriptors *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_INSTRINFO_ENUM
10#undef GET_INSTRINFO_ENUM
11namespace llvm::Hexagon {
12 enum {
13 PHI = 0,
14 INLINEASM = 1,
15 INLINEASM_BR = 2,
16 CFI_INSTRUCTION = 3,
17 EH_LABEL = 4,
18 GC_LABEL = 5,
19 ANNOTATION_LABEL = 6,
20 KILL = 7,
21 EXTRACT_SUBREG = 8,
22 INSERT_SUBREG = 9,
23 IMPLICIT_DEF = 10,
24 INIT_UNDEF = 11,
25 SUBREG_TO_REG = 12,
26 COPY_TO_REGCLASS = 13,
27 DBG_VALUE = 14,
28 DBG_VALUE_LIST = 15,
29 DBG_INSTR_REF = 16,
30 DBG_PHI = 17,
31 DBG_LABEL = 18,
32 REG_SEQUENCE = 19,
33 COPY = 20,
34 BUNDLE = 21,
35 LIFETIME_START = 22,
36 LIFETIME_END = 23,
37 PSEUDO_PROBE = 24,
38 ARITH_FENCE = 25,
39 STACKMAP = 26,
40 FENTRY_CALL = 27,
41 PATCHPOINT = 28,
42 LOAD_STACK_GUARD = 29,
43 PREALLOCATED_SETUP = 30,
44 PREALLOCATED_ARG = 31,
45 STATEPOINT = 32,
46 LOCAL_ESCAPE = 33,
47 FAULTING_OP = 34,
48 PATCHABLE_OP = 35,
49 PATCHABLE_FUNCTION_ENTER = 36,
50 PATCHABLE_RET = 37,
51 PATCHABLE_FUNCTION_EXIT = 38,
52 PATCHABLE_TAIL_CALL = 39,
53 PATCHABLE_EVENT_CALL = 40,
54 PATCHABLE_TYPED_EVENT_CALL = 41,
55 ICALL_BRANCH_FUNNEL = 42,
56 FAKE_USE = 43,
57 MEMBARRIER = 44,
58 JUMP_TABLE_DEBUG_INFO = 45,
59 CONVERGENCECTRL_ENTRY = 46,
60 CONVERGENCECTRL_ANCHOR = 47,
61 CONVERGENCECTRL_LOOP = 48,
62 CONVERGENCECTRL_GLUE = 49,
63 G_ASSERT_SEXT = 50,
64 G_ASSERT_ZEXT = 51,
65 G_ASSERT_ALIGN = 52,
66 G_ADD = 53,
67 G_SUB = 54,
68 G_MUL = 55,
69 G_SDIV = 56,
70 G_UDIV = 57,
71 G_SREM = 58,
72 G_UREM = 59,
73 G_SDIVREM = 60,
74 G_UDIVREM = 61,
75 G_AND = 62,
76 G_OR = 63,
77 G_XOR = 64,
78 G_ABDS = 65,
79 G_ABDU = 66,
80 G_IMPLICIT_DEF = 67,
81 G_PHI = 68,
82 G_FRAME_INDEX = 69,
83 G_GLOBAL_VALUE = 70,
84 G_PTRAUTH_GLOBAL_VALUE = 71,
85 G_CONSTANT_POOL = 72,
86 G_EXTRACT = 73,
87 G_UNMERGE_VALUES = 74,
88 G_INSERT = 75,
89 G_MERGE_VALUES = 76,
90 G_BUILD_VECTOR = 77,
91 G_BUILD_VECTOR_TRUNC = 78,
92 G_CONCAT_VECTORS = 79,
93 G_PTRTOINT = 80,
94 G_INTTOPTR = 81,
95 G_BITCAST = 82,
96 G_FREEZE = 83,
97 G_CONSTANT_FOLD_BARRIER = 84,
98 G_INTRINSIC_FPTRUNC_ROUND = 85,
99 G_INTRINSIC_TRUNC = 86,
100 G_INTRINSIC_ROUND = 87,
101 G_INTRINSIC_LRINT = 88,
102 G_INTRINSIC_LLRINT = 89,
103 G_INTRINSIC_ROUNDEVEN = 90,
104 G_READCYCLECOUNTER = 91,
105 G_READSTEADYCOUNTER = 92,
106 G_LOAD = 93,
107 G_SEXTLOAD = 94,
108 G_ZEXTLOAD = 95,
109 G_INDEXED_LOAD = 96,
110 G_INDEXED_SEXTLOAD = 97,
111 G_INDEXED_ZEXTLOAD = 98,
112 G_STORE = 99,
113 G_INDEXED_STORE = 100,
114 G_ATOMIC_CMPXCHG_WITH_SUCCESS = 101,
115 G_ATOMIC_CMPXCHG = 102,
116 G_ATOMICRMW_XCHG = 103,
117 G_ATOMICRMW_ADD = 104,
118 G_ATOMICRMW_SUB = 105,
119 G_ATOMICRMW_AND = 106,
120 G_ATOMICRMW_NAND = 107,
121 G_ATOMICRMW_OR = 108,
122 G_ATOMICRMW_XOR = 109,
123 G_ATOMICRMW_MAX = 110,
124 G_ATOMICRMW_MIN = 111,
125 G_ATOMICRMW_UMAX = 112,
126 G_ATOMICRMW_UMIN = 113,
127 G_ATOMICRMW_FADD = 114,
128 G_ATOMICRMW_FSUB = 115,
129 G_ATOMICRMW_FMAX = 116,
130 G_ATOMICRMW_FMIN = 117,
131 G_ATOMICRMW_FMAXIMUM = 118,
132 G_ATOMICRMW_FMINIMUM = 119,
133 G_ATOMICRMW_UINC_WRAP = 120,
134 G_ATOMICRMW_UDEC_WRAP = 121,
135 G_ATOMICRMW_USUB_COND = 122,
136 G_ATOMICRMW_USUB_SAT = 123,
137 G_FENCE = 124,
138 G_PREFETCH = 125,
139 G_BRCOND = 126,
140 G_BRINDIRECT = 127,
141 G_INVOKE_REGION_START = 128,
142 G_INTRINSIC = 129,
143 G_INTRINSIC_W_SIDE_EFFECTS = 130,
144 G_INTRINSIC_CONVERGENT = 131,
145 G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 132,
146 G_ANYEXT = 133,
147 G_TRUNC = 134,
148 G_CONSTANT = 135,
149 G_FCONSTANT = 136,
150 G_VASTART = 137,
151 G_VAARG = 138,
152 G_SEXT = 139,
153 G_SEXT_INREG = 140,
154 G_ZEXT = 141,
155 G_SHL = 142,
156 G_LSHR = 143,
157 G_ASHR = 144,
158 G_FSHL = 145,
159 G_FSHR = 146,
160 G_ROTR = 147,
161 G_ROTL = 148,
162 G_ICMP = 149,
163 G_FCMP = 150,
164 G_SCMP = 151,
165 G_UCMP = 152,
166 G_SELECT = 153,
167 G_UADDO = 154,
168 G_UADDE = 155,
169 G_USUBO = 156,
170 G_USUBE = 157,
171 G_SADDO = 158,
172 G_SADDE = 159,
173 G_SSUBO = 160,
174 G_SSUBE = 161,
175 G_UMULO = 162,
176 G_SMULO = 163,
177 G_UMULH = 164,
178 G_SMULH = 165,
179 G_UADDSAT = 166,
180 G_SADDSAT = 167,
181 G_USUBSAT = 168,
182 G_SSUBSAT = 169,
183 G_USHLSAT = 170,
184 G_SSHLSAT = 171,
185 G_SMULFIX = 172,
186 G_UMULFIX = 173,
187 G_SMULFIXSAT = 174,
188 G_UMULFIXSAT = 175,
189 G_SDIVFIX = 176,
190 G_UDIVFIX = 177,
191 G_SDIVFIXSAT = 178,
192 G_UDIVFIXSAT = 179,
193 G_FADD = 180,
194 G_FSUB = 181,
195 G_FMUL = 182,
196 G_FMA = 183,
197 G_FMAD = 184,
198 G_FDIV = 185,
199 G_FREM = 186,
200 G_FPOW = 187,
201 G_FPOWI = 188,
202 G_FEXP = 189,
203 G_FEXP2 = 190,
204 G_FEXP10 = 191,
205 G_FLOG = 192,
206 G_FLOG2 = 193,
207 G_FLOG10 = 194,
208 G_FLDEXP = 195,
209 G_FFREXP = 196,
210 G_FNEG = 197,
211 G_FPEXT = 198,
212 G_FPTRUNC = 199,
213 G_FPTOSI = 200,
214 G_FPTOUI = 201,
215 G_SITOFP = 202,
216 G_UITOFP = 203,
217 G_FPTOSI_SAT = 204,
218 G_FPTOUI_SAT = 205,
219 G_FABS = 206,
220 G_FCOPYSIGN = 207,
221 G_IS_FPCLASS = 208,
222 G_FCANONICALIZE = 209,
223 G_FMINNUM = 210,
224 G_FMAXNUM = 211,
225 G_FMINNUM_IEEE = 212,
226 G_FMAXNUM_IEEE = 213,
227 G_FMINIMUM = 214,
228 G_FMAXIMUM = 215,
229 G_FMINIMUMNUM = 216,
230 G_FMAXIMUMNUM = 217,
231 G_GET_FPENV = 218,
232 G_SET_FPENV = 219,
233 G_RESET_FPENV = 220,
234 G_GET_FPMODE = 221,
235 G_SET_FPMODE = 222,
236 G_RESET_FPMODE = 223,
237 G_PTR_ADD = 224,
238 G_PTRMASK = 225,
239 G_SMIN = 226,
240 G_SMAX = 227,
241 G_UMIN = 228,
242 G_UMAX = 229,
243 G_ABS = 230,
244 G_LROUND = 231,
245 G_LLROUND = 232,
246 G_BR = 233,
247 G_BRJT = 234,
248 G_VSCALE = 235,
249 G_INSERT_SUBVECTOR = 236,
250 G_EXTRACT_SUBVECTOR = 237,
251 G_INSERT_VECTOR_ELT = 238,
252 G_EXTRACT_VECTOR_ELT = 239,
253 G_SHUFFLE_VECTOR = 240,
254 G_SPLAT_VECTOR = 241,
255 G_STEP_VECTOR = 242,
256 G_VECTOR_COMPRESS = 243,
257 G_CTTZ = 244,
258 G_CTTZ_ZERO_UNDEF = 245,
259 G_CTLZ = 246,
260 G_CTLZ_ZERO_UNDEF = 247,
261 G_CTPOP = 248,
262 G_BSWAP = 249,
263 G_BITREVERSE = 250,
264 G_FCEIL = 251,
265 G_FCOS = 252,
266 G_FSIN = 253,
267 G_FSINCOS = 254,
268 G_FTAN = 255,
269 G_FACOS = 256,
270 G_FASIN = 257,
271 G_FATAN = 258,
272 G_FATAN2 = 259,
273 G_FCOSH = 260,
274 G_FSINH = 261,
275 G_FTANH = 262,
276 G_FSQRT = 263,
277 G_FFLOOR = 264,
278 G_FRINT = 265,
279 G_FNEARBYINT = 266,
280 G_ADDRSPACE_CAST = 267,
281 G_BLOCK_ADDR = 268,
282 G_JUMP_TABLE = 269,
283 G_DYN_STACKALLOC = 270,
284 G_STACKSAVE = 271,
285 G_STACKRESTORE = 272,
286 G_STRICT_FADD = 273,
287 G_STRICT_FSUB = 274,
288 G_STRICT_FMUL = 275,
289 G_STRICT_FDIV = 276,
290 G_STRICT_FREM = 277,
291 G_STRICT_FMA = 278,
292 G_STRICT_FSQRT = 279,
293 G_STRICT_FLDEXP = 280,
294 G_READ_REGISTER = 281,
295 G_WRITE_REGISTER = 282,
296 G_MEMCPY = 283,
297 G_MEMCPY_INLINE = 284,
298 G_MEMMOVE = 285,
299 G_MEMSET = 286,
300 G_BZERO = 287,
301 G_TRAP = 288,
302 G_DEBUGTRAP = 289,
303 G_UBSANTRAP = 290,
304 G_VECREDUCE_SEQ_FADD = 291,
305 G_VECREDUCE_SEQ_FMUL = 292,
306 G_VECREDUCE_FADD = 293,
307 G_VECREDUCE_FMUL = 294,
308 G_VECREDUCE_FMAX = 295,
309 G_VECREDUCE_FMIN = 296,
310 G_VECREDUCE_FMAXIMUM = 297,
311 G_VECREDUCE_FMINIMUM = 298,
312 G_VECREDUCE_ADD = 299,
313 G_VECREDUCE_MUL = 300,
314 G_VECREDUCE_AND = 301,
315 G_VECREDUCE_OR = 302,
316 G_VECREDUCE_XOR = 303,
317 G_VECREDUCE_SMAX = 304,
318 G_VECREDUCE_SMIN = 305,
319 G_VECREDUCE_UMAX = 306,
320 G_VECREDUCE_UMIN = 307,
321 G_SBFX = 308,
322 G_UBFX = 309,
323 A2_addsp = 310,
324 A2_iconst = 311,
325 A2_neg = 312,
326 A2_not = 313,
327 A2_tfrf = 314,
328 A2_tfrfnew = 315,
329 A2_tfrp = 316,
330 A2_tfrpf = 317,
331 A2_tfrpfnew = 318,
332 A2_tfrpi = 319,
333 A2_tfrpt = 320,
334 A2_tfrptnew = 321,
335 A2_tfrt = 322,
336 A2_tfrtnew = 323,
337 A2_vaddb_map = 324,
338 A2_vsubb_map = 325,
339 A2_zxtb = 326,
340 A4_boundscheck = 327,
341 ADJCALLSTACKDOWN = 328,
342 ADJCALLSTACKUP = 329,
343 C2_cmpgei = 330,
344 C2_cmpgeui = 331,
345 C2_cmplt = 332,
346 C2_cmpltu = 333,
347 C2_pxfer_map = 334,
348 DUPLEX_Pseudo = 335,
349 ENDLOOP0 = 336,
350 ENDLOOP01 = 337,
351 ENDLOOP1 = 338,
352 J2_endloop0 = 339,
353 J2_endloop01 = 340,
354 J2_endloop1 = 341,
355 J2_jumpf_nopred_map = 342,
356 J2_jumprf_nopred_map = 343,
357 J2_jumprt_nopred_map = 344,
358 J2_jumpt_nopred_map = 345,
359 J2_trap1_noregmap = 346,
360 L2_loadalignb_zomap = 347,
361 L2_loadalignh_zomap = 348,
362 L2_loadbsw2_zomap = 349,
363 L2_loadbsw4_zomap = 350,
364 L2_loadbzw2_zomap = 351,
365 L2_loadbzw4_zomap = 352,
366 L2_loadrb_zomap = 353,
367 L2_loadrd_zomap = 354,
368 L2_loadrh_zomap = 355,
369 L2_loadri_zomap = 356,
370 L2_loadrub_zomap = 357,
371 L2_loadruh_zomap = 358,
372 L2_ploadrbf_zomap = 359,
373 L2_ploadrbfnew_zomap = 360,
374 L2_ploadrbt_zomap = 361,
375 L2_ploadrbtnew_zomap = 362,
376 L2_ploadrdf_zomap = 363,
377 L2_ploadrdfnew_zomap = 364,
378 L2_ploadrdt_zomap = 365,
379 L2_ploadrdtnew_zomap = 366,
380 L2_ploadrhf_zomap = 367,
381 L2_ploadrhfnew_zomap = 368,
382 L2_ploadrht_zomap = 369,
383 L2_ploadrhtnew_zomap = 370,
384 L2_ploadrif_zomap = 371,
385 L2_ploadrifnew_zomap = 372,
386 L2_ploadrit_zomap = 373,
387 L2_ploadritnew_zomap = 374,
388 L2_ploadrubf_zomap = 375,
389 L2_ploadrubfnew_zomap = 376,
390 L2_ploadrubt_zomap = 377,
391 L2_ploadrubtnew_zomap = 378,
392 L2_ploadruhf_zomap = 379,
393 L2_ploadruhfnew_zomap = 380,
394 L2_ploadruht_zomap = 381,
395 L2_ploadruhtnew_zomap = 382,
396 L4_add_memopb_zomap = 383,
397 L4_add_memoph_zomap = 384,
398 L4_add_memopw_zomap = 385,
399 L4_and_memopb_zomap = 386,
400 L4_and_memoph_zomap = 387,
401 L4_and_memopw_zomap = 388,
402 L4_iadd_memopb_zomap = 389,
403 L4_iadd_memoph_zomap = 390,
404 L4_iadd_memopw_zomap = 391,
405 L4_iand_memopb_zomap = 392,
406 L4_iand_memoph_zomap = 393,
407 L4_iand_memopw_zomap = 394,
408 L4_ior_memopb_zomap = 395,
409 L4_ior_memoph_zomap = 396,
410 L4_ior_memopw_zomap = 397,
411 L4_isub_memopb_zomap = 398,
412 L4_isub_memoph_zomap = 399,
413 L4_isub_memopw_zomap = 400,
414 L4_or_memopb_zomap = 401,
415 L4_or_memoph_zomap = 402,
416 L4_or_memopw_zomap = 403,
417 L4_return_map_to_raw_f = 404,
418 L4_return_map_to_raw_fnew_pnt = 405,
419 L4_return_map_to_raw_fnew_pt = 406,
420 L4_return_map_to_raw_t = 407,
421 L4_return_map_to_raw_tnew_pnt = 408,
422 L4_return_map_to_raw_tnew_pt = 409,
423 L4_sub_memopb_zomap = 410,
424 L4_sub_memoph_zomap = 411,
425 L4_sub_memopw_zomap = 412,
426 L6_deallocframe_map_to_raw = 413,
427 L6_return_map_to_raw = 414,
428 LDriw_ctr = 415,
429 LDriw_pred = 416,
430 M2_mpysmi = 417,
431 M2_mpyui = 418,
432 M2_vrcmpys_acc_s1 = 419,
433 M2_vrcmpys_s1 = 420,
434 M2_vrcmpys_s1rp = 421,
435 M7_vdmpy = 422,
436 M7_vdmpy_acc = 423,
437 PS_aligna = 424,
438 PS_alloca = 425,
439 PS_call_instrprof_custom = 426,
440 PS_call_nr = 427,
441 PS_crash = 428,
442 PS_false = 429,
443 PS_fi = 430,
444 PS_fia = 431,
445 PS_loadrb_pci = 432,
446 PS_loadrb_pcr = 433,
447 PS_loadrd_pci = 434,
448 PS_loadrd_pcr = 435,
449 PS_loadrh_pci = 436,
450 PS_loadrh_pcr = 437,
451 PS_loadri_pci = 438,
452 PS_loadri_pcr = 439,
453 PS_loadrub_pci = 440,
454 PS_loadrub_pcr = 441,
455 PS_loadruh_pci = 442,
456 PS_loadruh_pcr = 443,
457 PS_pselect = 444,
458 PS_qfalse = 445,
459 PS_qtrue = 446,
460 PS_storerb_pci = 447,
461 PS_storerb_pcr = 448,
462 PS_storerd_pci = 449,
463 PS_storerd_pcr = 450,
464 PS_storerf_pci = 451,
465 PS_storerf_pcr = 452,
466 PS_storerh_pci = 453,
467 PS_storerh_pcr = 454,
468 PS_storeri_pci = 455,
469 PS_storeri_pcr = 456,
470 PS_tailcall_i = 457,
471 PS_tailcall_r = 458,
472 PS_true = 459,
473 PS_vdd0 = 460,
474 PS_vloadrq_ai = 461,
475 PS_vloadrv_ai = 462,
476 PS_vloadrv_nt_ai = 463,
477 PS_vloadrw_ai = 464,
478 PS_vloadrw_nt_ai = 465,
479 PS_vmulw = 466,
480 PS_vmulw_acc = 467,
481 PS_vselect = 468,
482 PS_vsplatib = 469,
483 PS_vsplatih = 470,
484 PS_vsplatiw = 471,
485 PS_vsplatrb = 472,
486 PS_vsplatrh = 473,
487 PS_vsplatrw = 474,
488 PS_vstorerq_ai = 475,
489 PS_vstorerv_ai = 476,
490 PS_vstorerv_nt_ai = 477,
491 PS_vstorerw_ai = 478,
492 PS_vstorerw_nt_ai = 479,
493 PS_wselect = 480,
494 S2_asr_i_p_rnd_goodsyntax = 481,
495 S2_asr_i_r_rnd_goodsyntax = 482,
496 S2_pstorerbf_zomap = 483,
497 S2_pstorerbnewf_zomap = 484,
498 S2_pstorerbnewt_zomap = 485,
499 S2_pstorerbt_zomap = 486,
500 S2_pstorerdf_zomap = 487,
501 S2_pstorerdt_zomap = 488,
502 S2_pstorerff_zomap = 489,
503 S2_pstorerft_zomap = 490,
504 S2_pstorerhf_zomap = 491,
505 S2_pstorerhnewf_zomap = 492,
506 S2_pstorerhnewt_zomap = 493,
507 S2_pstorerht_zomap = 494,
508 S2_pstorerif_zomap = 495,
509 S2_pstorerinewf_zomap = 496,
510 S2_pstorerinewt_zomap = 497,
511 S2_pstorerit_zomap = 498,
512 S2_storerb_zomap = 499,
513 S2_storerbnew_zomap = 500,
514 S2_storerd_zomap = 501,
515 S2_storerf_zomap = 502,
516 S2_storerh_zomap = 503,
517 S2_storerhnew_zomap = 504,
518 S2_storeri_zomap = 505,
519 S2_storerinew_zomap = 506,
520 S2_tableidxb_goodsyntax = 507,
521 S2_tableidxd_goodsyntax = 508,
522 S2_tableidxh_goodsyntax = 509,
523 S2_tableidxw_goodsyntax = 510,
524 S4_pstorerbfnew_zomap = 511,
525 S4_pstorerbnewfnew_zomap = 512,
526 S4_pstorerbnewtnew_zomap = 513,
527 S4_pstorerbtnew_zomap = 514,
528 S4_pstorerdfnew_zomap = 515,
529 S4_pstorerdtnew_zomap = 516,
530 S4_pstorerffnew_zomap = 517,
531 S4_pstorerftnew_zomap = 518,
532 S4_pstorerhfnew_zomap = 519,
533 S4_pstorerhnewfnew_zomap = 520,
534 S4_pstorerhnewtnew_zomap = 521,
535 S4_pstorerhtnew_zomap = 522,
536 S4_pstorerifnew_zomap = 523,
537 S4_pstorerinewfnew_zomap = 524,
538 S4_pstorerinewtnew_zomap = 525,
539 S4_pstoreritnew_zomap = 526,
540 S4_storeirb_zomap = 527,
541 S4_storeirbf_zomap = 528,
542 S4_storeirbfnew_zomap = 529,
543 S4_storeirbt_zomap = 530,
544 S4_storeirbtnew_zomap = 531,
545 S4_storeirh_zomap = 532,
546 S4_storeirhf_zomap = 533,
547 S4_storeirhfnew_zomap = 534,
548 S4_storeirht_zomap = 535,
549 S4_storeirhtnew_zomap = 536,
550 S4_storeiri_zomap = 537,
551 S4_storeirif_zomap = 538,
552 S4_storeirifnew_zomap = 539,
553 S4_storeirit_zomap = 540,
554 S4_storeiritnew_zomap = 541,
555 S5_asrhub_rnd_sat_goodsyntax = 542,
556 S5_vasrhrnd_goodsyntax = 543,
557 S6_allocframe_to_raw = 544,
558 STriw_ctr = 545,
559 STriw_pred = 546,
560 V6_MAP_equb = 547,
561 V6_MAP_equb_and = 548,
562 V6_MAP_equb_ior = 549,
563 V6_MAP_equb_xor = 550,
564 V6_MAP_equh = 551,
565 V6_MAP_equh_and = 552,
566 V6_MAP_equh_ior = 553,
567 V6_MAP_equh_xor = 554,
568 V6_MAP_equw = 555,
569 V6_MAP_equw_and = 556,
570 V6_MAP_equw_ior = 557,
571 V6_MAP_equw_xor = 558,
572 V6_dbl_ld0 = 559,
573 V6_dbl_st0 = 560,
574 V6_extractw_alt = 561,
575 V6_hi = 562,
576 V6_ld0 = 563,
577 V6_ldcnp0 = 564,
578 V6_ldcnpnt0 = 565,
579 V6_ldcp0 = 566,
580 V6_ldcpnt0 = 567,
581 V6_ldnp0 = 568,
582 V6_ldnpnt0 = 569,
583 V6_ldnt0 = 570,
584 V6_ldp0 = 571,
585 V6_ldpnt0 = 572,
586 V6_ldtnp0 = 573,
587 V6_ldtnpnt0 = 574,
588 V6_ldtp0 = 575,
589 V6_ldtpnt0 = 576,
590 V6_ldu0 = 577,
591 V6_lo = 578,
592 V6_st0 = 579,
593 V6_stn0 = 580,
594 V6_stnnt0 = 581,
595 V6_stnp0 = 582,
596 V6_stnpnt0 = 583,
597 V6_stnq0 = 584,
598 V6_stnqnt0 = 585,
599 V6_stnt0 = 586,
600 V6_stp0 = 587,
601 V6_stpnt0 = 588,
602 V6_stq0 = 589,
603 V6_stqnt0 = 590,
604 V6_stu0 = 591,
605 V6_stunp0 = 592,
606 V6_stup0 = 593,
607 V6_v10mpyubs10 = 594,
608 V6_v10mpyubs10_vxx = 595,
609 V6_v6mpyhubs10_alt = 596,
610 V6_v6mpyvubs10_alt = 597,
611 V6_vabsb_alt = 598,
612 V6_vabsb_sat_alt = 599,
613 V6_vabsdiffh_alt = 600,
614 V6_vabsdiffub_alt = 601,
615 V6_vabsdiffuh_alt = 602,
616 V6_vabsdiffw_alt = 603,
617 V6_vabsh_alt = 604,
618 V6_vabsh_sat_alt = 605,
619 V6_vabsub_alt = 606,
620 V6_vabsuh_alt = 607,
621 V6_vabsuw_alt = 608,
622 V6_vabsw_alt = 609,
623 V6_vabsw_sat_alt = 610,
624 V6_vaddb_alt = 611,
625 V6_vaddb_dv_alt = 612,
626 V6_vaddbnq_alt = 613,
627 V6_vaddbq_alt = 614,
628 V6_vaddbsat_alt = 615,
629 V6_vaddbsat_dv_alt = 616,
630 V6_vaddh_alt = 617,
631 V6_vaddh_dv_alt = 618,
632 V6_vaddhnq_alt = 619,
633 V6_vaddhq_alt = 620,
634 V6_vaddhsat_alt = 621,
635 V6_vaddhsat_dv_alt = 622,
636 V6_vaddhw_acc_alt = 623,
637 V6_vaddhw_alt = 624,
638 V6_vaddubh_acc_alt = 625,
639 V6_vaddubh_alt = 626,
640 V6_vaddubsat_alt = 627,
641 V6_vaddubsat_dv_alt = 628,
642 V6_vadduhsat_alt = 629,
643 V6_vadduhsat_dv_alt = 630,
644 V6_vadduhw_acc_alt = 631,
645 V6_vadduhw_alt = 632,
646 V6_vadduwsat_alt = 633,
647 V6_vadduwsat_dv_alt = 634,
648 V6_vaddw_alt = 635,
649 V6_vaddw_dv_alt = 636,
650 V6_vaddwnq_alt = 637,
651 V6_vaddwq_alt = 638,
652 V6_vaddwsat_alt = 639,
653 V6_vaddwsat_dv_alt = 640,
654 V6_vandnqrt_acc_alt = 641,
655 V6_vandnqrt_alt = 642,
656 V6_vandqrt_acc_alt = 643,
657 V6_vandqrt_alt = 644,
658 V6_vandvrt_acc_alt = 645,
659 V6_vandvrt_alt = 646,
660 V6_vaslh_acc_alt = 647,
661 V6_vaslh_alt = 648,
662 V6_vaslhv_alt = 649,
663 V6_vaslw_acc_alt = 650,
664 V6_vaslw_alt = 651,
665 V6_vaslwv_alt = 652,
666 V6_vasr_into_alt = 653,
667 V6_vasrh_acc_alt = 654,
668 V6_vasrh_alt = 655,
669 V6_vasrhv_alt = 656,
670 V6_vasrw_acc_alt = 657,
671 V6_vasrw_alt = 658,
672 V6_vasrwv_alt = 659,
673 V6_vassignp = 660,
674 V6_vavgb_alt = 661,
675 V6_vavgbrnd_alt = 662,
676 V6_vavgh_alt = 663,
677 V6_vavghrnd_alt = 664,
678 V6_vavgub_alt = 665,
679 V6_vavgubrnd_alt = 666,
680 V6_vavguh_alt = 667,
681 V6_vavguhrnd_alt = 668,
682 V6_vavguw_alt = 669,
683 V6_vavguwrnd_alt = 670,
684 V6_vavgw_alt = 671,
685 V6_vavgwrnd_alt = 672,
686 V6_vcl0h_alt = 673,
687 V6_vcl0w_alt = 674,
688 V6_vd0 = 675,
689 V6_vdd0 = 676,
690 V6_vdealb4w_alt = 677,
691 V6_vdealb_alt = 678,
692 V6_vdealh_alt = 679,
693 V6_vdmpybus_acc_alt = 680,
694 V6_vdmpybus_alt = 681,
695 V6_vdmpybus_dv_acc_alt = 682,
696 V6_vdmpybus_dv_alt = 683,
697 V6_vdmpyhb_acc_alt = 684,
698 V6_vdmpyhb_alt = 685,
699 V6_vdmpyhb_dv_acc_alt = 686,
700 V6_vdmpyhb_dv_alt = 687,
701 V6_vdmpyhisat_acc_alt = 688,
702 V6_vdmpyhisat_alt = 689,
703 V6_vdmpyhsat_acc_alt = 690,
704 V6_vdmpyhsat_alt = 691,
705 V6_vdmpyhsuisat_acc_alt = 692,
706 V6_vdmpyhsuisat_alt = 693,
707 V6_vdmpyhsusat_acc_alt = 694,
708 V6_vdmpyhsusat_alt = 695,
709 V6_vdmpyhvsat_acc_alt = 696,
710 V6_vdmpyhvsat_alt = 697,
711 V6_vdsaduh_acc_alt = 698,
712 V6_vdsaduh_alt = 699,
713 V6_vgathermh_pseudo = 700,
714 V6_vgathermhq_pseudo = 701,
715 V6_vgathermhw_pseudo = 702,
716 V6_vgathermhwq_pseudo = 703,
717 V6_vgathermw_pseudo = 704,
718 V6_vgathermwq_pseudo = 705,
719 V6_vlsrh_alt = 706,
720 V6_vlsrhv_alt = 707,
721 V6_vlsrw_alt = 708,
722 V6_vlsrwv_alt = 709,
723 V6_vmaxb_alt = 710,
724 V6_vmaxh_alt = 711,
725 V6_vmaxub_alt = 712,
726 V6_vmaxuh_alt = 713,
727 V6_vmaxw_alt = 714,
728 V6_vminb_alt = 715,
729 V6_vminh_alt = 716,
730 V6_vminub_alt = 717,
731 V6_vminuh_alt = 718,
732 V6_vminw_alt = 719,
733 V6_vmpabus_acc_alt = 720,
734 V6_vmpabus_alt = 721,
735 V6_vmpabusv_alt = 722,
736 V6_vmpabuu_acc_alt = 723,
737 V6_vmpabuu_alt = 724,
738 V6_vmpabuuv_alt = 725,
739 V6_vmpahb_acc_alt = 726,
740 V6_vmpahb_alt = 727,
741 V6_vmpauhb_acc_alt = 728,
742 V6_vmpauhb_alt = 729,
743 V6_vmpybus_acc_alt = 730,
744 V6_vmpybus_alt = 731,
745 V6_vmpybusv_acc_alt = 732,
746 V6_vmpybusv_alt = 733,
747 V6_vmpybv_acc_alt = 734,
748 V6_vmpybv_alt = 735,
749 V6_vmpyewuh_alt = 736,
750 V6_vmpyh_acc_alt = 737,
751 V6_vmpyh_alt = 738,
752 V6_vmpyhsat_acc_alt = 739,
753 V6_vmpyhsrs_alt = 740,
754 V6_vmpyhss_alt = 741,
755 V6_vmpyhus_acc_alt = 742,
756 V6_vmpyhus_alt = 743,
757 V6_vmpyhv_acc_alt = 744,
758 V6_vmpyhv_alt = 745,
759 V6_vmpyhvsrs_alt = 746,
760 V6_vmpyiewh_acc_alt = 747,
761 V6_vmpyiewuh_acc_alt = 748,
762 V6_vmpyiewuh_alt = 749,
763 V6_vmpyih_acc_alt = 750,
764 V6_vmpyih_alt = 751,
765 V6_vmpyihb_acc_alt = 752,
766 V6_vmpyihb_alt = 753,
767 V6_vmpyiowh_alt = 754,
768 V6_vmpyiwb_acc_alt = 755,
769 V6_vmpyiwb_alt = 756,
770 V6_vmpyiwh_acc_alt = 757,
771 V6_vmpyiwh_alt = 758,
772 V6_vmpyiwub_acc_alt = 759,
773 V6_vmpyiwub_alt = 760,
774 V6_vmpyowh_alt = 761,
775 V6_vmpyowh_rnd_alt = 762,
776 V6_vmpyowh_rnd_sacc_alt = 763,
777 V6_vmpyowh_sacc_alt = 764,
778 V6_vmpyub_acc_alt = 765,
779 V6_vmpyub_alt = 766,
780 V6_vmpyubv_acc_alt = 767,
781 V6_vmpyubv_alt = 768,
782 V6_vmpyuh_acc_alt = 769,
783 V6_vmpyuh_alt = 770,
784 V6_vmpyuhv_acc_alt = 771,
785 V6_vmpyuhv_alt = 772,
786 V6_vnavgb_alt = 773,
787 V6_vnavgh_alt = 774,
788 V6_vnavgub_alt = 775,
789 V6_vnavgw_alt = 776,
790 V6_vnormamth_alt = 777,
791 V6_vnormamtw_alt = 778,
792 V6_vpackeb_alt = 779,
793 V6_vpackeh_alt = 780,
794 V6_vpackhb_sat_alt = 781,
795 V6_vpackhub_sat_alt = 782,
796 V6_vpackob_alt = 783,
797 V6_vpackoh_alt = 784,
798 V6_vpackwh_sat_alt = 785,
799 V6_vpackwuh_sat_alt = 786,
800 V6_vpopcounth_alt = 787,
801 V6_vrmpybub_rtt_acc_alt = 788,
802 V6_vrmpybub_rtt_alt = 789,
803 V6_vrmpybus_acc_alt = 790,
804 V6_vrmpybus_alt = 791,
805 V6_vrmpybusi_acc_alt = 792,
806 V6_vrmpybusi_alt = 793,
807 V6_vrmpybusv_acc_alt = 794,
808 V6_vrmpybusv_alt = 795,
809 V6_vrmpybv_acc_alt = 796,
810 V6_vrmpybv_alt = 797,
811 V6_vrmpyub_acc_alt = 798,
812 V6_vrmpyub_alt = 799,
813 V6_vrmpyub_rtt_acc_alt = 800,
814 V6_vrmpyub_rtt_alt = 801,
815 V6_vrmpyubi_acc_alt = 802,
816 V6_vrmpyubi_alt = 803,
817 V6_vrmpyubv_acc_alt = 804,
818 V6_vrmpyubv_alt = 805,
819 V6_vrotr_alt = 806,
820 V6_vroundhb_alt = 807,
821 V6_vroundhub_alt = 808,
822 V6_vrounduhub_alt = 809,
823 V6_vrounduwuh_alt = 810,
824 V6_vroundwh_alt = 811,
825 V6_vroundwuh_alt = 812,
826 V6_vrsadubi_acc_alt = 813,
827 V6_vrsadubi_alt = 814,
828 V6_vsathub_alt = 815,
829 V6_vsatuwuh_alt = 816,
830 V6_vsatwh_alt = 817,
831 V6_vsb_alt = 818,
832 V6_vscattermh_add_alt = 819,
833 V6_vscattermh_alt = 820,
834 V6_vscattermhq_alt = 821,
835 V6_vscattermw_add_alt = 822,
836 V6_vscattermw_alt = 823,
837 V6_vscattermwh_add_alt = 824,
838 V6_vscattermwh_alt = 825,
839 V6_vscattermwhq_alt = 826,
840 V6_vscattermwq_alt = 827,
841 V6_vsh_alt = 828,
842 V6_vshufeh_alt = 829,
843 V6_vshuffb_alt = 830,
844 V6_vshuffeb_alt = 831,
845 V6_vshuffh_alt = 832,
846 V6_vshuffob_alt = 833,
847 V6_vshufoeb_alt = 834,
848 V6_vshufoeh_alt = 835,
849 V6_vshufoh_alt = 836,
850 V6_vsubb_alt = 837,
851 V6_vsubb_dv_alt = 838,
852 V6_vsubbnq_alt = 839,
853 V6_vsubbq_alt = 840,
854 V6_vsubbsat_alt = 841,
855 V6_vsubbsat_dv_alt = 842,
856 V6_vsubh_alt = 843,
857 V6_vsubh_dv_alt = 844,
858 V6_vsubhnq_alt = 845,
859 V6_vsubhq_alt = 846,
860 V6_vsubhsat_alt = 847,
861 V6_vsubhsat_dv_alt = 848,
862 V6_vsubhw_alt = 849,
863 V6_vsububh_alt = 850,
864 V6_vsububsat_alt = 851,
865 V6_vsububsat_dv_alt = 852,
866 V6_vsubuhsat_alt = 853,
867 V6_vsubuhsat_dv_alt = 854,
868 V6_vsubuhw_alt = 855,
869 V6_vsubuwsat_alt = 856,
870 V6_vsubuwsat_dv_alt = 857,
871 V6_vsubw_alt = 858,
872 V6_vsubw_dv_alt = 859,
873 V6_vsubwnq_alt = 860,
874 V6_vsubwq_alt = 861,
875 V6_vsubwsat_alt = 862,
876 V6_vsubwsat_dv_alt = 863,
877 V6_vtmpyb_acc_alt = 864,
878 V6_vtmpyb_alt = 865,
879 V6_vtmpybus_acc_alt = 866,
880 V6_vtmpybus_alt = 867,
881 V6_vtmpyhb_acc_alt = 868,
882 V6_vtmpyhb_alt = 869,
883 V6_vtran2x2_map = 870,
884 V6_vunpackb_alt = 871,
885 V6_vunpackh_alt = 872,
886 V6_vunpackob_alt = 873,
887 V6_vunpackoh_alt = 874,
888 V6_vunpackub_alt = 875,
889 V6_vunpackuh_alt = 876,
890 V6_vzb_alt = 877,
891 V6_vzh_alt = 878,
892 V6_zld0 = 879,
893 V6_zldp0 = 880,
894 Y2_crswap_old = 881,
895 Y2_dcfetch = 882,
896 Y2_k1lock_map = 883,
897 Y2_k1unlock_map = 884,
898 dup_A2_add = 885,
899 dup_A2_addi = 886,
900 dup_A2_andir = 887,
901 dup_A2_combineii = 888,
902 dup_A2_sxtb = 889,
903 dup_A2_sxth = 890,
904 dup_A2_tfr = 891,
905 dup_A2_tfrsi = 892,
906 dup_A2_zxtb = 893,
907 dup_A2_zxth = 894,
908 dup_A4_combineii = 895,
909 dup_A4_combineir = 896,
910 dup_A4_combineri = 897,
911 dup_C2_cmoveif = 898,
912 dup_C2_cmoveit = 899,
913 dup_C2_cmovenewif = 900,
914 dup_C2_cmovenewit = 901,
915 dup_C2_cmpeqi = 902,
916 dup_L2_deallocframe = 903,
917 dup_L2_loadrb_io = 904,
918 dup_L2_loadrd_io = 905,
919 dup_L2_loadrh_io = 906,
920 dup_L2_loadri_io = 907,
921 dup_L2_loadrub_io = 908,
922 dup_L2_loadruh_io = 909,
923 dup_S2_allocframe = 910,
924 dup_S2_storerb_io = 911,
925 dup_S2_storerd_io = 912,
926 dup_S2_storerh_io = 913,
927 dup_S2_storeri_io = 914,
928 dup_S4_storeirb_io = 915,
929 dup_S4_storeiri_io = 916,
930 A2_abs = 917,
931 A2_absp = 918,
932 A2_abssat = 919,
933 A2_add = 920,
934 A2_addh_h16_hh = 921,
935 A2_addh_h16_hl = 922,
936 A2_addh_h16_lh = 923,
937 A2_addh_h16_ll = 924,
938 A2_addh_h16_sat_hh = 925,
939 A2_addh_h16_sat_hl = 926,
940 A2_addh_h16_sat_lh = 927,
941 A2_addh_h16_sat_ll = 928,
942 A2_addh_l16_hl = 929,
943 A2_addh_l16_ll = 930,
944 A2_addh_l16_sat_hl = 931,
945 A2_addh_l16_sat_ll = 932,
946 A2_addi = 933,
947 A2_addp = 934,
948 A2_addpsat = 935,
949 A2_addsat = 936,
950 A2_addsph = 937,
951 A2_addspl = 938,
952 A2_and = 939,
953 A2_andir = 940,
954 A2_andp = 941,
955 A2_aslh = 942,
956 A2_asrh = 943,
957 A2_combine_hh = 944,
958 A2_combine_hl = 945,
959 A2_combine_lh = 946,
960 A2_combine_ll = 947,
961 A2_combineii = 948,
962 A2_combinew = 949,
963 A2_max = 950,
964 A2_maxp = 951,
965 A2_maxu = 952,
966 A2_maxup = 953,
967 A2_min = 954,
968 A2_minp = 955,
969 A2_minu = 956,
970 A2_minup = 957,
971 A2_negp = 958,
972 A2_negsat = 959,
973 A2_nop = 960,
974 A2_notp = 961,
975 A2_or = 962,
976 A2_orir = 963,
977 A2_orp = 964,
978 A2_paddf = 965,
979 A2_paddfnew = 966,
980 A2_paddif = 967,
981 A2_paddifnew = 968,
982 A2_paddit = 969,
983 A2_padditnew = 970,
984 A2_paddt = 971,
985 A2_paddtnew = 972,
986 A2_pandf = 973,
987 A2_pandfnew = 974,
988 A2_pandt = 975,
989 A2_pandtnew = 976,
990 A2_porf = 977,
991 A2_porfnew = 978,
992 A2_port = 979,
993 A2_portnew = 980,
994 A2_psubf = 981,
995 A2_psubfnew = 982,
996 A2_psubt = 983,
997 A2_psubtnew = 984,
998 A2_pxorf = 985,
999 A2_pxorfnew = 986,
1000 A2_pxort = 987,
1001 A2_pxortnew = 988,
1002 A2_roundsat = 989,
1003 A2_sat = 990,
1004 A2_satb = 991,
1005 A2_sath = 992,
1006 A2_satub = 993,
1007 A2_satuh = 994,
1008 A2_sub = 995,
1009 A2_subh_h16_hh = 996,
1010 A2_subh_h16_hl = 997,
1011 A2_subh_h16_lh = 998,
1012 A2_subh_h16_ll = 999,
1013 A2_subh_h16_sat_hh = 1000,
1014 A2_subh_h16_sat_hl = 1001,
1015 A2_subh_h16_sat_lh = 1002,
1016 A2_subh_h16_sat_ll = 1003,
1017 A2_subh_l16_hl = 1004,
1018 A2_subh_l16_ll = 1005,
1019 A2_subh_l16_sat_hl = 1006,
1020 A2_subh_l16_sat_ll = 1007,
1021 A2_subp = 1008,
1022 A2_subri = 1009,
1023 A2_subsat = 1010,
1024 A2_svaddh = 1011,
1025 A2_svaddhs = 1012,
1026 A2_svadduhs = 1013,
1027 A2_svavgh = 1014,
1028 A2_svavghs = 1015,
1029 A2_svnavgh = 1016,
1030 A2_svsubh = 1017,
1031 A2_svsubhs = 1018,
1032 A2_svsubuhs = 1019,
1033 A2_swiz = 1020,
1034 A2_sxtb = 1021,
1035 A2_sxth = 1022,
1036 A2_sxtw = 1023,
1037 A2_tfr = 1024,
1038 A2_tfrcrr = 1025,
1039 A2_tfrih = 1026,
1040 A2_tfril = 1027,
1041 A2_tfrrcr = 1028,
1042 A2_tfrsi = 1029,
1043 A2_vabsh = 1030,
1044 A2_vabshsat = 1031,
1045 A2_vabsw = 1032,
1046 A2_vabswsat = 1033,
1047 A2_vaddh = 1034,
1048 A2_vaddhs = 1035,
1049 A2_vaddub = 1036,
1050 A2_vaddubs = 1037,
1051 A2_vadduhs = 1038,
1052 A2_vaddw = 1039,
1053 A2_vaddws = 1040,
1054 A2_vavgh = 1041,
1055 A2_vavghcr = 1042,
1056 A2_vavghr = 1043,
1057 A2_vavgub = 1044,
1058 A2_vavgubr = 1045,
1059 A2_vavguh = 1046,
1060 A2_vavguhr = 1047,
1061 A2_vavguw = 1048,
1062 A2_vavguwr = 1049,
1063 A2_vavgw = 1050,
1064 A2_vavgwcr = 1051,
1065 A2_vavgwr = 1052,
1066 A2_vcmpbeq = 1053,
1067 A2_vcmpbgtu = 1054,
1068 A2_vcmpheq = 1055,
1069 A2_vcmphgt = 1056,
1070 A2_vcmphgtu = 1057,
1071 A2_vcmpweq = 1058,
1072 A2_vcmpwgt = 1059,
1073 A2_vcmpwgtu = 1060,
1074 A2_vconj = 1061,
1075 A2_vmaxb = 1062,
1076 A2_vmaxh = 1063,
1077 A2_vmaxub = 1064,
1078 A2_vmaxuh = 1065,
1079 A2_vmaxuw = 1066,
1080 A2_vmaxw = 1067,
1081 A2_vminb = 1068,
1082 A2_vminh = 1069,
1083 A2_vminub = 1070,
1084 A2_vminuh = 1071,
1085 A2_vminuw = 1072,
1086 A2_vminw = 1073,
1087 A2_vnavgh = 1074,
1088 A2_vnavghcr = 1075,
1089 A2_vnavghr = 1076,
1090 A2_vnavgw = 1077,
1091 A2_vnavgwcr = 1078,
1092 A2_vnavgwr = 1079,
1093 A2_vraddub = 1080,
1094 A2_vraddub_acc = 1081,
1095 A2_vrsadub = 1082,
1096 A2_vrsadub_acc = 1083,
1097 A2_vsubh = 1084,
1098 A2_vsubhs = 1085,
1099 A2_vsubub = 1086,
1100 A2_vsububs = 1087,
1101 A2_vsubuhs = 1088,
1102 A2_vsubw = 1089,
1103 A2_vsubws = 1090,
1104 A2_xor = 1091,
1105 A2_xorp = 1092,
1106 A2_zxth = 1093,
1107 A4_addp_c = 1094,
1108 A4_andn = 1095,
1109 A4_andnp = 1096,
1110 A4_bitsplit = 1097,
1111 A4_bitspliti = 1098,
1112 A4_boundscheck_hi = 1099,
1113 A4_boundscheck_lo = 1100,
1114 A4_cmpbeq = 1101,
1115 A4_cmpbeqi = 1102,
1116 A4_cmpbgt = 1103,
1117 A4_cmpbgti = 1104,
1118 A4_cmpbgtu = 1105,
1119 A4_cmpbgtui = 1106,
1120 A4_cmpheq = 1107,
1121 A4_cmpheqi = 1108,
1122 A4_cmphgt = 1109,
1123 A4_cmphgti = 1110,
1124 A4_cmphgtu = 1111,
1125 A4_cmphgtui = 1112,
1126 A4_combineii = 1113,
1127 A4_combineir = 1114,
1128 A4_combineri = 1115,
1129 A4_cround_ri = 1116,
1130 A4_cround_rr = 1117,
1131 A4_ext = 1118,
1132 A4_modwrapu = 1119,
1133 A4_orn = 1120,
1134 A4_ornp = 1121,
1135 A4_paslhf = 1122,
1136 A4_paslhfnew = 1123,
1137 A4_paslht = 1124,
1138 A4_paslhtnew = 1125,
1139 A4_pasrhf = 1126,
1140 A4_pasrhfnew = 1127,
1141 A4_pasrht = 1128,
1142 A4_pasrhtnew = 1129,
1143 A4_psxtbf = 1130,
1144 A4_psxtbfnew = 1131,
1145 A4_psxtbt = 1132,
1146 A4_psxtbtnew = 1133,
1147 A4_psxthf = 1134,
1148 A4_psxthfnew = 1135,
1149 A4_psxtht = 1136,
1150 A4_psxthtnew = 1137,
1151 A4_pzxtbf = 1138,
1152 A4_pzxtbfnew = 1139,
1153 A4_pzxtbt = 1140,
1154 A4_pzxtbtnew = 1141,
1155 A4_pzxthf = 1142,
1156 A4_pzxthfnew = 1143,
1157 A4_pzxtht = 1144,
1158 A4_pzxthtnew = 1145,
1159 A4_rcmpeq = 1146,
1160 A4_rcmpeqi = 1147,
1161 A4_rcmpneq = 1148,
1162 A4_rcmpneqi = 1149,
1163 A4_round_ri = 1150,
1164 A4_round_ri_sat = 1151,
1165 A4_round_rr = 1152,
1166 A4_round_rr_sat = 1153,
1167 A4_subp_c = 1154,
1168 A4_tfrcpp = 1155,
1169 A4_tfrpcp = 1156,
1170 A4_tlbmatch = 1157,
1171 A4_vcmpbeq_any = 1158,
1172 A4_vcmpbeqi = 1159,
1173 A4_vcmpbgt = 1160,
1174 A4_vcmpbgti = 1161,
1175 A4_vcmpbgtui = 1162,
1176 A4_vcmpheqi = 1163,
1177 A4_vcmphgti = 1164,
1178 A4_vcmphgtui = 1165,
1179 A4_vcmpweqi = 1166,
1180 A4_vcmpwgti = 1167,
1181 A4_vcmpwgtui = 1168,
1182 A4_vrmaxh = 1169,
1183 A4_vrmaxuh = 1170,
1184 A4_vrmaxuw = 1171,
1185 A4_vrmaxw = 1172,
1186 A4_vrminh = 1173,
1187 A4_vrminuh = 1174,
1188 A4_vrminuw = 1175,
1189 A4_vrminw = 1176,
1190 A5_ACS = 1177,
1191 A5_vaddhubs = 1178,
1192 A6_vcmpbeq_notany = 1179,
1193 A6_vminub_RdP = 1180,
1194 A7_clip = 1181,
1195 A7_croundd_ri = 1182,
1196 A7_croundd_rr = 1183,
1197 A7_vclip = 1184,
1198 C2_all8 = 1185,
1199 C2_and = 1186,
1200 C2_andn = 1187,
1201 C2_any8 = 1188,
1202 C2_bitsclr = 1189,
1203 C2_bitsclri = 1190,
1204 C2_bitsset = 1191,
1205 C2_ccombinewf = 1192,
1206 C2_ccombinewnewf = 1193,
1207 C2_ccombinewnewt = 1194,
1208 C2_ccombinewt = 1195,
1209 C2_cmoveif = 1196,
1210 C2_cmoveit = 1197,
1211 C2_cmovenewif = 1198,
1212 C2_cmovenewit = 1199,
1213 C2_cmpeq = 1200,
1214 C2_cmpeqi = 1201,
1215 C2_cmpeqp = 1202,
1216 C2_cmpgt = 1203,
1217 C2_cmpgti = 1204,
1218 C2_cmpgtp = 1205,
1219 C2_cmpgtu = 1206,
1220 C2_cmpgtui = 1207,
1221 C2_cmpgtup = 1208,
1222 C2_mask = 1209,
1223 C2_mux = 1210,
1224 C2_muxii = 1211,
1225 C2_muxir = 1212,
1226 C2_muxri = 1213,
1227 C2_not = 1214,
1228 C2_or = 1215,
1229 C2_orn = 1216,
1230 C2_tfrpr = 1217,
1231 C2_tfrrp = 1218,
1232 C2_vitpack = 1219,
1233 C2_vmux = 1220,
1234 C2_xor = 1221,
1235 C4_addipc = 1222,
1236 C4_and_and = 1223,
1237 C4_and_andn = 1224,
1238 C4_and_or = 1225,
1239 C4_and_orn = 1226,
1240 C4_cmplte = 1227,
1241 C4_cmpltei = 1228,
1242 C4_cmplteu = 1229,
1243 C4_cmplteui = 1230,
1244 C4_cmpneq = 1231,
1245 C4_cmpneqi = 1232,
1246 C4_fastcorner9 = 1233,
1247 C4_fastcorner9_not = 1234,
1248 C4_nbitsclr = 1235,
1249 C4_nbitsclri = 1236,
1250 C4_nbitsset = 1237,
1251 C4_or_and = 1238,
1252 C4_or_andn = 1239,
1253 C4_or_or = 1240,
1254 C4_or_orn = 1241,
1255 CALLProfile = 1242,
1256 CONST32 = 1243,
1257 CONST64 = 1244,
1258 DuplexIClass0 = 1245,
1259 DuplexIClass1 = 1246,
1260 DuplexIClass2 = 1247,
1261 DuplexIClass3 = 1248,
1262 DuplexIClass4 = 1249,
1263 DuplexIClass5 = 1250,
1264 DuplexIClass6 = 1251,
1265 DuplexIClass7 = 1252,
1266 DuplexIClass8 = 1253,
1267 DuplexIClass9 = 1254,
1268 DuplexIClassA = 1255,
1269 DuplexIClassB = 1256,
1270 DuplexIClassC = 1257,
1271 DuplexIClassD = 1258,
1272 DuplexIClassE = 1259,
1273 DuplexIClassF = 1260,
1274 EH_RETURN_JMPR = 1261,
1275 F2_conv_d2df = 1262,
1276 F2_conv_d2sf = 1263,
1277 F2_conv_df2d = 1264,
1278 F2_conv_df2d_chop = 1265,
1279 F2_conv_df2sf = 1266,
1280 F2_conv_df2ud = 1267,
1281 F2_conv_df2ud_chop = 1268,
1282 F2_conv_df2uw = 1269,
1283 F2_conv_df2uw_chop = 1270,
1284 F2_conv_df2w = 1271,
1285 F2_conv_df2w_chop = 1272,
1286 F2_conv_sf2d = 1273,
1287 F2_conv_sf2d_chop = 1274,
1288 F2_conv_sf2df = 1275,
1289 F2_conv_sf2ud = 1276,
1290 F2_conv_sf2ud_chop = 1277,
1291 F2_conv_sf2uw = 1278,
1292 F2_conv_sf2uw_chop = 1279,
1293 F2_conv_sf2w = 1280,
1294 F2_conv_sf2w_chop = 1281,
1295 F2_conv_ud2df = 1282,
1296 F2_conv_ud2sf = 1283,
1297 F2_conv_uw2df = 1284,
1298 F2_conv_uw2sf = 1285,
1299 F2_conv_w2df = 1286,
1300 F2_conv_w2sf = 1287,
1301 F2_dfadd = 1288,
1302 F2_dfclass = 1289,
1303 F2_dfcmpeq = 1290,
1304 F2_dfcmpge = 1291,
1305 F2_dfcmpgt = 1292,
1306 F2_dfcmpuo = 1293,
1307 F2_dfimm_n = 1294,
1308 F2_dfimm_p = 1295,
1309 F2_dfmax = 1296,
1310 F2_dfmin = 1297,
1311 F2_dfmpyfix = 1298,
1312 F2_dfmpyhh = 1299,
1313 F2_dfmpylh = 1300,
1314 F2_dfmpyll = 1301,
1315 F2_dfsub = 1302,
1316 F2_sfadd = 1303,
1317 F2_sfclass = 1304,
1318 F2_sfcmpeq = 1305,
1319 F2_sfcmpge = 1306,
1320 F2_sfcmpgt = 1307,
1321 F2_sfcmpuo = 1308,
1322 F2_sffixupd = 1309,
1323 F2_sffixupn = 1310,
1324 F2_sffixupr = 1311,
1325 F2_sffma = 1312,
1326 F2_sffma_lib = 1313,
1327 F2_sffma_sc = 1314,
1328 F2_sffms = 1315,
1329 F2_sffms_lib = 1316,
1330 F2_sfimm_n = 1317,
1331 F2_sfimm_p = 1318,
1332 F2_sfinvsqrta = 1319,
1333 F2_sfmax = 1320,
1334 F2_sfmin = 1321,
1335 F2_sfmpy = 1322,
1336 F2_sfrecipa = 1323,
1337 F2_sfsub = 1324,
1338 G4_tfrgcpp = 1325,
1339 G4_tfrgcrr = 1326,
1340 G4_tfrgpcp = 1327,
1341 G4_tfrgrcr = 1328,
1342 HI = 1329,
1343 J2_call = 1330,
1344 J2_callf = 1331,
1345 J2_callr = 1332,
1346 J2_callrf = 1333,
1347 J2_callrh = 1334,
1348 J2_callrt = 1335,
1349 J2_callt = 1336,
1350 J2_jump = 1337,
1351 J2_jumpf = 1338,
1352 J2_jumpfnew = 1339,
1353 J2_jumpfnewpt = 1340,
1354 J2_jumpfpt = 1341,
1355 J2_jumpr = 1342,
1356 J2_jumprf = 1343,
1357 J2_jumprfnew = 1344,
1358 J2_jumprfnewpt = 1345,
1359 J2_jumprfpt = 1346,
1360 J2_jumprgtez = 1347,
1361 J2_jumprgtezpt = 1348,
1362 J2_jumprh = 1349,
1363 J2_jumprltez = 1350,
1364 J2_jumprltezpt = 1351,
1365 J2_jumprnz = 1352,
1366 J2_jumprnzpt = 1353,
1367 J2_jumprt = 1354,
1368 J2_jumprtnew = 1355,
1369 J2_jumprtnewpt = 1356,
1370 J2_jumprtpt = 1357,
1371 J2_jumprz = 1358,
1372 J2_jumprzpt = 1359,
1373 J2_jumpt = 1360,
1374 J2_jumptnew = 1361,
1375 J2_jumptnewpt = 1362,
1376 J2_jumptpt = 1363,
1377 J2_loop0i = 1364,
1378 J2_loop0iext = 1365,
1379 J2_loop0r = 1366,
1380 J2_loop0rext = 1367,
1381 J2_loop1i = 1368,
1382 J2_loop1iext = 1369,
1383 J2_loop1r = 1370,
1384 J2_loop1rext = 1371,
1385 J2_pause = 1372,
1386 J2_ploop1si = 1373,
1387 J2_ploop1sr = 1374,
1388 J2_ploop2si = 1375,
1389 J2_ploop2sr = 1376,
1390 J2_ploop3si = 1377,
1391 J2_ploop3sr = 1378,
1392 J2_rte = 1379,
1393 J2_trap0 = 1380,
1394 J2_trap1 = 1381,
1395 J2_unpause = 1382,
1396 J4_cmpeq_f_jumpnv_nt = 1383,
1397 J4_cmpeq_f_jumpnv_t = 1384,
1398 J4_cmpeq_fp0_jump_nt = 1385,
1399 J4_cmpeq_fp0_jump_t = 1386,
1400 J4_cmpeq_fp1_jump_nt = 1387,
1401 J4_cmpeq_fp1_jump_t = 1388,
1402 J4_cmpeq_t_jumpnv_nt = 1389,
1403 J4_cmpeq_t_jumpnv_t = 1390,
1404 J4_cmpeq_tp0_jump_nt = 1391,
1405 J4_cmpeq_tp0_jump_t = 1392,
1406 J4_cmpeq_tp1_jump_nt = 1393,
1407 J4_cmpeq_tp1_jump_t = 1394,
1408 J4_cmpeqi_f_jumpnv_nt = 1395,
1409 J4_cmpeqi_f_jumpnv_t = 1396,
1410 J4_cmpeqi_fp0_jump_nt = 1397,
1411 J4_cmpeqi_fp0_jump_t = 1398,
1412 J4_cmpeqi_fp1_jump_nt = 1399,
1413 J4_cmpeqi_fp1_jump_t = 1400,
1414 J4_cmpeqi_t_jumpnv_nt = 1401,
1415 J4_cmpeqi_t_jumpnv_t = 1402,
1416 J4_cmpeqi_tp0_jump_nt = 1403,
1417 J4_cmpeqi_tp0_jump_t = 1404,
1418 J4_cmpeqi_tp1_jump_nt = 1405,
1419 J4_cmpeqi_tp1_jump_t = 1406,
1420 J4_cmpeqn1_f_jumpnv_nt = 1407,
1421 J4_cmpeqn1_f_jumpnv_t = 1408,
1422 J4_cmpeqn1_fp0_jump_nt = 1409,
1423 J4_cmpeqn1_fp0_jump_t = 1410,
1424 J4_cmpeqn1_fp1_jump_nt = 1411,
1425 J4_cmpeqn1_fp1_jump_t = 1412,
1426 J4_cmpeqn1_t_jumpnv_nt = 1413,
1427 J4_cmpeqn1_t_jumpnv_t = 1414,
1428 J4_cmpeqn1_tp0_jump_nt = 1415,
1429 J4_cmpeqn1_tp0_jump_t = 1416,
1430 J4_cmpeqn1_tp1_jump_nt = 1417,
1431 J4_cmpeqn1_tp1_jump_t = 1418,
1432 J4_cmpgt_f_jumpnv_nt = 1419,
1433 J4_cmpgt_f_jumpnv_t = 1420,
1434 J4_cmpgt_fp0_jump_nt = 1421,
1435 J4_cmpgt_fp0_jump_t = 1422,
1436 J4_cmpgt_fp1_jump_nt = 1423,
1437 J4_cmpgt_fp1_jump_t = 1424,
1438 J4_cmpgt_t_jumpnv_nt = 1425,
1439 J4_cmpgt_t_jumpnv_t = 1426,
1440 J4_cmpgt_tp0_jump_nt = 1427,
1441 J4_cmpgt_tp0_jump_t = 1428,
1442 J4_cmpgt_tp1_jump_nt = 1429,
1443 J4_cmpgt_tp1_jump_t = 1430,
1444 J4_cmpgti_f_jumpnv_nt = 1431,
1445 J4_cmpgti_f_jumpnv_t = 1432,
1446 J4_cmpgti_fp0_jump_nt = 1433,
1447 J4_cmpgti_fp0_jump_t = 1434,
1448 J4_cmpgti_fp1_jump_nt = 1435,
1449 J4_cmpgti_fp1_jump_t = 1436,
1450 J4_cmpgti_t_jumpnv_nt = 1437,
1451 J4_cmpgti_t_jumpnv_t = 1438,
1452 J4_cmpgti_tp0_jump_nt = 1439,
1453 J4_cmpgti_tp0_jump_t = 1440,
1454 J4_cmpgti_tp1_jump_nt = 1441,
1455 J4_cmpgti_tp1_jump_t = 1442,
1456 J4_cmpgtn1_f_jumpnv_nt = 1443,
1457 J4_cmpgtn1_f_jumpnv_t = 1444,
1458 J4_cmpgtn1_fp0_jump_nt = 1445,
1459 J4_cmpgtn1_fp0_jump_t = 1446,
1460 J4_cmpgtn1_fp1_jump_nt = 1447,
1461 J4_cmpgtn1_fp1_jump_t = 1448,
1462 J4_cmpgtn1_t_jumpnv_nt = 1449,
1463 J4_cmpgtn1_t_jumpnv_t = 1450,
1464 J4_cmpgtn1_tp0_jump_nt = 1451,
1465 J4_cmpgtn1_tp0_jump_t = 1452,
1466 J4_cmpgtn1_tp1_jump_nt = 1453,
1467 J4_cmpgtn1_tp1_jump_t = 1454,
1468 J4_cmpgtu_f_jumpnv_nt = 1455,
1469 J4_cmpgtu_f_jumpnv_t = 1456,
1470 J4_cmpgtu_fp0_jump_nt = 1457,
1471 J4_cmpgtu_fp0_jump_t = 1458,
1472 J4_cmpgtu_fp1_jump_nt = 1459,
1473 J4_cmpgtu_fp1_jump_t = 1460,
1474 J4_cmpgtu_t_jumpnv_nt = 1461,
1475 J4_cmpgtu_t_jumpnv_t = 1462,
1476 J4_cmpgtu_tp0_jump_nt = 1463,
1477 J4_cmpgtu_tp0_jump_t = 1464,
1478 J4_cmpgtu_tp1_jump_nt = 1465,
1479 J4_cmpgtu_tp1_jump_t = 1466,
1480 J4_cmpgtui_f_jumpnv_nt = 1467,
1481 J4_cmpgtui_f_jumpnv_t = 1468,
1482 J4_cmpgtui_fp0_jump_nt = 1469,
1483 J4_cmpgtui_fp0_jump_t = 1470,
1484 J4_cmpgtui_fp1_jump_nt = 1471,
1485 J4_cmpgtui_fp1_jump_t = 1472,
1486 J4_cmpgtui_t_jumpnv_nt = 1473,
1487 J4_cmpgtui_t_jumpnv_t = 1474,
1488 J4_cmpgtui_tp0_jump_nt = 1475,
1489 J4_cmpgtui_tp0_jump_t = 1476,
1490 J4_cmpgtui_tp1_jump_nt = 1477,
1491 J4_cmpgtui_tp1_jump_t = 1478,
1492 J4_cmplt_f_jumpnv_nt = 1479,
1493 J4_cmplt_f_jumpnv_t = 1480,
1494 J4_cmplt_t_jumpnv_nt = 1481,
1495 J4_cmplt_t_jumpnv_t = 1482,
1496 J4_cmpltu_f_jumpnv_nt = 1483,
1497 J4_cmpltu_f_jumpnv_t = 1484,
1498 J4_cmpltu_t_jumpnv_nt = 1485,
1499 J4_cmpltu_t_jumpnv_t = 1486,
1500 J4_hintjumpr = 1487,
1501 J4_jumpseti = 1488,
1502 J4_jumpsetr = 1489,
1503 J4_tstbit0_f_jumpnv_nt = 1490,
1504 J4_tstbit0_f_jumpnv_t = 1491,
1505 J4_tstbit0_fp0_jump_nt = 1492,
1506 J4_tstbit0_fp0_jump_t = 1493,
1507 J4_tstbit0_fp1_jump_nt = 1494,
1508 J4_tstbit0_fp1_jump_t = 1495,
1509 J4_tstbit0_t_jumpnv_nt = 1496,
1510 J4_tstbit0_t_jumpnv_t = 1497,
1511 J4_tstbit0_tp0_jump_nt = 1498,
1512 J4_tstbit0_tp0_jump_t = 1499,
1513 J4_tstbit0_tp1_jump_nt = 1500,
1514 J4_tstbit0_tp1_jump_t = 1501,
1515 L2_deallocframe = 1502,
1516 L2_loadalignb_io = 1503,
1517 L2_loadalignb_pbr = 1504,
1518 L2_loadalignb_pci = 1505,
1519 L2_loadalignb_pcr = 1506,
1520 L2_loadalignb_pi = 1507,
1521 L2_loadalignb_pr = 1508,
1522 L2_loadalignh_io = 1509,
1523 L2_loadalignh_pbr = 1510,
1524 L2_loadalignh_pci = 1511,
1525 L2_loadalignh_pcr = 1512,
1526 L2_loadalignh_pi = 1513,
1527 L2_loadalignh_pr = 1514,
1528 L2_loadbsw2_io = 1515,
1529 L2_loadbsw2_pbr = 1516,
1530 L2_loadbsw2_pci = 1517,
1531 L2_loadbsw2_pcr = 1518,
1532 L2_loadbsw2_pi = 1519,
1533 L2_loadbsw2_pr = 1520,
1534 L2_loadbsw4_io = 1521,
1535 L2_loadbsw4_pbr = 1522,
1536 L2_loadbsw4_pci = 1523,
1537 L2_loadbsw4_pcr = 1524,
1538 L2_loadbsw4_pi = 1525,
1539 L2_loadbsw4_pr = 1526,
1540 L2_loadbzw2_io = 1527,
1541 L2_loadbzw2_pbr = 1528,
1542 L2_loadbzw2_pci = 1529,
1543 L2_loadbzw2_pcr = 1530,
1544 L2_loadbzw2_pi = 1531,
1545 L2_loadbzw2_pr = 1532,
1546 L2_loadbzw4_io = 1533,
1547 L2_loadbzw4_pbr = 1534,
1548 L2_loadbzw4_pci = 1535,
1549 L2_loadbzw4_pcr = 1536,
1550 L2_loadbzw4_pi = 1537,
1551 L2_loadbzw4_pr = 1538,
1552 L2_loadrb_io = 1539,
1553 L2_loadrb_pbr = 1540,
1554 L2_loadrb_pci = 1541,
1555 L2_loadrb_pcr = 1542,
1556 L2_loadrb_pi = 1543,
1557 L2_loadrb_pr = 1544,
1558 L2_loadrbgp = 1545,
1559 L2_loadrd_io = 1546,
1560 L2_loadrd_pbr = 1547,
1561 L2_loadrd_pci = 1548,
1562 L2_loadrd_pcr = 1549,
1563 L2_loadrd_pi = 1550,
1564 L2_loadrd_pr = 1551,
1565 L2_loadrdgp = 1552,
1566 L2_loadrh_io = 1553,
1567 L2_loadrh_pbr = 1554,
1568 L2_loadrh_pci = 1555,
1569 L2_loadrh_pcr = 1556,
1570 L2_loadrh_pi = 1557,
1571 L2_loadrh_pr = 1558,
1572 L2_loadrhgp = 1559,
1573 L2_loadri_io = 1560,
1574 L2_loadri_pbr = 1561,
1575 L2_loadri_pci = 1562,
1576 L2_loadri_pcr = 1563,
1577 L2_loadri_pi = 1564,
1578 L2_loadri_pr = 1565,
1579 L2_loadrigp = 1566,
1580 L2_loadrub_io = 1567,
1581 L2_loadrub_pbr = 1568,
1582 L2_loadrub_pci = 1569,
1583 L2_loadrub_pcr = 1570,
1584 L2_loadrub_pi = 1571,
1585 L2_loadrub_pr = 1572,
1586 L2_loadrubgp = 1573,
1587 L2_loadruh_io = 1574,
1588 L2_loadruh_pbr = 1575,
1589 L2_loadruh_pci = 1576,
1590 L2_loadruh_pcr = 1577,
1591 L2_loadruh_pi = 1578,
1592 L2_loadruh_pr = 1579,
1593 L2_loadruhgp = 1580,
1594 L2_loadw_aq = 1581,
1595 L2_loadw_locked = 1582,
1596 L2_ploadrbf_io = 1583,
1597 L2_ploadrbf_pi = 1584,
1598 L2_ploadrbfnew_io = 1585,
1599 L2_ploadrbfnew_pi = 1586,
1600 L2_ploadrbt_io = 1587,
1601 L2_ploadrbt_pi = 1588,
1602 L2_ploadrbtnew_io = 1589,
1603 L2_ploadrbtnew_pi = 1590,
1604 L2_ploadrdf_io = 1591,
1605 L2_ploadrdf_pi = 1592,
1606 L2_ploadrdfnew_io = 1593,
1607 L2_ploadrdfnew_pi = 1594,
1608 L2_ploadrdt_io = 1595,
1609 L2_ploadrdt_pi = 1596,
1610 L2_ploadrdtnew_io = 1597,
1611 L2_ploadrdtnew_pi = 1598,
1612 L2_ploadrhf_io = 1599,
1613 L2_ploadrhf_pi = 1600,
1614 L2_ploadrhfnew_io = 1601,
1615 L2_ploadrhfnew_pi = 1602,
1616 L2_ploadrht_io = 1603,
1617 L2_ploadrht_pi = 1604,
1618 L2_ploadrhtnew_io = 1605,
1619 L2_ploadrhtnew_pi = 1606,
1620 L2_ploadrif_io = 1607,
1621 L2_ploadrif_pi = 1608,
1622 L2_ploadrifnew_io = 1609,
1623 L2_ploadrifnew_pi = 1610,
1624 L2_ploadrit_io = 1611,
1625 L2_ploadrit_pi = 1612,
1626 L2_ploadritnew_io = 1613,
1627 L2_ploadritnew_pi = 1614,
1628 L2_ploadrubf_io = 1615,
1629 L2_ploadrubf_pi = 1616,
1630 L2_ploadrubfnew_io = 1617,
1631 L2_ploadrubfnew_pi = 1618,
1632 L2_ploadrubt_io = 1619,
1633 L2_ploadrubt_pi = 1620,
1634 L2_ploadrubtnew_io = 1621,
1635 L2_ploadrubtnew_pi = 1622,
1636 L2_ploadruhf_io = 1623,
1637 L2_ploadruhf_pi = 1624,
1638 L2_ploadruhfnew_io = 1625,
1639 L2_ploadruhfnew_pi = 1626,
1640 L2_ploadruht_io = 1627,
1641 L2_ploadruht_pi = 1628,
1642 L2_ploadruhtnew_io = 1629,
1643 L2_ploadruhtnew_pi = 1630,
1644 L4_add_memopb_io = 1631,
1645 L4_add_memoph_io = 1632,
1646 L4_add_memopw_io = 1633,
1647 L4_and_memopb_io = 1634,
1648 L4_and_memoph_io = 1635,
1649 L4_and_memopw_io = 1636,
1650 L4_iadd_memopb_io = 1637,
1651 L4_iadd_memoph_io = 1638,
1652 L4_iadd_memopw_io = 1639,
1653 L4_iand_memopb_io = 1640,
1654 L4_iand_memoph_io = 1641,
1655 L4_iand_memopw_io = 1642,
1656 L4_ior_memopb_io = 1643,
1657 L4_ior_memoph_io = 1644,
1658 L4_ior_memopw_io = 1645,
1659 L4_isub_memopb_io = 1646,
1660 L4_isub_memoph_io = 1647,
1661 L4_isub_memopw_io = 1648,
1662 L4_loadalignb_ap = 1649,
1663 L4_loadalignb_ur = 1650,
1664 L4_loadalignh_ap = 1651,
1665 L4_loadalignh_ur = 1652,
1666 L4_loadbsw2_ap = 1653,
1667 L4_loadbsw2_ur = 1654,
1668 L4_loadbsw4_ap = 1655,
1669 L4_loadbsw4_ur = 1656,
1670 L4_loadbzw2_ap = 1657,
1671 L4_loadbzw2_ur = 1658,
1672 L4_loadbzw4_ap = 1659,
1673 L4_loadbzw4_ur = 1660,
1674 L4_loadd_aq = 1661,
1675 L4_loadd_locked = 1662,
1676 L4_loadrb_ap = 1663,
1677 L4_loadrb_rr = 1664,
1678 L4_loadrb_ur = 1665,
1679 L4_loadrd_ap = 1666,
1680 L4_loadrd_rr = 1667,
1681 L4_loadrd_ur = 1668,
1682 L4_loadrh_ap = 1669,
1683 L4_loadrh_rr = 1670,
1684 L4_loadrh_ur = 1671,
1685 L4_loadri_ap = 1672,
1686 L4_loadri_rr = 1673,
1687 L4_loadri_ur = 1674,
1688 L4_loadrub_ap = 1675,
1689 L4_loadrub_rr = 1676,
1690 L4_loadrub_ur = 1677,
1691 L4_loadruh_ap = 1678,
1692 L4_loadruh_rr = 1679,
1693 L4_loadruh_ur = 1680,
1694 L4_loadw_phys = 1681,
1695 L4_or_memopb_io = 1682,
1696 L4_or_memoph_io = 1683,
1697 L4_or_memopw_io = 1684,
1698 L4_ploadrbf_abs = 1685,
1699 L4_ploadrbf_rr = 1686,
1700 L4_ploadrbfnew_abs = 1687,
1701 L4_ploadrbfnew_rr = 1688,
1702 L4_ploadrbt_abs = 1689,
1703 L4_ploadrbt_rr = 1690,
1704 L4_ploadrbtnew_abs = 1691,
1705 L4_ploadrbtnew_rr = 1692,
1706 L4_ploadrdf_abs = 1693,
1707 L4_ploadrdf_rr = 1694,
1708 L4_ploadrdfnew_abs = 1695,
1709 L4_ploadrdfnew_rr = 1696,
1710 L4_ploadrdt_abs = 1697,
1711 L4_ploadrdt_rr = 1698,
1712 L4_ploadrdtnew_abs = 1699,
1713 L4_ploadrdtnew_rr = 1700,
1714 L4_ploadrhf_abs = 1701,
1715 L4_ploadrhf_rr = 1702,
1716 L4_ploadrhfnew_abs = 1703,
1717 L4_ploadrhfnew_rr = 1704,
1718 L4_ploadrht_abs = 1705,
1719 L4_ploadrht_rr = 1706,
1720 L4_ploadrhtnew_abs = 1707,
1721 L4_ploadrhtnew_rr = 1708,
1722 L4_ploadrif_abs = 1709,
1723 L4_ploadrif_rr = 1710,
1724 L4_ploadrifnew_abs = 1711,
1725 L4_ploadrifnew_rr = 1712,
1726 L4_ploadrit_abs = 1713,
1727 L4_ploadrit_rr = 1714,
1728 L4_ploadritnew_abs = 1715,
1729 L4_ploadritnew_rr = 1716,
1730 L4_ploadrubf_abs = 1717,
1731 L4_ploadrubf_rr = 1718,
1732 L4_ploadrubfnew_abs = 1719,
1733 L4_ploadrubfnew_rr = 1720,
1734 L4_ploadrubt_abs = 1721,
1735 L4_ploadrubt_rr = 1722,
1736 L4_ploadrubtnew_abs = 1723,
1737 L4_ploadrubtnew_rr = 1724,
1738 L4_ploadruhf_abs = 1725,
1739 L4_ploadruhf_rr = 1726,
1740 L4_ploadruhfnew_abs = 1727,
1741 L4_ploadruhfnew_rr = 1728,
1742 L4_ploadruht_abs = 1729,
1743 L4_ploadruht_rr = 1730,
1744 L4_ploadruhtnew_abs = 1731,
1745 L4_ploadruhtnew_rr = 1732,
1746 L4_return = 1733,
1747 L4_return_f = 1734,
1748 L4_return_fnew_pnt = 1735,
1749 L4_return_fnew_pt = 1736,
1750 L4_return_t = 1737,
1751 L4_return_tnew_pnt = 1738,
1752 L4_return_tnew_pt = 1739,
1753 L4_sub_memopb_io = 1740,
1754 L4_sub_memoph_io = 1741,
1755 L4_sub_memopw_io = 1742,
1756 L6_memcpy = 1743,
1757 LO = 1744,
1758 M2_acci = 1745,
1759 M2_accii = 1746,
1760 M2_cmaci_s0 = 1747,
1761 M2_cmacr_s0 = 1748,
1762 M2_cmacs_s0 = 1749,
1763 M2_cmacs_s1 = 1750,
1764 M2_cmacsc_s0 = 1751,
1765 M2_cmacsc_s1 = 1752,
1766 M2_cmpyi_s0 = 1753,
1767 M2_cmpyr_s0 = 1754,
1768 M2_cmpyrs_s0 = 1755,
1769 M2_cmpyrs_s1 = 1756,
1770 M2_cmpyrsc_s0 = 1757,
1771 M2_cmpyrsc_s1 = 1758,
1772 M2_cmpys_s0 = 1759,
1773 M2_cmpys_s1 = 1760,
1774 M2_cmpysc_s0 = 1761,
1775 M2_cmpysc_s1 = 1762,
1776 M2_cnacs_s0 = 1763,
1777 M2_cnacs_s1 = 1764,
1778 M2_cnacsc_s0 = 1765,
1779 M2_cnacsc_s1 = 1766,
1780 M2_dpmpyss_acc_s0 = 1767,
1781 M2_dpmpyss_nac_s0 = 1768,
1782 M2_dpmpyss_rnd_s0 = 1769,
1783 M2_dpmpyss_s0 = 1770,
1784 M2_dpmpyuu_acc_s0 = 1771,
1785 M2_dpmpyuu_nac_s0 = 1772,
1786 M2_dpmpyuu_s0 = 1773,
1787 M2_hmmpyh_rs1 = 1774,
1788 M2_hmmpyh_s1 = 1775,
1789 M2_hmmpyl_rs1 = 1776,
1790 M2_hmmpyl_s1 = 1777,
1791 M2_maci = 1778,
1792 M2_macsin = 1779,
1793 M2_macsip = 1780,
1794 M2_mmachs_rs0 = 1781,
1795 M2_mmachs_rs1 = 1782,
1796 M2_mmachs_s0 = 1783,
1797 M2_mmachs_s1 = 1784,
1798 M2_mmacls_rs0 = 1785,
1799 M2_mmacls_rs1 = 1786,
1800 M2_mmacls_s0 = 1787,
1801 M2_mmacls_s1 = 1788,
1802 M2_mmacuhs_rs0 = 1789,
1803 M2_mmacuhs_rs1 = 1790,
1804 M2_mmacuhs_s0 = 1791,
1805 M2_mmacuhs_s1 = 1792,
1806 M2_mmaculs_rs0 = 1793,
1807 M2_mmaculs_rs1 = 1794,
1808 M2_mmaculs_s0 = 1795,
1809 M2_mmaculs_s1 = 1796,
1810 M2_mmpyh_rs0 = 1797,
1811 M2_mmpyh_rs1 = 1798,
1812 M2_mmpyh_s0 = 1799,
1813 M2_mmpyh_s1 = 1800,
1814 M2_mmpyl_rs0 = 1801,
1815 M2_mmpyl_rs1 = 1802,
1816 M2_mmpyl_s0 = 1803,
1817 M2_mmpyl_s1 = 1804,
1818 M2_mmpyuh_rs0 = 1805,
1819 M2_mmpyuh_rs1 = 1806,
1820 M2_mmpyuh_s0 = 1807,
1821 M2_mmpyuh_s1 = 1808,
1822 M2_mmpyul_rs0 = 1809,
1823 M2_mmpyul_rs1 = 1810,
1824 M2_mmpyul_s0 = 1811,
1825 M2_mmpyul_s1 = 1812,
1826 M2_mnaci = 1813,
1827 M2_mpy_acc_hh_s0 = 1814,
1828 M2_mpy_acc_hh_s1 = 1815,
1829 M2_mpy_acc_hl_s0 = 1816,
1830 M2_mpy_acc_hl_s1 = 1817,
1831 M2_mpy_acc_lh_s0 = 1818,
1832 M2_mpy_acc_lh_s1 = 1819,
1833 M2_mpy_acc_ll_s0 = 1820,
1834 M2_mpy_acc_ll_s1 = 1821,
1835 M2_mpy_acc_sat_hh_s0 = 1822,
1836 M2_mpy_acc_sat_hh_s1 = 1823,
1837 M2_mpy_acc_sat_hl_s0 = 1824,
1838 M2_mpy_acc_sat_hl_s1 = 1825,
1839 M2_mpy_acc_sat_lh_s0 = 1826,
1840 M2_mpy_acc_sat_lh_s1 = 1827,
1841 M2_mpy_acc_sat_ll_s0 = 1828,
1842 M2_mpy_acc_sat_ll_s1 = 1829,
1843 M2_mpy_hh_s0 = 1830,
1844 M2_mpy_hh_s1 = 1831,
1845 M2_mpy_hl_s0 = 1832,
1846 M2_mpy_hl_s1 = 1833,
1847 M2_mpy_lh_s0 = 1834,
1848 M2_mpy_lh_s1 = 1835,
1849 M2_mpy_ll_s0 = 1836,
1850 M2_mpy_ll_s1 = 1837,
1851 M2_mpy_nac_hh_s0 = 1838,
1852 M2_mpy_nac_hh_s1 = 1839,
1853 M2_mpy_nac_hl_s0 = 1840,
1854 M2_mpy_nac_hl_s1 = 1841,
1855 M2_mpy_nac_lh_s0 = 1842,
1856 M2_mpy_nac_lh_s1 = 1843,
1857 M2_mpy_nac_ll_s0 = 1844,
1858 M2_mpy_nac_ll_s1 = 1845,
1859 M2_mpy_nac_sat_hh_s0 = 1846,
1860 M2_mpy_nac_sat_hh_s1 = 1847,
1861 M2_mpy_nac_sat_hl_s0 = 1848,
1862 M2_mpy_nac_sat_hl_s1 = 1849,
1863 M2_mpy_nac_sat_lh_s0 = 1850,
1864 M2_mpy_nac_sat_lh_s1 = 1851,
1865 M2_mpy_nac_sat_ll_s0 = 1852,
1866 M2_mpy_nac_sat_ll_s1 = 1853,
1867 M2_mpy_rnd_hh_s0 = 1854,
1868 M2_mpy_rnd_hh_s1 = 1855,
1869 M2_mpy_rnd_hl_s0 = 1856,
1870 M2_mpy_rnd_hl_s1 = 1857,
1871 M2_mpy_rnd_lh_s0 = 1858,
1872 M2_mpy_rnd_lh_s1 = 1859,
1873 M2_mpy_rnd_ll_s0 = 1860,
1874 M2_mpy_rnd_ll_s1 = 1861,
1875 M2_mpy_sat_hh_s0 = 1862,
1876 M2_mpy_sat_hh_s1 = 1863,
1877 M2_mpy_sat_hl_s0 = 1864,
1878 M2_mpy_sat_hl_s1 = 1865,
1879 M2_mpy_sat_lh_s0 = 1866,
1880 M2_mpy_sat_lh_s1 = 1867,
1881 M2_mpy_sat_ll_s0 = 1868,
1882 M2_mpy_sat_ll_s1 = 1869,
1883 M2_mpy_sat_rnd_hh_s0 = 1870,
1884 M2_mpy_sat_rnd_hh_s1 = 1871,
1885 M2_mpy_sat_rnd_hl_s0 = 1872,
1886 M2_mpy_sat_rnd_hl_s1 = 1873,
1887 M2_mpy_sat_rnd_lh_s0 = 1874,
1888 M2_mpy_sat_rnd_lh_s1 = 1875,
1889 M2_mpy_sat_rnd_ll_s0 = 1876,
1890 M2_mpy_sat_rnd_ll_s1 = 1877,
1891 M2_mpy_up = 1878,
1892 M2_mpy_up_s1 = 1879,
1893 M2_mpy_up_s1_sat = 1880,
1894 M2_mpyd_acc_hh_s0 = 1881,
1895 M2_mpyd_acc_hh_s1 = 1882,
1896 M2_mpyd_acc_hl_s0 = 1883,
1897 M2_mpyd_acc_hl_s1 = 1884,
1898 M2_mpyd_acc_lh_s0 = 1885,
1899 M2_mpyd_acc_lh_s1 = 1886,
1900 M2_mpyd_acc_ll_s0 = 1887,
1901 M2_mpyd_acc_ll_s1 = 1888,
1902 M2_mpyd_hh_s0 = 1889,
1903 M2_mpyd_hh_s1 = 1890,
1904 M2_mpyd_hl_s0 = 1891,
1905 M2_mpyd_hl_s1 = 1892,
1906 M2_mpyd_lh_s0 = 1893,
1907 M2_mpyd_lh_s1 = 1894,
1908 M2_mpyd_ll_s0 = 1895,
1909 M2_mpyd_ll_s1 = 1896,
1910 M2_mpyd_nac_hh_s0 = 1897,
1911 M2_mpyd_nac_hh_s1 = 1898,
1912 M2_mpyd_nac_hl_s0 = 1899,
1913 M2_mpyd_nac_hl_s1 = 1900,
1914 M2_mpyd_nac_lh_s0 = 1901,
1915 M2_mpyd_nac_lh_s1 = 1902,
1916 M2_mpyd_nac_ll_s0 = 1903,
1917 M2_mpyd_nac_ll_s1 = 1904,
1918 M2_mpyd_rnd_hh_s0 = 1905,
1919 M2_mpyd_rnd_hh_s1 = 1906,
1920 M2_mpyd_rnd_hl_s0 = 1907,
1921 M2_mpyd_rnd_hl_s1 = 1908,
1922 M2_mpyd_rnd_lh_s0 = 1909,
1923 M2_mpyd_rnd_lh_s1 = 1910,
1924 M2_mpyd_rnd_ll_s0 = 1911,
1925 M2_mpyd_rnd_ll_s1 = 1912,
1926 M2_mpyi = 1913,
1927 M2_mpysin = 1914,
1928 M2_mpysip = 1915,
1929 M2_mpysu_up = 1916,
1930 M2_mpyu_acc_hh_s0 = 1917,
1931 M2_mpyu_acc_hh_s1 = 1918,
1932 M2_mpyu_acc_hl_s0 = 1919,
1933 M2_mpyu_acc_hl_s1 = 1920,
1934 M2_mpyu_acc_lh_s0 = 1921,
1935 M2_mpyu_acc_lh_s1 = 1922,
1936 M2_mpyu_acc_ll_s0 = 1923,
1937 M2_mpyu_acc_ll_s1 = 1924,
1938 M2_mpyu_hh_s0 = 1925,
1939 M2_mpyu_hh_s1 = 1926,
1940 M2_mpyu_hl_s0 = 1927,
1941 M2_mpyu_hl_s1 = 1928,
1942 M2_mpyu_lh_s0 = 1929,
1943 M2_mpyu_lh_s1 = 1930,
1944 M2_mpyu_ll_s0 = 1931,
1945 M2_mpyu_ll_s1 = 1932,
1946 M2_mpyu_nac_hh_s0 = 1933,
1947 M2_mpyu_nac_hh_s1 = 1934,
1948 M2_mpyu_nac_hl_s0 = 1935,
1949 M2_mpyu_nac_hl_s1 = 1936,
1950 M2_mpyu_nac_lh_s0 = 1937,
1951 M2_mpyu_nac_lh_s1 = 1938,
1952 M2_mpyu_nac_ll_s0 = 1939,
1953 M2_mpyu_nac_ll_s1 = 1940,
1954 M2_mpyu_up = 1941,
1955 M2_mpyud_acc_hh_s0 = 1942,
1956 M2_mpyud_acc_hh_s1 = 1943,
1957 M2_mpyud_acc_hl_s0 = 1944,
1958 M2_mpyud_acc_hl_s1 = 1945,
1959 M2_mpyud_acc_lh_s0 = 1946,
1960 M2_mpyud_acc_lh_s1 = 1947,
1961 M2_mpyud_acc_ll_s0 = 1948,
1962 M2_mpyud_acc_ll_s1 = 1949,
1963 M2_mpyud_hh_s0 = 1950,
1964 M2_mpyud_hh_s1 = 1951,
1965 M2_mpyud_hl_s0 = 1952,
1966 M2_mpyud_hl_s1 = 1953,
1967 M2_mpyud_lh_s0 = 1954,
1968 M2_mpyud_lh_s1 = 1955,
1969 M2_mpyud_ll_s0 = 1956,
1970 M2_mpyud_ll_s1 = 1957,
1971 M2_mpyud_nac_hh_s0 = 1958,
1972 M2_mpyud_nac_hh_s1 = 1959,
1973 M2_mpyud_nac_hl_s0 = 1960,
1974 M2_mpyud_nac_hl_s1 = 1961,
1975 M2_mpyud_nac_lh_s0 = 1962,
1976 M2_mpyud_nac_lh_s1 = 1963,
1977 M2_mpyud_nac_ll_s0 = 1964,
1978 M2_mpyud_nac_ll_s1 = 1965,
1979 M2_nacci = 1966,
1980 M2_naccii = 1967,
1981 M2_subacc = 1968,
1982 M2_vabsdiffh = 1969,
1983 M2_vabsdiffw = 1970,
1984 M2_vcmac_s0_sat_i = 1971,
1985 M2_vcmac_s0_sat_r = 1972,
1986 M2_vcmpy_s0_sat_i = 1973,
1987 M2_vcmpy_s0_sat_r = 1974,
1988 M2_vcmpy_s1_sat_i = 1975,
1989 M2_vcmpy_s1_sat_r = 1976,
1990 M2_vdmacs_s0 = 1977,
1991 M2_vdmacs_s1 = 1978,
1992 M2_vdmpyrs_s0 = 1979,
1993 M2_vdmpyrs_s1 = 1980,
1994 M2_vdmpys_s0 = 1981,
1995 M2_vdmpys_s1 = 1982,
1996 M2_vmac2 = 1983,
1997 M2_vmac2es = 1984,
1998 M2_vmac2es_s0 = 1985,
1999 M2_vmac2es_s1 = 1986,
2000 M2_vmac2s_s0 = 1987,
2001 M2_vmac2s_s1 = 1988,
2002 M2_vmac2su_s0 = 1989,
2003 M2_vmac2su_s1 = 1990,
2004 M2_vmpy2es_s0 = 1991,
2005 M2_vmpy2es_s1 = 1992,
2006 M2_vmpy2s_s0 = 1993,
2007 M2_vmpy2s_s0pack = 1994,
2008 M2_vmpy2s_s1 = 1995,
2009 M2_vmpy2s_s1pack = 1996,
2010 M2_vmpy2su_s0 = 1997,
2011 M2_vmpy2su_s1 = 1998,
2012 M2_vraddh = 1999,
2013 M2_vradduh = 2000,
2014 M2_vrcmaci_s0 = 2001,
2015 M2_vrcmaci_s0c = 2002,
2016 M2_vrcmacr_s0 = 2003,
2017 M2_vrcmacr_s0c = 2004,
2018 M2_vrcmpyi_s0 = 2005,
2019 M2_vrcmpyi_s0c = 2006,
2020 M2_vrcmpyr_s0 = 2007,
2021 M2_vrcmpyr_s0c = 2008,
2022 M2_vrcmpys_acc_s1_h = 2009,
2023 M2_vrcmpys_acc_s1_l = 2010,
2024 M2_vrcmpys_s1_h = 2011,
2025 M2_vrcmpys_s1_l = 2012,
2026 M2_vrcmpys_s1rp_h = 2013,
2027 M2_vrcmpys_s1rp_l = 2014,
2028 M2_vrmac_s0 = 2015,
2029 M2_vrmpy_s0 = 2016,
2030 M2_xor_xacc = 2017,
2031 M4_and_and = 2018,
2032 M4_and_andn = 2019,
2033 M4_and_or = 2020,
2034 M4_and_xor = 2021,
2035 M4_cmpyi_wh = 2022,
2036 M4_cmpyi_whc = 2023,
2037 M4_cmpyr_wh = 2024,
2038 M4_cmpyr_whc = 2025,
2039 M4_mac_up_s1_sat = 2026,
2040 M4_mpyri_addi = 2027,
2041 M4_mpyri_addr = 2028,
2042 M4_mpyri_addr_u2 = 2029,
2043 M4_mpyrr_addi = 2030,
2044 M4_mpyrr_addr = 2031,
2045 M4_nac_up_s1_sat = 2032,
2046 M4_or_and = 2033,
2047 M4_or_andn = 2034,
2048 M4_or_or = 2035,
2049 M4_or_xor = 2036,
2050 M4_pmpyw = 2037,
2051 M4_pmpyw_acc = 2038,
2052 M4_vpmpyh = 2039,
2053 M4_vpmpyh_acc = 2040,
2054 M4_vrmpyeh_acc_s0 = 2041,
2055 M4_vrmpyeh_acc_s1 = 2042,
2056 M4_vrmpyeh_s0 = 2043,
2057 M4_vrmpyeh_s1 = 2044,
2058 M4_vrmpyoh_acc_s0 = 2045,
2059 M4_vrmpyoh_acc_s1 = 2046,
2060 M4_vrmpyoh_s0 = 2047,
2061 M4_vrmpyoh_s1 = 2048,
2062 M4_xor_and = 2049,
2063 M4_xor_andn = 2050,
2064 M4_xor_or = 2051,
2065 M4_xor_xacc = 2052,
2066 M5_vdmacbsu = 2053,
2067 M5_vdmpybsu = 2054,
2068 M5_vmacbsu = 2055,
2069 M5_vmacbuu = 2056,
2070 M5_vmpybsu = 2057,
2071 M5_vmpybuu = 2058,
2072 M5_vrmacbsu = 2059,
2073 M5_vrmacbuu = 2060,
2074 M5_vrmpybsu = 2061,
2075 M5_vrmpybuu = 2062,
2076 M6_vabsdiffb = 2063,
2077 M6_vabsdiffub = 2064,
2078 M7_dcmpyiw = 2065,
2079 M7_dcmpyiw_acc = 2066,
2080 M7_dcmpyiwc = 2067,
2081 M7_dcmpyiwc_acc = 2068,
2082 M7_dcmpyrw = 2069,
2083 M7_dcmpyrw_acc = 2070,
2084 M7_dcmpyrwc = 2071,
2085 M7_dcmpyrwc_acc = 2072,
2086 M7_wcmpyiw = 2073,
2087 M7_wcmpyiw_rnd = 2074,
2088 M7_wcmpyiwc = 2075,
2089 M7_wcmpyiwc_rnd = 2076,
2090 M7_wcmpyrw = 2077,
2091 M7_wcmpyrw_rnd = 2078,
2092 M7_wcmpyrwc = 2079,
2093 M7_wcmpyrwc_rnd = 2080,
2094 PS_call_stk = 2081,
2095 PS_callr_nr = 2082,
2096 PS_jmpret = 2083,
2097 PS_jmpretf = 2084,
2098 PS_jmpretfnew = 2085,
2099 PS_jmpretfnewpt = 2086,
2100 PS_jmprett = 2087,
2101 PS_jmprettnew = 2088,
2102 PS_jmprettnewpt = 2089,
2103 PS_loadrbabs = 2090,
2104 PS_loadrdabs = 2091,
2105 PS_loadrhabs = 2092,
2106 PS_loadriabs = 2093,
2107 PS_loadrubabs = 2094,
2108 PS_loadruhabs = 2095,
2109 PS_storerbabs = 2096,
2110 PS_storerbnewabs = 2097,
2111 PS_storerdabs = 2098,
2112 PS_storerfabs = 2099,
2113 PS_storerhabs = 2100,
2114 PS_storerhnewabs = 2101,
2115 PS_storeriabs = 2102,
2116 PS_storerinewabs = 2103,
2117 PS_trap1 = 2104,
2118 R6_release_at_vi = 2105,
2119 R6_release_st_vi = 2106,
2120 RESTORE_DEALLOC_BEFORE_TAILCALL_V4 = 2107,
2121 RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT = 2108,
2122 RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT_PIC = 2109,
2123 RESTORE_DEALLOC_BEFORE_TAILCALL_V4_PIC = 2110,
2124 RESTORE_DEALLOC_RET_JMP_V4 = 2111,
2125 RESTORE_DEALLOC_RET_JMP_V4_EXT = 2112,
2126 RESTORE_DEALLOC_RET_JMP_V4_EXT_PIC = 2113,
2127 RESTORE_DEALLOC_RET_JMP_V4_PIC = 2114,
2128 S2_addasl_rrri = 2115,
2129 S2_allocframe = 2116,
2130 S2_asl_i_p = 2117,
2131 S2_asl_i_p_acc = 2118,
2132 S2_asl_i_p_and = 2119,
2133 S2_asl_i_p_nac = 2120,
2134 S2_asl_i_p_or = 2121,
2135 S2_asl_i_p_xacc = 2122,
2136 S2_asl_i_r = 2123,
2137 S2_asl_i_r_acc = 2124,
2138 S2_asl_i_r_and = 2125,
2139 S2_asl_i_r_nac = 2126,
2140 S2_asl_i_r_or = 2127,
2141 S2_asl_i_r_sat = 2128,
2142 S2_asl_i_r_xacc = 2129,
2143 S2_asl_i_vh = 2130,
2144 S2_asl_i_vw = 2131,
2145 S2_asl_r_p = 2132,
2146 S2_asl_r_p_acc = 2133,
2147 S2_asl_r_p_and = 2134,
2148 S2_asl_r_p_nac = 2135,
2149 S2_asl_r_p_or = 2136,
2150 S2_asl_r_p_xor = 2137,
2151 S2_asl_r_r = 2138,
2152 S2_asl_r_r_acc = 2139,
2153 S2_asl_r_r_and = 2140,
2154 S2_asl_r_r_nac = 2141,
2155 S2_asl_r_r_or = 2142,
2156 S2_asl_r_r_sat = 2143,
2157 S2_asl_r_vh = 2144,
2158 S2_asl_r_vw = 2145,
2159 S2_asr_i_p = 2146,
2160 S2_asr_i_p_acc = 2147,
2161 S2_asr_i_p_and = 2148,
2162 S2_asr_i_p_nac = 2149,
2163 S2_asr_i_p_or = 2150,
2164 S2_asr_i_p_rnd = 2151,
2165 S2_asr_i_r = 2152,
2166 S2_asr_i_r_acc = 2153,
2167 S2_asr_i_r_and = 2154,
2168 S2_asr_i_r_nac = 2155,
2169 S2_asr_i_r_or = 2156,
2170 S2_asr_i_r_rnd = 2157,
2171 S2_asr_i_svw_trun = 2158,
2172 S2_asr_i_vh = 2159,
2173 S2_asr_i_vw = 2160,
2174 S2_asr_r_p = 2161,
2175 S2_asr_r_p_acc = 2162,
2176 S2_asr_r_p_and = 2163,
2177 S2_asr_r_p_nac = 2164,
2178 S2_asr_r_p_or = 2165,
2179 S2_asr_r_p_xor = 2166,
2180 S2_asr_r_r = 2167,
2181 S2_asr_r_r_acc = 2168,
2182 S2_asr_r_r_and = 2169,
2183 S2_asr_r_r_nac = 2170,
2184 S2_asr_r_r_or = 2171,
2185 S2_asr_r_r_sat = 2172,
2186 S2_asr_r_svw_trun = 2173,
2187 S2_asr_r_vh = 2174,
2188 S2_asr_r_vw = 2175,
2189 S2_brev = 2176,
2190 S2_brevp = 2177,
2191 S2_cabacdecbin = 2178,
2192 S2_cl0 = 2179,
2193 S2_cl0p = 2180,
2194 S2_cl1 = 2181,
2195 S2_cl1p = 2182,
2196 S2_clb = 2183,
2197 S2_clbnorm = 2184,
2198 S2_clbp = 2185,
2199 S2_clrbit_i = 2186,
2200 S2_clrbit_r = 2187,
2201 S2_ct0 = 2188,
2202 S2_ct0p = 2189,
2203 S2_ct1 = 2190,
2204 S2_ct1p = 2191,
2205 S2_deinterleave = 2192,
2206 S2_extractu = 2193,
2207 S2_extractu_rp = 2194,
2208 S2_extractup = 2195,
2209 S2_extractup_rp = 2196,
2210 S2_insert = 2197,
2211 S2_insert_rp = 2198,
2212 S2_insertp = 2199,
2213 S2_insertp_rp = 2200,
2214 S2_interleave = 2201,
2215 S2_lfsp = 2202,
2216 S2_lsl_r_p = 2203,
2217 S2_lsl_r_p_acc = 2204,
2218 S2_lsl_r_p_and = 2205,
2219 S2_lsl_r_p_nac = 2206,
2220 S2_lsl_r_p_or = 2207,
2221 S2_lsl_r_p_xor = 2208,
2222 S2_lsl_r_r = 2209,
2223 S2_lsl_r_r_acc = 2210,
2224 S2_lsl_r_r_and = 2211,
2225 S2_lsl_r_r_nac = 2212,
2226 S2_lsl_r_r_or = 2213,
2227 S2_lsl_r_vh = 2214,
2228 S2_lsl_r_vw = 2215,
2229 S2_lsr_i_p = 2216,
2230 S2_lsr_i_p_acc = 2217,
2231 S2_lsr_i_p_and = 2218,
2232 S2_lsr_i_p_nac = 2219,
2233 S2_lsr_i_p_or = 2220,
2234 S2_lsr_i_p_xacc = 2221,
2235 S2_lsr_i_r = 2222,
2236 S2_lsr_i_r_acc = 2223,
2237 S2_lsr_i_r_and = 2224,
2238 S2_lsr_i_r_nac = 2225,
2239 S2_lsr_i_r_or = 2226,
2240 S2_lsr_i_r_xacc = 2227,
2241 S2_lsr_i_vh = 2228,
2242 S2_lsr_i_vw = 2229,
2243 S2_lsr_r_p = 2230,
2244 S2_lsr_r_p_acc = 2231,
2245 S2_lsr_r_p_and = 2232,
2246 S2_lsr_r_p_nac = 2233,
2247 S2_lsr_r_p_or = 2234,
2248 S2_lsr_r_p_xor = 2235,
2249 S2_lsr_r_r = 2236,
2250 S2_lsr_r_r_acc = 2237,
2251 S2_lsr_r_r_and = 2238,
2252 S2_lsr_r_r_nac = 2239,
2253 S2_lsr_r_r_or = 2240,
2254 S2_lsr_r_vh = 2241,
2255 S2_lsr_r_vw = 2242,
2256 S2_mask = 2243,
2257 S2_packhl = 2244,
2258 S2_parityp = 2245,
2259 S2_pstorerbf_io = 2246,
2260 S2_pstorerbf_pi = 2247,
2261 S2_pstorerbfnew_pi = 2248,
2262 S2_pstorerbnewf_io = 2249,
2263 S2_pstorerbnewf_pi = 2250,
2264 S2_pstorerbnewfnew_pi = 2251,
2265 S2_pstorerbnewt_io = 2252,
2266 S2_pstorerbnewt_pi = 2253,
2267 S2_pstorerbnewtnew_pi = 2254,
2268 S2_pstorerbt_io = 2255,
2269 S2_pstorerbt_pi = 2256,
2270 S2_pstorerbtnew_pi = 2257,
2271 S2_pstorerdf_io = 2258,
2272 S2_pstorerdf_pi = 2259,
2273 S2_pstorerdfnew_pi = 2260,
2274 S2_pstorerdt_io = 2261,
2275 S2_pstorerdt_pi = 2262,
2276 S2_pstorerdtnew_pi = 2263,
2277 S2_pstorerff_io = 2264,
2278 S2_pstorerff_pi = 2265,
2279 S2_pstorerffnew_pi = 2266,
2280 S2_pstorerft_io = 2267,
2281 S2_pstorerft_pi = 2268,
2282 S2_pstorerftnew_pi = 2269,
2283 S2_pstorerhf_io = 2270,
2284 S2_pstorerhf_pi = 2271,
2285 S2_pstorerhfnew_pi = 2272,
2286 S2_pstorerhnewf_io = 2273,
2287 S2_pstorerhnewf_pi = 2274,
2288 S2_pstorerhnewfnew_pi = 2275,
2289 S2_pstorerhnewt_io = 2276,
2290 S2_pstorerhnewt_pi = 2277,
2291 S2_pstorerhnewtnew_pi = 2278,
2292 S2_pstorerht_io = 2279,
2293 S2_pstorerht_pi = 2280,
2294 S2_pstorerhtnew_pi = 2281,
2295 S2_pstorerif_io = 2282,
2296 S2_pstorerif_pi = 2283,
2297 S2_pstorerifnew_pi = 2284,
2298 S2_pstorerinewf_io = 2285,
2299 S2_pstorerinewf_pi = 2286,
2300 S2_pstorerinewfnew_pi = 2287,
2301 S2_pstorerinewt_io = 2288,
2302 S2_pstorerinewt_pi = 2289,
2303 S2_pstorerinewtnew_pi = 2290,
2304 S2_pstorerit_io = 2291,
2305 S2_pstorerit_pi = 2292,
2306 S2_pstoreritnew_pi = 2293,
2307 S2_setbit_i = 2294,
2308 S2_setbit_r = 2295,
2309 S2_shuffeb = 2296,
2310 S2_shuffeh = 2297,
2311 S2_shuffob = 2298,
2312 S2_shuffoh = 2299,
2313 S2_storerb_io = 2300,
2314 S2_storerb_pbr = 2301,
2315 S2_storerb_pci = 2302,
2316 S2_storerb_pcr = 2303,
2317 S2_storerb_pi = 2304,
2318 S2_storerb_pr = 2305,
2319 S2_storerbgp = 2306,
2320 S2_storerbnew_io = 2307,
2321 S2_storerbnew_pbr = 2308,
2322 S2_storerbnew_pci = 2309,
2323 S2_storerbnew_pcr = 2310,
2324 S2_storerbnew_pi = 2311,
2325 S2_storerbnew_pr = 2312,
2326 S2_storerbnewgp = 2313,
2327 S2_storerd_io = 2314,
2328 S2_storerd_pbr = 2315,
2329 S2_storerd_pci = 2316,
2330 S2_storerd_pcr = 2317,
2331 S2_storerd_pi = 2318,
2332 S2_storerd_pr = 2319,
2333 S2_storerdgp = 2320,
2334 S2_storerf_io = 2321,
2335 S2_storerf_pbr = 2322,
2336 S2_storerf_pci = 2323,
2337 S2_storerf_pcr = 2324,
2338 S2_storerf_pi = 2325,
2339 S2_storerf_pr = 2326,
2340 S2_storerfgp = 2327,
2341 S2_storerh_io = 2328,
2342 S2_storerh_pbr = 2329,
2343 S2_storerh_pci = 2330,
2344 S2_storerh_pcr = 2331,
2345 S2_storerh_pi = 2332,
2346 S2_storerh_pr = 2333,
2347 S2_storerhgp = 2334,
2348 S2_storerhnew_io = 2335,
2349 S2_storerhnew_pbr = 2336,
2350 S2_storerhnew_pci = 2337,
2351 S2_storerhnew_pcr = 2338,
2352 S2_storerhnew_pi = 2339,
2353 S2_storerhnew_pr = 2340,
2354 S2_storerhnewgp = 2341,
2355 S2_storeri_io = 2342,
2356 S2_storeri_pbr = 2343,
2357 S2_storeri_pci = 2344,
2358 S2_storeri_pcr = 2345,
2359 S2_storeri_pi = 2346,
2360 S2_storeri_pr = 2347,
2361 S2_storerigp = 2348,
2362 S2_storerinew_io = 2349,
2363 S2_storerinew_pbr = 2350,
2364 S2_storerinew_pci = 2351,
2365 S2_storerinew_pcr = 2352,
2366 S2_storerinew_pi = 2353,
2367 S2_storerinew_pr = 2354,
2368 S2_storerinewgp = 2355,
2369 S2_storew_locked = 2356,
2370 S2_storew_rl_at_vi = 2357,
2371 S2_storew_rl_st_vi = 2358,
2372 S2_svsathb = 2359,
2373 S2_svsathub = 2360,
2374 S2_tableidxb = 2361,
2375 S2_tableidxd = 2362,
2376 S2_tableidxh = 2363,
2377 S2_tableidxw = 2364,
2378 S2_togglebit_i = 2365,
2379 S2_togglebit_r = 2366,
2380 S2_tstbit_i = 2367,
2381 S2_tstbit_r = 2368,
2382 S2_valignib = 2369,
2383 S2_valignrb = 2370,
2384 S2_vcnegh = 2371,
2385 S2_vcrotate = 2372,
2386 S2_vrcnegh = 2373,
2387 S2_vrndpackwh = 2374,
2388 S2_vrndpackwhs = 2375,
2389 S2_vsathb = 2376,
2390 S2_vsathb_nopack = 2377,
2391 S2_vsathub = 2378,
2392 S2_vsathub_nopack = 2379,
2393 S2_vsatwh = 2380,
2394 S2_vsatwh_nopack = 2381,
2395 S2_vsatwuh = 2382,
2396 S2_vsatwuh_nopack = 2383,
2397 S2_vsplatrb = 2384,
2398 S2_vsplatrh = 2385,
2399 S2_vspliceib = 2386,
2400 S2_vsplicerb = 2387,
2401 S2_vsxtbh = 2388,
2402 S2_vsxthw = 2389,
2403 S2_vtrunehb = 2390,
2404 S2_vtrunewh = 2391,
2405 S2_vtrunohb = 2392,
2406 S2_vtrunowh = 2393,
2407 S2_vzxtbh = 2394,
2408 S2_vzxthw = 2395,
2409 S4_addaddi = 2396,
2410 S4_addi_asl_ri = 2397,
2411 S4_addi_lsr_ri = 2398,
2412 S4_andi_asl_ri = 2399,
2413 S4_andi_lsr_ri = 2400,
2414 S4_clbaddi = 2401,
2415 S4_clbpaddi = 2402,
2416 S4_clbpnorm = 2403,
2417 S4_extract = 2404,
2418 S4_extract_rp = 2405,
2419 S4_extractp = 2406,
2420 S4_extractp_rp = 2407,
2421 S4_lsli = 2408,
2422 S4_ntstbit_i = 2409,
2423 S4_ntstbit_r = 2410,
2424 S4_or_andi = 2411,
2425 S4_or_andix = 2412,
2426 S4_or_ori = 2413,
2427 S4_ori_asl_ri = 2414,
2428 S4_ori_lsr_ri = 2415,
2429 S4_parity = 2416,
2430 S4_pstorerbf_abs = 2417,
2431 S4_pstorerbf_rr = 2418,
2432 S4_pstorerbfnew_abs = 2419,
2433 S4_pstorerbfnew_io = 2420,
2434 S4_pstorerbfnew_rr = 2421,
2435 S4_pstorerbnewf_abs = 2422,
2436 S4_pstorerbnewf_rr = 2423,
2437 S4_pstorerbnewfnew_abs = 2424,
2438 S4_pstorerbnewfnew_io = 2425,
2439 S4_pstorerbnewfnew_rr = 2426,
2440 S4_pstorerbnewt_abs = 2427,
2441 S4_pstorerbnewt_rr = 2428,
2442 S4_pstorerbnewtnew_abs = 2429,
2443 S4_pstorerbnewtnew_io = 2430,
2444 S4_pstorerbnewtnew_rr = 2431,
2445 S4_pstorerbt_abs = 2432,
2446 S4_pstorerbt_rr = 2433,
2447 S4_pstorerbtnew_abs = 2434,
2448 S4_pstorerbtnew_io = 2435,
2449 S4_pstorerbtnew_rr = 2436,
2450 S4_pstorerdf_abs = 2437,
2451 S4_pstorerdf_rr = 2438,
2452 S4_pstorerdfnew_abs = 2439,
2453 S4_pstorerdfnew_io = 2440,
2454 S4_pstorerdfnew_rr = 2441,
2455 S4_pstorerdt_abs = 2442,
2456 S4_pstorerdt_rr = 2443,
2457 S4_pstorerdtnew_abs = 2444,
2458 S4_pstorerdtnew_io = 2445,
2459 S4_pstorerdtnew_rr = 2446,
2460 S4_pstorerff_abs = 2447,
2461 S4_pstorerff_rr = 2448,
2462 S4_pstorerffnew_abs = 2449,
2463 S4_pstorerffnew_io = 2450,
2464 S4_pstorerffnew_rr = 2451,
2465 S4_pstorerft_abs = 2452,
2466 S4_pstorerft_rr = 2453,
2467 S4_pstorerftnew_abs = 2454,
2468 S4_pstorerftnew_io = 2455,
2469 S4_pstorerftnew_rr = 2456,
2470 S4_pstorerhf_abs = 2457,
2471 S4_pstorerhf_rr = 2458,
2472 S4_pstorerhfnew_abs = 2459,
2473 S4_pstorerhfnew_io = 2460,
2474 S4_pstorerhfnew_rr = 2461,
2475 S4_pstorerhnewf_abs = 2462,
2476 S4_pstorerhnewf_rr = 2463,
2477 S4_pstorerhnewfnew_abs = 2464,
2478 S4_pstorerhnewfnew_io = 2465,
2479 S4_pstorerhnewfnew_rr = 2466,
2480 S4_pstorerhnewt_abs = 2467,
2481 S4_pstorerhnewt_rr = 2468,
2482 S4_pstorerhnewtnew_abs = 2469,
2483 S4_pstorerhnewtnew_io = 2470,
2484 S4_pstorerhnewtnew_rr = 2471,
2485 S4_pstorerht_abs = 2472,
2486 S4_pstorerht_rr = 2473,
2487 S4_pstorerhtnew_abs = 2474,
2488 S4_pstorerhtnew_io = 2475,
2489 S4_pstorerhtnew_rr = 2476,
2490 S4_pstorerif_abs = 2477,
2491 S4_pstorerif_rr = 2478,
2492 S4_pstorerifnew_abs = 2479,
2493 S4_pstorerifnew_io = 2480,
2494 S4_pstorerifnew_rr = 2481,
2495 S4_pstorerinewf_abs = 2482,
2496 S4_pstorerinewf_rr = 2483,
2497 S4_pstorerinewfnew_abs = 2484,
2498 S4_pstorerinewfnew_io = 2485,
2499 S4_pstorerinewfnew_rr = 2486,
2500 S4_pstorerinewt_abs = 2487,
2501 S4_pstorerinewt_rr = 2488,
2502 S4_pstorerinewtnew_abs = 2489,
2503 S4_pstorerinewtnew_io = 2490,
2504 S4_pstorerinewtnew_rr = 2491,
2505 S4_pstorerit_abs = 2492,
2506 S4_pstorerit_rr = 2493,
2507 S4_pstoreritnew_abs = 2494,
2508 S4_pstoreritnew_io = 2495,
2509 S4_pstoreritnew_rr = 2496,
2510 S4_stored_locked = 2497,
2511 S4_stored_rl_at_vi = 2498,
2512 S4_stored_rl_st_vi = 2499,
2513 S4_storeirb_io = 2500,
2514 S4_storeirbf_io = 2501,
2515 S4_storeirbfnew_io = 2502,
2516 S4_storeirbt_io = 2503,
2517 S4_storeirbtnew_io = 2504,
2518 S4_storeirh_io = 2505,
2519 S4_storeirhf_io = 2506,
2520 S4_storeirhfnew_io = 2507,
2521 S4_storeirht_io = 2508,
2522 S4_storeirhtnew_io = 2509,
2523 S4_storeiri_io = 2510,
2524 S4_storeirif_io = 2511,
2525 S4_storeirifnew_io = 2512,
2526 S4_storeirit_io = 2513,
2527 S4_storeiritnew_io = 2514,
2528 S4_storerb_ap = 2515,
2529 S4_storerb_rr = 2516,
2530 S4_storerb_ur = 2517,
2531 S4_storerbnew_ap = 2518,
2532 S4_storerbnew_rr = 2519,
2533 S4_storerbnew_ur = 2520,
2534 S4_storerd_ap = 2521,
2535 S4_storerd_rr = 2522,
2536 S4_storerd_ur = 2523,
2537 S4_storerf_ap = 2524,
2538 S4_storerf_rr = 2525,
2539 S4_storerf_ur = 2526,
2540 S4_storerh_ap = 2527,
2541 S4_storerh_rr = 2528,
2542 S4_storerh_ur = 2529,
2543 S4_storerhnew_ap = 2530,
2544 S4_storerhnew_rr = 2531,
2545 S4_storerhnew_ur = 2532,
2546 S4_storeri_ap = 2533,
2547 S4_storeri_rr = 2534,
2548 S4_storeri_ur = 2535,
2549 S4_storerinew_ap = 2536,
2550 S4_storerinew_rr = 2537,
2551 S4_storerinew_ur = 2538,
2552 S4_subaddi = 2539,
2553 S4_subi_asl_ri = 2540,
2554 S4_subi_lsr_ri = 2541,
2555 S4_vrcrotate = 2542,
2556 S4_vrcrotate_acc = 2543,
2557 S4_vxaddsubh = 2544,
2558 S4_vxaddsubhr = 2545,
2559 S4_vxaddsubw = 2546,
2560 S4_vxsubaddh = 2547,
2561 S4_vxsubaddhr = 2548,
2562 S4_vxsubaddw = 2549,
2563 S5_asrhub_rnd_sat = 2550,
2564 S5_asrhub_sat = 2551,
2565 S5_popcountp = 2552,
2566 S5_vasrhrnd = 2553,
2567 S6_rol_i_p = 2554,
2568 S6_rol_i_p_acc = 2555,
2569 S6_rol_i_p_and = 2556,
2570 S6_rol_i_p_nac = 2557,
2571 S6_rol_i_p_or = 2558,
2572 S6_rol_i_p_xacc = 2559,
2573 S6_rol_i_r = 2560,
2574 S6_rol_i_r_acc = 2561,
2575 S6_rol_i_r_and = 2562,
2576 S6_rol_i_r_nac = 2563,
2577 S6_rol_i_r_or = 2564,
2578 S6_rol_i_r_xacc = 2565,
2579 S6_vsplatrbp = 2566,
2580 S6_vtrunehb_ppp = 2567,
2581 S6_vtrunohb_ppp = 2568,
2582 SA1_addi = 2569,
2583 SA1_addrx = 2570,
2584 SA1_addsp = 2571,
2585 SA1_and1 = 2572,
2586 SA1_clrf = 2573,
2587 SA1_clrfnew = 2574,
2588 SA1_clrt = 2575,
2589 SA1_clrtnew = 2576,
2590 SA1_cmpeqi = 2577,
2591 SA1_combine0i = 2578,
2592 SA1_combine1i = 2579,
2593 SA1_combine2i = 2580,
2594 SA1_combine3i = 2581,
2595 SA1_combinerz = 2582,
2596 SA1_combinezr = 2583,
2597 SA1_dec = 2584,
2598 SA1_inc = 2585,
2599 SA1_seti = 2586,
2600 SA1_setin1 = 2587,
2601 SA1_sxtb = 2588,
2602 SA1_sxth = 2589,
2603 SA1_tfr = 2590,
2604 SA1_zxtb = 2591,
2605 SA1_zxth = 2592,
2606 SAVE_REGISTERS_CALL_V4 = 2593,
2607 SAVE_REGISTERS_CALL_V4STK = 2594,
2608 SAVE_REGISTERS_CALL_V4STK_EXT = 2595,
2609 SAVE_REGISTERS_CALL_V4STK_EXT_PIC = 2596,
2610 SAVE_REGISTERS_CALL_V4STK_PIC = 2597,
2611 SAVE_REGISTERS_CALL_V4_EXT = 2598,
2612 SAVE_REGISTERS_CALL_V4_EXT_PIC = 2599,
2613 SAVE_REGISTERS_CALL_V4_PIC = 2600,
2614 SL1_loadri_io = 2601,
2615 SL1_loadrub_io = 2602,
2616 SL2_deallocframe = 2603,
2617 SL2_jumpr31 = 2604,
2618 SL2_jumpr31_f = 2605,
2619 SL2_jumpr31_fnew = 2606,
2620 SL2_jumpr31_t = 2607,
2621 SL2_jumpr31_tnew = 2608,
2622 SL2_loadrb_io = 2609,
2623 SL2_loadrd_sp = 2610,
2624 SL2_loadrh_io = 2611,
2625 SL2_loadri_sp = 2612,
2626 SL2_loadruh_io = 2613,
2627 SL2_return = 2614,
2628 SL2_return_f = 2615,
2629 SL2_return_fnew = 2616,
2630 SL2_return_t = 2617,
2631 SL2_return_tnew = 2618,
2632 SS1_storeb_io = 2619,
2633 SS1_storew_io = 2620,
2634 SS2_allocframe = 2621,
2635 SS2_storebi0 = 2622,
2636 SS2_storebi1 = 2623,
2637 SS2_stored_sp = 2624,
2638 SS2_storeh_io = 2625,
2639 SS2_storew_sp = 2626,
2640 SS2_storewi0 = 2627,
2641 SS2_storewi1 = 2628,
2642 TFRI64_V2_ext = 2629,
2643 TFRI64_V4 = 2630,
2644 V6_extractw = 2631,
2645 V6_get_qfext = 2632,
2646 V6_get_qfext_oracc = 2633,
2647 V6_lvsplatb = 2634,
2648 V6_lvsplath = 2635,
2649 V6_lvsplatw = 2636,
2650 V6_pred_and = 2637,
2651 V6_pred_and_n = 2638,
2652 V6_pred_not = 2639,
2653 V6_pred_or = 2640,
2654 V6_pred_or_n = 2641,
2655 V6_pred_scalar2 = 2642,
2656 V6_pred_scalar2v2 = 2643,
2657 V6_pred_xor = 2644,
2658 V6_set_qfext = 2645,
2659 V6_shuffeqh = 2646,
2660 V6_shuffeqw = 2647,
2661 V6_v6mpyhubs10 = 2648,
2662 V6_v6mpyhubs10_vxx = 2649,
2663 V6_v6mpyvubs10 = 2650,
2664 V6_v6mpyvubs10_vxx = 2651,
2665 V6_vL32Ub_ai = 2652,
2666 V6_vL32Ub_pi = 2653,
2667 V6_vL32Ub_ppu = 2654,
2668 V6_vL32b_ai = 2655,
2669 V6_vL32b_cur_ai = 2656,
2670 V6_vL32b_cur_npred_ai = 2657,
2671 V6_vL32b_cur_npred_pi = 2658,
2672 V6_vL32b_cur_npred_ppu = 2659,
2673 V6_vL32b_cur_pi = 2660,
2674 V6_vL32b_cur_ppu = 2661,
2675 V6_vL32b_cur_pred_ai = 2662,
2676 V6_vL32b_cur_pred_pi = 2663,
2677 V6_vL32b_cur_pred_ppu = 2664,
2678 V6_vL32b_npred_ai = 2665,
2679 V6_vL32b_npred_pi = 2666,
2680 V6_vL32b_npred_ppu = 2667,
2681 V6_vL32b_nt_ai = 2668,
2682 V6_vL32b_nt_cur_ai = 2669,
2683 V6_vL32b_nt_cur_npred_ai = 2670,
2684 V6_vL32b_nt_cur_npred_pi = 2671,
2685 V6_vL32b_nt_cur_npred_ppu = 2672,
2686 V6_vL32b_nt_cur_pi = 2673,
2687 V6_vL32b_nt_cur_ppu = 2674,
2688 V6_vL32b_nt_cur_pred_ai = 2675,
2689 V6_vL32b_nt_cur_pred_pi = 2676,
2690 V6_vL32b_nt_cur_pred_ppu = 2677,
2691 V6_vL32b_nt_npred_ai = 2678,
2692 V6_vL32b_nt_npred_pi = 2679,
2693 V6_vL32b_nt_npred_ppu = 2680,
2694 V6_vL32b_nt_pi = 2681,
2695 V6_vL32b_nt_ppu = 2682,
2696 V6_vL32b_nt_pred_ai = 2683,
2697 V6_vL32b_nt_pred_pi = 2684,
2698 V6_vL32b_nt_pred_ppu = 2685,
2699 V6_vL32b_nt_tmp_ai = 2686,
2700 V6_vL32b_nt_tmp_npred_ai = 2687,
2701 V6_vL32b_nt_tmp_npred_pi = 2688,
2702 V6_vL32b_nt_tmp_npred_ppu = 2689,
2703 V6_vL32b_nt_tmp_pi = 2690,
2704 V6_vL32b_nt_tmp_ppu = 2691,
2705 V6_vL32b_nt_tmp_pred_ai = 2692,
2706 V6_vL32b_nt_tmp_pred_pi = 2693,
2707 V6_vL32b_nt_tmp_pred_ppu = 2694,
2708 V6_vL32b_pi = 2695,
2709 V6_vL32b_ppu = 2696,
2710 V6_vL32b_pred_ai = 2697,
2711 V6_vL32b_pred_pi = 2698,
2712 V6_vL32b_pred_ppu = 2699,
2713 V6_vL32b_tmp_ai = 2700,
2714 V6_vL32b_tmp_npred_ai = 2701,
2715 V6_vL32b_tmp_npred_pi = 2702,
2716 V6_vL32b_tmp_npred_ppu = 2703,
2717 V6_vL32b_tmp_pi = 2704,
2718 V6_vL32b_tmp_ppu = 2705,
2719 V6_vL32b_tmp_pred_ai = 2706,
2720 V6_vL32b_tmp_pred_pi = 2707,
2721 V6_vL32b_tmp_pred_ppu = 2708,
2722 V6_vS32Ub_ai = 2709,
2723 V6_vS32Ub_npred_ai = 2710,
2724 V6_vS32Ub_npred_pi = 2711,
2725 V6_vS32Ub_npred_ppu = 2712,
2726 V6_vS32Ub_pi = 2713,
2727 V6_vS32Ub_ppu = 2714,
2728 V6_vS32Ub_pred_ai = 2715,
2729 V6_vS32Ub_pred_pi = 2716,
2730 V6_vS32Ub_pred_ppu = 2717,
2731 V6_vS32b_ai = 2718,
2732 V6_vS32b_new_ai = 2719,
2733 V6_vS32b_new_npred_ai = 2720,
2734 V6_vS32b_new_npred_pi = 2721,
2735 V6_vS32b_new_npred_ppu = 2722,
2736 V6_vS32b_new_pi = 2723,
2737 V6_vS32b_new_ppu = 2724,
2738 V6_vS32b_new_pred_ai = 2725,
2739 V6_vS32b_new_pred_pi = 2726,
2740 V6_vS32b_new_pred_ppu = 2727,
2741 V6_vS32b_npred_ai = 2728,
2742 V6_vS32b_npred_pi = 2729,
2743 V6_vS32b_npred_ppu = 2730,
2744 V6_vS32b_nqpred_ai = 2731,
2745 V6_vS32b_nqpred_pi = 2732,
2746 V6_vS32b_nqpred_ppu = 2733,
2747 V6_vS32b_nt_ai = 2734,
2748 V6_vS32b_nt_new_ai = 2735,
2749 V6_vS32b_nt_new_npred_ai = 2736,
2750 V6_vS32b_nt_new_npred_pi = 2737,
2751 V6_vS32b_nt_new_npred_ppu = 2738,
2752 V6_vS32b_nt_new_pi = 2739,
2753 V6_vS32b_nt_new_ppu = 2740,
2754 V6_vS32b_nt_new_pred_ai = 2741,
2755 V6_vS32b_nt_new_pred_pi = 2742,
2756 V6_vS32b_nt_new_pred_ppu = 2743,
2757 V6_vS32b_nt_npred_ai = 2744,
2758 V6_vS32b_nt_npred_pi = 2745,
2759 V6_vS32b_nt_npred_ppu = 2746,
2760 V6_vS32b_nt_nqpred_ai = 2747,
2761 V6_vS32b_nt_nqpred_pi = 2748,
2762 V6_vS32b_nt_nqpred_ppu = 2749,
2763 V6_vS32b_nt_pi = 2750,
2764 V6_vS32b_nt_ppu = 2751,
2765 V6_vS32b_nt_pred_ai = 2752,
2766 V6_vS32b_nt_pred_pi = 2753,
2767 V6_vS32b_nt_pred_ppu = 2754,
2768 V6_vS32b_nt_qpred_ai = 2755,
2769 V6_vS32b_nt_qpred_pi = 2756,
2770 V6_vS32b_nt_qpred_ppu = 2757,
2771 V6_vS32b_pi = 2758,
2772 V6_vS32b_ppu = 2759,
2773 V6_vS32b_pred_ai = 2760,
2774 V6_vS32b_pred_pi = 2761,
2775 V6_vS32b_pred_ppu = 2762,
2776 V6_vS32b_qpred_ai = 2763,
2777 V6_vS32b_qpred_pi = 2764,
2778 V6_vS32b_qpred_ppu = 2765,
2779 V6_vS32b_srls_ai = 2766,
2780 V6_vS32b_srls_pi = 2767,
2781 V6_vS32b_srls_ppu = 2768,
2782 V6_vabs_f8 = 2769,
2783 V6_vabs_hf = 2770,
2784 V6_vabs_sf = 2771,
2785 V6_vabsb = 2772,
2786 V6_vabsb_sat = 2773,
2787 V6_vabsdiffh = 2774,
2788 V6_vabsdiffub = 2775,
2789 V6_vabsdiffuh = 2776,
2790 V6_vabsdiffw = 2777,
2791 V6_vabsh = 2778,
2792 V6_vabsh_sat = 2779,
2793 V6_vabsw = 2780,
2794 V6_vabsw_sat = 2781,
2795 V6_vadd_hf = 2782,
2796 V6_vadd_hf_f8 = 2783,
2797 V6_vadd_hf_hf = 2784,
2798 V6_vadd_qf16 = 2785,
2799 V6_vadd_qf16_mix = 2786,
2800 V6_vadd_qf32 = 2787,
2801 V6_vadd_qf32_mix = 2788,
2802 V6_vadd_sf = 2789,
2803 V6_vadd_sf_bf = 2790,
2804 V6_vadd_sf_hf = 2791,
2805 V6_vadd_sf_sf = 2792,
2806 V6_vaddb = 2793,
2807 V6_vaddb_dv = 2794,
2808 V6_vaddbnq = 2795,
2809 V6_vaddbq = 2796,
2810 V6_vaddbsat = 2797,
2811 V6_vaddbsat_dv = 2798,
2812 V6_vaddcarry = 2799,
2813 V6_vaddcarryo = 2800,
2814 V6_vaddcarrysat = 2801,
2815 V6_vaddclbh = 2802,
2816 V6_vaddclbw = 2803,
2817 V6_vaddh = 2804,
2818 V6_vaddh_dv = 2805,
2819 V6_vaddhnq = 2806,
2820 V6_vaddhq = 2807,
2821 V6_vaddhsat = 2808,
2822 V6_vaddhsat_dv = 2809,
2823 V6_vaddhw = 2810,
2824 V6_vaddhw_acc = 2811,
2825 V6_vaddubh = 2812,
2826 V6_vaddubh_acc = 2813,
2827 V6_vaddubsat = 2814,
2828 V6_vaddubsat_dv = 2815,
2829 V6_vaddububb_sat = 2816,
2830 V6_vadduhsat = 2817,
2831 V6_vadduhsat_dv = 2818,
2832 V6_vadduhw = 2819,
2833 V6_vadduhw_acc = 2820,
2834 V6_vadduwsat = 2821,
2835 V6_vadduwsat_dv = 2822,
2836 V6_vaddw = 2823,
2837 V6_vaddw_dv = 2824,
2838 V6_vaddwnq = 2825,
2839 V6_vaddwq = 2826,
2840 V6_vaddwsat = 2827,
2841 V6_vaddwsat_dv = 2828,
2842 V6_valignb = 2829,
2843 V6_valignbi = 2830,
2844 V6_vand = 2831,
2845 V6_vandnqrt = 2832,
2846 V6_vandnqrt_acc = 2833,
2847 V6_vandqrt = 2834,
2848 V6_vandqrt_acc = 2835,
2849 V6_vandvnqv = 2836,
2850 V6_vandvqv = 2837,
2851 V6_vandvrt = 2838,
2852 V6_vandvrt_acc = 2839,
2853 V6_vaslh = 2840,
2854 V6_vaslh_acc = 2841,
2855 V6_vaslhv = 2842,
2856 V6_vaslw = 2843,
2857 V6_vaslw_acc = 2844,
2858 V6_vaslwv = 2845,
2859 V6_vasr_into = 2846,
2860 V6_vasrh = 2847,
2861 V6_vasrh_acc = 2848,
2862 V6_vasrhbrndsat = 2849,
2863 V6_vasrhbsat = 2850,
2864 V6_vasrhubrndsat = 2851,
2865 V6_vasrhubsat = 2852,
2866 V6_vasrhv = 2853,
2867 V6_vasruhubrndsat = 2854,
2868 V6_vasruhubsat = 2855,
2869 V6_vasruwuhrndsat = 2856,
2870 V6_vasruwuhsat = 2857,
2871 V6_vasrvuhubrndsat = 2858,
2872 V6_vasrvuhubsat = 2859,
2873 V6_vasrvwuhrndsat = 2860,
2874 V6_vasrvwuhsat = 2861,
2875 V6_vasrw = 2862,
2876 V6_vasrw_acc = 2863,
2877 V6_vasrwh = 2864,
2878 V6_vasrwhrndsat = 2865,
2879 V6_vasrwhsat = 2866,
2880 V6_vasrwuhrndsat = 2867,
2881 V6_vasrwuhsat = 2868,
2882 V6_vasrwv = 2869,
2883 V6_vassign = 2870,
2884 V6_vassign_fp = 2871,
2885 V6_vassign_tmp = 2872,
2886 V6_vavgb = 2873,
2887 V6_vavgbrnd = 2874,
2888 V6_vavgh = 2875,
2889 V6_vavghrnd = 2876,
2890 V6_vavgub = 2877,
2891 V6_vavgubrnd = 2878,
2892 V6_vavguh = 2879,
2893 V6_vavguhrnd = 2880,
2894 V6_vavguw = 2881,
2895 V6_vavguwrnd = 2882,
2896 V6_vavgw = 2883,
2897 V6_vavgwrnd = 2884,
2898 V6_vccombine = 2885,
2899 V6_vcl0h = 2886,
2900 V6_vcl0w = 2887,
2901 V6_vcmov = 2888,
2902 V6_vcombine = 2889,
2903 V6_vcombine_tmp = 2890,
2904 V6_vconv_h_hf = 2891,
2905 V6_vconv_hf_h = 2892,
2906 V6_vconv_hf_qf16 = 2893,
2907 V6_vconv_hf_qf32 = 2894,
2908 V6_vconv_sf_qf32 = 2895,
2909 V6_vconv_sf_w = 2896,
2910 V6_vconv_w_sf = 2897,
2911 V6_vcvt2_b_hf = 2898,
2912 V6_vcvt2_hf_b = 2899,
2913 V6_vcvt2_hf_ub = 2900,
2914 V6_vcvt2_ub_hf = 2901,
2915 V6_vcvt_b_hf = 2902,
2916 V6_vcvt_bf_sf = 2903,
2917 V6_vcvt_f8_hf = 2904,
2918 V6_vcvt_h_hf = 2905,
2919 V6_vcvt_hf_b = 2906,
2920 V6_vcvt_hf_f8 = 2907,
2921 V6_vcvt_hf_h = 2908,
2922 V6_vcvt_hf_sf = 2909,
2923 V6_vcvt_hf_ub = 2910,
2924 V6_vcvt_hf_uh = 2911,
2925 V6_vcvt_sf_hf = 2912,
2926 V6_vcvt_ub_hf = 2913,
2927 V6_vcvt_uh_hf = 2914,
2928 V6_vdeal = 2915,
2929 V6_vdealb = 2916,
2930 V6_vdealb4w = 2917,
2931 V6_vdealh = 2918,
2932 V6_vdealvdd = 2919,
2933 V6_vdelta = 2920,
2934 V6_vdmpy_sf_hf = 2921,
2935 V6_vdmpy_sf_hf_acc = 2922,
2936 V6_vdmpybus = 2923,
2937 V6_vdmpybus_acc = 2924,
2938 V6_vdmpybus_dv = 2925,
2939 V6_vdmpybus_dv_acc = 2926,
2940 V6_vdmpyhb = 2927,
2941 V6_vdmpyhb_acc = 2928,
2942 V6_vdmpyhb_dv = 2929,
2943 V6_vdmpyhb_dv_acc = 2930,
2944 V6_vdmpyhisat = 2931,
2945 V6_vdmpyhisat_acc = 2932,
2946 V6_vdmpyhsat = 2933,
2947 V6_vdmpyhsat_acc = 2934,
2948 V6_vdmpyhsuisat = 2935,
2949 V6_vdmpyhsuisat_acc = 2936,
2950 V6_vdmpyhsusat = 2937,
2951 V6_vdmpyhsusat_acc = 2938,
2952 V6_vdmpyhvsat = 2939,
2953 V6_vdmpyhvsat_acc = 2940,
2954 V6_vdsaduh = 2941,
2955 V6_vdsaduh_acc = 2942,
2956 V6_veqb = 2943,
2957 V6_veqb_and = 2944,
2958 V6_veqb_or = 2945,
2959 V6_veqb_xor = 2946,
2960 V6_veqh = 2947,
2961 V6_veqh_and = 2948,
2962 V6_veqh_or = 2949,
2963 V6_veqh_xor = 2950,
2964 V6_veqw = 2951,
2965 V6_veqw_and = 2952,
2966 V6_veqw_or = 2953,
2967 V6_veqw_xor = 2954,
2968 V6_vfmax_f8 = 2955,
2969 V6_vfmax_hf = 2956,
2970 V6_vfmax_sf = 2957,
2971 V6_vfmin_f8 = 2958,
2972 V6_vfmin_hf = 2959,
2973 V6_vfmin_sf = 2960,
2974 V6_vfneg_f8 = 2961,
2975 V6_vfneg_hf = 2962,
2976 V6_vfneg_sf = 2963,
2977 V6_vgathermh = 2964,
2978 V6_vgathermhq = 2965,
2979 V6_vgathermhw = 2966,
2980 V6_vgathermhwq = 2967,
2981 V6_vgathermw = 2968,
2982 V6_vgathermwq = 2969,
2983 V6_vgtb = 2970,
2984 V6_vgtb_and = 2971,
2985 V6_vgtb_or = 2972,
2986 V6_vgtb_xor = 2973,
2987 V6_vgtbf = 2974,
2988 V6_vgtbf_and = 2975,
2989 V6_vgtbf_or = 2976,
2990 V6_vgtbf_xor = 2977,
2991 V6_vgth = 2978,
2992 V6_vgth_and = 2979,
2993 V6_vgth_or = 2980,
2994 V6_vgth_xor = 2981,
2995 V6_vgthf = 2982,
2996 V6_vgthf_and = 2983,
2997 V6_vgthf_or = 2984,
2998 V6_vgthf_xor = 2985,
2999 V6_vgtsf = 2986,
3000 V6_vgtsf_and = 2987,
3001 V6_vgtsf_or = 2988,
3002 V6_vgtsf_xor = 2989,
3003 V6_vgtub = 2990,
3004 V6_vgtub_and = 2991,
3005 V6_vgtub_or = 2992,
3006 V6_vgtub_xor = 2993,
3007 V6_vgtuh = 2994,
3008 V6_vgtuh_and = 2995,
3009 V6_vgtuh_or = 2996,
3010 V6_vgtuh_xor = 2997,
3011 V6_vgtuw = 2998,
3012 V6_vgtuw_and = 2999,
3013 V6_vgtuw_or = 3000,
3014 V6_vgtuw_xor = 3001,
3015 V6_vgtw = 3002,
3016 V6_vgtw_and = 3003,
3017 V6_vgtw_or = 3004,
3018 V6_vgtw_xor = 3005,
3019 V6_vhist = 3006,
3020 V6_vhistq = 3007,
3021 V6_vinsertwr = 3008,
3022 V6_vlalignb = 3009,
3023 V6_vlalignbi = 3010,
3024 V6_vlsrb = 3011,
3025 V6_vlsrh = 3012,
3026 V6_vlsrhv = 3013,
3027 V6_vlsrw = 3014,
3028 V6_vlsrwv = 3015,
3029 V6_vlut4 = 3016,
3030 V6_vlutvvb = 3017,
3031 V6_vlutvvb_nm = 3018,
3032 V6_vlutvvb_oracc = 3019,
3033 V6_vlutvvb_oracci = 3020,
3034 V6_vlutvvbi = 3021,
3035 V6_vlutvwh = 3022,
3036 V6_vlutvwh_nm = 3023,
3037 V6_vlutvwh_oracc = 3024,
3038 V6_vlutvwh_oracci = 3025,
3039 V6_vlutvwhi = 3026,
3040 V6_vmax_bf = 3027,
3041 V6_vmax_hf = 3028,
3042 V6_vmax_sf = 3029,
3043 V6_vmaxb = 3030,
3044 V6_vmaxh = 3031,
3045 V6_vmaxub = 3032,
3046 V6_vmaxuh = 3033,
3047 V6_vmaxw = 3034,
3048 V6_vmerge_qf = 3035,
3049 V6_vmin_bf = 3036,
3050 V6_vmin_hf = 3037,
3051 V6_vmin_sf = 3038,
3052 V6_vminb = 3039,
3053 V6_vminh = 3040,
3054 V6_vminub = 3041,
3055 V6_vminuh = 3042,
3056 V6_vminw = 3043,
3057 V6_vmpabus = 3044,
3058 V6_vmpabus_acc = 3045,
3059 V6_vmpabusv = 3046,
3060 V6_vmpabuu = 3047,
3061 V6_vmpabuu_acc = 3048,
3062 V6_vmpabuuv = 3049,
3063 V6_vmpahb = 3050,
3064 V6_vmpahb_acc = 3051,
3065 V6_vmpahhsat = 3052,
3066 V6_vmpauhb = 3053,
3067 V6_vmpauhb_acc = 3054,
3068 V6_vmpauhuhsat = 3055,
3069 V6_vmpsuhuhsat = 3056,
3070 V6_vmpy_hf_f8 = 3057,
3071 V6_vmpy_hf_f8_acc = 3058,
3072 V6_vmpy_hf_hf = 3059,
3073 V6_vmpy_hf_hf_acc = 3060,
3074 V6_vmpy_qf16 = 3061,
3075 V6_vmpy_qf16_hf = 3062,
3076 V6_vmpy_qf16_mix_hf = 3063,
3077 V6_vmpy_qf32 = 3064,
3078 V6_vmpy_qf32_hf = 3065,
3079 V6_vmpy_qf32_mix_hf = 3066,
3080 V6_vmpy_qf32_qf16 = 3067,
3081 V6_vmpy_qf32_sf = 3068,
3082 V6_vmpy_rt_hf = 3069,
3083 V6_vmpy_rt_qf16 = 3070,
3084 V6_vmpy_rt_sf = 3071,
3085 V6_vmpy_sf_bf = 3072,
3086 V6_vmpy_sf_bf_acc = 3073,
3087 V6_vmpy_sf_hf = 3074,
3088 V6_vmpy_sf_hf_acc = 3075,
3089 V6_vmpy_sf_sf = 3076,
3090 V6_vmpybus = 3077,
3091 V6_vmpybus_acc = 3078,
3092 V6_vmpybusv = 3079,
3093 V6_vmpybusv_acc = 3080,
3094 V6_vmpybv = 3081,
3095 V6_vmpybv_acc = 3082,
3096 V6_vmpyewuh = 3083,
3097 V6_vmpyewuh_64 = 3084,
3098 V6_vmpyh = 3085,
3099 V6_vmpyh_acc = 3086,
3100 V6_vmpyhsat_acc = 3087,
3101 V6_vmpyhsrs = 3088,
3102 V6_vmpyhss = 3089,
3103 V6_vmpyhus = 3090,
3104 V6_vmpyhus_acc = 3091,
3105 V6_vmpyhv = 3092,
3106 V6_vmpyhv_acc = 3093,
3107 V6_vmpyhvsrs = 3094,
3108 V6_vmpyieoh = 3095,
3109 V6_vmpyiewh_acc = 3096,
3110 V6_vmpyiewuh = 3097,
3111 V6_vmpyiewuh_acc = 3098,
3112 V6_vmpyih = 3099,
3113 V6_vmpyih_acc = 3100,
3114 V6_vmpyihb = 3101,
3115 V6_vmpyihb_acc = 3102,
3116 V6_vmpyiowh = 3103,
3117 V6_vmpyiwb = 3104,
3118 V6_vmpyiwb_acc = 3105,
3119 V6_vmpyiwh = 3106,
3120 V6_vmpyiwh_acc = 3107,
3121 V6_vmpyiwub = 3108,
3122 V6_vmpyiwub_acc = 3109,
3123 V6_vmpyowh = 3110,
3124 V6_vmpyowh_64_acc = 3111,
3125 V6_vmpyowh_rnd = 3112,
3126 V6_vmpyowh_rnd_sacc = 3113,
3127 V6_vmpyowh_sacc = 3114,
3128 V6_vmpyub = 3115,
3129 V6_vmpyub_acc = 3116,
3130 V6_vmpyubv = 3117,
3131 V6_vmpyubv_acc = 3118,
3132 V6_vmpyuh = 3119,
3133 V6_vmpyuh_acc = 3120,
3134 V6_vmpyuhe = 3121,
3135 V6_vmpyuhe_acc = 3122,
3136 V6_vmpyuhv = 3123,
3137 V6_vmpyuhv_acc = 3124,
3138 V6_vmpyuhvs = 3125,
3139 V6_vmux = 3126,
3140 V6_vnavgb = 3127,
3141 V6_vnavgh = 3128,
3142 V6_vnavgub = 3129,
3143 V6_vnavgw = 3130,
3144 V6_vnccombine = 3131,
3145 V6_vncmov = 3132,
3146 V6_vnormamth = 3133,
3147 V6_vnormamtw = 3134,
3148 V6_vnot = 3135,
3149 V6_vor = 3136,
3150 V6_vpackeb = 3137,
3151 V6_vpackeh = 3138,
3152 V6_vpackhb_sat = 3139,
3153 V6_vpackhub_sat = 3140,
3154 V6_vpackob = 3141,
3155 V6_vpackoh = 3142,
3156 V6_vpackwh_sat = 3143,
3157 V6_vpackwuh_sat = 3144,
3158 V6_vpopcounth = 3145,
3159 V6_vprefixqb = 3146,
3160 V6_vprefixqh = 3147,
3161 V6_vprefixqw = 3148,
3162 V6_vrdelta = 3149,
3163 V6_vrmpybub_rtt = 3150,
3164 V6_vrmpybub_rtt_acc = 3151,
3165 V6_vrmpybus = 3152,
3166 V6_vrmpybus_acc = 3153,
3167 V6_vrmpybusi = 3154,
3168 V6_vrmpybusi_acc = 3155,
3169 V6_vrmpybusv = 3156,
3170 V6_vrmpybusv_acc = 3157,
3171 V6_vrmpybv = 3158,
3172 V6_vrmpybv_acc = 3159,
3173 V6_vrmpyub = 3160,
3174 V6_vrmpyub_acc = 3161,
3175 V6_vrmpyub_rtt = 3162,
3176 V6_vrmpyub_rtt_acc = 3163,
3177 V6_vrmpyubi = 3164,
3178 V6_vrmpyubi_acc = 3165,
3179 V6_vrmpyubv = 3166,
3180 V6_vrmpyubv_acc = 3167,
3181 V6_vrmpyzbb_rt = 3168,
3182 V6_vrmpyzbb_rt_acc = 3169,
3183 V6_vrmpyzbb_rx = 3170,
3184 V6_vrmpyzbb_rx_acc = 3171,
3185 V6_vrmpyzbub_rt = 3172,
3186 V6_vrmpyzbub_rt_acc = 3173,
3187 V6_vrmpyzbub_rx = 3174,
3188 V6_vrmpyzbub_rx_acc = 3175,
3189 V6_vrmpyzcb_rt = 3176,
3190 V6_vrmpyzcb_rt_acc = 3177,
3191 V6_vrmpyzcb_rx = 3178,
3192 V6_vrmpyzcb_rx_acc = 3179,
3193 V6_vrmpyzcbs_rt = 3180,
3194 V6_vrmpyzcbs_rt_acc = 3181,
3195 V6_vrmpyzcbs_rx = 3182,
3196 V6_vrmpyzcbs_rx_acc = 3183,
3197 V6_vrmpyznb_rt = 3184,
3198 V6_vrmpyznb_rt_acc = 3185,
3199 V6_vrmpyznb_rx = 3186,
3200 V6_vrmpyznb_rx_acc = 3187,
3201 V6_vror = 3188,
3202 V6_vrotr = 3189,
3203 V6_vroundhb = 3190,
3204 V6_vroundhub = 3191,
3205 V6_vrounduhub = 3192,
3206 V6_vrounduwuh = 3193,
3207 V6_vroundwh = 3194,
3208 V6_vroundwuh = 3195,
3209 V6_vrsadubi = 3196,
3210 V6_vrsadubi_acc = 3197,
3211 V6_vsatdw = 3198,
3212 V6_vsathub = 3199,
3213 V6_vsatuwuh = 3200,
3214 V6_vsatwh = 3201,
3215 V6_vsb = 3202,
3216 V6_vscattermh = 3203,
3217 V6_vscattermh_add = 3204,
3218 V6_vscattermhq = 3205,
3219 V6_vscattermhw = 3206,
3220 V6_vscattermhw_add = 3207,
3221 V6_vscattermhwq = 3208,
3222 V6_vscattermw = 3209,
3223 V6_vscattermw_add = 3210,
3224 V6_vscattermwq = 3211,
3225 V6_vsh = 3212,
3226 V6_vshufeh = 3213,
3227 V6_vshuff = 3214,
3228 V6_vshuffb = 3215,
3229 V6_vshuffeb = 3216,
3230 V6_vshuffh = 3217,
3231 V6_vshuffob = 3218,
3232 V6_vshuffvdd = 3219,
3233 V6_vshufoeb = 3220,
3234 V6_vshufoeh = 3221,
3235 V6_vshufoh = 3222,
3236 V6_vsub_hf = 3223,
3237 V6_vsub_hf_f8 = 3224,
3238 V6_vsub_hf_hf = 3225,
3239 V6_vsub_qf16 = 3226,
3240 V6_vsub_qf16_mix = 3227,
3241 V6_vsub_qf32 = 3228,
3242 V6_vsub_qf32_mix = 3229,
3243 V6_vsub_sf = 3230,
3244 V6_vsub_sf_bf = 3231,
3245 V6_vsub_sf_hf = 3232,
3246 V6_vsub_sf_sf = 3233,
3247 V6_vsubb = 3234,
3248 V6_vsubb_dv = 3235,
3249 V6_vsubbnq = 3236,
3250 V6_vsubbq = 3237,
3251 V6_vsubbsat = 3238,
3252 V6_vsubbsat_dv = 3239,
3253 V6_vsubcarry = 3240,
3254 V6_vsubcarryo = 3241,
3255 V6_vsubh = 3242,
3256 V6_vsubh_dv = 3243,
3257 V6_vsubhnq = 3244,
3258 V6_vsubhq = 3245,
3259 V6_vsubhsat = 3246,
3260 V6_vsubhsat_dv = 3247,
3261 V6_vsubhw = 3248,
3262 V6_vsububh = 3249,
3263 V6_vsububsat = 3250,
3264 V6_vsububsat_dv = 3251,
3265 V6_vsubububb_sat = 3252,
3266 V6_vsubuhsat = 3253,
3267 V6_vsubuhsat_dv = 3254,
3268 V6_vsubuhw = 3255,
3269 V6_vsubuwsat = 3256,
3270 V6_vsubuwsat_dv = 3257,
3271 V6_vsubw = 3258,
3272 V6_vsubw_dv = 3259,
3273 V6_vsubwnq = 3260,
3274 V6_vsubwq = 3261,
3275 V6_vsubwsat = 3262,
3276 V6_vsubwsat_dv = 3263,
3277 V6_vswap = 3264,
3278 V6_vtmpyb = 3265,
3279 V6_vtmpyb_acc = 3266,
3280 V6_vtmpybus = 3267,
3281 V6_vtmpybus_acc = 3268,
3282 V6_vtmpyhb = 3269,
3283 V6_vtmpyhb_acc = 3270,
3284 V6_vunpackb = 3271,
3285 V6_vunpackh = 3272,
3286 V6_vunpackob = 3273,
3287 V6_vunpackoh = 3274,
3288 V6_vunpackub = 3275,
3289 V6_vunpackuh = 3276,
3290 V6_vwhist128 = 3277,
3291 V6_vwhist128m = 3278,
3292 V6_vwhist128q = 3279,
3293 V6_vwhist128qm = 3280,
3294 V6_vwhist256 = 3281,
3295 V6_vwhist256_sat = 3282,
3296 V6_vwhist256q = 3283,
3297 V6_vwhist256q_sat = 3284,
3298 V6_vxor = 3285,
3299 V6_vzb = 3286,
3300 V6_vzh = 3287,
3301 V6_zLd_ai = 3288,
3302 V6_zLd_pi = 3289,
3303 V6_zLd_ppu = 3290,
3304 V6_zLd_pred_ai = 3291,
3305 V6_zLd_pred_pi = 3292,
3306 V6_zLd_pred_ppu = 3293,
3307 V6_zextract = 3294,
3308 Y2_barrier = 3295,
3309 Y2_break = 3296,
3310 Y2_ciad = 3297,
3311 Y2_crswap0 = 3298,
3312 Y2_cswi = 3299,
3313 Y2_dccleana = 3300,
3314 Y2_dccleanidx = 3301,
3315 Y2_dccleaninva = 3302,
3316 Y2_dccleaninvidx = 3303,
3317 Y2_dcfetchbo = 3304,
3318 Y2_dcinva = 3305,
3319 Y2_dcinvidx = 3306,
3320 Y2_dckill = 3307,
3321 Y2_dctagr = 3308,
3322 Y2_dctagw = 3309,
3323 Y2_dczeroa = 3310,
3324 Y2_getimask = 3311,
3325 Y2_iassignr = 3312,
3326 Y2_iassignw = 3313,
3327 Y2_icdatar = 3314,
3328 Y2_icdataw = 3315,
3329 Y2_icinva = 3316,
3330 Y2_icinvidx = 3317,
3331 Y2_ickill = 3318,
3332 Y2_ictagr = 3319,
3333 Y2_ictagw = 3320,
3334 Y2_isync = 3321,
3335 Y2_k0lock = 3322,
3336 Y2_k0unlock = 3323,
3337 Y2_l2cleaninvidx = 3324,
3338 Y2_l2kill = 3325,
3339 Y2_resume = 3326,
3340 Y2_setimask = 3327,
3341 Y2_setprio = 3328,
3342 Y2_start = 3329,
3343 Y2_stop = 3330,
3344 Y2_swi = 3331,
3345 Y2_syncht = 3332,
3346 Y2_tfrscrr = 3333,
3347 Y2_tfrsrcr = 3334,
3348 Y2_tlblock = 3335,
3349 Y2_tlbp = 3336,
3350 Y2_tlbr = 3337,
3351 Y2_tlbunlock = 3338,
3352 Y2_tlbw = 3339,
3353 Y2_wait = 3340,
3354 Y4_crswap1 = 3341,
3355 Y4_crswap10 = 3342,
3356 Y4_l2fetch = 3343,
3357 Y4_l2tagr = 3344,
3358 Y4_l2tagw = 3345,
3359 Y4_nmi = 3346,
3360 Y4_siad = 3347,
3361 Y4_tfrscpp = 3348,
3362 Y4_tfrspcp = 3349,
3363 Y4_trace = 3350,
3364 Y5_ctlbw = 3351,
3365 Y5_l2cleanidx = 3352,
3366 Y5_l2fetch = 3353,
3367 Y5_l2gclean = 3354,
3368 Y5_l2gcleaninv = 3355,
3369 Y5_l2gunlock = 3356,
3370 Y5_l2invidx = 3357,
3371 Y5_l2locka = 3358,
3372 Y5_l2unlocka = 3359,
3373 Y5_tlbasidi = 3360,
3374 Y5_tlboc = 3361,
3375 Y6_diag = 3362,
3376 Y6_diag0 = 3363,
3377 Y6_diag1 = 3364,
3378 Y6_dmlink = 3365,
3379 Y6_dmpause = 3366,
3380 Y6_dmpoll = 3367,
3381 Y6_dmresume = 3368,
3382 Y6_dmstart = 3369,
3383 Y6_dmwait = 3370,
3384 Y6_l2gcleaninvpa = 3371,
3385 Y6_l2gcleanpa = 3372,
3386 dep_A2_addsat = 3373,
3387 dep_A2_subsat = 3374,
3388 dep_S2_packhl = 3375,
3389 invalid_decode = 3376,
3390 INSTRUCTION_LIST_END = 3377
3391 };
3392
3393} // end namespace llvm::Hexagon
3394#endif // GET_INSTRINFO_ENUM
3395
3396#ifdef GET_INSTRINFO_SCHED_ENUM
3397#undef GET_INSTRINFO_SCHED_ENUM
3398namespace llvm::Hexagon::Sched {
3399
3400 enum {
3401 NoInstrModel = 0,
3402 tc_01d44cb2 = 1,
3403 PSEUDO = 2,
3404 tc_c57d9f39 = 3,
3405 tc_1c2c7a4a = 4,
3406 tc_442395f3 = 5,
3407 tc_713b66bf = 6,
3408 tc_86173609 = 7,
3409 tc_5da50c4b = 8,
3410 tc_4a55d03c = 9,
3411 tc_d33e5eee = 10,
3412 tc_651cbe02 = 11,
3413 DUPLEX = 12,
3414 tc_ENDLOOP = 13,
3415 tc_23708a21 = 14,
3416 tc_56a124a7 = 15,
3417 tc_2f573607 = 16,
3418 tc_53c851ab = 17,
3419 tc_fedb7e19 = 18,
3420 tc_4222e6bf = 19,
3421 tc_075c8dd8 = 20,
3422 tc_9bcfb2ee = 21,
3423 tc_158aa3f7 = 22,
3424 tc_df5d53f9 = 23,
3425 tc_14ab4f41 = 24,
3426 tc_f38f92e1 = 25,
3427 tc_1981450d = 26,
3428 tc_e9170fb7 = 27,
3429 tc_40d64c94 = 28,
3430 LD_tc_ld_SLOT01 = 29,
3431 tc_38382228 = 30,
3432 tc_c21d7447 = 31,
3433 tc_7f8ae742 = 32,
3434 tc_5a4b5e58 = 33,
3435 tc_197dce51 = 34,
3436 tc_44fffc58 = 35,
3437 tc_5ceb2f9e = 36,
3438 tc_56c4f9fe = 37,
3439 tc_b4dc7630 = 38,
3440 tc_a2b365d2 = 39,
3441 tc_60e324ff = 40,
3442 tc_db5555f3 = 41,
3443 tc_c0749f3c = 42,
3444 PSEUDOM = 43,
3445 tc_3aacf4a8 = 44,
3446 tc_c4edf264 = 45,
3447 tc_c5dba46e = 46,
3448 tc_af25efd9 = 47,
3449 tc_0dfac0a7 = 48,
3450 tc_8035e91f = 49,
3451 tc_011e0e9d = 50,
3452 tc_ae5babd7 = 51,
3453 tc_5deb5e47 = 52,
3454 tc_bb831a7c = 53,
3455 tc_92240447 = 54,
3456 tc_7c31e19a = 55,
3457 tc_d03278fd = 56,
3458 tc_65cbd974 = 57,
3459 tc_934753bb = 58,
3460 ST_tc_st_SLOT01 = 59,
3461 CVI_VA = 60,
3462 tc_f175e046 = 61,
3463 tc_4942646a = 62,
3464 tc_0ec46cf9 = 63,
3465 tc_718b5c53 = 64,
3466 CVI_GATHER_PSEUDO = 65,
3467 tc_7dc63b5c = 66,
3468 tc_d45ba9cd = 67,
3469 tc_388f9897 = 68,
3470 tc_9124c04f = 69,
3471 tc_4ac61d92 = 70,
3472 tc_aee6250c = 71,
3473 tc_eed07714 = 72,
3474 tc_74a42bda = 73,
3475 tc_a9edeffa = 74,
3476 tc_838c4d7a = 75,
3477 tc_d61dfdc3 = 76,
3478 tc_8a825db2 = 77,
3479 tc_f34c1c21 = 78,
3480 tc_95a33176 = 79,
3481 tc_9f6cd987 = 80,
3482 tc_b837298f = 81,
3483 tc_8b5bd4f5 = 82,
3484 tc_84a7500d = 83,
3485 tc_7476d766 = 84,
3486 tc_49fdfd4b = 85,
3487 tc_f098b237 = 86,
3488 tc_20131976 = 87,
3489 tc_1d41f8b7 = 88,
3490 tc_a1297125 = 89,
3491 tc_112d30d6 = 90,
3492 tc_d68dca5c = 91,
3493 tc_788b1d09 = 92,
3494 tc_38e0bae9 = 93,
3495 tc_407e96f9 = 94,
3496 tc_7401744f = 95,
3497 tc_9b3c0462 = 96,
3498 tc_151bf368 = 97,
3499 tc_9c52f549 = 98,
3500 tc_55b33fda = 99,
3501 tc_6fc5dbea = 100,
3502 tc_3edca78f = 101,
3503 tc_a7a13fac = 102,
3504 tc_9783714b = 103,
3505 tc_f0e8e832 = 104,
3506 tc_65279839 = 105,
3507 tc_0a195f2c = 106,
3508 tc_01e1be3b = 107,
3509 tc_556f6577 = 108,
3510 tc_02fe1c65 = 109,
3511 tc_9e72dc89 = 110,
3512 tc_9edb7c77 = 111,
3513 tc_7f7f45f5 = 112,
3514 tc_c20701f0 = 113,
3515 tc_f7569068 = 114,
3516 tc_fae9dfa5 = 115,
3517 tc_6ae3426b = 116,
3518 tc_69bfb303 = 117,
3519 tc_362b0be2 = 118,
3520 tc_dc51281d = 119,
3521 tc_95f43c5e = 120,
3522 tc_decdde8a = 121,
3523 tc_eeda4109 = 122,
3524 tc_711c805f = 123,
3525 tc_ed03645c = 124,
3526 tc_42ff66ba = 125,
3527 tc_57a55b54 = 126,
3528 tc_f97707c1 = 127,
3529 tc_1248597c = 128,
3530 tc_9406230a = 129,
3531 tc_d57d649c = 130,
3532 tc_4abdbdc6 = 131,
3533 tc_6d861a95 = 132,
3534 tc_b9bec29e = 133,
3535 tc_45f9d1be = 134,
3536 tc_33e7e673 = 135,
3537 tc_24e109c7 = 136,
3538 tc_9e27f2f9 = 137,
3539 tc_f6e2aff9 = 138,
3540 tc_24f426ab = 139,
3541 tc_975a4e54 = 140,
3542 tc_e60def48 = 141,
3543 tc_5502c366 = 142,
3544 tc_7b9187d3 = 143,
3545 tc_f999c66e = 144,
3546 tc_1c7522a8 = 145,
3547 tc_76bb5435 = 146,
3548 tc_8a6d0d94 = 147,
3549 tc_2471c1c8 = 148,
3550 tc_64b00d8a = 149,
3551 tc_5f2afaf7 = 150,
3552 tc_ac65613f = 151,
3553 tc_a32e03e7 = 152,
3554 tc_822c3c68 = 153,
3555 tc_abfd9a6d = 154,
3556 tc_bf2ffc0f = 155,
3557 tc_ed3f8d2a = 156,
3558 tc_7c6d32e4 = 157,
3559 tc_45791fb8 = 158,
3560 tc_b7c4062a = 159,
3561 tc_5944960d = 160,
3562 tc_2c13e7f5 = 161,
3563 tc_a154b476 = 162,
3564 tc_a4e22bbd = 163,
3565 tc_503ce0f3 = 164,
3566 tc_0655b949 = 165,
3567 tc_6e20402a = 166,
3568 tc_db96aa6b = 167,
3569 tc_a7bdb22c = 168,
3570 tc_db596beb = 169,
3571 tc_a08b630b = 170,
3572 tc_1fcb8495 = 171,
3573 tc_9edefe01 = 172,
3574 tc_449acf79 = 173,
3575 tc_ce59038e = 174,
3576 tc_f529831b = 175,
3577 tc_addc37a8 = 176,
3578 tc_6f42bc60 = 177,
3579 tc_7af3a37e = 178,
3580 tc_e3d699e3 = 179,
3581 tc_ba9255a6 = 180,
3582 tc_1fe4ab69 = 181,
3583 tc_bb07f2c5 = 182,
3584 tc_8e82e8ca = 183,
3585 tc_cfa0e29b = 184,
3586 tc_0a6c20ae = 185,
3587 tc_0fac1eb8 = 186,
3588 tc_829d8a86 = 187,
3589 tc_280f7fe1 = 188,
3590 tc_887d1bb7 = 189,
3591 tc_96ef76ef = 190,
3592 tc_55a9a350 = 191,
3593 tc_f0cdeccf = 192,
3594 tc_a38c45dc = 193,
3595 tc_d3632d88 = 194,
3596 tc_5e4cf0e8 = 195,
3597 tc_ef921005 = 196,
3598 tc_5b347363 = 197,
3599 tc_3d14a17b = 198,
3600 tc_3fbf1042 = 199,
3601 tc_63567288 = 200,
3602 tc_59a7822c = 201,
3603 tc_937dd41c = 202,
3604 tc_a4ee89db = 203,
3605 tc_c818ff7f = 204,
3606 tc_1242dc2a = 205,
3607 tc_44d5a428 = 206,
3608 tc_540c3da3 = 207,
3609 tc_b091f1c6 = 208,
3610 tc_5bf8afbb = 209,
3611 tc_2b4c548e = 210,
3612 tc_bb599486 = 211,
3613 tc_a7e6707d = 212,
3614 tc_3c56e5ce = 213,
3615 tc_abe8c3b2 = 214,
3616 tc_453fe68d = 215,
3617 tc_1ba8a0cd = 216,
3618 tc_52447ecc = 217,
3619 tc_3904b926 = 218,
3620 tc_b9db8205 = 219,
3621 tc_663c80a7 = 220,
3622 tc_f21e8abb = 221,
3623 tc_131f1c81 = 222,
3624 tc_c7039829 = 223,
3625 tc_e2d2e9e5 = 224,
3626 tc_ab23f776 = 225,
3627 tc_7177e272 = 226,
3628 tc_e99d4c2e = 227,
3629 tc_6942b6e0 = 228,
3630 tc_a02a10a8 = 229,
3631 tc_54a0dc47 = 230,
3632 tc_447d9895 = 231,
3633 tc_191381c1 = 232,
3634 tc_3e2aaafc = 233,
3635 tc_3ce09744 = 234,
3636 tc_20a4bbec = 235,
3637 tc_5cdf8c84 = 236,
3638 tc_c127de3a = 237,
3639 tc_05ca8cfd = 238,
3640 tc_d8287c14 = 239,
3641 tc_257f6f7c = 240,
3642 tc_7e6a3e89 = 241,
3643 tc_e35c1e93 = 242,
3644 tc_08a4f1b6 = 243,
3645 tc_56e64202 = 244,
3646 tc_ac4046bc = 245,
3647 tc_2e8f5f6e = 246,
3648 tc_7417e785 = 247,
3649 tc_309dbb4f = 248,
3650 tc_df80eeb0 = 249,
3651 tc_16ff9ef8 = 250,
3652 tc_e2fdd6e6 = 251,
3653 tc_51d0ecc3 = 252,
3654 tc_531b383c = 253,
3655 tc_3c8c15d0 = 254,
3656 tc_0afc8be9 = 255,
3657 tc_561aaa58 = 256,
3658 tc_946013d8 = 257,
3659 tc_46d6c3e0 = 258,
3660 tc_87adc037 = 259,
3661 tc_a19b9305 = 260,
3662 tc_649072c2 = 261,
3663 tc_0b04c6c7 = 262,
3664 tc_660769f1 = 263,
3665 tc_dcca380f = 264,
3666 tc_72e2b393 = 265,
3667 tc_73efe966 = 266,
3668 tc_cda936da = 267,
3669 tc_a28f32b5 = 268,
3670 tc_7d68d5c2 = 269,
3671 tc_7095ecba = 270,
3672 tc_a69eeee1 = 271,
3673 tc_1381a97c = 272,
3674 tc_e3f68a46 = 273,
3675 tc_f1de44ef = 274,
3676 tc_9d1dc972 = 275,
3677 tc_90bcc1db = 276,
3678 tc_cd94bfe0 = 277,
3679 tc_15fdf750 = 278,
3680 tc_1ad8a370 = 279,
3681 tc_e675c45a = 280,
3682 tc_37820f4c = 281,
3683 tc_61bf7c03 = 282,
3684 tc_933f2b39 = 283,
3685 tc_26a377fe = 284,
3686 tc_2d4051cd = 285,
3687 tc_6e7fa133 = 286,
3688 tc_8772086c = 287,
3689 tc_b4416217 = 288,
3690 tc_9f363d21 = 289,
3691 tc_8e420e4d = 290,
3692 tc_7273323b = 291,
3693 tc_58d21193 = 292,
3694 tc_71646d06 = 293,
3695 tc_04da405a = 294,
3696 tc_2c745bb8 = 295,
3697 tc_b28e51aa = 296,
3698 tc_767c4e9d = 297,
3699 tc_e699ae41 = 298,
3700 tc_a0dbea28 = 299,
3701 tc_dd5b0695 = 300,
3702 tc_3ad719fb = 301,
3703 tc_77f94a5e = 302,
3704 tc_55255f2b = 303,
3705 tc_0a43be35 = 304,
3706 tc_b1ae5f67 = 305,
3707 tc_d234b61a = 306,
3708 tc_2237d952 = 307,
3709 tc_78f87ed3 = 308,
3710 tc_a724463d = 309,
3711 tc_6fb52018 = 310,
3712 tc_46c18ecf = 311,
3713 tc_9b20a062 = 312,
3714 tc_5a222e89 = 313,
3715 tc_0ba0d5da = 314,
3716 tc_7d6a2568 = 315,
3717 tc_759e57be = 316,
3718 tc_139ef484 = 317,
3719 tc_9b34f5e0 = 318,
3720 tc_7f58404a = 319,
3721 tc_b3d46584 = 320,
3722 tc_d71ea8fa = 321,
3723 tc_6aa823ab = 322,
3724 tc_b2196a3f = 323,
3725 tc_2c3e17fc = 324,
3726 tc_27106296 = 325,
3727 tc_a3070909 = 326,
3728 tc_512b1653 = 327,
3729 tc_d7718fbe = 328,
3730 tc_bb78483e = 329,
3731 tc_54f0cee2 = 330,
3732 tc_28e55c6f = 331,
3733 tc_4bf903b0 = 332,
3734 tc_7c28bd7e = 333,
3735 tc_invalid = 334,
3736 SCHED_LIST_END = 335
3737 };
3738} // end namespace llvm::Hexagon::Sched
3739#endif // GET_INSTRINFO_SCHED_ENUM
3740
3741#if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
3742namespace llvm {
3743
3744struct HexagonInstrTable {
3745 MCInstrDesc Insts[3377];
3746 static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo");
3747 MCOperandInfo OperandInfo[1079];
3748 static_assert(alignof(MCOperandInfo) >= alignof(MCPhysReg), "Unwanted padding between OperandInfo and ImplicitOps");
3749 MCPhysReg ImplicitOps[177];
3750};
3751
3752} // end namespace llvm
3753#endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
3754
3755#ifdef GET_INSTRINFO_MC_DESC
3756#undef GET_INSTRINFO_MC_DESC
3757namespace llvm {
3758
3759static_assert(sizeof(MCOperandInfo) % sizeof(MCPhysReg) == 0);
3760static constexpr unsigned HexagonImpOpBase = sizeof HexagonInstrTable::OperandInfo / (sizeof(MCPhysReg));
3761
3762extern const HexagonInstrTable HexagonDescs = {
3763 {
3764 { 3376, 0, 0, 4, 334, 0, 0, 1, HexagonImpOpBase + 0, 0, 0x0ULL }, // Inst #3376 = invalid_decode
3765 { 3375, 3, 1, 4, 8, 0, 0, 519, HexagonImpOpBase + 0, 0, 0x3ULL }, // Inst #3375 = dep_S2_packhl
3766 { 3374, 3, 1, 4, 77, 0, 1, 202, HexagonImpOpBase + 63, 0, 0x80000000008003ULL }, // Inst #3374 = dep_A2_subsat
3767 { 3373, 3, 1, 4, 77, 0, 1, 202, HexagonImpOpBase + 63, 0, 0x80000000008003ULL }, // Inst #3373 = dep_A2_addsat
3768 { 3372, 1, 0, 4, 333, 0, 0, 1078, HexagonImpOpBase + 0, 0, 0xa9ULL }, // Inst #3372 = Y6_l2gcleanpa
3769 { 3371, 1, 0, 4, 333, 0, 0, 1078, HexagonImpOpBase + 0, 0, 0xa9ULL }, // Inst #3371 = Y6_l2gcleaninvpa
3770 { 3370, 1, 1, 4, 332, 0, 0, 272, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x80a9ULL }, // Inst #3370 = Y6_dmwait
3771 { 3369, 1, 0, 4, 167, 0, 0, 272, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0xa9ULL }, // Inst #3369 = Y6_dmstart
3772 { 3368, 1, 0, 4, 167, 0, 0, 272, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0xa9ULL }, // Inst #3368 = Y6_dmresume
3773 { 3367, 1, 1, 4, 332, 0, 0, 272, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x80a9ULL }, // Inst #3367 = Y6_dmpoll
3774 { 3366, 1, 1, 4, 332, 0, 0, 272, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x80a9ULL }, // Inst #3366 = Y6_dmpause
3775 { 3365, 2, 0, 4, 178, 0, 0, 157, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0xa9ULL }, // Inst #3365 = Y6_dmlink
3776 { 3364, 2, 0, 4, 331, 0, 0, 162, HexagonImpOpBase + 0, 0, 0x5ULL }, // Inst #3364 = Y6_diag1
3777 { 3363, 2, 0, 4, 331, 0, 0, 162, HexagonImpOpBase + 0, 0, 0x5ULL }, // Inst #3363 = Y6_diag0
3778 { 3362, 1, 0, 4, 324, 0, 0, 272, HexagonImpOpBase + 0, 0, 0x5ULL }, // Inst #3362 = Y6_diag
3779 { 3361, 2, 1, 4, 322, 0, 0, 307, HexagonImpOpBase + 0, 0, 0x8085ULL }, // Inst #3361 = Y5_tlboc
3780 { 3360, 1, 0, 4, 330, 0, 0, 272, HexagonImpOpBase + 0, 0, 0x85ULL }, // Inst #3360 = Y5_tlbasidi
3781 { 3359, 1, 0, 4, 306, 0, 0, 272, HexagonImpOpBase + 0, 0, 0x129ULL }, // Inst #3359 = Y5_l2unlocka
3782 { 3358, 2, 1, 4, 309, 0, 0, 185, HexagonImpOpBase + 0, 0, 0x2129ULL }, // Inst #3358 = Y5_l2locka
3783 { 3357, 1, 0, 4, 306, 0, 0, 272, HexagonImpOpBase + 0, 0, 0x129ULL }, // Inst #3357 = Y5_l2invidx
3784 { 3356, 0, 0, 4, 320, 0, 0, 1, HexagonImpOpBase + 0, 0, 0xa9ULL }, // Inst #3356 = Y5_l2gunlock
3785 { 3355, 0, 0, 4, 320, 0, 0, 1, HexagonImpOpBase + 0, 0, 0xa9ULL }, // Inst #3355 = Y5_l2gcleaninv
3786 { 3354, 0, 0, 4, 320, 0, 0, 1, HexagonImpOpBase + 0, 0, 0xa9ULL }, // Inst #3354 = Y5_l2gclean
3787 { 3353, 2, 0, 4, 326, 0, 0, 307, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x129ULL }, // Inst #3353 = Y5_l2fetch
3788 { 3352, 1, 0, 4, 306, 0, 0, 272, HexagonImpOpBase + 0, 0, 0x129ULL }, // Inst #3352 = Y5_l2cleanidx
3789 { 3351, 3, 1, 4, 329, 0, 0, 212, HexagonImpOpBase + 0, 0, 0x8085ULL }, // Inst #3351 = Y5_ctlbw
3790 { 3350, 1, 0, 4, 328, 0, 0, 272, HexagonImpOpBase + 0, 0, 0x105ULL }, // Inst #3350 = Y4_trace
3791 { 3349, 2, 1, 4, 116, 0, 0, 1076, HexagonImpOpBase + 0, 0, 0x8005ULL }, // Inst #3349 = Y4_tfrspcp
3792 { 3348, 2, 1, 4, 115, 0, 0, 1074, HexagonImpOpBase + 0, 0, 0x5ULL }, // Inst #3348 = Y4_tfrscpp
3793 { 3347, 1, 0, 4, 304, 0, 0, 272, HexagonImpOpBase + 0, 0, 0x105ULL }, // Inst #3347 = Y4_siad
3794 { 3346, 1, 0, 4, 304, 0, 0, 272, HexagonImpOpBase + 0, 0, 0x85ULL }, // Inst #3346 = Y4_nmi
3795 { 3345, 2, 0, 4, 327, 0, 0, 157, HexagonImpOpBase + 0, 0, 0xa9ULL }, // Inst #3345 = Y4_l2tagw
3796 { 3344, 2, 1, 4, 309, 0, 0, 157, HexagonImpOpBase + 0, 0, 0x8129ULL }, // Inst #3344 = Y4_l2tagr
3797 { 3343, 2, 0, 4, 326, 0, 0, 157, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x129ULL }, // Inst #3343 = Y4_l2fetch
3798 { 3342, 3, 1, 4, 325, 2, 2, 1071, HexagonImpOpBase + 173, 0, 0x5ULL }, // Inst #3342 = Y4_crswap10
3799 { 3341, 2, 1, 4, 66, 1, 1, 493, HexagonImpOpBase + 171, 0, 0x8005ULL }, // Inst #3341 = Y4_crswap1
3800 { 3340, 1, 0, 4, 324, 0, 0, 272, HexagonImpOpBase + 0, 0, 0x85ULL }, // Inst #3340 = Y2_wait
3801 { 3339, 2, 0, 4, 323, 0, 0, 190, HexagonImpOpBase + 0, 0, 0x85ULL }, // Inst #3339 = Y2_tlbw
3802 { 3338, 0, 0, 4, 319, 0, 0, 1, HexagonImpOpBase + 0, 0, 0x85ULL }, // Inst #3338 = Y2_tlbunlock
3803 { 3337, 2, 1, 4, 322, 0, 0, 190, HexagonImpOpBase + 0, 0, 0x85ULL }, // Inst #3337 = Y2_tlbr
3804 { 3336, 2, 1, 4, 322, 0, 0, 157, HexagonImpOpBase + 0, 0, 0x8085ULL }, // Inst #3336 = Y2_tlbp
3805 { 3335, 0, 0, 4, 319, 0, 0, 1, HexagonImpOpBase + 0, 0, 0x85ULL }, // Inst #3335 = Y2_tlblock
3806 { 3334, 2, 1, 4, 116, 0, 0, 1069, HexagonImpOpBase + 0, 0, 0x8005ULL }, // Inst #3334 = Y2_tfrsrcr
3807 { 3333, 2, 1, 4, 115, 0, 0, 1067, HexagonImpOpBase + 0, 0, 0x8005ULL }, // Inst #3333 = Y2_tfrscrr
3808 { 3332, 0, 0, 4, 302, 0, 0, 1, HexagonImpOpBase + 0, 0, 0xa9ULL }, // Inst #3332 = Y2_syncht
3809 { 3331, 1, 0, 4, 304, 0, 0, 272, HexagonImpOpBase + 0, 0, 0x105ULL }, // Inst #3331 = Y2_swi
3810 { 3330, 1, 0, 4, 304, 0, 0, 272, HexagonImpOpBase + 0, 0, 0x85ULL }, // Inst #3330 = Y2_stop
3811 { 3329, 1, 0, 4, 304, 0, 0, 272, HexagonImpOpBase + 0, 0, 0x85ULL }, // Inst #3329 = Y2_start
3812 { 3328, 2, 0, 4, 321, 0, 0, 185, HexagonImpOpBase + 0, 0, 0x5ULL }, // Inst #3328 = Y2_setprio
3813 { 3327, 2, 0, 4, 321, 0, 0, 185, HexagonImpOpBase + 0, 0, 0x105ULL }, // Inst #3327 = Y2_setimask
3814 { 3326, 1, 0, 4, 304, 0, 0, 272, HexagonImpOpBase + 0, 0, 0x85ULL }, // Inst #3326 = Y2_resume
3815 { 3325, 0, 0, 4, 320, 0, 0, 1, HexagonImpOpBase + 0, 0, 0xa9ULL }, // Inst #3325 = Y2_l2kill
3816 { 3324, 1, 0, 4, 306, 0, 0, 272, HexagonImpOpBase + 0, 0, 0x129ULL }, // Inst #3324 = Y2_l2cleaninvidx
3817 { 3323, 0, 0, 4, 319, 0, 0, 1, HexagonImpOpBase + 0, 0, 0x85ULL }, // Inst #3323 = Y2_k0unlock
3818 { 3322, 0, 0, 4, 319, 0, 0, 1, HexagonImpOpBase + 0, 0, 0x85ULL }, // Inst #3322 = Y2_k0lock
3819 { 3321, 0, 0, 4, 318, 0, 0, 1, HexagonImpOpBase + 0, 0, 0xa3ULL }, // Inst #3321 = Y2_isync
3820 { 3320, 2, 0, 4, 317, 0, 0, 157, HexagonImpOpBase + 0, 0, 0xa3ULL }, // Inst #3320 = Y2_ictagw
3821 { 3319, 2, 1, 4, 316, 0, 0, 157, HexagonImpOpBase + 0, 0, 0x80a3ULL }, // Inst #3319 = Y2_ictagr
3822 { 3318, 0, 0, 4, 133, 0, 0, 1, HexagonImpOpBase + 0, 0, 0xa3ULL }, // Inst #3318 = Y2_ickill
3823 { 3317, 1, 0, 4, 315, 0, 0, 272, HexagonImpOpBase + 0, 0, 0xa3ULL }, // Inst #3317 = Y2_icinvidx
3824 { 3316, 1, 0, 4, 314, 0, 0, 272, HexagonImpOpBase + 0, 0, 0xa3ULL }, // Inst #3316 = Y2_icinva
3825 { 3315, 2, 0, 4, 313, 0, 0, 157, HexagonImpOpBase + 0, 0, 0xa3ULL }, // Inst #3315 = Y2_icdataw
3826 { 3314, 2, 1, 4, 312, 0, 0, 157, HexagonImpOpBase + 0, 0, 0x80a3ULL }, // Inst #3314 = Y2_icdatar
3827 { 3313, 1, 0, 4, 304, 0, 0, 272, HexagonImpOpBase + 0, 0, 0x105ULL }, // Inst #3313 = Y2_iassignw
3828 { 3312, 2, 1, 4, 311, 0, 0, 157, HexagonImpOpBase + 0, 0, 0x8105ULL }, // Inst #3312 = Y2_iassignr
3829 { 3311, 2, 1, 4, 311, 0, 0, 157, HexagonImpOpBase + 0, 0, 0x8105ULL }, // Inst #3311 = Y2_getimask
3830 { 3310, 1, 0, 4, 305, 0, 0, 272, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x229ULL }, // Inst #3310 = Y2_dczeroa
3831 { 3309, 2, 0, 4, 310, 0, 0, 157, HexagonImpOpBase + 0, 0, 0xa9ULL }, // Inst #3309 = Y2_dctagw
3832 { 3308, 2, 1, 4, 309, 0, 0, 157, HexagonImpOpBase + 0, 0, 0x8129ULL }, // Inst #3308 = Y2_dctagr
3833 { 3307, 0, 0, 4, 308, 0, 0, 1, HexagonImpOpBase + 0, 0, 0xa9ULL }, // Inst #3307 = Y2_dckill
3834 { 3306, 1, 0, 4, 306, 0, 0, 272, HexagonImpOpBase + 0, 0, 0x129ULL }, // Inst #3306 = Y2_dcinvidx
3835 { 3305, 1, 0, 4, 305, 0, 0, 272, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x229ULL }, // Inst #3305 = Y2_dcinva
3836 { 3304, 2, 0, 4, 307, 0, 0, 155, HexagonImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x38000000024ULL }, // Inst #3304 = Y2_dcfetchbo
3837 { 3303, 1, 0, 4, 306, 0, 0, 272, HexagonImpOpBase + 0, 0, 0x129ULL }, // Inst #3303 = Y2_dccleaninvidx
3838 { 3302, 1, 0, 4, 305, 0, 0, 272, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x229ULL }, // Inst #3302 = Y2_dccleaninva
3839 { 3301, 1, 0, 4, 306, 0, 0, 272, HexagonImpOpBase + 0, 0, 0x129ULL }, // Inst #3301 = Y2_dccleanidx
3840 { 3300, 1, 0, 4, 305, 0, 0, 272, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x229ULL }, // Inst #3300 = Y2_dccleana
3841 { 3299, 1, 0, 4, 304, 0, 0, 272, HexagonImpOpBase + 0, 0, 0x105ULL }, // Inst #3299 = Y2_cswi
3842 { 3298, 2, 1, 4, 66, 1, 1, 493, HexagonImpOpBase + 169, 0, 0x8005ULL }, // Inst #3298 = Y2_crswap0
3843 { 3297, 1, 0, 4, 304, 0, 0, 272, HexagonImpOpBase + 0, 0, 0x105ULL }, // Inst #3297 = Y2_ciad
3844 { 3296, 0, 0, 4, 303, 0, 0, 1, HexagonImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x85ULL }, // Inst #3296 = Y2_break
3845 { 3295, 0, 0, 4, 302, 0, 0, 1, HexagonImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x129ULL }, // Inst #3295 = Y2_barrier
3846 { 3294, 2, 1, 4, 209, 0, 0, 289, HexagonImpOpBase + 0, 0, 0x800000000008018ULL }, // Inst #3294 = V6_zextract
3847 { 3293, 4, 1, 4, 301, 0, 0, 1063, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x80006800000041fULL }, // Inst #3293 = V6_zLd_pred_ppu
3848 { 3292, 4, 1, 4, 301, 0, 0, 1059, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x80006800000041fULL }, // Inst #3292 = V6_zLd_pred_pi
3849 { 3291, 3, 0, 4, 300, 0, 0, 175, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x80003800000041fULL }, // Inst #3291 = V6_zLd_pred_ai
3850 { 3290, 3, 1, 4, 299, 0, 0, 946, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x80006800000001fULL }, // Inst #3290 = V6_zLd_ppu
3851 { 3289, 3, 1, 4, 299, 0, 0, 507, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x80006800000001fULL }, // Inst #3289 = V6_zLd_pi
3852 { 3288, 2, 0, 4, 298, 0, 0, 155, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x80003800000001fULL }, // Inst #3288 = V6_zLd_ai
3853 { 3287, 2, 1, 4, 288, 0, 0, 465, HexagonImpOpBase + 0, 0, 0x800000000008011ULL }, // Inst #3287 = V6_vzh
3854 { 3286, 2, 1, 4, 288, 0, 0, 465, HexagonImpOpBase + 0, 0, 0x800000000008011ULL }, // Inst #3286 = V6_vzb
3855 { 3285, 3, 1, 4, 37, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x3800000000008010ULL }, // Inst #3285 = V6_vxor
3856 { 3284, 1, 0, 4, 273, 0, 0, 249, HexagonImpOpBase + 0, 0, 0x80000000000000aULL }, // Inst #3284 = V6_vwhist256q_sat
3857 { 3283, 1, 0, 4, 273, 0, 0, 249, HexagonImpOpBase + 0, 0, 0x80000000000000aULL }, // Inst #3283 = V6_vwhist256q
3858 { 3282, 0, 0, 4, 272, 0, 0, 1, HexagonImpOpBase + 0, 0, 0x80000000000000aULL }, // Inst #3282 = V6_vwhist256_sat
3859 { 3281, 0, 0, 4, 272, 0, 0, 1, HexagonImpOpBase + 0, 0, 0x80000000000000aULL }, // Inst #3281 = V6_vwhist256
3860 { 3280, 2, 0, 4, 297, 0, 0, 1057, HexagonImpOpBase + 0, 0, 0x80000000000000aULL }, // Inst #3280 = V6_vwhist128qm
3861 { 3279, 1, 0, 4, 273, 0, 0, 249, HexagonImpOpBase + 0, 0, 0x80000000000000aULL }, // Inst #3279 = V6_vwhist128q
3862 { 3278, 1, 0, 4, 296, 0, 0, 0, HexagonImpOpBase + 0, 0, 0x80000000000000aULL }, // Inst #3278 = V6_vwhist128m
3863 { 3277, 0, 0, 4, 272, 0, 0, 1, HexagonImpOpBase + 0, 0, 0x80000000000000aULL }, // Inst #3277 = V6_vwhist128
3864 { 3276, 2, 1, 4, 294, 0, 0, 465, HexagonImpOpBase + 0, 0, 0x800000000008019ULL }, // Inst #3276 = V6_vunpackuh
3865 { 3275, 2, 1, 4, 294, 0, 0, 465, HexagonImpOpBase + 0, 0, 0x800000000008019ULL }, // Inst #3275 = V6_vunpackub
3866 { 3274, 3, 1, 4, 295, 0, 0, 490, HexagonImpOpBase + 0, 0, 0x840000000008019ULL }, // Inst #3274 = V6_vunpackoh
3867 { 3273, 3, 1, 4, 295, 0, 0, 490, HexagonImpOpBase + 0, 0, 0x840000000008019ULL }, // Inst #3273 = V6_vunpackob
3868 { 3272, 2, 1, 4, 294, 0, 0, 465, HexagonImpOpBase + 0, 0, 0x800000000008019ULL }, // Inst #3272 = V6_vunpackh
3869 { 3271, 2, 1, 4, 294, 0, 0, 465, HexagonImpOpBase + 0, 0, 0x800000000008019ULL }, // Inst #3271 = V6_vunpackb
3870 { 3270, 4, 1, 4, 263, 0, 0, 402, HexagonImpOpBase + 0, 0, 0x84000000000801dULL }, // Inst #3270 = V6_vtmpyhb_acc
3871 { 3269, 3, 1, 4, 262, 0, 0, 406, HexagonImpOpBase + 0, 0, 0x80000000000801dULL }, // Inst #3269 = V6_vtmpyhb
3872 { 3268, 4, 1, 4, 263, 0, 0, 402, HexagonImpOpBase + 0, 0, 0x84000000000801dULL }, // Inst #3268 = V6_vtmpybus_acc
3873 { 3267, 3, 1, 4, 262, 0, 0, 406, HexagonImpOpBase + 0, 0, 0x80000000000801dULL }, // Inst #3267 = V6_vtmpybus
3874 { 3266, 4, 1, 4, 263, 0, 0, 402, HexagonImpOpBase + 0, 0, 0x84000000000801dULL }, // Inst #3266 = V6_vtmpyb_acc
3875 { 3265, 3, 1, 4, 262, 0, 0, 406, HexagonImpOpBase + 0, 0, 0x80000000000801dULL }, // Inst #3265 = V6_vtmpyb
3876 { 3264, 4, 1, 4, 293, 0, 0, 1053, HexagonImpOpBase + 0, 0, 0x800000000008011ULL }, // Inst #3264 = V6_vswap
3877 { 3263, 3, 1, 4, 41, 0, 0, 364, HexagonImpOpBase + 0, 0, 0x800000000008011ULL }, // Inst #3263 = V6_vsubwsat_dv
3878 { 3262, 3, 1, 4, 37, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x3800000000008010ULL }, // Inst #3262 = V6_vsubwsat
3879 { 3261, 4, 1, 4, 240, 0, 0, 367, HexagonImpOpBase + 0, 0, 0x3800000000008010ULL }, // Inst #3261 = V6_vsubwq
3880 { 3260, 4, 1, 4, 240, 0, 0, 367, HexagonImpOpBase + 0, 0, 0x3800000000008010ULL }, // Inst #3260 = V6_vsubwnq
3881 { 3259, 3, 1, 4, 41, 0, 0, 364, HexagonImpOpBase + 0, 0, 0x800000000008011ULL }, // Inst #3259 = V6_vsubw_dv
3882 { 3258, 3, 1, 4, 37, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x3800000000008010ULL }, // Inst #3258 = V6_vsubw
3883 { 3257, 3, 1, 4, 41, 0, 0, 364, HexagonImpOpBase + 0, 0, 0x800000000008011ULL }, // Inst #3257 = V6_vsubuwsat_dv
3884 { 3256, 3, 1, 4, 37, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x3800000000008010ULL }, // Inst #3256 = V6_vsubuwsat
3885 { 3255, 3, 1, 4, 239, 0, 0, 375, HexagonImpOpBase + 0, 0, 0x80000000000801dULL }, // Inst #3255 = V6_vsubuhw
3886 { 3254, 3, 1, 4, 41, 0, 0, 364, HexagonImpOpBase + 0, 0, 0x800000000008011ULL }, // Inst #3254 = V6_vsubuhsat_dv
3887 { 3253, 3, 1, 4, 37, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x3800000000008010ULL }, // Inst #3253 = V6_vsubuhsat
3888 { 3252, 3, 1, 4, 37, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x3800000000008010ULL }, // Inst #3252 = V6_vsubububb_sat
3889 { 3251, 3, 1, 4, 41, 0, 0, 364, HexagonImpOpBase + 0, 0, 0x800000000008011ULL }, // Inst #3251 = V6_vsububsat_dv
3890 { 3250, 3, 1, 4, 37, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x3800000000008010ULL }, // Inst #3250 = V6_vsububsat
3891 { 3249, 3, 1, 4, 239, 0, 0, 375, HexagonImpOpBase + 0, 0, 0x80000000000801dULL }, // Inst #3249 = V6_vsububh
3892 { 3248, 3, 1, 4, 239, 0, 0, 375, HexagonImpOpBase + 0, 0, 0x80000000000801dULL }, // Inst #3248 = V6_vsubhw
3893 { 3247, 3, 1, 4, 41, 0, 0, 364, HexagonImpOpBase + 0, 0, 0x800000000008011ULL }, // Inst #3247 = V6_vsubhsat_dv
3894 { 3246, 3, 1, 4, 37, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x3800000000008010ULL }, // Inst #3246 = V6_vsubhsat
3895 { 3245, 4, 1, 4, 240, 0, 0, 367, HexagonImpOpBase + 0, 0, 0x3800000000008010ULL }, // Inst #3245 = V6_vsubhq
3896 { 3244, 4, 1, 4, 240, 0, 0, 367, HexagonImpOpBase + 0, 0, 0x3800000000008010ULL }, // Inst #3244 = V6_vsubhnq
3897 { 3243, 3, 1, 4, 41, 0, 0, 364, HexagonImpOpBase + 0, 0, 0x800000000008011ULL }, // Inst #3243 = V6_vsubh_dv
3898 { 3242, 3, 1, 4, 37, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x3800000000008010ULL }, // Inst #3242 = V6_vsubh
3899 { 3241, 4, 2, 4, 242, 0, 0, 954, HexagonImpOpBase + 0, 0, 0x3800000000008010ULL }, // Inst #3241 = V6_vsubcarryo
3900 { 3240, 5, 2, 4, 241, 0, 0, 949, HexagonImpOpBase + 0, 0, 0x3800000000008010ULL }, // Inst #3240 = V6_vsubcarry
3901 { 3239, 3, 1, 4, 41, 0, 0, 364, HexagonImpOpBase + 0, 0, 0x800000000008011ULL }, // Inst #3239 = V6_vsubbsat_dv
3902 { 3238, 3, 1, 4, 37, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x3800000000008010ULL }, // Inst #3238 = V6_vsubbsat
3903 { 3237, 4, 1, 4, 240, 0, 0, 367, HexagonImpOpBase + 0, 0, 0x3800000000008010ULL }, // Inst #3237 = V6_vsubbq
3904 { 3236, 4, 1, 4, 240, 0, 0, 367, HexagonImpOpBase + 0, 0, 0x3800000000008010ULL }, // Inst #3236 = V6_vsubbnq
3905 { 3235, 3, 1, 4, 41, 0, 0, 364, HexagonImpOpBase + 0, 0, 0x800000000008011ULL }, // Inst #3235 = V6_vsubb_dv
3906 { 3234, 3, 1, 4, 37, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x3800000000008010ULL }, // Inst #3234 = V6_vsubb
3907 { 3233, 3, 1, 4, 237, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x80000000000801cULL }, // Inst #3233 = V6_vsub_sf_sf
3908 { 3232, 3, 1, 4, 239, 0, 0, 375, HexagonImpOpBase + 0, 0, 0x80000000000801dULL }, // Inst #3232 = V6_vsub_sf_hf
3909 { 3231, 3, 1, 4, 239, 0, 0, 375, HexagonImpOpBase + 0, 0, 0x80000000000801dULL }, // Inst #3231 = V6_vsub_sf_bf
3910 { 3230, 3, 1, 4, 238, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x80000000000801aULL }, // Inst #3230 = V6_vsub_sf
3911 { 3229, 3, 1, 4, 238, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x80000000000801aULL }, // Inst #3229 = V6_vsub_qf32_mix
3912 { 3228, 3, 1, 4, 238, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x80000000000801aULL }, // Inst #3228 = V6_vsub_qf32
3913 { 3227, 3, 1, 4, 238, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x80000000000801aULL }, // Inst #3227 = V6_vsub_qf16_mix
3914 { 3226, 3, 1, 4, 238, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x80000000000801aULL }, // Inst #3226 = V6_vsub_qf16
3915 { 3225, 3, 1, 4, 237, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x80000000000801cULL }, // Inst #3225 = V6_vsub_hf_hf
3916 { 3224, 3, 1, 4, 239, 0, 0, 375, HexagonImpOpBase + 0, 0, 0x80000000000801dULL }, // Inst #3224 = V6_vsub_hf_f8
3917 { 3223, 3, 1, 4, 238, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x80000000000801aULL }, // Inst #3223 = V6_vsub_hf
3918 { 3222, 3, 1, 4, 37, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x3800000000008010ULL }, // Inst #3222 = V6_vshufoh
3919 { 3221, 3, 1, 4, 41, 0, 0, 375, HexagonImpOpBase + 0, 0, 0x800000000008011ULL }, // Inst #3221 = V6_vshufoeh
3920 { 3220, 3, 1, 4, 41, 0, 0, 375, HexagonImpOpBase + 0, 0, 0x800000000008011ULL }, // Inst #3220 = V6_vshufoeb
3921 { 3219, 4, 1, 4, 259, 0, 0, 983, HexagonImpOpBase + 0, 0, 0x800000000008019ULL }, // Inst #3219 = V6_vshuffvdd
3922 { 3218, 3, 1, 4, 37, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x3800000000008010ULL }, // Inst #3218 = V6_vshuffob
3923 { 3217, 2, 1, 4, 257, 0, 0, 359, HexagonImpOpBase + 0, 0, 0x800000000008018ULL }, // Inst #3217 = V6_vshuffh
3924 { 3216, 3, 1, 4, 37, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x3800000000008010ULL }, // Inst #3216 = V6_vshuffeb
3925 { 3215, 2, 1, 4, 257, 0, 0, 359, HexagonImpOpBase + 0, 0, 0x800000000008018ULL }, // Inst #3215 = V6_vshuffb
3926 { 3214, 5, 2, 4, 256, 0, 0, 485, HexagonImpOpBase + 0, 0, 0x80c000000008019ULL }, // Inst #3214 = V6_vshuff
3927 { 3213, 3, 1, 4, 37, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x3800000000008010ULL }, // Inst #3213 = V6_vshufeh
3928 { 3212, 2, 1, 4, 288, 0, 0, 465, HexagonImpOpBase + 0, 0, 0x800000000008011ULL }, // Inst #3212 = V6_vsh
3929 { 3211, 5, 0, 4, 290, 0, 0, 471, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x380018000000000bULL }, // Inst #3211 = V6_vscattermwq
3930 { 3210, 4, 0, 4, 289, 0, 0, 467, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x384018000000000bULL }, // Inst #3210 = V6_vscattermw_add
3931 { 3209, 4, 0, 4, 289, 0, 0, 467, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x380018000000000bULL }, // Inst #3209 = V6_vscattermw
3932 { 3208, 5, 0, 4, 292, 0, 0, 480, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x80010000000000cULL }, // Inst #3208 = V6_vscattermhwq
3933 { 3207, 4, 0, 4, 291, 0, 0, 476, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x84010000000000cULL }, // Inst #3207 = V6_vscattermhw_add
3934 { 3206, 4, 0, 4, 291, 0, 0, 476, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x80010000000000cULL }, // Inst #3206 = V6_vscattermhw
3935 { 3205, 5, 0, 4, 290, 0, 0, 471, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x380010000000000bULL }, // Inst #3205 = V6_vscattermhq
3936 { 3204, 4, 0, 4, 289, 0, 0, 467, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x384010000000000bULL }, // Inst #3204 = V6_vscattermh_add
3937 { 3203, 4, 0, 4, 289, 0, 0, 467, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x380010000000000bULL }, // Inst #3203 = V6_vscattermh
3938 { 3202, 2, 1, 4, 288, 0, 0, 465, HexagonImpOpBase + 0, 0, 0x800000000008011ULL }, // Inst #3202 = V6_vsb
3939 { 3201, 3, 1, 4, 287, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x3800000000008010ULL }, // Inst #3201 = V6_vsatwh
3940 { 3200, 3, 1, 4, 37, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x3800000000008010ULL }, // Inst #3200 = V6_vsatuwuh
3941 { 3199, 3, 1, 4, 287, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x3800000000008010ULL }, // Inst #3199 = V6_vsathub
3942 { 3198, 3, 1, 4, 37, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x3800000000008010ULL }, // Inst #3198 = V6_vsatdw
3943 { 3197, 5, 1, 4, 280, 0, 0, 456, HexagonImpOpBase + 0, 0, 0x84000000000801dULL }, // Inst #3197 = V6_vrsadubi_acc
3944 { 3196, 4, 1, 4, 279, 0, 0, 461, HexagonImpOpBase + 0, 0, 0x80000000000801dULL }, // Inst #3196 = V6_vrsadubi
3945 { 3195, 3, 1, 4, 238, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x80000000000801aULL }, // Inst #3195 = V6_vroundwuh
3946 { 3194, 3, 1, 4, 238, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x80000000000801aULL }, // Inst #3194 = V6_vroundwh
3947 { 3193, 3, 1, 4, 238, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x80000000000801aULL }, // Inst #3193 = V6_vrounduwuh
3948 { 3192, 3, 1, 4, 238, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x80000000000801aULL }, // Inst #3192 = V6_vrounduhub
3949 { 3191, 3, 1, 4, 238, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x80000000000801aULL }, // Inst #3191 = V6_vroundhub
3950 { 3190, 3, 1, 4, 238, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x80000000000801aULL }, // Inst #3190 = V6_vroundhb
3951 { 3189, 3, 1, 4, 238, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x80000000000801aULL }, // Inst #3189 = V6_vrotr
3952 { 3188, 3, 1, 4, 286, 0, 0, 396, HexagonImpOpBase + 0, 0, 0x800000000008018ULL }, // Inst #3188 = V6_vror
3953 { 3187, 5, 2, 4, 285, 0, 0, 1048, HexagonImpOpBase + 0, 0, 0x840000000008006ULL }, // Inst #3187 = V6_vrmpyznb_rx_acc
3954 { 3186, 4, 2, 4, 284, 0, 0, 1044, HexagonImpOpBase + 0, 0, 0x800000000008006ULL }, // Inst #3186 = V6_vrmpyznb_rx
3955 { 3185, 4, 1, 4, 283, 0, 0, 1040, HexagonImpOpBase + 0, 0, 0x840000000008006ULL }, // Inst #3185 = V6_vrmpyznb_rt_acc
3956 { 3184, 3, 1, 4, 282, 0, 0, 1037, HexagonImpOpBase + 0, 0, 0x800000000008006ULL }, // Inst #3184 = V6_vrmpyznb_rt
3957 { 3183, 5, 2, 4, 285, 0, 0, 1048, HexagonImpOpBase + 0, 0, 0x840000000008006ULL }, // Inst #3183 = V6_vrmpyzcbs_rx_acc
3958 { 3182, 4, 2, 4, 284, 0, 0, 1044, HexagonImpOpBase + 0, 0, 0x800000000008006ULL }, // Inst #3182 = V6_vrmpyzcbs_rx
3959 { 3181, 4, 1, 4, 283, 0, 0, 1040, HexagonImpOpBase + 0, 0, 0x840000000008006ULL }, // Inst #3181 = V6_vrmpyzcbs_rt_acc
3960 { 3180, 3, 1, 4, 282, 0, 0, 1037, HexagonImpOpBase + 0, 0, 0x800000000008006ULL }, // Inst #3180 = V6_vrmpyzcbs_rt
3961 { 3179, 5, 2, 4, 285, 0, 0, 1048, HexagonImpOpBase + 0, 0, 0x840000000008006ULL }, // Inst #3179 = V6_vrmpyzcb_rx_acc
3962 { 3178, 4, 2, 4, 284, 0, 0, 1044, HexagonImpOpBase + 0, 0, 0x800000000008006ULL }, // Inst #3178 = V6_vrmpyzcb_rx
3963 { 3177, 4, 1, 4, 283, 0, 0, 1040, HexagonImpOpBase + 0, 0, 0x840000000008006ULL }, // Inst #3177 = V6_vrmpyzcb_rt_acc
3964 { 3176, 3, 1, 4, 282, 0, 0, 1037, HexagonImpOpBase + 0, 0, 0x800000000008006ULL }, // Inst #3176 = V6_vrmpyzcb_rt
3965 { 3175, 5, 2, 4, 285, 0, 0, 1048, HexagonImpOpBase + 0, 0, 0x840000000008006ULL }, // Inst #3175 = V6_vrmpyzbub_rx_acc
3966 { 3174, 4, 2, 4, 284, 0, 0, 1044, HexagonImpOpBase + 0, 0, 0x800000000008006ULL }, // Inst #3174 = V6_vrmpyzbub_rx
3967 { 3173, 4, 1, 4, 283, 0, 0, 1040, HexagonImpOpBase + 0, 0, 0x840000000008006ULL }, // Inst #3173 = V6_vrmpyzbub_rt_acc
3968 { 3172, 3, 1, 4, 282, 0, 0, 1037, HexagonImpOpBase + 0, 0, 0x800000000008006ULL }, // Inst #3172 = V6_vrmpyzbub_rt
3969 { 3171, 5, 2, 4, 285, 0, 0, 1048, HexagonImpOpBase + 0, 0, 0x840000000008006ULL }, // Inst #3171 = V6_vrmpyzbb_rx_acc
3970 { 3170, 4, 2, 4, 284, 0, 0, 1044, HexagonImpOpBase + 0, 0, 0x800000000008006ULL }, // Inst #3170 = V6_vrmpyzbb_rx
3971 { 3169, 4, 1, 4, 283, 0, 0, 1040, HexagonImpOpBase + 0, 0, 0x840000000008006ULL }, // Inst #3169 = V6_vrmpyzbb_rt_acc
3972 { 3168, 3, 1, 4, 282, 0, 0, 1037, HexagonImpOpBase + 0, 0, 0x800000000008006ULL }, // Inst #3168 = V6_vrmpyzbb_rt
3973 { 3167, 4, 1, 4, 281, 0, 0, 416, HexagonImpOpBase + 0, 0, 0x84000000000801cULL }, // Inst #3167 = V6_vrmpyubv_acc
3974 { 3166, 3, 1, 4, 237, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x80000000000801cULL }, // Inst #3166 = V6_vrmpyubv
3975 { 3165, 5, 1, 4, 280, 0, 0, 456, HexagonImpOpBase + 0, 0, 0x84000000000801dULL }, // Inst #3165 = V6_vrmpyubi_acc
3976 { 3164, 4, 1, 4, 279, 0, 0, 461, HexagonImpOpBase + 0, 0, 0x80000000000801dULL }, // Inst #3164 = V6_vrmpyubi
3977 { 3163, 4, 1, 4, 278, 0, 0, 449, HexagonImpOpBase + 0, 0, 0x84000000000801bULL }, // Inst #3163 = V6_vrmpyub_rtt_acc
3978 { 3162, 3, 1, 4, 277, 0, 0, 453, HexagonImpOpBase + 0, 0, 0x80000000000801bULL }, // Inst #3162 = V6_vrmpyub_rtt
3979 { 3161, 4, 1, 4, 208, 0, 0, 392, HexagonImpOpBase + 0, 0, 0x84000000000801cULL }, // Inst #3161 = V6_vrmpyub_acc
3980 { 3160, 3, 1, 4, 261, 0, 0, 396, HexagonImpOpBase + 0, 0, 0x80000000000801cULL }, // Inst #3160 = V6_vrmpyub
3981 { 3159, 4, 1, 4, 281, 0, 0, 416, HexagonImpOpBase + 0, 0, 0x84000000000801cULL }, // Inst #3159 = V6_vrmpybv_acc
3982 { 3158, 3, 1, 4, 237, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x80000000000801cULL }, // Inst #3158 = V6_vrmpybv
3983 { 3157, 4, 1, 4, 281, 0, 0, 416, HexagonImpOpBase + 0, 0, 0x84000000000801cULL }, // Inst #3157 = V6_vrmpybusv_acc
3984 { 3156, 3, 1, 4, 237, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x80000000000801cULL }, // Inst #3156 = V6_vrmpybusv
3985 { 3155, 5, 1, 4, 280, 0, 0, 456, HexagonImpOpBase + 0, 0, 0x84000000000801dULL }, // Inst #3155 = V6_vrmpybusi_acc
3986 { 3154, 4, 1, 4, 279, 0, 0, 461, HexagonImpOpBase + 0, 0, 0x80000000000801dULL }, // Inst #3154 = V6_vrmpybusi
3987 { 3153, 4, 1, 4, 208, 0, 0, 392, HexagonImpOpBase + 0, 0, 0x84000000000801cULL }, // Inst #3153 = V6_vrmpybus_acc
3988 { 3152, 3, 1, 4, 261, 0, 0, 396, HexagonImpOpBase + 0, 0, 0x80000000000801cULL }, // Inst #3152 = V6_vrmpybus
3989 { 3151, 4, 1, 4, 278, 0, 0, 449, HexagonImpOpBase + 0, 0, 0x84000000000801bULL }, // Inst #3151 = V6_vrmpybub_rtt_acc
3990 { 3150, 3, 1, 4, 277, 0, 0, 453, HexagonImpOpBase + 0, 0, 0x80000000000801bULL }, // Inst #3150 = V6_vrmpybub_rtt
3991 { 3149, 3, 1, 4, 258, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x800000000008018ULL }, // Inst #3149 = V6_vrdelta
3992 { 3148, 2, 1, 4, 252, 0, 0, 1035, HexagonImpOpBase + 0, 0, 0x80000000000801aULL }, // Inst #3148 = V6_vprefixqw
3993 { 3147, 2, 1, 4, 252, 0, 0, 1035, HexagonImpOpBase + 0, 0, 0x80000000000801aULL }, // Inst #3147 = V6_vprefixqh
3994 { 3146, 2, 1, 4, 252, 0, 0, 1035, HexagonImpOpBase + 0, 0, 0x80000000000801aULL }, // Inst #3146 = V6_vprefixqb
3995 { 3145, 2, 1, 4, 252, 0, 0, 359, HexagonImpOpBase + 0, 0, 0x80000000000801aULL }, // Inst #3145 = V6_vpopcounth
3996 { 3144, 3, 1, 4, 258, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x800000000008018ULL }, // Inst #3144 = V6_vpackwuh_sat
3997 { 3143, 3, 1, 4, 258, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x800000000008018ULL }, // Inst #3143 = V6_vpackwh_sat
3998 { 3142, 3, 1, 4, 258, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x800000000008018ULL }, // Inst #3142 = V6_vpackoh
3999 { 3141, 3, 1, 4, 258, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x800000000008018ULL }, // Inst #3141 = V6_vpackob
4000 { 3140, 3, 1, 4, 258, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x800000000008018ULL }, // Inst #3140 = V6_vpackhub_sat
4001 { 3139, 3, 1, 4, 258, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x800000000008018ULL }, // Inst #3139 = V6_vpackhb_sat
4002 { 3138, 3, 1, 4, 258, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x800000000008018ULL }, // Inst #3138 = V6_vpackeh
4003 { 3137, 3, 1, 4, 258, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x800000000008018ULL }, // Inst #3137 = V6_vpackeb
4004 { 3136, 3, 1, 4, 37, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x3800000000008010ULL }, // Inst #3136 = V6_vor
4005 { 3135, 2, 1, 4, 63, 0, 0, 359, HexagonImpOpBase + 0, 0, 0x3800000000008010ULL }, // Inst #3135 = V6_vnot
4006 { 3134, 2, 1, 4, 252, 0, 0, 359, HexagonImpOpBase + 0, 0, 0x80000000000801aULL }, // Inst #3134 = V6_vnormamtw
4007 { 3133, 2, 1, 4, 252, 0, 0, 359, HexagonImpOpBase + 0, 0, 0x80000000000801aULL }, // Inst #3133 = V6_vnormamth
4008 { 3132, 3, 1, 4, 44, 0, 0, 980, HexagonImpOpBase + 0, 0, 0x1800000000008c10ULL }, // Inst #3132 = V6_vncmov
4009 { 3131, 4, 1, 4, 47, 0, 0, 976, HexagonImpOpBase + 0, 0, 0x800000000008c11ULL }, // Inst #3131 = V6_vnccombine
4010 { 3130, 3, 1, 4, 37, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x3800000000008010ULL }, // Inst #3130 = V6_vnavgw
4011 { 3129, 3, 1, 4, 37, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x3800000000008010ULL }, // Inst #3129 = V6_vnavgub
4012 { 3128, 3, 1, 4, 37, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x3800000000008010ULL }, // Inst #3128 = V6_vnavgh
4013 { 3127, 3, 1, 4, 37, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x3800000000008010ULL }, // Inst #3127 = V6_vnavgb
4014 { 3126, 4, 1, 4, 240, 0, 0, 954, HexagonImpOpBase + 0, 0, 0x3800000000008010ULL }, // Inst #3126 = V6_vmux
4015 { 3125, 3, 1, 4, 237, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x80000000000801cULL }, // Inst #3125 = V6_vmpyuhvs
4016 { 3124, 4, 1, 4, 243, 0, 0, 371, HexagonImpOpBase + 0, 0, 0x84000000000801dULL }, // Inst #3124 = V6_vmpyuhv_acc
4017 { 3123, 3, 1, 4, 239, 0, 0, 375, HexagonImpOpBase + 0, 0, 0x80000000000801dULL }, // Inst #3123 = V6_vmpyuhv
4018 { 3122, 4, 1, 4, 208, 0, 0, 392, HexagonImpOpBase + 0, 0, 0x84000000000801cULL }, // Inst #3122 = V6_vmpyuhe_acc
4019 { 3121, 3, 1, 4, 261, 0, 0, 396, HexagonImpOpBase + 0, 0, 0x80000000000801cULL }, // Inst #3121 = V6_vmpyuhe
4020 { 3120, 4, 1, 4, 263, 0, 0, 442, HexagonImpOpBase + 0, 0, 0x84000000000801dULL }, // Inst #3120 = V6_vmpyuh_acc
4021 { 3119, 3, 1, 4, 262, 0, 0, 446, HexagonImpOpBase + 0, 0, 0x80000000000801dULL }, // Inst #3119 = V6_vmpyuh
4022 { 3118, 4, 1, 4, 243, 0, 0, 371, HexagonImpOpBase + 0, 0, 0x84000000000801dULL }, // Inst #3118 = V6_vmpyubv_acc
4023 { 3117, 3, 1, 4, 239, 0, 0, 375, HexagonImpOpBase + 0, 0, 0x80000000000801dULL }, // Inst #3117 = V6_vmpyubv
4024 { 3116, 4, 1, 4, 263, 0, 0, 442, HexagonImpOpBase + 0, 0, 0x84000000000801dULL }, // Inst #3116 = V6_vmpyub_acc
4025 { 3115, 3, 1, 4, 262, 0, 0, 446, HexagonImpOpBase + 0, 0, 0x80000000000801dULL }, // Inst #3115 = V6_vmpyub
4026 { 3114, 4, 1, 4, 243, 0, 0, 416, HexagonImpOpBase + 0, 0, 0x84000000000801dULL }, // Inst #3114 = V6_vmpyowh_sacc
4027 { 3113, 4, 1, 4, 243, 0, 0, 416, HexagonImpOpBase + 0, 0, 0x84000000000801dULL }, // Inst #3113 = V6_vmpyowh_rnd_sacc
4028 { 3112, 3, 1, 4, 239, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x80000000000801dULL }, // Inst #3112 = V6_vmpyowh_rnd
4029 { 3111, 4, 1, 4, 243, 0, 0, 371, HexagonImpOpBase + 0, 0, 0x84000000000801dULL }, // Inst #3111 = V6_vmpyowh_64_acc
4030 { 3110, 3, 1, 4, 239, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x80000000000801dULL }, // Inst #3110 = V6_vmpyowh
4031 { 3109, 4, 1, 4, 208, 0, 0, 392, HexagonImpOpBase + 0, 0, 0x84000000000801cULL }, // Inst #3109 = V6_vmpyiwub_acc
4032 { 3108, 3, 1, 4, 261, 0, 0, 396, HexagonImpOpBase + 0, 0, 0x80000000000801cULL }, // Inst #3108 = V6_vmpyiwub
4033 { 3107, 4, 1, 4, 263, 0, 0, 392, HexagonImpOpBase + 0, 0, 0x84000000000801dULL }, // Inst #3107 = V6_vmpyiwh_acc
4034 { 3106, 3, 1, 4, 262, 0, 0, 396, HexagonImpOpBase + 0, 0, 0x80000000000801dULL }, // Inst #3106 = V6_vmpyiwh
4035 { 3105, 4, 1, 4, 208, 0, 0, 392, HexagonImpOpBase + 0, 0, 0x84000000000801cULL }, // Inst #3105 = V6_vmpyiwb_acc
4036 { 3104, 3, 1, 4, 261, 0, 0, 396, HexagonImpOpBase + 0, 0, 0x80000000000801cULL }, // Inst #3104 = V6_vmpyiwb
4037 { 3103, 3, 1, 4, 239, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x80000000000801dULL }, // Inst #3103 = V6_vmpyiowh
4038 { 3102, 4, 1, 4, 208, 0, 0, 392, HexagonImpOpBase + 0, 0, 0x84000000000801cULL }, // Inst #3102 = V6_vmpyihb_acc
4039 { 3101, 3, 1, 4, 261, 0, 0, 396, HexagonImpOpBase + 0, 0, 0x80000000000801cULL }, // Inst #3101 = V6_vmpyihb
4040 { 3100, 4, 1, 4, 243, 0, 0, 416, HexagonImpOpBase + 0, 0, 0x84000000000801dULL }, // Inst #3100 = V6_vmpyih_acc
4041 { 3099, 3, 1, 4, 239, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x80000000000801dULL }, // Inst #3099 = V6_vmpyih
4042 { 3098, 4, 1, 4, 243, 0, 0, 416, HexagonImpOpBase + 0, 0, 0x84000000000801dULL }, // Inst #3098 = V6_vmpyiewuh_acc
4043 { 3097, 3, 1, 4, 239, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x80000000000801dULL }, // Inst #3097 = V6_vmpyiewuh
4044 { 3096, 4, 1, 4, 243, 0, 0, 416, HexagonImpOpBase + 0, 0, 0x84000000000801dULL }, // Inst #3096 = V6_vmpyiewh_acc
4045 { 3095, 3, 1, 4, 237, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x80000000000801cULL }, // Inst #3095 = V6_vmpyieoh
4046 { 3094, 3, 1, 4, 266, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x80000000000801cULL }, // Inst #3094 = V6_vmpyhvsrs
4047 { 3093, 4, 1, 4, 243, 0, 0, 371, HexagonImpOpBase + 0, 0, 0x84000000000801dULL }, // Inst #3093 = V6_vmpyhv_acc
4048 { 3092, 3, 1, 4, 239, 0, 0, 375, HexagonImpOpBase + 0, 0, 0x80000000000801dULL }, // Inst #3092 = V6_vmpyhv
4049 { 3091, 4, 1, 4, 243, 0, 0, 371, HexagonImpOpBase + 0, 0, 0x84000000000801dULL }, // Inst #3091 = V6_vmpyhus_acc
4050 { 3090, 3, 1, 4, 239, 0, 0, 375, HexagonImpOpBase + 0, 0, 0x80000000000801dULL }, // Inst #3090 = V6_vmpyhus
4051 { 3089, 3, 1, 4, 264, 0, 0, 396, HexagonImpOpBase + 0, 0, 0x80000000000801cULL }, // Inst #3089 = V6_vmpyhss
4052 { 3088, 3, 1, 4, 264, 0, 0, 396, HexagonImpOpBase + 0, 0, 0x80000000000801cULL }, // Inst #3088 = V6_vmpyhsrs
4053 { 3087, 4, 1, 4, 263, 0, 0, 442, HexagonImpOpBase + 0, 0, 0x84000000000801dULL }, // Inst #3087 = V6_vmpyhsat_acc
4054 { 3086, 4, 1, 4, 263, 0, 0, 442, HexagonImpOpBase + 0, 0, 0x84000000000801dULL }, // Inst #3086 = V6_vmpyh_acc
4055 { 3085, 3, 1, 4, 262, 0, 0, 446, HexagonImpOpBase + 0, 0, 0x80000000000801dULL }, // Inst #3085 = V6_vmpyh
4056 { 3084, 3, 1, 4, 239, 0, 0, 375, HexagonImpOpBase + 0, 0, 0x80000000000801dULL }, // Inst #3084 = V6_vmpyewuh_64
4057 { 3083, 3, 1, 4, 239, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x80000000000801dULL }, // Inst #3083 = V6_vmpyewuh
4058 { 3082, 4, 1, 4, 243, 0, 0, 371, HexagonImpOpBase + 0, 0, 0x84000000000801dULL }, // Inst #3082 = V6_vmpybv_acc
4059 { 3081, 3, 1, 4, 239, 0, 0, 375, HexagonImpOpBase + 0, 0, 0x80000000000801dULL }, // Inst #3081 = V6_vmpybv
4060 { 3080, 4, 1, 4, 243, 0, 0, 371, HexagonImpOpBase + 0, 0, 0x84000000000801dULL }, // Inst #3080 = V6_vmpybusv_acc
4061 { 3079, 3, 1, 4, 239, 0, 0, 375, HexagonImpOpBase + 0, 0, 0x80000000000801dULL }, // Inst #3079 = V6_vmpybusv
4062 { 3078, 4, 1, 4, 263, 0, 0, 442, HexagonImpOpBase + 0, 0, 0x84000000000801dULL }, // Inst #3078 = V6_vmpybus_acc
4063 { 3077, 3, 1, 4, 262, 0, 0, 446, HexagonImpOpBase + 0, 0, 0x80000000000801dULL }, // Inst #3077 = V6_vmpybus
4064 { 3076, 3, 1, 4, 239, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x80000000000801dULL }, // Inst #3076 = V6_vmpy_sf_sf
4065 { 3075, 4, 1, 4, 243, 0, 0, 371, HexagonImpOpBase + 0, 0, 0x84000000000801dULL }, // Inst #3075 = V6_vmpy_sf_hf_acc
4066 { 3074, 3, 1, 4, 239, 0, 0, 375, HexagonImpOpBase + 0, 0, 0x80000000000801dULL }, // Inst #3074 = V6_vmpy_sf_hf
4067 { 3073, 4, 1, 4, 243, 0, 0, 371, HexagonImpOpBase + 0, 0, 0x84000000000801dULL }, // Inst #3073 = V6_vmpy_sf_bf_acc
4068 { 3072, 3, 1, 4, 239, 0, 0, 375, HexagonImpOpBase + 0, 0, 0x80000000000801dULL }, // Inst #3072 = V6_vmpy_sf_bf
4069 { 3071, 3, 1, 4, 262, 0, 0, 396, HexagonImpOpBase + 0, 0, 0x80000000000801dULL }, // Inst #3071 = V6_vmpy_rt_sf
4070 { 3070, 3, 1, 4, 262, 0, 0, 396, HexagonImpOpBase + 0, 0, 0x80000000000801dULL }, // Inst #3070 = V6_vmpy_rt_qf16
4071 { 3069, 3, 1, 4, 262, 0, 0, 396, HexagonImpOpBase + 0, 0, 0x80000000000801dULL }, // Inst #3069 = V6_vmpy_rt_hf
4072 { 3068, 3, 1, 4, 239, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x80000000000801dULL }, // Inst #3068 = V6_vmpy_qf32_sf
4073 { 3067, 3, 1, 4, 239, 0, 0, 375, HexagonImpOpBase + 0, 0, 0x80000000000801dULL }, // Inst #3067 = V6_vmpy_qf32_qf16
4074 { 3066, 3, 1, 4, 239, 0, 0, 375, HexagonImpOpBase + 0, 0, 0x80000000000801dULL }, // Inst #3066 = V6_vmpy_qf32_mix_hf
4075 { 3065, 3, 1, 4, 239, 0, 0, 375, HexagonImpOpBase + 0, 0, 0x80000000000801dULL }, // Inst #3065 = V6_vmpy_qf32_hf
4076 { 3064, 3, 1, 4, 239, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x80000000000801dULL }, // Inst #3064 = V6_vmpy_qf32
4077 { 3063, 3, 1, 4, 239, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x80000000000801dULL }, // Inst #3063 = V6_vmpy_qf16_mix_hf
4078 { 3062, 3, 1, 4, 239, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x80000000000801dULL }, // Inst #3062 = V6_vmpy_qf16_hf
4079 { 3061, 3, 1, 4, 239, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x80000000000801dULL }, // Inst #3061 = V6_vmpy_qf16
4080 { 3060, 4, 1, 4, 260, 0, 0, 416, HexagonImpOpBase + 0, 0, 0x84000000000801cULL }, // Inst #3060 = V6_vmpy_hf_hf_acc
4081 { 3059, 3, 1, 4, 237, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x80000000000801cULL }, // Inst #3059 = V6_vmpy_hf_hf
4082 { 3058, 4, 1, 4, 243, 0, 0, 371, HexagonImpOpBase + 0, 0, 0x84000000000801dULL }, // Inst #3058 = V6_vmpy_hf_f8_acc
4083 { 3057, 3, 1, 4, 239, 0, 0, 375, HexagonImpOpBase + 0, 0, 0x80000000000801dULL }, // Inst #3057 = V6_vmpy_hf_f8
4084 { 3056, 4, 1, 4, 276, 0, 0, 1031, HexagonImpOpBase + 0, 0, 0x80000000000801dULL }, // Inst #3056 = V6_vmpsuhuhsat
4085 { 3055, 4, 1, 4, 276, 0, 0, 1031, HexagonImpOpBase + 0, 0, 0x80000000000801dULL }, // Inst #3055 = V6_vmpauhuhsat
4086 { 3054, 4, 1, 4, 263, 0, 0, 402, HexagonImpOpBase + 0, 0, 0x84000000000801dULL }, // Inst #3054 = V6_vmpauhb_acc
4087 { 3053, 3, 1, 4, 262, 0, 0, 406, HexagonImpOpBase + 0, 0, 0x80000000000801dULL }, // Inst #3053 = V6_vmpauhb
4088 { 3052, 4, 1, 4, 276, 0, 0, 1031, HexagonImpOpBase + 0, 0, 0x80000000000801dULL }, // Inst #3052 = V6_vmpahhsat
4089 { 3051, 4, 1, 4, 263, 0, 0, 402, HexagonImpOpBase + 0, 0, 0x84000000000801dULL }, // Inst #3051 = V6_vmpahb_acc
4090 { 3050, 3, 1, 4, 262, 0, 0, 406, HexagonImpOpBase + 0, 0, 0x80000000000801dULL }, // Inst #3050 = V6_vmpahb
4091 { 3049, 3, 1, 4, 239, 0, 0, 364, HexagonImpOpBase + 0, 0, 0x80000000000801dULL }, // Inst #3049 = V6_vmpabuuv
4092 { 3048, 4, 1, 4, 263, 0, 0, 402, HexagonImpOpBase + 0, 0, 0x84000000000801dULL }, // Inst #3048 = V6_vmpabuu_acc
4093 { 3047, 3, 1, 4, 262, 0, 0, 406, HexagonImpOpBase + 0, 0, 0x80000000000801dULL }, // Inst #3047 = V6_vmpabuu
4094 { 3046, 3, 1, 4, 239, 0, 0, 364, HexagonImpOpBase + 0, 0, 0x80000000000801dULL }, // Inst #3046 = V6_vmpabusv
4095 { 3045, 4, 1, 4, 263, 0, 0, 402, HexagonImpOpBase + 0, 0, 0x84000000000801dULL }, // Inst #3045 = V6_vmpabus_acc
4096 { 3044, 3, 1, 4, 262, 0, 0, 406, HexagonImpOpBase + 0, 0, 0x80000000000801dULL }, // Inst #3044 = V6_vmpabus
4097 { 3043, 3, 1, 4, 37, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x3800000000008010ULL }, // Inst #3043 = V6_vminw
4098 { 3042, 3, 1, 4, 37, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x3800000000008010ULL }, // Inst #3042 = V6_vminuh
4099 { 3041, 3, 1, 4, 37, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x3800000000008010ULL }, // Inst #3041 = V6_vminub
4100 { 3040, 3, 1, 4, 37, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x3800000000008010ULL }, // Inst #3040 = V6_vminh
4101 { 3039, 3, 1, 4, 37, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x3800000000008010ULL }, // Inst #3039 = V6_vminb
4102 { 3038, 3, 1, 4, 37, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x3800000000008010ULL }, // Inst #3038 = V6_vmin_sf
4103 { 3037, 3, 1, 4, 37, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x3800000000008010ULL }, // Inst #3037 = V6_vmin_hf
4104 { 3036, 3, 1, 4, 267, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x80000000000801eULL }, // Inst #3036 = V6_vmin_bf
4105 { 3035, 3, 1, 4, 238, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x80000000000801aULL }, // Inst #3035 = V6_vmerge_qf
4106 { 3034, 3, 1, 4, 37, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x3800000000008010ULL }, // Inst #3034 = V6_vmaxw
4107 { 3033, 3, 1, 4, 37, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x3800000000008010ULL }, // Inst #3033 = V6_vmaxuh
4108 { 3032, 3, 1, 4, 37, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x3800000000008010ULL }, // Inst #3032 = V6_vmaxub
4109 { 3031, 3, 1, 4, 37, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x3800000000008010ULL }, // Inst #3031 = V6_vmaxh
4110 { 3030, 3, 1, 4, 37, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x3800000000008010ULL }, // Inst #3030 = V6_vmaxb
4111 { 3029, 3, 1, 4, 37, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x3800000000008010ULL }, // Inst #3029 = V6_vmax_sf
4112 { 3028, 3, 1, 4, 37, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x3800000000008010ULL }, // Inst #3028 = V6_vmax_hf
4113 { 3027, 3, 1, 4, 267, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x80000000000801eULL }, // Inst #3027 = V6_vmax_bf
4114 { 3026, 4, 1, 4, 259, 0, 0, 1027, HexagonImpOpBase + 0, 0, 0x800000000008019ULL }, // Inst #3026 = V6_vlutvwhi
4115 { 3025, 5, 1, 4, 275, 0, 0, 1022, HexagonImpOpBase + 0, 0, 0x840000000008019ULL }, // Inst #3025 = V6_vlutvwh_oracci
4116 { 3024, 5, 1, 4, 275, 0, 0, 1017, HexagonImpOpBase + 0, 0, 0x840000000008019ULL }, // Inst #3024 = V6_vlutvwh_oracc
4117 { 3023, 4, 1, 4, 259, 0, 0, 983, HexagonImpOpBase + 0, 0, 0x800000000008019ULL }, // Inst #3023 = V6_vlutvwh_nm
4118 { 3022, 4, 1, 4, 259, 0, 0, 983, HexagonImpOpBase + 0, 0, 0x800000000008019ULL }, // Inst #3022 = V6_vlutvwh
4119 { 3021, 4, 1, 4, 244, 0, 0, 966, HexagonImpOpBase + 0, 0, 0x800000000008018ULL }, // Inst #3021 = V6_vlutvvbi
4120 { 3020, 5, 1, 4, 275, 0, 0, 1012, HexagonImpOpBase + 0, 0, 0x840000000008019ULL }, // Inst #3020 = V6_vlutvvb_oracci
4121 { 3019, 5, 1, 4, 275, 0, 0, 1007, HexagonImpOpBase + 0, 0, 0x840000000008019ULL }, // Inst #3019 = V6_vlutvvb_oracc
4122 { 3018, 4, 1, 4, 244, 0, 0, 962, HexagonImpOpBase + 0, 0, 0x800000000008018ULL }, // Inst #3018 = V6_vlutvvb_nm
4123 { 3017, 4, 1, 4, 244, 0, 0, 962, HexagonImpOpBase + 0, 0, 0x800000000008018ULL }, // Inst #3017 = V6_vlutvvb
4124 { 3016, 3, 1, 4, 274, 0, 0, 1004, HexagonImpOpBase + 0, 0, 0x80000000000801dULL }, // Inst #3016 = V6_vlut4
4125 { 3015, 3, 1, 4, 238, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x80000000000801aULL }, // Inst #3015 = V6_vlsrwv
4126 { 3014, 3, 1, 4, 247, 0, 0, 396, HexagonImpOpBase + 0, 0, 0x80000000000801aULL }, // Inst #3014 = V6_vlsrw
4127 { 3013, 3, 1, 4, 238, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x80000000000801aULL }, // Inst #3013 = V6_vlsrhv
4128 { 3012, 3, 1, 4, 247, 0, 0, 396, HexagonImpOpBase + 0, 0, 0x80000000000801aULL }, // Inst #3012 = V6_vlsrh
4129 { 3011, 3, 1, 4, 247, 0, 0, 396, HexagonImpOpBase + 0, 0, 0x80000000000801aULL }, // Inst #3011 = V6_vlsrb
4130 { 3010, 4, 1, 4, 244, 0, 0, 966, HexagonImpOpBase + 0, 0, 0x800000000008018ULL }, // Inst #3010 = V6_vlalignbi
4131 { 3009, 4, 1, 4, 244, 0, 0, 962, HexagonImpOpBase + 0, 0, 0x800000000008018ULL }, // Inst #3009 = V6_vlalignb
4132 { 3008, 3, 1, 4, 245, 0, 0, 1001, HexagonImpOpBase + 0, 0, 0x80000000000801eULL }, // Inst #3008 = V6_vinsertwr
4133 { 3007, 1, 0, 4, 273, 0, 0, 249, HexagonImpOpBase + 0, 0, 0x80000000000000aULL }, // Inst #3007 = V6_vhistq
4134 { 3006, 0, 0, 4, 272, 0, 0, 1, HexagonImpOpBase + 0, 0, 0x80000000000000aULL }, // Inst #3006 = V6_vhist
4135 { 3005, 4, 1, 4, 240, 0, 0, 326, HexagonImpOpBase + 0, 0, 0x3800000000000010ULL }, // Inst #3005 = V6_vgtw_xor
4136 { 3004, 4, 1, 4, 240, 0, 0, 326, HexagonImpOpBase + 0, 0, 0x3840000000000010ULL }, // Inst #3004 = V6_vgtw_or
4137 { 3003, 4, 1, 4, 240, 0, 0, 326, HexagonImpOpBase + 0, 0, 0x3800000000000010ULL }, // Inst #3003 = V6_vgtw_and
4138 { 3002, 3, 1, 4, 37, 0, 0, 323, HexagonImpOpBase + 0, 0, 0x3800000000008010ULL }, // Inst #3002 = V6_vgtw
4139 { 3001, 4, 1, 4, 240, 0, 0, 326, HexagonImpOpBase + 0, 0, 0x3800000000000010ULL }, // Inst #3001 = V6_vgtuw_xor
4140 { 3000, 4, 1, 4, 240, 0, 0, 326, HexagonImpOpBase + 0, 0, 0x3840000000000010ULL }, // Inst #3000 = V6_vgtuw_or
4141 { 2999, 4, 1, 4, 240, 0, 0, 326, HexagonImpOpBase + 0, 0, 0x3800000000000010ULL }, // Inst #2999 = V6_vgtuw_and
4142 { 2998, 3, 1, 4, 37, 0, 0, 323, HexagonImpOpBase + 0, 0, 0x3800000000008010ULL }, // Inst #2998 = V6_vgtuw
4143 { 2997, 4, 1, 4, 240, 0, 0, 326, HexagonImpOpBase + 0, 0, 0x3800000000000010ULL }, // Inst #2997 = V6_vgtuh_xor
4144 { 2996, 4, 1, 4, 240, 0, 0, 326, HexagonImpOpBase + 0, 0, 0x3840000000000010ULL }, // Inst #2996 = V6_vgtuh_or
4145 { 2995, 4, 1, 4, 240, 0, 0, 326, HexagonImpOpBase + 0, 0, 0x3800000000000010ULL }, // Inst #2995 = V6_vgtuh_and
4146 { 2994, 3, 1, 4, 37, 0, 0, 323, HexagonImpOpBase + 0, 0, 0x3800000000008010ULL }, // Inst #2994 = V6_vgtuh
4147 { 2993, 4, 1, 4, 240, 0, 0, 326, HexagonImpOpBase + 0, 0, 0x3800000000000010ULL }, // Inst #2993 = V6_vgtub_xor
4148 { 2992, 4, 1, 4, 240, 0, 0, 326, HexagonImpOpBase + 0, 0, 0x3840000000000010ULL }, // Inst #2992 = V6_vgtub_or
4149 { 2991, 4, 1, 4, 240, 0, 0, 326, HexagonImpOpBase + 0, 0, 0x3800000000000010ULL }, // Inst #2991 = V6_vgtub_and
4150 { 2990, 3, 1, 4, 37, 0, 0, 323, HexagonImpOpBase + 0, 0, 0x3800000000008010ULL }, // Inst #2990 = V6_vgtub
4151 { 2989, 4, 1, 4, 240, 0, 0, 326, HexagonImpOpBase + 0, 0, 0x3800000000000010ULL }, // Inst #2989 = V6_vgtsf_xor
4152 { 2988, 4, 1, 4, 240, 0, 0, 326, HexagonImpOpBase + 0, 0, 0x3840000000000010ULL }, // Inst #2988 = V6_vgtsf_or
4153 { 2987, 4, 1, 4, 240, 0, 0, 326, HexagonImpOpBase + 0, 0, 0x3800000000000010ULL }, // Inst #2987 = V6_vgtsf_and
4154 { 2986, 3, 1, 4, 37, 0, 0, 323, HexagonImpOpBase + 0, 0, 0x3800000000008010ULL }, // Inst #2986 = V6_vgtsf
4155 { 2985, 4, 1, 4, 240, 0, 0, 326, HexagonImpOpBase + 0, 0, 0x3800000000000010ULL }, // Inst #2985 = V6_vgthf_xor
4156 { 2984, 4, 1, 4, 240, 0, 0, 326, HexagonImpOpBase + 0, 0, 0x3840000000000010ULL }, // Inst #2984 = V6_vgthf_or
4157 { 2983, 4, 1, 4, 240, 0, 0, 326, HexagonImpOpBase + 0, 0, 0x3800000000000010ULL }, // Inst #2983 = V6_vgthf_and
4158 { 2982, 3, 1, 4, 37, 0, 0, 323, HexagonImpOpBase + 0, 0, 0x3800000000008010ULL }, // Inst #2982 = V6_vgthf
4159 { 2981, 4, 1, 4, 240, 0, 0, 326, HexagonImpOpBase + 0, 0, 0x3800000000000010ULL }, // Inst #2981 = V6_vgth_xor
4160 { 2980, 4, 1, 4, 240, 0, 0, 326, HexagonImpOpBase + 0, 0, 0x3840000000000010ULL }, // Inst #2980 = V6_vgth_or
4161 { 2979, 4, 1, 4, 240, 0, 0, 326, HexagonImpOpBase + 0, 0, 0x3800000000000010ULL }, // Inst #2979 = V6_vgth_and
4162 { 2978, 3, 1, 4, 37, 0, 0, 323, HexagonImpOpBase + 0, 0, 0x3800000000008010ULL }, // Inst #2978 = V6_vgth
4163 { 2977, 4, 1, 4, 240, 0, 0, 326, HexagonImpOpBase + 0, 0, 0x3800000000000010ULL }, // Inst #2977 = V6_vgtbf_xor
4164 { 2976, 4, 1, 4, 240, 0, 0, 326, HexagonImpOpBase + 0, 0, 0x3840000000000010ULL }, // Inst #2976 = V6_vgtbf_or
4165 { 2975, 4, 1, 4, 240, 0, 0, 326, HexagonImpOpBase + 0, 0, 0x3800000000000010ULL }, // Inst #2975 = V6_vgtbf_and
4166 { 2974, 3, 1, 4, 37, 0, 0, 323, HexagonImpOpBase + 0, 0, 0x3800000000008010ULL }, // Inst #2974 = V6_vgtbf
4167 { 2973, 4, 1, 4, 240, 0, 0, 326, HexagonImpOpBase + 0, 0, 0x3800000000000010ULL }, // Inst #2973 = V6_vgtb_xor
4168 { 2972, 4, 1, 4, 240, 0, 0, 326, HexagonImpOpBase + 0, 0, 0x3840000000000010ULL }, // Inst #2972 = V6_vgtb_or
4169 { 2971, 4, 1, 4, 240, 0, 0, 326, HexagonImpOpBase + 0, 0, 0x3800000000000010ULL }, // Inst #2971 = V6_vgtb_and
4170 { 2970, 3, 1, 4, 37, 0, 0, 323, HexagonImpOpBase + 0, 0, 0x3800000000008010ULL }, // Inst #2970 = V6_vgtb
4171 { 2969, 4, 0, 4, 269, 0, 1, 990, HexagonImpOpBase + 168, 0|(1ULL<<MCID::MayLoad), 0x1800180000408007ULL }, // Inst #2969 = V6_vgathermwq
4172 { 2968, 3, 0, 4, 268, 0, 1, 987, HexagonImpOpBase + 168, 0|(1ULL<<MCID::MayLoad), 0x1800180000408007ULL }, // Inst #2968 = V6_vgathermw
4173 { 2967, 4, 0, 4, 271, 0, 1, 997, HexagonImpOpBase + 168, 0|(1ULL<<MCID::MayLoad), 0x800100000408008ULL }, // Inst #2967 = V6_vgathermhwq
4174 { 2966, 3, 0, 4, 270, 0, 1, 994, HexagonImpOpBase + 168, 0|(1ULL<<MCID::MayLoad), 0x800100000408008ULL }, // Inst #2966 = V6_vgathermhw
4175 { 2965, 4, 0, 4, 269, 0, 1, 990, HexagonImpOpBase + 168, 0|(1ULL<<MCID::MayLoad), 0x1800100000408007ULL }, // Inst #2965 = V6_vgathermhq
4176 { 2964, 3, 0, 4, 268, 0, 1, 987, HexagonImpOpBase + 168, 0|(1ULL<<MCID::MayLoad), 0x1800100000408007ULL }, // Inst #2964 = V6_vgathermh
4177 { 2963, 2, 1, 4, 236, 0, 0, 359, HexagonImpOpBase + 0, 0, 0x80000000000801eULL }, // Inst #2963 = V6_vfneg_sf
4178 { 2962, 2, 1, 4, 236, 0, 0, 359, HexagonImpOpBase + 0, 0, 0x80000000000801eULL }, // Inst #2962 = V6_vfneg_hf
4179 { 2961, 2, 1, 4, 236, 0, 0, 359, HexagonImpOpBase + 0, 0, 0x80000000000801eULL }, // Inst #2961 = V6_vfneg_f8
4180 { 2960, 3, 1, 4, 267, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x80000000000801eULL }, // Inst #2960 = V6_vfmin_sf
4181 { 2959, 3, 1, 4, 267, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x80000000000801eULL }, // Inst #2959 = V6_vfmin_hf
4182 { 2958, 3, 1, 4, 267, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x80000000000801eULL }, // Inst #2958 = V6_vfmin_f8
4183 { 2957, 3, 1, 4, 267, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x80000000000801eULL }, // Inst #2957 = V6_vfmax_sf
4184 { 2956, 3, 1, 4, 267, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x80000000000801eULL }, // Inst #2956 = V6_vfmax_hf
4185 { 2955, 3, 1, 4, 267, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x80000000000801eULL }, // Inst #2955 = V6_vfmax_f8
4186 { 2954, 4, 1, 4, 240, 0, 0, 326, HexagonImpOpBase + 0, 0, 0x3800000000000010ULL }, // Inst #2954 = V6_veqw_xor
4187 { 2953, 4, 1, 4, 240, 0, 0, 326, HexagonImpOpBase + 0, 0, 0x3840000000000010ULL }, // Inst #2953 = V6_veqw_or
4188 { 2952, 4, 1, 4, 240, 0, 0, 326, HexagonImpOpBase + 0, 0, 0x3800000000000010ULL }, // Inst #2952 = V6_veqw_and
4189 { 2951, 3, 1, 4, 37, 0, 0, 323, HexagonImpOpBase + 0, 0, 0x3800000000008010ULL }, // Inst #2951 = V6_veqw
4190 { 2950, 4, 1, 4, 240, 0, 0, 326, HexagonImpOpBase + 0, 0, 0x3800000000000010ULL }, // Inst #2950 = V6_veqh_xor
4191 { 2949, 4, 1, 4, 240, 0, 0, 326, HexagonImpOpBase + 0, 0, 0x3840000000000010ULL }, // Inst #2949 = V6_veqh_or
4192 { 2948, 4, 1, 4, 240, 0, 0, 326, HexagonImpOpBase + 0, 0, 0x3800000000000010ULL }, // Inst #2948 = V6_veqh_and
4193 { 2947, 3, 1, 4, 37, 0, 0, 323, HexagonImpOpBase + 0, 0, 0x3800000000008010ULL }, // Inst #2947 = V6_veqh
4194 { 2946, 4, 1, 4, 240, 0, 0, 326, HexagonImpOpBase + 0, 0, 0x3800000000000010ULL }, // Inst #2946 = V6_veqb_xor
4195 { 2945, 4, 1, 4, 240, 0, 0, 326, HexagonImpOpBase + 0, 0, 0x3840000000000010ULL }, // Inst #2945 = V6_veqb_or
4196 { 2944, 4, 1, 4, 240, 0, 0, 326, HexagonImpOpBase + 0, 0, 0x3800000000000010ULL }, // Inst #2944 = V6_veqb_and
4197 { 2943, 3, 1, 4, 37, 0, 0, 323, HexagonImpOpBase + 0, 0, 0x3800000000008010ULL }, // Inst #2943 = V6_veqb
4198 { 2942, 4, 1, 4, 263, 0, 0, 402, HexagonImpOpBase + 0, 0, 0x84000000000801dULL }, // Inst #2942 = V6_vdsaduh_acc
4199 { 2941, 3, 1, 4, 262, 0, 0, 406, HexagonImpOpBase + 0, 0, 0x80000000000801dULL }, // Inst #2941 = V6_vdsaduh
4200 { 2940, 4, 1, 4, 243, 0, 0, 416, HexagonImpOpBase + 0, 0, 0x84000000000801dULL }, // Inst #2940 = V6_vdmpyhvsat_acc
4201 { 2939, 3, 1, 4, 266, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x80000000000801cULL }, // Inst #2939 = V6_vdmpyhvsat
4202 { 2938, 4, 1, 4, 265, 0, 0, 392, HexagonImpOpBase + 0, 0, 0x84000000000801cULL }, // Inst #2938 = V6_vdmpyhsusat_acc
4203 { 2937, 3, 1, 4, 264, 0, 0, 396, HexagonImpOpBase + 0, 0, 0x80000000000801cULL }, // Inst #2937 = V6_vdmpyhsusat
4204 { 2936, 4, 1, 4, 263, 0, 0, 409, HexagonImpOpBase + 0, 0, 0x84000000000801dULL }, // Inst #2936 = V6_vdmpyhsuisat_acc
4205 { 2935, 3, 1, 4, 262, 0, 0, 413, HexagonImpOpBase + 0, 0, 0x80000000000801dULL }, // Inst #2935 = V6_vdmpyhsuisat
4206 { 2934, 4, 1, 4, 265, 0, 0, 392, HexagonImpOpBase + 0, 0, 0x84000000000801cULL }, // Inst #2934 = V6_vdmpyhsat_acc
4207 { 2933, 3, 1, 4, 264, 0, 0, 396, HexagonImpOpBase + 0, 0, 0x80000000000801cULL }, // Inst #2933 = V6_vdmpyhsat
4208 { 2932, 4, 1, 4, 263, 0, 0, 409, HexagonImpOpBase + 0, 0, 0x84000000000801dULL }, // Inst #2932 = V6_vdmpyhisat_acc
4209 { 2931, 3, 1, 4, 262, 0, 0, 413, HexagonImpOpBase + 0, 0, 0x80000000000801dULL }, // Inst #2931 = V6_vdmpyhisat
4210 { 2930, 4, 1, 4, 263, 0, 0, 402, HexagonImpOpBase + 0, 0, 0x84000000000801dULL }, // Inst #2930 = V6_vdmpyhb_dv_acc
4211 { 2929, 3, 1, 4, 262, 0, 0, 406, HexagonImpOpBase + 0, 0, 0x80000000000801dULL }, // Inst #2929 = V6_vdmpyhb_dv
4212 { 2928, 4, 1, 4, 208, 0, 0, 392, HexagonImpOpBase + 0, 0, 0x84000000000801cULL }, // Inst #2928 = V6_vdmpyhb_acc
4213 { 2927, 3, 1, 4, 261, 0, 0, 396, HexagonImpOpBase + 0, 0, 0x80000000000801cULL }, // Inst #2927 = V6_vdmpyhb
4214 { 2926, 4, 1, 4, 263, 0, 0, 402, HexagonImpOpBase + 0, 0, 0x84000000000801dULL }, // Inst #2926 = V6_vdmpybus_dv_acc
4215 { 2925, 3, 1, 4, 262, 0, 0, 406, HexagonImpOpBase + 0, 0, 0x80000000000801dULL }, // Inst #2925 = V6_vdmpybus_dv
4216 { 2924, 4, 1, 4, 208, 0, 0, 392, HexagonImpOpBase + 0, 0, 0x84000000000801cULL }, // Inst #2924 = V6_vdmpybus_acc
4217 { 2923, 3, 1, 4, 261, 0, 0, 396, HexagonImpOpBase + 0, 0, 0x80000000000801cULL }, // Inst #2923 = V6_vdmpybus
4218 { 2922, 4, 1, 4, 260, 0, 0, 416, HexagonImpOpBase + 0, 0, 0x84000000000801cULL }, // Inst #2922 = V6_vdmpy_sf_hf_acc
4219 { 2921, 3, 1, 4, 237, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x80000000000801cULL }, // Inst #2921 = V6_vdmpy_sf_hf
4220 { 2920, 3, 1, 4, 258, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x800000000008018ULL }, // Inst #2920 = V6_vdelta
4221 { 2919, 4, 1, 4, 259, 0, 0, 983, HexagonImpOpBase + 0, 0, 0x800000000008019ULL }, // Inst #2919 = V6_vdealvdd
4222 { 2918, 2, 1, 4, 257, 0, 0, 359, HexagonImpOpBase + 0, 0, 0x800000000008018ULL }, // Inst #2918 = V6_vdealh
4223 { 2917, 3, 1, 4, 258, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x800000000008018ULL }, // Inst #2917 = V6_vdealb4w
4224 { 2916, 2, 1, 4, 257, 0, 0, 359, HexagonImpOpBase + 0, 0, 0x800000000008018ULL }, // Inst #2916 = V6_vdealb
4225 { 2915, 5, 2, 4, 256, 0, 0, 485, HexagonImpOpBase + 0, 0, 0x80c000000008019ULL }, // Inst #2915 = V6_vdeal
4226 { 2914, 2, 1, 4, 254, 0, 0, 359, HexagonImpOpBase + 0, 0, 0x80000000000801cULL }, // Inst #2914 = V6_vcvt_uh_hf
4227 { 2913, 3, 1, 4, 237, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x80000000000801cULL }, // Inst #2913 = V6_vcvt_ub_hf
4228 { 2912, 2, 1, 4, 255, 0, 0, 465, HexagonImpOpBase + 0, 0, 0x80000000000801dULL }, // Inst #2912 = V6_vcvt_sf_hf
4229 { 2911, 2, 1, 4, 254, 0, 0, 359, HexagonImpOpBase + 0, 0, 0x80000000000801cULL }, // Inst #2911 = V6_vcvt_hf_uh
4230 { 2910, 2, 1, 4, 255, 0, 0, 465, HexagonImpOpBase + 0, 0, 0x80000000000801dULL }, // Inst #2910 = V6_vcvt_hf_ub
4231 { 2909, 3, 1, 4, 237, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x80000000000801cULL }, // Inst #2909 = V6_vcvt_hf_sf
4232 { 2908, 2, 1, 4, 254, 0, 0, 359, HexagonImpOpBase + 0, 0, 0x80000000000801cULL }, // Inst #2908 = V6_vcvt_hf_h
4233 { 2907, 2, 1, 4, 237, 0, 0, 465, HexagonImpOpBase + 0, 0, 0x80000000000801dULL }, // Inst #2907 = V6_vcvt_hf_f8
4234 { 2906, 2, 1, 4, 255, 0, 0, 465, HexagonImpOpBase + 0, 0, 0x80000000000801dULL }, // Inst #2906 = V6_vcvt_hf_b
4235 { 2905, 2, 1, 4, 254, 0, 0, 359, HexagonImpOpBase + 0, 0, 0x80000000000801cULL }, // Inst #2905 = V6_vcvt_h_hf
4236 { 2904, 3, 1, 4, 237, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x80000000000801cULL }, // Inst #2904 = V6_vcvt_f8_hf
4237 { 2903, 3, 1, 4, 237, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x80000000000801cULL }, // Inst #2903 = V6_vcvt_bf_sf
4238 { 2902, 3, 1, 4, 237, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x80000000000801cULL }, // Inst #2902 = V6_vcvt_b_hf
4239 { 2901, 3, 1, 4, 237, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x80000000000801cULL }, // Inst #2901 = V6_vcvt2_ub_hf
4240 { 2900, 2, 1, 4, 237, 0, 0, 465, HexagonImpOpBase + 0, 0, 0x80000000000801dULL }, // Inst #2900 = V6_vcvt2_hf_ub
4241 { 2899, 2, 1, 4, 237, 0, 0, 465, HexagonImpOpBase + 0, 0, 0x80000000000801dULL }, // Inst #2899 = V6_vcvt2_hf_b
4242 { 2898, 3, 1, 4, 237, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x80000000000801cULL }, // Inst #2898 = V6_vcvt2_b_hf
4243 { 2897, 2, 1, 4, 252, 0, 0, 359, HexagonImpOpBase + 0, 0, 0x80000000000801aULL }, // Inst #2897 = V6_vconv_w_sf
4244 { 2896, 2, 1, 4, 252, 0, 0, 359, HexagonImpOpBase + 0, 0, 0x80000000000801aULL }, // Inst #2896 = V6_vconv_sf_w
4245 { 2895, 2, 1, 4, 252, 0, 0, 359, HexagonImpOpBase + 0, 0, 0x80000000000801aULL }, // Inst #2895 = V6_vconv_sf_qf32
4246 { 2894, 2, 1, 4, 252, 0, 0, 337, HexagonImpOpBase + 0, 0, 0x80000000000801aULL }, // Inst #2894 = V6_vconv_hf_qf32
4247 { 2893, 2, 1, 4, 252, 0, 0, 359, HexagonImpOpBase + 0, 0, 0x80000000000801aULL }, // Inst #2893 = V6_vconv_hf_qf16
4248 { 2892, 2, 1, 4, 252, 0, 0, 359, HexagonImpOpBase + 0, 0, 0x80000000000801aULL }, // Inst #2892 = V6_vconv_hf_h
4249 { 2891, 2, 1, 4, 252, 0, 0, 359, HexagonImpOpBase + 0, 0, 0x80000000000801aULL }, // Inst #2891 = V6_vconv_h_hf
4250 { 2890, 3, 1, 4, 253, 0, 0, 375, HexagonImpOpBase + 0, 0, 0x90000000000801cULL }, // Inst #2890 = V6_vcombine_tmp
4251 { 2889, 3, 1, 4, 41, 0, 0, 375, HexagonImpOpBase + 0, 0|(1ULL<<MCID::RegSequence), 0x800000000008011ULL }, // Inst #2889 = V6_vcombine
4252 { 2888, 3, 1, 4, 44, 0, 0, 980, HexagonImpOpBase + 0, 0, 0x1800000000008410ULL }, // Inst #2888 = V6_vcmov
4253 { 2887, 2, 1, 4, 252, 0, 0, 359, HexagonImpOpBase + 0, 0, 0x80000000000801aULL }, // Inst #2887 = V6_vcl0w
4254 { 2886, 2, 1, 4, 252, 0, 0, 359, HexagonImpOpBase + 0, 0, 0x80000000000801aULL }, // Inst #2886 = V6_vcl0h
4255 { 2885, 4, 1, 4, 47, 0, 0, 976, HexagonImpOpBase + 0, 0, 0x800000000008411ULL }, // Inst #2885 = V6_vccombine
4256 { 2884, 3, 1, 4, 37, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x3800000000008010ULL }, // Inst #2884 = V6_vavgwrnd
4257 { 2883, 3, 1, 4, 37, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x3800000000008010ULL }, // Inst #2883 = V6_vavgw
4258 { 2882, 3, 1, 4, 37, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x3800000000008010ULL }, // Inst #2882 = V6_vavguwrnd
4259 { 2881, 3, 1, 4, 37, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x3800000000008010ULL }, // Inst #2881 = V6_vavguw
4260 { 2880, 3, 1, 4, 37, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x3800000000008010ULL }, // Inst #2880 = V6_vavguhrnd
4261 { 2879, 3, 1, 4, 37, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x3800000000008010ULL }, // Inst #2879 = V6_vavguh
4262 { 2878, 3, 1, 4, 37, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x3800000000008010ULL }, // Inst #2878 = V6_vavgubrnd
4263 { 2877, 3, 1, 4, 37, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x3800000000008010ULL }, // Inst #2877 = V6_vavgub
4264 { 2876, 3, 1, 4, 37, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x3800000000008010ULL }, // Inst #2876 = V6_vavghrnd
4265 { 2875, 3, 1, 4, 37, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x3800000000008010ULL }, // Inst #2875 = V6_vavgh
4266 { 2874, 3, 1, 4, 37, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x3800000000008010ULL }, // Inst #2874 = V6_vavgbrnd
4267 { 2873, 3, 1, 4, 37, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x3800000000008010ULL }, // Inst #2873 = V6_vavgb
4268 { 2872, 2, 1, 4, 251, 0, 0, 359, HexagonImpOpBase + 0, 0, 0x90000000000801cULL }, // Inst #2872 = V6_vassign_tmp
4269 { 2871, 2, 1, 4, 236, 0, 0, 359, HexagonImpOpBase + 0, 0, 0x80000000000801eULL }, // Inst #2871 = V6_vassign_fp
4270 { 2870, 2, 1, 4, 63, 0, 0, 359, HexagonImpOpBase + 0, 0, 0x1800000000008010ULL }, // Inst #2870 = V6_vassign
4271 { 2869, 3, 1, 4, 238, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x80000000000801aULL }, // Inst #2869 = V6_vasrwv
4272 { 2868, 4, 1, 4, 250, 0, 0, 962, HexagonImpOpBase + 0, 0, 0x80000000000801aULL }, // Inst #2868 = V6_vasrwuhsat
4273 { 2867, 4, 1, 4, 250, 0, 0, 962, HexagonImpOpBase + 0, 0, 0x80000000000801aULL }, // Inst #2867 = V6_vasrwuhrndsat
4274 { 2866, 4, 1, 4, 250, 0, 0, 962, HexagonImpOpBase + 0, 0, 0x80000000000801aULL }, // Inst #2866 = V6_vasrwhsat
4275 { 2865, 4, 1, 4, 250, 0, 0, 962, HexagonImpOpBase + 0, 0, 0x80000000000801aULL }, // Inst #2865 = V6_vasrwhrndsat
4276 { 2864, 4, 1, 4, 250, 0, 0, 962, HexagonImpOpBase + 0, 0, 0x80000000000801aULL }, // Inst #2864 = V6_vasrwh
4277 { 2863, 4, 1, 4, 248, 0, 0, 392, HexagonImpOpBase + 0, 0, 0x84000000000801aULL }, // Inst #2863 = V6_vasrw_acc
4278 { 2862, 3, 1, 4, 247, 0, 0, 396, HexagonImpOpBase + 0, 0, 0x80000000000801aULL }, // Inst #2862 = V6_vasrw
4279 { 2861, 3, 1, 4, 238, 0, 0, 973, HexagonImpOpBase + 0, 0, 0x480000000000801aULL }, // Inst #2861 = V6_vasrvwuhsat
4280 { 2860, 3, 1, 4, 238, 0, 0, 973, HexagonImpOpBase + 0, 0, 0x480000000000801aULL }, // Inst #2860 = V6_vasrvwuhrndsat
4281 { 2859, 3, 1, 4, 238, 0, 0, 973, HexagonImpOpBase + 0, 0, 0x480000000000801aULL }, // Inst #2859 = V6_vasrvuhubsat
4282 { 2858, 3, 1, 4, 238, 0, 0, 973, HexagonImpOpBase + 0, 0, 0x480000000000801aULL }, // Inst #2858 = V6_vasrvuhubrndsat
4283 { 2857, 4, 1, 4, 250, 0, 0, 962, HexagonImpOpBase + 0, 0, 0x80000000000801aULL }, // Inst #2857 = V6_vasruwuhsat
4284 { 2856, 4, 1, 4, 250, 0, 0, 962, HexagonImpOpBase + 0, 0, 0x80000000000801aULL }, // Inst #2856 = V6_vasruwuhrndsat
4285 { 2855, 4, 1, 4, 250, 0, 0, 962, HexagonImpOpBase + 0, 0, 0x80000000000801aULL }, // Inst #2855 = V6_vasruhubsat
4286 { 2854, 4, 1, 4, 250, 0, 0, 962, HexagonImpOpBase + 0, 0, 0x80000000000801aULL }, // Inst #2854 = V6_vasruhubrndsat
4287 { 2853, 3, 1, 4, 238, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x80000000000801aULL }, // Inst #2853 = V6_vasrhv
4288 { 2852, 4, 1, 4, 250, 0, 0, 962, HexagonImpOpBase + 0, 0, 0x80000000000801aULL }, // Inst #2852 = V6_vasrhubsat
4289 { 2851, 4, 1, 4, 250, 0, 0, 962, HexagonImpOpBase + 0, 0, 0x80000000000801aULL }, // Inst #2851 = V6_vasrhubrndsat
4290 { 2850, 4, 1, 4, 250, 0, 0, 962, HexagonImpOpBase + 0, 0, 0x80000000000801aULL }, // Inst #2850 = V6_vasrhbsat
4291 { 2849, 4, 1, 4, 250, 0, 0, 962, HexagonImpOpBase + 0, 0, 0x80000000000801aULL }, // Inst #2849 = V6_vasrhbrndsat
4292 { 2848, 4, 1, 4, 248, 0, 0, 392, HexagonImpOpBase + 0, 0, 0x84000000000801aULL }, // Inst #2848 = V6_vasrh_acc
4293 { 2847, 3, 1, 4, 247, 0, 0, 396, HexagonImpOpBase + 0, 0, 0x80000000000801aULL }, // Inst #2847 = V6_vasrh
4294 { 2846, 4, 1, 4, 249, 0, 0, 371, HexagonImpOpBase + 0, 0, 0x800000000008019ULL }, // Inst #2846 = V6_vasr_into
4295 { 2845, 3, 1, 4, 238, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x80000000000801aULL }, // Inst #2845 = V6_vaslwv
4296 { 2844, 4, 1, 4, 248, 0, 0, 392, HexagonImpOpBase + 0, 0, 0x84000000000801aULL }, // Inst #2844 = V6_vaslw_acc
4297 { 2843, 3, 1, 4, 247, 0, 0, 396, HexagonImpOpBase + 0, 0, 0x80000000000801aULL }, // Inst #2843 = V6_vaslw
4298 { 2842, 3, 1, 4, 238, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x80000000000801aULL }, // Inst #2842 = V6_vaslhv
4299 { 2841, 4, 1, 4, 248, 0, 0, 392, HexagonImpOpBase + 0, 0, 0x84000000000801aULL }, // Inst #2841 = V6_vaslh_acc
4300 { 2840, 3, 1, 4, 247, 0, 0, 396, HexagonImpOpBase + 0, 0, 0x80000000000801aULL }, // Inst #2840 = V6_vaslh
4301 { 2839, 4, 1, 4, 246, 0, 0, 385, HexagonImpOpBase + 0, 0, 0x84000000000001eULL }, // Inst #2839 = V6_vandvrt_acc
4302 { 2838, 3, 1, 4, 245, 0, 0, 389, HexagonImpOpBase + 0, 0, 0x80000000000801eULL }, // Inst #2838 = V6_vandvrt
4303 { 2837, 3, 1, 4, 37, 0, 0, 970, HexagonImpOpBase + 0, 0, 0x3800000000008010ULL }, // Inst #2837 = V6_vandvqv
4304 { 2836, 3, 1, 4, 37, 0, 0, 970, HexagonImpOpBase + 0, 0, 0x3800000000008010ULL }, // Inst #2836 = V6_vandvnqv
4305 { 2835, 4, 1, 4, 246, 0, 0, 378, HexagonImpOpBase + 0, 0, 0x84000000000801eULL }, // Inst #2835 = V6_vandqrt_acc
4306 { 2834, 3, 1, 4, 245, 0, 0, 382, HexagonImpOpBase + 0, 0, 0x80000000000801eULL }, // Inst #2834 = V6_vandqrt
4307 { 2833, 4, 1, 4, 246, 0, 0, 378, HexagonImpOpBase + 0, 0, 0x84000000000801eULL }, // Inst #2833 = V6_vandnqrt_acc
4308 { 2832, 3, 1, 4, 245, 0, 0, 382, HexagonImpOpBase + 0, 0, 0x80000000000801eULL }, // Inst #2832 = V6_vandnqrt
4309 { 2831, 3, 1, 4, 37, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x3800000000008010ULL }, // Inst #2831 = V6_vand
4310 { 2830, 4, 1, 4, 244, 0, 0, 966, HexagonImpOpBase + 0, 0, 0x800000000008018ULL }, // Inst #2830 = V6_valignbi
4311 { 2829, 4, 1, 4, 244, 0, 0, 962, HexagonImpOpBase + 0, 0, 0x800000000008018ULL }, // Inst #2829 = V6_valignb
4312 { 2828, 3, 1, 4, 41, 0, 0, 364, HexagonImpOpBase + 0, 0, 0x800000000008011ULL }, // Inst #2828 = V6_vaddwsat_dv
4313 { 2827, 3, 1, 4, 37, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x3800000000008010ULL }, // Inst #2827 = V6_vaddwsat
4314 { 2826, 4, 1, 4, 240, 0, 0, 367, HexagonImpOpBase + 0, 0, 0x3840000000008010ULL }, // Inst #2826 = V6_vaddwq
4315 { 2825, 4, 1, 4, 240, 0, 0, 367, HexagonImpOpBase + 0, 0, 0x3840000000008010ULL }, // Inst #2825 = V6_vaddwnq
4316 { 2824, 3, 1, 4, 41, 0, 0, 364, HexagonImpOpBase + 0, 0, 0x800000000008011ULL }, // Inst #2824 = V6_vaddw_dv
4317 { 2823, 3, 1, 4, 37, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x3800000000008010ULL }, // Inst #2823 = V6_vaddw
4318 { 2822, 3, 1, 4, 41, 0, 0, 364, HexagonImpOpBase + 0, 0, 0x800000000008011ULL }, // Inst #2822 = V6_vadduwsat_dv
4319 { 2821, 3, 1, 4, 37, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x3800000000008010ULL }, // Inst #2821 = V6_vadduwsat
4320 { 2820, 4, 1, 4, 243, 0, 0, 371, HexagonImpOpBase + 0, 0, 0x84000000000801dULL }, // Inst #2820 = V6_vadduhw_acc
4321 { 2819, 3, 1, 4, 239, 0, 0, 375, HexagonImpOpBase + 0, 0, 0x80000000000801dULL }, // Inst #2819 = V6_vadduhw
4322 { 2818, 3, 1, 4, 41, 0, 0, 364, HexagonImpOpBase + 0, 0, 0x800000000008011ULL }, // Inst #2818 = V6_vadduhsat_dv
4323 { 2817, 3, 1, 4, 37, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x3800000000008010ULL }, // Inst #2817 = V6_vadduhsat
4324 { 2816, 3, 1, 4, 37, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x3800000000008010ULL }, // Inst #2816 = V6_vaddububb_sat
4325 { 2815, 3, 1, 4, 41, 0, 0, 364, HexagonImpOpBase + 0, 0, 0x800000000008011ULL }, // Inst #2815 = V6_vaddubsat_dv
4326 { 2814, 3, 1, 4, 37, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x3800000000008010ULL }, // Inst #2814 = V6_vaddubsat
4327 { 2813, 4, 1, 4, 243, 0, 0, 371, HexagonImpOpBase + 0, 0, 0x84000000000801dULL }, // Inst #2813 = V6_vaddubh_acc
4328 { 2812, 3, 1, 4, 239, 0, 0, 375, HexagonImpOpBase + 0, 0, 0x80000000000801dULL }, // Inst #2812 = V6_vaddubh
4329 { 2811, 4, 1, 4, 243, 0, 0, 371, HexagonImpOpBase + 0, 0, 0x84000000000801dULL }, // Inst #2811 = V6_vaddhw_acc
4330 { 2810, 3, 1, 4, 239, 0, 0, 375, HexagonImpOpBase + 0, 0, 0x80000000000801dULL }, // Inst #2810 = V6_vaddhw
4331 { 2809, 3, 1, 4, 41, 0, 0, 364, HexagonImpOpBase + 0, 0, 0x800000000008011ULL }, // Inst #2809 = V6_vaddhsat_dv
4332 { 2808, 3, 1, 4, 37, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x3800000000008010ULL }, // Inst #2808 = V6_vaddhsat
4333 { 2807, 4, 1, 4, 240, 0, 0, 367, HexagonImpOpBase + 0, 0, 0x3840000000008010ULL }, // Inst #2807 = V6_vaddhq
4334 { 2806, 4, 1, 4, 240, 0, 0, 367, HexagonImpOpBase + 0, 0, 0x3840000000008010ULL }, // Inst #2806 = V6_vaddhnq
4335 { 2805, 3, 1, 4, 41, 0, 0, 364, HexagonImpOpBase + 0, 0, 0x800000000008011ULL }, // Inst #2805 = V6_vaddh_dv
4336 { 2804, 3, 1, 4, 37, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x3800000000008010ULL }, // Inst #2804 = V6_vaddh
4337 { 2803, 3, 1, 4, 238, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x80000000000801aULL }, // Inst #2803 = V6_vaddclbw
4338 { 2802, 3, 1, 4, 238, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x80000000000801aULL }, // Inst #2802 = V6_vaddclbh
4339 { 2801, 4, 1, 4, 240, 0, 0, 958, HexagonImpOpBase + 0, 0, 0x3800000000008010ULL }, // Inst #2801 = V6_vaddcarrysat
4340 { 2800, 4, 2, 4, 242, 0, 0, 954, HexagonImpOpBase + 0, 0, 0x3800000000008010ULL }, // Inst #2800 = V6_vaddcarryo
4341 { 2799, 5, 2, 4, 241, 0, 0, 949, HexagonImpOpBase + 0, 0, 0x3800000000008010ULL }, // Inst #2799 = V6_vaddcarry
4342 { 2798, 3, 1, 4, 41, 0, 0, 364, HexagonImpOpBase + 0, 0, 0x800000000008011ULL }, // Inst #2798 = V6_vaddbsat_dv
4343 { 2797, 3, 1, 4, 37, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x3800000000008010ULL }, // Inst #2797 = V6_vaddbsat
4344 { 2796, 4, 1, 4, 240, 0, 0, 367, HexagonImpOpBase + 0, 0, 0x3840000000008010ULL }, // Inst #2796 = V6_vaddbq
4345 { 2795, 4, 1, 4, 240, 0, 0, 367, HexagonImpOpBase + 0, 0, 0x3840000000008010ULL }, // Inst #2795 = V6_vaddbnq
4346 { 2794, 3, 1, 4, 41, 0, 0, 364, HexagonImpOpBase + 0, 0, 0x800000000008011ULL }, // Inst #2794 = V6_vaddb_dv
4347 { 2793, 3, 1, 4, 37, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x3800000000008010ULL }, // Inst #2793 = V6_vaddb
4348 { 2792, 3, 1, 4, 237, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x80000000000801cULL }, // Inst #2792 = V6_vadd_sf_sf
4349 { 2791, 3, 1, 4, 239, 0, 0, 375, HexagonImpOpBase + 0, 0, 0x80000000000801dULL }, // Inst #2791 = V6_vadd_sf_hf
4350 { 2790, 3, 1, 4, 239, 0, 0, 375, HexagonImpOpBase + 0, 0, 0x80000000000801dULL }, // Inst #2790 = V6_vadd_sf_bf
4351 { 2789, 3, 1, 4, 238, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x80000000000801aULL }, // Inst #2789 = V6_vadd_sf
4352 { 2788, 3, 1, 4, 238, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x80000000000801aULL }, // Inst #2788 = V6_vadd_qf32_mix
4353 { 2787, 3, 1, 4, 238, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x80000000000801aULL }, // Inst #2787 = V6_vadd_qf32
4354 { 2786, 3, 1, 4, 238, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x80000000000801aULL }, // Inst #2786 = V6_vadd_qf16_mix
4355 { 2785, 3, 1, 4, 238, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x80000000000801aULL }, // Inst #2785 = V6_vadd_qf16
4356 { 2784, 3, 1, 4, 237, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x80000000000801cULL }, // Inst #2784 = V6_vadd_hf_hf
4357 { 2783, 3, 1, 4, 239, 0, 0, 375, HexagonImpOpBase + 0, 0, 0x80000000000801dULL }, // Inst #2783 = V6_vadd_hf_f8
4358 { 2782, 3, 1, 4, 238, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x80000000000801aULL }, // Inst #2782 = V6_vadd_hf
4359 { 2781, 2, 1, 4, 63, 0, 0, 359, HexagonImpOpBase + 0, 0, 0x3800000000008010ULL }, // Inst #2781 = V6_vabsw_sat
4360 { 2780, 2, 1, 4, 63, 0, 0, 359, HexagonImpOpBase + 0, 0, 0x3800000000008010ULL }, // Inst #2780 = V6_vabsw
4361 { 2779, 2, 1, 4, 63, 0, 0, 359, HexagonImpOpBase + 0, 0, 0x3800000000008010ULL }, // Inst #2779 = V6_vabsh_sat
4362 { 2778, 2, 1, 4, 63, 0, 0, 359, HexagonImpOpBase + 0, 0, 0x3800000000008010ULL }, // Inst #2778 = V6_vabsh
4363 { 2777, 3, 1, 4, 237, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x80000000000801cULL }, // Inst #2777 = V6_vabsdiffw
4364 { 2776, 3, 1, 4, 237, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x80000000000801cULL }, // Inst #2776 = V6_vabsdiffuh
4365 { 2775, 3, 1, 4, 237, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x80000000000801cULL }, // Inst #2775 = V6_vabsdiffub
4366 { 2774, 3, 1, 4, 237, 0, 0, 361, HexagonImpOpBase + 0, 0, 0x80000000000801cULL }, // Inst #2774 = V6_vabsdiffh
4367 { 2773, 2, 1, 4, 63, 0, 0, 359, HexagonImpOpBase + 0, 0, 0x3800000000008010ULL }, // Inst #2773 = V6_vabsb_sat
4368 { 2772, 2, 1, 4, 63, 0, 0, 359, HexagonImpOpBase + 0, 0, 0x3800000000008010ULL }, // Inst #2772 = V6_vabsb
4369 { 2771, 2, 1, 4, 236, 0, 0, 359, HexagonImpOpBase + 0, 0, 0x80000000000801eULL }, // Inst #2771 = V6_vabs_sf
4370 { 2770, 2, 1, 4, 236, 0, 0, 359, HexagonImpOpBase + 0, 0, 0x80000000000801eULL }, // Inst #2770 = V6_vabs_hf
4371 { 2769, 2, 1, 4, 236, 0, 0, 359, HexagonImpOpBase + 0, 0, 0x80000000000801eULL }, // Inst #2769 = V6_vabs_f8
4372 { 2768, 3, 1, 4, 235, 0, 0, 946, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0xc002e000000000dULL }, // Inst #2768 = V6_vS32b_srls_ppu
4373 { 2767, 3, 1, 4, 235, 0, 0, 507, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0xc002e000000000dULL }, // Inst #2767 = V6_vS32b_srls_pi
4374 { 2766, 2, 0, 4, 234, 0, 0, 155, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0xc002b000000000dULL }, // Inst #2766 = V6_vS32b_srls_ai
4375 { 2765, 5, 1, 4, 232, 0, 0, 941, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x18002e0000000014ULL }, // Inst #2765 = V6_vS32b_qpred_ppu
4376 { 2764, 5, 1, 4, 232, 0, 0, 936, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x18002e0000000014ULL }, // Inst #2764 = V6_vS32b_qpred_pi
4377 { 2763, 4, 0, 4, 231, 0, 0, 932, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x18002b0000000014ULL }, // Inst #2763 = V6_vS32b_qpred_ai
4378 { 2762, 5, 1, 4, 230, 0, 0, 919, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x18002e0000080414ULL }, // Inst #2762 = V6_vS32b_pred_ppu
4379 { 2761, 5, 1, 4, 230, 0, 0, 914, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x18002e0000080414ULL }, // Inst #2761 = V6_vS32b_pred_pi
4380 { 2760, 4, 0, 4, 229, 0, 0, 910, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x18002b0000080414ULL }, // Inst #2760 = V6_vS32b_pred_ai
4381 { 2759, 4, 1, 4, 233, 0, 0, 928, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x18002e0000080014ULL }, // Inst #2759 = V6_vS32b_ppu
4382 { 2758, 4, 1, 4, 233, 0, 0, 924, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x18002e0000080014ULL }, // Inst #2758 = V6_vS32b_pi
4383 { 2757, 5, 1, 4, 232, 0, 0, 941, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x18002e0000000014ULL }, // Inst #2757 = V6_vS32b_nt_qpred_ppu
4384 { 2756, 5, 1, 4, 232, 0, 0, 936, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x18002e0000000014ULL }, // Inst #2756 = V6_vS32b_nt_qpred_pi
4385 { 2755, 4, 0, 4, 231, 0, 0, 932, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x18002b0000000014ULL }, // Inst #2755 = V6_vS32b_nt_qpred_ai
4386 { 2754, 5, 1, 4, 230, 0, 0, 919, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x18002e0000080414ULL }, // Inst #2754 = V6_vS32b_nt_pred_ppu
4387 { 2753, 5, 1, 4, 230, 0, 0, 914, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x18002e0000080414ULL }, // Inst #2753 = V6_vS32b_nt_pred_pi
4388 { 2752, 4, 0, 4, 229, 0, 0, 910, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x18002b0000080414ULL }, // Inst #2752 = V6_vS32b_nt_pred_ai
4389 { 2751, 4, 1, 4, 233, 0, 0, 928, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x18002e0000080014ULL }, // Inst #2751 = V6_vS32b_nt_ppu
4390 { 2750, 4, 1, 4, 233, 0, 0, 924, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x18002e0000080014ULL }, // Inst #2750 = V6_vS32b_nt_pi
4391 { 2749, 5, 1, 4, 232, 0, 0, 941, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x18002e0000000014ULL }, // Inst #2749 = V6_vS32b_nt_nqpred_ppu
4392 { 2748, 5, 1, 4, 232, 0, 0, 936, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x18002e0000000014ULL }, // Inst #2748 = V6_vS32b_nt_nqpred_pi
4393 { 2747, 4, 0, 4, 231, 0, 0, 932, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x18002b0000000014ULL }, // Inst #2747 = V6_vS32b_nt_nqpred_ai
4394 { 2746, 5, 1, 4, 230, 0, 0, 919, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x18002e0000080c14ULL }, // Inst #2746 = V6_vS32b_nt_npred_ppu
4395 { 2745, 5, 1, 4, 230, 0, 0, 914, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x18002e0000080c14ULL }, // Inst #2745 = V6_vS32b_nt_npred_pi
4396 { 2744, 4, 0, 4, 229, 0, 0, 910, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x18002b0000080c14ULL }, // Inst #2744 = V6_vS32b_nt_npred_ai
4397 { 2743, 5, 1, 4, 227, 0, 0, 919, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0xc002e0000144413ULL }, // Inst #2743 = V6_vS32b_nt_new_pred_ppu
4398 { 2742, 5, 1, 4, 227, 0, 0, 914, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0xc002e0000144413ULL }, // Inst #2742 = V6_vS32b_nt_new_pred_pi
4399 { 2741, 4, 0, 4, 226, 0, 0, 910, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0xc002b0000134413ULL }, // Inst #2741 = V6_vS32b_nt_new_pred_ai
4400 { 2740, 4, 1, 4, 228, 0, 0, 928, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc002e0000134013ULL }, // Inst #2740 = V6_vS32b_nt_new_ppu
4401 { 2739, 4, 1, 4, 228, 0, 0, 924, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc002e0000134013ULL }, // Inst #2739 = V6_vS32b_nt_new_pi
4402 { 2738, 5, 1, 4, 227, 0, 0, 919, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0xc002e0000144c13ULL }, // Inst #2738 = V6_vS32b_nt_new_npred_ppu
4403 { 2737, 5, 1, 4, 227, 0, 0, 914, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0xc002e0000144c13ULL }, // Inst #2737 = V6_vS32b_nt_new_npred_pi
4404 { 2736, 4, 0, 4, 226, 0, 0, 910, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0xc002b0000134c13ULL }, // Inst #2736 = V6_vS32b_nt_new_npred_ai
4405 { 2735, 3, 0, 4, 225, 0, 0, 294, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc002b0000124013ULL }, // Inst #2735 = V6_vS32b_nt_new_ai
4406 { 2734, 3, 0, 4, 46, 0, 0, 294, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x18002b0000080014ULL }, // Inst #2734 = V6_vS32b_nt_ai
4407 { 2733, 5, 1, 4, 232, 0, 0, 941, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x18002e0000000014ULL }, // Inst #2733 = V6_vS32b_nqpred_ppu
4408 { 2732, 5, 1, 4, 232, 0, 0, 936, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x18002e0000000014ULL }, // Inst #2732 = V6_vS32b_nqpred_pi
4409 { 2731, 4, 0, 4, 231, 0, 0, 932, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x18002b0000000014ULL }, // Inst #2731 = V6_vS32b_nqpred_ai
4410 { 2730, 5, 1, 4, 230, 0, 0, 919, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x18002e0000080c14ULL }, // Inst #2730 = V6_vS32b_npred_ppu
4411 { 2729, 5, 1, 4, 230, 0, 0, 914, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x18002e0000080c14ULL }, // Inst #2729 = V6_vS32b_npred_pi
4412 { 2728, 4, 0, 4, 229, 0, 0, 910, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x18002b0000080c14ULL }, // Inst #2728 = V6_vS32b_npred_ai
4413 { 2727, 5, 1, 4, 227, 0, 0, 919, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0xc002e0000144413ULL }, // Inst #2727 = V6_vS32b_new_pred_ppu
4414 { 2726, 5, 1, 4, 227, 0, 0, 914, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0xc002e0000144413ULL }, // Inst #2726 = V6_vS32b_new_pred_pi
4415 { 2725, 4, 0, 4, 226, 0, 0, 910, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0xc002b0000134413ULL }, // Inst #2725 = V6_vS32b_new_pred_ai
4416 { 2724, 4, 1, 4, 228, 0, 0, 928, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc002e0000134013ULL }, // Inst #2724 = V6_vS32b_new_ppu
4417 { 2723, 4, 1, 4, 228, 0, 0, 924, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc002e0000134013ULL }, // Inst #2723 = V6_vS32b_new_pi
4418 { 2722, 5, 1, 4, 227, 0, 0, 919, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0xc002e0000144c13ULL }, // Inst #2722 = V6_vS32b_new_npred_ppu
4419 { 2721, 5, 1, 4, 227, 0, 0, 914, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0xc002e0000144c13ULL }, // Inst #2721 = V6_vS32b_new_npred_pi
4420 { 2720, 4, 0, 4, 226, 0, 0, 910, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0xc002b0000134c13ULL }, // Inst #2720 = V6_vS32b_new_npred_ai
4421 { 2719, 3, 0, 4, 225, 0, 0, 294, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc002b0000124013ULL }, // Inst #2719 = V6_vS32b_new_ai
4422 { 2718, 3, 0, 4, 46, 0, 0, 294, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x18002b0000080014ULL }, // Inst #2718 = V6_vS32b_ai
4423 { 2717, 5, 1, 4, 223, 0, 0, 919, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x8002e0000000415ULL }, // Inst #2717 = V6_vS32Ub_pred_ppu
4424 { 2716, 5, 1, 4, 223, 0, 0, 914, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x8002e0000000415ULL }, // Inst #2716 = V6_vS32Ub_pred_pi
4425 { 2715, 4, 0, 4, 222, 0, 0, 910, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x8002b0000000415ULL }, // Inst #2715 = V6_vS32Ub_pred_ai
4426 { 2714, 4, 1, 4, 224, 0, 0, 928, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x8002e0000000015ULL }, // Inst #2714 = V6_vS32Ub_ppu
4427 { 2713, 4, 1, 4, 224, 0, 0, 924, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x8002e0000000015ULL }, // Inst #2713 = V6_vS32Ub_pi
4428 { 2712, 5, 1, 4, 223, 0, 0, 919, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x8002e0000000c15ULL }, // Inst #2712 = V6_vS32Ub_npred_ppu
4429 { 2711, 5, 1, 4, 223, 0, 0, 914, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x8002e0000000c15ULL }, // Inst #2711 = V6_vS32Ub_npred_pi
4430 { 2710, 4, 0, 4, 222, 0, 0, 910, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x8002b0000000c15ULL }, // Inst #2710 = V6_vS32Ub_npred_ai
4431 { 2709, 3, 0, 4, 221, 0, 0, 294, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x8002b0000000015ULL }, // Inst #2709 = V6_vS32Ub_ai
4432 { 2708, 5, 2, 4, 219, 0, 0, 905, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x9002e8000408416ULL }, // Inst #2708 = V6_vL32b_tmp_pred_ppu
4433 { 2707, 5, 2, 4, 219, 0, 0, 900, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x9002e8000408416ULL }, // Inst #2707 = V6_vL32b_tmp_pred_pi
4434 { 2706, 4, 1, 4, 218, 0, 0, 896, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x9002b8000408416ULL }, // Inst #2706 = V6_vL32b_tmp_pred_ai
4435 { 2705, 4, 2, 4, 220, 0, 0, 892, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x9002e8000408016ULL }, // Inst #2705 = V6_vL32b_tmp_ppu
4436 { 2704, 4, 2, 4, 220, 0, 0, 888, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x9002e8000408016ULL }, // Inst #2704 = V6_vL32b_tmp_pi
4437 { 2703, 5, 2, 4, 219, 0, 0, 905, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x9002e8000408c16ULL }, // Inst #2703 = V6_vL32b_tmp_npred_ppu
4438 { 2702, 5, 2, 4, 219, 0, 0, 900, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x9002e8000408c16ULL }, // Inst #2702 = V6_vL32b_tmp_npred_pi
4439 { 2701, 4, 1, 4, 218, 0, 0, 896, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x9002b8000408c16ULL }, // Inst #2701 = V6_vL32b_tmp_npred_ai
4440 { 2700, 3, 1, 4, 217, 0, 0, 277, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x9002b8000408016ULL }, // Inst #2700 = V6_vL32b_tmp_ai
4441 { 2699, 5, 2, 4, 215, 0, 0, 905, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x18002e8000408412ULL }, // Inst #2699 = V6_vL32b_pred_ppu
4442 { 2698, 5, 2, 4, 215, 0, 0, 900, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x18002e8000408412ULL }, // Inst #2698 = V6_vL32b_pred_pi
4443 { 2697, 4, 1, 4, 214, 0, 0, 896, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x18002b8000408412ULL }, // Inst #2697 = V6_vL32b_pred_ai
4444 { 2696, 4, 2, 4, 216, 0, 0, 892, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x18002e8000608012ULL }, // Inst #2696 = V6_vL32b_ppu
4445 { 2695, 4, 2, 4, 216, 0, 0, 888, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x18002e8000608012ULL }, // Inst #2695 = V6_vL32b_pi
4446 { 2694, 5, 2, 4, 219, 0, 0, 905, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x9002e8000408416ULL }, // Inst #2694 = V6_vL32b_nt_tmp_pred_ppu
4447 { 2693, 5, 2, 4, 219, 0, 0, 900, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x9002e8000408416ULL }, // Inst #2693 = V6_vL32b_nt_tmp_pred_pi
4448 { 2692, 4, 1, 4, 218, 0, 0, 896, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x9002b8000408416ULL }, // Inst #2692 = V6_vL32b_nt_tmp_pred_ai
4449 { 2691, 4, 2, 4, 220, 0, 0, 892, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x9002e8000408016ULL }, // Inst #2691 = V6_vL32b_nt_tmp_ppu
4450 { 2690, 4, 2, 4, 220, 0, 0, 888, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x9002e8000408016ULL }, // Inst #2690 = V6_vL32b_nt_tmp_pi
4451 { 2689, 5, 2, 4, 219, 0, 0, 905, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x9002e8000408c16ULL }, // Inst #2689 = V6_vL32b_nt_tmp_npred_ppu
4452 { 2688, 5, 2, 4, 219, 0, 0, 900, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x9002e8000408c16ULL }, // Inst #2688 = V6_vL32b_nt_tmp_npred_pi
4453 { 2687, 4, 1, 4, 218, 0, 0, 896, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x9002b8000408c16ULL }, // Inst #2687 = V6_vL32b_nt_tmp_npred_ai
4454 { 2686, 3, 1, 4, 217, 0, 0, 277, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x9002b8000408016ULL }, // Inst #2686 = V6_vL32b_nt_tmp_ai
4455 { 2685, 5, 2, 4, 215, 0, 0, 905, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x18002e8000408412ULL }, // Inst #2685 = V6_vL32b_nt_pred_ppu
4456 { 2684, 5, 2, 4, 215, 0, 0, 900, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x18002e8000408412ULL }, // Inst #2684 = V6_vL32b_nt_pred_pi
4457 { 2683, 4, 1, 4, 214, 0, 0, 896, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x18002b8000408412ULL }, // Inst #2683 = V6_vL32b_nt_pred_ai
4458 { 2682, 4, 2, 4, 216, 0, 0, 892, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x18002e8000608012ULL }, // Inst #2682 = V6_vL32b_nt_ppu
4459 { 2681, 4, 2, 4, 216, 0, 0, 888, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x18002e8000608012ULL }, // Inst #2681 = V6_vL32b_nt_pi
4460 { 2680, 5, 2, 4, 215, 0, 0, 905, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x18002e8000408c12ULL }, // Inst #2680 = V6_vL32b_nt_npred_ppu
4461 { 2679, 5, 2, 4, 215, 0, 0, 900, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x18002e8000408c12ULL }, // Inst #2679 = V6_vL32b_nt_npred_pi
4462 { 2678, 4, 1, 4, 214, 0, 0, 896, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x18002b8000408c12ULL }, // Inst #2678 = V6_vL32b_nt_npred_ai
4463 { 2677, 5, 2, 4, 215, 0, 0, 905, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x1c002e8000408412ULL }, // Inst #2677 = V6_vL32b_nt_cur_pred_ppu
4464 { 2676, 5, 2, 4, 215, 0, 0, 900, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x1c002e8000408412ULL }, // Inst #2676 = V6_vL32b_nt_cur_pred_pi
4465 { 2675, 4, 1, 4, 214, 0, 0, 896, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x1c002b8000408412ULL }, // Inst #2675 = V6_vL32b_nt_cur_pred_ai
4466 { 2674, 4, 2, 4, 216, 0, 0, 892, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x1c002e8000408012ULL }, // Inst #2674 = V6_vL32b_nt_cur_ppu
4467 { 2673, 4, 2, 4, 216, 0, 0, 888, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x1c002e8000408012ULL }, // Inst #2673 = V6_vL32b_nt_cur_pi
4468 { 2672, 5, 2, 4, 215, 0, 0, 905, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x1c002e8000408c12ULL }, // Inst #2672 = V6_vL32b_nt_cur_npred_ppu
4469 { 2671, 5, 2, 4, 215, 0, 0, 900, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x1c002e8000408c12ULL }, // Inst #2671 = V6_vL32b_nt_cur_npred_pi
4470 { 2670, 4, 1, 4, 214, 0, 0, 896, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x1c002b8000408c12ULL }, // Inst #2670 = V6_vL32b_nt_cur_npred_ai
4471 { 2669, 3, 1, 4, 42, 0, 0, 277, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x1c002b8000408012ULL }, // Inst #2669 = V6_vL32b_nt_cur_ai
4472 { 2668, 3, 1, 4, 42, 0, 0, 277, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x18002b8000608012ULL }, // Inst #2668 = V6_vL32b_nt_ai
4473 { 2667, 5, 2, 4, 215, 0, 0, 905, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x18002e8000408c12ULL }, // Inst #2667 = V6_vL32b_npred_ppu
4474 { 2666, 5, 2, 4, 215, 0, 0, 900, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x18002e8000408c12ULL }, // Inst #2666 = V6_vL32b_npred_pi
4475 { 2665, 4, 1, 4, 214, 0, 0, 896, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x18002b8000408c12ULL }, // Inst #2665 = V6_vL32b_npred_ai
4476 { 2664, 5, 2, 4, 215, 0, 0, 905, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x1c002e8000408412ULL }, // Inst #2664 = V6_vL32b_cur_pred_ppu
4477 { 2663, 5, 2, 4, 215, 0, 0, 900, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x1c002e8000408412ULL }, // Inst #2663 = V6_vL32b_cur_pred_pi
4478 { 2662, 4, 1, 4, 214, 0, 0, 896, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x1c002b8000408412ULL }, // Inst #2662 = V6_vL32b_cur_pred_ai
4479 { 2661, 4, 2, 4, 216, 0, 0, 892, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x1c002e8000408012ULL }, // Inst #2661 = V6_vL32b_cur_ppu
4480 { 2660, 4, 2, 4, 216, 0, 0, 888, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x1c002e8000408012ULL }, // Inst #2660 = V6_vL32b_cur_pi
4481 { 2659, 5, 2, 4, 215, 0, 0, 905, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x1c002e8000408c12ULL }, // Inst #2659 = V6_vL32b_cur_npred_ppu
4482 { 2658, 5, 2, 4, 215, 0, 0, 900, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x1c002e8000408c12ULL }, // Inst #2658 = V6_vL32b_cur_npred_pi
4483 { 2657, 4, 1, 4, 214, 0, 0, 896, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x1c002b8000408c12ULL }, // Inst #2657 = V6_vL32b_cur_npred_ai
4484 { 2656, 3, 1, 4, 42, 0, 0, 277, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x1c002b8000408012ULL }, // Inst #2656 = V6_vL32b_cur_ai
4485 { 2655, 3, 1, 4, 42, 0, 0, 277, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x18002b8000608012ULL }, // Inst #2655 = V6_vL32b_ai
4486 { 2654, 4, 2, 4, 213, 0, 0, 892, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x8002e8000408017ULL }, // Inst #2654 = V6_vL32Ub_ppu
4487 { 2653, 4, 2, 4, 213, 0, 0, 888, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x8002e8000408017ULL }, // Inst #2653 = V6_vL32Ub_pi
4488 { 2652, 3, 1, 4, 212, 0, 0, 277, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x8002b8000408017ULL }, // Inst #2652 = V6_vL32Ub_ai
4489 { 2651, 5, 1, 4, 211, 0, 0, 354, HexagonImpOpBase + 0, 0, 0x84000000000801dULL }, // Inst #2651 = V6_v6mpyvubs10_vxx
4490 { 2650, 4, 1, 4, 210, 0, 0, 350, HexagonImpOpBase + 0, 0, 0x80000000000801dULL }, // Inst #2650 = V6_v6mpyvubs10
4491 { 2649, 5, 1, 4, 211, 0, 0, 354, HexagonImpOpBase + 0, 0, 0x84000000000801dULL }, // Inst #2649 = V6_v6mpyhubs10_vxx
4492 { 2648, 4, 1, 4, 210, 0, 0, 350, HexagonImpOpBase + 0, 0, 0x80000000000801dULL }, // Inst #2648 = V6_v6mpyhubs10
4493 { 2647, 3, 1, 4, 41, 0, 0, 881, HexagonImpOpBase + 0, 0, 0x800000000008011ULL }, // Inst #2647 = V6_shuffeqw
4494 { 2646, 3, 1, 4, 41, 0, 0, 881, HexagonImpOpBase + 0, 0, 0x800000000008011ULL }, // Inst #2646 = V6_shuffeqh
4495 { 2645, 3, 1, 4, 208, 0, 0, 396, HexagonImpOpBase + 0, 0, 0x80000000000801cULL }, // Inst #2645 = V6_set_qfext
4496 { 2644, 3, 1, 4, 41, 0, 0, 881, HexagonImpOpBase + 0, 0, 0x800000000008011ULL }, // Inst #2644 = V6_pred_xor
4497 { 2643, 2, 1, 4, 209, 0, 0, 886, HexagonImpOpBase + 0, 0, 0x800000000008018ULL }, // Inst #2643 = V6_pred_scalar2v2
4498 { 2642, 2, 1, 4, 209, 0, 0, 886, HexagonImpOpBase + 0, 0, 0x800000000008018ULL }, // Inst #2642 = V6_pred_scalar2
4499 { 2641, 3, 1, 4, 41, 0, 0, 881, HexagonImpOpBase + 0, 0, 0x800000000008011ULL }, // Inst #2641 = V6_pred_or_n
4500 { 2640, 3, 1, 4, 41, 0, 0, 881, HexagonImpOpBase + 0, 0, 0x800000000008011ULL }, // Inst #2640 = V6_pred_or
4501 { 2639, 2, 1, 4, 63, 0, 0, 884, HexagonImpOpBase + 0, 0, 0x3800000000008010ULL }, // Inst #2639 = V6_pred_not
4502 { 2638, 3, 1, 4, 41, 0, 0, 881, HexagonImpOpBase + 0, 0, 0x800000000008011ULL }, // Inst #2638 = V6_pred_and_n
4503 { 2637, 3, 1, 4, 41, 0, 0, 881, HexagonImpOpBase + 0, 0, 0x800000000008011ULL }, // Inst #2637 = V6_pred_and
4504 { 2636, 2, 1, 4, 45, 0, 0, 289, HexagonImpOpBase + 0, 0, 0x80000000000801eULL }, // Inst #2636 = V6_lvsplatw
4505 { 2635, 2, 1, 4, 45, 0, 0, 289, HexagonImpOpBase + 0, 0, 0x80000000000801eULL }, // Inst #2635 = V6_lvsplath
4506 { 2634, 2, 1, 4, 45, 0, 0, 289, HexagonImpOpBase + 0, 0, 0x80000000000801eULL }, // Inst #2634 = V6_lvsplatb
4507 { 2633, 4, 1, 4, 208, 0, 0, 392, HexagonImpOpBase + 0, 0, 0x84000000000801cULL }, // Inst #2633 = V6_get_qfext_oracc
4508 { 2632, 3, 1, 4, 208, 0, 0, 396, HexagonImpOpBase + 0, 0, 0x80000000000801cULL }, // Inst #2632 = V6_get_qfext
4509 { 2631, 3, 1, 4, 207, 0, 0, 334, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x38000000000080a4ULL }, // Inst #2631 = V6_extractw
4510 { 2630, 2, 1, 4, 6, 0, 0, 167, HexagonImpOpBase + 0, 0, 0xc2800000ULL }, // Inst #2630 = TFRI64_V4
4511 { 2629, 3, 1, 4, 6, 0, 0, 495, HexagonImpOpBase + 0, 0, 0xc2800000ULL }, // Inst #2629 = TFRI64_V2_ext
4512 { 2628, 2, 0, 4, 206, 0, 0, 615, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x1b000000002aULL }, // Inst #2628 = SS2_storewi1
4513 { 2627, 2, 0, 4, 206, 0, 0, 615, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x1b000000002aULL }, // Inst #2627 = SS2_storewi0
4514 { 2626, 2, 0, 4, 165, 1, 0, 879, HexagonImpOpBase + 44, 0|(1ULL<<MCID::MayStore), 0x1b000000002aULL }, // Inst #2626 = SS2_storew_sp
4515 { 2625, 3, 0, 4, 51, 0, 0, 874, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x13000000002aULL }, // Inst #2625 = SS2_storeh_io
4516 { 2624, 2, 0, 4, 165, 1, 0, 877, HexagonImpOpBase + 44, 0|(1ULL<<MCID::MayStore), 0x23000000002aULL }, // Inst #2624 = SS2_stored_sp
4517 { 2623, 2, 0, 4, 206, 0, 0, 615, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0xb000000002aULL }, // Inst #2623 = SS2_storebi1
4518 { 2622, 2, 0, 4, 206, 0, 0, 615, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0xb000000002aULL }, // Inst #2622 = SS2_storebi0
4519 { 2621, 1, 0, 4, 205, 5, 2, 0, HexagonImpOpBase + 161, 0|(1ULL<<MCID::MayStore), 0x23000000002aULL }, // Inst #2621 = SS2_allocframe
4520 { 2620, 3, 0, 4, 51, 0, 0, 874, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x1b000000002aULL }, // Inst #2620 = SS1_storew_io
4521 { 2619, 3, 0, 4, 51, 0, 0, 874, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0xb000000002aULL }, // Inst #2619 = SS1_storeb_io
4522 { 2618, 0, 0, 4, 204, 3, 4, 1, HexagonImpOpBase + 154, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0x20900000142aULL }, // Inst #2618 = SL2_return_tnew
4523 { 2617, 0, 0, 4, 204, 3, 4, 1, HexagonImpOpBase + 154, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0x20900000042aULL }, // Inst #2617 = SL2_return_t
4524 { 2616, 0, 0, 4, 204, 3, 4, 1, HexagonImpOpBase + 154, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0x209000001c2aULL }, // Inst #2616 = SL2_return_fnew
4525 { 2615, 0, 0, 4, 204, 3, 4, 1, HexagonImpOpBase + 154, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0x209000000c2aULL }, // Inst #2615 = SL2_return_f
4526 { 2614, 0, 0, 4, 204, 2, 4, 1, HexagonImpOpBase + 148, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0x20900000002aULL }, // Inst #2614 = SL2_return
4527 { 2613, 3, 1, 4, 19, 0, 0, 609, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x13000000802aULL }, // Inst #2613 = SL2_loadruh_io
4528 { 2612, 2, 1, 4, 147, 1, 0, 615, HexagonImpOpBase + 44, 0|(1ULL<<MCID::MayLoad), 0x1b000000802aULL }, // Inst #2612 = SL2_loadri_sp
4529 { 2611, 3, 1, 4, 19, 0, 0, 609, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x13000000802aULL }, // Inst #2611 = SL2_loadrh_io
4530 { 2610, 2, 1, 4, 147, 1, 0, 870, HexagonImpOpBase + 44, 0|(1ULL<<MCID::MayLoad), 0x23000000802aULL }, // Inst #2610 = SL2_loadrd_sp
4531 { 2609, 3, 1, 4, 19, 0, 0, 609, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0xb000000802aULL }, // Inst #2609 = SL2_loadrb_io
4532 { 2608, 0, 0, 4, 203, 2, 1, 1, HexagonImpOpBase + 145, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x100000142aULL }, // Inst #2608 = SL2_jumpr31_tnew
4533 { 2607, 0, 0, 4, 203, 2, 1, 1, HexagonImpOpBase + 145, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x100000042aULL }, // Inst #2607 = SL2_jumpr31_t
4534 { 2606, 0, 0, 4, 203, 2, 1, 1, HexagonImpOpBase + 145, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x1000001c2aULL }, // Inst #2606 = SL2_jumpr31_fnew
4535 { 2605, 0, 0, 4, 203, 2, 1, 1, HexagonImpOpBase + 145, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x1000000c2aULL }, // Inst #2605 = SL2_jumpr31_f
4536 { 2604, 0, 0, 4, 203, 1, 1, 1, HexagonImpOpBase + 143, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x100000002aULL }, // Inst #2604 = SL2_jumpr31
4537 { 2603, 0, 0, 4, 202, 2, 3, 1, HexagonImpOpBase + 138, 0|(1ULL<<MCID::MayLoad), 0x20000000002aULL }, // Inst #2603 = SL2_deallocframe
4538 { 2602, 3, 1, 4, 19, 0, 0, 609, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0xb000000802aULL }, // Inst #2602 = SL1_loadrub_io
4539 { 2601, 3, 1, 4, 19, 0, 0, 609, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x1b000000802aULL }, // Inst #2601 = SL1_loadri_io
4540 { 2600, 1, 0, 4, 35, 2, 3, 0, HexagonImpOpBase + 133, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0xb10800023ULL }, // Inst #2600 = SAVE_REGISTERS_CALL_V4_PIC
4541 { 2599, 1, 0, 4, 35, 2, 3, 0, HexagonImpOpBase + 133, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0xb11800023ULL }, // Inst #2599 = SAVE_REGISTERS_CALL_V4_EXT_PIC
4542 { 2598, 1, 0, 4, 35, 2, 0, 0, HexagonImpOpBase + 122, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0xb11800023ULL }, // Inst #2598 = SAVE_REGISTERS_CALL_V4_EXT
4543 { 2597, 1, 0, 4, 35, 2, 4, 0, HexagonImpOpBase + 127, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0xb10800023ULL }, // Inst #2597 = SAVE_REGISTERS_CALL_V4STK_PIC
4544 { 2596, 1, 0, 4, 35, 2, 4, 0, HexagonImpOpBase + 127, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0xb11800023ULL }, // Inst #2596 = SAVE_REGISTERS_CALL_V4STK_EXT_PIC
4545 { 2595, 1, 0, 4, 35, 2, 1, 0, HexagonImpOpBase + 124, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0xb11800023ULL }, // Inst #2595 = SAVE_REGISTERS_CALL_V4STK_EXT
4546 { 2594, 1, 0, 4, 35, 2, 1, 0, HexagonImpOpBase + 124, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0xb10800023ULL }, // Inst #2594 = SAVE_REGISTERS_CALL_V4STK
4547 { 2593, 1, 0, 4, 35, 2, 0, 0, HexagonImpOpBase + 122, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0xb10800023ULL }, // Inst #2593 = SAVE_REGISTERS_CALL_V4
4548 { 2592, 2, 1, 4, 198, 0, 0, 867, HexagonImpOpBase + 0, 0, 0x802aULL }, // Inst #2592 = SA1_zxth
4549 { 2591, 2, 1, 4, 198, 0, 0, 867, HexagonImpOpBase + 0, 0, 0x802aULL }, // Inst #2591 = SA1_zxtb
4550 { 2590, 2, 1, 4, 198, 0, 0, 867, HexagonImpOpBase + 0, 0, 0x802aULL }, // Inst #2590 = SA1_tfr
4551 { 2589, 2, 1, 4, 198, 0, 0, 867, HexagonImpOpBase + 0, 0, 0x802aULL }, // Inst #2589 = SA1_sxth
4552 { 2588, 2, 1, 4, 198, 0, 0, 867, HexagonImpOpBase + 0, 0, 0x802aULL }, // Inst #2588 = SA1_sxtb
4553 { 2587, 2, 1, 4, 198, 0, 0, 615, HexagonImpOpBase + 0, 0, 0x802aULL }, // Inst #2587 = SA1_setin1
4554 { 2586, 2, 1, 4, 198, 0, 0, 615, HexagonImpOpBase + 0, 0, 0xc280802aULL }, // Inst #2586 = SA1_seti
4555 { 2585, 2, 1, 4, 198, 0, 0, 867, HexagonImpOpBase + 0, 0, 0x802aULL }, // Inst #2585 = SA1_inc
4556 { 2584, 3, 1, 4, 197, 0, 0, 609, HexagonImpOpBase + 0, 0, 0x802aULL }, // Inst #2584 = SA1_dec
4557 { 2583, 2, 1, 4, 198, 0, 0, 872, HexagonImpOpBase + 0, 0, 0x802aULL }, // Inst #2583 = SA1_combinezr
4558 { 2582, 2, 1, 4, 198, 0, 0, 872, HexagonImpOpBase + 0, 0, 0x802aULL }, // Inst #2582 = SA1_combinerz
4559 { 2581, 2, 1, 4, 198, 0, 0, 870, HexagonImpOpBase + 0, 0, 0x802aULL }, // Inst #2581 = SA1_combine3i
4560 { 2580, 2, 1, 4, 198, 0, 0, 870, HexagonImpOpBase + 0, 0, 0x802aULL }, // Inst #2580 = SA1_combine2i
4561 { 2579, 2, 1, 4, 198, 0, 0, 870, HexagonImpOpBase + 0, 0, 0x802aULL }, // Inst #2579 = SA1_combine1i
4562 { 2578, 2, 1, 4, 198, 0, 0, 870, HexagonImpOpBase + 0, 0, 0x802aULL }, // Inst #2578 = SA1_combine0i
4563 { 2577, 2, 0, 4, 201, 0, 1, 615, HexagonImpOpBase + 121, 0, 0x2aULL }, // Inst #2577 = SA1_cmpeqi
4564 { 2576, 1, 1, 4, 200, 1, 0, 869, HexagonImpOpBase + 121, 0, 0x942aULL }, // Inst #2576 = SA1_clrtnew
4565 { 2575, 1, 1, 4, 199, 1, 0, 869, HexagonImpOpBase + 121, 0, 0x842aULL }, // Inst #2575 = SA1_clrt
4566 { 2574, 1, 1, 4, 200, 1, 0, 869, HexagonImpOpBase + 121, 0, 0x9c2aULL }, // Inst #2574 = SA1_clrfnew
4567 { 2573, 1, 1, 4, 199, 1, 0, 869, HexagonImpOpBase + 121, 0, 0x8c2aULL }, // Inst #2573 = SA1_clrf
4568 { 2572, 2, 1, 4, 198, 0, 0, 867, HexagonImpOpBase + 0, 0, 0x802aULL }, // Inst #2572 = SA1_and1
4569 { 2571, 2, 1, 4, 198, 1, 0, 615, HexagonImpOpBase + 44, 0, 0x802aULL }, // Inst #2571 = SA1_addsp
4570 { 2570, 3, 1, 4, 197, 0, 0, 864, HexagonImpOpBase + 0, 0, 0x802aULL }, // Inst #2570 = SA1_addrx
4571 { 2569, 3, 1, 4, 197, 0, 0, 861, HexagonImpOpBase + 0, 0, 0xf480802aULL }, // Inst #2569 = SA1_addi
4572 { 2568, 3, 1, 4, 94, 0, 0, 169, HexagonImpOpBase + 0, 0, 0x2cULL }, // Inst #2568 = S6_vtrunohb_ppp
4573 { 2567, 3, 1, 4, 94, 0, 0, 169, HexagonImpOpBase + 0, 0, 0x2cULL }, // Inst #2567 = S6_vtrunehb_ppp
4574 { 2566, 2, 1, 4, 196, 0, 0, 190, HexagonImpOpBase + 0, 0, 0x2bULL }, // Inst #2566 = S6_vsplatrbp
4575 { 2565, 4, 1, 4, 195, 0, 0, 714, HexagonImpOpBase + 0, 0, 0x8000000000802bULL }, // Inst #2565 = S6_rol_i_r_xacc
4576 { 2564, 4, 1, 4, 195, 0, 0, 714, HexagonImpOpBase + 0, 0, 0x8000000000802bULL }, // Inst #2564 = S6_rol_i_r_or
4577 { 2563, 4, 1, 4, 195, 0, 0, 714, HexagonImpOpBase + 0, 0, 0x8000000000802bULL }, // Inst #2563 = S6_rol_i_r_nac
4578 { 2562, 4, 1, 4, 195, 0, 0, 714, HexagonImpOpBase + 0, 0, 0x8000000000802bULL }, // Inst #2562 = S6_rol_i_r_and
4579 { 2561, 4, 1, 4, 195, 0, 0, 714, HexagonImpOpBase + 0, 0, 0x8000000000802bULL }, // Inst #2561 = S6_rol_i_r_acc
4580 { 2560, 3, 1, 4, 94, 0, 0, 199, HexagonImpOpBase + 0, 0, 0x802bULL }, // Inst #2560 = S6_rol_i_r
4581 { 2559, 4, 1, 4, 195, 0, 0, 740, HexagonImpOpBase + 0, 0, 0x8000000000002bULL }, // Inst #2559 = S6_rol_i_p_xacc
4582 { 2558, 4, 1, 4, 195, 0, 0, 740, HexagonImpOpBase + 0, 0, 0x8000000000002bULL }, // Inst #2558 = S6_rol_i_p_or
4583 { 2557, 4, 1, 4, 195, 0, 0, 740, HexagonImpOpBase + 0, 0, 0x8000000000002bULL }, // Inst #2557 = S6_rol_i_p_nac
4584 { 2556, 4, 1, 4, 195, 0, 0, 740, HexagonImpOpBase + 0, 0, 0x8000000000002bULL }, // Inst #2556 = S6_rol_i_p_and
4585 { 2555, 4, 1, 4, 195, 0, 0, 740, HexagonImpOpBase + 0, 0, 0x8000000000002bULL }, // Inst #2555 = S6_rol_i_p_acc
4586 { 2554, 3, 1, 4, 94, 0, 0, 304, HexagonImpOpBase + 0, 0, 0x2bULL }, // Inst #2554 = S6_rol_i_p
4587 { 2553, 3, 1, 4, 48, 0, 0, 304, HexagonImpOpBase + 0, 0, 0x8000000000002bULL }, // Inst #2553 = S5_vasrhrnd
4588 { 2552, 2, 1, 4, 194, 0, 0, 307, HexagonImpOpBase + 0, 0, 0x8000000000802bULL }, // Inst #2552 = S5_popcountp
4589 { 2551, 3, 1, 4, 48, 0, 1, 314, HexagonImpOpBase + 63, 0, 0x8000000000802bULL }, // Inst #2551 = S5_asrhub_sat
4590 { 2550, 3, 1, 4, 48, 0, 1, 314, HexagonImpOpBase + 63, 0, 0x8000000000802bULL }, // Inst #2550 = S5_asrhub_rnd_sat
4591 { 2549, 3, 1, 4, 77, 0, 1, 169, HexagonImpOpBase + 63, 0, 0x8000000000002cULL }, // Inst #2549 = S4_vxsubaddw
4592 { 2548, 3, 1, 4, 48, 0, 1, 169, HexagonImpOpBase + 63, 0, 0x8000000000002cULL }, // Inst #2548 = S4_vxsubaddhr
4593 { 2547, 3, 1, 4, 77, 0, 1, 169, HexagonImpOpBase + 63, 0, 0x8000000000002cULL }, // Inst #2547 = S4_vxsubaddh
4594 { 2546, 3, 1, 4, 77, 0, 1, 169, HexagonImpOpBase + 63, 0, 0x8000000000002cULL }, // Inst #2546 = S4_vxaddsubw
4595 { 2545, 3, 1, 4, 48, 0, 1, 169, HexagonImpOpBase + 63, 0, 0x8000000000002cULL }, // Inst #2545 = S4_vxaddsubhr
4596 { 2544, 3, 1, 4, 77, 0, 1, 169, HexagonImpOpBase + 63, 0, 0x8000000000002cULL }, // Inst #2544 = S4_vxaddsubh
4597 { 2543, 5, 1, 4, 193, 0, 0, 856, HexagonImpOpBase + 0, 0, 0x8000000000002cULL }, // Inst #2543 = S4_vrcrotate_acc
4598 { 2542, 4, 1, 4, 192, 0, 0, 852, HexagonImpOpBase + 0, 0, 0x8000000000002cULL }, // Inst #2542 = S4_vrcrotate
4599 { 2541, 4, 1, 4, 161, 0, 0, 812, HexagonImpOpBase + 0, 0, 0x80000102808003ULL }, // Inst #2541 = S4_subi_lsr_ri
4600 { 2540, 4, 1, 4, 161, 0, 0, 812, HexagonImpOpBase + 0, 0, 0x80000102808003ULL }, // Inst #2540 = S4_subi_asl_ri
4601 { 2539, 4, 1, 4, 161, 0, 0, 726, HexagonImpOpBase + 0, 0, 0x800000d4808003ULL }, // Inst #2539 = S4_subaddi
4602 { 2538, 4, 0, 4, 191, 0, 0, 840, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x1c80c5934029ULL }, // Inst #2538 = S4_storerinew_ur
4603 { 2537, 4, 0, 4, 190, 0, 0, 726, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x1d8000134029ULL }, // Inst #2537 = S4_storerinew_rr
4604 { 2536, 3, 1, 4, 186, 0, 0, 510, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x1a80c3924029ULL }, // Inst #2536 = S4_storerinew_ap
4605 { 2535, 4, 0, 4, 189, 0, 0, 840, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x1c00c5880029ULL }, // Inst #2535 = S4_storeri_ur
4606 { 2534, 4, 0, 4, 188, 0, 0, 726, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x1d0000080029ULL }, // Inst #2534 = S4_storeri_rr
4607 { 2533, 3, 1, 4, 182, 0, 0, 510, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x1a00c3880029ULL }, // Inst #2533 = S4_storeri_ap
4608 { 2532, 4, 0, 4, 191, 0, 0, 840, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x1480c5934029ULL }, // Inst #2532 = S4_storerhnew_ur
4609 { 2531, 4, 0, 4, 190, 0, 0, 726, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x158000134029ULL }, // Inst #2531 = S4_storerhnew_rr
4610 { 2530, 3, 1, 4, 186, 0, 0, 510, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x1280c3924029ULL }, // Inst #2530 = S4_storerhnew_ap
4611 { 2529, 4, 0, 4, 189, 0, 0, 840, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x1400c5880029ULL }, // Inst #2529 = S4_storerh_ur
4612 { 2528, 4, 0, 4, 188, 0, 0, 726, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x150000080029ULL }, // Inst #2528 = S4_storerh_rr
4613 { 2527, 3, 1, 4, 182, 0, 0, 510, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x1200c3880029ULL }, // Inst #2527 = S4_storerh_ap
4614 { 2526, 4, 0, 4, 189, 0, 0, 840, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x1400c5800029ULL }, // Inst #2526 = S4_storerf_ur
4615 { 2525, 4, 0, 4, 188, 0, 0, 726, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x150000000029ULL }, // Inst #2525 = S4_storerf_rr
4616 { 2524, 3, 1, 4, 182, 0, 0, 510, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x1200c3800029ULL }, // Inst #2524 = S4_storerf_ap
4617 { 2523, 4, 0, 4, 189, 0, 0, 848, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x2400c5800029ULL }, // Inst #2523 = S4_storerd_ur
4618 { 2522, 4, 0, 4, 188, 0, 0, 844, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x250000000029ULL }, // Inst #2522 = S4_storerd_rr
4619 { 2521, 3, 1, 4, 182, 0, 0, 513, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x2200c3800029ULL }, // Inst #2521 = S4_storerd_ap
4620 { 2520, 4, 0, 4, 191, 0, 0, 840, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0xc80c5934029ULL }, // Inst #2520 = S4_storerbnew_ur
4621 { 2519, 4, 0, 4, 190, 0, 0, 726, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xd8000134029ULL }, // Inst #2519 = S4_storerbnew_rr
4622 { 2518, 3, 1, 4, 186, 0, 0, 510, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0xa80c3924029ULL }, // Inst #2518 = S4_storerbnew_ap
4623 { 2517, 4, 0, 4, 189, 0, 0, 840, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0xc00c5880029ULL }, // Inst #2517 = S4_storerb_ur
4624 { 2516, 4, 0, 4, 188, 0, 0, 726, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xd0000080029ULL }, // Inst #2516 = S4_storerb_rr
4625 { 2515, 3, 1, 4, 182, 0, 0, 510, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0xa00c3880029ULL }, // Inst #2515 = S4_storerb_ap
4626 { 2514, 4, 0, 4, 57, 0, 0, 836, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x1b00d6801429ULL }, // Inst #2514 = S4_storeiritnew_io
4627 { 2513, 4, 0, 4, 56, 0, 0, 836, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x1b00d6800429ULL }, // Inst #2513 = S4_storeirit_io
4628 { 2512, 4, 0, 4, 57, 0, 0, 836, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x1b00d6801c29ULL }, // Inst #2512 = S4_storeirifnew_io
4629 { 2511, 4, 0, 4, 56, 0, 0, 836, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x1b00d6800c29ULL }, // Inst #2511 = S4_storeirif_io
4630 { 2510, 3, 0, 4, 55, 0, 0, 516, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x1b0114800029ULL }, // Inst #2510 = S4_storeiri_io
4631 { 2509, 4, 0, 4, 57, 0, 0, 836, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x1300d6801429ULL }, // Inst #2509 = S4_storeirhtnew_io
4632 { 2508, 4, 0, 4, 56, 0, 0, 836, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x1300d6800429ULL }, // Inst #2508 = S4_storeirht_io
4633 { 2507, 4, 0, 4, 57, 0, 0, 836, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x1300d6801c29ULL }, // Inst #2507 = S4_storeirhfnew_io
4634 { 2506, 4, 0, 4, 56, 0, 0, 836, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x1300d6800c29ULL }, // Inst #2506 = S4_storeirhf_io
4635 { 2505, 3, 0, 4, 55, 0, 0, 516, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x130114800029ULL }, // Inst #2505 = S4_storeirh_io
4636 { 2504, 4, 0, 4, 57, 0, 0, 836, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0xb00d6801429ULL }, // Inst #2504 = S4_storeirbtnew_io
4637 { 2503, 4, 0, 4, 56, 0, 0, 836, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0xb00d6800429ULL }, // Inst #2503 = S4_storeirbt_io
4638 { 2502, 4, 0, 4, 57, 0, 0, 836, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0xb00d6801c29ULL }, // Inst #2502 = S4_storeirbfnew_io
4639 { 2501, 4, 0, 4, 56, 0, 0, 836, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0xb00d6800c29ULL }, // Inst #2501 = S4_storeirbf_io
4640 { 2500, 3, 0, 4, 55, 0, 0, 516, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xb0114800029ULL }, // Inst #2500 = S4_storeirb_io
4641 { 2499, 2, 0, 4, 178, 0, 0, 307, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x2000000000a9ULL }, // Inst #2499 = S4_stored_rl_st_vi
4642 { 2498, 2, 0, 4, 178, 0, 0, 307, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x2000000000a9ULL }, // Inst #2498 = S4_stored_rl_at_vi
4643 { 2497, 3, 1, 4, 177, 0, 0, 172, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x200000002129ULL }, // Inst #2497 = S4_stored_locked
4644 { 2496, 5, 0, 4, 183, 0, 0, 823, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x1d0000081429ULL }, // Inst #2496 = S4_pstoreritnew_rr
4645 { 2495, 4, 0, 4, 39, 0, 0, 760, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x1b090488142fULL }, // Inst #2495 = S4_pstoreritnew_io
4646 { 2494, 3, 0, 4, 182, 0, 0, 820, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x1900c3881429ULL }, // Inst #2494 = S4_pstoreritnew_abs
4647 { 2493, 5, 0, 4, 181, 0, 0, 823, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x1d0000080429ULL }, // Inst #2493 = S4_pstorerit_rr
4648 { 2492, 3, 0, 4, 180, 0, 0, 820, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x1900c3880429ULL }, // Inst #2492 = S4_pstorerit_abs
4649 { 2491, 5, 0, 4, 187, 0, 0, 823, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x1d8000145429ULL }, // Inst #2491 = S4_pstorerinewtnew_rr
4650 { 2490, 4, 0, 4, 54, 0, 0, 760, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x1b890493542fULL }, // Inst #2490 = S4_pstorerinewtnew_io
4651 { 2489, 3, 0, 4, 186, 0, 0, 820, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x1980c3925429ULL }, // Inst #2489 = S4_pstorerinewtnew_abs
4652 { 2488, 5, 0, 4, 185, 0, 0, 823, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x1d8000144429ULL }, // Inst #2488 = S4_pstorerinewt_rr
4653 { 2487, 3, 0, 4, 184, 0, 0, 820, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x1980c3924429ULL }, // Inst #2487 = S4_pstorerinewt_abs
4654 { 2486, 5, 0, 4, 187, 0, 0, 823, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x1d8000145c29ULL }, // Inst #2486 = S4_pstorerinewfnew_rr
4655 { 2485, 4, 0, 4, 54, 0, 0, 760, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x1b8904935c2fULL }, // Inst #2485 = S4_pstorerinewfnew_io
4656 { 2484, 3, 0, 4, 186, 0, 0, 820, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x1980c3925c29ULL }, // Inst #2484 = S4_pstorerinewfnew_abs
4657 { 2483, 5, 0, 4, 185, 0, 0, 823, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x1d8000144c29ULL }, // Inst #2483 = S4_pstorerinewf_rr
4658 { 2482, 3, 0, 4, 184, 0, 0, 820, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x1980c3924c29ULL }, // Inst #2482 = S4_pstorerinewf_abs
4659 { 2481, 5, 0, 4, 183, 0, 0, 823, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x1d0000081c29ULL }, // Inst #2481 = S4_pstorerifnew_rr
4660 { 2480, 4, 0, 4, 39, 0, 0, 760, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x1b0904881c2fULL }, // Inst #2480 = S4_pstorerifnew_io
4661 { 2479, 3, 0, 4, 182, 0, 0, 820, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x1900c3881c29ULL }, // Inst #2479 = S4_pstorerifnew_abs
4662 { 2478, 5, 0, 4, 181, 0, 0, 823, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x1d0000080c29ULL }, // Inst #2478 = S4_pstorerif_rr
4663 { 2477, 3, 0, 4, 180, 0, 0, 820, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x1900c3880c29ULL }, // Inst #2477 = S4_pstorerif_abs
4664 { 2476, 5, 0, 4, 183, 0, 0, 823, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x150000081429ULL }, // Inst #2476 = S4_pstorerhtnew_rr
4665 { 2475, 4, 0, 4, 39, 0, 0, 760, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x1304e488142fULL }, // Inst #2475 = S4_pstorerhtnew_io
4666 { 2474, 3, 0, 4, 182, 0, 0, 820, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x1100c3881429ULL }, // Inst #2474 = S4_pstorerhtnew_abs
4667 { 2473, 5, 0, 4, 181, 0, 0, 823, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x150000080429ULL }, // Inst #2473 = S4_pstorerht_rr
4668 { 2472, 3, 0, 4, 180, 0, 0, 820, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x1100c3880429ULL }, // Inst #2472 = S4_pstorerht_abs
4669 { 2471, 5, 0, 4, 187, 0, 0, 823, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x158000145429ULL }, // Inst #2471 = S4_pstorerhnewtnew_rr
4670 { 2470, 4, 0, 4, 54, 0, 0, 760, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x1384e493542fULL }, // Inst #2470 = S4_pstorerhnewtnew_io
4671 { 2469, 3, 0, 4, 186, 0, 0, 820, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x1180c3925429ULL }, // Inst #2469 = S4_pstorerhnewtnew_abs
4672 { 2468, 5, 0, 4, 185, 0, 0, 823, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x158000144429ULL }, // Inst #2468 = S4_pstorerhnewt_rr
4673 { 2467, 3, 0, 4, 184, 0, 0, 820, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x1180c3924429ULL }, // Inst #2467 = S4_pstorerhnewt_abs
4674 { 2466, 5, 0, 4, 187, 0, 0, 823, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x158000145c29ULL }, // Inst #2466 = S4_pstorerhnewfnew_rr
4675 { 2465, 4, 0, 4, 54, 0, 0, 760, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x1384e4935c2fULL }, // Inst #2465 = S4_pstorerhnewfnew_io
4676 { 2464, 3, 0, 4, 186, 0, 0, 820, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x1180c3925c29ULL }, // Inst #2464 = S4_pstorerhnewfnew_abs
4677 { 2463, 5, 0, 4, 185, 0, 0, 823, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x158000144c29ULL }, // Inst #2463 = S4_pstorerhnewf_rr
4678 { 2462, 3, 0, 4, 184, 0, 0, 820, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x1180c3924c29ULL }, // Inst #2462 = S4_pstorerhnewf_abs
4679 { 2461, 5, 0, 4, 183, 0, 0, 823, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x150000081c29ULL }, // Inst #2461 = S4_pstorerhfnew_rr
4680 { 2460, 4, 0, 4, 39, 0, 0, 760, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x1304e4881c2fULL }, // Inst #2460 = S4_pstorerhfnew_io
4681 { 2459, 3, 0, 4, 182, 0, 0, 820, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x1100c3881c29ULL }, // Inst #2459 = S4_pstorerhfnew_abs
4682 { 2458, 5, 0, 4, 181, 0, 0, 823, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x150000080c29ULL }, // Inst #2458 = S4_pstorerhf_rr
4683 { 2457, 3, 0, 4, 180, 0, 0, 820, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x1100c3880c29ULL }, // Inst #2457 = S4_pstorerhf_abs
4684 { 2456, 5, 0, 4, 183, 0, 0, 823, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x150000001429ULL }, // Inst #2456 = S4_pstorerftnew_rr
4685 { 2455, 4, 0, 4, 39, 0, 0, 760, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x1304e480142fULL }, // Inst #2455 = S4_pstorerftnew_io
4686 { 2454, 3, 0, 4, 182, 0, 0, 820, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x1100c3801429ULL }, // Inst #2454 = S4_pstorerftnew_abs
4687 { 2453, 5, 0, 4, 181, 0, 0, 823, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x150000000429ULL }, // Inst #2453 = S4_pstorerft_rr
4688 { 2452, 3, 0, 4, 180, 0, 0, 820, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x1100c3800429ULL }, // Inst #2452 = S4_pstorerft_abs
4689 { 2451, 5, 0, 4, 183, 0, 0, 823, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x150000001c29ULL }, // Inst #2451 = S4_pstorerffnew_rr
4690 { 2450, 4, 0, 4, 39, 0, 0, 760, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x1304e4801c2fULL }, // Inst #2450 = S4_pstorerffnew_io
4691 { 2449, 3, 0, 4, 182, 0, 0, 820, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x1100c3801c29ULL }, // Inst #2449 = S4_pstorerffnew_abs
4692 { 2448, 5, 0, 4, 181, 0, 0, 823, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x150000000c29ULL }, // Inst #2448 = S4_pstorerff_rr
4693 { 2447, 3, 0, 4, 180, 0, 0, 820, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x1100c3800c29ULL }, // Inst #2447 = S4_pstorerff_abs
4694 { 2446, 5, 0, 4, 183, 0, 0, 831, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x250000001429ULL }, // Inst #2446 = S4_pstorerdtnew_rr
4695 { 2445, 4, 0, 4, 39, 0, 0, 769, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x230d2480142fULL }, // Inst #2445 = S4_pstorerdtnew_io
4696 { 2444, 3, 0, 4, 182, 0, 0, 828, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x2100c3801429ULL }, // Inst #2444 = S4_pstorerdtnew_abs
4697 { 2443, 5, 0, 4, 181, 0, 0, 831, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x250000000429ULL }, // Inst #2443 = S4_pstorerdt_rr
4698 { 2442, 3, 0, 4, 180, 0, 0, 828, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x2100c3800429ULL }, // Inst #2442 = S4_pstorerdt_abs
4699 { 2441, 5, 0, 4, 183, 0, 0, 831, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x250000001c29ULL }, // Inst #2441 = S4_pstorerdfnew_rr
4700 { 2440, 4, 0, 4, 39, 0, 0, 769, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x230d24801c2fULL }, // Inst #2440 = S4_pstorerdfnew_io
4701 { 2439, 3, 0, 4, 182, 0, 0, 828, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x2100c3801c29ULL }, // Inst #2439 = S4_pstorerdfnew_abs
4702 { 2438, 5, 0, 4, 181, 0, 0, 831, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x250000000c29ULL }, // Inst #2438 = S4_pstorerdf_rr
4703 { 2437, 3, 0, 4, 180, 0, 0, 828, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x2100c3800c29ULL }, // Inst #2437 = S4_pstorerdf_abs
4704 { 2436, 5, 0, 4, 183, 0, 0, 823, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0xd0000081429ULL }, // Inst #2436 = S4_pstorerbtnew_rr
4705 { 2435, 4, 0, 4, 39, 0, 0, 760, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0xb00c488142fULL }, // Inst #2435 = S4_pstorerbtnew_io
4706 { 2434, 3, 0, 4, 182, 0, 0, 820, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x900c3881429ULL }, // Inst #2434 = S4_pstorerbtnew_abs
4707 { 2433, 5, 0, 4, 181, 0, 0, 823, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0xd0000080429ULL }, // Inst #2433 = S4_pstorerbt_rr
4708 { 2432, 3, 0, 4, 180, 0, 0, 820, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x900c3880429ULL }, // Inst #2432 = S4_pstorerbt_abs
4709 { 2431, 5, 0, 4, 187, 0, 0, 823, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0xd8000145429ULL }, // Inst #2431 = S4_pstorerbnewtnew_rr
4710 { 2430, 4, 0, 4, 54, 0, 0, 760, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0xb80c493542fULL }, // Inst #2430 = S4_pstorerbnewtnew_io
4711 { 2429, 3, 0, 4, 186, 0, 0, 820, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x980c3925429ULL }, // Inst #2429 = S4_pstorerbnewtnew_abs
4712 { 2428, 5, 0, 4, 185, 0, 0, 823, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0xd8000144429ULL }, // Inst #2428 = S4_pstorerbnewt_rr
4713 { 2427, 3, 0, 4, 184, 0, 0, 820, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x980c3924429ULL }, // Inst #2427 = S4_pstorerbnewt_abs
4714 { 2426, 5, 0, 4, 187, 0, 0, 823, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0xd8000145c29ULL }, // Inst #2426 = S4_pstorerbnewfnew_rr
4715 { 2425, 4, 0, 4, 54, 0, 0, 760, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0xb80c4935c2fULL }, // Inst #2425 = S4_pstorerbnewfnew_io
4716 { 2424, 3, 0, 4, 186, 0, 0, 820, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x980c3925c29ULL }, // Inst #2424 = S4_pstorerbnewfnew_abs
4717 { 2423, 5, 0, 4, 185, 0, 0, 823, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0xd8000144c29ULL }, // Inst #2423 = S4_pstorerbnewf_rr
4718 { 2422, 3, 0, 4, 184, 0, 0, 820, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x980c3924c29ULL }, // Inst #2422 = S4_pstorerbnewf_abs
4719 { 2421, 5, 0, 4, 183, 0, 0, 823, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0xd0000081c29ULL }, // Inst #2421 = S4_pstorerbfnew_rr
4720 { 2420, 4, 0, 4, 39, 0, 0, 760, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0xb00c4881c2fULL }, // Inst #2420 = S4_pstorerbfnew_io
4721 { 2419, 3, 0, 4, 182, 0, 0, 820, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x900c3881c29ULL }, // Inst #2419 = S4_pstorerbfnew_abs
4722 { 2418, 5, 0, 4, 181, 0, 0, 823, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0xd0000080c29ULL }, // Inst #2418 = S4_pstorerbf_rr
4723 { 2417, 3, 0, 4, 180, 0, 0, 820, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x900c3880c29ULL }, // Inst #2417 = S4_pstorerbf_abs
4724 { 2416, 3, 1, 4, 170, 0, 0, 202, HexagonImpOpBase + 0, 0, 0x80000000008003ULL }, // Inst #2416 = S4_parity
4725 { 2415, 4, 1, 4, 163, 0, 0, 812, HexagonImpOpBase + 0, 0, 0x80000102808003ULL }, // Inst #2415 = S4_ori_lsr_ri
4726 { 2414, 4, 1, 4, 163, 0, 0, 812, HexagonImpOpBase + 0, 0, 0x80000102808003ULL }, // Inst #2414 = S4_ori_asl_ri
4727 { 2413, 4, 1, 4, 163, 0, 0, 714, HexagonImpOpBase + 0, 0, 0x80000156808003ULL }, // Inst #2413 = S4_or_ori
4728 { 2412, 4, 1, 4, 163, 0, 0, 816, HexagonImpOpBase + 0, 0, 0x80000156808003ULL }, // Inst #2412 = S4_or_andix
4729 { 2411, 4, 1, 4, 163, 0, 0, 714, HexagonImpOpBase + 0, 0, 0x80000156808003ULL }, // Inst #2411 = S4_or_andi
4730 { 2410, 3, 1, 4, 9, 0, 0, 178, HexagonImpOpBase + 0, 0, 0x2cULL }, // Inst #2410 = S4_ntstbit_r
4731 { 2409, 3, 1, 4, 89, 0, 0, 175, HexagonImpOpBase + 0, 0, 0x2bULL }, // Inst #2409 = S4_ntstbit_i
4732 { 2408, 3, 1, 4, 8, 0, 0, 510, HexagonImpOpBase + 0, 0, 0x802cULL }, // Inst #2408 = S4_lsli
4733 { 2407, 3, 1, 4, 170, 0, 0, 169, HexagonImpOpBase + 0, 0, 0x8000000000002cULL }, // Inst #2407 = S4_extractp_rp
4734 { 2406, 4, 1, 4, 161, 0, 0, 747, HexagonImpOpBase + 0, 0, 0x8000000000002bULL }, // Inst #2406 = S4_extractp
4735 { 2405, 3, 1, 4, 170, 0, 0, 744, HexagonImpOpBase + 0, 0, 0x8000000000802cULL }, // Inst #2405 = S4_extract_rp
4736 { 2404, 4, 1, 4, 161, 0, 0, 686, HexagonImpOpBase + 0, 0, 0x8000000000802bULL }, // Inst #2404 = S4_extract
4737 { 2403, 2, 1, 4, 168, 0, 0, 307, HexagonImpOpBase + 0, 0, 0x8000000000802bULL }, // Inst #2403 = S4_clbpnorm
4738 { 2402, 3, 1, 4, 170, 0, 0, 314, HexagonImpOpBase + 0, 0, 0x8000000000802bULL }, // Inst #2402 = S4_clbpaddi
4739 { 2401, 3, 1, 4, 170, 0, 0, 199, HexagonImpOpBase + 0, 0, 0x8000000000802bULL }, // Inst #2401 = S4_clbaddi
4740 { 2400, 4, 1, 4, 163, 0, 0, 812, HexagonImpOpBase + 0, 0, 0x80000102808003ULL }, // Inst #2400 = S4_andi_lsr_ri
4741 { 2399, 4, 1, 4, 163, 0, 0, 812, HexagonImpOpBase + 0, 0, 0x80000102808003ULL }, // Inst #2399 = S4_andi_asl_ri
4742 { 2398, 4, 1, 4, 161, 0, 0, 812, HexagonImpOpBase + 0, 0, 0x80000102808003ULL }, // Inst #2398 = S4_addi_lsr_ri
4743 { 2397, 4, 1, 4, 161, 0, 0, 812, HexagonImpOpBase + 0, 0, 0x80000102808003ULL }, // Inst #2397 = S4_addi_asl_ri
4744 { 2396, 4, 1, 4, 161, 0, 0, 219, HexagonImpOpBase + 0, 0, 0x800000d6808003ULL }, // Inst #2396 = S4_addaddi
4745 { 2395, 2, 1, 4, 80, 0, 0, 190, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x2bULL }, // Inst #2395 = S2_vzxthw
4746 { 2394, 2, 1, 4, 80, 0, 0, 190, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x2bULL }, // Inst #2394 = S2_vzxtbh
4747 { 2393, 3, 1, 4, 8, 0, 0, 169, HexagonImpOpBase + 0, 0, 0x2cULL }, // Inst #2393 = S2_vtrunowh
4748 { 2392, 2, 1, 4, 80, 0, 0, 307, HexagonImpOpBase + 0, 0, 0x802bULL }, // Inst #2392 = S2_vtrunohb
4749 { 2391, 3, 1, 4, 8, 0, 0, 169, HexagonImpOpBase + 0, 0, 0x2cULL }, // Inst #2391 = S2_vtrunewh
4750 { 2390, 2, 1, 4, 80, 0, 0, 307, HexagonImpOpBase + 0, 0, 0x802bULL }, // Inst #2390 = S2_vtrunehb
4751 { 2389, 2, 1, 4, 80, 0, 0, 190, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x2bULL }, // Inst #2389 = S2_vsxthw
4752 { 2388, 2, 1, 4, 80, 0, 0, 190, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x2bULL }, // Inst #2388 = S2_vsxtbh
4753 { 2387, 4, 1, 4, 100, 0, 0, 808, HexagonImpOpBase + 0, 0, 0x2cULL }, // Inst #2387 = S2_vsplicerb
4754 { 2386, 4, 1, 4, 100, 0, 0, 804, HexagonImpOpBase + 0, 0, 0x2cULL }, // Inst #2386 = S2_vspliceib
4755 { 2385, 2, 1, 4, 80, 0, 0, 190, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x2bULL }, // Inst #2385 = S2_vsplatrh
4756 { 2384, 2, 1, 4, 80, 0, 0, 157, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x802bULL }, // Inst #2384 = S2_vsplatrb
4757 { 2383, 2, 1, 4, 80, 0, 1, 162, HexagonImpOpBase + 63, 0, 0x2bULL }, // Inst #2383 = S2_vsatwuh_nopack
4758 { 2382, 2, 1, 4, 80, 0, 1, 307, HexagonImpOpBase + 63, 0, 0x802bULL }, // Inst #2382 = S2_vsatwuh
4759 { 2381, 2, 1, 4, 80, 0, 1, 162, HexagonImpOpBase + 63, 0, 0x2bULL }, // Inst #2381 = S2_vsatwh_nopack
4760 { 2380, 2, 1, 4, 80, 0, 1, 307, HexagonImpOpBase + 63, 0, 0x802bULL }, // Inst #2380 = S2_vsatwh
4761 { 2379, 2, 1, 4, 80, 0, 1, 162, HexagonImpOpBase + 63, 0, 0x2bULL }, // Inst #2379 = S2_vsathub_nopack
4762 { 2378, 2, 1, 4, 80, 0, 1, 307, HexagonImpOpBase + 63, 0, 0x802bULL }, // Inst #2378 = S2_vsathub
4763 { 2377, 2, 1, 4, 80, 0, 1, 162, HexagonImpOpBase + 63, 0, 0x2bULL }, // Inst #2377 = S2_vsathb_nopack
4764 { 2376, 2, 1, 4, 80, 0, 1, 307, HexagonImpOpBase + 63, 0, 0x802bULL }, // Inst #2376 = S2_vsathb
4765 { 2375, 2, 1, 4, 76, 0, 1, 307, HexagonImpOpBase + 63, 0, 0x8000000000802bULL }, // Inst #2375 = S2_vrndpackwhs
4766 { 2374, 2, 1, 4, 179, 0, 0, 307, HexagonImpOpBase + 0, 0, 0x8000000000802bULL }, // Inst #2374 = S2_vrndpackwh
4767 { 2373, 4, 1, 4, 32, 0, 0, 205, HexagonImpOpBase + 0, 0, 0x8000000000002cULL }, // Inst #2373 = S2_vrcnegh
4768 { 2372, 3, 1, 4, 48, 0, 1, 209, HexagonImpOpBase + 63, 0, 0x8000000000002cULL }, // Inst #2372 = S2_vcrotate
4769 { 2371, 3, 1, 4, 77, 0, 1, 209, HexagonImpOpBase + 63, 0, 0x8000000000002cULL }, // Inst #2371 = S2_vcnegh
4770 { 2370, 4, 1, 4, 100, 0, 0, 808, HexagonImpOpBase + 0, 0, 0x2cULL }, // Inst #2370 = S2_valignrb
4771 { 2369, 4, 1, 4, 100, 0, 0, 804, HexagonImpOpBase + 0, 0, 0x2cULL }, // Inst #2369 = S2_valignib
4772 { 2368, 3, 1, 4, 9, 0, 0, 178, HexagonImpOpBase + 0, 0, 0x2cULL }, // Inst #2368 = S2_tstbit_r
4773 { 2367, 3, 1, 4, 89, 0, 0, 175, HexagonImpOpBase + 0, 0, 0x2bULL }, // Inst #2367 = S2_tstbit_i
4774 { 2366, 3, 1, 4, 8, 0, 0, 202, HexagonImpOpBase + 0, 0, 0x802cULL }, // Inst #2366 = S2_togglebit_r
4775 { 2365, 3, 1, 4, 8, 0, 0, 199, HexagonImpOpBase + 0, 0, 0x802bULL }, // Inst #2365 = S2_togglebit_i
4776 { 2364, 5, 1, 4, 53, 0, 0, 309, HexagonImpOpBase + 0, 0, 0x8000000000802bULL }, // Inst #2364 = S2_tableidxw
4777 { 2363, 5, 1, 4, 53, 0, 0, 309, HexagonImpOpBase + 0, 0, 0x8000000000802bULL }, // Inst #2363 = S2_tableidxh
4778 { 2362, 5, 1, 4, 53, 0, 0, 309, HexagonImpOpBase + 0, 0, 0x8000000000802bULL }, // Inst #2362 = S2_tableidxd
4779 { 2361, 5, 1, 4, 53, 0, 0, 309, HexagonImpOpBase + 0, 0, 0x8000000000802bULL }, // Inst #2361 = S2_tableidxb
4780 { 2360, 2, 1, 4, 80, 0, 1, 157, HexagonImpOpBase + 63, 0, 0x802bULL }, // Inst #2360 = S2_svsathub
4781 { 2359, 2, 1, 4, 80, 0, 1, 157, HexagonImpOpBase + 63, 0, 0x802bULL }, // Inst #2359 = S2_svsathb
4782 { 2358, 2, 0, 4, 178, 0, 0, 157, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x1800000000a9ULL }, // Inst #2358 = S2_storew_rl_st_vi
4783 { 2357, 2, 0, 4, 178, 0, 0, 157, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x1800000000a9ULL }, // Inst #2357 = S2_storew_rl_at_vi
4784 { 2356, 3, 1, 4, 177, 0, 0, 178, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x180000002129ULL }, // Inst #2356 = S2_storew_locked
4785 { 2355, 2, 0, 4, 166, 1, 0, 607, HexagonImpOpBase + 101, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x188a4011402fULL }, // Inst #2355 = S2_storerinewgp
4786 { 2354, 4, 1, 4, 54, 0, 0, 778, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x1e8000134029ULL }, // Inst #2354 = S2_storerinew_pr
4787 { 2353, 4, 1, 4, 54, 0, 0, 787, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x1e8000134029ULL }, // Inst #2353 = S2_storerinew_pi
4788 { 2352, 4, 1, 4, 54, 1, 0, 778, HexagonImpOpBase + 100, 0|(1ULL<<MCID::MayStore), 0x1e8000134029ULL }, // Inst #2352 = S2_storerinew_pcr
4789 { 2351, 5, 1, 4, 176, 1, 0, 782, HexagonImpOpBase + 100, 0|(1ULL<<MCID::MayStore), 0x1e8000144029ULL }, // Inst #2351 = S2_storerinew_pci
4790 { 2350, 4, 1, 4, 54, 0, 0, 778, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x1e8000134029ULL }, // Inst #2350 = S2_storerinew_pbr
4791 { 2349, 3, 0, 4, 52, 0, 0, 510, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x1b89b2924029ULL }, // Inst #2349 = S2_storerinew_io
4792 { 2348, 2, 0, 4, 165, 1, 0, 607, HexagonImpOpBase + 101, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x180a4008002fULL }, // Inst #2348 = S2_storerigp
4793 { 2347, 4, 1, 4, 39, 0, 0, 778, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x1e0000080029ULL }, // Inst #2347 = S2_storeri_pr
4794 { 2346, 4, 1, 4, 39, 0, 0, 787, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x1e0000080029ULL }, // Inst #2346 = S2_storeri_pi
4795 { 2345, 4, 1, 4, 39, 1, 0, 778, HexagonImpOpBase + 100, 0|(1ULL<<MCID::MayStore), 0x1e0000080029ULL }, // Inst #2345 = S2_storeri_pcr
4796 { 2344, 5, 1, 4, 38, 1, 0, 782, HexagonImpOpBase + 100, 0|(1ULL<<MCID::MayStore), 0x1e0000080029ULL }, // Inst #2344 = S2_storeri_pci
4797 { 2343, 4, 1, 4, 39, 0, 0, 778, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x1e0000080029ULL }, // Inst #2343 = S2_storeri_pbr
4798 { 2342, 3, 0, 4, 51, 0, 0, 510, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x1b09b2880029ULL }, // Inst #2342 = S2_storeri_io
4799 { 2341, 2, 0, 4, 166, 1, 0, 607, HexagonImpOpBase + 101, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x10862011402fULL }, // Inst #2341 = S2_storerhnewgp
4800 { 2340, 4, 1, 4, 54, 0, 0, 778, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x168000134029ULL }, // Inst #2340 = S2_storerhnew_pr
4801 { 2339, 4, 1, 4, 54, 0, 0, 787, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x1680001b4029ULL }, // Inst #2339 = S2_storerhnew_pi
4802 { 2338, 4, 1, 4, 54, 1, 0, 778, HexagonImpOpBase + 100, 0|(1ULL<<MCID::MayStore), 0x168000134029ULL }, // Inst #2338 = S2_storerhnew_pcr
4803 { 2337, 5, 1, 4, 176, 1, 0, 782, HexagonImpOpBase + 100, 0|(1ULL<<MCID::MayStore), 0x168000144029ULL }, // Inst #2337 = S2_storerhnew_pci
4804 { 2336, 4, 1, 4, 54, 0, 0, 778, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x168000134029ULL }, // Inst #2336 = S2_storerhnew_pbr
4805 { 2335, 3, 0, 4, 52, 0, 0, 510, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x138592924029ULL }, // Inst #2335 = S2_storerhnew_io
4806 { 2334, 2, 0, 4, 165, 1, 0, 607, HexagonImpOpBase + 101, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x10062008002fULL }, // Inst #2334 = S2_storerhgp
4807 { 2333, 4, 1, 4, 39, 0, 0, 778, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x160000080029ULL }, // Inst #2333 = S2_storerh_pr
4808 { 2332, 4, 1, 4, 39, 0, 0, 787, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x160000080029ULL }, // Inst #2332 = S2_storerh_pi
4809 { 2331, 4, 1, 4, 39, 1, 0, 778, HexagonImpOpBase + 100, 0|(1ULL<<MCID::MayStore), 0x160000080029ULL }, // Inst #2331 = S2_storerh_pcr
4810 { 2330, 5, 1, 4, 38, 1, 0, 782, HexagonImpOpBase + 100, 0|(1ULL<<MCID::MayStore), 0x160000080029ULL }, // Inst #2330 = S2_storerh_pci
4811 { 2329, 4, 1, 4, 39, 0, 0, 778, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x160000080029ULL }, // Inst #2329 = S2_storerh_pbr
4812 { 2328, 3, 0, 4, 51, 0, 0, 510, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x130592880029ULL }, // Inst #2328 = S2_storerh_io
4813 { 2327, 2, 0, 4, 165, 1, 0, 607, HexagonImpOpBase + 101, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x10062000002fULL }, // Inst #2327 = S2_storerfgp
4814 { 2326, 4, 1, 4, 39, 0, 0, 778, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x160000000029ULL }, // Inst #2326 = S2_storerf_pr
4815 { 2325, 4, 1, 4, 39, 0, 0, 787, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x160000000029ULL }, // Inst #2325 = S2_storerf_pi
4816 { 2324, 4, 1, 4, 39, 1, 0, 778, HexagonImpOpBase + 100, 0|(1ULL<<MCID::MayStore), 0x160000000029ULL }, // Inst #2324 = S2_storerf_pcr
4817 { 2323, 5, 1, 4, 38, 1, 0, 782, HexagonImpOpBase + 100, 0|(1ULL<<MCID::MayStore), 0x160000000029ULL }, // Inst #2323 = S2_storerf_pci
4818 { 2322, 4, 1, 4, 39, 0, 0, 778, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x160000000029ULL }, // Inst #2322 = S2_storerf_pbr
4819 { 2321, 3, 0, 4, 51, 0, 0, 510, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x130592800029ULL }, // Inst #2321 = S2_storerf_io
4820 { 2320, 2, 0, 4, 165, 1, 0, 738, HexagonImpOpBase + 101, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x200e6000002fULL }, // Inst #2320 = S2_storerdgp
4821 { 2319, 4, 1, 4, 39, 0, 0, 791, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x260000000029ULL }, // Inst #2319 = S2_storerd_pr
4822 { 2318, 4, 1, 4, 39, 0, 0, 800, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x260000000029ULL }, // Inst #2318 = S2_storerd_pi
4823 { 2317, 4, 1, 4, 39, 1, 0, 791, HexagonImpOpBase + 100, 0|(1ULL<<MCID::MayStore), 0x260000000029ULL }, // Inst #2317 = S2_storerd_pcr
4824 { 2316, 5, 1, 4, 38, 1, 0, 795, HexagonImpOpBase + 100, 0|(1ULL<<MCID::MayStore), 0x260000000029ULL }, // Inst #2316 = S2_storerd_pci
4825 { 2315, 4, 1, 4, 39, 0, 0, 791, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x260000000029ULL }, // Inst #2315 = S2_storerd_pbr
4826 { 2314, 3, 0, 4, 51, 0, 0, 513, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x230dd2800029ULL }, // Inst #2314 = S2_storerd_io
4827 { 2313, 2, 0, 4, 166, 1, 0, 607, HexagonImpOpBase + 101, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x8820011402fULL }, // Inst #2313 = S2_storerbnewgp
4828 { 2312, 4, 1, 4, 54, 0, 0, 778, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0xe8000134029ULL }, // Inst #2312 = S2_storerbnew_pr
4829 { 2311, 4, 1, 4, 54, 0, 0, 787, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xe80001b4029ULL }, // Inst #2311 = S2_storerbnew_pi
4830 { 2310, 4, 1, 4, 54, 1, 0, 778, HexagonImpOpBase + 100, 0|(1ULL<<MCID::MayStore), 0xe8000134029ULL }, // Inst #2310 = S2_storerbnew_pcr
4831 { 2309, 5, 1, 4, 176, 1, 0, 782, HexagonImpOpBase + 100, 0|(1ULL<<MCID::MayStore), 0xe8000144029ULL }, // Inst #2309 = S2_storerbnew_pci
4832 { 2308, 4, 1, 4, 54, 0, 0, 778, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0xe8000134029ULL }, // Inst #2308 = S2_storerbnew_pbr
4833 { 2307, 3, 0, 4, 52, 0, 0, 510, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xb8172924029ULL }, // Inst #2307 = S2_storerbnew_io
4834 { 2306, 2, 0, 4, 165, 1, 0, 607, HexagonImpOpBase + 101, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x8020008002fULL }, // Inst #2306 = S2_storerbgp
4835 { 2305, 4, 1, 4, 39, 0, 0, 778, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0xe0000080029ULL }, // Inst #2305 = S2_storerb_pr
4836 { 2304, 4, 1, 4, 39, 0, 0, 787, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xe0000080029ULL }, // Inst #2304 = S2_storerb_pi
4837 { 2303, 4, 1, 4, 39, 1, 0, 778, HexagonImpOpBase + 100, 0|(1ULL<<MCID::MayStore), 0xe0000080029ULL }, // Inst #2303 = S2_storerb_pcr
4838 { 2302, 5, 1, 4, 38, 1, 0, 782, HexagonImpOpBase + 100, 0|(1ULL<<MCID::MayStore), 0xe0000080029ULL }, // Inst #2302 = S2_storerb_pci
4839 { 2301, 4, 1, 4, 39, 0, 0, 778, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0xe0000080029ULL }, // Inst #2301 = S2_storerb_pbr
4840 { 2300, 3, 0, 4, 51, 0, 0, 510, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xb0172880029ULL }, // Inst #2300 = S2_storerb_io
4841 { 2299, 3, 1, 4, 8, 0, 0, 169, HexagonImpOpBase + 0, 0, 0x2cULL }, // Inst #2299 = S2_shuffoh
4842 { 2298, 3, 1, 4, 8, 0, 0, 169, HexagonImpOpBase + 0, 0, 0x2cULL }, // Inst #2298 = S2_shuffob
4843 { 2297, 3, 1, 4, 8, 0, 0, 169, HexagonImpOpBase + 0, 0, 0x2cULL }, // Inst #2297 = S2_shuffeh
4844 { 2296, 3, 1, 4, 8, 0, 0, 169, HexagonImpOpBase + 0, 0, 0x2cULL }, // Inst #2296 = S2_shuffeb
4845 { 2295, 3, 1, 4, 8, 0, 0, 202, HexagonImpOpBase + 0, 0, 0x802cULL }, // Inst #2295 = S2_setbit_r
4846 { 2294, 3, 1, 4, 8, 0, 0, 199, HexagonImpOpBase + 0, 0, 0x802bULL }, // Inst #2294 = S2_setbit_i
4847 { 2293, 5, 1, 4, 173, 0, 0, 764, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x1e0000081429ULL }, // Inst #2293 = S2_pstoreritnew_pi
4848 { 2292, 5, 1, 4, 172, 0, 0, 764, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x1e0000080429ULL }, // Inst #2292 = S2_pstorerit_pi
4849 { 2291, 4, 0, 4, 49, 0, 0, 760, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x1b090488042fULL }, // Inst #2291 = S2_pstorerit_io
4850 { 2290, 5, 1, 4, 175, 0, 0, 764, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x1e8000145429ULL }, // Inst #2290 = S2_pstorerinewtnew_pi
4851 { 2289, 5, 1, 4, 174, 0, 0, 764, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x1e8000144429ULL }, // Inst #2289 = S2_pstorerinewt_pi
4852 { 2288, 4, 0, 4, 50, 0, 0, 760, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x1b890493442fULL }, // Inst #2288 = S2_pstorerinewt_io
4853 { 2287, 5, 1, 4, 175, 0, 0, 764, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x1e8000145c29ULL }, // Inst #2287 = S2_pstorerinewfnew_pi
4854 { 2286, 5, 1, 4, 174, 0, 0, 764, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x1e8000144c29ULL }, // Inst #2286 = S2_pstorerinewf_pi
4855 { 2285, 4, 0, 4, 50, 0, 0, 760, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x1b8904934c2fULL }, // Inst #2285 = S2_pstorerinewf_io
4856 { 2284, 5, 1, 4, 173, 0, 0, 764, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x1e0000081c29ULL }, // Inst #2284 = S2_pstorerifnew_pi
4857 { 2283, 5, 1, 4, 172, 0, 0, 764, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x1e0000080c29ULL }, // Inst #2283 = S2_pstorerif_pi
4858 { 2282, 4, 0, 4, 49, 0, 0, 760, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x1b0904880c2fULL }, // Inst #2282 = S2_pstorerif_io
4859 { 2281, 5, 1, 4, 173, 0, 0, 764, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x160000081429ULL }, // Inst #2281 = S2_pstorerhtnew_pi
4860 { 2280, 5, 1, 4, 172, 0, 0, 764, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x160000080429ULL }, // Inst #2280 = S2_pstorerht_pi
4861 { 2279, 4, 0, 4, 49, 0, 0, 760, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x1304e488042fULL }, // Inst #2279 = S2_pstorerht_io
4862 { 2278, 5, 1, 4, 175, 0, 0, 764, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x168000145429ULL }, // Inst #2278 = S2_pstorerhnewtnew_pi
4863 { 2277, 5, 1, 4, 174, 0, 0, 764, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x168000144429ULL }, // Inst #2277 = S2_pstorerhnewt_pi
4864 { 2276, 4, 0, 4, 50, 0, 0, 760, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x1384e493442fULL }, // Inst #2276 = S2_pstorerhnewt_io
4865 { 2275, 5, 1, 4, 175, 0, 0, 764, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x168000145c29ULL }, // Inst #2275 = S2_pstorerhnewfnew_pi
4866 { 2274, 5, 1, 4, 174, 0, 0, 764, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x168000144c29ULL }, // Inst #2274 = S2_pstorerhnewf_pi
4867 { 2273, 4, 0, 4, 50, 0, 0, 760, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x1384e4934c2fULL }, // Inst #2273 = S2_pstorerhnewf_io
4868 { 2272, 5, 1, 4, 173, 0, 0, 764, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x160000081c29ULL }, // Inst #2272 = S2_pstorerhfnew_pi
4869 { 2271, 5, 1, 4, 172, 0, 0, 764, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x160000080c29ULL }, // Inst #2271 = S2_pstorerhf_pi
4870 { 2270, 4, 0, 4, 49, 0, 0, 760, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x1304e4880c2fULL }, // Inst #2270 = S2_pstorerhf_io
4871 { 2269, 5, 1, 4, 173, 0, 0, 764, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x160000001429ULL }, // Inst #2269 = S2_pstorerftnew_pi
4872 { 2268, 5, 1, 4, 172, 0, 0, 764, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x160000000429ULL }, // Inst #2268 = S2_pstorerft_pi
4873 { 2267, 4, 0, 4, 49, 0, 0, 760, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x1304e480042fULL }, // Inst #2267 = S2_pstorerft_io
4874 { 2266, 5, 1, 4, 173, 0, 0, 764, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x160000001c29ULL }, // Inst #2266 = S2_pstorerffnew_pi
4875 { 2265, 5, 1, 4, 172, 0, 0, 764, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x160000000c29ULL }, // Inst #2265 = S2_pstorerff_pi
4876 { 2264, 4, 0, 4, 49, 0, 0, 760, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x1304e4800c2fULL }, // Inst #2264 = S2_pstorerff_io
4877 { 2263, 5, 1, 4, 173, 0, 0, 773, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x260000001429ULL }, // Inst #2263 = S2_pstorerdtnew_pi
4878 { 2262, 5, 1, 4, 172, 0, 0, 773, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x260000000429ULL }, // Inst #2262 = S2_pstorerdt_pi
4879 { 2261, 4, 0, 4, 49, 0, 0, 769, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x230d2480042fULL }, // Inst #2261 = S2_pstorerdt_io
4880 { 2260, 5, 1, 4, 173, 0, 0, 773, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x260000001c29ULL }, // Inst #2260 = S2_pstorerdfnew_pi
4881 { 2259, 5, 1, 4, 172, 0, 0, 773, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x260000000c29ULL }, // Inst #2259 = S2_pstorerdf_pi
4882 { 2258, 4, 0, 4, 49, 0, 0, 769, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x230d24800c2fULL }, // Inst #2258 = S2_pstorerdf_io
4883 { 2257, 5, 1, 4, 173, 0, 0, 764, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0xe0000081429ULL }, // Inst #2257 = S2_pstorerbtnew_pi
4884 { 2256, 5, 1, 4, 172, 0, 0, 764, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0xe0000080429ULL }, // Inst #2256 = S2_pstorerbt_pi
4885 { 2255, 4, 0, 4, 49, 0, 0, 760, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0xb00c488042fULL }, // Inst #2255 = S2_pstorerbt_io
4886 { 2254, 5, 1, 4, 175, 0, 0, 764, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0xe8000145429ULL }, // Inst #2254 = S2_pstorerbnewtnew_pi
4887 { 2253, 5, 1, 4, 174, 0, 0, 764, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0xe8000144429ULL }, // Inst #2253 = S2_pstorerbnewt_pi
4888 { 2252, 4, 0, 4, 50, 0, 0, 760, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0xb80c493442fULL }, // Inst #2252 = S2_pstorerbnewt_io
4889 { 2251, 5, 1, 4, 175, 0, 0, 764, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0xe8000145c29ULL }, // Inst #2251 = S2_pstorerbnewfnew_pi
4890 { 2250, 5, 1, 4, 174, 0, 0, 764, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0xe8000144c29ULL }, // Inst #2250 = S2_pstorerbnewf_pi
4891 { 2249, 4, 0, 4, 50, 0, 0, 760, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0xb80c4934c2fULL }, // Inst #2249 = S2_pstorerbnewf_io
4892 { 2248, 5, 1, 4, 173, 0, 0, 764, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0xe0000081c29ULL }, // Inst #2248 = S2_pstorerbfnew_pi
4893 { 2247, 5, 1, 4, 172, 0, 0, 764, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0xe0000080c29ULL }, // Inst #2247 = S2_pstorerbf_pi
4894 { 2246, 4, 0, 4, 49, 0, 0, 760, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0xb00c4880c2fULL }, // Inst #2246 = S2_pstorerbf_io
4895 { 2245, 3, 1, 4, 170, 0, 0, 557, HexagonImpOpBase + 0, 0, 0x80000000008003ULL }, // Inst #2245 = S2_parityp
4896 { 2244, 3, 1, 4, 6, 0, 0, 519, HexagonImpOpBase + 0, 0, 0x1ULL }, // Inst #2244 = S2_packhl
4897 { 2243, 3, 1, 4, 171, 0, 0, 516, HexagonImpOpBase + 0, 0, 0x8000000000802bULL }, // Inst #2243 = S2_mask
4898 { 2242, 3, 1, 4, 8, 0, 0, 209, HexagonImpOpBase + 0, 0, 0x2cULL }, // Inst #2242 = S2_lsr_r_vw
4899 { 2241, 3, 1, 4, 8, 0, 0, 209, HexagonImpOpBase + 0, 0, 0x2cULL }, // Inst #2241 = S2_lsr_r_vh
4900 { 2240, 4, 1, 4, 163, 0, 0, 590, HexagonImpOpBase + 0, 0, 0x8000000000802cULL }, // Inst #2240 = S2_lsr_r_r_or
4901 { 2239, 4, 1, 4, 161, 0, 0, 590, HexagonImpOpBase + 0, 0, 0x8000000000802cULL }, // Inst #2239 = S2_lsr_r_r_nac
4902 { 2238, 4, 1, 4, 163, 0, 0, 590, HexagonImpOpBase + 0, 0, 0x8000000000802cULL }, // Inst #2238 = S2_lsr_r_r_and
4903 { 2237, 4, 1, 4, 161, 0, 0, 590, HexagonImpOpBase + 0, 0, 0x8000000000802cULL }, // Inst #2237 = S2_lsr_r_r_acc
4904 { 2236, 3, 1, 4, 8, 0, 0, 202, HexagonImpOpBase + 0, 0, 0x802cULL }, // Inst #2236 = S2_lsr_r_r
4905 { 2235, 4, 1, 4, 163, 0, 0, 205, HexagonImpOpBase + 0, 0, 0x8000000000002cULL }, // Inst #2235 = S2_lsr_r_p_xor
4906 { 2234, 4, 1, 4, 163, 0, 0, 205, HexagonImpOpBase + 0, 0, 0x8000000000002cULL }, // Inst #2234 = S2_lsr_r_p_or
4907 { 2233, 4, 1, 4, 161, 0, 0, 205, HexagonImpOpBase + 0, 0, 0x8000000000002cULL }, // Inst #2233 = S2_lsr_r_p_nac
4908 { 2232, 4, 1, 4, 163, 0, 0, 205, HexagonImpOpBase + 0, 0, 0x8000000000002cULL }, // Inst #2232 = S2_lsr_r_p_and
4909 { 2231, 4, 1, 4, 161, 0, 0, 205, HexagonImpOpBase + 0, 0, 0x8000000000002cULL }, // Inst #2231 = S2_lsr_r_p_acc
4910 { 2230, 3, 1, 4, 8, 0, 0, 209, HexagonImpOpBase + 0, 0, 0x2cULL }, // Inst #2230 = S2_lsr_r_p
4911 { 2229, 3, 1, 4, 8, 0, 0, 304, HexagonImpOpBase + 0, 0, 0x2bULL }, // Inst #2229 = S2_lsr_i_vw
4912 { 2228, 3, 1, 4, 8, 0, 0, 304, HexagonImpOpBase + 0, 0, 0x2bULL }, // Inst #2228 = S2_lsr_i_vh
4913 { 2227, 4, 1, 4, 163, 0, 0, 714, HexagonImpOpBase + 0, 0, 0x8000000000802bULL }, // Inst #2227 = S2_lsr_i_r_xacc
4914 { 2226, 4, 1, 4, 163, 0, 0, 714, HexagonImpOpBase + 0, 0, 0x8000000000802bULL }, // Inst #2226 = S2_lsr_i_r_or
4915 { 2225, 4, 1, 4, 161, 0, 0, 714, HexagonImpOpBase + 0, 0, 0x8000000000802bULL }, // Inst #2225 = S2_lsr_i_r_nac
4916 { 2224, 4, 1, 4, 163, 0, 0, 714, HexagonImpOpBase + 0, 0, 0x8000000000802bULL }, // Inst #2224 = S2_lsr_i_r_and
4917 { 2223, 4, 1, 4, 161, 0, 0, 714, HexagonImpOpBase + 0, 0, 0x8000000000802bULL }, // Inst #2223 = S2_lsr_i_r_acc
4918 { 2222, 3, 1, 4, 8, 0, 0, 199, HexagonImpOpBase + 0, 0, 0x802bULL }, // Inst #2222 = S2_lsr_i_r
4919 { 2221, 4, 1, 4, 163, 0, 0, 740, HexagonImpOpBase + 0, 0, 0x8000000000002bULL }, // Inst #2221 = S2_lsr_i_p_xacc
4920 { 2220, 4, 1, 4, 163, 0, 0, 740, HexagonImpOpBase + 0, 0, 0x8000000000002bULL }, // Inst #2220 = S2_lsr_i_p_or
4921 { 2219, 4, 1, 4, 161, 0, 0, 740, HexagonImpOpBase + 0, 0, 0x8000000000002bULL }, // Inst #2219 = S2_lsr_i_p_nac
4922 { 2218, 4, 1, 4, 163, 0, 0, 740, HexagonImpOpBase + 0, 0, 0x8000000000002bULL }, // Inst #2218 = S2_lsr_i_p_and
4923 { 2217, 4, 1, 4, 161, 0, 0, 740, HexagonImpOpBase + 0, 0, 0x8000000000002bULL }, // Inst #2217 = S2_lsr_i_p_acc
4924 { 2216, 3, 1, 4, 8, 0, 0, 304, HexagonImpOpBase + 0, 0, 0x2bULL }, // Inst #2216 = S2_lsr_i_p
4925 { 2215, 3, 1, 4, 8, 0, 0, 209, HexagonImpOpBase + 0, 0, 0x2cULL }, // Inst #2215 = S2_lsl_r_vw
4926 { 2214, 3, 1, 4, 8, 0, 0, 209, HexagonImpOpBase + 0, 0, 0x2cULL }, // Inst #2214 = S2_lsl_r_vh
4927 { 2213, 4, 1, 4, 163, 0, 0, 590, HexagonImpOpBase + 0, 0, 0x8000000000802cULL }, // Inst #2213 = S2_lsl_r_r_or
4928 { 2212, 4, 1, 4, 161, 0, 0, 590, HexagonImpOpBase + 0, 0, 0x8000000000802cULL }, // Inst #2212 = S2_lsl_r_r_nac
4929 { 2211, 4, 1, 4, 163, 0, 0, 590, HexagonImpOpBase + 0, 0, 0x8000000000802cULL }, // Inst #2211 = S2_lsl_r_r_and
4930 { 2210, 4, 1, 4, 161, 0, 0, 590, HexagonImpOpBase + 0, 0, 0x8000000000802cULL }, // Inst #2210 = S2_lsl_r_r_acc
4931 { 2209, 3, 1, 4, 8, 0, 0, 202, HexagonImpOpBase + 0, 0, 0x802cULL }, // Inst #2209 = S2_lsl_r_r
4932 { 2208, 4, 1, 4, 163, 0, 0, 205, HexagonImpOpBase + 0, 0, 0x8000000000002cULL }, // Inst #2208 = S2_lsl_r_p_xor
4933 { 2207, 4, 1, 4, 163, 0, 0, 205, HexagonImpOpBase + 0, 0, 0x8000000000002cULL }, // Inst #2207 = S2_lsl_r_p_or
4934 { 2206, 4, 1, 4, 161, 0, 0, 205, HexagonImpOpBase + 0, 0, 0x8000000000002cULL }, // Inst #2206 = S2_lsl_r_p_nac
4935 { 2205, 4, 1, 4, 163, 0, 0, 205, HexagonImpOpBase + 0, 0, 0x8000000000002cULL }, // Inst #2205 = S2_lsl_r_p_and
4936 { 2204, 4, 1, 4, 161, 0, 0, 205, HexagonImpOpBase + 0, 0, 0x8000000000002cULL }, // Inst #2204 = S2_lsl_r_p_acc
4937 { 2203, 3, 1, 4, 8, 0, 0, 209, HexagonImpOpBase + 0, 0, 0x2cULL }, // Inst #2203 = S2_lsl_r_p
4938 { 2202, 3, 1, 4, 170, 0, 0, 169, HexagonImpOpBase + 0, 0, 0x8000000000002cULL }, // Inst #2202 = S2_lfsp
4939 { 2201, 2, 1, 4, 168, 0, 0, 162, HexagonImpOpBase + 0, 0, 0x8000000000002bULL }, // Inst #2201 = S2_interleave
4940 { 2200, 4, 1, 4, 163, 0, 0, 215, HexagonImpOpBase + 0, 0, 0x8000000000002cULL }, // Inst #2200 = S2_insertp_rp
4941 { 2199, 5, 1, 4, 53, 0, 0, 755, HexagonImpOpBase + 0, 0, 0x8000000000002bULL }, // Inst #2199 = S2_insertp
4942 { 2198, 4, 1, 4, 163, 0, 0, 751, HexagonImpOpBase + 0, 0, 0x8000000000802cULL }, // Inst #2198 = S2_insert_rp
4943 { 2197, 5, 1, 4, 53, 0, 0, 309, HexagonImpOpBase + 0, 0, 0x8000000000802bULL }, // Inst #2197 = S2_insert
4944 { 2196, 3, 1, 4, 170, 0, 0, 169, HexagonImpOpBase + 0, 0, 0x8000000000002cULL }, // Inst #2196 = S2_extractup_rp
4945 { 2195, 4, 1, 4, 161, 0, 0, 747, HexagonImpOpBase + 0, 0, 0x8000000000002bULL }, // Inst #2195 = S2_extractup
4946 { 2194, 3, 1, 4, 170, 0, 0, 744, HexagonImpOpBase + 0, 0, 0x8000000000802cULL }, // Inst #2194 = S2_extractu_rp
4947 { 2193, 4, 1, 4, 161, 0, 0, 686, HexagonImpOpBase + 0, 0, 0x8000000000802bULL }, // Inst #2193 = S2_extractu
4948 { 2192, 2, 1, 4, 168, 0, 0, 162, HexagonImpOpBase + 0, 0, 0x8000000000002bULL }, // Inst #2192 = S2_deinterleave
4949 { 2191, 2, 1, 4, 168, 0, 0, 307, HexagonImpOpBase + 0, 0, 0x8000000000802bULL }, // Inst #2191 = S2_ct1p
4950 { 2190, 2, 1, 4, 168, 0, 0, 157, HexagonImpOpBase + 0, 0, 0x8000000000802bULL }, // Inst #2190 = S2_ct1
4951 { 2189, 2, 1, 4, 168, 0, 0, 307, HexagonImpOpBase + 0, 0, 0x8000000000802bULL }, // Inst #2189 = S2_ct0p
4952 { 2188, 2, 1, 4, 168, 0, 0, 157, HexagonImpOpBase + 0, 0, 0x8000000000802bULL }, // Inst #2188 = S2_ct0
4953 { 2187, 3, 1, 4, 8, 0, 0, 202, HexagonImpOpBase + 0, 0, 0x802cULL }, // Inst #2187 = S2_clrbit_r
4954 { 2186, 3, 1, 4, 8, 0, 0, 199, HexagonImpOpBase + 0, 0, 0x802bULL }, // Inst #2186 = S2_clrbit_i
4955 { 2185, 2, 1, 4, 168, 0, 0, 307, HexagonImpOpBase + 0, 0, 0x8000000000802bULL }, // Inst #2185 = S2_clbp
4956 { 2184, 2, 1, 4, 168, 0, 0, 157, HexagonImpOpBase + 0, 0, 0x8000000000802bULL }, // Inst #2184 = S2_clbnorm
4957 { 2183, 2, 1, 4, 168, 0, 0, 157, HexagonImpOpBase + 0, 0, 0x8000000000802bULL }, // Inst #2183 = S2_clb
4958 { 2182, 2, 1, 4, 168, 0, 0, 307, HexagonImpOpBase + 0, 0, 0x8000000000802bULL }, // Inst #2182 = S2_cl1p
4959 { 2181, 2, 1, 4, 168, 0, 0, 157, HexagonImpOpBase + 0, 0, 0x8000000000802bULL }, // Inst #2181 = S2_cl1
4960 { 2180, 2, 1, 4, 168, 0, 0, 307, HexagonImpOpBase + 0, 0, 0x8000000000802bULL }, // Inst #2180 = S2_cl0p
4961 { 2179, 2, 1, 4, 168, 0, 0, 157, HexagonImpOpBase + 0, 0, 0x8000000000802bULL }, // Inst #2179 = S2_cl0
4962 { 2178, 3, 1, 4, 169, 0, 1, 169, HexagonImpOpBase + 121, 0, 0x8000000000202cULL }, // Inst #2178 = S2_cabacdecbin
4963 { 2177, 2, 1, 4, 168, 0, 0, 162, HexagonImpOpBase + 0, 0, 0x8000000000002bULL }, // Inst #2177 = S2_brevp
4964 { 2176, 2, 1, 4, 168, 0, 0, 157, HexagonImpOpBase + 0, 0, 0x8000000000802bULL }, // Inst #2176 = S2_brev
4965 { 2175, 3, 1, 4, 8, 0, 0, 209, HexagonImpOpBase + 0, 0, 0x2cULL }, // Inst #2175 = S2_asr_r_vw
4966 { 2174, 3, 1, 4, 8, 0, 0, 209, HexagonImpOpBase + 0, 0, 0x2cULL }, // Inst #2174 = S2_asr_r_vh
4967 { 2173, 3, 1, 4, 78, 0, 0, 212, HexagonImpOpBase + 0, 0, 0x8000000000802cULL }, // Inst #2173 = S2_asr_r_svw_trun
4968 { 2172, 3, 1, 4, 77, 0, 1, 202, HexagonImpOpBase + 63, 0, 0x8000000000802cULL }, // Inst #2172 = S2_asr_r_r_sat
4969 { 2171, 4, 1, 4, 163, 0, 0, 590, HexagonImpOpBase + 0, 0, 0x8000000000802cULL }, // Inst #2171 = S2_asr_r_r_or
4970 { 2170, 4, 1, 4, 161, 0, 0, 590, HexagonImpOpBase + 0, 0, 0x8000000000802cULL }, // Inst #2170 = S2_asr_r_r_nac
4971 { 2169, 4, 1, 4, 163, 0, 0, 590, HexagonImpOpBase + 0, 0, 0x8000000000802cULL }, // Inst #2169 = S2_asr_r_r_and
4972 { 2168, 4, 1, 4, 161, 0, 0, 590, HexagonImpOpBase + 0, 0, 0x8000000000802cULL }, // Inst #2168 = S2_asr_r_r_acc
4973 { 2167, 3, 1, 4, 8, 0, 0, 202, HexagonImpOpBase + 0, 0, 0x802cULL }, // Inst #2167 = S2_asr_r_r
4974 { 2166, 4, 1, 4, 163, 0, 0, 205, HexagonImpOpBase + 0, 0, 0x8000000000002cULL }, // Inst #2166 = S2_asr_r_p_xor
4975 { 2165, 4, 1, 4, 163, 0, 0, 205, HexagonImpOpBase + 0, 0, 0x8000000000002cULL }, // Inst #2165 = S2_asr_r_p_or
4976 { 2164, 4, 1, 4, 161, 0, 0, 205, HexagonImpOpBase + 0, 0, 0x8000000000002cULL }, // Inst #2164 = S2_asr_r_p_nac
4977 { 2163, 4, 1, 4, 163, 0, 0, 205, HexagonImpOpBase + 0, 0, 0x8000000000002cULL }, // Inst #2163 = S2_asr_r_p_and
4978 { 2162, 4, 1, 4, 161, 0, 0, 205, HexagonImpOpBase + 0, 0, 0x8000000000002cULL }, // Inst #2162 = S2_asr_r_p_acc
4979 { 2161, 3, 1, 4, 8, 0, 0, 209, HexagonImpOpBase + 0, 0, 0x2cULL }, // Inst #2161 = S2_asr_r_p
4980 { 2160, 3, 1, 4, 8, 0, 0, 304, HexagonImpOpBase + 0, 0, 0x2bULL }, // Inst #2160 = S2_asr_i_vw
4981 { 2159, 3, 1, 4, 8, 0, 0, 304, HexagonImpOpBase + 0, 0, 0x2bULL }, // Inst #2159 = S2_asr_i_vh
4982 { 2158, 3, 1, 4, 78, 0, 0, 314, HexagonImpOpBase + 0, 0, 0x8000000000802bULL }, // Inst #2158 = S2_asr_i_svw_trun
4983 { 2157, 3, 1, 4, 48, 0, 0, 199, HexagonImpOpBase + 0, 0, 0x8000000000802bULL }, // Inst #2157 = S2_asr_i_r_rnd
4984 { 2156, 4, 1, 4, 163, 0, 0, 714, HexagonImpOpBase + 0, 0, 0x8000000000802bULL }, // Inst #2156 = S2_asr_i_r_or
4985 { 2155, 4, 1, 4, 161, 0, 0, 714, HexagonImpOpBase + 0, 0, 0x8000000000802bULL }, // Inst #2155 = S2_asr_i_r_nac
4986 { 2154, 4, 1, 4, 163, 0, 0, 714, HexagonImpOpBase + 0, 0, 0x8000000000802bULL }, // Inst #2154 = S2_asr_i_r_and
4987 { 2153, 4, 1, 4, 161, 0, 0, 714, HexagonImpOpBase + 0, 0, 0x8000000000802bULL }, // Inst #2153 = S2_asr_i_r_acc
4988 { 2152, 3, 1, 4, 8, 0, 0, 199, HexagonImpOpBase + 0, 0, 0x802bULL }, // Inst #2152 = S2_asr_i_r
4989 { 2151, 3, 1, 4, 48, 0, 0, 304, HexagonImpOpBase + 0, 0, 0x8000000000002bULL }, // Inst #2151 = S2_asr_i_p_rnd
4990 { 2150, 4, 1, 4, 163, 0, 0, 740, HexagonImpOpBase + 0, 0, 0x8000000000002bULL }, // Inst #2150 = S2_asr_i_p_or
4991 { 2149, 4, 1, 4, 161, 0, 0, 740, HexagonImpOpBase + 0, 0, 0x8000000000002bULL }, // Inst #2149 = S2_asr_i_p_nac
4992 { 2148, 4, 1, 4, 163, 0, 0, 740, HexagonImpOpBase + 0, 0, 0x8000000000002bULL }, // Inst #2148 = S2_asr_i_p_and
4993 { 2147, 4, 1, 4, 161, 0, 0, 740, HexagonImpOpBase + 0, 0, 0x8000000000002bULL }, // Inst #2147 = S2_asr_i_p_acc
4994 { 2146, 3, 1, 4, 8, 0, 0, 304, HexagonImpOpBase + 0, 0, 0x2bULL }, // Inst #2146 = S2_asr_i_p
4995 { 2145, 3, 1, 4, 8, 0, 0, 209, HexagonImpOpBase + 0, 0, 0x2cULL }, // Inst #2145 = S2_asl_r_vw
4996 { 2144, 3, 1, 4, 8, 0, 0, 209, HexagonImpOpBase + 0, 0, 0x2cULL }, // Inst #2144 = S2_asl_r_vh
4997 { 2143, 3, 1, 4, 77, 0, 1, 202, HexagonImpOpBase + 63, 0, 0x8000000000802cULL }, // Inst #2143 = S2_asl_r_r_sat
4998 { 2142, 4, 1, 4, 163, 0, 0, 590, HexagonImpOpBase + 0, 0, 0x8000000000802cULL }, // Inst #2142 = S2_asl_r_r_or
4999 { 2141, 4, 1, 4, 161, 0, 0, 590, HexagonImpOpBase + 0, 0, 0x8000000000802cULL }, // Inst #2141 = S2_asl_r_r_nac
5000 { 2140, 4, 1, 4, 163, 0, 0, 590, HexagonImpOpBase + 0, 0, 0x8000000000802cULL }, // Inst #2140 = S2_asl_r_r_and
5001 { 2139, 4, 1, 4, 161, 0, 0, 590, HexagonImpOpBase + 0, 0, 0x8000000000802cULL }, // Inst #2139 = S2_asl_r_r_acc
5002 { 2138, 3, 1, 4, 8, 0, 0, 202, HexagonImpOpBase + 0, 0, 0x802cULL }, // Inst #2138 = S2_asl_r_r
5003 { 2137, 4, 1, 4, 163, 0, 0, 205, HexagonImpOpBase + 0, 0, 0x8000000000002cULL }, // Inst #2137 = S2_asl_r_p_xor
5004 { 2136, 4, 1, 4, 163, 0, 0, 205, HexagonImpOpBase + 0, 0, 0x8000000000002cULL }, // Inst #2136 = S2_asl_r_p_or
5005 { 2135, 4, 1, 4, 161, 0, 0, 205, HexagonImpOpBase + 0, 0, 0x8000000000002cULL }, // Inst #2135 = S2_asl_r_p_nac
5006 { 2134, 4, 1, 4, 163, 0, 0, 205, HexagonImpOpBase + 0, 0, 0x8000000000002cULL }, // Inst #2134 = S2_asl_r_p_and
5007 { 2133, 4, 1, 4, 161, 0, 0, 205, HexagonImpOpBase + 0, 0, 0x8000000000002cULL }, // Inst #2133 = S2_asl_r_p_acc
5008 { 2132, 3, 1, 4, 8, 0, 0, 209, HexagonImpOpBase + 0, 0, 0x2cULL }, // Inst #2132 = S2_asl_r_p
5009 { 2131, 3, 1, 4, 8, 0, 0, 304, HexagonImpOpBase + 0, 0, 0x2bULL }, // Inst #2131 = S2_asl_i_vw
5010 { 2130, 3, 1, 4, 8, 0, 0, 304, HexagonImpOpBase + 0, 0, 0x2bULL }, // Inst #2130 = S2_asl_i_vh
5011 { 2129, 4, 1, 4, 163, 0, 0, 714, HexagonImpOpBase + 0, 0, 0x8000000000802bULL }, // Inst #2129 = S2_asl_i_r_xacc
5012 { 2128, 3, 1, 4, 77, 0, 1, 199, HexagonImpOpBase + 63, 0, 0x8000000000802bULL }, // Inst #2128 = S2_asl_i_r_sat
5013 { 2127, 4, 1, 4, 163, 0, 0, 714, HexagonImpOpBase + 0, 0, 0x8000000000802bULL }, // Inst #2127 = S2_asl_i_r_or
5014 { 2126, 4, 1, 4, 161, 0, 0, 714, HexagonImpOpBase + 0, 0, 0x8000000000802bULL }, // Inst #2126 = S2_asl_i_r_nac
5015 { 2125, 4, 1, 4, 163, 0, 0, 714, HexagonImpOpBase + 0, 0, 0x8000000000802bULL }, // Inst #2125 = S2_asl_i_r_and
5016 { 2124, 4, 1, 4, 161, 0, 0, 714, HexagonImpOpBase + 0, 0, 0x8000000000802bULL }, // Inst #2124 = S2_asl_i_r_acc
5017 { 2123, 3, 1, 4, 8, 0, 0, 199, HexagonImpOpBase + 0, 0, 0x802bULL }, // Inst #2123 = S2_asl_i_r
5018 { 2122, 4, 1, 4, 163, 0, 0, 740, HexagonImpOpBase + 0, 0, 0x8000000000002bULL }, // Inst #2122 = S2_asl_i_p_xacc
5019 { 2121, 4, 1, 4, 163, 0, 0, 740, HexagonImpOpBase + 0, 0, 0x8000000000002bULL }, // Inst #2121 = S2_asl_i_p_or
5020 { 2120, 4, 1, 4, 161, 0, 0, 740, HexagonImpOpBase + 0, 0, 0x8000000000002bULL }, // Inst #2120 = S2_asl_i_p_nac
5021 { 2119, 4, 1, 4, 163, 0, 0, 740, HexagonImpOpBase + 0, 0, 0x8000000000002bULL }, // Inst #2119 = S2_asl_i_p_and
5022 { 2118, 4, 1, 4, 161, 0, 0, 740, HexagonImpOpBase + 0, 0, 0x8000000000002bULL }, // Inst #2118 = S2_asl_i_p_acc
5023 { 2117, 3, 1, 4, 8, 0, 0, 304, HexagonImpOpBase + 0, 0, 0x2bULL }, // Inst #2117 = S2_asl_i_p
5024 { 2116, 3, 1, 4, 58, 4, 1, 507, HexagonImpOpBase + 58, 0|(1ULL<<MCID::MayStore), 0x230000008029ULL }, // Inst #2116 = S2_allocframe
5025 { 2115, 4, 1, 4, 161, 0, 0, 219, HexagonImpOpBase + 0, 0, 0x8000000000802cULL }, // Inst #2115 = S2_addasl_rrri
5026 { 2114, 1, 0, 4, 121, 0, 7, 0, HexagonImpOpBase + 114, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0xb10800023ULL }, // Inst #2114 = RESTORE_DEALLOC_RET_JMP_V4_PIC
5027 { 2113, 1, 0, 4, 121, 0, 7, 0, HexagonImpOpBase + 114, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0xb11800023ULL }, // Inst #2113 = RESTORE_DEALLOC_RET_JMP_V4_EXT_PIC
5028 { 2112, 1, 0, 4, 121, 0, 4, 0, HexagonImpOpBase + 110, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0xb11800023ULL }, // Inst #2112 = RESTORE_DEALLOC_RET_JMP_V4_EXT
5029 { 2111, 1, 0, 4, 121, 0, 4, 0, HexagonImpOpBase + 110, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0xb10800023ULL }, // Inst #2111 = RESTORE_DEALLOC_RET_JMP_V4
5030 { 2110, 1, 0, 4, 35, 0, 7, 0, HexagonImpOpBase + 114, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0xb10800023ULL }, // Inst #2110 = RESTORE_DEALLOC_BEFORE_TAILCALL_V4_PIC
5031 { 2109, 1, 0, 4, 35, 0, 7, 0, HexagonImpOpBase + 114, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0xb11800023ULL }, // Inst #2109 = RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT_PIC
5032 { 2108, 1, 0, 4, 35, 0, 4, 0, HexagonImpOpBase + 110, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0xb11800023ULL }, // Inst #2108 = RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT
5033 { 2107, 1, 0, 4, 35, 0, 4, 0, HexagonImpOpBase + 110, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0xb10800023ULL }, // Inst #2107 = RESTORE_DEALLOC_BEFORE_TAILCALL_V4
5034 { 2106, 1, 0, 4, 167, 0, 0, 272, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0xa9ULL }, // Inst #2106 = R6_release_st_vi
5035 { 2105, 1, 0, 4, 167, 0, 0, 272, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0xa9ULL }, // Inst #2105 = R6_release_at_vi
5036 { 2104, 1, 0, 4, 17, 0, 0, 0, HexagonImpOpBase + 0, 0, 0x23ULL }, // Inst #2104 = PS_trap1
5037 { 2103, 2, 0, 4, 166, 0, 0, 607, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x198a4111402fULL }, // Inst #2103 = PS_storerinewabs
5038 { 2102, 2, 0, 4, 165, 0, 0, 607, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x190a4108002fULL }, // Inst #2102 = PS_storeriabs
5039 { 2101, 2, 0, 4, 166, 0, 0, 607, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x11862111402fULL }, // Inst #2101 = PS_storerhnewabs
5040 { 2100, 2, 0, 4, 165, 0, 0, 607, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x11062108002fULL }, // Inst #2100 = PS_storerhabs
5041 { 2099, 2, 0, 4, 165, 0, 0, 607, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x11062100002fULL }, // Inst #2099 = PS_storerfabs
5042 { 2098, 2, 0, 4, 165, 0, 0, 738, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x210e6100002fULL }, // Inst #2098 = PS_storerdabs
5043 { 2097, 2, 0, 4, 166, 0, 0, 607, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x9820111402fULL }, // Inst #2097 = PS_storerbnewabs
5044 { 2096, 2, 0, 4, 165, 0, 0, 607, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x9020108002fULL }, // Inst #2096 = PS_storerbabs
5045 { 2095, 2, 1, 4, 147, 0, 0, 155, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x11062300802fULL }, // Inst #2095 = PS_loadruhabs
5046 { 2094, 2, 1, 4, 147, 0, 0, 155, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x9020300802fULL }, // Inst #2094 = PS_loadrubabs
5047 { 2093, 2, 1, 4, 147, 0, 0, 155, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x190a4300802fULL }, // Inst #2093 = PS_loadriabs
5048 { 2092, 2, 1, 4, 147, 0, 0, 155, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x11062300802fULL }, // Inst #2092 = PS_loadrhabs
5049 { 2091, 2, 1, 4, 147, 0, 0, 167, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x210e6300002fULL }, // Inst #2091 = PS_loadrdabs
5050 { 2090, 2, 1, 4, 147, 0, 0, 155, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x9020300802fULL }, // Inst #2090 = PS_loadrbabs
5051 { 2089, 2, 0, 4, 124, 0, 1, 185, HexagonImpOpBase + 55, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x801000001423ULL }, // Inst #2089 = PS_jmprettnewpt
5052 { 2088, 2, 0, 4, 124, 0, 1, 185, HexagonImpOpBase + 55, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x1000001423ULL }, // Inst #2088 = PS_jmprettnew
5053 { 2087, 2, 0, 4, 16, 0, 1, 185, HexagonImpOpBase + 55, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x1000000423ULL }, // Inst #2087 = PS_jmprett
5054 { 2086, 2, 0, 4, 124, 0, 1, 185, HexagonImpOpBase + 55, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x801000001c23ULL }, // Inst #2086 = PS_jmpretfnewpt
5055 { 2085, 2, 0, 4, 124, 0, 1, 185, HexagonImpOpBase + 55, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x1000001c23ULL }, // Inst #2085 = PS_jmpretfnew
5056 { 2084, 2, 0, 4, 16, 0, 1, 185, HexagonImpOpBase + 55, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x1000000c23ULL }, // Inst #2084 = PS_jmpretf
5057 { 2083, 1, 0, 4, 40, 0, 1, 272, HexagonImpOpBase + 55, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0x1000000023ULL }, // Inst #2083 = PS_jmpret
5058 { 2082, 1, 0, 4, 118, 0, 0, 272, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x1000000823ULL }, // Inst #2082 = PS_callr_nr
5059 { 2081, 1, 0, 4, 35, 0, 5, 0, HexagonImpOpBase + 105, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0xb10800023ULL }, // Inst #2081 = PS_call_stk
5060 { 2080, 3, 1, 4, 33, 0, 1, 557, HexagonImpOpBase + 63, 0, 0x80000000008025ULL }, // Inst #2080 = M7_wcmpyrwc_rnd
5061 { 2079, 3, 1, 4, 33, 0, 1, 557, HexagonImpOpBase + 63, 0, 0x80000000008025ULL }, // Inst #2079 = M7_wcmpyrwc
5062 { 2078, 3, 1, 4, 33, 0, 1, 557, HexagonImpOpBase + 63, 0, 0x80000000008025ULL }, // Inst #2078 = M7_wcmpyrw_rnd
5063 { 2077, 3, 1, 4, 33, 0, 1, 557, HexagonImpOpBase + 63, 0, 0x80000000008025ULL }, // Inst #2077 = M7_wcmpyrw
5064 { 2076, 3, 1, 4, 33, 0, 1, 557, HexagonImpOpBase + 63, 0, 0x80000000008025ULL }, // Inst #2076 = M7_wcmpyiwc_rnd
5065 { 2075, 3, 1, 4, 33, 0, 1, 557, HexagonImpOpBase + 63, 0, 0x80000000008025ULL }, // Inst #2075 = M7_wcmpyiwc
5066 { 2074, 3, 1, 4, 33, 0, 1, 557, HexagonImpOpBase + 63, 0, 0x80000000008025ULL }, // Inst #2074 = M7_wcmpyiw_rnd
5067 { 2073, 3, 1, 4, 33, 0, 1, 557, HexagonImpOpBase + 63, 0, 0x80000000008025ULL }, // Inst #2073 = M7_wcmpyiw
5068 { 2072, 4, 1, 4, 34, 0, 0, 215, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #2072 = M7_dcmpyrwc_acc
5069 { 2071, 3, 1, 4, 33, 0, 0, 169, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #2071 = M7_dcmpyrwc
5070 { 2070, 4, 1, 4, 34, 0, 0, 215, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #2070 = M7_dcmpyrw_acc
5071 { 2069, 3, 1, 4, 33, 0, 0, 169, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #2069 = M7_dcmpyrw
5072 { 2068, 4, 1, 4, 34, 0, 0, 215, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #2068 = M7_dcmpyiwc_acc
5073 { 2067, 3, 1, 4, 33, 0, 0, 169, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #2067 = M7_dcmpyiwc
5074 { 2066, 4, 1, 4, 34, 0, 0, 215, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #2066 = M7_dcmpyiw_acc
5075 { 2065, 3, 1, 4, 33, 0, 0, 169, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #2065 = M7_dcmpyiw
5076 { 2064, 3, 1, 4, 96, 0, 0, 169, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #2064 = M6_vabsdiffub
5077 { 2063, 3, 1, 4, 96, 0, 0, 169, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #2063 = M6_vabsdiffb
5078 { 2062, 3, 1, 4, 31, 0, 0, 169, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #2062 = M5_vrmpybuu
5079 { 2061, 3, 1, 4, 31, 0, 0, 169, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #2061 = M5_vrmpybsu
5080 { 2060, 4, 1, 4, 32, 0, 0, 215, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #2060 = M5_vrmacbuu
5081 { 2059, 4, 1, 4, 32, 0, 0, 215, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #2059 = M5_vrmacbsu
5082 { 2058, 3, 1, 4, 31, 0, 0, 519, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #2058 = M5_vmpybuu
5083 { 2057, 3, 1, 4, 31, 0, 0, 519, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #2057 = M5_vmpybsu
5084 { 2056, 4, 1, 4, 32, 0, 0, 718, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #2056 = M5_vmacbuu
5085 { 2055, 4, 1, 4, 32, 0, 0, 718, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #2055 = M5_vmacbsu
5086 { 2054, 3, 1, 4, 31, 0, 1, 169, HexagonImpOpBase + 63, 0, 0x80000000000025ULL }, // Inst #2054 = M5_vdmpybsu
5087 { 2053, 4, 1, 4, 32, 0, 1, 215, HexagonImpOpBase + 63, 0, 0x80000000000025ULL }, // Inst #2053 = M5_vdmacbsu
5088 { 2052, 4, 1, 4, 163, 0, 0, 215, HexagonImpOpBase + 0, 0, 0x8000000000002cULL }, // Inst #2052 = M4_xor_xacc
5089 { 2051, 4, 1, 4, 163, 0, 0, 590, HexagonImpOpBase + 0, 0, 0x80000000008025ULL }, // Inst #2051 = M4_xor_or
5090 { 2050, 4, 1, 4, 163, 0, 0, 590, HexagonImpOpBase + 0, 0, 0x80000000008025ULL }, // Inst #2050 = M4_xor_andn
5091 { 2049, 4, 1, 4, 163, 0, 0, 590, HexagonImpOpBase + 0, 0, 0x80000000008025ULL }, // Inst #2049 = M4_xor_and
5092 { 2048, 3, 1, 4, 31, 0, 0, 169, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #2048 = M4_vrmpyoh_s1
5093 { 2047, 3, 1, 4, 31, 0, 0, 169, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #2047 = M4_vrmpyoh_s0
5094 { 2046, 4, 1, 4, 32, 0, 0, 215, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #2046 = M4_vrmpyoh_acc_s1
5095 { 2045, 4, 1, 4, 32, 0, 0, 215, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #2045 = M4_vrmpyoh_acc_s0
5096 { 2044, 3, 1, 4, 31, 0, 0, 169, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #2044 = M4_vrmpyeh_s1
5097 { 2043, 3, 1, 4, 31, 0, 0, 169, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #2043 = M4_vrmpyeh_s0
5098 { 2042, 4, 1, 4, 32, 0, 0, 215, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #2042 = M4_vrmpyeh_acc_s1
5099 { 2041, 4, 1, 4, 32, 0, 0, 215, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #2041 = M4_vrmpyeh_acc_s0
5100 { 2040, 4, 1, 4, 32, 0, 0, 718, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #2040 = M4_vpmpyh_acc
5101 { 2039, 3, 1, 4, 31, 0, 0, 519, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #2039 = M4_vpmpyh
5102 { 2038, 4, 1, 4, 32, 0, 0, 718, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #2038 = M4_pmpyw_acc
5103 { 2037, 3, 1, 4, 31, 0, 0, 519, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #2037 = M4_pmpyw
5104 { 2036, 4, 1, 4, 163, 0, 0, 590, HexagonImpOpBase + 0, 0, 0x80000000008025ULL }, // Inst #2036 = M4_or_xor
5105 { 2035, 4, 1, 4, 163, 0, 0, 590, HexagonImpOpBase + 0, 0, 0x80000000008025ULL }, // Inst #2035 = M4_or_or
5106 { 2034, 4, 1, 4, 163, 0, 0, 590, HexagonImpOpBase + 0, 0, 0x80000000008025ULL }, // Inst #2034 = M4_or_andn
5107 { 2033, 4, 1, 4, 163, 0, 0, 590, HexagonImpOpBase + 0, 0, 0x80000000008025ULL }, // Inst #2033 = M4_or_and
5108 { 2032, 4, 1, 4, 32, 0, 1, 590, HexagonImpOpBase + 63, 0, 0x80000000008025ULL }, // Inst #2032 = M4_nac_up_s1_sat
5109 { 2031, 4, 1, 4, 32, 0, 0, 734, HexagonImpOpBase + 0, 0, 0x80000000008025ULL }, // Inst #2031 = M4_mpyrr_addr
5110 { 2030, 4, 1, 4, 32, 0, 0, 730, HexagonImpOpBase + 0, 0, 0x800000c2808003ULL }, // Inst #2030 = M4_mpyrr_addi
5111 { 2029, 4, 1, 4, 164, 0, 0, 726, HexagonImpOpBase + 0, 0, 0x80000000008003ULL }, // Inst #2029 = M4_mpyri_addr_u2
5112 { 2028, 4, 1, 4, 162, 0, 0, 219, HexagonImpOpBase + 0, 0, 0x800000c6808003ULL }, // Inst #2028 = M4_mpyri_addr
5113 { 2027, 4, 1, 4, 162, 0, 0, 722, HexagonImpOpBase + 0, 0, 0x800000c2808003ULL }, // Inst #2027 = M4_mpyri_addi
5114 { 2026, 4, 1, 4, 32, 0, 1, 590, HexagonImpOpBase + 63, 0, 0x80000000008025ULL }, // Inst #2026 = M4_mac_up_s1_sat
5115 { 2025, 3, 1, 4, 31, 0, 1, 212, HexagonImpOpBase + 63, 0, 0x8000000000802cULL }, // Inst #2025 = M4_cmpyr_whc
5116 { 2024, 3, 1, 4, 31, 0, 1, 212, HexagonImpOpBase + 63, 0, 0x8000000000802cULL }, // Inst #2024 = M4_cmpyr_wh
5117 { 2023, 3, 1, 4, 31, 0, 1, 212, HexagonImpOpBase + 63, 0, 0x8000000000802cULL }, // Inst #2023 = M4_cmpyi_whc
5118 { 2022, 3, 1, 4, 31, 0, 1, 212, HexagonImpOpBase + 63, 0, 0x8000000000802cULL }, // Inst #2022 = M4_cmpyi_wh
5119 { 2021, 4, 1, 4, 163, 0, 0, 590, HexagonImpOpBase + 0, 0, 0x80000000008025ULL }, // Inst #2021 = M4_and_xor
5120 { 2020, 4, 1, 4, 163, 0, 0, 590, HexagonImpOpBase + 0, 0, 0x80000000008025ULL }, // Inst #2020 = M4_and_or
5121 { 2019, 4, 1, 4, 163, 0, 0, 590, HexagonImpOpBase + 0, 0, 0x80000000008025ULL }, // Inst #2019 = M4_and_andn
5122 { 2018, 4, 1, 4, 163, 0, 0, 590, HexagonImpOpBase + 0, 0, 0x80000000008025ULL }, // Inst #2018 = M4_and_and
5123 { 2017, 4, 1, 4, 163, 0, 0, 590, HexagonImpOpBase + 0, 0, 0x80000000008025ULL }, // Inst #2017 = M2_xor_xacc
5124 { 2016, 3, 1, 4, 31, 0, 0, 169, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #2016 = M2_vrmpy_s0
5125 { 2015, 4, 1, 4, 32, 0, 0, 215, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #2015 = M2_vrmac_s0
5126 { 2014, 3, 1, 4, 31, 0, 1, 557, HexagonImpOpBase + 63, 0, 0x80000000008025ULL }, // Inst #2014 = M2_vrcmpys_s1rp_l
5127 { 2013, 3, 1, 4, 31, 0, 1, 557, HexagonImpOpBase + 63, 0, 0x80000000008025ULL }, // Inst #2013 = M2_vrcmpys_s1rp_h
5128 { 2012, 3, 1, 4, 31, 0, 1, 169, HexagonImpOpBase + 63, 0, 0x80000000000025ULL }, // Inst #2012 = M2_vrcmpys_s1_l
5129 { 2011, 3, 1, 4, 31, 0, 1, 169, HexagonImpOpBase + 63, 0, 0x80000000000025ULL }, // Inst #2011 = M2_vrcmpys_s1_h
5130 { 2010, 4, 1, 4, 32, 0, 1, 215, HexagonImpOpBase + 63, 0, 0x80000000000025ULL }, // Inst #2010 = M2_vrcmpys_acc_s1_l
5131 { 2009, 4, 1, 4, 32, 0, 1, 215, HexagonImpOpBase + 63, 0, 0x80000000000025ULL }, // Inst #2009 = M2_vrcmpys_acc_s1_h
5132 { 2008, 3, 1, 4, 31, 0, 0, 169, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #2008 = M2_vrcmpyr_s0c
5133 { 2007, 3, 1, 4, 31, 0, 0, 169, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #2007 = M2_vrcmpyr_s0
5134 { 2006, 3, 1, 4, 31, 0, 0, 169, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #2006 = M2_vrcmpyi_s0c
5135 { 2005, 3, 1, 4, 31, 0, 0, 169, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #2005 = M2_vrcmpyi_s0
5136 { 2004, 4, 1, 4, 32, 0, 0, 215, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #2004 = M2_vrcmacr_s0c
5137 { 2003, 4, 1, 4, 32, 0, 0, 215, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #2003 = M2_vrcmacr_s0
5138 { 2002, 4, 1, 4, 32, 0, 0, 215, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #2002 = M2_vrcmaci_s0c
5139 { 2001, 4, 1, 4, 32, 0, 0, 215, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #2001 = M2_vrcmaci_s0
5140 { 2000, 3, 1, 4, 31, 0, 0, 557, HexagonImpOpBase + 0, 0, 0x80000000008025ULL }, // Inst #2000 = M2_vradduh
5141 { 1999, 3, 1, 4, 31, 0, 0, 557, HexagonImpOpBase + 0, 0, 0x80000000008025ULL }, // Inst #1999 = M2_vraddh
5142 { 1998, 3, 1, 4, 31, 0, 1, 519, HexagonImpOpBase + 63, 0, 0x80000000000025ULL }, // Inst #1998 = M2_vmpy2su_s1
5143 { 1997, 3, 1, 4, 31, 0, 1, 519, HexagonImpOpBase + 63, 0, 0x80000000000025ULL }, // Inst #1997 = M2_vmpy2su_s0
5144 { 1996, 3, 1, 4, 31, 0, 1, 202, HexagonImpOpBase + 63, 0, 0x80000000008025ULL }, // Inst #1996 = M2_vmpy2s_s1pack
5145 { 1995, 3, 1, 4, 31, 0, 1, 519, HexagonImpOpBase + 63, 0, 0x80000000000025ULL }, // Inst #1995 = M2_vmpy2s_s1
5146 { 1994, 3, 1, 4, 31, 0, 1, 202, HexagonImpOpBase + 63, 0, 0x80000000008025ULL }, // Inst #1994 = M2_vmpy2s_s0pack
5147 { 1993, 3, 1, 4, 31, 0, 1, 519, HexagonImpOpBase + 63, 0, 0x80000000000025ULL }, // Inst #1993 = M2_vmpy2s_s0
5148 { 1992, 3, 1, 4, 31, 0, 1, 169, HexagonImpOpBase + 63, 0, 0x80000000000025ULL }, // Inst #1992 = M2_vmpy2es_s1
5149 { 1991, 3, 1, 4, 31, 0, 1, 169, HexagonImpOpBase + 63, 0, 0x80000000000025ULL }, // Inst #1991 = M2_vmpy2es_s0
5150 { 1990, 4, 1, 4, 32, 0, 1, 718, HexagonImpOpBase + 63, 0, 0x80000000000025ULL }, // Inst #1990 = M2_vmac2su_s1
5151 { 1989, 4, 1, 4, 32, 0, 1, 718, HexagonImpOpBase + 63, 0, 0x80000000000025ULL }, // Inst #1989 = M2_vmac2su_s0
5152 { 1988, 4, 1, 4, 32, 0, 1, 718, HexagonImpOpBase + 63, 0, 0x80000000000025ULL }, // Inst #1988 = M2_vmac2s_s1
5153 { 1987, 4, 1, 4, 32, 0, 1, 718, HexagonImpOpBase + 63, 0, 0x80000000000025ULL }, // Inst #1987 = M2_vmac2s_s0
5154 { 1986, 4, 1, 4, 32, 0, 1, 215, HexagonImpOpBase + 63, 0, 0x80000000000025ULL }, // Inst #1986 = M2_vmac2es_s1
5155 { 1985, 4, 1, 4, 32, 0, 1, 215, HexagonImpOpBase + 63, 0, 0x80000000000025ULL }, // Inst #1985 = M2_vmac2es_s0
5156 { 1984, 4, 1, 4, 32, 0, 0, 215, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #1984 = M2_vmac2es
5157 { 1983, 4, 1, 4, 32, 0, 0, 718, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #1983 = M2_vmac2
5158 { 1982, 3, 1, 4, 31, 0, 1, 169, HexagonImpOpBase + 63, 0, 0x80000000000025ULL }, // Inst #1982 = M2_vdmpys_s1
5159 { 1981, 3, 1, 4, 31, 0, 1, 169, HexagonImpOpBase + 63, 0, 0x80000000000025ULL }, // Inst #1981 = M2_vdmpys_s0
5160 { 1980, 3, 1, 4, 31, 0, 1, 557, HexagonImpOpBase + 63, 0, 0x80000000008025ULL }, // Inst #1980 = M2_vdmpyrs_s1
5161 { 1979, 3, 1, 4, 31, 0, 1, 557, HexagonImpOpBase + 63, 0, 0x80000000008025ULL }, // Inst #1979 = M2_vdmpyrs_s0
5162 { 1978, 4, 1, 4, 32, 0, 1, 215, HexagonImpOpBase + 63, 0, 0x80000000000025ULL }, // Inst #1978 = M2_vdmacs_s1
5163 { 1977, 4, 1, 4, 32, 0, 1, 215, HexagonImpOpBase + 63, 0, 0x80000000000025ULL }, // Inst #1977 = M2_vdmacs_s0
5164 { 1976, 3, 1, 4, 31, 0, 1, 169, HexagonImpOpBase + 63, 0, 0x80000000000025ULL }, // Inst #1976 = M2_vcmpy_s1_sat_r
5165 { 1975, 3, 1, 4, 31, 0, 1, 169, HexagonImpOpBase + 63, 0, 0x80000000000025ULL }, // Inst #1975 = M2_vcmpy_s1_sat_i
5166 { 1974, 3, 1, 4, 31, 0, 1, 169, HexagonImpOpBase + 63, 0, 0x80000000000025ULL }, // Inst #1974 = M2_vcmpy_s0_sat_r
5167 { 1973, 3, 1, 4, 31, 0, 1, 169, HexagonImpOpBase + 63, 0, 0x80000000000025ULL }, // Inst #1973 = M2_vcmpy_s0_sat_i
5168 { 1972, 4, 1, 4, 32, 0, 1, 215, HexagonImpOpBase + 63, 0, 0x80000000000025ULL }, // Inst #1972 = M2_vcmac_s0_sat_r
5169 { 1971, 4, 1, 4, 32, 0, 1, 215, HexagonImpOpBase + 63, 0, 0x80000000000025ULL }, // Inst #1971 = M2_vcmac_s0_sat_i
5170 { 1970, 3, 1, 4, 48, 0, 0, 169, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #1970 = M2_vabsdiffw
5171 { 1969, 3, 1, 4, 48, 0, 0, 169, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #1969 = M2_vabsdiffh
5172 { 1968, 4, 1, 4, 161, 0, 0, 590, HexagonImpOpBase + 0, 0, 0x80000000008025ULL }, // Inst #1968 = M2_subacc
5173 { 1967, 4, 1, 4, 161, 0, 0, 714, HexagonImpOpBase + 0, 0, 0x80000116808025ULL }, // Inst #1967 = M2_naccii
5174 { 1966, 4, 1, 4, 161, 0, 0, 590, HexagonImpOpBase + 0, 0, 0x80000000008025ULL }, // Inst #1966 = M2_nacci
5175 { 1965, 4, 1, 4, 32, 0, 0, 718, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #1965 = M2_mpyud_nac_ll_s1
5176 { 1964, 4, 1, 4, 32, 0, 0, 718, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #1964 = M2_mpyud_nac_ll_s0
5177 { 1963, 4, 1, 4, 32, 0, 0, 718, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #1963 = M2_mpyud_nac_lh_s1
5178 { 1962, 4, 1, 4, 32, 0, 0, 718, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #1962 = M2_mpyud_nac_lh_s0
5179 { 1961, 4, 1, 4, 32, 0, 0, 718, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #1961 = M2_mpyud_nac_hl_s1
5180 { 1960, 4, 1, 4, 32, 0, 0, 718, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #1960 = M2_mpyud_nac_hl_s0
5181 { 1959, 4, 1, 4, 32, 0, 0, 718, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #1959 = M2_mpyud_nac_hh_s1
5182 { 1958, 4, 1, 4, 32, 0, 0, 718, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #1958 = M2_mpyud_nac_hh_s0
5183 { 1957, 3, 1, 4, 31, 0, 0, 519, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #1957 = M2_mpyud_ll_s1
5184 { 1956, 3, 1, 4, 31, 0, 0, 519, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #1956 = M2_mpyud_ll_s0
5185 { 1955, 3, 1, 4, 31, 0, 0, 519, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #1955 = M2_mpyud_lh_s1
5186 { 1954, 3, 1, 4, 31, 0, 0, 519, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #1954 = M2_mpyud_lh_s0
5187 { 1953, 3, 1, 4, 31, 0, 0, 519, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #1953 = M2_mpyud_hl_s1
5188 { 1952, 3, 1, 4, 31, 0, 0, 519, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #1952 = M2_mpyud_hl_s0
5189 { 1951, 3, 1, 4, 31, 0, 0, 519, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #1951 = M2_mpyud_hh_s1
5190 { 1950, 3, 1, 4, 31, 0, 0, 519, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #1950 = M2_mpyud_hh_s0
5191 { 1949, 4, 1, 4, 32, 0, 0, 718, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #1949 = M2_mpyud_acc_ll_s1
5192 { 1948, 4, 1, 4, 32, 0, 0, 718, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #1948 = M2_mpyud_acc_ll_s0
5193 { 1947, 4, 1, 4, 32, 0, 0, 718, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #1947 = M2_mpyud_acc_lh_s1
5194 { 1946, 4, 1, 4, 32, 0, 0, 718, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #1946 = M2_mpyud_acc_lh_s0
5195 { 1945, 4, 1, 4, 32, 0, 0, 718, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #1945 = M2_mpyud_acc_hl_s1
5196 { 1944, 4, 1, 4, 32, 0, 0, 718, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #1944 = M2_mpyud_acc_hl_s0
5197 { 1943, 4, 1, 4, 32, 0, 0, 718, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #1943 = M2_mpyud_acc_hh_s1
5198 { 1942, 4, 1, 4, 32, 0, 0, 718, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #1942 = M2_mpyud_acc_hh_s0
5199 { 1941, 3, 1, 4, 31, 0, 0, 202, HexagonImpOpBase + 0, 0, 0x80000000008025ULL }, // Inst #1941 = M2_mpyu_up
5200 { 1940, 4, 1, 4, 32, 0, 0, 590, HexagonImpOpBase + 0, 0, 0x80000000008025ULL }, // Inst #1940 = M2_mpyu_nac_ll_s1
5201 { 1939, 4, 1, 4, 32, 0, 0, 590, HexagonImpOpBase + 0, 0, 0x80000000008025ULL }, // Inst #1939 = M2_mpyu_nac_ll_s0
5202 { 1938, 4, 1, 4, 32, 0, 0, 590, HexagonImpOpBase + 0, 0, 0x80000000008025ULL }, // Inst #1938 = M2_mpyu_nac_lh_s1
5203 { 1937, 4, 1, 4, 32, 0, 0, 590, HexagonImpOpBase + 0, 0, 0x80000000008025ULL }, // Inst #1937 = M2_mpyu_nac_lh_s0
5204 { 1936, 4, 1, 4, 32, 0, 0, 590, HexagonImpOpBase + 0, 0, 0x80000000008025ULL }, // Inst #1936 = M2_mpyu_nac_hl_s1
5205 { 1935, 4, 1, 4, 32, 0, 0, 590, HexagonImpOpBase + 0, 0, 0x80000000008025ULL }, // Inst #1935 = M2_mpyu_nac_hl_s0
5206 { 1934, 4, 1, 4, 32, 0, 0, 590, HexagonImpOpBase + 0, 0, 0x80000000008025ULL }, // Inst #1934 = M2_mpyu_nac_hh_s1
5207 { 1933, 4, 1, 4, 32, 0, 0, 590, HexagonImpOpBase + 0, 0, 0x80000000008025ULL }, // Inst #1933 = M2_mpyu_nac_hh_s0
5208 { 1932, 3, 1, 4, 31, 0, 0, 202, HexagonImpOpBase + 0, 0, 0x80000000008025ULL }, // Inst #1932 = M2_mpyu_ll_s1
5209 { 1931, 3, 1, 4, 31, 0, 0, 202, HexagonImpOpBase + 0, 0, 0x80000000008025ULL }, // Inst #1931 = M2_mpyu_ll_s0
5210 { 1930, 3, 1, 4, 31, 0, 0, 202, HexagonImpOpBase + 0, 0, 0x80000000008025ULL }, // Inst #1930 = M2_mpyu_lh_s1
5211 { 1929, 3, 1, 4, 31, 0, 0, 202, HexagonImpOpBase + 0, 0, 0x80000000008025ULL }, // Inst #1929 = M2_mpyu_lh_s0
5212 { 1928, 3, 1, 4, 31, 0, 0, 202, HexagonImpOpBase + 0, 0, 0x80000000008025ULL }, // Inst #1928 = M2_mpyu_hl_s1
5213 { 1927, 3, 1, 4, 31, 0, 0, 202, HexagonImpOpBase + 0, 0, 0x80000000008025ULL }, // Inst #1927 = M2_mpyu_hl_s0
5214 { 1926, 3, 1, 4, 31, 0, 0, 202, HexagonImpOpBase + 0, 0, 0x80000000008025ULL }, // Inst #1926 = M2_mpyu_hh_s1
5215 { 1925, 3, 1, 4, 31, 0, 0, 202, HexagonImpOpBase + 0, 0, 0x80000000008025ULL }, // Inst #1925 = M2_mpyu_hh_s0
5216 { 1924, 4, 1, 4, 32, 0, 0, 590, HexagonImpOpBase + 0, 0, 0x80000000008025ULL }, // Inst #1924 = M2_mpyu_acc_ll_s1
5217 { 1923, 4, 1, 4, 32, 0, 0, 590, HexagonImpOpBase + 0, 0, 0x80000000008025ULL }, // Inst #1923 = M2_mpyu_acc_ll_s0
5218 { 1922, 4, 1, 4, 32, 0, 0, 590, HexagonImpOpBase + 0, 0, 0x80000000008025ULL }, // Inst #1922 = M2_mpyu_acc_lh_s1
5219 { 1921, 4, 1, 4, 32, 0, 0, 590, HexagonImpOpBase + 0, 0, 0x80000000008025ULL }, // Inst #1921 = M2_mpyu_acc_lh_s0
5220 { 1920, 4, 1, 4, 32, 0, 0, 590, HexagonImpOpBase + 0, 0, 0x80000000008025ULL }, // Inst #1920 = M2_mpyu_acc_hl_s1
5221 { 1919, 4, 1, 4, 32, 0, 0, 590, HexagonImpOpBase + 0, 0, 0x80000000008025ULL }, // Inst #1919 = M2_mpyu_acc_hl_s0
5222 { 1918, 4, 1, 4, 32, 0, 0, 590, HexagonImpOpBase + 0, 0, 0x80000000008025ULL }, // Inst #1918 = M2_mpyu_acc_hh_s1
5223 { 1917, 4, 1, 4, 32, 0, 0, 590, HexagonImpOpBase + 0, 0, 0x80000000008025ULL }, // Inst #1917 = M2_mpyu_acc_hh_s0
5224 { 1916, 3, 1, 4, 31, 0, 0, 202, HexagonImpOpBase + 0, 0, 0x80000000008025ULL }, // Inst #1916 = M2_mpysu_up
5225 { 1915, 3, 1, 4, 30, 0, 0, 199, HexagonImpOpBase + 0, 0, 0x80000104808025ULL }, // Inst #1915 = M2_mpysip
5226 { 1914, 3, 1, 4, 30, 0, 0, 199, HexagonImpOpBase + 0, 0, 0x80000000008025ULL }, // Inst #1914 = M2_mpysin
5227 { 1913, 3, 1, 4, 31, 0, 0, 202, HexagonImpOpBase + 0, 0, 0x80000000008025ULL }, // Inst #1913 = M2_mpyi
5228 { 1912, 3, 1, 4, 31, 0, 0, 519, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #1912 = M2_mpyd_rnd_ll_s1
5229 { 1911, 3, 1, 4, 31, 0, 0, 519, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #1911 = M2_mpyd_rnd_ll_s0
5230 { 1910, 3, 1, 4, 31, 0, 0, 519, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #1910 = M2_mpyd_rnd_lh_s1
5231 { 1909, 3, 1, 4, 31, 0, 0, 519, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #1909 = M2_mpyd_rnd_lh_s0
5232 { 1908, 3, 1, 4, 31, 0, 0, 519, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #1908 = M2_mpyd_rnd_hl_s1
5233 { 1907, 3, 1, 4, 31, 0, 0, 519, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #1907 = M2_mpyd_rnd_hl_s0
5234 { 1906, 3, 1, 4, 31, 0, 0, 519, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #1906 = M2_mpyd_rnd_hh_s1
5235 { 1905, 3, 1, 4, 31, 0, 0, 519, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #1905 = M2_mpyd_rnd_hh_s0
5236 { 1904, 4, 1, 4, 32, 0, 0, 718, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #1904 = M2_mpyd_nac_ll_s1
5237 { 1903, 4, 1, 4, 32, 0, 0, 718, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #1903 = M2_mpyd_nac_ll_s0
5238 { 1902, 4, 1, 4, 32, 0, 0, 718, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #1902 = M2_mpyd_nac_lh_s1
5239 { 1901, 4, 1, 4, 32, 0, 0, 718, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #1901 = M2_mpyd_nac_lh_s0
5240 { 1900, 4, 1, 4, 32, 0, 0, 718, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #1900 = M2_mpyd_nac_hl_s1
5241 { 1899, 4, 1, 4, 32, 0, 0, 718, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #1899 = M2_mpyd_nac_hl_s0
5242 { 1898, 4, 1, 4, 32, 0, 0, 718, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #1898 = M2_mpyd_nac_hh_s1
5243 { 1897, 4, 1, 4, 32, 0, 0, 718, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #1897 = M2_mpyd_nac_hh_s0
5244 { 1896, 3, 1, 4, 31, 0, 0, 519, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #1896 = M2_mpyd_ll_s1
5245 { 1895, 3, 1, 4, 31, 0, 0, 519, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #1895 = M2_mpyd_ll_s0
5246 { 1894, 3, 1, 4, 31, 0, 0, 519, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #1894 = M2_mpyd_lh_s1
5247 { 1893, 3, 1, 4, 31, 0, 0, 519, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #1893 = M2_mpyd_lh_s0
5248 { 1892, 3, 1, 4, 31, 0, 0, 519, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #1892 = M2_mpyd_hl_s1
5249 { 1891, 3, 1, 4, 31, 0, 0, 519, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #1891 = M2_mpyd_hl_s0
5250 { 1890, 3, 1, 4, 31, 0, 0, 519, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #1890 = M2_mpyd_hh_s1
5251 { 1889, 3, 1, 4, 31, 0, 0, 519, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #1889 = M2_mpyd_hh_s0
5252 { 1888, 4, 1, 4, 32, 0, 0, 718, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #1888 = M2_mpyd_acc_ll_s1
5253 { 1887, 4, 1, 4, 32, 0, 0, 718, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #1887 = M2_mpyd_acc_ll_s0
5254 { 1886, 4, 1, 4, 32, 0, 0, 718, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #1886 = M2_mpyd_acc_lh_s1
5255 { 1885, 4, 1, 4, 32, 0, 0, 718, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #1885 = M2_mpyd_acc_lh_s0
5256 { 1884, 4, 1, 4, 32, 0, 0, 718, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #1884 = M2_mpyd_acc_hl_s1
5257 { 1883, 4, 1, 4, 32, 0, 0, 718, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #1883 = M2_mpyd_acc_hl_s0
5258 { 1882, 4, 1, 4, 32, 0, 0, 718, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #1882 = M2_mpyd_acc_hh_s1
5259 { 1881, 4, 1, 4, 32, 0, 0, 718, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #1881 = M2_mpyd_acc_hh_s0
5260 { 1880, 3, 1, 4, 31, 0, 1, 202, HexagonImpOpBase + 63, 0, 0x80000000008025ULL }, // Inst #1880 = M2_mpy_up_s1_sat
5261 { 1879, 3, 1, 4, 31, 0, 0, 202, HexagonImpOpBase + 0, 0, 0x80000000008025ULL }, // Inst #1879 = M2_mpy_up_s1
5262 { 1878, 3, 1, 4, 31, 0, 0, 202, HexagonImpOpBase + 0, 0, 0x80000000008025ULL }, // Inst #1878 = M2_mpy_up
5263 { 1877, 3, 1, 4, 31, 0, 1, 202, HexagonImpOpBase + 63, 0, 0x80000000008025ULL }, // Inst #1877 = M2_mpy_sat_rnd_ll_s1
5264 { 1876, 3, 1, 4, 31, 0, 1, 202, HexagonImpOpBase + 63, 0, 0x80000000008025ULL }, // Inst #1876 = M2_mpy_sat_rnd_ll_s0
5265 { 1875, 3, 1, 4, 31, 0, 1, 202, HexagonImpOpBase + 63, 0, 0x80000000008025ULL }, // Inst #1875 = M2_mpy_sat_rnd_lh_s1
5266 { 1874, 3, 1, 4, 31, 0, 1, 202, HexagonImpOpBase + 63, 0, 0x80000000008025ULL }, // Inst #1874 = M2_mpy_sat_rnd_lh_s0
5267 { 1873, 3, 1, 4, 31, 0, 1, 202, HexagonImpOpBase + 63, 0, 0x80000000008025ULL }, // Inst #1873 = M2_mpy_sat_rnd_hl_s1
5268 { 1872, 3, 1, 4, 31, 0, 1, 202, HexagonImpOpBase + 63, 0, 0x80000000008025ULL }, // Inst #1872 = M2_mpy_sat_rnd_hl_s0
5269 { 1871, 3, 1, 4, 31, 0, 1, 202, HexagonImpOpBase + 63, 0, 0x80000000008025ULL }, // Inst #1871 = M2_mpy_sat_rnd_hh_s1
5270 { 1870, 3, 1, 4, 31, 0, 1, 202, HexagonImpOpBase + 63, 0, 0x80000000008025ULL }, // Inst #1870 = M2_mpy_sat_rnd_hh_s0
5271 { 1869, 3, 1, 4, 31, 0, 1, 202, HexagonImpOpBase + 63, 0, 0x80000000008025ULL }, // Inst #1869 = M2_mpy_sat_ll_s1
5272 { 1868, 3, 1, 4, 31, 0, 1, 202, HexagonImpOpBase + 63, 0, 0x80000000008025ULL }, // Inst #1868 = M2_mpy_sat_ll_s0
5273 { 1867, 3, 1, 4, 31, 0, 1, 202, HexagonImpOpBase + 63, 0, 0x80000000008025ULL }, // Inst #1867 = M2_mpy_sat_lh_s1
5274 { 1866, 3, 1, 4, 31, 0, 1, 202, HexagonImpOpBase + 63, 0, 0x80000000008025ULL }, // Inst #1866 = M2_mpy_sat_lh_s0
5275 { 1865, 3, 1, 4, 31, 0, 1, 202, HexagonImpOpBase + 63, 0, 0x80000000008025ULL }, // Inst #1865 = M2_mpy_sat_hl_s1
5276 { 1864, 3, 1, 4, 31, 0, 1, 202, HexagonImpOpBase + 63, 0, 0x80000000008025ULL }, // Inst #1864 = M2_mpy_sat_hl_s0
5277 { 1863, 3, 1, 4, 31, 0, 1, 202, HexagonImpOpBase + 63, 0, 0x80000000008025ULL }, // Inst #1863 = M2_mpy_sat_hh_s1
5278 { 1862, 3, 1, 4, 31, 0, 1, 202, HexagonImpOpBase + 63, 0, 0x80000000008025ULL }, // Inst #1862 = M2_mpy_sat_hh_s0
5279 { 1861, 3, 1, 4, 31, 0, 0, 202, HexagonImpOpBase + 0, 0, 0x80000000008025ULL }, // Inst #1861 = M2_mpy_rnd_ll_s1
5280 { 1860, 3, 1, 4, 31, 0, 0, 202, HexagonImpOpBase + 0, 0, 0x80000000008025ULL }, // Inst #1860 = M2_mpy_rnd_ll_s0
5281 { 1859, 3, 1, 4, 31, 0, 0, 202, HexagonImpOpBase + 0, 0, 0x80000000008025ULL }, // Inst #1859 = M2_mpy_rnd_lh_s1
5282 { 1858, 3, 1, 4, 31, 0, 0, 202, HexagonImpOpBase + 0, 0, 0x80000000008025ULL }, // Inst #1858 = M2_mpy_rnd_lh_s0
5283 { 1857, 3, 1, 4, 31, 0, 0, 202, HexagonImpOpBase + 0, 0, 0x80000000008025ULL }, // Inst #1857 = M2_mpy_rnd_hl_s1
5284 { 1856, 3, 1, 4, 31, 0, 0, 202, HexagonImpOpBase + 0, 0, 0x80000000008025ULL }, // Inst #1856 = M2_mpy_rnd_hl_s0
5285 { 1855, 3, 1, 4, 31, 0, 0, 202, HexagonImpOpBase + 0, 0, 0x80000000008025ULL }, // Inst #1855 = M2_mpy_rnd_hh_s1
5286 { 1854, 3, 1, 4, 31, 0, 0, 202, HexagonImpOpBase + 0, 0, 0x80000000008025ULL }, // Inst #1854 = M2_mpy_rnd_hh_s0
5287 { 1853, 4, 1, 4, 32, 0, 1, 590, HexagonImpOpBase + 63, 0, 0x80000000008025ULL }, // Inst #1853 = M2_mpy_nac_sat_ll_s1
5288 { 1852, 4, 1, 4, 32, 0, 1, 590, HexagonImpOpBase + 63, 0, 0x80000000008025ULL }, // Inst #1852 = M2_mpy_nac_sat_ll_s0
5289 { 1851, 4, 1, 4, 32, 0, 1, 590, HexagonImpOpBase + 63, 0, 0x80000000008025ULL }, // Inst #1851 = M2_mpy_nac_sat_lh_s1
5290 { 1850, 4, 1, 4, 32, 0, 1, 590, HexagonImpOpBase + 63, 0, 0x80000000008025ULL }, // Inst #1850 = M2_mpy_nac_sat_lh_s0
5291 { 1849, 4, 1, 4, 32, 0, 1, 590, HexagonImpOpBase + 63, 0, 0x80000000008025ULL }, // Inst #1849 = M2_mpy_nac_sat_hl_s1
5292 { 1848, 4, 1, 4, 32, 0, 1, 590, HexagonImpOpBase + 63, 0, 0x80000000008025ULL }, // Inst #1848 = M2_mpy_nac_sat_hl_s0
5293 { 1847, 4, 1, 4, 32, 0, 1, 590, HexagonImpOpBase + 63, 0, 0x80000000008025ULL }, // Inst #1847 = M2_mpy_nac_sat_hh_s1
5294 { 1846, 4, 1, 4, 32, 0, 1, 590, HexagonImpOpBase + 63, 0, 0x80000000008025ULL }, // Inst #1846 = M2_mpy_nac_sat_hh_s0
5295 { 1845, 4, 1, 4, 32, 0, 0, 590, HexagonImpOpBase + 0, 0, 0x80000000008025ULL }, // Inst #1845 = M2_mpy_nac_ll_s1
5296 { 1844, 4, 1, 4, 32, 0, 0, 590, HexagonImpOpBase + 0, 0, 0x80000000008025ULL }, // Inst #1844 = M2_mpy_nac_ll_s0
5297 { 1843, 4, 1, 4, 32, 0, 0, 590, HexagonImpOpBase + 0, 0, 0x80000000008025ULL }, // Inst #1843 = M2_mpy_nac_lh_s1
5298 { 1842, 4, 1, 4, 32, 0, 0, 590, HexagonImpOpBase + 0, 0, 0x80000000008025ULL }, // Inst #1842 = M2_mpy_nac_lh_s0
5299 { 1841, 4, 1, 4, 32, 0, 0, 590, HexagonImpOpBase + 0, 0, 0x80000000008025ULL }, // Inst #1841 = M2_mpy_nac_hl_s1
5300 { 1840, 4, 1, 4, 32, 0, 0, 590, HexagonImpOpBase + 0, 0, 0x80000000008025ULL }, // Inst #1840 = M2_mpy_nac_hl_s0
5301 { 1839, 4, 1, 4, 32, 0, 0, 590, HexagonImpOpBase + 0, 0, 0x80000000008025ULL }, // Inst #1839 = M2_mpy_nac_hh_s1
5302 { 1838, 4, 1, 4, 32, 0, 0, 590, HexagonImpOpBase + 0, 0, 0x80000000008025ULL }, // Inst #1838 = M2_mpy_nac_hh_s0
5303 { 1837, 3, 1, 4, 31, 0, 0, 202, HexagonImpOpBase + 0, 0, 0x80000000008025ULL }, // Inst #1837 = M2_mpy_ll_s1
5304 { 1836, 3, 1, 4, 31, 0, 0, 202, HexagonImpOpBase + 0, 0, 0x80000000008025ULL }, // Inst #1836 = M2_mpy_ll_s0
5305 { 1835, 3, 1, 4, 31, 0, 0, 202, HexagonImpOpBase + 0, 0, 0x80000000008025ULL }, // Inst #1835 = M2_mpy_lh_s1
5306 { 1834, 3, 1, 4, 31, 0, 0, 202, HexagonImpOpBase + 0, 0, 0x80000000008025ULL }, // Inst #1834 = M2_mpy_lh_s0
5307 { 1833, 3, 1, 4, 31, 0, 0, 202, HexagonImpOpBase + 0, 0, 0x80000000008025ULL }, // Inst #1833 = M2_mpy_hl_s1
5308 { 1832, 3, 1, 4, 31, 0, 0, 202, HexagonImpOpBase + 0, 0, 0x80000000008025ULL }, // Inst #1832 = M2_mpy_hl_s0
5309 { 1831, 3, 1, 4, 31, 0, 0, 202, HexagonImpOpBase + 0, 0, 0x80000000008025ULL }, // Inst #1831 = M2_mpy_hh_s1
5310 { 1830, 3, 1, 4, 31, 0, 0, 202, HexagonImpOpBase + 0, 0, 0x80000000008025ULL }, // Inst #1830 = M2_mpy_hh_s0
5311 { 1829, 4, 1, 4, 32, 0, 1, 590, HexagonImpOpBase + 63, 0, 0x80000000008025ULL }, // Inst #1829 = M2_mpy_acc_sat_ll_s1
5312 { 1828, 4, 1, 4, 32, 0, 1, 590, HexagonImpOpBase + 63, 0, 0x80000000008025ULL }, // Inst #1828 = M2_mpy_acc_sat_ll_s0
5313 { 1827, 4, 1, 4, 32, 0, 1, 590, HexagonImpOpBase + 63, 0, 0x80000000008025ULL }, // Inst #1827 = M2_mpy_acc_sat_lh_s1
5314 { 1826, 4, 1, 4, 32, 0, 1, 590, HexagonImpOpBase + 63, 0, 0x80000000008025ULL }, // Inst #1826 = M2_mpy_acc_sat_lh_s0
5315 { 1825, 4, 1, 4, 32, 0, 1, 590, HexagonImpOpBase + 63, 0, 0x80000000008025ULL }, // Inst #1825 = M2_mpy_acc_sat_hl_s1
5316 { 1824, 4, 1, 4, 32, 0, 1, 590, HexagonImpOpBase + 63, 0, 0x80000000008025ULL }, // Inst #1824 = M2_mpy_acc_sat_hl_s0
5317 { 1823, 4, 1, 4, 32, 0, 1, 590, HexagonImpOpBase + 63, 0, 0x80000000008025ULL }, // Inst #1823 = M2_mpy_acc_sat_hh_s1
5318 { 1822, 4, 1, 4, 32, 0, 1, 590, HexagonImpOpBase + 63, 0, 0x80000000008025ULL }, // Inst #1822 = M2_mpy_acc_sat_hh_s0
5319 { 1821, 4, 1, 4, 32, 0, 0, 590, HexagonImpOpBase + 0, 0, 0x80000000008025ULL }, // Inst #1821 = M2_mpy_acc_ll_s1
5320 { 1820, 4, 1, 4, 32, 0, 0, 590, HexagonImpOpBase + 0, 0, 0x80000000008025ULL }, // Inst #1820 = M2_mpy_acc_ll_s0
5321 { 1819, 4, 1, 4, 32, 0, 0, 590, HexagonImpOpBase + 0, 0, 0x80000000008025ULL }, // Inst #1819 = M2_mpy_acc_lh_s1
5322 { 1818, 4, 1, 4, 32, 0, 0, 590, HexagonImpOpBase + 0, 0, 0x80000000008025ULL }, // Inst #1818 = M2_mpy_acc_lh_s0
5323 { 1817, 4, 1, 4, 32, 0, 0, 590, HexagonImpOpBase + 0, 0, 0x80000000008025ULL }, // Inst #1817 = M2_mpy_acc_hl_s1
5324 { 1816, 4, 1, 4, 32, 0, 0, 590, HexagonImpOpBase + 0, 0, 0x80000000008025ULL }, // Inst #1816 = M2_mpy_acc_hl_s0
5325 { 1815, 4, 1, 4, 32, 0, 0, 590, HexagonImpOpBase + 0, 0, 0x80000000008025ULL }, // Inst #1815 = M2_mpy_acc_hh_s1
5326 { 1814, 4, 1, 4, 32, 0, 0, 590, HexagonImpOpBase + 0, 0, 0x80000000008025ULL }, // Inst #1814 = M2_mpy_acc_hh_s0
5327 { 1813, 4, 1, 4, 107, 0, 0, 590, HexagonImpOpBase + 0, 0, 0x80000000008025ULL }, // Inst #1813 = M2_mnaci
5328 { 1812, 3, 1, 4, 31, 0, 1, 169, HexagonImpOpBase + 63, 0, 0x80000000000025ULL }, // Inst #1812 = M2_mmpyul_s1
5329 { 1811, 3, 1, 4, 31, 0, 1, 169, HexagonImpOpBase + 63, 0, 0x80000000000025ULL }, // Inst #1811 = M2_mmpyul_s0
5330 { 1810, 3, 1, 4, 31, 0, 1, 169, HexagonImpOpBase + 63, 0, 0x80000000000025ULL }, // Inst #1810 = M2_mmpyul_rs1
5331 { 1809, 3, 1, 4, 31, 0, 1, 169, HexagonImpOpBase + 63, 0, 0x80000000000025ULL }, // Inst #1809 = M2_mmpyul_rs0
5332 { 1808, 3, 1, 4, 31, 0, 1, 169, HexagonImpOpBase + 63, 0, 0x80000000000025ULL }, // Inst #1808 = M2_mmpyuh_s1
5333 { 1807, 3, 1, 4, 31, 0, 1, 169, HexagonImpOpBase + 63, 0, 0x80000000000025ULL }, // Inst #1807 = M2_mmpyuh_s0
5334 { 1806, 3, 1, 4, 31, 0, 1, 169, HexagonImpOpBase + 63, 0, 0x80000000000025ULL }, // Inst #1806 = M2_mmpyuh_rs1
5335 { 1805, 3, 1, 4, 31, 0, 1, 169, HexagonImpOpBase + 63, 0, 0x80000000000025ULL }, // Inst #1805 = M2_mmpyuh_rs0
5336 { 1804, 3, 1, 4, 31, 0, 1, 169, HexagonImpOpBase + 63, 0, 0x80000000000025ULL }, // Inst #1804 = M2_mmpyl_s1
5337 { 1803, 3, 1, 4, 31, 0, 1, 169, HexagonImpOpBase + 63, 0, 0x80000000000025ULL }, // Inst #1803 = M2_mmpyl_s0
5338 { 1802, 3, 1, 4, 31, 0, 1, 169, HexagonImpOpBase + 63, 0, 0x80000000000025ULL }, // Inst #1802 = M2_mmpyl_rs1
5339 { 1801, 3, 1, 4, 31, 0, 1, 169, HexagonImpOpBase + 63, 0, 0x80000000000025ULL }, // Inst #1801 = M2_mmpyl_rs0
5340 { 1800, 3, 1, 4, 31, 0, 1, 169, HexagonImpOpBase + 63, 0, 0x80000000000025ULL }, // Inst #1800 = M2_mmpyh_s1
5341 { 1799, 3, 1, 4, 31, 0, 1, 169, HexagonImpOpBase + 63, 0, 0x80000000000025ULL }, // Inst #1799 = M2_mmpyh_s0
5342 { 1798, 3, 1, 4, 31, 0, 1, 169, HexagonImpOpBase + 63, 0, 0x80000000000025ULL }, // Inst #1798 = M2_mmpyh_rs1
5343 { 1797, 3, 1, 4, 31, 0, 1, 169, HexagonImpOpBase + 63, 0, 0x80000000000025ULL }, // Inst #1797 = M2_mmpyh_rs0
5344 { 1796, 4, 1, 4, 32, 0, 1, 215, HexagonImpOpBase + 63, 0, 0x80000000000025ULL }, // Inst #1796 = M2_mmaculs_s1
5345 { 1795, 4, 1, 4, 32, 0, 1, 215, HexagonImpOpBase + 63, 0, 0x80000000000025ULL }, // Inst #1795 = M2_mmaculs_s0
5346 { 1794, 4, 1, 4, 32, 0, 1, 215, HexagonImpOpBase + 63, 0, 0x80000000000025ULL }, // Inst #1794 = M2_mmaculs_rs1
5347 { 1793, 4, 1, 4, 32, 0, 1, 215, HexagonImpOpBase + 63, 0, 0x80000000000025ULL }, // Inst #1793 = M2_mmaculs_rs0
5348 { 1792, 4, 1, 4, 32, 0, 1, 215, HexagonImpOpBase + 63, 0, 0x80000000000025ULL }, // Inst #1792 = M2_mmacuhs_s1
5349 { 1791, 4, 1, 4, 32, 0, 1, 215, HexagonImpOpBase + 63, 0, 0x80000000000025ULL }, // Inst #1791 = M2_mmacuhs_s0
5350 { 1790, 4, 1, 4, 32, 0, 1, 215, HexagonImpOpBase + 63, 0, 0x80000000000025ULL }, // Inst #1790 = M2_mmacuhs_rs1
5351 { 1789, 4, 1, 4, 32, 0, 1, 215, HexagonImpOpBase + 63, 0, 0x80000000000025ULL }, // Inst #1789 = M2_mmacuhs_rs0
5352 { 1788, 4, 1, 4, 32, 0, 1, 215, HexagonImpOpBase + 63, 0, 0x80000000000025ULL }, // Inst #1788 = M2_mmacls_s1
5353 { 1787, 4, 1, 4, 32, 0, 1, 215, HexagonImpOpBase + 63, 0, 0x80000000000025ULL }, // Inst #1787 = M2_mmacls_s0
5354 { 1786, 4, 1, 4, 32, 0, 1, 215, HexagonImpOpBase + 63, 0, 0x80000000000025ULL }, // Inst #1786 = M2_mmacls_rs1
5355 { 1785, 4, 1, 4, 32, 0, 1, 215, HexagonImpOpBase + 63, 0, 0x80000000000025ULL }, // Inst #1785 = M2_mmacls_rs0
5356 { 1784, 4, 1, 4, 32, 0, 1, 215, HexagonImpOpBase + 63, 0, 0x80000000000025ULL }, // Inst #1784 = M2_mmachs_s1
5357 { 1783, 4, 1, 4, 32, 0, 1, 215, HexagonImpOpBase + 63, 0, 0x80000000000025ULL }, // Inst #1783 = M2_mmachs_s0
5358 { 1782, 4, 1, 4, 32, 0, 1, 215, HexagonImpOpBase + 63, 0, 0x80000000000025ULL }, // Inst #1782 = M2_mmachs_rs1
5359 { 1781, 4, 1, 4, 32, 0, 1, 215, HexagonImpOpBase + 63, 0, 0x80000000000025ULL }, // Inst #1781 = M2_mmachs_rs0
5360 { 1780, 4, 1, 4, 162, 0, 0, 714, HexagonImpOpBase + 0, 0, 0x80000106808025ULL }, // Inst #1780 = M2_macsip
5361 { 1779, 4, 1, 4, 162, 0, 0, 714, HexagonImpOpBase + 0, 0, 0x80000106808025ULL }, // Inst #1779 = M2_macsin
5362 { 1778, 4, 1, 4, 32, 0, 0, 590, HexagonImpOpBase + 0, 0, 0x80000000008025ULL }, // Inst #1778 = M2_maci
5363 { 1777, 3, 1, 4, 31, 0, 1, 202, HexagonImpOpBase + 63, 0, 0x80000000008025ULL }, // Inst #1777 = M2_hmmpyl_s1
5364 { 1776, 3, 1, 4, 31, 0, 1, 202, HexagonImpOpBase + 63, 0, 0x80000000008025ULL }, // Inst #1776 = M2_hmmpyl_rs1
5365 { 1775, 3, 1, 4, 31, 0, 1, 202, HexagonImpOpBase + 63, 0, 0x80000000008025ULL }, // Inst #1775 = M2_hmmpyh_s1
5366 { 1774, 3, 1, 4, 31, 0, 1, 202, HexagonImpOpBase + 63, 0, 0x80000000008025ULL }, // Inst #1774 = M2_hmmpyh_rs1
5367 { 1773, 3, 1, 4, 31, 0, 0, 519, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #1773 = M2_dpmpyuu_s0
5368 { 1772, 4, 1, 4, 32, 0, 0, 718, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #1772 = M2_dpmpyuu_nac_s0
5369 { 1771, 4, 1, 4, 32, 0, 0, 718, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #1771 = M2_dpmpyuu_acc_s0
5370 { 1770, 3, 1, 4, 31, 0, 0, 519, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #1770 = M2_dpmpyss_s0
5371 { 1769, 3, 1, 4, 31, 0, 0, 202, HexagonImpOpBase + 0, 0, 0x80000000008025ULL }, // Inst #1769 = M2_dpmpyss_rnd_s0
5372 { 1768, 4, 1, 4, 32, 0, 0, 718, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #1768 = M2_dpmpyss_nac_s0
5373 { 1767, 4, 1, 4, 32, 0, 0, 718, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #1767 = M2_dpmpyss_acc_s0
5374 { 1766, 4, 1, 4, 32, 0, 1, 718, HexagonImpOpBase + 63, 0, 0x80000000000025ULL }, // Inst #1766 = M2_cnacsc_s1
5375 { 1765, 4, 1, 4, 32, 0, 1, 718, HexagonImpOpBase + 63, 0, 0x80000000000025ULL }, // Inst #1765 = M2_cnacsc_s0
5376 { 1764, 4, 1, 4, 32, 0, 1, 718, HexagonImpOpBase + 63, 0, 0x80000000000025ULL }, // Inst #1764 = M2_cnacs_s1
5377 { 1763, 4, 1, 4, 32, 0, 1, 718, HexagonImpOpBase + 63, 0, 0x80000000000025ULL }, // Inst #1763 = M2_cnacs_s0
5378 { 1762, 3, 1, 4, 31, 0, 1, 519, HexagonImpOpBase + 63, 0, 0x80000000000025ULL }, // Inst #1762 = M2_cmpysc_s1
5379 { 1761, 3, 1, 4, 31, 0, 1, 519, HexagonImpOpBase + 63, 0, 0x80000000000025ULL }, // Inst #1761 = M2_cmpysc_s0
5380 { 1760, 3, 1, 4, 31, 0, 1, 519, HexagonImpOpBase + 63, 0, 0x80000000000025ULL }, // Inst #1760 = M2_cmpys_s1
5381 { 1759, 3, 1, 4, 31, 0, 1, 519, HexagonImpOpBase + 63, 0, 0x80000000000025ULL }, // Inst #1759 = M2_cmpys_s0
5382 { 1758, 3, 1, 4, 31, 0, 1, 202, HexagonImpOpBase + 63, 0, 0x80000000008025ULL }, // Inst #1758 = M2_cmpyrsc_s1
5383 { 1757, 3, 1, 4, 31, 0, 1, 202, HexagonImpOpBase + 63, 0, 0x80000000008025ULL }, // Inst #1757 = M2_cmpyrsc_s0
5384 { 1756, 3, 1, 4, 31, 0, 1, 202, HexagonImpOpBase + 63, 0, 0x80000000008025ULL }, // Inst #1756 = M2_cmpyrs_s1
5385 { 1755, 3, 1, 4, 31, 0, 1, 202, HexagonImpOpBase + 63, 0, 0x80000000008025ULL }, // Inst #1755 = M2_cmpyrs_s0
5386 { 1754, 3, 1, 4, 31, 0, 0, 519, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #1754 = M2_cmpyr_s0
5387 { 1753, 3, 1, 4, 31, 0, 0, 519, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #1753 = M2_cmpyi_s0
5388 { 1752, 4, 1, 4, 32, 0, 1, 718, HexagonImpOpBase + 63, 0, 0x80000000000025ULL }, // Inst #1752 = M2_cmacsc_s1
5389 { 1751, 4, 1, 4, 32, 0, 1, 718, HexagonImpOpBase + 63, 0, 0x80000000000025ULL }, // Inst #1751 = M2_cmacsc_s0
5390 { 1750, 4, 1, 4, 32, 0, 1, 718, HexagonImpOpBase + 63, 0, 0x80000000000025ULL }, // Inst #1750 = M2_cmacs_s1
5391 { 1749, 4, 1, 4, 32, 0, 1, 718, HexagonImpOpBase + 63, 0, 0x80000000000025ULL }, // Inst #1749 = M2_cmacs_s0
5392 { 1748, 4, 1, 4, 32, 0, 0, 718, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #1748 = M2_cmacr_s0
5393 { 1747, 4, 1, 4, 32, 0, 0, 718, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #1747 = M2_cmaci_s0
5394 { 1746, 4, 1, 4, 161, 0, 0, 714, HexagonImpOpBase + 0, 0, 0x80000116808025ULL }, // Inst #1746 = M2_accii
5395 { 1745, 4, 1, 4, 161, 0, 0, 590, HexagonImpOpBase + 0, 0, 0x80000000008025ULL }, // Inst #1745 = M2_acci
5396 { 1744, 2, 1, 4, 6, 0, 0, 155, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable), 0x8000ULL }, // Inst #1744 = LO
5397 { 1743, 3, 0, 4, 160, 0, 0, 711, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0xa4ULL }, // Inst #1743 = L6_memcpy
5398 { 1742, 3, 0, 4, 21, 0, 0, 510, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1b8902800030ULL }, // Inst #1742 = L4_sub_memopw_io
5399 { 1741, 3, 0, 4, 21, 0, 0, 510, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1384e2800030ULL }, // Inst #1741 = L4_sub_memoph_io
5400 { 1740, 3, 0, 4, 21, 0, 0, 510, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0xb80c2800030ULL }, // Inst #1740 = L4_sub_memopb_io
5401 { 1739, 3, 1, 4, 24, 1, 2, 192, HexagonImpOpBase + 102, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xa09000001424ULL }, // Inst #1739 = L4_return_tnew_pt
5402 { 1738, 3, 1, 4, 24, 1, 2, 192, HexagonImpOpBase + 102, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0x209000001424ULL }, // Inst #1738 = L4_return_tnew_pnt
5403 { 1737, 3, 1, 4, 23, 1, 2, 192, HexagonImpOpBase + 102, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xa09000000424ULL }, // Inst #1737 = L4_return_t
5404 { 1736, 3, 1, 4, 24, 1, 2, 192, HexagonImpOpBase + 102, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xa09000001c24ULL }, // Inst #1736 = L4_return_fnew_pt
5405 { 1735, 3, 1, 4, 24, 1, 2, 192, HexagonImpOpBase + 102, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0x209000001c24ULL }, // Inst #1735 = L4_return_fnew_pnt
5406 { 1734, 3, 1, 4, 23, 1, 2, 192, HexagonImpOpBase + 102, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xa09000000c24ULL }, // Inst #1734 = L4_return_f
5407 { 1733, 2, 1, 4, 28, 1, 2, 190, HexagonImpOpBase + 102, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0xa09000000024ULL }, // Inst #1733 = L4_return
5408 { 1732, 5, 1, 4, 159, 0, 0, 698, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x150000009424ULL }, // Inst #1732 = L4_ploadruhtnew_rr
5409 { 1731, 3, 1, 4, 153, 0, 0, 504, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x1100c5809424ULL }, // Inst #1731 = L4_ploadruhtnew_abs
5410 { 1730, 5, 1, 4, 158, 0, 0, 698, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x150000008424ULL }, // Inst #1730 = L4_ploadruht_rr
5411 { 1729, 3, 1, 4, 157, 0, 0, 504, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x1100c5808424ULL }, // Inst #1729 = L4_ploadruht_abs
5412 { 1728, 5, 1, 4, 159, 0, 0, 698, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x150000009c24ULL }, // Inst #1728 = L4_ploadruhfnew_rr
5413 { 1727, 3, 1, 4, 153, 0, 0, 504, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x1100c5809c24ULL }, // Inst #1727 = L4_ploadruhfnew_abs
5414 { 1726, 5, 1, 4, 158, 0, 0, 698, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x150000008c24ULL }, // Inst #1726 = L4_ploadruhf_rr
5415 { 1725, 3, 1, 4, 157, 0, 0, 504, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x1100c5808c24ULL }, // Inst #1725 = L4_ploadruhf_abs
5416 { 1724, 5, 1, 4, 159, 0, 0, 698, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0xd0000009424ULL }, // Inst #1724 = L4_ploadrubtnew_rr
5417 { 1723, 3, 1, 4, 153, 0, 0, 504, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x900c5809424ULL }, // Inst #1723 = L4_ploadrubtnew_abs
5418 { 1722, 5, 1, 4, 158, 0, 0, 698, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0xd0000008424ULL }, // Inst #1722 = L4_ploadrubt_rr
5419 { 1721, 3, 1, 4, 157, 0, 0, 504, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x900c5808424ULL }, // Inst #1721 = L4_ploadrubt_abs
5420 { 1720, 5, 1, 4, 159, 0, 0, 698, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0xd0000009c24ULL }, // Inst #1720 = L4_ploadrubfnew_rr
5421 { 1719, 3, 1, 4, 153, 0, 0, 504, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x900c5809c24ULL }, // Inst #1719 = L4_ploadrubfnew_abs
5422 { 1718, 5, 1, 4, 158, 0, 0, 698, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0xd0000008c24ULL }, // Inst #1718 = L4_ploadrubf_rr
5423 { 1717, 3, 1, 4, 157, 0, 0, 504, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x900c5808c24ULL }, // Inst #1717 = L4_ploadrubf_abs
5424 { 1716, 5, 1, 4, 159, 0, 0, 698, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x1d0000009424ULL }, // Inst #1716 = L4_ploadritnew_rr
5425 { 1715, 3, 1, 4, 153, 0, 0, 504, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x1900c5809424ULL }, // Inst #1715 = L4_ploadritnew_abs
5426 { 1714, 5, 1, 4, 158, 0, 0, 698, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x1d0000008424ULL }, // Inst #1714 = L4_ploadrit_rr
5427 { 1713, 3, 1, 4, 157, 0, 0, 504, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x1900c5808424ULL }, // Inst #1713 = L4_ploadrit_abs
5428 { 1712, 5, 1, 4, 159, 0, 0, 698, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x1d0000009c24ULL }, // Inst #1712 = L4_ploadrifnew_rr
5429 { 1711, 3, 1, 4, 153, 0, 0, 504, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x1900c5809c24ULL }, // Inst #1711 = L4_ploadrifnew_abs
5430 { 1710, 5, 1, 4, 158, 0, 0, 698, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x1d0000008c24ULL }, // Inst #1710 = L4_ploadrif_rr
5431 { 1709, 3, 1, 4, 157, 0, 0, 504, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x1900c5808c24ULL }, // Inst #1709 = L4_ploadrif_abs
5432 { 1708, 5, 1, 4, 159, 0, 0, 698, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x150000009424ULL }, // Inst #1708 = L4_ploadrhtnew_rr
5433 { 1707, 3, 1, 4, 153, 0, 0, 504, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x1100c5809424ULL }, // Inst #1707 = L4_ploadrhtnew_abs
5434 { 1706, 5, 1, 4, 158, 0, 0, 698, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x150000008424ULL }, // Inst #1706 = L4_ploadrht_rr
5435 { 1705, 3, 1, 4, 157, 0, 0, 504, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x1100c5808424ULL }, // Inst #1705 = L4_ploadrht_abs
5436 { 1704, 5, 1, 4, 159, 0, 0, 698, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x150000009c24ULL }, // Inst #1704 = L4_ploadrhfnew_rr
5437 { 1703, 3, 1, 4, 153, 0, 0, 504, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x1100c5809c24ULL }, // Inst #1703 = L4_ploadrhfnew_abs
5438 { 1702, 5, 1, 4, 158, 0, 0, 698, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x150000008c24ULL }, // Inst #1702 = L4_ploadrhf_rr
5439 { 1701, 3, 1, 4, 157, 0, 0, 504, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x1100c5808c24ULL }, // Inst #1701 = L4_ploadrhf_abs
5440 { 1700, 5, 1, 4, 159, 0, 0, 706, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x250000001424ULL }, // Inst #1700 = L4_ploadrdtnew_rr
5441 { 1699, 3, 1, 4, 153, 0, 0, 703, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x2100c5801424ULL }, // Inst #1699 = L4_ploadrdtnew_abs
5442 { 1698, 5, 1, 4, 158, 0, 0, 706, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x250000000424ULL }, // Inst #1698 = L4_ploadrdt_rr
5443 { 1697, 3, 1, 4, 157, 0, 0, 703, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x2100c5800424ULL }, // Inst #1697 = L4_ploadrdt_abs
5444 { 1696, 5, 1, 4, 159, 0, 0, 706, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x250000001c24ULL }, // Inst #1696 = L4_ploadrdfnew_rr
5445 { 1695, 3, 1, 4, 153, 0, 0, 703, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x2100c5801c24ULL }, // Inst #1695 = L4_ploadrdfnew_abs
5446 { 1694, 5, 1, 4, 158, 0, 0, 706, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x250000000c24ULL }, // Inst #1694 = L4_ploadrdf_rr
5447 { 1693, 3, 1, 4, 157, 0, 0, 703, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x2100c5800c24ULL }, // Inst #1693 = L4_ploadrdf_abs
5448 { 1692, 5, 1, 4, 159, 0, 0, 698, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0xd0000009424ULL }, // Inst #1692 = L4_ploadrbtnew_rr
5449 { 1691, 3, 1, 4, 153, 0, 0, 504, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x900c5809424ULL }, // Inst #1691 = L4_ploadrbtnew_abs
5450 { 1690, 5, 1, 4, 158, 0, 0, 698, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0xd0000008424ULL }, // Inst #1690 = L4_ploadrbt_rr
5451 { 1689, 3, 1, 4, 157, 0, 0, 504, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x900c5808424ULL }, // Inst #1689 = L4_ploadrbt_abs
5452 { 1688, 5, 1, 4, 159, 0, 0, 698, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0xd0000009c24ULL }, // Inst #1688 = L4_ploadrbfnew_rr
5453 { 1687, 3, 1, 4, 153, 0, 0, 504, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x900c5809c24ULL }, // Inst #1687 = L4_ploadrbfnew_abs
5454 { 1686, 5, 1, 4, 158, 0, 0, 698, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0xd0000008c24ULL }, // Inst #1686 = L4_ploadrbf_rr
5455 { 1685, 3, 1, 4, 157, 0, 0, 504, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x900c5808c24ULL }, // Inst #1685 = L4_ploadrbf_abs
5456 { 1684, 3, 0, 4, 21, 0, 0, 510, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1b8902800030ULL }, // Inst #1684 = L4_or_memopw_io
5457 { 1683, 3, 0, 4, 21, 0, 0, 510, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1384e2800030ULL }, // Inst #1683 = L4_or_memoph_io
5458 { 1682, 3, 0, 4, 21, 0, 0, 510, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0xb80c2800030ULL }, // Inst #1682 = L4_or_memopb_io
5459 { 1681, 3, 1, 4, 156, 0, 0, 202, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x1800000080a4ULL }, // Inst #1681 = L4_loadw_phys
5460 { 1680, 4, 1, 4, 154, 0, 0, 686, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x1400c7808024ULL }, // Inst #1680 = L4_loadruh_ur
5461 { 1679, 4, 1, 4, 155, 0, 0, 219, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x150000008024ULL }, // Inst #1679 = L4_loadruh_rr
5462 { 1678, 3, 2, 4, 153, 0, 0, 199, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x1200c5808024ULL }, // Inst #1678 = L4_loadruh_ap
5463 { 1677, 4, 1, 4, 154, 0, 0, 686, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0xc00c7808024ULL }, // Inst #1677 = L4_loadrub_ur
5464 { 1676, 4, 1, 4, 155, 0, 0, 219, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xd0000008024ULL }, // Inst #1676 = L4_loadrub_rr
5465 { 1675, 3, 2, 4, 153, 0, 0, 199, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0xa00c5808024ULL }, // Inst #1675 = L4_loadrub_ap
5466 { 1674, 4, 1, 4, 154, 0, 0, 686, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x1c00c7808024ULL }, // Inst #1674 = L4_loadri_ur
5467 { 1673, 4, 1, 4, 155, 0, 0, 219, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x1d0000008024ULL }, // Inst #1673 = L4_loadri_rr
5468 { 1672, 3, 2, 4, 153, 0, 0, 199, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x1a00c5808024ULL }, // Inst #1672 = L4_loadri_ap
5469 { 1671, 4, 1, 4, 154, 0, 0, 686, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x1400c7808024ULL }, // Inst #1671 = L4_loadrh_ur
5470 { 1670, 4, 1, 4, 155, 0, 0, 219, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x150000008024ULL }, // Inst #1670 = L4_loadrh_rr
5471 { 1669, 3, 2, 4, 153, 0, 0, 199, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x1200c5808024ULL }, // Inst #1669 = L4_loadrh_ap
5472 { 1668, 4, 1, 4, 154, 0, 0, 690, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x2400c7800024ULL }, // Inst #1668 = L4_loadrd_ur
5473 { 1667, 4, 1, 4, 155, 0, 0, 694, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x250000000024ULL }, // Inst #1667 = L4_loadrd_rr
5474 { 1666, 3, 2, 4, 153, 0, 0, 501, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x2200c5800024ULL }, // Inst #1666 = L4_loadrd_ap
5475 { 1665, 4, 1, 4, 154, 0, 0, 686, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0xc00c7808024ULL }, // Inst #1665 = L4_loadrb_ur
5476 { 1664, 4, 1, 4, 155, 0, 0, 219, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xd0000008024ULL }, // Inst #1664 = L4_loadrb_rr
5477 { 1663, 3, 2, 4, 153, 0, 0, 199, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0xa00c5808024ULL }, // Inst #1663 = L4_loadrb_ap
5478 { 1662, 2, 1, 4, 149, 0, 0, 190, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x200000000124ULL }, // Inst #1662 = L4_loadd_locked
5479 { 1661, 2, 1, 4, 148, 0, 0, 190, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x200000000024ULL }, // Inst #1661 = L4_loadd_aq
5480 { 1660, 4, 1, 4, 154, 0, 0, 690, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x1c00c7800024ULL }, // Inst #1660 = L4_loadbzw4_ur
5481 { 1659, 3, 2, 4, 153, 0, 0, 501, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x1a00c5800024ULL }, // Inst #1659 = L4_loadbzw4_ap
5482 { 1658, 4, 1, 4, 154, 0, 0, 686, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x1400c7808024ULL }, // Inst #1658 = L4_loadbzw2_ur
5483 { 1657, 3, 2, 4, 153, 0, 0, 199, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x1200c5808024ULL }, // Inst #1657 = L4_loadbzw2_ap
5484 { 1656, 4, 1, 4, 154, 0, 0, 690, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x1c00c7800024ULL }, // Inst #1656 = L4_loadbsw4_ur
5485 { 1655, 3, 2, 4, 153, 0, 0, 501, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x1a00c5800024ULL }, // Inst #1655 = L4_loadbsw4_ap
5486 { 1654, 4, 1, 4, 154, 0, 0, 686, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x1400c7808024ULL }, // Inst #1654 = L4_loadbsw2_ur
5487 { 1653, 3, 2, 4, 153, 0, 0, 199, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x1200c5808024ULL }, // Inst #1653 = L4_loadbsw2_ap
5488 { 1652, 5, 1, 4, 152, 0, 0, 681, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x1400c9800024ULL }, // Inst #1652 = L4_loadalignh_ur
5489 { 1651, 4, 2, 4, 151, 0, 0, 677, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x1200c7800024ULL }, // Inst #1651 = L4_loadalignh_ap
5490 { 1650, 5, 1, 4, 152, 0, 0, 681, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0xc00c9800024ULL }, // Inst #1650 = L4_loadalignb_ur
5491 { 1649, 4, 2, 4, 151, 0, 0, 677, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0xa00c7800024ULL }, // Inst #1649 = L4_loadalignb_ap
5492 { 1648, 3, 0, 4, 22, 0, 0, 516, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1b8902800030ULL }, // Inst #1648 = L4_isub_memopw_io
5493 { 1647, 3, 0, 4, 22, 0, 0, 516, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1384e2800030ULL }, // Inst #1647 = L4_isub_memoph_io
5494 { 1646, 3, 0, 4, 22, 0, 0, 516, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0xb80c2800030ULL }, // Inst #1646 = L4_isub_memopb_io
5495 { 1645, 3, 0, 4, 22, 0, 0, 516, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1b8902800030ULL }, // Inst #1645 = L4_ior_memopw_io
5496 { 1644, 3, 0, 4, 22, 0, 0, 516, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1384e2800030ULL }, // Inst #1644 = L4_ior_memoph_io
5497 { 1643, 3, 0, 4, 22, 0, 0, 516, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0xb80c2800030ULL }, // Inst #1643 = L4_ior_memopb_io
5498 { 1642, 3, 0, 4, 22, 0, 0, 516, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1b8902800030ULL }, // Inst #1642 = L4_iand_memopw_io
5499 { 1641, 3, 0, 4, 22, 0, 0, 516, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1384e2800030ULL }, // Inst #1641 = L4_iand_memoph_io
5500 { 1640, 3, 0, 4, 22, 0, 0, 516, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0xb80c2800030ULL }, // Inst #1640 = L4_iand_memopb_io
5501 { 1639, 3, 0, 4, 22, 0, 0, 516, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1b8902800030ULL }, // Inst #1639 = L4_iadd_memopw_io
5502 { 1638, 3, 0, 4, 22, 0, 0, 516, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1384e2800030ULL }, // Inst #1638 = L4_iadd_memoph_io
5503 { 1637, 3, 0, 4, 22, 0, 0, 516, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0xb80c2800030ULL }, // Inst #1637 = L4_iadd_memopb_io
5504 { 1636, 3, 0, 4, 21, 0, 0, 510, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1b8902800030ULL }, // Inst #1636 = L4_and_memopw_io
5505 { 1635, 3, 0, 4, 21, 0, 0, 510, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1384e2800030ULL }, // Inst #1635 = L4_and_memoph_io
5506 { 1634, 3, 0, 4, 21, 0, 0, 510, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0xb80c2800030ULL }, // Inst #1634 = L4_and_memopb_io
5507 { 1633, 3, 0, 4, 21, 0, 0, 510, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1b8902800030ULL }, // Inst #1633 = L4_add_memopw_io
5508 { 1632, 3, 0, 4, 21, 0, 0, 510, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1384e2800030ULL }, // Inst #1632 = L4_add_memoph_io
5509 { 1631, 3, 0, 4, 21, 0, 0, 510, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0xb80c2800030ULL }, // Inst #1631 = L4_add_memopb_io
5510 { 1630, 5, 2, 4, 150, 0, 0, 663, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x160000009424ULL }, // Inst #1630 = L2_ploadruhtnew_pi
5511 { 1629, 4, 1, 4, 20, 0, 0, 526, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x1304e680942fULL }, // Inst #1629 = L2_ploadruhtnew_io
5512 { 1628, 5, 2, 4, 145, 0, 0, 663, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x160000008424ULL }, // Inst #1628 = L2_ploadruht_pi
5513 { 1627, 4, 1, 4, 18, 0, 0, 526, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x1304e680842fULL }, // Inst #1627 = L2_ploadruht_io
5514 { 1626, 5, 2, 4, 150, 0, 0, 663, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x160000009c24ULL }, // Inst #1626 = L2_ploadruhfnew_pi
5515 { 1625, 4, 1, 4, 20, 0, 0, 526, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x1304e6809c2fULL }, // Inst #1625 = L2_ploadruhfnew_io
5516 { 1624, 5, 2, 4, 145, 0, 0, 663, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x160000008c24ULL }, // Inst #1624 = L2_ploadruhf_pi
5517 { 1623, 4, 1, 4, 18, 0, 0, 526, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x1304e6808c2fULL }, // Inst #1623 = L2_ploadruhf_io
5518 { 1622, 5, 2, 4, 150, 0, 0, 663, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0xe0000009424ULL }, // Inst #1622 = L2_ploadrubtnew_pi
5519 { 1621, 4, 1, 4, 20, 0, 0, 526, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0xb00c680942fULL }, // Inst #1621 = L2_ploadrubtnew_io
5520 { 1620, 5, 2, 4, 145, 0, 0, 663, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0xe0000008424ULL }, // Inst #1620 = L2_ploadrubt_pi
5521 { 1619, 4, 1, 4, 18, 0, 0, 526, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0xb00c680842fULL }, // Inst #1619 = L2_ploadrubt_io
5522 { 1618, 5, 2, 4, 150, 0, 0, 663, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0xe0000009c24ULL }, // Inst #1618 = L2_ploadrubfnew_pi
5523 { 1617, 4, 1, 4, 20, 0, 0, 526, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0xb00c6809c2fULL }, // Inst #1617 = L2_ploadrubfnew_io
5524 { 1616, 5, 2, 4, 145, 0, 0, 663, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0xe0000008c24ULL }, // Inst #1616 = L2_ploadrubf_pi
5525 { 1615, 4, 1, 4, 18, 0, 0, 526, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0xb00c6808c2fULL }, // Inst #1615 = L2_ploadrubf_io
5526 { 1614, 5, 2, 4, 150, 0, 0, 663, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x1e0000009424ULL }, // Inst #1614 = L2_ploadritnew_pi
5527 { 1613, 4, 1, 4, 20, 0, 0, 526, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x1b090680942fULL }, // Inst #1613 = L2_ploadritnew_io
5528 { 1612, 5, 2, 4, 145, 0, 0, 663, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x1e0000008424ULL }, // Inst #1612 = L2_ploadrit_pi
5529 { 1611, 4, 1, 4, 18, 0, 0, 526, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x1b090680842fULL }, // Inst #1611 = L2_ploadrit_io
5530 { 1610, 5, 2, 4, 150, 0, 0, 663, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x1e0000009c24ULL }, // Inst #1610 = L2_ploadrifnew_pi
5531 { 1609, 4, 1, 4, 20, 0, 0, 526, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x1b0906809c2fULL }, // Inst #1609 = L2_ploadrifnew_io
5532 { 1608, 5, 2, 4, 145, 0, 0, 663, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x1e0000008c24ULL }, // Inst #1608 = L2_ploadrif_pi
5533 { 1607, 4, 1, 4, 18, 0, 0, 526, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x1b0906808c2fULL }, // Inst #1607 = L2_ploadrif_io
5534 { 1606, 5, 2, 4, 150, 0, 0, 663, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x160000009424ULL }, // Inst #1606 = L2_ploadrhtnew_pi
5535 { 1605, 4, 1, 4, 20, 0, 0, 526, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x1304e680942fULL }, // Inst #1605 = L2_ploadrhtnew_io
5536 { 1604, 5, 2, 4, 145, 0, 0, 663, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x160000008424ULL }, // Inst #1604 = L2_ploadrht_pi
5537 { 1603, 4, 1, 4, 18, 0, 0, 526, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x1304e680842fULL }, // Inst #1603 = L2_ploadrht_io
5538 { 1602, 5, 2, 4, 150, 0, 0, 663, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x160000009c24ULL }, // Inst #1602 = L2_ploadrhfnew_pi
5539 { 1601, 4, 1, 4, 20, 0, 0, 526, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x1304e6809c2fULL }, // Inst #1601 = L2_ploadrhfnew_io
5540 { 1600, 5, 2, 4, 145, 0, 0, 663, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x160000008c24ULL }, // Inst #1600 = L2_ploadrhf_pi
5541 { 1599, 4, 1, 4, 18, 0, 0, 526, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x1304e6808c2fULL }, // Inst #1599 = L2_ploadrhf_io
5542 { 1598, 5, 2, 4, 150, 0, 0, 672, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x260000001424ULL }, // Inst #1598 = L2_ploadrdtnew_pi
5543 { 1597, 4, 1, 4, 20, 0, 0, 668, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x230d2680142fULL }, // Inst #1597 = L2_ploadrdtnew_io
5544 { 1596, 5, 2, 4, 145, 0, 0, 672, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x260000000424ULL }, // Inst #1596 = L2_ploadrdt_pi
5545 { 1595, 4, 1, 4, 18, 0, 0, 668, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x230d2680042fULL }, // Inst #1595 = L2_ploadrdt_io
5546 { 1594, 5, 2, 4, 150, 0, 0, 672, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x260000001c24ULL }, // Inst #1594 = L2_ploadrdfnew_pi
5547 { 1593, 4, 1, 4, 20, 0, 0, 668, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x230d26801c2fULL }, // Inst #1593 = L2_ploadrdfnew_io
5548 { 1592, 5, 2, 4, 145, 0, 0, 672, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x260000000c24ULL }, // Inst #1592 = L2_ploadrdf_pi
5549 { 1591, 4, 1, 4, 18, 0, 0, 668, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x230d26800c2fULL }, // Inst #1591 = L2_ploadrdf_io
5550 { 1590, 5, 2, 4, 150, 0, 0, 663, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0xe0000009424ULL }, // Inst #1590 = L2_ploadrbtnew_pi
5551 { 1589, 4, 1, 4, 20, 0, 0, 526, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0xb00c680942fULL }, // Inst #1589 = L2_ploadrbtnew_io
5552 { 1588, 5, 2, 4, 145, 0, 0, 663, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0xe0000008424ULL }, // Inst #1588 = L2_ploadrbt_pi
5553 { 1587, 4, 1, 4, 18, 0, 0, 526, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0xb00c680842fULL }, // Inst #1587 = L2_ploadrbt_io
5554 { 1586, 5, 2, 4, 150, 0, 0, 663, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0xe0000009c24ULL }, // Inst #1586 = L2_ploadrbfnew_pi
5555 { 1585, 4, 1, 4, 20, 0, 0, 526, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0xb00c6809c2fULL }, // Inst #1585 = L2_ploadrbfnew_io
5556 { 1584, 5, 2, 4, 145, 0, 0, 663, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0xe0000008c24ULL }, // Inst #1584 = L2_ploadrbf_pi
5557 { 1583, 4, 1, 4, 18, 0, 0, 526, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0xb00c6808c2fULL }, // Inst #1583 = L2_ploadrbf_io
5558 { 1582, 2, 1, 4, 149, 0, 0, 157, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x180000008124ULL }, // Inst #1582 = L2_loadw_locked
5559 { 1581, 2, 1, 4, 148, 0, 0, 157, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x180000008024ULL }, // Inst #1581 = L2_loadw_aq
5560 { 1580, 2, 1, 4, 147, 1, 0, 155, HexagonImpOpBase + 101, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x10062200802fULL }, // Inst #1580 = L2_loadruhgp
5561 { 1579, 4, 2, 4, 20, 0, 0, 637, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x160000008024ULL }, // Inst #1579 = L2_loadruh_pr
5562 { 1578, 4, 2, 4, 20, 0, 0, 646, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x160000008024ULL }, // Inst #1578 = L2_loadruh_pi
5563 { 1577, 4, 2, 4, 20, 1, 0, 637, HexagonImpOpBase + 100, 0|(1ULL<<MCID::MayLoad), 0x160000008024ULL }, // Inst #1577 = L2_loadruh_pcr
5564 { 1576, 5, 2, 4, 36, 1, 0, 641, HexagonImpOpBase + 100, 0|(1ULL<<MCID::MayLoad), 0x160000008024ULL }, // Inst #1576 = L2_loadruh_pci
5565 { 1575, 4, 2, 4, 20, 0, 0, 637, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x160000008024ULL }, // Inst #1575 = L2_loadruh_pbr
5566 { 1574, 3, 1, 4, 19, 0, 0, 199, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x130594808024ULL }, // Inst #1574 = L2_loadruh_io
5567 { 1573, 2, 1, 4, 147, 1, 0, 155, HexagonImpOpBase + 101, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x8020200802fULL }, // Inst #1573 = L2_loadrubgp
5568 { 1572, 4, 2, 4, 20, 0, 0, 637, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0xe0000008024ULL }, // Inst #1572 = L2_loadrub_pr
5569 { 1571, 4, 2, 4, 20, 0, 0, 646, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xe0000008024ULL }, // Inst #1571 = L2_loadrub_pi
5570 { 1570, 4, 2, 4, 20, 1, 0, 637, HexagonImpOpBase + 100, 0|(1ULL<<MCID::MayLoad), 0xe0000008024ULL }, // Inst #1570 = L2_loadrub_pcr
5571 { 1569, 5, 2, 4, 36, 1, 0, 641, HexagonImpOpBase + 100, 0|(1ULL<<MCID::MayLoad), 0xe0000008024ULL }, // Inst #1569 = L2_loadrub_pci
5572 { 1568, 4, 2, 4, 20, 0, 0, 637, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0xe0000008024ULL }, // Inst #1568 = L2_loadrub_pbr
5573 { 1567, 3, 1, 4, 19, 0, 0, 199, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xb0174808024ULL }, // Inst #1567 = L2_loadrub_io
5574 { 1566, 2, 1, 4, 147, 1, 0, 155, HexagonImpOpBase + 101, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x180a4200802fULL }, // Inst #1566 = L2_loadrigp
5575 { 1565, 4, 2, 4, 20, 0, 0, 637, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x1e0000008024ULL }, // Inst #1565 = L2_loadri_pr
5576 { 1564, 4, 2, 4, 20, 0, 0, 646, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x1e0000008024ULL }, // Inst #1564 = L2_loadri_pi
5577 { 1563, 4, 2, 4, 20, 1, 0, 637, HexagonImpOpBase + 100, 0|(1ULL<<MCID::MayLoad), 0x1e0000008024ULL }, // Inst #1563 = L2_loadri_pcr
5578 { 1562, 5, 2, 4, 36, 1, 0, 641, HexagonImpOpBase + 100, 0|(1ULL<<MCID::MayLoad), 0x1e0000008024ULL }, // Inst #1562 = L2_loadri_pci
5579 { 1561, 4, 2, 4, 20, 0, 0, 637, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x1e0000008024ULL }, // Inst #1561 = L2_loadri_pbr
5580 { 1560, 3, 1, 4, 19, 0, 0, 199, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x1b09b4808024ULL }, // Inst #1560 = L2_loadri_io
5581 { 1559, 2, 1, 4, 147, 1, 0, 155, HexagonImpOpBase + 101, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x10062200802fULL }, // Inst #1559 = L2_loadrhgp
5582 { 1558, 4, 2, 4, 20, 0, 0, 637, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x160000008024ULL }, // Inst #1558 = L2_loadrh_pr
5583 { 1557, 4, 2, 4, 20, 0, 0, 646, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x160000008024ULL }, // Inst #1557 = L2_loadrh_pi
5584 { 1556, 4, 2, 4, 20, 1, 0, 637, HexagonImpOpBase + 100, 0|(1ULL<<MCID::MayLoad), 0x160000008024ULL }, // Inst #1556 = L2_loadrh_pcr
5585 { 1555, 5, 2, 4, 36, 1, 0, 641, HexagonImpOpBase + 100, 0|(1ULL<<MCID::MayLoad), 0x160000008024ULL }, // Inst #1555 = L2_loadrh_pci
5586 { 1554, 4, 2, 4, 20, 0, 0, 637, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x160000008024ULL }, // Inst #1554 = L2_loadrh_pbr
5587 { 1553, 3, 1, 4, 19, 0, 0, 199, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x130594808024ULL }, // Inst #1553 = L2_loadrh_io
5588 { 1552, 2, 1, 4, 147, 1, 0, 167, HexagonImpOpBase + 101, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x200e6200002fULL }, // Inst #1552 = L2_loadrdgp
5589 { 1551, 4, 2, 4, 20, 0, 0, 650, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x260000000024ULL }, // Inst #1551 = L2_loadrd_pr
5590 { 1550, 4, 2, 4, 20, 0, 0, 659, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x260000000024ULL }, // Inst #1550 = L2_loadrd_pi
5591 { 1549, 4, 2, 4, 20, 1, 0, 650, HexagonImpOpBase + 100, 0|(1ULL<<MCID::MayLoad), 0x260000000024ULL }, // Inst #1549 = L2_loadrd_pcr
5592 { 1548, 5, 2, 4, 36, 1, 0, 654, HexagonImpOpBase + 100, 0|(1ULL<<MCID::MayLoad), 0x260000000024ULL }, // Inst #1548 = L2_loadrd_pci
5593 { 1547, 4, 2, 4, 20, 0, 0, 650, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x260000000024ULL }, // Inst #1547 = L2_loadrd_pbr
5594 { 1546, 3, 1, 4, 19, 0, 0, 501, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x230dd4800024ULL }, // Inst #1546 = L2_loadrd_io
5595 { 1545, 2, 1, 4, 147, 1, 0, 155, HexagonImpOpBase + 101, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x8020200802fULL }, // Inst #1545 = L2_loadrbgp
5596 { 1544, 4, 2, 4, 20, 0, 0, 637, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0xe0000008024ULL }, // Inst #1544 = L2_loadrb_pr
5597 { 1543, 4, 2, 4, 20, 0, 0, 646, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xe0000008024ULL }, // Inst #1543 = L2_loadrb_pi
5598 { 1542, 4, 2, 4, 20, 1, 0, 637, HexagonImpOpBase + 100, 0|(1ULL<<MCID::MayLoad), 0xe0000008024ULL }, // Inst #1542 = L2_loadrb_pcr
5599 { 1541, 5, 2, 4, 36, 1, 0, 641, HexagonImpOpBase + 100, 0|(1ULL<<MCID::MayLoad), 0xe0000008024ULL }, // Inst #1541 = L2_loadrb_pci
5600 { 1540, 4, 2, 4, 20, 0, 0, 637, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0xe0000008024ULL }, // Inst #1540 = L2_loadrb_pbr
5601 { 1539, 3, 1, 4, 19, 0, 0, 199, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xb0174808024ULL }, // Inst #1539 = L2_loadrb_io
5602 { 1538, 4, 2, 4, 20, 0, 0, 650, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x1e0000000024ULL }, // Inst #1538 = L2_loadbzw4_pr
5603 { 1537, 4, 2, 4, 20, 0, 0, 659, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x1e0000000024ULL }, // Inst #1537 = L2_loadbzw4_pi
5604 { 1536, 4, 2, 4, 20, 1, 0, 650, HexagonImpOpBase + 100, 0|(1ULL<<MCID::MayLoad), 0x1e0000000024ULL }, // Inst #1536 = L2_loadbzw4_pcr
5605 { 1535, 5, 2, 4, 36, 1, 0, 654, HexagonImpOpBase + 100, 0|(1ULL<<MCID::MayLoad), 0x1e0000000024ULL }, // Inst #1535 = L2_loadbzw4_pci
5606 { 1534, 4, 2, 4, 20, 0, 0, 650, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x1e0000000024ULL }, // Inst #1534 = L2_loadbzw4_pbr
5607 { 1533, 3, 1, 4, 19, 0, 0, 501, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x1b09b4800024ULL }, // Inst #1533 = L2_loadbzw4_io
5608 { 1532, 4, 2, 4, 20, 0, 0, 637, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x160000008024ULL }, // Inst #1532 = L2_loadbzw2_pr
5609 { 1531, 4, 2, 4, 20, 0, 0, 646, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x160000008024ULL }, // Inst #1531 = L2_loadbzw2_pi
5610 { 1530, 4, 2, 4, 20, 1, 0, 637, HexagonImpOpBase + 100, 0|(1ULL<<MCID::MayLoad), 0x160000008024ULL }, // Inst #1530 = L2_loadbzw2_pcr
5611 { 1529, 5, 2, 4, 36, 1, 0, 641, HexagonImpOpBase + 100, 0|(1ULL<<MCID::MayLoad), 0x160000008024ULL }, // Inst #1529 = L2_loadbzw2_pci
5612 { 1528, 4, 2, 4, 20, 0, 0, 637, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x160000008024ULL }, // Inst #1528 = L2_loadbzw2_pbr
5613 { 1527, 3, 1, 4, 19, 0, 0, 199, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x130594808024ULL }, // Inst #1527 = L2_loadbzw2_io
5614 { 1526, 4, 2, 4, 20, 0, 0, 650, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x1e0000000024ULL }, // Inst #1526 = L2_loadbsw4_pr
5615 { 1525, 4, 2, 4, 20, 0, 0, 659, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x1e0000000024ULL }, // Inst #1525 = L2_loadbsw4_pi
5616 { 1524, 4, 2, 4, 20, 1, 0, 650, HexagonImpOpBase + 100, 0|(1ULL<<MCID::MayLoad), 0x1e0000000024ULL }, // Inst #1524 = L2_loadbsw4_pcr
5617 { 1523, 5, 2, 4, 36, 1, 0, 654, HexagonImpOpBase + 100, 0|(1ULL<<MCID::MayLoad), 0x1e0000000024ULL }, // Inst #1523 = L2_loadbsw4_pci
5618 { 1522, 4, 2, 4, 20, 0, 0, 650, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x1e0000000024ULL }, // Inst #1522 = L2_loadbsw4_pbr
5619 { 1521, 3, 1, 4, 19, 0, 0, 501, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x1b09b4800024ULL }, // Inst #1521 = L2_loadbsw4_io
5620 { 1520, 4, 2, 4, 20, 0, 0, 637, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x160000008024ULL }, // Inst #1520 = L2_loadbsw2_pr
5621 { 1519, 4, 2, 4, 20, 0, 0, 646, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x160000008024ULL }, // Inst #1519 = L2_loadbsw2_pi
5622 { 1518, 4, 2, 4, 20, 1, 0, 637, HexagonImpOpBase + 100, 0|(1ULL<<MCID::MayLoad), 0x160000008024ULL }, // Inst #1518 = L2_loadbsw2_pcr
5623 { 1517, 5, 2, 4, 36, 1, 0, 641, HexagonImpOpBase + 100, 0|(1ULL<<MCID::MayLoad), 0x160000008024ULL }, // Inst #1517 = L2_loadbsw2_pci
5624 { 1516, 4, 2, 4, 20, 0, 0, 637, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x160000008024ULL }, // Inst #1516 = L2_loadbsw2_pbr
5625 { 1515, 3, 1, 4, 19, 0, 0, 199, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x130594808024ULL }, // Inst #1515 = L2_loadbsw2_io
5626 { 1514, 5, 2, 4, 145, 0, 0, 621, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x160000000024ULL }, // Inst #1514 = L2_loadalignh_pr
5627 { 1513, 5, 2, 4, 145, 0, 0, 632, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x160000000024ULL }, // Inst #1513 = L2_loadalignh_pi
5628 { 1512, 5, 2, 4, 145, 1, 0, 621, HexagonImpOpBase + 100, 0|(1ULL<<MCID::MayLoad), 0x160000000024ULL }, // Inst #1512 = L2_loadalignh_pcr
5629 { 1511, 6, 2, 4, 146, 1, 0, 626, HexagonImpOpBase + 100, 0|(1ULL<<MCID::MayLoad), 0x160000000024ULL }, // Inst #1511 = L2_loadalignh_pci
5630 { 1510, 5, 2, 4, 145, 0, 0, 621, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x160000000024ULL }, // Inst #1510 = L2_loadalignh_pbr
5631 { 1509, 4, 1, 4, 18, 0, 0, 617, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x130596800024ULL }, // Inst #1509 = L2_loadalignh_io
5632 { 1508, 5, 2, 4, 145, 0, 0, 621, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0xe0000000024ULL }, // Inst #1508 = L2_loadalignb_pr
5633 { 1507, 5, 2, 4, 145, 0, 0, 632, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0xe0000000024ULL }, // Inst #1507 = L2_loadalignb_pi
5634 { 1506, 5, 2, 4, 145, 1, 0, 621, HexagonImpOpBase + 100, 0|(1ULL<<MCID::MayLoad), 0xe0000000024ULL }, // Inst #1506 = L2_loadalignb_pcr
5635 { 1505, 6, 2, 4, 146, 1, 0, 626, HexagonImpOpBase + 100, 0|(1ULL<<MCID::MayLoad), 0xe0000000024ULL }, // Inst #1505 = L2_loadalignb_pci
5636 { 1504, 5, 2, 4, 145, 0, 0, 621, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0xe0000000024ULL }, // Inst #1504 = L2_loadalignb_pbr
5637 { 1503, 4, 1, 4, 18, 0, 0, 617, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0xb0176800024ULL }, // Inst #1503 = L2_loadalignb_io
5638 { 1502, 2, 1, 4, 27, 1, 1, 190, HexagonImpOpBase + 56, 0|(1ULL<<MCID::MayLoad), 0x200000000024ULL }, // Inst #1502 = L2_deallocframe
5639 { 1501, 2, 0, 4, 144, 1, 2, 615, HexagonImpOpBase + 97, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x807972801404ULL }, // Inst #1501 = J4_tstbit0_tp1_jump_t
5640 { 1500, 2, 0, 4, 144, 1, 2, 615, HexagonImpOpBase + 97, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7972801404ULL }, // Inst #1500 = J4_tstbit0_tp1_jump_nt
5641 { 1499, 2, 0, 4, 144, 1, 2, 615, HexagonImpOpBase + 94, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x807972801404ULL }, // Inst #1499 = J4_tstbit0_tp0_jump_t
5642 { 1498, 2, 0, 4, 144, 1, 2, 615, HexagonImpOpBase + 94, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7972801404ULL }, // Inst #1498 = J4_tstbit0_tp0_jump_nt
5643 { 1497, 2, 0, 4, 143, 0, 1, 155, HexagonImpOpBase + 55, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x809972804427ULL }, // Inst #1497 = J4_tstbit0_t_jumpnv_t
5644 { 1496, 2, 0, 4, 143, 0, 1, 155, HexagonImpOpBase + 55, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x9972804427ULL }, // Inst #1496 = J4_tstbit0_t_jumpnv_nt
5645 { 1495, 2, 0, 4, 144, 1, 2, 615, HexagonImpOpBase + 97, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x807972801c04ULL }, // Inst #1495 = J4_tstbit0_fp1_jump_t
5646 { 1494, 2, 0, 4, 144, 1, 2, 615, HexagonImpOpBase + 97, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7972801c04ULL }, // Inst #1494 = J4_tstbit0_fp1_jump_nt
5647 { 1493, 2, 0, 4, 144, 1, 2, 615, HexagonImpOpBase + 94, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x807972801c04ULL }, // Inst #1493 = J4_tstbit0_fp0_jump_t
5648 { 1492, 2, 0, 4, 144, 1, 2, 615, HexagonImpOpBase + 94, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7972801c04ULL }, // Inst #1492 = J4_tstbit0_fp0_jump_nt
5649 { 1491, 2, 0, 4, 143, 0, 1, 155, HexagonImpOpBase + 55, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x809972804c27ULL }, // Inst #1491 = J4_tstbit0_f_jumpnv_t
5650 { 1490, 2, 0, 4, 143, 0, 1, 155, HexagonImpOpBase + 55, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x9972804c27ULL }, // Inst #1490 = J4_tstbit0_f_jumpnv_nt
5651 { 1489, 3, 1, 4, 142, 0, 1, 609, HexagonImpOpBase + 55, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x5974808004ULL }, // Inst #1489 = J4_jumpsetr
5652 { 1488, 3, 1, 4, 142, 0, 1, 612, HexagonImpOpBase + 55, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x5974808004ULL }, // Inst #1488 = J4_jumpseti
5653 { 1487, 1, 0, 4, 141, 0, 0, 272, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x7000000023ULL }, // Inst #1487 = J4_hintjumpr
5654 { 1486, 3, 0, 4, 140, 0, 1, 199, HexagonImpOpBase + 55, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x809974814427ULL }, // Inst #1486 = J4_cmpltu_t_jumpnv_t
5655 { 1485, 3, 0, 4, 140, 0, 1, 199, HexagonImpOpBase + 55, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x9974814427ULL }, // Inst #1485 = J4_cmpltu_t_jumpnv_nt
5656 { 1484, 3, 0, 4, 140, 0, 1, 199, HexagonImpOpBase + 55, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x809974814c27ULL }, // Inst #1484 = J4_cmpltu_f_jumpnv_t
5657 { 1483, 3, 0, 4, 140, 0, 1, 199, HexagonImpOpBase + 55, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x9974814c27ULL }, // Inst #1483 = J4_cmpltu_f_jumpnv_nt
5658 { 1482, 3, 0, 4, 140, 0, 1, 199, HexagonImpOpBase + 55, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x809974814427ULL }, // Inst #1482 = J4_cmplt_t_jumpnv_t
5659 { 1481, 3, 0, 4, 140, 0, 1, 199, HexagonImpOpBase + 55, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x9974814427ULL }, // Inst #1481 = J4_cmplt_t_jumpnv_nt
5660 { 1480, 3, 0, 4, 140, 0, 1, 199, HexagonImpOpBase + 55, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x809974814c27ULL }, // Inst #1480 = J4_cmplt_f_jumpnv_t
5661 { 1479, 3, 0, 4, 140, 0, 1, 199, HexagonImpOpBase + 55, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x9974814c27ULL }, // Inst #1479 = J4_cmplt_f_jumpnv_nt
5662 { 1478, 3, 0, 4, 139, 1, 2, 612, HexagonImpOpBase + 97, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x807974801404ULL }, // Inst #1478 = J4_cmpgtui_tp1_jump_t
5663 { 1477, 3, 0, 4, 139, 1, 2, 612, HexagonImpOpBase + 97, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7974801404ULL }, // Inst #1477 = J4_cmpgtui_tp1_jump_nt
5664 { 1476, 3, 0, 4, 139, 1, 2, 612, HexagonImpOpBase + 94, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x807974801404ULL }, // Inst #1476 = J4_cmpgtui_tp0_jump_t
5665 { 1475, 3, 0, 4, 139, 1, 2, 612, HexagonImpOpBase + 94, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7974801404ULL }, // Inst #1475 = J4_cmpgtui_tp0_jump_nt
5666 { 1474, 3, 0, 4, 138, 0, 1, 516, HexagonImpOpBase + 55, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x809974804427ULL }, // Inst #1474 = J4_cmpgtui_t_jumpnv_t
5667 { 1473, 3, 0, 4, 138, 0, 1, 516, HexagonImpOpBase + 55, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x9974804427ULL }, // Inst #1473 = J4_cmpgtui_t_jumpnv_nt
5668 { 1472, 3, 0, 4, 139, 1, 2, 612, HexagonImpOpBase + 97, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x807974801c04ULL }, // Inst #1472 = J4_cmpgtui_fp1_jump_t
5669 { 1471, 3, 0, 4, 139, 1, 2, 612, HexagonImpOpBase + 97, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7974801c04ULL }, // Inst #1471 = J4_cmpgtui_fp1_jump_nt
5670 { 1470, 3, 0, 4, 139, 1, 2, 612, HexagonImpOpBase + 94, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x807974801c04ULL }, // Inst #1470 = J4_cmpgtui_fp0_jump_t
5671 { 1469, 3, 0, 4, 139, 1, 2, 612, HexagonImpOpBase + 94, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7974801c04ULL }, // Inst #1469 = J4_cmpgtui_fp0_jump_nt
5672 { 1468, 3, 0, 4, 138, 0, 1, 516, HexagonImpOpBase + 55, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x809974804c27ULL }, // Inst #1468 = J4_cmpgtui_f_jumpnv_t
5673 { 1467, 3, 0, 4, 138, 0, 1, 516, HexagonImpOpBase + 55, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x9974804c27ULL }, // Inst #1467 = J4_cmpgtui_f_jumpnv_nt
5674 { 1466, 3, 0, 4, 137, 1, 2, 609, HexagonImpOpBase + 97, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x807974801404ULL }, // Inst #1466 = J4_cmpgtu_tp1_jump_t
5675 { 1465, 3, 0, 4, 137, 1, 2, 609, HexagonImpOpBase + 97, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7974801404ULL }, // Inst #1465 = J4_cmpgtu_tp1_jump_nt
5676 { 1464, 3, 0, 4, 137, 1, 2, 609, HexagonImpOpBase + 94, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x807974801404ULL }, // Inst #1464 = J4_cmpgtu_tp0_jump_t
5677 { 1463, 3, 0, 4, 137, 1, 2, 609, HexagonImpOpBase + 94, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7974801404ULL }, // Inst #1463 = J4_cmpgtu_tp0_jump_nt
5678 { 1462, 3, 0, 4, 136, 0, 1, 199, HexagonImpOpBase + 55, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x809974804427ULL }, // Inst #1462 = J4_cmpgtu_t_jumpnv_t
5679 { 1461, 3, 0, 4, 136, 0, 1, 199, HexagonImpOpBase + 55, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x9974804427ULL }, // Inst #1461 = J4_cmpgtu_t_jumpnv_nt
5680 { 1460, 3, 0, 4, 137, 1, 2, 609, HexagonImpOpBase + 97, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x807974801c04ULL }, // Inst #1460 = J4_cmpgtu_fp1_jump_t
5681 { 1459, 3, 0, 4, 137, 1, 2, 609, HexagonImpOpBase + 97, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7974801c04ULL }, // Inst #1459 = J4_cmpgtu_fp1_jump_nt
5682 { 1458, 3, 0, 4, 137, 1, 2, 609, HexagonImpOpBase + 94, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x807974801c04ULL }, // Inst #1458 = J4_cmpgtu_fp0_jump_t
5683 { 1457, 3, 0, 4, 137, 1, 2, 609, HexagonImpOpBase + 94, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7974801c04ULL }, // Inst #1457 = J4_cmpgtu_fp0_jump_nt
5684 { 1456, 3, 0, 4, 136, 0, 1, 199, HexagonImpOpBase + 55, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x809974804c27ULL }, // Inst #1456 = J4_cmpgtu_f_jumpnv_t
5685 { 1455, 3, 0, 4, 136, 0, 1, 199, HexagonImpOpBase + 55, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x9974804c27ULL }, // Inst #1455 = J4_cmpgtu_f_jumpnv_nt
5686 { 1454, 3, 0, 4, 139, 1, 2, 612, HexagonImpOpBase + 97, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x807974801404ULL }, // Inst #1454 = J4_cmpgtn1_tp1_jump_t
5687 { 1453, 3, 0, 4, 139, 1, 2, 612, HexagonImpOpBase + 97, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7974801404ULL }, // Inst #1453 = J4_cmpgtn1_tp1_jump_nt
5688 { 1452, 3, 0, 4, 139, 1, 2, 612, HexagonImpOpBase + 94, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x807974801404ULL }, // Inst #1452 = J4_cmpgtn1_tp0_jump_t
5689 { 1451, 3, 0, 4, 139, 1, 2, 612, HexagonImpOpBase + 94, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7974801404ULL }, // Inst #1451 = J4_cmpgtn1_tp0_jump_nt
5690 { 1450, 3, 0, 4, 138, 0, 1, 516, HexagonImpOpBase + 55, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x809974804427ULL }, // Inst #1450 = J4_cmpgtn1_t_jumpnv_t
5691 { 1449, 3, 0, 4, 138, 0, 1, 516, HexagonImpOpBase + 55, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x9974804427ULL }, // Inst #1449 = J4_cmpgtn1_t_jumpnv_nt
5692 { 1448, 3, 0, 4, 139, 1, 2, 612, HexagonImpOpBase + 97, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x807974801c04ULL }, // Inst #1448 = J4_cmpgtn1_fp1_jump_t
5693 { 1447, 3, 0, 4, 139, 1, 2, 612, HexagonImpOpBase + 97, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7974801c04ULL }, // Inst #1447 = J4_cmpgtn1_fp1_jump_nt
5694 { 1446, 3, 0, 4, 139, 1, 2, 612, HexagonImpOpBase + 94, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x807974801c04ULL }, // Inst #1446 = J4_cmpgtn1_fp0_jump_t
5695 { 1445, 3, 0, 4, 139, 1, 2, 612, HexagonImpOpBase + 94, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7974801c04ULL }, // Inst #1445 = J4_cmpgtn1_fp0_jump_nt
5696 { 1444, 3, 0, 4, 138, 0, 1, 516, HexagonImpOpBase + 55, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x809974804c27ULL }, // Inst #1444 = J4_cmpgtn1_f_jumpnv_t
5697 { 1443, 3, 0, 4, 138, 0, 1, 516, HexagonImpOpBase + 55, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x9974804c27ULL }, // Inst #1443 = J4_cmpgtn1_f_jumpnv_nt
5698 { 1442, 3, 0, 4, 139, 1, 2, 612, HexagonImpOpBase + 97, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x807974801404ULL }, // Inst #1442 = J4_cmpgti_tp1_jump_t
5699 { 1441, 3, 0, 4, 139, 1, 2, 612, HexagonImpOpBase + 97, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7974801404ULL }, // Inst #1441 = J4_cmpgti_tp1_jump_nt
5700 { 1440, 3, 0, 4, 139, 1, 2, 612, HexagonImpOpBase + 94, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x807974801404ULL }, // Inst #1440 = J4_cmpgti_tp0_jump_t
5701 { 1439, 3, 0, 4, 139, 1, 2, 612, HexagonImpOpBase + 94, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7974801404ULL }, // Inst #1439 = J4_cmpgti_tp0_jump_nt
5702 { 1438, 3, 0, 4, 138, 0, 1, 516, HexagonImpOpBase + 55, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x809974804427ULL }, // Inst #1438 = J4_cmpgti_t_jumpnv_t
5703 { 1437, 3, 0, 4, 138, 0, 1, 516, HexagonImpOpBase + 55, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x9974804427ULL }, // Inst #1437 = J4_cmpgti_t_jumpnv_nt
5704 { 1436, 3, 0, 4, 139, 1, 2, 612, HexagonImpOpBase + 97, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x807974801c04ULL }, // Inst #1436 = J4_cmpgti_fp1_jump_t
5705 { 1435, 3, 0, 4, 139, 1, 2, 612, HexagonImpOpBase + 97, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7974801c04ULL }, // Inst #1435 = J4_cmpgti_fp1_jump_nt
5706 { 1434, 3, 0, 4, 139, 1, 2, 612, HexagonImpOpBase + 94, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x807974801c04ULL }, // Inst #1434 = J4_cmpgti_fp0_jump_t
5707 { 1433, 3, 0, 4, 139, 1, 2, 612, HexagonImpOpBase + 94, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7974801c04ULL }, // Inst #1433 = J4_cmpgti_fp0_jump_nt
5708 { 1432, 3, 0, 4, 138, 0, 1, 516, HexagonImpOpBase + 55, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x809974804c27ULL }, // Inst #1432 = J4_cmpgti_f_jumpnv_t
5709 { 1431, 3, 0, 4, 138, 0, 1, 516, HexagonImpOpBase + 55, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x9974804c27ULL }, // Inst #1431 = J4_cmpgti_f_jumpnv_nt
5710 { 1430, 3, 0, 4, 137, 1, 2, 609, HexagonImpOpBase + 97, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x807974801404ULL }, // Inst #1430 = J4_cmpgt_tp1_jump_t
5711 { 1429, 3, 0, 4, 137, 1, 2, 609, HexagonImpOpBase + 97, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7974801404ULL }, // Inst #1429 = J4_cmpgt_tp1_jump_nt
5712 { 1428, 3, 0, 4, 137, 1, 2, 609, HexagonImpOpBase + 94, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x807974801404ULL }, // Inst #1428 = J4_cmpgt_tp0_jump_t
5713 { 1427, 3, 0, 4, 137, 1, 2, 609, HexagonImpOpBase + 94, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7974801404ULL }, // Inst #1427 = J4_cmpgt_tp0_jump_nt
5714 { 1426, 3, 0, 4, 136, 0, 1, 199, HexagonImpOpBase + 55, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x809974804427ULL }, // Inst #1426 = J4_cmpgt_t_jumpnv_t
5715 { 1425, 3, 0, 4, 136, 0, 1, 199, HexagonImpOpBase + 55, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x9974804427ULL }, // Inst #1425 = J4_cmpgt_t_jumpnv_nt
5716 { 1424, 3, 0, 4, 137, 1, 2, 609, HexagonImpOpBase + 97, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x807974801c04ULL }, // Inst #1424 = J4_cmpgt_fp1_jump_t
5717 { 1423, 3, 0, 4, 137, 1, 2, 609, HexagonImpOpBase + 97, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7974801c04ULL }, // Inst #1423 = J4_cmpgt_fp1_jump_nt
5718 { 1422, 3, 0, 4, 137, 1, 2, 609, HexagonImpOpBase + 94, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x807974801c04ULL }, // Inst #1422 = J4_cmpgt_fp0_jump_t
5719 { 1421, 3, 0, 4, 137, 1, 2, 609, HexagonImpOpBase + 94, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7974801c04ULL }, // Inst #1421 = J4_cmpgt_fp0_jump_nt
5720 { 1420, 3, 0, 4, 136, 0, 1, 199, HexagonImpOpBase + 55, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x809974804c27ULL }, // Inst #1420 = J4_cmpgt_f_jumpnv_t
5721 { 1419, 3, 0, 4, 136, 0, 1, 199, HexagonImpOpBase + 55, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x9974804c27ULL }, // Inst #1419 = J4_cmpgt_f_jumpnv_nt
5722 { 1418, 3, 0, 4, 139, 1, 2, 612, HexagonImpOpBase + 97, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x807974801404ULL }, // Inst #1418 = J4_cmpeqn1_tp1_jump_t
5723 { 1417, 3, 0, 4, 139, 1, 2, 612, HexagonImpOpBase + 97, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7974801404ULL }, // Inst #1417 = J4_cmpeqn1_tp1_jump_nt
5724 { 1416, 3, 0, 4, 139, 1, 2, 612, HexagonImpOpBase + 94, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x807974801404ULL }, // Inst #1416 = J4_cmpeqn1_tp0_jump_t
5725 { 1415, 3, 0, 4, 139, 1, 2, 612, HexagonImpOpBase + 94, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7974801404ULL }, // Inst #1415 = J4_cmpeqn1_tp0_jump_nt
5726 { 1414, 3, 0, 4, 138, 0, 1, 516, HexagonImpOpBase + 55, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x809974804427ULL }, // Inst #1414 = J4_cmpeqn1_t_jumpnv_t
5727 { 1413, 3, 0, 4, 138, 0, 1, 516, HexagonImpOpBase + 55, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x9974804427ULL }, // Inst #1413 = J4_cmpeqn1_t_jumpnv_nt
5728 { 1412, 3, 0, 4, 139, 1, 2, 612, HexagonImpOpBase + 97, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x807974801c04ULL }, // Inst #1412 = J4_cmpeqn1_fp1_jump_t
5729 { 1411, 3, 0, 4, 139, 1, 2, 612, HexagonImpOpBase + 97, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7974801c04ULL }, // Inst #1411 = J4_cmpeqn1_fp1_jump_nt
5730 { 1410, 3, 0, 4, 139, 1, 2, 612, HexagonImpOpBase + 94, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x807974801c04ULL }, // Inst #1410 = J4_cmpeqn1_fp0_jump_t
5731 { 1409, 3, 0, 4, 139, 1, 2, 612, HexagonImpOpBase + 94, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7974801c04ULL }, // Inst #1409 = J4_cmpeqn1_fp0_jump_nt
5732 { 1408, 3, 0, 4, 138, 0, 1, 516, HexagonImpOpBase + 55, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x809974804c27ULL }, // Inst #1408 = J4_cmpeqn1_f_jumpnv_t
5733 { 1407, 3, 0, 4, 138, 0, 1, 516, HexagonImpOpBase + 55, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x9974804c27ULL }, // Inst #1407 = J4_cmpeqn1_f_jumpnv_nt
5734 { 1406, 3, 0, 4, 139, 1, 2, 612, HexagonImpOpBase + 97, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x807974801404ULL }, // Inst #1406 = J4_cmpeqi_tp1_jump_t
5735 { 1405, 3, 0, 4, 139, 1, 2, 612, HexagonImpOpBase + 97, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7974801404ULL }, // Inst #1405 = J4_cmpeqi_tp1_jump_nt
5736 { 1404, 3, 0, 4, 139, 1, 2, 612, HexagonImpOpBase + 94, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x807974801404ULL }, // Inst #1404 = J4_cmpeqi_tp0_jump_t
5737 { 1403, 3, 0, 4, 139, 1, 2, 612, HexagonImpOpBase + 94, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7974801404ULL }, // Inst #1403 = J4_cmpeqi_tp0_jump_nt
5738 { 1402, 3, 0, 4, 138, 0, 1, 516, HexagonImpOpBase + 55, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x809974804427ULL }, // Inst #1402 = J4_cmpeqi_t_jumpnv_t
5739 { 1401, 3, 0, 4, 138, 0, 1, 516, HexagonImpOpBase + 55, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x9974804427ULL }, // Inst #1401 = J4_cmpeqi_t_jumpnv_nt
5740 { 1400, 3, 0, 4, 139, 1, 2, 612, HexagonImpOpBase + 97, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x807974801c04ULL }, // Inst #1400 = J4_cmpeqi_fp1_jump_t
5741 { 1399, 3, 0, 4, 139, 1, 2, 612, HexagonImpOpBase + 97, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7974801c04ULL }, // Inst #1399 = J4_cmpeqi_fp1_jump_nt
5742 { 1398, 3, 0, 4, 139, 1, 2, 612, HexagonImpOpBase + 94, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x807974801c04ULL }, // Inst #1398 = J4_cmpeqi_fp0_jump_t
5743 { 1397, 3, 0, 4, 139, 1, 2, 612, HexagonImpOpBase + 94, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7974801c04ULL }, // Inst #1397 = J4_cmpeqi_fp0_jump_nt
5744 { 1396, 3, 0, 4, 138, 0, 1, 516, HexagonImpOpBase + 55, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x809974804c27ULL }, // Inst #1396 = J4_cmpeqi_f_jumpnv_t
5745 { 1395, 3, 0, 4, 138, 0, 1, 516, HexagonImpOpBase + 55, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x9974804c27ULL }, // Inst #1395 = J4_cmpeqi_f_jumpnv_nt
5746 { 1394, 3, 0, 4, 137, 1, 2, 609, HexagonImpOpBase + 97, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x807974801404ULL }, // Inst #1394 = J4_cmpeq_tp1_jump_t
5747 { 1393, 3, 0, 4, 137, 1, 2, 609, HexagonImpOpBase + 97, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7974801404ULL }, // Inst #1393 = J4_cmpeq_tp1_jump_nt
5748 { 1392, 3, 0, 4, 137, 1, 2, 609, HexagonImpOpBase + 94, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x807974801404ULL }, // Inst #1392 = J4_cmpeq_tp0_jump_t
5749 { 1391, 3, 0, 4, 137, 1, 2, 609, HexagonImpOpBase + 94, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7974801404ULL }, // Inst #1391 = J4_cmpeq_tp0_jump_nt
5750 { 1390, 3, 0, 4, 136, 0, 1, 199, HexagonImpOpBase + 55, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x809974804427ULL }, // Inst #1390 = J4_cmpeq_t_jumpnv_t
5751 { 1389, 3, 0, 4, 136, 0, 1, 199, HexagonImpOpBase + 55, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x9974804427ULL }, // Inst #1389 = J4_cmpeq_t_jumpnv_nt
5752 { 1388, 3, 0, 4, 137, 1, 2, 609, HexagonImpOpBase + 97, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x807974801c04ULL }, // Inst #1388 = J4_cmpeq_fp1_jump_t
5753 { 1387, 3, 0, 4, 137, 1, 2, 609, HexagonImpOpBase + 97, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7974801c04ULL }, // Inst #1387 = J4_cmpeq_fp1_jump_nt
5754 { 1386, 3, 0, 4, 137, 1, 2, 609, HexagonImpOpBase + 94, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x807974801c04ULL }, // Inst #1386 = J4_cmpeq_fp0_jump_t
5755 { 1385, 3, 0, 4, 137, 1, 2, 609, HexagonImpOpBase + 94, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7974801c04ULL }, // Inst #1385 = J4_cmpeq_fp0_jump_nt
5756 { 1384, 3, 0, 4, 136, 0, 1, 199, HexagonImpOpBase + 55, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x809974804c27ULL }, // Inst #1384 = J4_cmpeq_f_jumpnv_t
5757 { 1383, 3, 0, 4, 136, 0, 1, 199, HexagonImpOpBase + 55, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x9974804c27ULL }, // Inst #1383 = J4_cmpeq_f_jumpnv_nt
5758 { 1382, 0, 0, 4, 135, 0, 0, 1, HexagonImpOpBase + 0, 0, 0xa3ULL }, // Inst #1382 = J2_unpause
5759 { 1381, 3, 1, 4, 17, 2, 3, 507, HexagonImpOpBase + 89, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80a3ULL }, // Inst #1381 = J2_trap1
5760 { 1380, 1, 0, 4, 134, 0, 0, 0, HexagonImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa3ULL }, // Inst #1380 = J2_trap0
5761 { 1379, 0, 0, 4, 133, 1, 1, 1, HexagonImpOpBase + 87, 0, 0x23ULL }, // Inst #1379 = J2_rte
5762 { 1378, 2, 0, 4, 132, 0, 4, 607, HexagonImpOpBase + 83, 0, 0x6930802005ULL }, // Inst #1378 = J2_ploop3sr
5763 { 1377, 2, 0, 4, 131, 0, 4, 13, HexagonImpOpBase + 83, 0, 0x6930802005ULL }, // Inst #1377 = J2_ploop3si
5764 { 1376, 2, 0, 4, 132, 0, 4, 607, HexagonImpOpBase + 83, 0, 0x6930802005ULL }, // Inst #1376 = J2_ploop2sr
5765 { 1375, 2, 0, 4, 131, 0, 4, 13, HexagonImpOpBase + 83, 0, 0x6930802005ULL }, // Inst #1375 = J2_ploop2si
5766 { 1374, 2, 0, 4, 132, 0, 4, 607, HexagonImpOpBase + 83, 0, 0x6930802005ULL }, // Inst #1374 = J2_ploop1sr
5767 { 1373, 2, 0, 4, 131, 0, 4, 13, HexagonImpOpBase + 83, 0, 0x6930802005ULL }, // Inst #1373 = J2_ploop1si
5768 { 1372, 1, 0, 4, 130, 0, 0, 0, HexagonImpOpBase + 0, 0, 0xa3ULL }, // Inst #1372 = J2_pause
5769 { 1371, 2, 0, 4, 129, 0, 2, 607, HexagonImpOpBase + 79, 0, 0x931800005ULL }, // Inst #1371 = J2_loop1rext
5770 { 1370, 2, 0, 4, 129, 0, 2, 607, HexagonImpOpBase + 81, 0, 0x6930800005ULL }, // Inst #1370 = J2_loop1r
5771 { 1369, 2, 0, 4, 128, 0, 3, 13, HexagonImpOpBase + 76, 0, 0x931800005ULL }, // Inst #1369 = J2_loop1iext
5772 { 1368, 2, 0, 4, 128, 0, 2, 13, HexagonImpOpBase + 81, 0, 0x6930800005ULL }, // Inst #1368 = J2_loop1i
5773 { 1367, 2, 0, 4, 129, 0, 2, 607, HexagonImpOpBase + 79, 0, 0x931800005ULL }, // Inst #1367 = J2_loop0rext
5774 { 1366, 2, 0, 4, 129, 0, 3, 607, HexagonImpOpBase + 73, 0, 0x6930800005ULL }, // Inst #1366 = J2_loop0r
5775 { 1365, 2, 0, 4, 128, 0, 3, 13, HexagonImpOpBase + 76, 0, 0x931800005ULL }, // Inst #1365 = J2_loop0iext
5776 { 1364, 2, 0, 4, 128, 0, 3, 13, HexagonImpOpBase + 73, 0, 0x6930800005ULL }, // Inst #1364 = J2_loop0i
5777 { 1363, 2, 0, 4, 123, 0, 1, 183, HexagonImpOpBase + 55, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x807a32800423ULL }, // Inst #1363 = J2_jumptpt
5778 { 1362, 2, 0, 4, 122, 0, 1, 183, HexagonImpOpBase + 55, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x807a32801423ULL }, // Inst #1362 = J2_jumptnewpt
5779 { 1361, 2, 0, 4, 122, 0, 1, 183, HexagonImpOpBase + 55, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7a32801423ULL }, // Inst #1361 = J2_jumptnew
5780 { 1360, 2, 0, 4, 15, 0, 1, 183, HexagonImpOpBase + 55, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7a32800423ULL }, // Inst #1360 = J2_jumpt
5781 { 1359, 2, 0, 4, 126, 0, 1, 155, HexagonImpOpBase + 55, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x807000001405ULL }, // Inst #1359 = J2_jumprzpt
5782 { 1358, 2, 0, 4, 126, 0, 1, 155, HexagonImpOpBase + 55, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7000001405ULL }, // Inst #1358 = J2_jumprz
5783 { 1357, 2, 0, 4, 125, 0, 1, 185, HexagonImpOpBase + 55, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x801000000423ULL }, // Inst #1357 = J2_jumprtpt
5784 { 1356, 2, 0, 4, 124, 0, 1, 185, HexagonImpOpBase + 55, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x801000001423ULL }, // Inst #1356 = J2_jumprtnewpt
5785 { 1355, 2, 0, 4, 124, 0, 1, 185, HexagonImpOpBase + 55, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x1000001423ULL }, // Inst #1355 = J2_jumprtnew
5786 { 1354, 2, 0, 4, 16, 0, 1, 185, HexagonImpOpBase + 55, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x1000000423ULL }, // Inst #1354 = J2_jumprt
5787 { 1353, 2, 0, 4, 126, 0, 1, 155, HexagonImpOpBase + 55, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x807000001405ULL }, // Inst #1353 = J2_jumprnzpt
5788 { 1352, 2, 0, 4, 126, 0, 1, 155, HexagonImpOpBase + 55, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7000001405ULL }, // Inst #1352 = J2_jumprnz
5789 { 1351, 2, 0, 4, 126, 0, 1, 155, HexagonImpOpBase + 55, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x807000001405ULL }, // Inst #1351 = J2_jumprltezpt
5790 { 1350, 2, 0, 4, 126, 0, 1, 155, HexagonImpOpBase + 55, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7000001405ULL }, // Inst #1350 = J2_jumprltez
5791 { 1349, 1, 0, 4, 127, 0, 1, 272, HexagonImpOpBase + 55, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x1000000023ULL }, // Inst #1349 = J2_jumprh
5792 { 1348, 2, 0, 4, 126, 0, 1, 155, HexagonImpOpBase + 55, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x807000001405ULL }, // Inst #1348 = J2_jumprgtezpt
5793 { 1347, 2, 0, 4, 126, 0, 1, 155, HexagonImpOpBase + 55, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7000001405ULL }, // Inst #1347 = J2_jumprgtez
5794 { 1346, 2, 0, 4, 125, 0, 1, 185, HexagonImpOpBase + 55, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x801000000c23ULL }, // Inst #1346 = J2_jumprfpt
5795 { 1345, 2, 0, 4, 124, 0, 1, 185, HexagonImpOpBase + 55, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x801000001c23ULL }, // Inst #1345 = J2_jumprfnewpt
5796 { 1344, 2, 0, 4, 124, 0, 1, 185, HexagonImpOpBase + 55, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x1000001c23ULL }, // Inst #1344 = J2_jumprfnew
5797 { 1343, 2, 0, 4, 16, 0, 1, 185, HexagonImpOpBase + 55, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x1000000c23ULL }, // Inst #1343 = J2_jumprf
5798 { 1342, 1, 0, 4, 40, 0, 1, 272, HexagonImpOpBase + 55, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0x1000000023ULL }, // Inst #1342 = J2_jumpr
5799 { 1341, 2, 0, 4, 123, 0, 1, 183, HexagonImpOpBase + 55, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x807a32800c23ULL }, // Inst #1341 = J2_jumpfpt
5800 { 1340, 2, 0, 4, 122, 0, 1, 183, HexagonImpOpBase + 55, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x807a32801c23ULL }, // Inst #1340 = J2_jumpfnewpt
5801 { 1339, 2, 0, 4, 122, 0, 1, 183, HexagonImpOpBase + 55, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7a32801c23ULL }, // Inst #1339 = J2_jumpfnew
5802 { 1338, 2, 0, 4, 15, 0, 1, 183, HexagonImpOpBase + 55, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7a32800c23ULL }, // Inst #1338 = J2_jumpf
5803 { 1337, 1, 0, 4, 121, 0, 1, 0, HexagonImpOpBase + 55, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0x5b10800023ULL }, // Inst #1337 = J2_jump
5804 { 1336, 2, 0, 4, 117, 1, 2, 183, HexagonImpOpBase + 68, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x80007a32800423ULL }, // Inst #1336 = J2_callt
5805 { 1335, 2, 0, 4, 119, 1, 2, 185, HexagonImpOpBase + 68, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x80001000000423ULL }, // Inst #1335 = J2_callrt
5806 { 1334, 1, 0, 4, 120, 0, 2, 272, HexagonImpOpBase + 71, 0|(1ULL<<MCID::Call), 0x80001000000023ULL }, // Inst #1334 = J2_callrh
5807 { 1333, 2, 0, 4, 119, 1, 2, 185, HexagonImpOpBase + 68, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x80001000000c23ULL }, // Inst #1333 = J2_callrf
5808 { 1332, 1, 0, 4, 118, 1, 2, 272, HexagonImpOpBase + 68, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x80001000000023ULL }, // Inst #1332 = J2_callr
5809 { 1331, 2, 0, 4, 117, 1, 2, 183, HexagonImpOpBase + 68, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x80007a32800c23ULL }, // Inst #1331 = J2_callf
5810 { 1330, 1, 0, 4, 35, 1, 2, 0, HexagonImpOpBase + 68, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x80005b10800023ULL }, // Inst #1330 = J2_call
5811 { 1329, 2, 1, 4, 6, 0, 0, 155, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable), 0x8000ULL }, // Inst #1329 = HI
5812 { 1328, 2, 1, 4, 116, 0, 0, 605, HexagonImpOpBase + 0, 0, 0x8005ULL }, // Inst #1328 = G4_tfrgrcr
5813 { 1327, 2, 1, 4, 116, 0, 0, 603, HexagonImpOpBase + 0, 0, 0x8005ULL }, // Inst #1327 = G4_tfrgpcp
5814 { 1326, 2, 1, 4, 115, 0, 0, 601, HexagonImpOpBase + 0, 0, 0x8005ULL }, // Inst #1326 = G4_tfrgcrr
5815 { 1325, 2, 1, 4, 115, 0, 0, 599, HexagonImpOpBase + 0, 0, 0x5ULL }, // Inst #1325 = G4_tfrgcpp
5816 { 1324, 3, 1, 4, 109, 1, 0, 202, HexagonImpOpBase + 67, 0, 0x1000000008025ULL }, // Inst #1324 = F2_sfsub
5817 { 1323, 4, 2, 4, 114, 0, 0, 522, HexagonImpOpBase + 0, 0, 0x100000000a025ULL }, // Inst #1323 = F2_sfrecipa
5818 { 1322, 3, 1, 4, 109, 1, 0, 202, HexagonImpOpBase + 67, 0|(1ULL<<MCID::Commutable), 0x1000000008025ULL }, // Inst #1322 = F2_sfmpy
5819 { 1321, 3, 1, 4, 113, 1, 0, 202, HexagonImpOpBase + 67, 0, 0x81000000008025ULL }, // Inst #1321 = F2_sfmin
5820 { 1320, 3, 1, 4, 113, 1, 0, 202, HexagonImpOpBase + 67, 0, 0x81000000008025ULL }, // Inst #1320 = F2_sfmax
5821 { 1319, 3, 2, 4, 112, 0, 0, 159, HexagonImpOpBase + 0, 0, 0x100000000a02bULL }, // Inst #1319 = F2_sfinvsqrta
5822 { 1318, 2, 1, 4, 105, 0, 0, 155, HexagonImpOpBase + 0, 0, 0x80000000008003ULL }, // Inst #1318 = F2_sfimm_p
5823 { 1317, 2, 1, 4, 105, 0, 0, 155, HexagonImpOpBase + 0, 0, 0x80000000008003ULL }, // Inst #1317 = F2_sfimm_n
5824 { 1316, 4, 1, 4, 110, 1, 0, 590, HexagonImpOpBase + 67, 0, 0x1000000008025ULL }, // Inst #1316 = F2_sffms_lib
5825 { 1315, 4, 1, 4, 110, 1, 0, 590, HexagonImpOpBase + 67, 0, 0x1000000008025ULL }, // Inst #1315 = F2_sffms
5826 { 1314, 5, 1, 4, 111, 1, 0, 594, HexagonImpOpBase + 67, 0, 0x1000000008025ULL }, // Inst #1314 = F2_sffma_sc
5827 { 1313, 4, 1, 4, 110, 1, 0, 590, HexagonImpOpBase + 67, 0, 0x1000000008025ULL }, // Inst #1313 = F2_sffma_lib
5828 { 1312, 4, 1, 4, 110, 1, 0, 590, HexagonImpOpBase + 67, 0, 0x1000000008025ULL }, // Inst #1312 = F2_sffma
5829 { 1311, 2, 1, 4, 103, 0, 0, 157, HexagonImpOpBase + 0, 0, 0x100000000802bULL }, // Inst #1311 = F2_sffixupr
5830 { 1310, 3, 1, 4, 109, 0, 0, 202, HexagonImpOpBase + 0, 0, 0x1000000008025ULL }, // Inst #1310 = F2_sffixupn
5831 { 1309, 3, 1, 4, 109, 0, 0, 202, HexagonImpOpBase + 0, 0, 0x1000000008025ULL }, // Inst #1309 = F2_sffixupd
5832 { 1308, 3, 1, 4, 9, 1, 0, 178, HexagonImpOpBase + 67, 0|(1ULL<<MCID::Compare), 0x100000000002cULL }, // Inst #1308 = F2_sfcmpuo
5833 { 1307, 3, 1, 4, 9, 1, 0, 178, HexagonImpOpBase + 67, 0|(1ULL<<MCID::Compare), 0x100000000002cULL }, // Inst #1307 = F2_sfcmpgt
5834 { 1306, 3, 1, 4, 9, 1, 0, 178, HexagonImpOpBase + 67, 0|(1ULL<<MCID::Compare), 0x100000000002cULL }, // Inst #1306 = F2_sfcmpge
5835 { 1305, 3, 1, 4, 9, 1, 0, 178, HexagonImpOpBase + 67, 0|(1ULL<<MCID::Compare), 0x100000000002cULL }, // Inst #1305 = F2_sfcmpeq
5836 { 1304, 3, 1, 4, 89, 1, 0, 175, HexagonImpOpBase + 67, 0, 0x100000000002bULL }, // Inst #1304 = F2_sfclass
5837 { 1303, 3, 1, 4, 109, 1, 0, 202, HexagonImpOpBase + 67, 0|(1ULL<<MCID::Commutable), 0x1000000008025ULL }, // Inst #1303 = F2_sfadd
5838 { 1302, 3, 1, 4, 104, 1, 0, 169, HexagonImpOpBase + 67, 0, 0x1000000000025ULL }, // Inst #1302 = F2_dfsub
5839 { 1301, 3, 1, 4, 108, 0, 0, 169, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #1301 = F2_dfmpyll
5840 { 1300, 4, 1, 4, 107, 0, 0, 215, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #1300 = F2_dfmpylh
5841 { 1299, 4, 1, 4, 106, 1, 0, 215, HexagonImpOpBase + 67, 0, 0x1000000000025ULL }, // Inst #1299 = F2_dfmpyhh
5842 { 1298, 3, 1, 4, 104, 1, 0, 169, HexagonImpOpBase + 67, 0, 0x1000000000025ULL }, // Inst #1298 = F2_dfmpyfix
5843 { 1297, 3, 1, 4, 96, 1, 0, 169, HexagonImpOpBase + 67, 0, 0x81000000000025ULL }, // Inst #1297 = F2_dfmin
5844 { 1296, 3, 1, 4, 96, 1, 0, 169, HexagonImpOpBase + 67, 0, 0x81000000000025ULL }, // Inst #1296 = F2_dfmax
5845 { 1295, 2, 1, 4, 105, 0, 0, 167, HexagonImpOpBase + 0, 0, 0x80000000000003ULL }, // Inst #1295 = F2_dfimm_p
5846 { 1294, 2, 1, 4, 105, 0, 0, 167, HexagonImpOpBase + 0, 0, 0x80000000000003ULL }, // Inst #1294 = F2_dfimm_n
5847 { 1293, 3, 1, 4, 9, 1, 0, 534, HexagonImpOpBase + 67, 0|(1ULL<<MCID::Compare), 0x1000000000003ULL }, // Inst #1293 = F2_dfcmpuo
5848 { 1292, 3, 1, 4, 9, 1, 0, 534, HexagonImpOpBase + 67, 0|(1ULL<<MCID::Compare), 0x1000000000003ULL }, // Inst #1292 = F2_dfcmpgt
5849 { 1291, 3, 1, 4, 9, 1, 0, 534, HexagonImpOpBase + 67, 0|(1ULL<<MCID::Compare), 0x1000000000003ULL }, // Inst #1291 = F2_dfcmpge
5850 { 1290, 3, 1, 4, 9, 1, 0, 534, HexagonImpOpBase + 67, 0|(1ULL<<MCID::Compare), 0x1000000000003ULL }, // Inst #1290 = F2_dfcmpeq
5851 { 1289, 3, 1, 4, 89, 1, 0, 549, HexagonImpOpBase + 67, 0, 0x1000000000003ULL }, // Inst #1289 = F2_dfclass
5852 { 1288, 3, 1, 4, 104, 1, 0, 169, HexagonImpOpBase + 67, 0, 0x1000000000025ULL }, // Inst #1288 = F2_dfadd
5853 { 1287, 2, 1, 4, 103, 1, 0, 157, HexagonImpOpBase + 67, 0, 0x100000000802bULL }, // Inst #1287 = F2_conv_w2sf
5854 { 1286, 2, 1, 4, 103, 1, 0, 190, HexagonImpOpBase + 67, 0, 0x100000000002bULL }, // Inst #1286 = F2_conv_w2df
5855 { 1285, 2, 1, 4, 103, 1, 0, 157, HexagonImpOpBase + 67, 0, 0x100000000802bULL }, // Inst #1285 = F2_conv_uw2sf
5856 { 1284, 2, 1, 4, 103, 1, 0, 190, HexagonImpOpBase + 67, 0, 0x100000000002bULL }, // Inst #1284 = F2_conv_uw2df
5857 { 1283, 2, 1, 4, 103, 1, 0, 307, HexagonImpOpBase + 67, 0, 0x100000000802bULL }, // Inst #1283 = F2_conv_ud2sf
5858 { 1282, 2, 1, 4, 103, 1, 0, 162, HexagonImpOpBase + 67, 0, 0x100000000002bULL }, // Inst #1282 = F2_conv_ud2df
5859 { 1281, 2, 1, 4, 103, 1, 0, 157, HexagonImpOpBase + 67, 0, 0x100000000802bULL }, // Inst #1281 = F2_conv_sf2w_chop
5860 { 1280, 2, 1, 4, 103, 1, 0, 157, HexagonImpOpBase + 67, 0, 0x100000000802bULL }, // Inst #1280 = F2_conv_sf2w
5861 { 1279, 2, 1, 4, 103, 1, 0, 157, HexagonImpOpBase + 67, 0, 0x100000000802bULL }, // Inst #1279 = F2_conv_sf2uw_chop
5862 { 1278, 2, 1, 4, 103, 1, 0, 157, HexagonImpOpBase + 67, 0, 0x100000000802bULL }, // Inst #1278 = F2_conv_sf2uw
5863 { 1277, 2, 1, 4, 103, 1, 0, 190, HexagonImpOpBase + 67, 0, 0x100000000002bULL }, // Inst #1277 = F2_conv_sf2ud_chop
5864 { 1276, 2, 1, 4, 103, 1, 0, 190, HexagonImpOpBase + 67, 0, 0x100000000002bULL }, // Inst #1276 = F2_conv_sf2ud
5865 { 1275, 2, 1, 4, 103, 1, 0, 190, HexagonImpOpBase + 67, 0, 0x100000000002bULL }, // Inst #1275 = F2_conv_sf2df
5866 { 1274, 2, 1, 4, 103, 1, 0, 190, HexagonImpOpBase + 67, 0, 0x100000000002bULL }, // Inst #1274 = F2_conv_sf2d_chop
5867 { 1273, 2, 1, 4, 103, 1, 0, 190, HexagonImpOpBase + 67, 0, 0x100000000002bULL }, // Inst #1273 = F2_conv_sf2d
5868 { 1272, 2, 1, 4, 103, 1, 0, 307, HexagonImpOpBase + 67, 0, 0x100000000802bULL }, // Inst #1272 = F2_conv_df2w_chop
5869 { 1271, 2, 1, 4, 103, 1, 0, 307, HexagonImpOpBase + 67, 0, 0x100000000802bULL }, // Inst #1271 = F2_conv_df2w
5870 { 1270, 2, 1, 4, 103, 1, 0, 307, HexagonImpOpBase + 67, 0, 0x100000000802bULL }, // Inst #1270 = F2_conv_df2uw_chop
5871 { 1269, 2, 1, 4, 103, 1, 0, 307, HexagonImpOpBase + 67, 0, 0x100000000802bULL }, // Inst #1269 = F2_conv_df2uw
5872 { 1268, 2, 1, 4, 103, 1, 0, 162, HexagonImpOpBase + 67, 0, 0x100000000002bULL }, // Inst #1268 = F2_conv_df2ud_chop
5873 { 1267, 2, 1, 4, 103, 1, 0, 162, HexagonImpOpBase + 67, 0, 0x100000000002bULL }, // Inst #1267 = F2_conv_df2ud
5874 { 1266, 2, 1, 4, 103, 1, 0, 307, HexagonImpOpBase + 67, 0, 0x100000000802bULL }, // Inst #1266 = F2_conv_df2sf
5875 { 1265, 2, 1, 4, 103, 1, 0, 162, HexagonImpOpBase + 67, 0, 0x100000000002bULL }, // Inst #1265 = F2_conv_df2d_chop
5876 { 1264, 2, 1, 4, 103, 1, 0, 162, HexagonImpOpBase + 67, 0, 0x100000000002bULL }, // Inst #1264 = F2_conv_df2d
5877 { 1263, 2, 1, 4, 103, 1, 0, 307, HexagonImpOpBase + 67, 0, 0x100000000802bULL }, // Inst #1263 = F2_conv_d2sf
5878 { 1262, 2, 1, 4, 103, 1, 0, 162, HexagonImpOpBase + 67, 0, 0x100000000002bULL }, // Inst #1262 = F2_conv_d2df
5879 { 1261, 1, 0, 4, 40, 1, 1, 272, HexagonImpOpBase + 65, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x1000000023ULL }, // Inst #1261 = EH_RETURN_JMPR
5880 { 1260, 0, 0, 4, 12, 0, 0, 1, HexagonImpOpBase + 0, 0, 0x20ULL }, // Inst #1260 = DuplexIClassF
5881 { 1259, 0, 0, 4, 12, 0, 0, 1, HexagonImpOpBase + 0, 0, 0x20ULL }, // Inst #1259 = DuplexIClassE
5882 { 1258, 0, 0, 4, 12, 0, 0, 1, HexagonImpOpBase + 0, 0, 0x20ULL }, // Inst #1258 = DuplexIClassD
5883 { 1257, 0, 0, 4, 12, 0, 0, 1, HexagonImpOpBase + 0, 0, 0x20ULL }, // Inst #1257 = DuplexIClassC
5884 { 1256, 0, 0, 4, 12, 0, 0, 1, HexagonImpOpBase + 0, 0, 0x20ULL }, // Inst #1256 = DuplexIClassB
5885 { 1255, 0, 0, 4, 12, 0, 0, 1, HexagonImpOpBase + 0, 0, 0x20ULL }, // Inst #1255 = DuplexIClassA
5886 { 1254, 0, 0, 4, 12, 0, 0, 1, HexagonImpOpBase + 0, 0, 0x20ULL }, // Inst #1254 = DuplexIClass9
5887 { 1253, 0, 0, 4, 12, 0, 0, 1, HexagonImpOpBase + 0, 0, 0x20ULL }, // Inst #1253 = DuplexIClass8
5888 { 1252, 0, 0, 4, 12, 0, 0, 1, HexagonImpOpBase + 0, 0, 0x20020ULL }, // Inst #1252 = DuplexIClass7
5889 { 1251, 0, 0, 4, 12, 0, 0, 1, HexagonImpOpBase + 0, 0, 0x20020ULL }, // Inst #1251 = DuplexIClass6
5890 { 1250, 0, 0, 4, 12, 0, 0, 1, HexagonImpOpBase + 0, 0, 0x20020ULL }, // Inst #1250 = DuplexIClass5
5891 { 1249, 0, 0, 4, 12, 0, 0, 1, HexagonImpOpBase + 0, 0, 0x20020ULL }, // Inst #1249 = DuplexIClass4
5892 { 1248, 0, 0, 4, 12, 0, 0, 1, HexagonImpOpBase + 0, 0, 0x20020ULL }, // Inst #1248 = DuplexIClass3
5893 { 1247, 0, 0, 4, 12, 0, 0, 1, HexagonImpOpBase + 0, 0, 0x20ULL }, // Inst #1247 = DuplexIClass2
5894 { 1246, 0, 0, 4, 12, 0, 0, 1, HexagonImpOpBase + 0, 0, 0x20ULL }, // Inst #1246 = DuplexIClass1
5895 { 1245, 0, 0, 4, 12, 0, 0, 1, HexagonImpOpBase + 0, 0, 0x20ULL }, // Inst #1245 = DuplexIClass0
5896 { 1244, 2, 1, 4, 29, 0, 0, 588, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable), 0x24ULL }, // Inst #1244 = CONST64
5897 { 1243, 2, 1, 4, 29, 0, 0, 586, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable), 0x24ULL }, // Inst #1243 = CONST32
5898 { 1242, 1, 0, 4, 35, 0, 1, 0, HexagonImpOpBase + 64, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0xb10800023ULL }, // Inst #1242 = CALLProfile
5899 { 1241, 4, 1, 4, 102, 0, 0, 582, HexagonImpOpBase + 0, 0, 0x5ULL }, // Inst #1241 = C4_or_orn
5900 { 1240, 4, 1, 4, 102, 0, 0, 582, HexagonImpOpBase + 0, 0, 0x5ULL }, // Inst #1240 = C4_or_or
5901 { 1239, 4, 1, 4, 102, 0, 0, 582, HexagonImpOpBase + 0, 0, 0x5ULL }, // Inst #1239 = C4_or_andn
5902 { 1238, 4, 1, 4, 102, 0, 0, 582, HexagonImpOpBase + 0, 0, 0x5ULL }, // Inst #1238 = C4_or_and
5903 { 1237, 3, 1, 4, 9, 0, 0, 178, HexagonImpOpBase + 0, 0, 0x2cULL }, // Inst #1237 = C4_nbitsset
5904 { 1236, 3, 1, 4, 89, 0, 0, 175, HexagonImpOpBase + 0, 0, 0x2bULL }, // Inst #1236 = C4_nbitsclri
5905 { 1235, 3, 1, 4, 9, 0, 0, 178, HexagonImpOpBase + 0, 0, 0x2cULL }, // Inst #1235 = C4_nbitsclr
5906 { 1234, 3, 1, 4, 11, 0, 0, 560, HexagonImpOpBase + 0, 0, 0x5ULL }, // Inst #1234 = C4_fastcorner9_not
5907 { 1233, 3, 1, 4, 11, 0, 0, 560, HexagonImpOpBase + 0, 0, 0x5ULL }, // Inst #1233 = C4_fastcorner9
5908 { 1232, 3, 1, 4, 10, 0, 0, 175, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Compare), 0x154800000ULL }, // Inst #1232 = C4_cmpneqi
5909 { 1231, 3, 1, 4, 98, 0, 0, 178, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable), 0x1ULL }, // Inst #1231 = C4_cmpneq
5910 { 1230, 3, 1, 4, 10, 0, 0, 175, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Compare), 0x124800000ULL }, // Inst #1230 = C4_cmplteui
5911 { 1229, 3, 1, 4, 98, 0, 0, 178, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Compare), 0x1ULL }, // Inst #1229 = C4_cmplteu
5912 { 1228, 3, 1, 4, 10, 0, 0, 175, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Compare), 0x154800000ULL }, // Inst #1228 = C4_cmpltei
5913 { 1227, 3, 1, 4, 98, 0, 0, 178, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Compare), 0x1ULL }, // Inst #1227 = C4_cmplte
5914 { 1226, 4, 1, 4, 102, 0, 0, 582, HexagonImpOpBase + 0, 0, 0x5ULL }, // Inst #1226 = C4_and_orn
5915 { 1225, 4, 1, 4, 102, 0, 0, 582, HexagonImpOpBase + 0, 0, 0x5ULL }, // Inst #1225 = C4_and_or
5916 { 1224, 4, 1, 4, 102, 0, 0, 582, HexagonImpOpBase + 0, 0, 0x5ULL }, // Inst #1224 = C4_and_andn
5917 { 1223, 4, 1, 4, 102, 0, 0, 582, HexagonImpOpBase + 0, 0, 0x5ULL }, // Inst #1223 = C4_and_and
5918 { 1222, 2, 1, 4, 101, 0, 0, 155, HexagonImpOpBase + 0, 0, 0xc2808005ULL }, // Inst #1222 = C4_addipc
5919 { 1221, 3, 1, 4, 11, 0, 0, 560, HexagonImpOpBase + 0, 0, 0x5ULL }, // Inst #1221 = C2_xor
5920 { 1220, 4, 1, 4, 100, 0, 0, 245, HexagonImpOpBase + 0, 0, 0x3ULL }, // Inst #1220 = C2_vmux
5921 { 1219, 3, 1, 4, 78, 0, 0, 579, HexagonImpOpBase + 0, 0, 0x8000000000802bULL }, // Inst #1219 = C2_vitpack
5922 { 1218, 2, 1, 4, 99, 0, 0, 185, HexagonImpOpBase + 0, 0, 0x2bULL }, // Inst #1218 = C2_tfrrp
5923 { 1217, 2, 1, 4, 80, 0, 0, 577, HexagonImpOpBase + 0, 0, 0x802bULL }, // Inst #1217 = C2_tfrpr
5924 { 1216, 3, 1, 4, 11, 0, 0, 560, HexagonImpOpBase + 0, 0, 0x5ULL }, // Inst #1216 = C2_orn
5925 { 1215, 3, 1, 4, 11, 0, 0, 560, HexagonImpOpBase + 0, 0, 0x5ULL }, // Inst #1215 = C2_or
5926 { 1214, 2, 1, 4, 97, 0, 0, 181, HexagonImpOpBase + 0, 0, 0x5ULL }, // Inst #1214 = C2_not
5927 { 1213, 4, 1, 4, 4, 0, 0, 573, HexagonImpOpBase + 0, 0, 0x114808000ULL }, // Inst #1213 = C2_muxri
5928 { 1212, 4, 1, 4, 4, 0, 0, 526, HexagonImpOpBase + 0, 0, 0x116808000ULL }, // Inst #1212 = C2_muxir
5929 { 1211, 4, 1, 4, 4, 0, 0, 569, HexagonImpOpBase + 0, 0, 0x114808000ULL }, // Inst #1211 = C2_muxii
5930 { 1210, 4, 1, 4, 4, 0, 0, 522, HexagonImpOpBase + 0, 0, 0x8001ULL }, // Inst #1210 = C2_mux
5931 { 1209, 2, 1, 4, 80, 0, 0, 567, HexagonImpOpBase + 0, 0, 0x2bULL }, // Inst #1209 = C2_mask
5932 { 1208, 3, 1, 4, 9, 0, 0, 534, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Compare), 0x3ULL }, // Inst #1208 = C2_cmpgtup
5933 { 1207, 3, 1, 4, 10, 0, 0, 175, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Compare), 0x124800000ULL }, // Inst #1207 = C2_cmpgtui
5934 { 1206, 3, 1, 4, 98, 0, 0, 178, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Compare), 0x1ULL }, // Inst #1206 = C2_cmpgtu
5935 { 1205, 3, 1, 4, 9, 0, 0, 534, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Compare), 0x3ULL }, // Inst #1205 = C2_cmpgtp
5936 { 1204, 3, 1, 4, 10, 0, 0, 175, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Compare), 0x154800000ULL }, // Inst #1204 = C2_cmpgti
5937 { 1203, 3, 1, 4, 98, 0, 0, 178, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Compare), 0x1ULL }, // Inst #1203 = C2_cmpgt
5938 { 1202, 3, 1, 4, 9, 0, 0, 534, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable), 0x3ULL }, // Inst #1202 = C2_cmpeqp
5939 { 1201, 3, 1, 4, 10, 0, 0, 175, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Compare), 0x154800000ULL }, // Inst #1201 = C2_cmpeqi
5940 { 1200, 3, 1, 4, 98, 0, 0, 178, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable), 0x1ULL }, // Inst #1200 = C2_cmpeq
5941 { 1199, 3, 1, 4, 7, 0, 0, 504, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MoveImm), 0x194809400ULL }, // Inst #1199 = C2_cmovenewit
5942 { 1198, 3, 1, 4, 7, 0, 0, 504, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MoveImm), 0x194809c00ULL }, // Inst #1198 = C2_cmovenewif
5943 { 1197, 3, 1, 4, 6, 0, 0, 504, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MoveImm), 0x194808400ULL }, // Inst #1197 = C2_cmoveit
5944 { 1196, 3, 1, 4, 6, 0, 0, 504, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MoveImm), 0x194808c00ULL }, // Inst #1196 = C2_cmoveif
5945 { 1195, 4, 1, 4, 4, 0, 0, 563, HexagonImpOpBase + 0, 0, 0x401ULL }, // Inst #1195 = C2_ccombinewt
5946 { 1194, 4, 1, 4, 5, 0, 0, 563, HexagonImpOpBase + 0, 0, 0x1401ULL }, // Inst #1194 = C2_ccombinewnewt
5947 { 1193, 4, 1, 4, 5, 0, 0, 563, HexagonImpOpBase + 0, 0, 0x1c01ULL }, // Inst #1193 = C2_ccombinewnewf
5948 { 1192, 4, 1, 4, 4, 0, 0, 563, HexagonImpOpBase + 0, 0, 0xc01ULL }, // Inst #1192 = C2_ccombinewf
5949 { 1191, 3, 1, 4, 9, 0, 0, 178, HexagonImpOpBase + 0, 0, 0x2cULL }, // Inst #1191 = C2_bitsset
5950 { 1190, 3, 1, 4, 89, 0, 0, 175, HexagonImpOpBase + 0, 0, 0x2bULL }, // Inst #1190 = C2_bitsclri
5951 { 1189, 3, 1, 4, 9, 0, 0, 178, HexagonImpOpBase + 0, 0, 0x2cULL }, // Inst #1189 = C2_bitsclr
5952 { 1188, 2, 1, 4, 97, 0, 0, 181, HexagonImpOpBase + 0, 0, 0x5ULL }, // Inst #1188 = C2_any8
5953 { 1187, 3, 1, 4, 11, 0, 0, 560, HexagonImpOpBase + 0, 0, 0x5ULL }, // Inst #1187 = C2_andn
5954 { 1186, 3, 1, 4, 11, 0, 0, 560, HexagonImpOpBase + 0, 0, 0x5ULL }, // Inst #1186 = C2_and
5955 { 1185, 2, 1, 4, 97, 0, 0, 181, HexagonImpOpBase + 0, 0, 0x5ULL }, // Inst #1185 = C2_all8
5956 { 1184, 3, 1, 4, 94, 0, 0, 304, HexagonImpOpBase + 0, 0, 0x2bULL }, // Inst #1184 = A7_vclip
5957 { 1183, 3, 1, 4, 96, 0, 0, 209, HexagonImpOpBase + 0, 0, 0x8000000000002cULL }, // Inst #1183 = A7_croundd_rr
5958 { 1182, 3, 1, 4, 96, 0, 0, 304, HexagonImpOpBase + 0, 0, 0x8000000000002bULL }, // Inst #1182 = A7_croundd_ri
5959 { 1181, 3, 1, 4, 94, 0, 0, 199, HexagonImpOpBase + 0, 0, 0x802bULL }, // Inst #1181 = A7_clip
5960 { 1180, 4, 2, 4, 95, 0, 0, 245, HexagonImpOpBase + 0, 0, 0x80000000002025ULL }, // Inst #1180 = A6_vminub_RdP
5961 { 1179, 3, 1, 4, 94, 0, 0, 534, HexagonImpOpBase + 0, 0, 0x3ULL }, // Inst #1179 = A6_vcmpbeq_notany
5962 { 1178, 3, 1, 4, 48, 0, 1, 557, HexagonImpOpBase + 63, 0, 0x8000000000802cULL }, // Inst #1178 = A5_vaddhubs
5963 { 1177, 5, 2, 4, 93, 0, 1, 552, HexagonImpOpBase + 63, 0, 0x80000000002025ULL }, // Inst #1177 = A5_ACS
5964 { 1176, 4, 1, 4, 92, 0, 0, 205, HexagonImpOpBase + 0, 0, 0x8000000000002cULL }, // Inst #1176 = A4_vrminw
5965 { 1175, 4, 1, 4, 92, 0, 0, 205, HexagonImpOpBase + 0, 0, 0x8000000000002cULL }, // Inst #1175 = A4_vrminuw
5966 { 1174, 4, 1, 4, 92, 0, 0, 205, HexagonImpOpBase + 0, 0, 0x8000000000002cULL }, // Inst #1174 = A4_vrminuh
5967 { 1173, 4, 1, 4, 92, 0, 0, 205, HexagonImpOpBase + 0, 0, 0x8000000000002cULL }, // Inst #1173 = A4_vrminh
5968 { 1172, 4, 1, 4, 92, 0, 0, 205, HexagonImpOpBase + 0, 0, 0x8000000000002cULL }, // Inst #1172 = A4_vrmaxw
5969 { 1171, 4, 1, 4, 92, 0, 0, 205, HexagonImpOpBase + 0, 0, 0x8000000000002cULL }, // Inst #1171 = A4_vrmaxuw
5970 { 1170, 4, 1, 4, 92, 0, 0, 205, HexagonImpOpBase + 0, 0, 0x8000000000002cULL }, // Inst #1170 = A4_vrmaxuh
5971 { 1169, 4, 1, 4, 92, 0, 0, 205, HexagonImpOpBase + 0, 0, 0x8000000000002cULL }, // Inst #1169 = A4_vrmaxh
5972 { 1168, 3, 1, 4, 89, 0, 0, 549, HexagonImpOpBase + 0, 0, 0x3ULL }, // Inst #1168 = A4_vcmpwgtui
5973 { 1167, 3, 1, 4, 89, 0, 0, 549, HexagonImpOpBase + 0, 0, 0x3ULL }, // Inst #1167 = A4_vcmpwgti
5974 { 1166, 3, 1, 4, 89, 0, 0, 549, HexagonImpOpBase + 0, 0, 0x3ULL }, // Inst #1166 = A4_vcmpweqi
5975 { 1165, 3, 1, 4, 89, 0, 0, 549, HexagonImpOpBase + 0, 0, 0x3ULL }, // Inst #1165 = A4_vcmphgtui
5976 { 1164, 3, 1, 4, 89, 0, 0, 549, HexagonImpOpBase + 0, 0, 0x3ULL }, // Inst #1164 = A4_vcmphgti
5977 { 1163, 3, 1, 4, 89, 0, 0, 549, HexagonImpOpBase + 0, 0, 0x3ULL }, // Inst #1163 = A4_vcmpheqi
5978 { 1162, 3, 1, 4, 89, 0, 0, 549, HexagonImpOpBase + 0, 0, 0x3ULL }, // Inst #1162 = A4_vcmpbgtui
5979 { 1161, 3, 1, 4, 89, 0, 0, 549, HexagonImpOpBase + 0, 0, 0x3ULL }, // Inst #1161 = A4_vcmpbgti
5980 { 1160, 3, 1, 4, 9, 0, 0, 534, HexagonImpOpBase + 0, 0, 0x3ULL }, // Inst #1160 = A4_vcmpbgt
5981 { 1159, 3, 1, 4, 89, 0, 0, 549, HexagonImpOpBase + 0, 0, 0x3ULL }, // Inst #1159 = A4_vcmpbeqi
5982 { 1158, 3, 1, 4, 9, 0, 0, 534, HexagonImpOpBase + 0, 0, 0x3ULL }, // Inst #1158 = A4_vcmpbeq_any
5983 { 1157, 3, 1, 4, 91, 0, 0, 546, HexagonImpOpBase + 0, 0, 0x2003ULL }, // Inst #1157 = A4_tlbmatch
5984 { 1156, 2, 1, 4, 85, 0, 0, 544, HexagonImpOpBase + 0, 0, 0x5ULL }, // Inst #1156 = A4_tfrpcp
5985 { 1155, 2, 1, 4, 84, 0, 0, 542, HexagonImpOpBase + 0, 0, 0x5ULL }, // Inst #1155 = A4_tfrcpp
5986 { 1154, 5, 2, 4, 88, 0, 0, 537, HexagonImpOpBase + 0, 0, 0x202cULL }, // Inst #1154 = A4_subp_c
5987 { 1153, 3, 1, 4, 48, 0, 1, 202, HexagonImpOpBase + 63, 0, 0x8000000000802cULL }, // Inst #1153 = A4_round_rr_sat
5988 { 1152, 3, 1, 4, 48, 0, 0, 202, HexagonImpOpBase + 0, 0, 0x8000000000802cULL }, // Inst #1152 = A4_round_rr
5989 { 1151, 3, 1, 4, 48, 0, 1, 199, HexagonImpOpBase + 63, 0, 0x8000000000802bULL }, // Inst #1151 = A4_round_ri_sat
5990 { 1150, 3, 1, 4, 48, 0, 0, 199, HexagonImpOpBase + 0, 0, 0x8000000000802bULL }, // Inst #1150 = A4_round_ri
5991 { 1149, 3, 1, 4, 6, 0, 0, 199, HexagonImpOpBase + 0, 0, 0x114808000ULL }, // Inst #1149 = A4_rcmpneqi
5992 { 1148, 3, 1, 4, 6, 0, 0, 202, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x8001ULL }, // Inst #1148 = A4_rcmpneq
5993 { 1147, 3, 1, 4, 6, 0, 0, 199, HexagonImpOpBase + 0, 0, 0x114808000ULL }, // Inst #1147 = A4_rcmpeqi
5994 { 1146, 3, 1, 4, 6, 0, 0, 202, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x8001ULL }, // Inst #1146 = A4_rcmpeq
5995 { 1145, 3, 1, 4, 7, 0, 0, 159, HexagonImpOpBase + 0, 0, 0x9400ULL }, // Inst #1145 = A4_pzxthtnew
5996 { 1144, 3, 1, 4, 6, 0, 0, 159, HexagonImpOpBase + 0, 0, 0x8400ULL }, // Inst #1144 = A4_pzxtht
5997 { 1143, 3, 1, 4, 7, 0, 0, 159, HexagonImpOpBase + 0, 0, 0x9c00ULL }, // Inst #1143 = A4_pzxthfnew
5998 { 1142, 3, 1, 4, 6, 0, 0, 159, HexagonImpOpBase + 0, 0, 0x8c00ULL }, // Inst #1142 = A4_pzxthf
5999 { 1141, 3, 1, 4, 7, 0, 0, 159, HexagonImpOpBase + 0, 0, 0x9400ULL }, // Inst #1141 = A4_pzxtbtnew
6000 { 1140, 3, 1, 4, 6, 0, 0, 159, HexagonImpOpBase + 0, 0, 0x8400ULL }, // Inst #1140 = A4_pzxtbt
6001 { 1139, 3, 1, 4, 7, 0, 0, 159, HexagonImpOpBase + 0, 0, 0x9c00ULL }, // Inst #1139 = A4_pzxtbfnew
6002 { 1138, 3, 1, 4, 6, 0, 0, 159, HexagonImpOpBase + 0, 0, 0x8c00ULL }, // Inst #1138 = A4_pzxtbf
6003 { 1137, 3, 1, 4, 7, 0, 0, 159, HexagonImpOpBase + 0, 0, 0x9400ULL }, // Inst #1137 = A4_psxthtnew
6004 { 1136, 3, 1, 4, 6, 0, 0, 159, HexagonImpOpBase + 0, 0, 0x8400ULL }, // Inst #1136 = A4_psxtht
6005 { 1135, 3, 1, 4, 7, 0, 0, 159, HexagonImpOpBase + 0, 0, 0x9c00ULL }, // Inst #1135 = A4_psxthfnew
6006 { 1134, 3, 1, 4, 6, 0, 0, 159, HexagonImpOpBase + 0, 0, 0x8c00ULL }, // Inst #1134 = A4_psxthf
6007 { 1133, 3, 1, 4, 7, 0, 0, 159, HexagonImpOpBase + 0, 0, 0x9400ULL }, // Inst #1133 = A4_psxtbtnew
6008 { 1132, 3, 1, 4, 6, 0, 0, 159, HexagonImpOpBase + 0, 0, 0x8400ULL }, // Inst #1132 = A4_psxtbt
6009 { 1131, 3, 1, 4, 7, 0, 0, 159, HexagonImpOpBase + 0, 0, 0x9c00ULL }, // Inst #1131 = A4_psxtbfnew
6010 { 1130, 3, 1, 4, 6, 0, 0, 159, HexagonImpOpBase + 0, 0, 0x8c00ULL }, // Inst #1130 = A4_psxtbf
6011 { 1129, 3, 1, 4, 7, 0, 0, 159, HexagonImpOpBase + 0, 0, 0x9400ULL }, // Inst #1129 = A4_pasrhtnew
6012 { 1128, 3, 1, 4, 6, 0, 0, 159, HexagonImpOpBase + 0, 0, 0x8400ULL }, // Inst #1128 = A4_pasrht
6013 { 1127, 3, 1, 4, 7, 0, 0, 159, HexagonImpOpBase + 0, 0, 0x9c00ULL }, // Inst #1127 = A4_pasrhfnew
6014 { 1126, 3, 1, 4, 6, 0, 0, 159, HexagonImpOpBase + 0, 0, 0x8c00ULL }, // Inst #1126 = A4_pasrhf
6015 { 1125, 3, 1, 4, 7, 0, 0, 159, HexagonImpOpBase + 0, 0, 0x9400ULL }, // Inst #1125 = A4_paslhtnew
6016 { 1124, 3, 1, 4, 6, 0, 0, 159, HexagonImpOpBase + 0, 0, 0x8400ULL }, // Inst #1124 = A4_paslht
6017 { 1123, 3, 1, 4, 7, 0, 0, 159, HexagonImpOpBase + 0, 0, 0x9c00ULL }, // Inst #1123 = A4_paslhfnew
6018 { 1122, 3, 1, 4, 6, 0, 0, 159, HexagonImpOpBase + 0, 0, 0x8c00ULL }, // Inst #1122 = A4_paslhf
6019 { 1121, 3, 1, 4, 8, 0, 0, 169, HexagonImpOpBase + 0, 0, 0x3ULL }, // Inst #1121 = A4_ornp
6020 { 1120, 3, 1, 4, 6, 0, 0, 202, HexagonImpOpBase + 0, 0, 0x8001ULL }, // Inst #1120 = A4_orn
6021 { 1119, 3, 1, 4, 77, 0, 0, 202, HexagonImpOpBase + 0, 0, 0x80000000008003ULL }, // Inst #1119 = A4_modwrapu
6022 { 1118, 1, 0, 4, 90, 0, 0, 0, HexagonImpOpBase + 0, 0, 0x22ULL }, // Inst #1118 = A4_ext
6023 { 1117, 3, 1, 4, 48, 0, 0, 202, HexagonImpOpBase + 0, 0, 0x8000000000802cULL }, // Inst #1117 = A4_cround_rr
6024 { 1116, 3, 1, 4, 48, 0, 0, 199, HexagonImpOpBase + 0, 0, 0x8000000000802bULL }, // Inst #1116 = A4_cround_ri
6025 { 1115, 3, 1, 4, 6, 0, 0, 501, HexagonImpOpBase + 0, 0, 0x114800000ULL }, // Inst #1115 = A4_combineri
6026 { 1114, 3, 1, 4, 6, 0, 0, 498, HexagonImpOpBase + 0, 0, 0x112800000ULL }, // Inst #1114 = A4_combineir
6027 { 1113, 3, 1, 4, 6, 0, 0, 495, HexagonImpOpBase + 0, 0, 0xc4800000ULL }, // Inst #1113 = A4_combineii
6028 { 1112, 3, 1, 4, 89, 0, 0, 175, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Compare), 0xe4800003ULL }, // Inst #1112 = A4_cmphgtui
6029 { 1111, 3, 1, 4, 9, 0, 0, 178, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Compare), 0x2cULL }, // Inst #1111 = A4_cmphgtu
6030 { 1110, 3, 1, 4, 89, 0, 0, 175, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Compare), 0x114800003ULL }, // Inst #1110 = A4_cmphgti
6031 { 1109, 3, 1, 4, 9, 0, 0, 178, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Compare), 0x2cULL }, // Inst #1109 = A4_cmphgt
6032 { 1108, 3, 1, 4, 89, 0, 0, 175, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable), 0x114800003ULL }, // Inst #1108 = A4_cmpheqi
6033 { 1107, 3, 1, 4, 9, 0, 0, 178, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable), 0x2cULL }, // Inst #1107 = A4_cmpheq
6034 { 1106, 3, 1, 4, 89, 0, 0, 175, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Compare), 0xe4800003ULL }, // Inst #1106 = A4_cmpbgtui
6035 { 1105, 3, 1, 4, 9, 0, 0, 178, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Compare), 0x2cULL }, // Inst #1105 = A4_cmpbgtu
6036 { 1104, 3, 1, 4, 89, 0, 0, 175, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Compare), 0x3ULL }, // Inst #1104 = A4_cmpbgti
6037 { 1103, 3, 1, 4, 9, 0, 0, 178, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Compare), 0x2cULL }, // Inst #1103 = A4_cmpbgt
6038 { 1102, 3, 1, 4, 89, 0, 0, 175, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable), 0x3ULL }, // Inst #1102 = A4_cmpbeqi
6039 { 1101, 3, 1, 4, 9, 0, 0, 178, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable), 0x2cULL }, // Inst #1101 = A4_cmpbeq
6040 { 1100, 3, 1, 4, 9, 0, 0, 534, HexagonImpOpBase + 0, 0, 0x3ULL }, // Inst #1100 = A4_boundscheck_lo
6041 { 1099, 3, 1, 4, 9, 0, 0, 534, HexagonImpOpBase + 0, 0, 0x3ULL }, // Inst #1099 = A4_boundscheck_hi
6042 { 1098, 3, 1, 4, 78, 0, 0, 501, HexagonImpOpBase + 0, 0, 0x8000000000002bULL }, // Inst #1098 = A4_bitspliti
6043 { 1097, 3, 1, 4, 78, 0, 0, 519, HexagonImpOpBase + 0, 0, 0x80000000000003ULL }, // Inst #1097 = A4_bitsplit
6044 { 1096, 3, 1, 4, 8, 0, 0, 169, HexagonImpOpBase + 0, 0, 0x3ULL }, // Inst #1096 = A4_andnp
6045 { 1095, 3, 1, 4, 6, 0, 0, 202, HexagonImpOpBase + 0, 0, 0x8001ULL }, // Inst #1095 = A4_andn
6046 { 1094, 5, 2, 4, 88, 0, 0, 537, HexagonImpOpBase + 0, 0, 0x202cULL }, // Inst #1094 = A4_addp_c
6047 { 1093, 2, 1, 4, 3, 0, 0, 157, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x8000ULL }, // Inst #1093 = A2_zxth
6048 { 1092, 3, 1, 4, 8, 0, 0, 169, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x3ULL }, // Inst #1092 = A2_xorp
6049 { 1091, 3, 1, 4, 6, 0, 0, 202, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x8001ULL }, // Inst #1091 = A2_xor
6050 { 1090, 3, 1, 4, 77, 0, 1, 169, HexagonImpOpBase + 63, 0, 0x80000000000003ULL }, // Inst #1090 = A2_vsubws
6051 { 1089, 3, 1, 4, 8, 0, 0, 169, HexagonImpOpBase + 0, 0, 0x3ULL }, // Inst #1089 = A2_vsubw
6052 { 1088, 3, 1, 4, 77, 0, 1, 169, HexagonImpOpBase + 63, 0, 0x80000000000003ULL }, // Inst #1088 = A2_vsubuhs
6053 { 1087, 3, 1, 4, 77, 0, 1, 169, HexagonImpOpBase + 63, 0, 0x80000000000003ULL }, // Inst #1087 = A2_vsububs
6054 { 1086, 3, 1, 4, 8, 0, 0, 169, HexagonImpOpBase + 0, 0, 0x3ULL }, // Inst #1086 = A2_vsubub
6055 { 1085, 3, 1, 4, 77, 0, 1, 169, HexagonImpOpBase + 63, 0, 0x80000000000003ULL }, // Inst #1085 = A2_vsubhs
6056 { 1084, 3, 1, 4, 8, 0, 0, 169, HexagonImpOpBase + 0, 0, 0x3ULL }, // Inst #1084 = A2_vsubh
6057 { 1083, 4, 1, 4, 32, 0, 0, 215, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #1083 = A2_vrsadub_acc
6058 { 1082, 3, 1, 4, 31, 0, 0, 169, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #1082 = A2_vrsadub
6059 { 1081, 4, 1, 4, 32, 0, 0, 215, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #1081 = A2_vraddub_acc
6060 { 1080, 3, 1, 4, 31, 0, 0, 169, HexagonImpOpBase + 0, 0, 0x80000000000025ULL }, // Inst #1080 = A2_vraddub
6061 { 1079, 3, 1, 4, 48, 0, 1, 169, HexagonImpOpBase + 63, 0, 0x80000000000003ULL }, // Inst #1079 = A2_vnavgwr
6062 { 1078, 3, 1, 4, 48, 0, 1, 169, HexagonImpOpBase + 63, 0, 0x80000000000003ULL }, // Inst #1078 = A2_vnavgwcr
6063 { 1077, 3, 1, 4, 86, 0, 0, 169, HexagonImpOpBase + 0, 0, 0x80000000000003ULL }, // Inst #1077 = A2_vnavgw
6064 { 1076, 3, 1, 4, 48, 0, 1, 169, HexagonImpOpBase + 63, 0, 0x80000000000003ULL }, // Inst #1076 = A2_vnavghr
6065 { 1075, 3, 1, 4, 48, 0, 1, 169, HexagonImpOpBase + 63, 0, 0x80000000000003ULL }, // Inst #1075 = A2_vnavghcr
6066 { 1074, 3, 1, 4, 86, 0, 0, 169, HexagonImpOpBase + 0, 0, 0x80000000000003ULL }, // Inst #1074 = A2_vnavgh
6067 { 1073, 3, 1, 4, 77, 0, 0, 169, HexagonImpOpBase + 0, 0, 0x80000000000003ULL }, // Inst #1073 = A2_vminw
6068 { 1072, 3, 1, 4, 77, 0, 0, 169, HexagonImpOpBase + 0, 0, 0x80000000000003ULL }, // Inst #1072 = A2_vminuw
6069 { 1071, 3, 1, 4, 77, 0, 0, 169, HexagonImpOpBase + 0, 0, 0x80000000000003ULL }, // Inst #1071 = A2_vminuh
6070 { 1070, 3, 1, 4, 77, 0, 0, 169, HexagonImpOpBase + 0, 0, 0x80000000000003ULL }, // Inst #1070 = A2_vminub
6071 { 1069, 3, 1, 4, 77, 0, 0, 169, HexagonImpOpBase + 0, 0, 0x80000000000003ULL }, // Inst #1069 = A2_vminh
6072 { 1068, 3, 1, 4, 77, 0, 0, 169, HexagonImpOpBase + 0, 0, 0x80000000000003ULL }, // Inst #1068 = A2_vminb
6073 { 1067, 3, 1, 4, 77, 0, 0, 169, HexagonImpOpBase + 0, 0, 0x80000000000003ULL }, // Inst #1067 = A2_vmaxw
6074 { 1066, 3, 1, 4, 77, 0, 0, 169, HexagonImpOpBase + 0, 0, 0x80000000000003ULL }, // Inst #1066 = A2_vmaxuw
6075 { 1065, 3, 1, 4, 77, 0, 0, 169, HexagonImpOpBase + 0, 0, 0x80000000000003ULL }, // Inst #1065 = A2_vmaxuh
6076 { 1064, 3, 1, 4, 77, 0, 0, 169, HexagonImpOpBase + 0, 0, 0x80000000000003ULL }, // Inst #1064 = A2_vmaxub
6077 { 1063, 3, 1, 4, 77, 0, 0, 169, HexagonImpOpBase + 0, 0, 0x80000000000003ULL }, // Inst #1063 = A2_vmaxh
6078 { 1062, 3, 1, 4, 77, 0, 0, 169, HexagonImpOpBase + 0, 0, 0x80000000000003ULL }, // Inst #1062 = A2_vmaxb
6079 { 1061, 2, 1, 4, 76, 0, 1, 162, HexagonImpOpBase + 63, 0, 0x8000000000002bULL }, // Inst #1061 = A2_vconj
6080 { 1060, 3, 1, 4, 9, 0, 0, 534, HexagonImpOpBase + 0, 0, 0x3ULL }, // Inst #1060 = A2_vcmpwgtu
6081 { 1059, 3, 1, 4, 9, 0, 0, 534, HexagonImpOpBase + 0, 0, 0x3ULL }, // Inst #1059 = A2_vcmpwgt
6082 { 1058, 3, 1, 4, 9, 0, 0, 534, HexagonImpOpBase + 0, 0, 0x3ULL }, // Inst #1058 = A2_vcmpweq
6083 { 1057, 3, 1, 4, 9, 0, 0, 534, HexagonImpOpBase + 0, 0, 0x3ULL }, // Inst #1057 = A2_vcmphgtu
6084 { 1056, 3, 1, 4, 9, 0, 0, 534, HexagonImpOpBase + 0, 0, 0x3ULL }, // Inst #1056 = A2_vcmphgt
6085 { 1055, 3, 1, 4, 9, 0, 0, 534, HexagonImpOpBase + 0, 0, 0x3ULL }, // Inst #1055 = A2_vcmpheq
6086 { 1054, 3, 1, 4, 9, 0, 0, 534, HexagonImpOpBase + 0, 0, 0x3ULL }, // Inst #1054 = A2_vcmpbgtu
6087 { 1053, 3, 1, 4, 9, 0, 0, 534, HexagonImpOpBase + 0, 0, 0x3ULL }, // Inst #1053 = A2_vcmpbeq
6088 { 1052, 3, 1, 4, 87, 0, 0, 169, HexagonImpOpBase + 0, 0, 0x80000000000003ULL }, // Inst #1052 = A2_vavgwr
6089 { 1051, 3, 1, 4, 48, 0, 0, 169, HexagonImpOpBase + 0, 0, 0x80000000000003ULL }, // Inst #1051 = A2_vavgwcr
6090 { 1050, 3, 1, 4, 86, 0, 0, 169, HexagonImpOpBase + 0, 0, 0x80000000000003ULL }, // Inst #1050 = A2_vavgw
6091 { 1049, 3, 1, 4, 87, 0, 0, 169, HexagonImpOpBase + 0, 0, 0x80000000000003ULL }, // Inst #1049 = A2_vavguwr
6092 { 1048, 3, 1, 4, 86, 0, 0, 169, HexagonImpOpBase + 0, 0, 0x80000000000003ULL }, // Inst #1048 = A2_vavguw
6093 { 1047, 3, 1, 4, 87, 0, 0, 169, HexagonImpOpBase + 0, 0, 0x80000000000003ULL }, // Inst #1047 = A2_vavguhr
6094 { 1046, 3, 1, 4, 86, 0, 0, 169, HexagonImpOpBase + 0, 0, 0x80000000000003ULL }, // Inst #1046 = A2_vavguh
6095 { 1045, 3, 1, 4, 87, 0, 0, 169, HexagonImpOpBase + 0, 0, 0x80000000000003ULL }, // Inst #1045 = A2_vavgubr
6096 { 1044, 3, 1, 4, 86, 0, 0, 169, HexagonImpOpBase + 0, 0, 0x80000000000003ULL }, // Inst #1044 = A2_vavgub
6097 { 1043, 3, 1, 4, 87, 0, 0, 169, HexagonImpOpBase + 0, 0, 0x80000000000003ULL }, // Inst #1043 = A2_vavghr
6098 { 1042, 3, 1, 4, 48, 0, 0, 169, HexagonImpOpBase + 0, 0, 0x80000000000003ULL }, // Inst #1042 = A2_vavghcr
6099 { 1041, 3, 1, 4, 86, 0, 0, 169, HexagonImpOpBase + 0, 0, 0x80000000000003ULL }, // Inst #1041 = A2_vavgh
6100 { 1040, 3, 1, 4, 77, 0, 1, 169, HexagonImpOpBase + 63, 0, 0x80000000000003ULL }, // Inst #1040 = A2_vaddws
6101 { 1039, 3, 1, 4, 8, 0, 0, 169, HexagonImpOpBase + 0, 0, 0x3ULL }, // Inst #1039 = A2_vaddw
6102 { 1038, 3, 1, 4, 77, 0, 1, 169, HexagonImpOpBase + 63, 0, 0x80000000000003ULL }, // Inst #1038 = A2_vadduhs
6103 { 1037, 3, 1, 4, 77, 0, 1, 169, HexagonImpOpBase + 63, 0, 0x80000000000003ULL }, // Inst #1037 = A2_vaddubs
6104 { 1036, 3, 1, 4, 8, 0, 0, 169, HexagonImpOpBase + 0, 0, 0x3ULL }, // Inst #1036 = A2_vaddub
6105 { 1035, 3, 1, 4, 77, 0, 1, 169, HexagonImpOpBase + 63, 0, 0x80000000000003ULL }, // Inst #1035 = A2_vaddhs
6106 { 1034, 3, 1, 4, 8, 0, 0, 169, HexagonImpOpBase + 0, 0, 0x3ULL }, // Inst #1034 = A2_vaddh
6107 { 1033, 2, 1, 4, 76, 0, 1, 162, HexagonImpOpBase + 63, 0, 0x8000000000002bULL }, // Inst #1033 = A2_vabswsat
6108 { 1032, 2, 1, 4, 76, 0, 0, 162, HexagonImpOpBase + 0, 0, 0x8000000000002bULL }, // Inst #1032 = A2_vabsw
6109 { 1031, 2, 1, 4, 76, 0, 1, 162, HexagonImpOpBase + 63, 0, 0x8000000000002bULL }, // Inst #1031 = A2_vabshsat
6110 { 1030, 2, 1, 4, 76, 0, 0, 162, HexagonImpOpBase + 0, 0, 0x8000000000002bULL }, // Inst #1030 = A2_vabsh
6111 { 1029, 2, 1, 4, 3, 0, 0, 155, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x212808000ULL }, // Inst #1029 = A2_tfrsi
6112 { 1028, 2, 1, 4, 85, 0, 0, 532, HexagonImpOpBase + 0, 0, 0x8005ULL }, // Inst #1028 = A2_tfrrcr
6113 { 1027, 3, 1, 4, 6, 0, 0, 507, HexagonImpOpBase + 0, 0, 0x8000ULL }, // Inst #1027 = A2_tfril
6114 { 1026, 3, 1, 4, 6, 0, 0, 507, HexagonImpOpBase + 0, 0, 0x8000ULL }, // Inst #1026 = A2_tfrih
6115 { 1025, 2, 1, 4, 84, 0, 0, 530, HexagonImpOpBase + 0, 0, 0x8005ULL }, // Inst #1025 = A2_tfrcrr
6116 { 1024, 2, 1, 4, 3, 0, 0, 157, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x8000ULL }, // Inst #1024 = A2_tfr
6117 { 1023, 2, 1, 4, 80, 0, 0, 190, HexagonImpOpBase + 0, 0, 0x2bULL }, // Inst #1023 = A2_sxtw
6118 { 1022, 2, 1, 4, 3, 0, 0, 157, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x8000ULL }, // Inst #1022 = A2_sxth
6119 { 1021, 2, 1, 4, 3, 0, 0, 157, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x8000ULL }, // Inst #1021 = A2_sxtb
6120 { 1020, 2, 1, 4, 80, 0, 0, 157, HexagonImpOpBase + 0, 0, 0x802bULL }, // Inst #1020 = A2_swiz
6121 { 1019, 3, 1, 4, 79, 0, 1, 202, HexagonImpOpBase + 63, 0, 0x80000000008001ULL }, // Inst #1019 = A2_svsubuhs
6122 { 1018, 3, 1, 4, 79, 0, 1, 202, HexagonImpOpBase + 63, 0, 0x80000000008001ULL }, // Inst #1018 = A2_svsubhs
6123 { 1017, 3, 1, 4, 6, 0, 0, 202, HexagonImpOpBase + 0, 0, 0x8001ULL }, // Inst #1017 = A2_svsubh
6124 { 1016, 3, 1, 4, 82, 0, 0, 202, HexagonImpOpBase + 0, 0, 0x80000000008001ULL }, // Inst #1016 = A2_svnavgh
6125 { 1015, 3, 1, 4, 83, 0, 0, 202, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x80000000008001ULL }, // Inst #1015 = A2_svavghs
6126 { 1014, 3, 1, 4, 82, 0, 0, 202, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x80000000008001ULL }, // Inst #1014 = A2_svavgh
6127 { 1013, 3, 1, 4, 79, 0, 1, 202, HexagonImpOpBase + 63, 0|(1ULL<<MCID::Commutable), 0x80000000008001ULL }, // Inst #1013 = A2_svadduhs
6128 { 1012, 3, 1, 4, 79, 0, 1, 202, HexagonImpOpBase + 63, 0|(1ULL<<MCID::Commutable), 0x80000000008001ULL }, // Inst #1012 = A2_svaddhs
6129 { 1011, 3, 1, 4, 6, 0, 0, 202, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x8001ULL }, // Inst #1011 = A2_svaddh
6130 { 1010, 3, 1, 4, 79, 0, 1, 202, HexagonImpOpBase + 63, 0, 0x80000000008001ULL }, // Inst #1010 = A2_subsat
6131 { 1009, 3, 1, 4, 6, 0, 0, 510, HexagonImpOpBase + 0, 0, 0x152808000ULL }, // Inst #1009 = A2_subri
6132 { 1008, 3, 1, 4, 8, 0, 0, 169, HexagonImpOpBase + 0, 0, 0x3ULL }, // Inst #1008 = A2_subp
6133 { 1007, 3, 1, 4, 77, 0, 1, 202, HexagonImpOpBase + 63, 0, 0x80000000008003ULL }, // Inst #1007 = A2_subh_l16_sat_ll
6134 { 1006, 3, 1, 4, 77, 0, 1, 202, HexagonImpOpBase + 63, 0, 0x80000000008003ULL }, // Inst #1006 = A2_subh_l16_sat_hl
6135 { 1005, 3, 1, 4, 78, 0, 0, 202, HexagonImpOpBase + 0, 0, 0x80000000008003ULL }, // Inst #1005 = A2_subh_l16_ll
6136 { 1004, 3, 1, 4, 78, 0, 0, 202, HexagonImpOpBase + 0, 0, 0x80000000008003ULL }, // Inst #1004 = A2_subh_l16_hl
6137 { 1003, 3, 1, 4, 77, 0, 1, 202, HexagonImpOpBase + 63, 0, 0x80000000008003ULL }, // Inst #1003 = A2_subh_h16_sat_ll
6138 { 1002, 3, 1, 4, 77, 0, 1, 202, HexagonImpOpBase + 63, 0, 0x80000000008003ULL }, // Inst #1002 = A2_subh_h16_sat_lh
6139 { 1001, 3, 1, 4, 77, 0, 1, 202, HexagonImpOpBase + 63, 0, 0x80000000008003ULL }, // Inst #1001 = A2_subh_h16_sat_hl
6140 { 1000, 3, 1, 4, 77, 0, 1, 202, HexagonImpOpBase + 63, 0, 0x80000000008003ULL }, // Inst #1000 = A2_subh_h16_sat_hh
6141 { 999, 3, 1, 4, 1, 0, 0, 202, HexagonImpOpBase + 0, 0, 0x80000000008003ULL }, // Inst #999 = A2_subh_h16_ll
6142 { 998, 3, 1, 4, 1, 0, 0, 202, HexagonImpOpBase + 0, 0, 0x80000000008003ULL }, // Inst #998 = A2_subh_h16_lh
6143 { 997, 3, 1, 4, 1, 0, 0, 202, HexagonImpOpBase + 0, 0, 0x80000000008003ULL }, // Inst #997 = A2_subh_h16_hl
6144 { 996, 3, 1, 4, 1, 0, 0, 202, HexagonImpOpBase + 0, 0, 0x80000000008003ULL }, // Inst #996 = A2_subh_h16_hh
6145 { 995, 3, 1, 4, 6, 0, 0, 202, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x8001ULL }, // Inst #995 = A2_sub
6146 { 994, 2, 1, 4, 80, 0, 1, 157, HexagonImpOpBase + 63, 0, 0x802bULL }, // Inst #994 = A2_satuh
6147 { 993, 2, 1, 4, 80, 0, 1, 157, HexagonImpOpBase + 63, 0, 0x802bULL }, // Inst #993 = A2_satub
6148 { 992, 2, 1, 4, 80, 0, 1, 157, HexagonImpOpBase + 63, 0, 0x802bULL }, // Inst #992 = A2_sath
6149 { 991, 2, 1, 4, 80, 0, 1, 157, HexagonImpOpBase + 63, 0, 0x802bULL }, // Inst #991 = A2_satb
6150 { 990, 2, 1, 4, 80, 0, 1, 307, HexagonImpOpBase + 63, 0, 0x802bULL }, // Inst #990 = A2_sat
6151 { 989, 2, 1, 4, 76, 0, 1, 307, HexagonImpOpBase + 63, 0, 0x8000000000802bULL }, // Inst #989 = A2_roundsat
6152 { 988, 4, 1, 4, 5, 0, 0, 522, HexagonImpOpBase + 0, 0, 0x9401ULL }, // Inst #988 = A2_pxortnew
6153 { 987, 4, 1, 4, 4, 0, 0, 522, HexagonImpOpBase + 0, 0, 0x8401ULL }, // Inst #987 = A2_pxort
6154 { 986, 4, 1, 4, 5, 0, 0, 522, HexagonImpOpBase + 0, 0, 0x9c01ULL }, // Inst #986 = A2_pxorfnew
6155 { 985, 4, 1, 4, 4, 0, 0, 522, HexagonImpOpBase + 0, 0, 0x8c01ULL }, // Inst #985 = A2_pxorf
6156 { 984, 4, 1, 4, 5, 0, 0, 522, HexagonImpOpBase + 0, 0, 0x9401ULL }, // Inst #984 = A2_psubtnew
6157 { 983, 4, 1, 4, 4, 0, 0, 522, HexagonImpOpBase + 0, 0, 0x8401ULL }, // Inst #983 = A2_psubt
6158 { 982, 4, 1, 4, 5, 0, 0, 522, HexagonImpOpBase + 0, 0, 0x9c01ULL }, // Inst #982 = A2_psubfnew
6159 { 981, 4, 1, 4, 4, 0, 0, 522, HexagonImpOpBase + 0, 0, 0x8c01ULL }, // Inst #981 = A2_psubf
6160 { 980, 4, 1, 4, 5, 0, 0, 522, HexagonImpOpBase + 0, 0, 0x9401ULL }, // Inst #980 = A2_portnew
6161 { 979, 4, 1, 4, 4, 0, 0, 522, HexagonImpOpBase + 0, 0, 0x8401ULL }, // Inst #979 = A2_port
6162 { 978, 4, 1, 4, 5, 0, 0, 522, HexagonImpOpBase + 0, 0, 0x9c01ULL }, // Inst #978 = A2_porfnew
6163 { 977, 4, 1, 4, 4, 0, 0, 522, HexagonImpOpBase + 0, 0, 0x8c01ULL }, // Inst #977 = A2_porf
6164 { 976, 4, 1, 4, 5, 0, 0, 522, HexagonImpOpBase + 0, 0, 0x9401ULL }, // Inst #976 = A2_pandtnew
6165 { 975, 4, 1, 4, 4, 0, 0, 522, HexagonImpOpBase + 0, 0, 0x8401ULL }, // Inst #975 = A2_pandt
6166 { 974, 4, 1, 4, 5, 0, 0, 522, HexagonImpOpBase + 0, 0, 0x9c01ULL }, // Inst #974 = A2_pandfnew
6167 { 973, 4, 1, 4, 4, 0, 0, 522, HexagonImpOpBase + 0, 0, 0x8c01ULL }, // Inst #973 = A2_pandf
6168 { 972, 4, 1, 4, 5, 0, 0, 522, HexagonImpOpBase + 0, 0, 0x9401ULL }, // Inst #972 = A2_paddtnew
6169 { 971, 4, 1, 4, 4, 0, 0, 522, HexagonImpOpBase + 0, 0, 0x8401ULL }, // Inst #971 = A2_paddt
6170 { 970, 4, 1, 4, 5, 0, 0, 526, HexagonImpOpBase + 0, 0, 0x116809400ULL }, // Inst #970 = A2_padditnew
6171 { 969, 4, 1, 4, 4, 0, 0, 526, HexagonImpOpBase + 0, 0, 0x116808400ULL }, // Inst #969 = A2_paddit
6172 { 968, 4, 1, 4, 5, 0, 0, 526, HexagonImpOpBase + 0, 0, 0x116809c00ULL }, // Inst #968 = A2_paddifnew
6173 { 967, 4, 1, 4, 4, 0, 0, 526, HexagonImpOpBase + 0, 0, 0x116808c00ULL }, // Inst #967 = A2_paddif
6174 { 966, 4, 1, 4, 5, 0, 0, 522, HexagonImpOpBase + 0, 0, 0x9c01ULL }, // Inst #966 = A2_paddfnew
6175 { 965, 4, 1, 4, 4, 0, 0, 522, HexagonImpOpBase + 0, 0, 0x8c01ULL }, // Inst #965 = A2_paddf
6176 { 964, 3, 1, 4, 8, 0, 0, 169, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x3ULL }, // Inst #964 = A2_orp
6177 { 963, 3, 1, 4, 6, 0, 0, 199, HexagonImpOpBase + 0, 0, 0x154808000ULL }, // Inst #963 = A2_orir
6178 { 962, 3, 1, 4, 6, 0, 0, 202, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x8001ULL }, // Inst #962 = A2_or
6179 { 961, 2, 1, 4, 80, 0, 0, 162, HexagonImpOpBase + 0, 0, 0x2bULL }, // Inst #961 = A2_notp
6180 { 960, 0, 0, 4, 81, 0, 0, 1, HexagonImpOpBase + 0, 0, 0x0ULL }, // Inst #960 = A2_nop
6181 { 959, 2, 1, 4, 76, 0, 1, 157, HexagonImpOpBase + 63, 0, 0x8000000000802bULL }, // Inst #959 = A2_negsat
6182 { 958, 2, 1, 4, 80, 0, 0, 162, HexagonImpOpBase + 0, 0, 0x2bULL }, // Inst #958 = A2_negp
6183 { 957, 3, 1, 4, 77, 0, 0, 169, HexagonImpOpBase + 0, 0, 0x80000000000003ULL }, // Inst #957 = A2_minup
6184 { 956, 3, 1, 4, 77, 0, 0, 202, HexagonImpOpBase + 0, 0, 0x80000000008003ULL }, // Inst #956 = A2_minu
6185 { 955, 3, 1, 4, 77, 0, 0, 169, HexagonImpOpBase + 0, 0, 0x80000000000003ULL }, // Inst #955 = A2_minp
6186 { 954, 3, 1, 4, 77, 0, 0, 202, HexagonImpOpBase + 0, 0, 0x80000000008003ULL }, // Inst #954 = A2_min
6187 { 953, 3, 1, 4, 77, 0, 0, 169, HexagonImpOpBase + 0, 0, 0x80000000000003ULL }, // Inst #953 = A2_maxup
6188 { 952, 3, 1, 4, 77, 0, 0, 202, HexagonImpOpBase + 0, 0, 0x80000000008003ULL }, // Inst #952 = A2_maxu
6189 { 951, 3, 1, 4, 77, 0, 0, 169, HexagonImpOpBase + 0, 0, 0x80000000000003ULL }, // Inst #951 = A2_maxp
6190 { 950, 3, 1, 4, 77, 0, 0, 202, HexagonImpOpBase + 0, 0, 0x80000000008003ULL }, // Inst #950 = A2_max
6191 { 949, 3, 1, 4, 6, 0, 0, 519, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x1ULL }, // Inst #949 = A2_combinew
6192 { 948, 3, 1, 4, 6, 0, 0, 495, HexagonImpOpBase + 0, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x112800000ULL }, // Inst #948 = A2_combineii
6193 { 947, 3, 1, 4, 6, 0, 0, 202, HexagonImpOpBase + 0, 0, 0x8001ULL }, // Inst #947 = A2_combine_ll
6194 { 946, 3, 1, 4, 6, 0, 0, 202, HexagonImpOpBase + 0, 0, 0x8001ULL }, // Inst #946 = A2_combine_lh
6195 { 945, 3, 1, 4, 6, 0, 0, 202, HexagonImpOpBase + 0, 0, 0x8001ULL }, // Inst #945 = A2_combine_hl
6196 { 944, 3, 1, 4, 6, 0, 0, 202, HexagonImpOpBase + 0, 0, 0x8001ULL }, // Inst #944 = A2_combine_hh
6197 { 943, 2, 1, 4, 3, 0, 0, 157, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x8000ULL }, // Inst #943 = A2_asrh
6198 { 942, 2, 1, 4, 3, 0, 0, 157, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Predicable), 0x8000ULL }, // Inst #942 = A2_aslh
6199 { 941, 3, 1, 4, 8, 0, 0, 169, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x3ULL }, // Inst #941 = A2_andp
6200 { 940, 3, 1, 4, 6, 0, 0, 199, HexagonImpOpBase + 0, 0, 0x154808000ULL }, // Inst #940 = A2_andir
6201 { 939, 3, 1, 4, 6, 0, 0, 202, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x8001ULL }, // Inst #939 = A2_and
6202 { 938, 3, 1, 4, 1, 0, 0, 169, HexagonImpOpBase + 0, 0, 0x80000000000003ULL }, // Inst #938 = A2_addspl
6203 { 937, 3, 1, 4, 1, 0, 0, 169, HexagonImpOpBase + 0, 0, 0x80000000000003ULL }, // Inst #937 = A2_addsph
6204 { 936, 3, 1, 4, 79, 0, 1, 202, HexagonImpOpBase + 63, 0|(1ULL<<MCID::Commutable), 0x80000000008001ULL }, // Inst #936 = A2_addsat
6205 { 935, 3, 1, 4, 77, 0, 1, 169, HexagonImpOpBase + 63, 0|(1ULL<<MCID::Commutable), 0x80000000000003ULL }, // Inst #935 = A2_addpsat
6206 { 934, 3, 1, 4, 8, 0, 0, 169, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Commutable), 0x3ULL }, // Inst #934 = A2_addp
6207 { 933, 3, 1, 4, 6, 0, 0, 199, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable), 0x214808002ULL }, // Inst #933 = A2_addi
6208 { 932, 3, 1, 4, 77, 0, 1, 202, HexagonImpOpBase + 63, 0, 0x80000000008003ULL }, // Inst #932 = A2_addh_l16_sat_ll
6209 { 931, 3, 1, 4, 77, 0, 1, 202, HexagonImpOpBase + 63, 0, 0x80000000008003ULL }, // Inst #931 = A2_addh_l16_sat_hl
6210 { 930, 3, 1, 4, 78, 0, 0, 202, HexagonImpOpBase + 0, 0, 0x80000000008003ULL }, // Inst #930 = A2_addh_l16_ll
6211 { 929, 3, 1, 4, 78, 0, 0, 202, HexagonImpOpBase + 0, 0, 0x80000000008003ULL }, // Inst #929 = A2_addh_l16_hl
6212 { 928, 3, 1, 4, 77, 0, 1, 202, HexagonImpOpBase + 63, 0, 0x80000000008003ULL }, // Inst #928 = A2_addh_h16_sat_ll
6213 { 927, 3, 1, 4, 77, 0, 1, 202, HexagonImpOpBase + 63, 0, 0x80000000008003ULL }, // Inst #927 = A2_addh_h16_sat_lh
6214 { 926, 3, 1, 4, 77, 0, 1, 202, HexagonImpOpBase + 63, 0, 0x80000000008003ULL }, // Inst #926 = A2_addh_h16_sat_hl
6215 { 925, 3, 1, 4, 77, 0, 1, 202, HexagonImpOpBase + 63, 0, 0x80000000008003ULL }, // Inst #925 = A2_addh_h16_sat_hh
6216 { 924, 3, 1, 4, 1, 0, 0, 202, HexagonImpOpBase + 0, 0, 0x80000000008003ULL }, // Inst #924 = A2_addh_h16_ll
6217 { 923, 3, 1, 4, 1, 0, 0, 202, HexagonImpOpBase + 0, 0, 0x80000000008003ULL }, // Inst #923 = A2_addh_h16_lh
6218 { 922, 3, 1, 4, 1, 0, 0, 202, HexagonImpOpBase + 0, 0, 0x80000000008003ULL }, // Inst #922 = A2_addh_h16_hl
6219 { 921, 3, 1, 4, 1, 0, 0, 202, HexagonImpOpBase + 0, 0, 0x80000000008003ULL }, // Inst #921 = A2_addh_h16_hh
6220 { 920, 3, 1, 4, 6, 0, 0, 202, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x8001ULL }, // Inst #920 = A2_add
6221 { 919, 2, 1, 4, 76, 0, 1, 157, HexagonImpOpBase + 63, 0, 0x8000000000802bULL }, // Inst #919 = A2_abssat
6222 { 918, 2, 1, 4, 76, 0, 0, 162, HexagonImpOpBase + 0, 0, 0x8000000000002bULL }, // Inst #918 = A2_absp
6223 { 917, 2, 1, 4, 76, 0, 0, 157, HexagonImpOpBase + 0, 0, 0x8000000000802bULL }, // Inst #917 = A2_abs
6224 { 916, 3, 0, 4, 75, 0, 0, 516, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x1b0114800030ULL }, // Inst #916 = dup_S4_storeiri_io
6225 { 915, 3, 0, 4, 75, 0, 0, 516, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0xb0114800030ULL }, // Inst #915 = dup_S4_storeirb_io
6226 { 914, 3, 0, 4, 74, 0, 0, 510, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x1b09b2800029ULL }, // Inst #914 = dup_S2_storeri_io
6227 { 913, 3, 0, 4, 74, 0, 0, 510, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x130592800029ULL }, // Inst #913 = dup_S2_storerh_io
6228 { 912, 3, 0, 4, 74, 0, 0, 513, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x230dd2800029ULL }, // Inst #912 = dup_S2_storerd_io
6229 { 911, 3, 0, 4, 74, 0, 0, 510, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0xb0172800029ULL }, // Inst #911 = dup_S2_storerb_io
6230 { 910, 3, 1, 4, 73, 4, 1, 507, HexagonImpOpBase + 58, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x230000008029ULL }, // Inst #910 = dup_S2_allocframe
6231 { 909, 3, 1, 4, 72, 0, 0, 199, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x130594808024ULL }, // Inst #909 = dup_L2_loadruh_io
6232 { 908, 3, 1, 4, 72, 0, 0, 199, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0xb0174808024ULL }, // Inst #908 = dup_L2_loadrub_io
6233 { 907, 3, 1, 4, 72, 0, 0, 199, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x1b09b4808024ULL }, // Inst #907 = dup_L2_loadri_io
6234 { 906, 3, 1, 4, 72, 0, 0, 199, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x130594808024ULL }, // Inst #906 = dup_L2_loadrh_io
6235 { 905, 3, 1, 4, 72, 0, 0, 501, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x230dd4800024ULL }, // Inst #905 = dup_L2_loadrd_io
6236 { 904, 3, 1, 4, 72, 0, 0, 199, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0xb0174808024ULL }, // Inst #904 = dup_L2_loadrb_io
6237 { 903, 2, 1, 4, 71, 1, 1, 190, HexagonImpOpBase + 56, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x200000000024ULL }, // Inst #903 = dup_L2_deallocframe
6238 { 902, 3, 1, 4, 68, 0, 0, 175, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x154800000ULL }, // Inst #902 = dup_C2_cmpeqi
6239 { 901, 3, 1, 4, 70, 0, 0, 504, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x194809400ULL }, // Inst #901 = dup_C2_cmovenewit
6240 { 900, 3, 1, 4, 70, 0, 0, 504, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x194809c00ULL }, // Inst #900 = dup_C2_cmovenewif
6241 { 899, 3, 1, 4, 68, 0, 0, 504, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x194808400ULL }, // Inst #899 = dup_C2_cmoveit
6242 { 898, 3, 1, 4, 68, 0, 0, 504, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x194808c00ULL }, // Inst #898 = dup_C2_cmoveif
6243 { 897, 3, 1, 4, 68, 0, 0, 501, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x114800000ULL }, // Inst #897 = dup_A4_combineri
6244 { 896, 3, 1, 4, 68, 0, 0, 498, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x112800000ULL }, // Inst #896 = dup_A4_combineir
6245 { 895, 3, 1, 4, 68, 0, 0, 495, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0xc4800000ULL }, // Inst #895 = dup_A4_combineii
6246 { 894, 2, 1, 4, 69, 0, 0, 157, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x8000ULL }, // Inst #894 = dup_A2_zxth
6247 { 893, 2, 1, 4, 2, 0, 0, 157, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x8026ULL }, // Inst #893 = dup_A2_zxtb
6248 { 892, 2, 1, 4, 69, 0, 0, 155, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x212808000ULL }, // Inst #892 = dup_A2_tfrsi
6249 { 891, 2, 1, 4, 69, 0, 0, 157, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x8000ULL }, // Inst #891 = dup_A2_tfr
6250 { 890, 2, 1, 4, 69, 0, 0, 157, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x8000ULL }, // Inst #890 = dup_A2_sxth
6251 { 889, 2, 1, 4, 69, 0, 0, 157, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x8000ULL }, // Inst #889 = dup_A2_sxtb
6252 { 888, 3, 1, 4, 68, 0, 0, 495, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x112800000ULL }, // Inst #888 = dup_A2_combineii
6253 { 887, 3, 1, 4, 68, 0, 0, 199, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x154808000ULL }, // Inst #887 = dup_A2_andir
6254 { 886, 3, 1, 4, 68, 0, 0, 199, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x214808002ULL }, // Inst #886 = dup_A2_addi
6255 { 885, 3, 1, 4, 68, 0, 0, 202, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x8001ULL }, // Inst #885 = dup_A2_add
6256 { 884, 0, 0, 4, 2, 0, 0, 1, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #884 = Y2_k1unlock_map
6257 { 883, 0, 0, 4, 2, 0, 0, 1, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #883 = Y2_k1lock_map
6258 { 882, 1, 0, 4, 67, 0, 0, 272, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x26ULL }, // Inst #882 = Y2_dcfetch
6259 { 881, 2, 1, 4, 66, 0, 0, 493, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x8026ULL }, // Inst #881 = Y2_crswap_old
6260 { 880, 2, 0, 4, 2, 0, 0, 185, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000000026ULL }, // Inst #880 = V6_zldp0
6261 { 879, 1, 0, 4, 2, 0, 0, 272, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000000026ULL }, // Inst #879 = V6_zld0
6262 { 878, 2, 1, 4, 2, 0, 0, 465, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #878 = V6_vzh_alt
6263 { 877, 2, 1, 4, 2, 0, 0, 465, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #877 = V6_vzb_alt
6264 { 876, 2, 1, 4, 2, 0, 0, 465, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #876 = V6_vunpackuh_alt
6265 { 875, 2, 1, 4, 2, 0, 0, 465, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #875 = V6_vunpackub_alt
6266 { 874, 3, 1, 4, 2, 0, 0, 490, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #874 = V6_vunpackoh_alt
6267 { 873, 3, 1, 4, 2, 0, 0, 490, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #873 = V6_vunpackob_alt
6268 { 872, 2, 1, 4, 2, 0, 0, 465, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #872 = V6_vunpackh_alt
6269 { 871, 2, 1, 4, 2, 0, 0, 465, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #871 = V6_vunpackb_alt
6270 { 870, 5, 2, 4, 2, 0, 0, 485, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x80c000000008026ULL }, // Inst #870 = V6_vtran2x2_map
6271 { 869, 3, 1, 4, 2, 0, 0, 406, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #869 = V6_vtmpyhb_alt
6272 { 868, 4, 1, 4, 2, 0, 0, 402, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #868 = V6_vtmpyhb_acc_alt
6273 { 867, 3, 1, 4, 2, 0, 0, 406, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #867 = V6_vtmpybus_alt
6274 { 866, 4, 1, 4, 2, 0, 0, 402, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #866 = V6_vtmpybus_acc_alt
6275 { 865, 3, 1, 4, 2, 0, 0, 406, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #865 = V6_vtmpyb_alt
6276 { 864, 4, 1, 4, 2, 0, 0, 402, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #864 = V6_vtmpyb_acc_alt
6277 { 863, 3, 1, 4, 2, 0, 0, 364, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #863 = V6_vsubwsat_dv_alt
6278 { 862, 3, 1, 4, 2, 0, 0, 361, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #862 = V6_vsubwsat_alt
6279 { 861, 4, 1, 4, 2, 0, 0, 367, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #861 = V6_vsubwq_alt
6280 { 860, 4, 1, 4, 2, 0, 0, 367, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #860 = V6_vsubwnq_alt
6281 { 859, 3, 1, 4, 2, 0, 0, 364, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #859 = V6_vsubw_dv_alt
6282 { 858, 3, 1, 4, 2, 0, 0, 361, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #858 = V6_vsubw_alt
6283 { 857, 3, 1, 4, 2, 0, 0, 364, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #857 = V6_vsubuwsat_dv_alt
6284 { 856, 3, 1, 4, 2, 0, 0, 361, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #856 = V6_vsubuwsat_alt
6285 { 855, 3, 1, 4, 2, 0, 0, 375, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #855 = V6_vsubuhw_alt
6286 { 854, 3, 1, 4, 2, 0, 0, 364, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #854 = V6_vsubuhsat_dv_alt
6287 { 853, 3, 1, 4, 2, 0, 0, 361, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #853 = V6_vsubuhsat_alt
6288 { 852, 3, 1, 4, 2, 0, 0, 364, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #852 = V6_vsububsat_dv_alt
6289 { 851, 3, 1, 4, 2, 0, 0, 361, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #851 = V6_vsububsat_alt
6290 { 850, 3, 1, 4, 2, 0, 0, 375, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #850 = V6_vsububh_alt
6291 { 849, 3, 1, 4, 2, 0, 0, 375, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #849 = V6_vsubhw_alt
6292 { 848, 3, 1, 4, 2, 0, 0, 364, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #848 = V6_vsubhsat_dv_alt
6293 { 847, 3, 1, 4, 2, 0, 0, 361, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #847 = V6_vsubhsat_alt
6294 { 846, 4, 1, 4, 2, 0, 0, 367, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #846 = V6_vsubhq_alt
6295 { 845, 4, 1, 4, 2, 0, 0, 367, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #845 = V6_vsubhnq_alt
6296 { 844, 3, 1, 4, 2, 0, 0, 364, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #844 = V6_vsubh_dv_alt
6297 { 843, 3, 1, 4, 2, 0, 0, 361, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #843 = V6_vsubh_alt
6298 { 842, 3, 1, 4, 2, 0, 0, 364, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #842 = V6_vsubbsat_dv_alt
6299 { 841, 3, 1, 4, 2, 0, 0, 361, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #841 = V6_vsubbsat_alt
6300 { 840, 4, 1, 4, 2, 0, 0, 367, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #840 = V6_vsubbq_alt
6301 { 839, 4, 1, 4, 2, 0, 0, 367, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #839 = V6_vsubbnq_alt
6302 { 838, 3, 1, 4, 2, 0, 0, 364, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #838 = V6_vsubb_dv_alt
6303 { 837, 3, 1, 4, 2, 0, 0, 361, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #837 = V6_vsubb_alt
6304 { 836, 3, 1, 4, 2, 0, 0, 361, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #836 = V6_vshufoh_alt
6305 { 835, 3, 1, 4, 2, 0, 0, 375, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #835 = V6_vshufoeh_alt
6306 { 834, 3, 1, 4, 2, 0, 0, 375, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #834 = V6_vshufoeb_alt
6307 { 833, 3, 1, 4, 2, 0, 0, 361, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #833 = V6_vshuffob_alt
6308 { 832, 2, 1, 4, 2, 0, 0, 359, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #832 = V6_vshuffh_alt
6309 { 831, 3, 1, 4, 2, 0, 0, 361, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #831 = V6_vshuffeb_alt
6310 { 830, 2, 1, 4, 2, 0, 0, 359, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #830 = V6_vshuffb_alt
6311 { 829, 3, 1, 4, 2, 0, 0, 361, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #829 = V6_vshufeh_alt
6312 { 828, 2, 1, 4, 2, 0, 0, 465, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #828 = V6_vsh_alt
6313 { 827, 5, 0, 4, 2, 0, 0, 471, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000000026ULL }, // Inst #827 = V6_vscattermwq_alt
6314 { 826, 5, 0, 4, 2, 0, 0, 480, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000000026ULL }, // Inst #826 = V6_vscattermwhq_alt
6315 { 825, 4, 0, 4, 2, 0, 0, 476, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000000026ULL }, // Inst #825 = V6_vscattermwh_alt
6316 { 824, 4, 0, 4, 2, 0, 0, 476, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x840000000000026ULL }, // Inst #824 = V6_vscattermwh_add_alt
6317 { 823, 4, 0, 4, 2, 0, 0, 467, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000000026ULL }, // Inst #823 = V6_vscattermw_alt
6318 { 822, 4, 0, 4, 2, 0, 0, 467, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x840000000000026ULL }, // Inst #822 = V6_vscattermw_add_alt
6319 { 821, 5, 0, 4, 2, 0, 0, 471, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000000026ULL }, // Inst #821 = V6_vscattermhq_alt
6320 { 820, 4, 0, 4, 2, 0, 0, 467, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000000026ULL }, // Inst #820 = V6_vscattermh_alt
6321 { 819, 4, 0, 4, 2, 0, 0, 467, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x840000000000026ULL }, // Inst #819 = V6_vscattermh_add_alt
6322 { 818, 2, 1, 4, 2, 0, 0, 465, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #818 = V6_vsb_alt
6323 { 817, 3, 1, 4, 2, 0, 0, 361, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #817 = V6_vsatwh_alt
6324 { 816, 3, 1, 4, 2, 0, 0, 361, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #816 = V6_vsatuwuh_alt
6325 { 815, 3, 1, 4, 2, 0, 0, 361, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #815 = V6_vsathub_alt
6326 { 814, 4, 1, 4, 2, 0, 0, 461, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #814 = V6_vrsadubi_alt
6327 { 813, 5, 1, 4, 2, 0, 0, 456, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #813 = V6_vrsadubi_acc_alt
6328 { 812, 3, 1, 4, 2, 0, 0, 361, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #812 = V6_vroundwuh_alt
6329 { 811, 3, 1, 4, 2, 0, 0, 361, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #811 = V6_vroundwh_alt
6330 { 810, 3, 1, 4, 2, 0, 0, 361, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #810 = V6_vrounduwuh_alt
6331 { 809, 3, 1, 4, 2, 0, 0, 361, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #809 = V6_vrounduhub_alt
6332 { 808, 3, 1, 4, 2, 0, 0, 361, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #808 = V6_vroundhub_alt
6333 { 807, 3, 1, 4, 2, 0, 0, 361, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #807 = V6_vroundhb_alt
6334 { 806, 3, 1, 4, 2, 0, 0, 361, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #806 = V6_vrotr_alt
6335 { 805, 3, 1, 4, 2, 0, 0, 361, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #805 = V6_vrmpyubv_alt
6336 { 804, 4, 1, 4, 2, 0, 0, 416, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #804 = V6_vrmpyubv_acc_alt
6337 { 803, 4, 1, 4, 2, 0, 0, 461, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #803 = V6_vrmpyubi_alt
6338 { 802, 5, 1, 4, 2, 0, 0, 456, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #802 = V6_vrmpyubi_acc_alt
6339 { 801, 3, 1, 4, 2, 0, 0, 453, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #801 = V6_vrmpyub_rtt_alt
6340 { 800, 4, 1, 4, 2, 0, 0, 449, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #800 = V6_vrmpyub_rtt_acc_alt
6341 { 799, 3, 1, 4, 2, 0, 0, 396, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #799 = V6_vrmpyub_alt
6342 { 798, 4, 1, 4, 2, 0, 0, 392, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #798 = V6_vrmpyub_acc_alt
6343 { 797, 3, 1, 4, 2, 0, 0, 361, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #797 = V6_vrmpybv_alt
6344 { 796, 4, 1, 4, 2, 0, 0, 416, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #796 = V6_vrmpybv_acc_alt
6345 { 795, 3, 1, 4, 2, 0, 0, 361, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #795 = V6_vrmpybusv_alt
6346 { 794, 4, 1, 4, 2, 0, 0, 416, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #794 = V6_vrmpybusv_acc_alt
6347 { 793, 4, 1, 4, 2, 0, 0, 461, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #793 = V6_vrmpybusi_alt
6348 { 792, 5, 1, 4, 2, 0, 0, 456, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #792 = V6_vrmpybusi_acc_alt
6349 { 791, 3, 1, 4, 2, 0, 0, 396, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #791 = V6_vrmpybus_alt
6350 { 790, 4, 1, 4, 2, 0, 0, 392, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #790 = V6_vrmpybus_acc_alt
6351 { 789, 3, 1, 4, 2, 0, 0, 453, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #789 = V6_vrmpybub_rtt_alt
6352 { 788, 4, 1, 4, 2, 0, 0, 449, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #788 = V6_vrmpybub_rtt_acc_alt
6353 { 787, 2, 1, 4, 2, 0, 0, 359, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #787 = V6_vpopcounth_alt
6354 { 786, 3, 1, 4, 2, 0, 0, 361, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #786 = V6_vpackwuh_sat_alt
6355 { 785, 3, 1, 4, 2, 0, 0, 361, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #785 = V6_vpackwh_sat_alt
6356 { 784, 3, 1, 4, 2, 0, 0, 361, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #784 = V6_vpackoh_alt
6357 { 783, 3, 1, 4, 2, 0, 0, 361, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #783 = V6_vpackob_alt
6358 { 782, 3, 1, 4, 2, 0, 0, 361, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #782 = V6_vpackhub_sat_alt
6359 { 781, 3, 1, 4, 2, 0, 0, 361, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #781 = V6_vpackhb_sat_alt
6360 { 780, 3, 1, 4, 2, 0, 0, 361, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #780 = V6_vpackeh_alt
6361 { 779, 3, 1, 4, 2, 0, 0, 361, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #779 = V6_vpackeb_alt
6362 { 778, 2, 1, 4, 2, 0, 0, 359, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #778 = V6_vnormamtw_alt
6363 { 777, 2, 1, 4, 2, 0, 0, 359, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #777 = V6_vnormamth_alt
6364 { 776, 3, 1, 4, 2, 0, 0, 361, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #776 = V6_vnavgw_alt
6365 { 775, 3, 1, 4, 2, 0, 0, 361, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #775 = V6_vnavgub_alt
6366 { 774, 3, 1, 4, 2, 0, 0, 361, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #774 = V6_vnavgh_alt
6367 { 773, 3, 1, 4, 2, 0, 0, 361, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #773 = V6_vnavgb_alt
6368 { 772, 3, 1, 4, 2, 0, 0, 375, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #772 = V6_vmpyuhv_alt
6369 { 771, 4, 1, 4, 2, 0, 0, 371, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #771 = V6_vmpyuhv_acc_alt
6370 { 770, 3, 1, 4, 2, 0, 0, 446, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #770 = V6_vmpyuh_alt
6371 { 769, 4, 1, 4, 2, 0, 0, 442, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #769 = V6_vmpyuh_acc_alt
6372 { 768, 3, 1, 4, 2, 0, 0, 375, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #768 = V6_vmpyubv_alt
6373 { 767, 4, 1, 4, 2, 0, 0, 371, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #767 = V6_vmpyubv_acc_alt
6374 { 766, 3, 1, 4, 2, 0, 0, 446, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #766 = V6_vmpyub_alt
6375 { 765, 4, 1, 4, 2, 0, 0, 442, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #765 = V6_vmpyub_acc_alt
6376 { 764, 4, 1, 4, 2, 0, 0, 416, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #764 = V6_vmpyowh_sacc_alt
6377 { 763, 4, 1, 4, 2, 0, 0, 416, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #763 = V6_vmpyowh_rnd_sacc_alt
6378 { 762, 3, 1, 4, 2, 0, 0, 361, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #762 = V6_vmpyowh_rnd_alt
6379 { 761, 3, 1, 4, 2, 0, 0, 361, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #761 = V6_vmpyowh_alt
6380 { 760, 3, 1, 4, 2, 0, 0, 396, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #760 = V6_vmpyiwub_alt
6381 { 759, 4, 1, 4, 2, 0, 0, 392, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #759 = V6_vmpyiwub_acc_alt
6382 { 758, 3, 1, 4, 2, 0, 0, 396, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #758 = V6_vmpyiwh_alt
6383 { 757, 4, 1, 4, 2, 0, 0, 392, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #757 = V6_vmpyiwh_acc_alt
6384 { 756, 3, 1, 4, 2, 0, 0, 396, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #756 = V6_vmpyiwb_alt
6385 { 755, 4, 1, 4, 2, 0, 0, 392, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #755 = V6_vmpyiwb_acc_alt
6386 { 754, 3, 1, 4, 2, 0, 0, 361, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #754 = V6_vmpyiowh_alt
6387 { 753, 3, 1, 4, 2, 0, 0, 396, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #753 = V6_vmpyihb_alt
6388 { 752, 4, 1, 4, 2, 0, 0, 392, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #752 = V6_vmpyihb_acc_alt
6389 { 751, 3, 1, 4, 2, 0, 0, 361, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #751 = V6_vmpyih_alt
6390 { 750, 4, 1, 4, 2, 0, 0, 416, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #750 = V6_vmpyih_acc_alt
6391 { 749, 3, 1, 4, 2, 0, 0, 361, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #749 = V6_vmpyiewuh_alt
6392 { 748, 4, 1, 4, 2, 0, 0, 416, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #748 = V6_vmpyiewuh_acc_alt
6393 { 747, 4, 1, 4, 2, 0, 0, 416, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #747 = V6_vmpyiewh_acc_alt
6394 { 746, 3, 1, 4, 2, 0, 0, 361, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #746 = V6_vmpyhvsrs_alt
6395 { 745, 3, 1, 4, 2, 0, 0, 375, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #745 = V6_vmpyhv_alt
6396 { 744, 4, 1, 4, 2, 0, 0, 371, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #744 = V6_vmpyhv_acc_alt
6397 { 743, 3, 1, 4, 2, 0, 0, 375, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #743 = V6_vmpyhus_alt
6398 { 742, 4, 1, 4, 2, 0, 0, 371, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #742 = V6_vmpyhus_acc_alt
6399 { 741, 3, 1, 4, 2, 0, 0, 396, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #741 = V6_vmpyhss_alt
6400 { 740, 3, 1, 4, 2, 0, 0, 396, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #740 = V6_vmpyhsrs_alt
6401 { 739, 4, 1, 4, 2, 0, 0, 442, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #739 = V6_vmpyhsat_acc_alt
6402 { 738, 3, 1, 4, 2, 0, 0, 446, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #738 = V6_vmpyh_alt
6403 { 737, 4, 1, 4, 2, 0, 0, 442, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #737 = V6_vmpyh_acc_alt
6404 { 736, 3, 1, 4, 2, 0, 0, 361, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #736 = V6_vmpyewuh_alt
6405 { 735, 3, 1, 4, 2, 0, 0, 375, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #735 = V6_vmpybv_alt
6406 { 734, 4, 1, 4, 2, 0, 0, 371, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #734 = V6_vmpybv_acc_alt
6407 { 733, 3, 1, 4, 2, 0, 0, 375, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #733 = V6_vmpybusv_alt
6408 { 732, 4, 1, 4, 2, 0, 0, 371, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #732 = V6_vmpybusv_acc_alt
6409 { 731, 3, 1, 4, 2, 0, 0, 446, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #731 = V6_vmpybus_alt
6410 { 730, 4, 1, 4, 2, 0, 0, 442, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #730 = V6_vmpybus_acc_alt
6411 { 729, 3, 1, 4, 2, 0, 0, 406, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #729 = V6_vmpauhb_alt
6412 { 728, 4, 1, 4, 2, 0, 0, 402, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #728 = V6_vmpauhb_acc_alt
6413 { 727, 3, 1, 4, 2, 0, 0, 406, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #727 = V6_vmpahb_alt
6414 { 726, 4, 1, 4, 2, 0, 0, 402, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #726 = V6_vmpahb_acc_alt
6415 { 725, 3, 1, 4, 2, 0, 0, 364, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #725 = V6_vmpabuuv_alt
6416 { 724, 3, 1, 4, 2, 0, 0, 406, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #724 = V6_vmpabuu_alt
6417 { 723, 4, 1, 4, 2, 0, 0, 402, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #723 = V6_vmpabuu_acc_alt
6418 { 722, 3, 1, 4, 2, 0, 0, 364, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #722 = V6_vmpabusv_alt
6419 { 721, 3, 1, 4, 2, 0, 0, 406, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #721 = V6_vmpabus_alt
6420 { 720, 4, 1, 4, 2, 0, 0, 402, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #720 = V6_vmpabus_acc_alt
6421 { 719, 3, 1, 4, 2, 0, 0, 361, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #719 = V6_vminw_alt
6422 { 718, 3, 1, 4, 2, 0, 0, 361, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #718 = V6_vminuh_alt
6423 { 717, 3, 1, 4, 2, 0, 0, 361, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #717 = V6_vminub_alt
6424 { 716, 3, 1, 4, 2, 0, 0, 361, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #716 = V6_vminh_alt
6425 { 715, 3, 1, 4, 2, 0, 0, 361, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #715 = V6_vminb_alt
6426 { 714, 3, 1, 4, 2, 0, 0, 361, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #714 = V6_vmaxw_alt
6427 { 713, 3, 1, 4, 2, 0, 0, 361, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #713 = V6_vmaxuh_alt
6428 { 712, 3, 1, 4, 2, 0, 0, 361, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #712 = V6_vmaxub_alt
6429 { 711, 3, 1, 4, 2, 0, 0, 361, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #711 = V6_vmaxh_alt
6430 { 710, 3, 1, 4, 2, 0, 0, 361, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #710 = V6_vmaxb_alt
6431 { 709, 3, 1, 4, 2, 0, 0, 361, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #709 = V6_vlsrwv_alt
6432 { 708, 3, 1, 4, 2, 0, 0, 396, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #708 = V6_vlsrw_alt
6433 { 707, 3, 1, 4, 2, 0, 0, 361, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #707 = V6_vlsrhv_alt
6434 { 706, 3, 1, 4, 2, 0, 0, 396, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #706 = V6_vlsrh_alt
6435 { 705, 6, 0, 4, 65, 0, 0, 425, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1b0000000007ULL }, // Inst #705 = V6_vgathermwq_pseudo
6436 { 704, 5, 0, 4, 65, 0, 0, 420, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1b0000000007ULL }, // Inst #704 = V6_vgathermw_pseudo
6437 { 703, 6, 0, 4, 65, 0, 0, 436, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x130000000007ULL }, // Inst #703 = V6_vgathermhwq_pseudo
6438 { 702, 5, 0, 4, 65, 0, 0, 431, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x130000000007ULL }, // Inst #702 = V6_vgathermhw_pseudo
6439 { 701, 6, 0, 4, 65, 0, 0, 425, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x130000000007ULL }, // Inst #701 = V6_vgathermhq_pseudo
6440 { 700, 5, 0, 4, 65, 0, 0, 420, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x130000000007ULL }, // Inst #700 = V6_vgathermh_pseudo
6441 { 699, 3, 1, 4, 2, 0, 0, 406, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #699 = V6_vdsaduh_alt
6442 { 698, 4, 1, 4, 2, 0, 0, 402, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #698 = V6_vdsaduh_acc_alt
6443 { 697, 3, 1, 4, 2, 0, 0, 361, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #697 = V6_vdmpyhvsat_alt
6444 { 696, 4, 1, 4, 2, 0, 0, 416, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #696 = V6_vdmpyhvsat_acc_alt
6445 { 695, 3, 1, 4, 2, 0, 0, 396, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #695 = V6_vdmpyhsusat_alt
6446 { 694, 4, 1, 4, 2, 0, 0, 392, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #694 = V6_vdmpyhsusat_acc_alt
6447 { 693, 3, 1, 4, 2, 0, 0, 413, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #693 = V6_vdmpyhsuisat_alt
6448 { 692, 4, 1, 4, 2, 0, 0, 409, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #692 = V6_vdmpyhsuisat_acc_alt
6449 { 691, 3, 1, 4, 2, 0, 0, 396, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #691 = V6_vdmpyhsat_alt
6450 { 690, 4, 1, 4, 2, 0, 0, 392, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #690 = V6_vdmpyhsat_acc_alt
6451 { 689, 3, 1, 4, 2, 0, 0, 413, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #689 = V6_vdmpyhisat_alt
6452 { 688, 4, 1, 4, 2, 0, 0, 409, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #688 = V6_vdmpyhisat_acc_alt
6453 { 687, 3, 1, 4, 2, 0, 0, 406, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #687 = V6_vdmpyhb_dv_alt
6454 { 686, 4, 1, 4, 2, 0, 0, 402, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #686 = V6_vdmpyhb_dv_acc_alt
6455 { 685, 3, 1, 4, 2, 0, 0, 396, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #685 = V6_vdmpyhb_alt
6456 { 684, 4, 1, 4, 2, 0, 0, 392, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #684 = V6_vdmpyhb_acc_alt
6457 { 683, 3, 1, 4, 2, 0, 0, 406, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #683 = V6_vdmpybus_dv_alt
6458 { 682, 4, 1, 4, 2, 0, 0, 402, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #682 = V6_vdmpybus_dv_acc_alt
6459 { 681, 3, 1, 4, 2, 0, 0, 396, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #681 = V6_vdmpybus_alt
6460 { 680, 4, 1, 4, 2, 0, 0, 392, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #680 = V6_vdmpybus_acc_alt
6461 { 679, 2, 1, 4, 2, 0, 0, 359, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #679 = V6_vdealh_alt
6462 { 678, 2, 1, 4, 2, 0, 0, 359, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #678 = V6_vdealb_alt
6463 { 677, 3, 1, 4, 2, 0, 0, 361, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #677 = V6_vdealb4w_alt
6464 { 676, 1, 1, 4, 64, 0, 0, 273, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #676 = V6_vdd0
6465 { 675, 1, 1, 4, 60, 0, 0, 401, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008010ULL }, // Inst #675 = V6_vd0
6466 { 674, 2, 1, 4, 2, 0, 0, 359, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #674 = V6_vcl0w_alt
6467 { 673, 2, 1, 4, 2, 0, 0, 359, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #673 = V6_vcl0h_alt
6468 { 672, 3, 1, 4, 2, 0, 0, 361, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #672 = V6_vavgwrnd_alt
6469 { 671, 3, 1, 4, 2, 0, 0, 361, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #671 = V6_vavgw_alt
6470 { 670, 3, 1, 4, 2, 0, 0, 361, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #670 = V6_vavguwrnd_alt
6471 { 669, 3, 1, 4, 2, 0, 0, 361, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #669 = V6_vavguw_alt
6472 { 668, 3, 1, 4, 2, 0, 0, 361, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #668 = V6_vavguhrnd_alt
6473 { 667, 3, 1, 4, 2, 0, 0, 361, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #667 = V6_vavguh_alt
6474 { 666, 3, 1, 4, 2, 0, 0, 361, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #666 = V6_vavgubrnd_alt
6475 { 665, 3, 1, 4, 2, 0, 0, 361, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #665 = V6_vavgub_alt
6476 { 664, 3, 1, 4, 2, 0, 0, 361, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #664 = V6_vavghrnd_alt
6477 { 663, 3, 1, 4, 2, 0, 0, 361, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #663 = V6_vavgh_alt
6478 { 662, 3, 1, 4, 2, 0, 0, 361, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #662 = V6_vavgbrnd_alt
6479 { 661, 3, 1, 4, 2, 0, 0, 361, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #661 = V6_vavgb_alt
6480 { 660, 2, 1, 4, 60, 0, 0, 399, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008011ULL }, // Inst #660 = V6_vassignp
6481 { 659, 3, 1, 4, 2, 0, 0, 361, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #659 = V6_vasrwv_alt
6482 { 658, 3, 1, 4, 2, 0, 0, 396, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #658 = V6_vasrw_alt
6483 { 657, 4, 1, 4, 2, 0, 0, 392, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #657 = V6_vasrw_acc_alt
6484 { 656, 3, 1, 4, 2, 0, 0, 361, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #656 = V6_vasrhv_alt
6485 { 655, 3, 1, 4, 2, 0, 0, 396, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #655 = V6_vasrh_alt
6486 { 654, 4, 1, 4, 2, 0, 0, 392, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #654 = V6_vasrh_acc_alt
6487 { 653, 4, 1, 4, 2, 0, 0, 371, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #653 = V6_vasr_into_alt
6488 { 652, 3, 1, 4, 2, 0, 0, 361, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #652 = V6_vaslwv_alt
6489 { 651, 3, 1, 4, 2, 0, 0, 396, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #651 = V6_vaslw_alt
6490 { 650, 4, 1, 4, 2, 0, 0, 392, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #650 = V6_vaslw_acc_alt
6491 { 649, 3, 1, 4, 2, 0, 0, 361, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #649 = V6_vaslhv_alt
6492 { 648, 3, 1, 4, 2, 0, 0, 396, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #648 = V6_vaslh_alt
6493 { 647, 4, 1, 4, 2, 0, 0, 392, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #647 = V6_vaslh_acc_alt
6494 { 646, 3, 1, 4, 2, 0, 0, 389, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #646 = V6_vandvrt_alt
6495 { 645, 4, 1, 4, 2, 0, 0, 385, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x840000000000026ULL }, // Inst #645 = V6_vandvrt_acc_alt
6496 { 644, 3, 1, 4, 2, 0, 0, 382, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #644 = V6_vandqrt_alt
6497 { 643, 4, 1, 4, 2, 0, 0, 378, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #643 = V6_vandqrt_acc_alt
6498 { 642, 3, 1, 4, 2, 0, 0, 382, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #642 = V6_vandnqrt_alt
6499 { 641, 4, 1, 4, 2, 0, 0, 378, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #641 = V6_vandnqrt_acc_alt
6500 { 640, 3, 1, 4, 2, 0, 0, 364, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #640 = V6_vaddwsat_dv_alt
6501 { 639, 3, 1, 4, 2, 0, 0, 361, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #639 = V6_vaddwsat_alt
6502 { 638, 4, 1, 4, 2, 0, 0, 367, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #638 = V6_vaddwq_alt
6503 { 637, 4, 1, 4, 2, 0, 0, 367, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #637 = V6_vaddwnq_alt
6504 { 636, 3, 1, 4, 2, 0, 0, 364, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #636 = V6_vaddw_dv_alt
6505 { 635, 3, 1, 4, 2, 0, 0, 361, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #635 = V6_vaddw_alt
6506 { 634, 3, 1, 4, 2, 0, 0, 364, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #634 = V6_vadduwsat_dv_alt
6507 { 633, 3, 1, 4, 2, 0, 0, 361, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #633 = V6_vadduwsat_alt
6508 { 632, 3, 1, 4, 2, 0, 0, 375, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #632 = V6_vadduhw_alt
6509 { 631, 4, 1, 4, 2, 0, 0, 371, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #631 = V6_vadduhw_acc_alt
6510 { 630, 3, 1, 4, 2, 0, 0, 364, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #630 = V6_vadduhsat_dv_alt
6511 { 629, 3, 1, 4, 2, 0, 0, 361, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #629 = V6_vadduhsat_alt
6512 { 628, 3, 1, 4, 2, 0, 0, 364, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #628 = V6_vaddubsat_dv_alt
6513 { 627, 3, 1, 4, 2, 0, 0, 361, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #627 = V6_vaddubsat_alt
6514 { 626, 3, 1, 4, 2, 0, 0, 375, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #626 = V6_vaddubh_alt
6515 { 625, 4, 1, 4, 2, 0, 0, 371, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #625 = V6_vaddubh_acc_alt
6516 { 624, 3, 1, 4, 2, 0, 0, 375, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #624 = V6_vaddhw_alt
6517 { 623, 4, 1, 4, 2, 0, 0, 371, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #623 = V6_vaddhw_acc_alt
6518 { 622, 3, 1, 4, 2, 0, 0, 364, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #622 = V6_vaddhsat_dv_alt
6519 { 621, 3, 1, 4, 2, 0, 0, 361, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #621 = V6_vaddhsat_alt
6520 { 620, 4, 1, 4, 2, 0, 0, 367, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #620 = V6_vaddhq_alt
6521 { 619, 4, 1, 4, 2, 0, 0, 367, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #619 = V6_vaddhnq_alt
6522 { 618, 3, 1, 4, 2, 0, 0, 364, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #618 = V6_vaddh_dv_alt
6523 { 617, 3, 1, 4, 2, 0, 0, 361, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #617 = V6_vaddh_alt
6524 { 616, 3, 1, 4, 2, 0, 0, 364, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #616 = V6_vaddbsat_dv_alt
6525 { 615, 3, 1, 4, 2, 0, 0, 361, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #615 = V6_vaddbsat_alt
6526 { 614, 4, 1, 4, 2, 0, 0, 367, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #614 = V6_vaddbq_alt
6527 { 613, 4, 1, 4, 2, 0, 0, 367, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x840000000008026ULL }, // Inst #613 = V6_vaddbnq_alt
6528 { 612, 3, 1, 4, 2, 0, 0, 364, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #612 = V6_vaddb_dv_alt
6529 { 611, 3, 1, 4, 2, 0, 0, 361, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #611 = V6_vaddb_alt
6530 { 610, 2, 1, 4, 2, 0, 0, 359, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #610 = V6_vabsw_sat_alt
6531 { 609, 2, 1, 4, 2, 0, 0, 359, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #609 = V6_vabsw_alt
6532 { 608, 2, 1, 4, 63, 0, 0, 359, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #608 = V6_vabsuw_alt
6533 { 607, 2, 1, 4, 63, 0, 0, 359, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #607 = V6_vabsuh_alt
6534 { 606, 2, 1, 4, 63, 0, 0, 359, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #606 = V6_vabsub_alt
6535 { 605, 2, 1, 4, 2, 0, 0, 359, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #605 = V6_vabsh_sat_alt
6536 { 604, 2, 1, 4, 2, 0, 0, 359, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #604 = V6_vabsh_alt
6537 { 603, 3, 1, 4, 2, 0, 0, 361, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #603 = V6_vabsdiffw_alt
6538 { 602, 3, 1, 4, 2, 0, 0, 361, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #602 = V6_vabsdiffuh_alt
6539 { 601, 3, 1, 4, 2, 0, 0, 361, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #601 = V6_vabsdiffub_alt
6540 { 600, 3, 1, 4, 2, 0, 0, 361, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #600 = V6_vabsdiffh_alt
6541 { 599, 2, 1, 4, 2, 0, 0, 359, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #599 = V6_vabsb_sat_alt
6542 { 598, 2, 1, 4, 2, 0, 0, 359, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #598 = V6_vabsb_alt
6543 { 597, 4, 1, 4, 2, 0, 0, 350, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #597 = V6_v6mpyvubs10_alt
6544 { 596, 4, 1, 4, 2, 0, 0, 350, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #596 = V6_v6mpyhubs10_alt
6545 { 595, 5, 1, 4, 62, 0, 0, 354, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x84000000000801cULL }, // Inst #595 = V6_v10mpyubs10_vxx
6546 { 594, 4, 1, 4, 61, 0, 0, 350, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x80000000000801cULL }, // Inst #594 = V6_v10mpyubs10
6547 { 593, 3, 0, 4, 2, 0, 0, 344, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000000014ULL }, // Inst #593 = V6_stup0
6548 { 592, 3, 0, 4, 2, 0, 0, 344, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000000014ULL }, // Inst #592 = V6_stunp0
6549 { 591, 2, 0, 4, 2, 0, 0, 342, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000000014ULL }, // Inst #591 = V6_stu0
6550 { 590, 3, 0, 4, 2, 0, 0, 347, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000000014ULL }, // Inst #590 = V6_stqnt0
6551 { 589, 3, 0, 4, 2, 0, 0, 347, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000000014ULL }, // Inst #589 = V6_stq0
6552 { 588, 3, 0, 4, 2, 0, 0, 344, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000000014ULL }, // Inst #588 = V6_stpnt0
6553 { 587, 3, 0, 4, 2, 0, 0, 344, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000000014ULL }, // Inst #587 = V6_stp0
6554 { 586, 2, 0, 4, 2, 0, 0, 342, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000000014ULL }, // Inst #586 = V6_stnt0
6555 { 585, 3, 0, 4, 2, 0, 0, 347, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000000014ULL }, // Inst #585 = V6_stnqnt0
6556 { 584, 3, 0, 4, 2, 0, 0, 347, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000000014ULL }, // Inst #584 = V6_stnq0
6557 { 583, 3, 0, 4, 2, 0, 0, 344, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000000014ULL }, // Inst #583 = V6_stnpnt0
6558 { 582, 3, 0, 4, 2, 0, 0, 344, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000000014ULL }, // Inst #582 = V6_stnp0
6559 { 581, 2, 0, 4, 2, 0, 0, 342, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000010014ULL }, // Inst #581 = V6_stnnt0
6560 { 580, 2, 0, 4, 2, 0, 0, 342, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000010014ULL }, // Inst #580 = V6_stn0
6561 { 579, 2, 0, 4, 2, 0, 0, 342, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000000014ULL }, // Inst #579 = V6_st0
6562 { 578, 2, 1, 4, 60, 0, 0, 337, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008010ULL }, // Inst #578 = V6_lo
6563 { 577, 2, 1, 4, 2, 0, 0, 289, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008012ULL }, // Inst #577 = V6_ldu0
6564 { 576, 3, 1, 4, 2, 0, 0, 339, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #576 = V6_ldtpnt0
6565 { 575, 3, 1, 4, 2, 0, 0, 339, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #575 = V6_ldtp0
6566 { 574, 3, 1, 4, 2, 0, 0, 339, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #574 = V6_ldtnpnt0
6567 { 573, 3, 1, 4, 2, 0, 0, 339, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #573 = V6_ldtnp0
6568 { 572, 3, 1, 4, 2, 0, 0, 339, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #572 = V6_ldpnt0
6569 { 571, 3, 1, 4, 2, 0, 0, 339, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #571 = V6_ldp0
6570 { 570, 2, 1, 4, 2, 0, 0, 289, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008012ULL }, // Inst #570 = V6_ldnt0
6571 { 569, 3, 1, 4, 2, 0, 0, 339, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #569 = V6_ldnpnt0
6572 { 568, 3, 1, 4, 2, 0, 0, 339, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #568 = V6_ldnp0
6573 { 567, 3, 1, 4, 2, 0, 0, 339, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #567 = V6_ldcpnt0
6574 { 566, 3, 1, 4, 2, 0, 0, 339, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #566 = V6_ldcp0
6575 { 565, 3, 1, 4, 2, 0, 0, 339, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #565 = V6_ldcnpnt0
6576 { 564, 3, 1, 4, 2, 0, 0, 339, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #564 = V6_ldcnp0
6577 { 563, 2, 1, 4, 2, 0, 0, 289, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008012ULL }, // Inst #563 = V6_ld0
6578 { 562, 2, 1, 4, 60, 0, 0, 337, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008010ULL }, // Inst #562 = V6_hi
6579 { 561, 3, 1, 4, 2, 0, 0, 334, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #561 = V6_extractw_alt
6580 { 560, 2, 0, 4, 2, 0, 0, 332, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x800000000000026ULL }, // Inst #560 = V6_dbl_st0
6581 { 559, 2, 1, 4, 2, 0, 0, 330, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x800000000408026ULL }, // Inst #559 = V6_dbl_ld0
6582 { 558, 4, 1, 4, 2, 0, 0, 326, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000000026ULL }, // Inst #558 = V6_MAP_equw_xor
6583 { 557, 4, 1, 4, 2, 0, 0, 326, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x840000000000026ULL }, // Inst #557 = V6_MAP_equw_ior
6584 { 556, 4, 1, 4, 2, 0, 0, 326, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000000026ULL }, // Inst #556 = V6_MAP_equw_and
6585 { 555, 3, 1, 4, 2, 0, 0, 323, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #555 = V6_MAP_equw
6586 { 554, 4, 1, 4, 2, 0, 0, 326, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000000026ULL }, // Inst #554 = V6_MAP_equh_xor
6587 { 553, 4, 1, 4, 2, 0, 0, 326, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x840000000000026ULL }, // Inst #553 = V6_MAP_equh_ior
6588 { 552, 4, 1, 4, 2, 0, 0, 326, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000000026ULL }, // Inst #552 = V6_MAP_equh_and
6589 { 551, 3, 1, 4, 2, 0, 0, 323, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #551 = V6_MAP_equh
6590 { 550, 4, 1, 4, 2, 0, 0, 326, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000000026ULL }, // Inst #550 = V6_MAP_equb_xor
6591 { 549, 4, 1, 4, 2, 0, 0, 326, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x840000000000026ULL }, // Inst #549 = V6_MAP_equb_ior
6592 { 548, 4, 1, 4, 2, 0, 0, 326, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000000026ULL }, // Inst #548 = V6_MAP_equb_and
6593 { 547, 3, 1, 4, 2, 0, 0, 323, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x800000000008026ULL }, // Inst #547 = V6_MAP_equb
6594 { 546, 3, 0, 4, 59, 0, 0, 320, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x1b2800029ULL }, // Inst #546 = STriw_pred
6595 { 545, 3, 0, 4, 59, 0, 0, 317, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x1b2800029ULL }, // Inst #545 = STriw_ctr
6596 { 544, 1, 0, 4, 58, 0, 0, 0, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #544 = S6_allocframe_to_raw
6597 { 543, 3, 1, 4, 48, 0, 0, 304, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x2bULL }, // Inst #543 = S5_vasrhrnd_goodsyntax
6598 { 542, 3, 1, 4, 48, 0, 0, 314, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x802bULL }, // Inst #542 = S5_asrhub_rnd_sat_goodsyntax
6599 { 541, 3, 0, 4, 57, 0, 0, 175, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #541 = S4_storeiritnew_zomap
6600 { 540, 3, 0, 4, 56, 0, 0, 175, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #540 = S4_storeirit_zomap
6601 { 539, 3, 0, 4, 57, 0, 0, 175, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #539 = S4_storeirifnew_zomap
6602 { 538, 3, 0, 4, 56, 0, 0, 175, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #538 = S4_storeirif_zomap
6603 { 537, 2, 0, 4, 55, 0, 0, 155, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #537 = S4_storeiri_zomap
6604 { 536, 3, 0, 4, 57, 0, 0, 175, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #536 = S4_storeirhtnew_zomap
6605 { 535, 3, 0, 4, 56, 0, 0, 175, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #535 = S4_storeirht_zomap
6606 { 534, 3, 0, 4, 57, 0, 0, 175, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #534 = S4_storeirhfnew_zomap
6607 { 533, 3, 0, 4, 56, 0, 0, 175, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #533 = S4_storeirhf_zomap
6608 { 532, 2, 0, 4, 55, 0, 0, 155, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #532 = S4_storeirh_zomap
6609 { 531, 3, 0, 4, 57, 0, 0, 175, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #531 = S4_storeirbtnew_zomap
6610 { 530, 3, 0, 4, 56, 0, 0, 175, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #530 = S4_storeirbt_zomap
6611 { 529, 3, 0, 4, 57, 0, 0, 175, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #529 = S4_storeirbfnew_zomap
6612 { 528, 3, 0, 4, 56, 0, 0, 175, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #528 = S4_storeirbf_zomap
6613 { 527, 2, 0, 4, 55, 0, 0, 155, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #527 = S4_storeirb_zomap
6614 { 526, 3, 0, 4, 39, 0, 0, 178, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #526 = S4_pstoreritnew_zomap
6615 { 525, 3, 0, 4, 54, 0, 0, 178, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x20026ULL }, // Inst #525 = S4_pstorerinewtnew_zomap
6616 { 524, 3, 0, 4, 54, 0, 0, 178, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x20026ULL }, // Inst #524 = S4_pstorerinewfnew_zomap
6617 { 523, 3, 0, 4, 39, 0, 0, 178, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #523 = S4_pstorerifnew_zomap
6618 { 522, 3, 0, 4, 39, 0, 0, 178, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #522 = S4_pstorerhtnew_zomap
6619 { 521, 3, 0, 4, 54, 0, 0, 178, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x20026ULL }, // Inst #521 = S4_pstorerhnewtnew_zomap
6620 { 520, 3, 0, 4, 54, 0, 0, 178, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x20026ULL }, // Inst #520 = S4_pstorerhnewfnew_zomap
6621 { 519, 3, 0, 4, 39, 0, 0, 178, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #519 = S4_pstorerhfnew_zomap
6622 { 518, 3, 0, 4, 39, 0, 0, 178, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #518 = S4_pstorerftnew_zomap
6623 { 517, 3, 0, 4, 39, 0, 0, 178, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #517 = S4_pstorerffnew_zomap
6624 { 516, 3, 0, 4, 39, 0, 0, 172, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #516 = S4_pstorerdtnew_zomap
6625 { 515, 3, 0, 4, 39, 0, 0, 172, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #515 = S4_pstorerdfnew_zomap
6626 { 514, 3, 0, 4, 39, 0, 0, 178, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #514 = S4_pstorerbtnew_zomap
6627 { 513, 3, 0, 4, 54, 0, 0, 178, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x20026ULL }, // Inst #513 = S4_pstorerbnewtnew_zomap
6628 { 512, 3, 0, 4, 54, 0, 0, 178, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x20026ULL }, // Inst #512 = S4_pstorerbnewfnew_zomap
6629 { 511, 3, 0, 4, 39, 0, 0, 178, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #511 = S4_pstorerbfnew_zomap
6630 { 510, 5, 1, 4, 53, 0, 0, 309, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x802bULL }, // Inst #510 = S2_tableidxw_goodsyntax
6631 { 509, 5, 1, 4, 53, 0, 0, 309, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x802bULL }, // Inst #509 = S2_tableidxh_goodsyntax
6632 { 508, 5, 1, 4, 53, 0, 0, 309, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x802bULL }, // Inst #508 = S2_tableidxd_goodsyntax
6633 { 507, 5, 1, 4, 53, 0, 0, 309, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x802bULL }, // Inst #507 = S2_tableidxb_goodsyntax
6634 { 506, 2, 0, 4, 52, 0, 0, 157, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x10026ULL }, // Inst #506 = S2_storerinew_zomap
6635 { 505, 2, 0, 4, 51, 0, 0, 157, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #505 = S2_storeri_zomap
6636 { 504, 2, 0, 4, 52, 0, 0, 157, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x10026ULL }, // Inst #504 = S2_storerhnew_zomap
6637 { 503, 2, 0, 4, 51, 0, 0, 157, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #503 = S2_storerh_zomap
6638 { 502, 2, 0, 4, 51, 0, 0, 157, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #502 = S2_storerf_zomap
6639 { 501, 2, 0, 4, 51, 0, 0, 307, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #501 = S2_storerd_zomap
6640 { 500, 2, 0, 4, 52, 0, 0, 157, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x10026ULL }, // Inst #500 = S2_storerbnew_zomap
6641 { 499, 2, 0, 4, 51, 0, 0, 157, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #499 = S2_storerb_zomap
6642 { 498, 3, 0, 4, 49, 0, 0, 178, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #498 = S2_pstorerit_zomap
6643 { 497, 3, 0, 4, 50, 0, 0, 178, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x20026ULL }, // Inst #497 = S2_pstorerinewt_zomap
6644 { 496, 3, 0, 4, 50, 0, 0, 178, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x20026ULL }, // Inst #496 = S2_pstorerinewf_zomap
6645 { 495, 3, 0, 4, 49, 0, 0, 178, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #495 = S2_pstorerif_zomap
6646 { 494, 3, 0, 4, 49, 0, 0, 178, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #494 = S2_pstorerht_zomap
6647 { 493, 3, 0, 4, 50, 0, 0, 178, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x20026ULL }, // Inst #493 = S2_pstorerhnewt_zomap
6648 { 492, 3, 0, 4, 50, 0, 0, 178, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x20026ULL }, // Inst #492 = S2_pstorerhnewf_zomap
6649 { 491, 3, 0, 4, 49, 0, 0, 178, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #491 = S2_pstorerhf_zomap
6650 { 490, 3, 0, 4, 49, 0, 0, 178, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #490 = S2_pstorerft_zomap
6651 { 489, 3, 0, 4, 49, 0, 0, 178, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #489 = S2_pstorerff_zomap
6652 { 488, 3, 0, 4, 49, 0, 0, 172, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #488 = S2_pstorerdt_zomap
6653 { 487, 3, 0, 4, 49, 0, 0, 172, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #487 = S2_pstorerdf_zomap
6654 { 486, 3, 0, 4, 49, 0, 0, 178, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #486 = S2_pstorerbt_zomap
6655 { 485, 3, 0, 4, 50, 0, 0, 178, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x20026ULL }, // Inst #485 = S2_pstorerbnewt_zomap
6656 { 484, 3, 0, 4, 50, 0, 0, 178, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x20026ULL }, // Inst #484 = S2_pstorerbnewf_zomap
6657 { 483, 3, 0, 4, 49, 0, 0, 178, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #483 = S2_pstorerbf_zomap
6658 { 482, 3, 1, 4, 48, 0, 0, 199, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x802bULL }, // Inst #482 = S2_asr_i_r_rnd_goodsyntax
6659 { 481, 3, 1, 4, 48, 0, 0, 304, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x2bULL }, // Inst #481 = S2_asr_i_p_rnd_goodsyntax
6660 { 480, 4, 1, 4, 47, 0, 0, 300, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x11ULL }, // Inst #480 = PS_wselect
6661 { 479, 3, 0, 4, 46, 0, 0, 297, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x280000000014ULL }, // Inst #479 = PS_vstorerw_nt_ai
6662 { 478, 3, 0, 4, 46, 0, 0, 297, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x280000000014ULL }, // Inst #478 = PS_vstorerw_ai
6663 { 477, 3, 0, 4, 46, 0, 0, 294, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x280000000014ULL }, // Inst #477 = PS_vstorerv_nt_ai
6664 { 476, 3, 0, 4, 46, 0, 0, 294, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x280000000014ULL }, // Inst #476 = PS_vstorerv_ai
6665 { 475, 3, 0, 4, 2, 0, 0, 291, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x28ULL }, // Inst #475 = PS_vstorerq_ai
6666 { 474, 2, 1, 4, 45, 0, 0, 289, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook), 0x1eULL }, // Inst #474 = PS_vsplatrw
6667 { 473, 2, 1, 4, 45, 0, 0, 289, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook), 0x1eULL }, // Inst #473 = PS_vsplatrh
6668 { 472, 2, 1, 4, 45, 0, 0, 289, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook), 0x1eULL }, // Inst #472 = PS_vsplatrb
6669 { 471, 2, 1, 4, 45, 0, 0, 287, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook), 0x1eULL }, // Inst #471 = PS_vsplatiw
6670 { 470, 2, 1, 4, 45, 0, 0, 287, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook), 0x1eULL }, // Inst #470 = PS_vsplatih
6671 { 469, 2, 1, 4, 45, 0, 0, 287, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook), 0x1eULL }, // Inst #469 = PS_vsplatib
6672 { 468, 4, 1, 4, 44, 0, 0, 283, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x10ULL }, // Inst #468 = PS_vselect
6673 { 467, 4, 1, 4, 43, 0, 0, 215, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x28ULL }, // Inst #467 = PS_vmulw_acc
6674 { 466, 3, 1, 4, 43, 0, 0, 169, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x28ULL }, // Inst #466 = PS_vmulw
6675 { 465, 3, 1, 4, 42, 0, 0, 280, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x280000000012ULL }, // Inst #465 = PS_vloadrw_nt_ai
6676 { 464, 3, 1, 4, 42, 0, 0, 280, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x280000000012ULL }, // Inst #464 = PS_vloadrw_ai
6677 { 463, 3, 1, 4, 42, 0, 0, 277, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x280000000012ULL }, // Inst #463 = PS_vloadrv_nt_ai
6678 { 462, 3, 1, 4, 42, 0, 0, 277, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x280000000012ULL }, // Inst #462 = PS_vloadrv_ai
6679 { 461, 3, 1, 4, 2, 0, 0, 274, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x28ULL }, // Inst #461 = PS_vloadrq_ai
6680 { 460, 1, 1, 4, 41, 0, 0, 273, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable), 0x11ULL }, // Inst #460 = PS_vdd0
6681 { 459, 1, 1, 4, 11, 0, 0, 195, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable), 0x5ULL }, // Inst #459 = PS_true
6682 { 458, 1, 0, 4, 40, 0, 1, 272, HexagonImpOpBase + 55, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x1000000023ULL }, // Inst #458 = PS_tailcall_r
6683 { 457, 1, 0, 4, 2, 0, 0, 0, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x28ULL }, // Inst #457 = PS_tailcall_i
6684 { 456, 5, 1, 4, 39, 1, 1, 256, HexagonImpOpBase + 53, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x1e0000000029ULL }, // Inst #456 = PS_storeri_pcr
6685 { 455, 6, 1, 4, 38, 1, 1, 250, HexagonImpOpBase + 53, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x1e0000000029ULL }, // Inst #455 = PS_storeri_pci
6686 { 454, 5, 1, 4, 39, 1, 1, 256, HexagonImpOpBase + 53, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x160000000029ULL }, // Inst #454 = PS_storerh_pcr
6687 { 453, 6, 1, 4, 38, 1, 1, 250, HexagonImpOpBase + 53, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x160000000029ULL }, // Inst #453 = PS_storerh_pci
6688 { 452, 5, 1, 4, 39, 1, 1, 256, HexagonImpOpBase + 53, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x160000000029ULL }, // Inst #452 = PS_storerf_pcr
6689 { 451, 6, 1, 4, 38, 1, 1, 250, HexagonImpOpBase + 53, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x160000000029ULL }, // Inst #451 = PS_storerf_pci
6690 { 450, 5, 1, 4, 39, 1, 1, 267, HexagonImpOpBase + 53, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x1e0000000029ULL }, // Inst #450 = PS_storerd_pcr
6691 { 449, 6, 1, 4, 38, 1, 1, 261, HexagonImpOpBase + 53, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x1e0000000029ULL }, // Inst #449 = PS_storerd_pci
6692 { 448, 5, 1, 4, 39, 1, 1, 256, HexagonImpOpBase + 53, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0xe0000000029ULL }, // Inst #448 = PS_storerb_pcr
6693 { 447, 6, 1, 4, 38, 1, 1, 250, HexagonImpOpBase + 53, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0xe0000000029ULL }, // Inst #447 = PS_storerb_pci
6694 { 446, 1, 1, 4, 37, 0, 0, 249, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable), 0x10ULL }, // Inst #446 = PS_qtrue
6695 { 445, 1, 1, 4, 37, 0, 0, 249, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable), 0x10ULL }, // Inst #445 = PS_qfalse
6696 { 444, 4, 1, 4, 6, 0, 0, 245, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #444 = PS_pselect
6697 { 443, 5, 2, 4, 20, 1, 1, 229, HexagonImpOpBase + 53, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x160000000024ULL }, // Inst #443 = PS_loadruh_pcr
6698 { 442, 6, 2, 4, 36, 1, 1, 223, HexagonImpOpBase + 53, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x160000000024ULL }, // Inst #442 = PS_loadruh_pci
6699 { 441, 5, 2, 4, 20, 1, 1, 229, HexagonImpOpBase + 53, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0xe0000000024ULL }, // Inst #441 = PS_loadrub_pcr
6700 { 440, 6, 2, 4, 36, 1, 1, 223, HexagonImpOpBase + 53, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0xe0000000024ULL }, // Inst #440 = PS_loadrub_pci
6701 { 439, 5, 2, 4, 20, 1, 1, 229, HexagonImpOpBase + 53, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x1e0000000024ULL }, // Inst #439 = PS_loadri_pcr
6702 { 438, 6, 2, 4, 36, 1, 1, 223, HexagonImpOpBase + 53, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x1e0000000024ULL }, // Inst #438 = PS_loadri_pci
6703 { 437, 5, 2, 4, 20, 1, 1, 229, HexagonImpOpBase + 53, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x160000000024ULL }, // Inst #437 = PS_loadrh_pcr
6704 { 436, 6, 2, 4, 36, 1, 1, 223, HexagonImpOpBase + 53, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x160000000024ULL }, // Inst #436 = PS_loadrh_pci
6705 { 435, 5, 2, 4, 20, 1, 1, 240, HexagonImpOpBase + 53, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x260000000024ULL }, // Inst #435 = PS_loadrd_pcr
6706 { 434, 6, 2, 4, 36, 1, 1, 234, HexagonImpOpBase + 53, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x260000000024ULL }, // Inst #434 = PS_loadrd_pci
6707 { 433, 5, 2, 4, 20, 1, 1, 229, HexagonImpOpBase + 53, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0xe0000000024ULL }, // Inst #433 = PS_loadrb_pcr
6708 { 432, 6, 2, 4, 36, 1, 1, 223, HexagonImpOpBase + 53, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0xe0000000024ULL }, // Inst #432 = PS_loadrb_pci
6709 { 431, 4, 1, 4, 2, 0, 0, 219, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x216800028ULL }, // Inst #431 = PS_fia
6710 { 430, 3, 1, 4, 2, 0, 0, 199, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x214800028ULL }, // Inst #430 = PS_fi
6711 { 429, 1, 1, 4, 11, 0, 0, 195, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable), 0x5ULL }, // Inst #429 = PS_false
6712 { 428, 0, 0, 4, 2, 0, 0, 1, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0xa8ULL }, // Inst #428 = PS_crash
6713 { 427, 1, 0, 4, 35, 0, 0, 0, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0xb10800028ULL }, // Inst #427 = PS_call_nr
6714 { 426, 2, 0, 4, 2, 0, 8, 13, HexagonImpOpBase + 45, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x28ULL }, // Inst #426 = PS_call_instrprof_custom
6715 { 425, 3, 1, 4, 2, 0, 1, 199, HexagonImpOpBase + 44, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x28ULL }, // Inst #425 = PS_alloca
6716 { 424, 2, 1, 4, 2, 1, 0, 155, HexagonImpOpBase + 43, 0|(1ULL<<MCID::Pseudo), 0x28ULL }, // Inst #424 = PS_aligna
6717 { 423, 4, 1, 4, 34, 0, 0, 215, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x25ULL }, // Inst #423 = M7_vdmpy_acc
6718 { 422, 3, 1, 4, 33, 0, 0, 169, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x25ULL }, // Inst #422 = M7_vdmpy
6719 { 421, 3, 1, 4, 31, 0, 0, 212, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x8025ULL }, // Inst #421 = M2_vrcmpys_s1rp
6720 { 420, 3, 1, 4, 31, 0, 0, 209, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x25ULL }, // Inst #420 = M2_vrcmpys_s1
6721 { 419, 4, 1, 4, 32, 0, 0, 205, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x25ULL }, // Inst #419 = M2_vrcmpys_acc_s1
6722 { 418, 3, 1, 4, 31, 0, 0, 202, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x8025ULL }, // Inst #418 = M2_mpyui
6723 { 417, 3, 1, 4, 30, 0, 0, 199, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x134808025ULL }, // Inst #417 = M2_mpysmi
6724 { 416, 3, 1, 4, 29, 0, 0, 175, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x1b4800024ULL }, // Inst #416 = LDriw_pred
6725 { 415, 3, 1, 4, 29, 0, 0, 196, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x1b4800024ULL }, // Inst #415 = LDriw_ctr
6726 { 414, 0, 0, 4, 28, 0, 0, 1, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #414 = L6_return_map_to_raw
6727 { 413, 0, 0, 4, 27, 0, 0, 1, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #413 = L6_deallocframe_map_to_raw
6728 { 412, 2, 0, 4, 21, 0, 0, 157, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #412 = L4_sub_memopw_zomap
6729 { 411, 2, 0, 4, 21, 0, 0, 157, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #411 = L4_sub_memoph_zomap
6730 { 410, 2, 0, 4, 21, 0, 0, 157, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #410 = L4_sub_memopb_zomap
6731 { 409, 1, 0, 4, 26, 0, 0, 195, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #409 = L4_return_map_to_raw_tnew_pt
6732 { 408, 1, 0, 4, 26, 0, 0, 195, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #408 = L4_return_map_to_raw_tnew_pnt
6733 { 407, 1, 0, 4, 25, 0, 0, 195, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #407 = L4_return_map_to_raw_t
6734 { 406, 1, 0, 4, 24, 0, 0, 195, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #406 = L4_return_map_to_raw_fnew_pt
6735 { 405, 1, 0, 4, 24, 0, 0, 195, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #405 = L4_return_map_to_raw_fnew_pnt
6736 { 404, 1, 0, 4, 23, 0, 0, 195, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #404 = L4_return_map_to_raw_f
6737 { 403, 2, 0, 4, 21, 0, 0, 157, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #403 = L4_or_memopw_zomap
6738 { 402, 2, 0, 4, 21, 0, 0, 157, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #402 = L4_or_memoph_zomap
6739 { 401, 2, 0, 4, 21, 0, 0, 157, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #401 = L4_or_memopb_zomap
6740 { 400, 2, 0, 4, 22, 0, 0, 155, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #400 = L4_isub_memopw_zomap
6741 { 399, 2, 0, 4, 22, 0, 0, 155, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #399 = L4_isub_memoph_zomap
6742 { 398, 2, 0, 4, 22, 0, 0, 155, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #398 = L4_isub_memopb_zomap
6743 { 397, 2, 0, 4, 22, 0, 0, 155, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #397 = L4_ior_memopw_zomap
6744 { 396, 2, 0, 4, 22, 0, 0, 155, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #396 = L4_ior_memoph_zomap
6745 { 395, 2, 0, 4, 22, 0, 0, 155, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #395 = L4_ior_memopb_zomap
6746 { 394, 2, 0, 4, 22, 0, 0, 155, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #394 = L4_iand_memopw_zomap
6747 { 393, 2, 0, 4, 22, 0, 0, 155, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #393 = L4_iand_memoph_zomap
6748 { 392, 2, 0, 4, 22, 0, 0, 155, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #392 = L4_iand_memopb_zomap
6749 { 391, 2, 0, 4, 22, 0, 0, 155, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #391 = L4_iadd_memopw_zomap
6750 { 390, 2, 0, 4, 22, 0, 0, 155, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #390 = L4_iadd_memoph_zomap
6751 { 389, 2, 0, 4, 22, 0, 0, 155, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #389 = L4_iadd_memopb_zomap
6752 { 388, 2, 0, 4, 21, 0, 0, 157, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #388 = L4_and_memopw_zomap
6753 { 387, 2, 0, 4, 21, 0, 0, 157, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #387 = L4_and_memoph_zomap
6754 { 386, 2, 0, 4, 21, 0, 0, 157, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #386 = L4_and_memopb_zomap
6755 { 385, 2, 0, 4, 21, 0, 0, 157, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #385 = L4_add_memopw_zomap
6756 { 384, 2, 0, 4, 21, 0, 0, 157, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #384 = L4_add_memoph_zomap
6757 { 383, 2, 0, 4, 21, 0, 0, 157, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #383 = L4_add_memopb_zomap
6758 { 382, 3, 1, 4, 20, 0, 0, 159, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x8026ULL }, // Inst #382 = L2_ploadruhtnew_zomap
6759 { 381, 3, 1, 4, 18, 0, 0, 159, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x8026ULL }, // Inst #381 = L2_ploadruht_zomap
6760 { 380, 3, 1, 4, 20, 0, 0, 159, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x8026ULL }, // Inst #380 = L2_ploadruhfnew_zomap
6761 { 379, 3, 1, 4, 18, 0, 0, 159, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x8026ULL }, // Inst #379 = L2_ploadruhf_zomap
6762 { 378, 3, 1, 4, 20, 0, 0, 159, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x8026ULL }, // Inst #378 = L2_ploadrubtnew_zomap
6763 { 377, 3, 1, 4, 18, 0, 0, 159, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x8026ULL }, // Inst #377 = L2_ploadrubt_zomap
6764 { 376, 3, 1, 4, 20, 0, 0, 159, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x8026ULL }, // Inst #376 = L2_ploadrubfnew_zomap
6765 { 375, 3, 1, 4, 18, 0, 0, 159, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x8026ULL }, // Inst #375 = L2_ploadrubf_zomap
6766 { 374, 3, 1, 4, 20, 0, 0, 159, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x8026ULL }, // Inst #374 = L2_ploadritnew_zomap
6767 { 373, 3, 1, 4, 18, 0, 0, 159, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x8026ULL }, // Inst #373 = L2_ploadrit_zomap
6768 { 372, 3, 1, 4, 20, 0, 0, 159, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x8026ULL }, // Inst #372 = L2_ploadrifnew_zomap
6769 { 371, 3, 1, 4, 18, 0, 0, 159, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x8026ULL }, // Inst #371 = L2_ploadrif_zomap
6770 { 370, 3, 1, 4, 20, 0, 0, 159, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x8026ULL }, // Inst #370 = L2_ploadrhtnew_zomap
6771 { 369, 3, 1, 4, 18, 0, 0, 159, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x8026ULL }, // Inst #369 = L2_ploadrht_zomap
6772 { 368, 3, 1, 4, 20, 0, 0, 159, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x8026ULL }, // Inst #368 = L2_ploadrhfnew_zomap
6773 { 367, 3, 1, 4, 18, 0, 0, 159, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x8026ULL }, // Inst #367 = L2_ploadrhf_zomap
6774 { 366, 3, 1, 4, 20, 0, 0, 192, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #366 = L2_ploadrdtnew_zomap
6775 { 365, 3, 1, 4, 18, 0, 0, 192, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #365 = L2_ploadrdt_zomap
6776 { 364, 3, 1, 4, 20, 0, 0, 192, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #364 = L2_ploadrdfnew_zomap
6777 { 363, 3, 1, 4, 18, 0, 0, 192, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #363 = L2_ploadrdf_zomap
6778 { 362, 3, 1, 4, 20, 0, 0, 159, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x8026ULL }, // Inst #362 = L2_ploadrbtnew_zomap
6779 { 361, 3, 1, 4, 18, 0, 0, 159, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x8026ULL }, // Inst #361 = L2_ploadrbt_zomap
6780 { 360, 3, 1, 4, 20, 0, 0, 159, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x8026ULL }, // Inst #360 = L2_ploadrbfnew_zomap
6781 { 359, 3, 1, 4, 18, 0, 0, 159, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x8026ULL }, // Inst #359 = L2_ploadrbf_zomap
6782 { 358, 2, 1, 4, 19, 0, 0, 157, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x8026ULL }, // Inst #358 = L2_loadruh_zomap
6783 { 357, 2, 1, 4, 19, 0, 0, 157, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x8026ULL }, // Inst #357 = L2_loadrub_zomap
6784 { 356, 2, 1, 4, 19, 0, 0, 157, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x8026ULL }, // Inst #356 = L2_loadri_zomap
6785 { 355, 2, 1, 4, 19, 0, 0, 157, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x8026ULL }, // Inst #355 = L2_loadrh_zomap
6786 { 354, 2, 1, 4, 19, 0, 0, 190, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #354 = L2_loadrd_zomap
6787 { 353, 2, 1, 4, 19, 0, 0, 157, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x8026ULL }, // Inst #353 = L2_loadrb_zomap
6788 { 352, 2, 1, 4, 19, 0, 0, 190, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #352 = L2_loadbzw4_zomap
6789 { 351, 2, 1, 4, 19, 0, 0, 157, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x8026ULL }, // Inst #351 = L2_loadbzw2_zomap
6790 { 350, 2, 1, 4, 19, 0, 0, 190, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #350 = L2_loadbsw4_zomap
6791 { 349, 2, 1, 4, 19, 0, 0, 157, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x8026ULL }, // Inst #349 = L2_loadbsw2_zomap
6792 { 348, 3, 1, 4, 18, 0, 0, 187, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #348 = L2_loadalignh_zomap
6793 { 347, 3, 1, 4, 18, 0, 0, 187, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #347 = L2_loadalignb_zomap
6794 { 346, 1, 0, 4, 17, 0, 0, 0, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x26ULL }, // Inst #346 = J2_trap1_noregmap
6795 { 345, 2, 0, 4, 15, 0, 0, 183, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #345 = J2_jumpt_nopred_map
6796 { 344, 2, 0, 4, 16, 0, 0, 185, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #344 = J2_jumprt_nopred_map
6797 { 343, 2, 0, 4, 16, 0, 0, 185, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #343 = J2_jumprf_nopred_map
6798 { 342, 2, 0, 4, 15, 0, 0, 183, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #342 = J2_jumpf_nopred_map
6799 { 341, 0, 0, 4, 14, 2, 2, 1, HexagonImpOpBase + 39, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x23ULL }, // Inst #341 = J2_endloop1
6800 { 340, 0, 0, 4, 14, 4, 5, 1, HexagonImpOpBase + 30, 0|(1ULL<<MCID::Pseudo), 0x23ULL }, // Inst #340 = J2_endloop01
6801 { 339, 0, 0, 4, 14, 2, 4, 1, HexagonImpOpBase + 24, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x23ULL }, // Inst #339 = J2_endloop0
6802 { 338, 1, 0, 4, 13, 2, 2, 0, HexagonImpOpBase + 20, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x21ULL }, // Inst #338 = ENDLOOP1
6803 { 337, 1, 0, 4, 13, 4, 3, 0, HexagonImpOpBase + 13, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x21ULL }, // Inst #337 = ENDLOOP01
6804 { 336, 1, 0, 4, 13, 2, 2, 0, HexagonImpOpBase + 9, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x21ULL }, // Inst #336 = ENDLOOP0
6805 { 335, 1, 0, 4, 12, 0, 0, 0, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x28ULL }, // Inst #335 = DUPLEX_Pseudo
6806 { 334, 2, 1, 4, 11, 0, 0, 181, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #334 = C2_pxfer_map
6807 { 333, 3, 1, 4, 10, 0, 0, 178, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare), 0x1ULL }, // Inst #333 = C2_cmpltu
6808 { 332, 3, 1, 4, 10, 0, 0, 178, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare), 0x1ULL }, // Inst #332 = C2_cmplt
6809 { 331, 3, 1, 4, 10, 0, 0, 175, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare), 0x0ULL }, // Inst #331 = C2_cmpgeui
6810 { 330, 3, 1, 4, 10, 0, 0, 175, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare), 0x0ULL }, // Inst #330 = C2_cmpgei
6811 { 329, 2, 0, 4, 2, 1, 3, 21, HexagonImpOpBase + 5, 0|(1ULL<<MCID::Pseudo), 0x28ULL }, // Inst #329 = ADJCALLSTACKUP
6812 { 328, 2, 0, 4, 2, 3, 2, 21, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x28ULL }, // Inst #328 = ADJCALLSTACKDOWN
6813 { 327, 3, 1, 4, 9, 0, 0, 172, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x3ULL }, // Inst #327 = A4_boundscheck
6814 { 326, 2, 1, 4, 6, 0, 0, 157, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable), 0x8000ULL }, // Inst #326 = A2_zxtb
6815 { 325, 3, 1, 4, 8, 0, 0, 169, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #325 = A2_vsubb_map
6816 { 324, 3, 1, 4, 8, 0, 0, 169, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x26ULL }, // Inst #324 = A2_vaddb_map
6817 { 323, 3, 1, 4, 5, 0, 0, 159, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x9400ULL }, // Inst #323 = A2_tfrtnew
6818 { 322, 3, 1, 4, 4, 0, 0, 159, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x8400ULL }, // Inst #322 = A2_tfrt
6819 { 321, 3, 1, 4, 7, 0, 0, 164, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x1400ULL }, // Inst #321 = A2_tfrptnew
6820 { 320, 3, 1, 4, 6, 0, 0, 164, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x400ULL }, // Inst #320 = A2_tfrpt
6821 { 319, 2, 1, 4, 6, 0, 0, 167, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x3ULL }, // Inst #319 = A2_tfrpi
6822 { 318, 3, 1, 4, 7, 0, 0, 164, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x1c00ULL }, // Inst #318 = A2_tfrpfnew
6823 { 317, 3, 1, 4, 6, 0, 0, 164, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0xc00ULL }, // Inst #317 = A2_tfrpf
6824 { 316, 2, 1, 4, 6, 0, 0, 162, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable), 0x0ULL }, // Inst #316 = A2_tfrp
6825 { 315, 3, 1, 4, 5, 0, 0, 159, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x9c00ULL }, // Inst #315 = A2_tfrfnew
6826 { 314, 3, 1, 4, 4, 0, 0, 159, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x8c00ULL }, // Inst #314 = A2_tfrf
6827 { 313, 2, 1, 4, 3, 0, 0, 157, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x8000ULL }, // Inst #313 = A2_not
6828 { 312, 2, 1, 4, 3, 0, 0, 157, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x8000ULL }, // Inst #312 = A2_neg
6829 { 311, 2, 1, 4, 2, 0, 0, 155, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x28ULL }, // Inst #311 = A2_iconst
6830 { 310, 3, 1, 4, 1, 0, 0, 152, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x3ULL }, // Inst #310 = A2_addsp
6831 { 309, 4, 1, 0, 0, 0, 0, 148, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #309 = G_UBFX
6832 { 308, 4, 1, 0, 0, 0, 0, 148, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #308 = G_SBFX
6833 { 307, 2, 1, 0, 0, 0, 0, 61, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #307 = G_VECREDUCE_UMIN
6834 { 306, 2, 1, 0, 0, 0, 0, 61, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #306 = G_VECREDUCE_UMAX
6835 { 305, 2, 1, 0, 0, 0, 0, 61, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #305 = G_VECREDUCE_SMIN
6836 { 304, 2, 1, 0, 0, 0, 0, 61, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #304 = G_VECREDUCE_SMAX
6837 { 303, 2, 1, 0, 0, 0, 0, 61, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #303 = G_VECREDUCE_XOR
6838 { 302, 2, 1, 0, 0, 0, 0, 61, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #302 = G_VECREDUCE_OR
6839 { 301, 2, 1, 0, 0, 0, 0, 61, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #301 = G_VECREDUCE_AND
6840 { 300, 2, 1, 0, 0, 0, 0, 61, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #300 = G_VECREDUCE_MUL
6841 { 299, 2, 1, 0, 0, 0, 0, 61, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #299 = G_VECREDUCE_ADD
6842 { 298, 2, 1, 0, 0, 0, 0, 61, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #298 = G_VECREDUCE_FMINIMUM
6843 { 297, 2, 1, 0, 0, 0, 0, 61, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #297 = G_VECREDUCE_FMAXIMUM
6844 { 296, 2, 1, 0, 0, 0, 0, 61, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #296 = G_VECREDUCE_FMIN
6845 { 295, 2, 1, 0, 0, 0, 0, 61, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #295 = G_VECREDUCE_FMAX
6846 { 294, 2, 1, 0, 0, 0, 0, 61, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #294 = G_VECREDUCE_FMUL
6847 { 293, 2, 1, 0, 0, 0, 0, 61, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #293 = G_VECREDUCE_FADD
6848 { 292, 3, 1, 0, 0, 0, 0, 131, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #292 = G_VECREDUCE_SEQ_FMUL
6849 { 291, 3, 1, 0, 0, 0, 0, 131, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #291 = G_VECREDUCE_SEQ_FADD
6850 { 290, 1, 0, 0, 0, 0, 0, 1, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #290 = G_UBSANTRAP
6851 { 289, 0, 0, 0, 0, 0, 0, 1, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #289 = G_DEBUGTRAP
6852 { 288, 0, 0, 0, 0, 0, 0, 1, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #288 = G_TRAP
6853 { 287, 3, 0, 0, 0, 0, 0, 58, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #287 = G_BZERO
6854 { 286, 4, 0, 0, 0, 0, 0, 144, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #286 = G_MEMSET
6855 { 285, 4, 0, 0, 0, 0, 0, 144, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #285 = G_MEMMOVE
6856 { 284, 3, 0, 0, 0, 0, 0, 131, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #284 = G_MEMCPY_INLINE
6857 { 283, 4, 0, 0, 0, 0, 0, 144, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #283 = G_MEMCPY
6858 { 282, 2, 0, 0, 0, 0, 0, 142, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #282 = G_WRITE_REGISTER
6859 { 281, 2, 1, 0, 0, 0, 0, 51, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #281 = G_READ_REGISTER
6860 { 280, 3, 1, 0, 0, 0, 0, 101, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #280 = G_STRICT_FLDEXP
6861 { 279, 2, 1, 0, 0, 0, 0, 67, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #279 = G_STRICT_FSQRT
6862 { 278, 4, 1, 0, 0, 0, 0, 46, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #278 = G_STRICT_FMA
6863 { 277, 3, 1, 0, 0, 0, 0, 43, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #277 = G_STRICT_FREM
6864 { 276, 3, 1, 0, 0, 0, 0, 43, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #276 = G_STRICT_FDIV
6865 { 275, 3, 1, 0, 0, 0, 0, 43, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #275 = G_STRICT_FMUL
6866 { 274, 3, 1, 0, 0, 0, 0, 43, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #274 = G_STRICT_FSUB
6867 { 273, 3, 1, 0, 0, 0, 0, 43, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #273 = G_STRICT_FADD
6868 { 272, 1, 0, 0, 0, 0, 0, 50, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #272 = G_STACKRESTORE
6869 { 271, 1, 1, 0, 0, 0, 0, 50, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #271 = G_STACKSAVE
6870 { 270, 3, 1, 0, 0, 0, 0, 69, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #270 = G_DYN_STACKALLOC
6871 { 269, 2, 1, 0, 0, 0, 0, 51, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #269 = G_JUMP_TABLE
6872 { 268, 2, 1, 0, 0, 0, 0, 51, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #268 = G_BLOCK_ADDR
6873 { 267, 2, 1, 0, 0, 0, 0, 61, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #267 = G_ADDRSPACE_CAST
6874 { 266, 2, 1, 0, 0, 0, 0, 67, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #266 = G_FNEARBYINT
6875 { 265, 2, 1, 0, 0, 0, 0, 67, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #265 = G_FRINT
6876 { 264, 2, 1, 0, 0, 0, 0, 67, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #264 = G_FFLOOR
6877 { 263, 2, 1, 0, 0, 0, 0, 67, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #263 = G_FSQRT
6878 { 262, 2, 1, 0, 0, 0, 0, 67, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #262 = G_FTANH
6879 { 261, 2, 1, 0, 0, 0, 0, 67, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #261 = G_FSINH
6880 { 260, 2, 1, 0, 0, 0, 0, 67, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #260 = G_FCOSH
6881 { 259, 3, 1, 0, 0, 0, 0, 43, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #259 = G_FATAN2
6882 { 258, 2, 1, 0, 0, 0, 0, 67, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #258 = G_FATAN
6883 { 257, 2, 1, 0, 0, 0, 0, 67, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #257 = G_FASIN
6884 { 256, 2, 1, 0, 0, 0, 0, 67, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #256 = G_FACOS
6885 { 255, 2, 1, 0, 0, 0, 0, 67, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #255 = G_FTAN
6886 { 254, 3, 2, 0, 0, 0, 0, 43, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #254 = G_FSINCOS
6887 { 253, 2, 1, 0, 0, 0, 0, 67, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #253 = G_FSIN
6888 { 252, 2, 1, 0, 0, 0, 0, 67, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #252 = G_FCOS
6889 { 251, 2, 1, 0, 0, 0, 0, 67, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #251 = G_FCEIL
6890 { 250, 2, 1, 0, 0, 0, 0, 67, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #250 = G_BITREVERSE
6891 { 249, 2, 1, 0, 0, 0, 0, 67, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #249 = G_BSWAP
6892 { 248, 2, 1, 0, 0, 0, 0, 61, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #248 = G_CTPOP
6893 { 247, 2, 1, 0, 0, 0, 0, 61, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #247 = G_CTLZ_ZERO_UNDEF
6894 { 246, 2, 1, 0, 0, 0, 0, 61, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #246 = G_CTLZ
6895 { 245, 2, 1, 0, 0, 0, 0, 61, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #245 = G_CTTZ_ZERO_UNDEF
6896 { 244, 2, 1, 0, 0, 0, 0, 61, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #244 = G_CTTZ
6897 { 243, 4, 1, 0, 0, 0, 0, 138, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #243 = G_VECTOR_COMPRESS
6898 { 242, 2, 1, 0, 0, 0, 0, 51, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #242 = G_STEP_VECTOR
6899 { 241, 2, 1, 0, 0, 0, 0, 61, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #241 = G_SPLAT_VECTOR
6900 { 240, 4, 1, 0, 0, 0, 0, 134, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #240 = G_SHUFFLE_VECTOR
6901 { 239, 3, 1, 0, 0, 0, 0, 131, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #239 = G_EXTRACT_VECTOR_ELT
6902 { 238, 4, 1, 0, 0, 0, 0, 127, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #238 = G_INSERT_VECTOR_ELT
6903 { 237, 3, 1, 0, 0, 0, 0, 58, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #237 = G_EXTRACT_SUBVECTOR
6904 { 236, 4, 1, 0, 0, 0, 0, 63, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #236 = G_INSERT_SUBVECTOR
6905 { 235, 2, 1, 0, 0, 0, 0, 51, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #235 = G_VSCALE
6906 { 234, 3, 0, 0, 0, 0, 0, 124, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #234 = G_BRJT
6907 { 233, 1, 0, 0, 0, 0, 0, 0, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #233 = G_BR
6908 { 232, 2, 1, 0, 0, 0, 0, 61, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #232 = G_LLROUND
6909 { 231, 2, 1, 0, 0, 0, 0, 61, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #231 = G_LROUND
6910 { 230, 2, 1, 0, 0, 0, 0, 67, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #230 = G_ABS
6911 { 229, 3, 1, 0, 0, 0, 0, 43, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #229 = G_UMAX
6912 { 228, 3, 1, 0, 0, 0, 0, 43, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #228 = G_UMIN
6913 { 227, 3, 1, 0, 0, 0, 0, 43, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #227 = G_SMAX
6914 { 226, 3, 1, 0, 0, 0, 0, 43, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #226 = G_SMIN
6915 { 225, 3, 1, 0, 0, 0, 0, 101, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #225 = G_PTRMASK
6916 { 224, 3, 1, 0, 0, 0, 0, 101, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #224 = G_PTR_ADD
6917 { 223, 0, 0, 0, 0, 0, 0, 1, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #223 = G_RESET_FPMODE
6918 { 222, 1, 0, 0, 0, 0, 0, 50, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #222 = G_SET_FPMODE
6919 { 221, 1, 1, 0, 0, 0, 0, 50, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #221 = G_GET_FPMODE
6920 { 220, 0, 0, 0, 0, 0, 0, 1, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #220 = G_RESET_FPENV
6921 { 219, 1, 0, 0, 0, 0, 0, 50, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #219 = G_SET_FPENV
6922 { 218, 1, 1, 0, 0, 0, 0, 50, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #218 = G_GET_FPENV
6923 { 217, 3, 1, 0, 0, 0, 0, 43, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #217 = G_FMAXIMUMNUM
6924 { 216, 3, 1, 0, 0, 0, 0, 43, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #216 = G_FMINIMUMNUM
6925 { 215, 3, 1, 0, 0, 0, 0, 43, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #215 = G_FMAXIMUM
6926 { 214, 3, 1, 0, 0, 0, 0, 43, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #214 = G_FMINIMUM
6927 { 213, 3, 1, 0, 0, 0, 0, 43, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #213 = G_FMAXNUM_IEEE
6928 { 212, 3, 1, 0, 0, 0, 0, 43, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #212 = G_FMINNUM_IEEE
6929 { 211, 3, 1, 0, 0, 0, 0, 43, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #211 = G_FMAXNUM
6930 { 210, 3, 1, 0, 0, 0, 0, 43, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #210 = G_FMINNUM
6931 { 209, 2, 1, 0, 0, 0, 0, 67, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #209 = G_FCANONICALIZE
6932 { 208, 3, 1, 0, 0, 0, 0, 98, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #208 = G_IS_FPCLASS
6933 { 207, 3, 1, 0, 0, 0, 0, 101, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #207 = G_FCOPYSIGN
6934 { 206, 2, 1, 0, 0, 0, 0, 67, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #206 = G_FABS
6935 { 205, 2, 1, 0, 0, 0, 0, 61, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #205 = G_FPTOUI_SAT
6936 { 204, 2, 1, 0, 0, 0, 0, 61, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #204 = G_FPTOSI_SAT
6937 { 203, 2, 1, 0, 0, 0, 0, 61, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #203 = G_UITOFP
6938 { 202, 2, 1, 0, 0, 0, 0, 61, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #202 = G_SITOFP
6939 { 201, 2, 1, 0, 0, 0, 0, 61, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #201 = G_FPTOUI
6940 { 200, 2, 1, 0, 0, 0, 0, 61, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #200 = G_FPTOSI
6941 { 199, 2, 1, 0, 0, 0, 0, 61, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #199 = G_FPTRUNC
6942 { 198, 2, 1, 0, 0, 0, 0, 61, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #198 = G_FPEXT
6943 { 197, 2, 1, 0, 0, 0, 0, 67, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #197 = G_FNEG
6944 { 196, 3, 2, 0, 0, 0, 0, 91, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #196 = G_FFREXP
6945 { 195, 3, 1, 0, 0, 0, 0, 101, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #195 = G_FLDEXP
6946 { 194, 2, 1, 0, 0, 0, 0, 67, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #194 = G_FLOG10
6947 { 193, 2, 1, 0, 0, 0, 0, 67, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #193 = G_FLOG2
6948 { 192, 2, 1, 0, 0, 0, 0, 67, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #192 = G_FLOG
6949 { 191, 2, 1, 0, 0, 0, 0, 67, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #191 = G_FEXP10
6950 { 190, 2, 1, 0, 0, 0, 0, 67, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #190 = G_FEXP2
6951 { 189, 2, 1, 0, 0, 0, 0, 67, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #189 = G_FEXP
6952 { 188, 3, 1, 0, 0, 0, 0, 101, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #188 = G_FPOWI
6953 { 187, 3, 1, 0, 0, 0, 0, 43, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #187 = G_FPOW
6954 { 186, 3, 1, 0, 0, 0, 0, 43, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #186 = G_FREM
6955 { 185, 3, 1, 0, 0, 0, 0, 43, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #185 = G_FDIV
6956 { 184, 4, 1, 0, 0, 0, 0, 46, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #184 = G_FMAD
6957 { 183, 4, 1, 0, 0, 0, 0, 46, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #183 = G_FMA
6958 { 182, 3, 1, 0, 0, 0, 0, 43, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #182 = G_FMUL
6959 { 181, 3, 1, 0, 0, 0, 0, 43, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #181 = G_FSUB
6960 { 180, 3, 1, 0, 0, 0, 0, 43, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #180 = G_FADD
6961 { 179, 4, 1, 0, 0, 0, 0, 120, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #179 = G_UDIVFIXSAT
6962 { 178, 4, 1, 0, 0, 0, 0, 120, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #178 = G_SDIVFIXSAT
6963 { 177, 4, 1, 0, 0, 0, 0, 120, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #177 = G_UDIVFIX
6964 { 176, 4, 1, 0, 0, 0, 0, 120, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #176 = G_SDIVFIX
6965 { 175, 4, 1, 0, 0, 0, 0, 120, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #175 = G_UMULFIXSAT
6966 { 174, 4, 1, 0, 0, 0, 0, 120, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #174 = G_SMULFIXSAT
6967 { 173, 4, 1, 0, 0, 0, 0, 120, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #173 = G_UMULFIX
6968 { 172, 4, 1, 0, 0, 0, 0, 120, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #172 = G_SMULFIX
6969 { 171, 3, 1, 0, 0, 0, 0, 101, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #171 = G_SSHLSAT
6970 { 170, 3, 1, 0, 0, 0, 0, 101, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #170 = G_USHLSAT
6971 { 169, 3, 1, 0, 0, 0, 0, 43, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #169 = G_SSUBSAT
6972 { 168, 3, 1, 0, 0, 0, 0, 43, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #168 = G_USUBSAT
6973 { 167, 3, 1, 0, 0, 0, 0, 43, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #167 = G_SADDSAT
6974 { 166, 3, 1, 0, 0, 0, 0, 43, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #166 = G_UADDSAT
6975 { 165, 3, 1, 0, 0, 0, 0, 43, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #165 = G_SMULH
6976 { 164, 3, 1, 0, 0, 0, 0, 43, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #164 = G_UMULH
6977 { 163, 4, 2, 0, 0, 0, 0, 87, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #163 = G_SMULO
6978 { 162, 4, 2, 0, 0, 0, 0, 87, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #162 = G_UMULO
6979 { 161, 5, 2, 0, 0, 0, 0, 115, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #161 = G_SSUBE
6980 { 160, 4, 2, 0, 0, 0, 0, 87, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #160 = G_SSUBO
6981 { 159, 5, 2, 0, 0, 0, 0, 115, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #159 = G_SADDE
6982 { 158, 4, 2, 0, 0, 0, 0, 87, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #158 = G_SADDO
6983 { 157, 5, 2, 0, 0, 0, 0, 115, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #157 = G_USUBE
6984 { 156, 4, 2, 0, 0, 0, 0, 87, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #156 = G_USUBO
6985 { 155, 5, 2, 0, 0, 0, 0, 115, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #155 = G_UADDE
6986 { 154, 4, 2, 0, 0, 0, 0, 87, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #154 = G_UADDO
6987 { 153, 4, 1, 0, 0, 0, 0, 87, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #153 = G_SELECT
6988 { 152, 3, 1, 0, 0, 0, 0, 112, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #152 = G_UCMP
6989 { 151, 3, 1, 0, 0, 0, 0, 112, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #151 = G_SCMP
6990 { 150, 4, 1, 0, 0, 0, 0, 108, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #150 = G_FCMP
6991 { 149, 4, 1, 0, 0, 0, 0, 108, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #149 = G_ICMP
6992 { 148, 3, 1, 0, 0, 0, 0, 101, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #148 = G_ROTL
6993 { 147, 3, 1, 0, 0, 0, 0, 101, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #147 = G_ROTR
6994 { 146, 4, 1, 0, 0, 0, 0, 104, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #146 = G_FSHR
6995 { 145, 4, 1, 0, 0, 0, 0, 104, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #145 = G_FSHL
6996 { 144, 3, 1, 0, 0, 0, 0, 101, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #144 = G_ASHR
6997 { 143, 3, 1, 0, 0, 0, 0, 101, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #143 = G_LSHR
6998 { 142, 3, 1, 0, 0, 0, 0, 101, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #142 = G_SHL
6999 { 141, 2, 1, 0, 0, 0, 0, 61, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #141 = G_ZEXT
7000 { 140, 3, 1, 0, 0, 0, 0, 40, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #140 = G_SEXT_INREG
7001 { 139, 2, 1, 0, 0, 0, 0, 61, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #139 = G_SEXT
7002 { 138, 3, 1, 0, 0, 0, 0, 98, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #138 = G_VAARG
7003 { 137, 1, 0, 0, 0, 0, 0, 50, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #137 = G_VASTART
7004 { 136, 2, 1, 0, 0, 0, 0, 51, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #136 = G_FCONSTANT
7005 { 135, 2, 1, 0, 0, 0, 0, 51, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #135 = G_CONSTANT
7006 { 134, 2, 1, 0, 0, 0, 0, 61, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #134 = G_TRUNC
7007 { 133, 2, 1, 0, 0, 0, 0, 61, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #133 = G_ANYEXT
7008 { 132, 1, 0, 0, 0, 0, 0, 0, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #132 = G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
7009 { 131, 1, 0, 0, 0, 0, 0, 0, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #131 = G_INTRINSIC_CONVERGENT
7010 { 130, 1, 0, 0, 0, 0, 0, 0, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #130 = G_INTRINSIC_W_SIDE_EFFECTS
7011 { 129, 1, 0, 0, 0, 0, 0, 0, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #129 = G_INTRINSIC
7012 { 128, 0, 0, 0, 0, 0, 0, 1, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #128 = G_INVOKE_REGION_START
7013 { 127, 1, 0, 0, 0, 0, 0, 50, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #127 = G_BRINDIRECT
7014 { 126, 2, 0, 0, 0, 0, 0, 51, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #126 = G_BRCOND
7015 { 125, 4, 0, 0, 0, 0, 0, 94, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #125 = G_PREFETCH
7016 { 124, 2, 0, 0, 0, 0, 0, 21, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #124 = G_FENCE
7017 { 123, 3, 1, 0, 0, 0, 0, 91, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #123 = G_ATOMICRMW_USUB_SAT
7018 { 122, 3, 1, 0, 0, 0, 0, 91, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #122 = G_ATOMICRMW_USUB_COND
7019 { 121, 3, 1, 0, 0, 0, 0, 91, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #121 = G_ATOMICRMW_UDEC_WRAP
7020 { 120, 3, 1, 0, 0, 0, 0, 91, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #120 = G_ATOMICRMW_UINC_WRAP
7021 { 119, 3, 1, 0, 0, 0, 0, 91, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #119 = G_ATOMICRMW_FMINIMUM
7022 { 118, 3, 1, 0, 0, 0, 0, 91, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #118 = G_ATOMICRMW_FMAXIMUM
7023 { 117, 3, 1, 0, 0, 0, 0, 91, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #117 = G_ATOMICRMW_FMIN
7024 { 116, 3, 1, 0, 0, 0, 0, 91, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #116 = G_ATOMICRMW_FMAX
7025 { 115, 3, 1, 0, 0, 0, 0, 91, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #115 = G_ATOMICRMW_FSUB
7026 { 114, 3, 1, 0, 0, 0, 0, 91, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #114 = G_ATOMICRMW_FADD
7027 { 113, 3, 1, 0, 0, 0, 0, 91, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #113 = G_ATOMICRMW_UMIN
7028 { 112, 3, 1, 0, 0, 0, 0, 91, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #112 = G_ATOMICRMW_UMAX
7029 { 111, 3, 1, 0, 0, 0, 0, 91, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #111 = G_ATOMICRMW_MIN
7030 { 110, 3, 1, 0, 0, 0, 0, 91, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #110 = G_ATOMICRMW_MAX
7031 { 109, 3, 1, 0, 0, 0, 0, 91, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #109 = G_ATOMICRMW_XOR
7032 { 108, 3, 1, 0, 0, 0, 0, 91, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #108 = G_ATOMICRMW_OR
7033 { 107, 3, 1, 0, 0, 0, 0, 91, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #107 = G_ATOMICRMW_NAND
7034 { 106, 3, 1, 0, 0, 0, 0, 91, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #106 = G_ATOMICRMW_AND
7035 { 105, 3, 1, 0, 0, 0, 0, 91, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #105 = G_ATOMICRMW_SUB
7036 { 104, 3, 1, 0, 0, 0, 0, 91, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #104 = G_ATOMICRMW_ADD
7037 { 103, 3, 1, 0, 0, 0, 0, 91, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #103 = G_ATOMICRMW_XCHG
7038 { 102, 4, 1, 0, 0, 0, 0, 87, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #102 = G_ATOMIC_CMPXCHG
7039 { 101, 5, 2, 0, 0, 0, 0, 82, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #101 = G_ATOMIC_CMPXCHG_WITH_SUCCESS
7040 { 100, 5, 1, 0, 0, 0, 0, 77, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #100 = G_INDEXED_STORE
7041 { 99, 2, 0, 0, 0, 0, 0, 61, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #99 = G_STORE
7042 { 98, 5, 2, 0, 0, 0, 0, 72, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #98 = G_INDEXED_ZEXTLOAD
7043 { 97, 5, 2, 0, 0, 0, 0, 72, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #97 = G_INDEXED_SEXTLOAD
7044 { 96, 5, 2, 0, 0, 0, 0, 72, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #96 = G_INDEXED_LOAD
7045 { 95, 2, 1, 0, 0, 0, 0, 61, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #95 = G_ZEXTLOAD
7046 { 94, 2, 1, 0, 0, 0, 0, 61, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #94 = G_SEXTLOAD
7047 { 93, 2, 1, 0, 0, 0, 0, 61, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #93 = G_LOAD
7048 { 92, 1, 1, 0, 0, 0, 0, 50, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #92 = G_READSTEADYCOUNTER
7049 { 91, 1, 1, 0, 0, 0, 0, 50, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #91 = G_READCYCLECOUNTER
7050 { 90, 2, 1, 0, 0, 0, 0, 67, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #90 = G_INTRINSIC_ROUNDEVEN
7051 { 89, 2, 1, 0, 0, 0, 0, 61, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #89 = G_INTRINSIC_LLRINT
7052 { 88, 2, 1, 0, 0, 0, 0, 61, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #88 = G_INTRINSIC_LRINT
7053 { 87, 2, 1, 0, 0, 0, 0, 67, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #87 = G_INTRINSIC_ROUND
7054 { 86, 2, 1, 0, 0, 0, 0, 67, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #86 = G_INTRINSIC_TRUNC
7055 { 85, 3, 1, 0, 0, 0, 0, 69, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #85 = G_INTRINSIC_FPTRUNC_ROUND
7056 { 84, 2, 1, 0, 0, 0, 0, 67, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #84 = G_CONSTANT_FOLD_BARRIER
7057 { 83, 2, 1, 0, 0, 0, 0, 67, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #83 = G_FREEZE
7058 { 82, 2, 1, 0, 0, 0, 0, 61, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #82 = G_BITCAST
7059 { 81, 2, 1, 0, 0, 0, 0, 61, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #81 = G_INTTOPTR
7060 { 80, 2, 1, 0, 0, 0, 0, 61, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #80 = G_PTRTOINT
7061 { 79, 2, 1, 0, 0, 0, 0, 61, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #79 = G_CONCAT_VECTORS
7062 { 78, 2, 1, 0, 0, 0, 0, 61, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #78 = G_BUILD_VECTOR_TRUNC
7063 { 77, 2, 1, 0, 0, 0, 0, 61, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #77 = G_BUILD_VECTOR
7064 { 76, 2, 1, 0, 0, 0, 0, 61, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #76 = G_MERGE_VALUES
7065 { 75, 4, 1, 0, 0, 0, 0, 63, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #75 = G_INSERT
7066 { 74, 2, 1, 0, 0, 0, 0, 61, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #74 = G_UNMERGE_VALUES
7067 { 73, 3, 1, 0, 0, 0, 0, 58, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #73 = G_EXTRACT
7068 { 72, 2, 1, 0, 0, 0, 0, 51, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #72 = G_CONSTANT_POOL
7069 { 71, 5, 1, 0, 0, 0, 0, 53, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #71 = G_PTRAUTH_GLOBAL_VALUE
7070 { 70, 2, 1, 0, 0, 0, 0, 51, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #70 = G_GLOBAL_VALUE
7071 { 69, 2, 1, 0, 0, 0, 0, 51, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #69 = G_FRAME_INDEX
7072 { 68, 1, 1, 0, 0, 0, 0, 50, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #68 = G_PHI
7073 { 67, 1, 1, 0, 0, 0, 0, 50, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #67 = G_IMPLICIT_DEF
7074 { 66, 3, 1, 0, 0, 0, 0, 43, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #66 = G_ABDU
7075 { 65, 3, 1, 0, 0, 0, 0, 43, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #65 = G_ABDS
7076 { 64, 3, 1, 0, 0, 0, 0, 43, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #64 = G_XOR
7077 { 63, 3, 1, 0, 0, 0, 0, 43, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #63 = G_OR
7078 { 62, 3, 1, 0, 0, 0, 0, 43, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #62 = G_AND
7079 { 61, 4, 2, 0, 0, 0, 0, 46, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #61 = G_UDIVREM
7080 { 60, 4, 2, 0, 0, 0, 0, 46, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #60 = G_SDIVREM
7081 { 59, 3, 1, 0, 0, 0, 0, 43, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #59 = G_UREM
7082 { 58, 3, 1, 0, 0, 0, 0, 43, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #58 = G_SREM
7083 { 57, 3, 1, 0, 0, 0, 0, 43, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #57 = G_UDIV
7084 { 56, 3, 1, 0, 0, 0, 0, 43, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #56 = G_SDIV
7085 { 55, 3, 1, 0, 0, 0, 0, 43, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #55 = G_MUL
7086 { 54, 3, 1, 0, 0, 0, 0, 43, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #54 = G_SUB
7087 { 53, 3, 1, 0, 0, 0, 0, 43, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #53 = G_ADD
7088 { 52, 3, 1, 0, 0, 0, 0, 40, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #52 = G_ASSERT_ALIGN
7089 { 51, 3, 1, 0, 0, 0, 0, 40, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #51 = G_ASSERT_ZEXT
7090 { 50, 3, 1, 0, 0, 0, 0, 40, HexagonImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #50 = G_ASSERT_SEXT
7091 { 49, 1, 0, 0, 0, 0, 0, 0, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #49 = CONVERGENCECTRL_GLUE
7092 { 48, 2, 1, 0, 0, 0, 0, 13, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #48 = CONVERGENCECTRL_LOOP
7093 { 47, 1, 1, 0, 0, 0, 0, 0, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #47 = CONVERGENCECTRL_ANCHOR
7094 { 46, 1, 1, 0, 0, 0, 0, 0, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #46 = CONVERGENCECTRL_ENTRY
7095 { 45, 1, 0, 0, 0, 0, 0, 1, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // Inst #45 = JUMP_TABLE_DEBUG_INFO
7096 { 44, 0, 0, 0, 0, 0, 0, 1, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #44 = MEMBARRIER
7097 { 43, 0, 0, 0, 0, 0, 0, 1, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #43 = FAKE_USE
7098 { 42, 0, 0, 0, 0, 0, 0, 1, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #42 = ICALL_BRANCH_FUNNEL
7099 { 41, 3, 0, 0, 0, 0, 0, 37, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #41 = PATCHABLE_TYPED_EVENT_CALL
7100 { 40, 2, 0, 0, 0, 0, 0, 35, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #40 = PATCHABLE_EVENT_CALL
7101 { 39, 0, 0, 0, 0, 0, 0, 1, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #39 = PATCHABLE_TAIL_CALL
7102 { 38, 0, 0, 0, 0, 0, 0, 1, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #38 = PATCHABLE_FUNCTION_EXIT
7103 { 37, 0, 0, 0, 0, 0, 0, 1, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #37 = PATCHABLE_RET
7104 { 36, 0, 0, 0, 0, 0, 0, 1, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #36 = PATCHABLE_FUNCTION_ENTER
7105 { 35, 0, 0, 0, 0, 0, 0, 1, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #35 = PATCHABLE_OP
7106 { 34, 1, 1, 0, 0, 0, 0, 0, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #34 = FAULTING_OP
7107 { 33, 2, 0, 0, 0, 0, 0, 33, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #33 = LOCAL_ESCAPE
7108 { 32, 0, 0, 0, 0, 0, 0, 1, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #32 = STATEPOINT
7109 { 31, 3, 1, 0, 0, 0, 0, 30, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #31 = PREALLOCATED_ARG
7110 { 30, 1, 0, 0, 0, 0, 0, 1, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #30 = PREALLOCATED_SETUP
7111 { 29, 1, 1, 0, 0, 0, 0, 29, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL }, // Inst #29 = LOAD_STACK_GUARD
7112 { 28, 6, 1, 0, 0, 0, 0, 23, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #28 = PATCHPOINT
7113 { 27, 0, 0, 0, 0, 0, 0, 1, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #27 = FENTRY_CALL
7114 { 26, 2, 0, 0, 0, 0, 0, 21, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #26 = STACKMAP
7115 { 25, 2, 1, 0, 0, 0, 0, 19, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // Inst #25 = ARITH_FENCE
7116 { 24, 4, 0, 0, 0, 0, 0, 15, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #24 = PSEUDO_PROBE
7117 { 23, 1, 0, 0, 0, 0, 0, 1, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // Inst #23 = LIFETIME_END
7118 { 22, 1, 0, 0, 0, 0, 0, 1, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // Inst #22 = LIFETIME_START
7119 { 21, 0, 0, 0, 0, 0, 0, 1, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #21 = BUNDLE
7120 { 20, 2, 1, 0, 0, 0, 0, 13, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #20 = COPY
7121 { 19, 2, 1, 0, 0, 0, 0, 13, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #19 = REG_SEQUENCE
7122 { 18, 1, 0, 0, 0, 0, 0, 0, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // Inst #18 = DBG_LABEL
7123 { 17, 0, 0, 0, 0, 0, 0, 1, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #17 = DBG_PHI
7124 { 16, 0, 0, 0, 0, 0, 0, 1, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #16 = DBG_INSTR_REF
7125 { 15, 0, 0, 0, 0, 0, 0, 1, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #15 = DBG_VALUE_LIST
7126 { 14, 0, 0, 0, 0, 0, 0, 1, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #14 = DBG_VALUE
7127 { 13, 3, 1, 0, 0, 0, 0, 2, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #13 = COPY_TO_REGCLASS
7128 { 12, 4, 1, 0, 0, 0, 0, 9, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #12 = SUBREG_TO_REG
7129 { 11, 1, 1, 0, 0, 0, 0, 0, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #11 = INIT_UNDEF
7130 { 10, 1, 1, 0, 0, 0, 0, 0, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #10 = IMPLICIT_DEF
7131 { 9, 4, 1, 0, 0, 0, 0, 5, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #9 = INSERT_SUBREG
7132 { 8, 3, 1, 0, 0, 0, 0, 2, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #8 = EXTRACT_SUBREG
7133 { 7, 0, 0, 0, 0, 0, 0, 1, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #7 = KILL
7134 { 6, 1, 0, 0, 0, 0, 0, 1, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // Inst #6 = ANNOTATION_LABEL
7135 { 5, 1, 0, 0, 0, 0, 0, 1, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // Inst #5 = GC_LABEL
7136 { 4, 1, 0, 0, 0, 0, 0, 1, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // Inst #4 = EH_LABEL
7137 { 3, 1, 0, 0, 0, 0, 0, 1, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // Inst #3 = CFI_INSTRUCTION
7138 { 2, 0, 0, 0, 0, 0, 0, 1, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2 = INLINEASM_BR
7139 { 1, 0, 0, 0, 0, 0, 0, 1, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #1 = INLINEASM
7140 { 0, 1, 1, 0, 0, 0, 0, 0, HexagonImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #0 = PHI
7141 }, {
7142 /* 0 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7143 /* 1 */
7144 /* 1 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
7145 /* 2 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
7146 /* 5 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
7147 /* 9 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
7148 /* 13 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7149 /* 15 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
7150 /* 19 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) },
7151 /* 21 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
7152 /* 23 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
7153 /* 29 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 },
7154 /* 30 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
7155 /* 33 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
7156 /* 35 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7157 /* 37 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7158 /* 40 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
7159 /* 43 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
7160 /* 46 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
7161 /* 50 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
7162 /* 51 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7163 /* 53 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
7164 /* 58 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
7165 /* 61 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
7166 /* 63 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
7167 /* 67 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
7168 /* 69 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
7169 /* 72 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7170 /* 77 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7171 /* 82 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
7172 /* 87 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
7173 /* 91 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
7174 /* 94 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
7175 /* 98 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7176 /* 101 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
7177 /* 104 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
7178 /* 108 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
7179 /* 112 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
7180 /* 115 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
7181 /* 120 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
7182 /* 124 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
7183 /* 127 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
7184 /* 131 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
7185 /* 134 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7186 /* 138 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
7187 /* 142 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
7188 /* 144 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
7189 /* 148 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
7190 /* 152 */ { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7191 /* 155 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7192 /* 157 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7193 /* 159 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7194 /* 162 */ { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7195 /* 164 */ { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7196 /* 167 */ { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7197 /* 169 */ { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7198 /* 172 */ { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7199 /* 175 */ { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7200 /* 178 */ { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7201 /* 181 */ { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7202 /* 183 */ { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7203 /* 185 */ { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7204 /* 187 */ { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7205 /* 190 */ { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7206 /* 192 */ { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7207 /* 195 */ { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7208 /* 196 */ { Hexagon::CtrRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7209 /* 199 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7210 /* 202 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7211 /* 205 */ { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7212 /* 209 */ { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7213 /* 212 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7214 /* 215 */ { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7215 /* 219 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7216 /* 223 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7217 /* 229 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7218 /* 234 */ { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7219 /* 240 */ { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7220 /* 245 */ { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7221 /* 249 */ { Hexagon::HvxQRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7222 /* 250 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7223 /* 256 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7224 /* 261 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7225 /* 267 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7226 /* 272 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7227 /* 273 */ { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7228 /* 274 */ { Hexagon::HvxQRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7229 /* 277 */ { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7230 /* 280 */ { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7231 /* 283 */ { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7232 /* 287 */ { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7233 /* 289 */ { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7234 /* 291 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::HvxQRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7235 /* 294 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7236 /* 297 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7237 /* 300 */ { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7238 /* 304 */ { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7239 /* 307 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7240 /* 309 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7241 /* 314 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7242 /* 317 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::CtrRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7243 /* 320 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7244 /* 323 */ { Hexagon::HvxQRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7245 /* 326 */ { Hexagon::HvxQRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxQRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7246 /* 330 */ { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7247 /* 332 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7248 /* 334 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7249 /* 337 */ { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7250 /* 339 */ { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7251 /* 342 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7252 /* 344 */ { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7253 /* 347 */ { Hexagon::HvxQRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7254 /* 350 */ { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7255 /* 354 */ { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7256 /* 359 */ { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7257 /* 361 */ { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7258 /* 364 */ { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7259 /* 367 */ { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxQRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7260 /* 371 */ { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7261 /* 375 */ { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7262 /* 378 */ { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Hexagon::HvxQRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7263 /* 382 */ { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxQRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7264 /* 385 */ { Hexagon::HvxQRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxQRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7265 /* 389 */ { Hexagon::HvxQRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7266 /* 392 */ { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7267 /* 396 */ { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7268 /* 399 */ { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7269 /* 401 */ { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7270 /* 402 */ { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7271 /* 406 */ { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7272 /* 409 */ { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7273 /* 413 */ { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7274 /* 416 */ { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7275 /* 420 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7276 /* 425 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::HvxQRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7277 /* 431 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7278 /* 436 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::HvxQRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7279 /* 442 */ { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7280 /* 446 */ { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7281 /* 449 */ { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7282 /* 453 */ { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7283 /* 456 */ { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7284 /* 461 */ { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7285 /* 465 */ { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7286 /* 467 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7287 /* 471 */ { Hexagon::HvxQRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7288 /* 476 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7289 /* 480 */ { Hexagon::HvxQRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7290 /* 485 */ { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7291 /* 490 */ { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7292 /* 493 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
7293 /* 495 */ { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7294 /* 498 */ { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7295 /* 501 */ { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7296 /* 504 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7297 /* 507 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7298 /* 510 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7299 /* 513 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7300 /* 516 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7301 /* 519 */ { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7302 /* 522 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7303 /* 526 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7304 /* 530 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::CtrRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7305 /* 532 */ { Hexagon::CtrRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7306 /* 534 */ { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7307 /* 537 */ { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) },
7308 /* 542 */ { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::CtrRegs64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7309 /* 544 */ { Hexagon::CtrRegs64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7310 /* 546 */ { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7311 /* 549 */ { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7312 /* 552 */ { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7313 /* 557 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7314 /* 560 */ { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7315 /* 563 */ { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7316 /* 567 */ { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7317 /* 569 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7318 /* 573 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7319 /* 577 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7320 /* 579 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7321 /* 582 */ { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7322 /* 586 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
7323 /* 588 */ { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
7324 /* 590 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7325 /* 594 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7326 /* 599 */ { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::GuestRegs64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7327 /* 601 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::GuestRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7328 /* 603 */ { Hexagon::GuestRegs64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7329 /* 605 */ { Hexagon::GuestRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7330 /* 607 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7331 /* 609 */ { Hexagon::GeneralSubRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::GeneralSubRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7332 /* 612 */ { Hexagon::GeneralSubRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7333 /* 615 */ { Hexagon::GeneralSubRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7334 /* 617 */ { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7335 /* 621 */ { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7336 /* 626 */ { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7337 /* 632 */ { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7338 /* 637 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7339 /* 641 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7340 /* 646 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7341 /* 650 */ { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7342 /* 654 */ { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7343 /* 659 */ { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7344 /* 663 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7345 /* 668 */ { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7346 /* 672 */ { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7347 /* 677 */ { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7348 /* 681 */ { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7349 /* 686 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7350 /* 690 */ { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7351 /* 694 */ { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7352 /* 698 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7353 /* 703 */ { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7354 /* 706 */ { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7355 /* 711 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7356 /* 714 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7357 /* 718 */ { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7358 /* 722 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7359 /* 726 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7360 /* 730 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7361 /* 734 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7362 /* 738 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7363 /* 740 */ { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7364 /* 744 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7365 /* 747 */ { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7366 /* 751 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7367 /* 755 */ { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7368 /* 760 */ { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7369 /* 764 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7370 /* 769 */ { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7371 /* 773 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7372 /* 778 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7373 /* 782 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7374 /* 787 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7375 /* 791 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7376 /* 795 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7377 /* 800 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7378 /* 804 */ { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7379 /* 808 */ { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7380 /* 812 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7381 /* 816 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7382 /* 820 */ { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7383 /* 823 */ { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7384 /* 828 */ { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7385 /* 831 */ { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7386 /* 836 */ { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7387 /* 840 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7388 /* 844 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7389 /* 848 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7390 /* 852 */ { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7391 /* 856 */ { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7392 /* 861 */ { Hexagon::GeneralSubRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::GeneralSubRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7393 /* 864 */ { Hexagon::GeneralSubRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::GeneralSubRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Hexagon::GeneralSubRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7394 /* 867 */ { Hexagon::GeneralSubRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::GeneralSubRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7395 /* 869 */ { Hexagon::GeneralSubRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7396 /* 870 */ { Hexagon::GeneralDoubleLow8RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7397 /* 872 */ { Hexagon::GeneralDoubleLow8RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::GeneralSubRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7398 /* 874 */ { Hexagon::GeneralSubRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::GeneralSubRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7399 /* 877 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::GeneralDoubleLow8RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7400 /* 879 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::GeneralSubRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7401 /* 881 */ { Hexagon::HvxQRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxQRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxQRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7402 /* 884 */ { Hexagon::HvxQRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxQRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7403 /* 886 */ { Hexagon::HvxQRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7404 /* 888 */ { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7405 /* 892 */ { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7406 /* 896 */ { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7407 /* 900 */ { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7408 /* 905 */ { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7409 /* 910 */ { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7410 /* 914 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7411 /* 919 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7412 /* 924 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7413 /* 928 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7414 /* 932 */ { Hexagon::HvxQRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7415 /* 936 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxQRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7416 /* 941 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxQRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7417 /* 946 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7418 /* 949 */ { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxQRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxQRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) },
7419 /* 954 */ { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxQRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7420 /* 958 */ { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxQRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7421 /* 962 */ { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsLow8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7422 /* 966 */ { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7423 /* 970 */ { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxQRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7424 /* 973 */ { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7425 /* 976 */ { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7426 /* 980 */ { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7427 /* 983 */ { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsLow8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7428 /* 987 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7429 /* 990 */ { Hexagon::HvxQRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7430 /* 994 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7431 /* 997 */ { Hexagon::HvxQRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7432 /* 1001 */ { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7433 /* 1004 */ { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7434 /* 1007 */ { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsLow8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7435 /* 1012 */ { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7436 /* 1017 */ { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsLow8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7437 /* 1022 */ { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7438 /* 1027 */ { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7439 /* 1031 */ { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7440 /* 1035 */ { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxQRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7441 /* 1037 */ { Hexagon::HvxVQRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsLow8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7442 /* 1040 */ { Hexagon::HvxVQRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVQRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsLow8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7443 /* 1044 */ { Hexagon::HvxVQRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsLow8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsLow8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) },
7444 /* 1048 */ { Hexagon::HvxVQRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsLow8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVQRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsLow8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) },
7445 /* 1053 */ { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxQRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7446 /* 1057 */ { Hexagon::HvxQRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7447 /* 1059 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7448 /* 1063 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7449 /* 1067 */ { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::SysRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7450 /* 1069 */ { Hexagon::SysRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7451 /* 1071 */ { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
7452 /* 1074 */ { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::SysRegs64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7453 /* 1076 */ { Hexagon::SysRegs64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7454 /* 1078 */ { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
7455 }, {
7456 /* 0 */
7457 /* 0 */ Hexagon::R31, Hexagon::R30, Hexagon::R29, Hexagon::R29, Hexagon::R30,
7458 /* 5 */ Hexagon::R29, Hexagon::R29, Hexagon::R30, Hexagon::R31,
7459 /* 9 */ Hexagon::SA0, Hexagon::LC0, Hexagon::PC, Hexagon::LC0,
7460 /* 13 */ Hexagon::SA0, Hexagon::SA1, Hexagon::LC0, Hexagon::LC1, Hexagon::PC, Hexagon::LC0, Hexagon::LC1,
7461 /* 20 */ Hexagon::SA1, Hexagon::LC1, Hexagon::PC, Hexagon::LC1,
7462 /* 24 */ Hexagon::LC0, Hexagon::SA0, Hexagon::LC0, Hexagon::P3, Hexagon::PC, Hexagon::USR,
7463 /* 30 */ Hexagon::LC0, Hexagon::LC1, Hexagon::SA0, Hexagon::SA1, Hexagon::LC0, Hexagon::LC1, Hexagon::P3, Hexagon::PC, Hexagon::USR,
7464 /* 39 */ Hexagon::LC1, Hexagon::SA1, Hexagon::LC1, Hexagon::PC,
7465 /* 43 */ Hexagon::R30,
7466 /* 44 */ Hexagon::R29,
7467 /* 45 */ Hexagon::R0, Hexagon::R14, Hexagon::R15, Hexagon::R28, Hexagon::R29, Hexagon::R30, Hexagon::R31, Hexagon::PC,
7468 /* 53 */ Hexagon::CS, Hexagon::CS,
7469 /* 55 */ Hexagon::PC,
7470 /* 56 */ Hexagon::FRAMEKEY, Hexagon::R29,
7471 /* 58 */ Hexagon::FRAMEKEY, Hexagon::FRAMELIMIT, Hexagon::R30, Hexagon::R31, Hexagon::R30,
7472 /* 63 */ Hexagon::USR_OVF,
7473 /* 64 */ Hexagon::R16,
7474 /* 65 */ Hexagon::R28, Hexagon::PC,
7475 /* 67 */ Hexagon::USR,
7476 /* 68 */ Hexagon::R29, Hexagon::PC, Hexagon::R31,
7477 /* 71 */ Hexagon::PC, Hexagon::R31,
7478 /* 73 */ Hexagon::LC0, Hexagon::SA0, Hexagon::USR,
7479 /* 76 */ Hexagon::SA0, Hexagon::LC0, Hexagon::USR,
7480 /* 79 */ Hexagon::SA1, Hexagon::LC1,
7481 /* 81 */ Hexagon::LC1, Hexagon::SA1,
7482 /* 83 */ Hexagon::LC0, Hexagon::P3, Hexagon::SA0, Hexagon::USR,
7483 /* 87 */ Hexagon::ELR, Hexagon::PC,
7484 /* 89 */ Hexagon::CCR, Hexagon::GOSP, Hexagon::CCR, Hexagon::GOSP, Hexagon::PC,
7485 /* 94 */ Hexagon::P0, Hexagon::P0, Hexagon::PC,
7486 /* 97 */ Hexagon::P1, Hexagon::P1, Hexagon::PC,
7487 /* 100 */ Hexagon::CS,
7488 /* 101 */ Hexagon::GP,
7489 /* 102 */ Hexagon::FRAMEKEY, Hexagon::PC, Hexagon::R29,
7490 /* 105 */ Hexagon::PC, Hexagon::R31, Hexagon::R6, Hexagon::R7, Hexagon::P0,
7491 /* 110 */ Hexagon::R29, Hexagon::R30, Hexagon::R31, Hexagon::PC,
7492 /* 114 */ Hexagon::R14, Hexagon::R15, Hexagon::R28, Hexagon::R29, Hexagon::R30, Hexagon::R31, Hexagon::PC,
7493 /* 121 */ Hexagon::P0,
7494 /* 122 */ Hexagon::R29, Hexagon::R31,
7495 /* 124 */ Hexagon::R29, Hexagon::R31, Hexagon::P0,
7496 /* 127 */ Hexagon::R29, Hexagon::R31, Hexagon::R14, Hexagon::R15, Hexagon::R28, Hexagon::P0,
7497 /* 133 */ Hexagon::R29, Hexagon::R31, Hexagon::R14, Hexagon::R15, Hexagon::R28,
7498 /* 138 */ Hexagon::FRAMEKEY, Hexagon::R30, Hexagon::R29, Hexagon::R30, Hexagon::R31,
7499 /* 143 */ Hexagon::R31, Hexagon::PC,
7500 /* 145 */ Hexagon::P0, Hexagon::R31, Hexagon::PC,
7501 /* 148 */ Hexagon::FRAMEKEY, Hexagon::R30, Hexagon::PC, Hexagon::R29, Hexagon::R30, Hexagon::R31,
7502 /* 154 */ Hexagon::FRAMEKEY, Hexagon::P0, Hexagon::R30, Hexagon::PC, Hexagon::R29, Hexagon::R30, Hexagon::R31,
7503 /* 161 */ Hexagon::FRAMEKEY, Hexagon::FRAMELIMIT, Hexagon::R29, Hexagon::R30, Hexagon::R31, Hexagon::R29, Hexagon::R30,
7504 /* 168 */ Hexagon::VTMP,
7505 /* 169 */ Hexagon::SGP0, Hexagon::SGP0,
7506 /* 171 */ Hexagon::SGP1, Hexagon::SGP1,
7507 /* 173 */ Hexagon::SGP0, Hexagon::SGP1, Hexagon::SGP0, Hexagon::SGP1,
7508 }
7509};
7510
7511
7512#ifdef __GNUC__
7513#pragma GCC diagnostic push
7514#pragma GCC diagnostic ignored "-Woverlength-strings"
7515#endif
7516extern const char HexagonInstrNameData[] = {
7517 /* 0 */ "G_FLOG10\000"
7518 /* 9 */ "G_FEXP10\000"
7519 /* 18 */ "Y4_crswap10\000"
7520 /* 30 */ "V6_v6mpyhubs10\000"
7521 /* 45 */ "V6_v6mpyvubs10\000"
7522 /* 60 */ "V6_v10mpyubs10\000"
7523 /* 75 */ "ENDLOOP0\000"
7524 /* 84 */ "V6_vdd0\000"
7525 /* 92 */ "PS_vdd0\000"
7526 /* 100 */ "V6_ld0\000"
7527 /* 107 */ "V6_dbl_ld0\000"
7528 /* 118 */ "V6_zld0\000"
7529 /* 126 */ "V6_vd0\000"
7530 /* 133 */ "Y6_diag0\000"
7531 /* 142 */ "SS2_storebi0\000"
7532 /* 155 */ "SS2_storewi0\000"
7533 /* 168 */ "S2_cl0\000"
7534 /* 175 */ "V6_stn0\000"
7535 /* 183 */ "J2_trap0\000"
7536 /* 192 */ "Y2_crswap0\000"
7537 /* 203 */ "V6_ldcp0\000"
7538 /* 212 */ "V6_ldp0\000"
7539 /* 220 */ "V6_zldp0\000"
7540 /* 229 */ "V6_ldcnp0\000"
7541 /* 239 */ "V6_ldnp0\000"
7542 /* 248 */ "V6_ldtnp0\000"
7543 /* 258 */ "V6_stnp0\000"
7544 /* 267 */ "V6_stunp0\000"
7545 /* 277 */ "J2_endloop0\000"
7546 /* 289 */ "V6_ldtp0\000"
7547 /* 298 */ "V6_stp0\000"
7548 /* 306 */ "V6_stup0\000"
7549 /* 315 */ "V6_stnq0\000"
7550 /* 324 */ "V6_stq0\000"
7551 /* 332 */ "M2_vrmac_s0\000"
7552 /* 344 */ "M2_dpmpyss_nac_s0\000"
7553 /* 362 */ "M2_dpmpyuu_nac_s0\000"
7554 /* 380 */ "M4_vrmpyeh_acc_s0\000"
7555 /* 398 */ "M4_vrmpyoh_acc_s0\000"
7556 /* 416 */ "M2_dpmpyss_acc_s0\000"
7557 /* 434 */ "M2_dpmpyuu_acc_s0\000"
7558 /* 452 */ "M2_cmacsc_s0\000"
7559 /* 465 */ "M2_cnacsc_s0\000"
7560 /* 478 */ "M2_cmpyrsc_s0\000"
7561 /* 492 */ "M2_cmpysc_s0\000"
7562 /* 505 */ "M2_dpmpyss_rnd_s0\000"
7563 /* 523 */ "M4_vrmpyeh_s0\000"
7564 /* 537 */ "M2_mpyud_nac_hh_s0\000"
7565 /* 556 */ "M2_mpyd_nac_hh_s0\000"
7566 /* 574 */ "M2_mpyu_nac_hh_s0\000"
7567 /* 592 */ "M2_mpy_nac_hh_s0\000"
7568 /* 609 */ "M2_mpyud_acc_hh_s0\000"
7569 /* 628 */ "M2_mpyd_acc_hh_s0\000"
7570 /* 646 */ "M2_mpyu_acc_hh_s0\000"
7571 /* 664 */ "M2_mpy_acc_hh_s0\000"
7572 /* 681 */ "M2_mpyd_rnd_hh_s0\000"
7573 /* 699 */ "M2_mpy_sat_rnd_hh_s0\000"
7574 /* 720 */ "M2_mpy_rnd_hh_s0\000"
7575 /* 737 */ "M2_mpyud_hh_s0\000"
7576 /* 752 */ "M2_mpyd_hh_s0\000"
7577 /* 766 */ "M2_mpy_nac_sat_hh_s0\000"
7578 /* 787 */ "M2_mpy_acc_sat_hh_s0\000"
7579 /* 808 */ "M2_mpy_sat_hh_s0\000"
7580 /* 825 */ "M2_mpyu_hh_s0\000"
7581 /* 839 */ "M2_mpy_hh_s0\000"
7582 /* 852 */ "M2_mpyud_nac_lh_s0\000"
7583 /* 871 */ "M2_mpyd_nac_lh_s0\000"
7584 /* 889 */ "M2_mpyu_nac_lh_s0\000"
7585 /* 907 */ "M2_mpy_nac_lh_s0\000"
7586 /* 924 */ "M2_mpyud_acc_lh_s0\000"
7587 /* 943 */ "M2_mpyd_acc_lh_s0\000"
7588 /* 961 */ "M2_mpyu_acc_lh_s0\000"
7589 /* 979 */ "M2_mpy_acc_lh_s0\000"
7590 /* 996 */ "M2_mpyd_rnd_lh_s0\000"
7591 /* 1014 */ "M2_mpy_sat_rnd_lh_s0\000"
7592 /* 1035 */ "M2_mpy_rnd_lh_s0\000"
7593 /* 1052 */ "M2_mpyud_lh_s0\000"
7594 /* 1067 */ "M2_mpyd_lh_s0\000"
7595 /* 1081 */ "M2_mpy_nac_sat_lh_s0\000"
7596 /* 1102 */ "M2_mpy_acc_sat_lh_s0\000"
7597 /* 1123 */ "M2_mpy_sat_lh_s0\000"
7598 /* 1140 */ "M2_mpyu_lh_s0\000"
7599 /* 1154 */ "M2_mpy_lh_s0\000"
7600 /* 1167 */ "M4_vrmpyoh_s0\000"
7601 /* 1181 */ "M2_mmpyuh_s0\000"
7602 /* 1194 */ "M2_mmpyh_s0\000"
7603 /* 1206 */ "M2_cmaci_s0\000"
7604 /* 1218 */ "M2_vrcmaci_s0\000"
7605 /* 1232 */ "M2_cmpyi_s0\000"
7606 /* 1244 */ "M2_vrcmpyi_s0\000"
7607 /* 1258 */ "M2_mpyud_nac_hl_s0\000"
7608 /* 1277 */ "M2_mpyd_nac_hl_s0\000"
7609 /* 1295 */ "M2_mpyu_nac_hl_s0\000"
7610 /* 1313 */ "M2_mpy_nac_hl_s0\000"
7611 /* 1330 */ "M2_mpyud_acc_hl_s0\000"
7612 /* 1349 */ "M2_mpyd_acc_hl_s0\000"
7613 /* 1367 */ "M2_mpyu_acc_hl_s0\000"
7614 /* 1385 */ "M2_mpy_acc_hl_s0\000"
7615 /* 1402 */ "M2_mpyd_rnd_hl_s0\000"
7616 /* 1420 */ "M2_mpy_sat_rnd_hl_s0\000"
7617 /* 1441 */ "M2_mpy_rnd_hl_s0\000"
7618 /* 1458 */ "M2_mpyud_hl_s0\000"
7619 /* 1473 */ "M2_mpyd_hl_s0\000"
7620 /* 1487 */ "M2_mpy_nac_sat_hl_s0\000"
7621 /* 1508 */ "M2_mpy_acc_sat_hl_s0\000"
7622 /* 1529 */ "M2_mpy_sat_hl_s0\000"
7623 /* 1546 */ "M2_mpyu_hl_s0\000"
7624 /* 1560 */ "M2_mpy_hl_s0\000"
7625 /* 1573 */ "M2_mpyud_nac_ll_s0\000"
7626 /* 1592 */ "M2_mpyd_nac_ll_s0\000"
7627 /* 1610 */ "M2_mpyu_nac_ll_s0\000"
7628 /* 1628 */ "M2_mpy_nac_ll_s0\000"
7629 /* 1645 */ "M2_mpyud_acc_ll_s0\000"
7630 /* 1664 */ "M2_mpyd_acc_ll_s0\000"
7631 /* 1682 */ "M2_mpyu_acc_ll_s0\000"
7632 /* 1700 */ "M2_mpy_acc_ll_s0\000"
7633 /* 1717 */ "M2_mpyd_rnd_ll_s0\000"
7634 /* 1735 */ "M2_mpy_sat_rnd_ll_s0\000"
7635 /* 1756 */ "M2_mpy_rnd_ll_s0\000"
7636 /* 1773 */ "M2_mpyud_ll_s0\000"
7637 /* 1788 */ "M2_mpyd_ll_s0\000"
7638 /* 1802 */ "M2_mpy_nac_sat_ll_s0\000"
7639 /* 1823 */ "M2_mpy_acc_sat_ll_s0\000"
7640 /* 1844 */ "M2_mpy_sat_ll_s0\000"
7641 /* 1861 */ "M2_mpyu_ll_s0\000"
7642 /* 1875 */ "M2_mpy_ll_s0\000"
7643 /* 1888 */ "M2_mmpyul_s0\000"
7644 /* 1901 */ "M2_mmpyl_s0\000"
7645 /* 1913 */ "M2_cmacr_s0\000"
7646 /* 1925 */ "M2_vrcmacr_s0\000"
7647 /* 1939 */ "M2_cmpyr_s0\000"
7648 /* 1951 */ "M2_vrcmpyr_s0\000"
7649 /* 1965 */ "M2_vmac2s_s0\000"
7650 /* 1978 */ "M2_vmpy2s_s0\000"
7651 /* 1991 */ "M2_cmacs_s0\000"
7652 /* 2003 */ "M2_vdmacs_s0\000"
7653 /* 2016 */ "M2_cnacs_s0\000"
7654 /* 2028 */ "M2_vmac2es_s0\000"
7655 /* 2042 */ "M2_vmpy2es_s0\000"
7656 /* 2056 */ "M2_mmachs_s0\000"
7657 /* 2069 */ "M2_mmacuhs_s0\000"
7658 /* 2083 */ "M2_mmacls_s0\000"
7659 /* 2096 */ "M2_mmaculs_s0\000"
7660 /* 2110 */ "M2_cmpyrs_s0\000"
7661 /* 2123 */ "M2_vdmpyrs_s0\000"
7662 /* 2137 */ "M2_dpmpyss_s0\000"
7663 /* 2151 */ "M2_cmpys_s0\000"
7664 /* 2163 */ "M2_vdmpys_s0\000"
7665 /* 2176 */ "M2_vmac2su_s0\000"
7666 /* 2190 */ "M2_vmpy2su_s0\000"
7667 /* 2204 */ "M2_dpmpyuu_s0\000"
7668 /* 2218 */ "M2_vrmpy_s0\000"
7669 /* 2230 */ "M2_mmpyuh_rs0\000"
7670 /* 2244 */ "M2_mmpyh_rs0\000"
7671 /* 2257 */ "M2_mmpyul_rs0\000"
7672 /* 2271 */ "M2_mmpyl_rs0\000"
7673 /* 2284 */ "M2_mmachs_rs0\000"
7674 /* 2298 */ "M2_mmacuhs_rs0\000"
7675 /* 2313 */ "M2_mmacls_rs0\000"
7676 /* 2327 */ "M2_mmaculs_rs0\000"
7677 /* 2342 */ "DuplexIClass0\000"
7678 /* 2356 */ "S2_ct0\000"
7679 /* 2363 */ "V6_ldnt0\000"
7680 /* 2372 */ "V6_stnnt0\000"
7681 /* 2382 */ "V6_ldcpnt0\000"
7682 /* 2393 */ "V6_ldpnt0\000"
7683 /* 2403 */ "V6_ldcnpnt0\000"
7684 /* 2415 */ "V6_ldnpnt0\000"
7685 /* 2426 */ "V6_ldtnpnt0\000"
7686 /* 2438 */ "V6_stnpnt0\000"
7687 /* 2449 */ "V6_ldtpnt0\000"
7688 /* 2460 */ "V6_stpnt0\000"
7689 /* 2470 */ "V6_stnqnt0\000"
7690 /* 2481 */ "V6_stqnt0\000"
7691 /* 2491 */ "V6_stnt0\000"
7692 /* 2500 */ "V6_st0\000"
7693 /* 2507 */ "V6_dbl_st0\000"
7694 /* 2518 */ "V6_ldu0\000"
7695 /* 2526 */ "V6_stu0\000"
7696 /* 2534 */ "ENDLOOP01\000"
7697 /* 2544 */ "J2_endloop01\000"
7698 /* 2557 */ "SL2_jumpr31\000"
7699 /* 2569 */ "ENDLOOP1\000"
7700 /* 2578 */ "SA1_and1\000"
7701 /* 2587 */ "Y6_diag1\000"
7702 /* 2596 */ "SS2_storebi1\000"
7703 /* 2609 */ "SS2_storewi1\000"
7704 /* 2622 */ "S2_cl1\000"
7705 /* 2629 */ "SA1_setin1\000"
7706 /* 2640 */ "J2_trap1\000"
7707 /* 2649 */ "PS_trap1\000"
7708 /* 2658 */ "Y4_crswap1\000"
7709 /* 2669 */ "J2_endloop1\000"
7710 /* 2681 */ "M4_vrmpyeh_acc_s1\000"
7711 /* 2699 */ "M4_vrmpyoh_acc_s1\000"
7712 /* 2717 */ "M2_vrcmpys_acc_s1\000"
7713 /* 2735 */ "M2_cmacsc_s1\000"
7714 /* 2748 */ "M2_cnacsc_s1\000"
7715 /* 2761 */ "M2_cmpyrsc_s1\000"
7716 /* 2775 */ "M2_cmpysc_s1\000"
7717 /* 2788 */ "M4_vrmpyeh_s1\000"
7718 /* 2802 */ "M2_mpyud_nac_hh_s1\000"
7719 /* 2821 */ "M2_mpyd_nac_hh_s1\000"
7720 /* 2839 */ "M2_mpyu_nac_hh_s1\000"
7721 /* 2857 */ "M2_mpy_nac_hh_s1\000"
7722 /* 2874 */ "M2_mpyud_acc_hh_s1\000"
7723 /* 2893 */ "M2_mpyd_acc_hh_s1\000"
7724 /* 2911 */ "M2_mpyu_acc_hh_s1\000"
7725 /* 2929 */ "M2_mpy_acc_hh_s1\000"
7726 /* 2946 */ "M2_mpyd_rnd_hh_s1\000"
7727 /* 2964 */ "M2_mpy_sat_rnd_hh_s1\000"
7728 /* 2985 */ "M2_mpy_rnd_hh_s1\000"
7729 /* 3002 */ "M2_mpyud_hh_s1\000"
7730 /* 3017 */ "M2_mpyd_hh_s1\000"
7731 /* 3031 */ "M2_mpy_nac_sat_hh_s1\000"
7732 /* 3052 */ "M2_mpy_acc_sat_hh_s1\000"
7733 /* 3073 */ "M2_mpy_sat_hh_s1\000"
7734 /* 3090 */ "M2_mpyu_hh_s1\000"
7735 /* 3104 */ "M2_mpy_hh_s1\000"
7736 /* 3117 */ "M2_mpyud_nac_lh_s1\000"
7737 /* 3136 */ "M2_mpyd_nac_lh_s1\000"
7738 /* 3154 */ "M2_mpyu_nac_lh_s1\000"
7739 /* 3172 */ "M2_mpy_nac_lh_s1\000"
7740 /* 3189 */ "M2_mpyud_acc_lh_s1\000"
7741 /* 3208 */ "M2_mpyd_acc_lh_s1\000"
7742 /* 3226 */ "M2_mpyu_acc_lh_s1\000"
7743 /* 3244 */ "M2_mpy_acc_lh_s1\000"
7744 /* 3261 */ "M2_mpyd_rnd_lh_s1\000"
7745 /* 3279 */ "M2_mpy_sat_rnd_lh_s1\000"
7746 /* 3300 */ "M2_mpy_rnd_lh_s1\000"
7747 /* 3317 */ "M2_mpyud_lh_s1\000"
7748 /* 3332 */ "M2_mpyd_lh_s1\000"
7749 /* 3346 */ "M2_mpy_nac_sat_lh_s1\000"
7750 /* 3367 */ "M2_mpy_acc_sat_lh_s1\000"
7751 /* 3388 */ "M2_mpy_sat_lh_s1\000"
7752 /* 3405 */ "M2_mpyu_lh_s1\000"
7753 /* 3419 */ "M2_mpy_lh_s1\000"
7754 /* 3432 */ "M4_vrmpyoh_s1\000"
7755 /* 3446 */ "M2_mmpyuh_s1\000"
7756 /* 3459 */ "M2_mmpyh_s1\000"
7757 /* 3471 */ "M2_hmmpyh_s1\000"
7758 /* 3484 */ "M2_mpyud_nac_hl_s1\000"
7759 /* 3503 */ "M2_mpyd_nac_hl_s1\000"
7760 /* 3521 */ "M2_mpyu_nac_hl_s1\000"
7761 /* 3539 */ "M2_mpy_nac_hl_s1\000"
7762 /* 3556 */ "M2_mpyud_acc_hl_s1\000"
7763 /* 3575 */ "M2_mpyd_acc_hl_s1\000"
7764 /* 3593 */ "M2_mpyu_acc_hl_s1\000"
7765 /* 3611 */ "M2_mpy_acc_hl_s1\000"
7766 /* 3628 */ "M2_mpyd_rnd_hl_s1\000"
7767 /* 3646 */ "M2_mpy_sat_rnd_hl_s1\000"
7768 /* 3667 */ "M2_mpy_rnd_hl_s1\000"
7769 /* 3684 */ "M2_mpyud_hl_s1\000"
7770 /* 3699 */ "M2_mpyd_hl_s1\000"
7771 /* 3713 */ "M2_mpy_nac_sat_hl_s1\000"
7772 /* 3734 */ "M2_mpy_acc_sat_hl_s1\000"
7773 /* 3755 */ "M2_mpy_sat_hl_s1\000"
7774 /* 3772 */ "M2_mpyu_hl_s1\000"
7775 /* 3786 */ "M2_mpy_hl_s1\000"
7776 /* 3799 */ "M2_mpyud_nac_ll_s1\000"
7777 /* 3818 */ "M2_mpyd_nac_ll_s1\000"
7778 /* 3836 */ "M2_mpyu_nac_ll_s1\000"
7779 /* 3854 */ "M2_mpy_nac_ll_s1\000"
7780 /* 3871 */ "M2_mpyud_acc_ll_s1\000"
7781 /* 3890 */ "M2_mpyd_acc_ll_s1\000"
7782 /* 3908 */ "M2_mpyu_acc_ll_s1\000"
7783 /* 3926 */ "M2_mpy_acc_ll_s1\000"
7784 /* 3943 */ "M2_mpyd_rnd_ll_s1\000"
7785 /* 3961 */ "M2_mpy_sat_rnd_ll_s1\000"
7786 /* 3982 */ "M2_mpy_rnd_ll_s1\000"
7787 /* 3999 */ "M2_mpyud_ll_s1\000"
7788 /* 4014 */ "M2_mpyd_ll_s1\000"
7789 /* 4028 */ "M2_mpy_nac_sat_ll_s1\000"
7790 /* 4049 */ "M2_mpy_acc_sat_ll_s1\000"
7791 /* 4070 */ "M2_mpy_sat_ll_s1\000"
7792 /* 4087 */ "M2_mpyu_ll_s1\000"
7793 /* 4101 */ "M2_mpy_ll_s1\000"
7794 /* 4114 */ "M2_mmpyul_s1\000"
7795 /* 4127 */ "M2_mmpyl_s1\000"
7796 /* 4139 */ "M2_hmmpyl_s1\000"
7797 /* 4152 */ "M2_mpy_up_s1\000"
7798 /* 4165 */ "M2_vmac2s_s1\000"
7799 /* 4178 */ "M2_vmpy2s_s1\000"
7800 /* 4191 */ "M2_cmacs_s1\000"
7801 /* 4203 */ "M2_vdmacs_s1\000"
7802 /* 4216 */ "M2_cnacs_s1\000"
7803 /* 4228 */ "M2_vmac2es_s1\000"
7804 /* 4242 */ "M2_vmpy2es_s1\000"
7805 /* 4256 */ "M2_mmachs_s1\000"
7806 /* 4269 */ "M2_mmacuhs_s1\000"
7807 /* 4283 */ "M2_mmacls_s1\000"
7808 /* 4296 */ "M2_mmaculs_s1\000"
7809 /* 4310 */ "M2_cmpyrs_s1\000"
7810 /* 4323 */ "M2_vdmpyrs_s1\000"
7811 /* 4337 */ "M2_cmpys_s1\000"
7812 /* 4349 */ "M2_vrcmpys_s1\000"
7813 /* 4363 */ "M2_vdmpys_s1\000"
7814 /* 4376 */ "M2_vmac2su_s1\000"
7815 /* 4390 */ "M2_vmpy2su_s1\000"
7816 /* 4404 */ "M2_mmpyuh_rs1\000"
7817 /* 4418 */ "M2_mmpyh_rs1\000"
7818 /* 4431 */ "M2_hmmpyh_rs1\000"
7819 /* 4445 */ "M2_mmpyul_rs1\000"
7820 /* 4459 */ "M2_mmpyl_rs1\000"
7821 /* 4472 */ "M2_hmmpyl_rs1\000"
7822 /* 4486 */ "M2_mmachs_rs1\000"
7823 /* 4500 */ "M2_mmacuhs_rs1\000"
7824 /* 4515 */ "M2_mmacls_rs1\000"
7825 /* 4529 */ "M2_mmaculs_rs1\000"
7826 /* 4544 */ "DuplexIClass1\000"
7827 /* 4558 */ "S2_ct1\000"
7828 /* 4565 */ "CONST32\000"
7829 /* 4573 */ "V6_vsub_qf32\000"
7830 /* 4586 */ "V6_vadd_qf32\000"
7831 /* 4599 */ "V6_vconv_hf_qf32\000"
7832 /* 4616 */ "V6_vconv_sf_qf32\000"
7833 /* 4633 */ "V6_vmpy_qf32\000"
7834 /* 4646 */ "G_FLOG2\000"
7835 /* 4654 */ "G_FATAN2\000"
7836 /* 4663 */ "G_FEXP2\000"
7837 /* 4671 */ "M2_vmac2\000"
7838 /* 4680 */ "V6_pred_scalar2\000"
7839 /* 4696 */ "DuplexIClass2\000"
7840 /* 4710 */ "M4_mpyri_addr_u2\000"
7841 /* 4727 */ "V6_pred_scalar2v2\000"
7842 /* 4745 */ "DuplexIClass3\000"
7843 /* 4759 */ "CONST64\000"
7844 /* 4767 */ "V6_vmpyewuh_64\000"
7845 /* 4782 */ "TFRI64_V4\000"
7846 /* 4792 */ "RESTORE_DEALLOC_BEFORE_TAILCALL_V4\000"
7847 /* 4827 */ "SAVE_REGISTERS_CALL_V4\000"
7848 /* 4850 */ "RESTORE_DEALLOC_RET_JMP_V4\000"
7849 /* 4877 */ "DuplexIClass4\000"
7850 /* 4891 */ "V6_vlut4\000"
7851 /* 4900 */ "DuplexIClass5\000"
7852 /* 4914 */ "V6_vmpy_qf32_qf16\000"
7853 /* 4932 */ "V6_vsub_qf16\000"
7854 /* 4945 */ "V6_vadd_qf16\000"
7855 /* 4958 */ "V6_vconv_hf_qf16\000"
7856 /* 4975 */ "V6_vmpy_rt_qf16\000"
7857 /* 4991 */ "V6_vmpy_qf16\000"
7858 /* 5004 */ "V6_vwhist256\000"
7859 /* 5017 */ "DuplexIClass6\000"
7860 /* 5031 */ "DuplexIClass7\000"
7861 /* 5045 */ "V6_vwhist128\000"
7862 /* 5058 */ "V6_vsub_hf_f8\000"
7863 /* 5072 */ "V6_vadd_hf_f8\000"
7864 /* 5086 */ "V6_vcvt_hf_f8\000"
7865 /* 5100 */ "V6_vmpy_hf_f8\000"
7866 /* 5114 */ "V6_vfneg_f8\000"
7867 /* 5126 */ "V6_vfmin_f8\000"
7868 /* 5138 */ "V6_vabs_f8\000"
7869 /* 5149 */ "V6_vfmax_f8\000"
7870 /* 5161 */ "C2_all8\000"
7871 /* 5169 */ "DuplexIClass8\000"
7872 /* 5183 */ "C2_any8\000"
7873 /* 5191 */ "C4_fastcorner9\000"
7874 /* 5206 */ "DuplexIClass9\000"
7875 /* 5220 */ "G_FMA\000"
7876 /* 5226 */ "G_STRICT_FMA\000"
7877 /* 5239 */ "DuplexIClassA\000"
7878 /* 5253 */ "G_FSUB\000"
7879 /* 5260 */ "G_STRICT_FSUB\000"
7880 /* 5274 */ "G_ATOMICRMW_FSUB\000"
7881 /* 5291 */ "G_SUB\000"
7882 /* 5297 */ "G_ATOMICRMW_SUB\000"
7883 /* 5313 */ "DuplexIClassB\000"
7884 /* 5327 */ "RESTORE_DEALLOC_BEFORE_TAILCALL_V4_PIC\000"
7885 /* 5366 */ "SAVE_REGISTERS_CALL_V4_PIC\000"
7886 /* 5393 */ "RESTORE_DEALLOC_RET_JMP_V4_PIC\000"
7887 /* 5424 */ "SAVE_REGISTERS_CALL_V4STK_PIC\000"
7888 /* 5454 */ "RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT_PIC\000"
7889 /* 5497 */ "SAVE_REGISTERS_CALL_V4_EXT_PIC\000"
7890 /* 5528 */ "RESTORE_DEALLOC_RET_JMP_V4_EXT_PIC\000"
7891 /* 5563 */ "SAVE_REGISTERS_CALL_V4STK_EXT_PIC\000"
7892 /* 5597 */ "G_INTRINSIC\000"
7893 /* 5609 */ "G_FPTRUNC\000"
7894 /* 5619 */ "G_INTRINSIC_TRUNC\000"
7895 /* 5637 */ "G_TRUNC\000"
7896 /* 5645 */ "G_BUILD_VECTOR_TRUNC\000"
7897 /* 5666 */ "G_DYN_STACKALLOC\000"
7898 /* 5683 */ "DuplexIClassC\000"
7899 /* 5697 */ "G_FMAD\000"
7900 /* 5704 */ "G_INDEXED_SEXTLOAD\000"
7901 /* 5723 */ "G_SEXTLOAD\000"
7902 /* 5734 */ "G_INDEXED_ZEXTLOAD\000"
7903 /* 5753 */ "G_ZEXTLOAD\000"
7904 /* 5764 */ "G_INDEXED_LOAD\000"
7905 /* 5779 */ "G_LOAD\000"
7906 /* 5786 */ "G_VECREDUCE_FADD\000"
7907 /* 5803 */ "G_FADD\000"
7908 /* 5810 */ "G_VECREDUCE_SEQ_FADD\000"
7909 /* 5831 */ "G_STRICT_FADD\000"
7910 /* 5845 */ "G_ATOMICRMW_FADD\000"
7911 /* 5862 */ "G_VECREDUCE_ADD\000"
7912 /* 5878 */ "G_ADD\000"
7913 /* 5884 */ "G_PTR_ADD\000"
7914 /* 5894 */ "G_ATOMICRMW_ADD\000"
7915 /* 5910 */ "G_ATOMICRMW_NAND\000"
7916 /* 5927 */ "G_VECREDUCE_AND\000"
7917 /* 5943 */ "G_AND\000"
7918 /* 5949 */ "G_ATOMICRMW_AND\000"
7919 /* 5965 */ "LIFETIME_END\000"
7920 /* 5978 */ "G_BRCOND\000"
7921 /* 5987 */ "G_ATOMICRMW_USUB_COND\000"
7922 /* 6009 */ "G_LLROUND\000"
7923 /* 6019 */ "G_LROUND\000"
7924 /* 6028 */ "G_INTRINSIC_ROUND\000"
7925 /* 6046 */ "G_INTRINSIC_FPTRUNC_ROUND\000"
7926 /* 6072 */ "LOAD_STACK_GUARD\000"
7927 /* 6089 */ "DuplexIClassD\000"
7928 /* 6103 */ "PSEUDO_PROBE\000"
7929 /* 6116 */ "G_SSUBE\000"
7930 /* 6124 */ "G_USUBE\000"
7931 /* 6132 */ "G_FENCE\000"
7932 /* 6140 */ "ARITH_FENCE\000"
7933 /* 6152 */ "REG_SEQUENCE\000"
7934 /* 6165 */ "G_SADDE\000"
7935 /* 6173 */ "G_UADDE\000"
7936 /* 6181 */ "G_GET_FPMODE\000"
7937 /* 6194 */ "G_RESET_FPMODE\000"
7938 /* 6209 */ "G_SET_FPMODE\000"
7939 /* 6222 */ "G_FMINNUM_IEEE\000"
7940 /* 6237 */ "G_FMAXNUM_IEEE\000"
7941 /* 6252 */ "G_VSCALE\000"
7942 /* 6261 */ "G_JUMP_TABLE\000"
7943 /* 6274 */ "BUNDLE\000"
7944 /* 6281 */ "G_MEMCPY_INLINE\000"
7945 /* 6297 */ "LOCAL_ESCAPE\000"
7946 /* 6310 */ "G_STACKRESTORE\000"
7947 /* 6325 */ "G_INDEXED_STORE\000"
7948 /* 6341 */ "G_STORE\000"
7949 /* 6349 */ "G_BITREVERSE\000"
7950 /* 6362 */ "FAKE_USE\000"
7951 /* 6371 */ "DBG_VALUE\000"
7952 /* 6381 */ "G_GLOBAL_VALUE\000"
7953 /* 6396 */ "G_PTRAUTH_GLOBAL_VALUE\000"
7954 /* 6419 */ "CONVERGENCECTRL_GLUE\000"
7955 /* 6440 */ "G_STACKSAVE\000"
7956 /* 6452 */ "G_MEMMOVE\000"
7957 /* 6462 */ "G_FREEZE\000"
7958 /* 6471 */ "G_FCANONICALIZE\000"
7959 /* 6487 */ "DuplexIClassE\000"
7960 /* 6501 */ "G_CTLZ_ZERO_UNDEF\000"
7961 /* 6519 */ "G_CTTZ_ZERO_UNDEF\000"
7962 /* 6537 */ "INIT_UNDEF\000"
7963 /* 6548 */ "G_IMPLICIT_DEF\000"
7964 /* 6563 */ "DBG_INSTR_REF\000"
7965 /* 6577 */ "DuplexIClassF\000"
7966 /* 6591 */ "G_FNEG\000"
7967 /* 6598 */ "EXTRACT_SUBREG\000"
7968 /* 6613 */ "INSERT_SUBREG\000"
7969 /* 6627 */ "G_SEXT_INREG\000"
7970 /* 6640 */ "SUBREG_TO_REG\000"
7971 /* 6654 */ "G_ATOMIC_CMPXCHG\000"
7972 /* 6671 */ "G_ATOMICRMW_XCHG\000"
7973 /* 6688 */ "G_FLOG\000"
7974 /* 6695 */ "G_VAARG\000"
7975 /* 6703 */ "PREALLOCATED_ARG\000"
7976 /* 6720 */ "G_PREFETCH\000"
7977 /* 6731 */ "G_SMULH\000"
7978 /* 6739 */ "G_UMULH\000"
7979 /* 6747 */ "G_FTANH\000"
7980 /* 6755 */ "G_FSINH\000"
7981 /* 6763 */ "G_FCOSH\000"
7982 /* 6771 */ "DBG_PHI\000"
7983 /* 6779 */ "G_FPTOSI\000"
7984 /* 6788 */ "G_FPTOUI\000"
7985 /* 6797 */ "G_FPOWI\000"
7986 /* 6805 */ "G_PTRMASK\000"
7987 /* 6815 */ "SAVE_REGISTERS_CALL_V4STK\000"
7988 /* 6841 */ "GC_LABEL\000"
7989 /* 6850 */ "DBG_LABEL\000"
7990 /* 6860 */ "EH_LABEL\000"
7991 /* 6869 */ "ANNOTATION_LABEL\000"
7992 /* 6886 */ "ICALL_BRANCH_FUNNEL\000"
7993 /* 6906 */ "G_FSHL\000"
7994 /* 6913 */ "G_SHL\000"
7995 /* 6919 */ "G_FCEIL\000"
7996 /* 6927 */ "PATCHABLE_TAIL_CALL\000"
7997 /* 6947 */ "PATCHABLE_TYPED_EVENT_CALL\000"
7998 /* 6974 */ "PATCHABLE_EVENT_CALL\000"
7999 /* 6995 */ "FENTRY_CALL\000"
8000 /* 7007 */ "KILL\000"
8001 /* 7012 */ "G_CONSTANT_POOL\000"
8002 /* 7028 */ "G_ROTL\000"
8003 /* 7035 */ "G_VECREDUCE_FMUL\000"
8004 /* 7052 */ "G_FMUL\000"
8005 /* 7059 */ "G_VECREDUCE_SEQ_FMUL\000"
8006 /* 7080 */ "G_STRICT_FMUL\000"
8007 /* 7094 */ "G_VECREDUCE_MUL\000"
8008 /* 7110 */ "G_MUL\000"
8009 /* 7116 */ "G_FREM\000"
8010 /* 7123 */ "G_STRICT_FREM\000"
8011 /* 7137 */ "G_SREM\000"
8012 /* 7144 */ "G_UREM\000"
8013 /* 7151 */ "G_SDIVREM\000"
8014 /* 7161 */ "G_UDIVREM\000"
8015 /* 7171 */ "INLINEASM\000"
8016 /* 7181 */ "G_VECREDUCE_FMINIMUM\000"
8017 /* 7202 */ "G_FMINIMUM\000"
8018 /* 7213 */ "G_ATOMICRMW_FMINIMUM\000"
8019 /* 7234 */ "G_VECREDUCE_FMAXIMUM\000"
8020 /* 7255 */ "G_FMAXIMUM\000"
8021 /* 7266 */ "G_ATOMICRMW_FMAXIMUM\000"
8022 /* 7287 */ "G_FMINIMUMNUM\000"
8023 /* 7301 */ "G_FMAXIMUMNUM\000"
8024 /* 7315 */ "G_FMINNUM\000"
8025 /* 7325 */ "G_FMAXNUM\000"
8026 /* 7335 */ "G_FATAN\000"
8027 /* 7343 */ "G_FTAN\000"
8028 /* 7350 */ "G_INTRINSIC_ROUNDEVEN\000"
8029 /* 7372 */ "G_ASSERT_ALIGN\000"
8030 /* 7387 */ "G_FCOPYSIGN\000"
8031 /* 7399 */ "G_VECREDUCE_FMIN\000"
8032 /* 7416 */ "G_ATOMICRMW_FMIN\000"
8033 /* 7433 */ "G_VECREDUCE_SMIN\000"
8034 /* 7450 */ "G_SMIN\000"
8035 /* 7457 */ "G_VECREDUCE_UMIN\000"
8036 /* 7474 */ "G_UMIN\000"
8037 /* 7481 */ "G_ATOMICRMW_UMIN\000"
8038 /* 7498 */ "G_ATOMICRMW_MIN\000"
8039 /* 7514 */ "G_FASIN\000"
8040 /* 7522 */ "G_FSIN\000"
8041 /* 7529 */ "CFI_INSTRUCTION\000"
8042 /* 7545 */ "ADJCALLSTACKDOWN\000"
8043 /* 7562 */ "G_SSUBO\000"
8044 /* 7570 */ "G_USUBO\000"
8045 /* 7578 */ "G_SADDO\000"
8046 /* 7586 */ "G_UADDO\000"
8047 /* 7594 */ "JUMP_TABLE_DEBUG_INFO\000"
8048 /* 7616 */ "G_SMULO\000"
8049 /* 7624 */ "G_UMULO\000"
8050 /* 7632 */ "G_BZERO\000"
8051 /* 7640 */ "STACKMAP\000"
8052 /* 7649 */ "G_DEBUGTRAP\000"
8053 /* 7661 */ "G_UBSANTRAP\000"
8054 /* 7673 */ "G_TRAP\000"
8055 /* 7680 */ "G_ATOMICRMW_UDEC_WRAP\000"
8056 /* 7702 */ "G_ATOMICRMW_UINC_WRAP\000"
8057 /* 7724 */ "G_BSWAP\000"
8058 /* 7732 */ "G_SITOFP\000"
8059 /* 7741 */ "G_UITOFP\000"
8060 /* 7750 */ "G_FCMP\000"
8061 /* 7757 */ "G_ICMP\000"
8062 /* 7764 */ "G_SCMP\000"
8063 /* 7771 */ "G_UCMP\000"
8064 /* 7778 */ "CONVERGENCECTRL_LOOP\000"
8065 /* 7799 */ "G_CTPOP\000"
8066 /* 7807 */ "PATCHABLE_OP\000"
8067 /* 7820 */ "FAULTING_OP\000"
8068 /* 7832 */ "ADJCALLSTACKUP\000"
8069 /* 7847 */ "PREALLOCATED_SETUP\000"
8070 /* 7866 */ "G_FLDEXP\000"
8071 /* 7875 */ "G_STRICT_FLDEXP\000"
8072 /* 7891 */ "G_FEXP\000"
8073 /* 7898 */ "G_FFREXP\000"
8074 /* 7907 */ "A6_vminub_RdP\000"
8075 /* 7921 */ "G_BR\000"
8076 /* 7926 */ "INLINEASM_BR\000"
8077 /* 7939 */ "G_BLOCK_ADDR\000"
8078 /* 7952 */ "MEMBARRIER\000"
8079 /* 7963 */ "G_CONSTANT_FOLD_BARRIER\000"
8080 /* 7987 */ "PATCHABLE_FUNCTION_ENTER\000"
8081 /* 8012 */ "G_READCYCLECOUNTER\000"
8082 /* 8031 */ "G_READSTEADYCOUNTER\000"
8083 /* 8051 */ "G_READ_REGISTER\000"
8084 /* 8067 */ "G_WRITE_REGISTER\000"
8085 /* 8084 */ "G_ASHR\000"
8086 /* 8091 */ "G_FSHR\000"
8087 /* 8098 */ "G_LSHR\000"
8088 /* 8105 */ "CONVERGENCECTRL_ANCHOR\000"
8089 /* 8128 */ "G_FFLOOR\000"
8090 /* 8137 */ "G_EXTRACT_SUBVECTOR\000"
8091 /* 8157 */ "G_INSERT_SUBVECTOR\000"
8092 /* 8176 */ "G_BUILD_VECTOR\000"
8093 /* 8191 */ "G_SHUFFLE_VECTOR\000"
8094 /* 8208 */ "G_STEP_VECTOR\000"
8095 /* 8222 */ "G_SPLAT_VECTOR\000"
8096 /* 8237 */ "G_VECREDUCE_XOR\000"
8097 /* 8253 */ "G_XOR\000"
8098 /* 8259 */ "G_ATOMICRMW_XOR\000"
8099 /* 8275 */ "G_VECREDUCE_OR\000"
8100 /* 8290 */ "G_OR\000"
8101 /* 8295 */ "G_ATOMICRMW_OR\000"
8102 /* 8310 */ "EH_RETURN_JMPR\000"
8103 /* 8325 */ "G_ROTR\000"
8104 /* 8332 */ "G_INTTOPTR\000"
8105 /* 8343 */ "G_FABS\000"
8106 /* 8350 */ "G_ABS\000"
8107 /* 8356 */ "A5_ACS\000"
8108 /* 8363 */ "G_ABDS\000"
8109 /* 8370 */ "G_UNMERGE_VALUES\000"
8110 /* 8387 */ "G_MERGE_VALUES\000"
8111 /* 8402 */ "G_FACOS\000"
8112 /* 8410 */ "G_FCOS\000"
8113 /* 8417 */ "G_FSINCOS\000"
8114 /* 8427 */ "G_CONCAT_VECTORS\000"
8115 /* 8444 */ "COPY_TO_REGCLASS\000"
8116 /* 8461 */ "G_IS_FPCLASS\000"
8117 /* 8474 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\000"
8118 /* 8504 */ "G_VECTOR_COMPRESS\000"
8119 /* 8522 */ "G_INTRINSIC_W_SIDE_EFFECTS\000"
8120 /* 8549 */ "G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS\000"
8121 /* 8587 */ "G_SSUBSAT\000"
8122 /* 8597 */ "G_USUBSAT\000"
8123 /* 8607 */ "G_SADDSAT\000"
8124 /* 8617 */ "G_UADDSAT\000"
8125 /* 8627 */ "G_SSHLSAT\000"
8126 /* 8637 */ "G_USHLSAT\000"
8127 /* 8647 */ "G_SMULFIXSAT\000"
8128 /* 8660 */ "G_UMULFIXSAT\000"
8129 /* 8673 */ "G_SDIVFIXSAT\000"
8130 /* 8686 */ "G_UDIVFIXSAT\000"
8131 /* 8699 */ "G_ATOMICRMW_USUB_SAT\000"
8132 /* 8720 */ "G_FPTOSI_SAT\000"
8133 /* 8733 */ "G_FPTOUI_SAT\000"
8134 /* 8746 */ "G_EXTRACT\000"
8135 /* 8756 */ "G_SELECT\000"
8136 /* 8765 */ "G_BRINDIRECT\000"
8137 /* 8778 */ "PATCHABLE_RET\000"
8138 /* 8792 */ "G_MEMSET\000"
8139 /* 8801 */ "PATCHABLE_FUNCTION_EXIT\000"
8140 /* 8825 */ "G_BRJT\000"
8141 /* 8832 */ "G_EXTRACT_VECTOR_ELT\000"
8142 /* 8853 */ "G_INSERT_VECTOR_ELT\000"
8143 /* 8873 */ "G_FCONSTANT\000"
8144 /* 8885 */ "G_CONSTANT\000"
8145 /* 8896 */ "G_INTRINSIC_CONVERGENT\000"
8146 /* 8919 */ "STATEPOINT\000"
8147 /* 8930 */ "PATCHPOINT\000"
8148 /* 8941 */ "G_PTRTOINT\000"
8149 /* 8952 */ "G_FRINT\000"
8150 /* 8960 */ "G_INTRINSIC_LLRINT\000"
8151 /* 8979 */ "G_INTRINSIC_LRINT\000"
8152 /* 8997 */ "G_FNEARBYINT\000"
8153 /* 9010 */ "G_VASTART\000"
8154 /* 9020 */ "LIFETIME_START\000"
8155 /* 9035 */ "G_INVOKE_REGION_START\000"
8156 /* 9057 */ "G_INSERT\000"
8157 /* 9066 */ "G_FSQRT\000"
8158 /* 9074 */ "G_STRICT_FSQRT\000"
8159 /* 9089 */ "G_BITCAST\000"
8160 /* 9099 */ "G_ADDRSPACE_CAST\000"
8161 /* 9116 */ "DBG_VALUE_LIST\000"
8162 /* 9131 */ "G_FPEXT\000"
8163 /* 9139 */ "G_SEXT\000"
8164 /* 9146 */ "G_ASSERT_SEXT\000"
8165 /* 9160 */ "G_ANYEXT\000"
8166 /* 9169 */ "G_ZEXT\000"
8167 /* 9176 */ "G_ASSERT_ZEXT\000"
8168 /* 9190 */ "RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT\000"
8169 /* 9229 */ "SAVE_REGISTERS_CALL_V4_EXT\000"
8170 /* 9256 */ "RESTORE_DEALLOC_RET_JMP_V4_EXT\000"
8171 /* 9287 */ "SAVE_REGISTERS_CALL_V4STK_EXT\000"
8172 /* 9317 */ "G_ABDU\000"
8173 /* 9324 */ "G_FDIV\000"
8174 /* 9331 */ "G_STRICT_FDIV\000"
8175 /* 9345 */ "G_SDIV\000"
8176 /* 9352 */ "G_UDIV\000"
8177 /* 9359 */ "G_GET_FPENV\000"
8178 /* 9371 */ "G_RESET_FPENV\000"
8179 /* 9385 */ "G_SET_FPENV\000"
8180 /* 9397 */ "G_FPOW\000"
8181 /* 9404 */ "G_VECREDUCE_FMAX\000"
8182 /* 9421 */ "G_ATOMICRMW_FMAX\000"
8183 /* 9438 */ "G_VECREDUCE_SMAX\000"
8184 /* 9455 */ "G_SMAX\000"
8185 /* 9462 */ "G_VECREDUCE_UMAX\000"
8186 /* 9479 */ "G_UMAX\000"
8187 /* 9486 */ "G_ATOMICRMW_UMAX\000"
8188 /* 9503 */ "G_ATOMICRMW_MAX\000"
8189 /* 9519 */ "G_FRAME_INDEX\000"
8190 /* 9533 */ "G_SBFX\000"
8191 /* 9540 */ "G_UBFX\000"
8192 /* 9547 */ "G_SMULFIX\000"
8193 /* 9557 */ "G_UMULFIX\000"
8194 /* 9567 */ "G_SDIVFIX\000"
8195 /* 9577 */ "G_UDIVFIX\000"
8196 /* 9587 */ "G_MEMCPY\000"
8197 /* 9596 */ "COPY\000"
8198 /* 9601 */ "CONVERGENCECTRL_ENTRY\000"
8199 /* 9623 */ "G_CTLZ\000"
8200 /* 9630 */ "G_CTTZ\000"
8201 /* 9637 */ "PS_alloca\000"
8202 /* 9647 */ "PS_fia\000"
8203 /* 9654 */ "Y5_l2locka\000"
8204 /* 9665 */ "Y5_l2unlocka\000"
8205 /* 9678 */ "F2_sffma\000"
8206 /* 9687 */ "Y2_dccleana\000"
8207 /* 9699 */ "PS_aligna\000"
8208 /* 9709 */ "Y2_dczeroa\000"
8209 /* 9720 */ "F2_sfrecipa\000"
8210 /* 9732 */ "Y6_l2gcleanpa\000"
8211 /* 9746 */ "Y6_l2gcleaninvpa\000"
8212 /* 9763 */ "V6_vrdelta\000"
8213 /* 9774 */ "V6_vdelta\000"
8214 /* 9784 */ "F2_sfinvsqrta\000"
8215 /* 9798 */ "Y2_dcinva\000"
8216 /* 9808 */ "Y2_icinva\000"
8217 /* 9818 */ "Y2_dccleaninva\000"
8218 /* 9833 */ "V6_vcvt2_hf_b\000"
8219 /* 9847 */ "V6_vcvt_hf_b\000"
8220 /* 9860 */ "V6_vsubb\000"
8221 /* 9869 */ "V6_vaddb\000"
8222 /* 9878 */ "S2_shuffeb\000"
8223 /* 9889 */ "V6_vshuffeb\000"
8224 /* 9901 */ "V6_vpackeb\000"
8225 /* 9912 */ "V6_vshufoeb\000"
8226 /* 9924 */ "M6_vabsdiffb\000"
8227 /* 9937 */ "V6_vshuffb\000"
8228 /* 9948 */ "V6_vnavgb\000"
8229 /* 9958 */ "V6_vavgb\000"
8230 /* 9967 */ "V6_vmpahb\000"
8231 /* 9977 */ "V6_vroundhb\000"
8232 /* 9989 */ "S2_vtrunehb\000"
8233 /* 10001 */ "V6_vmpyihb\000"
8234 /* 10012 */ "S2_vtrunohb\000"
8235 /* 10024 */ "S2_vsathb\000"
8236 /* 10034 */ "S2_svsathb\000"
8237 /* 10045 */ "V6_vmpauhb\000"
8238 /* 10056 */ "V6_vdmpyhb\000"
8239 /* 10067 */ "V6_vtmpyhb\000"
8240 /* 10078 */ "S2_vspliceib\000"
8241 /* 10091 */ "F2_sffma_lib\000"
8242 /* 10104 */ "F2_sffms_lib\000"
8243 /* 10117 */ "S2_valignib\000"
8244 /* 10129 */ "PS_vsplatib\000"
8245 /* 10141 */ "V6_vunpackb\000"
8246 /* 10153 */ "V6_vdealb\000"
8247 /* 10163 */ "S2_clb\000"
8248 /* 10170 */ "V6_vlalignb\000"
8249 /* 10182 */ "V6_valignb\000"
8250 /* 10193 */ "A2_vminb\000"
8251 /* 10202 */ "V6_vminb\000"
8252 /* 10211 */ "S2_shuffob\000"
8253 /* 10222 */ "V6_vshuffob\000"
8254 /* 10234 */ "V6_vunpackob\000"
8255 /* 10247 */ "V6_vpackob\000"
8256 /* 10258 */ "V6_veqb\000"
8257 /* 10266 */ "V6_vprefixqb\000"
8258 /* 10279 */ "S2_vsplicerb\000"
8259 /* 10292 */ "S2_valignrb\000"
8260 /* 10304 */ "V6_vlsrb\000"
8261 /* 10313 */ "S2_vsplatrb\000"
8262 /* 10325 */ "PS_vsplatrb\000"
8263 /* 10337 */ "V6_vabsb\000"
8264 /* 10346 */ "V6_vsb\000"
8265 /* 10353 */ "V6_lvsplatb\000"
8266 /* 10365 */ "A2_satb\000"
8267 /* 10373 */ "V6_vgtb\000"
8268 /* 10381 */ "SA1_sxtb\000"
8269 /* 10390 */ "dup_A2_sxtb\000"
8270 /* 10402 */ "SA1_zxtb\000"
8271 /* 10411 */ "dup_A2_zxtb\000"
8272 /* 10423 */ "V6_vcvt2_hf_ub\000"
8273 /* 10438 */ "V6_vcvt_hf_ub\000"
8274 /* 10452 */ "A2_vsubub\000"
8275 /* 10462 */ "A2_vrsadub\000"
8276 /* 10473 */ "A2_vraddub\000"
8277 /* 10484 */ "A2_vaddub\000"
8278 /* 10494 */ "M6_vabsdiffub\000"
8279 /* 10508 */ "V6_vabsdiffub\000"
8280 /* 10522 */ "V6_vnavgub\000"
8281 /* 10533 */ "A2_vavgub\000"
8282 /* 10543 */ "V6_vavgub\000"
8283 /* 10553 */ "V6_vroundhub\000"
8284 /* 10566 */ "S2_vsathub\000"
8285 /* 10577 */ "V6_vsathub\000"
8286 /* 10588 */ "S2_svsathub\000"
8287 /* 10600 */ "V6_vrounduhub\000"
8288 /* 10614 */ "V6_vunpackub\000"
8289 /* 10627 */ "A2_vminub\000"
8290 /* 10637 */ "V6_vminub\000"
8291 /* 10647 */ "V6_MAP_equb\000"
8292 /* 10659 */ "A2_sub\000"
8293 /* 10666 */ "F2_dfsub\000"
8294 /* 10675 */ "F2_sfsub\000"
8295 /* 10684 */ "A2_satub\000"
8296 /* 10693 */ "V6_vgtub\000"
8297 /* 10702 */ "V6_vmpyiwub\000"
8298 /* 10714 */ "A2_vmaxub\000"
8299 /* 10724 */ "V6_vmaxub\000"
8300 /* 10734 */ "V6_vrmpyub\000"
8301 /* 10745 */ "V6_vmpyub\000"
8302 /* 10755 */ "V6_vlutvvb\000"
8303 /* 10766 */ "V6_vmpyiwb\000"
8304 /* 10777 */ "A2_vmaxb\000"
8305 /* 10786 */ "V6_vmaxb\000"
8306 /* 10795 */ "S2_tableidxb\000"
8307 /* 10808 */ "V6_vtmpyb\000"
8308 /* 10818 */ "V6_vzb\000"
8309 /* 10825 */ "M2_vrcmaci_s0c\000"
8310 /* 10840 */ "M2_vrcmpyi_s0c\000"
8311 /* 10855 */ "M2_vrcmacr_s0c\000"
8312 /* 10870 */ "M2_vrcmpyr_s0c\000"
8313 /* 10885 */ "A4_subp_c\000"
8314 /* 10895 */ "A4_addp_c\000"
8315 /* 10905 */ "S6_rol_i_p_nac\000"
8316 /* 10920 */ "S2_asl_i_p_nac\000"
8317 /* 10935 */ "S2_asr_i_p_nac\000"
8318 /* 10950 */ "S2_lsr_i_p_nac\000"
8319 /* 10965 */ "S2_asl_r_p_nac\000"
8320 /* 10980 */ "S2_lsl_r_p_nac\000"
8321 /* 10995 */ "S2_asr_r_p_nac\000"
8322 /* 11010 */ "S2_lsr_r_p_nac\000"
8323 /* 11025 */ "S6_rol_i_r_nac\000"
8324 /* 11040 */ "S2_asl_i_r_nac\000"
8325 /* 11055 */ "S2_asr_i_r_nac\000"
8326 /* 11070 */ "S2_lsr_i_r_nac\000"
8327 /* 11085 */ "S2_asl_r_r_nac\000"
8328 /* 11100 */ "S2_lsl_r_r_nac\000"
8329 /* 11115 */ "S2_asr_r_r_nac\000"
8330 /* 11130 */ "S2_lsr_r_r_nac\000"
8331 /* 11145 */ "V6_vmpyowh_64_acc\000"
8332 /* 11163 */ "V6_vmpy_hf_f8_acc\000"
8333 /* 11181 */ "V6_vmpahb_acc\000"
8334 /* 11195 */ "V6_vmpyihb_acc\000"
8335 /* 11210 */ "V6_vmpauhb_acc\000"
8336 /* 11225 */ "V6_vdmpyhb_acc\000"
8337 /* 11240 */ "V6_vtmpyhb_acc\000"
8338 /* 11255 */ "A2_vrsadub_acc\000"
8339 /* 11270 */ "A2_vraddub_acc\000"
8340 /* 11285 */ "V6_vmpyiwub_acc\000"
8341 /* 11301 */ "V6_vrmpyub_acc\000"
8342 /* 11316 */ "V6_vmpyub_acc\000"
8343 /* 11330 */ "V6_vmpyiwb_acc\000"
8344 /* 11345 */ "V6_vtmpyb_acc\000"
8345 /* 11359 */ "M7_dcmpyiwc_acc\000"
8346 /* 11375 */ "M7_dcmpyrwc_acc\000"
8347 /* 11391 */ "V6_vmpyuhe_acc\000"
8348 /* 11406 */ "S4_vrcrotate_acc\000"
8349 /* 11423 */ "V6_vmpy_sf_bf_acc\000"
8350 /* 11441 */ "V6_vmpy_hf_hf_acc\000"
8351 /* 11459 */ "V6_vdmpy_sf_hf_acc\000"
8352 /* 11478 */ "V6_vmpy_sf_hf_acc\000"
8353 /* 11496 */ "V6_vaddubh_acc\000"
8354 /* 11511 */ "V6_vmpyih_acc\000"
8355 /* 11525 */ "V6_vaslh_acc\000"
8356 /* 11538 */ "V6_vasrh_acc\000"
8357 /* 11551 */ "V6_vdsaduh_acc\000"
8358 /* 11566 */ "V6_vmpyiewuh_acc\000"
8359 /* 11583 */ "V6_vmpyuh_acc\000"
8360 /* 11597 */ "V6_vmpyiewh_acc\000"
8361 /* 11613 */ "V6_vmpyiwh_acc\000"
8362 /* 11628 */ "M4_vpmpyh_acc\000"
8363 /* 11642 */ "V6_vmpyh_acc\000"
8364 /* 11655 */ "V6_vrsadubi_acc\000"
8365 /* 11671 */ "V6_vrmpyubi_acc\000"
8366 /* 11687 */ "V6_vrmpybusi_acc\000"
8367 /* 11704 */ "S6_rol_i_p_acc\000"
8368 /* 11719 */ "S2_asl_i_p_acc\000"
8369 /* 11734 */ "S2_asr_i_p_acc\000"
8370 /* 11749 */ "S2_lsr_i_p_acc\000"
8371 /* 11764 */ "S2_asl_r_p_acc\000"
8372 /* 11779 */ "S2_lsl_r_p_acc\000"
8373 /* 11794 */ "S2_asr_r_p_acc\000"
8374 /* 11809 */ "S2_lsr_r_p_acc\000"
8375 /* 11824 */ "S6_rol_i_r_acc\000"
8376 /* 11839 */ "S2_asl_i_r_acc\000"
8377 /* 11854 */ "S2_asr_i_r_acc\000"
8378 /* 11869 */ "S2_lsr_i_r_acc\000"
8379 /* 11884 */ "S2_asl_r_r_acc\000"
8380 /* 11899 */ "S2_lsl_r_r_acc\000"
8381 /* 11914 */ "S2_asr_r_r_acc\000"
8382 /* 11929 */ "S2_lsr_r_r_acc\000"
8383 /* 11944 */ "V6_vmpabus_acc\000"
8384 /* 11959 */ "V6_vdmpybus_acc\000"
8385 /* 11975 */ "V6_vrmpybus_acc\000"
8386 /* 11991 */ "V6_vtmpybus_acc\000"
8387 /* 12007 */ "V6_vmpybus_acc\000"
8388 /* 12022 */ "V6_vmpyhus_acc\000"
8389 /* 12037 */ "V6_vdmpyhsat_acc\000"
8390 /* 12054 */ "V6_vmpyhsat_acc\000"
8391 /* 12070 */ "V6_vdmpyhisat_acc\000"
8392 /* 12088 */ "V6_vdmpyhsuisat_acc\000"
8393 /* 12108 */ "V6_vdmpyhsusat_acc\000"
8394 /* 12127 */ "V6_vdmpyhvsat_acc\000"
8395 /* 12145 */ "V6_vrmpyzbb_rt_acc\000"
8396 /* 12164 */ "V6_vrmpyzcb_rt_acc\000"
8397 /* 12183 */ "V6_vrmpyznb_rt_acc\000"
8398 /* 12202 */ "V6_vrmpyzbub_rt_acc\000"
8399 /* 12222 */ "V6_vrmpyzcbs_rt_acc\000"
8400 /* 12242 */ "V6_vandqrt_acc\000"
8401 /* 12257 */ "V6_vandnqrt_acc\000"
8402 /* 12273 */ "V6_vandvrt_acc\000"
8403 /* 12288 */ "V6_vrmpybub_rtt_acc\000"
8404 /* 12308 */ "V6_vrmpyub_rtt_acc\000"
8405 /* 12327 */ "V6_vmpabuu_acc\000"
8406 /* 12342 */ "V6_vrmpyubv_acc\000"
8407 /* 12358 */ "V6_vmpyubv_acc\000"
8408 /* 12373 */ "V6_vrmpybv_acc\000"
8409 /* 12388 */ "V6_vmpybv_acc\000"
8410 /* 12402 */ "V6_vdmpyhb_dv_acc\000"
8411 /* 12420 */ "V6_vdmpybus_dv_acc\000"
8412 /* 12439 */ "V6_vmpyuhv_acc\000"
8413 /* 12454 */ "V6_vmpyhv_acc\000"
8414 /* 12468 */ "V6_vrmpybusv_acc\000"
8415 /* 12485 */ "V6_vmpybusv_acc\000"
8416 /* 12501 */ "V6_vaddhw_acc\000"
8417 /* 12515 */ "V6_vadduhw_acc\000"
8418 /* 12530 */ "M7_dcmpyiw_acc\000"
8419 /* 12545 */ "V6_vaslw_acc\000"
8420 /* 12558 */ "PS_vmulw_acc\000"
8421 /* 12571 */ "V6_vasrw_acc\000"
8422 /* 12584 */ "M7_dcmpyrw_acc\000"
8423 /* 12599 */ "M4_pmpyw_acc\000"
8424 /* 12612 */ "V6_vrmpyzbb_rx_acc\000"
8425 /* 12631 */ "V6_vrmpyzcb_rx_acc\000"
8426 /* 12650 */ "V6_vrmpyznb_rx_acc\000"
8427 /* 12669 */ "V6_vrmpyzbub_rx_acc\000"
8428 /* 12689 */ "V6_vrmpyzcbs_rx_acc\000"
8429 /* 12709 */ "M7_vdmpy_acc\000"
8430 /* 12722 */ "M2_subacc\000"
8431 /* 12732 */ "V6_vlutvvb_oracc\000"
8432 /* 12749 */ "V6_vlutvwh_oracc\000"
8433 /* 12766 */ "V6_get_qfext_oracc\000"
8434 /* 12785 */ "V6_vmpyowh_rnd_sacc\000"
8435 /* 12805 */ "V6_vmpyowh_sacc\000"
8436 /* 12821 */ "S6_rol_i_p_xacc\000"
8437 /* 12837 */ "S2_asl_i_p_xacc\000"
8438 /* 12853 */ "S2_lsr_i_p_xacc\000"
8439 /* 12869 */ "S6_rol_i_r_xacc\000"
8440 /* 12885 */ "S2_asl_i_r_xacc\000"
8441 /* 12901 */ "S2_lsr_i_r_xacc\000"
8442 /* 12917 */ "M2_xor_xacc\000"
8443 /* 12929 */ "M4_xor_xacc\000"
8444 /* 12941 */ "SA1_dec\000"
8445 /* 12949 */ "M4_cmpyi_whc\000"
8446 /* 12962 */ "M4_cmpyr_whc\000"
8447 /* 12975 */ "SA1_inc\000"
8448 /* 12983 */ "Y2_isync\000"
8449 /* 12992 */ "Y5_tlboc\000"
8450 /* 13001 */ "C4_addipc\000"
8451 /* 13011 */ "F2_sffma_sc\000"
8452 /* 13023 */ "M7_dcmpyiwc\000"
8453 /* 13035 */ "M7_wcmpyiwc\000"
8454 /* 13047 */ "M7_dcmpyrwc\000"
8455 /* 13059 */ "M7_wcmpyrwc\000"
8456 /* 13071 */ "F2_conv_df2d\000"
8457 /* 13084 */ "F2_conv_sf2d\000"
8458 /* 13097 */ "Y2_ciad\000"
8459 /* 13105 */ "Y4_siad\000"
8460 /* 13113 */ "dup_A2_add\000"
8461 /* 13124 */ "V6_vscattermh_add\000"
8462 /* 13142 */ "V6_vscattermhw_add\000"
8463 /* 13161 */ "V6_vscattermw_add\000"
8464 /* 13179 */ "F2_dfadd\000"
8465 /* 13188 */ "F2_sfadd\000"
8466 /* 13197 */ "V6_vshuffvdd\000"
8467 /* 13210 */ "V6_vdealvdd\000"
8468 /* 13222 */ "L4_loadd_locked\000"
8469 /* 13238 */ "S4_stored_locked\000"
8470 /* 13255 */ "L2_loadw_locked\000"
8471 /* 13271 */ "S2_storew_locked\000"
8472 /* 13288 */ "LDriw_pred\000"
8473 /* 13299 */ "STriw_pred\000"
8474 /* 13310 */ "Y2_crswap_old\000"
8475 /* 13324 */ "A2_and\000"
8476 /* 13331 */ "C2_and\000"
8477 /* 13338 */ "V6_veqb_and\000"
8478 /* 13350 */ "V6_vgtb_and\000"
8479 /* 13362 */ "V6_MAP_equb_and\000"
8480 /* 13378 */ "V6_vgtub_and\000"
8481 /* 13391 */ "V6_pred_and\000"
8482 /* 13403 */ "C4_and_and\000"
8483 /* 13414 */ "M4_and_and\000"
8484 /* 13425 */ "V6_vgtbf_and\000"
8485 /* 13438 */ "V6_vgthf_and\000"
8486 /* 13451 */ "V6_vgtsf_and\000"
8487 /* 13464 */ "V6_veqh_and\000"
8488 /* 13476 */ "V6_vgth_and\000"
8489 /* 13488 */ "V6_MAP_equh_and\000"
8490 /* 13504 */ "V6_vgtuh_and\000"
8491 /* 13517 */ "S6_rol_i_p_and\000"
8492 /* 13532 */ "S2_asl_i_p_and\000"
8493 /* 13547 */ "S2_asr_i_p_and\000"
8494 /* 13562 */ "S2_lsr_i_p_and\000"
8495 /* 13577 */ "S2_asl_r_p_and\000"
8496 /* 13592 */ "S2_lsl_r_p_and\000"
8497 /* 13607 */ "S2_asr_r_p_and\000"
8498 /* 13622 */ "S2_lsr_r_p_and\000"
8499 /* 13637 */ "S6_rol_i_r_and\000"
8500 /* 13652 */ "S2_asl_i_r_and\000"
8501 /* 13667 */ "S2_asr_i_r_and\000"
8502 /* 13682 */ "S2_lsr_i_r_and\000"
8503 /* 13697 */ "S2_asl_r_r_and\000"
8504 /* 13712 */ "S2_lsl_r_r_and\000"
8505 /* 13727 */ "S2_asr_r_r_and\000"
8506 /* 13742 */ "S2_lsr_r_r_and\000"
8507 /* 13757 */ "C4_or_and\000"
8508 /* 13767 */ "M4_or_and\000"
8509 /* 13777 */ "M4_xor_and\000"
8510 /* 13788 */ "V6_veqw_and\000"
8511 /* 13800 */ "V6_vgtw_and\000"
8512 /* 13812 */ "V6_MAP_equw_and\000"
8513 /* 13828 */ "V6_vgtuw_and\000"
8514 /* 13841 */ "V6_vand\000"
8515 /* 13849 */ "M7_wcmpyiwc_rnd\000"
8516 /* 13865 */ "M7_wcmpyrwc_rnd\000"
8517 /* 13881 */ "V6_vmpyowh_rnd\000"
8518 /* 13896 */ "S2_asr_i_p_rnd\000"
8519 /* 13911 */ "S2_asr_i_r_rnd\000"
8520 /* 13926 */ "M7_wcmpyiw_rnd\000"
8521 /* 13941 */ "M7_wcmpyrw_rnd\000"
8522 /* 13956 */ "V6_vavgbrnd\000"
8523 /* 13968 */ "V6_vavgubrnd\000"
8524 /* 13981 */ "V6_vavghrnd\000"
8525 /* 13993 */ "S5_vasrhrnd\000"
8526 /* 14005 */ "V6_vavguhrnd\000"
8527 /* 14018 */ "V6_vavgwrnd\000"
8528 /* 14030 */ "V6_vavguwrnd\000"
8529 /* 14043 */ "F2_sffixupd\000"
8530 /* 14055 */ "F2_conv_df2ud\000"
8531 /* 14069 */ "F2_conv_sf2ud\000"
8532 /* 14083 */ "S2_tableidxd\000"
8533 /* 14096 */ "Y4_trace\000"
8534 /* 14105 */ "invalid_decode\000"
8535 /* 14120 */ "F2_dfcmpge\000"
8536 /* 14131 */ "F2_sfcmpge\000"
8537 /* 14142 */ "V6_vmpyuhe\000"
8538 /* 14153 */ "CALLProfile\000"
8539 /* 14165 */ "SS2_allocframe\000"
8540 /* 14180 */ "dup_S2_allocframe\000"
8541 /* 14198 */ "SL2_deallocframe\000"
8542 /* 14215 */ "dup_L2_deallocframe\000"
8543 /* 14235 */ "Y2_resume\000"
8544 /* 14245 */ "Y6_dmresume\000"
8545 /* 14257 */ "V6_vnccombine\000"
8546 /* 14271 */ "V6_vccombine\000"
8547 /* 14284 */ "V6_vcombine\000"
8548 /* 14296 */ "PS_false\000"
8549 /* 14305 */ "PS_qfalse\000"
8550 /* 14315 */ "J2_pause\000"
8551 /* 14324 */ "Y6_dmpause\000"
8552 /* 14335 */ "J2_unpause\000"
8553 /* 14346 */ "S4_vrcrotate\000"
8554 /* 14359 */ "S2_vcrotate\000"
8555 /* 14371 */ "C4_cmplte\000"
8556 /* 14381 */ "J2_rte\000"
8557 /* 14388 */ "PS_true\000"
8558 /* 14396 */ "PS_qtrue\000"
8559 /* 14405 */ "S2_interleave\000"
8560 /* 14419 */ "S2_deinterleave\000"
8561 /* 14435 */ "SL2_jumpr31_f\000"
8562 /* 14449 */ "SL2_return_f\000"
8563 /* 14462 */ "L4_return_f\000"
8564 /* 14474 */ "L4_return_map_to_raw_f\000"
8565 /* 14497 */ "V6_vsub_sf_bf\000"
8566 /* 14511 */ "V6_vadd_sf_bf\000"
8567 /* 14525 */ "V6_vmpy_sf_bf\000"
8568 /* 14539 */ "V6_vmin_bf\000"
8569 /* 14550 */ "V6_vmax_bf\000"
8570 /* 14561 */ "V6_vgtbf\000"
8571 /* 14570 */ "A4_psxtbf\000"
8572 /* 14580 */ "A4_pzxtbf\000"
8573 /* 14590 */ "A2_psubf\000"
8574 /* 14599 */ "F2_conv_d2df\000"
8575 /* 14612 */ "F2_conv_ud2df\000"
8576 /* 14626 */ "F2_conv_sf2df\000"
8577 /* 14640 */ "F2_conv_w2df\000"
8578 /* 14653 */ "F2_conv_uw2df\000"
8579 /* 14667 */ "A2_paddf\000"
8580 /* 14676 */ "A2_pandf\000"
8581 /* 14685 */ "V6_vshuff\000"
8582 /* 14695 */ "V6_vmpy_qf32_hf\000"
8583 /* 14711 */ "V6_vmpy_qf16_hf\000"
8584 /* 14727 */ "V6_vcvt_f8_hf\000"
8585 /* 14741 */ "V6_vcvt2_b_hf\000"
8586 /* 14755 */ "V6_vcvt_b_hf\000"
8587 /* 14768 */ "V6_vcvt2_ub_hf\000"
8588 /* 14783 */ "V6_vcvt_ub_hf\000"
8589 /* 14797 */ "V6_vsub_hf\000"
8590 /* 14808 */ "V6_vadd_hf\000"
8591 /* 14819 */ "V6_vsub_hf_hf\000"
8592 /* 14833 */ "V6_vadd_hf_hf\000"
8593 /* 14847 */ "V6_vmpy_hf_hf\000"
8594 /* 14861 */ "V6_vsub_sf_hf\000"
8595 /* 14875 */ "V6_vadd_sf_hf\000"
8596 /* 14889 */ "V6_vcvt_sf_hf\000"
8597 /* 14903 */ "V6_vdmpy_sf_hf\000"
8598 /* 14918 */ "V6_vmpy_sf_hf\000"
8599 /* 14932 */ "V6_vfneg_hf\000"
8600 /* 14944 */ "V6_vcvt_h_hf\000"
8601 /* 14957 */ "V6_vconv_h_hf\000"
8602 /* 14971 */ "V6_vcvt_uh_hf\000"
8603 /* 14985 */ "V6_vfmin_hf\000"
8604 /* 14997 */ "V6_vmin_hf\000"
8605 /* 15008 */ "V6_vabs_hf\000"
8606 /* 15019 */ "V6_vmpy_rt_hf\000"
8607 /* 15033 */ "V6_vfmax_hf\000"
8608 /* 15045 */ "V6_vmax_hf\000"
8609 /* 15056 */ "V6_vmpy_qf32_mix_hf\000"
8610 /* 15076 */ "V6_vmpy_qf16_mix_hf\000"
8611 /* 15096 */ "A4_paslhf\000"
8612 /* 15106 */ "A4_pasrhf\000"
8613 /* 15116 */ "V6_vgthf\000"
8614 /* 15125 */ "A4_psxthf\000"
8615 /* 15135 */ "A4_pzxthf\000"
8616 /* 15145 */ "A2_paddif\000"
8617 /* 15155 */ "dup_C2_cmoveif\000"
8618 /* 15170 */ "dup_C2_cmovenewif\000"
8619 /* 15188 */ "J2_callf\000"
8620 /* 15197 */ "J2_jumpf\000"
8621 /* 15206 */ "A2_tfrpf\000"
8622 /* 15215 */ "V6_vmerge_qf\000"
8623 /* 15228 */ "A2_tfrf\000"
8624 /* 15236 */ "SA1_clrf\000"
8625 /* 15245 */ "J2_callrf\000"
8626 /* 15255 */ "A2_porf\000"
8627 /* 15263 */ "A2_pxorf\000"
8628 /* 15272 */ "J2_jumprf\000"
8629 /* 15282 */ "F2_conv_d2sf\000"
8630 /* 15295 */ "F2_conv_ud2sf\000"
8631 /* 15309 */ "F2_conv_df2sf\000"
8632 /* 15323 */ "F2_conv_w2sf\000"
8633 /* 15336 */ "F2_conv_uw2sf\000"
8634 /* 15350 */ "V6_vmpy_qf32_sf\000"
8635 /* 15366 */ "V6_vsub_sf\000"
8636 /* 15377 */ "V6_vadd_sf\000"
8637 /* 15388 */ "V6_vcvt_bf_sf\000"
8638 /* 15402 */ "V6_vcvt_hf_sf\000"
8639 /* 15416 */ "V6_vsub_sf_sf\000"
8640 /* 15430 */ "V6_vadd_sf_sf\000"
8641 /* 15444 */ "V6_vmpy_sf_sf\000"
8642 /* 15458 */ "V6_vfneg_sf\000"
8643 /* 15470 */ "V6_vfmin_sf\000"
8644 /* 15482 */ "V6_vmin_sf\000"
8645 /* 15493 */ "V6_vabs_sf\000"
8646 /* 15504 */ "V6_vmpy_rt_sf\000"
8647 /* 15518 */ "V6_vconv_w_sf\000"
8648 /* 15532 */ "V6_vfmax_sf\000"
8649 /* 15544 */ "V6_vmax_sf\000"
8650 /* 15555 */ "V6_vgtsf\000"
8651 /* 15564 */ "PS_jmpretf\000"
8652 /* 15575 */ "C2_ccombinewf\000"
8653 /* 15589 */ "C2_ccombinewnewf\000"
8654 /* 15606 */ "Y6_diag\000"
8655 /* 15614 */ "A2_neg\000"
8656 /* 15621 */ "V6_vcl0h\000"
8657 /* 15630 */ "M2_vrcmpys_acc_s1_h\000"
8658 /* 15650 */ "M2_vrcmpys_s1_h\000"
8659 /* 15666 */ "V6_vcvt_hf_h\000"
8660 /* 15679 */ "V6_vconv_hf_h\000"
8661 /* 15693 */ "M2_vrcmpys_s1rp_h\000"
8662 /* 15711 */ "V6_vaddclbh\000"
8663 /* 15723 */ "S2_vsxtbh\000"
8664 /* 15733 */ "S2_vzxtbh\000"
8665 /* 15743 */ "V6_vsububh\000"
8666 /* 15754 */ "V6_vaddubh\000"
8667 /* 15765 */ "S4_vxaddsubh\000"
8668 /* 15778 */ "A2_vsubh\000"
8669 /* 15787 */ "V6_vsubh\000"
8670 /* 15796 */ "A2_svsubh\000"
8671 /* 15806 */ "A4_tlbmatch\000"
8672 /* 15818 */ "Y4_l2fetch\000"
8673 /* 15829 */ "Y5_l2fetch\000"
8674 /* 15840 */ "Y2_dcfetch\000"
8675 /* 15851 */ "S4_vxsubaddh\000"
8676 /* 15864 */ "M2_vraddh\000"
8677 /* 15874 */ "A2_vaddh\000"
8678 /* 15883 */ "V6_vaddh\000"
8679 /* 15892 */ "A2_svaddh\000"
8680 /* 15902 */ "S2_shuffeh\000"
8681 /* 15913 */ "V6_vshufeh\000"
8682 /* 15924 */ "V6_vpackeh\000"
8683 /* 15935 */ "V6_vshufoeh\000"
8684 /* 15947 */ "M2_vabsdiffh\000"
8685 /* 15960 */ "V6_vabsdiffh\000"
8686 /* 15973 */ "V6_vshuffh\000"
8687 /* 15984 */ "S2_vrcnegh\000"
8688 /* 15995 */ "S2_vcnegh\000"
8689 /* 16005 */ "A2_vnavgh\000"
8690 /* 16015 */ "V6_vnavgh\000"
8691 /* 16025 */ "A2_svnavgh\000"
8692 /* 16036 */ "A2_vavgh\000"
8693 /* 16045 */ "V6_vavgh\000"
8694 /* 16054 */ "A2_svavgh\000"
8695 /* 16064 */ "A2_subh_h16_hh\000"
8696 /* 16079 */ "A2_addh_h16_hh\000"
8697 /* 16094 */ "A2_combine_hh\000"
8698 /* 16108 */ "A2_subh_h16_sat_hh\000"
8699 /* 16127 */ "A2_addh_h16_sat_hh\000"
8700 /* 16146 */ "F2_dfmpyhh\000"
8701 /* 16157 */ "A2_tfrih\000"
8702 /* 16166 */ "PS_vsplatih\000"
8703 /* 16178 */ "V6_vmpyih\000"
8704 /* 16188 */ "V6_vunpackh\000"
8705 /* 16200 */ "A2_subh_h16_lh\000"
8706 /* 16215 */ "A2_addh_h16_lh\000"
8707 /* 16230 */ "A2_combine_lh\000"
8708 /* 16244 */ "A2_subh_h16_sat_lh\000"
8709 /* 16263 */ "A2_addh_h16_sat_lh\000"
8710 /* 16282 */ "V6_vdealh\000"
8711 /* 16292 */ "A2_aslh\000"
8712 /* 16300 */ "V6_vaslh\000"
8713 /* 16309 */ "F2_dfmpylh\000"
8714 /* 16320 */ "V6_vgathermh\000"
8715 /* 16333 */ "V6_vscattermh\000"
8716 /* 16347 */ "A4_vrminh\000"
8717 /* 16357 */ "A2_vminh\000"
8718 /* 16366 */ "V6_vminh\000"
8719 /* 16375 */ "V6_vmpyieoh\000"
8720 /* 16387 */ "S2_shuffoh\000"
8721 /* 16398 */ "V6_vshufoh\000"
8722 /* 16409 */ "V6_vunpackoh\000"
8723 /* 16422 */ "V6_vpackoh\000"
8724 /* 16433 */ "A2_addsph\000"
8725 /* 16443 */ "V6_shuffeqh\000"
8726 /* 16455 */ "V6_veqh\000"
8727 /* 16463 */ "V6_vprefixqh\000"
8728 /* 16476 */ "J2_callrh\000"
8729 /* 16486 */ "J2_jumprh\000"
8730 /* 16496 */ "A2_asrh\000"
8731 /* 16504 */ "V6_vasrh\000"
8732 /* 16513 */ "V6_vlsrh\000"
8733 /* 16522 */ "S2_vsplatrh\000"
8734 /* 16534 */ "PS_vsplatrh\000"
8735 /* 16546 */ "PS_crash\000"
8736 /* 16555 */ "A2_vabsh\000"
8737 /* 16564 */ "V6_vabsh\000"
8738 /* 16573 */ "V6_vsh\000"
8739 /* 16580 */ "V6_lvsplath\000"
8740 /* 16592 */ "A2_sath\000"
8741 /* 16600 */ "V6_vgth\000"
8742 /* 16608 */ "V6_vnormamth\000"
8743 /* 16621 */ "V6_vpopcounth\000"
8744 /* 16635 */ "SA1_sxth\000"
8745 /* 16644 */ "dup_A2_sxth\000"
8746 /* 16656 */ "SA1_zxth\000"
8747 /* 16665 */ "dup_A2_zxth\000"
8748 /* 16677 */ "V6_vcvt_hf_uh\000"
8749 /* 16691 */ "V6_vdsaduh\000"
8750 /* 16702 */ "M2_vradduh\000"
8751 /* 16713 */ "V6_vabsdiffuh\000"
8752 /* 16727 */ "A2_vavguh\000"
8753 /* 16737 */ "V6_vavguh\000"
8754 /* 16747 */ "V6_vunpackuh\000"
8755 /* 16760 */ "A4_vrminuh\000"
8756 /* 16771 */ "A2_vminuh\000"
8757 /* 16781 */ "V6_vminuh\000"
8758 /* 16791 */ "V6_MAP_equh\000"
8759 /* 16803 */ "A2_satuh\000"
8760 /* 16812 */ "V6_vgtuh\000"
8761 /* 16821 */ "V6_vroundwuh\000"
8762 /* 16834 */ "V6_vmpyiewuh\000"
8763 /* 16847 */ "V6_vmpyewuh\000"
8764 /* 16859 */ "S2_vsatwuh\000"
8765 /* 16870 */ "V6_vrounduwuh\000"
8766 /* 16884 */ "V6_vsatuwuh\000"
8767 /* 16896 */ "A4_vrmaxuh\000"
8768 /* 16907 */ "A2_vmaxuh\000"
8769 /* 16917 */ "V6_vmaxuh\000"
8770 /* 16927 */ "V6_vmpyuh\000"
8771 /* 16937 */ "S2_asl_i_vh\000"
8772 /* 16949 */ "S2_asr_i_vh\000"
8773 /* 16961 */ "S2_lsr_i_vh\000"
8774 /* 16973 */ "S2_asl_r_vh\000"
8775 /* 16985 */ "S2_lsl_r_vh\000"
8776 /* 16997 */ "S2_asr_r_vh\000"
8777 /* 17009 */ "S2_lsr_r_vh\000"
8778 /* 17021 */ "M4_cmpyi_wh\000"
8779 /* 17033 */ "M4_cmpyr_wh\000"
8780 /* 17045 */ "V6_vroundwh\000"
8781 /* 17057 */ "S2_vtrunewh\000"
8782 /* 17069 */ "V6_vmpyiwh\000"
8783 /* 17080 */ "S2_vrndpackwh\000"
8784 /* 17094 */ "V6_vmpyiowh\000"
8785 /* 17106 */ "S2_vtrunowh\000"
8786 /* 17118 */ "V6_vmpyowh\000"
8787 /* 17129 */ "V6_vasrwh\000"
8788 /* 17139 */ "S2_vsatwh\000"
8789 /* 17149 */ "V6_vsatwh\000"
8790 /* 17159 */ "V6_vlutvwh\000"
8791 /* 17170 */ "A4_vrmaxh\000"
8792 /* 17180 */ "A2_vmaxh\000"
8793 /* 17189 */ "V6_vmaxh\000"
8794 /* 17198 */ "S2_tableidxh\000"
8795 /* 17211 */ "M4_vpmpyh\000"
8796 /* 17221 */ "V6_vmpyh\000"
8797 /* 17230 */ "V6_vzh\000"
8798 /* 17237 */ "SA1_combine0i\000"
8799 /* 17251 */ "J2_loop0i\000"
8800 /* 17261 */ "SA1_combine1i\000"
8801 /* 17275 */ "J2_loop1i\000"
8802 /* 17285 */ "SA1_combine2i\000"
8803 /* 17299 */ "SA1_combine3i\000"
8804 /* 17313 */ "PS_tailcall_i\000"
8805 /* 17327 */ "M2_vcmac_s0_sat_i\000"
8806 /* 17345 */ "M2_vcmpy_s0_sat_i\000"
8807 /* 17363 */ "M2_vcmpy_s1_sat_i\000"
8808 /* 17381 */ "S2_togglebit_i\000"
8809 /* 17396 */ "S2_clrbit_i\000"
8810 /* 17408 */ "S2_setbit_i\000"
8811 /* 17420 */ "S2_tstbit_i\000"
8812 /* 17432 */ "S4_ntstbit_i\000"
8813 /* 17445 */ "V6_vL32b_ai\000"
8814 /* 17457 */ "V6_vS32b_ai\000"
8815 /* 17469 */ "V6_vL32Ub_ai\000"
8816 /* 17482 */ "V6_vS32Ub_ai\000"
8817 /* 17495 */ "V6_zLd_ai\000"
8818 /* 17505 */ "V6_vL32b_pred_ai\000"
8819 /* 17522 */ "V6_vS32b_pred_ai\000"
8820 /* 17539 */ "V6_vS32Ub_pred_ai\000"
8821 /* 17557 */ "V6_zLd_pred_ai\000"
8822 /* 17572 */ "V6_vL32b_tmp_pred_ai\000"
8823 /* 17593 */ "V6_vL32b_nt_tmp_pred_ai\000"
8824 /* 17617 */ "V6_vL32b_cur_pred_ai\000"
8825 /* 17638 */ "V6_vL32b_nt_cur_pred_ai\000"
8826 /* 17662 */ "V6_vL32b_nt_pred_ai\000"
8827 /* 17682 */ "V6_vS32b_nt_pred_ai\000"
8828 /* 17702 */ "V6_vS32b_new_pred_ai\000"
8829 /* 17723 */ "V6_vS32b_nt_new_pred_ai\000"
8830 /* 17747 */ "V6_vL32b_npred_ai\000"
8831 /* 17765 */ "V6_vS32b_npred_ai\000"
8832 /* 17783 */ "V6_vS32Ub_npred_ai\000"
8833 /* 17802 */ "V6_vL32b_tmp_npred_ai\000"
8834 /* 17824 */ "V6_vL32b_nt_tmp_npred_ai\000"
8835 /* 17849 */ "V6_vL32b_cur_npred_ai\000"
8836 /* 17871 */ "V6_vL32b_nt_cur_npred_ai\000"
8837 /* 17896 */ "V6_vL32b_nt_npred_ai\000"
8838 /* 17917 */ "V6_vS32b_nt_npred_ai\000"
8839 /* 17938 */ "V6_vS32b_new_npred_ai\000"
8840 /* 17960 */ "V6_vS32b_nt_new_npred_ai\000"
8841 /* 17985 */ "V6_vS32b_qpred_ai\000"
8842 /* 18003 */ "V6_vS32b_nt_qpred_ai\000"
8843 /* 18024 */ "V6_vS32b_nqpred_ai\000"
8844 /* 18043 */ "V6_vS32b_nt_nqpred_ai\000"
8845 /* 18065 */ "V6_vL32b_tmp_ai\000"
8846 /* 18081 */ "V6_vL32b_nt_tmp_ai\000"
8847 /* 18100 */ "PS_vloadrq_ai\000"
8848 /* 18114 */ "PS_vstorerq_ai\000"
8849 /* 18129 */ "V6_vL32b_cur_ai\000"
8850 /* 18145 */ "V6_vL32b_nt_cur_ai\000"
8851 /* 18164 */ "V6_vS32b_srls_ai\000"
8852 /* 18181 */ "V6_vL32b_nt_ai\000"
8853 /* 18196 */ "V6_vS32b_nt_ai\000"
8854 /* 18211 */ "PS_vloadrv_nt_ai\000"
8855 /* 18228 */ "PS_vstorerv_nt_ai\000"
8856 /* 18246 */ "PS_vloadrw_nt_ai\000"
8857 /* 18263 */ "PS_vstorerw_nt_ai\000"
8858 /* 18281 */ "PS_vloadrv_ai\000"
8859 /* 18295 */ "PS_vstorerv_ai\000"
8860 /* 18310 */ "V6_vS32b_new_ai\000"
8861 /* 18326 */ "V6_vS32b_nt_new_ai\000"
8862 /* 18345 */ "PS_vloadrw_ai\000"
8863 /* 18359 */ "PS_vstorerw_ai\000"
8864 /* 18374 */ "V6_vlalignbi\000"
8865 /* 18387 */ "V6_valignbi\000"
8866 /* 18399 */ "V6_vrsadubi\000"
8867 /* 18411 */ "V6_vrmpyubi\000"
8868 /* 18423 */ "V6_vlutvvbi\000"
8869 /* 18435 */ "M2_maci\000"
8870 /* 18443 */ "M2_mnaci\000"
8871 /* 18452 */ "M2_acci\000"
8872 /* 18460 */ "M2_nacci\000"
8873 /* 18469 */ "V6_vlutvvb_oracci\000"
8874 /* 18487 */ "V6_vlutvwh_oracci\000"
8875 /* 18505 */ "L2_loadbsw2_pci\000"
8876 /* 18521 */ "L2_loadbzw2_pci\000"
8877 /* 18537 */ "L2_loadbsw4_pci\000"
8878 /* 18553 */ "L2_loadbzw4_pci\000"
8879 /* 18569 */ "L2_loadalignb_pci\000"
8880 /* 18587 */ "L2_loadrb_pci\000"
8881 /* 18601 */ "PS_loadrb_pci\000"
8882 /* 18615 */ "S2_storerb_pci\000"
8883 /* 18630 */ "PS_storerb_pci\000"
8884 /* 18645 */ "L2_loadrub_pci\000"
8885 /* 18660 */ "PS_loadrub_pci\000"
8886 /* 18675 */ "L2_loadrd_pci\000"
8887 /* 18689 */ "PS_loadrd_pci\000"
8888 /* 18703 */ "S2_storerd_pci\000"
8889 /* 18718 */ "PS_storerd_pci\000"
8890 /* 18733 */ "S2_storerf_pci\000"
8891 /* 18748 */ "PS_storerf_pci\000"
8892 /* 18763 */ "L2_loadalignh_pci\000"
8893 /* 18781 */ "L2_loadrh_pci\000"
8894 /* 18795 */ "PS_loadrh_pci\000"
8895 /* 18809 */ "S2_storerh_pci\000"
8896 /* 18824 */ "PS_storerh_pci\000"
8897 /* 18839 */ "L2_loadruh_pci\000"
8898 /* 18854 */ "PS_loadruh_pci\000"
8899 /* 18869 */ "L2_loadri_pci\000"
8900 /* 18883 */ "PS_loadri_pci\000"
8901 /* 18897 */ "S2_storeri_pci\000"
8902 /* 18912 */ "PS_storeri_pci\000"
8903 /* 18927 */ "S2_storerbnew_pci\000"
8904 /* 18945 */ "S2_storerhnew_pci\000"
8905 /* 18963 */ "S2_storerinew_pci\000"
8906 /* 18981 */ "SA1_addi\000"
8907 /* 18990 */ "dup_A2_addi\000"
8908 /* 19002 */ "M4_mpyri_addi\000"
8909 /* 19016 */ "M4_mpyrr_addi\000"
8910 /* 19030 */ "S4_clbaddi\000"
8911 /* 19041 */ "S4_subaddi\000"
8912 /* 19052 */ "S4_addaddi\000"
8913 /* 19063 */ "S4_clbpaddi\000"
8914 /* 19075 */ "Y5_tlbasidi\000"
8915 /* 19087 */ "S4_or_andi\000"
8916 /* 19098 */ "C2_cmpgei\000"
8917 /* 19108 */ "C4_cmpltei\000"
8918 /* 19119 */ "PS_fi\000"
8919 /* 19125 */ "V6_hi\000"
8920 /* 19131 */ "A4_boundscheck_hi\000"
8921 /* 19149 */ "V6_vlutvwhi\000"
8922 /* 19161 */ "M2_accii\000"
8923 /* 19170 */ "M2_naccii\000"
8924 /* 19180 */ "dup_A2_combineii\000"
8925 /* 19197 */ "dup_A4_combineii\000"
8926 /* 19214 */ "C2_muxii\000"
8927 /* 19223 */ "S4_lsli\000"
8928 /* 19231 */ "Y4_nmi\000"
8929 /* 19238 */ "M2_mpysmi\000"
8930 /* 19248 */ "L2_loadbsw2_pi\000"
8931 /* 19263 */ "L2_loadbzw2_pi\000"
8932 /* 19278 */ "L2_loadbsw4_pi\000"
8933 /* 19293 */ "L2_loadbzw4_pi\000"
8934 /* 19308 */ "V6_vL32b_pi\000"
8935 /* 19320 */ "V6_vS32b_pi\000"
8936 /* 19332 */ "V6_vL32Ub_pi\000"
8937 /* 19345 */ "V6_vS32Ub_pi\000"
8938 /* 19358 */ "L2_loadalignb_pi\000"
8939 /* 19375 */ "L2_loadrb_pi\000"
8940 /* 19388 */ "S2_storerb_pi\000"
8941 /* 19402 */ "L2_loadrub_pi\000"
8942 /* 19416 */ "V6_zLd_pi\000"
8943 /* 19426 */ "V6_vL32b_pred_pi\000"
8944 /* 19443 */ "V6_vS32b_pred_pi\000"
8945 /* 19460 */ "V6_vS32Ub_pred_pi\000"
8946 /* 19478 */ "V6_zLd_pred_pi\000"
8947 /* 19493 */ "V6_vL32b_tmp_pred_pi\000"
8948 /* 19514 */ "V6_vL32b_nt_tmp_pred_pi\000"
8949 /* 19538 */ "V6_vL32b_cur_pred_pi\000"
8950 /* 19559 */ "V6_vL32b_nt_cur_pred_pi\000"
8951 /* 19583 */ "V6_vL32b_nt_pred_pi\000"
8952 /* 19603 */ "V6_vS32b_nt_pred_pi\000"
8953 /* 19623 */ "V6_vS32b_new_pred_pi\000"
8954 /* 19644 */ "V6_vS32b_nt_new_pred_pi\000"
8955 /* 19668 */ "V6_vL32b_npred_pi\000"
8956 /* 19686 */ "V6_vS32b_npred_pi\000"
8957 /* 19704 */ "V6_vS32Ub_npred_pi\000"
8958 /* 19723 */ "V6_vL32b_tmp_npred_pi\000"
8959 /* 19745 */ "V6_vL32b_nt_tmp_npred_pi\000"
8960 /* 19770 */ "V6_vL32b_cur_npred_pi\000"
8961 /* 19792 */ "V6_vL32b_nt_cur_npred_pi\000"
8962 /* 19817 */ "V6_vL32b_nt_npred_pi\000"
8963 /* 19838 */ "V6_vS32b_nt_npred_pi\000"
8964 /* 19859 */ "V6_vS32b_new_npred_pi\000"
8965 /* 19881 */ "V6_vS32b_nt_new_npred_pi\000"
8966 /* 19906 */ "V6_vS32b_qpred_pi\000"
8967 /* 19924 */ "V6_vS32b_nt_qpred_pi\000"
8968 /* 19945 */ "V6_vS32b_nqpred_pi\000"
8969 /* 19964 */ "V6_vS32b_nt_nqpred_pi\000"
8970 /* 19986 */ "L2_loadrd_pi\000"
8971 /* 19999 */ "S2_storerd_pi\000"
8972 /* 20013 */ "L2_ploadrbf_pi\000"
8973 /* 20028 */ "S2_pstorerbf_pi\000"
8974 /* 20044 */ "L2_ploadrubf_pi\000"
8975 /* 20060 */ "L2_ploadrdf_pi\000"
8976 /* 20075 */ "S2_pstorerdf_pi\000"
8977 /* 20091 */ "S2_pstorerff_pi\000"
8978 /* 20107 */ "L2_ploadrhf_pi\000"
8979 /* 20122 */ "S2_pstorerhf_pi\000"
8980 /* 20138 */ "L2_ploadruhf_pi\000"
8981 /* 20154 */ "L2_ploadrif_pi\000"
8982 /* 20169 */ "S2_pstorerif_pi\000"
8983 /* 20185 */ "S2_storerf_pi\000"
8984 /* 20199 */ "S2_pstorerbnewf_pi\000"
8985 /* 20218 */ "S2_pstorerhnewf_pi\000"
8986 /* 20237 */ "S2_pstorerinewf_pi\000"
8987 /* 20256 */ "L2_loadalignh_pi\000"
8988 /* 20273 */ "L2_loadrh_pi\000"
8989 /* 20286 */ "S2_storerh_pi\000"
8990 /* 20300 */ "L2_loadruh_pi\000"
8991 /* 20314 */ "L2_loadri_pi\000"
8992 /* 20327 */ "S2_storeri_pi\000"
8993 /* 20341 */ "V6_vL32b_tmp_pi\000"
8994 /* 20357 */ "V6_vL32b_nt_tmp_pi\000"
8995 /* 20376 */ "V6_vL32b_cur_pi\000"
8996 /* 20392 */ "V6_vL32b_nt_cur_pi\000"
8997 /* 20411 */ "V6_vS32b_srls_pi\000"
8998 /* 20428 */ "L2_ploadrbt_pi\000"
8999 /* 20443 */ "S2_pstorerbt_pi\000"
9000 /* 20459 */ "L2_ploadrubt_pi\000"
9001 /* 20475 */ "L2_ploadrdt_pi\000"
9002 /* 20490 */ "S2_pstorerdt_pi\000"
9003 /* 20506 */ "S2_pstorerft_pi\000"
9004 /* 20522 */ "L2_ploadrht_pi\000"
9005 /* 20537 */ "S2_pstorerht_pi\000"
9006 /* 20553 */ "L2_ploadruht_pi\000"
9007 /* 20569 */ "L2_ploadrit_pi\000"
9008 /* 20584 */ "S2_pstorerit_pi\000"
9009 /* 20600 */ "V6_vL32b_nt_pi\000"
9010 /* 20615 */ "V6_vS32b_nt_pi\000"
9011 /* 20630 */ "S2_pstorerbnewt_pi\000"
9012 /* 20649 */ "S2_pstorerhnewt_pi\000"
9013 /* 20668 */ "S2_pstorerinewt_pi\000"
9014 /* 20687 */ "V6_vS32b_new_pi\000"
9015 /* 20703 */ "V6_vS32b_nt_new_pi\000"
9016 /* 20722 */ "S2_storerbnew_pi\000"
9017 /* 20739 */ "L2_ploadrbfnew_pi\000"
9018 /* 20757 */ "S2_pstorerbfnew_pi\000"
9019 /* 20776 */ "L2_ploadrubfnew_pi\000"
9020 /* 20795 */ "L2_ploadrdfnew_pi\000"
9021 /* 20813 */ "S2_pstorerdfnew_pi\000"
9022 /* 20832 */ "S2_pstorerffnew_pi\000"
9023 /* 20851 */ "L2_ploadrhfnew_pi\000"
9024 /* 20869 */ "S2_pstorerhfnew_pi\000"
9025 /* 20888 */ "L2_ploadruhfnew_pi\000"
9026 /* 20907 */ "L2_ploadrifnew_pi\000"
9027 /* 20925 */ "S2_pstorerifnew_pi\000"
9028 /* 20944 */ "S2_pstorerbnewfnew_pi\000"
9029 /* 20966 */ "S2_pstorerhnewfnew_pi\000"
9030 /* 20988 */ "S2_pstorerinewfnew_pi\000"
9031 /* 21010 */ "S2_storerhnew_pi\000"
9032 /* 21027 */ "S2_storerinew_pi\000"
9033 /* 21044 */ "L2_ploadrbtnew_pi\000"
9034 /* 21062 */ "S2_pstorerbtnew_pi\000"
9035 /* 21081 */ "L2_ploadrubtnew_pi\000"
9036 /* 21100 */ "L2_ploadrdtnew_pi\000"
9037 /* 21118 */ "S2_pstorerdtnew_pi\000"
9038 /* 21137 */ "S2_pstorerftnew_pi\000"
9039 /* 21156 */ "L2_ploadrhtnew_pi\000"
9040 /* 21174 */ "S2_pstorerhtnew_pi\000"
9041 /* 21193 */ "L2_ploadruhtnew_pi\000"
9042 /* 21212 */ "L2_ploadritnew_pi\000"
9043 /* 21230 */ "S2_pstoreritnew_pi\000"
9044 /* 21249 */ "S2_pstorerbnewtnew_pi\000"
9045 /* 21271 */ "S2_pstorerhnewtnew_pi\000"
9046 /* 21293 */ "S2_pstorerinewtnew_pi\000"
9047 /* 21315 */ "A2_tfrpi\000"
9048 /* 21324 */ "A4_cmpbeqi\000"
9049 /* 21335 */ "A4_vcmpbeqi\000"
9050 /* 21347 */ "A4_cmpheqi\000"
9051 /* 21358 */ "A4_vcmpheqi\000"
9052 /* 21370 */ "C4_cmpneqi\000"
9053 /* 21381 */ "A4_rcmpneqi\000"
9054 /* 21393 */ "SA1_cmpeqi\000"
9055 /* 21404 */ "dup_C2_cmpeqi\000"
9056 /* 21418 */ "A4_rcmpeqi\000"
9057 /* 21429 */ "A4_vcmpweqi\000"
9058 /* 21441 */ "A7_croundd_ri\000"
9059 /* 21455 */ "A4_round_ri\000"
9060 /* 21467 */ "A4_cround_ri\000"
9061 /* 21480 */ "S4_subi_asl_ri\000"
9062 /* 21495 */ "S4_addi_asl_ri\000"
9063 /* 21510 */ "S4_andi_asl_ri\000"
9064 /* 21525 */ "S4_ori_asl_ri\000"
9065 /* 21539 */ "S4_subi_lsr_ri\000"
9066 /* 21554 */ "S4_addi_lsr_ri\000"
9067 /* 21569 */ "S4_andi_lsr_ri\000"
9068 /* 21584 */ "S4_ori_lsr_ri\000"
9069 /* 21598 */ "A2_subri\000"
9070 /* 21607 */ "dup_A4_combineri\000"
9071 /* 21624 */ "C2_bitsclri\000"
9072 /* 21636 */ "C4_nbitsclri\000"
9073 /* 21649 */ "S4_or_ori\000"
9074 /* 21659 */ "S2_addasl_rrri\000"
9075 /* 21674 */ "C2_muxri\000"
9076 /* 21683 */ "J2_ploop1si\000"
9077 /* 21695 */ "J2_ploop2si\000"
9078 /* 21707 */ "J2_ploop3si\000"
9079 /* 21719 */ "dup_A2_tfrsi\000"
9080 /* 21732 */ "V6_vrmpybusi\000"
9081 /* 21745 */ "SA1_seti\000"
9082 /* 21754 */ "J4_jumpseti\000"
9083 /* 21766 */ "A4_cmpbgti\000"
9084 /* 21777 */ "A4_vcmpbgti\000"
9085 /* 21789 */ "A4_cmphgti\000"
9086 /* 21800 */ "A4_vcmphgti\000"
9087 /* 21812 */ "C2_cmpgti\000"
9088 /* 21822 */ "A4_vcmpwgti\000"
9089 /* 21834 */ "A4_bitspliti\000"
9090 /* 21847 */ "C2_cmpgeui\000"
9091 /* 21858 */ "C4_cmplteui\000"
9092 /* 21870 */ "A4_cmpbgtui\000"
9093 /* 21882 */ "A4_vcmpbgtui\000"
9094 /* 21895 */ "A4_cmphgtui\000"
9095 /* 21907 */ "A4_vcmphgtui\000"
9096 /* 21920 */ "C2_cmpgtui\000"
9097 /* 21931 */ "A4_vcmpwgtui\000"
9098 /* 21944 */ "M2_mpyui\000"
9099 /* 21953 */ "R6_release_at_vi\000"
9100 /* 21970 */ "S4_stored_rl_at_vi\000"
9101 /* 21989 */ "S2_storew_rl_at_vi\000"
9102 /* 22008 */ "R6_release_st_vi\000"
9103 /* 22025 */ "S4_stored_rl_st_vi\000"
9104 /* 22044 */ "S2_storew_rl_st_vi\000"
9105 /* 22063 */ "Y2_swi\000"
9106 /* 22070 */ "Y2_cswi\000"
9107 /* 22078 */ "M2_mpyi\000"
9108 /* 22086 */ "A2_vconj\000"
9109 /* 22095 */ "Y2_break\000"
9110 /* 22104 */ "M2_vmpy2s_s0pack\000"
9111 /* 22121 */ "M2_vmpy2s_s1pack\000"
9112 /* 22138 */ "S2_vsathb_nopack\000"
9113 /* 22155 */ "S2_vsathub_nopack\000"
9114 /* 22173 */ "S2_vsatwuh_nopack\000"
9115 /* 22191 */ "S2_vsatwh_nopack\000"
9116 /* 22208 */ "C2_vitpack\000"
9117 /* 22219 */ "A4_boundscheck\000"
9118 /* 22234 */ "Y2_k0lock\000"
9119 /* 22244 */ "Y2_tlblock\000"
9120 /* 22255 */ "Y2_k0unlock\000"
9121 /* 22267 */ "Y2_tlbunlock\000"
9122 /* 22280 */ "Y5_l2gunlock\000"
9123 /* 22293 */ "Y6_dmlink\000"
9124 /* 22303 */ "C2_mask\000"
9125 /* 22311 */ "S2_mask\000"
9126 /* 22319 */ "Y2_getimask\000"
9127 /* 22331 */ "Y2_setimask\000"
9128 /* 22343 */ "PS_call_stk\000"
9129 /* 22355 */ "M2_vrcmpys_acc_s1_l\000"
9130 /* 22375 */ "M2_vrcmpys_s1_l\000"
9131 /* 22391 */ "M2_vrcmpys_s1rp_l\000"
9132 /* 22409 */ "V6_vdeal\000"
9133 /* 22418 */ "A2_subh_h16_hl\000"
9134 /* 22433 */ "A2_addh_h16_hl\000"
9135 /* 22448 */ "A2_subh_l16_hl\000"
9136 /* 22463 */ "A2_addh_l16_hl\000"
9137 /* 22478 */ "A2_combine_hl\000"
9138 /* 22492 */ "A2_subh_h16_sat_hl\000"
9139 /* 22511 */ "A2_addh_h16_sat_hl\000"
9140 /* 22530 */ "A2_subh_l16_sat_hl\000"
9141 /* 22549 */ "A2_addh_l16_sat_hl\000"
9142 /* 22568 */ "dep_S2_packhl\000"
9143 /* 22582 */ "A2_tfril\000"
9144 /* 22591 */ "A2_subh_h16_ll\000"
9145 /* 22606 */ "A2_addh_h16_ll\000"
9146 /* 22621 */ "A2_subh_l16_ll\000"
9147 /* 22636 */ "A2_addh_l16_ll\000"
9148 /* 22651 */ "A2_combine_ll\000"
9149 /* 22665 */ "A2_subh_h16_sat_ll\000"
9150 /* 22684 */ "A2_addh_h16_sat_ll\000"
9151 /* 22703 */ "A2_subh_l16_sat_ll\000"
9152 /* 22722 */ "A2_addh_l16_sat_ll\000"
9153 /* 22741 */ "J2_call\000"
9154 /* 22749 */ "Y2_l2kill\000"
9155 /* 22759 */ "Y2_dckill\000"
9156 /* 22769 */ "Y2_ickill\000"
9157 /* 22779 */ "Y6_dmpoll\000"
9158 /* 22789 */ "F2_dfmpyll\000"
9159 /* 22800 */ "A2_addspl\000"
9160 /* 22810 */ "V6_vwhist128m\000"
9161 /* 22824 */ "V6_vlutvvb_nm\000"
9162 /* 22838 */ "V6_vlutvwh_nm\000"
9163 /* 22852 */ "PS_call_instrprof_custom\000"
9164 /* 22877 */ "V6_vwhist128qm\000"
9165 /* 22892 */ "S2_clbnorm\000"
9166 /* 22903 */ "S4_clbpnorm\000"
9167 /* 22915 */ "V6_pred_and_n\000"
9168 /* 22929 */ "F2_dfimm_n\000"
9169 /* 22940 */ "F2_sfimm_n\000"
9170 /* 22951 */ "V6_pred_or_n\000"
9171 /* 22964 */ "Y5_l2gclean\000"
9172 /* 22976 */ "C2_andn\000"
9173 /* 22984 */ "A4_andn\000"
9174 /* 22992 */ "C4_and_andn\000"
9175 /* 23004 */ "M4_and_andn\000"
9176 /* 23016 */ "C4_or_andn\000"
9177 /* 23027 */ "M4_or_andn\000"
9178 /* 23038 */ "M4_xor_andn\000"
9179 /* 23050 */ "V6_vassign\000"
9180 /* 23061 */ "S2_cabacdecbin\000"
9181 /* 23076 */ "A2_min\000"
9182 /* 23083 */ "F2_dfmin\000"
9183 /* 23092 */ "F2_sfmin\000"
9184 /* 23101 */ "M2_macsin\000"
9185 /* 23111 */ "M2_mpysin\000"
9186 /* 23121 */ "F2_sffixupn\000"
9187 /* 23133 */ "C2_orn\000"
9188 /* 23140 */ "A4_orn\000"
9189 /* 23147 */ "C4_and_orn\000"
9190 /* 23158 */ "C4_or_orn\000"
9191 /* 23168 */ "SL2_return\000"
9192 /* 23179 */ "L4_return\000"
9193 /* 23189 */ "S2_asr_i_svw_trun\000"
9194 /* 23207 */ "S2_asr_r_svw_trun\000"
9195 /* 23225 */ "Y2_dcfetchbo\000"
9196 /* 23238 */ "DUPLEX_Pseudo\000"
9197 /* 23252 */ "V6_vgathermh_pseudo\000"
9198 /* 23272 */ "V6_vgathermhq_pseudo\000"
9199 /* 23293 */ "V6_vgathermhwq_pseudo\000"
9200 /* 23315 */ "V6_vgathermwq_pseudo\000"
9201 /* 23336 */ "V6_vgathermhw_pseudo\000"
9202 /* 23357 */ "V6_vgathermw_pseudo\000"
9203 /* 23377 */ "L2_loadbsw2_io\000"
9204 /* 23392 */ "L2_loadbzw2_io\000"
9205 /* 23407 */ "L2_loadbsw4_io\000"
9206 /* 23422 */ "L2_loadbzw4_io\000"
9207 /* 23437 */ "SS1_storeb_io\000"
9208 /* 23451 */ "L2_loadalignb_io\000"
9209 /* 23468 */ "L4_sub_memopb_io\000"
9210 /* 23485 */ "L4_isub_memopb_io\000"
9211 /* 23503 */ "L4_add_memopb_io\000"
9212 /* 23520 */ "L4_iadd_memopb_io\000"
9213 /* 23538 */ "L4_and_memopb_io\000"
9214 /* 23555 */ "L4_iand_memopb_io\000"
9215 /* 23573 */ "L4_or_memopb_io\000"
9216 /* 23589 */ "L4_ior_memopb_io\000"
9217 /* 23606 */ "SL2_loadrb_io\000"
9218 /* 23620 */ "dup_L2_loadrb_io\000"
9219 /* 23637 */ "dup_S2_storerb_io\000"
9220 /* 23655 */ "dup_S4_storeirb_io\000"
9221 /* 23674 */ "SL1_loadrub_io\000"
9222 /* 23689 */ "dup_L2_loadrub_io\000"
9223 /* 23707 */ "dup_L2_loadrd_io\000"
9224 /* 23724 */ "dup_S2_storerd_io\000"
9225 /* 23742 */ "L2_ploadrbf_io\000"
9226 /* 23757 */ "S2_pstorerbf_io\000"
9227 /* 23773 */ "S4_storeirbf_io\000"
9228 /* 23789 */ "L2_ploadrubf_io\000"
9229 /* 23805 */ "L2_ploadrdf_io\000"
9230 /* 23820 */ "S2_pstorerdf_io\000"
9231 /* 23836 */ "S2_pstorerff_io\000"
9232 /* 23852 */ "L2_ploadrhf_io\000"
9233 /* 23867 */ "S2_pstorerhf_io\000"
9234 /* 23883 */ "S4_storeirhf_io\000"
9235 /* 23899 */ "L2_ploadruhf_io\000"
9236 /* 23915 */ "L2_ploadrif_io\000"
9237 /* 23930 */ "S2_pstorerif_io\000"
9238 /* 23946 */ "S4_storeirif_io\000"
9239 /* 23962 */ "S2_storerf_io\000"
9240 /* 23976 */ "S2_pstorerbnewf_io\000"
9241 /* 23995 */ "S2_pstorerhnewf_io\000"
9242 /* 24014 */ "S2_pstorerinewf_io\000"
9243 /* 24033 */ "SS2_storeh_io\000"
9244 /* 24047 */ "L2_loadalignh_io\000"
9245 /* 24064 */ "L4_sub_memoph_io\000"
9246 /* 24081 */ "L4_isub_memoph_io\000"
9247 /* 24099 */ "L4_add_memoph_io\000"
9248 /* 24116 */ "L4_iadd_memoph_io\000"
9249 /* 24134 */ "L4_and_memoph_io\000"
9250 /* 24151 */ "L4_iand_memoph_io\000"
9251 /* 24169 */ "L4_or_memoph_io\000"
9252 /* 24185 */ "L4_ior_memoph_io\000"
9253 /* 24202 */ "SL2_loadrh_io\000"
9254 /* 24216 */ "dup_L2_loadrh_io\000"
9255 /* 24233 */ "dup_S2_storerh_io\000"
9256 /* 24251 */ "S4_storeirh_io\000"
9257 /* 24266 */ "SL2_loadruh_io\000"
9258 /* 24281 */ "dup_L2_loadruh_io\000"
9259 /* 24299 */ "SL1_loadri_io\000"
9260 /* 24313 */ "dup_L2_loadri_io\000"
9261 /* 24330 */ "dup_S2_storeri_io\000"
9262 /* 24348 */ "dup_S4_storeiri_io\000"
9263 /* 24367 */ "L2_ploadrbt_io\000"
9264 /* 24382 */ "S2_pstorerbt_io\000"
9265 /* 24398 */ "S4_storeirbt_io\000"
9266 /* 24414 */ "L2_ploadrubt_io\000"
9267 /* 24430 */ "L2_ploadrdt_io\000"
9268 /* 24445 */ "S2_pstorerdt_io\000"
9269 /* 24461 */ "S2_pstorerft_io\000"
9270 /* 24477 */ "L2_ploadrht_io\000"
9271 /* 24492 */ "S2_pstorerht_io\000"
9272 /* 24508 */ "S4_storeirht_io\000"
9273 /* 24524 */ "L2_ploadruht_io\000"
9274 /* 24540 */ "L2_ploadrit_io\000"
9275 /* 24555 */ "S2_pstorerit_io\000"
9276 /* 24571 */ "S4_storeirit_io\000"
9277 /* 24587 */ "S2_pstorerbnewt_io\000"
9278 /* 24606 */ "S2_pstorerhnewt_io\000"
9279 /* 24625 */ "S2_pstorerinewt_io\000"
9280 /* 24644 */ "S2_storerbnew_io\000"
9281 /* 24661 */ "L2_ploadrbfnew_io\000"
9282 /* 24679 */ "S4_pstorerbfnew_io\000"
9283 /* 24698 */ "S4_storeirbfnew_io\000"
9284 /* 24717 */ "L2_ploadrubfnew_io\000"
9285 /* 24736 */ "L2_ploadrdfnew_io\000"
9286 /* 24754 */ "S4_pstorerdfnew_io\000"
9287 /* 24773 */ "S4_pstorerffnew_io\000"
9288 /* 24792 */ "L2_ploadrhfnew_io\000"
9289 /* 24810 */ "S4_pstorerhfnew_io\000"
9290 /* 24829 */ "S4_storeirhfnew_io\000"
9291 /* 24848 */ "L2_ploadruhfnew_io\000"
9292 /* 24867 */ "L2_ploadrifnew_io\000"
9293 /* 24885 */ "S4_pstorerifnew_io\000"
9294 /* 24904 */ "S4_storeirifnew_io\000"
9295 /* 24923 */ "S4_pstorerbnewfnew_io\000"
9296 /* 24945 */ "S4_pstorerhnewfnew_io\000"
9297 /* 24967 */ "S4_pstorerinewfnew_io\000"
9298 /* 24989 */ "S2_storerhnew_io\000"
9299 /* 25006 */ "S2_storerinew_io\000"
9300 /* 25023 */ "L2_ploadrbtnew_io\000"
9301 /* 25041 */ "S4_pstorerbtnew_io\000"
9302 /* 25060 */ "S4_storeirbtnew_io\000"
9303 /* 25079 */ "L2_ploadrubtnew_io\000"
9304 /* 25098 */ "L2_ploadrdtnew_io\000"
9305 /* 25116 */ "S4_pstorerdtnew_io\000"
9306 /* 25135 */ "S4_pstorerftnew_io\000"
9307 /* 25154 */ "L2_ploadrhtnew_io\000"
9308 /* 25172 */ "S4_pstorerhtnew_io\000"
9309 /* 25191 */ "S4_storeirhtnew_io\000"
9310 /* 25210 */ "L2_ploadruhtnew_io\000"
9311 /* 25229 */ "L2_ploadritnew_io\000"
9312 /* 25247 */ "S4_pstoreritnew_io\000"
9313 /* 25266 */ "S4_storeiritnew_io\000"
9314 /* 25285 */ "S4_pstorerbnewtnew_io\000"
9315 /* 25307 */ "S4_pstorerhnewtnew_io\000"
9316 /* 25329 */ "S4_pstorerinewtnew_io\000"
9317 /* 25351 */ "SS1_storew_io\000"
9318 /* 25365 */ "L4_sub_memopw_io\000"
9319 /* 25382 */ "L4_isub_memopw_io\000"
9320 /* 25400 */ "L4_add_memopw_io\000"
9321 /* 25417 */ "L4_iadd_memopw_io\000"
9322 /* 25435 */ "L4_and_memopw_io\000"
9323 /* 25452 */ "L4_iand_memopw_io\000"
9324 /* 25470 */ "L4_or_memopw_io\000"
9325 /* 25486 */ "L4_ior_memopw_io\000"
9326 /* 25503 */ "Y2_setprio\000"
9327 /* 25514 */ "V6_lo\000"
9328 /* 25520 */ "A4_boundscheck_lo\000"
9329 /* 25538 */ "V6_vasr_into\000"
9330 /* 25551 */ "F2_dfcmpuo\000"
9331 /* 25562 */ "F2_sfcmpuo\000"
9332 /* 25573 */ "V6_vsubcarryo\000"
9333 /* 25587 */ "V6_vaddcarryo\000"
9334 /* 25601 */ "S2_cl0p\000"
9335 /* 25609 */ "S2_ct0p\000"
9336 /* 25617 */ "S2_cl1p\000"
9337 /* 25625 */ "S2_ct1p\000"
9338 /* 25633 */ "S6_rol_i_p\000"
9339 /* 25644 */ "S2_asl_i_p\000"
9340 /* 25655 */ "S2_asr_i_p\000"
9341 /* 25666 */ "S2_lsr_i_p\000"
9342 /* 25677 */ "F2_dfimm_p\000"
9343 /* 25688 */ "F2_sfimm_p\000"
9344 /* 25699 */ "S2_asl_r_p\000"
9345 /* 25710 */ "S2_lsl_r_p\000"
9346 /* 25721 */ "S2_asr_r_p\000"
9347 /* 25732 */ "S2_lsr_r_p\000"
9348 /* 25743 */ "L4_loadbsw2_ap\000"
9349 /* 25758 */ "L4_loadbzw2_ap\000"
9350 /* 25773 */ "L4_loadbsw4_ap\000"
9351 /* 25788 */ "L4_loadbzw4_ap\000"
9352 /* 25803 */ "L4_loadalignb_ap\000"
9353 /* 25820 */ "L4_loadrb_ap\000"
9354 /* 25833 */ "S4_storerb_ap\000"
9355 /* 25847 */ "L4_loadrub_ap\000"
9356 /* 25861 */ "L4_loadrd_ap\000"
9357 /* 25874 */ "S4_storerd_ap\000"
9358 /* 25888 */ "S4_storerf_ap\000"
9359 /* 25902 */ "L4_loadalignh_ap\000"
9360 /* 25919 */ "L4_loadrh_ap\000"
9361 /* 25932 */ "S4_storerh_ap\000"
9362 /* 25946 */ "L4_loadruh_ap\000"
9363 /* 25960 */ "L4_loadri_ap\000"
9364 /* 25973 */ "S4_storeri_ap\000"
9365 /* 25987 */ "S4_storerbnew_ap\000"
9366 /* 26004 */ "S4_storerhnew_ap\000"
9367 /* 26021 */ "S4_storerinew_ap\000"
9368 /* 26038 */ "V6_vtran2x2_map\000"
9369 /* 26054 */ "A2_vsubb_map\000"
9370 /* 26067 */ "A2_vaddb_map\000"
9371 /* 26080 */ "J2_jumpf_nopred_map\000"
9372 /* 26100 */ "J2_jumprf_nopred_map\000"
9373 /* 26121 */ "J2_jumpt_nopred_map\000"
9374 /* 26141 */ "J2_jumprt_nopred_map\000"
9375 /* 26162 */ "Y2_k1lock_map\000"
9376 /* 26176 */ "Y2_k1unlock_map\000"
9377 /* 26192 */ "C2_pxfer_map\000"
9378 /* 26205 */ "J2_trap1_noregmap\000"
9379 /* 26223 */ "L2_loadbsw2_zomap\000"
9380 /* 26241 */ "L2_loadbzw2_zomap\000"
9381 /* 26259 */ "L2_loadbsw4_zomap\000"
9382 /* 26277 */ "L2_loadbzw4_zomap\000"
9383 /* 26295 */ "L2_loadalignb_zomap\000"
9384 /* 26315 */ "L4_sub_memopb_zomap\000"
9385 /* 26335 */ "L4_isub_memopb_zomap\000"
9386 /* 26356 */ "L4_add_memopb_zomap\000"
9387 /* 26376 */ "L4_iadd_memopb_zomap\000"
9388 /* 26397 */ "L4_and_memopb_zomap\000"
9389 /* 26417 */ "L4_iand_memopb_zomap\000"
9390 /* 26438 */ "L4_or_memopb_zomap\000"
9391 /* 26457 */ "L4_ior_memopb_zomap\000"
9392 /* 26477 */ "L2_loadrb_zomap\000"
9393 /* 26493 */ "S2_storerb_zomap\000"
9394 /* 26510 */ "S4_storeirb_zomap\000"
9395 /* 26528 */ "L2_loadrub_zomap\000"
9396 /* 26545 */ "L2_loadrd_zomap\000"
9397 /* 26561 */ "S2_storerd_zomap\000"
9398 /* 26578 */ "L2_ploadrbf_zomap\000"
9399 /* 26596 */ "S2_pstorerbf_zomap\000"
9400 /* 26615 */ "S4_storeirbf_zomap\000"
9401 /* 26634 */ "L2_ploadrubf_zomap\000"
9402 /* 26653 */ "L2_ploadrdf_zomap\000"
9403 /* 26671 */ "S2_pstorerdf_zomap\000"
9404 /* 26690 */ "S2_pstorerff_zomap\000"
9405 /* 26709 */ "L2_ploadrhf_zomap\000"
9406 /* 26727 */ "S2_pstorerhf_zomap\000"
9407 /* 26746 */ "S4_storeirhf_zomap\000"
9408 /* 26765 */ "L2_ploadruhf_zomap\000"
9409 /* 26784 */ "L2_ploadrif_zomap\000"
9410 /* 26802 */ "S2_pstorerif_zomap\000"
9411 /* 26821 */ "S4_storeirif_zomap\000"
9412 /* 26840 */ "S2_storerf_zomap\000"
9413 /* 26857 */ "S2_pstorerbnewf_zomap\000"
9414 /* 26879 */ "S2_pstorerhnewf_zomap\000"
9415 /* 26901 */ "S2_pstorerinewf_zomap\000"
9416 /* 26923 */ "L2_loadalignh_zomap\000"
9417 /* 26943 */ "L4_sub_memoph_zomap\000"
9418 /* 26963 */ "L4_isub_memoph_zomap\000"
9419 /* 26984 */ "L4_add_memoph_zomap\000"
9420 /* 27004 */ "L4_iadd_memoph_zomap\000"
9421 /* 27025 */ "L4_and_memoph_zomap\000"
9422 /* 27045 */ "L4_iand_memoph_zomap\000"
9423 /* 27066 */ "L4_or_memoph_zomap\000"
9424 /* 27085 */ "L4_ior_memoph_zomap\000"
9425 /* 27105 */ "L2_loadrh_zomap\000"
9426 /* 27121 */ "S2_storerh_zomap\000"
9427 /* 27138 */ "S4_storeirh_zomap\000"
9428 /* 27156 */ "L2_loadruh_zomap\000"
9429 /* 27173 */ "L2_loadri_zomap\000"
9430 /* 27189 */ "S2_storeri_zomap\000"
9431 /* 27206 */ "S4_storeiri_zomap\000"
9432 /* 27224 */ "L2_ploadrbt_zomap\000"
9433 /* 27242 */ "S2_pstorerbt_zomap\000"
9434 /* 27261 */ "S4_storeirbt_zomap\000"
9435 /* 27280 */ "L2_ploadrubt_zomap\000"
9436 /* 27299 */ "L2_ploadrdt_zomap\000"
9437 /* 27317 */ "S2_pstorerdt_zomap\000"
9438 /* 27336 */ "S2_pstorerft_zomap\000"
9439 /* 27355 */ "L2_ploadrht_zomap\000"
9440 /* 27373 */ "S2_pstorerht_zomap\000"
9441 /* 27392 */ "S4_storeirht_zomap\000"
9442 /* 27411 */ "L2_ploadruht_zomap\000"
9443 /* 27430 */ "L2_ploadrit_zomap\000"
9444 /* 27448 */ "S2_pstorerit_zomap\000"
9445 /* 27467 */ "S4_storeirit_zomap\000"
9446 /* 27486 */ "S2_pstorerbnewt_zomap\000"
9447 /* 27508 */ "S2_pstorerhnewt_zomap\000"
9448 /* 27530 */ "S2_pstorerinewt_zomap\000"
9449 /* 27552 */ "S2_storerbnew_zomap\000"
9450 /* 27572 */ "L2_ploadrbfnew_zomap\000"
9451 /* 27593 */ "S4_pstorerbfnew_zomap\000"
9452 /* 27615 */ "S4_storeirbfnew_zomap\000"
9453 /* 27637 */ "L2_ploadrubfnew_zomap\000"
9454 /* 27659 */ "L2_ploadrdfnew_zomap\000"
9455 /* 27680 */ "S4_pstorerdfnew_zomap\000"
9456 /* 27702 */ "S4_pstorerffnew_zomap\000"
9457 /* 27724 */ "L2_ploadrhfnew_zomap\000"
9458 /* 27745 */ "S4_pstorerhfnew_zomap\000"
9459 /* 27767 */ "S4_storeirhfnew_zomap\000"
9460 /* 27789 */ "L2_ploadruhfnew_zomap\000"
9461 /* 27811 */ "L2_ploadrifnew_zomap\000"
9462 /* 27832 */ "S4_pstorerifnew_zomap\000"
9463 /* 27854 */ "S4_storeirifnew_zomap\000"
9464 /* 27876 */ "S4_pstorerbnewfnew_zomap\000"
9465 /* 27901 */ "S4_pstorerhnewfnew_zomap\000"
9466 /* 27926 */ "S4_pstorerinewfnew_zomap\000"
9467 /* 27951 */ "S2_storerhnew_zomap\000"
9468 /* 27971 */ "S2_storerinew_zomap\000"
9469 /* 27991 */ "L2_ploadrbtnew_zomap\000"
9470 /* 28012 */ "S4_pstorerbtnew_zomap\000"
9471 /* 28034 */ "S4_storeirbtnew_zomap\000"
9472 /* 28056 */ "L2_ploadrubtnew_zomap\000"
9473 /* 28078 */ "L2_ploadrdtnew_zomap\000"
9474 /* 28099 */ "S4_pstorerdtnew_zomap\000"
9475 /* 28121 */ "S4_pstorerftnew_zomap\000"
9476 /* 28143 */ "L2_ploadrhtnew_zomap\000"
9477 /* 28164 */ "S4_pstorerhtnew_zomap\000"
9478 /* 28186 */ "S4_storeirhtnew_zomap\000"
9479 /* 28208 */ "L2_ploadruhtnew_zomap\000"
9480 /* 28230 */ "L2_ploadritnew_zomap\000"
9481 /* 28251 */ "S4_pstoreritnew_zomap\000"
9482 /* 28273 */ "S4_storeiritnew_zomap\000"
9483 /* 28295 */ "S4_pstorerbnewtnew_zomap\000"
9484 /* 28320 */ "S4_pstorerhnewtnew_zomap\000"
9485 /* 28345 */ "S4_pstorerinewtnew_zomap\000"
9486 /* 28370 */ "L4_sub_memopw_zomap\000"
9487 /* 28390 */ "L4_isub_memopw_zomap\000"
9488 /* 28411 */ "L4_add_memopw_zomap\000"
9489 /* 28431 */ "L4_iadd_memopw_zomap\000"
9490 /* 28452 */ "L4_and_memopw_zomap\000"
9491 /* 28472 */ "L4_iand_memopw_zomap\000"
9492 /* 28493 */ "L4_or_memopw_zomap\000"
9493 /* 28512 */ "L4_ior_memopw_zomap\000"
9494 /* 28532 */ "V6_vswap\000"
9495 /* 28541 */ "S2_clbp\000"
9496 /* 28549 */ "Y2_tlbp\000"
9497 /* 28557 */ "S6_vsplatrbp\000"
9498 /* 28570 */ "A2_subp\000"
9499 /* 28578 */ "G4_tfrgpcp\000"
9500 /* 28589 */ "A4_tfrpcp\000"
9501 /* 28599 */ "Y4_tfrspcp\000"
9502 /* 28610 */ "A2_addp\000"
9503 /* 28618 */ "A2_andp\000"
9504 /* 28626 */ "V6_vassign_fp\000"
9505 /* 28640 */ "L2_loadrbgp\000"
9506 /* 28652 */ "S2_storerbgp\000"
9507 /* 28665 */ "L2_loadrubgp\000"
9508 /* 28678 */ "L2_loadrdgp\000"
9509 /* 28690 */ "S2_storerdgp\000"
9510 /* 28703 */ "A2_negp\000"
9511 /* 28711 */ "S2_storerfgp\000"
9512 /* 28724 */ "L2_loadrhgp\000"
9513 /* 28736 */ "S2_storerhgp\000"
9514 /* 28749 */ "L2_loadruhgp\000"
9515 /* 28762 */ "L2_loadrigp\000"
9516 /* 28774 */ "S2_storerigp\000"
9517 /* 28787 */ "S2_storerbnewgp\000"
9518 /* 28803 */ "S2_storerhnewgp\000"
9519 /* 28819 */ "S2_storerinewgp\000"
9520 /* 28835 */ "A7_clip\000"
9521 /* 28843 */ "A7_vclip\000"
9522 /* 28852 */ "M2_macsip\000"
9523 /* 28862 */ "M2_mpysip\000"
9524 /* 28872 */ "V6_vcombine_tmp\000"
9525 /* 28888 */ "V6_vassign_tmp\000"
9526 /* 28903 */ "J2_jump\000"
9527 /* 28911 */ "A4_andnp\000"
9528 /* 28920 */ "V6_vassignp\000"
9529 /* 28932 */ "A2_minp\000"
9530 /* 28940 */ "A4_ornp\000"
9531 /* 28948 */ "F2_conv_df2d_chop\000"
9532 /* 28966 */ "F2_conv_sf2d_chop\000"
9533 /* 28984 */ "F2_conv_df2ud_chop\000"
9534 /* 29003 */ "F2_conv_sf2ud_chop\000"
9535 /* 29022 */ "F2_conv_df2w_chop\000"
9536 /* 29040 */ "F2_conv_sf2w_chop\000"
9537 /* 29058 */ "F2_conv_df2uw_chop\000"
9538 /* 29077 */ "F2_conv_sf2uw_chop\000"
9539 /* 29096 */ "A2_nop\000"
9540 /* 29103 */ "Y2_stop\000"
9541 /* 29111 */ "G4_tfrgcpp\000"
9542 /* 29122 */ "A4_tfrcpp\000"
9543 /* 29132 */ "Y4_tfrscpp\000"
9544 /* 29143 */ "S6_vtrunehb_ppp\000"
9545 /* 29159 */ "S6_vtrunohb_ppp\000"
9546 /* 29175 */ "C2_cmpeqp\000"
9547 /* 29185 */ "M2_vrcmpys_s1rp\000"
9548 /* 29201 */ "S4_extractp_rp\000"
9549 /* 29216 */ "S2_insertp_rp\000"
9550 /* 29230 */ "S2_extractup_rp\000"
9551 /* 29246 */ "S4_extract_rp\000"
9552 /* 29260 */ "S2_insert_rp\000"
9553 /* 29273 */ "S2_extractu_rp\000"
9554 /* 29288 */ "A2_tfrp\000"
9555 /* 29296 */ "A2_orp\000"
9556 /* 29303 */ "A2_xorp\000"
9557 /* 29311 */ "C2_tfrrp\000"
9558 /* 29320 */ "SS2_stored_sp\000"
9559 /* 29334 */ "SL2_loadrd_sp\000"
9560 /* 29348 */ "SL2_loadri_sp\000"
9561 /* 29362 */ "SS2_storew_sp\000"
9562 /* 29376 */ "A2_absp\000"
9563 /* 29384 */ "SA1_addsp\000"
9564 /* 29394 */ "A2_addsp\000"
9565 /* 29403 */ "S2_lfsp\000"
9566 /* 29411 */ "S4_extractp\000"
9567 /* 29423 */ "C2_cmpgtp\000"
9568 /* 29433 */ "S5_popcountp\000"
9569 /* 29446 */ "A2_notp\000"
9570 /* 29454 */ "S2_insertp\000"
9571 /* 29465 */ "M2_mpysu_up\000"
9572 /* 29477 */ "M2_mpyu_up\000"
9573 /* 29488 */ "M2_mpy_up\000"
9574 /* 29498 */ "A2_minup\000"
9575 /* 29507 */ "S2_extractup\000"
9576 /* 29520 */ "C2_cmpgtup\000"
9577 /* 29531 */ "A2_maxup\000"
9578 /* 29540 */ "S2_brevp\000"
9579 /* 29549 */ "A2_maxp\000"
9580 /* 29557 */ "S2_parityp\000"
9581 /* 29568 */ "V6_vwhist256q\000"
9582 /* 29582 */ "V6_vwhist128q\000"
9583 /* 29596 */ "L4_loadd_aq\000"
9584 /* 29608 */ "L2_loadw_aq\000"
9585 /* 29620 */ "V6_vsubbq\000"
9586 /* 29630 */ "V6_vaddbq\000"
9587 /* 29640 */ "A4_cmpbeq\000"
9588 /* 29650 */ "A2_vcmpbeq\000"
9589 /* 29661 */ "A4_cmpheq\000"
9590 /* 29671 */ "A2_vcmpheq\000"
9591 /* 29682 */ "C4_cmpneq\000"
9592 /* 29692 */ "A4_rcmpneq\000"
9593 /* 29703 */ "C2_cmpeq\000"
9594 /* 29712 */ "F2_dfcmpeq\000"
9595 /* 29723 */ "F2_sfcmpeq\000"
9596 /* 29734 */ "A4_rcmpeq\000"
9597 /* 29744 */ "A2_vcmpweq\000"
9598 /* 29755 */ "V6_vsubhq\000"
9599 /* 29765 */ "V6_vaddhq\000"
9600 /* 29775 */ "V6_vgathermhq\000"
9601 /* 29789 */ "V6_vscattermhq\000"
9602 /* 29804 */ "V6_vsubbnq\000"
9603 /* 29815 */ "V6_vaddbnq\000"
9604 /* 29826 */ "V6_vsubhnq\000"
9605 /* 29837 */ "V6_vaddhnq\000"
9606 /* 29848 */ "V6_vsubwnq\000"
9607 /* 29859 */ "V6_vaddwnq\000"
9608 /* 29870 */ "V6_vhistq\000"
9609 /* 29880 */ "V6_vsubwq\000"
9610 /* 29890 */ "V6_vaddwq\000"
9611 /* 29900 */ "V6_vgathermhwq\000"
9612 /* 29915 */ "V6_vscattermhwq\000"
9613 /* 29931 */ "V6_vgathermwq\000"
9614 /* 29945 */ "V6_vscattermwq\000"
9615 /* 29960 */ "J2_loop0r\000"
9616 /* 29970 */ "J2_loop1r\000"
9617 /* 29980 */ "S6_rol_i_r\000"
9618 /* 29991 */ "S2_asl_i_r\000"
9619 /* 30002 */ "S2_asr_i_r\000"
9620 /* 30013 */ "S2_lsr_i_r\000"
9621 /* 30024 */ "PS_tailcall_r\000"
9622 /* 30038 */ "S2_asl_r_r\000"
9623 /* 30049 */ "S2_lsl_r_r\000"
9624 /* 30060 */ "S2_asr_r_r\000"
9625 /* 30071 */ "S2_lsr_r_r\000"
9626 /* 30082 */ "M2_vcmac_s0_sat_r\000"
9627 /* 30100 */ "M2_vcmpy_s0_sat_r\000"
9628 /* 30118 */ "M2_vcmpy_s1_sat_r\000"
9629 /* 30136 */ "S2_togglebit_r\000"
9630 /* 30151 */ "S2_clrbit_r\000"
9631 /* 30163 */ "S2_setbit_r\000"
9632 /* 30175 */ "S2_tstbit_r\000"
9633 /* 30187 */ "S4_ntstbit_r\000"
9634 /* 30200 */ "Y2_icdatar\000"
9635 /* 30211 */ "Y2_tlbr\000"
9636 /* 30219 */ "L2_loadbsw2_pbr\000"
9637 /* 30235 */ "L2_loadbzw2_pbr\000"
9638 /* 30251 */ "L2_loadbsw4_pbr\000"
9639 /* 30267 */ "L2_loadbzw4_pbr\000"
9640 /* 30283 */ "L2_loadalignb_pbr\000"
9641 /* 30301 */ "L2_loadrb_pbr\000"
9642 /* 30315 */ "S2_storerb_pbr\000"
9643 /* 30330 */ "L2_loadrub_pbr\000"
9644 /* 30345 */ "L2_loadrd_pbr\000"
9645 /* 30359 */ "S2_storerd_pbr\000"
9646 /* 30374 */ "S2_storerf_pbr\000"
9647 /* 30389 */ "L2_loadalignh_pbr\000"
9648 /* 30407 */ "L2_loadrh_pbr\000"
9649 /* 30421 */ "S2_storerh_pbr\000"
9650 /* 30436 */ "L2_loadruh_pbr\000"
9651 /* 30451 */ "L2_loadri_pbr\000"
9652 /* 30465 */ "S2_storeri_pbr\000"
9653 /* 30480 */ "S2_storerbnew_pbr\000"
9654 /* 30498 */ "S2_storerhnew_pbr\000"
9655 /* 30516 */ "S2_storerinew_pbr\000"
9656 /* 30534 */ "A2_vavgubr\000"
9657 /* 30545 */ "A2_vnavghcr\000"
9658 /* 30557 */ "A2_vavghcr\000"
9659 /* 30568 */ "L2_loadbsw2_pcr\000"
9660 /* 30584 */ "L2_loadbzw2_pcr\000"
9661 /* 30600 */ "L2_loadbsw4_pcr\000"
9662 /* 30616 */ "L2_loadbzw4_pcr\000"
9663 /* 30632 */ "L2_loadalignb_pcr\000"
9664 /* 30650 */ "L2_loadrb_pcr\000"
9665 /* 30664 */ "PS_loadrb_pcr\000"
9666 /* 30678 */ "S2_storerb_pcr\000"
9667 /* 30693 */ "PS_storerb_pcr\000"
9668 /* 30708 */ "L2_loadrub_pcr\000"
9669 /* 30723 */ "PS_loadrub_pcr\000"
9670 /* 30738 */ "L2_loadrd_pcr\000"
9671 /* 30752 */ "PS_loadrd_pcr\000"
9672 /* 30766 */ "S2_storerd_pcr\000"
9673 /* 30781 */ "PS_storerd_pcr\000"
9674 /* 30796 */ "S2_storerf_pcr\000"
9675 /* 30811 */ "PS_storerf_pcr\000"
9676 /* 30826 */ "L2_loadalignh_pcr\000"
9677 /* 30844 */ "L2_loadrh_pcr\000"
9678 /* 30858 */ "PS_loadrh_pcr\000"
9679 /* 30872 */ "S2_storerh_pcr\000"
9680 /* 30887 */ "PS_storerh_pcr\000"
9681 /* 30902 */ "L2_loadruh_pcr\000"
9682 /* 30917 */ "PS_loadruh_pcr\000"
9683 /* 30932 */ "L2_loadri_pcr\000"
9684 /* 30946 */ "PS_loadri_pcr\000"
9685 /* 30960 */ "S2_storeri_pcr\000"
9686 /* 30975 */ "PS_storeri_pcr\000"
9687 /* 30990 */ "S2_storerbnew_pcr\000"
9688 /* 31008 */ "S2_storerhnew_pcr\000"
9689 /* 31026 */ "S2_storerinew_pcr\000"
9690 /* 31044 */ "G4_tfrgrcr\000"
9691 /* 31055 */ "A2_tfrrcr\000"
9692 /* 31065 */ "Y2_tfrsrcr\000"
9693 /* 31076 */ "A2_vnavgwcr\000"
9694 /* 31088 */ "A2_vavgwcr\000"
9695 /* 31099 */ "M4_mpyri_addr\000"
9696 /* 31113 */ "M4_mpyrr_addr\000"
9697 /* 31127 */ "Y2_barrier\000"
9698 /* 31138 */ "SA1_tfr\000"
9699 /* 31146 */ "dup_A2_tfr\000"
9700 /* 31157 */ "Y4_l2tagr\000"
9701 /* 31167 */ "Y2_dctagr\000"
9702 /* 31177 */ "Y2_ictagr\000"
9703 /* 31187 */ "S4_vxaddsubhr\000"
9704 /* 31201 */ "S4_vxsubaddhr\000"
9705 /* 31215 */ "A2_vnavghr\000"
9706 /* 31226 */ "A2_vavghr\000"
9707 /* 31236 */ "A2_vavguhr\000"
9708 /* 31247 */ "dup_A2_andir\000"
9709 /* 31260 */ "dup_A4_combineir\000"
9710 /* 31277 */ "A2_orir\000"
9711 /* 31285 */ "C2_muxir\000"
9712 /* 31294 */ "C2_bitsclr\000"
9713 /* 31305 */ "C4_nbitsclr\000"
9714 /* 31317 */ "J2_callr\000"
9715 /* 31326 */ "PS_call_nr\000"
9716 /* 31337 */ "PS_callr_nr\000"
9717 /* 31349 */ "Y2_iassignr\000"
9718 /* 31361 */ "A2_or\000"
9719 /* 31367 */ "C2_or\000"
9720 /* 31373 */ "V6_veqb_or\000"
9721 /* 31384 */ "V6_vgtb_or\000"
9722 /* 31395 */ "V6_vgtub_or\000"
9723 /* 31407 */ "V6_pred_or\000"
9724 /* 31418 */ "C4_and_or\000"
9725 /* 31428 */ "M4_and_or\000"
9726 /* 31438 */ "V6_vgtbf_or\000"
9727 /* 31450 */ "V6_vgthf_or\000"
9728 /* 31462 */ "V6_vgtsf_or\000"
9729 /* 31474 */ "V6_veqh_or\000"
9730 /* 31485 */ "V6_vgth_or\000"
9731 /* 31496 */ "V6_vgtuh_or\000"
9732 /* 31508 */ "S6_rol_i_p_or\000"
9733 /* 31522 */ "S2_asl_i_p_or\000"
9734 /* 31536 */ "S2_asr_i_p_or\000"
9735 /* 31550 */ "S2_lsr_i_p_or\000"
9736 /* 31564 */ "S2_asl_r_p_or\000"
9737 /* 31578 */ "S2_lsl_r_p_or\000"
9738 /* 31592 */ "S2_asr_r_p_or\000"
9739 /* 31606 */ "S2_lsr_r_p_or\000"
9740 /* 31620 */ "S6_rol_i_r_or\000"
9741 /* 31634 */ "S2_asl_i_r_or\000"
9742 /* 31648 */ "S2_asr_i_r_or\000"
9743 /* 31662 */ "S2_lsr_i_r_or\000"
9744 /* 31676 */ "S2_asl_r_r_or\000"
9745 /* 31690 */ "S2_lsl_r_r_or\000"
9746 /* 31704 */ "S2_asr_r_r_or\000"
9747 /* 31718 */ "S2_lsr_r_r_or\000"
9748 /* 31732 */ "C4_or_or\000"
9749 /* 31741 */ "M4_or_or\000"
9750 /* 31750 */ "M4_xor_or\000"
9751 /* 31760 */ "V6_veqw_or\000"
9752 /* 31771 */ "V6_vgtw_or\000"
9753 /* 31782 */ "V6_vgtuw_or\000"
9754 /* 31794 */ "V6_MAP_equb_ior\000"
9755 /* 31810 */ "V6_MAP_equh_ior\000"
9756 /* 31826 */ "V6_MAP_equw_ior\000"
9757 /* 31842 */ "V6_vror\000"
9758 /* 31850 */ "V6_vor\000"
9759 /* 31857 */ "A2_xor\000"
9760 /* 31864 */ "C2_xor\000"
9761 /* 31871 */ "V6_veqb_xor\000"
9762 /* 31883 */ "V6_vgtb_xor\000"
9763 /* 31895 */ "V6_MAP_equb_xor\000"
9764 /* 31911 */ "V6_vgtub_xor\000"
9765 /* 31924 */ "V6_pred_xor\000"
9766 /* 31936 */ "M4_and_xor\000"
9767 /* 31947 */ "V6_vgtbf_xor\000"
9768 /* 31960 */ "V6_vgthf_xor\000"
9769 /* 31973 */ "V6_vgtsf_xor\000"
9770 /* 31986 */ "V6_veqh_xor\000"
9771 /* 31998 */ "V6_vgth_xor\000"
9772 /* 32010 */ "V6_MAP_equh_xor\000"
9773 /* 32026 */ "V6_vgtuh_xor\000"
9774 /* 32039 */ "S2_asl_r_p_xor\000"
9775 /* 32054 */ "S2_lsl_r_p_xor\000"
9776 /* 32069 */ "S2_asr_r_p_xor\000"
9777 /* 32084 */ "S2_lsr_r_p_xor\000"
9778 /* 32099 */ "M4_or_xor\000"
9779 /* 32109 */ "V6_veqw_xor\000"
9780 /* 32121 */ "V6_vgtw_xor\000"
9781 /* 32133 */ "V6_MAP_equw_xor\000"
9782 /* 32149 */ "V6_vgtuw_xor\000"
9783 /* 32162 */ "V6_vxor\000"
9784 /* 32170 */ "L2_loadbsw2_pr\000"
9785 /* 32185 */ "L2_loadbzw2_pr\000"
9786 /* 32200 */ "L2_loadbsw4_pr\000"
9787 /* 32215 */ "L2_loadbzw4_pr\000"
9788 /* 32230 */ "L2_loadalignb_pr\000"
9789 /* 32247 */ "L2_loadrb_pr\000"
9790 /* 32260 */ "S2_storerb_pr\000"
9791 /* 32274 */ "L2_loadrub_pr\000"
9792 /* 32288 */ "L2_loadrd_pr\000"
9793 /* 32301 */ "S2_storerd_pr\000"
9794 /* 32315 */ "S2_storerf_pr\000"
9795 /* 32329 */ "L2_loadalignh_pr\000"
9796 /* 32346 */ "L2_loadrh_pr\000"
9797 /* 32359 */ "S2_storerh_pr\000"
9798 /* 32373 */ "L2_loadruh_pr\000"
9799 /* 32387 */ "L2_loadri_pr\000"
9800 /* 32400 */ "S2_storeri_pr\000"
9801 /* 32414 */ "S2_storerbnew_pr\000"
9802 /* 32431 */ "S2_storerhnew_pr\000"
9803 /* 32448 */ "S2_storerinew_pr\000"
9804 /* 32465 */ "J2_jumpr\000"
9805 /* 32474 */ "J4_hintjumpr\000"
9806 /* 32487 */ "C2_tfrpr\000"
9807 /* 32496 */ "F2_sffixupr\000"
9808 /* 32508 */ "L4_loadrb_rr\000"
9809 /* 32521 */ "S4_storerb_rr\000"
9810 /* 32535 */ "L4_loadrub_rr\000"
9811 /* 32549 */ "A7_croundd_rr\000"
9812 /* 32563 */ "A4_round_rr\000"
9813 /* 32575 */ "A4_cround_rr\000"
9814 /* 32588 */ "L4_loadrd_rr\000"
9815 /* 32601 */ "S4_storerd_rr\000"
9816 /* 32615 */ "L4_ploadrbf_rr\000"
9817 /* 32630 */ "S4_pstorerbf_rr\000"
9818 /* 32646 */ "L4_ploadrubf_rr\000"
9819 /* 32662 */ "L4_ploadrdf_rr\000"
9820 /* 32677 */ "S4_pstorerdf_rr\000"
9821 /* 32693 */ "S4_pstorerff_rr\000"
9822 /* 32709 */ "L4_ploadrhf_rr\000"
9823 /* 32724 */ "S4_pstorerhf_rr\000"
9824 /* 32740 */ "L4_ploadruhf_rr\000"
9825 /* 32756 */ "L4_ploadrif_rr\000"
9826 /* 32771 */ "S4_pstorerif_rr\000"
9827 /* 32787 */ "S4_storerf_rr\000"
9828 /* 32801 */ "S4_pstorerbnewf_rr\000"
9829 /* 32820 */ "S4_pstorerhnewf_rr\000"
9830 /* 32839 */ "S4_pstorerinewf_rr\000"
9831 /* 32858 */ "L4_loadrh_rr\000"
9832 /* 32871 */ "S4_storerh_rr\000"
9833 /* 32885 */ "L4_loadruh_rr\000"
9834 /* 32899 */ "L4_loadri_rr\000"
9835 /* 32912 */ "S4_storeri_rr\000"
9836 /* 32926 */ "L4_ploadrbt_rr\000"
9837 /* 32941 */ "S4_pstorerbt_rr\000"
9838 /* 32957 */ "L4_ploadrubt_rr\000"
9839 /* 32973 */ "L4_ploadrdt_rr\000"
9840 /* 32988 */ "S4_pstorerdt_rr\000"
9841 /* 33004 */ "S4_pstorerft_rr\000"
9842 /* 33020 */ "L4_ploadrht_rr\000"
9843 /* 33035 */ "S4_pstorerht_rr\000"
9844 /* 33051 */ "L4_ploadruht_rr\000"
9845 /* 33067 */ "L4_ploadrit_rr\000"
9846 /* 33082 */ "S4_pstorerit_rr\000"
9847 /* 33098 */ "S4_pstorerbnewt_rr\000"
9848 /* 33117 */ "S4_pstorerhnewt_rr\000"
9849 /* 33136 */ "S4_pstorerinewt_rr\000"
9850 /* 33155 */ "S4_storerbnew_rr\000"
9851 /* 33172 */ "L4_ploadrbfnew_rr\000"
9852 /* 33190 */ "S4_pstorerbfnew_rr\000"
9853 /* 33209 */ "L4_ploadrubfnew_rr\000"
9854 /* 33228 */ "L4_ploadrdfnew_rr\000"
9855 /* 33246 */ "S4_pstorerdfnew_rr\000"
9856 /* 33265 */ "S4_pstorerffnew_rr\000"
9857 /* 33284 */ "L4_ploadrhfnew_rr\000"
9858 /* 33302 */ "S4_pstorerhfnew_rr\000"
9859 /* 33321 */ "L4_ploadruhfnew_rr\000"
9860 /* 33340 */ "L4_ploadrifnew_rr\000"
9861 /* 33358 */ "S4_pstorerifnew_rr\000"
9862 /* 33377 */ "S4_pstorerbnewfnew_rr\000"
9863 /* 33399 */ "S4_pstorerhnewfnew_rr\000"
9864 /* 33421 */ "S4_pstorerinewfnew_rr\000"
9865 /* 33443 */ "S4_storerhnew_rr\000"
9866 /* 33460 */ "S4_storerinew_rr\000"
9867 /* 33477 */ "L4_ploadrbtnew_rr\000"
9868 /* 33495 */ "S4_pstorerbtnew_rr\000"
9869 /* 33514 */ "L4_ploadrubtnew_rr\000"
9870 /* 33533 */ "L4_ploadrdtnew_rr\000"
9871 /* 33551 */ "S4_pstorerdtnew_rr\000"
9872 /* 33570 */ "S4_pstorerftnew_rr\000"
9873 /* 33589 */ "L4_ploadrhtnew_rr\000"
9874 /* 33607 */ "S4_pstorerhtnew_rr\000"
9875 /* 33626 */ "L4_ploadruhtnew_rr\000"
9876 /* 33645 */ "L4_ploadritnew_rr\000"
9877 /* 33663 */ "S4_pstoreritnew_rr\000"
9878 /* 33682 */ "S4_pstorerbnewtnew_rr\000"
9879 /* 33704 */ "S4_pstorerhnewtnew_rr\000"
9880 /* 33726 */ "S4_pstorerinewtnew_rr\000"
9881 /* 33748 */ "G4_tfrgcrr\000"
9882 /* 33759 */ "A2_tfrcrr\000"
9883 /* 33769 */ "Y2_tfrscrr\000"
9884 /* 33780 */ "J2_ploop1sr\000"
9885 /* 33792 */ "J2_ploop2sr\000"
9886 /* 33804 */ "J2_ploop3sr\000"
9887 /* 33816 */ "LDriw_ctr\000"
9888 /* 33826 */ "STriw_ctr\000"
9889 /* 33836 */ "J4_jumpsetr\000"
9890 /* 33848 */ "V6_vrotr\000"
9891 /* 33857 */ "L4_loadbsw2_ur\000"
9892 /* 33872 */ "L4_loadbzw2_ur\000"
9893 /* 33887 */ "L4_loadbsw4_ur\000"
9894 /* 33902 */ "L4_loadbzw4_ur\000"
9895 /* 33917 */ "L4_loadalignb_ur\000"
9896 /* 33934 */ "L4_loadrb_ur\000"
9897 /* 33947 */ "S4_storerb_ur\000"
9898 /* 33961 */ "L4_loadrub_ur\000"
9899 /* 33975 */ "L4_loadrd_ur\000"
9900 /* 33988 */ "S4_storerd_ur\000"
9901 /* 34002 */ "S4_storerf_ur\000"
9902 /* 34016 */ "L4_loadalignh_ur\000"
9903 /* 34033 */ "L4_loadrh_ur\000"
9904 /* 34046 */ "S4_storerh_ur\000"
9905 /* 34060 */ "L4_loadruh_ur\000"
9906 /* 34074 */ "L4_loadri_ur\000"
9907 /* 34087 */ "S4_storeri_ur\000"
9908 /* 34101 */ "S4_storerbnew_ur\000"
9909 /* 34118 */ "S4_storerhnew_ur\000"
9910 /* 34135 */ "S4_storerinew_ur\000"
9911 /* 34152 */ "A2_vnavgwr\000"
9912 /* 34163 */ "A2_vavgwr\000"
9913 /* 34173 */ "V6_vinsertwr\000"
9914 /* 34186 */ "A2_vavguwr\000"
9915 /* 34197 */ "SA1_combinezr\000"
9916 /* 34211 */ "A2_abs\000"
9917 /* 34218 */ "L4_ploadrbf_abs\000"
9918 /* 34234 */ "S4_pstorerbf_abs\000"
9919 /* 34251 */ "L4_ploadrubf_abs\000"
9920 /* 34268 */ "L4_ploadrdf_abs\000"
9921 /* 34284 */ "S4_pstorerdf_abs\000"
9922 /* 34301 */ "S4_pstorerff_abs\000"
9923 /* 34318 */ "L4_ploadrhf_abs\000"
9924 /* 34334 */ "S4_pstorerhf_abs\000"
9925 /* 34351 */ "L4_ploadruhf_abs\000"
9926 /* 34368 */ "L4_ploadrif_abs\000"
9927 /* 34384 */ "S4_pstorerif_abs\000"
9928 /* 34401 */ "S4_pstorerbnewf_abs\000"
9929 /* 34421 */ "S4_pstorerhnewf_abs\000"
9930 /* 34441 */ "S4_pstorerinewf_abs\000"
9931 /* 34461 */ "L4_ploadrbt_abs\000"
9932 /* 34477 */ "S4_pstorerbt_abs\000"
9933 /* 34494 */ "L4_ploadrubt_abs\000"
9934 /* 34511 */ "L4_ploadrdt_abs\000"
9935 /* 34527 */ "S4_pstorerdt_abs\000"
9936 /* 34544 */ "S4_pstorerft_abs\000"
9937 /* 34561 */ "L4_ploadrht_abs\000"
9938 /* 34577 */ "S4_pstorerht_abs\000"
9939 /* 34594 */ "L4_ploadruht_abs\000"
9940 /* 34611 */ "L4_ploadrit_abs\000"
9941 /* 34627 */ "S4_pstorerit_abs\000"
9942 /* 34644 */ "S4_pstorerbnewt_abs\000"
9943 /* 34664 */ "S4_pstorerhnewt_abs\000"
9944 /* 34684 */ "S4_pstorerinewt_abs\000"
9945 /* 34704 */ "L4_ploadrbfnew_abs\000"
9946 /* 34723 */ "S4_pstorerbfnew_abs\000"
9947 /* 34743 */ "L4_ploadrubfnew_abs\000"
9948 /* 34763 */ "L4_ploadrdfnew_abs\000"
9949 /* 34782 */ "S4_pstorerdfnew_abs\000"
9950 /* 34802 */ "S4_pstorerffnew_abs\000"
9951 /* 34822 */ "L4_ploadrhfnew_abs\000"
9952 /* 34841 */ "S4_pstorerhfnew_abs\000"
9953 /* 34861 */ "L4_ploadruhfnew_abs\000"
9954 /* 34881 */ "L4_ploadrifnew_abs\000"
9955 /* 34900 */ "S4_pstorerifnew_abs\000"
9956 /* 34920 */ "S4_pstorerbnewfnew_abs\000"
9957 /* 34943 */ "S4_pstorerhnewfnew_abs\000"
9958 /* 34966 */ "S4_pstorerinewfnew_abs\000"
9959 /* 34989 */ "L4_ploadrbtnew_abs\000"
9960 /* 35008 */ "S4_pstorerbtnew_abs\000"
9961 /* 35028 */ "L4_ploadrubtnew_abs\000"
9962 /* 35048 */ "L4_ploadrdtnew_abs\000"
9963 /* 35067 */ "S4_pstorerdtnew_abs\000"
9964 /* 35087 */ "S4_pstorerftnew_abs\000"
9965 /* 35107 */ "L4_ploadrhtnew_abs\000"
9966 /* 35126 */ "S4_pstorerhtnew_abs\000"
9967 /* 35146 */ "L4_ploadruhtnew_abs\000"
9968 /* 35166 */ "L4_ploadritnew_abs\000"
9969 /* 35185 */ "S4_pstoreritnew_abs\000"
9970 /* 35205 */ "S4_pstorerbnewtnew_abs\000"
9971 /* 35228 */ "S4_pstorerhnewtnew_abs\000"
9972 /* 35251 */ "S4_pstorerinewtnew_abs\000"
9973 /* 35274 */ "PS_loadrbabs\000"
9974 /* 35287 */ "PS_storerbabs\000"
9975 /* 35301 */ "PS_loadrubabs\000"
9976 /* 35315 */ "PS_loadrdabs\000"
9977 /* 35328 */ "PS_storerdabs\000"
9978 /* 35342 */ "PS_storerfabs\000"
9979 /* 35356 */ "PS_loadrhabs\000"
9980 /* 35369 */ "PS_storerhabs\000"
9981 /* 35383 */ "PS_loadruhabs\000"
9982 /* 35397 */ "PS_loadriabs\000"
9983 /* 35410 */ "PS_storeriabs\000"
9984 /* 35424 */ "PS_storerbnewabs\000"
9985 /* 35441 */ "PS_storerhnewabs\000"
9986 /* 35458 */ "PS_storerinewabs\000"
9987 /* 35475 */ "A2_vsububs\000"
9988 /* 35486 */ "A2_vaddubs\000"
9989 /* 35497 */ "A5_vaddhubs\000"
9990 /* 35509 */ "M2_vmac2es\000"
9991 /* 35520 */ "A2_vsubhs\000"
9992 /* 35530 */ "A2_svsubhs\000"
9993 /* 35541 */ "A2_vaddhs\000"
9994 /* 35551 */ "A2_svaddhs\000"
9995 /* 35562 */ "A2_svavghs\000"
9996 /* 35573 */ "A2_vsubuhs\000"
9997 /* 35584 */ "A2_svsubuhs\000"
9998 /* 35596 */ "A2_vadduhs\000"
9999 /* 35607 */ "A2_svadduhs\000"
10000 /* 35619 */ "S2_vrndpackwhs\000"
10001 /* 35634 */ "F2_sffms\000"
10002 /* 35643 */ "V6_vmpyhsrs\000"
10003 /* 35655 */ "V6_vmpyhvsrs\000"
10004 /* 35668 */ "F2_dfclass\000"
10005 /* 35679 */ "F2_sfclass\000"
10006 /* 35690 */ "V6_vmpyhss\000"
10007 /* 35701 */ "V6_vmpabus\000"
10008 /* 35712 */ "V6_vdmpybus\000"
10009 /* 35724 */ "V6_vrmpybus\000"
10010 /* 35736 */ "V6_vtmpybus\000"
10011 /* 35748 */ "V6_vmpybus\000"
10012 /* 35759 */ "V6_vmpyhus\000"
10013 /* 35770 */ "V6_vmpyuhvs\000"
10014 /* 35782 */ "A2_vsubws\000"
10015 /* 35792 */ "A2_vaddws\000"
10016 /* 35802 */ "L4_loadw_phys\000"
10017 /* 35816 */ "SL2_jumpr31_t\000"
10018 /* 35830 */ "SL2_return_t\000"
10019 /* 35843 */ "L4_return_t\000"
10020 /* 35855 */ "J4_tstbit0_fp0_jump_t\000"
10021 /* 35877 */ "J4_cmpeqn1_fp0_jump_t\000"
10022 /* 35899 */ "J4_cmpgtn1_fp0_jump_t\000"
10023 /* 35921 */ "J4_cmpeqi_fp0_jump_t\000"
10024 /* 35942 */ "J4_cmpgti_fp0_jump_t\000"
10025 /* 35963 */ "J4_cmpgtui_fp0_jump_t\000"
10026 /* 35985 */ "J4_cmpeq_fp0_jump_t\000"
10027 /* 36005 */ "J4_cmpgt_fp0_jump_t\000"
10028 /* 36025 */ "J4_cmpgtu_fp0_jump_t\000"
10029 /* 36046 */ "J4_tstbit0_tp0_jump_t\000"
10030 /* 36068 */ "J4_cmpeqn1_tp0_jump_t\000"
10031 /* 36090 */ "J4_cmpgtn1_tp0_jump_t\000"
10032 /* 36112 */ "J4_cmpeqi_tp0_jump_t\000"
10033 /* 36133 */ "J4_cmpgti_tp0_jump_t\000"
10034 /* 36154 */ "J4_cmpgtui_tp0_jump_t\000"
10035 /* 36176 */ "J4_cmpeq_tp0_jump_t\000"
10036 /* 36196 */ "J4_cmpgt_tp0_jump_t\000"
10037 /* 36216 */ "J4_cmpgtu_tp0_jump_t\000"
10038 /* 36237 */ "J4_tstbit0_fp1_jump_t\000"
10039 /* 36259 */ "J4_cmpeqn1_fp1_jump_t\000"
10040 /* 36281 */ "J4_cmpgtn1_fp1_jump_t\000"
10041 /* 36303 */ "J4_cmpeqi_fp1_jump_t\000"
10042 /* 36324 */ "J4_cmpgti_fp1_jump_t\000"
10043 /* 36345 */ "J4_cmpgtui_fp1_jump_t\000"
10044 /* 36367 */ "J4_cmpeq_fp1_jump_t\000"
10045 /* 36387 */ "J4_cmpgt_fp1_jump_t\000"
10046 /* 36407 */ "J4_cmpgtu_fp1_jump_t\000"
10047 /* 36428 */ "J4_tstbit0_tp1_jump_t\000"
10048 /* 36450 */ "J4_cmpeqn1_tp1_jump_t\000"
10049 /* 36472 */ "J4_cmpgtn1_tp1_jump_t\000"
10050 /* 36494 */ "J4_cmpeqi_tp1_jump_t\000"
10051 /* 36515 */ "J4_cmpgti_tp1_jump_t\000"
10052 /* 36536 */ "J4_cmpgtui_tp1_jump_t\000"
10053 /* 36558 */ "J4_cmpeq_tp1_jump_t\000"
10054 /* 36578 */ "J4_cmpgt_tp1_jump_t\000"
10055 /* 36598 */ "J4_cmpgtu_tp1_jump_t\000"
10056 /* 36619 */ "J4_tstbit0_f_jumpnv_t\000"
10057 /* 36641 */ "J4_cmpeqn1_f_jumpnv_t\000"
10058 /* 36663 */ "J4_cmpgtn1_f_jumpnv_t\000"
10059 /* 36685 */ "J4_cmpeqi_f_jumpnv_t\000"
10060 /* 36706 */ "J4_cmpgti_f_jumpnv_t\000"
10061 /* 36727 */ "J4_cmpgtui_f_jumpnv_t\000"
10062 /* 36749 */ "J4_cmpeq_f_jumpnv_t\000"
10063 /* 36769 */ "J4_cmpgt_f_jumpnv_t\000"
10064 /* 36789 */ "J4_cmplt_f_jumpnv_t\000"
10065 /* 36809 */ "J4_cmpgtu_f_jumpnv_t\000"
10066 /* 36830 */ "J4_cmpltu_f_jumpnv_t\000"
10067 /* 36851 */ "J4_tstbit0_t_jumpnv_t\000"
10068 /* 36873 */ "J4_cmpeqn1_t_jumpnv_t\000"
10069 /* 36895 */ "J4_cmpgtn1_t_jumpnv_t\000"
10070 /* 36917 */ "J4_cmpeqi_t_jumpnv_t\000"
10071 /* 36938 */ "J4_cmpgti_t_jumpnv_t\000"
10072 /* 36959 */ "J4_cmpgtui_t_jumpnv_t\000"
10073 /* 36981 */ "J4_cmpeq_t_jumpnv_t\000"
10074 /* 37001 */ "J4_cmpgt_t_jumpnv_t\000"
10075 /* 37021 */ "J4_cmplt_t_jumpnv_t\000"
10076 /* 37041 */ "J4_cmpgtu_t_jumpnv_t\000"
10077 /* 37062 */ "J4_cmpltu_t_jumpnv_t\000"
10078 /* 37083 */ "L4_return_map_to_raw_t\000"
10079 /* 37106 */ "M4_mac_up_s1_sat\000"
10080 /* 37123 */ "M4_nac_up_s1_sat\000"
10081 /* 37140 */ "M2_mpy_up_s1_sat\000"
10082 /* 37157 */ "A2_sat\000"
10083 /* 37164 */ "V6_vwhist256_sat\000"
10084 /* 37181 */ "V6_vsubububb_sat\000"
10085 /* 37198 */ "V6_vaddububb_sat\000"
10086 /* 37215 */ "V6_vpackhb_sat\000"
10087 /* 37230 */ "V6_vabsb_sat\000"
10088 /* 37243 */ "V6_vpackhub_sat\000"
10089 /* 37259 */ "S5_asrhub_sat\000"
10090 /* 37273 */ "S5_asrhub_rnd_sat\000"
10091 /* 37291 */ "V6_vabsh_sat\000"
10092 /* 37304 */ "V6_vpackwuh_sat\000"
10093 /* 37320 */ "V6_vpackwh_sat\000"
10094 /* 37335 */ "A4_round_ri_sat\000"
10095 /* 37351 */ "V6_vwhist256q_sat\000"
10096 /* 37369 */ "S2_asl_i_r_sat\000"
10097 /* 37384 */ "S2_asl_r_r_sat\000"
10098 /* 37399 */ "S2_asr_r_r_sat\000"
10099 /* 37414 */ "A4_round_rr_sat\000"
10100 /* 37430 */ "V6_vabsw_sat\000"
10101 /* 37443 */ "V6_vsubbsat\000"
10102 /* 37455 */ "V6_vaddbsat\000"
10103 /* 37467 */ "V6_vasrhbsat\000"
10104 /* 37480 */ "V6_vsububsat\000"
10105 /* 37493 */ "V6_vaddubsat\000"
10106 /* 37506 */ "V6_vasrhubsat\000"
10107 /* 37520 */ "V6_vasruhubsat\000"
10108 /* 37535 */ "V6_vasrvuhubsat\000"
10109 /* 37551 */ "dep_A2_subsat\000"
10110 /* 37565 */ "dep_A2_addsat\000"
10111 /* 37579 */ "V6_vasrhbrndsat\000"
10112 /* 37595 */ "V6_vasrhubrndsat\000"
10113 /* 37612 */ "V6_vasruhubrndsat\000"
10114 /* 37630 */ "V6_vasrvuhubrndsat\000"
10115 /* 37649 */ "V6_vasrwuhrndsat\000"
10116 /* 37666 */ "V6_vasruwuhrndsat\000"
10117 /* 37684 */ "V6_vasrvwuhrndsat\000"
10118 /* 37702 */ "V6_vasrwhrndsat\000"
10119 /* 37718 */ "A2_roundsat\000"
10120 /* 37730 */ "A2_negsat\000"
10121 /* 37740 */ "V6_vsubhsat\000"
10122 /* 37752 */ "V6_vaddhsat\000"
10123 /* 37764 */ "V6_vmpahhsat\000"
10124 /* 37777 */ "A2_vabshsat\000"
10125 /* 37789 */ "V6_vsubuhsat\000"
10126 /* 37802 */ "V6_vadduhsat\000"
10127 /* 37815 */ "V6_vmpauhuhsat\000"
10128 /* 37830 */ "V6_vmpsuhuhsat\000"
10129 /* 37845 */ "V6_vasrwuhsat\000"
10130 /* 37859 */ "V6_vasruwuhsat\000"
10131 /* 37874 */ "V6_vasrvwuhsat\000"
10132 /* 37889 */ "V6_vasrwhsat\000"
10133 /* 37902 */ "V6_vdmpyhsat\000"
10134 /* 37915 */ "V6_vdmpyhisat\000"
10135 /* 37929 */ "V6_vdmpyhsuisat\000"
10136 /* 37945 */ "A2_addpsat\000"
10137 /* 37956 */ "A2_abssat\000"
10138 /* 37966 */ "V6_vdmpyhsusat\000"
10139 /* 37981 */ "V6_vdmpyhvsat\000"
10140 /* 37995 */ "V6_vsubwsat\000"
10141 /* 38007 */ "V6_vaddwsat\000"
10142 /* 38019 */ "A2_vabswsat\000"
10143 /* 38031 */ "V6_vsubuwsat\000"
10144 /* 38044 */ "V6_vadduwsat\000"
10145 /* 38057 */ "V6_vaddcarrysat\000"
10146 /* 38073 */ "A4_psxtbt\000"
10147 /* 38083 */ "A4_pzxtbt\000"
10148 /* 38093 */ "A2_psubt\000"
10149 /* 38102 */ "S4_extract\000"
10150 /* 38113 */ "V6_zextract\000"
10151 /* 38125 */ "PS_pselect\000"
10152 /* 38136 */ "PS_vselect\000"
10153 /* 38147 */ "PS_wselect\000"
10154 /* 38158 */ "A2_paddt\000"
10155 /* 38167 */ "A2_pandt\000"
10156 /* 38176 */ "PS_jmpret\000"
10157 /* 38186 */ "C2_bitsset\000"
10158 /* 38197 */ "C4_nbitsset\000"
10159 /* 38209 */ "A4_cmpbgt\000"
10160 /* 38219 */ "A4_vcmpbgt\000"
10161 /* 38230 */ "A4_cmphgt\000"
10162 /* 38240 */ "A2_vcmphgt\000"
10163 /* 38251 */ "C2_cmpgt\000"
10164 /* 38260 */ "F2_dfcmpgt\000"
10165 /* 38271 */ "F2_sfcmpgt\000"
10166 /* 38282 */ "A2_vcmpwgt\000"
10167 /* 38293 */ "Y2_syncht\000"
10168 /* 38303 */ "A4_paslht\000"
10169 /* 38313 */ "A4_pasrht\000"
10170 /* 38323 */ "A4_psxtht\000"
10171 /* 38333 */ "A4_pzxtht\000"
10172 /* 38343 */ "Y2_wait\000"
10173 /* 38351 */ "Y6_dmwait\000"
10174 /* 38361 */ "A2_paddit\000"
10175 /* 38371 */ "dup_C2_cmoveit\000"
10176 /* 38386 */ "A4_bitsplit\000"
10177 /* 38398 */ "dup_C2_cmovenewit\000"
10178 /* 38416 */ "V6_v6mpyhubs10_alt\000"
10179 /* 38435 */ "V6_v6mpyvubs10_alt\000"
10180 /* 38454 */ "V6_vsubb_alt\000"
10181 /* 38467 */ "V6_vaddb_alt\000"
10182 /* 38480 */ "V6_vshuffeb_alt\000"
10183 /* 38496 */ "V6_vpackeb_alt\000"
10184 /* 38511 */ "V6_vshufoeb_alt\000"
10185 /* 38527 */ "V6_vshuffb_alt\000"
10186 /* 38542 */ "V6_vnavgb_alt\000"
10187 /* 38556 */ "V6_vavgb_alt\000"
10188 /* 38569 */ "V6_vmpahb_alt\000"
10189 /* 38583 */ "V6_vroundhb_alt\000"
10190 /* 38599 */ "V6_vmpyihb_alt\000"
10191 /* 38614 */ "V6_vmpauhb_alt\000"
10192 /* 38629 */ "V6_vdmpyhb_alt\000"
10193 /* 38644 */ "V6_vtmpyhb_alt\000"
10194 /* 38659 */ "V6_vunpackb_alt\000"
10195 /* 38675 */ "V6_vdealb_alt\000"
10196 /* 38689 */ "V6_vminb_alt\000"
10197 /* 38702 */ "V6_vshuffob_alt\000"
10198 /* 38718 */ "V6_vunpackob_alt\000"
10199 /* 38735 */ "V6_vpackob_alt\000"
10200 /* 38750 */ "V6_vabsb_alt\000"
10201 /* 38763 */ "V6_vsb_alt\000"
10202 /* 38774 */ "V6_vabsdiffub_alt\000"
10203 /* 38792 */ "V6_vnavgub_alt\000"
10204 /* 38807 */ "V6_vavgub_alt\000"
10205 /* 38821 */ "V6_vroundhub_alt\000"
10206 /* 38838 */ "V6_vsathub_alt\000"
10207 /* 38853 */ "V6_vrounduhub_alt\000"
10208 /* 38871 */ "V6_vunpackub_alt\000"
10209 /* 38888 */ "V6_vminub_alt\000"
10210 /* 38902 */ "V6_vabsub_alt\000"
10211 /* 38916 */ "V6_vmpyiwub_alt\000"
10212 /* 38932 */ "V6_vmaxub_alt\000"
10213 /* 38946 */ "V6_vrmpyub_alt\000"
10214 /* 38961 */ "V6_vmpyub_alt\000"
10215 /* 38975 */ "V6_vmpyiwb_alt\000"
10216 /* 38990 */ "V6_vmaxb_alt\000"
10217 /* 39003 */ "V6_vtmpyb_alt\000"
10218 /* 39017 */ "V6_vzb_alt\000"
10219 /* 39028 */ "V6_vmpahb_acc_alt\000"
10220 /* 39046 */ "V6_vmpyihb_acc_alt\000"
10221 /* 39065 */ "V6_vmpauhb_acc_alt\000"
10222 /* 39084 */ "V6_vdmpyhb_acc_alt\000"
10223 /* 39103 */ "V6_vtmpyhb_acc_alt\000"
10224 /* 39122 */ "V6_vmpyiwub_acc_alt\000"
10225 /* 39142 */ "V6_vrmpyub_acc_alt\000"
10226 /* 39161 */ "V6_vmpyub_acc_alt\000"
10227 /* 39179 */ "V6_vmpyiwb_acc_alt\000"
10228 /* 39198 */ "V6_vtmpyb_acc_alt\000"
10229 /* 39216 */ "V6_vaddubh_acc_alt\000"
10230 /* 39235 */ "V6_vmpyih_acc_alt\000"
10231 /* 39253 */ "V6_vaslh_acc_alt\000"
10232 /* 39270 */ "V6_vasrh_acc_alt\000"
10233 /* 39287 */ "V6_vdsaduh_acc_alt\000"
10234 /* 39306 */ "V6_vmpyiewuh_acc_alt\000"
10235 /* 39327 */ "V6_vmpyuh_acc_alt\000"
10236 /* 39345 */ "V6_vmpyiewh_acc_alt\000"
10237 /* 39365 */ "V6_vmpyiwh_acc_alt\000"
10238 /* 39384 */ "V6_vmpyh_acc_alt\000"
10239 /* 39401 */ "V6_vrsadubi_acc_alt\000"
10240 /* 39421 */ "V6_vrmpyubi_acc_alt\000"
10241 /* 39441 */ "V6_vrmpybusi_acc_alt\000"
10242 /* 39462 */ "V6_vmpabus_acc_alt\000"
10243 /* 39481 */ "V6_vdmpybus_acc_alt\000"
10244 /* 39501 */ "V6_vrmpybus_acc_alt\000"
10245 /* 39521 */ "V6_vtmpybus_acc_alt\000"
10246 /* 39541 */ "V6_vmpybus_acc_alt\000"
10247 /* 39560 */ "V6_vmpyhus_acc_alt\000"
10248 /* 39579 */ "V6_vdmpyhsat_acc_alt\000"
10249 /* 39600 */ "V6_vmpyhsat_acc_alt\000"
10250 /* 39620 */ "V6_vdmpyhisat_acc_alt\000"
10251 /* 39642 */ "V6_vdmpyhsuisat_acc_alt\000"
10252 /* 39666 */ "V6_vdmpyhsusat_acc_alt\000"
10253 /* 39689 */ "V6_vdmpyhvsat_acc_alt\000"
10254 /* 39711 */ "V6_vandqrt_acc_alt\000"
10255 /* 39730 */ "V6_vandnqrt_acc_alt\000"
10256 /* 39750 */ "V6_vandvrt_acc_alt\000"
10257 /* 39769 */ "V6_vrmpybub_rtt_acc_alt\000"
10258 /* 39793 */ "V6_vrmpyub_rtt_acc_alt\000"
10259 /* 39816 */ "V6_vmpabuu_acc_alt\000"
10260 /* 39835 */ "V6_vrmpyubv_acc_alt\000"
10261 /* 39855 */ "V6_vmpyubv_acc_alt\000"
10262 /* 39874 */ "V6_vrmpybv_acc_alt\000"
10263 /* 39893 */ "V6_vmpybv_acc_alt\000"
10264 /* 39911 */ "V6_vdmpyhb_dv_acc_alt\000"
10265 /* 39933 */ "V6_vdmpybus_dv_acc_alt\000"
10266 /* 39956 */ "V6_vmpyuhv_acc_alt\000"
10267 /* 39975 */ "V6_vmpyhv_acc_alt\000"
10268 /* 39993 */ "V6_vrmpybusv_acc_alt\000"
10269 /* 40014 */ "V6_vmpybusv_acc_alt\000"
10270 /* 40034 */ "V6_vaddhw_acc_alt\000"
10271 /* 40052 */ "V6_vadduhw_acc_alt\000"
10272 /* 40071 */ "V6_vaslw_acc_alt\000"
10273 /* 40088 */ "V6_vasrw_acc_alt\000"
10274 /* 40105 */ "V6_vmpyowh_rnd_sacc_alt\000"
10275 /* 40129 */ "V6_vmpyowh_sacc_alt\000"
10276 /* 40149 */ "V6_vscattermh_add_alt\000"
10277 /* 40171 */ "V6_vscattermwh_add_alt\000"
10278 /* 40194 */ "V6_vscattermw_add_alt\000"
10279 /* 40216 */ "V6_vmpyowh_rnd_alt\000"
10280 /* 40235 */ "V6_vavgbrnd_alt\000"
10281 /* 40251 */ "V6_vavgubrnd_alt\000"
10282 /* 40268 */ "V6_vavghrnd_alt\000"
10283 /* 40284 */ "V6_vavguhrnd_alt\000"
10284 /* 40301 */ "V6_vavgwrnd_alt\000"
10285 /* 40317 */ "V6_vavguwrnd_alt\000"
10286 /* 40334 */ "V6_vcl0h_alt\000"
10287 /* 40347 */ "V6_vsububh_alt\000"
10288 /* 40362 */ "V6_vaddubh_alt\000"
10289 /* 40377 */ "V6_vsubh_alt\000"
10290 /* 40390 */ "V6_vaddh_alt\000"
10291 /* 40403 */ "V6_vshufeh_alt\000"
10292 /* 40418 */ "V6_vpackeh_alt\000"
10293 /* 40433 */ "V6_vshufoeh_alt\000"
10294 /* 40449 */ "V6_vabsdiffh_alt\000"
10295 /* 40466 */ "V6_vshuffh_alt\000"
10296 /* 40481 */ "V6_vnavgh_alt\000"
10297 /* 40495 */ "V6_vavgh_alt\000"
10298 /* 40508 */ "V6_vmpyih_alt\000"
10299 /* 40522 */ "V6_vunpackh_alt\000"
10300 /* 40538 */ "V6_vdealh_alt\000"
10301 /* 40552 */ "V6_vaslh_alt\000"
10302 /* 40565 */ "V6_vscattermh_alt\000"
10303 /* 40583 */ "V6_vminh_alt\000"
10304 /* 40596 */ "V6_vshufoh_alt\000"
10305 /* 40611 */ "V6_vunpackoh_alt\000"
10306 /* 40628 */ "V6_vpackoh_alt\000"
10307 /* 40643 */ "V6_vasrh_alt\000"
10308 /* 40656 */ "V6_vlsrh_alt\000"
10309 /* 40669 */ "V6_vabsh_alt\000"
10310 /* 40682 */ "V6_vsh_alt\000"
10311 /* 40693 */ "V6_vnormamth_alt\000"
10312 /* 40710 */ "V6_vpopcounth_alt\000"
10313 /* 40728 */ "V6_vdsaduh_alt\000"
10314 /* 40743 */ "V6_vabsdiffuh_alt\000"
10315 /* 40761 */ "V6_vavguh_alt\000"
10316 /* 40775 */ "V6_vunpackuh_alt\000"
10317 /* 40792 */ "V6_vminuh_alt\000"
10318 /* 40806 */ "V6_vabsuh_alt\000"
10319 /* 40820 */ "V6_vroundwuh_alt\000"
10320 /* 40837 */ "V6_vmpyiewuh_alt\000"
10321 /* 40854 */ "V6_vmpyewuh_alt\000"
10322 /* 40870 */ "V6_vrounduwuh_alt\000"
10323 /* 40888 */ "V6_vsatuwuh_alt\000"
10324 /* 40904 */ "V6_vmaxuh_alt\000"
10325 /* 40918 */ "V6_vmpyuh_alt\000"
10326 /* 40932 */ "V6_vroundwh_alt\000"
10327 /* 40948 */ "V6_vmpyiwh_alt\000"
10328 /* 40963 */ "V6_vscattermwh_alt\000"
10329 /* 40982 */ "V6_vmpyiowh_alt\000"
10330 /* 40998 */ "V6_vmpyowh_alt\000"
10331 /* 41013 */ "V6_vsatwh_alt\000"
10332 /* 41027 */ "V6_vmaxh_alt\000"
10333 /* 41040 */ "V6_vmpyh_alt\000"
10334 /* 41053 */ "V6_vzh_alt\000"
10335 /* 41064 */ "V6_vrsadubi_alt\000"
10336 /* 41080 */ "V6_vrmpyubi_alt\000"
10337 /* 41096 */ "V6_vrmpybusi_alt\000"
10338 /* 41113 */ "V6_vasr_into_alt\000"
10339 /* 41130 */ "V6_vsubbq_alt\000"
10340 /* 41144 */ "V6_vaddbq_alt\000"
10341 /* 41158 */ "V6_vsubhq_alt\000"
10342 /* 41172 */ "V6_vaddhq_alt\000"
10343 /* 41186 */ "V6_vscattermhq_alt\000"
10344 /* 41205 */ "V6_vscattermwhq_alt\000"
10345 /* 41225 */ "V6_vsubbnq_alt\000"
10346 /* 41240 */ "V6_vaddbnq_alt\000"
10347 /* 41255 */ "V6_vsubhnq_alt\000"
10348 /* 41270 */ "V6_vaddhnq_alt\000"
10349 /* 41285 */ "V6_vsubwnq_alt\000"
10350 /* 41300 */ "V6_vaddwnq_alt\000"
10351 /* 41315 */ "V6_vsubwq_alt\000"
10352 /* 41329 */ "V6_vaddwq_alt\000"
10353 /* 41343 */ "V6_vscattermwq_alt\000"
10354 /* 41362 */ "V6_vrotr_alt\000"
10355 /* 41375 */ "V6_vmpyhsrs_alt\000"
10356 /* 41391 */ "V6_vmpyhvsrs_alt\000"
10357 /* 41408 */ "V6_vmpyhss_alt\000"
10358 /* 41423 */ "V6_vmpabus_alt\000"
10359 /* 41438 */ "V6_vdmpybus_alt\000"
10360 /* 41454 */ "V6_vrmpybus_alt\000"
10361 /* 41470 */ "V6_vtmpybus_alt\000"
10362 /* 41486 */ "V6_vmpybus_alt\000"
10363 /* 41501 */ "V6_vmpyhus_alt\000"
10364 /* 41516 */ "V6_vpackhb_sat_alt\000"
10365 /* 41535 */ "V6_vabsb_sat_alt\000"
10366 /* 41552 */ "V6_vpackhub_sat_alt\000"
10367 /* 41572 */ "V6_vabsh_sat_alt\000"
10368 /* 41589 */ "V6_vpackwuh_sat_alt\000"
10369 /* 41609 */ "V6_vpackwh_sat_alt\000"
10370 /* 41628 */ "V6_vabsw_sat_alt\000"
10371 /* 41645 */ "V6_vsubbsat_alt\000"
10372 /* 41661 */ "V6_vaddbsat_alt\000"
10373 /* 41677 */ "V6_vsububsat_alt\000"
10374 /* 41694 */ "V6_vaddubsat_alt\000"
10375 /* 41711 */ "V6_vsubhsat_alt\000"
10376 /* 41727 */ "V6_vaddhsat_alt\000"
10377 /* 41743 */ "V6_vsubuhsat_alt\000"
10378 /* 41760 */ "V6_vadduhsat_alt\000"
10379 /* 41777 */ "V6_vdmpyhsat_alt\000"
10380 /* 41794 */ "V6_vdmpyhisat_alt\000"
10381 /* 41812 */ "V6_vdmpyhsuisat_alt\000"
10382 /* 41832 */ "V6_vdmpyhsusat_alt\000"
10383 /* 41851 */ "V6_vdmpyhvsat_alt\000"
10384 /* 41869 */ "V6_vsubwsat_alt\000"
10385 /* 41885 */ "V6_vaddwsat_alt\000"
10386 /* 41901 */ "V6_vsubuwsat_alt\000"
10387 /* 41918 */ "V6_vadduwsat_alt\000"
10388 /* 41935 */ "V6_vandqrt_alt\000"
10389 /* 41950 */ "V6_vandnqrt_alt\000"
10390 /* 41966 */ "V6_vandvrt_alt\000"
10391 /* 41981 */ "V6_vrmpybub_rtt_alt\000"
10392 /* 42001 */ "V6_vrmpyub_rtt_alt\000"
10393 /* 42020 */ "V6_vmpabuu_alt\000"
10394 /* 42035 */ "V6_vrmpyubv_alt\000"
10395 /* 42051 */ "V6_vmpyubv_alt\000"
10396 /* 42066 */ "V6_vrmpybv_alt\000"
10397 /* 42081 */ "V6_vmpybv_alt\000"
10398 /* 42095 */ "V6_vsubb_dv_alt\000"
10399 /* 42111 */ "V6_vaddb_dv_alt\000"
10400 /* 42127 */ "V6_vdmpyhb_dv_alt\000"
10401 /* 42145 */ "V6_vsubh_dv_alt\000"
10402 /* 42161 */ "V6_vaddh_dv_alt\000"
10403 /* 42177 */ "V6_vdmpybus_dv_alt\000"
10404 /* 42196 */ "V6_vsubbsat_dv_alt\000"
10405 /* 42215 */ "V6_vaddbsat_dv_alt\000"
10406 /* 42234 */ "V6_vsububsat_dv_alt\000"
10407 /* 42254 */ "V6_vaddubsat_dv_alt\000"
10408 /* 42274 */ "V6_vsubhsat_dv_alt\000"
10409 /* 42293 */ "V6_vaddhsat_dv_alt\000"
10410 /* 42312 */ "V6_vsubuhsat_dv_alt\000"
10411 /* 42332 */ "V6_vadduhsat_dv_alt\000"
10412 /* 42352 */ "V6_vsubwsat_dv_alt\000"
10413 /* 42371 */ "V6_vaddwsat_dv_alt\000"
10414 /* 42390 */ "V6_vsubuwsat_dv_alt\000"
10415 /* 42410 */ "V6_vadduwsat_dv_alt\000"
10416 /* 42430 */ "V6_vsubw_dv_alt\000"
10417 /* 42446 */ "V6_vaddw_dv_alt\000"
10418 /* 42462 */ "V6_vaslhv_alt\000"
10419 /* 42476 */ "V6_vasrhv_alt\000"
10420 /* 42490 */ "V6_vlsrhv_alt\000"
10421 /* 42504 */ "V6_vmpyuhv_alt\000"
10422 /* 42519 */ "V6_vmpyhv_alt\000"
10423 /* 42533 */ "V6_vmpabusv_alt\000"
10424 /* 42549 */ "V6_vrmpybusv_alt\000"
10425 /* 42566 */ "V6_vmpybusv_alt\000"
10426 /* 42582 */ "V6_vmpabuuv_alt\000"
10427 /* 42598 */ "V6_vaslwv_alt\000"
10428 /* 42612 */ "V6_vasrwv_alt\000"
10429 /* 42626 */ "V6_vlsrwv_alt\000"
10430 /* 42640 */ "V6_vcl0w_alt\000"
10431 /* 42653 */ "V6_vdealb4w_alt\000"
10432 /* 42669 */ "V6_vsubw_alt\000"
10433 /* 42682 */ "V6_vaddw_alt\000"
10434 /* 42695 */ "V6_vabsdiffw_alt\000"
10435 /* 42712 */ "V6_vnavgw_alt\000"
10436 /* 42726 */ "V6_vavgw_alt\000"
10437 /* 42739 */ "V6_vsubhw_alt\000"
10438 /* 42753 */ "V6_vaddhw_alt\000"
10439 /* 42767 */ "V6_vsubuhw_alt\000"
10440 /* 42782 */ "V6_vadduhw_alt\000"
10441 /* 42797 */ "V6_vaslw_alt\000"
10442 /* 42810 */ "V6_vscattermw_alt\000"
10443 /* 42828 */ "V6_vminw_alt\000"
10444 /* 42841 */ "V6_vasrw_alt\000"
10445 /* 42854 */ "V6_vlsrw_alt\000"
10446 /* 42867 */ "V6_vabsw_alt\000"
10447 /* 42880 */ "V6_extractw_alt\000"
10448 /* 42896 */ "V6_vnormamtw_alt\000"
10449 /* 42913 */ "V6_vavguw_alt\000"
10450 /* 42927 */ "V6_vabsuw_alt\000"
10451 /* 42941 */ "V6_vmaxw_alt\000"
10452 /* 42954 */ "J2_callt\000"
10453 /* 42963 */ "C2_cmplt\000"
10454 /* 42972 */ "J4_tstbit0_fp0_jump_nt\000"
10455 /* 42995 */ "J4_cmpeqn1_fp0_jump_nt\000"
10456 /* 43018 */ "J4_cmpgtn1_fp0_jump_nt\000"
10457 /* 43041 */ "J4_cmpeqi_fp0_jump_nt\000"
10458 /* 43063 */ "J4_cmpgti_fp0_jump_nt\000"
10459 /* 43085 */ "J4_cmpgtui_fp0_jump_nt\000"
10460 /* 43108 */ "J4_cmpeq_fp0_jump_nt\000"
10461 /* 43129 */ "J4_cmpgt_fp0_jump_nt\000"
10462 /* 43150 */ "J4_cmpgtu_fp0_jump_nt\000"
10463 /* 43172 */ "J4_tstbit0_tp0_jump_nt\000"
10464 /* 43195 */ "J4_cmpeqn1_tp0_jump_nt\000"
10465 /* 43218 */ "J4_cmpgtn1_tp0_jump_nt\000"
10466 /* 43241 */ "J4_cmpeqi_tp0_jump_nt\000"
10467 /* 43263 */ "J4_cmpgti_tp0_jump_nt\000"
10468 /* 43285 */ "J4_cmpgtui_tp0_jump_nt\000"
10469 /* 43308 */ "J4_cmpeq_tp0_jump_nt\000"
10470 /* 43329 */ "J4_cmpgt_tp0_jump_nt\000"
10471 /* 43350 */ "J4_cmpgtu_tp0_jump_nt\000"
10472 /* 43372 */ "J4_tstbit0_fp1_jump_nt\000"
10473 /* 43395 */ "J4_cmpeqn1_fp1_jump_nt\000"
10474 /* 43418 */ "J4_cmpgtn1_fp1_jump_nt\000"
10475 /* 43441 */ "J4_cmpeqi_fp1_jump_nt\000"
10476 /* 43463 */ "J4_cmpgti_fp1_jump_nt\000"
10477 /* 43485 */ "J4_cmpgtui_fp1_jump_nt\000"
10478 /* 43508 */ "J4_cmpeq_fp1_jump_nt\000"
10479 /* 43529 */ "J4_cmpgt_fp1_jump_nt\000"
10480 /* 43550 */ "J4_cmpgtu_fp1_jump_nt\000"
10481 /* 43572 */ "J4_tstbit0_tp1_jump_nt\000"
10482 /* 43595 */ "J4_cmpeqn1_tp1_jump_nt\000"
10483 /* 43618 */ "J4_cmpgtn1_tp1_jump_nt\000"
10484 /* 43641 */ "J4_cmpeqi_tp1_jump_nt\000"
10485 /* 43663 */ "J4_cmpgti_tp1_jump_nt\000"
10486 /* 43685 */ "J4_cmpgtui_tp1_jump_nt\000"
10487 /* 43708 */ "J4_cmpeq_tp1_jump_nt\000"
10488 /* 43729 */ "J4_cmpgt_tp1_jump_nt\000"
10489 /* 43750 */ "J4_cmpgtu_tp1_jump_nt\000"
10490 /* 43772 */ "J4_tstbit0_f_jumpnv_nt\000"
10491 /* 43795 */ "J4_cmpeqn1_f_jumpnv_nt\000"
10492 /* 43818 */ "J4_cmpgtn1_f_jumpnv_nt\000"
10493 /* 43841 */ "J4_cmpeqi_f_jumpnv_nt\000"
10494 /* 43863 */ "J4_cmpgti_f_jumpnv_nt\000"
10495 /* 43885 */ "J4_cmpgtui_f_jumpnv_nt\000"
10496 /* 43908 */ "J4_cmpeq_f_jumpnv_nt\000"
10497 /* 43929 */ "J4_cmpgt_f_jumpnv_nt\000"
10498 /* 43950 */ "J4_cmplt_f_jumpnv_nt\000"
10499 /* 43971 */ "J4_cmpgtu_f_jumpnv_nt\000"
10500 /* 43993 */ "J4_cmpltu_f_jumpnv_nt\000"
10501 /* 44015 */ "J4_tstbit0_t_jumpnv_nt\000"
10502 /* 44038 */ "J4_cmpeqn1_t_jumpnv_nt\000"
10503 /* 44061 */ "J4_cmpgtn1_t_jumpnv_nt\000"
10504 /* 44084 */ "J4_cmpeqi_t_jumpnv_nt\000"
10505 /* 44106 */ "J4_cmpgti_t_jumpnv_nt\000"
10506 /* 44128 */ "J4_cmpgtui_t_jumpnv_nt\000"
10507 /* 44151 */ "J4_cmpeq_t_jumpnv_nt\000"
10508 /* 44172 */ "J4_cmpgt_t_jumpnv_nt\000"
10509 /* 44193 */ "J4_cmplt_t_jumpnv_nt\000"
10510 /* 44214 */ "J4_cmpgtu_t_jumpnv_nt\000"
10511 /* 44236 */ "J4_cmpltu_t_jumpnv_nt\000"
10512 /* 44258 */ "L4_return_fnew_pnt\000"
10513 /* 44277 */ "L4_return_map_to_raw_fnew_pnt\000"
10514 /* 44307 */ "L4_return_tnew_pnt\000"
10515 /* 44326 */ "L4_return_map_to_raw_tnew_pnt\000"
10516 /* 44356 */ "A2_not\000"
10517 /* 44363 */ "C2_not\000"
10518 /* 44370 */ "C4_fastcorner9_not\000"
10519 /* 44389 */ "V6_pred_not\000"
10520 /* 44401 */ "V6_vnot\000"
10521 /* 44409 */ "L4_return_fnew_pt\000"
10522 /* 44427 */ "L4_return_map_to_raw_fnew_pt\000"
10523 /* 44456 */ "L4_return_tnew_pt\000"
10524 /* 44474 */ "L4_return_map_to_raw_tnew_pt\000"
10525 /* 44503 */ "J2_jumpfpt\000"
10526 /* 44514 */ "J2_jumprfpt\000"
10527 /* 44526 */ "J2_jumpt\000"
10528 /* 44535 */ "A2_tfrpt\000"
10529 /* 44544 */ "J2_jumptpt\000"
10530 /* 44555 */ "J2_jumprtpt\000"
10531 /* 44567 */ "J2_jumpfnewpt\000"
10532 /* 44581 */ "J2_jumprfnewpt\000"
10533 /* 44596 */ "PS_jmpretfnewpt\000"
10534 /* 44612 */ "J2_jumptnewpt\000"
10535 /* 44626 */ "J2_jumprtnewpt\000"
10536 /* 44641 */ "PS_jmprettnewpt\000"
10537 /* 44657 */ "J2_jumprgtezpt\000"
10538 /* 44672 */ "J2_jumprltezpt\000"
10539 /* 44687 */ "J2_jumprnzpt\000"
10540 /* 44700 */ "J2_jumprzpt\000"
10541 /* 44712 */ "V6_vrmpyzbb_rt\000"
10542 /* 44727 */ "V6_vrmpyzcb_rt\000"
10543 /* 44742 */ "V6_vrmpyznb_rt\000"
10544 /* 44757 */ "V6_vrmpyzbub_rt\000"
10545 /* 44773 */ "V6_vrmpyzcbs_rt\000"
10546 /* 44789 */ "Y2_start\000"
10547 /* 44798 */ "Y6_dmstart\000"
10548 /* 44809 */ "S2_insert\000"
10549 /* 44819 */ "A2_tfrt\000"
10550 /* 44827 */ "SA1_clrt\000"
10551 /* 44836 */ "J2_callrt\000"
10552 /* 44846 */ "A2_port\000"
10553 /* 44854 */ "A2_pxort\000"
10554 /* 44863 */ "J2_jumprt\000"
10555 /* 44873 */ "V6_vandqrt\000"
10556 /* 44884 */ "V6_vandnqrt\000"
10557 /* 44896 */ "V6_vandvrt\000"
10558 /* 44907 */ "V6_vhist\000"
10559 /* 44916 */ "A2_iconst\000"
10560 /* 44926 */ "PS_jmprett\000"
10561 /* 44937 */ "V6_vrmpybub_rtt\000"
10562 /* 44953 */ "V6_vrmpyub_rtt\000"
10563 /* 44968 */ "C2_ccombinewt\000"
10564 /* 44982 */ "C2_ccombinewnewt\000"
10565 /* 44999 */ "TFRI64_V2_ext\000"
10566 /* 45013 */ "A4_ext\000"
10567 /* 45020 */ "V6_get_qfext\000"
10568 /* 45033 */ "V6_set_qfext\000"
10569 /* 45046 */ "J2_loop0iext\000"
10570 /* 45059 */ "J2_loop1iext\000"
10571 /* 45072 */ "J2_loop0rext\000"
10572 /* 45085 */ "J2_loop1rext\000"
10573 /* 45098 */ "C4_cmplteu\000"
10574 /* 45109 */ "A2_minu\000"
10575 /* 45117 */ "A4_modwrapu\000"
10576 /* 45129 */ "V6_vL32b_ppu\000"
10577 /* 45142 */ "V6_vS32b_ppu\000"
10578 /* 45155 */ "V6_vL32Ub_ppu\000"
10579 /* 45169 */ "V6_vS32Ub_ppu\000"
10580 /* 45183 */ "V6_zLd_ppu\000"
10581 /* 45194 */ "V6_vL32b_pred_ppu\000"
10582 /* 45212 */ "V6_vS32b_pred_ppu\000"
10583 /* 45230 */ "V6_vS32Ub_pred_ppu\000"
10584 /* 45249 */ "V6_zLd_pred_ppu\000"
10585 /* 45265 */ "V6_vL32b_tmp_pred_ppu\000"
10586 /* 45287 */ "V6_vL32b_nt_tmp_pred_ppu\000"
10587 /* 45312 */ "V6_vL32b_cur_pred_ppu\000"
10588 /* 45334 */ "V6_vL32b_nt_cur_pred_ppu\000"
10589 /* 45359 */ "V6_vL32b_nt_pred_ppu\000"
10590 /* 45380 */ "V6_vS32b_nt_pred_ppu\000"
10591 /* 45401 */ "V6_vS32b_new_pred_ppu\000"
10592 /* 45423 */ "V6_vS32b_nt_new_pred_ppu\000"
10593 /* 45448 */ "V6_vL32b_npred_ppu\000"
10594 /* 45467 */ "V6_vS32b_npred_ppu\000"
10595 /* 45486 */ "V6_vS32Ub_npred_ppu\000"
10596 /* 45506 */ "V6_vL32b_tmp_npred_ppu\000"
10597 /* 45529 */ "V6_vL32b_nt_tmp_npred_ppu\000"
10598 /* 45555 */ "V6_vL32b_cur_npred_ppu\000"
10599 /* 45578 */ "V6_vL32b_nt_cur_npred_ppu\000"
10600 /* 45604 */ "V6_vL32b_nt_npred_ppu\000"
10601 /* 45626 */ "V6_vS32b_nt_npred_ppu\000"
10602 /* 45648 */ "V6_vS32b_new_npred_ppu\000"
10603 /* 45671 */ "V6_vS32b_nt_new_npred_ppu\000"
10604 /* 45697 */ "V6_vS32b_qpred_ppu\000"
10605 /* 45716 */ "V6_vS32b_nt_qpred_ppu\000"
10606 /* 45738 */ "V6_vS32b_nqpred_ppu\000"
10607 /* 45758 */ "V6_vS32b_nt_nqpred_ppu\000"
10608 /* 45781 */ "V6_vL32b_tmp_ppu\000"
10609 /* 45798 */ "V6_vL32b_nt_tmp_ppu\000"
10610 /* 45818 */ "V6_vL32b_cur_ppu\000"
10611 /* 45835 */ "V6_vL32b_nt_cur_ppu\000"
10612 /* 45855 */ "V6_vS32b_srls_ppu\000"
10613 /* 45873 */ "V6_vL32b_nt_ppu\000"
10614 /* 45889 */ "V6_vS32b_nt_ppu\000"
10615 /* 45905 */ "V6_vS32b_new_ppu\000"
10616 /* 45922 */ "V6_vS32b_nt_new_ppu\000"
10617 /* 45942 */ "M5_vdmacbsu\000"
10618 /* 45954 */ "M5_vrmacbsu\000"
10619 /* 45966 */ "M5_vmacbsu\000"
10620 /* 45977 */ "M5_vdmpybsu\000"
10621 /* 45989 */ "M5_vrmpybsu\000"
10622 /* 46001 */ "M5_vmpybsu\000"
10623 /* 46012 */ "S2_extractu\000"
10624 /* 46024 */ "A4_cmpbgtu\000"
10625 /* 46035 */ "A2_vcmpbgtu\000"
10626 /* 46047 */ "A4_cmphgtu\000"
10627 /* 46058 */ "A2_vcmphgtu\000"
10628 /* 46070 */ "C2_cmpgtu\000"
10629 /* 46080 */ "A2_vcmpwgtu\000"
10630 /* 46092 */ "C2_cmpltu\000"
10631 /* 46102 */ "V6_vmpabuu\000"
10632 /* 46113 */ "M5_vrmacbuu\000"
10633 /* 46125 */ "M5_vmacbuu\000"
10634 /* 46136 */ "M5_vrmpybuu\000"
10635 /* 46148 */ "M5_vmpybuu\000"
10636 /* 46159 */ "A2_maxu\000"
10637 /* 46167 */ "V6_vrmpyubv\000"
10638 /* 46179 */ "V6_vmpyubv\000"
10639 /* 46190 */ "V6_vrmpybv\000"
10640 /* 46201 */ "V6_vmpybv\000"
10641 /* 46211 */ "V6_vsubb_dv\000"
10642 /* 46223 */ "V6_vaddb_dv\000"
10643 /* 46235 */ "V6_vdmpyhb_dv\000"
10644 /* 46249 */ "V6_vsubh_dv\000"
10645 /* 46261 */ "V6_vaddh_dv\000"
10646 /* 46273 */ "V6_vdmpybus_dv\000"
10647 /* 46288 */ "V6_vsubbsat_dv\000"
10648 /* 46303 */ "V6_vaddbsat_dv\000"
10649 /* 46318 */ "V6_vsububsat_dv\000"
10650 /* 46334 */ "V6_vaddubsat_dv\000"
10651 /* 46350 */ "V6_vsubhsat_dv\000"
10652 /* 46365 */ "V6_vaddhsat_dv\000"
10653 /* 46380 */ "V6_vsubuhsat_dv\000"
10654 /* 46396 */ "V6_vadduhsat_dv\000"
10655 /* 46412 */ "V6_vsubwsat_dv\000"
10656 /* 46427 */ "V6_vaddwsat_dv\000"
10657 /* 46442 */ "V6_vsubuwsat_dv\000"
10658 /* 46458 */ "V6_vadduwsat_dv\000"
10659 /* 46474 */ "V6_vsubw_dv\000"
10660 /* 46486 */ "V6_vaddw_dv\000"
10661 /* 46498 */ "S2_brev\000"
10662 /* 46506 */ "V6_vaslhv\000"
10663 /* 46516 */ "V6_vasrhv\000"
10664 /* 46526 */ "V6_vlsrhv\000"
10665 /* 46536 */ "V6_vmpyuhv\000"
10666 /* 46547 */ "V6_vmpyhv\000"
10667 /* 46557 */ "Y5_l2gcleaninv\000"
10668 /* 46572 */ "V6_vncmov\000"
10669 /* 46582 */ "V6_vcmov\000"
10670 /* 46591 */ "V6_vandvnqv\000"
10671 /* 46603 */ "V6_vandvqv\000"
10672 /* 46614 */ "V6_vmpabusv\000"
10673 /* 46626 */ "V6_vrmpybusv\000"
10674 /* 46639 */ "V6_vmpybusv\000"
10675 /* 46651 */ "V6_vmpabuuv\000"
10676 /* 46663 */ "V6_vaslwv\000"
10677 /* 46673 */ "V6_vasrwv\000"
10678 /* 46683 */ "V6_vlsrwv\000"
10679 /* 46693 */ "V6_vcl0w\000"
10680 /* 46702 */ "F2_conv_df2w\000"
10681 /* 46715 */ "F2_conv_sf2w\000"
10682 /* 46728 */ "V6_vdealb4w\000"
10683 /* 46740 */ "V6_vconv_sf_w\000"
10684 /* 46754 */ "S6_allocframe_to_raw\000"
10685 /* 46775 */ "L6_deallocframe_map_to_raw\000"
10686 /* 46802 */ "L6_return_map_to_raw\000"
10687 /* 46823 */ "Y2_icdataw\000"
10688 /* 46834 */ "V6_vaddclbw\000"
10689 /* 46846 */ "Y2_tlbw\000"
10690 /* 46854 */ "Y5_ctlbw\000"
10691 /* 46863 */ "S4_vxaddsubw\000"
10692 /* 46876 */ "A2_vsubw\000"
10693 /* 46885 */ "V6_vsubw\000"
10694 /* 46894 */ "S4_vxsubaddw\000"
10695 /* 46907 */ "A2_vaddw\000"
10696 /* 46916 */ "V6_vaddw\000"
10697 /* 46925 */ "V6_vsatdw\000"
10698 /* 46935 */ "SL2_jumpr31_fnew\000"
10699 /* 46952 */ "SL2_return_fnew\000"
10700 /* 46968 */ "A4_psxtbfnew\000"
10701 /* 46981 */ "A4_pzxtbfnew\000"
10702 /* 46994 */ "A2_psubfnew\000"
10703 /* 47006 */ "A2_paddfnew\000"
10704 /* 47018 */ "A2_pandfnew\000"
10705 /* 47030 */ "A4_paslhfnew\000"
10706 /* 47043 */ "A4_pasrhfnew\000"
10707 /* 47056 */ "A4_psxthfnew\000"
10708 /* 47069 */ "A4_pzxthfnew\000"
10709 /* 47082 */ "A2_paddifnew\000"
10710 /* 47095 */ "J2_jumpfnew\000"
10711 /* 47107 */ "A2_tfrpfnew\000"
10712 /* 47119 */ "A2_tfrfnew\000"
10713 /* 47130 */ "SA1_clrfnew\000"
10714 /* 47142 */ "A2_porfnew\000"
10715 /* 47153 */ "A2_pxorfnew\000"
10716 /* 47165 */ "J2_jumprfnew\000"
10717 /* 47178 */ "PS_jmpretfnew\000"
10718 /* 47192 */ "A2_combinew\000"
10719 /* 47204 */ "SL2_jumpr31_tnew\000"
10720 /* 47221 */ "SL2_return_tnew\000"
10721 /* 47237 */ "A4_psxtbtnew\000"
10722 /* 47250 */ "A4_pzxtbtnew\000"
10723 /* 47263 */ "A2_psubtnew\000"
10724 /* 47275 */ "A2_paddtnew\000"
10725 /* 47287 */ "A2_pandtnew\000"
10726 /* 47299 */ "A4_paslhtnew\000"
10727 /* 47312 */ "A4_pasrhtnew\000"
10728 /* 47325 */ "A4_psxthtnew\000"
10729 /* 47338 */ "A4_pzxthtnew\000"
10730 /* 47351 */ "A2_padditnew\000"
10731 /* 47364 */ "J2_jumptnew\000"
10732 /* 47376 */ "A2_tfrptnew\000"
10733 /* 47388 */ "A2_tfrtnew\000"
10734 /* 47399 */ "SA1_clrtnew\000"
10735 /* 47411 */ "A2_portnew\000"
10736 /* 47422 */ "A2_pxortnew\000"
10737 /* 47434 */ "J2_jumprtnew\000"
10738 /* 47447 */ "PS_jmprettnew\000"
10739 /* 47461 */ "M2_vabsdiffw\000"
10740 /* 47474 */ "V6_vabsdiffw\000"
10741 /* 47487 */ "Y4_l2tagw\000"
10742 /* 47497 */ "Y2_dctagw\000"
10743 /* 47507 */ "Y2_ictagw\000"
10744 /* 47517 */ "A2_vnavgw\000"
10745 /* 47527 */ "V6_vnavgw\000"
10746 /* 47537 */ "A2_vavgw\000"
10747 /* 47546 */ "V6_vavgw\000"
10748 /* 47555 */ "V6_vsubhw\000"
10749 /* 47565 */ "V6_vaddhw\000"
10750 /* 47575 */ "V6_vgathermhw\000"
10751 /* 47589 */ "V6_vscattermhw\000"
10752 /* 47604 */ "S2_vsxthw\000"
10753 /* 47614 */ "S2_vzxthw\000"
10754 /* 47624 */ "V6_vsubuhw\000"
10755 /* 47635 */ "V6_vadduhw\000"
10756 /* 47646 */ "PS_vsplatiw\000"
10757 /* 47658 */ "M7_dcmpyiw\000"
10758 /* 47669 */ "M7_wcmpyiw\000"
10759 /* 47680 */ "V6_vaslw\000"
10760 /* 47689 */ "PS_vmulw\000"
10761 /* 47698 */ "V6_vgathermw\000"
10762 /* 47711 */ "V6_vscattermw\000"
10763 /* 47725 */ "Y2_iassignw\000"
10764 /* 47737 */ "A4_vrminw\000"
10765 /* 47747 */ "A2_vminw\000"
10766 /* 47756 */ "V6_vminw\000"
10767 /* 47765 */ "V6_shuffeqw\000"
10768 /* 47777 */ "V6_veqw\000"
10769 /* 47785 */ "V6_vprefixqw\000"
10770 /* 47798 */ "V6_vasrw\000"
10771 /* 47807 */ "V6_vlsrw\000"
10772 /* 47816 */ "PS_vsplatrw\000"
10773 /* 47828 */ "M7_dcmpyrw\000"
10774 /* 47839 */ "M7_wcmpyrw\000"
10775 /* 47850 */ "A2_vabsw\000"
10776 /* 47859 */ "V6_vabsw\000"
10777 /* 47868 */ "V6_lvsplatw\000"
10778 /* 47880 */ "V6_extractw\000"
10779 /* 47892 */ "V6_vgtw\000"
10780 /* 47900 */ "V6_vnormamtw\000"
10781 /* 47913 */ "A2_sxtw\000"
10782 /* 47921 */ "F2_conv_df2uw\000"
10783 /* 47935 */ "F2_conv_sf2uw\000"
10784 /* 47949 */ "A2_vavguw\000"
10785 /* 47959 */ "V6_vavguw\000"
10786 /* 47969 */ "A4_vrminuw\000"
10787 /* 47980 */ "A2_vminuw\000"
10788 /* 47990 */ "V6_MAP_equw\000"
10789 /* 48002 */ "V6_vgtuw\000"
10790 /* 48011 */ "A4_vrmaxuw\000"
10791 /* 48022 */ "A2_vmaxuw\000"
10792 /* 48032 */ "S2_asl_i_vw\000"
10793 /* 48044 */ "S2_asr_i_vw\000"
10794 /* 48056 */ "S2_lsr_i_vw\000"
10795 /* 48068 */ "S2_asl_r_vw\000"
10796 /* 48080 */ "S2_lsl_r_vw\000"
10797 /* 48092 */ "S2_asr_r_vw\000"
10798 /* 48104 */ "S2_lsr_r_vw\000"
10799 /* 48116 */ "A4_vrmaxw\000"
10800 /* 48126 */ "A2_vmaxw\000"
10801 /* 48135 */ "V6_vmaxw\000"
10802 /* 48144 */ "S2_tableidxw\000"
10803 /* 48157 */ "M4_pmpyw\000"
10804 /* 48166 */ "A2_max\000"
10805 /* 48173 */ "F2_dfmax\000"
10806 /* 48182 */ "F2_sfmax\000"
10807 /* 48191 */ "S2_tableidxb_goodsyntax\000"
10808 /* 48215 */ "S2_asr_i_p_rnd_goodsyntax\000"
10809 /* 48241 */ "S2_asr_i_r_rnd_goodsyntax\000"
10810 /* 48267 */ "S5_vasrhrnd_goodsyntax\000"
10811 /* 48290 */ "S2_tableidxd_goodsyntax\000"
10812 /* 48314 */ "S2_tableidxh_goodsyntax\000"
10813 /* 48338 */ "S5_asrhub_rnd_sat_goodsyntax\000"
10814 /* 48367 */ "S2_tableidxw_goodsyntax\000"
10815 /* 48391 */ "Y5_l2cleanidx\000"
10816 /* 48405 */ "Y2_dccleanidx\000"
10817 /* 48419 */ "Y5_l2invidx\000"
10818 /* 48431 */ "Y2_dcinvidx\000"
10819 /* 48443 */ "Y2_icinvidx\000"
10820 /* 48455 */ "Y2_l2cleaninvidx\000"
10821 /* 48472 */ "Y2_dccleaninvidx\000"
10822 /* 48489 */ "S4_or_andix\000"
10823 /* 48501 */ "F2_dfmpyfix\000"
10824 /* 48513 */ "V6_vsub_qf32_mix\000"
10825 /* 48530 */ "V6_vadd_qf32_mix\000"
10826 /* 48547 */ "V6_vsub_qf16_mix\000"
10827 /* 48564 */ "V6_vadd_qf16_mix\000"
10828 /* 48581 */ "V6_vrmpyzbb_rx\000"
10829 /* 48596 */ "V6_vrmpyzcb_rx\000"
10830 /* 48611 */ "V6_vrmpyznb_rx\000"
10831 /* 48626 */ "V6_vrmpyzbub_rx\000"
10832 /* 48642 */ "V6_vrmpyzcbs_rx\000"
10833 /* 48658 */ "SA1_addrx\000"
10834 /* 48668 */ "C2_mux\000"
10835 /* 48675 */ "C2_vmux\000"
10836 /* 48683 */ "V6_vmux\000"
10837 /* 48691 */ "V6_v6mpyhubs10_vxx\000"
10838 /* 48710 */ "V6_v6mpyvubs10_vxx\000"
10839 /* 48729 */ "V6_v10mpyubs10_vxx\000"
10840 /* 48748 */ "A4_vcmpbeq_any\000"
10841 /* 48763 */ "A6_vcmpbeq_notany\000"
10842 /* 48781 */ "L6_memcpy\000"
10843 /* 48791 */ "M7_vdmpy\000"
10844 /* 48800 */ "F2_sfmpy\000"
10845 /* 48809 */ "V6_vsubcarry\000"
10846 /* 48822 */ "V6_vaddcarry\000"
10847 /* 48835 */ "S4_parity\000"
10848 /* 48845 */ "J2_jumprgtez\000"
10849 /* 48858 */ "J2_jumprltez\000"
10850 /* 48871 */ "A2_swiz\000"
10851 /* 48879 */ "J2_jumprnz\000"
10852 /* 48890 */ "SA1_combinerz\000"
10853 /* 48904 */ "J2_jumprz\000"
10854};
10855#ifdef __GNUC__
10856#pragma GCC diagnostic pop
10857#endif
10858
10859extern const unsigned HexagonInstrNameIndices[] = {
10860 6775U, 7171U, 7926U, 7529U, 6860U, 6841U, 6869U, 7007U,
10861 6598U, 6613U, 6550U, 6537U, 6640U, 8444U, 6371U, 9116U,
10862 6563U, 6771U, 6850U, 6152U, 9596U, 6274U, 9020U, 5965U,
10863 6103U, 6140U, 7640U, 6995U, 8930U, 6072U, 7847U, 6703U,
10864 8919U, 6297U, 7820U, 7807U, 7987U, 8778U, 8801U, 6927U,
10865 6974U, 6947U, 6886U, 6362U, 7952U, 7594U, 9601U, 8105U,
10866 7778U, 6419U, 9146U, 9176U, 7372U, 5878U, 5291U, 7110U,
10867 9345U, 9352U, 7137U, 7144U, 7151U, 7161U, 5943U, 8290U,
10868 8253U, 8363U, 9317U, 6548U, 6773U, 9519U, 6381U, 6396U,
10869 7012U, 8746U, 8370U, 9057U, 8387U, 8176U, 5645U, 8427U,
10870 8941U, 8332U, 9089U, 6462U, 7963U, 6046U, 5619U, 6028U,
10871 8979U, 8960U, 7350U, 8012U, 8031U, 5779U, 5723U, 5753U,
10872 5764U, 5704U, 5734U, 6341U, 6325U, 8474U, 6654U, 6671U,
10873 5894U, 5297U, 5949U, 5910U, 8295U, 8259U, 9503U, 7498U,
10874 9486U, 7481U, 5845U, 5274U, 9421U, 7416U, 7266U, 7213U,
10875 7702U, 7680U, 5987U, 8699U, 6132U, 6720U, 5978U, 8765U,
10876 9035U, 5597U, 8522U, 8896U, 8549U, 9160U, 5637U, 8885U,
10877 8873U, 9010U, 6695U, 9139U, 6627U, 9169U, 6913U, 8098U,
10878 8084U, 6906U, 8091U, 8325U, 7028U, 7757U, 7750U, 7764U,
10879 7771U, 8756U, 7586U, 6173U, 7570U, 6124U, 7578U, 6165U,
10880 7562U, 6116U, 7624U, 7616U, 6739U, 6731U, 8617U, 8607U,
10881 8597U, 8587U, 8637U, 8627U, 9547U, 9557U, 8647U, 8660U,
10882 9567U, 9577U, 8673U, 8686U, 5803U, 5253U, 7052U, 5220U,
10883 5697U, 9324U, 7116U, 9397U, 6797U, 7891U, 4663U, 9U,
10884 6688U, 4646U, 0U, 7866U, 7898U, 6591U, 9131U, 5609U,
10885 6779U, 6788U, 7732U, 7741U, 8720U, 8733U, 8343U, 7387U,
10886 8461U, 6471U, 7315U, 7325U, 6222U, 6237U, 7202U, 7255U,
10887 7287U, 7301U, 9359U, 9385U, 9371U, 6181U, 6209U, 6194U,
10888 5884U, 6805U, 7450U, 9455U, 7474U, 9479U, 8350U, 6019U,
10889 6009U, 7921U, 8825U, 6252U, 8157U, 8137U, 8853U, 8832U,
10890 8191U, 8222U, 8208U, 8504U, 9630U, 6519U, 9623U, 6501U,
10891 7799U, 7724U, 6349U, 6919U, 8410U, 7522U, 8417U, 7343U,
10892 8402U, 7514U, 7335U, 4654U, 6763U, 6755U, 6747U, 9066U,
10893 8128U, 8952U, 8997U, 9099U, 7939U, 6261U, 5666U, 6440U,
10894 6310U, 5831U, 5260U, 7080U, 9331U, 7123U, 5226U, 9074U,
10895 7875U, 8051U, 8067U, 9587U, 6281U, 6452U, 8792U, 7632U,
10896 7673U, 7649U, 7661U, 5810U, 7059U, 5786U, 7035U, 9404U,
10897 7399U, 7234U, 7181U, 5862U, 7094U, 5927U, 8275U, 8237U,
10898 9438U, 7433U, 9462U, 7457U, 9533U, 9540U, 29394U, 44916U,
10899 15614U, 44356U, 15228U, 47119U, 29288U, 15206U, 47107U, 21315U,
10900 44535U, 47376U, 44819U, 47388U, 26067U, 26054U, 10415U, 22219U,
10901 7545U, 7832U, 19098U, 21847U, 42963U, 46092U, 26192U, 23238U,
10902 75U, 2534U, 2569U, 277U, 2544U, 2669U, 26080U, 26100U,
10903 26141U, 26121U, 26205U, 26295U, 26923U, 26223U, 26259U, 26241U,
10904 26277U, 26477U, 26545U, 27105U, 27173U, 26528U, 27156U, 26578U,
10905 27572U, 27224U, 27991U, 26653U, 27659U, 27299U, 28078U, 26709U,
10906 27724U, 27355U, 28143U, 26784U, 27811U, 27430U, 28230U, 26634U,
10907 27637U, 27280U, 28056U, 26765U, 27789U, 27411U, 28208U, 26356U,
10908 26984U, 28411U, 26397U, 27025U, 28452U, 26376U, 27004U, 28431U,
10909 26417U, 27045U, 28472U, 26457U, 27085U, 28512U, 26335U, 26963U,
10910 28390U, 26438U, 27066U, 28493U, 14474U, 44277U, 44427U, 37083U,
10911 44326U, 44474U, 26315U, 26943U, 28370U, 46775U, 46802U, 33816U,
10912 13288U, 19238U, 21944U, 2717U, 4349U, 29185U, 48791U, 12709U,
10913 9699U, 9637U, 22852U, 31326U, 16546U, 14296U, 19119U, 9647U,
10914 18601U, 30664U, 18689U, 30752U, 18795U, 30858U, 18883U, 30946U,
10915 18660U, 30723U, 18854U, 30917U, 38125U, 14305U, 14396U, 18630U,
10916 30693U, 18718U, 30781U, 18748U, 30811U, 18824U, 30887U, 18912U,
10917 30975U, 17313U, 30024U, 14388U, 92U, 18100U, 18281U, 18211U,
10918 18345U, 18246U, 47689U, 12558U, 38136U, 10129U, 16166U, 47646U,
10919 10325U, 16534U, 47816U, 18114U, 18295U, 18228U, 18359U, 18263U,
10920 38147U, 48215U, 48241U, 26596U, 26857U, 27486U, 27242U, 26671U,
10921 27317U, 26690U, 27336U, 26727U, 26879U, 27508U, 27373U, 26802U,
10922 26901U, 27530U, 27448U, 26493U, 27552U, 26561U, 26840U, 27121U,
10923 27951U, 27189U, 27971U, 48191U, 48290U, 48314U, 48367U, 27593U,
10924 27876U, 28295U, 28012U, 27680U, 28099U, 27702U, 28121U, 27745U,
10925 27901U, 28320U, 28164U, 27832U, 27926U, 28345U, 28251U, 26510U,
10926 26615U, 27615U, 27261U, 28034U, 27138U, 26746U, 27767U, 27392U,
10927 28186U, 27206U, 26821U, 27854U, 27467U, 28273U, 48338U, 48267U,
10928 46754U, 33826U, 13299U, 10647U, 13362U, 31794U, 31895U, 16791U,
10929 13488U, 31810U, 32010U, 47990U, 13812U, 31826U, 32133U, 107U,
10930 2507U, 42880U, 19125U, 100U, 229U, 2403U, 203U, 2382U,
10931 239U, 2415U, 2363U, 212U, 2393U, 248U, 2426U, 289U,
10932 2449U, 2518U, 25514U, 2500U, 175U, 2372U, 258U, 2438U,
10933 315U, 2470U, 2491U, 298U, 2460U, 324U, 2481U, 2526U,
10934 267U, 306U, 60U, 48729U, 38416U, 38435U, 38750U, 41535U,
10935 40449U, 38774U, 40743U, 42695U, 40669U, 41572U, 38902U, 40806U,
10936 42927U, 42867U, 41628U, 38467U, 42111U, 41240U, 41144U, 41661U,
10937 42215U, 40390U, 42161U, 41270U, 41172U, 41727U, 42293U, 40034U,
10938 42753U, 39216U, 40362U, 41694U, 42254U, 41760U, 42332U, 40052U,
10939 42782U, 41918U, 42410U, 42682U, 42446U, 41300U, 41329U, 41885U,
10940 42371U, 39730U, 41950U, 39711U, 41935U, 39750U, 41966U, 39253U,
10941 40552U, 42462U, 40071U, 42797U, 42598U, 41113U, 39270U, 40643U,
10942 42476U, 40088U, 42841U, 42612U, 28920U, 38556U, 40235U, 40495U,
10943 40268U, 38807U, 40251U, 40761U, 40284U, 42913U, 40317U, 42726U,
10944 40301U, 40334U, 42640U, 126U, 84U, 42653U, 38675U, 40538U,
10945 39481U, 41438U, 39933U, 42177U, 39084U, 38629U, 39911U, 42127U,
10946 39620U, 41794U, 39579U, 41777U, 39642U, 41812U, 39666U, 41832U,
10947 39689U, 41851U, 39287U, 40728U, 23252U, 23272U, 23336U, 23293U,
10948 23357U, 23315U, 40656U, 42490U, 42854U, 42626U, 38990U, 41027U,
10949 38932U, 40904U, 42941U, 38689U, 40583U, 38888U, 40792U, 42828U,
10950 39462U, 41423U, 42533U, 39816U, 42020U, 42582U, 39028U, 38569U,
10951 39065U, 38614U, 39541U, 41486U, 40014U, 42566U, 39893U, 42081U,
10952 40854U, 39384U, 41040U, 39600U, 41375U, 41408U, 39560U, 41501U,
10953 39975U, 42519U, 41391U, 39345U, 39306U, 40837U, 39235U, 40508U,
10954 39046U, 38599U, 40982U, 39179U, 38975U, 39365U, 40948U, 39122U,
10955 38916U, 40998U, 40216U, 40105U, 40129U, 39161U, 38961U, 39855U,
10956 42051U, 39327U, 40918U, 39956U, 42504U, 38542U, 40481U, 38792U,
10957 42712U, 40693U, 42896U, 38496U, 40418U, 41516U, 41552U, 38735U,
10958 40628U, 41609U, 41589U, 40710U, 39769U, 41981U, 39501U, 41454U,
10959 39441U, 41096U, 39993U, 42549U, 39874U, 42066U, 39142U, 38946U,
10960 39793U, 42001U, 39421U, 41080U, 39835U, 42035U, 41362U, 38583U,
10961 38821U, 38853U, 40870U, 40932U, 40820U, 39401U, 41064U, 38838U,
10962 40888U, 41013U, 38763U, 40149U, 40565U, 41186U, 40194U, 42810U,
10963 40171U, 40963U, 41205U, 41343U, 40682U, 40403U, 38527U, 38480U,
10964 40466U, 38702U, 38511U, 40433U, 40596U, 38454U, 42095U, 41225U,
10965 41130U, 41645U, 42196U, 40377U, 42145U, 41255U, 41158U, 41711U,
10966 42274U, 42739U, 40347U, 41677U, 42234U, 41743U, 42312U, 42767U,
10967 41901U, 42390U, 42669U, 42430U, 41285U, 41315U, 41869U, 42352U,
10968 39198U, 39003U, 39521U, 41470U, 39103U, 38644U, 26038U, 38659U,
10969 40522U, 38718U, 40611U, 38871U, 40775U, 39017U, 41053U, 118U,
10970 220U, 13310U, 15840U, 26162U, 26176U, 13113U, 18990U, 31247U,
10971 19180U, 10390U, 16644U, 31146U, 21719U, 10411U, 16665U, 19197U,
10972 31260U, 21607U, 15155U, 38371U, 15170U, 38398U, 21404U, 14215U,
10973 23620U, 23707U, 24216U, 24313U, 23689U, 24281U, 14180U, 23637U,
10974 23724U, 24233U, 24330U, 23655U, 24348U, 34211U, 29376U, 37956U,
10975 13117U, 16079U, 22433U, 16215U, 22606U, 16127U, 22511U, 16263U,
10976 22684U, 22463U, 22636U, 22549U, 22722U, 18994U, 28610U, 37945U,
10977 37569U, 16433U, 22800U, 13324U, 31251U, 28618U, 16292U, 16496U,
10978 16094U, 22478U, 16230U, 22651U, 19184U, 47192U, 48166U, 29549U,
10979 46159U, 29531U, 23076U, 28932U, 45109U, 29498U, 28703U, 37730U,
10980 29096U, 29446U, 31361U, 31277U, 29296U, 14667U, 47006U, 15145U,
10981 47082U, 38361U, 47351U, 38158U, 47275U, 14676U, 47018U, 38167U,
10982 47287U, 15255U, 47142U, 44846U, 47411U, 14590U, 46994U, 38093U,
10983 47263U, 15263U, 47153U, 44854U, 47422U, 37718U, 37157U, 10365U,
10984 16592U, 10684U, 16803U, 10659U, 16064U, 22418U, 16200U, 22591U,
10985 16108U, 22492U, 16244U, 22665U, 22448U, 22621U, 22530U, 22703U,
10986 28570U, 21598U, 37555U, 15892U, 35551U, 35607U, 16054U, 35562U,
10987 16025U, 15796U, 35530U, 35584U, 48871U, 10394U, 16648U, 47913U,
10988 31150U, 33759U, 16157U, 22582U, 31055U, 21723U, 16555U, 37777U,
10989 47850U, 38019U, 15874U, 35541U, 10484U, 35486U, 35596U, 46907U,
10990 35792U, 16036U, 30557U, 31226U, 10533U, 30534U, 16727U, 31236U,
10991 47949U, 34186U, 47537U, 31088U, 34163U, 29650U, 46035U, 29671U,
10992 38240U, 46058U, 29744U, 38282U, 46080U, 22086U, 10777U, 17180U,
10993 10714U, 16907U, 48022U, 48126U, 10193U, 16357U, 10627U, 16771U,
10994 47980U, 47747U, 16005U, 30545U, 31215U, 47517U, 31076U, 34152U,
10995 10473U, 11270U, 10462U, 11255U, 15778U, 35520U, 10452U, 35475U,
10996 35573U, 46876U, 35782U, 31857U, 29303U, 16669U, 10895U, 22984U,
10997 28911U, 38386U, 21834U, 19131U, 25520U, 29640U, 21324U, 38209U,
10998 21766U, 46024U, 21870U, 29661U, 21347U, 38230U, 21789U, 46047U,
10999 21895U, 19201U, 31264U, 21611U, 21467U, 32575U, 45013U, 45117U,
11000 23140U, 28940U, 15096U, 47030U, 38303U, 47299U, 15106U, 47043U,
11001 38313U, 47312U, 14570U, 46968U, 38073U, 47237U, 15125U, 47056U,
11002 38323U, 47325U, 14580U, 46981U, 38083U, 47250U, 15135U, 47069U,
11003 38333U, 47338U, 29734U, 21418U, 29692U, 21381U, 21455U, 37335U,
11004 32563U, 37414U, 10885U, 29122U, 28589U, 15806U, 48748U, 21335U,
11005 38219U, 21777U, 21882U, 21358U, 21800U, 21907U, 21429U, 21822U,
11006 21931U, 17170U, 16896U, 48011U, 48116U, 16347U, 16760U, 47969U,
11007 47737U, 8356U, 35497U, 48763U, 7907U, 28835U, 21441U, 32549U,
11008 28843U, 5161U, 13331U, 22976U, 5183U, 31294U, 21624U, 38186U,
11009 15575U, 15589U, 44982U, 44968U, 15159U, 38375U, 15174U, 38402U,
11010 29703U, 21408U, 29175U, 38251U, 21812U, 29423U, 46070U, 21920U,
11011 29520U, 22303U, 48668U, 19214U, 31285U, 21674U, 44363U, 31367U,
11012 23133U, 32487U, 29311U, 22208U, 48675U, 31864U, 13001U, 13403U,
11013 22992U, 31418U, 23147U, 14371U, 19108U, 45098U, 21858U, 29682U,
11014 21370U, 5191U, 44370U, 31305U, 21636U, 38197U, 13757U, 23016U,
11015 31732U, 23158U, 14153U, 4565U, 4759U, 2342U, 4544U, 4696U,
11016 4745U, 4877U, 4900U, 5017U, 5031U, 5169U, 5206U, 5239U,
11017 5313U, 5683U, 6089U, 6487U, 6577U, 8310U, 14599U, 15282U,
11018 13071U, 28948U, 15309U, 14055U, 28984U, 47921U, 29058U, 46702U,
11019 29022U, 13084U, 28966U, 14626U, 14069U, 29003U, 47935U, 29077U,
11020 46715U, 29040U, 14612U, 15295U, 14653U, 15336U, 14640U, 15323U,
11021 13179U, 35668U, 29712U, 14120U, 38260U, 25551U, 22929U, 25677U,
11022 48173U, 23083U, 48501U, 16146U, 16309U, 22789U, 10666U, 13188U,
11023 35679U, 29723U, 14131U, 38271U, 25562U, 14043U, 23121U, 32496U,
11024 9678U, 10091U, 13011U, 35634U, 10104U, 22940U, 25688U, 9784U,
11025 48182U, 23092U, 48800U, 9720U, 10675U, 29111U, 33748U, 28578U,
11026 31044U, 6776U, 22741U, 15188U, 31317U, 15245U, 16476U, 44836U,
11027 42954U, 28903U, 15197U, 47095U, 44567U, 44503U, 32465U, 15272U,
11028 47165U, 44581U, 44514U, 48845U, 44657U, 16486U, 48858U, 44672U,
11029 48879U, 44687U, 44863U, 47434U, 44626U, 44555U, 48904U, 44700U,
11030 44526U, 47364U, 44612U, 44544U, 17251U, 45046U, 29960U, 45072U,
11031 17275U, 45059U, 29970U, 45085U, 14315U, 21683U, 33780U, 21695U,
11032 33792U, 21707U, 33804U, 14381U, 183U, 2640U, 14335U, 43908U,
11033 36749U, 43108U, 35985U, 43508U, 36367U, 44151U, 36981U, 43308U,
11034 36176U, 43708U, 36558U, 43841U, 36685U, 43041U, 35921U, 43441U,
11035 36303U, 44084U, 36917U, 43241U, 36112U, 43641U, 36494U, 43795U,
11036 36641U, 42995U, 35877U, 43395U, 36259U, 44038U, 36873U, 43195U,
11037 36068U, 43595U, 36450U, 43929U, 36769U, 43129U, 36005U, 43529U,
11038 36387U, 44172U, 37001U, 43329U, 36196U, 43729U, 36578U, 43863U,
11039 36706U, 43063U, 35942U, 43463U, 36324U, 44106U, 36938U, 43263U,
11040 36133U, 43663U, 36515U, 43818U, 36663U, 43018U, 35899U, 43418U,
11041 36281U, 44061U, 36895U, 43218U, 36090U, 43618U, 36472U, 43971U,
11042 36809U, 43150U, 36025U, 43550U, 36407U, 44214U, 37041U, 43350U,
11043 36216U, 43750U, 36598U, 43885U, 36727U, 43085U, 35963U, 43485U,
11044 36345U, 44128U, 36959U, 43285U, 36154U, 43685U, 36536U, 43950U,
11045 36789U, 44193U, 37021U, 43993U, 36830U, 44236U, 37062U, 32474U,
11046 21754U, 33836U, 43772U, 36619U, 42972U, 35855U, 43372U, 36237U,
11047 44015U, 36851U, 43172U, 36046U, 43572U, 36428U, 14199U, 23451U,
11048 30283U, 18569U, 30632U, 19358U, 32230U, 24047U, 30389U, 18763U,
11049 30826U, 20256U, 32329U, 23377U, 30219U, 18505U, 30568U, 19248U,
11050 32170U, 23407U, 30251U, 18537U, 30600U, 19278U, 32200U, 23392U,
11051 30235U, 18521U, 30584U, 19263U, 32185U, 23422U, 30267U, 18553U,
11052 30616U, 19293U, 32215U, 23607U, 30301U, 18587U, 30650U, 19375U,
11053 32247U, 28640U, 23711U, 30345U, 18675U, 30738U, 19986U, 32288U,
11054 28678U, 24203U, 30407U, 18781U, 30844U, 20273U, 32346U, 28724U,
11055 24317U, 30451U, 18869U, 30932U, 20314U, 32387U, 28762U, 23693U,
11056 30330U, 18645U, 30708U, 19402U, 32274U, 28665U, 24267U, 30436U,
11057 18839U, 30902U, 20300U, 32373U, 28749U, 29608U, 13255U, 23742U,
11058 20013U, 24661U, 20739U, 24367U, 20428U, 25023U, 21044U, 23805U,
11059 20060U, 24736U, 20795U, 24430U, 20475U, 25098U, 21100U, 23852U,
11060 20107U, 24792U, 20851U, 24477U, 20522U, 25154U, 21156U, 23915U,
11061 20154U, 24867U, 20907U, 24540U, 20569U, 25229U, 21212U, 23789U,
11062 20044U, 24717U, 20776U, 24414U, 20459U, 25079U, 21081U, 23899U,
11063 20138U, 24848U, 20888U, 24524U, 20553U, 25210U, 21193U, 23503U,
11064 24099U, 25400U, 23538U, 24134U, 25435U, 23520U, 24116U, 25417U,
11065 23555U, 24151U, 25452U, 23589U, 24185U, 25486U, 23485U, 24081U,
11066 25382U, 25803U, 33917U, 25902U, 34016U, 25743U, 33857U, 25773U,
11067 33887U, 25758U, 33872U, 25788U, 33902U, 29596U, 13222U, 25820U,
11068 32508U, 33934U, 25861U, 32588U, 33975U, 25919U, 32858U, 34033U,
11069 25960U, 32899U, 34074U, 25847U, 32535U, 33961U, 25946U, 32885U,
11070 34060U, 35802U, 23573U, 24169U, 25470U, 34218U, 32615U, 34704U,
11071 33172U, 34461U, 32926U, 34989U, 33477U, 34268U, 32662U, 34763U,
11072 33228U, 34511U, 32973U, 35048U, 33533U, 34318U, 32709U, 34822U,
11073 33284U, 34561U, 33020U, 35107U, 33589U, 34368U, 32756U, 34881U,
11074 33340U, 34611U, 33067U, 35166U, 33645U, 34251U, 32646U, 34743U,
11075 33209U, 34494U, 32957U, 35028U, 33514U, 34351U, 32740U, 34861U,
11076 33321U, 34594U, 33051U, 35146U, 33626U, 23179U, 14462U, 44258U,
11077 44409U, 35843U, 44307U, 44456U, 23468U, 24064U, 25365U, 48781U,
11078 7621U, 18452U, 19161U, 1206U, 1913U, 1991U, 4191U, 452U,
11079 2735U, 1232U, 1939U, 2110U, 4310U, 478U, 2761U, 2151U,
11080 4337U, 492U, 2775U, 2016U, 4216U, 465U, 2748U, 416U,
11081 344U, 505U, 2137U, 434U, 362U, 2204U, 4431U, 3471U,
11082 4472U, 4139U, 18435U, 23101U, 28852U, 2284U, 4486U, 2056U,
11083 4256U, 2313U, 4515U, 2083U, 4283U, 2298U, 4500U, 2069U,
11084 4269U, 2327U, 4529U, 2096U, 4296U, 2244U, 4418U, 1194U,
11085 3459U, 2271U, 4459U, 1901U, 4127U, 2230U, 4404U, 1181U,
11086 3446U, 2257U, 4445U, 1888U, 4114U, 18443U, 664U, 2929U,
11087 1385U, 3611U, 979U, 3244U, 1700U, 3926U, 787U, 3052U,
11088 1508U, 3734U, 1102U, 3367U, 1823U, 4049U, 839U, 3104U,
11089 1560U, 3786U, 1154U, 3419U, 1875U, 4101U, 592U, 2857U,
11090 1313U, 3539U, 907U, 3172U, 1628U, 3854U, 766U, 3031U,
11091 1487U, 3713U, 1081U, 3346U, 1802U, 4028U, 720U, 2985U,
11092 1441U, 3667U, 1035U, 3300U, 1756U, 3982U, 808U, 3073U,
11093 1529U, 3755U, 1123U, 3388U, 1844U, 4070U, 699U, 2964U,
11094 1420U, 3646U, 1014U, 3279U, 1735U, 3961U, 29488U, 4152U,
11095 37140U, 628U, 2893U, 1349U, 3575U, 943U, 3208U, 1664U,
11096 3890U, 752U, 3017U, 1473U, 3699U, 1067U, 3332U, 1788U,
11097 4014U, 556U, 2821U, 1277U, 3503U, 871U, 3136U, 1592U,
11098 3818U, 681U, 2946U, 1402U, 3628U, 996U, 3261U, 1717U,
11099 3943U, 22078U, 23111U, 28862U, 29465U, 646U, 2911U, 1367U,
11100 3593U, 961U, 3226U, 1682U, 3908U, 825U, 3090U, 1546U,
11101 3772U, 1140U, 3405U, 1861U, 4087U, 574U, 2839U, 1295U,
11102 3521U, 889U, 3154U, 1610U, 3836U, 29477U, 609U, 2874U,
11103 1330U, 3556U, 924U, 3189U, 1645U, 3871U, 737U, 3002U,
11104 1458U, 3684U, 1052U, 3317U, 1773U, 3999U, 537U, 2802U,
11105 1258U, 3484U, 852U, 3117U, 1573U, 3799U, 18460U, 19170U,
11106 12722U, 15947U, 47461U, 17327U, 30082U, 17345U, 30100U, 17363U,
11107 30118U, 2003U, 4203U, 2123U, 4323U, 2163U, 4363U, 4671U,
11108 35509U, 2028U, 4228U, 1965U, 4165U, 2176U, 4376U, 2042U,
11109 4242U, 1978U, 22104U, 4178U, 22121U, 2190U, 4390U, 15864U,
11110 16702U, 1218U, 10825U, 1925U, 10855U, 1244U, 10840U, 1951U,
11111 10870U, 15630U, 22355U, 15650U, 22375U, 15693U, 22391U, 332U,
11112 2218U, 12917U, 13414U, 23004U, 31428U, 31936U, 17021U, 12949U,
11113 17033U, 12962U, 37106U, 19002U, 31099U, 4710U, 19016U, 31113U,
11114 37123U, 13767U, 23027U, 31741U, 32099U, 48157U, 12599U, 17211U,
11115 11628U, 380U, 2681U, 523U, 2788U, 398U, 2699U, 1167U,
11116 3432U, 13777U, 23038U, 31750U, 12929U, 45942U, 45977U, 45966U,
11117 46125U, 46001U, 46148U, 45954U, 46113U, 45989U, 46136U, 9924U,
11118 10494U, 47658U, 12530U, 13023U, 11359U, 47828U, 12584U, 13047U,
11119 11375U, 47669U, 13926U, 13035U, 13849U, 47839U, 13941U, 13059U,
11120 13865U, 22343U, 31337U, 38176U, 15564U, 47178U, 44596U, 44926U,
11121 47447U, 44641U, 35274U, 35315U, 35356U, 35397U, 35301U, 35383U,
11122 35287U, 35424U, 35328U, 35342U, 35369U, 35441U, 35410U, 35458U,
11123 2649U, 21953U, 22008U, 4792U, 9190U, 5454U, 5327U, 4850U,
11124 9256U, 5528U, 5393U, 21659U, 14166U, 25644U, 11719U, 13532U,
11125 10920U, 31522U, 12837U, 29991U, 11839U, 13652U, 11040U, 31634U,
11126 37369U, 12885U, 16937U, 48032U, 25699U, 11764U, 13577U, 10965U,
11127 31564U, 32039U, 30038U, 11884U, 13697U, 11085U, 31676U, 37384U,
11128 16973U, 48068U, 25655U, 11734U, 13547U, 10935U, 31536U, 13896U,
11129 30002U, 11854U, 13667U, 11055U, 31648U, 13911U, 23189U, 16949U,
11130 48044U, 25721U, 11794U, 13607U, 10995U, 31592U, 32069U, 30060U,
11131 11914U, 13727U, 11115U, 31704U, 37399U, 23207U, 16997U, 48092U,
11132 46498U, 29540U, 23061U, 168U, 25601U, 2622U, 25617U, 10163U,
11133 22892U, 28541U, 17396U, 30151U, 2356U, 25609U, 4558U, 25625U,
11134 14419U, 46012U, 29273U, 29507U, 29230U, 44809U, 29260U, 29454U,
11135 29216U, 14405U, 29403U, 25710U, 11779U, 13592U, 10980U, 31578U,
11136 32054U, 30049U, 11899U, 13712U, 11100U, 31690U, 16985U, 48080U,
11137 25666U, 11749U, 13562U, 10950U, 31550U, 12853U, 30013U, 11869U,
11138 13682U, 11070U, 31662U, 12901U, 16961U, 48056U, 25732U, 11809U,
11139 13622U, 11010U, 31606U, 32084U, 30071U, 11929U, 13742U, 11130U,
11140 31718U, 17009U, 48104U, 22311U, 22572U, 29557U, 23757U, 20028U,
11141 20757U, 23976U, 20199U, 20944U, 24587U, 20630U, 21249U, 24382U,
11142 20443U, 21062U, 23820U, 20075U, 20813U, 24445U, 20490U, 21118U,
11143 23836U, 20091U, 20832U, 24461U, 20506U, 21137U, 23867U, 20122U,
11144 20869U, 23995U, 20218U, 20966U, 24606U, 20649U, 21271U, 24492U,
11145 20537U, 21174U, 23930U, 20169U, 20925U, 24014U, 20237U, 20988U,
11146 24625U, 20668U, 21293U, 24555U, 20584U, 21230U, 17408U, 30163U,
11147 9878U, 15902U, 10211U, 16387U, 23641U, 30315U, 18615U, 30678U,
11148 19388U, 32260U, 28652U, 24644U, 30480U, 18927U, 30990U, 20722U,
11149 32414U, 28787U, 23728U, 30359U, 18703U, 30766U, 19999U, 32301U,
11150 28690U, 23962U, 30374U, 18733U, 30796U, 20185U, 32315U, 28711U,
11151 24237U, 30421U, 18809U, 30872U, 20286U, 32359U, 28736U, 24989U,
11152 30498U, 18945U, 31008U, 21010U, 32431U, 28803U, 24334U, 30465U,
11153 18897U, 30960U, 20327U, 32400U, 28774U, 25006U, 30516U, 18963U,
11154 31026U, 21027U, 32448U, 28819U, 13271U, 21989U, 22044U, 10034U,
11155 10588U, 10795U, 14083U, 17198U, 48144U, 17381U, 30136U, 17420U,
11156 30175U, 10117U, 10292U, 15995U, 14359U, 15984U, 17080U, 35619U,
11157 10024U, 22138U, 10566U, 22155U, 17139U, 22191U, 16859U, 22173U,
11158 10313U, 16522U, 10078U, 10279U, 15723U, 47604U, 9989U, 17057U,
11159 10012U, 17106U, 15733U, 47614U, 19052U, 21495U, 21554U, 21510U,
11160 21569U, 19030U, 19063U, 22903U, 38102U, 29246U, 29411U, 29201U,
11161 19223U, 17432U, 30187U, 19087U, 48489U, 21649U, 21525U, 21584U,
11162 48835U, 34234U, 32630U, 34723U, 24679U, 33190U, 34401U, 32801U,
11163 34920U, 24923U, 33377U, 34644U, 33098U, 35205U, 25285U, 33682U,
11164 34477U, 32941U, 35008U, 25041U, 33495U, 34284U, 32677U, 34782U,
11165 24754U, 33246U, 34527U, 32988U, 35067U, 25116U, 33551U, 34301U,
11166 32693U, 34802U, 24773U, 33265U, 34544U, 33004U, 35087U, 25135U,
11167 33570U, 34334U, 32724U, 34841U, 24810U, 33302U, 34421U, 32820U,
11168 34943U, 24945U, 33399U, 34664U, 33117U, 35228U, 25307U, 33704U,
11169 34577U, 33035U, 35126U, 25172U, 33607U, 34384U, 32771U, 34900U,
11170 24885U, 33358U, 34441U, 32839U, 34966U, 24967U, 33421U, 34684U,
11171 33136U, 35251U, 25329U, 33726U, 34627U, 33082U, 35185U, 25247U,
11172 33663U, 13238U, 21970U, 22025U, 23659U, 23773U, 24698U, 24398U,
11173 25060U, 24251U, 23883U, 24829U, 24508U, 25191U, 24352U, 23946U,
11174 24904U, 24571U, 25266U, 25833U, 32521U, 33947U, 25987U, 33155U,
11175 34101U, 25874U, 32601U, 33988U, 25888U, 32787U, 34002U, 25932U,
11176 32871U, 34046U, 26004U, 33443U, 34118U, 25973U, 32912U, 34087U,
11177 26021U, 33460U, 34135U, 19041U, 21480U, 21539U, 14346U, 11406U,
11178 15765U, 31187U, 46863U, 15851U, 31201U, 46894U, 37273U, 37259U,
11179 29433U, 13993U, 25633U, 11704U, 13517U, 10905U, 31508U, 12821U,
11180 29980U, 11824U, 13637U, 11025U, 31620U, 12869U, 28557U, 29143U,
11181 29159U, 18981U, 48658U, 29384U, 2578U, 15236U, 47130U, 44827U,
11182 47399U, 21393U, 17237U, 17261U, 17285U, 17299U, 48890U, 34197U,
11183 12941U, 12975U, 21745U, 2629U, 10381U, 16635U, 31138U, 10402U,
11184 16656U, 4827U, 6815U, 9287U, 5563U, 5424U, 9229U, 5497U,
11185 5366U, 24299U, 23674U, 14198U, 2557U, 14435U, 46935U, 35816U,
11186 47204U, 23606U, 29334U, 24202U, 29348U, 24266U, 23168U, 14449U,
11187 46952U, 35830U, 47221U, 23437U, 25351U, 14165U, 142U, 2596U,
11188 29320U, 24033U, 29362U, 155U, 2609U, 44999U, 4782U, 47880U,
11189 45020U, 12766U, 10353U, 16580U, 47868U, 13391U, 22915U, 44389U,
11190 31407U, 22951U, 4680U, 4727U, 31924U, 45033U, 16443U, 47765U,
11191 30U, 48691U, 45U, 48710U, 17469U, 19332U, 45155U, 17445U,
11192 18129U, 17849U, 19770U, 45555U, 20376U, 45818U, 17617U, 19538U,
11193 45312U, 17747U, 19668U, 45448U, 18181U, 18145U, 17871U, 19792U,
11194 45578U, 20392U, 45835U, 17638U, 19559U, 45334U, 17896U, 19817U,
11195 45604U, 20600U, 45873U, 17662U, 19583U, 45359U, 18081U, 17824U,
11196 19745U, 45529U, 20357U, 45798U, 17593U, 19514U, 45287U, 19308U,
11197 45129U, 17505U, 19426U, 45194U, 18065U, 17802U, 19723U, 45506U,
11198 20341U, 45781U, 17572U, 19493U, 45265U, 17482U, 17783U, 19704U,
11199 45486U, 19345U, 45169U, 17539U, 19460U, 45230U, 17457U, 18310U,
11200 17938U, 19859U, 45648U, 20687U, 45905U, 17702U, 19623U, 45401U,
11201 17765U, 19686U, 45467U, 18024U, 19945U, 45738U, 18196U, 18326U,
11202 17960U, 19881U, 45671U, 20703U, 45922U, 17723U, 19644U, 45423U,
11203 17917U, 19838U, 45626U, 18043U, 19964U, 45758U, 20615U, 45889U,
11204 17682U, 19603U, 45380U, 18003U, 19924U, 45716U, 19320U, 45142U,
11205 17522U, 19443U, 45212U, 17985U, 19906U, 45697U, 18164U, 20411U,
11206 45855U, 5138U, 15008U, 15493U, 10337U, 37230U, 15960U, 10508U,
11207 16713U, 47474U, 16564U, 37291U, 47859U, 37430U, 14808U, 5072U,
11208 14833U, 4945U, 48564U, 4586U, 48530U, 15377U, 14511U, 14875U,
11209 15430U, 9869U, 46223U, 29815U, 29630U, 37455U, 46303U, 48822U,
11210 25587U, 38057U, 15711U, 46834U, 15883U, 46261U, 29837U, 29765U,
11211 37752U, 46365U, 47565U, 12501U, 15754U, 11496U, 37493U, 46334U,
11212 37198U, 37802U, 46396U, 47635U, 12515U, 38044U, 46458U, 46916U,
11213 46486U, 29859U, 29890U, 38007U, 46427U, 10182U, 18387U, 13841U,
11214 44884U, 12257U, 44873U, 12242U, 46591U, 46603U, 44896U, 12273U,
11215 16300U, 11525U, 46506U, 47680U, 12545U, 46663U, 25538U, 16504U,
11216 11538U, 37579U, 37467U, 37595U, 37506U, 46516U, 37612U, 37520U,
11217 37666U, 37859U, 37630U, 37535U, 37684U, 37874U, 47798U, 12571U,
11218 17129U, 37702U, 37889U, 37649U, 37845U, 46673U, 23050U, 28626U,
11219 28888U, 9958U, 13956U, 16045U, 13981U, 10543U, 13968U, 16737U,
11220 14005U, 47959U, 14030U, 47546U, 14018U, 14271U, 15621U, 46693U,
11221 46582U, 14284U, 28872U, 14957U, 15679U, 4958U, 4599U, 4616U,
11222 46740U, 15518U, 14741U, 9833U, 10423U, 14768U, 14755U, 15388U,
11223 14727U, 14944U, 9847U, 5086U, 15666U, 15402U, 10438U, 16677U,
11224 14889U, 14783U, 14971U, 22409U, 10153U, 46728U, 16282U, 13210U,
11225 9774U, 14903U, 11459U, 35712U, 11959U, 46273U, 12420U, 10056U,
11226 11225U, 46235U, 12402U, 37915U, 12070U, 37902U, 12037U, 37929U,
11227 12088U, 37966U, 12108U, 37981U, 12127U, 16691U, 11551U, 10258U,
11228 13338U, 31373U, 31871U, 16455U, 13464U, 31474U, 31986U, 47777U,
11229 13788U, 31760U, 32109U, 5149U, 15033U, 15532U, 5126U, 14985U,
11230 15470U, 5114U, 14932U, 15458U, 16320U, 29775U, 47575U, 29900U,
11231 47698U, 29931U, 10373U, 13350U, 31384U, 31883U, 14561U, 13425U,
11232 31438U, 31947U, 16600U, 13476U, 31485U, 31998U, 15116U, 13438U,
11233 31450U, 31960U, 15555U, 13451U, 31462U, 31973U, 10693U, 13378U,
11234 31395U, 31911U, 16812U, 13504U, 31496U, 32026U, 48002U, 13828U,
11235 31782U, 32149U, 47892U, 13800U, 31771U, 32121U, 44907U, 29870U,
11236 34173U, 10170U, 18374U, 10304U, 16513U, 46526U, 47807U, 46683U,
11237 4891U, 10755U, 22824U, 12732U, 18469U, 18423U, 17159U, 22838U,
11238 12749U, 18487U, 19149U, 14550U, 15045U, 15544U, 10786U, 17189U,
11239 10724U, 16917U, 48135U, 15215U, 14539U, 14997U, 15482U, 10202U,
11240 16366U, 10637U, 16781U, 47756U, 35701U, 11944U, 46614U, 46102U,
11241 12327U, 46651U, 9967U, 11181U, 37764U, 10045U, 11210U, 37815U,
11242 37830U, 5100U, 11163U, 14847U, 11441U, 4991U, 14711U, 15076U,
11243 4633U, 14695U, 15056U, 4914U, 15350U, 15019U, 4975U, 15504U,
11244 14525U, 11423U, 14918U, 11478U, 15444U, 35748U, 12007U, 46639U,
11245 12485U, 46201U, 12388U, 16847U, 4767U, 17221U, 11642U, 12054U,
11246 35643U, 35690U, 35759U, 12022U, 46547U, 12454U, 35655U, 16375U,
11247 11597U, 16834U, 11566U, 16178U, 11511U, 10001U, 11195U, 17094U,
11248 10766U, 11330U, 17069U, 11613U, 10702U, 11285U, 17118U, 11145U,
11249 13881U, 12785U, 12805U, 10745U, 11316U, 46179U, 12358U, 16927U,
11250 11583U, 14142U, 11391U, 46536U, 12439U, 35770U, 48683U, 9948U,
11251 16015U, 10522U, 47527U, 14257U, 46572U, 16608U, 47900U, 44401U,
11252 31850U, 9901U, 15924U, 37215U, 37243U, 10247U, 16422U, 37320U,
11253 37304U, 16621U, 10266U, 16463U, 47785U, 9763U, 44937U, 12288U,
11254 35724U, 11975U, 21732U, 11687U, 46626U, 12468U, 46190U, 12373U,
11255 10734U, 11301U, 44953U, 12308U, 18411U, 11671U, 46167U, 12342U,
11256 44712U, 12145U, 48581U, 12612U, 44757U, 12202U, 48626U, 12669U,
11257 44727U, 12164U, 48596U, 12631U, 44773U, 12222U, 48642U, 12689U,
11258 44742U, 12183U, 48611U, 12650U, 31842U, 33848U, 9977U, 10553U,
11259 10600U, 16870U, 17045U, 16821U, 18399U, 11655U, 46925U, 10577U,
11260 16884U, 17149U, 10346U, 16333U, 13124U, 29789U, 47589U, 13142U,
11261 29915U, 47711U, 13161U, 29945U, 16573U, 15913U, 14685U, 9937U,
11262 9889U, 15973U, 10222U, 13197U, 9912U, 15935U, 16398U, 14797U,
11263 5058U, 14819U, 4932U, 48547U, 4573U, 48513U, 15366U, 14497U,
11264 14861U, 15416U, 9860U, 46211U, 29804U, 29620U, 37443U, 46288U,
11265 48809U, 25573U, 15787U, 46249U, 29826U, 29755U, 37740U, 46350U,
11266 47555U, 15743U, 37480U, 46318U, 37181U, 37789U, 46380U, 47624U,
11267 38031U, 46442U, 46885U, 46474U, 29848U, 29880U, 37995U, 46412U,
11268 28532U, 10808U, 11345U, 35736U, 11991U, 10067U, 11240U, 10141U,
11269 16188U, 10234U, 16409U, 10614U, 16747U, 5045U, 22810U, 29582U,
11270 22877U, 5004U, 37164U, 29568U, 37351U, 32162U, 10818U, 17230U,
11271 17495U, 19416U, 45183U, 17557U, 19478U, 45249U, 38113U, 31127U,
11272 22095U, 13097U, 192U, 22070U, 9687U, 48405U, 9818U, 48472U,
11273 23225U, 9798U, 48431U, 22759U, 31167U, 47497U, 9709U, 22319U,
11274 31349U, 47725U, 30200U, 46823U, 9808U, 48443U, 22769U, 31177U,
11275 47507U, 12983U, 22234U, 22255U, 48455U, 22749U, 14235U, 22331U,
11276 25503U, 44789U, 29103U, 22063U, 38293U, 33769U, 31065U, 22244U,
11277 28549U, 30211U, 22267U, 46846U, 38343U, 2658U, 18U, 15818U,
11278 31157U, 47487U, 19231U, 13105U, 29132U, 28599U, 14096U, 46854U,
11279 48391U, 15829U, 22964U, 46557U, 22280U, 48419U, 9654U, 9665U,
11280 19075U, 12992U, 15606U, 133U, 2587U, 22293U, 14324U, 22779U,
11281 14245U, 44798U, 38351U, 9746U, 9732U, 37565U, 37551U, 22568U,
11282 14105U,
11283};
11284
11285static inline void InitHexagonMCInstrInfo(MCInstrInfo *II) {
11286 II->InitMCInstrInfo(HexagonDescs.Insts, HexagonInstrNameIndices, HexagonInstrNameData, nullptr, nullptr, 3377);
11287}
11288
11289} // end namespace llvm
11290#endif // GET_INSTRINFO_MC_DESC
11291
11292#ifdef GET_INSTRINFO_HEADER
11293#undef GET_INSTRINFO_HEADER
11294namespace llvm {
11295struct HexagonGenInstrInfo : public TargetInstrInfo {
11296 explicit HexagonGenInstrInfo(unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u);
11297 ~HexagonGenInstrInfo() override = default;
11298
11299};
11300} // end namespace llvm
11301#endif // GET_INSTRINFO_HEADER
11302
11303#ifdef GET_INSTRINFO_HELPER_DECLS
11304#undef GET_INSTRINFO_HELPER_DECLS
11305
11306
11307#endif // GET_INSTRINFO_HELPER_DECLS
11308
11309#ifdef GET_INSTRINFO_HELPERS
11310#undef GET_INSTRINFO_HELPERS
11311
11312#endif // GET_INSTRINFO_HELPERS
11313
11314#ifdef GET_INSTRINFO_CTOR_DTOR
11315#undef GET_INSTRINFO_CTOR_DTOR
11316namespace llvm {
11317extern const HexagonInstrTable HexagonDescs;
11318extern const unsigned HexagonInstrNameIndices[];
11319extern const char HexagonInstrNameData[];
11320HexagonGenInstrInfo::HexagonGenInstrInfo(unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode)
11321 : TargetInstrInfo(CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {
11322 InitMCInstrInfo(HexagonDescs.Insts, HexagonInstrNameIndices, HexagonInstrNameData, nullptr, nullptr, 3377);
11323}
11324} // end namespace llvm
11325#endif // GET_INSTRINFO_CTOR_DTOR
11326
11327#ifdef GET_INSTRINFO_MC_HELPER_DECLS
11328#undef GET_INSTRINFO_MC_HELPER_DECLS
11329
11330namespace llvm {
11331class MCInst;
11332class FeatureBitset;
11333
11334namespace Hexagon_MC {
11335
11336void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features);
11337
11338} // end namespace Hexagon_MC
11339} // end namespace llvm
11340
11341#endif // GET_INSTRINFO_MC_HELPER_DECLS
11342
11343#ifdef GET_INSTRINFO_MC_HELPERS
11344#undef GET_INSTRINFO_MC_HELPERS
11345
11346namespace llvm::Hexagon_MC {
11347} // end namespace llvm::Hexagon_MC
11348#endif // GET_GENISTRINFO_MC_HELPERS
11349
11350#if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) ||\
11351 defined(GET_AVAILABLE_OPCODE_CHECKER)
11352#define GET_COMPUTE_FEATURES
11353#endif
11354#ifdef GET_COMPUTE_FEATURES
11355#undef GET_COMPUTE_FEATURES
11356namespace llvm::Hexagon_MC {
11357// Bits for subtarget features that participate in instruction matching.
11358enum SubtargetFeatureBits : uint8_t {
11359 Feature_HasV5Bit = 2,
11360 Feature_HasV55Bit = 3,
11361 Feature_HasV60Bit = 4,
11362 Feature_HasV62Bit = 5,
11363 Feature_HasV65Bit = 6,
11364 Feature_HasV66Bit = 7,
11365 Feature_HasV67Bit = 8,
11366 Feature_HasV68Bit = 9,
11367 Feature_HasV69Bit = 10,
11368 Feature_HasV71Bit = 11,
11369 Feature_HasV73Bit = 12,
11370 Feature_HasV75Bit = 13,
11371 Feature_HasV79Bit = 14,
11372 Feature_UseHVX64BBit = 18,
11373 Feature_UseHVX128BBit = 19,
11374 Feature_UseHVXBit = 17,
11375 Feature_UseHVXV60Bit = 22,
11376 Feature_UseHVXV62Bit = 23,
11377 Feature_UseHVXV65Bit = 24,
11378 Feature_UseHVXV66Bit = 25,
11379 Feature_UseHVXV67Bit = 26,
11380 Feature_UseHVXV68Bit = 27,
11381 Feature_UseHVXV69Bit = 28,
11382 Feature_UseHVXV71Bit = 29,
11383 Feature_UseHVXV73Bit = 30,
11384 Feature_UseHVXV75Bit = 31,
11385 Feature_UseHVXV79Bit = 32,
11386 Feature_UseAudioBit = 15,
11387 Feature_UseZRegBit = 33,
11388 Feature_HasPreV65Bit = 1,
11389 Feature_UseHVXIEEEFPBit = 20,
11390 Feature_UseHVXQFloatBit = 21,
11391 Feature_HasMemNoShufBit = 0,
11392 Feature_UseCabacBit = 16,
11393};
11394
11395inline FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) {
11396 FeatureBitset Features;
11397 if (FB[Hexagon::ArchV5])
11398 Features.set(Feature_HasV5Bit);
11399 if (FB[Hexagon::ArchV55])
11400 Features.set(Feature_HasV55Bit);
11401 if (FB[Hexagon::ArchV60])
11402 Features.set(Feature_HasV60Bit);
11403 if (FB[Hexagon::ArchV62])
11404 Features.set(Feature_HasV62Bit);
11405 if (FB[Hexagon::ArchV65])
11406 Features.set(Feature_HasV65Bit);
11407 if (FB[Hexagon::ArchV66])
11408 Features.set(Feature_HasV66Bit);
11409 if (FB[Hexagon::ArchV67])
11410 Features.set(Feature_HasV67Bit);
11411 if (FB[Hexagon::ArchV68])
11412 Features.set(Feature_HasV68Bit);
11413 if (FB[Hexagon::ArchV69])
11414 Features.set(Feature_HasV69Bit);
11415 if (FB[Hexagon::ArchV71])
11416 Features.set(Feature_HasV71Bit);
11417 if (FB[Hexagon::ArchV73])
11418 Features.set(Feature_HasV73Bit);
11419 if (FB[Hexagon::ArchV75])
11420 Features.set(Feature_HasV75Bit);
11421 if (FB[Hexagon::ArchV79])
11422 Features.set(Feature_HasV79Bit);
11423 if (FB[Hexagon::ExtensionHVX64B])
11424 Features.set(Feature_UseHVX64BBit);
11425 if (FB[Hexagon::ExtensionHVX128B])
11426 Features.set(Feature_UseHVX128BBit);
11427 if (FB[Hexagon::ExtensionHVXV60])
11428 Features.set(Feature_UseHVXBit);
11429 if (FB[Hexagon::ExtensionHVXV60])
11430 Features.set(Feature_UseHVXV60Bit);
11431 if (FB[Hexagon::ExtensionHVXV62])
11432 Features.set(Feature_UseHVXV62Bit);
11433 if (FB[Hexagon::ExtensionHVXV65])
11434 Features.set(Feature_UseHVXV65Bit);
11435 if (FB[Hexagon::ExtensionHVXV66])
11436 Features.set(Feature_UseHVXV66Bit);
11437 if (FB[Hexagon::ExtensionHVXV67])
11438 Features.set(Feature_UseHVXV67Bit);
11439 if (FB[Hexagon::ExtensionHVXV68])
11440 Features.set(Feature_UseHVXV68Bit);
11441 if (FB[Hexagon::ExtensionHVXV69])
11442 Features.set(Feature_UseHVXV69Bit);
11443 if (FB[Hexagon::ExtensionHVXV71])
11444 Features.set(Feature_UseHVXV71Bit);
11445 if (FB[Hexagon::ExtensionHVXV73])
11446 Features.set(Feature_UseHVXV73Bit);
11447 if (FB[Hexagon::ExtensionHVXV75])
11448 Features.set(Feature_UseHVXV75Bit);
11449 if (FB[Hexagon::ExtensionHVXV79])
11450 Features.set(Feature_UseHVXV79Bit);
11451 if (FB[Hexagon::ExtensionAudio])
11452 Features.set(Feature_UseAudioBit);
11453 if (FB[Hexagon::ExtensionZReg])
11454 Features.set(Feature_UseZRegBit);
11455 if (FB[Hexagon::FeaturePreV65])
11456 Features.set(Feature_HasPreV65Bit);
11457 if (FB[Hexagon::ExtensionHVXIEEEFP])
11458 Features.set(Feature_UseHVXIEEEFPBit);
11459 if (FB[Hexagon::ExtensionHVXQFloat])
11460 Features.set(Feature_UseHVXQFloatBit);
11461 if (FB[Hexagon::FeatureMemNoShuf])
11462 Features.set(Feature_HasMemNoShufBit);
11463 if (FB[Hexagon::FeatureCabac])
11464 Features.set(Feature_UseCabacBit);
11465 return Features;
11466}
11467
11468inline FeatureBitset computeRequiredFeatures(unsigned Opcode) {
11469 enum : uint8_t {
11470 CEFBS_None,
11471 CEFBS_HasPreV65,
11472 CEFBS_HasV55,
11473 CEFBS_HasV60,
11474 CEFBS_HasV62,
11475 CEFBS_HasV65,
11476 CEFBS_HasV66,
11477 CEFBS_HasV67,
11478 CEFBS_HasV68,
11479 CEFBS_HasV73,
11480 CEFBS_UseCabac,
11481 CEFBS_UseHVX,
11482 CEFBS_UseHVXV60,
11483 CEFBS_UseHVXV62,
11484 CEFBS_UseHVXV65,
11485 CEFBS_UseHVXV66,
11486 CEFBS_UseHVXV68,
11487 CEFBS_UseHVXV69,
11488 CEFBS_UseHVXV73,
11489 CEFBS_HasV60_UseHVX,
11490 CEFBS_HasV67_UseAudio,
11491 CEFBS_UseHVXV66_UseZReg,
11492 CEFBS_UseHVXV68_UseHVXIEEEFP,
11493 CEFBS_UseHVXV68_UseHVXQFloat,
11494 CEFBS_UseHVXV73_UseHVXIEEEFP,
11495 CEFBS_UseHVXV73_UseHVXQFloat,
11496 CEFBS_UseHVXV79_UseHVXIEEEFP,
11497 CEFBS_UseHVXV79_UseHVXQFloat,
11498 };
11499
11500 static constexpr FeatureBitset FeatureBitsets[] = {
11501 {}, // CEFBS_None
11502 {Feature_HasPreV65Bit, },
11503 {Feature_HasV55Bit, },
11504 {Feature_HasV60Bit, },
11505 {Feature_HasV62Bit, },
11506 {Feature_HasV65Bit, },
11507 {Feature_HasV66Bit, },
11508 {Feature_HasV67Bit, },
11509 {Feature_HasV68Bit, },
11510 {Feature_HasV73Bit, },
11511 {Feature_UseCabacBit, },
11512 {Feature_UseHVXBit, },
11513 {Feature_UseHVXV60Bit, },
11514 {Feature_UseHVXV62Bit, },
11515 {Feature_UseHVXV65Bit, },
11516 {Feature_UseHVXV66Bit, },
11517 {Feature_UseHVXV68Bit, },
11518 {Feature_UseHVXV69Bit, },
11519 {Feature_UseHVXV73Bit, },
11520 {Feature_HasV60Bit, Feature_UseHVXBit, },
11521 {Feature_HasV67Bit, Feature_UseAudioBit, },
11522 {Feature_UseHVXV66Bit, Feature_UseZRegBit, },
11523 {Feature_UseHVXV68Bit, Feature_UseHVXIEEEFPBit, },
11524 {Feature_UseHVXV68Bit, Feature_UseHVXQFloatBit, },
11525 {Feature_UseHVXV73Bit, Feature_UseHVXIEEEFPBit, },
11526 {Feature_UseHVXV73Bit, Feature_UseHVXQFloatBit, },
11527 {Feature_UseHVXV79Bit, Feature_UseHVXIEEEFPBit, },
11528 {Feature_UseHVXV79Bit, Feature_UseHVXQFloatBit, },
11529 };
11530 static constexpr uint8_t RequiredFeaturesRefs[] = {
11531 CEFBS_None, // PHI = 0
11532 CEFBS_None, // INLINEASM = 1
11533 CEFBS_None, // INLINEASM_BR = 2
11534 CEFBS_None, // CFI_INSTRUCTION = 3
11535 CEFBS_None, // EH_LABEL = 4
11536 CEFBS_None, // GC_LABEL = 5
11537 CEFBS_None, // ANNOTATION_LABEL = 6
11538 CEFBS_None, // KILL = 7
11539 CEFBS_None, // EXTRACT_SUBREG = 8
11540 CEFBS_None, // INSERT_SUBREG = 9
11541 CEFBS_None, // IMPLICIT_DEF = 10
11542 CEFBS_None, // INIT_UNDEF = 11
11543 CEFBS_None, // SUBREG_TO_REG = 12
11544 CEFBS_None, // COPY_TO_REGCLASS = 13
11545 CEFBS_None, // DBG_VALUE = 14
11546 CEFBS_None, // DBG_VALUE_LIST = 15
11547 CEFBS_None, // DBG_INSTR_REF = 16
11548 CEFBS_None, // DBG_PHI = 17
11549 CEFBS_None, // DBG_LABEL = 18
11550 CEFBS_None, // REG_SEQUENCE = 19
11551 CEFBS_None, // COPY = 20
11552 CEFBS_None, // BUNDLE = 21
11553 CEFBS_None, // LIFETIME_START = 22
11554 CEFBS_None, // LIFETIME_END = 23
11555 CEFBS_None, // PSEUDO_PROBE = 24
11556 CEFBS_None, // ARITH_FENCE = 25
11557 CEFBS_None, // STACKMAP = 26
11558 CEFBS_None, // FENTRY_CALL = 27
11559 CEFBS_None, // PATCHPOINT = 28
11560 CEFBS_None, // LOAD_STACK_GUARD = 29
11561 CEFBS_None, // PREALLOCATED_SETUP = 30
11562 CEFBS_None, // PREALLOCATED_ARG = 31
11563 CEFBS_None, // STATEPOINT = 32
11564 CEFBS_None, // LOCAL_ESCAPE = 33
11565 CEFBS_None, // FAULTING_OP = 34
11566 CEFBS_None, // PATCHABLE_OP = 35
11567 CEFBS_None, // PATCHABLE_FUNCTION_ENTER = 36
11568 CEFBS_None, // PATCHABLE_RET = 37
11569 CEFBS_None, // PATCHABLE_FUNCTION_EXIT = 38
11570 CEFBS_None, // PATCHABLE_TAIL_CALL = 39
11571 CEFBS_None, // PATCHABLE_EVENT_CALL = 40
11572 CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL = 41
11573 CEFBS_None, // ICALL_BRANCH_FUNNEL = 42
11574 CEFBS_None, // FAKE_USE = 43
11575 CEFBS_None, // MEMBARRIER = 44
11576 CEFBS_None, // JUMP_TABLE_DEBUG_INFO = 45
11577 CEFBS_None, // CONVERGENCECTRL_ENTRY = 46
11578 CEFBS_None, // CONVERGENCECTRL_ANCHOR = 47
11579 CEFBS_None, // CONVERGENCECTRL_LOOP = 48
11580 CEFBS_None, // CONVERGENCECTRL_GLUE = 49
11581 CEFBS_None, // G_ASSERT_SEXT = 50
11582 CEFBS_None, // G_ASSERT_ZEXT = 51
11583 CEFBS_None, // G_ASSERT_ALIGN = 52
11584 CEFBS_None, // G_ADD = 53
11585 CEFBS_None, // G_SUB = 54
11586 CEFBS_None, // G_MUL = 55
11587 CEFBS_None, // G_SDIV = 56
11588 CEFBS_None, // G_UDIV = 57
11589 CEFBS_None, // G_SREM = 58
11590 CEFBS_None, // G_UREM = 59
11591 CEFBS_None, // G_SDIVREM = 60
11592 CEFBS_None, // G_UDIVREM = 61
11593 CEFBS_None, // G_AND = 62
11594 CEFBS_None, // G_OR = 63
11595 CEFBS_None, // G_XOR = 64
11596 CEFBS_None, // G_ABDS = 65
11597 CEFBS_None, // G_ABDU = 66
11598 CEFBS_None, // G_IMPLICIT_DEF = 67
11599 CEFBS_None, // G_PHI = 68
11600 CEFBS_None, // G_FRAME_INDEX = 69
11601 CEFBS_None, // G_GLOBAL_VALUE = 70
11602 CEFBS_None, // G_PTRAUTH_GLOBAL_VALUE = 71
11603 CEFBS_None, // G_CONSTANT_POOL = 72
11604 CEFBS_None, // G_EXTRACT = 73
11605 CEFBS_None, // G_UNMERGE_VALUES = 74
11606 CEFBS_None, // G_INSERT = 75
11607 CEFBS_None, // G_MERGE_VALUES = 76
11608 CEFBS_None, // G_BUILD_VECTOR = 77
11609 CEFBS_None, // G_BUILD_VECTOR_TRUNC = 78
11610 CEFBS_None, // G_CONCAT_VECTORS = 79
11611 CEFBS_None, // G_PTRTOINT = 80
11612 CEFBS_None, // G_INTTOPTR = 81
11613 CEFBS_None, // G_BITCAST = 82
11614 CEFBS_None, // G_FREEZE = 83
11615 CEFBS_None, // G_CONSTANT_FOLD_BARRIER = 84
11616 CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND = 85
11617 CEFBS_None, // G_INTRINSIC_TRUNC = 86
11618 CEFBS_None, // G_INTRINSIC_ROUND = 87
11619 CEFBS_None, // G_INTRINSIC_LRINT = 88
11620 CEFBS_None, // G_INTRINSIC_LLRINT = 89
11621 CEFBS_None, // G_INTRINSIC_ROUNDEVEN = 90
11622 CEFBS_None, // G_READCYCLECOUNTER = 91
11623 CEFBS_None, // G_READSTEADYCOUNTER = 92
11624 CEFBS_None, // G_LOAD = 93
11625 CEFBS_None, // G_SEXTLOAD = 94
11626 CEFBS_None, // G_ZEXTLOAD = 95
11627 CEFBS_None, // G_INDEXED_LOAD = 96
11628 CEFBS_None, // G_INDEXED_SEXTLOAD = 97
11629 CEFBS_None, // G_INDEXED_ZEXTLOAD = 98
11630 CEFBS_None, // G_STORE = 99
11631 CEFBS_None, // G_INDEXED_STORE = 100
11632 CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS = 101
11633 CEFBS_None, // G_ATOMIC_CMPXCHG = 102
11634 CEFBS_None, // G_ATOMICRMW_XCHG = 103
11635 CEFBS_None, // G_ATOMICRMW_ADD = 104
11636 CEFBS_None, // G_ATOMICRMW_SUB = 105
11637 CEFBS_None, // G_ATOMICRMW_AND = 106
11638 CEFBS_None, // G_ATOMICRMW_NAND = 107
11639 CEFBS_None, // G_ATOMICRMW_OR = 108
11640 CEFBS_None, // G_ATOMICRMW_XOR = 109
11641 CEFBS_None, // G_ATOMICRMW_MAX = 110
11642 CEFBS_None, // G_ATOMICRMW_MIN = 111
11643 CEFBS_None, // G_ATOMICRMW_UMAX = 112
11644 CEFBS_None, // G_ATOMICRMW_UMIN = 113
11645 CEFBS_None, // G_ATOMICRMW_FADD = 114
11646 CEFBS_None, // G_ATOMICRMW_FSUB = 115
11647 CEFBS_None, // G_ATOMICRMW_FMAX = 116
11648 CEFBS_None, // G_ATOMICRMW_FMIN = 117
11649 CEFBS_None, // G_ATOMICRMW_FMAXIMUM = 118
11650 CEFBS_None, // G_ATOMICRMW_FMINIMUM = 119
11651 CEFBS_None, // G_ATOMICRMW_UINC_WRAP = 120
11652 CEFBS_None, // G_ATOMICRMW_UDEC_WRAP = 121
11653 CEFBS_None, // G_ATOMICRMW_USUB_COND = 122
11654 CEFBS_None, // G_ATOMICRMW_USUB_SAT = 123
11655 CEFBS_None, // G_FENCE = 124
11656 CEFBS_None, // G_PREFETCH = 125
11657 CEFBS_None, // G_BRCOND = 126
11658 CEFBS_None, // G_BRINDIRECT = 127
11659 CEFBS_None, // G_INVOKE_REGION_START = 128
11660 CEFBS_None, // G_INTRINSIC = 129
11661 CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS = 130
11662 CEFBS_None, // G_INTRINSIC_CONVERGENT = 131
11663 CEFBS_None, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 132
11664 CEFBS_None, // G_ANYEXT = 133
11665 CEFBS_None, // G_TRUNC = 134
11666 CEFBS_None, // G_CONSTANT = 135
11667 CEFBS_None, // G_FCONSTANT = 136
11668 CEFBS_None, // G_VASTART = 137
11669 CEFBS_None, // G_VAARG = 138
11670 CEFBS_None, // G_SEXT = 139
11671 CEFBS_None, // G_SEXT_INREG = 140
11672 CEFBS_None, // G_ZEXT = 141
11673 CEFBS_None, // G_SHL = 142
11674 CEFBS_None, // G_LSHR = 143
11675 CEFBS_None, // G_ASHR = 144
11676 CEFBS_None, // G_FSHL = 145
11677 CEFBS_None, // G_FSHR = 146
11678 CEFBS_None, // G_ROTR = 147
11679 CEFBS_None, // G_ROTL = 148
11680 CEFBS_None, // G_ICMP = 149
11681 CEFBS_None, // G_FCMP = 150
11682 CEFBS_None, // G_SCMP = 151
11683 CEFBS_None, // G_UCMP = 152
11684 CEFBS_None, // G_SELECT = 153
11685 CEFBS_None, // G_UADDO = 154
11686 CEFBS_None, // G_UADDE = 155
11687 CEFBS_None, // G_USUBO = 156
11688 CEFBS_None, // G_USUBE = 157
11689 CEFBS_None, // G_SADDO = 158
11690 CEFBS_None, // G_SADDE = 159
11691 CEFBS_None, // G_SSUBO = 160
11692 CEFBS_None, // G_SSUBE = 161
11693 CEFBS_None, // G_UMULO = 162
11694 CEFBS_None, // G_SMULO = 163
11695 CEFBS_None, // G_UMULH = 164
11696 CEFBS_None, // G_SMULH = 165
11697 CEFBS_None, // G_UADDSAT = 166
11698 CEFBS_None, // G_SADDSAT = 167
11699 CEFBS_None, // G_USUBSAT = 168
11700 CEFBS_None, // G_SSUBSAT = 169
11701 CEFBS_None, // G_USHLSAT = 170
11702 CEFBS_None, // G_SSHLSAT = 171
11703 CEFBS_None, // G_SMULFIX = 172
11704 CEFBS_None, // G_UMULFIX = 173
11705 CEFBS_None, // G_SMULFIXSAT = 174
11706 CEFBS_None, // G_UMULFIXSAT = 175
11707 CEFBS_None, // G_SDIVFIX = 176
11708 CEFBS_None, // G_UDIVFIX = 177
11709 CEFBS_None, // G_SDIVFIXSAT = 178
11710 CEFBS_None, // G_UDIVFIXSAT = 179
11711 CEFBS_None, // G_FADD = 180
11712 CEFBS_None, // G_FSUB = 181
11713 CEFBS_None, // G_FMUL = 182
11714 CEFBS_None, // G_FMA = 183
11715 CEFBS_None, // G_FMAD = 184
11716 CEFBS_None, // G_FDIV = 185
11717 CEFBS_None, // G_FREM = 186
11718 CEFBS_None, // G_FPOW = 187
11719 CEFBS_None, // G_FPOWI = 188
11720 CEFBS_None, // G_FEXP = 189
11721 CEFBS_None, // G_FEXP2 = 190
11722 CEFBS_None, // G_FEXP10 = 191
11723 CEFBS_None, // G_FLOG = 192
11724 CEFBS_None, // G_FLOG2 = 193
11725 CEFBS_None, // G_FLOG10 = 194
11726 CEFBS_None, // G_FLDEXP = 195
11727 CEFBS_None, // G_FFREXP = 196
11728 CEFBS_None, // G_FNEG = 197
11729 CEFBS_None, // G_FPEXT = 198
11730 CEFBS_None, // G_FPTRUNC = 199
11731 CEFBS_None, // G_FPTOSI = 200
11732 CEFBS_None, // G_FPTOUI = 201
11733 CEFBS_None, // G_SITOFP = 202
11734 CEFBS_None, // G_UITOFP = 203
11735 CEFBS_None, // G_FPTOSI_SAT = 204
11736 CEFBS_None, // G_FPTOUI_SAT = 205
11737 CEFBS_None, // G_FABS = 206
11738 CEFBS_None, // G_FCOPYSIGN = 207
11739 CEFBS_None, // G_IS_FPCLASS = 208
11740 CEFBS_None, // G_FCANONICALIZE = 209
11741 CEFBS_None, // G_FMINNUM = 210
11742 CEFBS_None, // G_FMAXNUM = 211
11743 CEFBS_None, // G_FMINNUM_IEEE = 212
11744 CEFBS_None, // G_FMAXNUM_IEEE = 213
11745 CEFBS_None, // G_FMINIMUM = 214
11746 CEFBS_None, // G_FMAXIMUM = 215
11747 CEFBS_None, // G_FMINIMUMNUM = 216
11748 CEFBS_None, // G_FMAXIMUMNUM = 217
11749 CEFBS_None, // G_GET_FPENV = 218
11750 CEFBS_None, // G_SET_FPENV = 219
11751 CEFBS_None, // G_RESET_FPENV = 220
11752 CEFBS_None, // G_GET_FPMODE = 221
11753 CEFBS_None, // G_SET_FPMODE = 222
11754 CEFBS_None, // G_RESET_FPMODE = 223
11755 CEFBS_None, // G_PTR_ADD = 224
11756 CEFBS_None, // G_PTRMASK = 225
11757 CEFBS_None, // G_SMIN = 226
11758 CEFBS_None, // G_SMAX = 227
11759 CEFBS_None, // G_UMIN = 228
11760 CEFBS_None, // G_UMAX = 229
11761 CEFBS_None, // G_ABS = 230
11762 CEFBS_None, // G_LROUND = 231
11763 CEFBS_None, // G_LLROUND = 232
11764 CEFBS_None, // G_BR = 233
11765 CEFBS_None, // G_BRJT = 234
11766 CEFBS_None, // G_VSCALE = 235
11767 CEFBS_None, // G_INSERT_SUBVECTOR = 236
11768 CEFBS_None, // G_EXTRACT_SUBVECTOR = 237
11769 CEFBS_None, // G_INSERT_VECTOR_ELT = 238
11770 CEFBS_None, // G_EXTRACT_VECTOR_ELT = 239
11771 CEFBS_None, // G_SHUFFLE_VECTOR = 240
11772 CEFBS_None, // G_SPLAT_VECTOR = 241
11773 CEFBS_None, // G_STEP_VECTOR = 242
11774 CEFBS_None, // G_VECTOR_COMPRESS = 243
11775 CEFBS_None, // G_CTTZ = 244
11776 CEFBS_None, // G_CTTZ_ZERO_UNDEF = 245
11777 CEFBS_None, // G_CTLZ = 246
11778 CEFBS_None, // G_CTLZ_ZERO_UNDEF = 247
11779 CEFBS_None, // G_CTPOP = 248
11780 CEFBS_None, // G_BSWAP = 249
11781 CEFBS_None, // G_BITREVERSE = 250
11782 CEFBS_None, // G_FCEIL = 251
11783 CEFBS_None, // G_FCOS = 252
11784 CEFBS_None, // G_FSIN = 253
11785 CEFBS_None, // G_FSINCOS = 254
11786 CEFBS_None, // G_FTAN = 255
11787 CEFBS_None, // G_FACOS = 256
11788 CEFBS_None, // G_FASIN = 257
11789 CEFBS_None, // G_FATAN = 258
11790 CEFBS_None, // G_FATAN2 = 259
11791 CEFBS_None, // G_FCOSH = 260
11792 CEFBS_None, // G_FSINH = 261
11793 CEFBS_None, // G_FTANH = 262
11794 CEFBS_None, // G_FSQRT = 263
11795 CEFBS_None, // G_FFLOOR = 264
11796 CEFBS_None, // G_FRINT = 265
11797 CEFBS_None, // G_FNEARBYINT = 266
11798 CEFBS_None, // G_ADDRSPACE_CAST = 267
11799 CEFBS_None, // G_BLOCK_ADDR = 268
11800 CEFBS_None, // G_JUMP_TABLE = 269
11801 CEFBS_None, // G_DYN_STACKALLOC = 270
11802 CEFBS_None, // G_STACKSAVE = 271
11803 CEFBS_None, // G_STACKRESTORE = 272
11804 CEFBS_None, // G_STRICT_FADD = 273
11805 CEFBS_None, // G_STRICT_FSUB = 274
11806 CEFBS_None, // G_STRICT_FMUL = 275
11807 CEFBS_None, // G_STRICT_FDIV = 276
11808 CEFBS_None, // G_STRICT_FREM = 277
11809 CEFBS_None, // G_STRICT_FMA = 278
11810 CEFBS_None, // G_STRICT_FSQRT = 279
11811 CEFBS_None, // G_STRICT_FLDEXP = 280
11812 CEFBS_None, // G_READ_REGISTER = 281
11813 CEFBS_None, // G_WRITE_REGISTER = 282
11814 CEFBS_None, // G_MEMCPY = 283
11815 CEFBS_None, // G_MEMCPY_INLINE = 284
11816 CEFBS_None, // G_MEMMOVE = 285
11817 CEFBS_None, // G_MEMSET = 286
11818 CEFBS_None, // G_BZERO = 287
11819 CEFBS_None, // G_TRAP = 288
11820 CEFBS_None, // G_DEBUGTRAP = 289
11821 CEFBS_None, // G_UBSANTRAP = 290
11822 CEFBS_None, // G_VECREDUCE_SEQ_FADD = 291
11823 CEFBS_None, // G_VECREDUCE_SEQ_FMUL = 292
11824 CEFBS_None, // G_VECREDUCE_FADD = 293
11825 CEFBS_None, // G_VECREDUCE_FMUL = 294
11826 CEFBS_None, // G_VECREDUCE_FMAX = 295
11827 CEFBS_None, // G_VECREDUCE_FMIN = 296
11828 CEFBS_None, // G_VECREDUCE_FMAXIMUM = 297
11829 CEFBS_None, // G_VECREDUCE_FMINIMUM = 298
11830 CEFBS_None, // G_VECREDUCE_ADD = 299
11831 CEFBS_None, // G_VECREDUCE_MUL = 300
11832 CEFBS_None, // G_VECREDUCE_AND = 301
11833 CEFBS_None, // G_VECREDUCE_OR = 302
11834 CEFBS_None, // G_VECREDUCE_XOR = 303
11835 CEFBS_None, // G_VECREDUCE_SMAX = 304
11836 CEFBS_None, // G_VECREDUCE_SMIN = 305
11837 CEFBS_None, // G_VECREDUCE_UMAX = 306
11838 CEFBS_None, // G_VECREDUCE_UMIN = 307
11839 CEFBS_None, // G_SBFX = 308
11840 CEFBS_None, // G_UBFX = 309
11841 CEFBS_None, // A2_addsp = 310
11842 CEFBS_None, // A2_iconst = 311
11843 CEFBS_None, // A2_neg = 312
11844 CEFBS_None, // A2_not = 313
11845 CEFBS_None, // A2_tfrf = 314
11846 CEFBS_None, // A2_tfrfnew = 315
11847 CEFBS_None, // A2_tfrp = 316
11848 CEFBS_None, // A2_tfrpf = 317
11849 CEFBS_None, // A2_tfrpfnew = 318
11850 CEFBS_None, // A2_tfrpi = 319
11851 CEFBS_None, // A2_tfrpt = 320
11852 CEFBS_None, // A2_tfrptnew = 321
11853 CEFBS_None, // A2_tfrt = 322
11854 CEFBS_None, // A2_tfrtnew = 323
11855 CEFBS_None, // A2_vaddb_map = 324
11856 CEFBS_None, // A2_vsubb_map = 325
11857 CEFBS_None, // A2_zxtb = 326
11858 CEFBS_None, // A4_boundscheck = 327
11859 CEFBS_None, // ADJCALLSTACKDOWN = 328
11860 CEFBS_None, // ADJCALLSTACKUP = 329
11861 CEFBS_None, // C2_cmpgei = 330
11862 CEFBS_None, // C2_cmpgeui = 331
11863 CEFBS_None, // C2_cmplt = 332
11864 CEFBS_None, // C2_cmpltu = 333
11865 CEFBS_None, // C2_pxfer_map = 334
11866 CEFBS_None, // DUPLEX_Pseudo = 335
11867 CEFBS_None, // ENDLOOP0 = 336
11868 CEFBS_None, // ENDLOOP01 = 337
11869 CEFBS_None, // ENDLOOP1 = 338
11870 CEFBS_None, // J2_endloop0 = 339
11871 CEFBS_None, // J2_endloop01 = 340
11872 CEFBS_None, // J2_endloop1 = 341
11873 CEFBS_HasV60, // J2_jumpf_nopred_map = 342
11874 CEFBS_HasV60, // J2_jumprf_nopred_map = 343
11875 CEFBS_HasV60, // J2_jumprt_nopred_map = 344
11876 CEFBS_HasV60, // J2_jumpt_nopred_map = 345
11877 CEFBS_HasV65, // J2_trap1_noregmap = 346
11878 CEFBS_None, // L2_loadalignb_zomap = 347
11879 CEFBS_None, // L2_loadalignh_zomap = 348
11880 CEFBS_None, // L2_loadbsw2_zomap = 349
11881 CEFBS_None, // L2_loadbsw4_zomap = 350
11882 CEFBS_None, // L2_loadbzw2_zomap = 351
11883 CEFBS_None, // L2_loadbzw4_zomap = 352
11884 CEFBS_None, // L2_loadrb_zomap = 353
11885 CEFBS_None, // L2_loadrd_zomap = 354
11886 CEFBS_None, // L2_loadrh_zomap = 355
11887 CEFBS_None, // L2_loadri_zomap = 356
11888 CEFBS_None, // L2_loadrub_zomap = 357
11889 CEFBS_None, // L2_loadruh_zomap = 358
11890 CEFBS_None, // L2_ploadrbf_zomap = 359
11891 CEFBS_None, // L2_ploadrbfnew_zomap = 360
11892 CEFBS_None, // L2_ploadrbt_zomap = 361
11893 CEFBS_None, // L2_ploadrbtnew_zomap = 362
11894 CEFBS_None, // L2_ploadrdf_zomap = 363
11895 CEFBS_None, // L2_ploadrdfnew_zomap = 364
11896 CEFBS_None, // L2_ploadrdt_zomap = 365
11897 CEFBS_None, // L2_ploadrdtnew_zomap = 366
11898 CEFBS_None, // L2_ploadrhf_zomap = 367
11899 CEFBS_None, // L2_ploadrhfnew_zomap = 368
11900 CEFBS_None, // L2_ploadrht_zomap = 369
11901 CEFBS_None, // L2_ploadrhtnew_zomap = 370
11902 CEFBS_None, // L2_ploadrif_zomap = 371
11903 CEFBS_None, // L2_ploadrifnew_zomap = 372
11904 CEFBS_None, // L2_ploadrit_zomap = 373
11905 CEFBS_None, // L2_ploadritnew_zomap = 374
11906 CEFBS_None, // L2_ploadrubf_zomap = 375
11907 CEFBS_None, // L2_ploadrubfnew_zomap = 376
11908 CEFBS_None, // L2_ploadrubt_zomap = 377
11909 CEFBS_None, // L2_ploadrubtnew_zomap = 378
11910 CEFBS_None, // L2_ploadruhf_zomap = 379
11911 CEFBS_None, // L2_ploadruhfnew_zomap = 380
11912 CEFBS_None, // L2_ploadruht_zomap = 381
11913 CEFBS_None, // L2_ploadruhtnew_zomap = 382
11914 CEFBS_None, // L4_add_memopb_zomap = 383
11915 CEFBS_None, // L4_add_memoph_zomap = 384
11916 CEFBS_None, // L4_add_memopw_zomap = 385
11917 CEFBS_None, // L4_and_memopb_zomap = 386
11918 CEFBS_None, // L4_and_memoph_zomap = 387
11919 CEFBS_None, // L4_and_memopw_zomap = 388
11920 CEFBS_None, // L4_iadd_memopb_zomap = 389
11921 CEFBS_None, // L4_iadd_memoph_zomap = 390
11922 CEFBS_None, // L4_iadd_memopw_zomap = 391
11923 CEFBS_None, // L4_iand_memopb_zomap = 392
11924 CEFBS_None, // L4_iand_memoph_zomap = 393
11925 CEFBS_None, // L4_iand_memopw_zomap = 394
11926 CEFBS_None, // L4_ior_memopb_zomap = 395
11927 CEFBS_None, // L4_ior_memoph_zomap = 396
11928 CEFBS_None, // L4_ior_memopw_zomap = 397
11929 CEFBS_None, // L4_isub_memopb_zomap = 398
11930 CEFBS_None, // L4_isub_memoph_zomap = 399
11931 CEFBS_None, // L4_isub_memopw_zomap = 400
11932 CEFBS_None, // L4_or_memopb_zomap = 401
11933 CEFBS_None, // L4_or_memoph_zomap = 402
11934 CEFBS_None, // L4_or_memopw_zomap = 403
11935 CEFBS_HasV65, // L4_return_map_to_raw_f = 404
11936 CEFBS_HasV65, // L4_return_map_to_raw_fnew_pnt = 405
11937 CEFBS_HasV65, // L4_return_map_to_raw_fnew_pt = 406
11938 CEFBS_HasV65, // L4_return_map_to_raw_t = 407
11939 CEFBS_HasV65, // L4_return_map_to_raw_tnew_pnt = 408
11940 CEFBS_HasV65, // L4_return_map_to_raw_tnew_pt = 409
11941 CEFBS_None, // L4_sub_memopb_zomap = 410
11942 CEFBS_None, // L4_sub_memoph_zomap = 411
11943 CEFBS_None, // L4_sub_memopw_zomap = 412
11944 CEFBS_HasV65, // L6_deallocframe_map_to_raw = 413
11945 CEFBS_HasV65, // L6_return_map_to_raw = 414
11946 CEFBS_None, // LDriw_ctr = 415
11947 CEFBS_None, // LDriw_pred = 416
11948 CEFBS_None, // M2_mpysmi = 417
11949 CEFBS_None, // M2_mpyui = 418
11950 CEFBS_None, // M2_vrcmpys_acc_s1 = 419
11951 CEFBS_None, // M2_vrcmpys_s1 = 420
11952 CEFBS_None, // M2_vrcmpys_s1rp = 421
11953 CEFBS_HasV67, // M7_vdmpy = 422
11954 CEFBS_HasV67, // M7_vdmpy_acc = 423
11955 CEFBS_None, // PS_aligna = 424
11956 CEFBS_None, // PS_alloca = 425
11957 CEFBS_None, // PS_call_instrprof_custom = 426
11958 CEFBS_None, // PS_call_nr = 427
11959 CEFBS_None, // PS_crash = 428
11960 CEFBS_None, // PS_false = 429
11961 CEFBS_None, // PS_fi = 430
11962 CEFBS_None, // PS_fia = 431
11963 CEFBS_None, // PS_loadrb_pci = 432
11964 CEFBS_None, // PS_loadrb_pcr = 433
11965 CEFBS_None, // PS_loadrd_pci = 434
11966 CEFBS_None, // PS_loadrd_pcr = 435
11967 CEFBS_None, // PS_loadrh_pci = 436
11968 CEFBS_None, // PS_loadrh_pcr = 437
11969 CEFBS_None, // PS_loadri_pci = 438
11970 CEFBS_None, // PS_loadri_pcr = 439
11971 CEFBS_None, // PS_loadrub_pci = 440
11972 CEFBS_None, // PS_loadrub_pcr = 441
11973 CEFBS_None, // PS_loadruh_pci = 442
11974 CEFBS_None, // PS_loadruh_pcr = 443
11975 CEFBS_None, // PS_pselect = 444
11976 CEFBS_None, // PS_qfalse = 445
11977 CEFBS_None, // PS_qtrue = 446
11978 CEFBS_None, // PS_storerb_pci = 447
11979 CEFBS_None, // PS_storerb_pcr = 448
11980 CEFBS_None, // PS_storerd_pci = 449
11981 CEFBS_None, // PS_storerd_pcr = 450
11982 CEFBS_None, // PS_storerf_pci = 451
11983 CEFBS_None, // PS_storerf_pcr = 452
11984 CEFBS_None, // PS_storerh_pci = 453
11985 CEFBS_None, // PS_storerh_pcr = 454
11986 CEFBS_None, // PS_storeri_pci = 455
11987 CEFBS_None, // PS_storeri_pcr = 456
11988 CEFBS_None, // PS_tailcall_i = 457
11989 CEFBS_None, // PS_tailcall_r = 458
11990 CEFBS_None, // PS_true = 459
11991 CEFBS_None, // PS_vdd0 = 460
11992 CEFBS_HasV60_UseHVX, // PS_vloadrq_ai = 461
11993 CEFBS_HasV60_UseHVX, // PS_vloadrv_ai = 462
11994 CEFBS_HasV60_UseHVX, // PS_vloadrv_nt_ai = 463
11995 CEFBS_HasV60_UseHVX, // PS_vloadrw_ai = 464
11996 CEFBS_HasV60_UseHVX, // PS_vloadrw_nt_ai = 465
11997 CEFBS_None, // PS_vmulw = 466
11998 CEFBS_None, // PS_vmulw_acc = 467
11999 CEFBS_HasV60_UseHVX, // PS_vselect = 468
12000 CEFBS_UseHVX, // PS_vsplatib = 469
12001 CEFBS_UseHVX, // PS_vsplatih = 470
12002 CEFBS_UseHVX, // PS_vsplatiw = 471
12003 CEFBS_UseHVX, // PS_vsplatrb = 472
12004 CEFBS_UseHVX, // PS_vsplatrh = 473
12005 CEFBS_UseHVX, // PS_vsplatrw = 474
12006 CEFBS_HasV60_UseHVX, // PS_vstorerq_ai = 475
12007 CEFBS_HasV60_UseHVX, // PS_vstorerv_ai = 476
12008 CEFBS_HasV60_UseHVX, // PS_vstorerv_nt_ai = 477
12009 CEFBS_HasV60_UseHVX, // PS_vstorerw_ai = 478
12010 CEFBS_HasV60_UseHVX, // PS_vstorerw_nt_ai = 479
12011 CEFBS_HasV60_UseHVX, // PS_wselect = 480
12012 CEFBS_None, // S2_asr_i_p_rnd_goodsyntax = 481
12013 CEFBS_None, // S2_asr_i_r_rnd_goodsyntax = 482
12014 CEFBS_None, // S2_pstorerbf_zomap = 483
12015 CEFBS_None, // S2_pstorerbnewf_zomap = 484
12016 CEFBS_None, // S2_pstorerbnewt_zomap = 485
12017 CEFBS_None, // S2_pstorerbt_zomap = 486
12018 CEFBS_None, // S2_pstorerdf_zomap = 487
12019 CEFBS_None, // S2_pstorerdt_zomap = 488
12020 CEFBS_None, // S2_pstorerff_zomap = 489
12021 CEFBS_None, // S2_pstorerft_zomap = 490
12022 CEFBS_None, // S2_pstorerhf_zomap = 491
12023 CEFBS_None, // S2_pstorerhnewf_zomap = 492
12024 CEFBS_None, // S2_pstorerhnewt_zomap = 493
12025 CEFBS_None, // S2_pstorerht_zomap = 494
12026 CEFBS_None, // S2_pstorerif_zomap = 495
12027 CEFBS_None, // S2_pstorerinewf_zomap = 496
12028 CEFBS_None, // S2_pstorerinewt_zomap = 497
12029 CEFBS_None, // S2_pstorerit_zomap = 498
12030 CEFBS_None, // S2_storerb_zomap = 499
12031 CEFBS_None, // S2_storerbnew_zomap = 500
12032 CEFBS_None, // S2_storerd_zomap = 501
12033 CEFBS_None, // S2_storerf_zomap = 502
12034 CEFBS_None, // S2_storerh_zomap = 503
12035 CEFBS_None, // S2_storerhnew_zomap = 504
12036 CEFBS_None, // S2_storeri_zomap = 505
12037 CEFBS_None, // S2_storerinew_zomap = 506
12038 CEFBS_None, // S2_tableidxb_goodsyntax = 507
12039 CEFBS_None, // S2_tableidxd_goodsyntax = 508
12040 CEFBS_None, // S2_tableidxh_goodsyntax = 509
12041 CEFBS_None, // S2_tableidxw_goodsyntax = 510
12042 CEFBS_None, // S4_pstorerbfnew_zomap = 511
12043 CEFBS_None, // S4_pstorerbnewfnew_zomap = 512
12044 CEFBS_None, // S4_pstorerbnewtnew_zomap = 513
12045 CEFBS_None, // S4_pstorerbtnew_zomap = 514
12046 CEFBS_None, // S4_pstorerdfnew_zomap = 515
12047 CEFBS_None, // S4_pstorerdtnew_zomap = 516
12048 CEFBS_None, // S4_pstorerffnew_zomap = 517
12049 CEFBS_None, // S4_pstorerftnew_zomap = 518
12050 CEFBS_None, // S4_pstorerhfnew_zomap = 519
12051 CEFBS_None, // S4_pstorerhnewfnew_zomap = 520
12052 CEFBS_None, // S4_pstorerhnewtnew_zomap = 521
12053 CEFBS_None, // S4_pstorerhtnew_zomap = 522
12054 CEFBS_None, // S4_pstorerifnew_zomap = 523
12055 CEFBS_None, // S4_pstorerinewfnew_zomap = 524
12056 CEFBS_None, // S4_pstorerinewtnew_zomap = 525
12057 CEFBS_None, // S4_pstoreritnew_zomap = 526
12058 CEFBS_None, // S4_storeirb_zomap = 527
12059 CEFBS_None, // S4_storeirbf_zomap = 528
12060 CEFBS_None, // S4_storeirbfnew_zomap = 529
12061 CEFBS_None, // S4_storeirbt_zomap = 530
12062 CEFBS_None, // S4_storeirbtnew_zomap = 531
12063 CEFBS_None, // S4_storeirh_zomap = 532
12064 CEFBS_None, // S4_storeirhf_zomap = 533
12065 CEFBS_None, // S4_storeirhfnew_zomap = 534
12066 CEFBS_None, // S4_storeirht_zomap = 535
12067 CEFBS_None, // S4_storeirhtnew_zomap = 536
12068 CEFBS_None, // S4_storeiri_zomap = 537
12069 CEFBS_None, // S4_storeirif_zomap = 538
12070 CEFBS_None, // S4_storeirifnew_zomap = 539
12071 CEFBS_None, // S4_storeirit_zomap = 540
12072 CEFBS_None, // S4_storeiritnew_zomap = 541
12073 CEFBS_None, // S5_asrhub_rnd_sat_goodsyntax = 542
12074 CEFBS_None, // S5_vasrhrnd_goodsyntax = 543
12075 CEFBS_HasV65, // S6_allocframe_to_raw = 544
12076 CEFBS_None, // STriw_ctr = 545
12077 CEFBS_None, // STriw_pred = 546
12078 CEFBS_UseHVXV60, // V6_MAP_equb = 547
12079 CEFBS_UseHVXV60, // V6_MAP_equb_and = 548
12080 CEFBS_UseHVXV60, // V6_MAP_equb_ior = 549
12081 CEFBS_UseHVXV60, // V6_MAP_equb_xor = 550
12082 CEFBS_UseHVXV60, // V6_MAP_equh = 551
12083 CEFBS_UseHVXV60, // V6_MAP_equh_and = 552
12084 CEFBS_UseHVXV60, // V6_MAP_equh_ior = 553
12085 CEFBS_UseHVXV60, // V6_MAP_equh_xor = 554
12086 CEFBS_UseHVXV60, // V6_MAP_equw = 555
12087 CEFBS_UseHVXV60, // V6_MAP_equw_and = 556
12088 CEFBS_UseHVXV60, // V6_MAP_equw_ior = 557
12089 CEFBS_UseHVXV60, // V6_MAP_equw_xor = 558
12090 CEFBS_UseHVXV73, // V6_dbl_ld0 = 559
12091 CEFBS_UseHVXV73, // V6_dbl_st0 = 560
12092 CEFBS_UseHVXV60, // V6_extractw_alt = 561
12093 CEFBS_UseHVXV60, // V6_hi = 562
12094 CEFBS_UseHVXV60, // V6_ld0 = 563
12095 CEFBS_UseHVXV62, // V6_ldcnp0 = 564
12096 CEFBS_UseHVXV62, // V6_ldcnpnt0 = 565
12097 CEFBS_UseHVXV62, // V6_ldcp0 = 566
12098 CEFBS_UseHVXV62, // V6_ldcpnt0 = 567
12099 CEFBS_UseHVXV62, // V6_ldnp0 = 568
12100 CEFBS_UseHVXV62, // V6_ldnpnt0 = 569
12101 CEFBS_UseHVXV60, // V6_ldnt0 = 570
12102 CEFBS_UseHVXV62, // V6_ldp0 = 571
12103 CEFBS_UseHVXV62, // V6_ldpnt0 = 572
12104 CEFBS_UseHVXV62, // V6_ldtnp0 = 573
12105 CEFBS_UseHVXV62, // V6_ldtnpnt0 = 574
12106 CEFBS_UseHVXV62, // V6_ldtp0 = 575
12107 CEFBS_UseHVXV62, // V6_ldtpnt0 = 576
12108 CEFBS_UseHVXV60, // V6_ldu0 = 577
12109 CEFBS_UseHVXV60, // V6_lo = 578
12110 CEFBS_UseHVXV60, // V6_st0 = 579
12111 CEFBS_UseHVXV60, // V6_stn0 = 580
12112 CEFBS_UseHVXV60, // V6_stnnt0 = 581
12113 CEFBS_UseHVXV60, // V6_stnp0 = 582
12114 CEFBS_UseHVXV60, // V6_stnpnt0 = 583
12115 CEFBS_UseHVXV60, // V6_stnq0 = 584
12116 CEFBS_UseHVXV60, // V6_stnqnt0 = 585
12117 CEFBS_UseHVXV60, // V6_stnt0 = 586
12118 CEFBS_UseHVXV60, // V6_stp0 = 587
12119 CEFBS_UseHVXV60, // V6_stpnt0 = 588
12120 CEFBS_UseHVXV60, // V6_stq0 = 589
12121 CEFBS_UseHVXV60, // V6_stqnt0 = 590
12122 CEFBS_UseHVXV60, // V6_stu0 = 591
12123 CEFBS_UseHVXV60, // V6_stunp0 = 592
12124 CEFBS_UseHVXV60, // V6_stup0 = 593
12125 CEFBS_UseHVXV69, // V6_v10mpyubs10 = 594
12126 CEFBS_UseHVXV69, // V6_v10mpyubs10_vxx = 595
12127 CEFBS_UseHVXV68, // V6_v6mpyhubs10_alt = 596
12128 CEFBS_UseHVXV68, // V6_v6mpyvubs10_alt = 597
12129 CEFBS_UseHVXV65, // V6_vabsb_alt = 598
12130 CEFBS_UseHVXV65, // V6_vabsb_sat_alt = 599
12131 CEFBS_UseHVXV60, // V6_vabsdiffh_alt = 600
12132 CEFBS_UseHVXV60, // V6_vabsdiffub_alt = 601
12133 CEFBS_UseHVXV60, // V6_vabsdiffuh_alt = 602
12134 CEFBS_UseHVXV60, // V6_vabsdiffw_alt = 603
12135 CEFBS_UseHVXV60, // V6_vabsh_alt = 604
12136 CEFBS_UseHVXV60, // V6_vabsh_sat_alt = 605
12137 CEFBS_UseHVXV65, // V6_vabsub_alt = 606
12138 CEFBS_UseHVXV65, // V6_vabsuh_alt = 607
12139 CEFBS_UseHVXV65, // V6_vabsuw_alt = 608
12140 CEFBS_UseHVXV60, // V6_vabsw_alt = 609
12141 CEFBS_UseHVXV60, // V6_vabsw_sat_alt = 610
12142 CEFBS_UseHVXV60, // V6_vaddb_alt = 611
12143 CEFBS_UseHVXV60, // V6_vaddb_dv_alt = 612
12144 CEFBS_UseHVXV60, // V6_vaddbnq_alt = 613
12145 CEFBS_UseHVXV60, // V6_vaddbq_alt = 614
12146 CEFBS_UseHVXV62, // V6_vaddbsat_alt = 615
12147 CEFBS_UseHVXV62, // V6_vaddbsat_dv_alt = 616
12148 CEFBS_UseHVXV60, // V6_vaddh_alt = 617
12149 CEFBS_UseHVXV60, // V6_vaddh_dv_alt = 618
12150 CEFBS_UseHVXV60, // V6_vaddhnq_alt = 619
12151 CEFBS_UseHVXV60, // V6_vaddhq_alt = 620
12152 CEFBS_UseHVXV60, // V6_vaddhsat_alt = 621
12153 CEFBS_UseHVXV60, // V6_vaddhsat_dv_alt = 622
12154 CEFBS_UseHVXV62, // V6_vaddhw_acc_alt = 623
12155 CEFBS_UseHVXV60, // V6_vaddhw_alt = 624
12156 CEFBS_UseHVXV62, // V6_vaddubh_acc_alt = 625
12157 CEFBS_UseHVXV60, // V6_vaddubh_alt = 626
12158 CEFBS_UseHVXV60, // V6_vaddubsat_alt = 627
12159 CEFBS_UseHVXV60, // V6_vaddubsat_dv_alt = 628
12160 CEFBS_UseHVXV60, // V6_vadduhsat_alt = 629
12161 CEFBS_UseHVXV60, // V6_vadduhsat_dv_alt = 630
12162 CEFBS_UseHVXV62, // V6_vadduhw_acc_alt = 631
12163 CEFBS_UseHVXV60, // V6_vadduhw_alt = 632
12164 CEFBS_UseHVXV62, // V6_vadduwsat_alt = 633
12165 CEFBS_UseHVXV62, // V6_vadduwsat_dv_alt = 634
12166 CEFBS_UseHVXV60, // V6_vaddw_alt = 635
12167 CEFBS_UseHVXV60, // V6_vaddw_dv_alt = 636
12168 CEFBS_UseHVXV60, // V6_vaddwnq_alt = 637
12169 CEFBS_UseHVXV60, // V6_vaddwq_alt = 638
12170 CEFBS_UseHVXV60, // V6_vaddwsat_alt = 639
12171 CEFBS_UseHVXV60, // V6_vaddwsat_dv_alt = 640
12172 CEFBS_UseHVXV62, // V6_vandnqrt_acc_alt = 641
12173 CEFBS_UseHVXV62, // V6_vandnqrt_alt = 642
12174 CEFBS_UseHVXV60, // V6_vandqrt_acc_alt = 643
12175 CEFBS_UseHVXV60, // V6_vandqrt_alt = 644
12176 CEFBS_UseHVXV60, // V6_vandvrt_acc_alt = 645
12177 CEFBS_UseHVXV60, // V6_vandvrt_alt = 646
12178 CEFBS_UseHVXV65, // V6_vaslh_acc_alt = 647
12179 CEFBS_UseHVXV60, // V6_vaslh_alt = 648
12180 CEFBS_UseHVXV60, // V6_vaslhv_alt = 649
12181 CEFBS_UseHVXV60, // V6_vaslw_acc_alt = 650
12182 CEFBS_UseHVXV60, // V6_vaslw_alt = 651
12183 CEFBS_UseHVXV60, // V6_vaslwv_alt = 652
12184 CEFBS_UseHVXV66, // V6_vasr_into_alt = 653
12185 CEFBS_UseHVXV65, // V6_vasrh_acc_alt = 654
12186 CEFBS_UseHVXV60, // V6_vasrh_alt = 655
12187 CEFBS_UseHVXV60, // V6_vasrhv_alt = 656
12188 CEFBS_UseHVXV60, // V6_vasrw_acc_alt = 657
12189 CEFBS_UseHVXV60, // V6_vasrw_alt = 658
12190 CEFBS_UseHVXV60, // V6_vasrwv_alt = 659
12191 CEFBS_UseHVXV60, // V6_vassignp = 660
12192 CEFBS_UseHVXV65, // V6_vavgb_alt = 661
12193 CEFBS_UseHVXV65, // V6_vavgbrnd_alt = 662
12194 CEFBS_UseHVXV60, // V6_vavgh_alt = 663
12195 CEFBS_UseHVXV60, // V6_vavghrnd_alt = 664
12196 CEFBS_UseHVXV60, // V6_vavgub_alt = 665
12197 CEFBS_UseHVXV60, // V6_vavgubrnd_alt = 666
12198 CEFBS_UseHVXV60, // V6_vavguh_alt = 667
12199 CEFBS_UseHVXV60, // V6_vavguhrnd_alt = 668
12200 CEFBS_UseHVXV65, // V6_vavguw_alt = 669
12201 CEFBS_UseHVXV65, // V6_vavguwrnd_alt = 670
12202 CEFBS_UseHVXV60, // V6_vavgw_alt = 671
12203 CEFBS_UseHVXV60, // V6_vavgwrnd_alt = 672
12204 CEFBS_UseHVXV60, // V6_vcl0h_alt = 673
12205 CEFBS_UseHVXV60, // V6_vcl0w_alt = 674
12206 CEFBS_UseHVXV60, // V6_vd0 = 675
12207 CEFBS_UseHVXV65, // V6_vdd0 = 676
12208 CEFBS_UseHVXV60, // V6_vdealb4w_alt = 677
12209 CEFBS_UseHVXV60, // V6_vdealb_alt = 678
12210 CEFBS_UseHVXV60, // V6_vdealh_alt = 679
12211 CEFBS_UseHVXV60, // V6_vdmpybus_acc_alt = 680
12212 CEFBS_UseHVXV60, // V6_vdmpybus_alt = 681
12213 CEFBS_UseHVXV60, // V6_vdmpybus_dv_acc_alt = 682
12214 CEFBS_UseHVXV60, // V6_vdmpybus_dv_alt = 683
12215 CEFBS_UseHVXV60, // V6_vdmpyhb_acc_alt = 684
12216 CEFBS_UseHVXV60, // V6_vdmpyhb_alt = 685
12217 CEFBS_UseHVXV60, // V6_vdmpyhb_dv_acc_alt = 686
12218 CEFBS_UseHVXV60, // V6_vdmpyhb_dv_alt = 687
12219 CEFBS_UseHVXV60, // V6_vdmpyhisat_acc_alt = 688
12220 CEFBS_UseHVXV60, // V6_vdmpyhisat_alt = 689
12221 CEFBS_UseHVXV60, // V6_vdmpyhsat_acc_alt = 690
12222 CEFBS_UseHVXV60, // V6_vdmpyhsat_alt = 691
12223 CEFBS_UseHVXV60, // V6_vdmpyhsuisat_acc_alt = 692
12224 CEFBS_UseHVXV60, // V6_vdmpyhsuisat_alt = 693
12225 CEFBS_UseHVXV60, // V6_vdmpyhsusat_acc_alt = 694
12226 CEFBS_UseHVXV60, // V6_vdmpyhsusat_alt = 695
12227 CEFBS_UseHVXV60, // V6_vdmpyhvsat_acc_alt = 696
12228 CEFBS_UseHVXV60, // V6_vdmpyhvsat_alt = 697
12229 CEFBS_UseHVXV60, // V6_vdsaduh_acc_alt = 698
12230 CEFBS_UseHVXV60, // V6_vdsaduh_alt = 699
12231 CEFBS_None, // V6_vgathermh_pseudo = 700
12232 CEFBS_None, // V6_vgathermhq_pseudo = 701
12233 CEFBS_None, // V6_vgathermhw_pseudo = 702
12234 CEFBS_None, // V6_vgathermhwq_pseudo = 703
12235 CEFBS_None, // V6_vgathermw_pseudo = 704
12236 CEFBS_None, // V6_vgathermwq_pseudo = 705
12237 CEFBS_UseHVXV60, // V6_vlsrh_alt = 706
12238 CEFBS_UseHVXV60, // V6_vlsrhv_alt = 707
12239 CEFBS_UseHVXV60, // V6_vlsrw_alt = 708
12240 CEFBS_UseHVXV60, // V6_vlsrwv_alt = 709
12241 CEFBS_UseHVXV62, // V6_vmaxb_alt = 710
12242 CEFBS_UseHVXV60, // V6_vmaxh_alt = 711
12243 CEFBS_UseHVXV60, // V6_vmaxub_alt = 712
12244 CEFBS_UseHVXV60, // V6_vmaxuh_alt = 713
12245 CEFBS_UseHVXV60, // V6_vmaxw_alt = 714
12246 CEFBS_UseHVXV62, // V6_vminb_alt = 715
12247 CEFBS_UseHVXV60, // V6_vminh_alt = 716
12248 CEFBS_UseHVXV60, // V6_vminub_alt = 717
12249 CEFBS_UseHVXV60, // V6_vminuh_alt = 718
12250 CEFBS_UseHVXV60, // V6_vminw_alt = 719
12251 CEFBS_UseHVXV60, // V6_vmpabus_acc_alt = 720
12252 CEFBS_UseHVXV60, // V6_vmpabus_alt = 721
12253 CEFBS_UseHVXV60, // V6_vmpabusv_alt = 722
12254 CEFBS_UseHVXV65, // V6_vmpabuu_acc_alt = 723
12255 CEFBS_UseHVXV65, // V6_vmpabuu_alt = 724
12256 CEFBS_UseHVXV60, // V6_vmpabuuv_alt = 725
12257 CEFBS_UseHVXV60, // V6_vmpahb_acc_alt = 726
12258 CEFBS_UseHVXV60, // V6_vmpahb_alt = 727
12259 CEFBS_UseHVXV62, // V6_vmpauhb_acc_alt = 728
12260 CEFBS_UseHVXV62, // V6_vmpauhb_alt = 729
12261 CEFBS_UseHVXV60, // V6_vmpybus_acc_alt = 730
12262 CEFBS_UseHVXV60, // V6_vmpybus_alt = 731
12263 CEFBS_UseHVXV60, // V6_vmpybusv_acc_alt = 732
12264 CEFBS_UseHVXV60, // V6_vmpybusv_alt = 733
12265 CEFBS_UseHVXV60, // V6_vmpybv_acc_alt = 734
12266 CEFBS_UseHVXV60, // V6_vmpybv_alt = 735
12267 CEFBS_UseHVXV60, // V6_vmpyewuh_alt = 736
12268 CEFBS_UseHVXV65, // V6_vmpyh_acc_alt = 737
12269 CEFBS_UseHVXV60, // V6_vmpyh_alt = 738
12270 CEFBS_UseHVXV60, // V6_vmpyhsat_acc_alt = 739
12271 CEFBS_UseHVXV60, // V6_vmpyhsrs_alt = 740
12272 CEFBS_UseHVXV60, // V6_vmpyhss_alt = 741
12273 CEFBS_UseHVXV60, // V6_vmpyhus_acc_alt = 742
12274 CEFBS_UseHVXV60, // V6_vmpyhus_alt = 743
12275 CEFBS_UseHVXV60, // V6_vmpyhv_acc_alt = 744
12276 CEFBS_UseHVXV60, // V6_vmpyhv_alt = 745
12277 CEFBS_UseHVXV60, // V6_vmpyhvsrs_alt = 746
12278 CEFBS_UseHVXV60, // V6_vmpyiewh_acc_alt = 747
12279 CEFBS_UseHVXV60, // V6_vmpyiewuh_acc_alt = 748
12280 CEFBS_UseHVXV60, // V6_vmpyiewuh_alt = 749
12281 CEFBS_UseHVXV60, // V6_vmpyih_acc_alt = 750
12282 CEFBS_UseHVXV60, // V6_vmpyih_alt = 751
12283 CEFBS_UseHVXV60, // V6_vmpyihb_acc_alt = 752
12284 CEFBS_UseHVXV60, // V6_vmpyihb_alt = 753
12285 CEFBS_UseHVXV60, // V6_vmpyiowh_alt = 754
12286 CEFBS_UseHVXV60, // V6_vmpyiwb_acc_alt = 755
12287 CEFBS_UseHVXV60, // V6_vmpyiwb_alt = 756
12288 CEFBS_UseHVXV60, // V6_vmpyiwh_acc_alt = 757
12289 CEFBS_UseHVXV60, // V6_vmpyiwh_alt = 758
12290 CEFBS_UseHVXV62, // V6_vmpyiwub_acc_alt = 759
12291 CEFBS_UseHVXV62, // V6_vmpyiwub_alt = 760
12292 CEFBS_UseHVXV60, // V6_vmpyowh_alt = 761
12293 CEFBS_UseHVXV60, // V6_vmpyowh_rnd_alt = 762
12294 CEFBS_UseHVXV60, // V6_vmpyowh_rnd_sacc_alt = 763
12295 CEFBS_UseHVXV60, // V6_vmpyowh_sacc_alt = 764
12296 CEFBS_UseHVXV60, // V6_vmpyub_acc_alt = 765
12297 CEFBS_UseHVXV60, // V6_vmpyub_alt = 766
12298 CEFBS_UseHVXV60, // V6_vmpyubv_acc_alt = 767
12299 CEFBS_UseHVXV60, // V6_vmpyubv_alt = 768
12300 CEFBS_UseHVXV60, // V6_vmpyuh_acc_alt = 769
12301 CEFBS_UseHVXV60, // V6_vmpyuh_alt = 770
12302 CEFBS_UseHVXV60, // V6_vmpyuhv_acc_alt = 771
12303 CEFBS_UseHVXV60, // V6_vmpyuhv_alt = 772
12304 CEFBS_UseHVXV65, // V6_vnavgb_alt = 773
12305 CEFBS_UseHVXV60, // V6_vnavgh_alt = 774
12306 CEFBS_UseHVXV60, // V6_vnavgub_alt = 775
12307 CEFBS_UseHVXV60, // V6_vnavgw_alt = 776
12308 CEFBS_UseHVXV60, // V6_vnormamth_alt = 777
12309 CEFBS_UseHVXV60, // V6_vnormamtw_alt = 778
12310 CEFBS_UseHVXV60, // V6_vpackeb_alt = 779
12311 CEFBS_UseHVXV60, // V6_vpackeh_alt = 780
12312 CEFBS_UseHVXV60, // V6_vpackhb_sat_alt = 781
12313 CEFBS_UseHVXV60, // V6_vpackhub_sat_alt = 782
12314 CEFBS_UseHVXV60, // V6_vpackob_alt = 783
12315 CEFBS_UseHVXV60, // V6_vpackoh_alt = 784
12316 CEFBS_UseHVXV60, // V6_vpackwh_sat_alt = 785
12317 CEFBS_UseHVXV60, // V6_vpackwuh_sat_alt = 786
12318 CEFBS_UseHVXV60, // V6_vpopcounth_alt = 787
12319 CEFBS_UseHVXV65, // V6_vrmpybub_rtt_acc_alt = 788
12320 CEFBS_UseHVXV65, // V6_vrmpybub_rtt_alt = 789
12321 CEFBS_UseHVXV60, // V6_vrmpybus_acc_alt = 790
12322 CEFBS_UseHVXV60, // V6_vrmpybus_alt = 791
12323 CEFBS_UseHVXV60, // V6_vrmpybusi_acc_alt = 792
12324 CEFBS_UseHVXV60, // V6_vrmpybusi_alt = 793
12325 CEFBS_UseHVXV60, // V6_vrmpybusv_acc_alt = 794
12326 CEFBS_UseHVXV60, // V6_vrmpybusv_alt = 795
12327 CEFBS_UseHVXV60, // V6_vrmpybv_acc_alt = 796
12328 CEFBS_UseHVXV60, // V6_vrmpybv_alt = 797
12329 CEFBS_UseHVXV60, // V6_vrmpyub_acc_alt = 798
12330 CEFBS_UseHVXV60, // V6_vrmpyub_alt = 799
12331 CEFBS_UseHVXV65, // V6_vrmpyub_rtt_acc_alt = 800
12332 CEFBS_UseHVXV65, // V6_vrmpyub_rtt_alt = 801
12333 CEFBS_UseHVXV60, // V6_vrmpyubi_acc_alt = 802
12334 CEFBS_UseHVXV60, // V6_vrmpyubi_alt = 803
12335 CEFBS_UseHVXV60, // V6_vrmpyubv_acc_alt = 804
12336 CEFBS_UseHVXV60, // V6_vrmpyubv_alt = 805
12337 CEFBS_UseHVXV66, // V6_vrotr_alt = 806
12338 CEFBS_UseHVXV60, // V6_vroundhb_alt = 807
12339 CEFBS_UseHVXV60, // V6_vroundhub_alt = 808
12340 CEFBS_UseHVXV62, // V6_vrounduhub_alt = 809
12341 CEFBS_UseHVXV62, // V6_vrounduwuh_alt = 810
12342 CEFBS_UseHVXV60, // V6_vroundwh_alt = 811
12343 CEFBS_UseHVXV60, // V6_vroundwuh_alt = 812
12344 CEFBS_UseHVXV60, // V6_vrsadubi_acc_alt = 813
12345 CEFBS_UseHVXV60, // V6_vrsadubi_alt = 814
12346 CEFBS_UseHVXV60, // V6_vsathub_alt = 815
12347 CEFBS_UseHVXV62, // V6_vsatuwuh_alt = 816
12348 CEFBS_UseHVXV60, // V6_vsatwh_alt = 817
12349 CEFBS_UseHVXV60, // V6_vsb_alt = 818
12350 CEFBS_UseHVXV65, // V6_vscattermh_add_alt = 819
12351 CEFBS_UseHVXV65, // V6_vscattermh_alt = 820
12352 CEFBS_UseHVXV65, // V6_vscattermhq_alt = 821
12353 CEFBS_UseHVXV65, // V6_vscattermw_add_alt = 822
12354 CEFBS_UseHVXV65, // V6_vscattermw_alt = 823
12355 CEFBS_UseHVXV65, // V6_vscattermwh_add_alt = 824
12356 CEFBS_UseHVXV65, // V6_vscattermwh_alt = 825
12357 CEFBS_UseHVXV65, // V6_vscattermwhq_alt = 826
12358 CEFBS_UseHVXV65, // V6_vscattermwq_alt = 827
12359 CEFBS_UseHVXV60, // V6_vsh_alt = 828
12360 CEFBS_UseHVXV60, // V6_vshufeh_alt = 829
12361 CEFBS_UseHVXV60, // V6_vshuffb_alt = 830
12362 CEFBS_UseHVXV60, // V6_vshuffeb_alt = 831
12363 CEFBS_UseHVXV60, // V6_vshuffh_alt = 832
12364 CEFBS_UseHVXV60, // V6_vshuffob_alt = 833
12365 CEFBS_UseHVXV60, // V6_vshufoeb_alt = 834
12366 CEFBS_UseHVXV60, // V6_vshufoeh_alt = 835
12367 CEFBS_UseHVXV60, // V6_vshufoh_alt = 836
12368 CEFBS_UseHVXV60, // V6_vsubb_alt = 837
12369 CEFBS_UseHVXV60, // V6_vsubb_dv_alt = 838
12370 CEFBS_UseHVXV60, // V6_vsubbnq_alt = 839
12371 CEFBS_UseHVXV60, // V6_vsubbq_alt = 840
12372 CEFBS_UseHVXV62, // V6_vsubbsat_alt = 841
12373 CEFBS_UseHVXV62, // V6_vsubbsat_dv_alt = 842
12374 CEFBS_UseHVXV60, // V6_vsubh_alt = 843
12375 CEFBS_UseHVXV60, // V6_vsubh_dv_alt = 844
12376 CEFBS_UseHVXV60, // V6_vsubhnq_alt = 845
12377 CEFBS_UseHVXV60, // V6_vsubhq_alt = 846
12378 CEFBS_UseHVXV60, // V6_vsubhsat_alt = 847
12379 CEFBS_UseHVXV60, // V6_vsubhsat_dv_alt = 848
12380 CEFBS_UseHVXV60, // V6_vsubhw_alt = 849
12381 CEFBS_UseHVXV60, // V6_vsububh_alt = 850
12382 CEFBS_UseHVXV60, // V6_vsububsat_alt = 851
12383 CEFBS_UseHVXV60, // V6_vsububsat_dv_alt = 852
12384 CEFBS_UseHVXV60, // V6_vsubuhsat_alt = 853
12385 CEFBS_UseHVXV60, // V6_vsubuhsat_dv_alt = 854
12386 CEFBS_UseHVXV60, // V6_vsubuhw_alt = 855
12387 CEFBS_UseHVXV62, // V6_vsubuwsat_alt = 856
12388 CEFBS_UseHVXV62, // V6_vsubuwsat_dv_alt = 857
12389 CEFBS_UseHVXV60, // V6_vsubw_alt = 858
12390 CEFBS_UseHVXV60, // V6_vsubw_dv_alt = 859
12391 CEFBS_UseHVXV60, // V6_vsubwnq_alt = 860
12392 CEFBS_UseHVXV60, // V6_vsubwq_alt = 861
12393 CEFBS_UseHVXV60, // V6_vsubwsat_alt = 862
12394 CEFBS_UseHVXV60, // V6_vsubwsat_dv_alt = 863
12395 CEFBS_UseHVXV60, // V6_vtmpyb_acc_alt = 864
12396 CEFBS_UseHVXV60, // V6_vtmpyb_alt = 865
12397 CEFBS_UseHVXV60, // V6_vtmpybus_acc_alt = 866
12398 CEFBS_UseHVXV60, // V6_vtmpybus_alt = 867
12399 CEFBS_UseHVXV60, // V6_vtmpyhb_acc_alt = 868
12400 CEFBS_UseHVXV60, // V6_vtmpyhb_alt = 869
12401 CEFBS_UseHVXV60, // V6_vtran2x2_map = 870
12402 CEFBS_UseHVXV60, // V6_vunpackb_alt = 871
12403 CEFBS_UseHVXV60, // V6_vunpackh_alt = 872
12404 CEFBS_UseHVXV60, // V6_vunpackob_alt = 873
12405 CEFBS_UseHVXV60, // V6_vunpackoh_alt = 874
12406 CEFBS_UseHVXV60, // V6_vunpackub_alt = 875
12407 CEFBS_UseHVXV60, // V6_vunpackuh_alt = 876
12408 CEFBS_UseHVXV60, // V6_vzb_alt = 877
12409 CEFBS_UseHVXV60, // V6_vzh_alt = 878
12410 CEFBS_UseHVXV66, // V6_zld0 = 879
12411 CEFBS_UseHVXV66, // V6_zldp0 = 880
12412 CEFBS_None, // Y2_crswap_old = 881
12413 CEFBS_None, // Y2_dcfetch = 882
12414 CEFBS_HasV65, // Y2_k1lock_map = 883
12415 CEFBS_HasV65, // Y2_k1unlock_map = 884
12416 CEFBS_HasV73, // dup_A2_add = 885
12417 CEFBS_HasV73, // dup_A2_addi = 886
12418 CEFBS_HasV73, // dup_A2_andir = 887
12419 CEFBS_HasV73, // dup_A2_combineii = 888
12420 CEFBS_HasV73, // dup_A2_sxtb = 889
12421 CEFBS_HasV73, // dup_A2_sxth = 890
12422 CEFBS_HasV73, // dup_A2_tfr = 891
12423 CEFBS_HasV73, // dup_A2_tfrsi = 892
12424 CEFBS_HasV73, // dup_A2_zxtb = 893
12425 CEFBS_HasV73, // dup_A2_zxth = 894
12426 CEFBS_HasV73, // dup_A4_combineii = 895
12427 CEFBS_HasV73, // dup_A4_combineir = 896
12428 CEFBS_HasV73, // dup_A4_combineri = 897
12429 CEFBS_HasV73, // dup_C2_cmoveif = 898
12430 CEFBS_HasV73, // dup_C2_cmoveit = 899
12431 CEFBS_HasV73, // dup_C2_cmovenewif = 900
12432 CEFBS_HasV73, // dup_C2_cmovenewit = 901
12433 CEFBS_HasV73, // dup_C2_cmpeqi = 902
12434 CEFBS_HasV73, // dup_L2_deallocframe = 903
12435 CEFBS_HasV73, // dup_L2_loadrb_io = 904
12436 CEFBS_HasV73, // dup_L2_loadrd_io = 905
12437 CEFBS_HasV73, // dup_L2_loadrh_io = 906
12438 CEFBS_HasV73, // dup_L2_loadri_io = 907
12439 CEFBS_HasV73, // dup_L2_loadrub_io = 908
12440 CEFBS_HasV73, // dup_L2_loadruh_io = 909
12441 CEFBS_HasV73, // dup_S2_allocframe = 910
12442 CEFBS_HasV73, // dup_S2_storerb_io = 911
12443 CEFBS_HasV73, // dup_S2_storerd_io = 912
12444 CEFBS_HasV73, // dup_S2_storerh_io = 913
12445 CEFBS_HasV73, // dup_S2_storeri_io = 914
12446 CEFBS_HasV73, // dup_S4_storeirb_io = 915
12447 CEFBS_HasV73, // dup_S4_storeiri_io = 916
12448 CEFBS_None, // A2_abs = 917
12449 CEFBS_None, // A2_absp = 918
12450 CEFBS_None, // A2_abssat = 919
12451 CEFBS_None, // A2_add = 920
12452 CEFBS_None, // A2_addh_h16_hh = 921
12453 CEFBS_None, // A2_addh_h16_hl = 922
12454 CEFBS_None, // A2_addh_h16_lh = 923
12455 CEFBS_None, // A2_addh_h16_ll = 924
12456 CEFBS_None, // A2_addh_h16_sat_hh = 925
12457 CEFBS_None, // A2_addh_h16_sat_hl = 926
12458 CEFBS_None, // A2_addh_h16_sat_lh = 927
12459 CEFBS_None, // A2_addh_h16_sat_ll = 928
12460 CEFBS_None, // A2_addh_l16_hl = 929
12461 CEFBS_None, // A2_addh_l16_ll = 930
12462 CEFBS_None, // A2_addh_l16_sat_hl = 931
12463 CEFBS_None, // A2_addh_l16_sat_ll = 932
12464 CEFBS_None, // A2_addi = 933
12465 CEFBS_None, // A2_addp = 934
12466 CEFBS_None, // A2_addpsat = 935
12467 CEFBS_None, // A2_addsat = 936
12468 CEFBS_None, // A2_addsph = 937
12469 CEFBS_None, // A2_addspl = 938
12470 CEFBS_None, // A2_and = 939
12471 CEFBS_None, // A2_andir = 940
12472 CEFBS_None, // A2_andp = 941
12473 CEFBS_None, // A2_aslh = 942
12474 CEFBS_None, // A2_asrh = 943
12475 CEFBS_None, // A2_combine_hh = 944
12476 CEFBS_None, // A2_combine_hl = 945
12477 CEFBS_None, // A2_combine_lh = 946
12478 CEFBS_None, // A2_combine_ll = 947
12479 CEFBS_None, // A2_combineii = 948
12480 CEFBS_None, // A2_combinew = 949
12481 CEFBS_None, // A2_max = 950
12482 CEFBS_None, // A2_maxp = 951
12483 CEFBS_None, // A2_maxu = 952
12484 CEFBS_None, // A2_maxup = 953
12485 CEFBS_None, // A2_min = 954
12486 CEFBS_None, // A2_minp = 955
12487 CEFBS_None, // A2_minu = 956
12488 CEFBS_None, // A2_minup = 957
12489 CEFBS_None, // A2_negp = 958
12490 CEFBS_None, // A2_negsat = 959
12491 CEFBS_None, // A2_nop = 960
12492 CEFBS_None, // A2_notp = 961
12493 CEFBS_None, // A2_or = 962
12494 CEFBS_None, // A2_orir = 963
12495 CEFBS_None, // A2_orp = 964
12496 CEFBS_None, // A2_paddf = 965
12497 CEFBS_None, // A2_paddfnew = 966
12498 CEFBS_None, // A2_paddif = 967
12499 CEFBS_None, // A2_paddifnew = 968
12500 CEFBS_None, // A2_paddit = 969
12501 CEFBS_None, // A2_padditnew = 970
12502 CEFBS_None, // A2_paddt = 971
12503 CEFBS_None, // A2_paddtnew = 972
12504 CEFBS_None, // A2_pandf = 973
12505 CEFBS_None, // A2_pandfnew = 974
12506 CEFBS_None, // A2_pandt = 975
12507 CEFBS_None, // A2_pandtnew = 976
12508 CEFBS_None, // A2_porf = 977
12509 CEFBS_None, // A2_porfnew = 978
12510 CEFBS_None, // A2_port = 979
12511 CEFBS_None, // A2_portnew = 980
12512 CEFBS_None, // A2_psubf = 981
12513 CEFBS_None, // A2_psubfnew = 982
12514 CEFBS_None, // A2_psubt = 983
12515 CEFBS_None, // A2_psubtnew = 984
12516 CEFBS_None, // A2_pxorf = 985
12517 CEFBS_None, // A2_pxorfnew = 986
12518 CEFBS_None, // A2_pxort = 987
12519 CEFBS_None, // A2_pxortnew = 988
12520 CEFBS_None, // A2_roundsat = 989
12521 CEFBS_None, // A2_sat = 990
12522 CEFBS_None, // A2_satb = 991
12523 CEFBS_None, // A2_sath = 992
12524 CEFBS_None, // A2_satub = 993
12525 CEFBS_None, // A2_satuh = 994
12526 CEFBS_None, // A2_sub = 995
12527 CEFBS_None, // A2_subh_h16_hh = 996
12528 CEFBS_None, // A2_subh_h16_hl = 997
12529 CEFBS_None, // A2_subh_h16_lh = 998
12530 CEFBS_None, // A2_subh_h16_ll = 999
12531 CEFBS_None, // A2_subh_h16_sat_hh = 1000
12532 CEFBS_None, // A2_subh_h16_sat_hl = 1001
12533 CEFBS_None, // A2_subh_h16_sat_lh = 1002
12534 CEFBS_None, // A2_subh_h16_sat_ll = 1003
12535 CEFBS_None, // A2_subh_l16_hl = 1004
12536 CEFBS_None, // A2_subh_l16_ll = 1005
12537 CEFBS_None, // A2_subh_l16_sat_hl = 1006
12538 CEFBS_None, // A2_subh_l16_sat_ll = 1007
12539 CEFBS_None, // A2_subp = 1008
12540 CEFBS_None, // A2_subri = 1009
12541 CEFBS_None, // A2_subsat = 1010
12542 CEFBS_None, // A2_svaddh = 1011
12543 CEFBS_None, // A2_svaddhs = 1012
12544 CEFBS_None, // A2_svadduhs = 1013
12545 CEFBS_None, // A2_svavgh = 1014
12546 CEFBS_None, // A2_svavghs = 1015
12547 CEFBS_None, // A2_svnavgh = 1016
12548 CEFBS_None, // A2_svsubh = 1017
12549 CEFBS_None, // A2_svsubhs = 1018
12550 CEFBS_None, // A2_svsubuhs = 1019
12551 CEFBS_None, // A2_swiz = 1020
12552 CEFBS_None, // A2_sxtb = 1021
12553 CEFBS_None, // A2_sxth = 1022
12554 CEFBS_None, // A2_sxtw = 1023
12555 CEFBS_None, // A2_tfr = 1024
12556 CEFBS_None, // A2_tfrcrr = 1025
12557 CEFBS_None, // A2_tfrih = 1026
12558 CEFBS_None, // A2_tfril = 1027
12559 CEFBS_None, // A2_tfrrcr = 1028
12560 CEFBS_None, // A2_tfrsi = 1029
12561 CEFBS_None, // A2_vabsh = 1030
12562 CEFBS_None, // A2_vabshsat = 1031
12563 CEFBS_None, // A2_vabsw = 1032
12564 CEFBS_None, // A2_vabswsat = 1033
12565 CEFBS_None, // A2_vaddh = 1034
12566 CEFBS_None, // A2_vaddhs = 1035
12567 CEFBS_None, // A2_vaddub = 1036
12568 CEFBS_None, // A2_vaddubs = 1037
12569 CEFBS_None, // A2_vadduhs = 1038
12570 CEFBS_None, // A2_vaddw = 1039
12571 CEFBS_None, // A2_vaddws = 1040
12572 CEFBS_None, // A2_vavgh = 1041
12573 CEFBS_None, // A2_vavghcr = 1042
12574 CEFBS_None, // A2_vavghr = 1043
12575 CEFBS_None, // A2_vavgub = 1044
12576 CEFBS_None, // A2_vavgubr = 1045
12577 CEFBS_None, // A2_vavguh = 1046
12578 CEFBS_None, // A2_vavguhr = 1047
12579 CEFBS_None, // A2_vavguw = 1048
12580 CEFBS_None, // A2_vavguwr = 1049
12581 CEFBS_None, // A2_vavgw = 1050
12582 CEFBS_None, // A2_vavgwcr = 1051
12583 CEFBS_None, // A2_vavgwr = 1052
12584 CEFBS_None, // A2_vcmpbeq = 1053
12585 CEFBS_None, // A2_vcmpbgtu = 1054
12586 CEFBS_None, // A2_vcmpheq = 1055
12587 CEFBS_None, // A2_vcmphgt = 1056
12588 CEFBS_None, // A2_vcmphgtu = 1057
12589 CEFBS_None, // A2_vcmpweq = 1058
12590 CEFBS_None, // A2_vcmpwgt = 1059
12591 CEFBS_None, // A2_vcmpwgtu = 1060
12592 CEFBS_None, // A2_vconj = 1061
12593 CEFBS_None, // A2_vmaxb = 1062
12594 CEFBS_None, // A2_vmaxh = 1063
12595 CEFBS_None, // A2_vmaxub = 1064
12596 CEFBS_None, // A2_vmaxuh = 1065
12597 CEFBS_None, // A2_vmaxuw = 1066
12598 CEFBS_None, // A2_vmaxw = 1067
12599 CEFBS_None, // A2_vminb = 1068
12600 CEFBS_None, // A2_vminh = 1069
12601 CEFBS_None, // A2_vminub = 1070
12602 CEFBS_None, // A2_vminuh = 1071
12603 CEFBS_None, // A2_vminuw = 1072
12604 CEFBS_None, // A2_vminw = 1073
12605 CEFBS_None, // A2_vnavgh = 1074
12606 CEFBS_None, // A2_vnavghcr = 1075
12607 CEFBS_None, // A2_vnavghr = 1076
12608 CEFBS_None, // A2_vnavgw = 1077
12609 CEFBS_None, // A2_vnavgwcr = 1078
12610 CEFBS_None, // A2_vnavgwr = 1079
12611 CEFBS_None, // A2_vraddub = 1080
12612 CEFBS_None, // A2_vraddub_acc = 1081
12613 CEFBS_None, // A2_vrsadub = 1082
12614 CEFBS_None, // A2_vrsadub_acc = 1083
12615 CEFBS_None, // A2_vsubh = 1084
12616 CEFBS_None, // A2_vsubhs = 1085
12617 CEFBS_None, // A2_vsubub = 1086
12618 CEFBS_None, // A2_vsububs = 1087
12619 CEFBS_None, // A2_vsubuhs = 1088
12620 CEFBS_None, // A2_vsubw = 1089
12621 CEFBS_None, // A2_vsubws = 1090
12622 CEFBS_None, // A2_xor = 1091
12623 CEFBS_None, // A2_xorp = 1092
12624 CEFBS_None, // A2_zxth = 1093
12625 CEFBS_None, // A4_addp_c = 1094
12626 CEFBS_None, // A4_andn = 1095
12627 CEFBS_None, // A4_andnp = 1096
12628 CEFBS_None, // A4_bitsplit = 1097
12629 CEFBS_None, // A4_bitspliti = 1098
12630 CEFBS_None, // A4_boundscheck_hi = 1099
12631 CEFBS_None, // A4_boundscheck_lo = 1100
12632 CEFBS_None, // A4_cmpbeq = 1101
12633 CEFBS_None, // A4_cmpbeqi = 1102
12634 CEFBS_None, // A4_cmpbgt = 1103
12635 CEFBS_None, // A4_cmpbgti = 1104
12636 CEFBS_None, // A4_cmpbgtu = 1105
12637 CEFBS_None, // A4_cmpbgtui = 1106
12638 CEFBS_None, // A4_cmpheq = 1107
12639 CEFBS_None, // A4_cmpheqi = 1108
12640 CEFBS_None, // A4_cmphgt = 1109
12641 CEFBS_None, // A4_cmphgti = 1110
12642 CEFBS_None, // A4_cmphgtu = 1111
12643 CEFBS_None, // A4_cmphgtui = 1112
12644 CEFBS_None, // A4_combineii = 1113
12645 CEFBS_None, // A4_combineir = 1114
12646 CEFBS_None, // A4_combineri = 1115
12647 CEFBS_None, // A4_cround_ri = 1116
12648 CEFBS_None, // A4_cround_rr = 1117
12649 CEFBS_None, // A4_ext = 1118
12650 CEFBS_None, // A4_modwrapu = 1119
12651 CEFBS_None, // A4_orn = 1120
12652 CEFBS_None, // A4_ornp = 1121
12653 CEFBS_None, // A4_paslhf = 1122
12654 CEFBS_None, // A4_paslhfnew = 1123
12655 CEFBS_None, // A4_paslht = 1124
12656 CEFBS_None, // A4_paslhtnew = 1125
12657 CEFBS_None, // A4_pasrhf = 1126
12658 CEFBS_None, // A4_pasrhfnew = 1127
12659 CEFBS_None, // A4_pasrht = 1128
12660 CEFBS_None, // A4_pasrhtnew = 1129
12661 CEFBS_None, // A4_psxtbf = 1130
12662 CEFBS_None, // A4_psxtbfnew = 1131
12663 CEFBS_None, // A4_psxtbt = 1132
12664 CEFBS_None, // A4_psxtbtnew = 1133
12665 CEFBS_None, // A4_psxthf = 1134
12666 CEFBS_None, // A4_psxthfnew = 1135
12667 CEFBS_None, // A4_psxtht = 1136
12668 CEFBS_None, // A4_psxthtnew = 1137
12669 CEFBS_None, // A4_pzxtbf = 1138
12670 CEFBS_None, // A4_pzxtbfnew = 1139
12671 CEFBS_None, // A4_pzxtbt = 1140
12672 CEFBS_None, // A4_pzxtbtnew = 1141
12673 CEFBS_None, // A4_pzxthf = 1142
12674 CEFBS_None, // A4_pzxthfnew = 1143
12675 CEFBS_None, // A4_pzxtht = 1144
12676 CEFBS_None, // A4_pzxthtnew = 1145
12677 CEFBS_None, // A4_rcmpeq = 1146
12678 CEFBS_None, // A4_rcmpeqi = 1147
12679 CEFBS_None, // A4_rcmpneq = 1148
12680 CEFBS_None, // A4_rcmpneqi = 1149
12681 CEFBS_None, // A4_round_ri = 1150
12682 CEFBS_None, // A4_round_ri_sat = 1151
12683 CEFBS_None, // A4_round_rr = 1152
12684 CEFBS_None, // A4_round_rr_sat = 1153
12685 CEFBS_None, // A4_subp_c = 1154
12686 CEFBS_None, // A4_tfrcpp = 1155
12687 CEFBS_None, // A4_tfrpcp = 1156
12688 CEFBS_None, // A4_tlbmatch = 1157
12689 CEFBS_None, // A4_vcmpbeq_any = 1158
12690 CEFBS_None, // A4_vcmpbeqi = 1159
12691 CEFBS_None, // A4_vcmpbgt = 1160
12692 CEFBS_None, // A4_vcmpbgti = 1161
12693 CEFBS_None, // A4_vcmpbgtui = 1162
12694 CEFBS_None, // A4_vcmpheqi = 1163
12695 CEFBS_None, // A4_vcmphgti = 1164
12696 CEFBS_None, // A4_vcmphgtui = 1165
12697 CEFBS_None, // A4_vcmpweqi = 1166
12698 CEFBS_None, // A4_vcmpwgti = 1167
12699 CEFBS_None, // A4_vcmpwgtui = 1168
12700 CEFBS_None, // A4_vrmaxh = 1169
12701 CEFBS_None, // A4_vrmaxuh = 1170
12702 CEFBS_None, // A4_vrmaxuw = 1171
12703 CEFBS_None, // A4_vrmaxw = 1172
12704 CEFBS_None, // A4_vrminh = 1173
12705 CEFBS_None, // A4_vrminuh = 1174
12706 CEFBS_None, // A4_vrminuw = 1175
12707 CEFBS_None, // A4_vrminw = 1176
12708 CEFBS_HasV55, // A5_ACS = 1177
12709 CEFBS_None, // A5_vaddhubs = 1178
12710 CEFBS_HasV65, // A6_vcmpbeq_notany = 1179
12711 CEFBS_HasV62, // A6_vminub_RdP = 1180
12712 CEFBS_HasV67_UseAudio, // A7_clip = 1181
12713 CEFBS_HasV67_UseAudio, // A7_croundd_ri = 1182
12714 CEFBS_HasV67_UseAudio, // A7_croundd_rr = 1183
12715 CEFBS_HasV67_UseAudio, // A7_vclip = 1184
12716 CEFBS_None, // C2_all8 = 1185
12717 CEFBS_None, // C2_and = 1186
12718 CEFBS_None, // C2_andn = 1187
12719 CEFBS_None, // C2_any8 = 1188
12720 CEFBS_None, // C2_bitsclr = 1189
12721 CEFBS_None, // C2_bitsclri = 1190
12722 CEFBS_None, // C2_bitsset = 1191
12723 CEFBS_None, // C2_ccombinewf = 1192
12724 CEFBS_None, // C2_ccombinewnewf = 1193
12725 CEFBS_None, // C2_ccombinewnewt = 1194
12726 CEFBS_None, // C2_ccombinewt = 1195
12727 CEFBS_None, // C2_cmoveif = 1196
12728 CEFBS_None, // C2_cmoveit = 1197
12729 CEFBS_None, // C2_cmovenewif = 1198
12730 CEFBS_None, // C2_cmovenewit = 1199
12731 CEFBS_None, // C2_cmpeq = 1200
12732 CEFBS_None, // C2_cmpeqi = 1201
12733 CEFBS_None, // C2_cmpeqp = 1202
12734 CEFBS_None, // C2_cmpgt = 1203
12735 CEFBS_None, // C2_cmpgti = 1204
12736 CEFBS_None, // C2_cmpgtp = 1205
12737 CEFBS_None, // C2_cmpgtu = 1206
12738 CEFBS_None, // C2_cmpgtui = 1207
12739 CEFBS_None, // C2_cmpgtup = 1208
12740 CEFBS_None, // C2_mask = 1209
12741 CEFBS_None, // C2_mux = 1210
12742 CEFBS_None, // C2_muxii = 1211
12743 CEFBS_None, // C2_muxir = 1212
12744 CEFBS_None, // C2_muxri = 1213
12745 CEFBS_None, // C2_not = 1214
12746 CEFBS_None, // C2_or = 1215
12747 CEFBS_None, // C2_orn = 1216
12748 CEFBS_None, // C2_tfrpr = 1217
12749 CEFBS_None, // C2_tfrrp = 1218
12750 CEFBS_None, // C2_vitpack = 1219
12751 CEFBS_None, // C2_vmux = 1220
12752 CEFBS_None, // C2_xor = 1221
12753 CEFBS_None, // C4_addipc = 1222
12754 CEFBS_None, // C4_and_and = 1223
12755 CEFBS_None, // C4_and_andn = 1224
12756 CEFBS_None, // C4_and_or = 1225
12757 CEFBS_None, // C4_and_orn = 1226
12758 CEFBS_None, // C4_cmplte = 1227
12759 CEFBS_None, // C4_cmpltei = 1228
12760 CEFBS_None, // C4_cmplteu = 1229
12761 CEFBS_None, // C4_cmplteui = 1230
12762 CEFBS_None, // C4_cmpneq = 1231
12763 CEFBS_None, // C4_cmpneqi = 1232
12764 CEFBS_None, // C4_fastcorner9 = 1233
12765 CEFBS_None, // C4_fastcorner9_not = 1234
12766 CEFBS_None, // C4_nbitsclr = 1235
12767 CEFBS_None, // C4_nbitsclri = 1236
12768 CEFBS_None, // C4_nbitsset = 1237
12769 CEFBS_None, // C4_or_and = 1238
12770 CEFBS_None, // C4_or_andn = 1239
12771 CEFBS_None, // C4_or_or = 1240
12772 CEFBS_None, // C4_or_orn = 1241
12773 CEFBS_None, // CALLProfile = 1242
12774 CEFBS_None, // CONST32 = 1243
12775 CEFBS_None, // CONST64 = 1244
12776 CEFBS_None, // DuplexIClass0 = 1245
12777 CEFBS_None, // DuplexIClass1 = 1246
12778 CEFBS_None, // DuplexIClass2 = 1247
12779 CEFBS_None, // DuplexIClass3 = 1248
12780 CEFBS_None, // DuplexIClass4 = 1249
12781 CEFBS_None, // DuplexIClass5 = 1250
12782 CEFBS_None, // DuplexIClass6 = 1251
12783 CEFBS_None, // DuplexIClass7 = 1252
12784 CEFBS_None, // DuplexIClass8 = 1253
12785 CEFBS_None, // DuplexIClass9 = 1254
12786 CEFBS_None, // DuplexIClassA = 1255
12787 CEFBS_None, // DuplexIClassB = 1256
12788 CEFBS_None, // DuplexIClassC = 1257
12789 CEFBS_None, // DuplexIClassD = 1258
12790 CEFBS_None, // DuplexIClassE = 1259
12791 CEFBS_None, // DuplexIClassF = 1260
12792 CEFBS_None, // EH_RETURN_JMPR = 1261
12793 CEFBS_None, // F2_conv_d2df = 1262
12794 CEFBS_None, // F2_conv_d2sf = 1263
12795 CEFBS_None, // F2_conv_df2d = 1264
12796 CEFBS_None, // F2_conv_df2d_chop = 1265
12797 CEFBS_None, // F2_conv_df2sf = 1266
12798 CEFBS_None, // F2_conv_df2ud = 1267
12799 CEFBS_None, // F2_conv_df2ud_chop = 1268
12800 CEFBS_None, // F2_conv_df2uw = 1269
12801 CEFBS_None, // F2_conv_df2uw_chop = 1270
12802 CEFBS_None, // F2_conv_df2w = 1271
12803 CEFBS_None, // F2_conv_df2w_chop = 1272
12804 CEFBS_None, // F2_conv_sf2d = 1273
12805 CEFBS_None, // F2_conv_sf2d_chop = 1274
12806 CEFBS_None, // F2_conv_sf2df = 1275
12807 CEFBS_None, // F2_conv_sf2ud = 1276
12808 CEFBS_None, // F2_conv_sf2ud_chop = 1277
12809 CEFBS_None, // F2_conv_sf2uw = 1278
12810 CEFBS_None, // F2_conv_sf2uw_chop = 1279
12811 CEFBS_None, // F2_conv_sf2w = 1280
12812 CEFBS_None, // F2_conv_sf2w_chop = 1281
12813 CEFBS_None, // F2_conv_ud2df = 1282
12814 CEFBS_None, // F2_conv_ud2sf = 1283
12815 CEFBS_None, // F2_conv_uw2df = 1284
12816 CEFBS_None, // F2_conv_uw2sf = 1285
12817 CEFBS_None, // F2_conv_w2df = 1286
12818 CEFBS_None, // F2_conv_w2sf = 1287
12819 CEFBS_HasV66, // F2_dfadd = 1288
12820 CEFBS_None, // F2_dfclass = 1289
12821 CEFBS_None, // F2_dfcmpeq = 1290
12822 CEFBS_None, // F2_dfcmpge = 1291
12823 CEFBS_None, // F2_dfcmpgt = 1292
12824 CEFBS_None, // F2_dfcmpuo = 1293
12825 CEFBS_None, // F2_dfimm_n = 1294
12826 CEFBS_None, // F2_dfimm_p = 1295
12827 CEFBS_HasV67, // F2_dfmax = 1296
12828 CEFBS_HasV67, // F2_dfmin = 1297
12829 CEFBS_HasV67, // F2_dfmpyfix = 1298
12830 CEFBS_HasV67, // F2_dfmpyhh = 1299
12831 CEFBS_HasV67, // F2_dfmpylh = 1300
12832 CEFBS_HasV67, // F2_dfmpyll = 1301
12833 CEFBS_HasV66, // F2_dfsub = 1302
12834 CEFBS_None, // F2_sfadd = 1303
12835 CEFBS_None, // F2_sfclass = 1304
12836 CEFBS_None, // F2_sfcmpeq = 1305
12837 CEFBS_None, // F2_sfcmpge = 1306
12838 CEFBS_None, // F2_sfcmpgt = 1307
12839 CEFBS_None, // F2_sfcmpuo = 1308
12840 CEFBS_None, // F2_sffixupd = 1309
12841 CEFBS_None, // F2_sffixupn = 1310
12842 CEFBS_None, // F2_sffixupr = 1311
12843 CEFBS_None, // F2_sffma = 1312
12844 CEFBS_None, // F2_sffma_lib = 1313
12845 CEFBS_None, // F2_sffma_sc = 1314
12846 CEFBS_None, // F2_sffms = 1315
12847 CEFBS_None, // F2_sffms_lib = 1316
12848 CEFBS_None, // F2_sfimm_n = 1317
12849 CEFBS_None, // F2_sfimm_p = 1318
12850 CEFBS_None, // F2_sfinvsqrta = 1319
12851 CEFBS_None, // F2_sfmax = 1320
12852 CEFBS_None, // F2_sfmin = 1321
12853 CEFBS_None, // F2_sfmpy = 1322
12854 CEFBS_None, // F2_sfrecipa = 1323
12855 CEFBS_None, // F2_sfsub = 1324
12856 CEFBS_None, // G4_tfrgcpp = 1325
12857 CEFBS_None, // G4_tfrgcrr = 1326
12858 CEFBS_None, // G4_tfrgpcp = 1327
12859 CEFBS_None, // G4_tfrgrcr = 1328
12860 CEFBS_None, // HI = 1329
12861 CEFBS_None, // J2_call = 1330
12862 CEFBS_None, // J2_callf = 1331
12863 CEFBS_None, // J2_callr = 1332
12864 CEFBS_None, // J2_callrf = 1333
12865 CEFBS_HasV73, // J2_callrh = 1334
12866 CEFBS_None, // J2_callrt = 1335
12867 CEFBS_None, // J2_callt = 1336
12868 CEFBS_None, // J2_jump = 1337
12869 CEFBS_None, // J2_jumpf = 1338
12870 CEFBS_None, // J2_jumpfnew = 1339
12871 CEFBS_None, // J2_jumpfnewpt = 1340
12872 CEFBS_HasV60, // J2_jumpfpt = 1341
12873 CEFBS_None, // J2_jumpr = 1342
12874 CEFBS_None, // J2_jumprf = 1343
12875 CEFBS_None, // J2_jumprfnew = 1344
12876 CEFBS_None, // J2_jumprfnewpt = 1345
12877 CEFBS_HasV60, // J2_jumprfpt = 1346
12878 CEFBS_None, // J2_jumprgtez = 1347
12879 CEFBS_None, // J2_jumprgtezpt = 1348
12880 CEFBS_HasV73, // J2_jumprh = 1349
12881 CEFBS_None, // J2_jumprltez = 1350
12882 CEFBS_None, // J2_jumprltezpt = 1351
12883 CEFBS_None, // J2_jumprnz = 1352
12884 CEFBS_None, // J2_jumprnzpt = 1353
12885 CEFBS_None, // J2_jumprt = 1354
12886 CEFBS_None, // J2_jumprtnew = 1355
12887 CEFBS_None, // J2_jumprtnewpt = 1356
12888 CEFBS_HasV60, // J2_jumprtpt = 1357
12889 CEFBS_None, // J2_jumprz = 1358
12890 CEFBS_None, // J2_jumprzpt = 1359
12891 CEFBS_None, // J2_jumpt = 1360
12892 CEFBS_None, // J2_jumptnew = 1361
12893 CEFBS_None, // J2_jumptnewpt = 1362
12894 CEFBS_HasV60, // J2_jumptpt = 1363
12895 CEFBS_None, // J2_loop0i = 1364
12896 CEFBS_None, // J2_loop0iext = 1365
12897 CEFBS_None, // J2_loop0r = 1366
12898 CEFBS_None, // J2_loop0rext = 1367
12899 CEFBS_None, // J2_loop1i = 1368
12900 CEFBS_None, // J2_loop1iext = 1369
12901 CEFBS_None, // J2_loop1r = 1370
12902 CEFBS_None, // J2_loop1rext = 1371
12903 CEFBS_None, // J2_pause = 1372
12904 CEFBS_None, // J2_ploop1si = 1373
12905 CEFBS_None, // J2_ploop1sr = 1374
12906 CEFBS_None, // J2_ploop2si = 1375
12907 CEFBS_None, // J2_ploop2sr = 1376
12908 CEFBS_None, // J2_ploop3si = 1377
12909 CEFBS_None, // J2_ploop3sr = 1378
12910 CEFBS_None, // J2_rte = 1379
12911 CEFBS_None, // J2_trap0 = 1380
12912 CEFBS_HasV65, // J2_trap1 = 1381
12913 CEFBS_HasV73, // J2_unpause = 1382
12914 CEFBS_None, // J4_cmpeq_f_jumpnv_nt = 1383
12915 CEFBS_None, // J4_cmpeq_f_jumpnv_t = 1384
12916 CEFBS_None, // J4_cmpeq_fp0_jump_nt = 1385
12917 CEFBS_None, // J4_cmpeq_fp0_jump_t = 1386
12918 CEFBS_None, // J4_cmpeq_fp1_jump_nt = 1387
12919 CEFBS_None, // J4_cmpeq_fp1_jump_t = 1388
12920 CEFBS_None, // J4_cmpeq_t_jumpnv_nt = 1389
12921 CEFBS_None, // J4_cmpeq_t_jumpnv_t = 1390
12922 CEFBS_None, // J4_cmpeq_tp0_jump_nt = 1391
12923 CEFBS_None, // J4_cmpeq_tp0_jump_t = 1392
12924 CEFBS_None, // J4_cmpeq_tp1_jump_nt = 1393
12925 CEFBS_None, // J4_cmpeq_tp1_jump_t = 1394
12926 CEFBS_None, // J4_cmpeqi_f_jumpnv_nt = 1395
12927 CEFBS_None, // J4_cmpeqi_f_jumpnv_t = 1396
12928 CEFBS_None, // J4_cmpeqi_fp0_jump_nt = 1397
12929 CEFBS_None, // J4_cmpeqi_fp0_jump_t = 1398
12930 CEFBS_None, // J4_cmpeqi_fp1_jump_nt = 1399
12931 CEFBS_None, // J4_cmpeqi_fp1_jump_t = 1400
12932 CEFBS_None, // J4_cmpeqi_t_jumpnv_nt = 1401
12933 CEFBS_None, // J4_cmpeqi_t_jumpnv_t = 1402
12934 CEFBS_None, // J4_cmpeqi_tp0_jump_nt = 1403
12935 CEFBS_None, // J4_cmpeqi_tp0_jump_t = 1404
12936 CEFBS_None, // J4_cmpeqi_tp1_jump_nt = 1405
12937 CEFBS_None, // J4_cmpeqi_tp1_jump_t = 1406
12938 CEFBS_None, // J4_cmpeqn1_f_jumpnv_nt = 1407
12939 CEFBS_None, // J4_cmpeqn1_f_jumpnv_t = 1408
12940 CEFBS_None, // J4_cmpeqn1_fp0_jump_nt = 1409
12941 CEFBS_None, // J4_cmpeqn1_fp0_jump_t = 1410
12942 CEFBS_None, // J4_cmpeqn1_fp1_jump_nt = 1411
12943 CEFBS_None, // J4_cmpeqn1_fp1_jump_t = 1412
12944 CEFBS_None, // J4_cmpeqn1_t_jumpnv_nt = 1413
12945 CEFBS_None, // J4_cmpeqn1_t_jumpnv_t = 1414
12946 CEFBS_None, // J4_cmpeqn1_tp0_jump_nt = 1415
12947 CEFBS_None, // J4_cmpeqn1_tp0_jump_t = 1416
12948 CEFBS_None, // J4_cmpeqn1_tp1_jump_nt = 1417
12949 CEFBS_None, // J4_cmpeqn1_tp1_jump_t = 1418
12950 CEFBS_None, // J4_cmpgt_f_jumpnv_nt = 1419
12951 CEFBS_None, // J4_cmpgt_f_jumpnv_t = 1420
12952 CEFBS_None, // J4_cmpgt_fp0_jump_nt = 1421
12953 CEFBS_None, // J4_cmpgt_fp0_jump_t = 1422
12954 CEFBS_None, // J4_cmpgt_fp1_jump_nt = 1423
12955 CEFBS_None, // J4_cmpgt_fp1_jump_t = 1424
12956 CEFBS_None, // J4_cmpgt_t_jumpnv_nt = 1425
12957 CEFBS_None, // J4_cmpgt_t_jumpnv_t = 1426
12958 CEFBS_None, // J4_cmpgt_tp0_jump_nt = 1427
12959 CEFBS_None, // J4_cmpgt_tp0_jump_t = 1428
12960 CEFBS_None, // J4_cmpgt_tp1_jump_nt = 1429
12961 CEFBS_None, // J4_cmpgt_tp1_jump_t = 1430
12962 CEFBS_None, // J4_cmpgti_f_jumpnv_nt = 1431
12963 CEFBS_None, // J4_cmpgti_f_jumpnv_t = 1432
12964 CEFBS_None, // J4_cmpgti_fp0_jump_nt = 1433
12965 CEFBS_None, // J4_cmpgti_fp0_jump_t = 1434
12966 CEFBS_None, // J4_cmpgti_fp1_jump_nt = 1435
12967 CEFBS_None, // J4_cmpgti_fp1_jump_t = 1436
12968 CEFBS_None, // J4_cmpgti_t_jumpnv_nt = 1437
12969 CEFBS_None, // J4_cmpgti_t_jumpnv_t = 1438
12970 CEFBS_None, // J4_cmpgti_tp0_jump_nt = 1439
12971 CEFBS_None, // J4_cmpgti_tp0_jump_t = 1440
12972 CEFBS_None, // J4_cmpgti_tp1_jump_nt = 1441
12973 CEFBS_None, // J4_cmpgti_tp1_jump_t = 1442
12974 CEFBS_None, // J4_cmpgtn1_f_jumpnv_nt = 1443
12975 CEFBS_None, // J4_cmpgtn1_f_jumpnv_t = 1444
12976 CEFBS_None, // J4_cmpgtn1_fp0_jump_nt = 1445
12977 CEFBS_None, // J4_cmpgtn1_fp0_jump_t = 1446
12978 CEFBS_None, // J4_cmpgtn1_fp1_jump_nt = 1447
12979 CEFBS_None, // J4_cmpgtn1_fp1_jump_t = 1448
12980 CEFBS_None, // J4_cmpgtn1_t_jumpnv_nt = 1449
12981 CEFBS_None, // J4_cmpgtn1_t_jumpnv_t = 1450
12982 CEFBS_None, // J4_cmpgtn1_tp0_jump_nt = 1451
12983 CEFBS_None, // J4_cmpgtn1_tp0_jump_t = 1452
12984 CEFBS_None, // J4_cmpgtn1_tp1_jump_nt = 1453
12985 CEFBS_None, // J4_cmpgtn1_tp1_jump_t = 1454
12986 CEFBS_None, // J4_cmpgtu_f_jumpnv_nt = 1455
12987 CEFBS_None, // J4_cmpgtu_f_jumpnv_t = 1456
12988 CEFBS_None, // J4_cmpgtu_fp0_jump_nt = 1457
12989 CEFBS_None, // J4_cmpgtu_fp0_jump_t = 1458
12990 CEFBS_None, // J4_cmpgtu_fp1_jump_nt = 1459
12991 CEFBS_None, // J4_cmpgtu_fp1_jump_t = 1460
12992 CEFBS_None, // J4_cmpgtu_t_jumpnv_nt = 1461
12993 CEFBS_None, // J4_cmpgtu_t_jumpnv_t = 1462
12994 CEFBS_None, // J4_cmpgtu_tp0_jump_nt = 1463
12995 CEFBS_None, // J4_cmpgtu_tp0_jump_t = 1464
12996 CEFBS_None, // J4_cmpgtu_tp1_jump_nt = 1465
12997 CEFBS_None, // J4_cmpgtu_tp1_jump_t = 1466
12998 CEFBS_None, // J4_cmpgtui_f_jumpnv_nt = 1467
12999 CEFBS_None, // J4_cmpgtui_f_jumpnv_t = 1468
13000 CEFBS_None, // J4_cmpgtui_fp0_jump_nt = 1469
13001 CEFBS_None, // J4_cmpgtui_fp0_jump_t = 1470
13002 CEFBS_None, // J4_cmpgtui_fp1_jump_nt = 1471
13003 CEFBS_None, // J4_cmpgtui_fp1_jump_t = 1472
13004 CEFBS_None, // J4_cmpgtui_t_jumpnv_nt = 1473
13005 CEFBS_None, // J4_cmpgtui_t_jumpnv_t = 1474
13006 CEFBS_None, // J4_cmpgtui_tp0_jump_nt = 1475
13007 CEFBS_None, // J4_cmpgtui_tp0_jump_t = 1476
13008 CEFBS_None, // J4_cmpgtui_tp1_jump_nt = 1477
13009 CEFBS_None, // J4_cmpgtui_tp1_jump_t = 1478
13010 CEFBS_None, // J4_cmplt_f_jumpnv_nt = 1479
13011 CEFBS_None, // J4_cmplt_f_jumpnv_t = 1480
13012 CEFBS_None, // J4_cmplt_t_jumpnv_nt = 1481
13013 CEFBS_None, // J4_cmplt_t_jumpnv_t = 1482
13014 CEFBS_None, // J4_cmpltu_f_jumpnv_nt = 1483
13015 CEFBS_None, // J4_cmpltu_f_jumpnv_t = 1484
13016 CEFBS_None, // J4_cmpltu_t_jumpnv_nt = 1485
13017 CEFBS_None, // J4_cmpltu_t_jumpnv_t = 1486
13018 CEFBS_None, // J4_hintjumpr = 1487
13019 CEFBS_None, // J4_jumpseti = 1488
13020 CEFBS_None, // J4_jumpsetr = 1489
13021 CEFBS_None, // J4_tstbit0_f_jumpnv_nt = 1490
13022 CEFBS_None, // J4_tstbit0_f_jumpnv_t = 1491
13023 CEFBS_None, // J4_tstbit0_fp0_jump_nt = 1492
13024 CEFBS_None, // J4_tstbit0_fp0_jump_t = 1493
13025 CEFBS_None, // J4_tstbit0_fp1_jump_nt = 1494
13026 CEFBS_None, // J4_tstbit0_fp1_jump_t = 1495
13027 CEFBS_None, // J4_tstbit0_t_jumpnv_nt = 1496
13028 CEFBS_None, // J4_tstbit0_t_jumpnv_t = 1497
13029 CEFBS_None, // J4_tstbit0_tp0_jump_nt = 1498
13030 CEFBS_None, // J4_tstbit0_tp0_jump_t = 1499
13031 CEFBS_None, // J4_tstbit0_tp1_jump_nt = 1500
13032 CEFBS_None, // J4_tstbit0_tp1_jump_t = 1501
13033 CEFBS_None, // L2_deallocframe = 1502
13034 CEFBS_None, // L2_loadalignb_io = 1503
13035 CEFBS_None, // L2_loadalignb_pbr = 1504
13036 CEFBS_None, // L2_loadalignb_pci = 1505
13037 CEFBS_None, // L2_loadalignb_pcr = 1506
13038 CEFBS_None, // L2_loadalignb_pi = 1507
13039 CEFBS_None, // L2_loadalignb_pr = 1508
13040 CEFBS_None, // L2_loadalignh_io = 1509
13041 CEFBS_None, // L2_loadalignh_pbr = 1510
13042 CEFBS_None, // L2_loadalignh_pci = 1511
13043 CEFBS_None, // L2_loadalignh_pcr = 1512
13044 CEFBS_None, // L2_loadalignh_pi = 1513
13045 CEFBS_None, // L2_loadalignh_pr = 1514
13046 CEFBS_None, // L2_loadbsw2_io = 1515
13047 CEFBS_None, // L2_loadbsw2_pbr = 1516
13048 CEFBS_None, // L2_loadbsw2_pci = 1517
13049 CEFBS_None, // L2_loadbsw2_pcr = 1518
13050 CEFBS_None, // L2_loadbsw2_pi = 1519
13051 CEFBS_None, // L2_loadbsw2_pr = 1520
13052 CEFBS_None, // L2_loadbsw4_io = 1521
13053 CEFBS_None, // L2_loadbsw4_pbr = 1522
13054 CEFBS_None, // L2_loadbsw4_pci = 1523
13055 CEFBS_None, // L2_loadbsw4_pcr = 1524
13056 CEFBS_None, // L2_loadbsw4_pi = 1525
13057 CEFBS_None, // L2_loadbsw4_pr = 1526
13058 CEFBS_None, // L2_loadbzw2_io = 1527
13059 CEFBS_None, // L2_loadbzw2_pbr = 1528
13060 CEFBS_None, // L2_loadbzw2_pci = 1529
13061 CEFBS_None, // L2_loadbzw2_pcr = 1530
13062 CEFBS_None, // L2_loadbzw2_pi = 1531
13063 CEFBS_None, // L2_loadbzw2_pr = 1532
13064 CEFBS_None, // L2_loadbzw4_io = 1533
13065 CEFBS_None, // L2_loadbzw4_pbr = 1534
13066 CEFBS_None, // L2_loadbzw4_pci = 1535
13067 CEFBS_None, // L2_loadbzw4_pcr = 1536
13068 CEFBS_None, // L2_loadbzw4_pi = 1537
13069 CEFBS_None, // L2_loadbzw4_pr = 1538
13070 CEFBS_None, // L2_loadrb_io = 1539
13071 CEFBS_None, // L2_loadrb_pbr = 1540
13072 CEFBS_None, // L2_loadrb_pci = 1541
13073 CEFBS_None, // L2_loadrb_pcr = 1542
13074 CEFBS_None, // L2_loadrb_pi = 1543
13075 CEFBS_None, // L2_loadrb_pr = 1544
13076 CEFBS_None, // L2_loadrbgp = 1545
13077 CEFBS_None, // L2_loadrd_io = 1546
13078 CEFBS_None, // L2_loadrd_pbr = 1547
13079 CEFBS_None, // L2_loadrd_pci = 1548
13080 CEFBS_None, // L2_loadrd_pcr = 1549
13081 CEFBS_None, // L2_loadrd_pi = 1550
13082 CEFBS_None, // L2_loadrd_pr = 1551
13083 CEFBS_None, // L2_loadrdgp = 1552
13084 CEFBS_None, // L2_loadrh_io = 1553
13085 CEFBS_None, // L2_loadrh_pbr = 1554
13086 CEFBS_None, // L2_loadrh_pci = 1555
13087 CEFBS_None, // L2_loadrh_pcr = 1556
13088 CEFBS_None, // L2_loadrh_pi = 1557
13089 CEFBS_None, // L2_loadrh_pr = 1558
13090 CEFBS_None, // L2_loadrhgp = 1559
13091 CEFBS_None, // L2_loadri_io = 1560
13092 CEFBS_None, // L2_loadri_pbr = 1561
13093 CEFBS_None, // L2_loadri_pci = 1562
13094 CEFBS_None, // L2_loadri_pcr = 1563
13095 CEFBS_None, // L2_loadri_pi = 1564
13096 CEFBS_None, // L2_loadri_pr = 1565
13097 CEFBS_None, // L2_loadrigp = 1566
13098 CEFBS_None, // L2_loadrub_io = 1567
13099 CEFBS_None, // L2_loadrub_pbr = 1568
13100 CEFBS_None, // L2_loadrub_pci = 1569
13101 CEFBS_None, // L2_loadrub_pcr = 1570
13102 CEFBS_None, // L2_loadrub_pi = 1571
13103 CEFBS_None, // L2_loadrub_pr = 1572
13104 CEFBS_None, // L2_loadrubgp = 1573
13105 CEFBS_None, // L2_loadruh_io = 1574
13106 CEFBS_None, // L2_loadruh_pbr = 1575
13107 CEFBS_None, // L2_loadruh_pci = 1576
13108 CEFBS_None, // L2_loadruh_pcr = 1577
13109 CEFBS_None, // L2_loadruh_pi = 1578
13110 CEFBS_None, // L2_loadruh_pr = 1579
13111 CEFBS_None, // L2_loadruhgp = 1580
13112 CEFBS_HasV68, // L2_loadw_aq = 1581
13113 CEFBS_None, // L2_loadw_locked = 1582
13114 CEFBS_None, // L2_ploadrbf_io = 1583
13115 CEFBS_None, // L2_ploadrbf_pi = 1584
13116 CEFBS_None, // L2_ploadrbfnew_io = 1585
13117 CEFBS_None, // L2_ploadrbfnew_pi = 1586
13118 CEFBS_None, // L2_ploadrbt_io = 1587
13119 CEFBS_None, // L2_ploadrbt_pi = 1588
13120 CEFBS_None, // L2_ploadrbtnew_io = 1589
13121 CEFBS_None, // L2_ploadrbtnew_pi = 1590
13122 CEFBS_None, // L2_ploadrdf_io = 1591
13123 CEFBS_None, // L2_ploadrdf_pi = 1592
13124 CEFBS_None, // L2_ploadrdfnew_io = 1593
13125 CEFBS_None, // L2_ploadrdfnew_pi = 1594
13126 CEFBS_None, // L2_ploadrdt_io = 1595
13127 CEFBS_None, // L2_ploadrdt_pi = 1596
13128 CEFBS_None, // L2_ploadrdtnew_io = 1597
13129 CEFBS_None, // L2_ploadrdtnew_pi = 1598
13130 CEFBS_None, // L2_ploadrhf_io = 1599
13131 CEFBS_None, // L2_ploadrhf_pi = 1600
13132 CEFBS_None, // L2_ploadrhfnew_io = 1601
13133 CEFBS_None, // L2_ploadrhfnew_pi = 1602
13134 CEFBS_None, // L2_ploadrht_io = 1603
13135 CEFBS_None, // L2_ploadrht_pi = 1604
13136 CEFBS_None, // L2_ploadrhtnew_io = 1605
13137 CEFBS_None, // L2_ploadrhtnew_pi = 1606
13138 CEFBS_None, // L2_ploadrif_io = 1607
13139 CEFBS_None, // L2_ploadrif_pi = 1608
13140 CEFBS_None, // L2_ploadrifnew_io = 1609
13141 CEFBS_None, // L2_ploadrifnew_pi = 1610
13142 CEFBS_None, // L2_ploadrit_io = 1611
13143 CEFBS_None, // L2_ploadrit_pi = 1612
13144 CEFBS_None, // L2_ploadritnew_io = 1613
13145 CEFBS_None, // L2_ploadritnew_pi = 1614
13146 CEFBS_None, // L2_ploadrubf_io = 1615
13147 CEFBS_None, // L2_ploadrubf_pi = 1616
13148 CEFBS_None, // L2_ploadrubfnew_io = 1617
13149 CEFBS_None, // L2_ploadrubfnew_pi = 1618
13150 CEFBS_None, // L2_ploadrubt_io = 1619
13151 CEFBS_None, // L2_ploadrubt_pi = 1620
13152 CEFBS_None, // L2_ploadrubtnew_io = 1621
13153 CEFBS_None, // L2_ploadrubtnew_pi = 1622
13154 CEFBS_None, // L2_ploadruhf_io = 1623
13155 CEFBS_None, // L2_ploadruhf_pi = 1624
13156 CEFBS_None, // L2_ploadruhfnew_io = 1625
13157 CEFBS_None, // L2_ploadruhfnew_pi = 1626
13158 CEFBS_None, // L2_ploadruht_io = 1627
13159 CEFBS_None, // L2_ploadruht_pi = 1628
13160 CEFBS_None, // L2_ploadruhtnew_io = 1629
13161 CEFBS_None, // L2_ploadruhtnew_pi = 1630
13162 CEFBS_None, // L4_add_memopb_io = 1631
13163 CEFBS_None, // L4_add_memoph_io = 1632
13164 CEFBS_None, // L4_add_memopw_io = 1633
13165 CEFBS_None, // L4_and_memopb_io = 1634
13166 CEFBS_None, // L4_and_memoph_io = 1635
13167 CEFBS_None, // L4_and_memopw_io = 1636
13168 CEFBS_None, // L4_iadd_memopb_io = 1637
13169 CEFBS_None, // L4_iadd_memoph_io = 1638
13170 CEFBS_None, // L4_iadd_memopw_io = 1639
13171 CEFBS_None, // L4_iand_memopb_io = 1640
13172 CEFBS_None, // L4_iand_memoph_io = 1641
13173 CEFBS_None, // L4_iand_memopw_io = 1642
13174 CEFBS_None, // L4_ior_memopb_io = 1643
13175 CEFBS_None, // L4_ior_memoph_io = 1644
13176 CEFBS_None, // L4_ior_memopw_io = 1645
13177 CEFBS_None, // L4_isub_memopb_io = 1646
13178 CEFBS_None, // L4_isub_memoph_io = 1647
13179 CEFBS_None, // L4_isub_memopw_io = 1648
13180 CEFBS_None, // L4_loadalignb_ap = 1649
13181 CEFBS_None, // L4_loadalignb_ur = 1650
13182 CEFBS_None, // L4_loadalignh_ap = 1651
13183 CEFBS_None, // L4_loadalignh_ur = 1652
13184 CEFBS_None, // L4_loadbsw2_ap = 1653
13185 CEFBS_None, // L4_loadbsw2_ur = 1654
13186 CEFBS_None, // L4_loadbsw4_ap = 1655
13187 CEFBS_None, // L4_loadbsw4_ur = 1656
13188 CEFBS_None, // L4_loadbzw2_ap = 1657
13189 CEFBS_None, // L4_loadbzw2_ur = 1658
13190 CEFBS_None, // L4_loadbzw4_ap = 1659
13191 CEFBS_None, // L4_loadbzw4_ur = 1660
13192 CEFBS_HasV68, // L4_loadd_aq = 1661
13193 CEFBS_None, // L4_loadd_locked = 1662
13194 CEFBS_None, // L4_loadrb_ap = 1663
13195 CEFBS_None, // L4_loadrb_rr = 1664
13196 CEFBS_None, // L4_loadrb_ur = 1665
13197 CEFBS_None, // L4_loadrd_ap = 1666
13198 CEFBS_None, // L4_loadrd_rr = 1667
13199 CEFBS_None, // L4_loadrd_ur = 1668
13200 CEFBS_None, // L4_loadrh_ap = 1669
13201 CEFBS_None, // L4_loadrh_rr = 1670
13202 CEFBS_None, // L4_loadrh_ur = 1671
13203 CEFBS_None, // L4_loadri_ap = 1672
13204 CEFBS_None, // L4_loadri_rr = 1673
13205 CEFBS_None, // L4_loadri_ur = 1674
13206 CEFBS_None, // L4_loadrub_ap = 1675
13207 CEFBS_None, // L4_loadrub_rr = 1676
13208 CEFBS_None, // L4_loadrub_ur = 1677
13209 CEFBS_None, // L4_loadruh_ap = 1678
13210 CEFBS_None, // L4_loadruh_rr = 1679
13211 CEFBS_None, // L4_loadruh_ur = 1680
13212 CEFBS_None, // L4_loadw_phys = 1681
13213 CEFBS_None, // L4_or_memopb_io = 1682
13214 CEFBS_None, // L4_or_memoph_io = 1683
13215 CEFBS_None, // L4_or_memopw_io = 1684
13216 CEFBS_None, // L4_ploadrbf_abs = 1685
13217 CEFBS_None, // L4_ploadrbf_rr = 1686
13218 CEFBS_None, // L4_ploadrbfnew_abs = 1687
13219 CEFBS_None, // L4_ploadrbfnew_rr = 1688
13220 CEFBS_None, // L4_ploadrbt_abs = 1689
13221 CEFBS_None, // L4_ploadrbt_rr = 1690
13222 CEFBS_None, // L4_ploadrbtnew_abs = 1691
13223 CEFBS_None, // L4_ploadrbtnew_rr = 1692
13224 CEFBS_None, // L4_ploadrdf_abs = 1693
13225 CEFBS_None, // L4_ploadrdf_rr = 1694
13226 CEFBS_None, // L4_ploadrdfnew_abs = 1695
13227 CEFBS_None, // L4_ploadrdfnew_rr = 1696
13228 CEFBS_None, // L4_ploadrdt_abs = 1697
13229 CEFBS_None, // L4_ploadrdt_rr = 1698
13230 CEFBS_None, // L4_ploadrdtnew_abs = 1699
13231 CEFBS_None, // L4_ploadrdtnew_rr = 1700
13232 CEFBS_None, // L4_ploadrhf_abs = 1701
13233 CEFBS_None, // L4_ploadrhf_rr = 1702
13234 CEFBS_None, // L4_ploadrhfnew_abs = 1703
13235 CEFBS_None, // L4_ploadrhfnew_rr = 1704
13236 CEFBS_None, // L4_ploadrht_abs = 1705
13237 CEFBS_None, // L4_ploadrht_rr = 1706
13238 CEFBS_None, // L4_ploadrhtnew_abs = 1707
13239 CEFBS_None, // L4_ploadrhtnew_rr = 1708
13240 CEFBS_None, // L4_ploadrif_abs = 1709
13241 CEFBS_None, // L4_ploadrif_rr = 1710
13242 CEFBS_None, // L4_ploadrifnew_abs = 1711
13243 CEFBS_None, // L4_ploadrifnew_rr = 1712
13244 CEFBS_None, // L4_ploadrit_abs = 1713
13245 CEFBS_None, // L4_ploadrit_rr = 1714
13246 CEFBS_None, // L4_ploadritnew_abs = 1715
13247 CEFBS_None, // L4_ploadritnew_rr = 1716
13248 CEFBS_None, // L4_ploadrubf_abs = 1717
13249 CEFBS_None, // L4_ploadrubf_rr = 1718
13250 CEFBS_None, // L4_ploadrubfnew_abs = 1719
13251 CEFBS_None, // L4_ploadrubfnew_rr = 1720
13252 CEFBS_None, // L4_ploadrubt_abs = 1721
13253 CEFBS_None, // L4_ploadrubt_rr = 1722
13254 CEFBS_None, // L4_ploadrubtnew_abs = 1723
13255 CEFBS_None, // L4_ploadrubtnew_rr = 1724
13256 CEFBS_None, // L4_ploadruhf_abs = 1725
13257 CEFBS_None, // L4_ploadruhf_rr = 1726
13258 CEFBS_None, // L4_ploadruhfnew_abs = 1727
13259 CEFBS_None, // L4_ploadruhfnew_rr = 1728
13260 CEFBS_None, // L4_ploadruht_abs = 1729
13261 CEFBS_None, // L4_ploadruht_rr = 1730
13262 CEFBS_None, // L4_ploadruhtnew_abs = 1731
13263 CEFBS_None, // L4_ploadruhtnew_rr = 1732
13264 CEFBS_None, // L4_return = 1733
13265 CEFBS_None, // L4_return_f = 1734
13266 CEFBS_None, // L4_return_fnew_pnt = 1735
13267 CEFBS_None, // L4_return_fnew_pt = 1736
13268 CEFBS_None, // L4_return_t = 1737
13269 CEFBS_None, // L4_return_tnew_pnt = 1738
13270 CEFBS_None, // L4_return_tnew_pt = 1739
13271 CEFBS_None, // L4_sub_memopb_io = 1740
13272 CEFBS_None, // L4_sub_memoph_io = 1741
13273 CEFBS_None, // L4_sub_memopw_io = 1742
13274 CEFBS_HasV66, // L6_memcpy = 1743
13275 CEFBS_None, // LO = 1744
13276 CEFBS_None, // M2_acci = 1745
13277 CEFBS_None, // M2_accii = 1746
13278 CEFBS_None, // M2_cmaci_s0 = 1747
13279 CEFBS_None, // M2_cmacr_s0 = 1748
13280 CEFBS_None, // M2_cmacs_s0 = 1749
13281 CEFBS_None, // M2_cmacs_s1 = 1750
13282 CEFBS_None, // M2_cmacsc_s0 = 1751
13283 CEFBS_None, // M2_cmacsc_s1 = 1752
13284 CEFBS_None, // M2_cmpyi_s0 = 1753
13285 CEFBS_None, // M2_cmpyr_s0 = 1754
13286 CEFBS_None, // M2_cmpyrs_s0 = 1755
13287 CEFBS_None, // M2_cmpyrs_s1 = 1756
13288 CEFBS_None, // M2_cmpyrsc_s0 = 1757
13289 CEFBS_None, // M2_cmpyrsc_s1 = 1758
13290 CEFBS_None, // M2_cmpys_s0 = 1759
13291 CEFBS_None, // M2_cmpys_s1 = 1760
13292 CEFBS_None, // M2_cmpysc_s0 = 1761
13293 CEFBS_None, // M2_cmpysc_s1 = 1762
13294 CEFBS_None, // M2_cnacs_s0 = 1763
13295 CEFBS_None, // M2_cnacs_s1 = 1764
13296 CEFBS_None, // M2_cnacsc_s0 = 1765
13297 CEFBS_None, // M2_cnacsc_s1 = 1766
13298 CEFBS_None, // M2_dpmpyss_acc_s0 = 1767
13299 CEFBS_None, // M2_dpmpyss_nac_s0 = 1768
13300 CEFBS_None, // M2_dpmpyss_rnd_s0 = 1769
13301 CEFBS_None, // M2_dpmpyss_s0 = 1770
13302 CEFBS_None, // M2_dpmpyuu_acc_s0 = 1771
13303 CEFBS_None, // M2_dpmpyuu_nac_s0 = 1772
13304 CEFBS_None, // M2_dpmpyuu_s0 = 1773
13305 CEFBS_None, // M2_hmmpyh_rs1 = 1774
13306 CEFBS_None, // M2_hmmpyh_s1 = 1775
13307 CEFBS_None, // M2_hmmpyl_rs1 = 1776
13308 CEFBS_None, // M2_hmmpyl_s1 = 1777
13309 CEFBS_None, // M2_maci = 1778
13310 CEFBS_None, // M2_macsin = 1779
13311 CEFBS_None, // M2_macsip = 1780
13312 CEFBS_None, // M2_mmachs_rs0 = 1781
13313 CEFBS_None, // M2_mmachs_rs1 = 1782
13314 CEFBS_None, // M2_mmachs_s0 = 1783
13315 CEFBS_None, // M2_mmachs_s1 = 1784
13316 CEFBS_None, // M2_mmacls_rs0 = 1785
13317 CEFBS_None, // M2_mmacls_rs1 = 1786
13318 CEFBS_None, // M2_mmacls_s0 = 1787
13319 CEFBS_None, // M2_mmacls_s1 = 1788
13320 CEFBS_None, // M2_mmacuhs_rs0 = 1789
13321 CEFBS_None, // M2_mmacuhs_rs1 = 1790
13322 CEFBS_None, // M2_mmacuhs_s0 = 1791
13323 CEFBS_None, // M2_mmacuhs_s1 = 1792
13324 CEFBS_None, // M2_mmaculs_rs0 = 1793
13325 CEFBS_None, // M2_mmaculs_rs1 = 1794
13326 CEFBS_None, // M2_mmaculs_s0 = 1795
13327 CEFBS_None, // M2_mmaculs_s1 = 1796
13328 CEFBS_None, // M2_mmpyh_rs0 = 1797
13329 CEFBS_None, // M2_mmpyh_rs1 = 1798
13330 CEFBS_None, // M2_mmpyh_s0 = 1799
13331 CEFBS_None, // M2_mmpyh_s1 = 1800
13332 CEFBS_None, // M2_mmpyl_rs0 = 1801
13333 CEFBS_None, // M2_mmpyl_rs1 = 1802
13334 CEFBS_None, // M2_mmpyl_s0 = 1803
13335 CEFBS_None, // M2_mmpyl_s1 = 1804
13336 CEFBS_None, // M2_mmpyuh_rs0 = 1805
13337 CEFBS_None, // M2_mmpyuh_rs1 = 1806
13338 CEFBS_None, // M2_mmpyuh_s0 = 1807
13339 CEFBS_None, // M2_mmpyuh_s1 = 1808
13340 CEFBS_None, // M2_mmpyul_rs0 = 1809
13341 CEFBS_None, // M2_mmpyul_rs1 = 1810
13342 CEFBS_None, // M2_mmpyul_s0 = 1811
13343 CEFBS_None, // M2_mmpyul_s1 = 1812
13344 CEFBS_HasV66, // M2_mnaci = 1813
13345 CEFBS_None, // M2_mpy_acc_hh_s0 = 1814
13346 CEFBS_None, // M2_mpy_acc_hh_s1 = 1815
13347 CEFBS_None, // M2_mpy_acc_hl_s0 = 1816
13348 CEFBS_None, // M2_mpy_acc_hl_s1 = 1817
13349 CEFBS_None, // M2_mpy_acc_lh_s0 = 1818
13350 CEFBS_None, // M2_mpy_acc_lh_s1 = 1819
13351 CEFBS_None, // M2_mpy_acc_ll_s0 = 1820
13352 CEFBS_None, // M2_mpy_acc_ll_s1 = 1821
13353 CEFBS_None, // M2_mpy_acc_sat_hh_s0 = 1822
13354 CEFBS_None, // M2_mpy_acc_sat_hh_s1 = 1823
13355 CEFBS_None, // M2_mpy_acc_sat_hl_s0 = 1824
13356 CEFBS_None, // M2_mpy_acc_sat_hl_s1 = 1825
13357 CEFBS_None, // M2_mpy_acc_sat_lh_s0 = 1826
13358 CEFBS_None, // M2_mpy_acc_sat_lh_s1 = 1827
13359 CEFBS_None, // M2_mpy_acc_sat_ll_s0 = 1828
13360 CEFBS_None, // M2_mpy_acc_sat_ll_s1 = 1829
13361 CEFBS_None, // M2_mpy_hh_s0 = 1830
13362 CEFBS_None, // M2_mpy_hh_s1 = 1831
13363 CEFBS_None, // M2_mpy_hl_s0 = 1832
13364 CEFBS_None, // M2_mpy_hl_s1 = 1833
13365 CEFBS_None, // M2_mpy_lh_s0 = 1834
13366 CEFBS_None, // M2_mpy_lh_s1 = 1835
13367 CEFBS_None, // M2_mpy_ll_s0 = 1836
13368 CEFBS_None, // M2_mpy_ll_s1 = 1837
13369 CEFBS_None, // M2_mpy_nac_hh_s0 = 1838
13370 CEFBS_None, // M2_mpy_nac_hh_s1 = 1839
13371 CEFBS_None, // M2_mpy_nac_hl_s0 = 1840
13372 CEFBS_None, // M2_mpy_nac_hl_s1 = 1841
13373 CEFBS_None, // M2_mpy_nac_lh_s0 = 1842
13374 CEFBS_None, // M2_mpy_nac_lh_s1 = 1843
13375 CEFBS_None, // M2_mpy_nac_ll_s0 = 1844
13376 CEFBS_None, // M2_mpy_nac_ll_s1 = 1845
13377 CEFBS_None, // M2_mpy_nac_sat_hh_s0 = 1846
13378 CEFBS_None, // M2_mpy_nac_sat_hh_s1 = 1847
13379 CEFBS_None, // M2_mpy_nac_sat_hl_s0 = 1848
13380 CEFBS_None, // M2_mpy_nac_sat_hl_s1 = 1849
13381 CEFBS_None, // M2_mpy_nac_sat_lh_s0 = 1850
13382 CEFBS_None, // M2_mpy_nac_sat_lh_s1 = 1851
13383 CEFBS_None, // M2_mpy_nac_sat_ll_s0 = 1852
13384 CEFBS_None, // M2_mpy_nac_sat_ll_s1 = 1853
13385 CEFBS_None, // M2_mpy_rnd_hh_s0 = 1854
13386 CEFBS_None, // M2_mpy_rnd_hh_s1 = 1855
13387 CEFBS_None, // M2_mpy_rnd_hl_s0 = 1856
13388 CEFBS_None, // M2_mpy_rnd_hl_s1 = 1857
13389 CEFBS_None, // M2_mpy_rnd_lh_s0 = 1858
13390 CEFBS_None, // M2_mpy_rnd_lh_s1 = 1859
13391 CEFBS_None, // M2_mpy_rnd_ll_s0 = 1860
13392 CEFBS_None, // M2_mpy_rnd_ll_s1 = 1861
13393 CEFBS_None, // M2_mpy_sat_hh_s0 = 1862
13394 CEFBS_None, // M2_mpy_sat_hh_s1 = 1863
13395 CEFBS_None, // M2_mpy_sat_hl_s0 = 1864
13396 CEFBS_None, // M2_mpy_sat_hl_s1 = 1865
13397 CEFBS_None, // M2_mpy_sat_lh_s0 = 1866
13398 CEFBS_None, // M2_mpy_sat_lh_s1 = 1867
13399 CEFBS_None, // M2_mpy_sat_ll_s0 = 1868
13400 CEFBS_None, // M2_mpy_sat_ll_s1 = 1869
13401 CEFBS_None, // M2_mpy_sat_rnd_hh_s0 = 1870
13402 CEFBS_None, // M2_mpy_sat_rnd_hh_s1 = 1871
13403 CEFBS_None, // M2_mpy_sat_rnd_hl_s0 = 1872
13404 CEFBS_None, // M2_mpy_sat_rnd_hl_s1 = 1873
13405 CEFBS_None, // M2_mpy_sat_rnd_lh_s0 = 1874
13406 CEFBS_None, // M2_mpy_sat_rnd_lh_s1 = 1875
13407 CEFBS_None, // M2_mpy_sat_rnd_ll_s0 = 1876
13408 CEFBS_None, // M2_mpy_sat_rnd_ll_s1 = 1877
13409 CEFBS_None, // M2_mpy_up = 1878
13410 CEFBS_None, // M2_mpy_up_s1 = 1879
13411 CEFBS_None, // M2_mpy_up_s1_sat = 1880
13412 CEFBS_None, // M2_mpyd_acc_hh_s0 = 1881
13413 CEFBS_None, // M2_mpyd_acc_hh_s1 = 1882
13414 CEFBS_None, // M2_mpyd_acc_hl_s0 = 1883
13415 CEFBS_None, // M2_mpyd_acc_hl_s1 = 1884
13416 CEFBS_None, // M2_mpyd_acc_lh_s0 = 1885
13417 CEFBS_None, // M2_mpyd_acc_lh_s1 = 1886
13418 CEFBS_None, // M2_mpyd_acc_ll_s0 = 1887
13419 CEFBS_None, // M2_mpyd_acc_ll_s1 = 1888
13420 CEFBS_None, // M2_mpyd_hh_s0 = 1889
13421 CEFBS_None, // M2_mpyd_hh_s1 = 1890
13422 CEFBS_None, // M2_mpyd_hl_s0 = 1891
13423 CEFBS_None, // M2_mpyd_hl_s1 = 1892
13424 CEFBS_None, // M2_mpyd_lh_s0 = 1893
13425 CEFBS_None, // M2_mpyd_lh_s1 = 1894
13426 CEFBS_None, // M2_mpyd_ll_s0 = 1895
13427 CEFBS_None, // M2_mpyd_ll_s1 = 1896
13428 CEFBS_None, // M2_mpyd_nac_hh_s0 = 1897
13429 CEFBS_None, // M2_mpyd_nac_hh_s1 = 1898
13430 CEFBS_None, // M2_mpyd_nac_hl_s0 = 1899
13431 CEFBS_None, // M2_mpyd_nac_hl_s1 = 1900
13432 CEFBS_None, // M2_mpyd_nac_lh_s0 = 1901
13433 CEFBS_None, // M2_mpyd_nac_lh_s1 = 1902
13434 CEFBS_None, // M2_mpyd_nac_ll_s0 = 1903
13435 CEFBS_None, // M2_mpyd_nac_ll_s1 = 1904
13436 CEFBS_None, // M2_mpyd_rnd_hh_s0 = 1905
13437 CEFBS_None, // M2_mpyd_rnd_hh_s1 = 1906
13438 CEFBS_None, // M2_mpyd_rnd_hl_s0 = 1907
13439 CEFBS_None, // M2_mpyd_rnd_hl_s1 = 1908
13440 CEFBS_None, // M2_mpyd_rnd_lh_s0 = 1909
13441 CEFBS_None, // M2_mpyd_rnd_lh_s1 = 1910
13442 CEFBS_None, // M2_mpyd_rnd_ll_s0 = 1911
13443 CEFBS_None, // M2_mpyd_rnd_ll_s1 = 1912
13444 CEFBS_None, // M2_mpyi = 1913
13445 CEFBS_None, // M2_mpysin = 1914
13446 CEFBS_None, // M2_mpysip = 1915
13447 CEFBS_None, // M2_mpysu_up = 1916
13448 CEFBS_None, // M2_mpyu_acc_hh_s0 = 1917
13449 CEFBS_None, // M2_mpyu_acc_hh_s1 = 1918
13450 CEFBS_None, // M2_mpyu_acc_hl_s0 = 1919
13451 CEFBS_None, // M2_mpyu_acc_hl_s1 = 1920
13452 CEFBS_None, // M2_mpyu_acc_lh_s0 = 1921
13453 CEFBS_None, // M2_mpyu_acc_lh_s1 = 1922
13454 CEFBS_None, // M2_mpyu_acc_ll_s0 = 1923
13455 CEFBS_None, // M2_mpyu_acc_ll_s1 = 1924
13456 CEFBS_None, // M2_mpyu_hh_s0 = 1925
13457 CEFBS_None, // M2_mpyu_hh_s1 = 1926
13458 CEFBS_None, // M2_mpyu_hl_s0 = 1927
13459 CEFBS_None, // M2_mpyu_hl_s1 = 1928
13460 CEFBS_None, // M2_mpyu_lh_s0 = 1929
13461 CEFBS_None, // M2_mpyu_lh_s1 = 1930
13462 CEFBS_None, // M2_mpyu_ll_s0 = 1931
13463 CEFBS_None, // M2_mpyu_ll_s1 = 1932
13464 CEFBS_None, // M2_mpyu_nac_hh_s0 = 1933
13465 CEFBS_None, // M2_mpyu_nac_hh_s1 = 1934
13466 CEFBS_None, // M2_mpyu_nac_hl_s0 = 1935
13467 CEFBS_None, // M2_mpyu_nac_hl_s1 = 1936
13468 CEFBS_None, // M2_mpyu_nac_lh_s0 = 1937
13469 CEFBS_None, // M2_mpyu_nac_lh_s1 = 1938
13470 CEFBS_None, // M2_mpyu_nac_ll_s0 = 1939
13471 CEFBS_None, // M2_mpyu_nac_ll_s1 = 1940
13472 CEFBS_None, // M2_mpyu_up = 1941
13473 CEFBS_None, // M2_mpyud_acc_hh_s0 = 1942
13474 CEFBS_None, // M2_mpyud_acc_hh_s1 = 1943
13475 CEFBS_None, // M2_mpyud_acc_hl_s0 = 1944
13476 CEFBS_None, // M2_mpyud_acc_hl_s1 = 1945
13477 CEFBS_None, // M2_mpyud_acc_lh_s0 = 1946
13478 CEFBS_None, // M2_mpyud_acc_lh_s1 = 1947
13479 CEFBS_None, // M2_mpyud_acc_ll_s0 = 1948
13480 CEFBS_None, // M2_mpyud_acc_ll_s1 = 1949
13481 CEFBS_None, // M2_mpyud_hh_s0 = 1950
13482 CEFBS_None, // M2_mpyud_hh_s1 = 1951
13483 CEFBS_None, // M2_mpyud_hl_s0 = 1952
13484 CEFBS_None, // M2_mpyud_hl_s1 = 1953
13485 CEFBS_None, // M2_mpyud_lh_s0 = 1954
13486 CEFBS_None, // M2_mpyud_lh_s1 = 1955
13487 CEFBS_None, // M2_mpyud_ll_s0 = 1956
13488 CEFBS_None, // M2_mpyud_ll_s1 = 1957
13489 CEFBS_None, // M2_mpyud_nac_hh_s0 = 1958
13490 CEFBS_None, // M2_mpyud_nac_hh_s1 = 1959
13491 CEFBS_None, // M2_mpyud_nac_hl_s0 = 1960
13492 CEFBS_None, // M2_mpyud_nac_hl_s1 = 1961
13493 CEFBS_None, // M2_mpyud_nac_lh_s0 = 1962
13494 CEFBS_None, // M2_mpyud_nac_lh_s1 = 1963
13495 CEFBS_None, // M2_mpyud_nac_ll_s0 = 1964
13496 CEFBS_None, // M2_mpyud_nac_ll_s1 = 1965
13497 CEFBS_None, // M2_nacci = 1966
13498 CEFBS_None, // M2_naccii = 1967
13499 CEFBS_None, // M2_subacc = 1968
13500 CEFBS_None, // M2_vabsdiffh = 1969
13501 CEFBS_None, // M2_vabsdiffw = 1970
13502 CEFBS_None, // M2_vcmac_s0_sat_i = 1971
13503 CEFBS_None, // M2_vcmac_s0_sat_r = 1972
13504 CEFBS_None, // M2_vcmpy_s0_sat_i = 1973
13505 CEFBS_None, // M2_vcmpy_s0_sat_r = 1974
13506 CEFBS_None, // M2_vcmpy_s1_sat_i = 1975
13507 CEFBS_None, // M2_vcmpy_s1_sat_r = 1976
13508 CEFBS_None, // M2_vdmacs_s0 = 1977
13509 CEFBS_None, // M2_vdmacs_s1 = 1978
13510 CEFBS_None, // M2_vdmpyrs_s0 = 1979
13511 CEFBS_None, // M2_vdmpyrs_s1 = 1980
13512 CEFBS_None, // M2_vdmpys_s0 = 1981
13513 CEFBS_None, // M2_vdmpys_s1 = 1982
13514 CEFBS_None, // M2_vmac2 = 1983
13515 CEFBS_None, // M2_vmac2es = 1984
13516 CEFBS_None, // M2_vmac2es_s0 = 1985
13517 CEFBS_None, // M2_vmac2es_s1 = 1986
13518 CEFBS_None, // M2_vmac2s_s0 = 1987
13519 CEFBS_None, // M2_vmac2s_s1 = 1988
13520 CEFBS_None, // M2_vmac2su_s0 = 1989
13521 CEFBS_None, // M2_vmac2su_s1 = 1990
13522 CEFBS_None, // M2_vmpy2es_s0 = 1991
13523 CEFBS_None, // M2_vmpy2es_s1 = 1992
13524 CEFBS_None, // M2_vmpy2s_s0 = 1993
13525 CEFBS_None, // M2_vmpy2s_s0pack = 1994
13526 CEFBS_None, // M2_vmpy2s_s1 = 1995
13527 CEFBS_None, // M2_vmpy2s_s1pack = 1996
13528 CEFBS_None, // M2_vmpy2su_s0 = 1997
13529 CEFBS_None, // M2_vmpy2su_s1 = 1998
13530 CEFBS_None, // M2_vraddh = 1999
13531 CEFBS_None, // M2_vradduh = 2000
13532 CEFBS_None, // M2_vrcmaci_s0 = 2001
13533 CEFBS_None, // M2_vrcmaci_s0c = 2002
13534 CEFBS_None, // M2_vrcmacr_s0 = 2003
13535 CEFBS_None, // M2_vrcmacr_s0c = 2004
13536 CEFBS_None, // M2_vrcmpyi_s0 = 2005
13537 CEFBS_None, // M2_vrcmpyi_s0c = 2006
13538 CEFBS_None, // M2_vrcmpyr_s0 = 2007
13539 CEFBS_None, // M2_vrcmpyr_s0c = 2008
13540 CEFBS_None, // M2_vrcmpys_acc_s1_h = 2009
13541 CEFBS_None, // M2_vrcmpys_acc_s1_l = 2010
13542 CEFBS_None, // M2_vrcmpys_s1_h = 2011
13543 CEFBS_None, // M2_vrcmpys_s1_l = 2012
13544 CEFBS_None, // M2_vrcmpys_s1rp_h = 2013
13545 CEFBS_None, // M2_vrcmpys_s1rp_l = 2014
13546 CEFBS_None, // M2_vrmac_s0 = 2015
13547 CEFBS_None, // M2_vrmpy_s0 = 2016
13548 CEFBS_None, // M2_xor_xacc = 2017
13549 CEFBS_None, // M4_and_and = 2018
13550 CEFBS_None, // M4_and_andn = 2019
13551 CEFBS_None, // M4_and_or = 2020
13552 CEFBS_None, // M4_and_xor = 2021
13553 CEFBS_None, // M4_cmpyi_wh = 2022
13554 CEFBS_None, // M4_cmpyi_whc = 2023
13555 CEFBS_None, // M4_cmpyr_wh = 2024
13556 CEFBS_None, // M4_cmpyr_whc = 2025
13557 CEFBS_None, // M4_mac_up_s1_sat = 2026
13558 CEFBS_None, // M4_mpyri_addi = 2027
13559 CEFBS_None, // M4_mpyri_addr = 2028
13560 CEFBS_None, // M4_mpyri_addr_u2 = 2029
13561 CEFBS_None, // M4_mpyrr_addi = 2030
13562 CEFBS_None, // M4_mpyrr_addr = 2031
13563 CEFBS_None, // M4_nac_up_s1_sat = 2032
13564 CEFBS_None, // M4_or_and = 2033
13565 CEFBS_None, // M4_or_andn = 2034
13566 CEFBS_None, // M4_or_or = 2035
13567 CEFBS_None, // M4_or_xor = 2036
13568 CEFBS_None, // M4_pmpyw = 2037
13569 CEFBS_None, // M4_pmpyw_acc = 2038
13570 CEFBS_None, // M4_vpmpyh = 2039
13571 CEFBS_None, // M4_vpmpyh_acc = 2040
13572 CEFBS_None, // M4_vrmpyeh_acc_s0 = 2041
13573 CEFBS_None, // M4_vrmpyeh_acc_s1 = 2042
13574 CEFBS_None, // M4_vrmpyeh_s0 = 2043
13575 CEFBS_None, // M4_vrmpyeh_s1 = 2044
13576 CEFBS_None, // M4_vrmpyoh_acc_s0 = 2045
13577 CEFBS_None, // M4_vrmpyoh_acc_s1 = 2046
13578 CEFBS_None, // M4_vrmpyoh_s0 = 2047
13579 CEFBS_None, // M4_vrmpyoh_s1 = 2048
13580 CEFBS_None, // M4_xor_and = 2049
13581 CEFBS_None, // M4_xor_andn = 2050
13582 CEFBS_None, // M4_xor_or = 2051
13583 CEFBS_None, // M4_xor_xacc = 2052
13584 CEFBS_None, // M5_vdmacbsu = 2053
13585 CEFBS_None, // M5_vdmpybsu = 2054
13586 CEFBS_None, // M5_vmacbsu = 2055
13587 CEFBS_None, // M5_vmacbuu = 2056
13588 CEFBS_None, // M5_vmpybsu = 2057
13589 CEFBS_None, // M5_vmpybuu = 2058
13590 CEFBS_None, // M5_vrmacbsu = 2059
13591 CEFBS_None, // M5_vrmacbuu = 2060
13592 CEFBS_None, // M5_vrmpybsu = 2061
13593 CEFBS_None, // M5_vrmpybuu = 2062
13594 CEFBS_HasV62, // M6_vabsdiffb = 2063
13595 CEFBS_HasV62, // M6_vabsdiffub = 2064
13596 CEFBS_HasV67_UseAudio, // M7_dcmpyiw = 2065
13597 CEFBS_HasV67_UseAudio, // M7_dcmpyiw_acc = 2066
13598 CEFBS_HasV67_UseAudio, // M7_dcmpyiwc = 2067
13599 CEFBS_HasV67_UseAudio, // M7_dcmpyiwc_acc = 2068
13600 CEFBS_HasV67_UseAudio, // M7_dcmpyrw = 2069
13601 CEFBS_HasV67_UseAudio, // M7_dcmpyrw_acc = 2070
13602 CEFBS_HasV67_UseAudio, // M7_dcmpyrwc = 2071
13603 CEFBS_HasV67_UseAudio, // M7_dcmpyrwc_acc = 2072
13604 CEFBS_HasV67_UseAudio, // M7_wcmpyiw = 2073
13605 CEFBS_HasV67_UseAudio, // M7_wcmpyiw_rnd = 2074
13606 CEFBS_HasV67_UseAudio, // M7_wcmpyiwc = 2075
13607 CEFBS_HasV67_UseAudio, // M7_wcmpyiwc_rnd = 2076
13608 CEFBS_HasV67_UseAudio, // M7_wcmpyrw = 2077
13609 CEFBS_HasV67_UseAudio, // M7_wcmpyrw_rnd = 2078
13610 CEFBS_HasV67_UseAudio, // M7_wcmpyrwc = 2079
13611 CEFBS_HasV67_UseAudio, // M7_wcmpyrwc_rnd = 2080
13612 CEFBS_None, // PS_call_stk = 2081
13613 CEFBS_None, // PS_callr_nr = 2082
13614 CEFBS_None, // PS_jmpret = 2083
13615 CEFBS_None, // PS_jmpretf = 2084
13616 CEFBS_None, // PS_jmpretfnew = 2085
13617 CEFBS_None, // PS_jmpretfnewpt = 2086
13618 CEFBS_None, // PS_jmprett = 2087
13619 CEFBS_None, // PS_jmprettnew = 2088
13620 CEFBS_None, // PS_jmprettnewpt = 2089
13621 CEFBS_None, // PS_loadrbabs = 2090
13622 CEFBS_None, // PS_loadrdabs = 2091
13623 CEFBS_None, // PS_loadrhabs = 2092
13624 CEFBS_None, // PS_loadriabs = 2093
13625 CEFBS_None, // PS_loadrubabs = 2094
13626 CEFBS_None, // PS_loadruhabs = 2095
13627 CEFBS_None, // PS_storerbabs = 2096
13628 CEFBS_None, // PS_storerbnewabs = 2097
13629 CEFBS_None, // PS_storerdabs = 2098
13630 CEFBS_None, // PS_storerfabs = 2099
13631 CEFBS_None, // PS_storerhabs = 2100
13632 CEFBS_None, // PS_storerhnewabs = 2101
13633 CEFBS_None, // PS_storeriabs = 2102
13634 CEFBS_None, // PS_storerinewabs = 2103
13635 CEFBS_HasPreV65, // PS_trap1 = 2104
13636 CEFBS_HasV68, // R6_release_at_vi = 2105
13637 CEFBS_HasV68, // R6_release_st_vi = 2106
13638 CEFBS_None, // RESTORE_DEALLOC_BEFORE_TAILCALL_V4 = 2107
13639 CEFBS_None, // RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT = 2108
13640 CEFBS_None, // RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT_PIC = 2109
13641 CEFBS_None, // RESTORE_DEALLOC_BEFORE_TAILCALL_V4_PIC = 2110
13642 CEFBS_None, // RESTORE_DEALLOC_RET_JMP_V4 = 2111
13643 CEFBS_None, // RESTORE_DEALLOC_RET_JMP_V4_EXT = 2112
13644 CEFBS_None, // RESTORE_DEALLOC_RET_JMP_V4_EXT_PIC = 2113
13645 CEFBS_None, // RESTORE_DEALLOC_RET_JMP_V4_PIC = 2114
13646 CEFBS_None, // S2_addasl_rrri = 2115
13647 CEFBS_None, // S2_allocframe = 2116
13648 CEFBS_None, // S2_asl_i_p = 2117
13649 CEFBS_None, // S2_asl_i_p_acc = 2118
13650 CEFBS_None, // S2_asl_i_p_and = 2119
13651 CEFBS_None, // S2_asl_i_p_nac = 2120
13652 CEFBS_None, // S2_asl_i_p_or = 2121
13653 CEFBS_None, // S2_asl_i_p_xacc = 2122
13654 CEFBS_None, // S2_asl_i_r = 2123
13655 CEFBS_None, // S2_asl_i_r_acc = 2124
13656 CEFBS_None, // S2_asl_i_r_and = 2125
13657 CEFBS_None, // S2_asl_i_r_nac = 2126
13658 CEFBS_None, // S2_asl_i_r_or = 2127
13659 CEFBS_None, // S2_asl_i_r_sat = 2128
13660 CEFBS_None, // S2_asl_i_r_xacc = 2129
13661 CEFBS_None, // S2_asl_i_vh = 2130
13662 CEFBS_None, // S2_asl_i_vw = 2131
13663 CEFBS_None, // S2_asl_r_p = 2132
13664 CEFBS_None, // S2_asl_r_p_acc = 2133
13665 CEFBS_None, // S2_asl_r_p_and = 2134
13666 CEFBS_None, // S2_asl_r_p_nac = 2135
13667 CEFBS_None, // S2_asl_r_p_or = 2136
13668 CEFBS_None, // S2_asl_r_p_xor = 2137
13669 CEFBS_None, // S2_asl_r_r = 2138
13670 CEFBS_None, // S2_asl_r_r_acc = 2139
13671 CEFBS_None, // S2_asl_r_r_and = 2140
13672 CEFBS_None, // S2_asl_r_r_nac = 2141
13673 CEFBS_None, // S2_asl_r_r_or = 2142
13674 CEFBS_None, // S2_asl_r_r_sat = 2143
13675 CEFBS_None, // S2_asl_r_vh = 2144
13676 CEFBS_None, // S2_asl_r_vw = 2145
13677 CEFBS_None, // S2_asr_i_p = 2146
13678 CEFBS_None, // S2_asr_i_p_acc = 2147
13679 CEFBS_None, // S2_asr_i_p_and = 2148
13680 CEFBS_None, // S2_asr_i_p_nac = 2149
13681 CEFBS_None, // S2_asr_i_p_or = 2150
13682 CEFBS_None, // S2_asr_i_p_rnd = 2151
13683 CEFBS_None, // S2_asr_i_r = 2152
13684 CEFBS_None, // S2_asr_i_r_acc = 2153
13685 CEFBS_None, // S2_asr_i_r_and = 2154
13686 CEFBS_None, // S2_asr_i_r_nac = 2155
13687 CEFBS_None, // S2_asr_i_r_or = 2156
13688 CEFBS_None, // S2_asr_i_r_rnd = 2157
13689 CEFBS_None, // S2_asr_i_svw_trun = 2158
13690 CEFBS_None, // S2_asr_i_vh = 2159
13691 CEFBS_None, // S2_asr_i_vw = 2160
13692 CEFBS_None, // S2_asr_r_p = 2161
13693 CEFBS_None, // S2_asr_r_p_acc = 2162
13694 CEFBS_None, // S2_asr_r_p_and = 2163
13695 CEFBS_None, // S2_asr_r_p_nac = 2164
13696 CEFBS_None, // S2_asr_r_p_or = 2165
13697 CEFBS_None, // S2_asr_r_p_xor = 2166
13698 CEFBS_None, // S2_asr_r_r = 2167
13699 CEFBS_None, // S2_asr_r_r_acc = 2168
13700 CEFBS_None, // S2_asr_r_r_and = 2169
13701 CEFBS_None, // S2_asr_r_r_nac = 2170
13702 CEFBS_None, // S2_asr_r_r_or = 2171
13703 CEFBS_None, // S2_asr_r_r_sat = 2172
13704 CEFBS_None, // S2_asr_r_svw_trun = 2173
13705 CEFBS_None, // S2_asr_r_vh = 2174
13706 CEFBS_None, // S2_asr_r_vw = 2175
13707 CEFBS_None, // S2_brev = 2176
13708 CEFBS_None, // S2_brevp = 2177
13709 CEFBS_UseCabac, // S2_cabacdecbin = 2178
13710 CEFBS_None, // S2_cl0 = 2179
13711 CEFBS_None, // S2_cl0p = 2180
13712 CEFBS_None, // S2_cl1 = 2181
13713 CEFBS_None, // S2_cl1p = 2182
13714 CEFBS_None, // S2_clb = 2183
13715 CEFBS_None, // S2_clbnorm = 2184
13716 CEFBS_None, // S2_clbp = 2185
13717 CEFBS_None, // S2_clrbit_i = 2186
13718 CEFBS_None, // S2_clrbit_r = 2187
13719 CEFBS_None, // S2_ct0 = 2188
13720 CEFBS_None, // S2_ct0p = 2189
13721 CEFBS_None, // S2_ct1 = 2190
13722 CEFBS_None, // S2_ct1p = 2191
13723 CEFBS_None, // S2_deinterleave = 2192
13724 CEFBS_None, // S2_extractu = 2193
13725 CEFBS_None, // S2_extractu_rp = 2194
13726 CEFBS_None, // S2_extractup = 2195
13727 CEFBS_None, // S2_extractup_rp = 2196
13728 CEFBS_None, // S2_insert = 2197
13729 CEFBS_None, // S2_insert_rp = 2198
13730 CEFBS_None, // S2_insertp = 2199
13731 CEFBS_None, // S2_insertp_rp = 2200
13732 CEFBS_None, // S2_interleave = 2201
13733 CEFBS_None, // S2_lfsp = 2202
13734 CEFBS_None, // S2_lsl_r_p = 2203
13735 CEFBS_None, // S2_lsl_r_p_acc = 2204
13736 CEFBS_None, // S2_lsl_r_p_and = 2205
13737 CEFBS_None, // S2_lsl_r_p_nac = 2206
13738 CEFBS_None, // S2_lsl_r_p_or = 2207
13739 CEFBS_None, // S2_lsl_r_p_xor = 2208
13740 CEFBS_None, // S2_lsl_r_r = 2209
13741 CEFBS_None, // S2_lsl_r_r_acc = 2210
13742 CEFBS_None, // S2_lsl_r_r_and = 2211
13743 CEFBS_None, // S2_lsl_r_r_nac = 2212
13744 CEFBS_None, // S2_lsl_r_r_or = 2213
13745 CEFBS_None, // S2_lsl_r_vh = 2214
13746 CEFBS_None, // S2_lsl_r_vw = 2215
13747 CEFBS_None, // S2_lsr_i_p = 2216
13748 CEFBS_None, // S2_lsr_i_p_acc = 2217
13749 CEFBS_None, // S2_lsr_i_p_and = 2218
13750 CEFBS_None, // S2_lsr_i_p_nac = 2219
13751 CEFBS_None, // S2_lsr_i_p_or = 2220
13752 CEFBS_None, // S2_lsr_i_p_xacc = 2221
13753 CEFBS_None, // S2_lsr_i_r = 2222
13754 CEFBS_None, // S2_lsr_i_r_acc = 2223
13755 CEFBS_None, // S2_lsr_i_r_and = 2224
13756 CEFBS_None, // S2_lsr_i_r_nac = 2225
13757 CEFBS_None, // S2_lsr_i_r_or = 2226
13758 CEFBS_None, // S2_lsr_i_r_xacc = 2227
13759 CEFBS_None, // S2_lsr_i_vh = 2228
13760 CEFBS_None, // S2_lsr_i_vw = 2229
13761 CEFBS_None, // S2_lsr_r_p = 2230
13762 CEFBS_None, // S2_lsr_r_p_acc = 2231
13763 CEFBS_None, // S2_lsr_r_p_and = 2232
13764 CEFBS_None, // S2_lsr_r_p_nac = 2233
13765 CEFBS_None, // S2_lsr_r_p_or = 2234
13766 CEFBS_None, // S2_lsr_r_p_xor = 2235
13767 CEFBS_None, // S2_lsr_r_r = 2236
13768 CEFBS_None, // S2_lsr_r_r_acc = 2237
13769 CEFBS_None, // S2_lsr_r_r_and = 2238
13770 CEFBS_None, // S2_lsr_r_r_nac = 2239
13771 CEFBS_None, // S2_lsr_r_r_or = 2240
13772 CEFBS_None, // S2_lsr_r_vh = 2241
13773 CEFBS_None, // S2_lsr_r_vw = 2242
13774 CEFBS_HasV66, // S2_mask = 2243
13775 CEFBS_None, // S2_packhl = 2244
13776 CEFBS_None, // S2_parityp = 2245
13777 CEFBS_None, // S2_pstorerbf_io = 2246
13778 CEFBS_None, // S2_pstorerbf_pi = 2247
13779 CEFBS_None, // S2_pstorerbfnew_pi = 2248
13780 CEFBS_None, // S2_pstorerbnewf_io = 2249
13781 CEFBS_None, // S2_pstorerbnewf_pi = 2250
13782 CEFBS_None, // S2_pstorerbnewfnew_pi = 2251
13783 CEFBS_None, // S2_pstorerbnewt_io = 2252
13784 CEFBS_None, // S2_pstorerbnewt_pi = 2253
13785 CEFBS_None, // S2_pstorerbnewtnew_pi = 2254
13786 CEFBS_None, // S2_pstorerbt_io = 2255
13787 CEFBS_None, // S2_pstorerbt_pi = 2256
13788 CEFBS_None, // S2_pstorerbtnew_pi = 2257
13789 CEFBS_None, // S2_pstorerdf_io = 2258
13790 CEFBS_None, // S2_pstorerdf_pi = 2259
13791 CEFBS_None, // S2_pstorerdfnew_pi = 2260
13792 CEFBS_None, // S2_pstorerdt_io = 2261
13793 CEFBS_None, // S2_pstorerdt_pi = 2262
13794 CEFBS_None, // S2_pstorerdtnew_pi = 2263
13795 CEFBS_None, // S2_pstorerff_io = 2264
13796 CEFBS_None, // S2_pstorerff_pi = 2265
13797 CEFBS_None, // S2_pstorerffnew_pi = 2266
13798 CEFBS_None, // S2_pstorerft_io = 2267
13799 CEFBS_None, // S2_pstorerft_pi = 2268
13800 CEFBS_None, // S2_pstorerftnew_pi = 2269
13801 CEFBS_None, // S2_pstorerhf_io = 2270
13802 CEFBS_None, // S2_pstorerhf_pi = 2271
13803 CEFBS_None, // S2_pstorerhfnew_pi = 2272
13804 CEFBS_None, // S2_pstorerhnewf_io = 2273
13805 CEFBS_None, // S2_pstorerhnewf_pi = 2274
13806 CEFBS_None, // S2_pstorerhnewfnew_pi = 2275
13807 CEFBS_None, // S2_pstorerhnewt_io = 2276
13808 CEFBS_None, // S2_pstorerhnewt_pi = 2277
13809 CEFBS_None, // S2_pstorerhnewtnew_pi = 2278
13810 CEFBS_None, // S2_pstorerht_io = 2279
13811 CEFBS_None, // S2_pstorerht_pi = 2280
13812 CEFBS_None, // S2_pstorerhtnew_pi = 2281
13813 CEFBS_None, // S2_pstorerif_io = 2282
13814 CEFBS_None, // S2_pstorerif_pi = 2283
13815 CEFBS_None, // S2_pstorerifnew_pi = 2284
13816 CEFBS_None, // S2_pstorerinewf_io = 2285
13817 CEFBS_None, // S2_pstorerinewf_pi = 2286
13818 CEFBS_None, // S2_pstorerinewfnew_pi = 2287
13819 CEFBS_None, // S2_pstorerinewt_io = 2288
13820 CEFBS_None, // S2_pstorerinewt_pi = 2289
13821 CEFBS_None, // S2_pstorerinewtnew_pi = 2290
13822 CEFBS_None, // S2_pstorerit_io = 2291
13823 CEFBS_None, // S2_pstorerit_pi = 2292
13824 CEFBS_None, // S2_pstoreritnew_pi = 2293
13825 CEFBS_None, // S2_setbit_i = 2294
13826 CEFBS_None, // S2_setbit_r = 2295
13827 CEFBS_None, // S2_shuffeb = 2296
13828 CEFBS_None, // S2_shuffeh = 2297
13829 CEFBS_None, // S2_shuffob = 2298
13830 CEFBS_None, // S2_shuffoh = 2299
13831 CEFBS_None, // S2_storerb_io = 2300
13832 CEFBS_None, // S2_storerb_pbr = 2301
13833 CEFBS_None, // S2_storerb_pci = 2302
13834 CEFBS_None, // S2_storerb_pcr = 2303
13835 CEFBS_None, // S2_storerb_pi = 2304
13836 CEFBS_None, // S2_storerb_pr = 2305
13837 CEFBS_None, // S2_storerbgp = 2306
13838 CEFBS_None, // S2_storerbnew_io = 2307
13839 CEFBS_None, // S2_storerbnew_pbr = 2308
13840 CEFBS_None, // S2_storerbnew_pci = 2309
13841 CEFBS_None, // S2_storerbnew_pcr = 2310
13842 CEFBS_None, // S2_storerbnew_pi = 2311
13843 CEFBS_None, // S2_storerbnew_pr = 2312
13844 CEFBS_None, // S2_storerbnewgp = 2313
13845 CEFBS_None, // S2_storerd_io = 2314
13846 CEFBS_None, // S2_storerd_pbr = 2315
13847 CEFBS_None, // S2_storerd_pci = 2316
13848 CEFBS_None, // S2_storerd_pcr = 2317
13849 CEFBS_None, // S2_storerd_pi = 2318
13850 CEFBS_None, // S2_storerd_pr = 2319
13851 CEFBS_None, // S2_storerdgp = 2320
13852 CEFBS_None, // S2_storerf_io = 2321
13853 CEFBS_None, // S2_storerf_pbr = 2322
13854 CEFBS_None, // S2_storerf_pci = 2323
13855 CEFBS_None, // S2_storerf_pcr = 2324
13856 CEFBS_None, // S2_storerf_pi = 2325
13857 CEFBS_None, // S2_storerf_pr = 2326
13858 CEFBS_None, // S2_storerfgp = 2327
13859 CEFBS_None, // S2_storerh_io = 2328
13860 CEFBS_None, // S2_storerh_pbr = 2329
13861 CEFBS_None, // S2_storerh_pci = 2330
13862 CEFBS_None, // S2_storerh_pcr = 2331
13863 CEFBS_None, // S2_storerh_pi = 2332
13864 CEFBS_None, // S2_storerh_pr = 2333
13865 CEFBS_None, // S2_storerhgp = 2334
13866 CEFBS_None, // S2_storerhnew_io = 2335
13867 CEFBS_None, // S2_storerhnew_pbr = 2336
13868 CEFBS_None, // S2_storerhnew_pci = 2337
13869 CEFBS_None, // S2_storerhnew_pcr = 2338
13870 CEFBS_None, // S2_storerhnew_pi = 2339
13871 CEFBS_None, // S2_storerhnew_pr = 2340
13872 CEFBS_None, // S2_storerhnewgp = 2341
13873 CEFBS_None, // S2_storeri_io = 2342
13874 CEFBS_None, // S2_storeri_pbr = 2343
13875 CEFBS_None, // S2_storeri_pci = 2344
13876 CEFBS_None, // S2_storeri_pcr = 2345
13877 CEFBS_None, // S2_storeri_pi = 2346
13878 CEFBS_None, // S2_storeri_pr = 2347
13879 CEFBS_None, // S2_storerigp = 2348
13880 CEFBS_None, // S2_storerinew_io = 2349
13881 CEFBS_None, // S2_storerinew_pbr = 2350
13882 CEFBS_None, // S2_storerinew_pci = 2351
13883 CEFBS_None, // S2_storerinew_pcr = 2352
13884 CEFBS_None, // S2_storerinew_pi = 2353
13885 CEFBS_None, // S2_storerinew_pr = 2354
13886 CEFBS_None, // S2_storerinewgp = 2355
13887 CEFBS_None, // S2_storew_locked = 2356
13888 CEFBS_HasV68, // S2_storew_rl_at_vi = 2357
13889 CEFBS_HasV68, // S2_storew_rl_st_vi = 2358
13890 CEFBS_None, // S2_svsathb = 2359
13891 CEFBS_None, // S2_svsathub = 2360
13892 CEFBS_None, // S2_tableidxb = 2361
13893 CEFBS_None, // S2_tableidxd = 2362
13894 CEFBS_None, // S2_tableidxh = 2363
13895 CEFBS_None, // S2_tableidxw = 2364
13896 CEFBS_None, // S2_togglebit_i = 2365
13897 CEFBS_None, // S2_togglebit_r = 2366
13898 CEFBS_None, // S2_tstbit_i = 2367
13899 CEFBS_None, // S2_tstbit_r = 2368
13900 CEFBS_None, // S2_valignib = 2369
13901 CEFBS_None, // S2_valignrb = 2370
13902 CEFBS_None, // S2_vcnegh = 2371
13903 CEFBS_None, // S2_vcrotate = 2372
13904 CEFBS_None, // S2_vrcnegh = 2373
13905 CEFBS_None, // S2_vrndpackwh = 2374
13906 CEFBS_None, // S2_vrndpackwhs = 2375
13907 CEFBS_None, // S2_vsathb = 2376
13908 CEFBS_None, // S2_vsathb_nopack = 2377
13909 CEFBS_None, // S2_vsathub = 2378
13910 CEFBS_None, // S2_vsathub_nopack = 2379
13911 CEFBS_None, // S2_vsatwh = 2380
13912 CEFBS_None, // S2_vsatwh_nopack = 2381
13913 CEFBS_None, // S2_vsatwuh = 2382
13914 CEFBS_None, // S2_vsatwuh_nopack = 2383
13915 CEFBS_None, // S2_vsplatrb = 2384
13916 CEFBS_None, // S2_vsplatrh = 2385
13917 CEFBS_None, // S2_vspliceib = 2386
13918 CEFBS_None, // S2_vsplicerb = 2387
13919 CEFBS_None, // S2_vsxtbh = 2388
13920 CEFBS_None, // S2_vsxthw = 2389
13921 CEFBS_None, // S2_vtrunehb = 2390
13922 CEFBS_None, // S2_vtrunewh = 2391
13923 CEFBS_None, // S2_vtrunohb = 2392
13924 CEFBS_None, // S2_vtrunowh = 2393
13925 CEFBS_None, // S2_vzxtbh = 2394
13926 CEFBS_None, // S2_vzxthw = 2395
13927 CEFBS_None, // S4_addaddi = 2396
13928 CEFBS_None, // S4_addi_asl_ri = 2397
13929 CEFBS_None, // S4_addi_lsr_ri = 2398
13930 CEFBS_None, // S4_andi_asl_ri = 2399
13931 CEFBS_None, // S4_andi_lsr_ri = 2400
13932 CEFBS_None, // S4_clbaddi = 2401
13933 CEFBS_None, // S4_clbpaddi = 2402
13934 CEFBS_None, // S4_clbpnorm = 2403
13935 CEFBS_None, // S4_extract = 2404
13936 CEFBS_None, // S4_extract_rp = 2405
13937 CEFBS_None, // S4_extractp = 2406
13938 CEFBS_None, // S4_extractp_rp = 2407
13939 CEFBS_None, // S4_lsli = 2408
13940 CEFBS_None, // S4_ntstbit_i = 2409
13941 CEFBS_None, // S4_ntstbit_r = 2410
13942 CEFBS_None, // S4_or_andi = 2411
13943 CEFBS_None, // S4_or_andix = 2412
13944 CEFBS_None, // S4_or_ori = 2413
13945 CEFBS_None, // S4_ori_asl_ri = 2414
13946 CEFBS_None, // S4_ori_lsr_ri = 2415
13947 CEFBS_None, // S4_parity = 2416
13948 CEFBS_None, // S4_pstorerbf_abs = 2417
13949 CEFBS_None, // S4_pstorerbf_rr = 2418
13950 CEFBS_None, // S4_pstorerbfnew_abs = 2419
13951 CEFBS_None, // S4_pstorerbfnew_io = 2420
13952 CEFBS_None, // S4_pstorerbfnew_rr = 2421
13953 CEFBS_None, // S4_pstorerbnewf_abs = 2422
13954 CEFBS_None, // S4_pstorerbnewf_rr = 2423
13955 CEFBS_None, // S4_pstorerbnewfnew_abs = 2424
13956 CEFBS_None, // S4_pstorerbnewfnew_io = 2425
13957 CEFBS_None, // S4_pstorerbnewfnew_rr = 2426
13958 CEFBS_None, // S4_pstorerbnewt_abs = 2427
13959 CEFBS_None, // S4_pstorerbnewt_rr = 2428
13960 CEFBS_None, // S4_pstorerbnewtnew_abs = 2429
13961 CEFBS_None, // S4_pstorerbnewtnew_io = 2430
13962 CEFBS_None, // S4_pstorerbnewtnew_rr = 2431
13963 CEFBS_None, // S4_pstorerbt_abs = 2432
13964 CEFBS_None, // S4_pstorerbt_rr = 2433
13965 CEFBS_None, // S4_pstorerbtnew_abs = 2434
13966 CEFBS_None, // S4_pstorerbtnew_io = 2435
13967 CEFBS_None, // S4_pstorerbtnew_rr = 2436
13968 CEFBS_None, // S4_pstorerdf_abs = 2437
13969 CEFBS_None, // S4_pstorerdf_rr = 2438
13970 CEFBS_None, // S4_pstorerdfnew_abs = 2439
13971 CEFBS_None, // S4_pstorerdfnew_io = 2440
13972 CEFBS_None, // S4_pstorerdfnew_rr = 2441
13973 CEFBS_None, // S4_pstorerdt_abs = 2442
13974 CEFBS_None, // S4_pstorerdt_rr = 2443
13975 CEFBS_None, // S4_pstorerdtnew_abs = 2444
13976 CEFBS_None, // S4_pstorerdtnew_io = 2445
13977 CEFBS_None, // S4_pstorerdtnew_rr = 2446
13978 CEFBS_None, // S4_pstorerff_abs = 2447
13979 CEFBS_None, // S4_pstorerff_rr = 2448
13980 CEFBS_None, // S4_pstorerffnew_abs = 2449
13981 CEFBS_None, // S4_pstorerffnew_io = 2450
13982 CEFBS_None, // S4_pstorerffnew_rr = 2451
13983 CEFBS_None, // S4_pstorerft_abs = 2452
13984 CEFBS_None, // S4_pstorerft_rr = 2453
13985 CEFBS_None, // S4_pstorerftnew_abs = 2454
13986 CEFBS_None, // S4_pstorerftnew_io = 2455
13987 CEFBS_None, // S4_pstorerftnew_rr = 2456
13988 CEFBS_None, // S4_pstorerhf_abs = 2457
13989 CEFBS_None, // S4_pstorerhf_rr = 2458
13990 CEFBS_None, // S4_pstorerhfnew_abs = 2459
13991 CEFBS_None, // S4_pstorerhfnew_io = 2460
13992 CEFBS_None, // S4_pstorerhfnew_rr = 2461
13993 CEFBS_None, // S4_pstorerhnewf_abs = 2462
13994 CEFBS_None, // S4_pstorerhnewf_rr = 2463
13995 CEFBS_None, // S4_pstorerhnewfnew_abs = 2464
13996 CEFBS_None, // S4_pstorerhnewfnew_io = 2465
13997 CEFBS_None, // S4_pstorerhnewfnew_rr = 2466
13998 CEFBS_None, // S4_pstorerhnewt_abs = 2467
13999 CEFBS_None, // S4_pstorerhnewt_rr = 2468
14000 CEFBS_None, // S4_pstorerhnewtnew_abs = 2469
14001 CEFBS_None, // S4_pstorerhnewtnew_io = 2470
14002 CEFBS_None, // S4_pstorerhnewtnew_rr = 2471
14003 CEFBS_None, // S4_pstorerht_abs = 2472
14004 CEFBS_None, // S4_pstorerht_rr = 2473
14005 CEFBS_None, // S4_pstorerhtnew_abs = 2474
14006 CEFBS_None, // S4_pstorerhtnew_io = 2475
14007 CEFBS_None, // S4_pstorerhtnew_rr = 2476
14008 CEFBS_None, // S4_pstorerif_abs = 2477
14009 CEFBS_None, // S4_pstorerif_rr = 2478
14010 CEFBS_None, // S4_pstorerifnew_abs = 2479
14011 CEFBS_None, // S4_pstorerifnew_io = 2480
14012 CEFBS_None, // S4_pstorerifnew_rr = 2481
14013 CEFBS_None, // S4_pstorerinewf_abs = 2482
14014 CEFBS_None, // S4_pstorerinewf_rr = 2483
14015 CEFBS_None, // S4_pstorerinewfnew_abs = 2484
14016 CEFBS_None, // S4_pstorerinewfnew_io = 2485
14017 CEFBS_None, // S4_pstorerinewfnew_rr = 2486
14018 CEFBS_None, // S4_pstorerinewt_abs = 2487
14019 CEFBS_None, // S4_pstorerinewt_rr = 2488
14020 CEFBS_None, // S4_pstorerinewtnew_abs = 2489
14021 CEFBS_None, // S4_pstorerinewtnew_io = 2490
14022 CEFBS_None, // S4_pstorerinewtnew_rr = 2491
14023 CEFBS_None, // S4_pstorerit_abs = 2492
14024 CEFBS_None, // S4_pstorerit_rr = 2493
14025 CEFBS_None, // S4_pstoreritnew_abs = 2494
14026 CEFBS_None, // S4_pstoreritnew_io = 2495
14027 CEFBS_None, // S4_pstoreritnew_rr = 2496
14028 CEFBS_None, // S4_stored_locked = 2497
14029 CEFBS_HasV68, // S4_stored_rl_at_vi = 2498
14030 CEFBS_HasV68, // S4_stored_rl_st_vi = 2499
14031 CEFBS_None, // S4_storeirb_io = 2500
14032 CEFBS_None, // S4_storeirbf_io = 2501
14033 CEFBS_None, // S4_storeirbfnew_io = 2502
14034 CEFBS_None, // S4_storeirbt_io = 2503
14035 CEFBS_None, // S4_storeirbtnew_io = 2504
14036 CEFBS_None, // S4_storeirh_io = 2505
14037 CEFBS_None, // S4_storeirhf_io = 2506
14038 CEFBS_None, // S4_storeirhfnew_io = 2507
14039 CEFBS_None, // S4_storeirht_io = 2508
14040 CEFBS_None, // S4_storeirhtnew_io = 2509
14041 CEFBS_None, // S4_storeiri_io = 2510
14042 CEFBS_None, // S4_storeirif_io = 2511
14043 CEFBS_None, // S4_storeirifnew_io = 2512
14044 CEFBS_None, // S4_storeirit_io = 2513
14045 CEFBS_None, // S4_storeiritnew_io = 2514
14046 CEFBS_None, // S4_storerb_ap = 2515
14047 CEFBS_None, // S4_storerb_rr = 2516
14048 CEFBS_None, // S4_storerb_ur = 2517
14049 CEFBS_None, // S4_storerbnew_ap = 2518
14050 CEFBS_None, // S4_storerbnew_rr = 2519
14051 CEFBS_None, // S4_storerbnew_ur = 2520
14052 CEFBS_None, // S4_storerd_ap = 2521
14053 CEFBS_None, // S4_storerd_rr = 2522
14054 CEFBS_None, // S4_storerd_ur = 2523
14055 CEFBS_None, // S4_storerf_ap = 2524
14056 CEFBS_None, // S4_storerf_rr = 2525
14057 CEFBS_None, // S4_storerf_ur = 2526
14058 CEFBS_None, // S4_storerh_ap = 2527
14059 CEFBS_None, // S4_storerh_rr = 2528
14060 CEFBS_None, // S4_storerh_ur = 2529
14061 CEFBS_None, // S4_storerhnew_ap = 2530
14062 CEFBS_None, // S4_storerhnew_rr = 2531
14063 CEFBS_None, // S4_storerhnew_ur = 2532
14064 CEFBS_None, // S4_storeri_ap = 2533
14065 CEFBS_None, // S4_storeri_rr = 2534
14066 CEFBS_None, // S4_storeri_ur = 2535
14067 CEFBS_None, // S4_storerinew_ap = 2536
14068 CEFBS_None, // S4_storerinew_rr = 2537
14069 CEFBS_None, // S4_storerinew_ur = 2538
14070 CEFBS_None, // S4_subaddi = 2539
14071 CEFBS_None, // S4_subi_asl_ri = 2540
14072 CEFBS_None, // S4_subi_lsr_ri = 2541
14073 CEFBS_None, // S4_vrcrotate = 2542
14074 CEFBS_None, // S4_vrcrotate_acc = 2543
14075 CEFBS_None, // S4_vxaddsubh = 2544
14076 CEFBS_None, // S4_vxaddsubhr = 2545
14077 CEFBS_None, // S4_vxaddsubw = 2546
14078 CEFBS_None, // S4_vxsubaddh = 2547
14079 CEFBS_None, // S4_vxsubaddhr = 2548
14080 CEFBS_None, // S4_vxsubaddw = 2549
14081 CEFBS_None, // S5_asrhub_rnd_sat = 2550
14082 CEFBS_None, // S5_asrhub_sat = 2551
14083 CEFBS_None, // S5_popcountp = 2552
14084 CEFBS_None, // S5_vasrhrnd = 2553
14085 CEFBS_HasV60, // S6_rol_i_p = 2554
14086 CEFBS_HasV60, // S6_rol_i_p_acc = 2555
14087 CEFBS_HasV60, // S6_rol_i_p_and = 2556
14088 CEFBS_HasV60, // S6_rol_i_p_nac = 2557
14089 CEFBS_HasV60, // S6_rol_i_p_or = 2558
14090 CEFBS_HasV60, // S6_rol_i_p_xacc = 2559
14091 CEFBS_HasV60, // S6_rol_i_r = 2560
14092 CEFBS_HasV60, // S6_rol_i_r_acc = 2561
14093 CEFBS_HasV60, // S6_rol_i_r_and = 2562
14094 CEFBS_HasV60, // S6_rol_i_r_nac = 2563
14095 CEFBS_HasV60, // S6_rol_i_r_or = 2564
14096 CEFBS_HasV60, // S6_rol_i_r_xacc = 2565
14097 CEFBS_HasV62, // S6_vsplatrbp = 2566
14098 CEFBS_HasV62, // S6_vtrunehb_ppp = 2567
14099 CEFBS_HasV62, // S6_vtrunohb_ppp = 2568
14100 CEFBS_None, // SA1_addi = 2569
14101 CEFBS_None, // SA1_addrx = 2570
14102 CEFBS_None, // SA1_addsp = 2571
14103 CEFBS_None, // SA1_and1 = 2572
14104 CEFBS_None, // SA1_clrf = 2573
14105 CEFBS_None, // SA1_clrfnew = 2574
14106 CEFBS_None, // SA1_clrt = 2575
14107 CEFBS_None, // SA1_clrtnew = 2576
14108 CEFBS_None, // SA1_cmpeqi = 2577
14109 CEFBS_None, // SA1_combine0i = 2578
14110 CEFBS_None, // SA1_combine1i = 2579
14111 CEFBS_None, // SA1_combine2i = 2580
14112 CEFBS_None, // SA1_combine3i = 2581
14113 CEFBS_None, // SA1_combinerz = 2582
14114 CEFBS_None, // SA1_combinezr = 2583
14115 CEFBS_None, // SA1_dec = 2584
14116 CEFBS_None, // SA1_inc = 2585
14117 CEFBS_None, // SA1_seti = 2586
14118 CEFBS_None, // SA1_setin1 = 2587
14119 CEFBS_None, // SA1_sxtb = 2588
14120 CEFBS_None, // SA1_sxth = 2589
14121 CEFBS_None, // SA1_tfr = 2590
14122 CEFBS_None, // SA1_zxtb = 2591
14123 CEFBS_None, // SA1_zxth = 2592
14124 CEFBS_None, // SAVE_REGISTERS_CALL_V4 = 2593
14125 CEFBS_None, // SAVE_REGISTERS_CALL_V4STK = 2594
14126 CEFBS_None, // SAVE_REGISTERS_CALL_V4STK_EXT = 2595
14127 CEFBS_None, // SAVE_REGISTERS_CALL_V4STK_EXT_PIC = 2596
14128 CEFBS_None, // SAVE_REGISTERS_CALL_V4STK_PIC = 2597
14129 CEFBS_None, // SAVE_REGISTERS_CALL_V4_EXT = 2598
14130 CEFBS_None, // SAVE_REGISTERS_CALL_V4_EXT_PIC = 2599
14131 CEFBS_None, // SAVE_REGISTERS_CALL_V4_PIC = 2600
14132 CEFBS_None, // SL1_loadri_io = 2601
14133 CEFBS_None, // SL1_loadrub_io = 2602
14134 CEFBS_None, // SL2_deallocframe = 2603
14135 CEFBS_None, // SL2_jumpr31 = 2604
14136 CEFBS_None, // SL2_jumpr31_f = 2605
14137 CEFBS_None, // SL2_jumpr31_fnew = 2606
14138 CEFBS_None, // SL2_jumpr31_t = 2607
14139 CEFBS_None, // SL2_jumpr31_tnew = 2608
14140 CEFBS_None, // SL2_loadrb_io = 2609
14141 CEFBS_None, // SL2_loadrd_sp = 2610
14142 CEFBS_None, // SL2_loadrh_io = 2611
14143 CEFBS_None, // SL2_loadri_sp = 2612
14144 CEFBS_None, // SL2_loadruh_io = 2613
14145 CEFBS_None, // SL2_return = 2614
14146 CEFBS_None, // SL2_return_f = 2615
14147 CEFBS_None, // SL2_return_fnew = 2616
14148 CEFBS_None, // SL2_return_t = 2617
14149 CEFBS_None, // SL2_return_tnew = 2618
14150 CEFBS_None, // SS1_storeb_io = 2619
14151 CEFBS_None, // SS1_storew_io = 2620
14152 CEFBS_None, // SS2_allocframe = 2621
14153 CEFBS_None, // SS2_storebi0 = 2622
14154 CEFBS_None, // SS2_storebi1 = 2623
14155 CEFBS_None, // SS2_stored_sp = 2624
14156 CEFBS_None, // SS2_storeh_io = 2625
14157 CEFBS_None, // SS2_storew_sp = 2626
14158 CEFBS_None, // SS2_storewi0 = 2627
14159 CEFBS_None, // SS2_storewi1 = 2628
14160 CEFBS_None, // TFRI64_V2_ext = 2629
14161 CEFBS_None, // TFRI64_V4 = 2630
14162 CEFBS_UseHVXV60, // V6_extractw = 2631
14163 CEFBS_UseHVXV79_UseHVXQFloat, // V6_get_qfext = 2632
14164 CEFBS_UseHVXV79_UseHVXQFloat, // V6_get_qfext_oracc = 2633
14165 CEFBS_UseHVXV62, // V6_lvsplatb = 2634
14166 CEFBS_UseHVXV62, // V6_lvsplath = 2635
14167 CEFBS_UseHVXV60, // V6_lvsplatw = 2636
14168 CEFBS_UseHVXV60, // V6_pred_and = 2637
14169 CEFBS_UseHVXV60, // V6_pred_and_n = 2638
14170 CEFBS_UseHVXV60, // V6_pred_not = 2639
14171 CEFBS_UseHVXV60, // V6_pred_or = 2640
14172 CEFBS_UseHVXV60, // V6_pred_or_n = 2641
14173 CEFBS_UseHVXV60, // V6_pred_scalar2 = 2642
14174 CEFBS_UseHVXV62, // V6_pred_scalar2v2 = 2643
14175 CEFBS_UseHVXV60, // V6_pred_xor = 2644
14176 CEFBS_UseHVXV79_UseHVXQFloat, // V6_set_qfext = 2645
14177 CEFBS_UseHVXV62, // V6_shuffeqh = 2646
14178 CEFBS_UseHVXV62, // V6_shuffeqw = 2647
14179 CEFBS_UseHVXV68, // V6_v6mpyhubs10 = 2648
14180 CEFBS_UseHVXV68, // V6_v6mpyhubs10_vxx = 2649
14181 CEFBS_UseHVXV68, // V6_v6mpyvubs10 = 2650
14182 CEFBS_UseHVXV68, // V6_v6mpyvubs10_vxx = 2651
14183 CEFBS_UseHVXV60, // V6_vL32Ub_ai = 2652
14184 CEFBS_UseHVXV60, // V6_vL32Ub_pi = 2653
14185 CEFBS_UseHVXV60, // V6_vL32Ub_ppu = 2654
14186 CEFBS_UseHVXV60, // V6_vL32b_ai = 2655
14187 CEFBS_UseHVXV60, // V6_vL32b_cur_ai = 2656
14188 CEFBS_UseHVXV62, // V6_vL32b_cur_npred_ai = 2657
14189 CEFBS_UseHVXV62, // V6_vL32b_cur_npred_pi = 2658
14190 CEFBS_UseHVXV62, // V6_vL32b_cur_npred_ppu = 2659
14191 CEFBS_UseHVXV60, // V6_vL32b_cur_pi = 2660
14192 CEFBS_UseHVXV60, // V6_vL32b_cur_ppu = 2661
14193 CEFBS_UseHVXV62, // V6_vL32b_cur_pred_ai = 2662
14194 CEFBS_UseHVXV62, // V6_vL32b_cur_pred_pi = 2663
14195 CEFBS_UseHVXV62, // V6_vL32b_cur_pred_ppu = 2664
14196 CEFBS_UseHVXV62, // V6_vL32b_npred_ai = 2665
14197 CEFBS_UseHVXV62, // V6_vL32b_npred_pi = 2666
14198 CEFBS_UseHVXV62, // V6_vL32b_npred_ppu = 2667
14199 CEFBS_UseHVXV60, // V6_vL32b_nt_ai = 2668
14200 CEFBS_UseHVXV60, // V6_vL32b_nt_cur_ai = 2669
14201 CEFBS_UseHVXV62, // V6_vL32b_nt_cur_npred_ai = 2670
14202 CEFBS_UseHVXV62, // V6_vL32b_nt_cur_npred_pi = 2671
14203 CEFBS_UseHVXV62, // V6_vL32b_nt_cur_npred_ppu = 2672
14204 CEFBS_UseHVXV60, // V6_vL32b_nt_cur_pi = 2673
14205 CEFBS_UseHVXV60, // V6_vL32b_nt_cur_ppu = 2674
14206 CEFBS_UseHVXV62, // V6_vL32b_nt_cur_pred_ai = 2675
14207 CEFBS_UseHVXV62, // V6_vL32b_nt_cur_pred_pi = 2676
14208 CEFBS_UseHVXV62, // V6_vL32b_nt_cur_pred_ppu = 2677
14209 CEFBS_UseHVXV62, // V6_vL32b_nt_npred_ai = 2678
14210 CEFBS_UseHVXV62, // V6_vL32b_nt_npred_pi = 2679
14211 CEFBS_UseHVXV62, // V6_vL32b_nt_npred_ppu = 2680
14212 CEFBS_UseHVXV60, // V6_vL32b_nt_pi = 2681
14213 CEFBS_UseHVXV60, // V6_vL32b_nt_ppu = 2682
14214 CEFBS_UseHVXV62, // V6_vL32b_nt_pred_ai = 2683
14215 CEFBS_UseHVXV62, // V6_vL32b_nt_pred_pi = 2684
14216 CEFBS_UseHVXV62, // V6_vL32b_nt_pred_ppu = 2685
14217 CEFBS_UseHVXV60, // V6_vL32b_nt_tmp_ai = 2686
14218 CEFBS_UseHVXV62, // V6_vL32b_nt_tmp_npred_ai = 2687
14219 CEFBS_UseHVXV62, // V6_vL32b_nt_tmp_npred_pi = 2688
14220 CEFBS_UseHVXV62, // V6_vL32b_nt_tmp_npred_ppu = 2689
14221 CEFBS_UseHVXV60, // V6_vL32b_nt_tmp_pi = 2690
14222 CEFBS_UseHVXV60, // V6_vL32b_nt_tmp_ppu = 2691
14223 CEFBS_UseHVXV62, // V6_vL32b_nt_tmp_pred_ai = 2692
14224 CEFBS_UseHVXV62, // V6_vL32b_nt_tmp_pred_pi = 2693
14225 CEFBS_UseHVXV62, // V6_vL32b_nt_tmp_pred_ppu = 2694
14226 CEFBS_UseHVXV60, // V6_vL32b_pi = 2695
14227 CEFBS_UseHVXV60, // V6_vL32b_ppu = 2696
14228 CEFBS_UseHVXV62, // V6_vL32b_pred_ai = 2697
14229 CEFBS_UseHVXV62, // V6_vL32b_pred_pi = 2698
14230 CEFBS_UseHVXV62, // V6_vL32b_pred_ppu = 2699
14231 CEFBS_UseHVXV60, // V6_vL32b_tmp_ai = 2700
14232 CEFBS_UseHVXV62, // V6_vL32b_tmp_npred_ai = 2701
14233 CEFBS_UseHVXV62, // V6_vL32b_tmp_npred_pi = 2702
14234 CEFBS_UseHVXV62, // V6_vL32b_tmp_npred_ppu = 2703
14235 CEFBS_UseHVXV60, // V6_vL32b_tmp_pi = 2704
14236 CEFBS_UseHVXV60, // V6_vL32b_tmp_ppu = 2705
14237 CEFBS_UseHVXV62, // V6_vL32b_tmp_pred_ai = 2706
14238 CEFBS_UseHVXV62, // V6_vL32b_tmp_pred_pi = 2707
14239 CEFBS_UseHVXV62, // V6_vL32b_tmp_pred_ppu = 2708
14240 CEFBS_UseHVXV60, // V6_vS32Ub_ai = 2709
14241 CEFBS_UseHVXV60, // V6_vS32Ub_npred_ai = 2710
14242 CEFBS_UseHVXV60, // V6_vS32Ub_npred_pi = 2711
14243 CEFBS_UseHVXV60, // V6_vS32Ub_npred_ppu = 2712
14244 CEFBS_UseHVXV60, // V6_vS32Ub_pi = 2713
14245 CEFBS_UseHVXV60, // V6_vS32Ub_ppu = 2714
14246 CEFBS_UseHVXV60, // V6_vS32Ub_pred_ai = 2715
14247 CEFBS_UseHVXV60, // V6_vS32Ub_pred_pi = 2716
14248 CEFBS_UseHVXV60, // V6_vS32Ub_pred_ppu = 2717
14249 CEFBS_UseHVXV60, // V6_vS32b_ai = 2718
14250 CEFBS_UseHVXV60, // V6_vS32b_new_ai = 2719
14251 CEFBS_UseHVXV60, // V6_vS32b_new_npred_ai = 2720
14252 CEFBS_UseHVXV60, // V6_vS32b_new_npred_pi = 2721
14253 CEFBS_UseHVXV60, // V6_vS32b_new_npred_ppu = 2722
14254 CEFBS_UseHVXV60, // V6_vS32b_new_pi = 2723
14255 CEFBS_UseHVXV60, // V6_vS32b_new_ppu = 2724
14256 CEFBS_UseHVXV60, // V6_vS32b_new_pred_ai = 2725
14257 CEFBS_UseHVXV60, // V6_vS32b_new_pred_pi = 2726
14258 CEFBS_UseHVXV60, // V6_vS32b_new_pred_ppu = 2727
14259 CEFBS_UseHVXV60, // V6_vS32b_npred_ai = 2728
14260 CEFBS_UseHVXV60, // V6_vS32b_npred_pi = 2729
14261 CEFBS_UseHVXV60, // V6_vS32b_npred_ppu = 2730
14262 CEFBS_UseHVXV60, // V6_vS32b_nqpred_ai = 2731
14263 CEFBS_UseHVXV60, // V6_vS32b_nqpred_pi = 2732
14264 CEFBS_UseHVXV60, // V6_vS32b_nqpred_ppu = 2733
14265 CEFBS_UseHVXV60, // V6_vS32b_nt_ai = 2734
14266 CEFBS_UseHVXV60, // V6_vS32b_nt_new_ai = 2735
14267 CEFBS_UseHVXV60, // V6_vS32b_nt_new_npred_ai = 2736
14268 CEFBS_UseHVXV60, // V6_vS32b_nt_new_npred_pi = 2737
14269 CEFBS_UseHVXV60, // V6_vS32b_nt_new_npred_ppu = 2738
14270 CEFBS_UseHVXV60, // V6_vS32b_nt_new_pi = 2739
14271 CEFBS_UseHVXV60, // V6_vS32b_nt_new_ppu = 2740
14272 CEFBS_UseHVXV60, // V6_vS32b_nt_new_pred_ai = 2741
14273 CEFBS_UseHVXV60, // V6_vS32b_nt_new_pred_pi = 2742
14274 CEFBS_UseHVXV60, // V6_vS32b_nt_new_pred_ppu = 2743
14275 CEFBS_UseHVXV60, // V6_vS32b_nt_npred_ai = 2744
14276 CEFBS_UseHVXV60, // V6_vS32b_nt_npred_pi = 2745
14277 CEFBS_UseHVXV60, // V6_vS32b_nt_npred_ppu = 2746
14278 CEFBS_UseHVXV60, // V6_vS32b_nt_nqpred_ai = 2747
14279 CEFBS_UseHVXV60, // V6_vS32b_nt_nqpred_pi = 2748
14280 CEFBS_UseHVXV60, // V6_vS32b_nt_nqpred_ppu = 2749
14281 CEFBS_UseHVXV60, // V6_vS32b_nt_pi = 2750
14282 CEFBS_UseHVXV60, // V6_vS32b_nt_ppu = 2751
14283 CEFBS_UseHVXV60, // V6_vS32b_nt_pred_ai = 2752
14284 CEFBS_UseHVXV60, // V6_vS32b_nt_pred_pi = 2753
14285 CEFBS_UseHVXV60, // V6_vS32b_nt_pred_ppu = 2754
14286 CEFBS_UseHVXV60, // V6_vS32b_nt_qpred_ai = 2755
14287 CEFBS_UseHVXV60, // V6_vS32b_nt_qpred_pi = 2756
14288 CEFBS_UseHVXV60, // V6_vS32b_nt_qpred_ppu = 2757
14289 CEFBS_UseHVXV60, // V6_vS32b_pi = 2758
14290 CEFBS_UseHVXV60, // V6_vS32b_ppu = 2759
14291 CEFBS_UseHVXV60, // V6_vS32b_pred_ai = 2760
14292 CEFBS_UseHVXV60, // V6_vS32b_pred_pi = 2761
14293 CEFBS_UseHVXV60, // V6_vS32b_pred_ppu = 2762
14294 CEFBS_UseHVXV60, // V6_vS32b_qpred_ai = 2763
14295 CEFBS_UseHVXV60, // V6_vS32b_qpred_pi = 2764
14296 CEFBS_UseHVXV60, // V6_vS32b_qpred_ppu = 2765
14297 CEFBS_UseHVXV65, // V6_vS32b_srls_ai = 2766
14298 CEFBS_UseHVXV65, // V6_vS32b_srls_pi = 2767
14299 CEFBS_UseHVXV65, // V6_vS32b_srls_ppu = 2768
14300 CEFBS_UseHVXV79_UseHVXIEEEFP, // V6_vabs_f8 = 2769
14301 CEFBS_UseHVXV68_UseHVXIEEEFP, // V6_vabs_hf = 2770
14302 CEFBS_UseHVXV68_UseHVXIEEEFP, // V6_vabs_sf = 2771
14303 CEFBS_UseHVXV65, // V6_vabsb = 2772
14304 CEFBS_UseHVXV65, // V6_vabsb_sat = 2773
14305 CEFBS_UseHVXV60, // V6_vabsdiffh = 2774
14306 CEFBS_UseHVXV60, // V6_vabsdiffub = 2775
14307 CEFBS_UseHVXV60, // V6_vabsdiffuh = 2776
14308 CEFBS_UseHVXV60, // V6_vabsdiffw = 2777
14309 CEFBS_UseHVXV60, // V6_vabsh = 2778
14310 CEFBS_UseHVXV60, // V6_vabsh_sat = 2779
14311 CEFBS_UseHVXV60, // V6_vabsw = 2780
14312 CEFBS_UseHVXV60, // V6_vabsw_sat = 2781
14313 CEFBS_UseHVXV68_UseHVXQFloat, // V6_vadd_hf = 2782
14314 CEFBS_UseHVXV79_UseHVXIEEEFP, // V6_vadd_hf_f8 = 2783
14315 CEFBS_UseHVXV68_UseHVXIEEEFP, // V6_vadd_hf_hf = 2784
14316 CEFBS_UseHVXV68_UseHVXQFloat, // V6_vadd_qf16 = 2785
14317 CEFBS_UseHVXV68_UseHVXQFloat, // V6_vadd_qf16_mix = 2786
14318 CEFBS_UseHVXV68_UseHVXQFloat, // V6_vadd_qf32 = 2787
14319 CEFBS_UseHVXV68_UseHVXQFloat, // V6_vadd_qf32_mix = 2788
14320 CEFBS_UseHVXV68_UseHVXQFloat, // V6_vadd_sf = 2789
14321 CEFBS_UseHVXV73_UseHVXIEEEFP, // V6_vadd_sf_bf = 2790
14322 CEFBS_UseHVXV68_UseHVXIEEEFP, // V6_vadd_sf_hf = 2791
14323 CEFBS_UseHVXV68_UseHVXIEEEFP, // V6_vadd_sf_sf = 2792
14324 CEFBS_UseHVXV60, // V6_vaddb = 2793
14325 CEFBS_UseHVXV60, // V6_vaddb_dv = 2794
14326 CEFBS_UseHVXV60, // V6_vaddbnq = 2795
14327 CEFBS_UseHVXV60, // V6_vaddbq = 2796
14328 CEFBS_UseHVXV62, // V6_vaddbsat = 2797
14329 CEFBS_UseHVXV62, // V6_vaddbsat_dv = 2798
14330 CEFBS_UseHVXV62, // V6_vaddcarry = 2799
14331 CEFBS_UseHVXV66, // V6_vaddcarryo = 2800
14332 CEFBS_UseHVXV66, // V6_vaddcarrysat = 2801
14333 CEFBS_UseHVXV62, // V6_vaddclbh = 2802
14334 CEFBS_UseHVXV62, // V6_vaddclbw = 2803
14335 CEFBS_UseHVXV60, // V6_vaddh = 2804
14336 CEFBS_UseHVXV60, // V6_vaddh_dv = 2805
14337 CEFBS_UseHVXV60, // V6_vaddhnq = 2806
14338 CEFBS_UseHVXV60, // V6_vaddhq = 2807
14339 CEFBS_UseHVXV60, // V6_vaddhsat = 2808
14340 CEFBS_UseHVXV60, // V6_vaddhsat_dv = 2809
14341 CEFBS_UseHVXV60, // V6_vaddhw = 2810
14342 CEFBS_UseHVXV62, // V6_vaddhw_acc = 2811
14343 CEFBS_UseHVXV60, // V6_vaddubh = 2812
14344 CEFBS_UseHVXV62, // V6_vaddubh_acc = 2813
14345 CEFBS_UseHVXV60, // V6_vaddubsat = 2814
14346 CEFBS_UseHVXV60, // V6_vaddubsat_dv = 2815
14347 CEFBS_UseHVXV62, // V6_vaddububb_sat = 2816
14348 CEFBS_UseHVXV60, // V6_vadduhsat = 2817
14349 CEFBS_UseHVXV60, // V6_vadduhsat_dv = 2818
14350 CEFBS_UseHVXV60, // V6_vadduhw = 2819
14351 CEFBS_UseHVXV62, // V6_vadduhw_acc = 2820
14352 CEFBS_UseHVXV62, // V6_vadduwsat = 2821
14353 CEFBS_UseHVXV62, // V6_vadduwsat_dv = 2822
14354 CEFBS_UseHVXV60, // V6_vaddw = 2823
14355 CEFBS_UseHVXV60, // V6_vaddw_dv = 2824
14356 CEFBS_UseHVXV60, // V6_vaddwnq = 2825
14357 CEFBS_UseHVXV60, // V6_vaddwq = 2826
14358 CEFBS_UseHVXV60, // V6_vaddwsat = 2827
14359 CEFBS_UseHVXV60, // V6_vaddwsat_dv = 2828
14360 CEFBS_UseHVXV60, // V6_valignb = 2829
14361 CEFBS_UseHVXV60, // V6_valignbi = 2830
14362 CEFBS_UseHVXV60, // V6_vand = 2831
14363 CEFBS_UseHVXV62, // V6_vandnqrt = 2832
14364 CEFBS_UseHVXV62, // V6_vandnqrt_acc = 2833
14365 CEFBS_UseHVXV60, // V6_vandqrt = 2834
14366 CEFBS_UseHVXV60, // V6_vandqrt_acc = 2835
14367 CEFBS_UseHVXV62, // V6_vandvnqv = 2836
14368 CEFBS_UseHVXV62, // V6_vandvqv = 2837
14369 CEFBS_UseHVXV60, // V6_vandvrt = 2838
14370 CEFBS_UseHVXV60, // V6_vandvrt_acc = 2839
14371 CEFBS_UseHVXV60, // V6_vaslh = 2840
14372 CEFBS_UseHVXV65, // V6_vaslh_acc = 2841
14373 CEFBS_UseHVXV60, // V6_vaslhv = 2842
14374 CEFBS_UseHVXV60, // V6_vaslw = 2843
14375 CEFBS_UseHVXV60, // V6_vaslw_acc = 2844
14376 CEFBS_UseHVXV60, // V6_vaslwv = 2845
14377 CEFBS_UseHVXV66, // V6_vasr_into = 2846
14378 CEFBS_UseHVXV60, // V6_vasrh = 2847
14379 CEFBS_UseHVXV65, // V6_vasrh_acc = 2848
14380 CEFBS_UseHVXV60, // V6_vasrhbrndsat = 2849
14381 CEFBS_UseHVXV62, // V6_vasrhbsat = 2850
14382 CEFBS_UseHVXV60, // V6_vasrhubrndsat = 2851
14383 CEFBS_UseHVXV60, // V6_vasrhubsat = 2852
14384 CEFBS_UseHVXV60, // V6_vasrhv = 2853
14385 CEFBS_UseHVXV65, // V6_vasruhubrndsat = 2854
14386 CEFBS_UseHVXV65, // V6_vasruhubsat = 2855
14387 CEFBS_UseHVXV62, // V6_vasruwuhrndsat = 2856
14388 CEFBS_UseHVXV65, // V6_vasruwuhsat = 2857
14389 CEFBS_UseHVXV69, // V6_vasrvuhubrndsat = 2858
14390 CEFBS_UseHVXV69, // V6_vasrvuhubsat = 2859
14391 CEFBS_UseHVXV69, // V6_vasrvwuhrndsat = 2860
14392 CEFBS_UseHVXV69, // V6_vasrvwuhsat = 2861
14393 CEFBS_UseHVXV60, // V6_vasrw = 2862
14394 CEFBS_UseHVXV60, // V6_vasrw_acc = 2863
14395 CEFBS_UseHVXV60, // V6_vasrwh = 2864
14396 CEFBS_UseHVXV60, // V6_vasrwhrndsat = 2865
14397 CEFBS_UseHVXV60, // V6_vasrwhsat = 2866
14398 CEFBS_UseHVXV62, // V6_vasrwuhrndsat = 2867
14399 CEFBS_UseHVXV60, // V6_vasrwuhsat = 2868
14400 CEFBS_UseHVXV60, // V6_vasrwv = 2869
14401 CEFBS_UseHVXV60, // V6_vassign = 2870
14402 CEFBS_UseHVXV68_UseHVXIEEEFP, // V6_vassign_fp = 2871
14403 CEFBS_UseHVXV69, // V6_vassign_tmp = 2872
14404 CEFBS_UseHVXV65, // V6_vavgb = 2873
14405 CEFBS_UseHVXV65, // V6_vavgbrnd = 2874
14406 CEFBS_UseHVXV60, // V6_vavgh = 2875
14407 CEFBS_UseHVXV60, // V6_vavghrnd = 2876
14408 CEFBS_UseHVXV60, // V6_vavgub = 2877
14409 CEFBS_UseHVXV60, // V6_vavgubrnd = 2878
14410 CEFBS_UseHVXV60, // V6_vavguh = 2879
14411 CEFBS_UseHVXV60, // V6_vavguhrnd = 2880
14412 CEFBS_UseHVXV65, // V6_vavguw = 2881
14413 CEFBS_UseHVXV65, // V6_vavguwrnd = 2882
14414 CEFBS_UseHVXV60, // V6_vavgw = 2883
14415 CEFBS_UseHVXV60, // V6_vavgwrnd = 2884
14416 CEFBS_UseHVXV60, // V6_vccombine = 2885
14417 CEFBS_UseHVXV60, // V6_vcl0h = 2886
14418 CEFBS_UseHVXV60, // V6_vcl0w = 2887
14419 CEFBS_UseHVXV60, // V6_vcmov = 2888
14420 CEFBS_UseHVXV60, // V6_vcombine = 2889
14421 CEFBS_UseHVXV69, // V6_vcombine_tmp = 2890
14422 CEFBS_UseHVXV73, // V6_vconv_h_hf = 2891
14423 CEFBS_UseHVXV73, // V6_vconv_hf_h = 2892
14424 CEFBS_UseHVXV68_UseHVXQFloat, // V6_vconv_hf_qf16 = 2893
14425 CEFBS_UseHVXV68_UseHVXQFloat, // V6_vconv_hf_qf32 = 2894
14426 CEFBS_UseHVXV68_UseHVXQFloat, // V6_vconv_sf_qf32 = 2895
14427 CEFBS_UseHVXV73, // V6_vconv_sf_w = 2896
14428 CEFBS_UseHVXV73, // V6_vconv_w_sf = 2897
14429 CEFBS_UseHVXV79_UseHVXIEEEFP, // V6_vcvt2_b_hf = 2898
14430 CEFBS_UseHVXV79_UseHVXIEEEFP, // V6_vcvt2_hf_b = 2899
14431 CEFBS_UseHVXV79_UseHVXIEEEFP, // V6_vcvt2_hf_ub = 2900
14432 CEFBS_UseHVXV79_UseHVXIEEEFP, // V6_vcvt2_ub_hf = 2901
14433 CEFBS_UseHVXV68_UseHVXIEEEFP, // V6_vcvt_b_hf = 2902
14434 CEFBS_UseHVXV73_UseHVXIEEEFP, // V6_vcvt_bf_sf = 2903
14435 CEFBS_UseHVXV79_UseHVXIEEEFP, // V6_vcvt_f8_hf = 2904
14436 CEFBS_UseHVXV68_UseHVXIEEEFP, // V6_vcvt_h_hf = 2905
14437 CEFBS_UseHVXV68_UseHVXIEEEFP, // V6_vcvt_hf_b = 2906
14438 CEFBS_UseHVXV79_UseHVXIEEEFP, // V6_vcvt_hf_f8 = 2907
14439 CEFBS_UseHVXV68_UseHVXIEEEFP, // V6_vcvt_hf_h = 2908
14440 CEFBS_UseHVXV68_UseHVXIEEEFP, // V6_vcvt_hf_sf = 2909
14441 CEFBS_UseHVXV68_UseHVXIEEEFP, // V6_vcvt_hf_ub = 2910
14442 CEFBS_UseHVXV68_UseHVXIEEEFP, // V6_vcvt_hf_uh = 2911
14443 CEFBS_UseHVXV68_UseHVXIEEEFP, // V6_vcvt_sf_hf = 2912
14444 CEFBS_UseHVXV68_UseHVXIEEEFP, // V6_vcvt_ub_hf = 2913
14445 CEFBS_UseHVXV68_UseHVXIEEEFP, // V6_vcvt_uh_hf = 2914
14446 CEFBS_UseHVXV60, // V6_vdeal = 2915
14447 CEFBS_UseHVXV60, // V6_vdealb = 2916
14448 CEFBS_UseHVXV60, // V6_vdealb4w = 2917
14449 CEFBS_UseHVXV60, // V6_vdealh = 2918
14450 CEFBS_UseHVXV60, // V6_vdealvdd = 2919
14451 CEFBS_UseHVXV60, // V6_vdelta = 2920
14452 CEFBS_UseHVXV68_UseHVXIEEEFP, // V6_vdmpy_sf_hf = 2921
14453 CEFBS_UseHVXV68_UseHVXIEEEFP, // V6_vdmpy_sf_hf_acc = 2922
14454 CEFBS_UseHVXV60, // V6_vdmpybus = 2923
14455 CEFBS_UseHVXV60, // V6_vdmpybus_acc = 2924
14456 CEFBS_UseHVXV60, // V6_vdmpybus_dv = 2925
14457 CEFBS_UseHVXV60, // V6_vdmpybus_dv_acc = 2926
14458 CEFBS_UseHVXV60, // V6_vdmpyhb = 2927
14459 CEFBS_UseHVXV60, // V6_vdmpyhb_acc = 2928
14460 CEFBS_UseHVXV60, // V6_vdmpyhb_dv = 2929
14461 CEFBS_UseHVXV60, // V6_vdmpyhb_dv_acc = 2930
14462 CEFBS_UseHVXV60, // V6_vdmpyhisat = 2931
14463 CEFBS_UseHVXV60, // V6_vdmpyhisat_acc = 2932
14464 CEFBS_UseHVXV60, // V6_vdmpyhsat = 2933
14465 CEFBS_UseHVXV60, // V6_vdmpyhsat_acc = 2934
14466 CEFBS_UseHVXV60, // V6_vdmpyhsuisat = 2935
14467 CEFBS_UseHVXV60, // V6_vdmpyhsuisat_acc = 2936
14468 CEFBS_UseHVXV60, // V6_vdmpyhsusat = 2937
14469 CEFBS_UseHVXV60, // V6_vdmpyhsusat_acc = 2938
14470 CEFBS_UseHVXV60, // V6_vdmpyhvsat = 2939
14471 CEFBS_UseHVXV60, // V6_vdmpyhvsat_acc = 2940
14472 CEFBS_UseHVXV60, // V6_vdsaduh = 2941
14473 CEFBS_UseHVXV60, // V6_vdsaduh_acc = 2942
14474 CEFBS_UseHVXV60, // V6_veqb = 2943
14475 CEFBS_UseHVXV60, // V6_veqb_and = 2944
14476 CEFBS_UseHVXV60, // V6_veqb_or = 2945
14477 CEFBS_UseHVXV60, // V6_veqb_xor = 2946
14478 CEFBS_UseHVXV60, // V6_veqh = 2947
14479 CEFBS_UseHVXV60, // V6_veqh_and = 2948
14480 CEFBS_UseHVXV60, // V6_veqh_or = 2949
14481 CEFBS_UseHVXV60, // V6_veqh_xor = 2950
14482 CEFBS_UseHVXV60, // V6_veqw = 2951
14483 CEFBS_UseHVXV60, // V6_veqw_and = 2952
14484 CEFBS_UseHVXV60, // V6_veqw_or = 2953
14485 CEFBS_UseHVXV60, // V6_veqw_xor = 2954
14486 CEFBS_UseHVXV79_UseHVXIEEEFP, // V6_vfmax_f8 = 2955
14487 CEFBS_UseHVXV68_UseHVXIEEEFP, // V6_vfmax_hf = 2956
14488 CEFBS_UseHVXV68_UseHVXIEEEFP, // V6_vfmax_sf = 2957
14489 CEFBS_UseHVXV79_UseHVXIEEEFP, // V6_vfmin_f8 = 2958
14490 CEFBS_UseHVXV68_UseHVXIEEEFP, // V6_vfmin_hf = 2959
14491 CEFBS_UseHVXV68_UseHVXIEEEFP, // V6_vfmin_sf = 2960
14492 CEFBS_UseHVXV79_UseHVXIEEEFP, // V6_vfneg_f8 = 2961
14493 CEFBS_UseHVXV68_UseHVXIEEEFP, // V6_vfneg_hf = 2962
14494 CEFBS_UseHVXV68_UseHVXIEEEFP, // V6_vfneg_sf = 2963
14495 CEFBS_UseHVXV65, // V6_vgathermh = 2964
14496 CEFBS_UseHVXV65, // V6_vgathermhq = 2965
14497 CEFBS_UseHVXV65, // V6_vgathermhw = 2966
14498 CEFBS_UseHVXV65, // V6_vgathermhwq = 2967
14499 CEFBS_UseHVXV65, // V6_vgathermw = 2968
14500 CEFBS_UseHVXV65, // V6_vgathermwq = 2969
14501 CEFBS_UseHVXV60, // V6_vgtb = 2970
14502 CEFBS_UseHVXV60, // V6_vgtb_and = 2971
14503 CEFBS_UseHVXV60, // V6_vgtb_or = 2972
14504 CEFBS_UseHVXV60, // V6_vgtb_xor = 2973
14505 CEFBS_UseHVXV73_UseHVXQFloat, // V6_vgtbf = 2974
14506 CEFBS_UseHVXV73_UseHVXQFloat, // V6_vgtbf_and = 2975
14507 CEFBS_UseHVXV73_UseHVXQFloat, // V6_vgtbf_or = 2976
14508 CEFBS_UseHVXV73_UseHVXQFloat, // V6_vgtbf_xor = 2977
14509 CEFBS_UseHVXV60, // V6_vgth = 2978
14510 CEFBS_UseHVXV60, // V6_vgth_and = 2979
14511 CEFBS_UseHVXV60, // V6_vgth_or = 2980
14512 CEFBS_UseHVXV60, // V6_vgth_xor = 2981
14513 CEFBS_UseHVXV68, // V6_vgthf = 2982
14514 CEFBS_UseHVXV68, // V6_vgthf_and = 2983
14515 CEFBS_UseHVXV68, // V6_vgthf_or = 2984
14516 CEFBS_UseHVXV68, // V6_vgthf_xor = 2985
14517 CEFBS_UseHVXV68, // V6_vgtsf = 2986
14518 CEFBS_UseHVXV68, // V6_vgtsf_and = 2987
14519 CEFBS_UseHVXV68, // V6_vgtsf_or = 2988
14520 CEFBS_UseHVXV68, // V6_vgtsf_xor = 2989
14521 CEFBS_UseHVXV60, // V6_vgtub = 2990
14522 CEFBS_UseHVXV60, // V6_vgtub_and = 2991
14523 CEFBS_UseHVXV60, // V6_vgtub_or = 2992
14524 CEFBS_UseHVXV60, // V6_vgtub_xor = 2993
14525 CEFBS_UseHVXV60, // V6_vgtuh = 2994
14526 CEFBS_UseHVXV60, // V6_vgtuh_and = 2995
14527 CEFBS_UseHVXV60, // V6_vgtuh_or = 2996
14528 CEFBS_UseHVXV60, // V6_vgtuh_xor = 2997
14529 CEFBS_UseHVXV60, // V6_vgtuw = 2998
14530 CEFBS_UseHVXV60, // V6_vgtuw_and = 2999
14531 CEFBS_UseHVXV60, // V6_vgtuw_or = 3000
14532 CEFBS_UseHVXV60, // V6_vgtuw_xor = 3001
14533 CEFBS_UseHVXV60, // V6_vgtw = 3002
14534 CEFBS_UseHVXV60, // V6_vgtw_and = 3003
14535 CEFBS_UseHVXV60, // V6_vgtw_or = 3004
14536 CEFBS_UseHVXV60, // V6_vgtw_xor = 3005
14537 CEFBS_UseHVXV60, // V6_vhist = 3006
14538 CEFBS_UseHVXV60, // V6_vhistq = 3007
14539 CEFBS_UseHVXV60, // V6_vinsertwr = 3008
14540 CEFBS_UseHVXV60, // V6_vlalignb = 3009
14541 CEFBS_UseHVXV60, // V6_vlalignbi = 3010
14542 CEFBS_UseHVXV62, // V6_vlsrb = 3011
14543 CEFBS_UseHVXV60, // V6_vlsrh = 3012
14544 CEFBS_UseHVXV60, // V6_vlsrhv = 3013
14545 CEFBS_UseHVXV60, // V6_vlsrw = 3014
14546 CEFBS_UseHVXV60, // V6_vlsrwv = 3015
14547 CEFBS_UseHVXV65, // V6_vlut4 = 3016
14548 CEFBS_UseHVXV60, // V6_vlutvvb = 3017
14549 CEFBS_UseHVXV62, // V6_vlutvvb_nm = 3018
14550 CEFBS_UseHVXV60, // V6_vlutvvb_oracc = 3019
14551 CEFBS_UseHVXV62, // V6_vlutvvb_oracci = 3020
14552 CEFBS_UseHVXV62, // V6_vlutvvbi = 3021
14553 CEFBS_UseHVXV60, // V6_vlutvwh = 3022
14554 CEFBS_UseHVXV62, // V6_vlutvwh_nm = 3023
14555 CEFBS_UseHVXV60, // V6_vlutvwh_oracc = 3024
14556 CEFBS_UseHVXV62, // V6_vlutvwh_oracci = 3025
14557 CEFBS_UseHVXV62, // V6_vlutvwhi = 3026
14558 CEFBS_UseHVXV73_UseHVXIEEEFP, // V6_vmax_bf = 3027
14559 CEFBS_UseHVXV68_UseHVXQFloat, // V6_vmax_hf = 3028
14560 CEFBS_UseHVXV68_UseHVXQFloat, // V6_vmax_sf = 3029
14561 CEFBS_UseHVXV62, // V6_vmaxb = 3030
14562 CEFBS_UseHVXV60, // V6_vmaxh = 3031
14563 CEFBS_UseHVXV60, // V6_vmaxub = 3032
14564 CEFBS_UseHVXV60, // V6_vmaxuh = 3033
14565 CEFBS_UseHVXV60, // V6_vmaxw = 3034
14566 CEFBS_UseHVXV79_UseHVXQFloat, // V6_vmerge_qf = 3035
14567 CEFBS_UseHVXV73_UseHVXIEEEFP, // V6_vmin_bf = 3036
14568 CEFBS_UseHVXV68_UseHVXQFloat, // V6_vmin_hf = 3037
14569 CEFBS_UseHVXV68_UseHVXQFloat, // V6_vmin_sf = 3038
14570 CEFBS_UseHVXV62, // V6_vminb = 3039
14571 CEFBS_UseHVXV60, // V6_vminh = 3040
14572 CEFBS_UseHVXV60, // V6_vminub = 3041
14573 CEFBS_UseHVXV60, // V6_vminuh = 3042
14574 CEFBS_UseHVXV60, // V6_vminw = 3043
14575 CEFBS_UseHVXV60, // V6_vmpabus = 3044
14576 CEFBS_UseHVXV60, // V6_vmpabus_acc = 3045
14577 CEFBS_UseHVXV60, // V6_vmpabusv = 3046
14578 CEFBS_UseHVXV65, // V6_vmpabuu = 3047
14579 CEFBS_UseHVXV65, // V6_vmpabuu_acc = 3048
14580 CEFBS_UseHVXV60, // V6_vmpabuuv = 3049
14581 CEFBS_UseHVXV60, // V6_vmpahb = 3050
14582 CEFBS_UseHVXV60, // V6_vmpahb_acc = 3051
14583 CEFBS_UseHVXV65, // V6_vmpahhsat = 3052
14584 CEFBS_UseHVXV62, // V6_vmpauhb = 3053
14585 CEFBS_UseHVXV62, // V6_vmpauhb_acc = 3054
14586 CEFBS_UseHVXV65, // V6_vmpauhuhsat = 3055
14587 CEFBS_UseHVXV65, // V6_vmpsuhuhsat = 3056
14588 CEFBS_UseHVXV79_UseHVXIEEEFP, // V6_vmpy_hf_f8 = 3057
14589 CEFBS_UseHVXV79_UseHVXIEEEFP, // V6_vmpy_hf_f8_acc = 3058
14590 CEFBS_UseHVXV68_UseHVXIEEEFP, // V6_vmpy_hf_hf = 3059
14591 CEFBS_UseHVXV68_UseHVXIEEEFP, // V6_vmpy_hf_hf_acc = 3060
14592 CEFBS_UseHVXV68_UseHVXQFloat, // V6_vmpy_qf16 = 3061
14593 CEFBS_UseHVXV68_UseHVXQFloat, // V6_vmpy_qf16_hf = 3062
14594 CEFBS_UseHVXV68_UseHVXQFloat, // V6_vmpy_qf16_mix_hf = 3063
14595 CEFBS_UseHVXV68_UseHVXQFloat, // V6_vmpy_qf32 = 3064
14596 CEFBS_UseHVXV68_UseHVXQFloat, // V6_vmpy_qf32_hf = 3065
14597 CEFBS_UseHVXV68_UseHVXQFloat, // V6_vmpy_qf32_mix_hf = 3066
14598 CEFBS_UseHVXV68_UseHVXQFloat, // V6_vmpy_qf32_qf16 = 3067
14599 CEFBS_UseHVXV68_UseHVXQFloat, // V6_vmpy_qf32_sf = 3068
14600 CEFBS_UseHVXV79_UseHVXQFloat, // V6_vmpy_rt_hf = 3069
14601 CEFBS_UseHVXV79_UseHVXQFloat, // V6_vmpy_rt_qf16 = 3070
14602 CEFBS_UseHVXV79_UseHVXQFloat, // V6_vmpy_rt_sf = 3071
14603 CEFBS_UseHVXV73_UseHVXIEEEFP, // V6_vmpy_sf_bf = 3072
14604 CEFBS_UseHVXV73_UseHVXIEEEFP, // V6_vmpy_sf_bf_acc = 3073
14605 CEFBS_UseHVXV68_UseHVXIEEEFP, // V6_vmpy_sf_hf = 3074
14606 CEFBS_UseHVXV68_UseHVXIEEEFP, // V6_vmpy_sf_hf_acc = 3075
14607 CEFBS_UseHVXV68_UseHVXIEEEFP, // V6_vmpy_sf_sf = 3076
14608 CEFBS_UseHVXV60, // V6_vmpybus = 3077
14609 CEFBS_UseHVXV60, // V6_vmpybus_acc = 3078
14610 CEFBS_UseHVXV60, // V6_vmpybusv = 3079
14611 CEFBS_UseHVXV60, // V6_vmpybusv_acc = 3080
14612 CEFBS_UseHVXV60, // V6_vmpybv = 3081
14613 CEFBS_UseHVXV60, // V6_vmpybv_acc = 3082
14614 CEFBS_UseHVXV60, // V6_vmpyewuh = 3083
14615 CEFBS_UseHVXV62, // V6_vmpyewuh_64 = 3084
14616 CEFBS_UseHVXV60, // V6_vmpyh = 3085
14617 CEFBS_UseHVXV65, // V6_vmpyh_acc = 3086
14618 CEFBS_UseHVXV60, // V6_vmpyhsat_acc = 3087
14619 CEFBS_UseHVXV60, // V6_vmpyhsrs = 3088
14620 CEFBS_UseHVXV60, // V6_vmpyhss = 3089
14621 CEFBS_UseHVXV60, // V6_vmpyhus = 3090
14622 CEFBS_UseHVXV60, // V6_vmpyhus_acc = 3091
14623 CEFBS_UseHVXV60, // V6_vmpyhv = 3092
14624 CEFBS_UseHVXV60, // V6_vmpyhv_acc = 3093
14625 CEFBS_UseHVXV60, // V6_vmpyhvsrs = 3094
14626 CEFBS_UseHVXV60, // V6_vmpyieoh = 3095
14627 CEFBS_UseHVXV60, // V6_vmpyiewh_acc = 3096
14628 CEFBS_UseHVXV60, // V6_vmpyiewuh = 3097
14629 CEFBS_UseHVXV60, // V6_vmpyiewuh_acc = 3098
14630 CEFBS_UseHVXV60, // V6_vmpyih = 3099
14631 CEFBS_UseHVXV60, // V6_vmpyih_acc = 3100
14632 CEFBS_UseHVXV60, // V6_vmpyihb = 3101
14633 CEFBS_UseHVXV60, // V6_vmpyihb_acc = 3102
14634 CEFBS_UseHVXV60, // V6_vmpyiowh = 3103
14635 CEFBS_UseHVXV60, // V6_vmpyiwb = 3104
14636 CEFBS_UseHVXV60, // V6_vmpyiwb_acc = 3105
14637 CEFBS_UseHVXV60, // V6_vmpyiwh = 3106
14638 CEFBS_UseHVXV60, // V6_vmpyiwh_acc = 3107
14639 CEFBS_UseHVXV62, // V6_vmpyiwub = 3108
14640 CEFBS_UseHVXV62, // V6_vmpyiwub_acc = 3109
14641 CEFBS_UseHVXV60, // V6_vmpyowh = 3110
14642 CEFBS_UseHVXV62, // V6_vmpyowh_64_acc = 3111
14643 CEFBS_UseHVXV60, // V6_vmpyowh_rnd = 3112
14644 CEFBS_UseHVXV60, // V6_vmpyowh_rnd_sacc = 3113
14645 CEFBS_UseHVXV60, // V6_vmpyowh_sacc = 3114
14646 CEFBS_UseHVXV60, // V6_vmpyub = 3115
14647 CEFBS_UseHVXV60, // V6_vmpyub_acc = 3116
14648 CEFBS_UseHVXV60, // V6_vmpyubv = 3117
14649 CEFBS_UseHVXV60, // V6_vmpyubv_acc = 3118
14650 CEFBS_UseHVXV60, // V6_vmpyuh = 3119
14651 CEFBS_UseHVXV60, // V6_vmpyuh_acc = 3120
14652 CEFBS_UseHVXV65, // V6_vmpyuhe = 3121
14653 CEFBS_UseHVXV65, // V6_vmpyuhe_acc = 3122
14654 CEFBS_UseHVXV60, // V6_vmpyuhv = 3123
14655 CEFBS_UseHVXV60, // V6_vmpyuhv_acc = 3124
14656 CEFBS_UseHVXV69, // V6_vmpyuhvs = 3125
14657 CEFBS_UseHVXV60, // V6_vmux = 3126
14658 CEFBS_UseHVXV65, // V6_vnavgb = 3127
14659 CEFBS_UseHVXV60, // V6_vnavgh = 3128
14660 CEFBS_UseHVXV60, // V6_vnavgub = 3129
14661 CEFBS_UseHVXV60, // V6_vnavgw = 3130
14662 CEFBS_UseHVXV60, // V6_vnccombine = 3131
14663 CEFBS_UseHVXV60, // V6_vncmov = 3132
14664 CEFBS_UseHVXV60, // V6_vnormamth = 3133
14665 CEFBS_UseHVXV60, // V6_vnormamtw = 3134
14666 CEFBS_UseHVXV60, // V6_vnot = 3135
14667 CEFBS_UseHVXV60, // V6_vor = 3136
14668 CEFBS_UseHVXV60, // V6_vpackeb = 3137
14669 CEFBS_UseHVXV60, // V6_vpackeh = 3138
14670 CEFBS_UseHVXV60, // V6_vpackhb_sat = 3139
14671 CEFBS_UseHVXV60, // V6_vpackhub_sat = 3140
14672 CEFBS_UseHVXV60, // V6_vpackob = 3141
14673 CEFBS_UseHVXV60, // V6_vpackoh = 3142
14674 CEFBS_UseHVXV60, // V6_vpackwh_sat = 3143
14675 CEFBS_UseHVXV60, // V6_vpackwuh_sat = 3144
14676 CEFBS_UseHVXV60, // V6_vpopcounth = 3145
14677 CEFBS_UseHVXV65, // V6_vprefixqb = 3146
14678 CEFBS_UseHVXV65, // V6_vprefixqh = 3147
14679 CEFBS_UseHVXV65, // V6_vprefixqw = 3148
14680 CEFBS_UseHVXV60, // V6_vrdelta = 3149
14681 CEFBS_UseHVXV65, // V6_vrmpybub_rtt = 3150
14682 CEFBS_UseHVXV65, // V6_vrmpybub_rtt_acc = 3151
14683 CEFBS_UseHVXV60, // V6_vrmpybus = 3152
14684 CEFBS_UseHVXV60, // V6_vrmpybus_acc = 3153
14685 CEFBS_UseHVXV60, // V6_vrmpybusi = 3154
14686 CEFBS_UseHVXV60, // V6_vrmpybusi_acc = 3155
14687 CEFBS_UseHVXV60, // V6_vrmpybusv = 3156
14688 CEFBS_UseHVXV60, // V6_vrmpybusv_acc = 3157
14689 CEFBS_UseHVXV60, // V6_vrmpybv = 3158
14690 CEFBS_UseHVXV60, // V6_vrmpybv_acc = 3159
14691 CEFBS_UseHVXV60, // V6_vrmpyub = 3160
14692 CEFBS_UseHVXV60, // V6_vrmpyub_acc = 3161
14693 CEFBS_UseHVXV65, // V6_vrmpyub_rtt = 3162
14694 CEFBS_UseHVXV65, // V6_vrmpyub_rtt_acc = 3163
14695 CEFBS_UseHVXV60, // V6_vrmpyubi = 3164
14696 CEFBS_UseHVXV60, // V6_vrmpyubi_acc = 3165
14697 CEFBS_UseHVXV60, // V6_vrmpyubv = 3166
14698 CEFBS_UseHVXV60, // V6_vrmpyubv_acc = 3167
14699 CEFBS_UseHVXV66_UseZReg, // V6_vrmpyzbb_rt = 3168
14700 CEFBS_UseHVXV66_UseZReg, // V6_vrmpyzbb_rt_acc = 3169
14701 CEFBS_UseHVXV66_UseZReg, // V6_vrmpyzbb_rx = 3170
14702 CEFBS_UseHVXV66_UseZReg, // V6_vrmpyzbb_rx_acc = 3171
14703 CEFBS_UseHVXV66_UseZReg, // V6_vrmpyzbub_rt = 3172
14704 CEFBS_UseHVXV66_UseZReg, // V6_vrmpyzbub_rt_acc = 3173
14705 CEFBS_UseHVXV66_UseZReg, // V6_vrmpyzbub_rx = 3174
14706 CEFBS_UseHVXV66_UseZReg, // V6_vrmpyzbub_rx_acc = 3175
14707 CEFBS_UseHVXV66_UseZReg, // V6_vrmpyzcb_rt = 3176
14708 CEFBS_UseHVXV66_UseZReg, // V6_vrmpyzcb_rt_acc = 3177
14709 CEFBS_UseHVXV66_UseZReg, // V6_vrmpyzcb_rx = 3178
14710 CEFBS_UseHVXV66_UseZReg, // V6_vrmpyzcb_rx_acc = 3179
14711 CEFBS_UseHVXV66_UseZReg, // V6_vrmpyzcbs_rt = 3180
14712 CEFBS_UseHVXV66_UseZReg, // V6_vrmpyzcbs_rt_acc = 3181
14713 CEFBS_UseHVXV66_UseZReg, // V6_vrmpyzcbs_rx = 3182
14714 CEFBS_UseHVXV66_UseZReg, // V6_vrmpyzcbs_rx_acc = 3183
14715 CEFBS_UseHVXV66_UseZReg, // V6_vrmpyznb_rt = 3184
14716 CEFBS_UseHVXV66_UseZReg, // V6_vrmpyznb_rt_acc = 3185
14717 CEFBS_UseHVXV66_UseZReg, // V6_vrmpyznb_rx = 3186
14718 CEFBS_UseHVXV66_UseZReg, // V6_vrmpyznb_rx_acc = 3187
14719 CEFBS_UseHVXV60, // V6_vror = 3188
14720 CEFBS_UseHVXV66, // V6_vrotr = 3189
14721 CEFBS_UseHVXV60, // V6_vroundhb = 3190
14722 CEFBS_UseHVXV60, // V6_vroundhub = 3191
14723 CEFBS_UseHVXV62, // V6_vrounduhub = 3192
14724 CEFBS_UseHVXV62, // V6_vrounduwuh = 3193
14725 CEFBS_UseHVXV60, // V6_vroundwh = 3194
14726 CEFBS_UseHVXV60, // V6_vroundwuh = 3195
14727 CEFBS_UseHVXV60, // V6_vrsadubi = 3196
14728 CEFBS_UseHVXV60, // V6_vrsadubi_acc = 3197
14729 CEFBS_UseHVXV66, // V6_vsatdw = 3198
14730 CEFBS_UseHVXV60, // V6_vsathub = 3199
14731 CEFBS_UseHVXV62, // V6_vsatuwuh = 3200
14732 CEFBS_UseHVXV60, // V6_vsatwh = 3201
14733 CEFBS_UseHVXV60, // V6_vsb = 3202
14734 CEFBS_UseHVXV65, // V6_vscattermh = 3203
14735 CEFBS_UseHVXV65, // V6_vscattermh_add = 3204
14736 CEFBS_UseHVXV65, // V6_vscattermhq = 3205
14737 CEFBS_UseHVXV65, // V6_vscattermhw = 3206
14738 CEFBS_UseHVXV65, // V6_vscattermhw_add = 3207
14739 CEFBS_UseHVXV65, // V6_vscattermhwq = 3208
14740 CEFBS_UseHVXV65, // V6_vscattermw = 3209
14741 CEFBS_UseHVXV65, // V6_vscattermw_add = 3210
14742 CEFBS_UseHVXV65, // V6_vscattermwq = 3211
14743 CEFBS_UseHVXV60, // V6_vsh = 3212
14744 CEFBS_UseHVXV60, // V6_vshufeh = 3213
14745 CEFBS_UseHVXV60, // V6_vshuff = 3214
14746 CEFBS_UseHVXV60, // V6_vshuffb = 3215
14747 CEFBS_UseHVXV60, // V6_vshuffeb = 3216
14748 CEFBS_UseHVXV60, // V6_vshuffh = 3217
14749 CEFBS_UseHVXV60, // V6_vshuffob = 3218
14750 CEFBS_UseHVXV60, // V6_vshuffvdd = 3219
14751 CEFBS_UseHVXV60, // V6_vshufoeb = 3220
14752 CEFBS_UseHVXV60, // V6_vshufoeh = 3221
14753 CEFBS_UseHVXV60, // V6_vshufoh = 3222
14754 CEFBS_UseHVXV68_UseHVXQFloat, // V6_vsub_hf = 3223
14755 CEFBS_UseHVXV79_UseHVXIEEEFP, // V6_vsub_hf_f8 = 3224
14756 CEFBS_UseHVXV68_UseHVXIEEEFP, // V6_vsub_hf_hf = 3225
14757 CEFBS_UseHVXV68_UseHVXQFloat, // V6_vsub_qf16 = 3226
14758 CEFBS_UseHVXV68_UseHVXQFloat, // V6_vsub_qf16_mix = 3227
14759 CEFBS_UseHVXV68_UseHVXQFloat, // V6_vsub_qf32 = 3228
14760 CEFBS_UseHVXV68_UseHVXQFloat, // V6_vsub_qf32_mix = 3229
14761 CEFBS_UseHVXV68_UseHVXQFloat, // V6_vsub_sf = 3230
14762 CEFBS_UseHVXV73_UseHVXIEEEFP, // V6_vsub_sf_bf = 3231
14763 CEFBS_UseHVXV68_UseHVXIEEEFP, // V6_vsub_sf_hf = 3232
14764 CEFBS_UseHVXV68_UseHVXIEEEFP, // V6_vsub_sf_sf = 3233
14765 CEFBS_UseHVXV60, // V6_vsubb = 3234
14766 CEFBS_UseHVXV60, // V6_vsubb_dv = 3235
14767 CEFBS_UseHVXV60, // V6_vsubbnq = 3236
14768 CEFBS_UseHVXV60, // V6_vsubbq = 3237
14769 CEFBS_UseHVXV62, // V6_vsubbsat = 3238
14770 CEFBS_UseHVXV62, // V6_vsubbsat_dv = 3239
14771 CEFBS_UseHVXV62, // V6_vsubcarry = 3240
14772 CEFBS_UseHVXV66, // V6_vsubcarryo = 3241
14773 CEFBS_UseHVXV60, // V6_vsubh = 3242
14774 CEFBS_UseHVXV60, // V6_vsubh_dv = 3243
14775 CEFBS_UseHVXV60, // V6_vsubhnq = 3244
14776 CEFBS_UseHVXV60, // V6_vsubhq = 3245
14777 CEFBS_UseHVXV60, // V6_vsubhsat = 3246
14778 CEFBS_UseHVXV60, // V6_vsubhsat_dv = 3247
14779 CEFBS_UseHVXV60, // V6_vsubhw = 3248
14780 CEFBS_UseHVXV60, // V6_vsububh = 3249
14781 CEFBS_UseHVXV60, // V6_vsububsat = 3250
14782 CEFBS_UseHVXV60, // V6_vsububsat_dv = 3251
14783 CEFBS_UseHVXV62, // V6_vsubububb_sat = 3252
14784 CEFBS_UseHVXV60, // V6_vsubuhsat = 3253
14785 CEFBS_UseHVXV60, // V6_vsubuhsat_dv = 3254
14786 CEFBS_UseHVXV60, // V6_vsubuhw = 3255
14787 CEFBS_UseHVXV62, // V6_vsubuwsat = 3256
14788 CEFBS_UseHVXV62, // V6_vsubuwsat_dv = 3257
14789 CEFBS_UseHVXV60, // V6_vsubw = 3258
14790 CEFBS_UseHVXV60, // V6_vsubw_dv = 3259
14791 CEFBS_UseHVXV60, // V6_vsubwnq = 3260
14792 CEFBS_UseHVXV60, // V6_vsubwq = 3261
14793 CEFBS_UseHVXV60, // V6_vsubwsat = 3262
14794 CEFBS_UseHVXV60, // V6_vsubwsat_dv = 3263
14795 CEFBS_UseHVXV60, // V6_vswap = 3264
14796 CEFBS_UseHVXV60, // V6_vtmpyb = 3265
14797 CEFBS_UseHVXV60, // V6_vtmpyb_acc = 3266
14798 CEFBS_UseHVXV60, // V6_vtmpybus = 3267
14799 CEFBS_UseHVXV60, // V6_vtmpybus_acc = 3268
14800 CEFBS_UseHVXV60, // V6_vtmpyhb = 3269
14801 CEFBS_UseHVXV60, // V6_vtmpyhb_acc = 3270
14802 CEFBS_UseHVXV60, // V6_vunpackb = 3271
14803 CEFBS_UseHVXV60, // V6_vunpackh = 3272
14804 CEFBS_UseHVXV60, // V6_vunpackob = 3273
14805 CEFBS_UseHVXV60, // V6_vunpackoh = 3274
14806 CEFBS_UseHVXV60, // V6_vunpackub = 3275
14807 CEFBS_UseHVXV60, // V6_vunpackuh = 3276
14808 CEFBS_UseHVXV62, // V6_vwhist128 = 3277
14809 CEFBS_UseHVXV62, // V6_vwhist128m = 3278
14810 CEFBS_UseHVXV62, // V6_vwhist128q = 3279
14811 CEFBS_UseHVXV62, // V6_vwhist128qm = 3280
14812 CEFBS_UseHVXV62, // V6_vwhist256 = 3281
14813 CEFBS_UseHVXV62, // V6_vwhist256_sat = 3282
14814 CEFBS_UseHVXV62, // V6_vwhist256q = 3283
14815 CEFBS_UseHVXV62, // V6_vwhist256q_sat = 3284
14816 CEFBS_UseHVXV60, // V6_vxor = 3285
14817 CEFBS_UseHVXV60, // V6_vzb = 3286
14818 CEFBS_UseHVXV60, // V6_vzh = 3287
14819 CEFBS_UseHVXV66_UseZReg, // V6_zLd_ai = 3288
14820 CEFBS_UseHVXV66_UseZReg, // V6_zLd_pi = 3289
14821 CEFBS_UseHVXV66_UseZReg, // V6_zLd_ppu = 3290
14822 CEFBS_UseHVXV66_UseZReg, // V6_zLd_pred_ai = 3291
14823 CEFBS_UseHVXV66_UseZReg, // V6_zLd_pred_pi = 3292
14824 CEFBS_UseHVXV66_UseZReg, // V6_zLd_pred_ppu = 3293
14825 CEFBS_UseHVXV66_UseZReg, // V6_zextract = 3294
14826 CEFBS_None, // Y2_barrier = 3295
14827 CEFBS_None, // Y2_break = 3296
14828 CEFBS_None, // Y2_ciad = 3297
14829 CEFBS_None, // Y2_crswap0 = 3298
14830 CEFBS_None, // Y2_cswi = 3299
14831 CEFBS_None, // Y2_dccleana = 3300
14832 CEFBS_None, // Y2_dccleanidx = 3301
14833 CEFBS_None, // Y2_dccleaninva = 3302
14834 CEFBS_None, // Y2_dccleaninvidx = 3303
14835 CEFBS_None, // Y2_dcfetchbo = 3304
14836 CEFBS_None, // Y2_dcinva = 3305
14837 CEFBS_None, // Y2_dcinvidx = 3306
14838 CEFBS_None, // Y2_dckill = 3307
14839 CEFBS_None, // Y2_dctagr = 3308
14840 CEFBS_None, // Y2_dctagw = 3309
14841 CEFBS_None, // Y2_dczeroa = 3310
14842 CEFBS_None, // Y2_getimask = 3311
14843 CEFBS_None, // Y2_iassignr = 3312
14844 CEFBS_None, // Y2_iassignw = 3313
14845 CEFBS_None, // Y2_icdatar = 3314
14846 CEFBS_HasV66, // Y2_icdataw = 3315
14847 CEFBS_None, // Y2_icinva = 3316
14848 CEFBS_None, // Y2_icinvidx = 3317
14849 CEFBS_None, // Y2_ickill = 3318
14850 CEFBS_None, // Y2_ictagr = 3319
14851 CEFBS_None, // Y2_ictagw = 3320
14852 CEFBS_None, // Y2_isync = 3321
14853 CEFBS_None, // Y2_k0lock = 3322
14854 CEFBS_None, // Y2_k0unlock = 3323
14855 CEFBS_None, // Y2_l2cleaninvidx = 3324
14856 CEFBS_None, // Y2_l2kill = 3325
14857 CEFBS_None, // Y2_resume = 3326
14858 CEFBS_None, // Y2_setimask = 3327
14859 CEFBS_HasV66, // Y2_setprio = 3328
14860 CEFBS_None, // Y2_start = 3329
14861 CEFBS_None, // Y2_stop = 3330
14862 CEFBS_None, // Y2_swi = 3331
14863 CEFBS_None, // Y2_syncht = 3332
14864 CEFBS_None, // Y2_tfrscrr = 3333
14865 CEFBS_None, // Y2_tfrsrcr = 3334
14866 CEFBS_None, // Y2_tlblock = 3335
14867 CEFBS_None, // Y2_tlbp = 3336
14868 CEFBS_None, // Y2_tlbr = 3337
14869 CEFBS_None, // Y2_tlbunlock = 3338
14870 CEFBS_None, // Y2_tlbw = 3339
14871 CEFBS_HasV65, // Y2_wait = 3340
14872 CEFBS_None, // Y4_crswap1 = 3341
14873 CEFBS_None, // Y4_crswap10 = 3342
14874 CEFBS_None, // Y4_l2fetch = 3343
14875 CEFBS_None, // Y4_l2tagr = 3344
14876 CEFBS_None, // Y4_l2tagw = 3345
14877 CEFBS_None, // Y4_nmi = 3346
14878 CEFBS_None, // Y4_siad = 3347
14879 CEFBS_None, // Y4_tfrscpp = 3348
14880 CEFBS_None, // Y4_tfrspcp = 3349
14881 CEFBS_None, // Y4_trace = 3350
14882 CEFBS_None, // Y5_ctlbw = 3351
14883 CEFBS_None, // Y5_l2cleanidx = 3352
14884 CEFBS_None, // Y5_l2fetch = 3353
14885 CEFBS_None, // Y5_l2gclean = 3354
14886 CEFBS_None, // Y5_l2gcleaninv = 3355
14887 CEFBS_None, // Y5_l2gunlock = 3356
14888 CEFBS_None, // Y5_l2invidx = 3357
14889 CEFBS_None, // Y5_l2locka = 3358
14890 CEFBS_None, // Y5_l2unlocka = 3359
14891 CEFBS_None, // Y5_tlbasidi = 3360
14892 CEFBS_None, // Y5_tlboc = 3361
14893 CEFBS_HasV67, // Y6_diag = 3362
14894 CEFBS_HasV67, // Y6_diag0 = 3363
14895 CEFBS_HasV67, // Y6_diag1 = 3364
14896 CEFBS_HasV68, // Y6_dmlink = 3365
14897 CEFBS_HasV68, // Y6_dmpause = 3366
14898 CEFBS_HasV68, // Y6_dmpoll = 3367
14899 CEFBS_HasV68, // Y6_dmresume = 3368
14900 CEFBS_HasV68, // Y6_dmstart = 3369
14901 CEFBS_HasV68, // Y6_dmwait = 3370
14902 CEFBS_None, // Y6_l2gcleaninvpa = 3371
14903 CEFBS_None, // Y6_l2gcleanpa = 3372
14904 CEFBS_None, // dep_A2_addsat = 3373
14905 CEFBS_None, // dep_A2_subsat = 3374
14906 CEFBS_None, // dep_S2_packhl = 3375
14907 CEFBS_None, // invalid_decode = 3376
14908 };
14909
14910 assert(Opcode < 3377);
14911 return FeatureBitsets[RequiredFeaturesRefs[Opcode]];
14912}
14913
14914} // end namespace llvm::Hexagon_MC
14915#endif // GET_COMPUTE_FEATURES
14916
14917#ifdef GET_AVAILABLE_OPCODE_CHECKER
14918#undef GET_AVAILABLE_OPCODE_CHECKER
14919namespace llvm::Hexagon_MC {
14920bool isOpcodeAvailable(unsigned Opcode, const FeatureBitset &Features) {
14921 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
14922 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
14923 FeatureBitset MissingFeatures =
14924 (AvailableFeatures & RequiredFeatures) ^
14925 RequiredFeatures;
14926 return !MissingFeatures.any();
14927}
14928} // end namespace llvm::Hexagon_MC
14929#endif // GET_AVAILABLE_OPCODE_CHECKER
14930
14931#ifdef ENABLE_INSTR_PREDICATE_VERIFIER
14932#undef ENABLE_INSTR_PREDICATE_VERIFIER
14933#include <sstream>
14934
14935namespace llvm::Hexagon_MC {
14936#ifndef NDEBUG
14937static const char *SubtargetFeatureNames[] = {
14938 "Feature_HasMemNoShuf",
14939 "Feature_HasPreV65",
14940 "Feature_HasV5",
14941 "Feature_HasV55",
14942 "Feature_HasV60",
14943 "Feature_HasV62",
14944 "Feature_HasV65",
14945 "Feature_HasV66",
14946 "Feature_HasV67",
14947 "Feature_HasV68",
14948 "Feature_HasV69",
14949 "Feature_HasV71",
14950 "Feature_HasV73",
14951 "Feature_HasV75",
14952 "Feature_HasV79",
14953 "Feature_UseAudio",
14954 "Feature_UseCabac",
14955 "Feature_UseHVX",
14956 "Feature_UseHVX64B",
14957 "Feature_UseHVX128B",
14958 "Feature_UseHVXIEEEFP",
14959 "Feature_UseHVXQFloat",
14960 "Feature_UseHVXV60",
14961 "Feature_UseHVXV62",
14962 "Feature_UseHVXV65",
14963 "Feature_UseHVXV66",
14964 "Feature_UseHVXV67",
14965 "Feature_UseHVXV68",
14966 "Feature_UseHVXV69",
14967 "Feature_UseHVXV71",
14968 "Feature_UseHVXV73",
14969 "Feature_UseHVXV75",
14970 "Feature_UseHVXV79",
14971 "Feature_UseZReg",
14972 nullptr
14973};
14974
14975#endif // NDEBUG
14976
14977void verifyInstructionPredicates(
14978 unsigned Opcode, const FeatureBitset &Features) {
14979#ifndef NDEBUG
14980 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
14981 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
14982 FeatureBitset MissingFeatures =
14983 (AvailableFeatures & RequiredFeatures) ^
14984 RequiredFeatures;
14985 if (MissingFeatures.any()) {
14986 std::ostringstream Msg;
14987 Msg << "Attempting to emit " << &HexagonInstrNameData[HexagonInstrNameIndices[Opcode]]
14988 << " instruction but the ";
14989 for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i)
14990 if (MissingFeatures.test(i))
14991 Msg << SubtargetFeatureNames[i] << " ";
14992 Msg << "predicate(s) are not met";
14993 report_fatal_error(Msg.str().c_str());
14994 }
14995#endif // NDEBUG
14996}
14997} // end namespace llvm::Hexagon_MC
14998#endif // ENABLE_INSTR_PREDICATE_VERIFIER
14999
15000#ifdef GET_INSTRMAP_INFO
15001#undef GET_INSTRMAP_INFO
15002namespace llvm::Hexagon {
15003
15004enum InputType {
15005 InputType_reg
15006};
15007
15008enum InstrType {
15009 InstrType_Pseudo,
15010 InstrType_Real
15011};
15012
15013enum NValueST {
15014 NValueST_true,
15015 NValueST_false
15016};
15017
15018enum PNewValue {
15019 PNewValue_new,
15020 PNewValue_
15021};
15022
15023enum PredSense {
15024 PredSense_false,
15025 PredSense_true
15026};
15027
15028enum addrMode {
15029 addrMode_BaseImmOffset,
15030 addrMode_Absolute,
15031 addrMode_PostInc,
15032 addrMode_BaseRegOffset,
15033 addrMode_BaseLongOffset
15034};
15035
15036enum isBrTaken {
15037 isBrTaken_false,
15038 isBrTaken_true
15039};
15040
15041// changeAddrMode_abs_io
15042LLVM_READONLY
15043int changeAddrMode_abs_io(uint16_t Opcode) {
15044 using namespace Hexagon;
15045 static constexpr uint16_t Table[][2] = {
15046 { L4_ploadrbf_abs, L2_ploadrbf_io },
15047 { L4_ploadrbfnew_abs, L2_ploadrbfnew_io },
15048 { L4_ploadrbt_abs, L2_ploadrbt_io },
15049 { L4_ploadrbtnew_abs, L2_ploadrbtnew_io },
15050 { L4_ploadrdf_abs, L2_ploadrdf_io },
15051 { L4_ploadrdfnew_abs, L2_ploadrdfnew_io },
15052 { L4_ploadrdt_abs, L2_ploadrdt_io },
15053 { L4_ploadrdtnew_abs, L2_ploadrdtnew_io },
15054 { L4_ploadrhf_abs, L2_ploadrhf_io },
15055 { L4_ploadrhfnew_abs, L2_ploadrhfnew_io },
15056 { L4_ploadrht_abs, L2_ploadrht_io },
15057 { L4_ploadrhtnew_abs, L2_ploadrhtnew_io },
15058 { L4_ploadrif_abs, L2_ploadrif_io },
15059 { L4_ploadrifnew_abs, L2_ploadrifnew_io },
15060 { L4_ploadrit_abs, L2_ploadrit_io },
15061 { L4_ploadritnew_abs, L2_ploadritnew_io },
15062 { L4_ploadrubf_abs, L2_ploadrubf_io },
15063 { L4_ploadrubfnew_abs, L2_ploadrubfnew_io },
15064 { L4_ploadrubt_abs, L2_ploadrubt_io },
15065 { L4_ploadrubtnew_abs, L2_ploadrubtnew_io },
15066 { L4_ploadruhf_abs, L2_ploadruhf_io },
15067 { L4_ploadruhfnew_abs, L2_ploadruhfnew_io },
15068 { L4_ploadruht_abs, L2_ploadruht_io },
15069 { L4_ploadruhtnew_abs, L2_ploadruhtnew_io },
15070 { PS_loadrbabs, L2_loadrb_io },
15071 { PS_loadrdabs, L2_loadrd_io },
15072 { PS_loadrhabs, L2_loadrh_io },
15073 { PS_loadriabs, L2_loadri_io },
15074 { PS_loadrubabs, L2_loadrub_io },
15075 { PS_loadruhabs, L2_loadruh_io },
15076 { PS_storerbabs, S2_storerb_io },
15077 { PS_storerbnewabs, S2_storerbnew_io },
15078 { PS_storerdabs, S2_storerd_io },
15079 { PS_storerfabs, S2_storerf_io },
15080 { PS_storerhabs, S2_storerh_io },
15081 { PS_storerhnewabs, S2_storerhnew_io },
15082 { PS_storeriabs, S2_storeri_io },
15083 { PS_storerinewabs, S2_storerinew_io },
15084 { S4_pstorerbf_abs, S2_pstorerbf_io },
15085 { S4_pstorerbfnew_abs, S4_pstorerbfnew_io },
15086 { S4_pstorerbnewf_abs, S2_pstorerbnewf_io },
15087 { S4_pstorerbnewfnew_abs, S4_pstorerbnewfnew_io },
15088 { S4_pstorerbnewt_abs, S2_pstorerbnewt_io },
15089 { S4_pstorerbnewtnew_abs, S4_pstorerbnewtnew_io },
15090 { S4_pstorerbt_abs, S2_pstorerbt_io },
15091 { S4_pstorerbtnew_abs, S4_pstorerbtnew_io },
15092 { S4_pstorerdf_abs, S2_pstorerdf_io },
15093 { S4_pstorerdfnew_abs, S4_pstorerdfnew_io },
15094 { S4_pstorerdt_abs, S2_pstorerdt_io },
15095 { S4_pstorerdtnew_abs, S4_pstorerdtnew_io },
15096 { S4_pstorerff_abs, S2_pstorerff_io },
15097 { S4_pstorerffnew_abs, S4_pstorerffnew_io },
15098 { S4_pstorerft_abs, S2_pstorerft_io },
15099 { S4_pstorerftnew_abs, S4_pstorerftnew_io },
15100 { S4_pstorerhf_abs, S2_pstorerhf_io },
15101 { S4_pstorerhfnew_abs, S4_pstorerhfnew_io },
15102 { S4_pstorerhnewf_abs, S2_pstorerhnewf_io },
15103 { S4_pstorerhnewfnew_abs, S4_pstorerhnewfnew_io },
15104 { S4_pstorerhnewt_abs, S2_pstorerhnewt_io },
15105 { S4_pstorerhnewtnew_abs, S4_pstorerhnewtnew_io },
15106 { S4_pstorerht_abs, S2_pstorerht_io },
15107 { S4_pstorerhtnew_abs, S4_pstorerhtnew_io },
15108 { S4_pstorerif_abs, S2_pstorerif_io },
15109 { S4_pstorerifnew_abs, S4_pstorerifnew_io },
15110 { S4_pstorerinewf_abs, S2_pstorerinewf_io },
15111 { S4_pstorerinewfnew_abs, S4_pstorerinewfnew_io },
15112 { S4_pstorerinewt_abs, S2_pstorerinewt_io },
15113 { S4_pstorerinewtnew_abs, S4_pstorerinewtnew_io },
15114 { S4_pstorerit_abs, S2_pstorerit_io },
15115 { S4_pstoreritnew_abs, S4_pstoreritnew_io },
15116 }; // End of Table
15117
15118 unsigned mid;
15119 unsigned start = 0;
15120 unsigned end = 70;
15121 while (start < end) {
15122 mid = start + (end - start) / 2;
15123 if (Opcode == Table[mid][0])
15124 break;
15125 if (Opcode < Table[mid][0])
15126 end = mid;
15127 else
15128 start = mid + 1;
15129 }
15130 if (start == end)
15131 return -1; // Instruction doesn't exist in this table.
15132
15133 return Table[mid][1];
15134}
15135
15136// changeAddrMode_io_abs
15137LLVM_READONLY
15138int changeAddrMode_io_abs(uint16_t Opcode) {
15139 using namespace Hexagon;
15140 static constexpr uint16_t Table[][2] = {
15141 { L2_loadrb_io, PS_loadrbabs },
15142 { L2_loadrd_io, PS_loadrdabs },
15143 { L2_loadrh_io, PS_loadrhabs },
15144 { L2_loadri_io, PS_loadriabs },
15145 { L2_loadrub_io, PS_loadrubabs },
15146 { L2_loadruh_io, PS_loadruhabs },
15147 { L2_ploadrbf_io, L4_ploadrbf_abs },
15148 { L2_ploadrbfnew_io, L4_ploadrbfnew_abs },
15149 { L2_ploadrbt_io, L4_ploadrbt_abs },
15150 { L2_ploadrbtnew_io, L4_ploadrbtnew_abs },
15151 { L2_ploadrdf_io, L4_ploadrdf_abs },
15152 { L2_ploadrdfnew_io, L4_ploadrdfnew_abs },
15153 { L2_ploadrdt_io, L4_ploadrdt_abs },
15154 { L2_ploadrdtnew_io, L4_ploadrdtnew_abs },
15155 { L2_ploadrhf_io, L4_ploadrhf_abs },
15156 { L2_ploadrhfnew_io, L4_ploadrhfnew_abs },
15157 { L2_ploadrht_io, L4_ploadrht_abs },
15158 { L2_ploadrhtnew_io, L4_ploadrhtnew_abs },
15159 { L2_ploadrif_io, L4_ploadrif_abs },
15160 { L2_ploadrifnew_io, L4_ploadrifnew_abs },
15161 { L2_ploadrit_io, L4_ploadrit_abs },
15162 { L2_ploadritnew_io, L4_ploadritnew_abs },
15163 { L2_ploadrubf_io, L4_ploadrubf_abs },
15164 { L2_ploadrubfnew_io, L4_ploadrubfnew_abs },
15165 { L2_ploadrubt_io, L4_ploadrubt_abs },
15166 { L2_ploadrubtnew_io, L4_ploadrubtnew_abs },
15167 { L2_ploadruhf_io, L4_ploadruhf_abs },
15168 { L2_ploadruhfnew_io, L4_ploadruhfnew_abs },
15169 { L2_ploadruht_io, L4_ploadruht_abs },
15170 { L2_ploadruhtnew_io, L4_ploadruhtnew_abs },
15171 { S2_pstorerbf_io, S4_pstorerbf_abs },
15172 { S2_pstorerbnewf_io, S4_pstorerbnewf_abs },
15173 { S2_pstorerbnewt_io, S4_pstorerbnewt_abs },
15174 { S2_pstorerbt_io, S4_pstorerbt_abs },
15175 { S2_pstorerdf_io, S4_pstorerdf_abs },
15176 { S2_pstorerdt_io, S4_pstorerdt_abs },
15177 { S2_pstorerff_io, S4_pstorerff_abs },
15178 { S2_pstorerft_io, S4_pstorerft_abs },
15179 { S2_pstorerhf_io, S4_pstorerhf_abs },
15180 { S2_pstorerhnewf_io, S4_pstorerhnewf_abs },
15181 { S2_pstorerhnewt_io, S4_pstorerhnewt_abs },
15182 { S2_pstorerht_io, S4_pstorerht_abs },
15183 { S2_pstorerif_io, S4_pstorerif_abs },
15184 { S2_pstorerinewf_io, S4_pstorerinewf_abs },
15185 { S2_pstorerinewt_io, S4_pstorerinewt_abs },
15186 { S2_pstorerit_io, S4_pstorerit_abs },
15187 { S2_storerb_io, PS_storerbabs },
15188 { S2_storerbnew_io, PS_storerbnewabs },
15189 { S2_storerd_io, PS_storerdabs },
15190 { S2_storerf_io, PS_storerfabs },
15191 { S2_storerh_io, PS_storerhabs },
15192 { S2_storerhnew_io, PS_storerhnewabs },
15193 { S2_storeri_io, PS_storeriabs },
15194 { S2_storerinew_io, PS_storerinewabs },
15195 { S4_pstorerbfnew_io, S4_pstorerbfnew_abs },
15196 { S4_pstorerbnewfnew_io, S4_pstorerbnewfnew_abs },
15197 { S4_pstorerbnewtnew_io, S4_pstorerbnewtnew_abs },
15198 { S4_pstorerbtnew_io, S4_pstorerbtnew_abs },
15199 { S4_pstorerdfnew_io, S4_pstorerdfnew_abs },
15200 { S4_pstorerdtnew_io, S4_pstorerdtnew_abs },
15201 { S4_pstorerffnew_io, S4_pstorerffnew_abs },
15202 { S4_pstorerftnew_io, S4_pstorerftnew_abs },
15203 { S4_pstorerhfnew_io, S4_pstorerhfnew_abs },
15204 { S4_pstorerhnewfnew_io, S4_pstorerhnewfnew_abs },
15205 { S4_pstorerhnewtnew_io, S4_pstorerhnewtnew_abs },
15206 { S4_pstorerhtnew_io, S4_pstorerhtnew_abs },
15207 { S4_pstorerifnew_io, S4_pstorerifnew_abs },
15208 { S4_pstorerinewfnew_io, S4_pstorerinewfnew_abs },
15209 { S4_pstorerinewtnew_io, S4_pstorerinewtnew_abs },
15210 { S4_pstoreritnew_io, S4_pstoreritnew_abs },
15211 }; // End of Table
15212
15213 unsigned mid;
15214 unsigned start = 0;
15215 unsigned end = 70;
15216 while (start < end) {
15217 mid = start + (end - start) / 2;
15218 if (Opcode == Table[mid][0])
15219 break;
15220 if (Opcode < Table[mid][0])
15221 end = mid;
15222 else
15223 start = mid + 1;
15224 }
15225 if (start == end)
15226 return -1; // Instruction doesn't exist in this table.
15227
15228 return Table[mid][1];
15229}
15230
15231// changeAddrMode_io_pi
15232LLVM_READONLY
15233int changeAddrMode_io_pi(uint16_t Opcode) {
15234 using namespace Hexagon;
15235 static constexpr uint16_t Table[][2] = {
15236 { L2_loadrb_io, L2_loadrb_pi },
15237 { L2_loadrd_io, L2_loadrd_pi },
15238 { L2_loadrh_io, L2_loadrh_pi },
15239 { L2_loadri_io, L2_loadri_pi },
15240 { L2_loadrub_io, L2_loadrub_pi },
15241 { L2_loadruh_io, L2_loadruh_pi },
15242 { S2_storerb_io, S2_storerb_pi },
15243 { S2_storerd_io, S2_storerd_pi },
15244 { S2_storerf_io, S2_storerf_pi },
15245 { S2_storerh_io, S2_storerh_pi },
15246 { S2_storeri_io, S2_storeri_pi },
15247 { V6_vL32Ub_ai, V6_vL32Ub_pi },
15248 { V6_vL32b_ai, V6_vL32b_pi },
15249 { V6_vL32b_cur_ai, V6_vL32b_cur_pi },
15250 { V6_vL32b_nt_ai, V6_vL32b_nt_pi },
15251 { V6_vL32b_nt_cur_ai, V6_vL32b_nt_cur_pi },
15252 { V6_vL32b_nt_tmp_ai, V6_vL32b_nt_tmp_pi },
15253 { V6_vL32b_tmp_ai, V6_vL32b_tmp_pi },
15254 { V6_vS32Ub_ai, V6_vS32Ub_pi },
15255 { V6_vS32b_ai, V6_vS32b_pi },
15256 { V6_vS32b_new_ai, V6_vS32b_new_pi },
15257 { V6_vS32b_nt_ai, V6_vS32b_nt_pi },
15258 { V6_vS32b_nt_new_ai, V6_vS32b_nt_new_pi },
15259 { V6_zLd_ai, V6_zLd_pi },
15260 }; // End of Table
15261
15262 unsigned mid;
15263 unsigned start = 0;
15264 unsigned end = 24;
15265 while (start < end) {
15266 mid = start + (end - start) / 2;
15267 if (Opcode == Table[mid][0])
15268 break;
15269 if (Opcode < Table[mid][0])
15270 end = mid;
15271 else
15272 start = mid + 1;
15273 }
15274 if (start == end)
15275 return -1; // Instruction doesn't exist in this table.
15276
15277 return Table[mid][1];
15278}
15279
15280// changeAddrMode_io_rr
15281LLVM_READONLY
15282int changeAddrMode_io_rr(uint16_t Opcode) {
15283 using namespace Hexagon;
15284 static constexpr uint16_t Table[][2] = {
15285 { L2_loadrb_io, L4_loadrb_rr },
15286 { L2_loadrd_io, L4_loadrd_rr },
15287 { L2_loadrh_io, L4_loadrh_rr },
15288 { L2_loadri_io, L4_loadri_rr },
15289 { L2_loadrub_io, L4_loadrub_rr },
15290 { L2_loadruh_io, L4_loadruh_rr },
15291 { L2_ploadrbf_io, L4_ploadrbf_rr },
15292 { L2_ploadrbfnew_io, L4_ploadrbfnew_rr },
15293 { L2_ploadrbt_io, L4_ploadrbt_rr },
15294 { L2_ploadrbtnew_io, L4_ploadrbtnew_rr },
15295 { L2_ploadrdf_io, L4_ploadrdf_rr },
15296 { L2_ploadrdfnew_io, L4_ploadrdfnew_rr },
15297 { L2_ploadrdt_io, L4_ploadrdt_rr },
15298 { L2_ploadrdtnew_io, L4_ploadrdtnew_rr },
15299 { L2_ploadrhf_io, L4_ploadrhf_rr },
15300 { L2_ploadrhfnew_io, L4_ploadrhfnew_rr },
15301 { L2_ploadrht_io, L4_ploadrht_rr },
15302 { L2_ploadrhtnew_io, L4_ploadrhtnew_rr },
15303 { L2_ploadrif_io, L4_ploadrif_rr },
15304 { L2_ploadrifnew_io, L4_ploadrifnew_rr },
15305 { L2_ploadrit_io, L4_ploadrit_rr },
15306 { L2_ploadritnew_io, L4_ploadritnew_rr },
15307 { L2_ploadrubf_io, L4_ploadrubf_rr },
15308 { L2_ploadrubfnew_io, L4_ploadrubfnew_rr },
15309 { L2_ploadrubt_io, L4_ploadrubt_rr },
15310 { L2_ploadrubtnew_io, L4_ploadrubtnew_rr },
15311 { L2_ploadruhf_io, L4_ploadruhf_rr },
15312 { L2_ploadruhfnew_io, L4_ploadruhfnew_rr },
15313 { L2_ploadruht_io, L4_ploadruht_rr },
15314 { L2_ploadruhtnew_io, L4_ploadruhtnew_rr },
15315 { S2_pstorerbf_io, S4_pstorerbf_rr },
15316 { S2_pstorerbnewf_io, S4_pstorerbnewf_rr },
15317 { S2_pstorerbnewt_io, S4_pstorerbnewt_rr },
15318 { S2_pstorerbt_io, S4_pstorerbt_rr },
15319 { S2_pstorerdf_io, S4_pstorerdf_rr },
15320 { S2_pstorerdt_io, S4_pstorerdt_rr },
15321 { S2_pstorerff_io, S4_pstorerff_rr },
15322 { S2_pstorerft_io, S4_pstorerft_rr },
15323 { S2_pstorerhf_io, S4_pstorerhf_rr },
15324 { S2_pstorerhnewf_io, S4_pstorerhnewf_rr },
15325 { S2_pstorerhnewt_io, S4_pstorerhnewt_rr },
15326 { S2_pstorerht_io, S4_pstorerht_rr },
15327 { S2_pstorerif_io, S4_pstorerif_rr },
15328 { S2_pstorerinewf_io, S4_pstorerinewf_rr },
15329 { S2_pstorerinewt_io, S4_pstorerinewt_rr },
15330 { S2_pstorerit_io, S4_pstorerit_rr },
15331 { S2_storerb_io, S4_storerb_rr },
15332 { S2_storerbnew_io, S4_storerbnew_rr },
15333 { S2_storerd_io, S4_storerd_rr },
15334 { S2_storerf_io, S4_storerf_rr },
15335 { S2_storerh_io, S4_storerh_rr },
15336 { S2_storerhnew_io, S4_storerhnew_rr },
15337 { S2_storeri_io, S4_storeri_rr },
15338 { S2_storerinew_io, S4_storerinew_rr },
15339 { S4_pstorerbfnew_io, S4_pstorerbfnew_rr },
15340 { S4_pstorerbnewfnew_io, S4_pstorerbnewfnew_rr },
15341 { S4_pstorerbnewtnew_io, S4_pstorerbnewtnew_rr },
15342 { S4_pstorerbtnew_io, S4_pstorerbtnew_rr },
15343 { S4_pstorerdfnew_io, S4_pstorerdfnew_rr },
15344 { S4_pstorerdtnew_io, S4_pstorerdtnew_rr },
15345 { S4_pstorerffnew_io, S4_pstorerffnew_rr },
15346 { S4_pstorerftnew_io, S4_pstorerftnew_rr },
15347 { S4_pstorerhfnew_io, S4_pstorerhfnew_rr },
15348 { S4_pstorerhnewfnew_io, S4_pstorerhnewfnew_rr },
15349 { S4_pstorerhnewtnew_io, S4_pstorerhnewtnew_rr },
15350 { S4_pstorerhtnew_io, S4_pstorerhtnew_rr },
15351 { S4_pstorerifnew_io, S4_pstorerifnew_rr },
15352 { S4_pstorerinewfnew_io, S4_pstorerinewfnew_rr },
15353 { S4_pstorerinewtnew_io, S4_pstorerinewtnew_rr },
15354 { S4_pstoreritnew_io, S4_pstoreritnew_rr },
15355 }; // End of Table
15356
15357 unsigned mid;
15358 unsigned start = 0;
15359 unsigned end = 70;
15360 while (start < end) {
15361 mid = start + (end - start) / 2;
15362 if (Opcode == Table[mid][0])
15363 break;
15364 if (Opcode < Table[mid][0])
15365 end = mid;
15366 else
15367 start = mid + 1;
15368 }
15369 if (start == end)
15370 return -1; // Instruction doesn't exist in this table.
15371
15372 return Table[mid][1];
15373}
15374
15375// changeAddrMode_pi_io
15376LLVM_READONLY
15377int changeAddrMode_pi_io(uint16_t Opcode) {
15378 using namespace Hexagon;
15379 static constexpr uint16_t Table[][2] = {
15380 { L2_loadrb_pi, L2_loadrb_io },
15381 { L2_loadrd_pi, L2_loadrd_io },
15382 { L2_loadrh_pi, L2_loadrh_io },
15383 { L2_loadri_pi, L2_loadri_io },
15384 { L2_loadrub_pi, L2_loadrub_io },
15385 { L2_loadruh_pi, L2_loadruh_io },
15386 { S2_storerb_pi, S2_storerb_io },
15387 { S2_storerd_pi, S2_storerd_io },
15388 { S2_storerf_pi, S2_storerf_io },
15389 { S2_storerh_pi, S2_storerh_io },
15390 { S2_storeri_pi, S2_storeri_io },
15391 { V6_vL32Ub_pi, V6_vL32Ub_ai },
15392 { V6_vL32b_cur_pi, V6_vL32b_cur_ai },
15393 { V6_vL32b_nt_cur_pi, V6_vL32b_nt_cur_ai },
15394 { V6_vL32b_nt_pi, V6_vL32b_nt_ai },
15395 { V6_vL32b_nt_tmp_pi, V6_vL32b_nt_tmp_ai },
15396 { V6_vL32b_pi, V6_vL32b_ai },
15397 { V6_vL32b_tmp_pi, V6_vL32b_tmp_ai },
15398 { V6_vS32Ub_pi, V6_vS32Ub_ai },
15399 { V6_vS32b_new_pi, V6_vS32b_new_ai },
15400 { V6_vS32b_nt_new_pi, V6_vS32b_nt_new_ai },
15401 { V6_vS32b_nt_pi, V6_vS32b_nt_ai },
15402 { V6_vS32b_pi, V6_vS32b_ai },
15403 { V6_zLd_pi, V6_zLd_ai },
15404 }; // End of Table
15405
15406 unsigned mid;
15407 unsigned start = 0;
15408 unsigned end = 24;
15409 while (start < end) {
15410 mid = start + (end - start) / 2;
15411 if (Opcode == Table[mid][0])
15412 break;
15413 if (Opcode < Table[mid][0])
15414 end = mid;
15415 else
15416 start = mid + 1;
15417 }
15418 if (start == end)
15419 return -1; // Instruction doesn't exist in this table.
15420
15421 return Table[mid][1];
15422}
15423
15424// changeAddrMode_rr_io
15425LLVM_READONLY
15426int changeAddrMode_rr_io(uint16_t Opcode) {
15427 using namespace Hexagon;
15428 static constexpr uint16_t Table[][2] = {
15429 { L4_loadrb_rr, L2_loadrb_io },
15430 { L4_loadrd_rr, L2_loadrd_io },
15431 { L4_loadrh_rr, L2_loadrh_io },
15432 { L4_loadri_rr, L2_loadri_io },
15433 { L4_loadrub_rr, L2_loadrub_io },
15434 { L4_loadruh_rr, L2_loadruh_io },
15435 { L4_ploadrbf_rr, L2_ploadrbf_io },
15436 { L4_ploadrbfnew_rr, L2_ploadrbfnew_io },
15437 { L4_ploadrbt_rr, L2_ploadrbt_io },
15438 { L4_ploadrbtnew_rr, L2_ploadrbtnew_io },
15439 { L4_ploadrdf_rr, L2_ploadrdf_io },
15440 { L4_ploadrdfnew_rr, L2_ploadrdfnew_io },
15441 { L4_ploadrdt_rr, L2_ploadrdt_io },
15442 { L4_ploadrdtnew_rr, L2_ploadrdtnew_io },
15443 { L4_ploadrhf_rr, L2_ploadrhf_io },
15444 { L4_ploadrhfnew_rr, L2_ploadrhfnew_io },
15445 { L4_ploadrht_rr, L2_ploadrht_io },
15446 { L4_ploadrhtnew_rr, L2_ploadrhtnew_io },
15447 { L4_ploadrif_rr, L2_ploadrif_io },
15448 { L4_ploadrifnew_rr, L2_ploadrifnew_io },
15449 { L4_ploadrit_rr, L2_ploadrit_io },
15450 { L4_ploadritnew_rr, L2_ploadritnew_io },
15451 { L4_ploadrubf_rr, L2_ploadrubf_io },
15452 { L4_ploadrubfnew_rr, L2_ploadrubfnew_io },
15453 { L4_ploadrubt_rr, L2_ploadrubt_io },
15454 { L4_ploadrubtnew_rr, L2_ploadrubtnew_io },
15455 { L4_ploadruhf_rr, L2_ploadruhf_io },
15456 { L4_ploadruhfnew_rr, L2_ploadruhfnew_io },
15457 { L4_ploadruht_rr, L2_ploadruht_io },
15458 { L4_ploadruhtnew_rr, L2_ploadruhtnew_io },
15459 { S4_pstorerbf_rr, S2_pstorerbf_io },
15460 { S4_pstorerbfnew_rr, S4_pstorerbfnew_io },
15461 { S4_pstorerbnewf_rr, S2_pstorerbnewf_io },
15462 { S4_pstorerbnewfnew_rr, S4_pstorerbnewfnew_io },
15463 { S4_pstorerbnewt_rr, S2_pstorerbnewt_io },
15464 { S4_pstorerbnewtnew_rr, S4_pstorerbnewtnew_io },
15465 { S4_pstorerbt_rr, S2_pstorerbt_io },
15466 { S4_pstorerbtnew_rr, S4_pstorerbtnew_io },
15467 { S4_pstorerdf_rr, S2_pstorerdf_io },
15468 { S4_pstorerdfnew_rr, S4_pstorerdfnew_io },
15469 { S4_pstorerdt_rr, S2_pstorerdt_io },
15470 { S4_pstorerdtnew_rr, S4_pstorerdtnew_io },
15471 { S4_pstorerff_rr, S2_pstorerff_io },
15472 { S4_pstorerffnew_rr, S4_pstorerffnew_io },
15473 { S4_pstorerft_rr, S2_pstorerft_io },
15474 { S4_pstorerftnew_rr, S4_pstorerftnew_io },
15475 { S4_pstorerhf_rr, S2_pstorerhf_io },
15476 { S4_pstorerhfnew_rr, S4_pstorerhfnew_io },
15477 { S4_pstorerhnewf_rr, S2_pstorerhnewf_io },
15478 { S4_pstorerhnewfnew_rr, S4_pstorerhnewfnew_io },
15479 { S4_pstorerhnewt_rr, S2_pstorerhnewt_io },
15480 { S4_pstorerhnewtnew_rr, S4_pstorerhnewtnew_io },
15481 { S4_pstorerht_rr, S2_pstorerht_io },
15482 { S4_pstorerhtnew_rr, S4_pstorerhtnew_io },
15483 { S4_pstorerif_rr, S2_pstorerif_io },
15484 { S4_pstorerifnew_rr, S4_pstorerifnew_io },
15485 { S4_pstorerinewf_rr, S2_pstorerinewf_io },
15486 { S4_pstorerinewfnew_rr, S4_pstorerinewfnew_io },
15487 { S4_pstorerinewt_rr, S2_pstorerinewt_io },
15488 { S4_pstorerinewtnew_rr, S4_pstorerinewtnew_io },
15489 { S4_pstorerit_rr, S2_pstorerit_io },
15490 { S4_pstoreritnew_rr, S4_pstoreritnew_io },
15491 { S4_storerb_rr, S2_storerb_io },
15492 { S4_storerbnew_rr, S2_storerbnew_io },
15493 { S4_storerd_rr, S2_storerd_io },
15494 { S4_storerf_rr, S2_storerf_io },
15495 { S4_storerh_rr, S2_storerh_io },
15496 { S4_storerhnew_rr, S2_storerhnew_io },
15497 { S4_storeri_rr, S2_storeri_io },
15498 { S4_storerinew_rr, S2_storerinew_io },
15499 }; // End of Table
15500
15501 unsigned mid;
15502 unsigned start = 0;
15503 unsigned end = 70;
15504 while (start < end) {
15505 mid = start + (end - start) / 2;
15506 if (Opcode == Table[mid][0])
15507 break;
15508 if (Opcode < Table[mid][0])
15509 end = mid;
15510 else
15511 start = mid + 1;
15512 }
15513 if (start == end)
15514 return -1; // Instruction doesn't exist in this table.
15515
15516 return Table[mid][1];
15517}
15518
15519// changeAddrMode_rr_ur
15520LLVM_READONLY
15521int changeAddrMode_rr_ur(uint16_t Opcode) {
15522 using namespace Hexagon;
15523 static constexpr uint16_t Table[][2] = {
15524 { L4_loadrb_rr, L4_loadrb_ur },
15525 { L4_loadrd_rr, L4_loadrd_ur },
15526 { L4_loadrh_rr, L4_loadrh_ur },
15527 { L4_loadri_rr, L4_loadri_ur },
15528 { L4_loadrub_rr, L4_loadrub_ur },
15529 { L4_loadruh_rr, L4_loadruh_ur },
15530 { S4_storerb_rr, S4_storerb_ur },
15531 { S4_storerd_rr, S4_storerd_ur },
15532 { S4_storerf_rr, S4_storerf_ur },
15533 { S4_storerh_rr, S4_storerh_ur },
15534 { S4_storeri_rr, S4_storeri_ur },
15535 }; // End of Table
15536
15537 unsigned mid;
15538 unsigned start = 0;
15539 unsigned end = 11;
15540 while (start < end) {
15541 mid = start + (end - start) / 2;
15542 if (Opcode == Table[mid][0])
15543 break;
15544 if (Opcode < Table[mid][0])
15545 end = mid;
15546 else
15547 start = mid + 1;
15548 }
15549 if (start == end)
15550 return -1; // Instruction doesn't exist in this table.
15551
15552 return Table[mid][1];
15553}
15554
15555// changeAddrMode_ur_rr
15556LLVM_READONLY
15557int changeAddrMode_ur_rr(uint16_t Opcode) {
15558 using namespace Hexagon;
15559 static constexpr uint16_t Table[][2] = {
15560 { L4_loadrb_ur, L4_loadrb_rr },
15561 { L4_loadrd_ur, L4_loadrd_rr },
15562 { L4_loadrh_ur, L4_loadrh_rr },
15563 { L4_loadri_ur, L4_loadri_rr },
15564 { L4_loadrub_ur, L4_loadrub_rr },
15565 { L4_loadruh_ur, L4_loadruh_rr },
15566 { S4_storerb_ur, S4_storerb_rr },
15567 { S4_storerd_ur, S4_storerd_rr },
15568 { S4_storerf_ur, S4_storerf_rr },
15569 { S4_storerh_ur, S4_storerh_rr },
15570 { S4_storeri_ur, S4_storeri_rr },
15571 }; // End of Table
15572
15573 unsigned mid;
15574 unsigned start = 0;
15575 unsigned end = 11;
15576 while (start < end) {
15577 mid = start + (end - start) / 2;
15578 if (Opcode == Table[mid][0])
15579 break;
15580 if (Opcode < Table[mid][0])
15581 end = mid;
15582 else
15583 start = mid + 1;
15584 }
15585 if (start == end)
15586 return -1; // Instruction doesn't exist in this table.
15587
15588 return Table[mid][1];
15589}
15590
15591// getFalsePredOpcode
15592LLVM_READONLY
15593int getFalsePredOpcode(uint16_t Opcode) {
15594 using namespace Hexagon;
15595 static constexpr uint16_t Table[][2] = {
15596 { A2_tfrpt, A2_tfrpf },
15597 { A2_tfrptnew, A2_tfrpfnew },
15598 { A2_tfrt, A2_tfrf },
15599 { A2_tfrtnew, A2_tfrfnew },
15600 { A2_paddit, A2_paddif },
15601 { A2_padditnew, A2_paddifnew },
15602 { A2_paddt, A2_paddf },
15603 { A2_paddtnew, A2_paddfnew },
15604 { A2_pandt, A2_pandf },
15605 { A2_pandtnew, A2_pandfnew },
15606 { A2_port, A2_porf },
15607 { A2_portnew, A2_porfnew },
15608 { A2_psubt, A2_psubf },
15609 { A2_psubtnew, A2_psubfnew },
15610 { A2_pxort, A2_pxorf },
15611 { A2_pxortnew, A2_pxorfnew },
15612 { A4_paslht, A4_paslhf },
15613 { A4_paslhtnew, A4_paslhfnew },
15614 { A4_pasrht, A4_pasrhf },
15615 { A4_pasrhtnew, A4_pasrhfnew },
15616 { A4_psxtbt, A4_psxtbf },
15617 { A4_psxtbtnew, A4_psxtbfnew },
15618 { A4_psxtht, A4_psxthf },
15619 { A4_psxthtnew, A4_psxthfnew },
15620 { A4_pzxtbt, A4_pzxtbf },
15621 { A4_pzxtbtnew, A4_pzxtbfnew },
15622 { A4_pzxtht, A4_pzxthf },
15623 { A4_pzxthtnew, A4_pzxthfnew },
15624 { C2_ccombinewnewt, C2_ccombinewnewf },
15625 { C2_ccombinewt, C2_ccombinewf },
15626 { C2_cmoveit, C2_cmoveif },
15627 { C2_cmovenewit, C2_cmovenewif },
15628 { J2_callt, J2_callf },
15629 { J2_jumprt, J2_jumprf },
15630 { J2_jumprtnew, J2_jumprfnew },
15631 { J2_jumprtnewpt, J2_jumprfnewpt },
15632 { J2_jumprtpt, J2_jumprfpt },
15633 { J2_jumpt, J2_jumpf },
15634 { J2_jumptnew, J2_jumpfnew },
15635 { J2_jumptnewpt, J2_jumpfnewpt },
15636 { J2_jumptpt, J2_jumpfpt },
15637 { J4_cmpeq_t_jumpnv_nt, J4_cmpeq_f_jumpnv_nt },
15638 { J4_cmpeq_t_jumpnv_t, J4_cmpeq_f_jumpnv_t },
15639 { J4_cmpeq_tp0_jump_nt, J4_cmpeq_fp0_jump_nt },
15640 { J4_cmpeq_tp0_jump_t, J4_cmpeq_fp0_jump_t },
15641 { J4_cmpeq_tp1_jump_nt, J4_cmpeq_fp1_jump_nt },
15642 { J4_cmpeq_tp1_jump_t, J4_cmpeq_fp1_jump_t },
15643 { J4_cmpeqi_t_jumpnv_nt, J4_cmpeqi_f_jumpnv_nt },
15644 { J4_cmpeqi_t_jumpnv_t, J4_cmpeqi_f_jumpnv_t },
15645 { J4_cmpeqi_tp0_jump_nt, J4_cmpeqi_fp0_jump_nt },
15646 { J4_cmpeqi_tp0_jump_t, J4_cmpeqi_fp0_jump_t },
15647 { J4_cmpeqi_tp1_jump_nt, J4_cmpeqi_fp1_jump_nt },
15648 { J4_cmpeqi_tp1_jump_t, J4_cmpeqi_fp1_jump_t },
15649 { J4_cmpeqn1_t_jumpnv_nt, J4_cmpeqn1_f_jumpnv_nt },
15650 { J4_cmpeqn1_t_jumpnv_t, J4_cmpeqn1_f_jumpnv_t },
15651 { J4_cmpeqn1_tp0_jump_nt, J4_cmpeqn1_fp0_jump_nt },
15652 { J4_cmpeqn1_tp0_jump_t, J4_cmpeqn1_fp0_jump_t },
15653 { J4_cmpeqn1_tp1_jump_nt, J4_cmpeqn1_fp1_jump_nt },
15654 { J4_cmpeqn1_tp1_jump_t, J4_cmpeqn1_fp1_jump_t },
15655 { J4_cmpgt_t_jumpnv_nt, J4_cmpgt_f_jumpnv_nt },
15656 { J4_cmpgt_t_jumpnv_t, J4_cmpgt_f_jumpnv_t },
15657 { J4_cmpgt_tp0_jump_nt, J4_cmpgt_fp0_jump_nt },
15658 { J4_cmpgt_tp0_jump_t, J4_cmpgt_fp0_jump_t },
15659 { J4_cmpgt_tp1_jump_nt, J4_cmpgt_fp1_jump_nt },
15660 { J4_cmpgt_tp1_jump_t, J4_cmpgt_fp1_jump_t },
15661 { J4_cmpgti_t_jumpnv_nt, J4_cmpgti_f_jumpnv_nt },
15662 { J4_cmpgti_t_jumpnv_t, J4_cmpgti_f_jumpnv_t },
15663 { J4_cmpgti_tp0_jump_nt, J4_cmpgti_fp0_jump_nt },
15664 { J4_cmpgti_tp0_jump_t, J4_cmpgti_fp0_jump_t },
15665 { J4_cmpgti_tp1_jump_nt, J4_cmpgti_fp1_jump_nt },
15666 { J4_cmpgti_tp1_jump_t, J4_cmpgti_fp1_jump_t },
15667 { J4_cmpgtn1_t_jumpnv_nt, J4_cmpgtn1_f_jumpnv_nt },
15668 { J4_cmpgtn1_t_jumpnv_t, J4_cmpgtn1_f_jumpnv_t },
15669 { J4_cmpgtn1_tp0_jump_nt, J4_cmpgtn1_fp0_jump_nt },
15670 { J4_cmpgtn1_tp0_jump_t, J4_cmpgtn1_fp0_jump_t },
15671 { J4_cmpgtn1_tp1_jump_nt, J4_cmpgtn1_fp1_jump_nt },
15672 { J4_cmpgtn1_tp1_jump_t, J4_cmpgtn1_fp1_jump_t },
15673 { J4_cmpgtu_t_jumpnv_nt, J4_cmpgtu_f_jumpnv_nt },
15674 { J4_cmpgtu_t_jumpnv_t, J4_cmpgtu_f_jumpnv_t },
15675 { J4_cmpgtu_tp0_jump_nt, J4_cmpgtu_fp0_jump_nt },
15676 { J4_cmpgtu_tp0_jump_t, J4_cmpgtu_fp0_jump_t },
15677 { J4_cmpgtu_tp1_jump_nt, J4_cmpgtu_fp1_jump_nt },
15678 { J4_cmpgtu_tp1_jump_t, J4_cmpgtu_fp1_jump_t },
15679 { J4_cmpgtui_t_jumpnv_nt, J4_cmpgtui_f_jumpnv_nt },
15680 { J4_cmpgtui_t_jumpnv_t, J4_cmpgtui_f_jumpnv_t },
15681 { J4_cmpgtui_tp0_jump_nt, J4_cmpgtui_fp0_jump_nt },
15682 { J4_cmpgtui_tp0_jump_t, J4_cmpgtui_fp0_jump_t },
15683 { J4_cmpgtui_tp1_jump_nt, J4_cmpgtui_fp1_jump_nt },
15684 { J4_cmpgtui_tp1_jump_t, J4_cmpgtui_fp1_jump_t },
15685 { J4_cmplt_t_jumpnv_nt, J4_cmplt_f_jumpnv_nt },
15686 { J4_cmplt_t_jumpnv_t, J4_cmplt_f_jumpnv_t },
15687 { J4_cmpltu_t_jumpnv_nt, J4_cmpltu_f_jumpnv_nt },
15688 { J4_cmpltu_t_jumpnv_t, J4_cmpltu_f_jumpnv_t },
15689 { L2_ploadrbt_io, L2_ploadrbf_io },
15690 { L2_ploadrbt_pi, L2_ploadrbf_pi },
15691 { L2_ploadrbtnew_io, L2_ploadrbfnew_io },
15692 { L2_ploadrbtnew_pi, L2_ploadrbfnew_pi },
15693 { L2_ploadrdt_io, L2_ploadrdf_io },
15694 { L2_ploadrdt_pi, L2_ploadrdf_pi },
15695 { L2_ploadrdtnew_io, L2_ploadrdfnew_io },
15696 { L2_ploadrdtnew_pi, L2_ploadrdfnew_pi },
15697 { L2_ploadrht_io, L2_ploadrhf_io },
15698 { L2_ploadrht_pi, L2_ploadrhf_pi },
15699 { L2_ploadrhtnew_io, L2_ploadrhfnew_io },
15700 { L2_ploadrhtnew_pi, L2_ploadrhfnew_pi },
15701 { L2_ploadrit_io, L2_ploadrif_io },
15702 { L2_ploadrit_pi, L2_ploadrif_pi },
15703 { L2_ploadritnew_io, L2_ploadrifnew_io },
15704 { L2_ploadritnew_pi, L2_ploadrifnew_pi },
15705 { L2_ploadrubt_io, L2_ploadrubf_io },
15706 { L2_ploadrubt_pi, L2_ploadrubf_pi },
15707 { L2_ploadrubtnew_io, L2_ploadrubfnew_io },
15708 { L2_ploadrubtnew_pi, L2_ploadrubfnew_pi },
15709 { L2_ploadruht_io, L2_ploadruhf_io },
15710 { L2_ploadruht_pi, L2_ploadruhf_pi },
15711 { L2_ploadruhtnew_io, L2_ploadruhfnew_io },
15712 { L2_ploadruhtnew_pi, L2_ploadruhfnew_pi },
15713 { L4_ploadrbt_abs, L4_ploadrbf_abs },
15714 { L4_ploadrbt_rr, L4_ploadrbf_rr },
15715 { L4_ploadrbtnew_abs, L4_ploadrbfnew_abs },
15716 { L4_ploadrbtnew_rr, L4_ploadrbfnew_rr },
15717 { L4_ploadrdt_abs, L4_ploadrdf_abs },
15718 { L4_ploadrdt_rr, L4_ploadrdf_rr },
15719 { L4_ploadrdtnew_abs, L4_ploadrdfnew_abs },
15720 { L4_ploadrdtnew_rr, L4_ploadrdfnew_rr },
15721 { L4_ploadrht_abs, L4_ploadrhf_abs },
15722 { L4_ploadrht_rr, L4_ploadrhf_rr },
15723 { L4_ploadrhtnew_abs, L4_ploadrhfnew_abs },
15724 { L4_ploadrhtnew_rr, L4_ploadrhfnew_rr },
15725 { L4_ploadrit_abs, L4_ploadrif_abs },
15726 { L4_ploadrit_rr, L4_ploadrif_rr },
15727 { L4_ploadritnew_abs, L4_ploadrifnew_abs },
15728 { L4_ploadritnew_rr, L4_ploadrifnew_rr },
15729 { L4_ploadrubt_abs, L4_ploadrubf_abs },
15730 { L4_ploadrubt_rr, L4_ploadrubf_rr },
15731 { L4_ploadrubtnew_abs, L4_ploadrubfnew_abs },
15732 { L4_ploadrubtnew_rr, L4_ploadrubfnew_rr },
15733 { L4_ploadruht_abs, L4_ploadruhf_abs },
15734 { L4_ploadruht_rr, L4_ploadruhf_rr },
15735 { L4_ploadruhtnew_abs, L4_ploadruhfnew_abs },
15736 { L4_ploadruhtnew_rr, L4_ploadruhfnew_rr },
15737 { L4_return_t, L4_return_f },
15738 { L4_return_tnew_pnt, L4_return_fnew_pnt },
15739 { L4_return_tnew_pt, L4_return_fnew_pt },
15740 { PS_jmprett, PS_jmpretf },
15741 { PS_jmprettnew, PS_jmpretfnew },
15742 { PS_jmprettnewpt, PS_jmpretfnewpt },
15743 { S2_pstorerbnewt_io, S2_pstorerbnewf_io },
15744 { S2_pstorerbnewt_pi, S2_pstorerbnewf_pi },
15745 { S2_pstorerbnewtnew_pi, S2_pstorerbnewfnew_pi },
15746 { S2_pstorerbt_io, S2_pstorerbf_io },
15747 { S2_pstorerbt_pi, S2_pstorerbf_pi },
15748 { S2_pstorerbtnew_pi, S2_pstorerbfnew_pi },
15749 { S2_pstorerdt_io, S2_pstorerdf_io },
15750 { S2_pstorerdt_pi, S2_pstorerdf_pi },
15751 { S2_pstorerdtnew_pi, S2_pstorerdfnew_pi },
15752 { S2_pstorerft_io, S2_pstorerff_io },
15753 { S2_pstorerft_pi, S2_pstorerff_pi },
15754 { S2_pstorerftnew_pi, S2_pstorerffnew_pi },
15755 { S2_pstorerhnewt_io, S2_pstorerhnewf_io },
15756 { S2_pstorerhnewt_pi, S2_pstorerhnewf_pi },
15757 { S2_pstorerhnewtnew_pi, S2_pstorerhnewfnew_pi },
15758 { S2_pstorerht_io, S2_pstorerhf_io },
15759 { S2_pstorerht_pi, S2_pstorerhf_pi },
15760 { S2_pstorerhtnew_pi, S2_pstorerhfnew_pi },
15761 { S2_pstorerinewt_io, S2_pstorerinewf_io },
15762 { S2_pstorerinewt_pi, S2_pstorerinewf_pi },
15763 { S2_pstorerinewtnew_pi, S2_pstorerinewfnew_pi },
15764 { S2_pstorerit_io, S2_pstorerif_io },
15765 { S2_pstorerit_pi, S2_pstorerif_pi },
15766 { S2_pstoreritnew_pi, S2_pstorerifnew_pi },
15767 { S4_pstorerbnewt_abs, S4_pstorerbnewf_abs },
15768 { S4_pstorerbnewt_rr, S4_pstorerbnewf_rr },
15769 { S4_pstorerbnewtnew_abs, S4_pstorerbnewfnew_abs },
15770 { S4_pstorerbnewtnew_io, S4_pstorerbnewfnew_io },
15771 { S4_pstorerbnewtnew_rr, S4_pstorerbnewfnew_rr },
15772 { S4_pstorerbt_abs, S4_pstorerbf_abs },
15773 { S4_pstorerbt_rr, S4_pstorerbf_rr },
15774 { S4_pstorerbtnew_abs, S4_pstorerbfnew_abs },
15775 { S4_pstorerbtnew_io, S4_pstorerbfnew_io },
15776 { S4_pstorerbtnew_rr, S4_pstorerbfnew_rr },
15777 { S4_pstorerdt_abs, S4_pstorerdf_abs },
15778 { S4_pstorerdt_rr, S4_pstorerdf_rr },
15779 { S4_pstorerdtnew_abs, S4_pstorerdfnew_abs },
15780 { S4_pstorerdtnew_io, S4_pstorerdfnew_io },
15781 { S4_pstorerdtnew_rr, S4_pstorerdfnew_rr },
15782 { S4_pstorerft_abs, S4_pstorerff_abs },
15783 { S4_pstorerft_rr, S4_pstorerff_rr },
15784 { S4_pstorerftnew_abs, S4_pstorerffnew_abs },
15785 { S4_pstorerftnew_io, S4_pstorerffnew_io },
15786 { S4_pstorerftnew_rr, S4_pstorerffnew_rr },
15787 { S4_pstorerhnewt_abs, S4_pstorerhnewf_abs },
15788 { S4_pstorerhnewt_rr, S4_pstorerhnewf_rr },
15789 { S4_pstorerhnewtnew_abs, S4_pstorerhnewfnew_abs },
15790 { S4_pstorerhnewtnew_io, S4_pstorerhnewfnew_io },
15791 { S4_pstorerhnewtnew_rr, S4_pstorerhnewfnew_rr },
15792 { S4_pstorerht_abs, S4_pstorerhf_abs },
15793 { S4_pstorerht_rr, S4_pstorerhf_rr },
15794 { S4_pstorerhtnew_abs, S4_pstorerhfnew_abs },
15795 { S4_pstorerhtnew_io, S4_pstorerhfnew_io },
15796 { S4_pstorerhtnew_rr, S4_pstorerhfnew_rr },
15797 { S4_pstorerinewt_abs, S4_pstorerinewf_abs },
15798 { S4_pstorerinewt_rr, S4_pstorerinewf_rr },
15799 { S4_pstorerinewtnew_abs, S4_pstorerinewfnew_abs },
15800 { S4_pstorerinewtnew_io, S4_pstorerinewfnew_io },
15801 { S4_pstorerinewtnew_rr, S4_pstorerinewfnew_rr },
15802 { S4_pstorerit_abs, S4_pstorerif_abs },
15803 { S4_pstorerit_rr, S4_pstorerif_rr },
15804 { S4_pstoreritnew_abs, S4_pstorerifnew_abs },
15805 { S4_pstoreritnew_io, S4_pstorerifnew_io },
15806 { S4_pstoreritnew_rr, S4_pstorerifnew_rr },
15807 { S4_storeirbt_io, S4_storeirbf_io },
15808 { S4_storeirbtnew_io, S4_storeirbfnew_io },
15809 { S4_storeirht_io, S4_storeirhf_io },
15810 { S4_storeirhtnew_io, S4_storeirhfnew_io },
15811 { S4_storeirit_io, S4_storeirif_io },
15812 { S4_storeiritnew_io, S4_storeirifnew_io },
15813 { V6_vL32b_cur_pred_ai, V6_vL32b_cur_npred_ai },
15814 { V6_vL32b_cur_pred_pi, V6_vL32b_cur_npred_pi },
15815 { V6_vL32b_cur_pred_ppu, V6_vL32b_cur_npred_ppu },
15816 { V6_vL32b_nt_cur_pred_ai, V6_vL32b_nt_cur_npred_ai },
15817 { V6_vL32b_nt_cur_pred_pi, V6_vL32b_nt_cur_npred_pi },
15818 { V6_vL32b_nt_cur_pred_ppu, V6_vL32b_nt_cur_npred_ppu },
15819 { V6_vL32b_nt_pred_ai, V6_vL32b_nt_npred_ai },
15820 { V6_vL32b_nt_pred_pi, V6_vL32b_nt_npred_pi },
15821 { V6_vL32b_nt_pred_ppu, V6_vL32b_nt_npred_ppu },
15822 { V6_vL32b_nt_tmp_pred_ai, V6_vL32b_nt_tmp_npred_ai },
15823 { V6_vL32b_nt_tmp_pred_pi, V6_vL32b_nt_tmp_npred_pi },
15824 { V6_vL32b_nt_tmp_pred_ppu, V6_vL32b_nt_tmp_npred_ppu },
15825 { V6_vL32b_pred_ai, V6_vL32b_npred_ai },
15826 { V6_vL32b_pred_pi, V6_vL32b_npred_pi },
15827 { V6_vL32b_pred_ppu, V6_vL32b_npred_ppu },
15828 { V6_vL32b_tmp_pred_ai, V6_vL32b_tmp_npred_ai },
15829 { V6_vL32b_tmp_pred_pi, V6_vL32b_tmp_npred_pi },
15830 { V6_vL32b_tmp_pred_ppu, V6_vL32b_tmp_npred_ppu },
15831 { V6_vS32Ub_pred_ai, V6_vS32Ub_npred_ai },
15832 { V6_vS32Ub_pred_pi, V6_vS32Ub_npred_pi },
15833 { V6_vS32Ub_pred_ppu, V6_vS32Ub_npred_ppu },
15834 { V6_vS32b_new_pred_ai, V6_vS32b_new_npred_ai },
15835 { V6_vS32b_new_pred_pi, V6_vS32b_new_npred_pi },
15836 { V6_vS32b_new_pred_ppu, V6_vS32b_new_npred_ppu },
15837 { V6_vS32b_nt_new_pred_ai, V6_vS32b_nt_new_npred_ai },
15838 { V6_vS32b_nt_new_pred_pi, V6_vS32b_nt_new_npred_pi },
15839 { V6_vS32b_nt_new_pred_ppu, V6_vS32b_nt_new_npred_ppu },
15840 { V6_vS32b_nt_pred_ai, V6_vS32b_nt_npred_ai },
15841 { V6_vS32b_nt_pred_pi, V6_vS32b_nt_npred_pi },
15842 { V6_vS32b_nt_pred_ppu, V6_vS32b_nt_npred_ppu },
15843 { V6_vS32b_pred_ai, V6_vS32b_npred_ai },
15844 { V6_vS32b_pred_pi, V6_vS32b_npred_pi },
15845 { V6_vS32b_pred_ppu, V6_vS32b_npred_ppu },
15846 }; // End of Table
15847
15848 unsigned mid;
15849 unsigned start = 0;
15850 unsigned end = 250;
15851 while (start < end) {
15852 mid = start + (end - start) / 2;
15853 if (Opcode == Table[mid][0])
15854 break;
15855 if (Opcode < Table[mid][0])
15856 end = mid;
15857 else
15858 start = mid + 1;
15859 }
15860 if (start == end)
15861 return -1; // Instruction doesn't exist in this table.
15862
15863 return Table[mid][1];
15864}
15865
15866// getNewValueOpcode
15867LLVM_READONLY
15868int getNewValueOpcode(uint16_t Opcode) {
15869 using namespace Hexagon;
15870 static constexpr uint16_t Table[][2] = {
15871 { PS_storerbabs, PS_storerbnewabs },
15872 { PS_storerhabs, PS_storerhnewabs },
15873 { PS_storeriabs, PS_storerinewabs },
15874 { S2_pstorerbf_io, S2_pstorerbnewf_io },
15875 { S2_pstorerbf_pi, S2_pstorerbnewf_pi },
15876 { S2_pstorerbfnew_pi, S2_pstorerbnewfnew_pi },
15877 { S2_pstorerbt_io, S2_pstorerbnewt_io },
15878 { S2_pstorerbt_pi, S2_pstorerbnewt_pi },
15879 { S2_pstorerbtnew_pi, S2_pstorerbnewtnew_pi },
15880 { S2_pstorerhf_io, S2_pstorerhnewf_io },
15881 { S2_pstorerhf_pi, S2_pstorerhnewf_pi },
15882 { S2_pstorerhfnew_pi, S2_pstorerhnewfnew_pi },
15883 { S2_pstorerht_io, S2_pstorerhnewt_io },
15884 { S2_pstorerht_pi, S2_pstorerhnewt_pi },
15885 { S2_pstorerhtnew_pi, S2_pstorerhnewtnew_pi },
15886 { S2_pstorerif_io, S2_pstorerinewf_io },
15887 { S2_pstorerif_pi, S2_pstorerinewf_pi },
15888 { S2_pstorerifnew_pi, S2_pstorerinewfnew_pi },
15889 { S2_pstorerit_io, S2_pstorerinewt_io },
15890 { S2_pstorerit_pi, S2_pstorerinewt_pi },
15891 { S2_pstoreritnew_pi, S2_pstorerinewtnew_pi },
15892 { S2_storerb_io, S2_storerbnew_io },
15893 { S2_storerb_pbr, S2_storerbnew_pbr },
15894 { S2_storerb_pci, S2_storerbnew_pci },
15895 { S2_storerb_pcr, S2_storerbnew_pcr },
15896 { S2_storerb_pi, S2_storerbnew_pi },
15897 { S2_storerb_pr, S2_storerbnew_pr },
15898 { S2_storerbgp, S2_storerbnewgp },
15899 { S2_storerh_io, S2_storerhnew_io },
15900 { S2_storerh_pbr, S2_storerhnew_pbr },
15901 { S2_storerh_pci, S2_storerhnew_pci },
15902 { S2_storerh_pcr, S2_storerhnew_pcr },
15903 { S2_storerh_pi, S2_storerhnew_pi },
15904 { S2_storerh_pr, S2_storerhnew_pr },
15905 { S2_storerhgp, S2_storerhnewgp },
15906 { S2_storeri_io, S2_storerinew_io },
15907 { S2_storeri_pbr, S2_storerinew_pbr },
15908 { S2_storeri_pci, S2_storerinew_pci },
15909 { S2_storeri_pcr, S2_storerinew_pcr },
15910 { S2_storeri_pi, S2_storerinew_pi },
15911 { S2_storeri_pr, S2_storerinew_pr },
15912 { S2_storerigp, S2_storerinewgp },
15913 { S4_pstorerbf_abs, S4_pstorerbnewf_abs },
15914 { S4_pstorerbf_rr, S4_pstorerbnewf_rr },
15915 { S4_pstorerbfnew_abs, S4_pstorerbnewfnew_abs },
15916 { S4_pstorerbfnew_io, S4_pstorerbnewfnew_io },
15917 { S4_pstorerbfnew_rr, S4_pstorerbnewfnew_rr },
15918 { S4_pstorerbt_abs, S4_pstorerbnewt_abs },
15919 { S4_pstorerbt_rr, S4_pstorerbnewt_rr },
15920 { S4_pstorerbtnew_abs, S4_pstorerbnewtnew_abs },
15921 { S4_pstorerbtnew_io, S4_pstorerbnewtnew_io },
15922 { S4_pstorerbtnew_rr, S4_pstorerbnewtnew_rr },
15923 { S4_pstorerhf_abs, S4_pstorerhnewf_abs },
15924 { S4_pstorerhf_rr, S4_pstorerhnewf_rr },
15925 { S4_pstorerhfnew_abs, S4_pstorerhnewfnew_abs },
15926 { S4_pstorerhfnew_io, S4_pstorerhnewfnew_io },
15927 { S4_pstorerhfnew_rr, S4_pstorerhnewfnew_rr },
15928 { S4_pstorerht_abs, S4_pstorerhnewt_abs },
15929 { S4_pstorerht_rr, S4_pstorerhnewt_rr },
15930 { S4_pstorerhtnew_abs, S4_pstorerhnewtnew_abs },
15931 { S4_pstorerhtnew_io, S4_pstorerhnewtnew_io },
15932 { S4_pstorerhtnew_rr, S4_pstorerhnewtnew_rr },
15933 { S4_pstorerif_abs, S4_pstorerinewf_abs },
15934 { S4_pstorerif_rr, S4_pstorerinewf_rr },
15935 { S4_pstorerifnew_abs, S4_pstorerinewfnew_abs },
15936 { S4_pstorerifnew_io, S4_pstorerinewfnew_io },
15937 { S4_pstorerifnew_rr, S4_pstorerinewfnew_rr },
15938 { S4_pstorerit_abs, S4_pstorerinewt_abs },
15939 { S4_pstorerit_rr, S4_pstorerinewt_rr },
15940 { S4_pstoreritnew_abs, S4_pstorerinewtnew_abs },
15941 { S4_pstoreritnew_io, S4_pstorerinewtnew_io },
15942 { S4_pstoreritnew_rr, S4_pstorerinewtnew_rr },
15943 { S4_storerb_ap, S4_storerbnew_ap },
15944 { S4_storerb_rr, S4_storerbnew_rr },
15945 { S4_storerb_ur, S4_storerbnew_ur },
15946 { S4_storerh_ap, S4_storerhnew_ap },
15947 { S4_storerh_rr, S4_storerhnew_rr },
15948 { S4_storerh_ur, S4_storerhnew_ur },
15949 { S4_storeri_ap, S4_storerinew_ap },
15950 { S4_storeri_rr, S4_storerinew_rr },
15951 { S4_storeri_ur, S4_storerinew_ur },
15952 { V6_vS32b_ai, V6_vS32b_new_ai },
15953 { V6_vS32b_npred_ai, V6_vS32b_new_npred_ai },
15954 { V6_vS32b_npred_pi, V6_vS32b_new_npred_pi },
15955 { V6_vS32b_npred_ppu, V6_vS32b_new_npred_ppu },
15956 { V6_vS32b_nt_ai, V6_vS32b_nt_new_ai },
15957 { V6_vS32b_nt_npred_ai, V6_vS32b_nt_new_npred_ai },
15958 { V6_vS32b_nt_npred_pi, V6_vS32b_nt_new_npred_pi },
15959 { V6_vS32b_nt_npred_ppu, V6_vS32b_nt_new_npred_ppu },
15960 { V6_vS32b_nt_pi, V6_vS32b_nt_new_pi },
15961 { V6_vS32b_nt_ppu, V6_vS32b_nt_new_ppu },
15962 { V6_vS32b_nt_pred_ai, V6_vS32b_nt_new_pred_ai },
15963 { V6_vS32b_nt_pred_pi, V6_vS32b_nt_new_pred_pi },
15964 { V6_vS32b_nt_pred_ppu, V6_vS32b_nt_new_pred_ppu },
15965 { V6_vS32b_pi, V6_vS32b_new_pi },
15966 { V6_vS32b_ppu, V6_vS32b_new_ppu },
15967 { V6_vS32b_pred_ai, V6_vS32b_new_pred_ai },
15968 { V6_vS32b_pred_pi, V6_vS32b_new_pred_pi },
15969 { V6_vS32b_pred_ppu, V6_vS32b_new_pred_ppu },
15970 }; // End of Table
15971
15972 unsigned mid;
15973 unsigned start = 0;
15974 unsigned end = 99;
15975 while (start < end) {
15976 mid = start + (end - start) / 2;
15977 if (Opcode == Table[mid][0])
15978 break;
15979 if (Opcode < Table[mid][0])
15980 end = mid;
15981 else
15982 start = mid + 1;
15983 }
15984 if (start == end)
15985 return -1; // Instruction doesn't exist in this table.
15986
15987 return Table[mid][1];
15988}
15989
15990// getNonNVStore
15991LLVM_READONLY
15992int getNonNVStore(uint16_t Opcode) {
15993 using namespace Hexagon;
15994 static constexpr uint16_t Table[][2] = {
15995 { PS_storerbnewabs, PS_storerbabs },
15996 { PS_storerhnewabs, PS_storerhabs },
15997 { PS_storerinewabs, PS_storeriabs },
15998 { S2_pstorerbnewf_io, S2_pstorerbf_io },
15999 { S2_pstorerbnewf_pi, S2_pstorerbf_pi },
16000 { S2_pstorerbnewfnew_pi, S2_pstorerbfnew_pi },
16001 { S2_pstorerbnewt_io, S2_pstorerbt_io },
16002 { S2_pstorerbnewt_pi, S2_pstorerbt_pi },
16003 { S2_pstorerbnewtnew_pi, S2_pstorerbtnew_pi },
16004 { S2_pstorerhnewf_io, S2_pstorerhf_io },
16005 { S2_pstorerhnewf_pi, S2_pstorerhf_pi },
16006 { S2_pstorerhnewfnew_pi, S2_pstorerhfnew_pi },
16007 { S2_pstorerhnewt_io, S2_pstorerht_io },
16008 { S2_pstorerhnewt_pi, S2_pstorerht_pi },
16009 { S2_pstorerhnewtnew_pi, S2_pstorerhtnew_pi },
16010 { S2_pstorerinewf_io, S2_pstorerif_io },
16011 { S2_pstorerinewf_pi, S2_pstorerif_pi },
16012 { S2_pstorerinewfnew_pi, S2_pstorerifnew_pi },
16013 { S2_pstorerinewt_io, S2_pstorerit_io },
16014 { S2_pstorerinewt_pi, S2_pstorerit_pi },
16015 { S2_pstorerinewtnew_pi, S2_pstoreritnew_pi },
16016 { S2_storerbnew_io, S2_storerb_io },
16017 { S2_storerbnew_pbr, S2_storerb_pbr },
16018 { S2_storerbnew_pci, S2_storerb_pci },
16019 { S2_storerbnew_pcr, S2_storerb_pcr },
16020 { S2_storerbnew_pi, S2_storerb_pi },
16021 { S2_storerbnew_pr, S2_storerb_pr },
16022 { S2_storerbnewgp, S2_storerbgp },
16023 { S2_storerhnew_io, S2_storerh_io },
16024 { S2_storerhnew_pbr, S2_storerh_pbr },
16025 { S2_storerhnew_pci, S2_storerh_pci },
16026 { S2_storerhnew_pcr, S2_storerh_pcr },
16027 { S2_storerhnew_pi, S2_storerh_pi },
16028 { S2_storerhnew_pr, S2_storerh_pr },
16029 { S2_storerhnewgp, S2_storerhgp },
16030 { S2_storerinew_io, S2_storeri_io },
16031 { S2_storerinew_pbr, S2_storeri_pbr },
16032 { S2_storerinew_pci, S2_storeri_pci },
16033 { S2_storerinew_pcr, S2_storeri_pcr },
16034 { S2_storerinew_pi, S2_storeri_pi },
16035 { S2_storerinew_pr, S2_storeri_pr },
16036 { S2_storerinewgp, S2_storerigp },
16037 { S4_pstorerbnewf_abs, S4_pstorerbf_abs },
16038 { S4_pstorerbnewf_rr, S4_pstorerbf_rr },
16039 { S4_pstorerbnewfnew_abs, S4_pstorerbfnew_abs },
16040 { S4_pstorerbnewfnew_io, S4_pstorerbfnew_io },
16041 { S4_pstorerbnewfnew_rr, S4_pstorerbfnew_rr },
16042 { S4_pstorerbnewt_abs, S4_pstorerbt_abs },
16043 { S4_pstorerbnewt_rr, S4_pstorerbt_rr },
16044 { S4_pstorerbnewtnew_abs, S4_pstorerbtnew_abs },
16045 { S4_pstorerbnewtnew_io, S4_pstorerbtnew_io },
16046 { S4_pstorerbnewtnew_rr, S4_pstorerbtnew_rr },
16047 { S4_pstorerhnewf_abs, S4_pstorerhf_abs },
16048 { S4_pstorerhnewf_rr, S4_pstorerhf_rr },
16049 { S4_pstorerhnewfnew_abs, S4_pstorerhfnew_abs },
16050 { S4_pstorerhnewfnew_io, S4_pstorerhfnew_io },
16051 { S4_pstorerhnewfnew_rr, S4_pstorerhfnew_rr },
16052 { S4_pstorerhnewt_abs, S4_pstorerht_abs },
16053 { S4_pstorerhnewt_rr, S4_pstorerht_rr },
16054 { S4_pstorerhnewtnew_abs, S4_pstorerhtnew_abs },
16055 { S4_pstorerhnewtnew_io, S4_pstorerhtnew_io },
16056 { S4_pstorerhnewtnew_rr, S4_pstorerhtnew_rr },
16057 { S4_pstorerinewf_abs, S4_pstorerif_abs },
16058 { S4_pstorerinewf_rr, S4_pstorerif_rr },
16059 { S4_pstorerinewfnew_abs, S4_pstorerifnew_abs },
16060 { S4_pstorerinewfnew_io, S4_pstorerifnew_io },
16061 { S4_pstorerinewfnew_rr, S4_pstorerifnew_rr },
16062 { S4_pstorerinewt_abs, S4_pstorerit_abs },
16063 { S4_pstorerinewt_rr, S4_pstorerit_rr },
16064 { S4_pstorerinewtnew_abs, S4_pstoreritnew_abs },
16065 { S4_pstorerinewtnew_io, S4_pstoreritnew_io },
16066 { S4_pstorerinewtnew_rr, S4_pstoreritnew_rr },
16067 { S4_storerbnew_ap, S4_storerb_ap },
16068 { S4_storerbnew_rr, S4_storerb_rr },
16069 { S4_storerbnew_ur, S4_storerb_ur },
16070 { S4_storerhnew_ap, S4_storerh_ap },
16071 { S4_storerhnew_rr, S4_storerh_rr },
16072 { S4_storerhnew_ur, S4_storerh_ur },
16073 { S4_storerinew_ap, S4_storeri_ap },
16074 { S4_storerinew_rr, S4_storeri_rr },
16075 { S4_storerinew_ur, S4_storeri_ur },
16076 { V6_vS32b_new_ai, V6_vS32b_ai },
16077 { V6_vS32b_new_npred_ai, V6_vS32b_npred_ai },
16078 { V6_vS32b_new_npred_pi, V6_vS32b_npred_pi },
16079 { V6_vS32b_new_npred_ppu, V6_vS32b_npred_ppu },
16080 { V6_vS32b_new_pi, V6_vS32b_pi },
16081 { V6_vS32b_new_ppu, V6_vS32b_ppu },
16082 { V6_vS32b_new_pred_ai, V6_vS32b_pred_ai },
16083 { V6_vS32b_new_pred_pi, V6_vS32b_pred_pi },
16084 { V6_vS32b_new_pred_ppu, V6_vS32b_pred_ppu },
16085 { V6_vS32b_nt_new_ai, V6_vS32b_nt_ai },
16086 { V6_vS32b_nt_new_npred_ai, V6_vS32b_nt_npred_ai },
16087 { V6_vS32b_nt_new_npred_pi, V6_vS32b_nt_npred_pi },
16088 { V6_vS32b_nt_new_npred_ppu, V6_vS32b_nt_npred_ppu },
16089 { V6_vS32b_nt_new_pi, V6_vS32b_nt_pi },
16090 { V6_vS32b_nt_new_ppu, V6_vS32b_nt_ppu },
16091 { V6_vS32b_nt_new_pred_ai, V6_vS32b_nt_pred_ai },
16092 { V6_vS32b_nt_new_pred_pi, V6_vS32b_nt_pred_pi },
16093 { V6_vS32b_nt_new_pred_ppu, V6_vS32b_nt_pred_ppu },
16094 }; // End of Table
16095
16096 unsigned mid;
16097 unsigned start = 0;
16098 unsigned end = 99;
16099 while (start < end) {
16100 mid = start + (end - start) / 2;
16101 if (Opcode == Table[mid][0])
16102 break;
16103 if (Opcode < Table[mid][0])
16104 end = mid;
16105 else
16106 start = mid + 1;
16107 }
16108 if (start == end)
16109 return -1; // Instruction doesn't exist in this table.
16110
16111 return Table[mid][1];
16112}
16113
16114// getPredNewOpcode
16115LLVM_READONLY
16116int getPredNewOpcode(uint16_t Opcode) {
16117 using namespace Hexagon;
16118 static constexpr uint16_t Table[][2] = {
16119 { A2_tfrf, A2_tfrfnew },
16120 { A2_tfrpf, A2_tfrpfnew },
16121 { A2_tfrpt, A2_tfrptnew },
16122 { A2_tfrt, A2_tfrtnew },
16123 { A2_paddf, A2_paddfnew },
16124 { A2_paddif, A2_paddifnew },
16125 { A2_paddit, A2_padditnew },
16126 { A2_paddt, A2_paddtnew },
16127 { A2_pandf, A2_pandfnew },
16128 { A2_pandt, A2_pandtnew },
16129 { A2_porf, A2_porfnew },
16130 { A2_port, A2_portnew },
16131 { A2_psubf, A2_psubfnew },
16132 { A2_psubt, A2_psubtnew },
16133 { A2_pxorf, A2_pxorfnew },
16134 { A2_pxort, A2_pxortnew },
16135 { A4_paslhf, A4_paslhfnew },
16136 { A4_paslht, A4_paslhtnew },
16137 { A4_pasrhf, A4_pasrhfnew },
16138 { A4_pasrht, A4_pasrhtnew },
16139 { A4_psxtbf, A4_psxtbfnew },
16140 { A4_psxtbt, A4_psxtbtnew },
16141 { A4_psxthf, A4_psxthfnew },
16142 { A4_psxtht, A4_psxthtnew },
16143 { A4_pzxtbf, A4_pzxtbfnew },
16144 { A4_pzxtbt, A4_pzxtbtnew },
16145 { A4_pzxthf, A4_pzxthfnew },
16146 { A4_pzxtht, A4_pzxthtnew },
16147 { C2_ccombinewf, C2_ccombinewnewf },
16148 { C2_ccombinewt, C2_ccombinewnewt },
16149 { C2_cmoveif, C2_cmovenewif },
16150 { C2_cmoveit, C2_cmovenewit },
16151 { J2_jumpf, J2_jumpfnew },
16152 { J2_jumpfpt, J2_jumpfnewpt },
16153 { J2_jumprf, J2_jumprfnew },
16154 { J2_jumprfpt, J2_jumprfnewpt },
16155 { J2_jumprt, J2_jumprtnew },
16156 { J2_jumprtpt, J2_jumprtnewpt },
16157 { J2_jumpt, J2_jumptnew },
16158 { J2_jumptpt, J2_jumptnewpt },
16159 { L2_ploadrbf_io, L2_ploadrbfnew_io },
16160 { L2_ploadrbf_pi, L2_ploadrbfnew_pi },
16161 { L2_ploadrbt_io, L2_ploadrbtnew_io },
16162 { L2_ploadrbt_pi, L2_ploadrbtnew_pi },
16163 { L2_ploadrdf_io, L2_ploadrdfnew_io },
16164 { L2_ploadrdf_pi, L2_ploadrdfnew_pi },
16165 { L2_ploadrdt_io, L2_ploadrdtnew_io },
16166 { L2_ploadrdt_pi, L2_ploadrdtnew_pi },
16167 { L2_ploadrhf_io, L2_ploadrhfnew_io },
16168 { L2_ploadrhf_pi, L2_ploadrhfnew_pi },
16169 { L2_ploadrht_io, L2_ploadrhtnew_io },
16170 { L2_ploadrht_pi, L2_ploadrhtnew_pi },
16171 { L2_ploadrif_io, L2_ploadrifnew_io },
16172 { L2_ploadrif_pi, L2_ploadrifnew_pi },
16173 { L2_ploadrit_io, L2_ploadritnew_io },
16174 { L2_ploadrit_pi, L2_ploadritnew_pi },
16175 { L2_ploadrubf_io, L2_ploadrubfnew_io },
16176 { L2_ploadrubf_pi, L2_ploadrubfnew_pi },
16177 { L2_ploadrubt_io, L2_ploadrubtnew_io },
16178 { L2_ploadrubt_pi, L2_ploadrubtnew_pi },
16179 { L2_ploadruhf_io, L2_ploadruhfnew_io },
16180 { L2_ploadruhf_pi, L2_ploadruhfnew_pi },
16181 { L2_ploadruht_io, L2_ploadruhtnew_io },
16182 { L2_ploadruht_pi, L2_ploadruhtnew_pi },
16183 { L4_ploadrbf_abs, L4_ploadrbfnew_abs },
16184 { L4_ploadrbf_rr, L4_ploadrbfnew_rr },
16185 { L4_ploadrbt_abs, L4_ploadrbtnew_abs },
16186 { L4_ploadrbt_rr, L4_ploadrbtnew_rr },
16187 { L4_ploadrdf_abs, L4_ploadrdfnew_abs },
16188 { L4_ploadrdf_rr, L4_ploadrdfnew_rr },
16189 { L4_ploadrdt_abs, L4_ploadrdtnew_abs },
16190 { L4_ploadrdt_rr, L4_ploadrdtnew_rr },
16191 { L4_ploadrhf_abs, L4_ploadrhfnew_abs },
16192 { L4_ploadrhf_rr, L4_ploadrhfnew_rr },
16193 { L4_ploadrht_abs, L4_ploadrhtnew_abs },
16194 { L4_ploadrht_rr, L4_ploadrhtnew_rr },
16195 { L4_ploadrif_abs, L4_ploadrifnew_abs },
16196 { L4_ploadrif_rr, L4_ploadrifnew_rr },
16197 { L4_ploadrit_abs, L4_ploadritnew_abs },
16198 { L4_ploadrit_rr, L4_ploadritnew_rr },
16199 { L4_ploadrubf_abs, L4_ploadrubfnew_abs },
16200 { L4_ploadrubf_rr, L4_ploadrubfnew_rr },
16201 { L4_ploadrubt_abs, L4_ploadrubtnew_abs },
16202 { L4_ploadrubt_rr, L4_ploadrubtnew_rr },
16203 { L4_ploadruhf_abs, L4_ploadruhfnew_abs },
16204 { L4_ploadruhf_rr, L4_ploadruhfnew_rr },
16205 { L4_ploadruht_abs, L4_ploadruhtnew_abs },
16206 { L4_ploadruht_rr, L4_ploadruhtnew_rr },
16207 { L4_return_f, L4_return_fnew_pt },
16208 { L4_return_t, L4_return_tnew_pt },
16209 { PS_jmpretf, PS_jmpretfnew },
16210 { PS_jmprett, PS_jmprettnew },
16211 { S2_pstorerbf_io, S4_pstorerbfnew_io },
16212 { S2_pstorerbf_pi, S2_pstorerbfnew_pi },
16213 { S2_pstorerbnewf_io, S4_pstorerbnewfnew_io },
16214 { S2_pstorerbnewf_pi, S2_pstorerbnewfnew_pi },
16215 { S2_pstorerbnewt_io, S4_pstorerbnewtnew_io },
16216 { S2_pstorerbnewt_pi, S2_pstorerbnewtnew_pi },
16217 { S2_pstorerbt_io, S4_pstorerbtnew_io },
16218 { S2_pstorerbt_pi, S2_pstorerbtnew_pi },
16219 { S2_pstorerdf_io, S4_pstorerdfnew_io },
16220 { S2_pstorerdf_pi, S2_pstorerdfnew_pi },
16221 { S2_pstorerdt_io, S4_pstorerdtnew_io },
16222 { S2_pstorerdt_pi, S2_pstorerdtnew_pi },
16223 { S2_pstorerff_io, S4_pstorerffnew_io },
16224 { S2_pstorerff_pi, S2_pstorerffnew_pi },
16225 { S2_pstorerft_io, S4_pstorerftnew_io },
16226 { S2_pstorerft_pi, S2_pstorerftnew_pi },
16227 { S2_pstorerhf_io, S4_pstorerhfnew_io },
16228 { S2_pstorerhf_pi, S2_pstorerhfnew_pi },
16229 { S2_pstorerhnewf_io, S4_pstorerhnewfnew_io },
16230 { S2_pstorerhnewf_pi, S2_pstorerhnewfnew_pi },
16231 { S2_pstorerhnewt_io, S4_pstorerhnewtnew_io },
16232 { S2_pstorerhnewt_pi, S2_pstorerhnewtnew_pi },
16233 { S2_pstorerht_io, S4_pstorerhtnew_io },
16234 { S2_pstorerht_pi, S2_pstorerhtnew_pi },
16235 { S2_pstorerif_io, S4_pstorerifnew_io },
16236 { S2_pstorerif_pi, S2_pstorerifnew_pi },
16237 { S2_pstorerinewf_io, S4_pstorerinewfnew_io },
16238 { S2_pstorerinewf_pi, S2_pstorerinewfnew_pi },
16239 { S2_pstorerinewt_io, S4_pstorerinewtnew_io },
16240 { S2_pstorerinewt_pi, S2_pstorerinewtnew_pi },
16241 { S2_pstorerit_io, S4_pstoreritnew_io },
16242 { S2_pstorerit_pi, S2_pstoreritnew_pi },
16243 { S4_pstorerbf_abs, S4_pstorerbfnew_abs },
16244 { S4_pstorerbf_rr, S4_pstorerbfnew_rr },
16245 { S4_pstorerbnewf_abs, S4_pstorerbnewfnew_abs },
16246 { S4_pstorerbnewf_rr, S4_pstorerbnewfnew_rr },
16247 { S4_pstorerbnewt_abs, S4_pstorerbnewtnew_abs },
16248 { S4_pstorerbnewt_rr, S4_pstorerbnewtnew_rr },
16249 { S4_pstorerbt_abs, S4_pstorerbtnew_abs },
16250 { S4_pstorerbt_rr, S4_pstorerbtnew_rr },
16251 { S4_pstorerdf_abs, S4_pstorerdfnew_abs },
16252 { S4_pstorerdf_rr, S4_pstorerdfnew_rr },
16253 { S4_pstorerdt_abs, S4_pstorerdtnew_abs },
16254 { S4_pstorerdt_rr, S4_pstorerdtnew_rr },
16255 { S4_pstorerff_abs, S4_pstorerffnew_abs },
16256 { S4_pstorerff_rr, S4_pstorerffnew_rr },
16257 { S4_pstorerft_abs, S4_pstorerftnew_abs },
16258 { S4_pstorerft_rr, S4_pstorerftnew_rr },
16259 { S4_pstorerhf_abs, S4_pstorerhfnew_abs },
16260 { S4_pstorerhf_rr, S4_pstorerhfnew_rr },
16261 { S4_pstorerhnewf_abs, S4_pstorerhnewfnew_abs },
16262 { S4_pstorerhnewf_rr, S4_pstorerhnewfnew_rr },
16263 { S4_pstorerhnewt_abs, S4_pstorerhnewtnew_abs },
16264 { S4_pstorerhnewt_rr, S4_pstorerhnewtnew_rr },
16265 { S4_pstorerht_abs, S4_pstorerhtnew_abs },
16266 { S4_pstorerht_rr, S4_pstorerhtnew_rr },
16267 { S4_pstorerif_abs, S4_pstorerifnew_abs },
16268 { S4_pstorerif_rr, S4_pstorerifnew_rr },
16269 { S4_pstorerinewf_abs, S4_pstorerinewfnew_abs },
16270 { S4_pstorerinewf_rr, S4_pstorerinewfnew_rr },
16271 { S4_pstorerinewt_abs, S4_pstorerinewtnew_abs },
16272 { S4_pstorerinewt_rr, S4_pstorerinewtnew_rr },
16273 { S4_pstorerit_abs, S4_pstoreritnew_abs },
16274 { S4_pstorerit_rr, S4_pstoreritnew_rr },
16275 { S4_storeirbf_io, S4_storeirbfnew_io },
16276 { S4_storeirbt_io, S4_storeirbtnew_io },
16277 { S4_storeirhf_io, S4_storeirhfnew_io },
16278 { S4_storeirht_io, S4_storeirhtnew_io },
16279 { S4_storeirif_io, S4_storeirifnew_io },
16280 { S4_storeirit_io, S4_storeiritnew_io },
16281 }; // End of Table
16282
16283 unsigned mid;
16284 unsigned start = 0;
16285 unsigned end = 162;
16286 while (start < end) {
16287 mid = start + (end - start) / 2;
16288 if (Opcode == Table[mid][0])
16289 break;
16290 if (Opcode < Table[mid][0])
16291 end = mid;
16292 else
16293 start = mid + 1;
16294 }
16295 if (start == end)
16296 return -1; // Instruction doesn't exist in this table.
16297
16298 return Table[mid][1];
16299}
16300
16301// getPredOldOpcode
16302LLVM_READONLY
16303int getPredOldOpcode(uint16_t Opcode) {
16304 using namespace Hexagon;
16305 static constexpr uint16_t Table[][2] = {
16306 { A2_tfrfnew, A2_tfrf },
16307 { A2_tfrpfnew, A2_tfrpf },
16308 { A2_tfrptnew, A2_tfrpt },
16309 { A2_tfrtnew, A2_tfrt },
16310 { A2_paddfnew, A2_paddf },
16311 { A2_paddifnew, A2_paddif },
16312 { A2_padditnew, A2_paddit },
16313 { A2_paddtnew, A2_paddt },
16314 { A2_pandfnew, A2_pandf },
16315 { A2_pandtnew, A2_pandt },
16316 { A2_porfnew, A2_porf },
16317 { A2_portnew, A2_port },
16318 { A2_psubfnew, A2_psubf },
16319 { A2_psubtnew, A2_psubt },
16320 { A2_pxorfnew, A2_pxorf },
16321 { A2_pxortnew, A2_pxort },
16322 { A4_paslhfnew, A4_paslhf },
16323 { A4_paslhtnew, A4_paslht },
16324 { A4_pasrhfnew, A4_pasrhf },
16325 { A4_pasrhtnew, A4_pasrht },
16326 { A4_psxtbfnew, A4_psxtbf },
16327 { A4_psxtbtnew, A4_psxtbt },
16328 { A4_psxthfnew, A4_psxthf },
16329 { A4_psxthtnew, A4_psxtht },
16330 { A4_pzxtbfnew, A4_pzxtbf },
16331 { A4_pzxtbtnew, A4_pzxtbt },
16332 { A4_pzxthfnew, A4_pzxthf },
16333 { A4_pzxthtnew, A4_pzxtht },
16334 { C2_ccombinewnewf, C2_ccombinewf },
16335 { C2_ccombinewnewt, C2_ccombinewt },
16336 { C2_cmovenewif, C2_cmoveif },
16337 { C2_cmovenewit, C2_cmoveit },
16338 { J2_jumpfnew, J2_jumpf },
16339 { J2_jumpfnewpt, J2_jumpfpt },
16340 { J2_jumprfnew, J2_jumprf },
16341 { J2_jumprfnewpt, J2_jumprfpt },
16342 { J2_jumprtnew, J2_jumprt },
16343 { J2_jumprtnewpt, J2_jumprtpt },
16344 { J2_jumptnew, J2_jumpt },
16345 { J2_jumptnewpt, J2_jumptpt },
16346 { L2_ploadrbfnew_io, L2_ploadrbf_io },
16347 { L2_ploadrbfnew_pi, L2_ploadrbf_pi },
16348 { L2_ploadrbtnew_io, L2_ploadrbt_io },
16349 { L2_ploadrbtnew_pi, L2_ploadrbt_pi },
16350 { L2_ploadrdfnew_io, L2_ploadrdf_io },
16351 { L2_ploadrdfnew_pi, L2_ploadrdf_pi },
16352 { L2_ploadrdtnew_io, L2_ploadrdt_io },
16353 { L2_ploadrdtnew_pi, L2_ploadrdt_pi },
16354 { L2_ploadrhfnew_io, L2_ploadrhf_io },
16355 { L2_ploadrhfnew_pi, L2_ploadrhf_pi },
16356 { L2_ploadrhtnew_io, L2_ploadrht_io },
16357 { L2_ploadrhtnew_pi, L2_ploadrht_pi },
16358 { L2_ploadrifnew_io, L2_ploadrif_io },
16359 { L2_ploadrifnew_pi, L2_ploadrif_pi },
16360 { L2_ploadritnew_io, L2_ploadrit_io },
16361 { L2_ploadritnew_pi, L2_ploadrit_pi },
16362 { L2_ploadrubfnew_io, L2_ploadrubf_io },
16363 { L2_ploadrubfnew_pi, L2_ploadrubf_pi },
16364 { L2_ploadrubtnew_io, L2_ploadrubt_io },
16365 { L2_ploadrubtnew_pi, L2_ploadrubt_pi },
16366 { L2_ploadruhfnew_io, L2_ploadruhf_io },
16367 { L2_ploadruhfnew_pi, L2_ploadruhf_pi },
16368 { L2_ploadruhtnew_io, L2_ploadruht_io },
16369 { L2_ploadruhtnew_pi, L2_ploadruht_pi },
16370 { L4_ploadrbfnew_abs, L4_ploadrbf_abs },
16371 { L4_ploadrbfnew_rr, L4_ploadrbf_rr },
16372 { L4_ploadrbtnew_abs, L4_ploadrbt_abs },
16373 { L4_ploadrbtnew_rr, L4_ploadrbt_rr },
16374 { L4_ploadrdfnew_abs, L4_ploadrdf_abs },
16375 { L4_ploadrdfnew_rr, L4_ploadrdf_rr },
16376 { L4_ploadrdtnew_abs, L4_ploadrdt_abs },
16377 { L4_ploadrdtnew_rr, L4_ploadrdt_rr },
16378 { L4_ploadrhfnew_abs, L4_ploadrhf_abs },
16379 { L4_ploadrhfnew_rr, L4_ploadrhf_rr },
16380 { L4_ploadrhtnew_abs, L4_ploadrht_abs },
16381 { L4_ploadrhtnew_rr, L4_ploadrht_rr },
16382 { L4_ploadrifnew_abs, L4_ploadrif_abs },
16383 { L4_ploadrifnew_rr, L4_ploadrif_rr },
16384 { L4_ploadritnew_abs, L4_ploadrit_abs },
16385 { L4_ploadritnew_rr, L4_ploadrit_rr },
16386 { L4_ploadrubfnew_abs, L4_ploadrubf_abs },
16387 { L4_ploadrubfnew_rr, L4_ploadrubf_rr },
16388 { L4_ploadrubtnew_abs, L4_ploadrubt_abs },
16389 { L4_ploadrubtnew_rr, L4_ploadrubt_rr },
16390 { L4_ploadruhfnew_abs, L4_ploadruhf_abs },
16391 { L4_ploadruhfnew_rr, L4_ploadruhf_rr },
16392 { L4_ploadruhtnew_abs, L4_ploadruht_abs },
16393 { L4_ploadruhtnew_rr, L4_ploadruht_rr },
16394 { L4_return_fnew_pt, L4_return_f },
16395 { L4_return_tnew_pt, L4_return_t },
16396 { PS_jmpretfnew, PS_jmpretf },
16397 { PS_jmprettnew, PS_jmprett },
16398 { S2_pstorerbfnew_pi, S2_pstorerbf_pi },
16399 { S2_pstorerbnewfnew_pi, S2_pstorerbnewf_pi },
16400 { S2_pstorerbnewtnew_pi, S2_pstorerbnewt_pi },
16401 { S2_pstorerbtnew_pi, S2_pstorerbt_pi },
16402 { S2_pstorerdfnew_pi, S2_pstorerdf_pi },
16403 { S2_pstorerdtnew_pi, S2_pstorerdt_pi },
16404 { S2_pstorerffnew_pi, S2_pstorerff_pi },
16405 { S2_pstorerftnew_pi, S2_pstorerft_pi },
16406 { S2_pstorerhfnew_pi, S2_pstorerhf_pi },
16407 { S2_pstorerhnewfnew_pi, S2_pstorerhnewf_pi },
16408 { S2_pstorerhnewtnew_pi, S2_pstorerhnewt_pi },
16409 { S2_pstorerhtnew_pi, S2_pstorerht_pi },
16410 { S2_pstorerifnew_pi, S2_pstorerif_pi },
16411 { S2_pstorerinewfnew_pi, S2_pstorerinewf_pi },
16412 { S2_pstorerinewtnew_pi, S2_pstorerinewt_pi },
16413 { S2_pstoreritnew_pi, S2_pstorerit_pi },
16414 { S4_pstorerbfnew_abs, S4_pstorerbf_abs },
16415 { S4_pstorerbfnew_io, S2_pstorerbf_io },
16416 { S4_pstorerbfnew_rr, S4_pstorerbf_rr },
16417 { S4_pstorerbnewfnew_abs, S4_pstorerbnewf_abs },
16418 { S4_pstorerbnewfnew_io, S2_pstorerbnewf_io },
16419 { S4_pstorerbnewfnew_rr, S4_pstorerbnewf_rr },
16420 { S4_pstorerbnewtnew_abs, S4_pstorerbnewt_abs },
16421 { S4_pstorerbnewtnew_io, S2_pstorerbnewt_io },
16422 { S4_pstorerbnewtnew_rr, S4_pstorerbnewt_rr },
16423 { S4_pstorerbtnew_abs, S4_pstorerbt_abs },
16424 { S4_pstorerbtnew_io, S2_pstorerbt_io },
16425 { S4_pstorerbtnew_rr, S4_pstorerbt_rr },
16426 { S4_pstorerdfnew_abs, S4_pstorerdf_abs },
16427 { S4_pstorerdfnew_io, S2_pstorerdf_io },
16428 { S4_pstorerdfnew_rr, S4_pstorerdf_rr },
16429 { S4_pstorerdtnew_abs, S4_pstorerdt_abs },
16430 { S4_pstorerdtnew_io, S2_pstorerdt_io },
16431 { S4_pstorerdtnew_rr, S4_pstorerdt_rr },
16432 { S4_pstorerffnew_abs, S4_pstorerff_abs },
16433 { S4_pstorerffnew_io, S2_pstorerff_io },
16434 { S4_pstorerffnew_rr, S4_pstorerff_rr },
16435 { S4_pstorerftnew_abs, S4_pstorerft_abs },
16436 { S4_pstorerftnew_io, S2_pstorerft_io },
16437 { S4_pstorerftnew_rr, S4_pstorerft_rr },
16438 { S4_pstorerhfnew_abs, S4_pstorerhf_abs },
16439 { S4_pstorerhfnew_io, S2_pstorerhf_io },
16440 { S4_pstorerhfnew_rr, S4_pstorerhf_rr },
16441 { S4_pstorerhnewfnew_abs, S4_pstorerhnewf_abs },
16442 { S4_pstorerhnewfnew_io, S2_pstorerhnewf_io },
16443 { S4_pstorerhnewfnew_rr, S4_pstorerhnewf_rr },
16444 { S4_pstorerhnewtnew_abs, S4_pstorerhnewt_abs },
16445 { S4_pstorerhnewtnew_io, S2_pstorerhnewt_io },
16446 { S4_pstorerhnewtnew_rr, S4_pstorerhnewt_rr },
16447 { S4_pstorerhtnew_abs, S4_pstorerht_abs },
16448 { S4_pstorerhtnew_io, S2_pstorerht_io },
16449 { S4_pstorerhtnew_rr, S4_pstorerht_rr },
16450 { S4_pstorerifnew_abs, S4_pstorerif_abs },
16451 { S4_pstorerifnew_io, S2_pstorerif_io },
16452 { S4_pstorerifnew_rr, S4_pstorerif_rr },
16453 { S4_pstorerinewfnew_abs, S4_pstorerinewf_abs },
16454 { S4_pstorerinewfnew_io, S2_pstorerinewf_io },
16455 { S4_pstorerinewfnew_rr, S4_pstorerinewf_rr },
16456 { S4_pstorerinewtnew_abs, S4_pstorerinewt_abs },
16457 { S4_pstorerinewtnew_io, S2_pstorerinewt_io },
16458 { S4_pstorerinewtnew_rr, S4_pstorerinewt_rr },
16459 { S4_pstoreritnew_abs, S4_pstorerit_abs },
16460 { S4_pstoreritnew_io, S2_pstorerit_io },
16461 { S4_pstoreritnew_rr, S4_pstorerit_rr },
16462 { S4_storeirbfnew_io, S4_storeirbf_io },
16463 { S4_storeirbtnew_io, S4_storeirbt_io },
16464 { S4_storeirhfnew_io, S4_storeirhf_io },
16465 { S4_storeirhtnew_io, S4_storeirht_io },
16466 { S4_storeirifnew_io, S4_storeirif_io },
16467 { S4_storeiritnew_io, S4_storeirit_io },
16468 }; // End of Table
16469
16470 unsigned mid;
16471 unsigned start = 0;
16472 unsigned end = 162;
16473 while (start < end) {
16474 mid = start + (end - start) / 2;
16475 if (Opcode == Table[mid][0])
16476 break;
16477 if (Opcode < Table[mid][0])
16478 end = mid;
16479 else
16480 start = mid + 1;
16481 }
16482 if (start == end)
16483 return -1; // Instruction doesn't exist in this table.
16484
16485 return Table[mid][1];
16486}
16487
16488// getPredOpcode
16489LLVM_READONLY
16490int getPredOpcode(uint16_t Opcode, enum PredSense inPredSense) {
16491 using namespace Hexagon;
16492 static constexpr uint16_t Table[][3] = {
16493 { A2_tfrp, A2_tfrpt, A2_tfrpf },
16494 { A2_zxtb, A4_pzxtbt, A4_pzxtbf },
16495 { A2_add, A2_paddt, A2_paddf },
16496 { A2_addi, A2_paddit, A2_paddif },
16497 { A2_and, A2_pandt, A2_pandf },
16498 { A2_aslh, A4_paslht, A4_paslhf },
16499 { A2_asrh, A4_pasrht, A4_pasrhf },
16500 { A2_combinew, C2_ccombinewt, C2_ccombinewf },
16501 { A2_or, A2_port, A2_porf },
16502 { A2_sub, A2_psubt, A2_psubf },
16503 { A2_sxtb, A4_psxtbt, A4_psxtbf },
16504 { A2_sxth, A4_psxtht, A4_psxthf },
16505 { A2_tfr, A2_tfrt, A2_tfrf },
16506 { A2_tfrsi, C2_cmoveit, C2_cmoveif },
16507 { A2_xor, A2_pxort, A2_pxorf },
16508 { A2_zxth, A4_pzxtht, A4_pzxthf },
16509 { J2_call, J2_callt, J2_callf },
16510 { J2_jump, J2_jumpt, J2_jumpf },
16511 { J2_jumpr, J2_jumprt, J2_jumprf },
16512 { L2_loadrb_io, L2_ploadrbt_io, L2_ploadrbf_io },
16513 { L2_loadrb_pi, L2_ploadrbt_pi, L2_ploadrbf_pi },
16514 { L2_loadrbgp, L4_ploadrbt_abs, L4_ploadrbf_abs },
16515 { L2_loadrd_io, L2_ploadrdt_io, L2_ploadrdf_io },
16516 { L2_loadrd_pi, L2_ploadrdt_pi, L2_ploadrdf_pi },
16517 { L2_loadrdgp, L4_ploadrdt_abs, L4_ploadrdf_abs },
16518 { L2_loadrh_io, L2_ploadrht_io, L2_ploadrhf_io },
16519 { L2_loadrh_pi, L2_ploadrht_pi, L2_ploadrhf_pi },
16520 { L2_loadrhgp, L4_ploadrht_abs, L4_ploadrhf_abs },
16521 { L2_loadri_io, L2_ploadrit_io, L2_ploadrif_io },
16522 { L2_loadri_pi, L2_ploadrit_pi, L2_ploadrif_pi },
16523 { L2_loadrigp, L4_ploadrit_abs, L4_ploadrif_abs },
16524 { L2_loadrub_io, L2_ploadrubt_io, L2_ploadrubf_io },
16525 { L2_loadrub_pi, L2_ploadrubt_pi, L2_ploadrubf_pi },
16526 { L2_loadrubgp, L4_ploadrubt_abs, L4_ploadrubf_abs },
16527 { L2_loadruh_io, L2_ploadruht_io, L2_ploadruhf_io },
16528 { L2_loadruh_pi, L2_ploadruht_pi, L2_ploadruhf_pi },
16529 { L2_loadruhgp, L4_ploadruht_abs, L4_ploadruhf_abs },
16530 { L4_loadrb_rr, L4_ploadrbt_rr, L4_ploadrbf_rr },
16531 { L4_loadrd_rr, L4_ploadrdt_rr, L4_ploadrdf_rr },
16532 { L4_loadrh_rr, L4_ploadrht_rr, L4_ploadrhf_rr },
16533 { L4_loadri_rr, L4_ploadrit_rr, L4_ploadrif_rr },
16534 { L4_loadrub_rr, L4_ploadrubt_rr, L4_ploadrubf_rr },
16535 { L4_loadruh_rr, L4_ploadruht_rr, L4_ploadruhf_rr },
16536 { L4_return, L4_return_t, L4_return_f },
16537 { PS_jmpret, PS_jmprett, PS_jmpretf },
16538 { PS_loadrbabs, L4_ploadrbt_abs, L4_ploadrbf_abs },
16539 { PS_loadrdabs, L4_ploadrdt_abs, L4_ploadrdf_abs },
16540 { PS_loadrhabs, L4_ploadrht_abs, L4_ploadrhf_abs },
16541 { PS_loadriabs, L4_ploadrit_abs, L4_ploadrif_abs },
16542 { PS_loadrubabs, L4_ploadrubt_abs, L4_ploadrubf_abs },
16543 { PS_loadruhabs, L4_ploadruht_abs, L4_ploadruhf_abs },
16544 { PS_storerbabs, S4_pstorerbt_abs, S4_pstorerbf_abs },
16545 { PS_storerbnewabs, S4_pstorerbnewt_abs, S4_pstorerbnewf_abs },
16546 { PS_storerdabs, S4_pstorerdt_abs, S4_pstorerdf_abs },
16547 { PS_storerfabs, S4_pstorerft_abs, S4_pstorerff_abs },
16548 { PS_storerhabs, S4_pstorerht_abs, S4_pstorerhf_abs },
16549 { PS_storerhnewabs, S4_pstorerhnewt_abs, S4_pstorerhnewf_abs },
16550 { PS_storeriabs, S4_pstorerit_abs, S4_pstorerif_abs },
16551 { PS_storerinewabs, S4_pstorerinewt_abs, S4_pstorerinewf_abs },
16552 { S2_storerb_io, S2_pstorerbt_io, S2_pstorerbf_io },
16553 { S2_storerb_pi, S2_pstorerbt_pi, S2_pstorerbf_pi },
16554 { S2_storerbgp, S4_pstorerbt_abs, S4_pstorerbf_abs },
16555 { S2_storerbnew_io, S2_pstorerbnewt_io, S2_pstorerbnewf_io },
16556 { S2_storerbnew_pi, S2_pstorerbnewt_pi, S2_pstorerbnewf_pi },
16557 { S2_storerbnewgp, S4_pstorerbnewt_abs, S4_pstorerbnewf_abs },
16558 { S2_storerd_io, S2_pstorerdt_io, S2_pstorerdf_io },
16559 { S2_storerd_pi, S2_pstorerdt_pi, S2_pstorerdf_pi },
16560 { S2_storerdgp, S4_pstorerdt_abs, S4_pstorerdf_abs },
16561 { S2_storerf_io, S2_pstorerft_io, S2_pstorerff_io },
16562 { S2_storerf_pi, S2_pstorerft_pi, S2_pstorerff_pi },
16563 { S2_storerfgp, S4_pstorerft_abs, S4_pstorerff_abs },
16564 { S2_storerh_io, S2_pstorerht_io, S2_pstorerhf_io },
16565 { S2_storerh_pi, S2_pstorerht_pi, S2_pstorerhf_pi },
16566 { S2_storerhgp, S4_pstorerht_abs, S4_pstorerhf_abs },
16567 { S2_storerhnew_io, S2_pstorerhnewt_io, S2_pstorerhnewf_io },
16568 { S2_storerhnew_pi, S2_pstorerhnewt_pi, S2_pstorerhnewf_pi },
16569 { S2_storerhnewgp, S4_pstorerhnewt_abs, S4_pstorerhnewf_abs },
16570 { S2_storeri_io, S2_pstorerit_io, S2_pstorerif_io },
16571 { S2_storeri_pi, S2_pstorerit_pi, S2_pstorerif_pi },
16572 { S2_storerigp, S4_pstorerit_abs, S4_pstorerif_abs },
16573 { S2_storerinew_io, S2_pstorerinewt_io, S2_pstorerinewf_io },
16574 { S2_storerinew_pi, S2_pstorerinewt_pi, S2_pstorerinewf_pi },
16575 { S2_storerinewgp, S4_pstorerinewt_abs, S4_pstorerinewf_abs },
16576 { S4_storeirb_io, S4_storeirbt_io, S4_storeirbf_io },
16577 { S4_storeirh_io, S4_storeirht_io, S4_storeirhf_io },
16578 { S4_storeiri_io, S4_storeirit_io, S4_storeirif_io },
16579 { S4_storerb_rr, S4_pstorerbt_rr, S4_pstorerbf_rr },
16580 { S4_storerbnew_rr, S4_pstorerbnewt_rr, S4_pstorerbnewf_rr },
16581 { S4_storerd_rr, S4_pstorerdt_rr, S4_pstorerdf_rr },
16582 { S4_storerf_rr, S4_pstorerft_rr, S4_pstorerff_rr },
16583 { S4_storerf_ur, S4_pstorerft_rr, S4_pstorerff_rr },
16584 { S4_storerh_rr, S4_pstorerht_rr, S4_pstorerhf_rr },
16585 { S4_storerhnew_rr, S4_pstorerhnewt_rr, S4_pstorerhnewf_rr },
16586 { S4_storeri_rr, S4_pstorerit_rr, S4_pstorerif_rr },
16587 { S4_storerinew_rr, S4_pstorerinewt_rr, S4_pstorerinewf_rr },
16588 { V6_vL32b_ai, V6_vL32b_pred_ai, V6_vL32b_npred_ai },
16589 { V6_vL32b_cur_ai, V6_vL32b_cur_pred_ai, V6_vL32b_cur_npred_ai },
16590 { V6_vL32b_cur_pi, V6_vL32b_cur_pred_pi, V6_vL32b_cur_npred_pi },
16591 { V6_vL32b_cur_ppu, V6_vL32b_cur_pred_ppu, V6_vL32b_cur_npred_ppu },
16592 { V6_vL32b_nt_ai, V6_vL32b_nt_pred_ai, V6_vL32b_nt_npred_ai },
16593 { V6_vL32b_nt_cur_ai, V6_vL32b_nt_cur_pred_ai, V6_vL32b_nt_cur_npred_ai },
16594 { V6_vL32b_nt_cur_pi, V6_vL32b_nt_cur_pred_pi, V6_vL32b_nt_cur_npred_pi },
16595 { V6_vL32b_nt_cur_ppu, V6_vL32b_nt_cur_pred_ppu, V6_vL32b_nt_cur_npred_ppu },
16596 { V6_vL32b_nt_pi, V6_vL32b_nt_pred_pi, V6_vL32b_nt_npred_pi },
16597 { V6_vL32b_nt_ppu, V6_vL32b_nt_pred_ppu, V6_vL32b_nt_npred_ppu },
16598 { V6_vL32b_nt_tmp_ai, V6_vL32b_nt_tmp_pred_ai, V6_vL32b_nt_tmp_npred_ai },
16599 { V6_vL32b_nt_tmp_pi, V6_vL32b_nt_tmp_pred_pi, V6_vL32b_nt_tmp_npred_pi },
16600 { V6_vL32b_nt_tmp_ppu, V6_vL32b_nt_tmp_pred_ppu, V6_vL32b_nt_tmp_npred_ppu },
16601 { V6_vL32b_pi, V6_vL32b_pred_pi, V6_vL32b_npred_pi },
16602 { V6_vL32b_ppu, V6_vL32b_pred_ppu, V6_vL32b_npred_ppu },
16603 { V6_vL32b_tmp_ai, V6_vL32b_tmp_pred_ai, V6_vL32b_tmp_npred_ai },
16604 { V6_vL32b_tmp_pi, V6_vL32b_tmp_pred_pi, V6_vL32b_tmp_npred_pi },
16605 { V6_vL32b_tmp_ppu, V6_vL32b_tmp_pred_ppu, V6_vL32b_tmp_npred_ppu },
16606 { V6_vS32Ub_ai, V6_vS32Ub_pred_ai, V6_vS32Ub_npred_ai },
16607 { V6_vS32Ub_pi, V6_vS32Ub_pred_pi, V6_vS32Ub_npred_pi },
16608 { V6_vS32Ub_ppu, V6_vS32Ub_pred_ppu, V6_vS32Ub_npred_ppu },
16609 { V6_vS32b_ai, V6_vS32b_pred_ai, V6_vS32b_npred_ai },
16610 { V6_vS32b_new_ai, V6_vS32b_new_pred_ai, V6_vS32b_new_npred_ai },
16611 { V6_vS32b_new_pi, V6_vS32b_new_pred_pi, V6_vS32b_new_npred_pi },
16612 { V6_vS32b_new_ppu, V6_vS32b_new_pred_ppu, V6_vS32b_new_npred_ppu },
16613 { V6_vS32b_nt_ai, V6_vS32b_nt_pred_ai, V6_vS32b_nt_npred_ai },
16614 { V6_vS32b_nt_new_ai, V6_vS32b_nt_new_pred_ai, V6_vS32b_nt_new_npred_ai },
16615 { V6_vS32b_nt_new_pi, V6_vS32b_nt_new_pred_pi, V6_vS32b_nt_new_npred_pi },
16616 { V6_vS32b_nt_new_ppu, V6_vS32b_nt_new_pred_ppu, V6_vS32b_nt_new_npred_ppu },
16617 { V6_vS32b_nt_pi, V6_vS32b_nt_pred_pi, V6_vS32b_nt_npred_pi },
16618 { V6_vS32b_nt_ppu, V6_vS32b_nt_pred_ppu, V6_vS32b_nt_npred_ppu },
16619 { V6_vS32b_pi, V6_vS32b_pred_pi, V6_vS32b_npred_pi },
16620 { V6_vS32b_ppu, V6_vS32b_pred_ppu, V6_vS32b_npred_ppu },
16621 }; // End of Table
16622
16623 unsigned mid;
16624 unsigned start = 0;
16625 unsigned end = 128;
16626 while (start < end) {
16627 mid = start + (end - start) / 2;
16628 if (Opcode == Table[mid][0])
16629 break;
16630 if (Opcode < Table[mid][0])
16631 end = mid;
16632 else
16633 start = mid + 1;
16634 }
16635 if (start == end)
16636 return -1; // Instruction doesn't exist in this table.
16637
16638 if (inPredSense == PredSense_true)
16639 return Table[mid][1];
16640 if (inPredSense == PredSense_false)
16641 return Table[mid][2];
16642 return -1;}
16643
16644// getRealHWInstr
16645LLVM_READONLY
16646int getRealHWInstr(uint16_t Opcode, enum InstrType inInstrType) {
16647 using namespace Hexagon;
16648 return -1;
16649}
16650
16651// getRegForm
16652LLVM_READONLY
16653int getRegForm(uint16_t Opcode) {
16654 using namespace Hexagon;
16655 static constexpr uint16_t Table[][2] = {
16656 { M2_mpysmi, M2_mpyi },
16657 { A2_addi, A2_add },
16658 { A2_andir, A2_and },
16659 { A2_orir, A2_or },
16660 { A2_paddif, A2_paddf },
16661 { A2_paddifnew, A2_paddfnew },
16662 { A2_paddit, A2_paddt },
16663 { A2_padditnew, A2_paddtnew },
16664 { A2_subri, A2_sub },
16665 { A4_cmpbeqi, A4_cmpbeq },
16666 { A4_cmpbgti, A4_cmpbgt },
16667 { A4_cmpbgtui, A4_cmpbgtu },
16668 { A4_cmpheqi, A4_cmpheq },
16669 { A4_cmphgti, A4_cmphgt },
16670 { A4_cmphgtui, A4_cmphgtu },
16671 { C2_cmoveif, A2_tfrf },
16672 { C2_cmoveit, A2_tfrt },
16673 { C2_cmovenewif, A2_tfrfnew },
16674 { C2_cmovenewit, A2_tfrtnew },
16675 { C2_cmpeqi, C2_cmpeq },
16676 { C2_cmpgti, C2_cmpgt },
16677 { C2_cmpgtui, C2_cmpgtu },
16678 { C4_cmpltei, C4_cmplte },
16679 { C4_cmplteui, C4_cmplteu },
16680 { C4_cmpneqi, C4_cmpneq },
16681 { M2_accii, M2_acci },
16682 { M2_macsip, M2_maci },
16683 { M4_mpyrr_addi, M4_mpyrr_addr },
16684 }; // End of Table
16685
16686 unsigned mid;
16687 unsigned start = 0;
16688 unsigned end = 28;
16689 while (start < end) {
16690 mid = start + (end - start) / 2;
16691 if (Opcode == Table[mid][0])
16692 break;
16693 if (Opcode < Table[mid][0])
16694 end = mid;
16695 else
16696 start = mid + 1;
16697 }
16698 if (start == end)
16699 return -1; // Instruction doesn't exist in this table.
16700
16701 return Table[mid][1];
16702}
16703
16704// getTruePredOpcode
16705LLVM_READONLY
16706int getTruePredOpcode(uint16_t Opcode) {
16707 using namespace Hexagon;
16708 static constexpr uint16_t Table[][2] = {
16709 { A2_tfrf, A2_tfrt },
16710 { A2_tfrfnew, A2_tfrtnew },
16711 { A2_tfrpf, A2_tfrpt },
16712 { A2_tfrpfnew, A2_tfrptnew },
16713 { A2_paddf, A2_paddt },
16714 { A2_paddfnew, A2_paddtnew },
16715 { A2_paddif, A2_paddit },
16716 { A2_paddifnew, A2_padditnew },
16717 { A2_pandf, A2_pandt },
16718 { A2_pandfnew, A2_pandtnew },
16719 { A2_porf, A2_port },
16720 { A2_porfnew, A2_portnew },
16721 { A2_psubf, A2_psubt },
16722 { A2_psubfnew, A2_psubtnew },
16723 { A2_pxorf, A2_pxort },
16724 { A2_pxorfnew, A2_pxortnew },
16725 { A4_paslhf, A4_paslht },
16726 { A4_paslhfnew, A4_paslhtnew },
16727 { A4_pasrhf, A4_pasrht },
16728 { A4_pasrhfnew, A4_pasrhtnew },
16729 { A4_psxtbf, A4_psxtbt },
16730 { A4_psxtbfnew, A4_psxtbtnew },
16731 { A4_psxthf, A4_psxtht },
16732 { A4_psxthfnew, A4_psxthtnew },
16733 { A4_pzxtbf, A4_pzxtbt },
16734 { A4_pzxtbfnew, A4_pzxtbtnew },
16735 { A4_pzxthf, A4_pzxtht },
16736 { A4_pzxthfnew, A4_pzxthtnew },
16737 { C2_ccombinewf, C2_ccombinewt },
16738 { C2_ccombinewnewf, C2_ccombinewnewt },
16739 { C2_cmoveif, C2_cmoveit },
16740 { C2_cmovenewif, C2_cmovenewit },
16741 { J2_callf, J2_callt },
16742 { J2_jumpf, J2_jumpt },
16743 { J2_jumpfnew, J2_jumptnew },
16744 { J2_jumpfnewpt, J2_jumptnewpt },
16745 { J2_jumpfpt, J2_jumptpt },
16746 { J2_jumprf, J2_jumprt },
16747 { J2_jumprfnew, J2_jumprtnew },
16748 { J2_jumprfnewpt, J2_jumprtnewpt },
16749 { J2_jumprfpt, J2_jumprtpt },
16750 { J4_cmpeq_f_jumpnv_nt, J4_cmpeq_t_jumpnv_nt },
16751 { J4_cmpeq_f_jumpnv_t, J4_cmpeq_t_jumpnv_t },
16752 { J4_cmpeq_fp0_jump_nt, J4_cmpeq_tp0_jump_nt },
16753 { J4_cmpeq_fp0_jump_t, J4_cmpeq_tp0_jump_t },
16754 { J4_cmpeq_fp1_jump_nt, J4_cmpeq_tp1_jump_nt },
16755 { J4_cmpeq_fp1_jump_t, J4_cmpeq_tp1_jump_t },
16756 { J4_cmpeqi_f_jumpnv_nt, J4_cmpeqi_t_jumpnv_nt },
16757 { J4_cmpeqi_f_jumpnv_t, J4_cmpeqi_t_jumpnv_t },
16758 { J4_cmpeqi_fp0_jump_nt, J4_cmpeqi_tp0_jump_nt },
16759 { J4_cmpeqi_fp0_jump_t, J4_cmpeqi_tp0_jump_t },
16760 { J4_cmpeqi_fp1_jump_nt, J4_cmpeqi_tp1_jump_nt },
16761 { J4_cmpeqi_fp1_jump_t, J4_cmpeqi_tp1_jump_t },
16762 { J4_cmpeqn1_f_jumpnv_nt, J4_cmpeqn1_t_jumpnv_nt },
16763 { J4_cmpeqn1_f_jumpnv_t, J4_cmpeqn1_t_jumpnv_t },
16764 { J4_cmpeqn1_fp0_jump_nt, J4_cmpeqn1_tp0_jump_nt },
16765 { J4_cmpeqn1_fp0_jump_t, J4_cmpeqn1_tp0_jump_t },
16766 { J4_cmpeqn1_fp1_jump_nt, J4_cmpeqn1_tp1_jump_nt },
16767 { J4_cmpeqn1_fp1_jump_t, J4_cmpeqn1_tp1_jump_t },
16768 { J4_cmpgt_f_jumpnv_nt, J4_cmpgt_t_jumpnv_nt },
16769 { J4_cmpgt_f_jumpnv_t, J4_cmpgt_t_jumpnv_t },
16770 { J4_cmpgt_fp0_jump_nt, J4_cmpgt_tp0_jump_nt },
16771 { J4_cmpgt_fp0_jump_t, J4_cmpgt_tp0_jump_t },
16772 { J4_cmpgt_fp1_jump_nt, J4_cmpgt_tp1_jump_nt },
16773 { J4_cmpgt_fp1_jump_t, J4_cmpgt_tp1_jump_t },
16774 { J4_cmpgti_f_jumpnv_nt, J4_cmpgti_t_jumpnv_nt },
16775 { J4_cmpgti_f_jumpnv_t, J4_cmpgti_t_jumpnv_t },
16776 { J4_cmpgti_fp0_jump_nt, J4_cmpgti_tp0_jump_nt },
16777 { J4_cmpgti_fp0_jump_t, J4_cmpgti_tp0_jump_t },
16778 { J4_cmpgti_fp1_jump_nt, J4_cmpgti_tp1_jump_nt },
16779 { J4_cmpgti_fp1_jump_t, J4_cmpgti_tp1_jump_t },
16780 { J4_cmpgtn1_f_jumpnv_nt, J4_cmpgtn1_t_jumpnv_nt },
16781 { J4_cmpgtn1_f_jumpnv_t, J4_cmpgtn1_t_jumpnv_t },
16782 { J4_cmpgtn1_fp0_jump_nt, J4_cmpgtn1_tp0_jump_nt },
16783 { J4_cmpgtn1_fp0_jump_t, J4_cmpgtn1_tp0_jump_t },
16784 { J4_cmpgtn1_fp1_jump_nt, J4_cmpgtn1_tp1_jump_nt },
16785 { J4_cmpgtn1_fp1_jump_t, J4_cmpgtn1_tp1_jump_t },
16786 { J4_cmpgtu_f_jumpnv_nt, J4_cmpgtu_t_jumpnv_nt },
16787 { J4_cmpgtu_f_jumpnv_t, J4_cmpgtu_t_jumpnv_t },
16788 { J4_cmpgtu_fp0_jump_nt, J4_cmpgtu_tp0_jump_nt },
16789 { J4_cmpgtu_fp0_jump_t, J4_cmpgtu_tp0_jump_t },
16790 { J4_cmpgtu_fp1_jump_nt, J4_cmpgtu_tp1_jump_nt },
16791 { J4_cmpgtu_fp1_jump_t, J4_cmpgtu_tp1_jump_t },
16792 { J4_cmpgtui_f_jumpnv_nt, J4_cmpgtui_t_jumpnv_nt },
16793 { J4_cmpgtui_f_jumpnv_t, J4_cmpgtui_t_jumpnv_t },
16794 { J4_cmpgtui_fp0_jump_nt, J4_cmpgtui_tp0_jump_nt },
16795 { J4_cmpgtui_fp0_jump_t, J4_cmpgtui_tp0_jump_t },
16796 { J4_cmpgtui_fp1_jump_nt, J4_cmpgtui_tp1_jump_nt },
16797 { J4_cmpgtui_fp1_jump_t, J4_cmpgtui_tp1_jump_t },
16798 { J4_cmplt_f_jumpnv_nt, J4_cmplt_t_jumpnv_nt },
16799 { J4_cmplt_f_jumpnv_t, J4_cmplt_t_jumpnv_t },
16800 { J4_cmpltu_f_jumpnv_nt, J4_cmpltu_t_jumpnv_nt },
16801 { J4_cmpltu_f_jumpnv_t, J4_cmpltu_t_jumpnv_t },
16802 { L2_ploadrbf_io, L2_ploadrbt_io },
16803 { L2_ploadrbf_pi, L2_ploadrbt_pi },
16804 { L2_ploadrbfnew_io, L2_ploadrbtnew_io },
16805 { L2_ploadrbfnew_pi, L2_ploadrbtnew_pi },
16806 { L2_ploadrdf_io, L2_ploadrdt_io },
16807 { L2_ploadrdf_pi, L2_ploadrdt_pi },
16808 { L2_ploadrdfnew_io, L2_ploadrdtnew_io },
16809 { L2_ploadrdfnew_pi, L2_ploadrdtnew_pi },
16810 { L2_ploadrhf_io, L2_ploadrht_io },
16811 { L2_ploadrhf_pi, L2_ploadrht_pi },
16812 { L2_ploadrhfnew_io, L2_ploadrhtnew_io },
16813 { L2_ploadrhfnew_pi, L2_ploadrhtnew_pi },
16814 { L2_ploadrif_io, L2_ploadrit_io },
16815 { L2_ploadrif_pi, L2_ploadrit_pi },
16816 { L2_ploadrifnew_io, L2_ploadritnew_io },
16817 { L2_ploadrifnew_pi, L2_ploadritnew_pi },
16818 { L2_ploadrubf_io, L2_ploadrubt_io },
16819 { L2_ploadrubf_pi, L2_ploadrubt_pi },
16820 { L2_ploadrubfnew_io, L2_ploadrubtnew_io },
16821 { L2_ploadrubfnew_pi, L2_ploadrubtnew_pi },
16822 { L2_ploadruhf_io, L2_ploadruht_io },
16823 { L2_ploadruhf_pi, L2_ploadruht_pi },
16824 { L2_ploadruhfnew_io, L2_ploadruhtnew_io },
16825 { L2_ploadruhfnew_pi, L2_ploadruhtnew_pi },
16826 { L4_ploadrbf_abs, L4_ploadrbt_abs },
16827 { L4_ploadrbf_rr, L4_ploadrbt_rr },
16828 { L4_ploadrbfnew_abs, L4_ploadrbtnew_abs },
16829 { L4_ploadrbfnew_rr, L4_ploadrbtnew_rr },
16830 { L4_ploadrdf_abs, L4_ploadrdt_abs },
16831 { L4_ploadrdf_rr, L4_ploadrdt_rr },
16832 { L4_ploadrdfnew_abs, L4_ploadrdtnew_abs },
16833 { L4_ploadrdfnew_rr, L4_ploadrdtnew_rr },
16834 { L4_ploadrhf_abs, L4_ploadrht_abs },
16835 { L4_ploadrhf_rr, L4_ploadrht_rr },
16836 { L4_ploadrhfnew_abs, L4_ploadrhtnew_abs },
16837 { L4_ploadrhfnew_rr, L4_ploadrhtnew_rr },
16838 { L4_ploadrif_abs, L4_ploadrit_abs },
16839 { L4_ploadrif_rr, L4_ploadrit_rr },
16840 { L4_ploadrifnew_abs, L4_ploadritnew_abs },
16841 { L4_ploadrifnew_rr, L4_ploadritnew_rr },
16842 { L4_ploadrubf_abs, L4_ploadrubt_abs },
16843 { L4_ploadrubf_rr, L4_ploadrubt_rr },
16844 { L4_ploadrubfnew_abs, L4_ploadrubtnew_abs },
16845 { L4_ploadrubfnew_rr, L4_ploadrubtnew_rr },
16846 { L4_ploadruhf_abs, L4_ploadruht_abs },
16847 { L4_ploadruhf_rr, L4_ploadruht_rr },
16848 { L4_ploadruhfnew_abs, L4_ploadruhtnew_abs },
16849 { L4_ploadruhfnew_rr, L4_ploadruhtnew_rr },
16850 { L4_return_f, L4_return_t },
16851 { L4_return_fnew_pnt, L4_return_tnew_pnt },
16852 { L4_return_fnew_pt, L4_return_tnew_pt },
16853 { PS_jmpretf, PS_jmprett },
16854 { PS_jmpretfnew, PS_jmprettnew },
16855 { PS_jmpretfnewpt, PS_jmprettnewpt },
16856 { S2_pstorerbf_io, S2_pstorerbt_io },
16857 { S2_pstorerbf_pi, S2_pstorerbt_pi },
16858 { S2_pstorerbfnew_pi, S2_pstorerbtnew_pi },
16859 { S2_pstorerbnewf_io, S2_pstorerbnewt_io },
16860 { S2_pstorerbnewf_pi, S2_pstorerbnewt_pi },
16861 { S2_pstorerbnewfnew_pi, S2_pstorerbnewtnew_pi },
16862 { S2_pstorerdf_io, S2_pstorerdt_io },
16863 { S2_pstorerdf_pi, S2_pstorerdt_pi },
16864 { S2_pstorerdfnew_pi, S2_pstorerdtnew_pi },
16865 { S2_pstorerff_io, S2_pstorerft_io },
16866 { S2_pstorerff_pi, S2_pstorerft_pi },
16867 { S2_pstorerffnew_pi, S2_pstorerftnew_pi },
16868 { S2_pstorerhf_io, S2_pstorerht_io },
16869 { S2_pstorerhf_pi, S2_pstorerht_pi },
16870 { S2_pstorerhfnew_pi, S2_pstorerhtnew_pi },
16871 { S2_pstorerhnewf_io, S2_pstorerhnewt_io },
16872 { S2_pstorerhnewf_pi, S2_pstorerhnewt_pi },
16873 { S2_pstorerhnewfnew_pi, S2_pstorerhnewtnew_pi },
16874 { S2_pstorerif_io, S2_pstorerit_io },
16875 { S2_pstorerif_pi, S2_pstorerit_pi },
16876 { S2_pstorerifnew_pi, S2_pstoreritnew_pi },
16877 { S2_pstorerinewf_io, S2_pstorerinewt_io },
16878 { S2_pstorerinewf_pi, S2_pstorerinewt_pi },
16879 { S2_pstorerinewfnew_pi, S2_pstorerinewtnew_pi },
16880 { S4_pstorerbf_abs, S4_pstorerbt_abs },
16881 { S4_pstorerbf_rr, S4_pstorerbt_rr },
16882 { S4_pstorerbfnew_abs, S4_pstorerbtnew_abs },
16883 { S4_pstorerbfnew_io, S4_pstorerbtnew_io },
16884 { S4_pstorerbfnew_rr, S4_pstorerbtnew_rr },
16885 { S4_pstorerbnewf_abs, S4_pstorerbnewt_abs },
16886 { S4_pstorerbnewf_rr, S4_pstorerbnewt_rr },
16887 { S4_pstorerbnewfnew_abs, S4_pstorerbnewtnew_abs },
16888 { S4_pstorerbnewfnew_io, S4_pstorerbnewtnew_io },
16889 { S4_pstorerbnewfnew_rr, S4_pstorerbnewtnew_rr },
16890 { S4_pstorerdf_abs, S4_pstorerdt_abs },
16891 { S4_pstorerdf_rr, S4_pstorerdt_rr },
16892 { S4_pstorerdfnew_abs, S4_pstorerdtnew_abs },
16893 { S4_pstorerdfnew_io, S4_pstorerdtnew_io },
16894 { S4_pstorerdfnew_rr, S4_pstorerdtnew_rr },
16895 { S4_pstorerff_abs, S4_pstorerft_abs },
16896 { S4_pstorerff_rr, S4_pstorerft_rr },
16897 { S4_pstorerffnew_abs, S4_pstorerftnew_abs },
16898 { S4_pstorerffnew_io, S4_pstorerftnew_io },
16899 { S4_pstorerffnew_rr, S4_pstorerftnew_rr },
16900 { S4_pstorerhf_abs, S4_pstorerht_abs },
16901 { S4_pstorerhf_rr, S4_pstorerht_rr },
16902 { S4_pstorerhfnew_abs, S4_pstorerhtnew_abs },
16903 { S4_pstorerhfnew_io, S4_pstorerhtnew_io },
16904 { S4_pstorerhfnew_rr, S4_pstorerhtnew_rr },
16905 { S4_pstorerhnewf_abs, S4_pstorerhnewt_abs },
16906 { S4_pstorerhnewf_rr, S4_pstorerhnewt_rr },
16907 { S4_pstorerhnewfnew_abs, S4_pstorerhnewtnew_abs },
16908 { S4_pstorerhnewfnew_io, S4_pstorerhnewtnew_io },
16909 { S4_pstorerhnewfnew_rr, S4_pstorerhnewtnew_rr },
16910 { S4_pstorerif_abs, S4_pstorerit_abs },
16911 { S4_pstorerif_rr, S4_pstorerit_rr },
16912 { S4_pstorerifnew_abs, S4_pstoreritnew_abs },
16913 { S4_pstorerifnew_io, S4_pstoreritnew_io },
16914 { S4_pstorerifnew_rr, S4_pstoreritnew_rr },
16915 { S4_pstorerinewf_abs, S4_pstorerinewt_abs },
16916 { S4_pstorerinewf_rr, S4_pstorerinewt_rr },
16917 { S4_pstorerinewfnew_abs, S4_pstorerinewtnew_abs },
16918 { S4_pstorerinewfnew_io, S4_pstorerinewtnew_io },
16919 { S4_pstorerinewfnew_rr, S4_pstorerinewtnew_rr },
16920 { S4_storeirbf_io, S4_storeirbt_io },
16921 { S4_storeirbfnew_io, S4_storeirbtnew_io },
16922 { S4_storeirhf_io, S4_storeirht_io },
16923 { S4_storeirhfnew_io, S4_storeirhtnew_io },
16924 { S4_storeirif_io, S4_storeirit_io },
16925 { S4_storeirifnew_io, S4_storeiritnew_io },
16926 { V6_vL32b_cur_npred_ai, V6_vL32b_cur_pred_ai },
16927 { V6_vL32b_cur_npred_pi, V6_vL32b_cur_pred_pi },
16928 { V6_vL32b_cur_npred_ppu, V6_vL32b_cur_pred_ppu },
16929 { V6_vL32b_npred_ai, V6_vL32b_pred_ai },
16930 { V6_vL32b_npred_pi, V6_vL32b_pred_pi },
16931 { V6_vL32b_npred_ppu, V6_vL32b_pred_ppu },
16932 { V6_vL32b_nt_cur_npred_ai, V6_vL32b_nt_cur_pred_ai },
16933 { V6_vL32b_nt_cur_npred_pi, V6_vL32b_nt_cur_pred_pi },
16934 { V6_vL32b_nt_cur_npred_ppu, V6_vL32b_nt_cur_pred_ppu },
16935 { V6_vL32b_nt_npred_ai, V6_vL32b_nt_pred_ai },
16936 { V6_vL32b_nt_npred_pi, V6_vL32b_nt_pred_pi },
16937 { V6_vL32b_nt_npred_ppu, V6_vL32b_nt_pred_ppu },
16938 { V6_vL32b_nt_tmp_npred_ai, V6_vL32b_nt_tmp_pred_ai },
16939 { V6_vL32b_nt_tmp_npred_pi, V6_vL32b_nt_tmp_pred_pi },
16940 { V6_vL32b_nt_tmp_npred_ppu, V6_vL32b_nt_tmp_pred_ppu },
16941 { V6_vL32b_tmp_npred_ai, V6_vL32b_tmp_pred_ai },
16942 { V6_vL32b_tmp_npred_pi, V6_vL32b_tmp_pred_pi },
16943 { V6_vL32b_tmp_npred_ppu, V6_vL32b_tmp_pred_ppu },
16944 { V6_vS32Ub_npred_ai, V6_vS32Ub_pred_ai },
16945 { V6_vS32Ub_npred_pi, V6_vS32Ub_pred_pi },
16946 { V6_vS32Ub_npred_ppu, V6_vS32Ub_pred_ppu },
16947 { V6_vS32b_new_npred_ai, V6_vS32b_new_pred_ai },
16948 { V6_vS32b_new_npred_pi, V6_vS32b_new_pred_pi },
16949 { V6_vS32b_new_npred_ppu, V6_vS32b_new_pred_ppu },
16950 { V6_vS32b_npred_ai, V6_vS32b_pred_ai },
16951 { V6_vS32b_npred_pi, V6_vS32b_pred_pi },
16952 { V6_vS32b_npred_ppu, V6_vS32b_pred_ppu },
16953 { V6_vS32b_nt_new_npred_ai, V6_vS32b_nt_new_pred_ai },
16954 { V6_vS32b_nt_new_npred_pi, V6_vS32b_nt_new_pred_pi },
16955 { V6_vS32b_nt_new_npred_ppu, V6_vS32b_nt_new_pred_ppu },
16956 { V6_vS32b_nt_npred_ai, V6_vS32b_nt_pred_ai },
16957 { V6_vS32b_nt_npred_pi, V6_vS32b_nt_pred_pi },
16958 { V6_vS32b_nt_npred_ppu, V6_vS32b_nt_pred_ppu },
16959 }; // End of Table
16960
16961 unsigned mid;
16962 unsigned start = 0;
16963 unsigned end = 250;
16964 while (start < end) {
16965 mid = start + (end - start) / 2;
16966 if (Opcode == Table[mid][0])
16967 break;
16968 if (Opcode < Table[mid][0])
16969 end = mid;
16970 else
16971 start = mid + 1;
16972 }
16973 if (start == end)
16974 return -1; // Instruction doesn't exist in this table.
16975
16976 return Table[mid][1];
16977}
16978
16979// notTakenBranchPrediction
16980LLVM_READONLY
16981int notTakenBranchPrediction(uint16_t Opcode) {
16982 using namespace Hexagon;
16983 static constexpr uint16_t Table[][2] = {
16984 { J2_jumpfnewpt, J2_jumpfnew },
16985 { J2_jumpfpt, J2_jumpf },
16986 { J2_jumprfnewpt, J2_jumprfnew },
16987 { J2_jumprfpt, J2_jumprf },
16988 { J2_jumprtnewpt, J2_jumprtnew },
16989 { J2_jumprtpt, J2_jumprt },
16990 { J2_jumptnewpt, J2_jumptnew },
16991 { J2_jumptpt, J2_jumpt },
16992 { J4_cmpeq_f_jumpnv_t, J4_cmpeq_f_jumpnv_nt },
16993 { J4_cmpeq_fp0_jump_t, J4_cmpeq_fp0_jump_nt },
16994 { J4_cmpeq_fp1_jump_t, J4_cmpeq_fp1_jump_nt },
16995 { J4_cmpeq_t_jumpnv_t, J4_cmpeq_t_jumpnv_nt },
16996 { J4_cmpeq_tp0_jump_t, J4_cmpeq_tp0_jump_nt },
16997 { J4_cmpeq_tp1_jump_t, J4_cmpeq_tp1_jump_nt },
16998 { J4_cmpeqi_f_jumpnv_t, J4_cmpeqi_f_jumpnv_nt },
16999 { J4_cmpeqi_fp0_jump_t, J4_cmpeqi_fp0_jump_nt },
17000 { J4_cmpeqi_fp1_jump_t, J4_cmpeqi_fp1_jump_nt },
17001 { J4_cmpeqi_t_jumpnv_t, J4_cmpeqi_t_jumpnv_nt },
17002 { J4_cmpeqi_tp0_jump_t, J4_cmpeqi_tp0_jump_nt },
17003 { J4_cmpeqi_tp1_jump_t, J4_cmpeqi_tp1_jump_nt },
17004 { J4_cmpeqn1_f_jumpnv_t, J4_cmpeqn1_f_jumpnv_nt },
17005 { J4_cmpeqn1_fp0_jump_t, J4_cmpeqn1_fp0_jump_nt },
17006 { J4_cmpeqn1_fp1_jump_t, J4_cmpeqn1_fp1_jump_nt },
17007 { J4_cmpeqn1_t_jumpnv_t, J4_cmpeqn1_t_jumpnv_nt },
17008 { J4_cmpeqn1_tp0_jump_t, J4_cmpeqn1_tp0_jump_nt },
17009 { J4_cmpeqn1_tp1_jump_t, J4_cmpeqn1_tp1_jump_nt },
17010 { J4_cmpgt_f_jumpnv_t, J4_cmpgt_f_jumpnv_nt },
17011 { J4_cmpgt_fp0_jump_t, J4_cmpgt_fp0_jump_nt },
17012 { J4_cmpgt_fp1_jump_t, J4_cmpgt_fp1_jump_nt },
17013 { J4_cmpgt_t_jumpnv_t, J4_cmpgt_t_jumpnv_nt },
17014 { J4_cmpgt_tp0_jump_t, J4_cmpgt_tp0_jump_nt },
17015 { J4_cmpgt_tp1_jump_t, J4_cmpgt_tp1_jump_nt },
17016 { J4_cmpgti_f_jumpnv_t, J4_cmpgti_f_jumpnv_nt },
17017 { J4_cmpgti_fp0_jump_t, J4_cmpgti_fp0_jump_nt },
17018 { J4_cmpgti_fp1_jump_t, J4_cmpgti_fp1_jump_nt },
17019 { J4_cmpgti_t_jumpnv_t, J4_cmpgti_t_jumpnv_nt },
17020 { J4_cmpgti_tp0_jump_t, J4_cmpgti_tp0_jump_nt },
17021 { J4_cmpgti_tp1_jump_t, J4_cmpgti_tp1_jump_nt },
17022 { J4_cmpgtn1_f_jumpnv_t, J4_cmpgtn1_f_jumpnv_nt },
17023 { J4_cmpgtn1_fp0_jump_t, J4_cmpgtn1_fp0_jump_nt },
17024 { J4_cmpgtn1_fp1_jump_t, J4_cmpgtn1_fp1_jump_nt },
17025 { J4_cmpgtn1_t_jumpnv_t, J4_cmpgtn1_t_jumpnv_nt },
17026 { J4_cmpgtn1_tp0_jump_t, J4_cmpgtn1_tp0_jump_nt },
17027 { J4_cmpgtn1_tp1_jump_t, J4_cmpgtn1_tp1_jump_nt },
17028 { J4_cmpgtu_f_jumpnv_t, J4_cmpgtu_f_jumpnv_nt },
17029 { J4_cmpgtu_fp0_jump_t, J4_cmpgtu_fp0_jump_nt },
17030 { J4_cmpgtu_fp1_jump_t, J4_cmpgtu_fp1_jump_nt },
17031 { J4_cmpgtu_t_jumpnv_t, J4_cmpgtu_t_jumpnv_nt },
17032 { J4_cmpgtu_tp0_jump_t, J4_cmpgtu_tp0_jump_nt },
17033 { J4_cmpgtu_tp1_jump_t, J4_cmpgtu_tp1_jump_nt },
17034 { J4_cmpgtui_f_jumpnv_t, J4_cmpgtui_f_jumpnv_nt },
17035 { J4_cmpgtui_fp0_jump_t, J4_cmpgtui_fp0_jump_nt },
17036 { J4_cmpgtui_fp1_jump_t, J4_cmpgtui_fp1_jump_nt },
17037 { J4_cmpgtui_t_jumpnv_t, J4_cmpgtui_t_jumpnv_nt },
17038 { J4_cmpgtui_tp0_jump_t, J4_cmpgtui_tp0_jump_nt },
17039 { J4_cmpgtui_tp1_jump_t, J4_cmpgtui_tp1_jump_nt },
17040 { J4_cmplt_f_jumpnv_t, J4_cmplt_f_jumpnv_nt },
17041 { J4_cmplt_t_jumpnv_t, J4_cmplt_t_jumpnv_nt },
17042 { J4_cmpltu_f_jumpnv_t, J4_cmpltu_f_jumpnv_nt },
17043 { J4_cmpltu_t_jumpnv_t, J4_cmpltu_t_jumpnv_nt },
17044 { L4_return_fnew_pt, L4_return_fnew_pnt },
17045 { L4_return_tnew_pt, L4_return_tnew_pnt },
17046 { PS_jmpretfnewpt, PS_jmpretfnew },
17047 { PS_jmprettnewpt, PS_jmprettnew },
17048 }; // End of Table
17049
17050 unsigned mid;
17051 unsigned start = 0;
17052 unsigned end = 64;
17053 while (start < end) {
17054 mid = start + (end - start) / 2;
17055 if (Opcode == Table[mid][0])
17056 break;
17057 if (Opcode < Table[mid][0])
17058 end = mid;
17059 else
17060 start = mid + 1;
17061 }
17062 if (start == end)
17063 return -1; // Instruction doesn't exist in this table.
17064
17065 return Table[mid][1];
17066}
17067
17068// takenBranchPrediction
17069LLVM_READONLY
17070int takenBranchPrediction(uint16_t Opcode) {
17071 using namespace Hexagon;
17072 static constexpr uint16_t Table[][2] = {
17073 { J2_jumpf, J2_jumpfpt },
17074 { J2_jumpfnew, J2_jumpfnewpt },
17075 { J2_jumprf, J2_jumprfpt },
17076 { J2_jumprfnew, J2_jumprfnewpt },
17077 { J2_jumprt, J2_jumprtpt },
17078 { J2_jumprtnew, J2_jumprtnewpt },
17079 { J2_jumpt, J2_jumptpt },
17080 { J2_jumptnew, J2_jumptnewpt },
17081 { J4_cmpeq_f_jumpnv_nt, J4_cmpeq_f_jumpnv_t },
17082 { J4_cmpeq_fp0_jump_nt, J4_cmpeq_fp0_jump_t },
17083 { J4_cmpeq_fp1_jump_nt, J4_cmpeq_fp1_jump_t },
17084 { J4_cmpeq_t_jumpnv_nt, J4_cmpeq_t_jumpnv_t },
17085 { J4_cmpeq_tp0_jump_nt, J4_cmpeq_tp0_jump_t },
17086 { J4_cmpeq_tp1_jump_nt, J4_cmpeq_tp1_jump_t },
17087 { J4_cmpeqi_f_jumpnv_nt, J4_cmpeqi_f_jumpnv_t },
17088 { J4_cmpeqi_fp0_jump_nt, J4_cmpeqi_fp0_jump_t },
17089 { J4_cmpeqi_fp1_jump_nt, J4_cmpeqi_fp1_jump_t },
17090 { J4_cmpeqi_t_jumpnv_nt, J4_cmpeqi_t_jumpnv_t },
17091 { J4_cmpeqi_tp0_jump_nt, J4_cmpeqi_tp0_jump_t },
17092 { J4_cmpeqi_tp1_jump_nt, J4_cmpeqi_tp1_jump_t },
17093 { J4_cmpeqn1_f_jumpnv_nt, J4_cmpeqn1_f_jumpnv_t },
17094 { J4_cmpeqn1_fp0_jump_nt, J4_cmpeqn1_fp0_jump_t },
17095 { J4_cmpeqn1_fp1_jump_nt, J4_cmpeqn1_fp1_jump_t },
17096 { J4_cmpeqn1_t_jumpnv_nt, J4_cmpeqn1_t_jumpnv_t },
17097 { J4_cmpeqn1_tp0_jump_nt, J4_cmpeqn1_tp0_jump_t },
17098 { J4_cmpeqn1_tp1_jump_nt, J4_cmpeqn1_tp1_jump_t },
17099 { J4_cmpgt_f_jumpnv_nt, J4_cmpgt_f_jumpnv_t },
17100 { J4_cmpgt_fp0_jump_nt, J4_cmpgt_fp0_jump_t },
17101 { J4_cmpgt_fp1_jump_nt, J4_cmpgt_fp1_jump_t },
17102 { J4_cmpgt_t_jumpnv_nt, J4_cmpgt_t_jumpnv_t },
17103 { J4_cmpgt_tp0_jump_nt, J4_cmpgt_tp0_jump_t },
17104 { J4_cmpgt_tp1_jump_nt, J4_cmpgt_tp1_jump_t },
17105 { J4_cmpgti_f_jumpnv_nt, J4_cmpgti_f_jumpnv_t },
17106 { J4_cmpgti_fp0_jump_nt, J4_cmpgti_fp0_jump_t },
17107 { J4_cmpgti_fp1_jump_nt, J4_cmpgti_fp1_jump_t },
17108 { J4_cmpgti_t_jumpnv_nt, J4_cmpgti_t_jumpnv_t },
17109 { J4_cmpgti_tp0_jump_nt, J4_cmpgti_tp0_jump_t },
17110 { J4_cmpgti_tp1_jump_nt, J4_cmpgti_tp1_jump_t },
17111 { J4_cmpgtn1_f_jumpnv_nt, J4_cmpgtn1_f_jumpnv_t },
17112 { J4_cmpgtn1_fp0_jump_nt, J4_cmpgtn1_fp0_jump_t },
17113 { J4_cmpgtn1_fp1_jump_nt, J4_cmpgtn1_fp1_jump_t },
17114 { J4_cmpgtn1_t_jumpnv_nt, J4_cmpgtn1_t_jumpnv_t },
17115 { J4_cmpgtn1_tp0_jump_nt, J4_cmpgtn1_tp0_jump_t },
17116 { J4_cmpgtn1_tp1_jump_nt, J4_cmpgtn1_tp1_jump_t },
17117 { J4_cmpgtu_f_jumpnv_nt, J4_cmpgtu_f_jumpnv_t },
17118 { J4_cmpgtu_fp0_jump_nt, J4_cmpgtu_fp0_jump_t },
17119 { J4_cmpgtu_fp1_jump_nt, J4_cmpgtu_fp1_jump_t },
17120 { J4_cmpgtu_t_jumpnv_nt, J4_cmpgtu_t_jumpnv_t },
17121 { J4_cmpgtu_tp0_jump_nt, J4_cmpgtu_tp0_jump_t },
17122 { J4_cmpgtu_tp1_jump_nt, J4_cmpgtu_tp1_jump_t },
17123 { J4_cmpgtui_f_jumpnv_nt, J4_cmpgtui_f_jumpnv_t },
17124 { J4_cmpgtui_fp0_jump_nt, J4_cmpgtui_fp0_jump_t },
17125 { J4_cmpgtui_fp1_jump_nt, J4_cmpgtui_fp1_jump_t },
17126 { J4_cmpgtui_t_jumpnv_nt, J4_cmpgtui_t_jumpnv_t },
17127 { J4_cmpgtui_tp0_jump_nt, J4_cmpgtui_tp0_jump_t },
17128 { J4_cmpgtui_tp1_jump_nt, J4_cmpgtui_tp1_jump_t },
17129 { J4_cmplt_f_jumpnv_nt, J4_cmplt_f_jumpnv_t },
17130 { J4_cmplt_t_jumpnv_nt, J4_cmplt_t_jumpnv_t },
17131 { J4_cmpltu_f_jumpnv_nt, J4_cmpltu_f_jumpnv_t },
17132 { J4_cmpltu_t_jumpnv_nt, J4_cmpltu_t_jumpnv_t },
17133 { L4_return_fnew_pnt, L4_return_fnew_pt },
17134 { L4_return_tnew_pnt, L4_return_tnew_pt },
17135 { PS_jmpretfnew, PS_jmpretfnewpt },
17136 { PS_jmprettnew, PS_jmprettnewpt },
17137 }; // End of Table
17138
17139 unsigned mid;
17140 unsigned start = 0;
17141 unsigned end = 64;
17142 while (start < end) {
17143 mid = start + (end - start) / 2;
17144 if (Opcode == Table[mid][0])
17145 break;
17146 if (Opcode < Table[mid][0])
17147 end = mid;
17148 else
17149 start = mid + 1;
17150 }
17151 if (start == end)
17152 return -1; // Instruction doesn't exist in this table.
17153
17154 return Table[mid][1];
17155}
17156
17157} // end namespace llvm::Hexagon
17158#endif // GET_INSTRMAP_INFO
17159
17160