1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register Enum Values *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9
10#ifdef GET_REGINFO_ENUM
11#undef GET_REGINFO_ENUM
12
13namespace llvm {
14
15class MCRegisterClass;
16extern const MCRegisterClass HexagonMCRegisterClasses[];
17
18namespace Hexagon {
19enum : unsigned {
20 NoRegister,
21 BADVA = 1,
22 CCR = 2,
23 CFGBASE = 3,
24 CS = 4,
25 DIAG = 5,
26 ELR = 6,
27 EVB = 7,
28 FRAMEKEY = 8,
29 FRAMELIMIT = 9,
30 GELR = 10,
31 GOSP = 11,
32 GP = 12,
33 GPCYCLEHI = 13,
34 GPCYCLELO = 14,
35 GSR = 15,
36 HTID = 16,
37 IMASK = 17,
38 ISDBEN = 18,
39 ISDBGPR = 19,
40 ISDBMBXIN = 20,
41 ISDBMBXOUT = 21,
42 ISDBST = 22,
43 MODECTL = 23,
44 PC = 24,
45 PCYCLEHI = 25,
46 PCYCLELO = 26,
47 PKTCOUNT = 27,
48 PKTCOUNTHI = 28,
49 PKTCOUNTLO = 29,
50 PMUCFG = 30,
51 PMUEVTCFG = 31,
52 REV = 32,
53 SSR = 33,
54 STID = 34,
55 SYSCFG = 35,
56 UGP = 36,
57 UPCYCLE = 37,
58 UPCYCLEHI = 38,
59 UPCYCLELO = 39,
60 USR = 40,
61 USR_OVF = 41,
62 UTIMER = 42,
63 UTIMERHI = 43,
64 UTIMERLO = 44,
65 VID = 45,
66 VTMP = 46,
67 BADVA0 = 47,
68 BADVA1 = 48,
69 BRKPTCFG0 = 49,
70 BRKPTCFG1 = 50,
71 BRKPTPC0 = 51,
72 BRKPTPC1 = 52,
73 C5 = 53,
74 C8 = 54,
75 CS0 = 55,
76 CS1 = 56,
77 D0 = 57,
78 D1 = 58,
79 D2 = 59,
80 D3 = 60,
81 D4 = 61,
82 D5 = 62,
83 D6 = 63,
84 D7 = 64,
85 D8 = 65,
86 D9 = 66,
87 D10 = 67,
88 D11 = 68,
89 D12 = 69,
90 D13 = 70,
91 D14 = 71,
92 D15 = 72,
93 G3 = 73,
94 G4 = 74,
95 G5 = 75,
96 G6 = 76,
97 G7 = 77,
98 G8 = 78,
99 G9 = 79,
100 G10 = 80,
101 G11 = 81,
102 G12 = 82,
103 G13 = 83,
104 G14 = 84,
105 G15 = 85,
106 G20 = 86,
107 G21 = 87,
108 G22 = 88,
109 G23 = 89,
110 G30 = 90,
111 G31 = 91,
112 GPMUCNT0 = 92,
113 GPMUCNT1 = 93,
114 GPMUCNT2 = 94,
115 GPMUCNT3 = 95,
116 GPMUCNT4 = 96,
117 GPMUCNT5 = 97,
118 GPMUCNT6 = 98,
119 GPMUCNT7 = 99,
120 ISDBCFG0 = 100,
121 ISDBCFG1 = 101,
122 LC0 = 102,
123 LC1 = 103,
124 M0 = 104,
125 M1 = 105,
126 P0 = 106,
127 P1 = 107,
128 P2 = 108,
129 P3 = 109,
130 PMUCNT0 = 110,
131 PMUCNT1 = 111,
132 PMUCNT2 = 112,
133 PMUCNT3 = 113,
134 Q0 = 114,
135 Q1 = 115,
136 Q2 = 116,
137 Q3 = 117,
138 R0 = 118,
139 R1 = 119,
140 R2 = 120,
141 R3 = 121,
142 R4 = 122,
143 R5 = 123,
144 R6 = 124,
145 R7 = 125,
146 R8 = 126,
147 R9 = 127,
148 R10 = 128,
149 R11 = 129,
150 R12 = 130,
151 R13 = 131,
152 R14 = 132,
153 R15 = 133,
154 R16 = 134,
155 R17 = 135,
156 R18 = 136,
157 R19 = 137,
158 R20 = 138,
159 R21 = 139,
160 R22 = 140,
161 R23 = 141,
162 R24 = 142,
163 R25 = 143,
164 R26 = 144,
165 R27 = 145,
166 R28 = 146,
167 R29 = 147,
168 R30 = 148,
169 R31 = 149,
170 S11 = 150,
171 S12 = 151,
172 S13 = 152,
173 S14 = 153,
174 S15 = 154,
175 S19 = 155,
176 S20 = 156,
177 S22 = 157,
178 S23 = 158,
179 S24 = 159,
180 S25 = 160,
181 S26 = 161,
182 S35 = 162,
183 S44 = 163,
184 S45 = 164,
185 S46 = 165,
186 S47 = 166,
187 S54 = 167,
188 S55 = 168,
189 S56 = 169,
190 S57 = 170,
191 S58 = 171,
192 S59 = 172,
193 S60 = 173,
194 S61 = 174,
195 S62 = 175,
196 S63 = 176,
197 S64 = 177,
198 S65 = 178,
199 S66 = 179,
200 S67 = 180,
201 S68 = 181,
202 S69 = 182,
203 S70 = 183,
204 S71 = 184,
205 S72 = 185,
206 S73 = 186,
207 S74 = 187,
208 S75 = 188,
209 S76 = 189,
210 S77 = 190,
211 S78 = 191,
212 S79 = 192,
213 S80 = 193,
214 SA0 = 194,
215 SA1 = 195,
216 SGP0 = 196,
217 SGP1 = 197,
218 V0 = 198,
219 V1 = 199,
220 V2 = 200,
221 V3 = 201,
222 V4 = 202,
223 V5 = 203,
224 V6 = 204,
225 V7 = 205,
226 V8 = 206,
227 V9 = 207,
228 V10 = 208,
229 V11 = 209,
230 V12 = 210,
231 V13 = 211,
232 V14 = 212,
233 V15 = 213,
234 V16 = 214,
235 V17 = 215,
236 V18 = 216,
237 V19 = 217,
238 V20 = 218,
239 V21 = 219,
240 V22 = 220,
241 V23 = 221,
242 V24 = 222,
243 V25 = 223,
244 V26 = 224,
245 V27 = 225,
246 V28 = 226,
247 V29 = 227,
248 V30 = 228,
249 V31 = 229,
250 VF0 = 230,
251 VF1 = 231,
252 VF2 = 232,
253 VF3 = 233,
254 VF4 = 234,
255 VF5 = 235,
256 VF6 = 236,
257 VF7 = 237,
258 VF8 = 238,
259 VF9 = 239,
260 VF10 = 240,
261 VF11 = 241,
262 VF12 = 242,
263 VF13 = 243,
264 VF14 = 244,
265 VF15 = 245,
266 VF16 = 246,
267 VF17 = 247,
268 VF18 = 248,
269 VF19 = 249,
270 VF20 = 250,
271 VF21 = 251,
272 VF22 = 252,
273 VF23 = 253,
274 VF24 = 254,
275 VF25 = 255,
276 VF26 = 256,
277 VF27 = 257,
278 VF28 = 258,
279 VF29 = 259,
280 VF30 = 260,
281 VF31 = 261,
282 VFR0 = 262,
283 VFR1 = 263,
284 VFR2 = 264,
285 VFR3 = 265,
286 VFR4 = 266,
287 VFR5 = 267,
288 VFR6 = 268,
289 VFR7 = 269,
290 VFR8 = 270,
291 VFR9 = 271,
292 VFR10 = 272,
293 VFR11 = 273,
294 VFR12 = 274,
295 VFR13 = 275,
296 VFR14 = 276,
297 VFR15 = 277,
298 VFR16 = 278,
299 VFR17 = 279,
300 VFR18 = 280,
301 VFR19 = 281,
302 VFR20 = 282,
303 VFR21 = 283,
304 VFR22 = 284,
305 VFR23 = 285,
306 VFR24 = 286,
307 VFR25 = 287,
308 VFR26 = 288,
309 VFR27 = 289,
310 VFR28 = 290,
311 VFR29 = 291,
312 VFR30 = 292,
313 VFR31 = 293,
314 VQ0 = 294,
315 VQ1 = 295,
316 VQ2 = 296,
317 VQ3 = 297,
318 VQ4 = 298,
319 VQ5 = 299,
320 VQ6 = 300,
321 VQ7 = 301,
322 W0 = 302,
323 W1 = 303,
324 W2 = 304,
325 W3 = 305,
326 W4 = 306,
327 W5 = 307,
328 W6 = 308,
329 W7 = 309,
330 W8 = 310,
331 W9 = 311,
332 W10 = 312,
333 W11 = 313,
334 W12 = 314,
335 W13 = 315,
336 W14 = 316,
337 W15 = 317,
338 WR0 = 318,
339 WR1 = 319,
340 WR2 = 320,
341 WR3 = 321,
342 WR4 = 322,
343 WR5 = 323,
344 WR6 = 324,
345 WR7 = 325,
346 WR8 = 326,
347 WR9 = 327,
348 WR10 = 328,
349 WR11 = 329,
350 WR12 = 330,
351 WR13 = 331,
352 WR14 = 332,
353 WR15 = 333,
354 C1_0 = 334,
355 C3_2 = 335,
356 C5_4 = 336,
357 C7_6 = 337,
358 C9_8 = 338,
359 C11_10 = 339,
360 C17_16 = 340,
361 G1_0 = 341,
362 G3_2 = 342,
363 G5_4 = 343,
364 G7_6 = 344,
365 G9_8 = 345,
366 G11_10 = 346,
367 G13_12 = 347,
368 G15_14 = 348,
369 G17_16 = 349,
370 G19_18 = 350,
371 G21_20 = 351,
372 G23_22 = 352,
373 G25_24 = 353,
374 G27_26 = 354,
375 G29_28 = 355,
376 G31_30 = 356,
377 P3_0 = 357,
378 S3_2 = 358,
379 S5_4 = 359,
380 S7_6 = 360,
381 S9_8 = 361,
382 S11_10 = 362,
383 S13_12 = 363,
384 S15_14 = 364,
385 S17_16 = 365,
386 S19_18 = 366,
387 S21_20 = 367,
388 S23_22 = 368,
389 S25_24 = 369,
390 S27_26 = 370,
391 S29_28 = 371,
392 S31_30 = 372,
393 S33_32 = 373,
394 S35_34 = 374,
395 S37_36 = 375,
396 S39_38 = 376,
397 S41_40 = 377,
398 S43_42 = 378,
399 S45_44 = 379,
400 S47_46 = 380,
401 S49_48 = 381,
402 S51_50 = 382,
403 S53_52 = 383,
404 S55_54 = 384,
405 S57_56 = 385,
406 S59_58 = 386,
407 S61_60 = 387,
408 S63_62 = 388,
409 S65_64 = 389,
410 S67_66 = 390,
411 S69_68 = 391,
412 S71_70 = 392,
413 S73_72 = 393,
414 S75_74 = 394,
415 S77_76 = 395,
416 S79_78 = 396,
417 SGP1_0 = 397,
418 NUM_TARGET_REGS // 398
419};
420} // end namespace Hexagon
421
422// Register classes
423
424namespace Hexagon {
425enum {
426 UsrBitsRegClassID = 0,
427 SysRegsRegClassID = 1,
428 GuestRegsRegClassID = 2,
429 IntRegsRegClassID = 3,
430 CtrRegsRegClassID = 4,
431 GeneralSubRegsRegClassID = 5,
432 V62RegsRegClassID = 6,
433 IntRegsLow8RegClassID = 7,
434 CtrRegs_and_V62RegsRegClassID = 8,
435 PredRegsRegClassID = 9,
436 V62Regs_with_isub_hiRegClassID = 10,
437 ModRegsRegClassID = 11,
438 CtrRegs_with_subreg_overflowRegClassID = 12,
439 V65RegsRegClassID = 13,
440 SysRegs64RegClassID = 14,
441 DoubleRegsRegClassID = 15,
442 GuestRegs64RegClassID = 16,
443 VectRegRevRegClassID = 17,
444 CtrRegs64RegClassID = 18,
445 GeneralDoubleLow8RegsRegClassID = 19,
446 DoubleRegs_with_isub_hi_in_IntRegsLow8RegClassID = 20,
447 CtrRegs64_and_V62RegsRegClassID = 21,
448 CtrRegs64_with_isub_hi_in_ModRegsRegClassID = 22,
449 HvxQRRegClassID = 23,
450 HvxVRRegClassID = 24,
451 HvxVR_and_V65RegsRegClassID = 25,
452 HvxWRRegClassID = 26,
453 HvxWR_and_VectRegRevRegClassID = 27,
454 HvxVQRRegClassID = 28,
455
456};
457} // end namespace Hexagon
458
459
460// Subregister indices
461
462namespace Hexagon {
463enum : uint16_t {
464 NoSubRegister,
465 isub_hi, // 1
466 isub_lo, // 2
467 subreg_overflow, // 3
468 vsub_fake, // 4
469 vsub_hi, // 5
470 vsub_lo, // 6
471 wsub_hi, // 7
472 wsub_lo, // 8
473 wsub_hi_then_vsub_fake, // 9
474 wsub_hi_then_vsub_hi, // 10
475 wsub_hi_then_vsub_lo, // 11
476 NUM_TARGET_SUBREGS
477};
478} // end namespace Hexagon
479
480// Register pressure sets enum.
481namespace Hexagon {
482enum RegisterPressureSets {
483 HvxVR_and_V65Regs = 0,
484 ModRegs = 1,
485 HvxQR = 2,
486 IntRegsLow8 = 3,
487 PredRegs = 4,
488 GeneralSubRegs = 5,
489 IntRegs = 6,
490 HvxVR = 7,
491};
492} // end namespace Hexagon
493
494} // end namespace llvm
495
496#endif // GET_REGINFO_ENUM
497
498/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
499|* *|
500|* MC Register Information *|
501|* *|
502|* Automatically generated file, do not edit! *|
503|* *|
504\*===----------------------------------------------------------------------===*/
505
506
507#ifdef GET_REGINFO_MC_DESC
508#undef GET_REGINFO_MC_DESC
509
510namespace llvm {
511
512extern const int16_t HexagonRegDiffLists[] = {
513 /* 0 */ 21, -304, 0,
514 /* 3 */ -209, -158, 0,
515 /* 6 */ -211, -111, 0,
516 /* 9 */ -140, -92, 0,
517 /* 12 */ -77, 0,
518 /* 14 */ -76, 0,
519 /* 16 */ -75, 0,
520 /* 18 */ -74, 0,
521 /* 20 */ -73, 0,
522 /* 22 */ -72, 0,
523 /* 24 */ -71, 0,
524 /* 26 */ -70, 0,
525 /* 28 */ -69, 0,
526 /* 30 */ -68, 0,
527 /* 32 */ -67, 0,
528 /* 34 */ -66, 0,
529 /* 36 */ -65, 0,
530 /* 38 */ -64, 0,
531 /* 40 */ -63, 0,
532 /* 42 */ -62, 0,
533 /* 44 */ -61, 0,
534 /* 46 */ -52, 0,
535 /* 48 */ -51, 0,
536 /* 50 */ -327, -31, 0,
537 /* 53 */ -284, -30, 0,
538 /* 56 */ -324, -28, 0,
539 /* 59 */ -303, -24, 0,
540 /* 62 */ -21, 0,
541 /* 64 */ 72, -16, 0,
542 /* 67 */ -345, -15, 0,
543 /* 70 */ 72, -15, 0,
544 /* 73 */ 72, -14, 0,
545 /* 76 */ 72, -13, 0,
546 /* 79 */ 72, -12, 0,
547 /* 82 */ 72, -11, 0,
548 /* 85 */ 72, -10, 0,
549 /* 88 */ 72, -9, 0,
550 /* 91 */ 72, -8, 0,
551 /* 94 */ -324, -2, 0,
552 /* 97 */ -352, -1, 0,
553 /* 100 */ -346, -1, 0,
554 /* 103 */ -339, -1, 0,
555 /* 106 */ -331, -1, 0,
556 /* 109 */ -205, -1, 0,
557 /* 112 */ -204, -1, 0,
558 /* 115 */ 2, -1, 0,
559 /* 118 */ -360, 1, 0,
560 /* 121 */ -357, 1, 0,
561 /* 124 */ -312, 1, 0,
562 /* 127 */ -271, 1, 0,
563 /* 130 */ -270, 1, 0,
564 /* 133 */ -269, 1, 0,
565 /* 136 */ -268, 1, 0,
566 /* 139 */ -267, 1, 0,
567 /* 142 */ -266, 1, 0,
568 /* 145 */ -265, 1, 0,
569 /* 148 */ -264, 1, 0,
570 /* 151 */ -262, 1, 0,
571 /* 154 */ -261, 1, 0,
572 /* 157 */ -253, 1, 0,
573 /* 160 */ -252, 1, 0,
574 /* 163 */ -233, 1, 0,
575 /* 166 */ -217, 1, 0,
576 /* 169 */ -216, 1, 0,
577 /* 172 */ -215, 1, 0,
578 /* 175 */ -214, 1, 0,
579 /* 178 */ -213, 1, 0,
580 /* 181 */ -212, 1, 0,
581 /* 184 */ -211, 1, 0,
582 /* 187 */ -210, 1, 0,
583 /* 190 */ -209, 1, 0,
584 /* 193 */ -208, 1, 0,
585 /* 196 */ -207, 1, 0,
586 /* 199 */ -201, 1, 0,
587 /* 202 */ 1, 1, 1, 15, 1, 0,
588 /* 208 */ 1, 1, 1, 17, 1, 0,
589 /* 214 */ 1, 1, 1, 19, 1, 0,
590 /* 220 */ 1, 1, 1, 21, 1, 0,
591 /* 226 */ 1, 1, 1, 23, 1, 0,
592 /* 232 */ 1, 1, 1, 25, 1, 0,
593 /* 238 */ 1, 1, 1, 27, 1, 0,
594 /* 244 */ 1, 1, 1, 29, 1, 0,
595 /* 250 */ 51, 1, 0,
596 /* 253 */ 61, 1, 0,
597 /* 256 */ 62, 1, 0,
598 /* 259 */ 63, 1, 0,
599 /* 262 */ 64, 1, 0,
600 /* 265 */ 65, 1, 0,
601 /* 268 */ 66, 1, 0,
602 /* 271 */ 67, 1, 0,
603 /* 274 */ 68, 1, 0,
604 /* 277 */ 69, 1, 0,
605 /* 280 */ 70, 1, 0,
606 /* 283 */ 71, 1, 0,
607 /* 286 */ 72, 1, 0,
608 /* 289 */ 73, 1, 0,
609 /* 292 */ 74, 1, 0,
610 /* 295 */ 75, 1, 0,
611 /* 298 */ 76, 1, 0,
612 /* 301 */ 2, 0,
613 /* 303 */ -331, 5, 0,
614 /* 306 */ 15, 12, 0,
615 /* 309 */ -358, 16, 0,
616 /* 312 */ 15, -90, 1, 17, 73, -89, 1, 16, 0,
617 /* 321 */ -90, 1, 17, 0,
618 /* 325 */ 14, -92, 1, 19, 73, -91, 1, 18, 0,
619 /* 334 */ -92, 1, 19, 0,
620 /* 338 */ 13, -94, 1, 21, 73, -93, 1, 20, 0,
621 /* 347 */ -94, 1, 21, 0,
622 /* 351 */ 12, -96, 1, 23, 73, -95, 1, 22, 0,
623 /* 360 */ -96, 1, 23, 0,
624 /* 364 */ 103, -8, 24, 0,
625 /* 368 */ 104, -8, 24, 0,
626 /* 372 */ 11, -98, 1, 25, 73, -97, 1, 24, 0,
627 /* 381 */ 101, -9, 25, 0,
628 /* 385 */ 102, -9, 25, 0,
629 /* 389 */ 103, -9, 25, 0,
630 /* 393 */ -98, 1, 25, 0,
631 /* 397 */ 99, -10, 26, 0,
632 /* 401 */ 100, -10, 26, 0,
633 /* 405 */ 101, -10, 26, 0,
634 /* 409 */ 10, -100, 1, 27, 73, -99, 1, 26, 0,
635 /* 418 */ -366, 27, 0,
636 /* 421 */ 97, -11, 27, 0,
637 /* 425 */ 98, -11, 27, 0,
638 /* 429 */ 99, -11, 27, 0,
639 /* 433 */ -100, 1, 27, 0,
640 /* 437 */ 95, -12, 28, 0,
641 /* 441 */ 96, -12, 28, 0,
642 /* 445 */ 97, -12, 28, 0,
643 /* 449 */ 9, -102, 1, 29, 73, -101, 1, 28, 0,
644 /* 458 */ 93, -13, 29, 0,
645 /* 462 */ 94, -13, 29, 0,
646 /* 466 */ 95, -13, 29, 0,
647 /* 470 */ -102, 1, 29, 0,
648 /* 474 */ 91, -14, 30, 0,
649 /* 478 */ 92, -14, 30, 0,
650 /* 482 */ 93, -14, 30, 0,
651 /* 486 */ 8, -104, 1, 31, 73, -103, 1, 30, 0,
652 /* 495 */ 89, -15, 31, 0,
653 /* 499 */ 90, -15, 31, 0,
654 /* 503 */ 91, -15, 31, 0,
655 /* 507 */ -104, 1, 31, 0,
656 /* 511 */ 88, -16, 32, 0,
657 /* 515 */ 89, -16, 32, 0,
658 /* 519 */ 33, 0,
659 /* 521 */ -105, 1, 48, 0,
660 /* 525 */ -106, 1, 49, 0,
661 /* 529 */ -107, 1, 50, 0,
662 /* 533 */ -108, 1, 51, 0,
663 /* 537 */ -109, 1, 52, 0,
664 /* 541 */ -110, 1, 53, 0,
665 /* 545 */ -111, 1, 54, 0,
666 /* 549 */ -112, 1, 55, 0,
667 /* 553 */ -113, 1, 56, 0,
668 /* 557 */ -114, 1, 57, 0,
669 /* 561 */ -115, 1, 58, 0,
670 /* 565 */ -116, 1, 59, 0,
671 /* 569 */ -117, 1, 60, 0,
672 /* 573 */ -273, 61, 0,
673 /* 576 */ -118, 1, 61, 0,
674 /* 580 */ -331, 62, 0,
675 /* 583 */ -119, 1, 62, 0,
676 /* 587 */ -120, 1, 63, 0,
677 /* 591 */ 64, 0,
678 /* 593 */ 73, 0,
679 /* 595 */ -351, 78, 0,
680 /* 598 */ 89, 0,
681 /* 600 */ 97, 0,
682 /* 602 */ 104, 0,
683 /* 604 */ 116, 0,
684 /* 606 */ -331, 120, 0,
685 /* 609 */ -345, 133, 0,
686 /* 612 */ 140, 0,
687 /* 614 */ 142, 0,
688 /* 616 */ 68, 2, 2, 2, 153, 0,
689 /* 622 */ 200, 0,
690 /* 624 */ 201, 0,
691 /* 626 */ 204, 0,
692 /* 628 */ 205, 0,
693 /* 630 */ 206, 0,
694 /* 632 */ 207, 0,
695 /* 634 */ 208, 0,
696 /* 636 */ 209, 0,
697 /* 638 */ 210, 0,
698 /* 640 */ 211, 0,
699 /* 642 */ 212, 0,
700 /* 644 */ 213, 0,
701 /* 646 */ 214, 0,
702 /* 648 */ 215, 0,
703 /* 650 */ 216, 0,
704 /* 652 */ 217, 0,
705 /* 654 */ 232, 0,
706 /* 656 */ 233, 0,
707 /* 658 */ 251, 0,
708 /* 660 */ 252, 0,
709 /* 662 */ 253, 0,
710 /* 664 */ 260, 0,
711 /* 666 */ 261, 0,
712 /* 668 */ 262, 0,
713 /* 670 */ 263, 0,
714 /* 672 */ 264, 0,
715 /* 674 */ 265, 0,
716 /* 676 */ 266, 0,
717 /* 678 */ 267, 0,
718 /* 680 */ 268, 0,
719 /* 682 */ 269, 0,
720 /* 684 */ 270, 0,
721 /* 686 */ 271, 0,
722 /* 688 */ 273, 0,
723 /* 690 */ 283, 0,
724 /* 692 */ 284, 0,
725 /* 694 */ 303, 0,
726 /* 696 */ 311, 0,
727 /* 698 */ 312, 0,
728 /* 700 */ 314, 0,
729 /* 702 */ 322, 0,
730 /* 704 */ 324, 0,
731 /* 706 */ 326, 0,
732 /* 708 */ 327, 0,
733 /* 710 */ 331, 0,
734 /* 712 */ 332, 0,
735 /* 714 */ 339, 0,
736 /* 716 */ 340, 0,
737 /* 718 */ 342, 0,
738 /* 720 */ 345, 0,
739 /* 722 */ 346, 0,
740 /* 724 */ 347, 0,
741 /* 726 */ 351, 0,
742 /* 728 */ 352, 0,
743 /* 730 */ 353, 0,
744 /* 732 */ 356, 0,
745 /* 734 */ 357, 0,
746 /* 736 */ 358, 0,
747 /* 738 */ 359, 0,
748 /* 740 */ 360, 0,
749 /* 742 */ 366, 0,
750 /* 744 */ 367, 0,
751};
752
753extern const LaneBitmask HexagonLaneMaskLists[] = {
754 /* 0 */ LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000001),
755 /* 2 */ LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000000000002),
756 /* 4 */ LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000002),
757 /* 7 */ LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000002),
758 /* 13 */ LaneBitmask(0x0000000000000020), LaneBitmask(0x0000000000000010), LaneBitmask(0x0000000000000008),
759 /* 16 */ LaneBitmask(0x0000000000000020), LaneBitmask(0x0000000000000010), LaneBitmask(0x0000000000000100), LaneBitmask(0x0000000000000080), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000040),
760 /* 22 */ LaneBitmask(0x0000000000000004), LaneBitmask(0xFFFFFFFFFFFFFFFF),
761 /* 24 */ LaneBitmask(0xFFFFFFFFFFFFFFFF), LaneBitmask(0xFFFFFFFFFFFFFFFF), LaneBitmask(0xFFFFFFFFFFFFFFFF), LaneBitmask(0xFFFFFFFFFFFFFFFF), LaneBitmask(0xFFFFFFFFFFFFFFFF),
762};
763
764extern const uint16_t HexagonSubRegIdxLists[] = {
765 /* 0 */ 2, 1,
766 /* 2 */ 3,
767 /* 3 */ 6, 5, 4,
768 /* 6 */ 8, 6, 5, 4, 7, 11, 10, 9,
769};
770
771
772#ifdef __GNUC__
773#pragma GCC diagnostic push
774#pragma GCC diagnostic ignored "-Woverlength-strings"
775#endif
776extern const char HexagonRegStrings[] = {
777 /* 0 */ "D10\000"
778 /* 4 */ "VF10\000"
779 /* 9 */ "G10\000"
780 /* 13 */ "VFR10\000"
781 /* 19 */ "WR10\000"
782 /* 24 */ "V10\000"
783 /* 28 */ "W10\000"
784 /* 32 */ "C11_10\000"
785 /* 39 */ "G11_10\000"
786 /* 46 */ "S11_10\000"
787 /* 53 */ "VF20\000"
788 /* 58 */ "G20\000"
789 /* 62 */ "VFR20\000"
790 /* 68 */ "S20\000"
791 /* 72 */ "V20\000"
792 /* 76 */ "G21_20\000"
793 /* 83 */ "S21_20\000"
794 /* 90 */ "VF30\000"
795 /* 95 */ "G30\000"
796 /* 99 */ "VFR30\000"
797 /* 105 */ "V30\000"
798 /* 109 */ "G31_30\000"
799 /* 116 */ "S31_30\000"
800 /* 123 */ "S41_40\000"
801 /* 130 */ "S51_50\000"
802 /* 137 */ "S60\000"
803 /* 141 */ "S61_60\000"
804 /* 148 */ "S70\000"
805 /* 152 */ "S71_70\000"
806 /* 159 */ "S80\000"
807 /* 163 */ "SA0\000"
808 /* 167 */ "BADVA0\000"
809 /* 174 */ "LC0\000"
810 /* 178 */ "BRKPTPC0\000"
811 /* 187 */ "D0\000"
812 /* 190 */ "VF0\000"
813 /* 194 */ "ISDBCFG0\000"
814 /* 203 */ "BRKPTCFG0\000"
815 /* 213 */ "M0\000"
816 /* 216 */ "SGP0\000"
817 /* 221 */ "VQ0\000"
818 /* 225 */ "VFR0\000"
819 /* 230 */ "WR0\000"
820 /* 234 */ "CS0\000"
821 /* 238 */ "GPMUCNT0\000"
822 /* 247 */ "V0\000"
823 /* 250 */ "W0\000"
824 /* 253 */ "C1_0\000"
825 /* 258 */ "G1_0\000"
826 /* 263 */ "SGP1_0\000"
827 /* 270 */ "P3_0\000"
828 /* 275 */ "D11\000"
829 /* 279 */ "VF11\000"
830 /* 284 */ "G11\000"
831 /* 288 */ "VFR11\000"
832 /* 294 */ "WR11\000"
833 /* 299 */ "S11\000"
834 /* 303 */ "V11\000"
835 /* 307 */ "W11\000"
836 /* 311 */ "VF21\000"
837 /* 316 */ "G21\000"
838 /* 320 */ "VFR21\000"
839 /* 326 */ "V21\000"
840 /* 330 */ "VF31\000"
841 /* 335 */ "G31\000"
842 /* 339 */ "VFR31\000"
843 /* 345 */ "V31\000"
844 /* 349 */ "S61\000"
845 /* 353 */ "S71\000"
846 /* 357 */ "SA1\000"
847 /* 361 */ "BADVA1\000"
848 /* 368 */ "LC1\000"
849 /* 372 */ "BRKPTPC1\000"
850 /* 381 */ "D1\000"
851 /* 384 */ "VF1\000"
852 /* 388 */ "ISDBCFG1\000"
853 /* 397 */ "BRKPTCFG1\000"
854 /* 407 */ "M1\000"
855 /* 410 */ "SGP1\000"
856 /* 415 */ "VQ1\000"
857 /* 419 */ "VFR1\000"
858 /* 424 */ "WR1\000"
859 /* 428 */ "CS1\000"
860 /* 432 */ "GPMUCNT1\000"
861 /* 441 */ "V1\000"
862 /* 444 */ "W1\000"
863 /* 447 */ "D12\000"
864 /* 451 */ "VF12\000"
865 /* 456 */ "G12\000"
866 /* 460 */ "VFR12\000"
867 /* 466 */ "WR12\000"
868 /* 471 */ "S12\000"
869 /* 475 */ "V12\000"
870 /* 479 */ "W12\000"
871 /* 483 */ "G13_12\000"
872 /* 490 */ "S13_12\000"
873 /* 497 */ "VF22\000"
874 /* 502 */ "G22\000"
875 /* 506 */ "VFR22\000"
876 /* 512 */ "S22\000"
877 /* 516 */ "V22\000"
878 /* 520 */ "G23_22\000"
879 /* 527 */ "S23_22\000"
880 /* 534 */ "S33_32\000"
881 /* 541 */ "S43_42\000"
882 /* 548 */ "S53_52\000"
883 /* 555 */ "S62\000"
884 /* 559 */ "S63_62\000"
885 /* 566 */ "S72\000"
886 /* 570 */ "S73_72\000"
887 /* 577 */ "D2\000"
888 /* 580 */ "VF2\000"
889 /* 584 */ "P2\000"
890 /* 587 */ "VQ2\000"
891 /* 591 */ "VFR2\000"
892 /* 596 */ "WR2\000"
893 /* 600 */ "GPMUCNT2\000"
894 /* 609 */ "V2\000"
895 /* 612 */ "W2\000"
896 /* 615 */ "C3_2\000"
897 /* 620 */ "G3_2\000"
898 /* 625 */ "S3_2\000"
899 /* 630 */ "D13\000"
900 /* 634 */ "VF13\000"
901 /* 639 */ "G13\000"
902 /* 643 */ "VFR13\000"
903 /* 649 */ "WR13\000"
904 /* 654 */ "S13\000"
905 /* 658 */ "V13\000"
906 /* 662 */ "W13\000"
907 /* 666 */ "VF23\000"
908 /* 671 */ "G23\000"
909 /* 675 */ "VFR23\000"
910 /* 681 */ "S23\000"
911 /* 685 */ "V23\000"
912 /* 689 */ "S63\000"
913 /* 693 */ "S73\000"
914 /* 697 */ "D3\000"
915 /* 700 */ "VF3\000"
916 /* 704 */ "G3\000"
917 /* 707 */ "P3\000"
918 /* 710 */ "VQ3\000"
919 /* 714 */ "VFR3\000"
920 /* 719 */ "WR3\000"
921 /* 723 */ "GPMUCNT3\000"
922 /* 732 */ "V3\000"
923 /* 735 */ "W3\000"
924 /* 738 */ "D14\000"
925 /* 742 */ "VF14\000"
926 /* 747 */ "G14\000"
927 /* 751 */ "VFR14\000"
928 /* 757 */ "WR14\000"
929 /* 762 */ "S14\000"
930 /* 766 */ "V14\000"
931 /* 770 */ "W14\000"
932 /* 774 */ "G15_14\000"
933 /* 781 */ "S15_14\000"
934 /* 788 */ "VF24\000"
935 /* 793 */ "VFR24\000"
936 /* 799 */ "S24\000"
937 /* 803 */ "V24\000"
938 /* 807 */ "G25_24\000"
939 /* 814 */ "S25_24\000"
940 /* 821 */ "S35_34\000"
941 /* 828 */ "S44\000"
942 /* 832 */ "S45_44\000"
943 /* 839 */ "S54\000"
944 /* 843 */ "S55_54\000"
945 /* 850 */ "S64\000"
946 /* 854 */ "S65_64\000"
947 /* 861 */ "S74\000"
948 /* 865 */ "S75_74\000"
949 /* 872 */ "D4\000"
950 /* 875 */ "VF4\000"
951 /* 879 */ "G4\000"
952 /* 882 */ "VQ4\000"
953 /* 886 */ "VFR4\000"
954 /* 891 */ "WR4\000"
955 /* 895 */ "GPMUCNT4\000"
956 /* 904 */ "V4\000"
957 /* 907 */ "W4\000"
958 /* 910 */ "C5_4\000"
959 /* 915 */ "G5_4\000"
960 /* 920 */ "S5_4\000"
961 /* 925 */ "D15\000"
962 /* 929 */ "VF15\000"
963 /* 934 */ "G15\000"
964 /* 938 */ "VFR15\000"
965 /* 944 */ "WR15\000"
966 /* 949 */ "S15\000"
967 /* 953 */ "V15\000"
968 /* 957 */ "W15\000"
969 /* 961 */ "VF25\000"
970 /* 966 */ "VFR25\000"
971 /* 972 */ "S25\000"
972 /* 976 */ "V25\000"
973 /* 980 */ "S35\000"
974 /* 984 */ "S45\000"
975 /* 988 */ "S55\000"
976 /* 992 */ "S65\000"
977 /* 996 */ "S75\000"
978 /* 1000 */ "C5\000"
979 /* 1003 */ "D5\000"
980 /* 1006 */ "VF5\000"
981 /* 1010 */ "G5\000"
982 /* 1013 */ "VQ5\000"
983 /* 1017 */ "VFR5\000"
984 /* 1022 */ "WR5\000"
985 /* 1026 */ "GPMUCNT5\000"
986 /* 1035 */ "V5\000"
987 /* 1038 */ "W5\000"
988 /* 1041 */ "VF16\000"
989 /* 1046 */ "VFR16\000"
990 /* 1052 */ "V16\000"
991 /* 1056 */ "C17_16\000"
992 /* 1063 */ "G17_16\000"
993 /* 1070 */ "S17_16\000"
994 /* 1077 */ "VF26\000"
995 /* 1082 */ "VFR26\000"
996 /* 1088 */ "S26\000"
997 /* 1092 */ "V26\000"
998 /* 1096 */ "G27_26\000"
999 /* 1103 */ "S27_26\000"
1000 /* 1110 */ "S37_36\000"
1001 /* 1117 */ "S46\000"
1002 /* 1121 */ "S47_46\000"
1003 /* 1128 */ "S56\000"
1004 /* 1132 */ "S57_56\000"
1005 /* 1139 */ "S66\000"
1006 /* 1143 */ "S67_66\000"
1007 /* 1150 */ "S76\000"
1008 /* 1154 */ "S77_76\000"
1009 /* 1161 */ "D6\000"
1010 /* 1164 */ "VF6\000"
1011 /* 1168 */ "G6\000"
1012 /* 1171 */ "VQ6\000"
1013 /* 1175 */ "VFR6\000"
1014 /* 1180 */ "WR6\000"
1015 /* 1184 */ "GPMUCNT6\000"
1016 /* 1193 */ "V6\000"
1017 /* 1196 */ "W6\000"
1018 /* 1199 */ "C7_6\000"
1019 /* 1204 */ "G7_6\000"
1020 /* 1209 */ "S7_6\000"
1021 /* 1214 */ "VF17\000"
1022 /* 1219 */ "VFR17\000"
1023 /* 1225 */ "V17\000"
1024 /* 1229 */ "VF27\000"
1025 /* 1234 */ "VFR27\000"
1026 /* 1240 */ "V27\000"
1027 /* 1244 */ "S47\000"
1028 /* 1248 */ "S57\000"
1029 /* 1252 */ "S67\000"
1030 /* 1256 */ "S77\000"
1031 /* 1260 */ "D7\000"
1032 /* 1263 */ "VF7\000"
1033 /* 1267 */ "G7\000"
1034 /* 1270 */ "VQ7\000"
1035 /* 1274 */ "VFR7\000"
1036 /* 1279 */ "WR7\000"
1037 /* 1283 */ "GPMUCNT7\000"
1038 /* 1292 */ "V7\000"
1039 /* 1295 */ "W7\000"
1040 /* 1298 */ "VF18\000"
1041 /* 1303 */ "VFR18\000"
1042 /* 1309 */ "V18\000"
1043 /* 1313 */ "G19_18\000"
1044 /* 1320 */ "S19_18\000"
1045 /* 1327 */ "VF28\000"
1046 /* 1332 */ "VFR28\000"
1047 /* 1338 */ "V28\000"
1048 /* 1342 */ "G29_28\000"
1049 /* 1349 */ "S29_28\000"
1050 /* 1356 */ "S39_38\000"
1051 /* 1363 */ "S49_48\000"
1052 /* 1370 */ "S58\000"
1053 /* 1374 */ "S59_58\000"
1054 /* 1381 */ "S68\000"
1055 /* 1385 */ "S69_68\000"
1056 /* 1392 */ "S78\000"
1057 /* 1396 */ "S79_78\000"
1058 /* 1403 */ "C8\000"
1059 /* 1406 */ "D8\000"
1060 /* 1409 */ "VF8\000"
1061 /* 1413 */ "G8\000"
1062 /* 1416 */ "VFR8\000"
1063 /* 1421 */ "WR8\000"
1064 /* 1425 */ "V8\000"
1065 /* 1428 */ "W8\000"
1066 /* 1431 */ "C9_8\000"
1067 /* 1436 */ "G9_8\000"
1068 /* 1441 */ "S9_8\000"
1069 /* 1446 */ "VF19\000"
1070 /* 1451 */ "VFR19\000"
1071 /* 1457 */ "S19\000"
1072 /* 1461 */ "V19\000"
1073 /* 1465 */ "VF29\000"
1074 /* 1470 */ "VFR29\000"
1075 /* 1476 */ "V29\000"
1076 /* 1480 */ "S59\000"
1077 /* 1484 */ "S69\000"
1078 /* 1488 */ "S79\000"
1079 /* 1492 */ "D9\000"
1080 /* 1495 */ "VF9\000"
1081 /* 1499 */ "G9\000"
1082 /* 1502 */ "VFR9\000"
1083 /* 1507 */ "WR9\000"
1084 /* 1511 */ "V9\000"
1085 /* 1514 */ "W9\000"
1086 /* 1517 */ "BADVA\000"
1087 /* 1523 */ "EVB\000"
1088 /* 1527 */ "PC\000"
1089 /* 1530 */ "HTID\000"
1090 /* 1535 */ "STID\000"
1091 /* 1540 */ "VID\000"
1092 /* 1544 */ "UPCYCLE\000"
1093 /* 1552 */ "CFGBASE\000"
1094 /* 1560 */ "USR_OVF\000"
1095 /* 1568 */ "DIAG\000"
1096 /* 1573 */ "SYSCFG\000"
1097 /* 1580 */ "PMUEVTCFG\000"
1098 /* 1590 */ "PMUCFG\000"
1099 /* 1597 */ "GPCYCLEHI\000"
1100 /* 1607 */ "UPCYCLEHI\000"
1101 /* 1617 */ "UTIMERHI\000"
1102 /* 1626 */ "PKTCOUNTHI\000"
1103 /* 1637 */ "IMASK\000"
1104 /* 1643 */ "MODECTL\000"
1105 /* 1651 */ "ISDBEN\000"
1106 /* 1658 */ "ISDBMBXIN\000"
1107 /* 1668 */ "GPCYCLELO\000"
1108 /* 1678 */ "UPCYCLELO\000"
1109 /* 1688 */ "UTIMERLO\000"
1110 /* 1697 */ "PKTCOUNTLO\000"
1111 /* 1708 */ "UGP\000"
1112 /* 1712 */ "VTMP\000"
1113 /* 1717 */ "GOSP\000"
1114 /* 1722 */ "CCR\000"
1115 /* 1726 */ "UTIMER\000"
1116 /* 1733 */ "GELR\000"
1117 /* 1738 */ "ISDBGPR\000"
1118 /* 1746 */ "GSR\000"
1119 /* 1750 */ "SSR\000"
1120 /* 1754 */ "USR\000"
1121 /* 1758 */ "CS\000"
1122 /* 1761 */ "FRAMELIMIT\000"
1123 /* 1772 */ "PKTCOUNT\000"
1124 /* 1781 */ "ISDBST\000"
1125 /* 1788 */ "ISDBMBXOUT\000"
1126 /* 1799 */ "REV\000"
1127 /* 1803 */ "FRAMEKEY\000"
1128};
1129#ifdef __GNUC__
1130#pragma GCC diagnostic pop
1131#endif
1132
1133extern const MCRegisterDesc HexagonRegDesc[] = { // Descriptors
1134 { 3, 0, 0, 0, 0, 0, 0, 0 },
1135 { 1517, 2, 740, 2, 8192, 23, 0, 0 },
1136 { 1722, 2, 736, 2, 8193, 23, 0, 0 },
1137 { 1552, 2, 744, 2, 8194, 23, 0, 0 },
1138 { 1758, 250, 2, 0, 487427, 0, 0, 0 },
1139 { 1568, 2, 742, 2, 8197, 23, 0, 0 },
1140 { 1734, 2, 728, 2, 8198, 23, 0, 0 },
1141 { 1523, 2, 736, 2, 8199, 23, 0, 0 },
1142 { 1803, 2, 712, 2, 8200, 23, 0, 0 },
1143 { 1761, 2, 710, 2, 8201, 23, 0, 0 },
1144 { 1733, 2, 710, 2, 8202, 23, 0, 0 },
1145 { 1717, 2, 710, 2, 8203, 23, 0, 0 },
1146 { 1709, 2, 708, 2, 8204, 23, 0, 0 },
1147 { 1597, 2, 716, 2, 8205, 23, 0, 0 },
1148 { 1668, 2, 714, 2, 8206, 23, 0, 0 },
1149 { 1746, 2, 706, 2, 8207, 23, 0, 0 },
1150 { 1530, 2, 720, 2, 8208, 23, 0, 0 },
1151 { 1637, 2, 720, 2, 8209, 23, 0, 0 },
1152 { 1651, 2, 740, 2, 8210, 23, 0, 0 },
1153 { 1738, 2, 738, 2, 8211, 23, 0, 0 },
1154 { 1658, 2, 734, 2, 8212, 23, 0, 0 },
1155 { 1788, 2, 732, 2, 8213, 23, 0, 0 },
1156 { 1781, 2, 726, 2, 8214, 23, 0, 0 },
1157 { 1643, 2, 718, 2, 8215, 23, 0, 0 },
1158 { 1527, 2, 700, 2, 8216, 23, 0, 0 },
1159 { 1598, 2, 724, 2, 8217, 23, 0, 0 },
1160 { 1669, 2, 722, 2, 8218, 23, 0, 0 },
1161 { 1772, 115, 2, 0, 487451, 0, 0, 0 },
1162 { 1626, 2, 98, 2, 8220, 23, 0, 0 },
1163 { 1697, 2, 95, 2, 8219, 23, 0, 0 },
1164 { 1590, 2, 730, 2, 8221, 23, 0, 0 },
1165 { 1580, 2, 728, 2, 8222, 23, 0, 0 },
1166 { 1799, 2, 714, 2, 8223, 23, 0, 0 },
1167 { 1750, 2, 708, 2, 8224, 23, 0, 0 },
1168 { 1535, 2, 704, 2, 8225, 23, 0, 0 },
1169 { 1573, 2, 710, 2, 8226, 23, 0, 0 },
1170 { 1708, 2, 694, 2, 8227, 23, 0, 0 },
1171 { 1544, 115, 2, 0, 487460, 0, 0, 0 },
1172 { 1607, 2, 98, 2, 8229, 23, 0, 0 },
1173 { 1678, 2, 95, 2, 8228, 23, 0, 0 },
1174 { 1754, 119, 2, 2, 487462, 22, 0, 0 },
1175 { 1560, 2, 98, 2, 8230, 23, 0, 0 },
1176 { 1726, 115, 2, 0, 487464, 0, 0, 0 },
1177 { 1617, 2, 98, 2, 8233, 23, 0, 0 },
1178 { 1688, 2, 95, 2, 8232, 23, 0, 0 },
1179 { 1540, 2, 702, 2, 8234, 23, 0, 0 },
1180 { 1712, 2, 2, 2, 8235, 23, 0, 0 },
1181 { 167, 2, 698, 2, 8236, 23, 0, 0 },
1182 { 361, 2, 696, 2, 8237, 23, 0, 0 },
1183 { 203, 2, 706, 2, 8238, 23, 0, 0 },
1184 { 397, 2, 706, 2, 8239, 23, 0, 0 },
1185 { 178, 2, 704, 2, 8240, 23, 0, 0 },
1186 { 372, 2, 704, 2, 8241, 23, 0, 0 },
1187 { 1000, 2, 690, 2, 8242, 23, 0, 0 },
1188 { 1403, 2, 692, 2, 1257511, 27, 0, 0 },
1189 { 234, 2, 48, 2, 8195, 23, 0, 0 },
1190 { 428, 2, 46, 2, 8196, 23, 0, 0 },
1191 { 187, 253, 2, 0, 487476, 0, 0, 0 },
1192 { 381, 256, 2, 0, 487478, 0, 0, 0 },
1193 { 577, 259, 2, 0, 487480, 0, 0, 0 },
1194 { 697, 262, 2, 0, 487482, 0, 0, 0 },
1195 { 872, 265, 2, 0, 487484, 0, 0, 0 },
1196 { 1003, 268, 2, 0, 487486, 0, 0, 0 },
1197 { 1161, 271, 2, 0, 487488, 0, 0, 0 },
1198 { 1260, 274, 2, 0, 487490, 0, 0, 0 },
1199 { 1406, 277, 2, 0, 487492, 0, 0, 0 },
1200 { 1492, 280, 2, 0, 487494, 0, 0, 0 },
1201 { 0, 283, 2, 0, 487496, 0, 0, 0 },
1202 { 275, 286, 2, 0, 487498, 0, 0, 0 },
1203 { 447, 289, 2, 0, 487500, 0, 0, 0 },
1204 { 630, 292, 2, 0, 487502, 0, 0, 0 },
1205 { 738, 295, 2, 0, 487504, 0, 0, 0 },
1206 { 925, 298, 2, 0, 487506, 0, 0, 0 },
1207 { 704, 2, 682, 2, 8276, 23, 0, 0 },
1208 { 879, 2, 682, 2, 8277, 23, 0, 0 },
1209 { 1010, 2, 680, 2, 8278, 23, 0, 0 },
1210 { 1168, 2, 680, 2, 8279, 23, 0, 0 },
1211 { 1267, 2, 678, 2, 8280, 23, 0, 0 },
1212 { 1413, 2, 678, 2, 8281, 23, 0, 0 },
1213 { 1499, 2, 676, 2, 8282, 23, 0, 0 },
1214 { 9, 2, 676, 2, 8283, 23, 0, 0 },
1215 { 284, 2, 674, 2, 8284, 23, 0, 0 },
1216 { 456, 2, 674, 2, 8285, 23, 0, 0 },
1217 { 639, 2, 672, 2, 8286, 23, 0, 0 },
1218 { 747, 2, 672, 2, 8287, 23, 0, 0 },
1219 { 934, 2, 670, 2, 8288, 23, 0, 0 },
1220 { 58, 2, 674, 2, 8289, 23, 0, 0 },
1221 { 316, 2, 672, 2, 8290, 23, 0, 0 },
1222 { 502, 2, 672, 2, 8291, 23, 0, 0 },
1223 { 671, 2, 670, 2, 8292, 23, 0, 0 },
1224 { 95, 2, 676, 2, 8293, 23, 0, 0 },
1225 { 335, 2, 674, 2, 8294, 23, 0, 0 },
1226 { 238, 2, 668, 2, 8295, 23, 0, 0 },
1227 { 432, 2, 666, 2, 8296, 23, 0, 0 },
1228 { 600, 2, 666, 2, 8297, 23, 0, 0 },
1229 { 723, 2, 664, 2, 8298, 23, 0, 0 },
1230 { 895, 2, 662, 2, 8299, 23, 0, 0 },
1231 { 1026, 2, 660, 2, 8300, 23, 0, 0 },
1232 { 1184, 2, 660, 2, 8301, 23, 0, 0 },
1233 { 1283, 2, 658, 2, 8302, 23, 0, 0 },
1234 { 194, 2, 688, 2, 8303, 23, 0, 0 },
1235 { 388, 2, 688, 2, 8304, 23, 0, 0 },
1236 { 174, 2, 654, 2, 8305, 23, 0, 0 },
1237 { 368, 2, 654, 2, 8306, 23, 0, 0 },
1238 { 213, 2, 656, 2, 8307, 23, 0, 0 },
1239 { 407, 2, 654, 2, 8308, 23, 0, 0 },
1240 { 218, 2, 2, 2, 487541, 27, 0, 0 },
1241 { 412, 2, 2, 2, 487543, 27, 0, 0 },
1242 { 584, 2, 2, 2, 487545, 27, 0, 0 },
1243 { 707, 2, 2, 2, 487547, 27, 0, 0 },
1244 { 239, 2, 686, 2, 8317, 23, 0, 0 },
1245 { 433, 2, 684, 2, 8318, 23, 0, 0 },
1246 { 601, 2, 684, 2, 8319, 23, 0, 0 },
1247 { 724, 2, 682, 2, 8320, 23, 0, 0 },
1248 { 222, 2, 2, 2, 8321, 23, 0, 0 },
1249 { 416, 2, 2, 2, 8322, 23, 0, 0 },
1250 { 588, 2, 2, 2, 8323, 23, 0, 0 },
1251 { 711, 2, 2, 2, 8324, 23, 0, 0 },
1252 { 227, 2, 44, 2, 8244, 23, 0, 0 },
1253 { 421, 2, 42, 2, 8245, 23, 0, 0 },
1254 { 593, 2, 42, 2, 8246, 23, 0, 0 },
1255 { 716, 2, 40, 2, 8247, 23, 0, 0 },
1256 { 888, 2, 40, 2, 8248, 23, 0, 0 },
1257 { 1019, 2, 38, 2, 8249, 23, 0, 0 },
1258 { 1177, 2, 38, 2, 8250, 23, 0, 0 },
1259 { 1276, 2, 36, 2, 8251, 23, 0, 0 },
1260 { 1418, 2, 36, 2, 8252, 23, 0, 0 },
1261 { 1504, 2, 34, 2, 8253, 23, 0, 0 },
1262 { 15, 2, 34, 2, 8254, 23, 0, 0 },
1263 { 290, 2, 32, 2, 8255, 23, 0, 0 },
1264 { 462, 2, 32, 2, 8256, 23, 0, 0 },
1265 { 645, 2, 30, 2, 8257, 23, 0, 0 },
1266 { 753, 2, 30, 2, 8258, 23, 0, 0 },
1267 { 940, 2, 28, 2, 8259, 23, 0, 0 },
1268 { 1048, 2, 28, 2, 8260, 23, 0, 0 },
1269 { 1221, 2, 26, 2, 8261, 23, 0, 0 },
1270 { 1305, 2, 26, 2, 8262, 23, 0, 0 },
1271 { 1453, 2, 24, 2, 8263, 23, 0, 0 },
1272 { 64, 2, 24, 2, 8264, 23, 0, 0 },
1273 { 322, 2, 22, 2, 8265, 23, 0, 0 },
1274 { 508, 2, 22, 2, 8266, 23, 0, 0 },
1275 { 677, 2, 20, 2, 8267, 23, 0, 0 },
1276 { 795, 2, 20, 2, 8268, 23, 0, 0 },
1277 { 968, 2, 18, 2, 8269, 23, 0, 0 },
1278 { 1084, 2, 18, 2, 8270, 23, 0, 0 },
1279 { 1236, 2, 16, 2, 8271, 23, 0, 0 },
1280 { 1334, 2, 16, 2, 8272, 23, 0, 0 },
1281 { 1472, 2, 14, 2, 8273, 23, 0, 0 },
1282 { 101, 2, 14, 2, 8274, 23, 0, 0 },
1283 { 341, 2, 12, 2, 8275, 23, 0, 0 },
1284 { 299, 2, 642, 2, 8325, 23, 0, 0 },
1285 { 471, 2, 642, 2, 8326, 23, 0, 0 },
1286 { 654, 2, 640, 2, 8327, 23, 0, 0 },
1287 { 762, 2, 640, 2, 8328, 23, 0, 0 },
1288 { 949, 2, 638, 2, 8329, 23, 0, 0 },
1289 { 1457, 2, 640, 2, 8330, 23, 0, 0 },
1290 { 68, 2, 640, 2, 8331, 23, 0, 0 },
1291 { 512, 2, 640, 2, 8332, 23, 0, 0 },
1292 { 681, 2, 638, 2, 8333, 23, 0, 0 },
1293 { 799, 2, 638, 2, 8334, 23, 0, 0 },
1294 { 972, 2, 636, 2, 8335, 23, 0, 0 },
1295 { 1088, 2, 636, 2, 8336, 23, 0, 0 },
1296 { 980, 2, 642, 2, 8337, 23, 0, 0 },
1297 { 828, 2, 650, 2, 8338, 23, 0, 0 },
1298 { 984, 2, 648, 2, 8339, 23, 0, 0 },
1299 { 1117, 2, 648, 2, 8340, 23, 0, 0 },
1300 { 1244, 2, 646, 2, 8341, 23, 0, 0 },
1301 { 839, 2, 652, 2, 8342, 23, 0, 0 },
1302 { 988, 2, 650, 2, 8343, 23, 0, 0 },
1303 { 1128, 2, 650, 2, 8344, 23, 0, 0 },
1304 { 1248, 2, 648, 2, 8345, 23, 0, 0 },
1305 { 1370, 2, 648, 2, 8346, 23, 0, 0 },
1306 { 1480, 2, 646, 2, 8347, 23, 0, 0 },
1307 { 137, 2, 646, 2, 8348, 23, 0, 0 },
1308 { 349, 2, 644, 2, 8349, 23, 0, 0 },
1309 { 555, 2, 644, 2, 8350, 23, 0, 0 },
1310 { 689, 2, 642, 2, 8351, 23, 0, 0 },
1311 { 850, 2, 642, 2, 8352, 23, 0, 0 },
1312 { 992, 2, 640, 2, 8353, 23, 0, 0 },
1313 { 1139, 2, 640, 2, 8354, 23, 0, 0 },
1314 { 1252, 2, 638, 2, 8355, 23, 0, 0 },
1315 { 1381, 2, 638, 2, 8356, 23, 0, 0 },
1316 { 1484, 2, 636, 2, 8357, 23, 0, 0 },
1317 { 148, 2, 636, 2, 8358, 23, 0, 0 },
1318 { 353, 2, 634, 2, 8359, 23, 0, 0 },
1319 { 566, 2, 634, 2, 8360, 23, 0, 0 },
1320 { 693, 2, 632, 2, 8361, 23, 0, 0 },
1321 { 861, 2, 632, 2, 8362, 23, 0, 0 },
1322 { 996, 2, 630, 2, 8363, 23, 0, 0 },
1323 { 1150, 2, 630, 2, 8364, 23, 0, 0 },
1324 { 1256, 2, 628, 2, 8365, 23, 0, 0 },
1325 { 1392, 2, 628, 2, 8366, 23, 0, 0 },
1326 { 1488, 2, 626, 2, 8367, 23, 0, 0 },
1327 { 159, 2, 2, 2, 8368, 23, 0, 0 },
1328 { 163, 2, 612, 2, 8369, 23, 0, 0 },
1329 { 357, 2, 612, 2, 8370, 23, 0, 0 },
1330 { 216, 2, 624, 2, 8371, 23, 0, 0 },
1331 { 410, 2, 622, 2, 8372, 23, 0, 0 },
1332 { 247, 2, 368, 2, 8373, 23, 0, 0 },
1333 { 441, 2, 364, 2, 8374, 23, 0, 0 },
1334 { 609, 2, 389, 2, 8375, 23, 0, 0 },
1335 { 732, 2, 385, 2, 8376, 23, 0, 0 },
1336 { 904, 2, 385, 2, 8377, 23, 0, 0 },
1337 { 1035, 2, 381, 2, 8378, 23, 0, 0 },
1338 { 1193, 2, 405, 2, 8379, 23, 0, 0 },
1339 { 1292, 2, 401, 2, 8380, 23, 0, 0 },
1340 { 1425, 2, 401, 2, 8381, 23, 0, 0 },
1341 { 1511, 2, 397, 2, 8382, 23, 0, 0 },
1342 { 24, 2, 429, 2, 8383, 23, 0, 0 },
1343 { 303, 2, 425, 2, 8384, 23, 0, 0 },
1344 { 475, 2, 425, 2, 8385, 23, 0, 0 },
1345 { 658, 2, 421, 2, 8386, 23, 0, 0 },
1346 { 766, 2, 445, 2, 8387, 23, 0, 0 },
1347 { 953, 2, 441, 2, 8388, 23, 0, 0 },
1348 { 1052, 2, 441, 2, 8389, 23, 0, 0 },
1349 { 1225, 2, 437, 2, 8390, 23, 0, 0 },
1350 { 1309, 2, 466, 2, 8391, 23, 0, 0 },
1351 { 1461, 2, 462, 2, 8392, 23, 0, 0 },
1352 { 72, 2, 462, 2, 8393, 23, 0, 0 },
1353 { 326, 2, 458, 2, 8394, 23, 0, 0 },
1354 { 516, 2, 482, 2, 8395, 23, 0, 0 },
1355 { 685, 2, 478, 2, 8396, 23, 0, 0 },
1356 { 803, 2, 478, 2, 8397, 23, 0, 0 },
1357 { 976, 2, 474, 2, 8398, 23, 0, 0 },
1358 { 1092, 2, 503, 2, 8399, 23, 0, 0 },
1359 { 1240, 2, 499, 2, 8400, 23, 0, 0 },
1360 { 1338, 2, 499, 2, 8401, 23, 0, 0 },
1361 { 1476, 2, 495, 2, 8402, 23, 0, 0 },
1362 { 105, 2, 515, 2, 8403, 23, 0, 0 },
1363 { 345, 2, 511, 2, 8404, 23, 0, 0 },
1364 { 190, 2, 91, 2, 8405, 23, 0, 1 },
1365 { 384, 2, 88, 2, 8406, 23, 0, 1 },
1366 { 580, 2, 88, 2, 8407, 23, 0, 1 },
1367 { 700, 2, 85, 2, 8408, 23, 0, 1 },
1368 { 875, 2, 85, 2, 8409, 23, 0, 1 },
1369 { 1006, 2, 82, 2, 8410, 23, 0, 1 },
1370 { 1164, 2, 82, 2, 8411, 23, 0, 1 },
1371 { 1263, 2, 79, 2, 8412, 23, 0, 1 },
1372 { 1409, 2, 79, 2, 8413, 23, 0, 1 },
1373 { 1495, 2, 76, 2, 8414, 23, 0, 1 },
1374 { 4, 2, 76, 2, 8415, 23, 0, 1 },
1375 { 279, 2, 73, 2, 8416, 23, 0, 1 },
1376 { 451, 2, 73, 2, 8417, 23, 0, 1 },
1377 { 634, 2, 70, 2, 8418, 23, 0, 1 },
1378 { 742, 2, 70, 2, 8419, 23, 0, 1 },
1379 { 929, 2, 64, 2, 8420, 23, 0, 1 },
1380 { 1041, 2, 2, 2, 8421, 23, 0, 1 },
1381 { 1214, 2, 2, 2, 8422, 23, 0, 1 },
1382 { 1298, 2, 2, 2, 8423, 23, 0, 1 },
1383 { 1446, 2, 2, 2, 8424, 23, 0, 1 },
1384 { 53, 2, 2, 2, 8425, 23, 0, 1 },
1385 { 311, 2, 2, 2, 8426, 23, 0, 1 },
1386 { 497, 2, 2, 2, 8427, 23, 0, 1 },
1387 { 666, 2, 2, 2, 8428, 23, 0, 1 },
1388 { 788, 2, 2, 2, 8429, 23, 0, 1 },
1389 { 961, 2, 2, 2, 8430, 23, 0, 1 },
1390 { 1077, 2, 2, 2, 8431, 23, 0, 1 },
1391 { 1229, 2, 2, 2, 8432, 23, 0, 1 },
1392 { 1327, 2, 2, 2, 8433, 23, 0, 1 },
1393 { 1465, 2, 2, 2, 8434, 23, 0, 1 },
1394 { 90, 2, 2, 2, 8435, 23, 0, 1 },
1395 { 330, 2, 2, 2, 8436, 23, 0, 1 },
1396 { 225, 2, 555, 2, 8437, 23, 0, 1 },
1397 { 419, 2, 555, 2, 8438, 23, 0, 1 },
1398 { 591, 2, 555, 2, 8439, 23, 0, 1 },
1399 { 714, 2, 555, 2, 8440, 23, 0, 1 },
1400 { 886, 2, 555, 2, 8441, 23, 0, 1 },
1401 { 1017, 2, 555, 2, 8442, 23, 0, 1 },
1402 { 1175, 2, 555, 2, 8443, 23, 0, 1 },
1403 { 1274, 2, 555, 2, 8444, 23, 0, 1 },
1404 { 1416, 2, 555, 2, 8445, 23, 0, 1 },
1405 { 1502, 2, 555, 2, 8446, 23, 0, 1 },
1406 { 13, 2, 555, 2, 8447, 23, 0, 1 },
1407 { 288, 2, 555, 2, 8448, 23, 0, 1 },
1408 { 460, 2, 555, 2, 8449, 23, 0, 1 },
1409 { 643, 2, 555, 2, 8450, 23, 0, 1 },
1410 { 751, 2, 555, 2, 8451, 23, 0, 1 },
1411 { 938, 2, 555, 2, 8452, 23, 0, 1 },
1412 { 1046, 2, 2, 2, 8453, 23, 0, 1 },
1413 { 1219, 2, 2, 2, 8454, 23, 0, 1 },
1414 { 1303, 2, 2, 2, 8455, 23, 0, 1 },
1415 { 1451, 2, 2, 2, 8456, 23, 0, 1 },
1416 { 62, 2, 2, 2, 8457, 23, 0, 1 },
1417 { 320, 2, 2, 2, 8458, 23, 0, 1 },
1418 { 506, 2, 2, 2, 8459, 23, 0, 1 },
1419 { 675, 2, 2, 2, 8460, 23, 0, 1 },
1420 { 793, 2, 2, 2, 8461, 23, 0, 1 },
1421 { 966, 2, 2, 2, 8462, 23, 0, 1 },
1422 { 1082, 2, 2, 2, 8463, 23, 0, 1 },
1423 { 1234, 2, 2, 2, 8464, 23, 0, 1 },
1424 { 1332, 2, 2, 2, 8465, 23, 0, 1 },
1425 { 1470, 2, 2, 2, 8466, 23, 0, 1 },
1426 { 99, 2, 2, 2, 8467, 23, 0, 1 },
1427 { 339, 2, 2, 2, 8468, 23, 0, 1 },
1428 { 221, 486, 2, 6, 999605, 16, 0, 0 },
1429 { 415, 449, 2, 6, 975033, 16, 0, 0 },
1430 { 587, 409, 2, 6, 950461, 16, 0, 0 },
1431 { 710, 372, 2, 6, 925889, 16, 0, 0 },
1432 { 882, 351, 2, 6, 901317, 16, 0, 0 },
1433 { 1013, 338, 2, 6, 876745, 16, 0, 0 },
1434 { 1171, 325, 2, 6, 852173, 16, 0, 0 },
1435 { 1270, 312, 2, 6, 827601, 16, 0, 0 },
1436 { 250, 507, 92, 3, 2080949, 13, 0, 0 },
1437 { 444, 491, 89, 3, 2015415, 13, 0, 0 },
1438 { 612, 470, 89, 3, 1929401, 13, 0, 0 },
1439 { 735, 454, 86, 3, 1863867, 13, 0, 0 },
1440 { 907, 433, 86, 3, 1777853, 13, 0, 0 },
1441 { 1038, 414, 83, 3, 1700031, 13, 0, 0 },
1442 { 1196, 393, 83, 3, 1614017, 13, 0, 0 },
1443 { 1295, 377, 80, 3, 1548483, 13, 0, 0 },
1444 { 1428, 360, 80, 3, 1478853, 13, 0, 0 },
1445 { 1514, 356, 77, 3, 1462471, 13, 0, 0 },
1446 { 28, 347, 77, 3, 1425609, 13, 0, 0 },
1447 { 307, 343, 74, 3, 1409227, 13, 0, 0 },
1448 { 479, 334, 74, 3, 1372365, 13, 0, 0 },
1449 { 662, 330, 68, 3, 1355983, 13, 0, 0 },
1450 { 770, 321, 68, 3, 1319121, 13, 0, 0 },
1451 { 957, 317, 65, 3, 1302739, 13, 0, 0 },
1452 { 230, 587, 2, 3, 2408629, 13, 0, 0 },
1453 { 424, 583, 2, 3, 2392247, 13, 0, 0 },
1454 { 596, 576, 2, 3, 2363577, 13, 0, 0 },
1455 { 719, 569, 2, 3, 2334907, 13, 0, 0 },
1456 { 891, 565, 2, 3, 2318525, 13, 0, 0 },
1457 { 1022, 561, 2, 3, 2302143, 13, 0, 0 },
1458 { 1180, 557, 2, 3, 2285761, 13, 0, 0 },
1459 { 1279, 553, 2, 3, 2269379, 13, 0, 0 },
1460 { 1421, 549, 2, 3, 2252997, 13, 0, 0 },
1461 { 1507, 545, 2, 3, 2236615, 13, 0, 0 },
1462 { 19, 541, 2, 3, 2220233, 13, 0, 0 },
1463 { 294, 537, 2, 3, 2203851, 13, 0, 0 },
1464 { 466, 533, 2, 3, 2187469, 13, 0, 0 },
1465 { 649, 529, 2, 3, 2171087, 13, 0, 0 },
1466 { 757, 525, 2, 3, 2154705, 13, 0, 0 },
1467 { 944, 521, 2, 3, 2138323, 13, 0, 0 },
1468 { 253, 9, 2, 0, 2420849, 2, 0, 0 },
1469 { 615, 9, 2, 0, 2420850, 2, 0, 0 },
1470 { 910, 0, 2, 0, 2523186, 7, 0, 0 },
1471 { 1199, 163, 2, 0, 487539, 0, 0, 0 },
1472 { 1431, 53, 2, 0, 1253400, 4, 0, 0 },
1473 { 32, 59, 2, 0, 1482764, 2, 0, 0 },
1474 { 1056, 106, 2, 0, 487432, 2, 0, 0 },
1475 { 258, 303, 2, 0, 1245194, 0, 0, 0 },
1476 { 620, 580, 2, 0, 2428939, 0, 0, 0 },
1477 { 915, 133, 2, 0, 487509, 0, 0, 0 },
1478 { 1204, 136, 2, 0, 487511, 0, 0, 0 },
1479 { 1436, 139, 2, 0, 487513, 0, 0, 0 },
1480 { 39, 142, 2, 0, 487515, 0, 0, 0 },
1481 { 483, 145, 2, 0, 487517, 0, 0, 0 },
1482 { 774, 148, 2, 0, 487519, 0, 0, 0 },
1483 { 1063, 157, 2, 0, 487531, 0, 0, 0 },
1484 { 1313, 160, 2, 0, 487533, 0, 0, 0 },
1485 { 76, 145, 2, 0, 487521, 0, 0, 0 },
1486 { 520, 148, 2, 0, 487523, 0, 0, 0 },
1487 { 807, 103, 2, 0, 487437, 2, 0, 0 },
1488 { 1096, 151, 2, 0, 487527, 0, 0, 0 },
1489 { 1342, 154, 2, 0, 487529, 0, 0, 0 },
1490 { 109, 142, 2, 0, 487525, 0, 0, 0 },
1491 { 270, 2, 62, 2, 2527350, 24, 0, 0 },
1492 { 625, 56, 2, 0, 1716230, 2, 0, 0 },
1493 { 920, 124, 2, 0, 487468, 0, 0, 0 },
1494 { 1209, 50, 2, 0, 2035713, 2, 0, 0 },
1495 { 1441, 67, 2, 0, 1269760, 2, 0, 0 },
1496 { 46, 609, 2, 0, 2474001, 0, 0, 0 },
1497 { 490, 181, 2, 0, 487558, 0, 0, 0 },
1498 { 781, 184, 2, 0, 487560, 0, 0, 0 },
1499 { 1070, 309, 2, 0, 1269767, 0, 0, 0 },
1500 { 1320, 606, 2, 0, 2465826, 0, 0, 0 },
1501 { 83, 6, 2, 0, 2457642, 2, 0, 0 },
1502 { 527, 184, 2, 0, 487564, 0, 0, 0 },
1503 { 814, 187, 2, 0, 487566, 0, 0, 0 },
1504 { 1103, 3, 2, 0, 2514946, 2, 0, 0 },
1505 { 1349, 418, 2, 0, 1634309, 0, 0, 0 },
1506 { 116, 100, 2, 0, 487449, 2, 0, 0 },
1507 { 534, 595, 2, 0, 2449430, 0, 0, 0 },
1508 { 821, 573, 2, 0, 2125936, 0, 0, 0 },
1509 { 1110, 94, 2, 0, 1232942, 2, 0, 0 },
1510 { 1356, 94, 2, 0, 1232943, 2, 0, 0 },
1511 { 123, 121, 2, 0, 487444, 0, 0, 0 },
1512 { 541, 118, 2, 0, 487442, 0, 0, 0 },
1513 { 832, 169, 2, 0, 487570, 0, 0, 0 },
1514 { 1121, 172, 2, 0, 487572, 0, 0, 0 },
1515 { 1363, 127, 2, 0, 487549, 0, 0, 0 },
1516 { 130, 130, 2, 0, 487551, 0, 0, 0 },
1517 { 548, 97, 2, 0, 487453, 2, 0, 0 },
1518 { 843, 166, 2, 0, 487574, 0, 0, 0 },
1519 { 1132, 169, 2, 0, 487576, 0, 0, 0 },
1520 { 1374, 172, 2, 0, 487578, 0, 0, 0 },
1521 { 141, 175, 2, 0, 487580, 0, 0, 0 },
1522 { 559, 178, 2, 0, 487582, 0, 0, 0 },
1523 { 854, 181, 2, 0, 487584, 0, 0, 0 },
1524 { 1143, 184, 2, 0, 487586, 0, 0, 0 },
1525 { 1385, 187, 2, 0, 487588, 0, 0, 0 },
1526 { 152, 190, 2, 0, 487590, 0, 0, 0 },
1527 { 570, 193, 2, 0, 487592, 0, 0, 0 },
1528 { 865, 196, 2, 0, 487594, 0, 0, 0 },
1529 { 1154, 109, 2, 0, 487596, 2, 0, 0 },
1530 { 1396, 112, 2, 0, 487598, 2, 0, 0 },
1531 { 263, 199, 2, 0, 487603, 0, 0, 0 },
1532};
1533
1534extern const MCPhysReg HexagonRegUnitRoots[][2] = {
1535 { Hexagon::BADVA },
1536 { Hexagon::CCR },
1537 { Hexagon::CFGBASE },
1538 { Hexagon::CS0 },
1539 { Hexagon::CS1 },
1540 { Hexagon::DIAG },
1541 { Hexagon::ELR },
1542 { Hexagon::EVB },
1543 { Hexagon::FRAMEKEY },
1544 { Hexagon::FRAMELIMIT },
1545 { Hexagon::GELR },
1546 { Hexagon::GOSP },
1547 { Hexagon::GP },
1548 { Hexagon::GPCYCLEHI },
1549 { Hexagon::GPCYCLELO },
1550 { Hexagon::GSR },
1551 { Hexagon::HTID },
1552 { Hexagon::IMASK },
1553 { Hexagon::ISDBEN },
1554 { Hexagon::ISDBGPR },
1555 { Hexagon::ISDBMBXIN },
1556 { Hexagon::ISDBMBXOUT },
1557 { Hexagon::ISDBST },
1558 { Hexagon::MODECTL },
1559 { Hexagon::PC },
1560 { Hexagon::PCYCLEHI },
1561 { Hexagon::PCYCLELO },
1562 { Hexagon::PKTCOUNTLO },
1563 { Hexagon::PKTCOUNTHI },
1564 { Hexagon::PMUCFG },
1565 { Hexagon::PMUEVTCFG },
1566 { Hexagon::REV },
1567 { Hexagon::SSR },
1568 { Hexagon::STID },
1569 { Hexagon::SYSCFG },
1570 { Hexagon::UGP },
1571 { Hexagon::UPCYCLELO },
1572 { Hexagon::UPCYCLEHI },
1573 { Hexagon::USR_OVF },
1574 { Hexagon::USR, Hexagon::C8 },
1575 { Hexagon::UTIMERLO },
1576 { Hexagon::UTIMERHI },
1577 { Hexagon::VID },
1578 { Hexagon::VTMP },
1579 { Hexagon::BADVA0 },
1580 { Hexagon::BADVA1 },
1581 { Hexagon::BRKPTCFG0 },
1582 { Hexagon::BRKPTCFG1 },
1583 { Hexagon::BRKPTPC0 },
1584 { Hexagon::BRKPTPC1 },
1585 { Hexagon::C5 },
1586 { Hexagon::C8 },
1587 { Hexagon::R0 },
1588 { Hexagon::R1 },
1589 { Hexagon::R2 },
1590 { Hexagon::R3 },
1591 { Hexagon::R4 },
1592 { Hexagon::R5 },
1593 { Hexagon::R6 },
1594 { Hexagon::R7 },
1595 { Hexagon::R8 },
1596 { Hexagon::R9 },
1597 { Hexagon::R10 },
1598 { Hexagon::R11 },
1599 { Hexagon::R12 },
1600 { Hexagon::R13 },
1601 { Hexagon::R14 },
1602 { Hexagon::R15 },
1603 { Hexagon::R16 },
1604 { Hexagon::R17 },
1605 { Hexagon::R18 },
1606 { Hexagon::R19 },
1607 { Hexagon::R20 },
1608 { Hexagon::R21 },
1609 { Hexagon::R22 },
1610 { Hexagon::R23 },
1611 { Hexagon::R24 },
1612 { Hexagon::R25 },
1613 { Hexagon::R26 },
1614 { Hexagon::R27 },
1615 { Hexagon::R28 },
1616 { Hexagon::R29 },
1617 { Hexagon::R30 },
1618 { Hexagon::R31 },
1619 { Hexagon::G3 },
1620 { Hexagon::G4 },
1621 { Hexagon::G5 },
1622 { Hexagon::G6 },
1623 { Hexagon::G7 },
1624 { Hexagon::G8 },
1625 { Hexagon::G9 },
1626 { Hexagon::G10 },
1627 { Hexagon::G11 },
1628 { Hexagon::G12 },
1629 { Hexagon::G13 },
1630 { Hexagon::G14 },
1631 { Hexagon::G15 },
1632 { Hexagon::G20 },
1633 { Hexagon::G21 },
1634 { Hexagon::G22 },
1635 { Hexagon::G23 },
1636 { Hexagon::G30 },
1637 { Hexagon::G31 },
1638 { Hexagon::GPMUCNT0 },
1639 { Hexagon::GPMUCNT1 },
1640 { Hexagon::GPMUCNT2 },
1641 { Hexagon::GPMUCNT3 },
1642 { Hexagon::GPMUCNT4 },
1643 { Hexagon::GPMUCNT5 },
1644 { Hexagon::GPMUCNT6 },
1645 { Hexagon::GPMUCNT7 },
1646 { Hexagon::ISDBCFG0 },
1647 { Hexagon::ISDBCFG1 },
1648 { Hexagon::LC0 },
1649 { Hexagon::LC1 },
1650 { Hexagon::M0 },
1651 { Hexagon::M1 },
1652 { Hexagon::P0 },
1653 { Hexagon::P0, Hexagon::P3_0 },
1654 { Hexagon::P1 },
1655 { Hexagon::P1, Hexagon::P3_0 },
1656 { Hexagon::P2 },
1657 { Hexagon::P2, Hexagon::P3_0 },
1658 { Hexagon::P3 },
1659 { Hexagon::P3, Hexagon::P3_0 },
1660 { Hexagon::PMUCNT0 },
1661 { Hexagon::PMUCNT1 },
1662 { Hexagon::PMUCNT2 },
1663 { Hexagon::PMUCNT3 },
1664 { Hexagon::Q0 },
1665 { Hexagon::Q1 },
1666 { Hexagon::Q2 },
1667 { Hexagon::Q3 },
1668 { Hexagon::S11 },
1669 { Hexagon::S12 },
1670 { Hexagon::S13 },
1671 { Hexagon::S14 },
1672 { Hexagon::S15 },
1673 { Hexagon::S19 },
1674 { Hexagon::S20 },
1675 { Hexagon::S22 },
1676 { Hexagon::S23 },
1677 { Hexagon::S24 },
1678 { Hexagon::S25 },
1679 { Hexagon::S26 },
1680 { Hexagon::S35 },
1681 { Hexagon::S44 },
1682 { Hexagon::S45 },
1683 { Hexagon::S46 },
1684 { Hexagon::S47 },
1685 { Hexagon::S54 },
1686 { Hexagon::S55 },
1687 { Hexagon::S56 },
1688 { Hexagon::S57 },
1689 { Hexagon::S58 },
1690 { Hexagon::S59 },
1691 { Hexagon::S60 },
1692 { Hexagon::S61 },
1693 { Hexagon::S62 },
1694 { Hexagon::S63 },
1695 { Hexagon::S64 },
1696 { Hexagon::S65 },
1697 { Hexagon::S66 },
1698 { Hexagon::S67 },
1699 { Hexagon::S68 },
1700 { Hexagon::S69 },
1701 { Hexagon::S70 },
1702 { Hexagon::S71 },
1703 { Hexagon::S72 },
1704 { Hexagon::S73 },
1705 { Hexagon::S74 },
1706 { Hexagon::S75 },
1707 { Hexagon::S76 },
1708 { Hexagon::S77 },
1709 { Hexagon::S78 },
1710 { Hexagon::S79 },
1711 { Hexagon::S80 },
1712 { Hexagon::SA0 },
1713 { Hexagon::SA1 },
1714 { Hexagon::SGP0 },
1715 { Hexagon::SGP1 },
1716 { Hexagon::V0 },
1717 { Hexagon::V1 },
1718 { Hexagon::V2 },
1719 { Hexagon::V3 },
1720 { Hexagon::V4 },
1721 { Hexagon::V5 },
1722 { Hexagon::V6 },
1723 { Hexagon::V7 },
1724 { Hexagon::V8 },
1725 { Hexagon::V9 },
1726 { Hexagon::V10 },
1727 { Hexagon::V11 },
1728 { Hexagon::V12 },
1729 { Hexagon::V13 },
1730 { Hexagon::V14 },
1731 { Hexagon::V15 },
1732 { Hexagon::V16 },
1733 { Hexagon::V17 },
1734 { Hexagon::V18 },
1735 { Hexagon::V19 },
1736 { Hexagon::V20 },
1737 { Hexagon::V21 },
1738 { Hexagon::V22 },
1739 { Hexagon::V23 },
1740 { Hexagon::V24 },
1741 { Hexagon::V25 },
1742 { Hexagon::V26 },
1743 { Hexagon::V27 },
1744 { Hexagon::V28 },
1745 { Hexagon::V29 },
1746 { Hexagon::V30 },
1747 { Hexagon::V31 },
1748 { Hexagon::VF0 },
1749 { Hexagon::VF1 },
1750 { Hexagon::VF2 },
1751 { Hexagon::VF3 },
1752 { Hexagon::VF4 },
1753 { Hexagon::VF5 },
1754 { Hexagon::VF6 },
1755 { Hexagon::VF7 },
1756 { Hexagon::VF8 },
1757 { Hexagon::VF9 },
1758 { Hexagon::VF10 },
1759 { Hexagon::VF11 },
1760 { Hexagon::VF12 },
1761 { Hexagon::VF13 },
1762 { Hexagon::VF14 },
1763 { Hexagon::VF15 },
1764 { Hexagon::VF16 },
1765 { Hexagon::VF17 },
1766 { Hexagon::VF18 },
1767 { Hexagon::VF19 },
1768 { Hexagon::VF20 },
1769 { Hexagon::VF21 },
1770 { Hexagon::VF22 },
1771 { Hexagon::VF23 },
1772 { Hexagon::VF24 },
1773 { Hexagon::VF25 },
1774 { Hexagon::VF26 },
1775 { Hexagon::VF27 },
1776 { Hexagon::VF28 },
1777 { Hexagon::VF29 },
1778 { Hexagon::VF30 },
1779 { Hexagon::VF31 },
1780 { Hexagon::VFR0 },
1781 { Hexagon::VFR1 },
1782 { Hexagon::VFR2 },
1783 { Hexagon::VFR3 },
1784 { Hexagon::VFR4 },
1785 { Hexagon::VFR5 },
1786 { Hexagon::VFR6 },
1787 { Hexagon::VFR7 },
1788 { Hexagon::VFR8 },
1789 { Hexagon::VFR9 },
1790 { Hexagon::VFR10 },
1791 { Hexagon::VFR11 },
1792 { Hexagon::VFR12 },
1793 { Hexagon::VFR13 },
1794 { Hexagon::VFR14 },
1795 { Hexagon::VFR15 },
1796 { Hexagon::VFR16 },
1797 { Hexagon::VFR17 },
1798 { Hexagon::VFR18 },
1799 { Hexagon::VFR19 },
1800 { Hexagon::VFR20 },
1801 { Hexagon::VFR21 },
1802 { Hexagon::VFR22 },
1803 { Hexagon::VFR23 },
1804 { Hexagon::VFR24 },
1805 { Hexagon::VFR25 },
1806 { Hexagon::VFR26 },
1807 { Hexagon::VFR27 },
1808 { Hexagon::VFR28 },
1809 { Hexagon::VFR29 },
1810 { Hexagon::VFR30 },
1811 { Hexagon::VFR31 },
1812 { Hexagon::P3_0 },
1813};
1814
1815namespace { // Register classes...
1816 // UsrBits Register Class...
1817 const MCPhysReg UsrBits[] = {
1818 Hexagon::USR_OVF,
1819 };
1820
1821 // UsrBits Bit set.
1822 const uint8_t UsrBitsBits[] = {
1823 0x00, 0x00, 0x00, 0x00, 0x00, 0x02,
1824 };
1825
1826 // SysRegs Register Class...
1827 const MCPhysReg SysRegs[] = {
1828 Hexagon::SGP0, Hexagon::SGP1, Hexagon::STID, Hexagon::ELR, Hexagon::BADVA0, Hexagon::BADVA1, Hexagon::SSR, Hexagon::CCR, Hexagon::HTID, Hexagon::BADVA, Hexagon::IMASK, Hexagon::S11, Hexagon::S12, Hexagon::S13, Hexagon::S14, Hexagon::S15, Hexagon::S19, Hexagon::S23, Hexagon::S25, Hexagon::EVB, Hexagon::MODECTL, Hexagon::SYSCFG, Hexagon::S20, Hexagon::VID, Hexagon::S22, Hexagon::S24, Hexagon::S26, Hexagon::CFGBASE, Hexagon::DIAG, Hexagon::REV, Hexagon::PCYCLEHI, Hexagon::PCYCLELO, Hexagon::ISDBST, Hexagon::ISDBCFG0, Hexagon::ISDBCFG1, Hexagon::S35, Hexagon::BRKPTPC0, Hexagon::BRKPTCFG0, Hexagon::BRKPTPC1, Hexagon::BRKPTCFG1, Hexagon::ISDBMBXIN, Hexagon::ISDBMBXOUT, Hexagon::ISDBEN, Hexagon::ISDBGPR, Hexagon::S44, Hexagon::S45, Hexagon::S46, Hexagon::S47, Hexagon::PMUCNT0, Hexagon::PMUCNT1, Hexagon::PMUCNT2, Hexagon::PMUCNT3, Hexagon::PMUEVTCFG, Hexagon::PMUCFG, Hexagon::S54, Hexagon::S55, Hexagon::S56, Hexagon::S57, Hexagon::S58, Hexagon::S59, Hexagon::S60, Hexagon::S61, Hexagon::S62, Hexagon::S63, Hexagon::S64, Hexagon::S65, Hexagon::S66, Hexagon::S67, Hexagon::S68, Hexagon::S69, Hexagon::S70, Hexagon::S71, Hexagon::S72, Hexagon::S73, Hexagon::S74, Hexagon::S75, Hexagon::S76, Hexagon::S77, Hexagon::S78, Hexagon::S79, Hexagon::S80,
1829 };
1830
1831 // SysRegs Bit set.
1832 const uint8_t SysRegsBits[] = {
1833 0xee, 0x00, 0xff, 0xc6, 0x0f, 0xa0, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0xc0, 0x03, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xff, 0x33,
1834 };
1835
1836 // GuestRegs Register Class...
1837 const MCPhysReg GuestRegs[] = {
1838 Hexagon::GELR, Hexagon::GSR, Hexagon::GOSP, Hexagon::G3, Hexagon::G4, Hexagon::G5, Hexagon::G6, Hexagon::G7, Hexagon::G8, Hexagon::G9, Hexagon::G10, Hexagon::G11, Hexagon::G12, Hexagon::G13, Hexagon::G14, Hexagon::G15, Hexagon::GPMUCNT4, Hexagon::GPMUCNT5, Hexagon::GPMUCNT6, Hexagon::GPMUCNT7, Hexagon::G20, Hexagon::G21, Hexagon::G22, Hexagon::G23, Hexagon::GPCYCLELO, Hexagon::GPCYCLEHI, Hexagon::GPMUCNT0, Hexagon::GPMUCNT1, Hexagon::GPMUCNT2, Hexagon::GPMUCNT3, Hexagon::G30, Hexagon::G31,
1839 };
1840
1841 // GuestRegs Bit set.
1842 const uint8_t GuestRegsBits[] = {
1843 0x00, 0xec, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0x0f,
1844 };
1845
1846 // IntRegs Register Class...
1847 const MCPhysReg IntRegs[] = {
1848 Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4, Hexagon::R5, Hexagon::R6, Hexagon::R7, Hexagon::R8, Hexagon::R9, Hexagon::R12, Hexagon::R13, Hexagon::R14, Hexagon::R15, Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19, Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, Hexagon::R24, Hexagon::R25, Hexagon::R26, Hexagon::R27, Hexagon::R28, Hexagon::R10, Hexagon::R11, Hexagon::R29, Hexagon::R30, Hexagon::R31,
1849 };
1850
1851 // IntRegs Bit set.
1852 const uint8_t IntRegsBits[] = {
1853 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x3f,
1854 };
1855
1856 // CtrRegs Register Class...
1857 const MCPhysReg CtrRegs[] = {
1858 Hexagon::LC0, Hexagon::SA0, Hexagon::LC1, Hexagon::SA1, Hexagon::P3_0, Hexagon::C5, Hexagon::C8, Hexagon::PC, Hexagon::UGP, Hexagon::GP, Hexagon::CS0, Hexagon::CS1, Hexagon::UPCYCLELO, Hexagon::UPCYCLEHI, Hexagon::FRAMELIMIT, Hexagon::FRAMEKEY, Hexagon::PKTCOUNTLO, Hexagon::PKTCOUNTHI, Hexagon::UTIMERLO, Hexagon::UTIMERHI, Hexagon::M0, Hexagon::M1, Hexagon::USR,
1859 };
1860
1861 // CtrRegs Bit set.
1862 const uint8_t CtrRegsBits[] = {
1863 0x00, 0x13, 0x00, 0x31, 0xd0, 0x19, 0xe0, 0x01, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20,
1864 };
1865
1866 // GeneralSubRegs Register Class...
1867 const MCPhysReg GeneralSubRegs[] = {
1868 Hexagon::R23, Hexagon::R22, Hexagon::R21, Hexagon::R20, Hexagon::R19, Hexagon::R18, Hexagon::R17, Hexagon::R16, Hexagon::R7, Hexagon::R6, Hexagon::R5, Hexagon::R4, Hexagon::R3, Hexagon::R2, Hexagon::R1, Hexagon::R0,
1869 };
1870
1871 // GeneralSubRegs Bit set.
1872 const uint8_t GeneralSubRegsBits[] = {
1873 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x3f, 0xc0, 0x3f,
1874 };
1875
1876 // V62Regs Register Class...
1877 const MCPhysReg V62Regs[] = {
1878 Hexagon::FRAMELIMIT, Hexagon::FRAMEKEY, Hexagon::C17_16, Hexagon::PKTCOUNTLO, Hexagon::PKTCOUNTHI, Hexagon::PKTCOUNT, Hexagon::UTIMERLO, Hexagon::UTIMERHI, Hexagon::UTIMER,
1879 };
1880
1881 // V62Regs Bit set.
1882 const uint8_t V62RegsBits[] = {
1883 0x00, 0x03, 0x00, 0x38, 0x00, 0x1c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10,
1884 };
1885
1886 // IntRegsLow8 Register Class...
1887 const MCPhysReg IntRegsLow8[] = {
1888 Hexagon::R7, Hexagon::R6, Hexagon::R5, Hexagon::R4, Hexagon::R3, Hexagon::R2, Hexagon::R1, Hexagon::R0,
1889 };
1890
1891 // IntRegsLow8 Bit set.
1892 const uint8_t IntRegsLow8Bits[] = {
1893 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x3f,
1894 };
1895
1896 // CtrRegs_and_V62Regs Register Class...
1897 const MCPhysReg CtrRegs_and_V62Regs[] = {
1898 Hexagon::FRAMELIMIT, Hexagon::FRAMEKEY, Hexagon::PKTCOUNTLO, Hexagon::PKTCOUNTHI, Hexagon::UTIMERLO, Hexagon::UTIMERHI,
1899 };
1900
1901 // CtrRegs_and_V62Regs Bit set.
1902 const uint8_t CtrRegs_and_V62RegsBits[] = {
1903 0x00, 0x03, 0x00, 0x30, 0x00, 0x18,
1904 };
1905
1906 // PredRegs Register Class...
1907 const MCPhysReg PredRegs[] = {
1908 Hexagon::P0, Hexagon::P1, Hexagon::P2, Hexagon::P3,
1909 };
1910
1911 // PredRegs Bit set.
1912 const uint8_t PredRegsBits[] = {
1913 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c,
1914 };
1915
1916 // V62Regs_with_isub_hi Register Class...
1917 const MCPhysReg V62Regs_with_isub_hi[] = {
1918 Hexagon::C17_16, Hexagon::PKTCOUNT, Hexagon::UTIMER,
1919 };
1920
1921 // V62Regs_with_isub_hi Bit set.
1922 const uint8_t V62Regs_with_isub_hiBits[] = {
1923 0x00, 0x00, 0x00, 0x08, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10,
1924 };
1925
1926 // ModRegs Register Class...
1927 const MCPhysReg ModRegs[] = {
1928 Hexagon::M0, Hexagon::M1,
1929 };
1930
1931 // ModRegs Bit set.
1932 const uint8_t ModRegsBits[] = {
1933 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03,
1934 };
1935
1936 // CtrRegs_with_subreg_overflow Register Class...
1937 const MCPhysReg CtrRegs_with_subreg_overflow[] = {
1938 Hexagon::USR,
1939 };
1940
1941 // CtrRegs_with_subreg_overflow Bit set.
1942 const uint8_t CtrRegs_with_subreg_overflowBits[] = {
1943 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
1944 };
1945
1946 // V65Regs Register Class...
1947 const MCPhysReg V65Regs[] = {
1948 Hexagon::VTMP,
1949 };
1950
1951 // V65Regs Bit set.
1952 const uint8_t V65RegsBits[] = {
1953 0x00, 0x00, 0x00, 0x00, 0x00, 0x40,
1954 };
1955
1956 // SysRegs64 Register Class...
1957 const MCPhysReg SysRegs64[] = {
1958 Hexagon::SGP1_0, Hexagon::S3_2, Hexagon::S5_4, Hexagon::S7_6, Hexagon::S9_8, Hexagon::S11_10, Hexagon::S13_12, Hexagon::S15_14, Hexagon::S17_16, Hexagon::S19_18, Hexagon::S21_20, Hexagon::S23_22, Hexagon::S25_24, Hexagon::S27_26, Hexagon::S29_28, Hexagon::S31_30, Hexagon::S33_32, Hexagon::S35_34, Hexagon::S37_36, Hexagon::S39_38, Hexagon::S41_40, Hexagon::S43_42, Hexagon::S45_44, Hexagon::S47_46, Hexagon::S49_48, Hexagon::S51_50, Hexagon::S53_52, Hexagon::S55_54, Hexagon::S57_56, Hexagon::S59_58, Hexagon::S61_60, Hexagon::S63_62, Hexagon::S65_64, Hexagon::S67_66, Hexagon::S69_68, Hexagon::S71_70, Hexagon::S73_72, Hexagon::S75_74, Hexagon::S77_76, Hexagon::S79_78,
1959 };
1960
1961 // SysRegs64 Bit set.
1962 const uint8_t SysRegs64Bits[] = {
1963 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0xff, 0x3f,
1964 };
1965
1966 // DoubleRegs Register Class...
1967 const MCPhysReg DoubleRegs[] = {
1968 Hexagon::D0, Hexagon::D1, Hexagon::D2, Hexagon::D3, Hexagon::D4, Hexagon::D6, Hexagon::D7, Hexagon::D8, Hexagon::D9, Hexagon::D10, Hexagon::D11, Hexagon::D12, Hexagon::D13, Hexagon::D5, Hexagon::D14, Hexagon::D15,
1969 };
1970
1971 // DoubleRegs Bit set.
1972 const uint8_t DoubleRegsBits[] = {
1973 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0x01,
1974 };
1975
1976 // GuestRegs64 Register Class...
1977 const MCPhysReg GuestRegs64[] = {
1978 Hexagon::G1_0, Hexagon::G3_2, Hexagon::G5_4, Hexagon::G7_6, Hexagon::G9_8, Hexagon::G11_10, Hexagon::G13_12, Hexagon::G15_14, Hexagon::G17_16, Hexagon::G19_18, Hexagon::G21_20, Hexagon::G23_22, Hexagon::G25_24, Hexagon::G27_26, Hexagon::G29_28, Hexagon::G31_30,
1979 };
1980
1981 // GuestRegs64 Bit set.
1982 const uint8_t GuestRegs64Bits[] = {
1983 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f,
1984 };
1985
1986 // VectRegRev Register Class...
1987 const MCPhysReg VectRegRev[] = {
1988 Hexagon::WR0, Hexagon::WR1, Hexagon::WR2, Hexagon::WR3, Hexagon::WR4, Hexagon::WR5, Hexagon::WR6, Hexagon::WR7, Hexagon::WR8, Hexagon::WR9, Hexagon::WR10, Hexagon::WR11, Hexagon::WR12, Hexagon::WR13, Hexagon::WR14, Hexagon::WR15,
1989 };
1990
1991 // VectRegRev Bit set.
1992 const uint8_t VectRegRevBits[] = {
1993 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x3f,
1994 };
1995
1996 // CtrRegs64 Register Class...
1997 const MCPhysReg CtrRegs64[] = {
1998 Hexagon::C1_0, Hexagon::C3_2, Hexagon::C5_4, Hexagon::C7_6, Hexagon::C9_8, Hexagon::C11_10, Hexagon::CS, Hexagon::UPCYCLE, Hexagon::C17_16, Hexagon::PKTCOUNT, Hexagon::UTIMER,
1999 };
2000
2001 // CtrRegs64 Bit set.
2002 const uint8_t CtrRegs64Bits[] = {
2003 0x10, 0x00, 0x00, 0x08, 0x20, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x1f,
2004 };
2005
2006 // GeneralDoubleLow8Regs Register Class...
2007 const MCPhysReg GeneralDoubleLow8Regs[] = {
2008 Hexagon::D11, Hexagon::D10, Hexagon::D9, Hexagon::D8, Hexagon::D3, Hexagon::D2, Hexagon::D1, Hexagon::D0,
2009 };
2010
2011 // GeneralDoubleLow8Regs Bit set.
2012 const uint8_t GeneralDoubleLow8RegsBits[] = {
2013 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1e, 0x1e,
2014 };
2015
2016 // DoubleRegs_with_isub_hi_in_IntRegsLow8 Register Class...
2017 const MCPhysReg DoubleRegs_with_isub_hi_in_IntRegsLow8[] = {
2018 Hexagon::D3, Hexagon::D2, Hexagon::D1, Hexagon::D0,
2019 };
2020
2021 // DoubleRegs_with_isub_hi_in_IntRegsLow8 Bit set.
2022 const uint8_t DoubleRegs_with_isub_hi_in_IntRegsLow8Bits[] = {
2023 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1e,
2024 };
2025
2026 // CtrRegs64_and_V62Regs Register Class...
2027 const MCPhysReg CtrRegs64_and_V62Regs[] = {
2028 Hexagon::C17_16, Hexagon::PKTCOUNT, Hexagon::UTIMER,
2029 };
2030
2031 // CtrRegs64_and_V62Regs Bit set.
2032 const uint8_t CtrRegs64_and_V62RegsBits[] = {
2033 0x00, 0x00, 0x00, 0x08, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10,
2034 };
2035
2036 // CtrRegs64_with_isub_hi_in_ModRegs Register Class...
2037 const MCPhysReg CtrRegs64_with_isub_hi_in_ModRegs[] = {
2038 Hexagon::C7_6,
2039 };
2040
2041 // CtrRegs64_with_isub_hi_in_ModRegs Bit set.
2042 const uint8_t CtrRegs64_with_isub_hi_in_ModRegsBits[] = {
2043 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02,
2044 };
2045
2046 // HvxQR Register Class...
2047 const MCPhysReg HvxQR[] = {
2048 Hexagon::Q0, Hexagon::Q1, Hexagon::Q2, Hexagon::Q3,
2049 };
2050
2051 // HvxQR Bit set.
2052 const uint8_t HvxQRBits[] = {
2053 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c,
2054 };
2055
2056 // HvxVR Register Class...
2057 const MCPhysReg HvxVR[] = {
2058 Hexagon::V0, Hexagon::V1, Hexagon::V2, Hexagon::V3, Hexagon::V4, Hexagon::V5, Hexagon::V6, Hexagon::V7, Hexagon::V8, Hexagon::V9, Hexagon::V10, Hexagon::V11, Hexagon::V12, Hexagon::V13, Hexagon::V14, Hexagon::V15, Hexagon::V16, Hexagon::V17, Hexagon::V18, Hexagon::V19, Hexagon::V20, Hexagon::V21, Hexagon::V22, Hexagon::V23, Hexagon::V24, Hexagon::V25, Hexagon::V26, Hexagon::V27, Hexagon::V28, Hexagon::V29, Hexagon::V30, Hexagon::V31, Hexagon::VTMP,
2059 };
2060
2061 // HvxVR Bit set.
2062 const uint8_t HvxVRBits[] = {
2063 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x3f,
2064 };
2065
2066 // HvxVR_and_V65Regs Register Class...
2067 const MCPhysReg HvxVR_and_V65Regs[] = {
2068 Hexagon::VTMP,
2069 };
2070
2071 // HvxVR_and_V65Regs Bit set.
2072 const uint8_t HvxVR_and_V65RegsBits[] = {
2073 0x00, 0x00, 0x00, 0x00, 0x00, 0x40,
2074 };
2075
2076 // HvxWR Register Class...
2077 const MCPhysReg HvxWR[] = {
2078 Hexagon::W0, Hexagon::W1, Hexagon::W2, Hexagon::W3, Hexagon::W4, Hexagon::W5, Hexagon::W6, Hexagon::W7, Hexagon::W8, Hexagon::W9, Hexagon::W10, Hexagon::W11, Hexagon::W12, Hexagon::W13, Hexagon::W14, Hexagon::W15, Hexagon::WR0, Hexagon::WR1, Hexagon::WR2, Hexagon::WR3, Hexagon::WR4, Hexagon::WR5, Hexagon::WR6, Hexagon::WR7, Hexagon::WR8, Hexagon::WR9, Hexagon::WR10, Hexagon::WR11, Hexagon::WR12, Hexagon::WR13, Hexagon::WR14, Hexagon::WR15,
2079 };
2080
2081 // HvxWR Bit set.
2082 const uint8_t HvxWRBits[] = {
2083 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x3f,
2084 };
2085
2086 // HvxWR_and_VectRegRev Register Class...
2087 const MCPhysReg HvxWR_and_VectRegRev[] = {
2088 Hexagon::WR0, Hexagon::WR1, Hexagon::WR2, Hexagon::WR3, Hexagon::WR4, Hexagon::WR5, Hexagon::WR6, Hexagon::WR7, Hexagon::WR8, Hexagon::WR9, Hexagon::WR10, Hexagon::WR11, Hexagon::WR12, Hexagon::WR13, Hexagon::WR14, Hexagon::WR15,
2089 };
2090
2091 // HvxWR_and_VectRegRev Bit set.
2092 const uint8_t HvxWR_and_VectRegRevBits[] = {
2093 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x3f,
2094 };
2095
2096 // HvxVQR Register Class...
2097 const MCPhysReg HvxVQR[] = {
2098 Hexagon::VQ0, Hexagon::VQ1, Hexagon::VQ2, Hexagon::VQ3, Hexagon::VQ4, Hexagon::VQ5, Hexagon::VQ6, Hexagon::VQ7,
2099 };
2100
2101 // HvxVQR Bit set.
2102 const uint8_t HvxVQRBits[] = {
2103 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x3f,
2104 };
2105
2106} // end anonymous namespace
2107
2108
2109#ifdef __GNUC__
2110#pragma GCC diagnostic push
2111#pragma GCC diagnostic ignored "-Woverlength-strings"
2112#endif
2113extern const char HexagonRegClassStrings[] = {
2114 /* 0 */ "CtrRegs64\000"
2115 /* 10 */ "SysRegs64\000"
2116 /* 20 */ "GuestRegs64\000"
2117 /* 32 */ "DoubleRegs_with_isub_hi_in_IntRegsLow8\000"
2118 /* 71 */ "HvxVQR\000"
2119 /* 78 */ "HvxQR\000"
2120 /* 84 */ "HvxVR\000"
2121 /* 90 */ "HvxWR\000"
2122 /* 96 */ "V62Regs_with_isub_hi\000"
2123 /* 117 */ "CtrRegs64_and_V62Regs\000"
2124 /* 139 */ "CtrRegs_and_V62Regs\000"
2125 /* 159 */ "HvxVR_and_V65Regs\000"
2126 /* 177 */ "GeneralDoubleLow8Regs\000"
2127 /* 199 */ "GeneralSubRegs\000"
2128 /* 214 */ "PredRegs\000"
2129 /* 223 */ "CtrRegs64_with_isub_hi_in_ModRegs\000"
2130 /* 257 */ "DoubleRegs\000"
2131 /* 268 */ "CtrRegs\000"
2132 /* 276 */ "SysRegs\000"
2133 /* 284 */ "IntRegs\000"
2134 /* 292 */ "GuestRegs\000"
2135 /* 302 */ "UsrBits\000"
2136 /* 310 */ "HvxWR_and_VectRegRev\000"
2137 /* 331 */ "CtrRegs_with_subreg_overflow\000"
2138};
2139#ifdef __GNUC__
2140#pragma GCC diagnostic pop
2141#endif
2142
2143extern const MCRegisterClass HexagonMCRegisterClasses[] = {
2144 { UsrBits, UsrBitsBits, 302, 1, sizeof(UsrBitsBits), Hexagon::UsrBitsRegClassID, 1, 1, false, false },
2145 { SysRegs, SysRegsBits, 276, 81, sizeof(SysRegsBits), Hexagon::SysRegsRegClassID, 32, 1, false, false },
2146 { GuestRegs, GuestRegsBits, 292, 32, sizeof(GuestRegsBits), Hexagon::GuestRegsRegClassID, 32, 1, false, false },
2147 { IntRegs, IntRegsBits, 284, 32, sizeof(IntRegsBits), Hexagon::IntRegsRegClassID, 32, 1, true, false },
2148 { CtrRegs, CtrRegsBits, 268, 23, sizeof(CtrRegsBits), Hexagon::CtrRegsRegClassID, 32, 1, false, false },
2149 { GeneralSubRegs, GeneralSubRegsBits, 199, 16, sizeof(GeneralSubRegsBits), Hexagon::GeneralSubRegsRegClassID, 32, 1, true, false },
2150 { V62Regs, V62RegsBits, 131, 9, sizeof(V62RegsBits), Hexagon::V62RegsRegClassID, 32, 1, false, false },
2151 { IntRegsLow8, IntRegsLow8Bits, 59, 8, sizeof(IntRegsLow8Bits), Hexagon::IntRegsLow8RegClassID, 32, 1, true, false },
2152 { CtrRegs_and_V62Regs, CtrRegs_and_V62RegsBits, 139, 6, sizeof(CtrRegs_and_V62RegsBits), Hexagon::CtrRegs_and_V62RegsRegClassID, 32, 1, false, false },
2153 { PredRegs, PredRegsBits, 214, 4, sizeof(PredRegsBits), Hexagon::PredRegsRegClassID, 32, 1, true, false },
2154 { V62Regs_with_isub_hi, V62Regs_with_isub_hiBits, 96, 3, sizeof(V62Regs_with_isub_hiBits), Hexagon::V62Regs_with_isub_hiRegClassID, 32, 1, false, false },
2155 { ModRegs, ModRegsBits, 249, 2, sizeof(ModRegsBits), Hexagon::ModRegsRegClassID, 32, 1, true, false },
2156 { CtrRegs_with_subreg_overflow, CtrRegs_with_subreg_overflowBits, 331, 1, sizeof(CtrRegs_with_subreg_overflowBits), Hexagon::CtrRegs_with_subreg_overflowRegClassID, 32, 1, false, false },
2157 { V65Regs, V65RegsBits, 169, 1, sizeof(V65RegsBits), Hexagon::V65RegsRegClassID, 32, 1, false, false },
2158 { SysRegs64, SysRegs64Bits, 10, 40, sizeof(SysRegs64Bits), Hexagon::SysRegs64RegClassID, 64, 1, false, false },
2159 { DoubleRegs, DoubleRegsBits, 257, 16, sizeof(DoubleRegsBits), Hexagon::DoubleRegsRegClassID, 64, 1, true, false },
2160 { GuestRegs64, GuestRegs64Bits, 20, 16, sizeof(GuestRegs64Bits), Hexagon::GuestRegs64RegClassID, 64, 1, false, false },
2161 { VectRegRev, VectRegRevBits, 320, 16, sizeof(VectRegRevBits), Hexagon::VectRegRevRegClassID, 64, 1, true, false },
2162 { CtrRegs64, CtrRegs64Bits, 0, 11, sizeof(CtrRegs64Bits), Hexagon::CtrRegs64RegClassID, 64, 1, false, false },
2163 { GeneralDoubleLow8Regs, GeneralDoubleLow8RegsBits, 177, 8, sizeof(GeneralDoubleLow8RegsBits), Hexagon::GeneralDoubleLow8RegsRegClassID, 64, 1, true, false },
2164 { DoubleRegs_with_isub_hi_in_IntRegsLow8, DoubleRegs_with_isub_hi_in_IntRegsLow8Bits, 32, 4, sizeof(DoubleRegs_with_isub_hi_in_IntRegsLow8Bits), Hexagon::DoubleRegs_with_isub_hi_in_IntRegsLow8RegClassID, 64, 1, true, false },
2165 { CtrRegs64_and_V62Regs, CtrRegs64_and_V62RegsBits, 117, 3, sizeof(CtrRegs64_and_V62RegsBits), Hexagon::CtrRegs64_and_V62RegsRegClassID, 64, 1, false, false },
2166 { CtrRegs64_with_isub_hi_in_ModRegs, CtrRegs64_with_isub_hi_in_ModRegsBits, 223, 1, sizeof(CtrRegs64_with_isub_hi_in_ModRegsBits), Hexagon::CtrRegs64_with_isub_hi_in_ModRegsRegClassID, 64, 1, false, false },
2167 { HvxQR, HvxQRBits, 78, 4, sizeof(HvxQRBits), Hexagon::HvxQRRegClassID, 0, 1, true, false },
2168 { HvxVR, HvxVRBits, 84, 33, sizeof(HvxVRBits), Hexagon::HvxVRRegClassID, 0, 1, true, false },
2169 { HvxVR_and_V65Regs, HvxVR_and_V65RegsBits, 159, 1, sizeof(HvxVR_and_V65RegsBits), Hexagon::HvxVR_and_V65RegsRegClassID, 0, 1, true, false },
2170 { HvxWR, HvxWRBits, 90, 32, sizeof(HvxWRBits), Hexagon::HvxWRRegClassID, 0, 1, true, false },
2171 { HvxWR_and_VectRegRev, HvxWR_and_VectRegRevBits, 310, 16, sizeof(HvxWR_and_VectRegRevBits), Hexagon::HvxWR_and_VectRegRevRegClassID, 0, 1, true, false },
2172 { HvxVQR, HvxVQRBits, 71, 8, sizeof(HvxVQRBits), Hexagon::HvxVQRRegClassID, 0, 1, true, false },
2173};
2174
2175// Hexagon Dwarf<->LLVM register mappings.
2176extern const MCRegisterInfo::DwarfLLVMRegPair HexagonDwarfFlavour0Dwarf2L[] = {
2177 { 0U, Hexagon::R0 },
2178 { 1U, Hexagon::R1 },
2179 { 2U, Hexagon::R2 },
2180 { 3U, Hexagon::R3 },
2181 { 4U, Hexagon::R4 },
2182 { 5U, Hexagon::R5 },
2183 { 6U, Hexagon::R6 },
2184 { 7U, Hexagon::R7 },
2185 { 8U, Hexagon::R8 },
2186 { 9U, Hexagon::R9 },
2187 { 10U, Hexagon::R10 },
2188 { 11U, Hexagon::R11 },
2189 { 12U, Hexagon::R12 },
2190 { 13U, Hexagon::R13 },
2191 { 14U, Hexagon::R14 },
2192 { 15U, Hexagon::R15 },
2193 { 16U, Hexagon::R16 },
2194 { 17U, Hexagon::R17 },
2195 { 18U, Hexagon::R18 },
2196 { 19U, Hexagon::R19 },
2197 { 20U, Hexagon::R20 },
2198 { 21U, Hexagon::R21 },
2199 { 22U, Hexagon::R22 },
2200 { 23U, Hexagon::R23 },
2201 { 24U, Hexagon::R24 },
2202 { 25U, Hexagon::R25 },
2203 { 26U, Hexagon::R26 },
2204 { 27U, Hexagon::R27 },
2205 { 28U, Hexagon::R28 },
2206 { 29U, Hexagon::R29 },
2207 { 30U, Hexagon::R30 },
2208 { 31U, Hexagon::R31 },
2209 { 32U, Hexagon::D0 },
2210 { 34U, Hexagon::D1 },
2211 { 36U, Hexagon::D2 },
2212 { 38U, Hexagon::D3 },
2213 { 40U, Hexagon::D4 },
2214 { 42U, Hexagon::D5 },
2215 { 44U, Hexagon::D6 },
2216 { 46U, Hexagon::D7 },
2217 { 48U, Hexagon::D8 },
2218 { 50U, Hexagon::D9 },
2219 { 52U, Hexagon::D10 },
2220 { 54U, Hexagon::D11 },
2221 { 56U, Hexagon::D12 },
2222 { 58U, Hexagon::D13 },
2223 { 60U, Hexagon::D14 },
2224 { 62U, Hexagon::D15 },
2225 { 63U, Hexagon::P0 },
2226 { 64U, Hexagon::P1 },
2227 { 65U, Hexagon::P2 },
2228 { 66U, Hexagon::P3 },
2229 { 67U, Hexagon::C1_0 },
2230 { 68U, Hexagon::LC0 },
2231 { 69U, Hexagon::C3_2 },
2232 { 70U, Hexagon::LC1 },
2233 { 71U, Hexagon::P3_0 },
2234 { 72U, Hexagon::C7_6 },
2235 { 73U, Hexagon::M0 },
2236 { 74U, Hexagon::C9_8 },
2237 { 75U, Hexagon::C8 },
2238 { 76U, Hexagon::C11_10 },
2239 { 77U, Hexagon::UGP },
2240 { 78U, Hexagon::GP },
2241 { 79U, Hexagon::CS0 },
2242 { 80U, Hexagon::CS1 },
2243 { 81U, Hexagon::UPCYCLELO },
2244 { 82U, Hexagon::UPCYCLEHI },
2245 { 83U, Hexagon::C17_16 },
2246 { 84U, Hexagon::FRAMEKEY },
2247 { 85U, Hexagon::PKTCOUNTLO },
2248 { 86U, Hexagon::PKTCOUNTHI },
2249 { 97U, Hexagon::UTIMERLO },
2250 { 98U, Hexagon::UTIMERHI },
2251 { 99U, Hexagon::W0 },
2252 { 100U, Hexagon::V1 },
2253 { 101U, Hexagon::W1 },
2254 { 102U, Hexagon::V3 },
2255 { 103U, Hexagon::W2 },
2256 { 104U, Hexagon::V5 },
2257 { 105U, Hexagon::W3 },
2258 { 106U, Hexagon::V7 },
2259 { 107U, Hexagon::W4 },
2260 { 108U, Hexagon::V9 },
2261 { 109U, Hexagon::W5 },
2262 { 110U, Hexagon::V11 },
2263 { 111U, Hexagon::W6 },
2264 { 112U, Hexagon::V13 },
2265 { 113U, Hexagon::W7 },
2266 { 114U, Hexagon::V15 },
2267 { 115U, Hexagon::W8 },
2268 { 116U, Hexagon::V17 },
2269 { 117U, Hexagon::W9 },
2270 { 118U, Hexagon::V19 },
2271 { 119U, Hexagon::W10 },
2272 { 120U, Hexagon::V21 },
2273 { 121U, Hexagon::W11 },
2274 { 122U, Hexagon::V23 },
2275 { 123U, Hexagon::W12 },
2276 { 124U, Hexagon::V25 },
2277 { 125U, Hexagon::W13 },
2278 { 126U, Hexagon::V27 },
2279 { 127U, Hexagon::W14 },
2280 { 128U, Hexagon::V29 },
2281 { 129U, Hexagon::W15 },
2282 { 130U, Hexagon::V31 },
2283 { 131U, Hexagon::Q0 },
2284 { 132U, Hexagon::Q1 },
2285 { 133U, Hexagon::Q2 },
2286 { 134U, Hexagon::Q3 },
2287 { 144U, Hexagon::SGP1_0 },
2288 { 145U, Hexagon::SGP1 },
2289 { 146U, Hexagon::S3_2 },
2290 { 147U, Hexagon::ELR },
2291 { 148U, Hexagon::S5_4 },
2292 { 149U, Hexagon::BADVA1 },
2293 { 150U, Hexagon::S7_6 },
2294 { 151U, Hexagon::CCR },
2295 { 152U, Hexagon::S9_8 },
2296 { 153U, Hexagon::BADVA },
2297 { 154U, Hexagon::S11_10 },
2298 { 155U, Hexagon::S11 },
2299 { 156U, Hexagon::S13_12 },
2300 { 157U, Hexagon::S13 },
2301 { 158U, Hexagon::S15_14 },
2302 { 159U, Hexagon::S15 },
2303 { 160U, Hexagon::S17_16 },
2304 { 161U, Hexagon::WR0 },
2305 { 162U, Hexagon::S19_18 },
2306 { 163U, Hexagon::WR2 },
2307 { 164U, Hexagon::S21_20 },
2308 { 165U, Hexagon::WR4 },
2309 { 166U, Hexagon::S23_22 },
2310 { 167U, Hexagon::WR6 },
2311 { 168U, Hexagon::S25_24 },
2312 { 169U, Hexagon::WR8 },
2313 { 170U, Hexagon::S27_26 },
2314 { 171U, Hexagon::WR10 },
2315 { 172U, Hexagon::S29_28 },
2316 { 173U, Hexagon::WR12 },
2317 { 174U, Hexagon::S31_30 },
2318 { 175U, Hexagon::WR14 },
2319 { 176U, Hexagon::S33_32 },
2320 { 177U, Hexagon::ISDBCFG0 },
2321 { 178U, Hexagon::S35_34 },
2322 { 179U, Hexagon::S35 },
2323 { 180U, Hexagon::S37_36 },
2324 { 181U, Hexagon::BRKPTCFG0 },
2325 { 182U, Hexagon::S39_38 },
2326 { 183U, Hexagon::BRKPTCFG1 },
2327 { 184U, Hexagon::S41_40 },
2328 { 185U, Hexagon::ISDBMBXOUT },
2329 { 186U, Hexagon::S43_42 },
2330 { 187U, Hexagon::ISDBGPR },
2331 { 188U, Hexagon::S45_44 },
2332 { 189U, Hexagon::S45 },
2333 { 190U, Hexagon::S47_46 },
2334 { 191U, Hexagon::S47 },
2335 { 192U, Hexagon::S49_48 },
2336 { 193U, Hexagon::PMUCNT1 },
2337 { 194U, Hexagon::S51_50 },
2338 { 195U, Hexagon::PMUCNT3 },
2339 { 196U, Hexagon::S53_52 },
2340 { 197U, Hexagon::PMUCFG },
2341 { 198U, Hexagon::S55_54 },
2342 { 199U, Hexagon::S55 },
2343 { 200U, Hexagon::S57_56 },
2344 { 201U, Hexagon::S57 },
2345 { 202U, Hexagon::S59_58 },
2346 { 203U, Hexagon::S59 },
2347 { 204U, Hexagon::S61_60 },
2348 { 205U, Hexagon::S61 },
2349 { 206U, Hexagon::S63_62 },
2350 { 207U, Hexagon::S63 },
2351 { 208U, Hexagon::S65_64 },
2352 { 209U, Hexagon::S65 },
2353 { 210U, Hexagon::S67_66 },
2354 { 211U, Hexagon::S67 },
2355 { 212U, Hexagon::S69_68 },
2356 { 213U, Hexagon::S69 },
2357 { 214U, Hexagon::S71_70 },
2358 { 215U, Hexagon::S71 },
2359 { 216U, Hexagon::S73_72 },
2360 { 217U, Hexagon::S73 },
2361 { 218U, Hexagon::S75_74 },
2362 { 219U, Hexagon::S77_76 },
2363 { 220U, Hexagon::S79_78 },
2364 { 221U, Hexagon::S77 },
2365 { 222U, Hexagon::G3_2 },
2366 { 223U, Hexagon::S79 },
2367 { 224U, Hexagon::G5_4 },
2368 { 225U, Hexagon::G5 },
2369 { 226U, Hexagon::G7_6 },
2370 { 227U, Hexagon::G7 },
2371 { 228U, Hexagon::G9_8 },
2372 { 229U, Hexagon::G9 },
2373 { 230U, Hexagon::G11_10 },
2374 { 231U, Hexagon::G11 },
2375 { 232U, Hexagon::G13_12 },
2376 { 233U, Hexagon::G13 },
2377 { 234U, Hexagon::G15_14 },
2378 { 235U, Hexagon::G15 },
2379 { 236U, Hexagon::G17_16 },
2380 { 237U, Hexagon::GPMUCNT5 },
2381 { 238U, Hexagon::G19_18 },
2382 { 239U, Hexagon::GPMUCNT7 },
2383 { 240U, Hexagon::G21_20 },
2384 { 241U, Hexagon::G21 },
2385 { 242U, Hexagon::G23_22 },
2386 { 243U, Hexagon::G23 },
2387 { 244U, Hexagon::G25_24 },
2388 { 245U, Hexagon::GPCYCLEHI },
2389 { 246U, Hexagon::G27_26 },
2390 { 247U, Hexagon::GPMUCNT1 },
2391 { 248U, Hexagon::G29_28 },
2392 { 249U, Hexagon::GPMUCNT3 },
2393 { 250U, Hexagon::G31_30 },
2394 { 251U, Hexagon::G31 },
2395 { 252U, Hexagon::VQ0 },
2396 { 253U, Hexagon::VQ1 },
2397 { 254U, Hexagon::VQ2 },
2398 { 255U, Hexagon::VQ3 },
2399 { 256U, Hexagon::VQ4 },
2400 { 257U, Hexagon::VQ5 },
2401 { 258U, Hexagon::VQ6 },
2402 { 259U, Hexagon::VQ7 },
2403 { 999999U, Hexagon::VF0 },
2404 { 1000000U, Hexagon::VF1 },
2405 { 1000001U, Hexagon::VF2 },
2406 { 1000002U, Hexagon::VF3 },
2407 { 1000003U, Hexagon::VF4 },
2408 { 1000004U, Hexagon::VF5 },
2409 { 1000005U, Hexagon::VF6 },
2410 { 1000006U, Hexagon::VF7 },
2411 { 1000007U, Hexagon::VF8 },
2412 { 1000008U, Hexagon::VF9 },
2413 { 1000009U, Hexagon::VF10 },
2414 { 1000010U, Hexagon::VF11 },
2415 { 1000011U, Hexagon::VF12 },
2416 { 1000012U, Hexagon::VF13 },
2417 { 1000013U, Hexagon::VF14 },
2418 { 1000014U, Hexagon::VF15 },
2419 { 1000015U, Hexagon::VF16 },
2420 { 1000016U, Hexagon::VF17 },
2421 { 1000017U, Hexagon::VF18 },
2422 { 1000018U, Hexagon::VF19 },
2423 { 1000019U, Hexagon::VF20 },
2424 { 1000020U, Hexagon::VF21 },
2425 { 1000021U, Hexagon::VF22 },
2426 { 1000022U, Hexagon::VF23 },
2427 { 1000023U, Hexagon::VF24 },
2428 { 1000024U, Hexagon::VF25 },
2429 { 1000025U, Hexagon::VF26 },
2430 { 1000026U, Hexagon::VF27 },
2431 { 1000027U, Hexagon::VF28 },
2432 { 1000028U, Hexagon::VF29 },
2433 { 1000029U, Hexagon::VF30 },
2434 { 1000030U, Hexagon::VF31 },
2435 { 9999999U, Hexagon::VFR0 },
2436 { 10000000U, Hexagon::VFR1 },
2437 { 10000001U, Hexagon::VFR2 },
2438 { 10000002U, Hexagon::VFR3 },
2439 { 10000003U, Hexagon::VFR4 },
2440 { 10000004U, Hexagon::VFR5 },
2441 { 10000005U, Hexagon::VFR6 },
2442 { 10000006U, Hexagon::VFR7 },
2443 { 10000007U, Hexagon::VFR8 },
2444 { 10000008U, Hexagon::VFR9 },
2445 { 10000009U, Hexagon::VFR10 },
2446 { 10000010U, Hexagon::VFR11 },
2447 { 10000011U, Hexagon::VFR12 },
2448 { 10000012U, Hexagon::VFR13 },
2449 { 10000013U, Hexagon::VFR14 },
2450 { 10000014U, Hexagon::VFR15 },
2451 { 10000015U, Hexagon::VFR16 },
2452 { 10000016U, Hexagon::VFR17 },
2453 { 10000017U, Hexagon::VFR18 },
2454 { 10000018U, Hexagon::VFR19 },
2455 { 10000019U, Hexagon::VFR20 },
2456 { 10000020U, Hexagon::VFR21 },
2457 { 10000021U, Hexagon::VFR22 },
2458 { 10000022U, Hexagon::VFR23 },
2459 { 10000023U, Hexagon::VFR24 },
2460 { 10000024U, Hexagon::VFR25 },
2461 { 10000025U, Hexagon::VFR26 },
2462 { 10000026U, Hexagon::VFR27 },
2463 { 10000027U, Hexagon::VFR28 },
2464 { 10000028U, Hexagon::VFR29 },
2465 { 10000029U, Hexagon::VFR30 },
2466 { 10000030U, Hexagon::VFR31 },
2467};
2468extern const unsigned HexagonDwarfFlavour0Dwarf2LSize = std::size(HexagonDwarfFlavour0Dwarf2L);
2469
2470extern const MCRegisterInfo::DwarfLLVMRegPair HexagonEHFlavour0Dwarf2L[] = {
2471 { 0U, Hexagon::R0 },
2472 { 1U, Hexagon::R1 },
2473 { 2U, Hexagon::R2 },
2474 { 3U, Hexagon::R3 },
2475 { 4U, Hexagon::R4 },
2476 { 5U, Hexagon::R5 },
2477 { 6U, Hexagon::R6 },
2478 { 7U, Hexagon::R7 },
2479 { 8U, Hexagon::R8 },
2480 { 9U, Hexagon::R9 },
2481 { 10U, Hexagon::R10 },
2482 { 11U, Hexagon::R11 },
2483 { 12U, Hexagon::R12 },
2484 { 13U, Hexagon::R13 },
2485 { 14U, Hexagon::R14 },
2486 { 15U, Hexagon::R15 },
2487 { 16U, Hexagon::R16 },
2488 { 17U, Hexagon::R17 },
2489 { 18U, Hexagon::R18 },
2490 { 19U, Hexagon::R19 },
2491 { 20U, Hexagon::R20 },
2492 { 21U, Hexagon::R21 },
2493 { 22U, Hexagon::R22 },
2494 { 23U, Hexagon::R23 },
2495 { 24U, Hexagon::R24 },
2496 { 25U, Hexagon::R25 },
2497 { 26U, Hexagon::R26 },
2498 { 27U, Hexagon::R27 },
2499 { 28U, Hexagon::R28 },
2500 { 29U, Hexagon::R29 },
2501 { 30U, Hexagon::R30 },
2502 { 31U, Hexagon::R31 },
2503 { 32U, Hexagon::D0 },
2504 { 34U, Hexagon::D1 },
2505 { 36U, Hexagon::D2 },
2506 { 38U, Hexagon::D3 },
2507 { 40U, Hexagon::D4 },
2508 { 42U, Hexagon::D5 },
2509 { 44U, Hexagon::D6 },
2510 { 46U, Hexagon::D7 },
2511 { 48U, Hexagon::D8 },
2512 { 50U, Hexagon::D9 },
2513 { 52U, Hexagon::D10 },
2514 { 54U, Hexagon::D11 },
2515 { 56U, Hexagon::D12 },
2516 { 58U, Hexagon::D13 },
2517 { 60U, Hexagon::D14 },
2518 { 62U, Hexagon::D15 },
2519 { 63U, Hexagon::P0 },
2520 { 64U, Hexagon::P1 },
2521 { 65U, Hexagon::P2 },
2522 { 66U, Hexagon::P3 },
2523 { 67U, Hexagon::C1_0 },
2524 { 68U, Hexagon::LC0 },
2525 { 69U, Hexagon::C3_2 },
2526 { 70U, Hexagon::LC1 },
2527 { 71U, Hexagon::P3_0 },
2528 { 72U, Hexagon::C7_6 },
2529 { 73U, Hexagon::M0 },
2530 { 74U, Hexagon::C9_8 },
2531 { 75U, Hexagon::C8 },
2532 { 76U, Hexagon::C11_10 },
2533 { 77U, Hexagon::UGP },
2534 { 78U, Hexagon::GP },
2535 { 79U, Hexagon::CS0 },
2536 { 80U, Hexagon::CS1 },
2537 { 81U, Hexagon::UPCYCLELO },
2538 { 82U, Hexagon::UPCYCLEHI },
2539 { 83U, Hexagon::C17_16 },
2540 { 84U, Hexagon::FRAMEKEY },
2541 { 85U, Hexagon::PKTCOUNTLO },
2542 { 86U, Hexagon::PKTCOUNTHI },
2543 { 97U, Hexagon::UTIMERLO },
2544 { 98U, Hexagon::UTIMERHI },
2545 { 99U, Hexagon::W0 },
2546 { 100U, Hexagon::V1 },
2547 { 101U, Hexagon::W1 },
2548 { 102U, Hexagon::V3 },
2549 { 103U, Hexagon::W2 },
2550 { 104U, Hexagon::V5 },
2551 { 105U, Hexagon::W3 },
2552 { 106U, Hexagon::V7 },
2553 { 107U, Hexagon::W4 },
2554 { 108U, Hexagon::V9 },
2555 { 109U, Hexagon::W5 },
2556 { 110U, Hexagon::V11 },
2557 { 111U, Hexagon::W6 },
2558 { 112U, Hexagon::V13 },
2559 { 113U, Hexagon::W7 },
2560 { 114U, Hexagon::V15 },
2561 { 115U, Hexagon::W8 },
2562 { 116U, Hexagon::V17 },
2563 { 117U, Hexagon::W9 },
2564 { 118U, Hexagon::V19 },
2565 { 119U, Hexagon::W10 },
2566 { 120U, Hexagon::V21 },
2567 { 121U, Hexagon::W11 },
2568 { 122U, Hexagon::V23 },
2569 { 123U, Hexagon::W12 },
2570 { 124U, Hexagon::V25 },
2571 { 125U, Hexagon::W13 },
2572 { 126U, Hexagon::V27 },
2573 { 127U, Hexagon::W14 },
2574 { 128U, Hexagon::V29 },
2575 { 129U, Hexagon::W15 },
2576 { 130U, Hexagon::V31 },
2577 { 131U, Hexagon::Q0 },
2578 { 132U, Hexagon::Q1 },
2579 { 133U, Hexagon::Q2 },
2580 { 134U, Hexagon::Q3 },
2581 { 144U, Hexagon::SGP1_0 },
2582 { 145U, Hexagon::SGP1 },
2583 { 146U, Hexagon::S3_2 },
2584 { 147U, Hexagon::ELR },
2585 { 148U, Hexagon::S5_4 },
2586 { 149U, Hexagon::BADVA1 },
2587 { 150U, Hexagon::S7_6 },
2588 { 151U, Hexagon::CCR },
2589 { 152U, Hexagon::S9_8 },
2590 { 153U, Hexagon::BADVA },
2591 { 154U, Hexagon::S11_10 },
2592 { 155U, Hexagon::S11 },
2593 { 156U, Hexagon::S13_12 },
2594 { 157U, Hexagon::S13 },
2595 { 158U, Hexagon::S15_14 },
2596 { 159U, Hexagon::S15 },
2597 { 160U, Hexagon::S17_16 },
2598 { 161U, Hexagon::WR0 },
2599 { 162U, Hexagon::S19_18 },
2600 { 163U, Hexagon::WR2 },
2601 { 164U, Hexagon::S21_20 },
2602 { 165U, Hexagon::WR4 },
2603 { 166U, Hexagon::S23_22 },
2604 { 167U, Hexagon::WR6 },
2605 { 168U, Hexagon::S25_24 },
2606 { 169U, Hexagon::WR8 },
2607 { 170U, Hexagon::S27_26 },
2608 { 171U, Hexagon::WR10 },
2609 { 172U, Hexagon::S29_28 },
2610 { 173U, Hexagon::WR12 },
2611 { 174U, Hexagon::S31_30 },
2612 { 175U, Hexagon::WR14 },
2613 { 176U, Hexagon::S33_32 },
2614 { 177U, Hexagon::ISDBCFG0 },
2615 { 178U, Hexagon::S35_34 },
2616 { 179U, Hexagon::S35 },
2617 { 180U, Hexagon::S37_36 },
2618 { 181U, Hexagon::BRKPTCFG0 },
2619 { 182U, Hexagon::S39_38 },
2620 { 183U, Hexagon::BRKPTCFG1 },
2621 { 184U, Hexagon::S41_40 },
2622 { 185U, Hexagon::ISDBMBXOUT },
2623 { 186U, Hexagon::S43_42 },
2624 { 187U, Hexagon::ISDBGPR },
2625 { 188U, Hexagon::S45_44 },
2626 { 189U, Hexagon::S45 },
2627 { 190U, Hexagon::S47_46 },
2628 { 191U, Hexagon::S47 },
2629 { 192U, Hexagon::S49_48 },
2630 { 193U, Hexagon::PMUCNT1 },
2631 { 194U, Hexagon::S51_50 },
2632 { 195U, Hexagon::PMUCNT3 },
2633 { 196U, Hexagon::S53_52 },
2634 { 197U, Hexagon::PMUCFG },
2635 { 198U, Hexagon::S55_54 },
2636 { 199U, Hexagon::S55 },
2637 { 200U, Hexagon::S57_56 },
2638 { 201U, Hexagon::S57 },
2639 { 202U, Hexagon::S59_58 },
2640 { 203U, Hexagon::S59 },
2641 { 204U, Hexagon::S61_60 },
2642 { 205U, Hexagon::S61 },
2643 { 206U, Hexagon::S63_62 },
2644 { 207U, Hexagon::S63 },
2645 { 208U, Hexagon::S65_64 },
2646 { 209U, Hexagon::S65 },
2647 { 210U, Hexagon::S67_66 },
2648 { 211U, Hexagon::S67 },
2649 { 212U, Hexagon::S69_68 },
2650 { 213U, Hexagon::S69 },
2651 { 214U, Hexagon::S71_70 },
2652 { 215U, Hexagon::S71 },
2653 { 216U, Hexagon::S73_72 },
2654 { 217U, Hexagon::S73 },
2655 { 218U, Hexagon::S75_74 },
2656 { 219U, Hexagon::S77_76 },
2657 { 220U, Hexagon::S79_78 },
2658 { 221U, Hexagon::S77 },
2659 { 222U, Hexagon::G3_2 },
2660 { 223U, Hexagon::S79 },
2661 { 224U, Hexagon::G5_4 },
2662 { 225U, Hexagon::G5 },
2663 { 226U, Hexagon::G7_6 },
2664 { 227U, Hexagon::G7 },
2665 { 228U, Hexagon::G9_8 },
2666 { 229U, Hexagon::G9 },
2667 { 230U, Hexagon::G11_10 },
2668 { 231U, Hexagon::G11 },
2669 { 232U, Hexagon::G13_12 },
2670 { 233U, Hexagon::G13 },
2671 { 234U, Hexagon::G15_14 },
2672 { 235U, Hexagon::G15 },
2673 { 236U, Hexagon::G17_16 },
2674 { 237U, Hexagon::GPMUCNT5 },
2675 { 238U, Hexagon::G19_18 },
2676 { 239U, Hexagon::GPMUCNT7 },
2677 { 240U, Hexagon::G21_20 },
2678 { 241U, Hexagon::G21 },
2679 { 242U, Hexagon::G23_22 },
2680 { 243U, Hexagon::G23 },
2681 { 244U, Hexagon::G25_24 },
2682 { 245U, Hexagon::GPCYCLEHI },
2683 { 246U, Hexagon::G27_26 },
2684 { 247U, Hexagon::GPMUCNT1 },
2685 { 248U, Hexagon::G29_28 },
2686 { 249U, Hexagon::GPMUCNT3 },
2687 { 250U, Hexagon::G31_30 },
2688 { 251U, Hexagon::G31 },
2689 { 252U, Hexagon::VQ0 },
2690 { 253U, Hexagon::VQ1 },
2691 { 254U, Hexagon::VQ2 },
2692 { 255U, Hexagon::VQ3 },
2693 { 256U, Hexagon::VQ4 },
2694 { 257U, Hexagon::VQ5 },
2695 { 258U, Hexagon::VQ6 },
2696 { 259U, Hexagon::VQ7 },
2697 { 999999U, Hexagon::VF0 },
2698 { 1000000U, Hexagon::VF1 },
2699 { 1000001U, Hexagon::VF2 },
2700 { 1000002U, Hexagon::VF3 },
2701 { 1000003U, Hexagon::VF4 },
2702 { 1000004U, Hexagon::VF5 },
2703 { 1000005U, Hexagon::VF6 },
2704 { 1000006U, Hexagon::VF7 },
2705 { 1000007U, Hexagon::VF8 },
2706 { 1000008U, Hexagon::VF9 },
2707 { 1000009U, Hexagon::VF10 },
2708 { 1000010U, Hexagon::VF11 },
2709 { 1000011U, Hexagon::VF12 },
2710 { 1000012U, Hexagon::VF13 },
2711 { 1000013U, Hexagon::VF14 },
2712 { 1000014U, Hexagon::VF15 },
2713 { 1000015U, Hexagon::VF16 },
2714 { 1000016U, Hexagon::VF17 },
2715 { 1000017U, Hexagon::VF18 },
2716 { 1000018U, Hexagon::VF19 },
2717 { 1000019U, Hexagon::VF20 },
2718 { 1000020U, Hexagon::VF21 },
2719 { 1000021U, Hexagon::VF22 },
2720 { 1000022U, Hexagon::VF23 },
2721 { 1000023U, Hexagon::VF24 },
2722 { 1000024U, Hexagon::VF25 },
2723 { 1000025U, Hexagon::VF26 },
2724 { 1000026U, Hexagon::VF27 },
2725 { 1000027U, Hexagon::VF28 },
2726 { 1000028U, Hexagon::VF29 },
2727 { 1000029U, Hexagon::VF30 },
2728 { 1000030U, Hexagon::VF31 },
2729 { 9999999U, Hexagon::VFR0 },
2730 { 10000000U, Hexagon::VFR1 },
2731 { 10000001U, Hexagon::VFR2 },
2732 { 10000002U, Hexagon::VFR3 },
2733 { 10000003U, Hexagon::VFR4 },
2734 { 10000004U, Hexagon::VFR5 },
2735 { 10000005U, Hexagon::VFR6 },
2736 { 10000006U, Hexagon::VFR7 },
2737 { 10000007U, Hexagon::VFR8 },
2738 { 10000008U, Hexagon::VFR9 },
2739 { 10000009U, Hexagon::VFR10 },
2740 { 10000010U, Hexagon::VFR11 },
2741 { 10000011U, Hexagon::VFR12 },
2742 { 10000012U, Hexagon::VFR13 },
2743 { 10000013U, Hexagon::VFR14 },
2744 { 10000014U, Hexagon::VFR15 },
2745 { 10000015U, Hexagon::VFR16 },
2746 { 10000016U, Hexagon::VFR17 },
2747 { 10000017U, Hexagon::VFR18 },
2748 { 10000018U, Hexagon::VFR19 },
2749 { 10000019U, Hexagon::VFR20 },
2750 { 10000020U, Hexagon::VFR21 },
2751 { 10000021U, Hexagon::VFR22 },
2752 { 10000022U, Hexagon::VFR23 },
2753 { 10000023U, Hexagon::VFR24 },
2754 { 10000024U, Hexagon::VFR25 },
2755 { 10000025U, Hexagon::VFR26 },
2756 { 10000026U, Hexagon::VFR27 },
2757 { 10000027U, Hexagon::VFR28 },
2758 { 10000028U, Hexagon::VFR29 },
2759 { 10000029U, Hexagon::VFR30 },
2760 { 10000030U, Hexagon::VFR31 },
2761};
2762extern const unsigned HexagonEHFlavour0Dwarf2LSize = std::size(HexagonEHFlavour0Dwarf2L);
2763
2764extern const MCRegisterInfo::DwarfLLVMRegPair HexagonDwarfFlavour0L2Dwarf[] = {
2765 { Hexagon::BADVA, 153U },
2766 { Hexagon::CCR, 151U },
2767 { Hexagon::CFGBASE, 171U },
2768 { Hexagon::CS, 78U },
2769 { Hexagon::DIAG, 172U },
2770 { Hexagon::ELR, 147U },
2771 { Hexagon::EVB, 160U },
2772 { Hexagon::FRAMEKEY, 84U },
2773 { Hexagon::FRAMELIMIT, 83U },
2774 { Hexagon::GELR, 220U },
2775 { Hexagon::GOSP, 222U },
2776 { Hexagon::GP, 78U },
2777 { Hexagon::GPCYCLEHI, 245U },
2778 { Hexagon::GPCYCLELO, 244U },
2779 { Hexagon::GSR, 221U },
2780 { Hexagon::HTID, 152U },
2781 { Hexagon::IMASK, 154U },
2782 { Hexagon::ISDBEN, 186U },
2783 { Hexagon::ISDBGPR, 187U },
2784 { Hexagon::ISDBMBXIN, 184U },
2785 { Hexagon::ISDBMBXOUT, 185U },
2786 { Hexagon::ISDBST, 176U },
2787 { Hexagon::MODECTL, 161U },
2788 { Hexagon::PC, 76U },
2789 { Hexagon::PCYCLEHI, 175U },
2790 { Hexagon::PCYCLELO, 174U },
2791 { Hexagon::PKTCOUNT, 85U },
2792 { Hexagon::PKTCOUNTHI, 86U },
2793 { Hexagon::PKTCOUNTLO, 85U },
2794 { Hexagon::PMUCFG, 197U },
2795 { Hexagon::PMUEVTCFG, 196U },
2796 { Hexagon::REV, 173U },
2797 { Hexagon::SSR, 150U },
2798 { Hexagon::STID, 146U },
2799 { Hexagon::SYSCFG, 162U },
2800 { Hexagon::UGP, 77U },
2801 { Hexagon::UPCYCLE, 80U },
2802 { Hexagon::UPCYCLEHI, 82U },
2803 { Hexagon::UPCYCLELO, 81U },
2804 { Hexagon::USR, 75U },
2805 { Hexagon::UTIMER, 97U },
2806 { Hexagon::UTIMERHI, 98U },
2807 { Hexagon::UTIMERLO, 97U },
2808 { Hexagon::VID, 165U },
2809 { Hexagon::VTMP, 131U },
2810 { Hexagon::BADVA0, 148U },
2811 { Hexagon::BADVA1, 149U },
2812 { Hexagon::BRKPTCFG0, 181U },
2813 { Hexagon::BRKPTCFG1, 183U },
2814 { Hexagon::BRKPTPC0, 180U },
2815 { Hexagon::BRKPTPC1, 182U },
2816 { Hexagon::C5, 72U },
2817 { Hexagon::C8, 75U },
2818 { Hexagon::CS0, 79U },
2819 { Hexagon::CS1, 80U },
2820 { Hexagon::D0, 32U },
2821 { Hexagon::D1, 34U },
2822 { Hexagon::D2, 36U },
2823 { Hexagon::D3, 38U },
2824 { Hexagon::D4, 40U },
2825 { Hexagon::D5, 42U },
2826 { Hexagon::D6, 44U },
2827 { Hexagon::D7, 46U },
2828 { Hexagon::D8, 48U },
2829 { Hexagon::D9, 50U },
2830 { Hexagon::D10, 52U },
2831 { Hexagon::D11, 54U },
2832 { Hexagon::D12, 56U },
2833 { Hexagon::D13, 58U },
2834 { Hexagon::D14, 60U },
2835 { Hexagon::D15, 62U },
2836 { Hexagon::G3, 223U },
2837 { Hexagon::G4, 224U },
2838 { Hexagon::G5, 225U },
2839 { Hexagon::G6, 226U },
2840 { Hexagon::G7, 227U },
2841 { Hexagon::G8, 228U },
2842 { Hexagon::G9, 229U },
2843 { Hexagon::G10, 230U },
2844 { Hexagon::G11, 231U },
2845 { Hexagon::G12, 232U },
2846 { Hexagon::G13, 233U },
2847 { Hexagon::G14, 234U },
2848 { Hexagon::G15, 235U },
2849 { Hexagon::G20, 240U },
2850 { Hexagon::G21, 241U },
2851 { Hexagon::G22, 242U },
2852 { Hexagon::G23, 243U },
2853 { Hexagon::G30, 250U },
2854 { Hexagon::G31, 251U },
2855 { Hexagon::GPMUCNT0, 246U },
2856 { Hexagon::GPMUCNT1, 247U },
2857 { Hexagon::GPMUCNT2, 248U },
2858 { Hexagon::GPMUCNT3, 249U },
2859 { Hexagon::GPMUCNT4, 236U },
2860 { Hexagon::GPMUCNT5, 237U },
2861 { Hexagon::GPMUCNT6, 238U },
2862 { Hexagon::GPMUCNT7, 239U },
2863 { Hexagon::ISDBCFG0, 177U },
2864 { Hexagon::ISDBCFG1, 178U },
2865 { Hexagon::LC0, 68U },
2866 { Hexagon::LC1, 70U },
2867 { Hexagon::M0, 73U },
2868 { Hexagon::M1, 74U },
2869 { Hexagon::P0, 63U },
2870 { Hexagon::P1, 64U },
2871 { Hexagon::P2, 65U },
2872 { Hexagon::P3, 66U },
2873 { Hexagon::PMUCNT0, 192U },
2874 { Hexagon::PMUCNT1, 193U },
2875 { Hexagon::PMUCNT2, 194U },
2876 { Hexagon::PMUCNT3, 195U },
2877 { Hexagon::Q0, 131U },
2878 { Hexagon::Q1, 132U },
2879 { Hexagon::Q2, 133U },
2880 { Hexagon::Q3, 134U },
2881 { Hexagon::R0, 0U },
2882 { Hexagon::R1, 1U },
2883 { Hexagon::R2, 2U },
2884 { Hexagon::R3, 3U },
2885 { Hexagon::R4, 4U },
2886 { Hexagon::R5, 5U },
2887 { Hexagon::R6, 6U },
2888 { Hexagon::R7, 7U },
2889 { Hexagon::R8, 8U },
2890 { Hexagon::R9, 9U },
2891 { Hexagon::R10, 10U },
2892 { Hexagon::R11, 11U },
2893 { Hexagon::R12, 12U },
2894 { Hexagon::R13, 13U },
2895 { Hexagon::R14, 14U },
2896 { Hexagon::R15, 15U },
2897 { Hexagon::R16, 16U },
2898 { Hexagon::R17, 17U },
2899 { Hexagon::R18, 18U },
2900 { Hexagon::R19, 19U },
2901 { Hexagon::R20, 20U },
2902 { Hexagon::R21, 21U },
2903 { Hexagon::R22, 22U },
2904 { Hexagon::R23, 23U },
2905 { Hexagon::R24, 24U },
2906 { Hexagon::R25, 25U },
2907 { Hexagon::R26, 26U },
2908 { Hexagon::R27, 27U },
2909 { Hexagon::R28, 28U },
2910 { Hexagon::R29, 29U },
2911 { Hexagon::R30, 30U },
2912 { Hexagon::R31, 31U },
2913 { Hexagon::S11, 155U },
2914 { Hexagon::S12, 156U },
2915 { Hexagon::S13, 157U },
2916 { Hexagon::S14, 158U },
2917 { Hexagon::S15, 159U },
2918 { Hexagon::S19, 163U },
2919 { Hexagon::S20, 164U },
2920 { Hexagon::S22, 166U },
2921 { Hexagon::S23, 167U },
2922 { Hexagon::S24, 168U },
2923 { Hexagon::S25, 169U },
2924 { Hexagon::S26, 170U },
2925 { Hexagon::S35, 179U },
2926 { Hexagon::S44, 188U },
2927 { Hexagon::S45, 189U },
2928 { Hexagon::S46, 190U },
2929 { Hexagon::S47, 191U },
2930 { Hexagon::S54, 198U },
2931 { Hexagon::S55, 199U },
2932 { Hexagon::S56, 200U },
2933 { Hexagon::S57, 201U },
2934 { Hexagon::S58, 202U },
2935 { Hexagon::S59, 203U },
2936 { Hexagon::S60, 204U },
2937 { Hexagon::S61, 205U },
2938 { Hexagon::S62, 206U },
2939 { Hexagon::S63, 207U },
2940 { Hexagon::S64, 208U },
2941 { Hexagon::S65, 209U },
2942 { Hexagon::S66, 210U },
2943 { Hexagon::S67, 211U },
2944 { Hexagon::S68, 212U },
2945 { Hexagon::S69, 213U },
2946 { Hexagon::S70, 214U },
2947 { Hexagon::S71, 215U },
2948 { Hexagon::S72, 216U },
2949 { Hexagon::S73, 217U },
2950 { Hexagon::S74, 218U },
2951 { Hexagon::S75, 219U },
2952 { Hexagon::S76, 220U },
2953 { Hexagon::S77, 221U },
2954 { Hexagon::S78, 222U },
2955 { Hexagon::S79, 223U },
2956 { Hexagon::S80, 224U },
2957 { Hexagon::SA0, 67U },
2958 { Hexagon::SA1, 69U },
2959 { Hexagon::SGP0, 144U },
2960 { Hexagon::SGP1, 145U },
2961 { Hexagon::V0, 99U },
2962 { Hexagon::V1, 100U },
2963 { Hexagon::V2, 101U },
2964 { Hexagon::V3, 102U },
2965 { Hexagon::V4, 103U },
2966 { Hexagon::V5, 104U },
2967 { Hexagon::V6, 105U },
2968 { Hexagon::V7, 106U },
2969 { Hexagon::V8, 107U },
2970 { Hexagon::V9, 108U },
2971 { Hexagon::V10, 109U },
2972 { Hexagon::V11, 110U },
2973 { Hexagon::V12, 111U },
2974 { Hexagon::V13, 112U },
2975 { Hexagon::V14, 113U },
2976 { Hexagon::V15, 114U },
2977 { Hexagon::V16, 115U },
2978 { Hexagon::V17, 116U },
2979 { Hexagon::V18, 117U },
2980 { Hexagon::V19, 118U },
2981 { Hexagon::V20, 119U },
2982 { Hexagon::V21, 120U },
2983 { Hexagon::V22, 121U },
2984 { Hexagon::V23, 122U },
2985 { Hexagon::V24, 123U },
2986 { Hexagon::V25, 124U },
2987 { Hexagon::V26, 125U },
2988 { Hexagon::V27, 126U },
2989 { Hexagon::V28, 127U },
2990 { Hexagon::V29, 128U },
2991 { Hexagon::V30, 129U },
2992 { Hexagon::V31, 130U },
2993 { Hexagon::VF0, 999999U },
2994 { Hexagon::VF1, 1000000U },
2995 { Hexagon::VF2, 1000001U },
2996 { Hexagon::VF3, 1000002U },
2997 { Hexagon::VF4, 1000003U },
2998 { Hexagon::VF5, 1000004U },
2999 { Hexagon::VF6, 1000005U },
3000 { Hexagon::VF7, 1000006U },
3001 { Hexagon::VF8, 1000007U },
3002 { Hexagon::VF9, 1000008U },
3003 { Hexagon::VF10, 1000009U },
3004 { Hexagon::VF11, 1000010U },
3005 { Hexagon::VF12, 1000011U },
3006 { Hexagon::VF13, 1000012U },
3007 { Hexagon::VF14, 1000013U },
3008 { Hexagon::VF15, 1000014U },
3009 { Hexagon::VF16, 1000015U },
3010 { Hexagon::VF17, 1000016U },
3011 { Hexagon::VF18, 1000017U },
3012 { Hexagon::VF19, 1000018U },
3013 { Hexagon::VF20, 1000019U },
3014 { Hexagon::VF21, 1000020U },
3015 { Hexagon::VF22, 1000021U },
3016 { Hexagon::VF23, 1000022U },
3017 { Hexagon::VF24, 1000023U },
3018 { Hexagon::VF25, 1000024U },
3019 { Hexagon::VF26, 1000025U },
3020 { Hexagon::VF27, 1000026U },
3021 { Hexagon::VF28, 1000027U },
3022 { Hexagon::VF29, 1000028U },
3023 { Hexagon::VF30, 1000029U },
3024 { Hexagon::VF31, 1000030U },
3025 { Hexagon::VFR0, 9999999U },
3026 { Hexagon::VFR1, 10000000U },
3027 { Hexagon::VFR2, 10000001U },
3028 { Hexagon::VFR3, 10000002U },
3029 { Hexagon::VFR4, 10000003U },
3030 { Hexagon::VFR5, 10000004U },
3031 { Hexagon::VFR6, 10000005U },
3032 { Hexagon::VFR7, 10000006U },
3033 { Hexagon::VFR8, 10000007U },
3034 { Hexagon::VFR9, 10000008U },
3035 { Hexagon::VFR10, 10000009U },
3036 { Hexagon::VFR11, 10000010U },
3037 { Hexagon::VFR12, 10000011U },
3038 { Hexagon::VFR13, 10000012U },
3039 { Hexagon::VFR14, 10000013U },
3040 { Hexagon::VFR15, 10000014U },
3041 { Hexagon::VFR16, 10000015U },
3042 { Hexagon::VFR17, 10000016U },
3043 { Hexagon::VFR18, 10000017U },
3044 { Hexagon::VFR19, 10000018U },
3045 { Hexagon::VFR20, 10000019U },
3046 { Hexagon::VFR21, 10000020U },
3047 { Hexagon::VFR22, 10000021U },
3048 { Hexagon::VFR23, 10000022U },
3049 { Hexagon::VFR24, 10000023U },
3050 { Hexagon::VFR25, 10000024U },
3051 { Hexagon::VFR26, 10000025U },
3052 { Hexagon::VFR27, 10000026U },
3053 { Hexagon::VFR28, 10000027U },
3054 { Hexagon::VFR29, 10000028U },
3055 { Hexagon::VFR30, 10000029U },
3056 { Hexagon::VFR31, 10000030U },
3057 { Hexagon::VQ0, 252U },
3058 { Hexagon::VQ1, 253U },
3059 { Hexagon::VQ2, 254U },
3060 { Hexagon::VQ3, 255U },
3061 { Hexagon::VQ4, 256U },
3062 { Hexagon::VQ5, 257U },
3063 { Hexagon::VQ6, 258U },
3064 { Hexagon::VQ7, 259U },
3065 { Hexagon::W0, 99U },
3066 { Hexagon::W1, 101U },
3067 { Hexagon::W2, 103U },
3068 { Hexagon::W3, 105U },
3069 { Hexagon::W4, 107U },
3070 { Hexagon::W5, 109U },
3071 { Hexagon::W6, 111U },
3072 { Hexagon::W7, 113U },
3073 { Hexagon::W8, 115U },
3074 { Hexagon::W9, 117U },
3075 { Hexagon::W10, 119U },
3076 { Hexagon::W11, 121U },
3077 { Hexagon::W12, 123U },
3078 { Hexagon::W13, 125U },
3079 { Hexagon::W14, 127U },
3080 { Hexagon::W15, 129U },
3081 { Hexagon::WR0, 161U },
3082 { Hexagon::WR1, 162U },
3083 { Hexagon::WR2, 163U },
3084 { Hexagon::WR3, 164U },
3085 { Hexagon::WR4, 165U },
3086 { Hexagon::WR5, 166U },
3087 { Hexagon::WR6, 167U },
3088 { Hexagon::WR7, 168U },
3089 { Hexagon::WR8, 169U },
3090 { Hexagon::WR9, 170U },
3091 { Hexagon::WR10, 171U },
3092 { Hexagon::WR11, 172U },
3093 { Hexagon::WR12, 173U },
3094 { Hexagon::WR13, 174U },
3095 { Hexagon::WR14, 175U },
3096 { Hexagon::WR15, 176U },
3097 { Hexagon::C1_0, 67U },
3098 { Hexagon::C3_2, 69U },
3099 { Hexagon::C5_4, 71U },
3100 { Hexagon::C7_6, 72U },
3101 { Hexagon::C9_8, 74U },
3102 { Hexagon::C11_10, 76U },
3103 { Hexagon::C17_16, 83U },
3104 { Hexagon::G1_0, 220U },
3105 { Hexagon::G3_2, 222U },
3106 { Hexagon::G5_4, 224U },
3107 { Hexagon::G7_6, 226U },
3108 { Hexagon::G9_8, 228U },
3109 { Hexagon::G11_10, 230U },
3110 { Hexagon::G13_12, 232U },
3111 { Hexagon::G15_14, 234U },
3112 { Hexagon::G17_16, 236U },
3113 { Hexagon::G19_18, 238U },
3114 { Hexagon::G21_20, 240U },
3115 { Hexagon::G23_22, 242U },
3116 { Hexagon::G25_24, 244U },
3117 { Hexagon::G27_26, 246U },
3118 { Hexagon::G29_28, 248U },
3119 { Hexagon::G31_30, 250U },
3120 { Hexagon::P3_0, 71U },
3121 { Hexagon::S3_2, 146U },
3122 { Hexagon::S5_4, 148U },
3123 { Hexagon::S7_6, 150U },
3124 { Hexagon::S9_8, 152U },
3125 { Hexagon::S11_10, 154U },
3126 { Hexagon::S13_12, 156U },
3127 { Hexagon::S15_14, 158U },
3128 { Hexagon::S17_16, 160U },
3129 { Hexagon::S19_18, 162U },
3130 { Hexagon::S21_20, 164U },
3131 { Hexagon::S23_22, 166U },
3132 { Hexagon::S25_24, 168U },
3133 { Hexagon::S27_26, 170U },
3134 { Hexagon::S29_28, 172U },
3135 { Hexagon::S31_30, 174U },
3136 { Hexagon::S33_32, 176U },
3137 { Hexagon::S35_34, 178U },
3138 { Hexagon::S37_36, 180U },
3139 { Hexagon::S39_38, 182U },
3140 { Hexagon::S41_40, 184U },
3141 { Hexagon::S43_42, 186U },
3142 { Hexagon::S45_44, 188U },
3143 { Hexagon::S47_46, 190U },
3144 { Hexagon::S49_48, 192U },
3145 { Hexagon::S51_50, 194U },
3146 { Hexagon::S53_52, 196U },
3147 { Hexagon::S55_54, 198U },
3148 { Hexagon::S57_56, 200U },
3149 { Hexagon::S59_58, 202U },
3150 { Hexagon::S61_60, 204U },
3151 { Hexagon::S63_62, 206U },
3152 { Hexagon::S65_64, 208U },
3153 { Hexagon::S67_66, 210U },
3154 { Hexagon::S69_68, 212U },
3155 { Hexagon::S71_70, 214U },
3156 { Hexagon::S73_72, 216U },
3157 { Hexagon::S75_74, 218U },
3158 { Hexagon::S77_76, 219U },
3159 { Hexagon::S79_78, 220U },
3160 { Hexagon::SGP1_0, 144U },
3161};
3162extern const unsigned HexagonDwarfFlavour0L2DwarfSize = std::size(HexagonDwarfFlavour0L2Dwarf);
3163
3164extern const MCRegisterInfo::DwarfLLVMRegPair HexagonEHFlavour0L2Dwarf[] = {
3165 { Hexagon::BADVA, 153U },
3166 { Hexagon::CCR, 151U },
3167 { Hexagon::CFGBASE, 171U },
3168 { Hexagon::CS, 78U },
3169 { Hexagon::DIAG, 172U },
3170 { Hexagon::ELR, 147U },
3171 { Hexagon::EVB, 160U },
3172 { Hexagon::FRAMEKEY, 84U },
3173 { Hexagon::FRAMELIMIT, 83U },
3174 { Hexagon::GELR, 220U },
3175 { Hexagon::GOSP, 222U },
3176 { Hexagon::GP, 78U },
3177 { Hexagon::GPCYCLEHI, 245U },
3178 { Hexagon::GPCYCLELO, 244U },
3179 { Hexagon::GSR, 221U },
3180 { Hexagon::HTID, 152U },
3181 { Hexagon::IMASK, 154U },
3182 { Hexagon::ISDBEN, 186U },
3183 { Hexagon::ISDBGPR, 187U },
3184 { Hexagon::ISDBMBXIN, 184U },
3185 { Hexagon::ISDBMBXOUT, 185U },
3186 { Hexagon::ISDBST, 176U },
3187 { Hexagon::MODECTL, 161U },
3188 { Hexagon::PC, 76U },
3189 { Hexagon::PCYCLEHI, 175U },
3190 { Hexagon::PCYCLELO, 174U },
3191 { Hexagon::PKTCOUNT, 85U },
3192 { Hexagon::PKTCOUNTHI, 86U },
3193 { Hexagon::PKTCOUNTLO, 85U },
3194 { Hexagon::PMUCFG, 197U },
3195 { Hexagon::PMUEVTCFG, 196U },
3196 { Hexagon::REV, 173U },
3197 { Hexagon::SSR, 150U },
3198 { Hexagon::STID, 146U },
3199 { Hexagon::SYSCFG, 162U },
3200 { Hexagon::UGP, 77U },
3201 { Hexagon::UPCYCLE, 80U },
3202 { Hexagon::UPCYCLEHI, 82U },
3203 { Hexagon::UPCYCLELO, 81U },
3204 { Hexagon::USR, 75U },
3205 { Hexagon::UTIMER, 97U },
3206 { Hexagon::UTIMERHI, 98U },
3207 { Hexagon::UTIMERLO, 97U },
3208 { Hexagon::VID, 165U },
3209 { Hexagon::VTMP, 131U },
3210 { Hexagon::BADVA0, 148U },
3211 { Hexagon::BADVA1, 149U },
3212 { Hexagon::BRKPTCFG0, 181U },
3213 { Hexagon::BRKPTCFG1, 183U },
3214 { Hexagon::BRKPTPC0, 180U },
3215 { Hexagon::BRKPTPC1, 182U },
3216 { Hexagon::C5, 72U },
3217 { Hexagon::C8, 75U },
3218 { Hexagon::CS0, 79U },
3219 { Hexagon::CS1, 80U },
3220 { Hexagon::D0, 32U },
3221 { Hexagon::D1, 34U },
3222 { Hexagon::D2, 36U },
3223 { Hexagon::D3, 38U },
3224 { Hexagon::D4, 40U },
3225 { Hexagon::D5, 42U },
3226 { Hexagon::D6, 44U },
3227 { Hexagon::D7, 46U },
3228 { Hexagon::D8, 48U },
3229 { Hexagon::D9, 50U },
3230 { Hexagon::D10, 52U },
3231 { Hexagon::D11, 54U },
3232 { Hexagon::D12, 56U },
3233 { Hexagon::D13, 58U },
3234 { Hexagon::D14, 60U },
3235 { Hexagon::D15, 62U },
3236 { Hexagon::G3, 223U },
3237 { Hexagon::G4, 224U },
3238 { Hexagon::G5, 225U },
3239 { Hexagon::G6, 226U },
3240 { Hexagon::G7, 227U },
3241 { Hexagon::G8, 228U },
3242 { Hexagon::G9, 229U },
3243 { Hexagon::G10, 230U },
3244 { Hexagon::G11, 231U },
3245 { Hexagon::G12, 232U },
3246 { Hexagon::G13, 233U },
3247 { Hexagon::G14, 234U },
3248 { Hexagon::G15, 235U },
3249 { Hexagon::G20, 240U },
3250 { Hexagon::G21, 241U },
3251 { Hexagon::G22, 242U },
3252 { Hexagon::G23, 243U },
3253 { Hexagon::G30, 250U },
3254 { Hexagon::G31, 251U },
3255 { Hexagon::GPMUCNT0, 246U },
3256 { Hexagon::GPMUCNT1, 247U },
3257 { Hexagon::GPMUCNT2, 248U },
3258 { Hexagon::GPMUCNT3, 249U },
3259 { Hexagon::GPMUCNT4, 236U },
3260 { Hexagon::GPMUCNT5, 237U },
3261 { Hexagon::GPMUCNT6, 238U },
3262 { Hexagon::GPMUCNT7, 239U },
3263 { Hexagon::ISDBCFG0, 177U },
3264 { Hexagon::ISDBCFG1, 178U },
3265 { Hexagon::LC0, 68U },
3266 { Hexagon::LC1, 70U },
3267 { Hexagon::M0, 73U },
3268 { Hexagon::M1, 74U },
3269 { Hexagon::P0, 63U },
3270 { Hexagon::P1, 64U },
3271 { Hexagon::P2, 65U },
3272 { Hexagon::P3, 66U },
3273 { Hexagon::PMUCNT0, 192U },
3274 { Hexagon::PMUCNT1, 193U },
3275 { Hexagon::PMUCNT2, 194U },
3276 { Hexagon::PMUCNT3, 195U },
3277 { Hexagon::Q0, 131U },
3278 { Hexagon::Q1, 132U },
3279 { Hexagon::Q2, 133U },
3280 { Hexagon::Q3, 134U },
3281 { Hexagon::R0, 0U },
3282 { Hexagon::R1, 1U },
3283 { Hexagon::R2, 2U },
3284 { Hexagon::R3, 3U },
3285 { Hexagon::R4, 4U },
3286 { Hexagon::R5, 5U },
3287 { Hexagon::R6, 6U },
3288 { Hexagon::R7, 7U },
3289 { Hexagon::R8, 8U },
3290 { Hexagon::R9, 9U },
3291 { Hexagon::R10, 10U },
3292 { Hexagon::R11, 11U },
3293 { Hexagon::R12, 12U },
3294 { Hexagon::R13, 13U },
3295 { Hexagon::R14, 14U },
3296 { Hexagon::R15, 15U },
3297 { Hexagon::R16, 16U },
3298 { Hexagon::R17, 17U },
3299 { Hexagon::R18, 18U },
3300 { Hexagon::R19, 19U },
3301 { Hexagon::R20, 20U },
3302 { Hexagon::R21, 21U },
3303 { Hexagon::R22, 22U },
3304 { Hexagon::R23, 23U },
3305 { Hexagon::R24, 24U },
3306 { Hexagon::R25, 25U },
3307 { Hexagon::R26, 26U },
3308 { Hexagon::R27, 27U },
3309 { Hexagon::R28, 28U },
3310 { Hexagon::R29, 29U },
3311 { Hexagon::R30, 30U },
3312 { Hexagon::R31, 31U },
3313 { Hexagon::S11, 155U },
3314 { Hexagon::S12, 156U },
3315 { Hexagon::S13, 157U },
3316 { Hexagon::S14, 158U },
3317 { Hexagon::S15, 159U },
3318 { Hexagon::S19, 163U },
3319 { Hexagon::S20, 164U },
3320 { Hexagon::S22, 166U },
3321 { Hexagon::S23, 167U },
3322 { Hexagon::S24, 168U },
3323 { Hexagon::S25, 169U },
3324 { Hexagon::S26, 170U },
3325 { Hexagon::S35, 179U },
3326 { Hexagon::S44, 188U },
3327 { Hexagon::S45, 189U },
3328 { Hexagon::S46, 190U },
3329 { Hexagon::S47, 191U },
3330 { Hexagon::S54, 198U },
3331 { Hexagon::S55, 199U },
3332 { Hexagon::S56, 200U },
3333 { Hexagon::S57, 201U },
3334 { Hexagon::S58, 202U },
3335 { Hexagon::S59, 203U },
3336 { Hexagon::S60, 204U },
3337 { Hexagon::S61, 205U },
3338 { Hexagon::S62, 206U },
3339 { Hexagon::S63, 207U },
3340 { Hexagon::S64, 208U },
3341 { Hexagon::S65, 209U },
3342 { Hexagon::S66, 210U },
3343 { Hexagon::S67, 211U },
3344 { Hexagon::S68, 212U },
3345 { Hexagon::S69, 213U },
3346 { Hexagon::S70, 214U },
3347 { Hexagon::S71, 215U },
3348 { Hexagon::S72, 216U },
3349 { Hexagon::S73, 217U },
3350 { Hexagon::S74, 218U },
3351 { Hexagon::S75, 219U },
3352 { Hexagon::S76, 220U },
3353 { Hexagon::S77, 221U },
3354 { Hexagon::S78, 222U },
3355 { Hexagon::S79, 223U },
3356 { Hexagon::S80, 224U },
3357 { Hexagon::SA0, 67U },
3358 { Hexagon::SA1, 69U },
3359 { Hexagon::SGP0, 144U },
3360 { Hexagon::SGP1, 145U },
3361 { Hexagon::V0, 99U },
3362 { Hexagon::V1, 100U },
3363 { Hexagon::V2, 101U },
3364 { Hexagon::V3, 102U },
3365 { Hexagon::V4, 103U },
3366 { Hexagon::V5, 104U },
3367 { Hexagon::V6, 105U },
3368 { Hexagon::V7, 106U },
3369 { Hexagon::V8, 107U },
3370 { Hexagon::V9, 108U },
3371 { Hexagon::V10, 109U },
3372 { Hexagon::V11, 110U },
3373 { Hexagon::V12, 111U },
3374 { Hexagon::V13, 112U },
3375 { Hexagon::V14, 113U },
3376 { Hexagon::V15, 114U },
3377 { Hexagon::V16, 115U },
3378 { Hexagon::V17, 116U },
3379 { Hexagon::V18, 117U },
3380 { Hexagon::V19, 118U },
3381 { Hexagon::V20, 119U },
3382 { Hexagon::V21, 120U },
3383 { Hexagon::V22, 121U },
3384 { Hexagon::V23, 122U },
3385 { Hexagon::V24, 123U },
3386 { Hexagon::V25, 124U },
3387 { Hexagon::V26, 125U },
3388 { Hexagon::V27, 126U },
3389 { Hexagon::V28, 127U },
3390 { Hexagon::V29, 128U },
3391 { Hexagon::V30, 129U },
3392 { Hexagon::V31, 130U },
3393 { Hexagon::VF0, 999999U },
3394 { Hexagon::VF1, 1000000U },
3395 { Hexagon::VF2, 1000001U },
3396 { Hexagon::VF3, 1000002U },
3397 { Hexagon::VF4, 1000003U },
3398 { Hexagon::VF5, 1000004U },
3399 { Hexagon::VF6, 1000005U },
3400 { Hexagon::VF7, 1000006U },
3401 { Hexagon::VF8, 1000007U },
3402 { Hexagon::VF9, 1000008U },
3403 { Hexagon::VF10, 1000009U },
3404 { Hexagon::VF11, 1000010U },
3405 { Hexagon::VF12, 1000011U },
3406 { Hexagon::VF13, 1000012U },
3407 { Hexagon::VF14, 1000013U },
3408 { Hexagon::VF15, 1000014U },
3409 { Hexagon::VF16, 1000015U },
3410 { Hexagon::VF17, 1000016U },
3411 { Hexagon::VF18, 1000017U },
3412 { Hexagon::VF19, 1000018U },
3413 { Hexagon::VF20, 1000019U },
3414 { Hexagon::VF21, 1000020U },
3415 { Hexagon::VF22, 1000021U },
3416 { Hexagon::VF23, 1000022U },
3417 { Hexagon::VF24, 1000023U },
3418 { Hexagon::VF25, 1000024U },
3419 { Hexagon::VF26, 1000025U },
3420 { Hexagon::VF27, 1000026U },
3421 { Hexagon::VF28, 1000027U },
3422 { Hexagon::VF29, 1000028U },
3423 { Hexagon::VF30, 1000029U },
3424 { Hexagon::VF31, 1000030U },
3425 { Hexagon::VFR0, 9999999U },
3426 { Hexagon::VFR1, 10000000U },
3427 { Hexagon::VFR2, 10000001U },
3428 { Hexagon::VFR3, 10000002U },
3429 { Hexagon::VFR4, 10000003U },
3430 { Hexagon::VFR5, 10000004U },
3431 { Hexagon::VFR6, 10000005U },
3432 { Hexagon::VFR7, 10000006U },
3433 { Hexagon::VFR8, 10000007U },
3434 { Hexagon::VFR9, 10000008U },
3435 { Hexagon::VFR10, 10000009U },
3436 { Hexagon::VFR11, 10000010U },
3437 { Hexagon::VFR12, 10000011U },
3438 { Hexagon::VFR13, 10000012U },
3439 { Hexagon::VFR14, 10000013U },
3440 { Hexagon::VFR15, 10000014U },
3441 { Hexagon::VFR16, 10000015U },
3442 { Hexagon::VFR17, 10000016U },
3443 { Hexagon::VFR18, 10000017U },
3444 { Hexagon::VFR19, 10000018U },
3445 { Hexagon::VFR20, 10000019U },
3446 { Hexagon::VFR21, 10000020U },
3447 { Hexagon::VFR22, 10000021U },
3448 { Hexagon::VFR23, 10000022U },
3449 { Hexagon::VFR24, 10000023U },
3450 { Hexagon::VFR25, 10000024U },
3451 { Hexagon::VFR26, 10000025U },
3452 { Hexagon::VFR27, 10000026U },
3453 { Hexagon::VFR28, 10000027U },
3454 { Hexagon::VFR29, 10000028U },
3455 { Hexagon::VFR30, 10000029U },
3456 { Hexagon::VFR31, 10000030U },
3457 { Hexagon::VQ0, 252U },
3458 { Hexagon::VQ1, 253U },
3459 { Hexagon::VQ2, 254U },
3460 { Hexagon::VQ3, 255U },
3461 { Hexagon::VQ4, 256U },
3462 { Hexagon::VQ5, 257U },
3463 { Hexagon::VQ6, 258U },
3464 { Hexagon::VQ7, 259U },
3465 { Hexagon::W0, 99U },
3466 { Hexagon::W1, 101U },
3467 { Hexagon::W2, 103U },
3468 { Hexagon::W3, 105U },
3469 { Hexagon::W4, 107U },
3470 { Hexagon::W5, 109U },
3471 { Hexagon::W6, 111U },
3472 { Hexagon::W7, 113U },
3473 { Hexagon::W8, 115U },
3474 { Hexagon::W9, 117U },
3475 { Hexagon::W10, 119U },
3476 { Hexagon::W11, 121U },
3477 { Hexagon::W12, 123U },
3478 { Hexagon::W13, 125U },
3479 { Hexagon::W14, 127U },
3480 { Hexagon::W15, 129U },
3481 { Hexagon::WR0, 161U },
3482 { Hexagon::WR1, 162U },
3483 { Hexagon::WR2, 163U },
3484 { Hexagon::WR3, 164U },
3485 { Hexagon::WR4, 165U },
3486 { Hexagon::WR5, 166U },
3487 { Hexagon::WR6, 167U },
3488 { Hexagon::WR7, 168U },
3489 { Hexagon::WR8, 169U },
3490 { Hexagon::WR9, 170U },
3491 { Hexagon::WR10, 171U },
3492 { Hexagon::WR11, 172U },
3493 { Hexagon::WR12, 173U },
3494 { Hexagon::WR13, 174U },
3495 { Hexagon::WR14, 175U },
3496 { Hexagon::WR15, 176U },
3497 { Hexagon::C1_0, 67U },
3498 { Hexagon::C3_2, 69U },
3499 { Hexagon::C5_4, 71U },
3500 { Hexagon::C7_6, 72U },
3501 { Hexagon::C9_8, 74U },
3502 { Hexagon::C11_10, 76U },
3503 { Hexagon::C17_16, 83U },
3504 { Hexagon::G1_0, 220U },
3505 { Hexagon::G3_2, 222U },
3506 { Hexagon::G5_4, 224U },
3507 { Hexagon::G7_6, 226U },
3508 { Hexagon::G9_8, 228U },
3509 { Hexagon::G11_10, 230U },
3510 { Hexagon::G13_12, 232U },
3511 { Hexagon::G15_14, 234U },
3512 { Hexagon::G17_16, 236U },
3513 { Hexagon::G19_18, 238U },
3514 { Hexagon::G21_20, 240U },
3515 { Hexagon::G23_22, 242U },
3516 { Hexagon::G25_24, 244U },
3517 { Hexagon::G27_26, 246U },
3518 { Hexagon::G29_28, 248U },
3519 { Hexagon::G31_30, 250U },
3520 { Hexagon::P3_0, 71U },
3521 { Hexagon::S3_2, 146U },
3522 { Hexagon::S5_4, 148U },
3523 { Hexagon::S7_6, 150U },
3524 { Hexagon::S9_8, 152U },
3525 { Hexagon::S11_10, 154U },
3526 { Hexagon::S13_12, 156U },
3527 { Hexagon::S15_14, 158U },
3528 { Hexagon::S17_16, 160U },
3529 { Hexagon::S19_18, 162U },
3530 { Hexagon::S21_20, 164U },
3531 { Hexagon::S23_22, 166U },
3532 { Hexagon::S25_24, 168U },
3533 { Hexagon::S27_26, 170U },
3534 { Hexagon::S29_28, 172U },
3535 { Hexagon::S31_30, 174U },
3536 { Hexagon::S33_32, 176U },
3537 { Hexagon::S35_34, 178U },
3538 { Hexagon::S37_36, 180U },
3539 { Hexagon::S39_38, 182U },
3540 { Hexagon::S41_40, 184U },
3541 { Hexagon::S43_42, 186U },
3542 { Hexagon::S45_44, 188U },
3543 { Hexagon::S47_46, 190U },
3544 { Hexagon::S49_48, 192U },
3545 { Hexagon::S51_50, 194U },
3546 { Hexagon::S53_52, 196U },
3547 { Hexagon::S55_54, 198U },
3548 { Hexagon::S57_56, 200U },
3549 { Hexagon::S59_58, 202U },
3550 { Hexagon::S61_60, 204U },
3551 { Hexagon::S63_62, 206U },
3552 { Hexagon::S65_64, 208U },
3553 { Hexagon::S67_66, 210U },
3554 { Hexagon::S69_68, 212U },
3555 { Hexagon::S71_70, 214U },
3556 { Hexagon::S73_72, 216U },
3557 { Hexagon::S75_74, 218U },
3558 { Hexagon::S77_76, 219U },
3559 { Hexagon::S79_78, 220U },
3560 { Hexagon::SGP1_0, 144U },
3561};
3562extern const unsigned HexagonEHFlavour0L2DwarfSize = std::size(HexagonEHFlavour0L2Dwarf);
3563
3564extern const uint16_t HexagonRegEncodingTable[] = {
3565 0,
3566 9,
3567 7,
3568 27,
3569 12,
3570 28,
3571 3,
3572 16,
3573 17,
3574 16,
3575 0,
3576 2,
3577 11,
3578 25,
3579 24,
3580 1,
3581 8,
3582 10,
3583 42,
3584 43,
3585 40,
3586 41,
3587 32,
3588 17,
3589 9,
3590 31,
3591 30,
3592 18,
3593 19,
3594 18,
3595 53,
3596 52,
3597 29,
3598 6,
3599 2,
3600 18,
3601 10,
3602 14,
3603 15,
3604 14,
3605 8,
3606 0,
3607 30,
3608 31,
3609 30,
3610 21,
3611 0,
3612 4,
3613 5,
3614 37,
3615 39,
3616 36,
3617 38,
3618 5,
3619 8,
3620 12,
3621 13,
3622 0,
3623 2,
3624 4,
3625 6,
3626 8,
3627 10,
3628 12,
3629 14,
3630 16,
3631 18,
3632 20,
3633 22,
3634 24,
3635 26,
3636 28,
3637 30,
3638 3,
3639 4,
3640 5,
3641 6,
3642 7,
3643 8,
3644 9,
3645 10,
3646 11,
3647 12,
3648 13,
3649 14,
3650 15,
3651 20,
3652 21,
3653 22,
3654 23,
3655 30,
3656 31,
3657 26,
3658 27,
3659 28,
3660 29,
3661 16,
3662 17,
3663 18,
3664 19,
3665 33,
3666 34,
3667 1,
3668 3,
3669 6,
3670 7,
3671 0,
3672 1,
3673 2,
3674 3,
3675 48,
3676 49,
3677 50,
3678 51,
3679 0,
3680 1,
3681 2,
3682 3,
3683 0,
3684 1,
3685 2,
3686 3,
3687 4,
3688 5,
3689 6,
3690 7,
3691 8,
3692 9,
3693 10,
3694 11,
3695 12,
3696 13,
3697 14,
3698 15,
3699 16,
3700 17,
3701 18,
3702 19,
3703 20,
3704 21,
3705 22,
3706 23,
3707 24,
3708 25,
3709 26,
3710 27,
3711 28,
3712 29,
3713 30,
3714 31,
3715 11,
3716 12,
3717 13,
3718 14,
3719 15,
3720 19,
3721 20,
3722 22,
3723 23,
3724 24,
3725 25,
3726 26,
3727 35,
3728 44,
3729 45,
3730 46,
3731 47,
3732 54,
3733 55,
3734 56,
3735 57,
3736 58,
3737 59,
3738 60,
3739 61,
3740 62,
3741 63,
3742 64,
3743 65,
3744 66,
3745 67,
3746 68,
3747 69,
3748 70,
3749 71,
3750 72,
3751 73,
3752 74,
3753 75,
3754 76,
3755 77,
3756 78,
3757 79,
3758 80,
3759 0,
3760 2,
3761 0,
3762 1,
3763 0,
3764 1,
3765 2,
3766 3,
3767 4,
3768 5,
3769 6,
3770 7,
3771 8,
3772 9,
3773 10,
3774 11,
3775 12,
3776 13,
3777 14,
3778 15,
3779 16,
3780 17,
3781 18,
3782 19,
3783 20,
3784 21,
3785 22,
3786 23,
3787 24,
3788 25,
3789 26,
3790 27,
3791 28,
3792 29,
3793 30,
3794 31,
3795 0,
3796 0,
3797 0,
3798 0,
3799 0,
3800 0,
3801 0,
3802 0,
3803 0,
3804 0,
3805 0,
3806 0,
3807 0,
3808 0,
3809 0,
3810 0,
3811 0,
3812 0,
3813 0,
3814 0,
3815 0,
3816 0,
3817 0,
3818 0,
3819 0,
3820 0,
3821 0,
3822 0,
3823 0,
3824 0,
3825 0,
3826 0,
3827 0,
3828 0,
3829 0,
3830 0,
3831 0,
3832 0,
3833 0,
3834 0,
3835 0,
3836 0,
3837 0,
3838 0,
3839 0,
3840 0,
3841 0,
3842 0,
3843 0,
3844 0,
3845 0,
3846 0,
3847 0,
3848 0,
3849 0,
3850 0,
3851 0,
3852 0,
3853 0,
3854 0,
3855 0,
3856 0,
3857 0,
3858 0,
3859 0,
3860 4,
3861 8,
3862 12,
3863 16,
3864 20,
3865 24,
3866 28,
3867 0,
3868 2,
3869 4,
3870 6,
3871 8,
3872 10,
3873 12,
3874 14,
3875 16,
3876 18,
3877 20,
3878 22,
3879 24,
3880 26,
3881 28,
3882 30,
3883 1,
3884 3,
3885 5,
3886 7,
3887 9,
3888 11,
3889 13,
3890 15,
3891 17,
3892 19,
3893 21,
3894 23,
3895 25,
3896 27,
3897 29,
3898 31,
3899 0,
3900 2,
3901 4,
3902 6,
3903 8,
3904 10,
3905 16,
3906 0,
3907 2,
3908 4,
3909 6,
3910 8,
3911 10,
3912 12,
3913 14,
3914 16,
3915 18,
3916 20,
3917 22,
3918 24,
3919 26,
3920 28,
3921 30,
3922 4,
3923 2,
3924 4,
3925 6,
3926 8,
3927 10,
3928 12,
3929 14,
3930 16,
3931 18,
3932 20,
3933 22,
3934 24,
3935 26,
3936 28,
3937 30,
3938 32,
3939 34,
3940 36,
3941 38,
3942 40,
3943 42,
3944 44,
3945 46,
3946 48,
3947 50,
3948 52,
3949 54,
3950 56,
3951 58,
3952 60,
3953 62,
3954 64,
3955 66,
3956 68,
3957 70,
3958 72,
3959 74,
3960 76,
3961 78,
3962 0,
3963};
3964static inline void InitHexagonMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
3965 RI->InitMCRegisterInfo(HexagonRegDesc, 398, RA, PC, HexagonMCRegisterClasses, 29, HexagonRegUnitRoots, 278, HexagonRegDiffLists, HexagonLaneMaskLists, HexagonRegStrings, HexagonRegClassStrings, HexagonSubRegIdxLists, 12,
3966HexagonRegEncodingTable);
3967
3968 switch (DwarfFlavour) {
3969 default:
3970 llvm_unreachable("Unknown DWARF flavour");
3971 case 0:
3972 RI->mapDwarfRegsToLLVMRegs(HexagonDwarfFlavour0Dwarf2L, HexagonDwarfFlavour0Dwarf2LSize, false);
3973 break;
3974 }
3975 switch (EHFlavour) {
3976 default:
3977 llvm_unreachable("Unknown DWARF flavour");
3978 case 0:
3979 RI->mapDwarfRegsToLLVMRegs(HexagonEHFlavour0Dwarf2L, HexagonEHFlavour0Dwarf2LSize, true);
3980 break;
3981 }
3982 switch (DwarfFlavour) {
3983 default:
3984 llvm_unreachable("Unknown DWARF flavour");
3985 case 0:
3986 RI->mapLLVMRegsToDwarfRegs(HexagonDwarfFlavour0L2Dwarf, HexagonDwarfFlavour0L2DwarfSize, false);
3987 break;
3988 }
3989 switch (EHFlavour) {
3990 default:
3991 llvm_unreachable("Unknown DWARF flavour");
3992 case 0:
3993 RI->mapLLVMRegsToDwarfRegs(HexagonEHFlavour0L2Dwarf, HexagonEHFlavour0L2DwarfSize, true);
3994 break;
3995 }
3996}
3997
3998} // end namespace llvm
3999
4000#endif // GET_REGINFO_MC_DESC
4001
4002/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
4003|* *|
4004|* Register Information Header Fragment *|
4005|* *|
4006|* Automatically generated file, do not edit! *|
4007|* *|
4008\*===----------------------------------------------------------------------===*/
4009
4010
4011#ifdef GET_REGINFO_HEADER
4012#undef GET_REGINFO_HEADER
4013
4014#include "llvm/CodeGen/TargetRegisterInfo.h"
4015
4016namespace llvm {
4017
4018class HexagonFrameLowering;
4019
4020struct HexagonGenRegisterInfo : public TargetRegisterInfo {
4021 explicit HexagonGenRegisterInfo(unsigned RA, unsigned D = 0, unsigned E = 0,
4022 unsigned PC = 0, unsigned HwMode = 0);
4023 unsigned composeSubRegIndicesImpl(unsigned, unsigned) const override;
4024 unsigned reverseComposeSubRegIndicesImpl(unsigned, unsigned) const override;
4025 LaneBitmask composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
4026 LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
4027 const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass *, unsigned) const override;
4028 const TargetRegisterClass *getSubRegisterClass(const TargetRegisterClass *, unsigned) const override;
4029 const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override;
4030 unsigned getRegUnitWeight(unsigned RegUnit) const override;
4031 unsigned getNumRegPressureSets() const override;
4032 const char *getRegPressureSetName(unsigned Idx) const override;
4033 unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override;
4034 const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override;
4035 const int *getRegUnitPressureSets(unsigned RegUnit) const override;
4036 ArrayRef<const char *> getRegMaskNames() const override;
4037 ArrayRef<const uint32_t *> getRegMasks() const override;
4038 bool isGeneralPurposeRegister(const MachineFunction &, MCRegister) const override;
4039 bool isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const override;
4040 bool isFixedRegister(const MachineFunction &, MCRegister) const override;
4041 bool isArgumentRegister(const MachineFunction &, MCRegister) const override;
4042 bool isConstantPhysReg(MCRegister PhysReg) const override final;
4043 /// Devirtualized TargetFrameLowering.
4044 static const HexagonFrameLowering *getFrameLowering(
4045 const MachineFunction &MF);
4046};
4047
4048namespace Hexagon { // Register classes
4049 extern const TargetRegisterClass UsrBitsRegClass;
4050 extern const TargetRegisterClass SysRegsRegClass;
4051 extern const TargetRegisterClass GuestRegsRegClass;
4052 extern const TargetRegisterClass IntRegsRegClass;
4053 extern const TargetRegisterClass CtrRegsRegClass;
4054 extern const TargetRegisterClass GeneralSubRegsRegClass;
4055 extern const TargetRegisterClass V62RegsRegClass;
4056 extern const TargetRegisterClass IntRegsLow8RegClass;
4057 extern const TargetRegisterClass CtrRegs_and_V62RegsRegClass;
4058 extern const TargetRegisterClass PredRegsRegClass;
4059 extern const TargetRegisterClass V62Regs_with_isub_hiRegClass;
4060 extern const TargetRegisterClass ModRegsRegClass;
4061 extern const TargetRegisterClass CtrRegs_with_subreg_overflowRegClass;
4062 extern const TargetRegisterClass V65RegsRegClass;
4063 extern const TargetRegisterClass SysRegs64RegClass;
4064 extern const TargetRegisterClass DoubleRegsRegClass;
4065 extern const TargetRegisterClass GuestRegs64RegClass;
4066 extern const TargetRegisterClass VectRegRevRegClass;
4067 extern const TargetRegisterClass CtrRegs64RegClass;
4068 extern const TargetRegisterClass GeneralDoubleLow8RegsRegClass;
4069 extern const TargetRegisterClass DoubleRegs_with_isub_hi_in_IntRegsLow8RegClass;
4070 extern const TargetRegisterClass CtrRegs64_and_V62RegsRegClass;
4071 extern const TargetRegisterClass CtrRegs64_with_isub_hi_in_ModRegsRegClass;
4072 extern const TargetRegisterClass HvxQRRegClass;
4073 extern const TargetRegisterClass HvxVRRegClass;
4074 extern const TargetRegisterClass HvxVR_and_V65RegsRegClass;
4075 extern const TargetRegisterClass HvxWRRegClass;
4076 extern const TargetRegisterClass HvxWR_and_VectRegRevRegClass;
4077 extern const TargetRegisterClass HvxVQRRegClass;
4078} // end namespace Hexagon
4079
4080} // end namespace llvm
4081
4082#endif // GET_REGINFO_HEADER
4083
4084/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
4085|* *|
4086|* Target Register and Register Classes Information *|
4087|* *|
4088|* Automatically generated file, do not edit! *|
4089|* *|
4090\*===----------------------------------------------------------------------===*/
4091
4092
4093#ifdef GET_REGINFO_TARGET_DESC
4094#undef GET_REGINFO_TARGET_DESC
4095
4096namespace llvm {
4097
4098extern const MCRegisterClass HexagonMCRegisterClasses[];
4099
4100static const MVT::SimpleValueType VTLists[] = {
4101 /* 0 */ MVT::i1, MVT::Other,
4102 /* 2 */ MVT::i1, MVT::v2i1, MVT::v4i1, MVT::v8i1, MVT::v4i8, MVT::v2i16, MVT::i32, MVT::Other,
4103 /* 10 */ MVT::i64, MVT::Other,
4104 /* 12 */ MVT::v64i1, MVT::v64i1, MVT::v32i1, MVT::v16i1, MVT::Other,
4105 /* 17 */ MVT::v128i1, MVT::v128i1, MVT::v64i1, MVT::v32i1, MVT::Other,
4106 /* 22 */ MVT::i32, MVT::f32, MVT::v4i8, MVT::v2i16, MVT::Other,
4107 /* 27 */ MVT::i64, MVT::f64, MVT::v8i8, MVT::v4i16, MVT::v2i32, MVT::Other,
4108 /* 33 */ MVT::v64i8, MVT::v32i16, MVT::v16i32, MVT::v32f16, MVT::v16f32, MVT::Other,
4109 /* 39 */ MVT::v128i8, MVT::v64i16, MVT::v32i32, MVT::v64f16, MVT::v32f32, MVT::Other,
4110 /* 45 */ MVT::v256i8, MVT::v128i16, MVT::v64i32, MVT::v128f16, MVT::v64f32, MVT::Other,
4111 /* 51 */ MVT::Untyped, MVT::Other,
4112};
4113
4114static const char *SubRegIndexNameTable[] = { "isub_hi", "isub_lo", "subreg_overflow", "vsub_fake", "vsub_hi", "vsub_lo", "wsub_hi", "wsub_lo", "wsub_hi_then_vsub_fake", "wsub_hi_then_vsub_hi", "wsub_hi_then_vsub_lo", "" };
4115
4116static const TargetRegisterInfo::SubRegCoveredBits SubRegIdxRangeTable[] = {
4117 { 65535, 65535 },
4118 { 32, 32 }, // isub_hi
4119 { 0, 32 }, // isub_lo
4120 { 0, 1 }, // subreg_overflow
4121 { 65535, 65535 }, // vsub_fake
4122 { 65535, 65535 }, // vsub_hi
4123 { 65535, 65535 }, // vsub_lo
4124 { 65535, 65535 }, // wsub_hi
4125 { 65535, 65535 }, // wsub_lo
4126 { 65535, 65535 }, // wsub_hi_then_vsub_fake
4127 { 65535, 65535 }, // wsub_hi_then_vsub_hi
4128 { 65535, 65535 }, // wsub_hi_then_vsub_lo
4129 { 65535, 65535 },
4130 { 32, 32 }, // isub_hi
4131 { 0, 32 }, // isub_lo
4132 { 0, 1 }, // subreg_overflow
4133 { 65535, 65535 }, // vsub_fake
4134 { 65535, 65535 }, // vsub_hi
4135 { 65535, 65535 }, // vsub_lo
4136 { 65535, 65535 }, // wsub_hi
4137 { 65535, 65535 }, // wsub_lo
4138 { 65535, 65535 }, // wsub_hi_then_vsub_fake
4139 { 65535, 65535 }, // wsub_hi_then_vsub_hi
4140 { 65535, 65535 }, // wsub_hi_then_vsub_lo
4141 { 65535, 65535 },
4142 { 32, 32 }, // isub_hi
4143 { 0, 32 }, // isub_lo
4144 { 0, 1 }, // subreg_overflow
4145 { 65535, 65535 }, // vsub_fake
4146 { 65535, 65535 }, // vsub_hi
4147 { 65535, 65535 }, // vsub_lo
4148 { 65535, 65535 }, // wsub_hi
4149 { 65535, 65535 }, // wsub_lo
4150 { 65535, 65535 }, // wsub_hi_then_vsub_fake
4151 { 65535, 65535 }, // wsub_hi_then_vsub_hi
4152 { 65535, 65535 }, // wsub_hi_then_vsub_lo
4153};
4154
4155
4156static const LaneBitmask SubRegIndexLaneMaskTable[] = {
4157 LaneBitmask::getAll(),
4158 LaneBitmask(0x0000000000000001), // isub_hi
4159 LaneBitmask(0x0000000000000002), // isub_lo
4160 LaneBitmask(0x0000000000000004), // subreg_overflow
4161 LaneBitmask(0x0000000000000008), // vsub_fake
4162 LaneBitmask(0x0000000000000010), // vsub_hi
4163 LaneBitmask(0x0000000000000020), // vsub_lo
4164 LaneBitmask(0x00000000000001C0), // wsub_hi
4165 LaneBitmask(0x0000000000000038), // wsub_lo
4166 LaneBitmask(0x0000000000000040), // wsub_hi_then_vsub_fake
4167 LaneBitmask(0x0000000000000080), // wsub_hi_then_vsub_hi
4168 LaneBitmask(0x0000000000000100), // wsub_hi_then_vsub_lo
4169 };
4170
4171
4172
4173static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
4174 // Mode = 0 (Default)
4175 { 1, 1, 0, /*VTLists+*/0 }, // UsrBits
4176 { 32, 32, 32, /*VTLists+*/8 }, // SysRegs
4177 { 32, 32, 32, /*VTLists+*/8 }, // GuestRegs
4178 { 32, 32, 32, /*VTLists+*/22 }, // IntRegs
4179 { 32, 32, 32, /*VTLists+*/8 }, // CtrRegs
4180 { 32, 32, 32, /*VTLists+*/8 }, // GeneralSubRegs
4181 { 32, 32, 32, /*VTLists+*/8 }, // V62Regs
4182 { 32, 32, 32, /*VTLists+*/8 }, // IntRegsLow8
4183 { 32, 32, 32, /*VTLists+*/8 }, // CtrRegs_and_V62Regs
4184 { 32, 32, 32, /*VTLists+*/2 }, // PredRegs
4185 { 32, 32, 32, /*VTLists+*/8 }, // V62Regs_with_isub_hi
4186 { 32, 32, 32, /*VTLists+*/8 }, // ModRegs
4187 { 32, 32, 32, /*VTLists+*/8 }, // CtrRegs_with_subreg_overflow
4188 { 32, 32, 32, /*VTLists+*/8 }, // V65Regs
4189 { 64, 64, 64, /*VTLists+*/10 }, // SysRegs64
4190 { 64, 64, 64, /*VTLists+*/27 }, // DoubleRegs
4191 { 64, 64, 64, /*VTLists+*/10 }, // GuestRegs64
4192 { 64, 64, 64, /*VTLists+*/10 }, // VectRegRev
4193 { 64, 64, 64, /*VTLists+*/10 }, // CtrRegs64
4194 { 64, 64, 64, /*VTLists+*/10 }, // GeneralDoubleLow8Regs
4195 { 64, 64, 64, /*VTLists+*/10 }, // DoubleRegs_with_isub_hi_in_IntRegsLow8
4196 { 64, 64, 64, /*VTLists+*/10 }, // CtrRegs64_and_V62Regs
4197 { 64, 64, 64, /*VTLists+*/10 }, // CtrRegs64_with_isub_hi_in_ModRegs
4198 { 64, 512, 512, /*VTLists+*/12 }, // HvxQR
4199 { 512, 512, 512, /*VTLists+*/33 }, // HvxVR
4200 { 512, 512, 512, /*VTLists+*/33 }, // HvxVR_and_V65Regs
4201 { 1024, 1024, 512, /*VTLists+*/39 }, // HvxWR
4202 { 1024, 1024, 512, /*VTLists+*/39 }, // HvxWR_and_VectRegRev
4203 { 2048, 2048, 512, /*VTLists+*/51 }, // HvxVQR
4204 // Mode = 1 (Hvx64)
4205 { 1, 1, 0, /*VTLists+*/0 }, // UsrBits
4206 { 32, 32, 32, /*VTLists+*/8 }, // SysRegs
4207 { 32, 32, 32, /*VTLists+*/8 }, // GuestRegs
4208 { 32, 32, 32, /*VTLists+*/22 }, // IntRegs
4209 { 32, 32, 32, /*VTLists+*/8 }, // CtrRegs
4210 { 32, 32, 32, /*VTLists+*/8 }, // GeneralSubRegs
4211 { 32, 32, 32, /*VTLists+*/8 }, // V62Regs
4212 { 32, 32, 32, /*VTLists+*/8 }, // IntRegsLow8
4213 { 32, 32, 32, /*VTLists+*/8 }, // CtrRegs_and_V62Regs
4214 { 32, 32, 32, /*VTLists+*/2 }, // PredRegs
4215 { 32, 32, 32, /*VTLists+*/8 }, // V62Regs_with_isub_hi
4216 { 32, 32, 32, /*VTLists+*/8 }, // ModRegs
4217 { 32, 32, 32, /*VTLists+*/8 }, // CtrRegs_with_subreg_overflow
4218 { 32, 32, 32, /*VTLists+*/8 }, // V65Regs
4219 { 64, 64, 64, /*VTLists+*/10 }, // SysRegs64
4220 { 64, 64, 64, /*VTLists+*/27 }, // DoubleRegs
4221 { 64, 64, 64, /*VTLists+*/10 }, // GuestRegs64
4222 { 64, 64, 64, /*VTLists+*/10 }, // VectRegRev
4223 { 64, 64, 64, /*VTLists+*/10 }, // CtrRegs64
4224 { 64, 64, 64, /*VTLists+*/10 }, // GeneralDoubleLow8Regs
4225 { 64, 64, 64, /*VTLists+*/10 }, // DoubleRegs_with_isub_hi_in_IntRegsLow8
4226 { 64, 64, 64, /*VTLists+*/10 }, // CtrRegs64_and_V62Regs
4227 { 64, 64, 64, /*VTLists+*/10 }, // CtrRegs64_with_isub_hi_in_ModRegs
4228 { 64, 512, 512, /*VTLists+*/12 }, // HvxQR
4229 { 512, 512, 512, /*VTLists+*/33 }, // HvxVR
4230 { 512, 512, 512, /*VTLists+*/33 }, // HvxVR_and_V65Regs
4231 { 1024, 1024, 512, /*VTLists+*/39 }, // HvxWR
4232 { 1024, 1024, 512, /*VTLists+*/39 }, // HvxWR_and_VectRegRev
4233 { 2048, 2048, 512, /*VTLists+*/51 }, // HvxVQR
4234 // Mode = 2 (Hvx128)
4235 { 1, 1, 0, /*VTLists+*/0 }, // UsrBits
4236 { 32, 32, 32, /*VTLists+*/8 }, // SysRegs
4237 { 32, 32, 32, /*VTLists+*/8 }, // GuestRegs
4238 { 32, 32, 32, /*VTLists+*/22 }, // IntRegs
4239 { 32, 32, 32, /*VTLists+*/8 }, // CtrRegs
4240 { 32, 32, 32, /*VTLists+*/8 }, // GeneralSubRegs
4241 { 32, 32, 32, /*VTLists+*/8 }, // V62Regs
4242 { 32, 32, 32, /*VTLists+*/8 }, // IntRegsLow8
4243 { 32, 32, 32, /*VTLists+*/8 }, // CtrRegs_and_V62Regs
4244 { 32, 32, 32, /*VTLists+*/2 }, // PredRegs
4245 { 32, 32, 32, /*VTLists+*/8 }, // V62Regs_with_isub_hi
4246 { 32, 32, 32, /*VTLists+*/8 }, // ModRegs
4247 { 32, 32, 32, /*VTLists+*/8 }, // CtrRegs_with_subreg_overflow
4248 { 32, 32, 32, /*VTLists+*/8 }, // V65Regs
4249 { 64, 64, 64, /*VTLists+*/10 }, // SysRegs64
4250 { 64, 64, 64, /*VTLists+*/27 }, // DoubleRegs
4251 { 64, 64, 64, /*VTLists+*/10 }, // GuestRegs64
4252 { 64, 64, 64, /*VTLists+*/10 }, // VectRegRev
4253 { 64, 64, 64, /*VTLists+*/10 }, // CtrRegs64
4254 { 64, 64, 64, /*VTLists+*/10 }, // GeneralDoubleLow8Regs
4255 { 64, 64, 64, /*VTLists+*/10 }, // DoubleRegs_with_isub_hi_in_IntRegsLow8
4256 { 64, 64, 64, /*VTLists+*/10 }, // CtrRegs64_and_V62Regs
4257 { 64, 64, 64, /*VTLists+*/10 }, // CtrRegs64_with_isub_hi_in_ModRegs
4258 { 128, 1024, 1024, /*VTLists+*/17 }, // HvxQR
4259 { 1024, 1024, 1024, /*VTLists+*/39 }, // HvxVR
4260 { 1024, 1024, 1024, /*VTLists+*/39 }, // HvxVR_and_V65Regs
4261 { 2048, 2048, 1024, /*VTLists+*/45 }, // HvxWR
4262 { 2048, 2048, 1024, /*VTLists+*/45 }, // HvxWR_and_VectRegRev
4263 { 4096, 4096, 1024, /*VTLists+*/51 }, // HvxVQR
4264};
4265static const uint32_t UsrBitsSubClassMask[] = {
4266 0x00000001,
4267 0x00001000, // subreg_overflow
4268};
4269
4270static const uint32_t SysRegsSubClassMask[] = {
4271 0x00000002,
4272 0x00004000, // isub_hi
4273 0x00004000, // isub_lo
4274};
4275
4276static const uint32_t GuestRegsSubClassMask[] = {
4277 0x00000004,
4278 0x00010000, // isub_hi
4279 0x00010000, // isub_lo
4280};
4281
4282static const uint32_t IntRegsSubClassMask[] = {
4283 0x000000a8,
4284 0x00188000, // isub_hi
4285 0x00188000, // isub_lo
4286};
4287
4288static const uint32_t CtrRegsSubClassMask[] = {
4289 0x00001910,
4290 0x00640400, // isub_hi
4291 0x00640400, // isub_lo
4292};
4293
4294static const uint32_t GeneralSubRegsSubClassMask[] = {
4295 0x000000a0,
4296 0x00180000, // isub_hi
4297 0x00180000, // isub_lo
4298};
4299
4300static const uint32_t V62RegsSubClassMask[] = {
4301 0x00200540,
4302 0x00200400, // isub_hi
4303 0x00200400, // isub_lo
4304};
4305
4306static const uint32_t IntRegsLow8SubClassMask[] = {
4307 0x00000080,
4308 0x00100000, // isub_hi
4309 0x00100000, // isub_lo
4310};
4311
4312static const uint32_t CtrRegs_and_V62RegsSubClassMask[] = {
4313 0x00000100,
4314 0x00200400, // isub_hi
4315 0x00200400, // isub_lo
4316};
4317
4318static const uint32_t PredRegsSubClassMask[] = {
4319 0x00000200,
4320};
4321
4322static const uint32_t V62Regs_with_isub_hiSubClassMask[] = {
4323 0x00200400,
4324};
4325
4326static const uint32_t ModRegsSubClassMask[] = {
4327 0x00000800,
4328 0x00400000, // isub_hi
4329 0x00400000, // isub_lo
4330};
4331
4332static const uint32_t CtrRegs_with_subreg_overflowSubClassMask[] = {
4333 0x00001000,
4334};
4335
4336static const uint32_t V65RegsSubClassMask[] = {
4337 0x02002000,
4338};
4339
4340static const uint32_t SysRegs64SubClassMask[] = {
4341 0x00004000,
4342};
4343
4344static const uint32_t DoubleRegsSubClassMask[] = {
4345 0x00188000,
4346};
4347
4348static const uint32_t GuestRegs64SubClassMask[] = {
4349 0x00010000,
4350};
4351
4352static const uint32_t VectRegRevSubClassMask[] = {
4353 0x08020000,
4354};
4355
4356static const uint32_t CtrRegs64SubClassMask[] = {
4357 0x00640000,
4358};
4359
4360static const uint32_t GeneralDoubleLow8RegsSubClassMask[] = {
4361 0x00180000,
4362};
4363
4364static const uint32_t DoubleRegs_with_isub_hi_in_IntRegsLow8SubClassMask[] = {
4365 0x00100000,
4366};
4367
4368static const uint32_t CtrRegs64_and_V62RegsSubClassMask[] = {
4369 0x00200000,
4370};
4371
4372static const uint32_t CtrRegs64_with_isub_hi_in_ModRegsSubClassMask[] = {
4373 0x00400000,
4374};
4375
4376static const uint32_t HvxQRSubClassMask[] = {
4377 0x00800000,
4378};
4379
4380static const uint32_t HvxVRSubClassMask[] = {
4381 0x03000000,
4382 0x1c020000, // vsub_hi
4383 0x1c020000, // vsub_lo
4384 0x10000000, // wsub_hi_then_vsub_hi
4385 0x10000000, // wsub_hi_then_vsub_lo
4386};
4387
4388static const uint32_t HvxVR_and_V65RegsSubClassMask[] = {
4389 0x02000000,
4390};
4391
4392static const uint32_t HvxWRSubClassMask[] = {
4393 0x0c000000,
4394 0x10000000, // wsub_hi
4395 0x10000000, // wsub_lo
4396};
4397
4398static const uint32_t HvxWR_and_VectRegRevSubClassMask[] = {
4399 0x08000000,
4400};
4401
4402static const uint32_t HvxVQRSubClassMask[] = {
4403 0x10000000,
4404};
4405
4406static const uint16_t SuperRegIdxSeqs[] = {
4407 /* 0 */ 1, 2, 0,
4408 /* 3 */ 3, 0,
4409 /* 5 */ 7, 8, 0,
4410 /* 8 */ 5, 6, 10, 11, 0,
4411};
4412
4413static unsigned const GeneralSubRegsSuperclasses[] = {
4414 Hexagon::IntRegsRegClassID,
4415};
4416
4417static unsigned const IntRegsLow8Superclasses[] = {
4418 Hexagon::IntRegsRegClassID,
4419 Hexagon::GeneralSubRegsRegClassID,
4420};
4421
4422static unsigned const CtrRegs_and_V62RegsSuperclasses[] = {
4423 Hexagon::CtrRegsRegClassID,
4424 Hexagon::V62RegsRegClassID,
4425};
4426
4427static unsigned const V62Regs_with_isub_hiSuperclasses[] = {
4428 Hexagon::V62RegsRegClassID,
4429};
4430
4431static unsigned const ModRegsSuperclasses[] = {
4432 Hexagon::CtrRegsRegClassID,
4433};
4434
4435static unsigned const CtrRegs_with_subreg_overflowSuperclasses[] = {
4436 Hexagon::CtrRegsRegClassID,
4437};
4438
4439static unsigned const GeneralDoubleLow8RegsSuperclasses[] = {
4440 Hexagon::DoubleRegsRegClassID,
4441};
4442
4443static unsigned const DoubleRegs_with_isub_hi_in_IntRegsLow8Superclasses[] = {
4444 Hexagon::DoubleRegsRegClassID,
4445 Hexagon::GeneralDoubleLow8RegsRegClassID,
4446};
4447
4448static unsigned const CtrRegs64_and_V62RegsSuperclasses[] = {
4449 Hexagon::V62RegsRegClassID,
4450 Hexagon::V62Regs_with_isub_hiRegClassID,
4451 Hexagon::CtrRegs64RegClassID,
4452};
4453
4454static unsigned const CtrRegs64_with_isub_hi_in_ModRegsSuperclasses[] = {
4455 Hexagon::CtrRegs64RegClassID,
4456};
4457
4458static unsigned const HvxVR_and_V65RegsSuperclasses[] = {
4459 Hexagon::V65RegsRegClassID,
4460 Hexagon::HvxVRRegClassID,
4461};
4462
4463static unsigned const HvxWR_and_VectRegRevSuperclasses[] = {
4464 Hexagon::VectRegRevRegClassID,
4465 Hexagon::HvxWRRegClassID,
4466};
4467
4468
4469namespace Hexagon { // Register class instances
4470 extern const TargetRegisterClass UsrBitsRegClass = {
4471 &HexagonMCRegisterClasses[UsrBitsRegClassID],
4472 UsrBitsSubClassMask,
4473 SuperRegIdxSeqs + 3,
4474 LaneBitmask(0x0000000000000001),
4475 0,
4476 false,
4477 0x00, /* TSFlags */
4478 false, /* HasDisjunctSubRegs */
4479 false, /* CoveredBySubRegs */
4480 nullptr, 0,
4481 nullptr
4482 };
4483
4484 extern const TargetRegisterClass SysRegsRegClass = {
4485 &HexagonMCRegisterClasses[SysRegsRegClassID],
4486 SysRegsSubClassMask,
4487 SuperRegIdxSeqs + 0,
4488 LaneBitmask(0x0000000000000001),
4489 0,
4490 false,
4491 0x00, /* TSFlags */
4492 false, /* HasDisjunctSubRegs */
4493 false, /* CoveredBySubRegs */
4494 nullptr, 0,
4495 nullptr
4496 };
4497
4498 extern const TargetRegisterClass GuestRegsRegClass = {
4499 &HexagonMCRegisterClasses[GuestRegsRegClassID],
4500 GuestRegsSubClassMask,
4501 SuperRegIdxSeqs + 0,
4502 LaneBitmask(0x0000000000000001),
4503 0,
4504 false,
4505 0x00, /* TSFlags */
4506 false, /* HasDisjunctSubRegs */
4507 false, /* CoveredBySubRegs */
4508 nullptr, 0,
4509 nullptr
4510 };
4511
4512 extern const TargetRegisterClass IntRegsRegClass = {
4513 &HexagonMCRegisterClasses[IntRegsRegClassID],
4514 IntRegsSubClassMask,
4515 SuperRegIdxSeqs + 0,
4516 LaneBitmask(0x0000000000000001),
4517 0,
4518 false,
4519 0x00, /* TSFlags */
4520 false, /* HasDisjunctSubRegs */
4521 false, /* CoveredBySubRegs */
4522 nullptr, 0,
4523 nullptr
4524 };
4525
4526 extern const TargetRegisterClass CtrRegsRegClass = {
4527 &HexagonMCRegisterClasses[CtrRegsRegClassID],
4528 CtrRegsSubClassMask,
4529 SuperRegIdxSeqs + 0,
4530 LaneBitmask(0x0000000000000004),
4531 0,
4532 false,
4533 0x00, /* TSFlags */
4534 false, /* HasDisjunctSubRegs */
4535 false, /* CoveredBySubRegs */
4536 nullptr, 0,
4537 nullptr
4538 };
4539
4540 extern const TargetRegisterClass GeneralSubRegsRegClass = {
4541 &HexagonMCRegisterClasses[GeneralSubRegsRegClassID],
4542 GeneralSubRegsSubClassMask,
4543 SuperRegIdxSeqs + 0,
4544 LaneBitmask(0x0000000000000001),
4545 0,
4546 false,
4547 0x00, /* TSFlags */
4548 false, /* HasDisjunctSubRegs */
4549 false, /* CoveredBySubRegs */
4550 GeneralSubRegsSuperclasses, 1,
4551 nullptr
4552 };
4553
4554 extern const TargetRegisterClass V62RegsRegClass = {
4555 &HexagonMCRegisterClasses[V62RegsRegClassID],
4556 V62RegsSubClassMask,
4557 SuperRegIdxSeqs + 0,
4558 LaneBitmask(0x0000000000000003),
4559 0,
4560 false,
4561 0x00, /* TSFlags */
4562 true, /* HasDisjunctSubRegs */
4563 false, /* CoveredBySubRegs */
4564 nullptr, 0,
4565 nullptr
4566 };
4567
4568 extern const TargetRegisterClass IntRegsLow8RegClass = {
4569 &HexagonMCRegisterClasses[IntRegsLow8RegClassID],
4570 IntRegsLow8SubClassMask,
4571 SuperRegIdxSeqs + 0,
4572 LaneBitmask(0x0000000000000001),
4573 0,
4574 false,
4575 0x00, /* TSFlags */
4576 false, /* HasDisjunctSubRegs */
4577 false, /* CoveredBySubRegs */
4578 IntRegsLow8Superclasses, 2,
4579 nullptr
4580 };
4581
4582 extern const TargetRegisterClass CtrRegs_and_V62RegsRegClass = {
4583 &HexagonMCRegisterClasses[CtrRegs_and_V62RegsRegClassID],
4584 CtrRegs_and_V62RegsSubClassMask,
4585 SuperRegIdxSeqs + 0,
4586 LaneBitmask(0x0000000000000001),
4587 0,
4588 false,
4589 0x00, /* TSFlags */
4590 false, /* HasDisjunctSubRegs */
4591 false, /* CoveredBySubRegs */
4592 CtrRegs_and_V62RegsSuperclasses, 2,
4593 nullptr
4594 };
4595
4596 extern const TargetRegisterClass PredRegsRegClass = {
4597 &HexagonMCRegisterClasses[PredRegsRegClassID],
4598 PredRegsSubClassMask,
4599 SuperRegIdxSeqs + 2,
4600 LaneBitmask(0x0000000000000001),
4601 0,
4602 false,
4603 0x00, /* TSFlags */
4604 false, /* HasDisjunctSubRegs */
4605 false, /* CoveredBySubRegs */
4606 nullptr, 0,
4607 nullptr
4608 };
4609
4610 extern const TargetRegisterClass V62Regs_with_isub_hiRegClass = {
4611 &HexagonMCRegisterClasses[V62Regs_with_isub_hiRegClassID],
4612 V62Regs_with_isub_hiSubClassMask,
4613 SuperRegIdxSeqs + 2,
4614 LaneBitmask(0x0000000000000003),
4615 0,
4616 false,
4617 0x00, /* TSFlags */
4618 true, /* HasDisjunctSubRegs */
4619 true, /* CoveredBySubRegs */
4620 V62Regs_with_isub_hiSuperclasses, 1,
4621 nullptr
4622 };
4623
4624 extern const TargetRegisterClass ModRegsRegClass = {
4625 &HexagonMCRegisterClasses[ModRegsRegClassID],
4626 ModRegsSubClassMask,
4627 SuperRegIdxSeqs + 0,
4628 LaneBitmask(0x0000000000000001),
4629 0,
4630 false,
4631 0x00, /* TSFlags */
4632 false, /* HasDisjunctSubRegs */
4633 false, /* CoveredBySubRegs */
4634 ModRegsSuperclasses, 1,
4635 nullptr
4636 };
4637
4638 extern const TargetRegisterClass CtrRegs_with_subreg_overflowRegClass = {
4639 &HexagonMCRegisterClasses[CtrRegs_with_subreg_overflowRegClassID],
4640 CtrRegs_with_subreg_overflowSubClassMask,
4641 SuperRegIdxSeqs + 2,
4642 LaneBitmask(0x0000000000000004),
4643 0,
4644 false,
4645 0x00, /* TSFlags */
4646 false, /* HasDisjunctSubRegs */
4647 false, /* CoveredBySubRegs */
4648 CtrRegs_with_subreg_overflowSuperclasses, 1,
4649 nullptr
4650 };
4651
4652 extern const TargetRegisterClass V65RegsRegClass = {
4653 &HexagonMCRegisterClasses[V65RegsRegClassID],
4654 V65RegsSubClassMask,
4655 SuperRegIdxSeqs + 2,
4656 LaneBitmask(0x0000000000000001),
4657 0,
4658 false,
4659 0x00, /* TSFlags */
4660 false, /* HasDisjunctSubRegs */
4661 false, /* CoveredBySubRegs */
4662 nullptr, 0,
4663 nullptr
4664 };
4665
4666 extern const TargetRegisterClass SysRegs64RegClass = {
4667 &HexagonMCRegisterClasses[SysRegs64RegClassID],
4668 SysRegs64SubClassMask,
4669 SuperRegIdxSeqs + 2,
4670 LaneBitmask(0x0000000000000003),
4671 0,
4672 false,
4673 0x00, /* TSFlags */
4674 true, /* HasDisjunctSubRegs */
4675 true, /* CoveredBySubRegs */
4676 nullptr, 0,
4677 nullptr
4678 };
4679
4680 extern const TargetRegisterClass DoubleRegsRegClass = {
4681 &HexagonMCRegisterClasses[DoubleRegsRegClassID],
4682 DoubleRegsSubClassMask,
4683 SuperRegIdxSeqs + 2,
4684 LaneBitmask(0x0000000000000003),
4685 0,
4686 false,
4687 0x00, /* TSFlags */
4688 true, /* HasDisjunctSubRegs */
4689 true, /* CoveredBySubRegs */
4690 nullptr, 0,
4691 nullptr
4692 };
4693
4694 extern const TargetRegisterClass GuestRegs64RegClass = {
4695 &HexagonMCRegisterClasses[GuestRegs64RegClassID],
4696 GuestRegs64SubClassMask,
4697 SuperRegIdxSeqs + 2,
4698 LaneBitmask(0x0000000000000003),
4699 0,
4700 false,
4701 0x00, /* TSFlags */
4702 true, /* HasDisjunctSubRegs */
4703 true, /* CoveredBySubRegs */
4704 nullptr, 0,
4705 nullptr
4706 };
4707
4708 extern const TargetRegisterClass VectRegRevRegClass = {
4709 &HexagonMCRegisterClasses[VectRegRevRegClassID],
4710 VectRegRevSubClassMask,
4711 SuperRegIdxSeqs + 2,
4712 LaneBitmask(0x0000000000000038),
4713 0,
4714 false,
4715 0x00, /* TSFlags */
4716 true, /* HasDisjunctSubRegs */
4717 true, /* CoveredBySubRegs */
4718 nullptr, 0,
4719 nullptr
4720 };
4721
4722 extern const TargetRegisterClass CtrRegs64RegClass = {
4723 &HexagonMCRegisterClasses[CtrRegs64RegClassID],
4724 CtrRegs64SubClassMask,
4725 SuperRegIdxSeqs + 2,
4726 LaneBitmask(0x0000000000000003),
4727 0,
4728 false,
4729 0x00, /* TSFlags */
4730 true, /* HasDisjunctSubRegs */
4731 true, /* CoveredBySubRegs */
4732 nullptr, 0,
4733 nullptr
4734 };
4735
4736 extern const TargetRegisterClass GeneralDoubleLow8RegsRegClass = {
4737 &HexagonMCRegisterClasses[GeneralDoubleLow8RegsRegClassID],
4738 GeneralDoubleLow8RegsSubClassMask,
4739 SuperRegIdxSeqs + 2,
4740 LaneBitmask(0x0000000000000003),
4741 0,
4742 false,
4743 0x00, /* TSFlags */
4744 true, /* HasDisjunctSubRegs */
4745 true, /* CoveredBySubRegs */
4746 GeneralDoubleLow8RegsSuperclasses, 1,
4747 nullptr
4748 };
4749
4750 extern const TargetRegisterClass DoubleRegs_with_isub_hi_in_IntRegsLow8RegClass = {
4751 &HexagonMCRegisterClasses[DoubleRegs_with_isub_hi_in_IntRegsLow8RegClassID],
4752 DoubleRegs_with_isub_hi_in_IntRegsLow8SubClassMask,
4753 SuperRegIdxSeqs + 2,
4754 LaneBitmask(0x0000000000000003),
4755 0,
4756 false,
4757 0x00, /* TSFlags */
4758 true, /* HasDisjunctSubRegs */
4759 true, /* CoveredBySubRegs */
4760 DoubleRegs_with_isub_hi_in_IntRegsLow8Superclasses, 2,
4761 nullptr
4762 };
4763
4764 extern const TargetRegisterClass CtrRegs64_and_V62RegsRegClass = {
4765 &HexagonMCRegisterClasses[CtrRegs64_and_V62RegsRegClassID],
4766 CtrRegs64_and_V62RegsSubClassMask,
4767 SuperRegIdxSeqs + 2,
4768 LaneBitmask(0x0000000000000003),
4769 0,
4770 false,
4771 0x00, /* TSFlags */
4772 true, /* HasDisjunctSubRegs */
4773 true, /* CoveredBySubRegs */
4774 CtrRegs64_and_V62RegsSuperclasses, 3,
4775 nullptr
4776 };
4777
4778 extern const TargetRegisterClass CtrRegs64_with_isub_hi_in_ModRegsRegClass = {
4779 &HexagonMCRegisterClasses[CtrRegs64_with_isub_hi_in_ModRegsRegClassID],
4780 CtrRegs64_with_isub_hi_in_ModRegsSubClassMask,
4781 SuperRegIdxSeqs + 2,
4782 LaneBitmask(0x0000000000000003),
4783 0,
4784 false,
4785 0x00, /* TSFlags */
4786 true, /* HasDisjunctSubRegs */
4787 true, /* CoveredBySubRegs */
4788 CtrRegs64_with_isub_hi_in_ModRegsSuperclasses, 1,
4789 nullptr
4790 };
4791
4792 extern const TargetRegisterClass HvxQRRegClass = {
4793 &HexagonMCRegisterClasses[HvxQRRegClassID],
4794 HvxQRSubClassMask,
4795 SuperRegIdxSeqs + 2,
4796 LaneBitmask(0x0000000000000001),
4797 0,
4798 false,
4799 0x00, /* TSFlags */
4800 false, /* HasDisjunctSubRegs */
4801 false, /* CoveredBySubRegs */
4802 nullptr, 0,
4803 nullptr
4804 };
4805
4806 extern const TargetRegisterClass HvxVRRegClass = {
4807 &HexagonMCRegisterClasses[HvxVRRegClassID],
4808 HvxVRSubClassMask,
4809 SuperRegIdxSeqs + 8,
4810 LaneBitmask(0x0000000000000001),
4811 0,
4812 false,
4813 0x00, /* TSFlags */
4814 false, /* HasDisjunctSubRegs */
4815 false, /* CoveredBySubRegs */
4816 nullptr, 0,
4817 nullptr
4818 };
4819
4820 extern const TargetRegisterClass HvxVR_and_V65RegsRegClass = {
4821 &HexagonMCRegisterClasses[HvxVR_and_V65RegsRegClassID],
4822 HvxVR_and_V65RegsSubClassMask,
4823 SuperRegIdxSeqs + 2,
4824 LaneBitmask(0x0000000000000001),
4825 0,
4826 false,
4827 0x00, /* TSFlags */
4828 false, /* HasDisjunctSubRegs */
4829 false, /* CoveredBySubRegs */
4830 HvxVR_and_V65RegsSuperclasses, 2,
4831 nullptr
4832 };
4833
4834 extern const TargetRegisterClass HvxWRRegClass = {
4835 &HexagonMCRegisterClasses[HvxWRRegClassID],
4836 HvxWRSubClassMask,
4837 SuperRegIdxSeqs + 5,
4838 LaneBitmask(0x0000000000000038),
4839 0,
4840 false,
4841 0x00, /* TSFlags */
4842 true, /* HasDisjunctSubRegs */
4843 true, /* CoveredBySubRegs */
4844 nullptr, 0,
4845 nullptr
4846 };
4847
4848 extern const TargetRegisterClass HvxWR_and_VectRegRevRegClass = {
4849 &HexagonMCRegisterClasses[HvxWR_and_VectRegRevRegClassID],
4850 HvxWR_and_VectRegRevSubClassMask,
4851 SuperRegIdxSeqs + 2,
4852 LaneBitmask(0x0000000000000038),
4853 0,
4854 false,
4855 0x00, /* TSFlags */
4856 true, /* HasDisjunctSubRegs */
4857 true, /* CoveredBySubRegs */
4858 HvxWR_and_VectRegRevSuperclasses, 2,
4859 nullptr
4860 };
4861
4862 extern const TargetRegisterClass HvxVQRRegClass = {
4863 &HexagonMCRegisterClasses[HvxVQRRegClassID],
4864 HvxVQRSubClassMask,
4865 SuperRegIdxSeqs + 2,
4866 LaneBitmask(0x00000000000001F8),
4867 0,
4868 false,
4869 0x00, /* TSFlags */
4870 true, /* HasDisjunctSubRegs */
4871 true, /* CoveredBySubRegs */
4872 nullptr, 0,
4873 nullptr
4874 };
4875
4876} // end namespace Hexagon
4877
4878namespace {
4879 const TargetRegisterClass *const RegisterClasses[] = {
4880 &Hexagon::UsrBitsRegClass,
4881 &Hexagon::SysRegsRegClass,
4882 &Hexagon::GuestRegsRegClass,
4883 &Hexagon::IntRegsRegClass,
4884 &Hexagon::CtrRegsRegClass,
4885 &Hexagon::GeneralSubRegsRegClass,
4886 &Hexagon::V62RegsRegClass,
4887 &Hexagon::IntRegsLow8RegClass,
4888 &Hexagon::CtrRegs_and_V62RegsRegClass,
4889 &Hexagon::PredRegsRegClass,
4890 &Hexagon::V62Regs_with_isub_hiRegClass,
4891 &Hexagon::ModRegsRegClass,
4892 &Hexagon::CtrRegs_with_subreg_overflowRegClass,
4893 &Hexagon::V65RegsRegClass,
4894 &Hexagon::SysRegs64RegClass,
4895 &Hexagon::DoubleRegsRegClass,
4896 &Hexagon::GuestRegs64RegClass,
4897 &Hexagon::VectRegRevRegClass,
4898 &Hexagon::CtrRegs64RegClass,
4899 &Hexagon::GeneralDoubleLow8RegsRegClass,
4900 &Hexagon::DoubleRegs_with_isub_hi_in_IntRegsLow8RegClass,
4901 &Hexagon::CtrRegs64_and_V62RegsRegClass,
4902 &Hexagon::CtrRegs64_with_isub_hi_in_ModRegsRegClass,
4903 &Hexagon::HvxQRRegClass,
4904 &Hexagon::HvxVRRegClass,
4905 &Hexagon::HvxVR_and_V65RegsRegClass,
4906 &Hexagon::HvxWRRegClass,
4907 &Hexagon::HvxWR_and_VectRegRevRegClass,
4908 &Hexagon::HvxVQRRegClass,
4909 };
4910} // end anonymous namespace
4911
4912static const uint8_t CostPerUseTable[] = {
49130, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
4914
4915
4916static const bool InAllocatableClassTable[] = {
4917false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, };
4918
4919
4920static const TargetRegisterInfoDesc HexagonRegInfoDesc = { // Extra Descriptors
4921CostPerUseTable, 1, InAllocatableClassTable};
4922
4923unsigned HexagonGenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
4924 static const uint8_t RowMap[11] = {
4925 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0,
4926 };
4927 static const uint8_t Rows[2][11] = {
4928 { 0, 0, 0, Hexagon::wsub_hi_then_vsub_fake, Hexagon::wsub_hi_then_vsub_hi, Hexagon::wsub_hi_then_vsub_lo, 0, 0, 0, 0, 0, },
4929 { 0, 0, 0, Hexagon::vsub_fake, Hexagon::vsub_hi, Hexagon::vsub_lo, 0, 0, 0, 0, 0, },
4930 };
4931
4932 --IdxA; assert(IdxA < 11); (void) IdxA;
4933 --IdxB; assert(IdxB < 11);
4934 return Rows[RowMap[IdxA]][IdxB];
4935}
4936
4937unsigned HexagonGenRegisterInfo::reverseComposeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
4938 static const uint8_t Table[11][11] = {
4939 { 0, 0, 0, 0, 0, 0, 0, 0, Hexagon::vsub_fake, Hexagon::vsub_hi, Hexagon::vsub_lo, },
4940 { 0, 0, 0, 0, 0, 0, 0, 0, Hexagon::vsub_fake, Hexagon::vsub_hi, Hexagon::vsub_lo, },
4941 { 0, 0, 0, 0, 0, 0, 0, 0, Hexagon::vsub_fake, Hexagon::vsub_hi, Hexagon::vsub_lo, },
4942 { 0, 0, 0, 0, 0, 0, 0, 0, Hexagon::vsub_fake, Hexagon::vsub_hi, Hexagon::vsub_lo, },
4943 { 0, 0, 0, 0, 0, 0, 0, 0, Hexagon::vsub_fake, Hexagon::vsub_hi, Hexagon::vsub_lo, },
4944 { 0, 0, 0, 0, 0, 0, 0, 0, Hexagon::vsub_fake, Hexagon::vsub_hi, Hexagon::vsub_lo, },
4945 { 0, 0, 0, 0, 0, 0, 0, 0, Hexagon::vsub_fake, Hexagon::vsub_hi, Hexagon::vsub_lo, },
4946 { 0, 0, 0, Hexagon::vsub_fake, Hexagon::vsub_hi, Hexagon::vsub_lo, 0, 0, 0, 0, 0, },
4947 { 0, 0, 0, 0, 0, 0, 0, 0, Hexagon::vsub_fake, Hexagon::vsub_hi, Hexagon::vsub_lo, },
4948 { 0, 0, 0, 0, 0, 0, 0, 0, Hexagon::vsub_fake, Hexagon::vsub_hi, Hexagon::vsub_lo, },
4949 { 0, 0, 0, 0, 0, 0, 0, 0, Hexagon::vsub_fake, Hexagon::vsub_hi, Hexagon::vsub_lo, },
4950 };
4951
4952 --IdxA; assert(IdxA < 11);
4953 --IdxB; assert(IdxB < 11);
4954 return Table[IdxA][IdxB];
4955 }
4956
4957 struct MaskRolOp {
4958 LaneBitmask Mask;
4959 uint8_t RotateLeft;
4960 };
4961 static const MaskRolOp LaneMaskComposeSequences[] = {
4962 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 0 }, { LaneBitmask::getNone(), 0 }, // Sequence 0
4963 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 1 }, { LaneBitmask::getNone(), 0 }, // Sequence 2
4964 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 2 }, { LaneBitmask::getNone(), 0 }, // Sequence 4
4965 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 3 }, { LaneBitmask::getNone(), 0 }, // Sequence 6
4966 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 4 }, { LaneBitmask::getNone(), 0 }, // Sequence 8
4967 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 5 }, { LaneBitmask::getNone(), 0 }, // Sequence 10
4968 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 6 }, { LaneBitmask::getNone(), 0 }, // Sequence 12
4969 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 7 }, { LaneBitmask::getNone(), 0 }, // Sequence 14
4970 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 8 }, { LaneBitmask::getNone(), 0 } // Sequence 16
4971 };
4972 static const uint8_t CompositeSequences[] = {
4973 0, // to isub_hi
4974 2, // to isub_lo
4975 4, // to subreg_overflow
4976 6, // to vsub_fake
4977 8, // to vsub_hi
4978 10, // to vsub_lo
4979 6, // to wsub_hi
4980 0, // to wsub_lo
4981 12, // to wsub_hi_then_vsub_fake
4982 14, // to wsub_hi_then_vsub_hi
4983 16 // to wsub_hi_then_vsub_lo
4984 };
4985
4986LaneBitmask HexagonGenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
4987 --IdxA; assert(IdxA < 11 && "Subregister index out of bounds");
4988 LaneBitmask Result;
4989 for (const MaskRolOp *Ops =
4990 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
4991 Ops->Mask.any(); ++Ops) {
4992 LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
4993 if (unsigned S = Ops->RotateLeft)
4994 Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));
4995 else
4996 Result |= LaneBitmask(M);
4997 }
4998 return Result;
4999}
5000
5001LaneBitmask HexagonGenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
5002 LaneMask &= getSubRegIndexLaneMask(IdxA);
5003 --IdxA; assert(IdxA < 11 && "Subregister index out of bounds");
5004 LaneBitmask Result;
5005 for (const MaskRolOp *Ops =
5006 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
5007 Ops->Mask.any(); ++Ops) {
5008 LaneBitmask::Type M = LaneMask.getAsInteger();
5009 if (unsigned S = Ops->RotateLeft)
5010 Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));
5011 else
5012 Result |= LaneBitmask(M);
5013 }
5014 return Result;
5015}
5016
5017const TargetRegisterClass *HexagonGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
5018 static const uint8_t Table[29][11] = {
5019 { // UsrBits
5020 0, // isub_hi
5021 0, // isub_lo
5022 0, // subreg_overflow
5023 0, // vsub_fake
5024 0, // vsub_hi
5025 0, // vsub_lo
5026 0, // wsub_hi
5027 0, // wsub_lo
5028 0, // wsub_hi_then_vsub_fake
5029 0, // wsub_hi_then_vsub_hi
5030 0, // wsub_hi_then_vsub_lo
5031 },
5032 { // SysRegs
5033 0, // isub_hi
5034 0, // isub_lo
5035 0, // subreg_overflow
5036 0, // vsub_fake
5037 0, // vsub_hi
5038 0, // vsub_lo
5039 0, // wsub_hi
5040 0, // wsub_lo
5041 0, // wsub_hi_then_vsub_fake
5042 0, // wsub_hi_then_vsub_hi
5043 0, // wsub_hi_then_vsub_lo
5044 },
5045 { // GuestRegs
5046 0, // isub_hi
5047 0, // isub_lo
5048 0, // subreg_overflow
5049 0, // vsub_fake
5050 0, // vsub_hi
5051 0, // vsub_lo
5052 0, // wsub_hi
5053 0, // wsub_lo
5054 0, // wsub_hi_then_vsub_fake
5055 0, // wsub_hi_then_vsub_hi
5056 0, // wsub_hi_then_vsub_lo
5057 },
5058 { // IntRegs
5059 0, // isub_hi
5060 0, // isub_lo
5061 0, // subreg_overflow
5062 0, // vsub_fake
5063 0, // vsub_hi
5064 0, // vsub_lo
5065 0, // wsub_hi
5066 0, // wsub_lo
5067 0, // wsub_hi_then_vsub_fake
5068 0, // wsub_hi_then_vsub_hi
5069 0, // wsub_hi_then_vsub_lo
5070 },
5071 { // CtrRegs
5072 0, // isub_hi
5073 0, // isub_lo
5074 13, // subreg_overflow -> CtrRegs_with_subreg_overflow
5075 0, // vsub_fake
5076 0, // vsub_hi
5077 0, // vsub_lo
5078 0, // wsub_hi
5079 0, // wsub_lo
5080 0, // wsub_hi_then_vsub_fake
5081 0, // wsub_hi_then_vsub_hi
5082 0, // wsub_hi_then_vsub_lo
5083 },
5084 { // GeneralSubRegs
5085 0, // isub_hi
5086 0, // isub_lo
5087 0, // subreg_overflow
5088 0, // vsub_fake
5089 0, // vsub_hi
5090 0, // vsub_lo
5091 0, // wsub_hi
5092 0, // wsub_lo
5093 0, // wsub_hi_then_vsub_fake
5094 0, // wsub_hi_then_vsub_hi
5095 0, // wsub_hi_then_vsub_lo
5096 },
5097 { // V62Regs
5098 11, // isub_hi -> V62Regs_with_isub_hi
5099 11, // isub_lo -> V62Regs_with_isub_hi
5100 0, // subreg_overflow
5101 0, // vsub_fake
5102 0, // vsub_hi
5103 0, // vsub_lo
5104 0, // wsub_hi
5105 0, // wsub_lo
5106 0, // wsub_hi_then_vsub_fake
5107 0, // wsub_hi_then_vsub_hi
5108 0, // wsub_hi_then_vsub_lo
5109 },
5110 { // IntRegsLow8
5111 0, // isub_hi
5112 0, // isub_lo
5113 0, // subreg_overflow
5114 0, // vsub_fake
5115 0, // vsub_hi
5116 0, // vsub_lo
5117 0, // wsub_hi
5118 0, // wsub_lo
5119 0, // wsub_hi_then_vsub_fake
5120 0, // wsub_hi_then_vsub_hi
5121 0, // wsub_hi_then_vsub_lo
5122 },
5123 { // CtrRegs_and_V62Regs
5124 0, // isub_hi
5125 0, // isub_lo
5126 0, // subreg_overflow
5127 0, // vsub_fake
5128 0, // vsub_hi
5129 0, // vsub_lo
5130 0, // wsub_hi
5131 0, // wsub_lo
5132 0, // wsub_hi_then_vsub_fake
5133 0, // wsub_hi_then_vsub_hi
5134 0, // wsub_hi_then_vsub_lo
5135 },
5136 { // PredRegs
5137 0, // isub_hi
5138 0, // isub_lo
5139 0, // subreg_overflow
5140 0, // vsub_fake
5141 0, // vsub_hi
5142 0, // vsub_lo
5143 0, // wsub_hi
5144 0, // wsub_lo
5145 0, // wsub_hi_then_vsub_fake
5146 0, // wsub_hi_then_vsub_hi
5147 0, // wsub_hi_then_vsub_lo
5148 },
5149 { // V62Regs_with_isub_hi
5150 11, // isub_hi -> V62Regs_with_isub_hi
5151 11, // isub_lo -> V62Regs_with_isub_hi
5152 0, // subreg_overflow
5153 0, // vsub_fake
5154 0, // vsub_hi
5155 0, // vsub_lo
5156 0, // wsub_hi
5157 0, // wsub_lo
5158 0, // wsub_hi_then_vsub_fake
5159 0, // wsub_hi_then_vsub_hi
5160 0, // wsub_hi_then_vsub_lo
5161 },
5162 { // ModRegs
5163 0, // isub_hi
5164 0, // isub_lo
5165 0, // subreg_overflow
5166 0, // vsub_fake
5167 0, // vsub_hi
5168 0, // vsub_lo
5169 0, // wsub_hi
5170 0, // wsub_lo
5171 0, // wsub_hi_then_vsub_fake
5172 0, // wsub_hi_then_vsub_hi
5173 0, // wsub_hi_then_vsub_lo
5174 },
5175 { // CtrRegs_with_subreg_overflow
5176 0, // isub_hi
5177 0, // isub_lo
5178 13, // subreg_overflow -> CtrRegs_with_subreg_overflow
5179 0, // vsub_fake
5180 0, // vsub_hi
5181 0, // vsub_lo
5182 0, // wsub_hi
5183 0, // wsub_lo
5184 0, // wsub_hi_then_vsub_fake
5185 0, // wsub_hi_then_vsub_hi
5186 0, // wsub_hi_then_vsub_lo
5187 },
5188 { // V65Regs
5189 0, // isub_hi
5190 0, // isub_lo
5191 0, // subreg_overflow
5192 0, // vsub_fake
5193 0, // vsub_hi
5194 0, // vsub_lo
5195 0, // wsub_hi
5196 0, // wsub_lo
5197 0, // wsub_hi_then_vsub_fake
5198 0, // wsub_hi_then_vsub_hi
5199 0, // wsub_hi_then_vsub_lo
5200 },
5201 { // SysRegs64
5202 15, // isub_hi -> SysRegs64
5203 15, // isub_lo -> SysRegs64
5204 0, // subreg_overflow
5205 0, // vsub_fake
5206 0, // vsub_hi
5207 0, // vsub_lo
5208 0, // wsub_hi
5209 0, // wsub_lo
5210 0, // wsub_hi_then_vsub_fake
5211 0, // wsub_hi_then_vsub_hi
5212 0, // wsub_hi_then_vsub_lo
5213 },
5214 { // DoubleRegs
5215 16, // isub_hi -> DoubleRegs
5216 16, // isub_lo -> DoubleRegs
5217 0, // subreg_overflow
5218 0, // vsub_fake
5219 0, // vsub_hi
5220 0, // vsub_lo
5221 0, // wsub_hi
5222 0, // wsub_lo
5223 0, // wsub_hi_then_vsub_fake
5224 0, // wsub_hi_then_vsub_hi
5225 0, // wsub_hi_then_vsub_lo
5226 },
5227 { // GuestRegs64
5228 17, // isub_hi -> GuestRegs64
5229 17, // isub_lo -> GuestRegs64
5230 0, // subreg_overflow
5231 0, // vsub_fake
5232 0, // vsub_hi
5233 0, // vsub_lo
5234 0, // wsub_hi
5235 0, // wsub_lo
5236 0, // wsub_hi_then_vsub_fake
5237 0, // wsub_hi_then_vsub_hi
5238 0, // wsub_hi_then_vsub_lo
5239 },
5240 { // VectRegRev
5241 0, // isub_hi
5242 0, // isub_lo
5243 0, // subreg_overflow
5244 18, // vsub_fake -> VectRegRev
5245 18, // vsub_hi -> VectRegRev
5246 18, // vsub_lo -> VectRegRev
5247 0, // wsub_hi
5248 0, // wsub_lo
5249 0, // wsub_hi_then_vsub_fake
5250 0, // wsub_hi_then_vsub_hi
5251 0, // wsub_hi_then_vsub_lo
5252 },
5253 { // CtrRegs64
5254 19, // isub_hi -> CtrRegs64
5255 19, // isub_lo -> CtrRegs64
5256 0, // subreg_overflow
5257 0, // vsub_fake
5258 0, // vsub_hi
5259 0, // vsub_lo
5260 0, // wsub_hi
5261 0, // wsub_lo
5262 0, // wsub_hi_then_vsub_fake
5263 0, // wsub_hi_then_vsub_hi
5264 0, // wsub_hi_then_vsub_lo
5265 },
5266 { // GeneralDoubleLow8Regs
5267 20, // isub_hi -> GeneralDoubleLow8Regs
5268 20, // isub_lo -> GeneralDoubleLow8Regs
5269 0, // subreg_overflow
5270 0, // vsub_fake
5271 0, // vsub_hi
5272 0, // vsub_lo
5273 0, // wsub_hi
5274 0, // wsub_lo
5275 0, // wsub_hi_then_vsub_fake
5276 0, // wsub_hi_then_vsub_hi
5277 0, // wsub_hi_then_vsub_lo
5278 },
5279 { // DoubleRegs_with_isub_hi_in_IntRegsLow8
5280 21, // isub_hi -> DoubleRegs_with_isub_hi_in_IntRegsLow8
5281 21, // isub_lo -> DoubleRegs_with_isub_hi_in_IntRegsLow8
5282 0, // subreg_overflow
5283 0, // vsub_fake
5284 0, // vsub_hi
5285 0, // vsub_lo
5286 0, // wsub_hi
5287 0, // wsub_lo
5288 0, // wsub_hi_then_vsub_fake
5289 0, // wsub_hi_then_vsub_hi
5290 0, // wsub_hi_then_vsub_lo
5291 },
5292 { // CtrRegs64_and_V62Regs
5293 22, // isub_hi -> CtrRegs64_and_V62Regs
5294 22, // isub_lo -> CtrRegs64_and_V62Regs
5295 0, // subreg_overflow
5296 0, // vsub_fake
5297 0, // vsub_hi
5298 0, // vsub_lo
5299 0, // wsub_hi
5300 0, // wsub_lo
5301 0, // wsub_hi_then_vsub_fake
5302 0, // wsub_hi_then_vsub_hi
5303 0, // wsub_hi_then_vsub_lo
5304 },
5305 { // CtrRegs64_with_isub_hi_in_ModRegs
5306 23, // isub_hi -> CtrRegs64_with_isub_hi_in_ModRegs
5307 23, // isub_lo -> CtrRegs64_with_isub_hi_in_ModRegs
5308 0, // subreg_overflow
5309 0, // vsub_fake
5310 0, // vsub_hi
5311 0, // vsub_lo
5312 0, // wsub_hi
5313 0, // wsub_lo
5314 0, // wsub_hi_then_vsub_fake
5315 0, // wsub_hi_then_vsub_hi
5316 0, // wsub_hi_then_vsub_lo
5317 },
5318 { // HvxQR
5319 0, // isub_hi
5320 0, // isub_lo
5321 0, // subreg_overflow
5322 0, // vsub_fake
5323 0, // vsub_hi
5324 0, // vsub_lo
5325 0, // wsub_hi
5326 0, // wsub_lo
5327 0, // wsub_hi_then_vsub_fake
5328 0, // wsub_hi_then_vsub_hi
5329 0, // wsub_hi_then_vsub_lo
5330 },
5331 { // HvxVR
5332 0, // isub_hi
5333 0, // isub_lo
5334 0, // subreg_overflow
5335 0, // vsub_fake
5336 0, // vsub_hi
5337 0, // vsub_lo
5338 0, // wsub_hi
5339 0, // wsub_lo
5340 0, // wsub_hi_then_vsub_fake
5341 0, // wsub_hi_then_vsub_hi
5342 0, // wsub_hi_then_vsub_lo
5343 },
5344 { // HvxVR_and_V65Regs
5345 0, // isub_hi
5346 0, // isub_lo
5347 0, // subreg_overflow
5348 0, // vsub_fake
5349 0, // vsub_hi
5350 0, // vsub_lo
5351 0, // wsub_hi
5352 0, // wsub_lo
5353 0, // wsub_hi_then_vsub_fake
5354 0, // wsub_hi_then_vsub_hi
5355 0, // wsub_hi_then_vsub_lo
5356 },
5357 { // HvxWR
5358 0, // isub_hi
5359 0, // isub_lo
5360 0, // subreg_overflow
5361 27, // vsub_fake -> HvxWR
5362 27, // vsub_hi -> HvxWR
5363 27, // vsub_lo -> HvxWR
5364 0, // wsub_hi
5365 0, // wsub_lo
5366 0, // wsub_hi_then_vsub_fake
5367 0, // wsub_hi_then_vsub_hi
5368 0, // wsub_hi_then_vsub_lo
5369 },
5370 { // HvxWR_and_VectRegRev
5371 0, // isub_hi
5372 0, // isub_lo
5373 0, // subreg_overflow
5374 28, // vsub_fake -> HvxWR_and_VectRegRev
5375 28, // vsub_hi -> HvxWR_and_VectRegRev
5376 28, // vsub_lo -> HvxWR_and_VectRegRev
5377 0, // wsub_hi
5378 0, // wsub_lo
5379 0, // wsub_hi_then_vsub_fake
5380 0, // wsub_hi_then_vsub_hi
5381 0, // wsub_hi_then_vsub_lo
5382 },
5383 { // HvxVQR
5384 0, // isub_hi
5385 0, // isub_lo
5386 0, // subreg_overflow
5387 29, // vsub_fake -> HvxVQR
5388 29, // vsub_hi -> HvxVQR
5389 29, // vsub_lo -> HvxVQR
5390 29, // wsub_hi -> HvxVQR
5391 29, // wsub_lo -> HvxVQR
5392 29, // wsub_hi_then_vsub_fake -> HvxVQR
5393 29, // wsub_hi_then_vsub_hi -> HvxVQR
5394 29, // wsub_hi_then_vsub_lo -> HvxVQR
5395 },
5396 };
5397 assert(RC && "Missing regclass");
5398 if (!Idx) return RC;
5399 --Idx;
5400 assert(Idx < 11 && "Bad subreg");
5401 unsigned TV = Table[RC->getID()][Idx];
5402 return TV ? getRegClass(TV - 1) : nullptr;
5403}
5404
5405const TargetRegisterClass *HexagonGenRegisterInfo::getSubRegisterClass(const TargetRegisterClass *RC, unsigned Idx) const {
5406 static const uint8_t Table[29][11] = {
5407 { // UsrBits
5408 0, // UsrBits:isub_hi
5409 0, // UsrBits:isub_lo
5410 0, // UsrBits:subreg_overflow
5411 0, // UsrBits:vsub_fake
5412 0, // UsrBits:vsub_hi
5413 0, // UsrBits:vsub_lo
5414 0, // UsrBits:wsub_hi
5415 0, // UsrBits:wsub_lo
5416 0, // UsrBits:wsub_hi_then_vsub_fake
5417 0, // UsrBits:wsub_hi_then_vsub_hi
5418 0, // UsrBits:wsub_hi_then_vsub_lo
5419 },
5420 { // SysRegs
5421 0, // SysRegs:isub_hi
5422 0, // SysRegs:isub_lo
5423 0, // SysRegs:subreg_overflow
5424 0, // SysRegs:vsub_fake
5425 0, // SysRegs:vsub_hi
5426 0, // SysRegs:vsub_lo
5427 0, // SysRegs:wsub_hi
5428 0, // SysRegs:wsub_lo
5429 0, // SysRegs:wsub_hi_then_vsub_fake
5430 0, // SysRegs:wsub_hi_then_vsub_hi
5431 0, // SysRegs:wsub_hi_then_vsub_lo
5432 },
5433 { // GuestRegs
5434 0, // GuestRegs:isub_hi
5435 0, // GuestRegs:isub_lo
5436 0, // GuestRegs:subreg_overflow
5437 0, // GuestRegs:vsub_fake
5438 0, // GuestRegs:vsub_hi
5439 0, // GuestRegs:vsub_lo
5440 0, // GuestRegs:wsub_hi
5441 0, // GuestRegs:wsub_lo
5442 0, // GuestRegs:wsub_hi_then_vsub_fake
5443 0, // GuestRegs:wsub_hi_then_vsub_hi
5444 0, // GuestRegs:wsub_hi_then_vsub_lo
5445 },
5446 { // IntRegs
5447 0, // IntRegs:isub_hi
5448 0, // IntRegs:isub_lo
5449 0, // IntRegs:subreg_overflow
5450 0, // IntRegs:vsub_fake
5451 0, // IntRegs:vsub_hi
5452 0, // IntRegs:vsub_lo
5453 0, // IntRegs:wsub_hi
5454 0, // IntRegs:wsub_lo
5455 0, // IntRegs:wsub_hi_then_vsub_fake
5456 0, // IntRegs:wsub_hi_then_vsub_hi
5457 0, // IntRegs:wsub_hi_then_vsub_lo
5458 },
5459 { // CtrRegs
5460 0, // CtrRegs:isub_hi
5461 0, // CtrRegs:isub_lo
5462 1, // CtrRegs:subreg_overflow -> UsrBits
5463 0, // CtrRegs:vsub_fake
5464 0, // CtrRegs:vsub_hi
5465 0, // CtrRegs:vsub_lo
5466 0, // CtrRegs:wsub_hi
5467 0, // CtrRegs:wsub_lo
5468 0, // CtrRegs:wsub_hi_then_vsub_fake
5469 0, // CtrRegs:wsub_hi_then_vsub_hi
5470 0, // CtrRegs:wsub_hi_then_vsub_lo
5471 },
5472 { // GeneralSubRegs
5473 0, // GeneralSubRegs:isub_hi
5474 0, // GeneralSubRegs:isub_lo
5475 0, // GeneralSubRegs:subreg_overflow
5476 0, // GeneralSubRegs:vsub_fake
5477 0, // GeneralSubRegs:vsub_hi
5478 0, // GeneralSubRegs:vsub_lo
5479 0, // GeneralSubRegs:wsub_hi
5480 0, // GeneralSubRegs:wsub_lo
5481 0, // GeneralSubRegs:wsub_hi_then_vsub_fake
5482 0, // GeneralSubRegs:wsub_hi_then_vsub_hi
5483 0, // GeneralSubRegs:wsub_hi_then_vsub_lo
5484 },
5485 { // V62Regs
5486 9, // V62Regs:isub_hi -> CtrRegs_and_V62Regs
5487 9, // V62Regs:isub_lo -> CtrRegs_and_V62Regs
5488 0, // V62Regs:subreg_overflow
5489 0, // V62Regs:vsub_fake
5490 0, // V62Regs:vsub_hi
5491 0, // V62Regs:vsub_lo
5492 0, // V62Regs:wsub_hi
5493 0, // V62Regs:wsub_lo
5494 0, // V62Regs:wsub_hi_then_vsub_fake
5495 0, // V62Regs:wsub_hi_then_vsub_hi
5496 0, // V62Regs:wsub_hi_then_vsub_lo
5497 },
5498 { // IntRegsLow8
5499 0, // IntRegsLow8:isub_hi
5500 0, // IntRegsLow8:isub_lo
5501 0, // IntRegsLow8:subreg_overflow
5502 0, // IntRegsLow8:vsub_fake
5503 0, // IntRegsLow8:vsub_hi
5504 0, // IntRegsLow8:vsub_lo
5505 0, // IntRegsLow8:wsub_hi
5506 0, // IntRegsLow8:wsub_lo
5507 0, // IntRegsLow8:wsub_hi_then_vsub_fake
5508 0, // IntRegsLow8:wsub_hi_then_vsub_hi
5509 0, // IntRegsLow8:wsub_hi_then_vsub_lo
5510 },
5511 { // CtrRegs_and_V62Regs
5512 0, // CtrRegs_and_V62Regs:isub_hi
5513 0, // CtrRegs_and_V62Regs:isub_lo
5514 0, // CtrRegs_and_V62Regs:subreg_overflow
5515 0, // CtrRegs_and_V62Regs:vsub_fake
5516 0, // CtrRegs_and_V62Regs:vsub_hi
5517 0, // CtrRegs_and_V62Regs:vsub_lo
5518 0, // CtrRegs_and_V62Regs:wsub_hi
5519 0, // CtrRegs_and_V62Regs:wsub_lo
5520 0, // CtrRegs_and_V62Regs:wsub_hi_then_vsub_fake
5521 0, // CtrRegs_and_V62Regs:wsub_hi_then_vsub_hi
5522 0, // CtrRegs_and_V62Regs:wsub_hi_then_vsub_lo
5523 },
5524 { // PredRegs
5525 0, // PredRegs:isub_hi
5526 0, // PredRegs:isub_lo
5527 0, // PredRegs:subreg_overflow
5528 0, // PredRegs:vsub_fake
5529 0, // PredRegs:vsub_hi
5530 0, // PredRegs:vsub_lo
5531 0, // PredRegs:wsub_hi
5532 0, // PredRegs:wsub_lo
5533 0, // PredRegs:wsub_hi_then_vsub_fake
5534 0, // PredRegs:wsub_hi_then_vsub_hi
5535 0, // PredRegs:wsub_hi_then_vsub_lo
5536 },
5537 { // V62Regs_with_isub_hi
5538 9, // V62Regs_with_isub_hi:isub_hi -> CtrRegs_and_V62Regs
5539 9, // V62Regs_with_isub_hi:isub_lo -> CtrRegs_and_V62Regs
5540 0, // V62Regs_with_isub_hi:subreg_overflow
5541 0, // V62Regs_with_isub_hi:vsub_fake
5542 0, // V62Regs_with_isub_hi:vsub_hi
5543 0, // V62Regs_with_isub_hi:vsub_lo
5544 0, // V62Regs_with_isub_hi:wsub_hi
5545 0, // V62Regs_with_isub_hi:wsub_lo
5546 0, // V62Regs_with_isub_hi:wsub_hi_then_vsub_fake
5547 0, // V62Regs_with_isub_hi:wsub_hi_then_vsub_hi
5548 0, // V62Regs_with_isub_hi:wsub_hi_then_vsub_lo
5549 },
5550 { // ModRegs
5551 0, // ModRegs:isub_hi
5552 0, // ModRegs:isub_lo
5553 0, // ModRegs:subreg_overflow
5554 0, // ModRegs:vsub_fake
5555 0, // ModRegs:vsub_hi
5556 0, // ModRegs:vsub_lo
5557 0, // ModRegs:wsub_hi
5558 0, // ModRegs:wsub_lo
5559 0, // ModRegs:wsub_hi_then_vsub_fake
5560 0, // ModRegs:wsub_hi_then_vsub_hi
5561 0, // ModRegs:wsub_hi_then_vsub_lo
5562 },
5563 { // CtrRegs_with_subreg_overflow
5564 0, // CtrRegs_with_subreg_overflow:isub_hi
5565 0, // CtrRegs_with_subreg_overflow:isub_lo
5566 1, // CtrRegs_with_subreg_overflow:subreg_overflow -> UsrBits
5567 0, // CtrRegs_with_subreg_overflow:vsub_fake
5568 0, // CtrRegs_with_subreg_overflow:vsub_hi
5569 0, // CtrRegs_with_subreg_overflow:vsub_lo
5570 0, // CtrRegs_with_subreg_overflow:wsub_hi
5571 0, // CtrRegs_with_subreg_overflow:wsub_lo
5572 0, // CtrRegs_with_subreg_overflow:wsub_hi_then_vsub_fake
5573 0, // CtrRegs_with_subreg_overflow:wsub_hi_then_vsub_hi
5574 0, // CtrRegs_with_subreg_overflow:wsub_hi_then_vsub_lo
5575 },
5576 { // V65Regs
5577 0, // V65Regs:isub_hi
5578 0, // V65Regs:isub_lo
5579 0, // V65Regs:subreg_overflow
5580 0, // V65Regs:vsub_fake
5581 0, // V65Regs:vsub_hi
5582 0, // V65Regs:vsub_lo
5583 0, // V65Regs:wsub_hi
5584 0, // V65Regs:wsub_lo
5585 0, // V65Regs:wsub_hi_then_vsub_fake
5586 0, // V65Regs:wsub_hi_then_vsub_hi
5587 0, // V65Regs:wsub_hi_then_vsub_lo
5588 },
5589 { // SysRegs64
5590 2, // SysRegs64:isub_hi -> SysRegs
5591 2, // SysRegs64:isub_lo -> SysRegs
5592 0, // SysRegs64:subreg_overflow
5593 0, // SysRegs64:vsub_fake
5594 0, // SysRegs64:vsub_hi
5595 0, // SysRegs64:vsub_lo
5596 0, // SysRegs64:wsub_hi
5597 0, // SysRegs64:wsub_lo
5598 0, // SysRegs64:wsub_hi_then_vsub_fake
5599 0, // SysRegs64:wsub_hi_then_vsub_hi
5600 0, // SysRegs64:wsub_hi_then_vsub_lo
5601 },
5602 { // DoubleRegs
5603 4, // DoubleRegs:isub_hi -> IntRegs
5604 4, // DoubleRegs:isub_lo -> IntRegs
5605 0, // DoubleRegs:subreg_overflow
5606 0, // DoubleRegs:vsub_fake
5607 0, // DoubleRegs:vsub_hi
5608 0, // DoubleRegs:vsub_lo
5609 0, // DoubleRegs:wsub_hi
5610 0, // DoubleRegs:wsub_lo
5611 0, // DoubleRegs:wsub_hi_then_vsub_fake
5612 0, // DoubleRegs:wsub_hi_then_vsub_hi
5613 0, // DoubleRegs:wsub_hi_then_vsub_lo
5614 },
5615 { // GuestRegs64
5616 3, // GuestRegs64:isub_hi -> GuestRegs
5617 3, // GuestRegs64:isub_lo -> GuestRegs
5618 0, // GuestRegs64:subreg_overflow
5619 0, // GuestRegs64:vsub_fake
5620 0, // GuestRegs64:vsub_hi
5621 0, // GuestRegs64:vsub_lo
5622 0, // GuestRegs64:wsub_hi
5623 0, // GuestRegs64:wsub_lo
5624 0, // GuestRegs64:wsub_hi_then_vsub_fake
5625 0, // GuestRegs64:wsub_hi_then_vsub_hi
5626 0, // GuestRegs64:wsub_hi_then_vsub_lo
5627 },
5628 { // VectRegRev
5629 0, // VectRegRev:isub_hi
5630 0, // VectRegRev:isub_lo
5631 0, // VectRegRev:subreg_overflow
5632 0, // VectRegRev:vsub_fake
5633 25, // VectRegRev:vsub_hi -> HvxVR
5634 25, // VectRegRev:vsub_lo -> HvxVR
5635 0, // VectRegRev:wsub_hi
5636 0, // VectRegRev:wsub_lo
5637 0, // VectRegRev:wsub_hi_then_vsub_fake
5638 0, // VectRegRev:wsub_hi_then_vsub_hi
5639 0, // VectRegRev:wsub_hi_then_vsub_lo
5640 },
5641 { // CtrRegs64
5642 5, // CtrRegs64:isub_hi -> CtrRegs
5643 5, // CtrRegs64:isub_lo -> CtrRegs
5644 0, // CtrRegs64:subreg_overflow
5645 0, // CtrRegs64:vsub_fake
5646 0, // CtrRegs64:vsub_hi
5647 0, // CtrRegs64:vsub_lo
5648 0, // CtrRegs64:wsub_hi
5649 0, // CtrRegs64:wsub_lo
5650 0, // CtrRegs64:wsub_hi_then_vsub_fake
5651 0, // CtrRegs64:wsub_hi_then_vsub_hi
5652 0, // CtrRegs64:wsub_hi_then_vsub_lo
5653 },
5654 { // GeneralDoubleLow8Regs
5655 6, // GeneralDoubleLow8Regs:isub_hi -> GeneralSubRegs
5656 6, // GeneralDoubleLow8Regs:isub_lo -> GeneralSubRegs
5657 0, // GeneralDoubleLow8Regs:subreg_overflow
5658 0, // GeneralDoubleLow8Regs:vsub_fake
5659 0, // GeneralDoubleLow8Regs:vsub_hi
5660 0, // GeneralDoubleLow8Regs:vsub_lo
5661 0, // GeneralDoubleLow8Regs:wsub_hi
5662 0, // GeneralDoubleLow8Regs:wsub_lo
5663 0, // GeneralDoubleLow8Regs:wsub_hi_then_vsub_fake
5664 0, // GeneralDoubleLow8Regs:wsub_hi_then_vsub_hi
5665 0, // GeneralDoubleLow8Regs:wsub_hi_then_vsub_lo
5666 },
5667 { // DoubleRegs_with_isub_hi_in_IntRegsLow8
5668 8, // DoubleRegs_with_isub_hi_in_IntRegsLow8:isub_hi -> IntRegsLow8
5669 8, // DoubleRegs_with_isub_hi_in_IntRegsLow8:isub_lo -> IntRegsLow8
5670 0, // DoubleRegs_with_isub_hi_in_IntRegsLow8:subreg_overflow
5671 0, // DoubleRegs_with_isub_hi_in_IntRegsLow8:vsub_fake
5672 0, // DoubleRegs_with_isub_hi_in_IntRegsLow8:vsub_hi
5673 0, // DoubleRegs_with_isub_hi_in_IntRegsLow8:vsub_lo
5674 0, // DoubleRegs_with_isub_hi_in_IntRegsLow8:wsub_hi
5675 0, // DoubleRegs_with_isub_hi_in_IntRegsLow8:wsub_lo
5676 0, // DoubleRegs_with_isub_hi_in_IntRegsLow8:wsub_hi_then_vsub_fake
5677 0, // DoubleRegs_with_isub_hi_in_IntRegsLow8:wsub_hi_then_vsub_hi
5678 0, // DoubleRegs_with_isub_hi_in_IntRegsLow8:wsub_hi_then_vsub_lo
5679 },
5680 { // CtrRegs64_and_V62Regs
5681 9, // CtrRegs64_and_V62Regs:isub_hi -> CtrRegs_and_V62Regs
5682 9, // CtrRegs64_and_V62Regs:isub_lo -> CtrRegs_and_V62Regs
5683 0, // CtrRegs64_and_V62Regs:subreg_overflow
5684 0, // CtrRegs64_and_V62Regs:vsub_fake
5685 0, // CtrRegs64_and_V62Regs:vsub_hi
5686 0, // CtrRegs64_and_V62Regs:vsub_lo
5687 0, // CtrRegs64_and_V62Regs:wsub_hi
5688 0, // CtrRegs64_and_V62Regs:wsub_lo
5689 0, // CtrRegs64_and_V62Regs:wsub_hi_then_vsub_fake
5690 0, // CtrRegs64_and_V62Regs:wsub_hi_then_vsub_hi
5691 0, // CtrRegs64_and_V62Regs:wsub_hi_then_vsub_lo
5692 },
5693 { // CtrRegs64_with_isub_hi_in_ModRegs
5694 12, // CtrRegs64_with_isub_hi_in_ModRegs:isub_hi -> ModRegs
5695 12, // CtrRegs64_with_isub_hi_in_ModRegs:isub_lo -> ModRegs
5696 0, // CtrRegs64_with_isub_hi_in_ModRegs:subreg_overflow
5697 0, // CtrRegs64_with_isub_hi_in_ModRegs:vsub_fake
5698 0, // CtrRegs64_with_isub_hi_in_ModRegs:vsub_hi
5699 0, // CtrRegs64_with_isub_hi_in_ModRegs:vsub_lo
5700 0, // CtrRegs64_with_isub_hi_in_ModRegs:wsub_hi
5701 0, // CtrRegs64_with_isub_hi_in_ModRegs:wsub_lo
5702 0, // CtrRegs64_with_isub_hi_in_ModRegs:wsub_hi_then_vsub_fake
5703 0, // CtrRegs64_with_isub_hi_in_ModRegs:wsub_hi_then_vsub_hi
5704 0, // CtrRegs64_with_isub_hi_in_ModRegs:wsub_hi_then_vsub_lo
5705 },
5706 { // HvxQR
5707 0, // HvxQR:isub_hi
5708 0, // HvxQR:isub_lo
5709 0, // HvxQR:subreg_overflow
5710 0, // HvxQR:vsub_fake
5711 0, // HvxQR:vsub_hi
5712 0, // HvxQR:vsub_lo
5713 0, // HvxQR:wsub_hi
5714 0, // HvxQR:wsub_lo
5715 0, // HvxQR:wsub_hi_then_vsub_fake
5716 0, // HvxQR:wsub_hi_then_vsub_hi
5717 0, // HvxQR:wsub_hi_then_vsub_lo
5718 },
5719 { // HvxVR
5720 0, // HvxVR:isub_hi
5721 0, // HvxVR:isub_lo
5722 0, // HvxVR:subreg_overflow
5723 0, // HvxVR:vsub_fake
5724 0, // HvxVR:vsub_hi
5725 0, // HvxVR:vsub_lo
5726 0, // HvxVR:wsub_hi
5727 0, // HvxVR:wsub_lo
5728 0, // HvxVR:wsub_hi_then_vsub_fake
5729 0, // HvxVR:wsub_hi_then_vsub_hi
5730 0, // HvxVR:wsub_hi_then_vsub_lo
5731 },
5732 { // HvxVR_and_V65Regs
5733 0, // HvxVR_and_V65Regs:isub_hi
5734 0, // HvxVR_and_V65Regs:isub_lo
5735 0, // HvxVR_and_V65Regs:subreg_overflow
5736 0, // HvxVR_and_V65Regs:vsub_fake
5737 0, // HvxVR_and_V65Regs:vsub_hi
5738 0, // HvxVR_and_V65Regs:vsub_lo
5739 0, // HvxVR_and_V65Regs:wsub_hi
5740 0, // HvxVR_and_V65Regs:wsub_lo
5741 0, // HvxVR_and_V65Regs:wsub_hi_then_vsub_fake
5742 0, // HvxVR_and_V65Regs:wsub_hi_then_vsub_hi
5743 0, // HvxVR_and_V65Regs:wsub_hi_then_vsub_lo
5744 },
5745 { // HvxWR
5746 0, // HvxWR:isub_hi
5747 0, // HvxWR:isub_lo
5748 0, // HvxWR:subreg_overflow
5749 0, // HvxWR:vsub_fake
5750 25, // HvxWR:vsub_hi -> HvxVR
5751 25, // HvxWR:vsub_lo -> HvxVR
5752 0, // HvxWR:wsub_hi
5753 0, // HvxWR:wsub_lo
5754 0, // HvxWR:wsub_hi_then_vsub_fake
5755 0, // HvxWR:wsub_hi_then_vsub_hi
5756 0, // HvxWR:wsub_hi_then_vsub_lo
5757 },
5758 { // HvxWR_and_VectRegRev
5759 0, // HvxWR_and_VectRegRev:isub_hi
5760 0, // HvxWR_and_VectRegRev:isub_lo
5761 0, // HvxWR_and_VectRegRev:subreg_overflow
5762 0, // HvxWR_and_VectRegRev:vsub_fake
5763 25, // HvxWR_and_VectRegRev:vsub_hi -> HvxVR
5764 25, // HvxWR_and_VectRegRev:vsub_lo -> HvxVR
5765 0, // HvxWR_and_VectRegRev:wsub_hi
5766 0, // HvxWR_and_VectRegRev:wsub_lo
5767 0, // HvxWR_and_VectRegRev:wsub_hi_then_vsub_fake
5768 0, // HvxWR_and_VectRegRev:wsub_hi_then_vsub_hi
5769 0, // HvxWR_and_VectRegRev:wsub_hi_then_vsub_lo
5770 },
5771 { // HvxVQR
5772 0, // HvxVQR:isub_hi
5773 0, // HvxVQR:isub_lo
5774 0, // HvxVQR:subreg_overflow
5775 0, // HvxVQR:vsub_fake
5776 25, // HvxVQR:vsub_hi -> HvxVR
5777 25, // HvxVQR:vsub_lo -> HvxVR
5778 27, // HvxVQR:wsub_hi -> HvxWR
5779 27, // HvxVQR:wsub_lo -> HvxWR
5780 0, // HvxVQR:wsub_hi_then_vsub_fake
5781 25, // HvxVQR:wsub_hi_then_vsub_hi -> HvxVR
5782 25, // HvxVQR:wsub_hi_then_vsub_lo -> HvxVR
5783 },
5784 };
5785 assert(RC && "Missing regclass");
5786 if (!Idx) return RC;
5787 --Idx;
5788 assert(Idx < 11 && "Bad subreg");
5789 unsigned TV = Table[RC->getID()][Idx];
5790 return TV ? getRegClass(TV - 1) : nullptr;
5791}
5792
5793/// Get the weight in units of pressure for this register class.
5794const RegClassWeight &HexagonGenRegisterInfo::
5795getRegClassWeight(const TargetRegisterClass *RC) const {
5796 static const RegClassWeight RCWeightTable[] = {
5797 {0, 0}, // UsrBits
5798 {0, 0}, // SysRegs
5799 {0, 0}, // GuestRegs
5800 {1, 32}, // IntRegs
5801 {0, 6}, // CtrRegs
5802 {1, 16}, // GeneralSubRegs
5803 {0, 0}, // V62Regs
5804 {1, 8}, // IntRegsLow8
5805 {0, 0}, // CtrRegs_and_V62Regs
5806 {2, 8}, // PredRegs
5807 {0, 0}, // V62Regs_with_isub_hi
5808 {1, 2}, // ModRegs
5809 {0, 0}, // CtrRegs_with_subreg_overflow
5810 {1, 1}, // V65Regs
5811 {0, 0}, // SysRegs64
5812 {2, 32}, // DoubleRegs
5813 {0, 0}, // GuestRegs64
5814 {2, 32}, // VectRegRev
5815 {0, 6}, // CtrRegs64
5816 {2, 16}, // GeneralDoubleLow8Regs
5817 {2, 8}, // DoubleRegs_with_isub_hi_in_IntRegsLow8
5818 {0, 0}, // CtrRegs64_and_V62Regs
5819 {2, 2}, // CtrRegs64_with_isub_hi_in_ModRegs
5820 {1, 4}, // HvxQR
5821 {1, 33}, // HvxVR
5822 {1, 1}, // HvxVR_and_V65Regs
5823 {2, 32}, // HvxWR
5824 {2, 32}, // HvxWR_and_VectRegRev
5825 {4, 32}, // HvxVQR
5826 };
5827 return RCWeightTable[RC->getID()];
5828}
5829
5830/// Get the weight in units of pressure for this register unit.
5831unsigned HexagonGenRegisterInfo::
5832getRegUnitWeight(unsigned RegUnit) const {
5833 assert(RegUnit < 278 && "invalid register unit");
5834 // All register units have unit weight.
5835 return 1;
5836}
5837
5838
5839// Get the number of dimensions of register pressure.
5840unsigned HexagonGenRegisterInfo::getNumRegPressureSets() const {
5841 return 8;
5842}
5843
5844// Get the name of this register unit pressure set.
5845const char *HexagonGenRegisterInfo::
5846getRegPressureSetName(unsigned Idx) const {
5847 static const char *PressureNameTable[] = {
5848 "HvxVR_and_V65Regs",
5849 "ModRegs",
5850 "HvxQR",
5851 "IntRegsLow8",
5852 "PredRegs",
5853 "GeneralSubRegs",
5854 "IntRegs",
5855 "HvxVR",
5856 };
5857 return PressureNameTable[Idx];
5858}
5859
5860// Get the register unit pressure limit for this dimension.
5861// This limit must be adjusted dynamically for reserved registers.
5862unsigned HexagonGenRegisterInfo::
5863getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
5864 static const uint8_t PressureLimitTable[] = {
5865 1, // 0: HvxVR_and_V65Regs
5866 2, // 1: ModRegs
5867 4, // 2: HvxQR
5868 8, // 3: IntRegsLow8
5869 8, // 4: PredRegs
5870 16, // 5: GeneralSubRegs
5871 32, // 6: IntRegs
5872 33, // 7: HvxVR
5873 };
5874 return PressureLimitTable[Idx];
5875}
5876
5877/// Table of pressure sets per register class or unit.
5878static const int RCSetsTable[] = {
5879 /* 0 */ 1, -1,
5880 /* 2 */ 2, -1,
5881 /* 4 */ 4, -1,
5882 /* 6 */ 3, 5, 6, -1,
5883 /* 10 */ 0, 7, -1,
5884};
5885
5886/// Get the dimensions of register pressure impacted by this register class.
5887/// Returns a -1 terminated array of pressure set IDs
5888const int *HexagonGenRegisterInfo::
5889getRegClassPressureSets(const TargetRegisterClass *RC) const {
5890 static const uint8_t RCSetStartTable[] = {
5891 1,1,1,8,1,7,1,6,1,4,1,0,1,1,1,8,1,11,1,7,6,1,1,2,11,10,11,11,11,};
5892 return &RCSetsTable[RCSetStartTable[RC->getID()]];
5893}
5894
5895/// Get the dimensions of register pressure impacted by this register unit.
5896/// Returns a -1 terminated array of pressure set IDs
5897const int *HexagonGenRegisterInfo::
5898getRegUnitPressureSets(unsigned RegUnit) const {
5899 assert(RegUnit < 278 && "invalid register unit");
5900 static const uint8_t RUSetStartTable[] = {
5901 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,10,1,1,1,1,1,1,1,1,6,6,6,6,6,6,6,6,8,8,8,8,8,8,8,8,7,7,7,7,7,7,7,7,8,8,8,8,8,8,8,8,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,4,4,4,4,4,4,4,4,1,1,1,1,2,2,2,2,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,};
5902 return &RCSetsTable[RUSetStartTable[RegUnit]];
5903}
5904
5905extern const MCRegisterDesc HexagonRegDesc[];
5906extern const int16_t HexagonRegDiffLists[];
5907extern const LaneBitmask HexagonLaneMaskLists[];
5908extern const char HexagonRegStrings[];
5909extern const char HexagonRegClassStrings[];
5910extern const MCPhysReg HexagonRegUnitRoots[][2];
5911extern const uint16_t HexagonSubRegIdxLists[];
5912extern const uint16_t HexagonRegEncodingTable[];
5913// Hexagon Dwarf<->LLVM register mappings.
5914extern const MCRegisterInfo::DwarfLLVMRegPair HexagonDwarfFlavour0Dwarf2L[];
5915extern const unsigned HexagonDwarfFlavour0Dwarf2LSize;
5916
5917extern const MCRegisterInfo::DwarfLLVMRegPair HexagonEHFlavour0Dwarf2L[];
5918extern const unsigned HexagonEHFlavour0Dwarf2LSize;
5919
5920extern const MCRegisterInfo::DwarfLLVMRegPair HexagonDwarfFlavour0L2Dwarf[];
5921extern const unsigned HexagonDwarfFlavour0L2DwarfSize;
5922
5923extern const MCRegisterInfo::DwarfLLVMRegPair HexagonEHFlavour0L2Dwarf[];
5924extern const unsigned HexagonEHFlavour0L2DwarfSize;
5925
5926HexagonGenRegisterInfo::
5927HexagonGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
5928 unsigned PC, unsigned HwMode)
5929 : TargetRegisterInfo(&HexagonRegInfoDesc, RegisterClasses, RegisterClasses+29,
5930 SubRegIndexNameTable, SubRegIdxRangeTable, SubRegIndexLaneMaskTable,
5931 LaneBitmask(0xFFFFFFFFFFFFFFFB), RegClassInfos, VTLists, HwMode) {
5932 InitMCRegisterInfo(HexagonRegDesc, 398, RA, PC,
5933 HexagonMCRegisterClasses, 29,
5934 HexagonRegUnitRoots,
5935 278,
5936 HexagonRegDiffLists,
5937 HexagonLaneMaskLists,
5938 HexagonRegStrings,
5939 HexagonRegClassStrings,
5940 HexagonSubRegIdxLists,
5941 12,
5942 HexagonRegEncodingTable);
5943
5944 switch (DwarfFlavour) {
5945 default:
5946 llvm_unreachable("Unknown DWARF flavour");
5947 case 0:
5948 mapDwarfRegsToLLVMRegs(HexagonDwarfFlavour0Dwarf2L, HexagonDwarfFlavour0Dwarf2LSize, false);
5949 break;
5950 }
5951 switch (EHFlavour) {
5952 default:
5953 llvm_unreachable("Unknown DWARF flavour");
5954 case 0:
5955 mapDwarfRegsToLLVMRegs(HexagonEHFlavour0Dwarf2L, HexagonEHFlavour0Dwarf2LSize, true);
5956 break;
5957 }
5958 switch (DwarfFlavour) {
5959 default:
5960 llvm_unreachable("Unknown DWARF flavour");
5961 case 0:
5962 mapLLVMRegsToDwarfRegs(HexagonDwarfFlavour0L2Dwarf, HexagonDwarfFlavour0L2DwarfSize, false);
5963 break;
5964 }
5965 switch (EHFlavour) {
5966 default:
5967 llvm_unreachable("Unknown DWARF flavour");
5968 case 0:
5969 mapLLVMRegsToDwarfRegs(HexagonEHFlavour0L2Dwarf, HexagonEHFlavour0L2DwarfSize, true);
5970 break;
5971 }
5972}
5973
5974static const MCPhysReg HexagonCSR_SaveList[] = { Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19, Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, Hexagon::R24, Hexagon::R25, Hexagon::R26, Hexagon::R27, 0 };
5975static const uint32_t HexagonCSR_RegMask[] = { 0x00000000, 0x00000000, 0x0000007e, 0x00000000, 0x0003ffc0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
5976
5977
5978ArrayRef<const uint32_t *> HexagonGenRegisterInfo::getRegMasks() const {
5979 static const uint32_t *const Masks[] = {
5980 HexagonCSR_RegMask,
5981 };
5982 return ArrayRef(Masks);
5983}
5984
5985bool HexagonGenRegisterInfo::
5986isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
5987 return
5988 false;
5989}
5990
5991bool HexagonGenRegisterInfo::
5992isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const {
5993 return
5994 false;
5995}
5996
5997bool HexagonGenRegisterInfo::
5998isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
5999 return
6000 false;
6001}
6002
6003bool HexagonGenRegisterInfo::
6004isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
6005 return
6006 false;
6007}
6008
6009bool HexagonGenRegisterInfo::
6010isConstantPhysReg(MCRegister PhysReg) const {
6011 return
6012 false;
6013}
6014
6015ArrayRef<const char *> HexagonGenRegisterInfo::getRegMaskNames() const {
6016 static const char *Names[] = {
6017 "HexagonCSR",
6018 };
6019 return ArrayRef(Names);
6020}
6021
6022const HexagonFrameLowering *
6023HexagonGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
6024 return static_cast<const HexagonFrameLowering *>(
6025 MF.getSubtarget().getFrameLowering());
6026}
6027
6028} // end namespace llvm
6029
6030#endif // GET_REGINFO_TARGET_DESC
6031
6032