LanaiGenInstrInfo.inc source code [llvm_projects/build/lib/Target/Lanai/LanaiGenInstrInfo.inc]

1	/===- TableGen'erated file -------------------------------------- C++ --===\
2	\| \|
3	\| Target Instruction Enum Values and Descriptors \|
4	\| \|
5	\| Automatically generated file, do not edit! \|
6	\| \|
7	\===----------------------------------------------------------------------===/
8
9	#ifdef GET_INSTRINFO_ENUM
10	#undef GET_INSTRINFO_ENUM
11	namespace llvm::Lanai {
12	enum {
13	PHI = `0`,
14	INLINEASM = `1`,
15	INLINEASM_BR = `2`,
16	CFI_INSTRUCTION = `3`,
17	EH_LABEL = `4`,
18	GC_LABEL = `5`,
19	ANNOTATION_LABEL = `6`,
20	KILL = `7`,
21	EXTRACT_SUBREG = `8`,
22	INSERT_SUBREG = `9`,
23	IMPLICIT_DEF = `10`,
24	INIT_UNDEF = `11`,
25	SUBREG_TO_REG = `12`,
26	COPY_TO_REGCLASS = `13`,
27	DBG_VALUE = `14`,
28	DBG_VALUE_LIST = `15`,
29	DBG_INSTR_REF = `16`,
30	DBG_PHI = `17`,
31	DBG_LABEL = `18`,
32	REG_SEQUENCE = `19`,
33	COPY = `20`,
34	BUNDLE = `21`,
35	LIFETIME_START = `22`,
36	LIFETIME_END = `23`,
37	PSEUDO_PROBE = `24`,
38	ARITH_FENCE = `25`,
39	STACKMAP = `26`,
40	FENTRY_CALL = `27`,
41	PATCHPOINT = `28`,
42	LOAD_STACK_GUARD = `29`,
43	PREALLOCATED_SETUP = `30`,
44	PREALLOCATED_ARG = `31`,
45	STATEPOINT = `32`,
46	LOCAL_ESCAPE = `33`,
47	FAULTING_OP = `34`,
48	PATCHABLE_OP = `35`,
49	PATCHABLE_FUNCTION_ENTER = `36`,
50	PATCHABLE_RET = `37`,
51	PATCHABLE_FUNCTION_EXIT = `38`,
52	PATCHABLE_TAIL_CALL = `39`,
53	PATCHABLE_EVENT_CALL = `40`,
54	PATCHABLE_TYPED_EVENT_CALL = `41`,
55	ICALL_BRANCH_FUNNEL = `42`,
56	FAKE_USE = `43`,
57	MEMBARRIER = `44`,
58	JUMP_TABLE_DEBUG_INFO = `45`,
59	CONVERGENCECTRL_ENTRY = `46`,
60	CONVERGENCECTRL_ANCHOR = `47`,
61	CONVERGENCECTRL_LOOP = `48`,
62	CONVERGENCECTRL_GLUE = `49`,
63	G_ASSERT_SEXT = `50`,
64	G_ASSERT_ZEXT = `51`,
65	G_ASSERT_ALIGN = `52`,
66	G_ADD = `53`,
67	G_SUB = `54`,
68	G_MUL = `55`,
69	G_SDIV = `56`,
70	G_UDIV = `57`,
71	G_SREM = `58`,
72	G_UREM = `59`,
73	G_SDIVREM = `60`,
74	G_UDIVREM = `61`,
75	G_AND = `62`,
76	G_OR = `63`,
77	G_XOR = `64`,
78	G_ABDS = `65`,
79	G_ABDU = `66`,
80	G_IMPLICIT_DEF = `67`,
81	G_PHI = `68`,
82	G_FRAME_INDEX = `69`,
83	G_GLOBAL_VALUE = `70`,
84	G_PTRAUTH_GLOBAL_VALUE = `71`,
85	G_CONSTANT_POOL = `72`,
86	G_EXTRACT = `73`,
87	G_UNMERGE_VALUES = `74`,
88	G_INSERT = `75`,
89	G_MERGE_VALUES = `76`,
90	G_BUILD_VECTOR = `77`,
91	G_BUILD_VECTOR_TRUNC = `78`,
92	G_CONCAT_VECTORS = `79`,
93	G_PTRTOINT = `80`,
94	G_INTTOPTR = `81`,
95	G_BITCAST = `82`,
96	G_FREEZE = `83`,
97	G_CONSTANT_FOLD_BARRIER = `84`,
98	G_INTRINSIC_FPTRUNC_ROUND = `85`,
99	G_INTRINSIC_TRUNC = `86`,
100	G_INTRINSIC_ROUND = `87`,
101	G_INTRINSIC_LRINT = `88`,
102	G_INTRINSIC_LLRINT = `89`,
103	G_INTRINSIC_ROUNDEVEN = `90`,
104	G_READCYCLECOUNTER = `91`,
105	G_READSTEADYCOUNTER = `92`,
106	G_LOAD = `93`,
107	G_SEXTLOAD = `94`,
108	G_ZEXTLOAD = `95`,
109	G_INDEXED_LOAD = `96`,
110	G_INDEXED_SEXTLOAD = `97`,
111	G_INDEXED_ZEXTLOAD = `98`,
112	G_STORE = `99`,
113	G_INDEXED_STORE = `100`,
114	G_ATOMIC_CMPXCHG_WITH_SUCCESS = `101`,
115	G_ATOMIC_CMPXCHG = `102`,
116	G_ATOMICRMW_XCHG = `103`,
117	G_ATOMICRMW_ADD = `104`,
118	G_ATOMICRMW_SUB = `105`,
119	G_ATOMICRMW_AND = `106`,
120	G_ATOMICRMW_NAND = `107`,
121	G_ATOMICRMW_OR = `108`,
122	G_ATOMICRMW_XOR = `109`,
123	G_ATOMICRMW_MAX = `110`,
124	G_ATOMICRMW_MIN = `111`,
125	G_ATOMICRMW_UMAX = `112`,
126	G_ATOMICRMW_UMIN = `113`,
127	G_ATOMICRMW_FADD = `114`,
128	G_ATOMICRMW_FSUB = `115`,
129	G_ATOMICRMW_FMAX = `116`,
130	G_ATOMICRMW_FMIN = `117`,
131	G_ATOMICRMW_FMAXIMUM = `118`,
132	G_ATOMICRMW_FMINIMUM = `119`,
133	G_ATOMICRMW_UINC_WRAP = `120`,
134	G_ATOMICRMW_UDEC_WRAP = `121`,
135	G_ATOMICRMW_USUB_COND = `122`,
136	G_ATOMICRMW_USUB_SAT = `123`,
137	G_FENCE = `124`,
138	G_PREFETCH = `125`,
139	G_BRCOND = `126`,
140	G_BRINDIRECT = `127`,
141	G_INVOKE_REGION_START = `128`,
142	G_INTRINSIC = `129`,
143	G_INTRINSIC_W_SIDE_EFFECTS = `130`,
144	G_INTRINSIC_CONVERGENT = `131`,
145	G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = `132`,
146	G_ANYEXT = `133`,
147	G_TRUNC = `134`,
148	G_CONSTANT = `135`,
149	G_FCONSTANT = `136`,
150	G_VASTART = `137`,
151	G_VAARG = `138`,
152	G_SEXT = `139`,
153	G_SEXT_INREG = `140`,
154	G_ZEXT = `141`,
155	G_SHL = `142`,
156	G_LSHR = `143`,
157	G_ASHR = `144`,
158	G_FSHL = `145`,
159	G_FSHR = `146`,
160	G_ROTR = `147`,
161	G_ROTL = `148`,
162	G_ICMP = `149`,
163	G_FCMP = `150`,
164	G_SCMP = `151`,
165	G_UCMP = `152`,
166	G_SELECT = `153`,
167	G_UADDO = `154`,
168	G_UADDE = `155`,
169	G_USUBO = `156`,
170	G_USUBE = `157`,
171	G_SADDO = `158`,
172	G_SADDE = `159`,
173	G_SSUBO = `160`,
174	G_SSUBE = `161`,
175	G_UMULO = `162`,
176	G_SMULO = `163`,
177	G_UMULH = `164`,
178	G_SMULH = `165`,
179	G_UADDSAT = `166`,
180	G_SADDSAT = `167`,
181	G_USUBSAT = `168`,
182	G_SSUBSAT = `169`,
183	G_USHLSAT = `170`,
184	G_SSHLSAT = `171`,
185	G_SMULFIX = `172`,
186	G_UMULFIX = `173`,
187	G_SMULFIXSAT = `174`,
188	G_UMULFIXSAT = `175`,
189	G_SDIVFIX = `176`,
190	G_UDIVFIX = `177`,
191	G_SDIVFIXSAT = `178`,
192	G_UDIVFIXSAT = `179`,
193	G_FADD = `180`,
194	G_FSUB = `181`,
195	G_FMUL = `182`,
196	G_FMA = `183`,
197	G_FMAD = `184`,
198	G_FDIV = `185`,
199	G_FREM = `186`,
200	G_FPOW = `187`,
201	G_FPOWI = `188`,
202	G_FEXP = `189`,
203	G_FEXP2 = `190`,
204	G_FEXP10 = `191`,
205	G_FLOG = `192`,
206	G_FLOG2 = `193`,
207	G_FLOG10 = `194`,
208	G_FLDEXP = `195`,
209	G_FFREXP = `196`,
210	G_FNEG = `197`,
211	G_FPEXT = `198`,
212	G_FPTRUNC = `199`,
213	G_FPTOSI = `200`,
214	G_FPTOUI = `201`,
215	G_SITOFP = `202`,
216	G_UITOFP = `203`,
217	G_FPTOSI_SAT = `204`,
218	G_FPTOUI_SAT = `205`,
219	G_FABS = `206`,
220	G_FCOPYSIGN = `207`,
221	G_IS_FPCLASS = `208`,
222	G_FCANONICALIZE = `209`,
223	G_FMINNUM = `210`,
224	G_FMAXNUM = `211`,
225	G_FMINNUM_IEEE = `212`,
226	G_FMAXNUM_IEEE = `213`,
227	G_FMINIMUM = `214`,
228	G_FMAXIMUM = `215`,
229	G_FMINIMUMNUM = `216`,
230	G_FMAXIMUMNUM = `217`,
231	G_GET_FPENV = `218`,
232	G_SET_FPENV = `219`,
233	G_RESET_FPENV = `220`,
234	G_GET_FPMODE = `221`,
235	G_SET_FPMODE = `222`,
236	G_RESET_FPMODE = `223`,
237	G_PTR_ADD = `224`,
238	G_PTRMASK = `225`,
239	G_SMIN = `226`,
240	G_SMAX = `227`,
241	G_UMIN = `228`,
242	G_UMAX = `229`,
243	G_ABS = `230`,
244	G_LROUND = `231`,
245	G_LLROUND = `232`,
246	G_BR = `233`,
247	G_BRJT = `234`,
248	G_VSCALE = `235`,
249	G_INSERT_SUBVECTOR = `236`,
250	G_EXTRACT_SUBVECTOR = `237`,
251	G_INSERT_VECTOR_ELT = `238`,
252	G_EXTRACT_VECTOR_ELT = `239`,
253	G_SHUFFLE_VECTOR = `240`,
254	G_SPLAT_VECTOR = `241`,
255	G_STEP_VECTOR = `242`,
256	G_VECTOR_COMPRESS = `243`,
257	G_CTTZ = `244`,
258	G_CTTZ_ZERO_UNDEF = `245`,
259	G_CTLZ = `246`,
260	G_CTLZ_ZERO_UNDEF = `247`,
261	G_CTPOP = `248`,
262	G_BSWAP = `249`,
263	G_BITREVERSE = `250`,
264	G_FCEIL = `251`,
265	G_FCOS = `252`,
266	G_FSIN = `253`,
267	G_FSINCOS = `254`,
268	G_FTAN = `255`,
269	G_FACOS = `256`,
270	G_FASIN = `257`,
271	G_FATAN = `258`,
272	G_FATAN2 = `259`,
273	G_FCOSH = `260`,
274	G_FSINH = `261`,
275	G_FTANH = `262`,
276	G_FSQRT = `263`,
277	G_FFLOOR = `264`,
278	G_FRINT = `265`,
279	G_FNEARBYINT = `266`,
280	G_ADDRSPACE_CAST = `267`,
281	G_BLOCK_ADDR = `268`,
282	G_JUMP_TABLE = `269`,
283	G_DYN_STACKALLOC = `270`,
284	G_STACKSAVE = `271`,
285	G_STACKRESTORE = `272`,
286	G_STRICT_FADD = `273`,
287	G_STRICT_FSUB = `274`,
288	G_STRICT_FMUL = `275`,
289	G_STRICT_FDIV = `276`,
290	G_STRICT_FREM = `277`,
291	G_STRICT_FMA = `278`,
292	G_STRICT_FSQRT = `279`,
293	G_STRICT_FLDEXP = `280`,
294	G_READ_REGISTER = `281`,
295	G_WRITE_REGISTER = `282`,
296	G_MEMCPY = `283`,
297	G_MEMCPY_INLINE = `284`,
298	G_MEMMOVE = `285`,
299	G_MEMSET = `286`,
300	G_BZERO = `287`,
301	G_TRAP = `288`,
302	G_DEBUGTRAP = `289`,
303	G_UBSANTRAP = `290`,
304	G_VECREDUCE_SEQ_FADD = `291`,
305	G_VECREDUCE_SEQ_FMUL = `292`,
306	G_VECREDUCE_FADD = `293`,
307	G_VECREDUCE_FMUL = `294`,
308	G_VECREDUCE_FMAX = `295`,
309	G_VECREDUCE_FMIN = `296`,
310	G_VECREDUCE_FMAXIMUM = `297`,
311	G_VECREDUCE_FMINIMUM = `298`,
312	G_VECREDUCE_ADD = `299`,
313	G_VECREDUCE_MUL = `300`,
314	G_VECREDUCE_AND = `301`,
315	G_VECREDUCE_OR = `302`,
316	G_VECREDUCE_XOR = `303`,
317	G_VECREDUCE_SMAX = `304`,
318	G_VECREDUCE_SMIN = `305`,
319	G_VECREDUCE_UMAX = `306`,
320	G_VECREDUCE_UMIN = `307`,
321	G_SBFX = `308`,
322	G_UBFX = `309`,
323	ADJCALLSTACKDOWN = `310`,
324	ADJCALLSTACKUP = `311`,
325	ADJDYNALLOC = `312`,
326	CALL = `313`,
327	CALLR = `314`,
328	ADDC_F_I_HI = `315`,
329	ADDC_F_I_LO = `316`,
330	ADDC_F_R = `317`,
331	ADDC_I_HI = `318`,
332	ADDC_I_LO = `319`,
333	ADDC_R = `320`,
334	ADD_F_I_HI = `321`,
335	ADD_F_I_LO = `322`,
336	ADD_F_R = `323`,
337	ADD_I_HI = `324`,
338	ADD_I_LO = `325`,
339	ADD_R = `326`,
340	AND_F_I_HI = `327`,
341	AND_F_I_LO = `328`,
342	AND_F_R = `329`,
343	AND_I_HI = `330`,
344	AND_I_LO = `331`,
345	AND_R = `332`,
346	BRCC = `333`,
347	BRIND_CC = `334`,
348	BRIND_CCA = `335`,
349	BRR = `336`,
350	BT = `337`,
351	JR = `338`,
352	LDADDR = `339`,
353	LDBs_RI = `340`,
354	LDBs_RR = `341`,
355	LDBz_RI = `342`,
356	LDBz_RR = `343`,
357	LDHs_RI = `344`,
358	LDHs_RR = `345`,
359	LDHz_RI = `346`,
360	LDHz_RR = `347`,
361	LDW_RI = `348`,
362	LDW_RR = `349`,
363	LDWz_RR = `350`,
364	LEADZ = `351`,
365	LOG0 = `352`,
366	LOG1 = `353`,
367	LOG2 = `354`,
368	LOG3 = `355`,
369	LOG4 = `356`,
370	MOVHI = `357`,
371	NOP = `358`,
372	OR_F_I_HI = `359`,
373	OR_F_I_LO = `360`,
374	OR_F_R = `361`,
375	OR_I_HI = `362`,
376	OR_I_LO = `363`,
377	OR_R = `364`,
378	POPC = `365`,
379	RET = `366`,
380	SA_F_I = `367`,
381	SA_I = `368`,
382	SCC = `369`,
383	SELECT = `370`,
384	SFSUB_F_RI_HI = `371`,
385	SFSUB_F_RI_LO = `372`,
386	SFSUB_F_RR = `373`,
387	SHL_F_R = `374`,
388	SHL_R = `375`,
389	SLI = `376`,
390	SL_F_I = `377`,
391	SL_I = `378`,
392	SRA_F_R = `379`,
393	SRA_R = `380`,
394	SRL_F_R = `381`,
395	SRL_R = `382`,
396	STADDR = `383`,
397	STB_RI = `384`,
398	STB_RR = `385`,
399	STH_RI = `386`,
400	STH_RR = `387`,
401	SUBB_F_I_HI = `388`,
402	SUBB_F_I_LO = `389`,
403	SUBB_F_R = `390`,
404	SUBB_I_HI = `391`,
405	SUBB_I_LO = `392`,
406	SUBB_R = `393`,
407	SUB_F_I_HI = `394`,
408	SUB_F_I_LO = `395`,
409	SUB_F_R = `396`,
410	SUB_I_HI = `397`,
411	SUB_I_LO = `398`,
412	SUB_R = `399`,
413	SW_RI = `400`,
414	SW_RR = `401`,
415	TRAILZ = `402`,
416	XOR_F_I_HI = `403`,
417	XOR_F_I_LO = `404`,
418	XOR_F_R = `405`,
419	XOR_I_HI = `406`,
420	XOR_I_LO = `407`,
421	XOR_R = `408`,
422	INSTRUCTION_LIST_END = `409`
423	};
424
425	} // end namespace llvm::Lanai
426	#endif // GET_INSTRINFO_ENUM
427
428	#ifdef GET_INSTRINFO_SCHED_ENUM
429	#undef GET_INSTRINFO_SCHED_ENUM
430	namespace llvm::Lanai::Sched {
431
432	enum {
433	NoInstrModel = `0`,
434	IIC_ALU_WriteALU = `1`,
435	IIC_ALU = `2`,
436	IIC_LD_WriteLD = `3`,
437	IIC_LDSW_WriteLDSW = `4`,
438	WriteLD = `5`,
439	IIC_ST_WriteST = `6`,
440	IIC_STSW_WriteSTSW = `7`,
441	SCHED_LIST_END = `8`
442	};
443	} // end namespace llvm::Lanai::Sched
444	#endif // GET_INSTRINFO_SCHED_ENUM
445
446	#if defined(GET_INSTRINFO_MC_DESC) \|\| defined(GET_INSTRINFO_CTOR_DTOR)
447	namespace llvm {
448
449	struct LanaiInstrTable {
450	MCInstrDesc Insts[`409`];
451	static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo");
452	MCOperandInfo OperandInfo[`178`];
453	static_assert(alignof(MCOperandInfo) >= alignof(MCPhysReg), "Unwanted padding between OperandInfo and ImplicitOps");
454	MCPhysReg ImplicitOps[`8`];
455	};
456
457	} // end namespace llvm
458	#endif // defined(GET_INSTRINFO_MC_DESC) \|\| defined(GET_INSTRINFO_CTOR_DTOR)
459
460	#ifdef GET_INSTRINFO_MC_DESC
461	#undef GET_INSTRINFO_MC_DESC
462	namespace llvm {
463
464	static_assert(sizeof(MCOperandInfo) % sizeof(MCPhysReg) == `0`);
465	static constexpr unsigned LanaiImpOpBase = sizeof LanaiInstrTable::OperandInfo / (sizeof(MCPhysReg));
466
467	extern const LanaiInstrTable LanaiDescs = {
468	{
469	{ `408`, `4`, `1`, `4`, `1`, `0`, `0`, `158`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Predicable)\|(`1ULL`<<MCID::Commutable)\|(`1ULL`<<MCID::CheapAsAMove)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #408 = XOR_R
470	{ `407`, `3`, `1`, `4`, `1`, `0`, `0`, `155`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Commutable)\|(`1ULL`<<MCID::CheapAsAMove)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #407 = XOR_I_LO
471	{ `406`, `3`, `1`, `4`, `1`, `0`, `0`, `155`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Commutable)\|(`1ULL`<<MCID::CheapAsAMove)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #406 = XOR_I_HI
472	{ `405`, `4`, `1`, `4`, `1`, `0`, `1`, `158`, LanaiImpOpBase + `6`, `0`\|(`1ULL`<<MCID::Predicable)\|(`1ULL`<<MCID::Commutable)\|(`1ULL`<<MCID::CheapAsAMove)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #405 = XOR_F_R
473	{ `404`, `3`, `1`, `4`, `1`, `0`, `1`, `155`, LanaiImpOpBase + `6`, `0`\|(`1ULL`<<MCID::Commutable)\|(`1ULL`<<MCID::CheapAsAMove)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #404 = XOR_F_I_LO
474	{ `403`, `3`, `1`, `4`, `1`, `0`, `1`, `155`, LanaiImpOpBase + `6`, `0`\|(`1ULL`<<MCID::Commutable)\|(`1ULL`<<MCID::CheapAsAMove)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #403 = XOR_F_I_HI
475	{ `402`, `2`, `1`, `4`, `1`, `0`, `0`, `152`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #402 = TRAILZ
476	{ `401`, `4`, `0`, `4`, `6`, `0`, `0`, `170`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #401 = SW_RR
477	{ `400`, `4`, `0`, `4`, `6`, `0`, `0`, `166`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #400 = SW_RI
478	{ `399`, `4`, `1`, `4`, `1`, `0`, `0`, `158`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Predicable)\|(`1ULL`<<MCID::CheapAsAMove)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #399 = SUB_R
479	{ `398`, `3`, `1`, `4`, `1`, `0`, `0`, `155`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::CheapAsAMove)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #398 = SUB_I_LO
480	{ `397`, `3`, `1`, `4`, `1`, `0`, `0`, `155`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::CheapAsAMove)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #397 = SUB_I_HI
481	{ `396`, `4`, `1`, `4`, `1`, `0`, `1`, `158`, LanaiImpOpBase + `6`, `0`\|(`1ULL`<<MCID::Predicable)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #396 = SUB_F_R
482	{ `395`, `3`, `1`, `4`, `1`, `0`, `1`, `155`, LanaiImpOpBase + `6`, `0`\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #395 = SUB_F_I_LO
483	{ `394`, `3`, `1`, `4`, `1`, `0`, `1`, `155`, LanaiImpOpBase + `6`, `0`\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #394 = SUB_F_I_HI
484	{ `393`, `4`, `1`, `4`, `1`, `1`, `0`, `158`, LanaiImpOpBase + `6`, `0`\|(`1ULL`<<MCID::Predicable)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #393 = SUBB_R
485	{ `392`, `3`, `1`, `4`, `1`, `1`, `0`, `155`, LanaiImpOpBase + `6`, `0`\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #392 = SUBB_I_LO
486	{ `391`, `3`, `1`, `4`, `1`, `1`, `0`, `155`, LanaiImpOpBase + `6`, `0`\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #391 = SUBB_I_HI
487	{ `390`, `4`, `1`, `4`, `1`, `1`, `1`, `158`, LanaiImpOpBase + `4`, `0`\|(`1ULL`<<MCID::Predicable)\|(`1ULL`<<MCID::CheapAsAMove)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #390 = SUBB_F_R
488	{ `389`, `3`, `1`, `4`, `1`, `1`, `1`, `155`, LanaiImpOpBase + `4`, `0`\|(`1ULL`<<MCID::CheapAsAMove)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #389 = SUBB_F_I_LO
489	{ `388`, `3`, `1`, `4`, `1`, `1`, `1`, `155`, LanaiImpOpBase + `4`, `0`\|(`1ULL`<<MCID::CheapAsAMove)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #388 = SUBB_F_I_HI
490	{ `387`, `4`, `0`, `4`, `6`, `0`, `0`, `170`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #387 = STH_RR
491	{ `386`, `4`, `0`, `4`, `7`, `0`, `0`, `166`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #386 = STH_RI
492	{ `385`, `4`, `0`, `4`, `6`, `0`, `0`, `170`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #385 = STB_RR
493	{ `384`, `4`, `0`, `4`, `7`, `0`, `0`, `166`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #384 = STB_RI
494	{ `383`, `2`, `0`, `4`, `6`, `0`, `0`, `162`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #383 = STADDR
495	{ `382`, `4`, `1`, `4`, `1`, `0`, `0`, `158`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Predicable)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #382 = SRL_R
496	{ `381`, `4`, `1`, `4`, `1`, `0`, `1`, `158`, LanaiImpOpBase + `6`, `0`\|(`1ULL`<<MCID::Predicable)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #381 = SRL_F_R
497	{ `380`, `4`, `1`, `4`, `1`, `0`, `0`, `158`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Predicable)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #380 = SRA_R
498	{ `379`, `4`, `1`, `4`, `1`, `0`, `1`, `158`, LanaiImpOpBase + `6`, `0`\|(`1ULL`<<MCID::Predicable)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #379 = SRA_F_R
499	{ `378`, `3`, `1`, `4`, `1`, `0`, `0`, `155`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Rematerializable)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #378 = SL_I
500	{ `377`, `3`, `1`, `4`, `1`, `0`, `1`, `155`, LanaiImpOpBase + `6`, `0`\|(`1ULL`<<MCID::Rematerializable)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #377 = SL_F_I
501	{ `376`, `2`, `1`, `4`, `0`, `0`, `0`, `162`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Rematerializable)\|(`1ULL`<<MCID::CheapAsAMove)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #376 = SLI
502	{ `375`, `4`, `1`, `4`, `1`, `0`, `0`, `158`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Predicable)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #375 = SHL_R
503	{ `374`, `4`, `1`, `4`, `1`, `0`, `1`, `158`, LanaiImpOpBase + `6`, `0`\|(`1ULL`<<MCID::Predicable)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #374 = SHL_F_R
504	{ `373`, `2`, `0`, `4`, `1`, `0`, `1`, `152`, LanaiImpOpBase + `6`, `0`\|(`1ULL`<<MCID::Compare)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #373 = SFSUB_F_RR
505	{ `372`, `2`, `0`, `4`, `1`, `0`, `1`, `162`, LanaiImpOpBase + `6`, `0`\|(`1ULL`<<MCID::Compare)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #372 = SFSUB_F_RI_LO
506	{ `371`, `2`, `0`, `4`, `1`, `0`, `1`, `162`, LanaiImpOpBase + `6`, `0`\|(`1ULL`<<MCID::Compare)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #371 = SFSUB_F_RI_HI
507	{ `370`, `4`, `1`, `4`, `1`, `1`, `0`, `174`, LanaiImpOpBase + `6`, `0`\|(`1ULL`<<MCID::Select)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #370 = SELECT
508	{ `369`, `2`, `1`, `4`, `2`, `1`, `0`, `162`, LanaiImpOpBase + `6`, `0`\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #369 = SCC
509	{ `368`, `3`, `1`, `4`, `1`, `0`, `0`, `155`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Rematerializable)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #368 = SA_I
510	{ `367`, `3`, `1`, `4`, `1`, `0`, `1`, `155`, LanaiImpOpBase + `6`, `0`\|(`1ULL`<<MCID::Rematerializable)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #367 = SA_F_I
511	{ `366`, `0`, `0`, `4`, `0`, `1`, `0`, `1`, LanaiImpOpBase + `7`, `0`\|(`1ULL`<<MCID::Return)\|(`1ULL`<<MCID::Barrier)\|(`1ULL`<<MCID::DelaySlot)\|(`1ULL`<<MCID::Terminator)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #366 = RET
512	{ `365`, `2`, `1`, `4`, `1`, `0`, `0`, `152`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #365 = POPC
513	{ `364`, `4`, `1`, `4`, `1`, `0`, `0`, `158`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Predicable)\|(`1ULL`<<MCID::Commutable)\|(`1ULL`<<MCID::CheapAsAMove)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #364 = OR_R
514	{ `363`, `3`, `1`, `4`, `1`, `0`, `0`, `155`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Commutable)\|(`1ULL`<<MCID::CheapAsAMove)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #363 = OR_I_LO
515	{ `362`, `3`, `1`, `4`, `1`, `0`, `0`, `155`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Commutable)\|(`1ULL`<<MCID::CheapAsAMove)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #362 = OR_I_HI
516	{ `361`, `4`, `1`, `4`, `1`, `0`, `1`, `158`, LanaiImpOpBase + `6`, `0`\|(`1ULL`<<MCID::Predicable)\|(`1ULL`<<MCID::Commutable)\|(`1ULL`<<MCID::CheapAsAMove)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #361 = OR_F_R
517	{ `360`, `3`, `1`, `4`, `1`, `0`, `1`, `155`, LanaiImpOpBase + `6`, `0`\|(`1ULL`<<MCID::Commutable)\|(`1ULL`<<MCID::CheapAsAMove)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #360 = OR_F_I_LO
518	{ `359`, `3`, `1`, `4`, `1`, `0`, `1`, `155`, LanaiImpOpBase + `6`, `0`\|(`1ULL`<<MCID::Commutable)\|(`1ULL`<<MCID::CheapAsAMove)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #359 = OR_F_I_HI
519	{ `358`, `0`, `0`, `4`, `0`, `0`, `0`, `1`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #358 = NOP
520	{ `357`, `2`, `1`, `4`, `1`, `0`, `0`, `162`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Rematerializable)\|(`1ULL`<<MCID::CheapAsAMove)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #357 = MOVHI
521	{ `356`, `0`, `0`, `4`, `0`, `0`, `0`, `1`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #356 = LOG4
522	{ `355`, `0`, `0`, `4`, `0`, `0`, `0`, `1`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #355 = LOG3
523	{ `354`, `0`, `0`, `4`, `0`, `0`, `0`, `1`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #354 = LOG2
524	{ `353`, `0`, `0`, `4`, `0`, `0`, `0`, `1`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #353 = LOG1
525	{ `352`, `0`, `0`, `4`, `0`, `0`, `0`, `1`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #352 = LOG0
526	{ `351`, `2`, `1`, `4`, `1`, `0`, `0`, `152`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #351 = LEADZ
527	{ `350`, `4`, `1`, `4`, `5`, `0`, `0`, `170`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #350 = LDWz_RR
528	{ `349`, `4`, `1`, `4`, `5`, `0`, `0`, `170`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #349 = LDW_RR
529	{ `348`, `4`, `1`, `4`, `3`, `0`, `0`, `166`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::Rematerializable)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #348 = LDW_RI
530	{ `347`, `4`, `1`, `4`, `5`, `0`, `0`, `170`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #347 = LDHz_RR
531	{ `346`, `4`, `1`, `4`, `4`, `0`, `0`, `166`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::Rematerializable)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #346 = LDHz_RI
532	{ `345`, `4`, `1`, `4`, `5`, `0`, `0`, `170`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #345 = LDHs_RR
533	{ `344`, `4`, `1`, `4`, `4`, `0`, `0`, `166`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::Rematerializable)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #344 = LDHs_RI
534	{ `343`, `4`, `1`, `4`, `5`, `0`, `0`, `170`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #343 = LDBz_RR
535	{ `342`, `4`, `1`, `4`, `4`, `0`, `0`, `166`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::Rematerializable)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #342 = LDBz_RI
536	{ `341`, `4`, `1`, `4`, `5`, `0`, `0`, `170`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #341 = LDBs_RR
537	{ `340`, `4`, `1`, `4`, `4`, `0`, `0`, `166`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::Rematerializable)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #340 = LDBs_RI
538	{ `339`, `2`, `1`, `4`, `3`, `0`, `0`, `162`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::Rematerializable)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #339 = LDADDR
539	{ `338`, `1`, `0`, `4`, `1`, `0`, `0`, `154`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Branch)\|(`1ULL`<<MCID::IndirectBranch)\|(`1ULL`<<MCID::Barrier)\|(`1ULL`<<MCID::DelaySlot)\|(`1ULL`<<MCID::Terminator)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #338 = JR
540	{ `337`, `1`, `0`, `4`, `2`, `0`, `0`, `0`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Branch)\|(`1ULL`<<MCID::Barrier)\|(`1ULL`<<MCID::DelaySlot)\|(`1ULL`<<MCID::Terminator)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #337 = BT
541	{ `336`, `2`, `0`, `4`, `0`, `1`, `0`, `164`, LanaiImpOpBase + `6`, `0`\|(`1ULL`<<MCID::Branch)\|(`1ULL`<<MCID::Barrier)\|(`1ULL`<<MCID::DelaySlot)\|(`1ULL`<<MCID::Terminator)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #336 = BRR
542	{ `335`, `3`, `0`, `4`, `1`, `1`, `0`, `155`, LanaiImpOpBase + `6`, `0`\|(`1ULL`<<MCID::Branch)\|(`1ULL`<<MCID::IndirectBranch)\|(`1ULL`<<MCID::Barrier)\|(`1ULL`<<MCID::DelaySlot)\|(`1ULL`<<MCID::Terminator)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #335 = BRIND_CCA
543	{ `334`, `2`, `0`, `4`, `1`, `1`, `0`, `162`, LanaiImpOpBase + `6`, `0`\|(`1ULL`<<MCID::Branch)\|(`1ULL`<<MCID::IndirectBranch)\|(`1ULL`<<MCID::Barrier)\|(`1ULL`<<MCID::DelaySlot)\|(`1ULL`<<MCID::Terminator)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #334 = BRIND_CC
544	{ `333`, `2`, `0`, `4`, `2`, `1`, `0`, `13`, LanaiImpOpBase + `6`, `0`\|(`1ULL`<<MCID::Branch)\|(`1ULL`<<MCID::Barrier)\|(`1ULL`<<MCID::DelaySlot)\|(`1ULL`<<MCID::Terminator)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #333 = BRCC
545	{ `332`, `4`, `1`, `4`, `1`, `0`, `0`, `158`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Predicable)\|(`1ULL`<<MCID::Commutable)\|(`1ULL`<<MCID::CheapAsAMove)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #332 = AND_R
546	{ `331`, `3`, `1`, `4`, `1`, `0`, `0`, `155`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Commutable)\|(`1ULL`<<MCID::CheapAsAMove)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #331 = AND_I_LO
547	{ `330`, `3`, `1`, `4`, `1`, `0`, `0`, `155`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Commutable)\|(`1ULL`<<MCID::CheapAsAMove)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #330 = AND_I_HI
548	{ `329`, `4`, `1`, `4`, `1`, `0`, `1`, `158`, LanaiImpOpBase + `6`, `0`\|(`1ULL`<<MCID::Predicable)\|(`1ULL`<<MCID::Commutable)\|(`1ULL`<<MCID::CheapAsAMove)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #329 = AND_F_R
549	{ `328`, `3`, `1`, `4`, `1`, `0`, `1`, `155`, LanaiImpOpBase + `6`, `0`\|(`1ULL`<<MCID::Commutable)\|(`1ULL`<<MCID::CheapAsAMove)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #328 = AND_F_I_LO
550	{ `327`, `3`, `1`, `4`, `1`, `0`, `1`, `155`, LanaiImpOpBase + `6`, `0`\|(`1ULL`<<MCID::Commutable)\|(`1ULL`<<MCID::CheapAsAMove)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #327 = AND_F_I_HI
551	{ `326`, `4`, `1`, `4`, `1`, `0`, `0`, `158`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Predicable)\|(`1ULL`<<MCID::Commutable)\|(`1ULL`<<MCID::CheapAsAMove)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #326 = ADD_R
552	{ `325`, `3`, `1`, `4`, `1`, `0`, `0`, `155`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Commutable)\|(`1ULL`<<MCID::CheapAsAMove)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #325 = ADD_I_LO
553	{ `324`, `3`, `1`, `4`, `1`, `0`, `0`, `155`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Commutable)\|(`1ULL`<<MCID::CheapAsAMove)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #324 = ADD_I_HI
554	{ `323`, `4`, `1`, `4`, `1`, `0`, `1`, `158`, LanaiImpOpBase + `6`, `0`\|(`1ULL`<<MCID::Predicable)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #323 = ADD_F_R
555	{ `322`, `3`, `1`, `4`, `1`, `0`, `1`, `155`, LanaiImpOpBase + `6`, `0`\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #322 = ADD_F_I_LO
556	{ `321`, `3`, `1`, `4`, `1`, `0`, `1`, `155`, LanaiImpOpBase + `6`, `0`\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #321 = ADD_F_I_HI
557	{ `320`, `4`, `1`, `4`, `1`, `1`, `0`, `158`, LanaiImpOpBase + `6`, `0`\|(`1ULL`<<MCID::Predicable)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #320 = ADDC_R
558	{ `319`, `3`, `1`, `4`, `1`, `1`, `0`, `155`, LanaiImpOpBase + `6`, `0`\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #319 = ADDC_I_LO
559	{ `318`, `3`, `1`, `4`, `1`, `1`, `0`, `155`, LanaiImpOpBase + `6`, `0`\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #318 = ADDC_I_HI
560	{ `317`, `4`, `1`, `4`, `1`, `1`, `1`, `158`, LanaiImpOpBase + `4`, `0`\|(`1ULL`<<MCID::Predicable)\|(`1ULL`<<MCID::CheapAsAMove)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #317 = ADDC_F_R
561	{ `316`, `3`, `1`, `4`, `1`, `1`, `1`, `155`, LanaiImpOpBase + `4`, `0`\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::CheapAsAMove)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #316 = ADDC_F_I_LO
562	{ `315`, `3`, `1`, `4`, `1`, `1`, `1`, `155`, LanaiImpOpBase + `4`, `0`\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::CheapAsAMove)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #315 = ADDC_F_I_HI
563	{ `314`, `1`, `0`, `4`, `0`, `1`, `1`, `154`, LanaiImpOpBase + `2`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::DelaySlot)\|(`1ULL`<<MCID::Call)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #314 = CALLR
564	{ `313`, `1`, `0`, `4`, `0`, `1`, `1`, `0`, LanaiImpOpBase + `2`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::DelaySlot)\|(`1ULL`<<MCID::Call)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #313 = CALL
565	{ `312`, `2`, `1`, `4`, `0`, `1`, `1`, `152`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #312 = ADJDYNALLOC
566	{ `311`, `2`, `0`, `4`, `0`, `1`, `1`, `21`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #311 = ADJCALLSTACKUP
567	{ `310`, `2`, `0`, `4`, `0`, `1`, `1`, `21`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #310 = ADJCALLSTACKDOWN
568	{ `309`, `4`, `1`, `0`, `0`, `0`, `0`, `148`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #309 = G_UBFX
569	{ `308`, `4`, `1`, `0`, `0`, `0`, `0`, `148`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #308 = G_SBFX
570	{ `307`, `2`, `1`, `0`, `0`, `0`, `0`, `61`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #307 = G_VECREDUCE_UMIN
571	{ `306`, `2`, `1`, `0`, `0`, `0`, `0`, `61`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #306 = G_VECREDUCE_UMAX
572	{ `305`, `2`, `1`, `0`, `0`, `0`, `0`, `61`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #305 = G_VECREDUCE_SMIN
573	{ `304`, `2`, `1`, `0`, `0`, `0`, `0`, `61`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #304 = G_VECREDUCE_SMAX
574	{ `303`, `2`, `1`, `0`, `0`, `0`, `0`, `61`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #303 = G_VECREDUCE_XOR
575	{ `302`, `2`, `1`, `0`, `0`, `0`, `0`, `61`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #302 = G_VECREDUCE_OR
576	{ `301`, `2`, `1`, `0`, `0`, `0`, `0`, `61`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #301 = G_VECREDUCE_AND
577	{ `300`, `2`, `1`, `0`, `0`, `0`, `0`, `61`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #300 = G_VECREDUCE_MUL
578	{ `299`, `2`, `1`, `0`, `0`, `0`, `0`, `61`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #299 = G_VECREDUCE_ADD
579	{ `298`, `2`, `1`, `0`, `0`, `0`, `0`, `61`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #298 = G_VECREDUCE_FMINIMUM
580	{ `297`, `2`, `1`, `0`, `0`, `0`, `0`, `61`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #297 = G_VECREDUCE_FMAXIMUM
581	{ `296`, `2`, `1`, `0`, `0`, `0`, `0`, `61`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #296 = G_VECREDUCE_FMIN
582	{ `295`, `2`, `1`, `0`, `0`, `0`, `0`, `61`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #295 = G_VECREDUCE_FMAX
583	{ `294`, `2`, `1`, `0`, `0`, `0`, `0`, `61`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #294 = G_VECREDUCE_FMUL
584	{ `293`, `2`, `1`, `0`, `0`, `0`, `0`, `61`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #293 = G_VECREDUCE_FADD
585	{ `292`, `3`, `1`, `0`, `0`, `0`, `0`, `131`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #292 = G_VECREDUCE_SEQ_FMUL
586	{ `291`, `3`, `1`, `0`, `0`, `0`, `0`, `131`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #291 = G_VECREDUCE_SEQ_FADD
587	{ `290`, `1`, `0`, `0`, `0`, `0`, `0`, `1`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #290 = G_UBSANTRAP
588	{ `289`, `0`, `0`, `0`, `0`, `0`, `0`, `1`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #289 = G_DEBUGTRAP
589	{ `288`, `0`, `0`, `0`, `0`, `0`, `0`, `1`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #288 = G_TRAP
590	{ `287`, `3`, `0`, `0`, `0`, `0`, `0`, `58`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #287 = G_BZERO
591	{ `286`, `4`, `0`, `0`, `0`, `0`, `0`, `144`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #286 = G_MEMSET
592	{ `285`, `4`, `0`, `0`, `0`, `0`, `0`, `144`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #285 = G_MEMMOVE
593	{ `284`, `3`, `0`, `0`, `0`, `0`, `0`, `131`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #284 = G_MEMCPY_INLINE
594	{ `283`, `4`, `0`, `0`, `0`, `0`, `0`, `144`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #283 = G_MEMCPY
595	{ `282`, `2`, `0`, `0`, `0`, `0`, `0`, `142`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq)\|(`1ULL`<<MCID::Convergent), `0x0ULL` }, // Inst #282 = G_WRITE_REGISTER
596	{ `281`, `2`, `1`, `0`, `0`, `0`, `0`, `51`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq)\|(`1ULL`<<MCID::Convergent), `0x0ULL` }, // Inst #281 = G_READ_REGISTER
597	{ `280`, `3`, `1`, `0`, `0`, `0`, `0`, `101`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::MayRaiseFPException)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #280 = G_STRICT_FLDEXP
598	{ `279`, `2`, `1`, `0`, `0`, `0`, `0`, `67`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::MayRaiseFPException)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #279 = G_STRICT_FSQRT
599	{ `278`, `4`, `1`, `0`, `0`, `0`, `0`, `46`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::MayRaiseFPException)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #278 = G_STRICT_FMA
600	{ `277`, `3`, `1`, `0`, `0`, `0`, `0`, `43`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::MayRaiseFPException)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #277 = G_STRICT_FREM
601	{ `276`, `3`, `1`, `0`, `0`, `0`, `0`, `43`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::MayRaiseFPException)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #276 = G_STRICT_FDIV
602	{ `275`, `3`, `1`, `0`, `0`, `0`, `0`, `43`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::MayRaiseFPException)\|(`1ULL`<<MCID::Commutable)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #275 = G_STRICT_FMUL
603	{ `274`, `3`, `1`, `0`, `0`, `0`, `0`, `43`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::MayRaiseFPException)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #274 = G_STRICT_FSUB
604	{ `273`, `3`, `1`, `0`, `0`, `0`, `0`, `43`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::MayRaiseFPException)\|(`1ULL`<<MCID::Commutable)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #273 = G_STRICT_FADD
605	{ `272`, `1`, `0`, `0`, `0`, `0`, `0`, `50`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #272 = G_STACKRESTORE
606	{ `271`, `1`, `1`, `0`, `0`, `0`, `0`, `50`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #271 = G_STACKSAVE
607	{ `270`, `3`, `1`, `0`, `0`, `0`, `0`, `69`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #270 = G_DYN_STACKALLOC
608	{ `269`, `2`, `1`, `0`, `0`, `0`, `0`, `51`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #269 = G_JUMP_TABLE
609	{ `268`, `2`, `1`, `0`, `0`, `0`, `0`, `51`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #268 = G_BLOCK_ADDR
610	{ `267`, `2`, `1`, `0`, `0`, `0`, `0`, `61`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #267 = G_ADDRSPACE_CAST
611	{ `266`, `2`, `1`, `0`, `0`, `0`, `0`, `67`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #266 = G_FNEARBYINT
612	{ `265`, `2`, `1`, `0`, `0`, `0`, `0`, `67`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #265 = G_FRINT
613	{ `264`, `2`, `1`, `0`, `0`, `0`, `0`, `67`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #264 = G_FFLOOR
614	{ `263`, `2`, `1`, `0`, `0`, `0`, `0`, `67`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #263 = G_FSQRT
615	{ `262`, `2`, `1`, `0`, `0`, `0`, `0`, `67`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #262 = G_FTANH
616	{ `261`, `2`, `1`, `0`, `0`, `0`, `0`, `67`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #261 = G_FSINH
617	{ `260`, `2`, `1`, `0`, `0`, `0`, `0`, `67`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #260 = G_FCOSH
618	{ `259`, `3`, `1`, `0`, `0`, `0`, `0`, `43`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #259 = G_FATAN2
619	{ `258`, `2`, `1`, `0`, `0`, `0`, `0`, `67`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #258 = G_FATAN
620	{ `257`, `2`, `1`, `0`, `0`, `0`, `0`, `67`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #257 = G_FASIN
621	{ `256`, `2`, `1`, `0`, `0`, `0`, `0`, `67`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #256 = G_FACOS
622	{ `255`, `2`, `1`, `0`, `0`, `0`, `0`, `67`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #255 = G_FTAN
623	{ `254`, `3`, `2`, `0`, `0`, `0`, `0`, `43`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #254 = G_FSINCOS
624	{ `253`, `2`, `1`, `0`, `0`, `0`, `0`, `67`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #253 = G_FSIN
625	{ `252`, `2`, `1`, `0`, `0`, `0`, `0`, `67`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #252 = G_FCOS
626	{ `251`, `2`, `1`, `0`, `0`, `0`, `0`, `67`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #251 = G_FCEIL
627	{ `250`, `2`, `1`, `0`, `0`, `0`, `0`, `67`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #250 = G_BITREVERSE
628	{ `249`, `2`, `1`, `0`, `0`, `0`, `0`, `67`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #249 = G_BSWAP
629	{ `248`, `2`, `1`, `0`, `0`, `0`, `0`, `61`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #248 = G_CTPOP
630	{ `247`, `2`, `1`, `0`, `0`, `0`, `0`, `61`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #247 = G_CTLZ_ZERO_UNDEF
631	{ `246`, `2`, `1`, `0`, `0`, `0`, `0`, `61`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #246 = G_CTLZ
632	{ `245`, `2`, `1`, `0`, `0`, `0`, `0`, `61`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #245 = G_CTTZ_ZERO_UNDEF
633	{ `244`, `2`, `1`, `0`, `0`, `0`, `0`, `61`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #244 = G_CTTZ
634	{ `243`, `4`, `1`, `0`, `0`, `0`, `0`, `138`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #243 = G_VECTOR_COMPRESS
635	{ `242`, `2`, `1`, `0`, `0`, `0`, `0`, `51`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #242 = G_STEP_VECTOR
636	{ `241`, `2`, `1`, `0`, `0`, `0`, `0`, `61`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #241 = G_SPLAT_VECTOR
637	{ `240`, `4`, `1`, `0`, `0`, `0`, `0`, `134`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #240 = G_SHUFFLE_VECTOR
638	{ `239`, `3`, `1`, `0`, `0`, `0`, `0`, `131`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #239 = G_EXTRACT_VECTOR_ELT
639	{ `238`, `4`, `1`, `0`, `0`, `0`, `0`, `127`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #238 = G_INSERT_VECTOR_ELT
640	{ `237`, `3`, `1`, `0`, `0`, `0`, `0`, `58`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #237 = G_EXTRACT_SUBVECTOR
641	{ `236`, `4`, `1`, `0`, `0`, `0`, `0`, `63`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #236 = G_INSERT_SUBVECTOR
642	{ `235`, `2`, `1`, `0`, `0`, `0`, `0`, `51`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #235 = G_VSCALE
643	{ `234`, `3`, `0`, `0`, `0`, `0`, `0`, `124`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Branch)\|(`1ULL`<<MCID::IndirectBranch)\|(`1ULL`<<MCID::Barrier)\|(`1ULL`<<MCID::Terminator)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #234 = G_BRJT
644	{ `233`, `1`, `0`, `0`, `0`, `0`, `0`, `0`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Branch)\|(`1ULL`<<MCID::Barrier)\|(`1ULL`<<MCID::Terminator)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #233 = G_BR
645	{ `232`, `2`, `1`, `0`, `0`, `0`, `0`, `61`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #232 = G_LLROUND
646	{ `231`, `2`, `1`, `0`, `0`, `0`, `0`, `61`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #231 = G_LROUND
647	{ `230`, `2`, `1`, `0`, `0`, `0`, `0`, `67`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #230 = G_ABS
648	{ `229`, `3`, `1`, `0`, `0`, `0`, `0`, `43`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Commutable)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #229 = G_UMAX
649	{ `228`, `3`, `1`, `0`, `0`, `0`, `0`, `43`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Commutable)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #228 = G_UMIN
650	{ `227`, `3`, `1`, `0`, `0`, `0`, `0`, `43`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Commutable)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #227 = G_SMAX
651	{ `226`, `3`, `1`, `0`, `0`, `0`, `0`, `43`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Commutable)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #226 = G_SMIN
652	{ `225`, `3`, `1`, `0`, `0`, `0`, `0`, `101`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #225 = G_PTRMASK
653	{ `224`, `3`, `1`, `0`, `0`, `0`, `0`, `101`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #224 = G_PTR_ADD
654	{ `223`, `0`, `0`, `0`, `0`, `0`, `0`, `1`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #223 = G_RESET_FPMODE
655	{ `222`, `1`, `0`, `0`, `0`, `0`, `0`, `50`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #222 = G_SET_FPMODE
656	{ `221`, `1`, `1`, `0`, `0`, `0`, `0`, `50`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #221 = G_GET_FPMODE
657	{ `220`, `0`, `0`, `0`, `0`, `0`, `0`, `1`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #220 = G_RESET_FPENV
658	{ `219`, `1`, `0`, `0`, `0`, `0`, `0`, `50`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #219 = G_SET_FPENV
659	{ `218`, `1`, `1`, `0`, `0`, `0`, `0`, `50`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #218 = G_GET_FPENV
660	{ `217`, `3`, `1`, `0`, `0`, `0`, `0`, `43`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Commutable)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #217 = G_FMAXIMUMNUM
661	{ `216`, `3`, `1`, `0`, `0`, `0`, `0`, `43`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Commutable)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #216 = G_FMINIMUMNUM
662	{ `215`, `3`, `1`, `0`, `0`, `0`, `0`, `43`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Commutable)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #215 = G_FMAXIMUM
663	{ `214`, `3`, `1`, `0`, `0`, `0`, `0`, `43`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Commutable)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #214 = G_FMINIMUM
664	{ `213`, `3`, `1`, `0`, `0`, `0`, `0`, `43`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Commutable)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #213 = G_FMAXNUM_IEEE
665	{ `212`, `3`, `1`, `0`, `0`, `0`, `0`, `43`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Commutable)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #212 = G_FMINNUM_IEEE
666	{ `211`, `3`, `1`, `0`, `0`, `0`, `0`, `43`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Commutable)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #211 = G_FMAXNUM
667	{ `210`, `3`, `1`, `0`, `0`, `0`, `0`, `43`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Commutable)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #210 = G_FMINNUM
668	{ `209`, `2`, `1`, `0`, `0`, `0`, `0`, `67`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #209 = G_FCANONICALIZE
669	{ `208`, `3`, `1`, `0`, `0`, `0`, `0`, `98`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #208 = G_IS_FPCLASS
670	{ `207`, `3`, `1`, `0`, `0`, `0`, `0`, `101`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #207 = G_FCOPYSIGN
671	{ `206`, `2`, `1`, `0`, `0`, `0`, `0`, `67`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #206 = G_FABS
672	{ `205`, `2`, `1`, `0`, `0`, `0`, `0`, `61`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #205 = G_FPTOUI_SAT
673	{ `204`, `2`, `1`, `0`, `0`, `0`, `0`, `61`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #204 = G_FPTOSI_SAT
674	{ `203`, `2`, `1`, `0`, `0`, `0`, `0`, `61`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #203 = G_UITOFP
675	{ `202`, `2`, `1`, `0`, `0`, `0`, `0`, `61`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #202 = G_SITOFP
676	{ `201`, `2`, `1`, `0`, `0`, `0`, `0`, `61`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #201 = G_FPTOUI
677	{ `200`, `2`, `1`, `0`, `0`, `0`, `0`, `61`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #200 = G_FPTOSI
678	{ `199`, `2`, `1`, `0`, `0`, `0`, `0`, `61`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #199 = G_FPTRUNC
679	{ `198`, `2`, `1`, `0`, `0`, `0`, `0`, `61`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #198 = G_FPEXT
680	{ `197`, `2`, `1`, `0`, `0`, `0`, `0`, `67`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #197 = G_FNEG
681	{ `196`, `3`, `2`, `0`, `0`, `0`, `0`, `91`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #196 = G_FFREXP
682	{ `195`, `3`, `1`, `0`, `0`, `0`, `0`, `101`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #195 = G_FLDEXP
683	{ `194`, `2`, `1`, `0`, `0`, `0`, `0`, `67`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #194 = G_FLOG10
684	{ `193`, `2`, `1`, `0`, `0`, `0`, `0`, `67`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #193 = G_FLOG2
685	{ `192`, `2`, `1`, `0`, `0`, `0`, `0`, `67`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #192 = G_FLOG
686	{ `191`, `2`, `1`, `0`, `0`, `0`, `0`, `67`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #191 = G_FEXP10
687	{ `190`, `2`, `1`, `0`, `0`, `0`, `0`, `67`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #190 = G_FEXP2
688	{ `189`, `2`, `1`, `0`, `0`, `0`, `0`, `67`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #189 = G_FEXP
689	{ `188`, `3`, `1`, `0`, `0`, `0`, `0`, `101`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #188 = G_FPOWI
690	{ `187`, `3`, `1`, `0`, `0`, `0`, `0`, `43`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #187 = G_FPOW
691	{ `186`, `3`, `1`, `0`, `0`, `0`, `0`, `43`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #186 = G_FREM
692	{ `185`, `3`, `1`, `0`, `0`, `0`, `0`, `43`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #185 = G_FDIV
693	{ `184`, `4`, `1`, `0`, `0`, `0`, `0`, `46`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #184 = G_FMAD
694	{ `183`, `4`, `1`, `0`, `0`, `0`, `0`, `46`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #183 = G_FMA
695	{ `182`, `3`, `1`, `0`, `0`, `0`, `0`, `43`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Commutable)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #182 = G_FMUL
696	{ `181`, `3`, `1`, `0`, `0`, `0`, `0`, `43`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #181 = G_FSUB
697	{ `180`, `3`, `1`, `0`, `0`, `0`, `0`, `43`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Commutable)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #180 = G_FADD
698	{ `179`, `4`, `1`, `0`, `0`, `0`, `0`, `120`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #179 = G_UDIVFIXSAT
699	{ `178`, `4`, `1`, `0`, `0`, `0`, `0`, `120`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #178 = G_SDIVFIXSAT
700	{ `177`, `4`, `1`, `0`, `0`, `0`, `0`, `120`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #177 = G_UDIVFIX
701	{ `176`, `4`, `1`, `0`, `0`, `0`, `0`, `120`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #176 = G_SDIVFIX
702	{ `175`, `4`, `1`, `0`, `0`, `0`, `0`, `120`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Commutable)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #175 = G_UMULFIXSAT
703	{ `174`, `4`, `1`, `0`, `0`, `0`, `0`, `120`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Commutable)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #174 = G_SMULFIXSAT
704	{ `173`, `4`, `1`, `0`, `0`, `0`, `0`, `120`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Commutable)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #173 = G_UMULFIX
705	{ `172`, `4`, `1`, `0`, `0`, `0`, `0`, `120`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Commutable)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #172 = G_SMULFIX
706	{ `171`, `3`, `1`, `0`, `0`, `0`, `0`, `101`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #171 = G_SSHLSAT
707	{ `170`, `3`, `1`, `0`, `0`, `0`, `0`, `101`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #170 = G_USHLSAT
708	{ `169`, `3`, `1`, `0`, `0`, `0`, `0`, `43`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #169 = G_SSUBSAT
709	{ `168`, `3`, `1`, `0`, `0`, `0`, `0`, `43`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #168 = G_USUBSAT
710	{ `167`, `3`, `1`, `0`, `0`, `0`, `0`, `43`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Commutable)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #167 = G_SADDSAT
711	{ `166`, `3`, `1`, `0`, `0`, `0`, `0`, `43`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Commutable)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #166 = G_UADDSAT
712	{ `165`, `3`, `1`, `0`, `0`, `0`, `0`, `43`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Commutable)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #165 = G_SMULH
713	{ `164`, `3`, `1`, `0`, `0`, `0`, `0`, `43`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Commutable)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #164 = G_UMULH
714	{ `163`, `4`, `2`, `0`, `0`, `0`, `0`, `87`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Commutable)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #163 = G_SMULO
715	{ `162`, `4`, `2`, `0`, `0`, `0`, `0`, `87`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Commutable)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #162 = G_UMULO
716	{ `161`, `5`, `2`, `0`, `0`, `0`, `0`, `115`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #161 = G_SSUBE
717	{ `160`, `4`, `2`, `0`, `0`, `0`, `0`, `87`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #160 = G_SSUBO
718	{ `159`, `5`, `2`, `0`, `0`, `0`, `0`, `115`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #159 = G_SADDE
719	{ `158`, `4`, `2`, `0`, `0`, `0`, `0`, `87`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Commutable)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #158 = G_SADDO
720	{ `157`, `5`, `2`, `0`, `0`, `0`, `0`, `115`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #157 = G_USUBE
721	{ `156`, `4`, `2`, `0`, `0`, `0`, `0`, `87`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #156 = G_USUBO
722	{ `155`, `5`, `2`, `0`, `0`, `0`, `0`, `115`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #155 = G_UADDE
723	{ `154`, `4`, `2`, `0`, `0`, `0`, `0`, `87`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Commutable)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #154 = G_UADDO
724	{ `153`, `4`, `1`, `0`, `0`, `0`, `0`, `87`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #153 = G_SELECT
725	{ `152`, `3`, `1`, `0`, `0`, `0`, `0`, `112`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #152 = G_UCMP
726	{ `151`, `3`, `1`, `0`, `0`, `0`, `0`, `112`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #151 = G_SCMP
727	{ `150`, `4`, `1`, `0`, `0`, `0`, `0`, `108`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #150 = G_FCMP
728	{ `149`, `4`, `1`, `0`, `0`, `0`, `0`, `108`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #149 = G_ICMP
729	{ `148`, `3`, `1`, `0`, `0`, `0`, `0`, `101`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #148 = G_ROTL
730	{ `147`, `3`, `1`, `0`, `0`, `0`, `0`, `101`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #147 = G_ROTR
731	{ `146`, `4`, `1`, `0`, `0`, `0`, `0`, `104`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #146 = G_FSHR
732	{ `145`, `4`, `1`, `0`, `0`, `0`, `0`, `104`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #145 = G_FSHL
733	{ `144`, `3`, `1`, `0`, `0`, `0`, `0`, `101`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #144 = G_ASHR
734	{ `143`, `3`, `1`, `0`, `0`, `0`, `0`, `101`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #143 = G_LSHR
735	{ `142`, `3`, `1`, `0`, `0`, `0`, `0`, `101`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #142 = G_SHL
736	{ `141`, `2`, `1`, `0`, `0`, `0`, `0`, `61`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #141 = G_ZEXT
737	{ `140`, `3`, `1`, `0`, `0`, `0`, `0`, `40`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #140 = G_SEXT_INREG
738	{ `139`, `2`, `1`, `0`, `0`, `0`, `0`, `61`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #139 = G_SEXT
739	{ `138`, `3`, `1`, `0`, `0`, `0`, `0`, `98`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #138 = G_VAARG
740	{ `137`, `1`, `0`, `0`, `0`, `0`, `0`, `50`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #137 = G_VASTART
741	{ `136`, `2`, `1`, `0`, `0`, `0`, `0`, `51`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #136 = G_FCONSTANT
742	{ `135`, `2`, `1`, `0`, `0`, `0`, `0`, `51`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #135 = G_CONSTANT
743	{ `134`, `2`, `1`, `0`, `0`, `0`, `0`, `61`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #134 = G_TRUNC
744	{ `133`, `2`, `1`, `0`, `0`, `0`, `0`, `61`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #133 = G_ANYEXT
745	{ `132`, `1`, `0`, `0`, `0`, `0`, `0`, `0`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::Variadic)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq)\|(`1ULL`<<MCID::Convergent), `0x0ULL` }, // Inst #132 = G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
746	{ `131`, `1`, `0`, `0`, `0`, `0`, `0`, `0`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Variadic)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq)\|(`1ULL`<<MCID::Convergent), `0x0ULL` }, // Inst #131 = G_INTRINSIC_CONVERGENT
747	{ `130`, `1`, `0`, `0`, `0`, `0`, `0`, `0`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::Variadic)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #130 = G_INTRINSIC_W_SIDE_EFFECTS
748	{ `129`, `1`, `0`, `0`, `0`, `0`, `0`, `0`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Variadic)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #129 = G_INTRINSIC
749	{ `128`, `0`, `0`, `0`, `0`, `0`, `0`, `1`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Terminator)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #128 = G_INVOKE_REGION_START
750	{ `127`, `1`, `0`, `0`, `0`, `0`, `0`, `50`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Branch)\|(`1ULL`<<MCID::IndirectBranch)\|(`1ULL`<<MCID::Barrier)\|(`1ULL`<<MCID::Terminator)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #127 = G_BRINDIRECT
751	{ `126`, `2`, `0`, `0`, `0`, `0`, `0`, `51`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Branch)\|(`1ULL`<<MCID::Terminator)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #126 = G_BRCOND
752	{ `125`, `4`, `0`, `0`, `0`, `0`, `0`, `94`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #125 = G_PREFETCH
753	{ `124`, `2`, `0`, `0`, `0`, `0`, `0`, `21`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #124 = G_FENCE
754	{ `123`, `3`, `1`, `0`, `0`, `0`, `0`, `91`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #123 = G_ATOMICRMW_USUB_SAT
755	{ `122`, `3`, `1`, `0`, `0`, `0`, `0`, `91`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #122 = G_ATOMICRMW_USUB_COND
756	{ `121`, `3`, `1`, `0`, `0`, `0`, `0`, `91`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #121 = G_ATOMICRMW_UDEC_WRAP
757	{ `120`, `3`, `1`, `0`, `0`, `0`, `0`, `91`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #120 = G_ATOMICRMW_UINC_WRAP
758	{ `119`, `3`, `1`, `0`, `0`, `0`, `0`, `91`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #119 = G_ATOMICRMW_FMINIMUM
759	{ `118`, `3`, `1`, `0`, `0`, `0`, `0`, `91`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #118 = G_ATOMICRMW_FMAXIMUM
760	{ `117`, `3`, `1`, `0`, `0`, `0`, `0`, `91`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #117 = G_ATOMICRMW_FMIN
761	{ `116`, `3`, `1`, `0`, `0`, `0`, `0`, `91`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #116 = G_ATOMICRMW_FMAX
762	{ `115`, `3`, `1`, `0`, `0`, `0`, `0`, `91`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #115 = G_ATOMICRMW_FSUB
763	{ `114`, `3`, `1`, `0`, `0`, `0`, `0`, `91`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #114 = G_ATOMICRMW_FADD
764	{ `113`, `3`, `1`, `0`, `0`, `0`, `0`, `91`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #113 = G_ATOMICRMW_UMIN
765	{ `112`, `3`, `1`, `0`, `0`, `0`, `0`, `91`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #112 = G_ATOMICRMW_UMAX
766	{ `111`, `3`, `1`, `0`, `0`, `0`, `0`, `91`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #111 = G_ATOMICRMW_MIN
767	{ `110`, `3`, `1`, `0`, `0`, `0`, `0`, `91`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #110 = G_ATOMICRMW_MAX
768	{ `109`, `3`, `1`, `0`, `0`, `0`, `0`, `91`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #109 = G_ATOMICRMW_XOR
769	{ `108`, `3`, `1`, `0`, `0`, `0`, `0`, `91`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #108 = G_ATOMICRMW_OR
770	{ `107`, `3`, `1`, `0`, `0`, `0`, `0`, `91`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #107 = G_ATOMICRMW_NAND
771	{ `106`, `3`, `1`, `0`, `0`, `0`, `0`, `91`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #106 = G_ATOMICRMW_AND
772	{ `105`, `3`, `1`, `0`, `0`, `0`, `0`, `91`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #105 = G_ATOMICRMW_SUB
773	{ `104`, `3`, `1`, `0`, `0`, `0`, `0`, `91`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #104 = G_ATOMICRMW_ADD
774	{ `103`, `3`, `1`, `0`, `0`, `0`, `0`, `91`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #103 = G_ATOMICRMW_XCHG
775	{ `102`, `4`, `1`, `0`, `0`, `0`, `0`, `87`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #102 = G_ATOMIC_CMPXCHG
776	{ `101`, `5`, `2`, `0`, `0`, `0`, `0`, `82`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #101 = G_ATOMIC_CMPXCHG_WITH_SUCCESS
777	{ `100`, `5`, `1`, `0`, `0`, `0`, `0`, `77`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #100 = G_INDEXED_STORE
778	{ `99`, `2`, `0`, `0`, `0`, `0`, `0`, `61`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #99 = G_STORE
779	{ `98`, `5`, `2`, `0`, `0`, `0`, `0`, `72`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #98 = G_INDEXED_ZEXTLOAD
780	{ `97`, `5`, `2`, `0`, `0`, `0`, `0`, `72`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #97 = G_INDEXED_SEXTLOAD
781	{ `96`, `5`, `2`, `0`, `0`, `0`, `0`, `72`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #96 = G_INDEXED_LOAD
782	{ `95`, `2`, `1`, `0`, `0`, `0`, `0`, `61`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #95 = G_ZEXTLOAD
783	{ `94`, `2`, `1`, `0`, `0`, `0`, `0`, `61`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #94 = G_SEXTLOAD
784	{ `93`, `2`, `1`, `0`, `0`, `0`, `0`, `61`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #93 = G_LOAD
785	{ `92`, `1`, `1`, `0`, `0`, `0`, `0`, `50`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #92 = G_READSTEADYCOUNTER
786	{ `91`, `1`, `1`, `0`, `0`, `0`, `0`, `50`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #91 = G_READCYCLECOUNTER
787	{ `90`, `2`, `1`, `0`, `0`, `0`, `0`, `67`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #90 = G_INTRINSIC_ROUNDEVEN
788	{ `89`, `2`, `1`, `0`, `0`, `0`, `0`, `61`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #89 = G_INTRINSIC_LLRINT
789	{ `88`, `2`, `1`, `0`, `0`, `0`, `0`, `61`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #88 = G_INTRINSIC_LRINT
790	{ `87`, `2`, `1`, `0`, `0`, `0`, `0`, `67`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #87 = G_INTRINSIC_ROUND
791	{ `86`, `2`, `1`, `0`, `0`, `0`, `0`, `67`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #86 = G_INTRINSIC_TRUNC
792	{ `85`, `3`, `1`, `0`, `0`, `0`, `0`, `69`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #85 = G_INTRINSIC_FPTRUNC_ROUND
793	{ `84`, `2`, `1`, `0`, `0`, `0`, `0`, `67`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #84 = G_CONSTANT_FOLD_BARRIER
794	{ `83`, `2`, `1`, `0`, `0`, `0`, `0`, `67`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #83 = G_FREEZE
795	{ `82`, `2`, `1`, `0`, `0`, `0`, `0`, `61`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #82 = G_BITCAST
796	{ `81`, `2`, `1`, `0`, `0`, `0`, `0`, `61`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #81 = G_INTTOPTR
797	{ `80`, `2`, `1`, `0`, `0`, `0`, `0`, `61`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #80 = G_PTRTOINT
798	{ `79`, `2`, `1`, `0`, `0`, `0`, `0`, `61`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Variadic)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #79 = G_CONCAT_VECTORS
799	{ `78`, `2`, `1`, `0`, `0`, `0`, `0`, `61`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Variadic)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #78 = G_BUILD_VECTOR_TRUNC
800	{ `77`, `2`, `1`, `0`, `0`, `0`, `0`, `61`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Variadic)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #77 = G_BUILD_VECTOR
801	{ `76`, `2`, `1`, `0`, `0`, `0`, `0`, `61`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Variadic)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #76 = G_MERGE_VALUES
802	{ `75`, `4`, `1`, `0`, `0`, `0`, `0`, `63`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #75 = G_INSERT
803	{ `74`, `2`, `1`, `0`, `0`, `0`, `0`, `61`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Variadic)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #74 = G_UNMERGE_VALUES
804	{ `73`, `3`, `1`, `0`, `0`, `0`, `0`, `58`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #73 = G_EXTRACT
805	{ `72`, `2`, `1`, `0`, `0`, `0`, `0`, `51`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #72 = G_CONSTANT_POOL
806	{ `71`, `5`, `1`, `0`, `0`, `0`, `0`, `53`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #71 = G_PTRAUTH_GLOBAL_VALUE
807	{ `70`, `2`, `1`, `0`, `0`, `0`, `0`, `51`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #70 = G_GLOBAL_VALUE
808	{ `69`, `2`, `1`, `0`, `0`, `0`, `0`, `51`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #69 = G_FRAME_INDEX
809	{ `68`, `1`, `1`, `0`, `0`, `0`, `0`, `50`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Variadic)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #68 = G_PHI
810	{ `67`, `1`, `1`, `0`, `0`, `0`, `0`, `50`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #67 = G_IMPLICIT_DEF
811	{ `66`, `3`, `1`, `0`, `0`, `0`, `0`, `43`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Commutable)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #66 = G_ABDU
812	{ `65`, `3`, `1`, `0`, `0`, `0`, `0`, `43`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Commutable)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #65 = G_ABDS
813	{ `64`, `3`, `1`, `0`, `0`, `0`, `0`, `43`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Commutable)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #64 = G_XOR
814	{ `63`, `3`, `1`, `0`, `0`, `0`, `0`, `43`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Commutable)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #63 = G_OR
815	{ `62`, `3`, `1`, `0`, `0`, `0`, `0`, `43`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Commutable)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #62 = G_AND
816	{ `61`, `4`, `2`, `0`, `0`, `0`, `0`, `46`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #61 = G_UDIVREM
817	{ `60`, `4`, `2`, `0`, `0`, `0`, `0`, `46`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #60 = G_SDIVREM
818	{ `59`, `3`, `1`, `0`, `0`, `0`, `0`, `43`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #59 = G_UREM
819	{ `58`, `3`, `1`, `0`, `0`, `0`, `0`, `43`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #58 = G_SREM
820	{ `57`, `3`, `1`, `0`, `0`, `0`, `0`, `43`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #57 = G_UDIV
821	{ `56`, `3`, `1`, `0`, `0`, `0`, `0`, `43`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #56 = G_SDIV
822	{ `55`, `3`, `1`, `0`, `0`, `0`, `0`, `43`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Commutable)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #55 = G_MUL
823	{ `54`, `3`, `1`, `0`, `0`, `0`, `0`, `43`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #54 = G_SUB
824	{ `53`, `3`, `1`, `0`, `0`, `0`, `0`, `43`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Commutable)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #53 = G_ADD
825	{ `52`, `3`, `1`, `0`, `0`, `0`, `0`, `40`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #52 = G_ASSERT_ALIGN
826	{ `51`, `3`, `1`, `0`, `0`, `0`, `0`, `40`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #51 = G_ASSERT_ZEXT
827	{ `50`, `3`, `1`, `0`, `0`, `0`, `0`, `40`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #50 = G_ASSERT_SEXT
828	{ `49`, `1`, `0`, `0`, `0`, `0`, `0`, `0`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Meta)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq)\|(`1ULL`<<MCID::Convergent), `0x0ULL` }, // Inst #49 = CONVERGENCECTRL_GLUE
829	{ `48`, `2`, `1`, `0`, `0`, `0`, `0`, `13`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Meta)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq)\|(`1ULL`<<MCID::Convergent), `0x0ULL` }, // Inst #48 = CONVERGENCECTRL_LOOP
830	{ `47`, `1`, `1`, `0`, `0`, `0`, `0`, `0`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Meta)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq)\|(`1ULL`<<MCID::Convergent), `0x0ULL` }, // Inst #47 = CONVERGENCECTRL_ANCHOR
831	{ `46`, `1`, `1`, `0`, `0`, `0`, `0`, `0`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Meta)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq)\|(`1ULL`<<MCID::Convergent), `0x0ULL` }, // Inst #46 = CONVERGENCECTRL_ENTRY
832	{ `45`, `1`, `0`, `0`, `0`, `0`, `0`, `1`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Meta)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #45 = JUMP_TABLE_DEBUG_INFO
833	{ `44`, `0`, `0`, `0`, `0`, `0`, `0`, `1`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Meta)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #44 = MEMBARRIER
834	{ `43`, `0`, `0`, `0`, `0`, `0`, `0`, `1`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Meta)\|(`1ULL`<<MCID::Variadic)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #43 = FAKE_USE
835	{ `42`, `0`, `0`, `0`, `0`, `0`, `0`, `1`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Variadic)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #42 = ICALL_BRANCH_FUNNEL
836	{ `41`, `3`, `0`, `0`, `0`, `0`, `0`, `37`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Call)\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::UsesCustomInserter)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #41 = PATCHABLE_TYPED_EVENT_CALL
837	{ `40`, `2`, `0`, `0`, `0`, `0`, `0`, `35`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Call)\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::UsesCustomInserter)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #40 = PATCHABLE_EVENT_CALL
838	{ `39`, `0`, `0`, `0`, `0`, `0`, `0`, `1`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Return)\|(`1ULL`<<MCID::UsesCustomInserter)\|(`1ULL`<<MCID::Variadic)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #39 = PATCHABLE_TAIL_CALL
839	{ `38`, `0`, `0`, `0`, `0`, `0`, `0`, `1`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::UsesCustomInserter)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #38 = PATCHABLE_FUNCTION_EXIT
840	{ `37`, `0`, `0`, `0`, `0`, `0`, `0`, `1`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Return)\|(`1ULL`<<MCID::Terminator)\|(`1ULL`<<MCID::UsesCustomInserter)\|(`1ULL`<<MCID::Variadic)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #37 = PATCHABLE_RET
841	{ `36`, `0`, `0`, `0`, `0`, `0`, `0`, `1`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::UsesCustomInserter)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #36 = PATCHABLE_FUNCTION_ENTER
842	{ `35`, `0`, `0`, `0`, `0`, `0`, `0`, `1`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::UsesCustomInserter)\|(`1ULL`<<MCID::Variadic)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #35 = PATCHABLE_OP
843	{ `34`, `1`, `1`, `0`, `0`, `0`, `0`, `0`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Branch)\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::Terminator)\|(`1ULL`<<MCID::UsesCustomInserter)\|(`1ULL`<<MCID::Variadic)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #34 = FAULTING_OP
844	{ `33`, `2`, `0`, `0`, `0`, `0`, `0`, `33`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #33 = LOCAL_ESCAPE
845	{ `32`, `0`, `0`, `0`, `0`, `0`, `0`, `1`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Call)\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::UsesCustomInserter)\|(`1ULL`<<MCID::Variadic)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #32 = STATEPOINT
846	{ `31`, `3`, `1`, `0`, `0`, `0`, `0`, `30`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::UsesCustomInserter)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #31 = PREALLOCATED_ARG
847	{ `30`, `1`, `0`, `0`, `0`, `0`, `0`, `1`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::UsesCustomInserter)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #30 = PREALLOCATED_SETUP
848	{ `29`, `1`, `1`, `0`, `0`, `0`, `0`, `29`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::Rematerializable)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #29 = LOAD_STACK_GUARD
849	{ `28`, `6`, `1`, `0`, `0`, `0`, `0`, `23`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Call)\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::UsesCustomInserter)\|(`1ULL`<<MCID::Variadic)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #28 = PATCHPOINT
850	{ `27`, `0`, `0`, `0`, `0`, `0`, `0`, `1`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Call)\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::UsesCustomInserter)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #27 = FENTRY_CALL
851	{ `26`, `2`, `0`, `0`, `0`, `0`, `0`, `21`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Call)\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::UsesCustomInserter)\|(`1ULL`<<MCID::Variadic)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #26 = STACKMAP
852	{ `25`, `2`, `1`, `0`, `0`, `0`, `0`, `19`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Meta)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #25 = ARITH_FENCE
853	{ `24`, `4`, `0`, `0`, `0`, `0`, `0`, `15`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Meta)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #24 = PSEUDO_PROBE
854	{ `23`, `1`, `0`, `0`, `0`, `0`, `0`, `1`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Meta)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #23 = LIFETIME_END
855	{ `22`, `1`, `0`, `0`, `0`, `0`, `0`, `1`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Meta)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #22 = LIFETIME_START
856	{ `21`, `0`, `0`, `0`, `0`, `0`, `0`, `1`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Variadic)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #21 = BUNDLE
857	{ `20`, `2`, `1`, `0`, `0`, `0`, `0`, `13`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::CheapAsAMove)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #20 = COPY
858	{ `19`, `2`, `1`, `0`, `0`, `0`, `0`, `13`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Variadic)\|(`1ULL`<<MCID::CheapAsAMove)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #19 = REG_SEQUENCE
859	{ `18`, `1`, `0`, `0`, `0`, `0`, `0`, `0`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Meta)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #18 = DBG_LABEL
860	{ `17`, `0`, `0`, `0`, `0`, `0`, `0`, `1`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Meta)\|(`1ULL`<<MCID::Variadic)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #17 = DBG_PHI
861	{ `16`, `0`, `0`, `0`, `0`, `0`, `0`, `1`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Meta)\|(`1ULL`<<MCID::Variadic)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #16 = DBG_INSTR_REF
862	{ `15`, `0`, `0`, `0`, `0`, `0`, `0`, `1`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Meta)\|(`1ULL`<<MCID::Variadic)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #15 = DBG_VALUE_LIST
863	{ `14`, `0`, `0`, `0`, `0`, `0`, `0`, `1`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Meta)\|(`1ULL`<<MCID::Variadic)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #14 = DBG_VALUE
864	{ `13`, `3`, `1`, `0`, `0`, `0`, `0`, `2`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::CheapAsAMove)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #13 = COPY_TO_REGCLASS
865	{ `12`, `4`, `1`, `0`, `0`, `0`, `0`, `9`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #12 = SUBREG_TO_REG
866	{ `11`, `1`, `1`, `0`, `0`, `0`, `0`, `0`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #11 = INIT_UNDEF
867	{ `10`, `1`, `1`, `0`, `0`, `0`, `0`, `0`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Meta)\|(`1ULL`<<MCID::Rematerializable)\|(`1ULL`<<MCID::CheapAsAMove)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #10 = IMPLICIT_DEF
868	{ `9`, `4`, `1`, `0`, `0`, `0`, `0`, `5`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #9 = INSERT_SUBREG
869	{ `8`, `3`, `1`, `0`, `0`, `0`, `0`, `2`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #8 = EXTRACT_SUBREG
870	{ `7`, `0`, `0`, `0`, `0`, `0`, `0`, `1`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Meta)\|(`1ULL`<<MCID::Variadic)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #7 = KILL
871	{ `6`, `1`, `0`, `0`, `0`, `0`, `0`, `1`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::NotDuplicable)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #6 = ANNOTATION_LABEL
872	{ `5`, `1`, `0`, `0`, `0`, `0`, `0`, `1`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Meta)\|(`1ULL`<<MCID::NotDuplicable)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #5 = GC_LABEL
873	{ `4`, `1`, `0`, `0`, `0`, `0`, `0`, `1`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Meta)\|(`1ULL`<<MCID::NotDuplicable)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #4 = EH_LABEL
874	{ `3`, `1`, `0`, `0`, `0`, `0`, `0`, `1`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Meta)\|(`1ULL`<<MCID::NotDuplicable)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #3 = CFI_INSTRUCTION
875	{ `2`, `0`, `0`, `0`, `0`, `0`, `0`, `1`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Variadic)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #2 = INLINEASM_BR
876	{ `1`, `0`, `0`, `0`, `0`, `0`, `0`, `1`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Variadic)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #1 = INLINEASM
877	{ `0`, `1`, `1`, `0`, `0`, `0`, `0`, `0`, LanaiImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Variadic)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #0 = PHI
878	}, {
879	/ 0 / { -`1`, `0`, MCOI::OPERAND_UNKNOWN, `0` },
880	/ 1 /
881	/ 1 / { -`1`, `0`, MCOI::OPERAND_IMMEDIATE, `0` },
882	/ 2 / { -`1`, `0`, MCOI::OPERAND_UNKNOWN, `0` }, { -`1`, `0`, MCOI::OPERAND_UNKNOWN, `0` }, { -`1`, `0`, MCOI::OPERAND_IMMEDIATE, `0` },
883	/ 5 / { -`1`, `0`, MCOI::OPERAND_UNKNOWN, `0` }, { -`1`, `0`, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(`0`) }, { -`1`, `0`, MCOI::OPERAND_UNKNOWN, `0` }, { -`1`, `0`, MCOI::OPERAND_IMMEDIATE, `0` },
884	/ 9 / { -`1`, `0`, MCOI::OPERAND_UNKNOWN, `0` }, { -`1`, `0`, MCOI::OPERAND_UNKNOWN, `0` }, { -`1`, `0`, MCOI::OPERAND_UNKNOWN, `0` }, { -`1`, `0`, MCOI::OPERAND_IMMEDIATE, `0` },
885	/ 13 / { -`1`, `0`, MCOI::OPERAND_UNKNOWN, `0` }, { -`1`, `0`, MCOI::OPERAND_UNKNOWN, `0` },
886	/ 15 / { -`1`, `0`, MCOI::OPERAND_IMMEDIATE, `0` }, { -`1`, `0`, MCOI::OPERAND_IMMEDIATE, `0` }, { -`1`, `0`, MCOI::OPERAND_IMMEDIATE, `0` }, { -`1`, `0`, MCOI::OPERAND_IMMEDIATE, `0` },
887	/ 19 / { -`1`, `0`, MCOI::OPERAND_UNKNOWN, `0` }, { -`1`, `0`, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(`0`) },
888	/ 21 / { -`1`, `0`, MCOI::OPERAND_IMMEDIATE, `0` }, { -`1`, `0`, MCOI::OPERAND_IMMEDIATE, `0` },
889	/ 23 / { -`1`, `0`, MCOI::OPERAND_UNKNOWN, `0` }, { -`1`, `0`, MCOI::OPERAND_IMMEDIATE, `0` }, { -`1`, `0`, MCOI::OPERAND_IMMEDIATE, `0` }, { -`1`, `0`, MCOI::OPERAND_UNKNOWN, `0` }, { -`1`, `0`, MCOI::OPERAND_IMMEDIATE, `0` }, { -`1`, `0`, MCOI::OPERAND_IMMEDIATE, `0` },
890	/ 29 / { `0`, `0`\|(`1`<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, `0` },
891	/ 30 / { `0`, `0`\|(`1`<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, `0` }, { -`1`, `0`, MCOI::OPERAND_IMMEDIATE, `0` }, { -`1`, `0`, MCOI::OPERAND_IMMEDIATE, `0` },
892	/ 33 / { `0`, `0`\|(`1`<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, `0` }, { -`1`, `0`, MCOI::OPERAND_IMMEDIATE, `0` },
893	/ 35 / { `0`, `0`\|(`1`<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, `0` }, { -`1`, `0`, MCOI::OPERAND_UNKNOWN, `0` },
894	/ 37 / { -`1`, `0`, MCOI::OPERAND_UNKNOWN, `0` }, { `0`, `0`\|(`1`<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, `0` }, { -`1`, `0`, MCOI::OPERAND_UNKNOWN, `0` },
895	/ 40 / { -`1`, `0`, MCOI::OPERAND_GENERIC_0, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_0, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_IMM_0, `0` },
896	/ 43 / { -`1`, `0`, MCOI::OPERAND_GENERIC_0, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_0, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_0, `0` },
897	/ 46 / { -`1`, `0`, MCOI::OPERAND_GENERIC_0, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_0, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_0, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_0, `0` },
898	/ 50 / { -`1`, `0`, MCOI::OPERAND_GENERIC_0, `0` },
899	/ 51 / { -`1`, `0`, MCOI::OPERAND_GENERIC_0, `0` }, { -`1`, `0`, MCOI::OPERAND_UNKNOWN, `0` },
900	/ 53 / { -`1`, `0`, MCOI::OPERAND_GENERIC_0, `0` }, { -`1`, `0`, MCOI::OPERAND_UNKNOWN, `0` }, { -`1`, `0`, MCOI::OPERAND_IMMEDIATE, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_1, `0` }, { -`1`, `0`, MCOI::OPERAND_IMMEDIATE, `0` },
901	/ 58 / { -`1`, `0`, MCOI::OPERAND_GENERIC_0, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_1, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_IMM_0, `0` },
902	/ 61 / { -`1`, `0`, MCOI::OPERAND_GENERIC_0, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_1, `0` },
903	/ 63 / { -`1`, `0`, MCOI::OPERAND_GENERIC_0, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_0, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_1, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_IMM_0, `0` },
904	/ 67 / { -`1`, `0`, MCOI::OPERAND_GENERIC_0, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_0, `0` },
905	/ 69 / { -`1`, `0`, MCOI::OPERAND_GENERIC_0, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_1, `0` }, { -`1`, `0`, MCOI::OPERAND_IMMEDIATE, `0` },
906	/ 72 / { -`1`, `0`, MCOI::OPERAND_GENERIC_0, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_1, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_1, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_2, `0` }, { -`1`, `0`, MCOI::OPERAND_UNKNOWN, `0` },
907	/ 77 / { -`1`, `0`, MCOI::OPERAND_GENERIC_0, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_1, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_0, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_2, `0` }, { -`1`, `0`, MCOI::OPERAND_UNKNOWN, `0` },
908	/ 82 / { -`1`, `0`, MCOI::OPERAND_GENERIC_0, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_1, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_2, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_0, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_0, `0` },
909	/ 87 / { -`1`, `0`, MCOI::OPERAND_GENERIC_0, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_1, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_0, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_0, `0` },
910	/ 91 / { -`1`, `0`, MCOI::OPERAND_GENERIC_0, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_1, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_0, `0` },
911	/ 94 / { -`1`, `0`, MCOI::OPERAND_GENERIC_0, `0` }, { -`1`, `0`, MCOI::OPERAND_IMMEDIATE, `0` }, { -`1`, `0`, MCOI::OPERAND_IMMEDIATE, `0` }, { -`1`, `0`, MCOI::OPERAND_IMMEDIATE, `0` },
912	/ 98 / { -`1`, `0`, MCOI::OPERAND_GENERIC_0, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_1, `0` }, { -`1`, `0`, MCOI::OPERAND_UNKNOWN, `0` },
913	/ 101 / { -`1`, `0`, MCOI::OPERAND_GENERIC_0, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_0, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_1, `0` },
914	/ 104 / { -`1`, `0`, MCOI::OPERAND_GENERIC_0, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_0, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_0, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_1, `0` },
915	/ 108 / { -`1`, `0`, MCOI::OPERAND_GENERIC_0, `0` }, { -`1`, `0`, MCOI::OPERAND_UNKNOWN, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_1, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_1, `0` },
916	/ 112 / { -`1`, `0`, MCOI::OPERAND_GENERIC_0, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_1, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_1, `0` },
917	/ 115 / { -`1`, `0`, MCOI::OPERAND_GENERIC_0, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_1, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_0, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_0, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_1, `0` },
918	/ 120 / { -`1`, `0`, MCOI::OPERAND_GENERIC_0, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_0, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_0, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_IMM_0, `0` },
919	/ 124 / { -`1`, `0`, MCOI::OPERAND_GENERIC_0, `0` }, { -`1`, `0`, MCOI::OPERAND_UNKNOWN, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_1, `0` },
920	/ 127 / { -`1`, `0`, MCOI::OPERAND_GENERIC_0, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_0, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_1, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_2, `0` },
921	/ 131 / { -`1`, `0`, MCOI::OPERAND_GENERIC_0, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_1, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_2, `0` },
922	/ 134 / { -`1`, `0`, MCOI::OPERAND_GENERIC_0, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_1, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_1, `0` }, { -`1`, `0`, MCOI::OPERAND_UNKNOWN, `0` },
923	/ 138 / { -`1`, `0`, MCOI::OPERAND_GENERIC_0, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_0, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_1, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_0, `0` },
924	/ 142 / { -`1`, `0`, MCOI::OPERAND_UNKNOWN, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_0, `0` },
925	/ 144 / { -`1`, `0`, MCOI::OPERAND_GENERIC_0, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_1, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_2, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_IMM_0, `0` },
926	/ 148 / { -`1`, `0`, MCOI::OPERAND_GENERIC_0, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_0, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_1, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_1, `0` },
927	/ 152 / { Lanai::GPRRegClassID, `0`, MCOI::OPERAND_REGISTER, `0` }, { Lanai::GPRRegClassID, `0`, MCOI::OPERAND_REGISTER, `0` },
928	/ 154 / { Lanai::GPRRegClassID, `0`, MCOI::OPERAND_REGISTER, `0` },
929	/ 155 / { Lanai::GPRRegClassID, `0`, MCOI::OPERAND_REGISTER, `0` }, { Lanai::GPRRegClassID, `0`, MCOI::OPERAND_REGISTER, `0` }, { -`1`, `0`, MCOI::OPERAND_UNKNOWN, `0` },
930	/ 158 / { Lanai::GPRRegClassID, `0`, MCOI::OPERAND_REGISTER, `0` }, { Lanai::GPRRegClassID, `0`, MCOI::OPERAND_REGISTER, `0` }, { Lanai::GPRRegClassID, `0`, MCOI::OPERAND_REGISTER, `0` }, { -`1`, `0`\|(`1`<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, `0` },
931	/ 162 / { Lanai::GPRRegClassID, `0`, MCOI::OPERAND_REGISTER, `0` }, { -`1`, `0`, MCOI::OPERAND_UNKNOWN, `0` },
932	/ 164 / { -`1`, `0`, MCOI::OPERAND_IMMEDIATE, `0` }, { -`1`, `0`, MCOI::OPERAND_UNKNOWN, `0` },
933	/ 166 / { Lanai::GPRRegClassID, `0`, MCOI::OPERAND_REGISTER, `0` }, { Lanai::GPRRegClassID, `0`, MCOI::OPERAND_UNKNOWN, `0` }, { -`1`, `0`, MCOI::OPERAND_UNKNOWN, `0` }, { -`1`, `0`, MCOI::OPERAND_UNKNOWN, `0` },
934	/ 170 / { Lanai::GPRRegClassID, `0`, MCOI::OPERAND_REGISTER, `0` }, { Lanai::GPRRegClassID, `0`, MCOI::OPERAND_UNKNOWN, `0` }, { Lanai::GPRRegClassID, `0`, MCOI::OPERAND_UNKNOWN, `0` }, { -`1`, `0`, MCOI::OPERAND_UNKNOWN, `0` },
935	/ 174 / { Lanai::GPRRegClassID, `0`, MCOI::OPERAND_REGISTER, `0` }, { Lanai::GPRRegClassID, `0`, MCOI::OPERAND_REGISTER, `0` }, { Lanai::GPRRegClassID, `0`, MCOI::OPERAND_REGISTER, `0` }, { -`1`, `0`, MCOI::OPERAND_UNKNOWN, `0` },
936	}, {
937	/ 0 /
938	/ 0 / Lanai::SP, Lanai::SP,
939	/ 2 / Lanai::SP, Lanai::RCA,
940	/ 4 / Lanai::SR, Lanai::SR,
941	/ 6 / Lanai::SR,
942	/ 7 / Lanai::RCA,
943	}
944	};
945
946
947	#ifdef __GNUC__
948	#pragma GCC diagnostic push
949	#pragma GCC diagnostic ignored "-Woverlength-strings"
950	#endif
951	extern const char LanaiInstrNameData[] = {
952	/ 0 / "G_FLOG10\000"
953	/ 9 / "G_FEXP10\000"
954	/ 18 / "LOG0\000"
955	/ 23 / "LOG1\000"
956	/ 28 / "G_FLOG2\000"
957	/ 36 / "G_FATAN2\000"
958	/ 45 / "G_FEXP2\000"
959	/ 53 / "LOG3\000"
960	/ 58 / "LOG4\000"
961	/ 63 / "BRIND_CCA\000"
962	/ 73 / "G_FMA\000"
963	/ 79 / "G_STRICT_FMA\000"
964	/ 92 / "G_FSUB\000"
965	/ 99 / "G_STRICT_FSUB\000"
966	/ 113 / "G_ATOMICRMW_FSUB\000"
967	/ 130 / "G_SUB\000"
968	/ 136 / "G_ATOMICRMW_SUB\000"
969	/ 152 / "BRCC\000"
970	/ 157 / "SCC\000"
971	/ 161 / "BRIND_CC\000"
972	/ 170 / "G_INTRINSIC\000"
973	/ 182 / "G_FPTRUNC\000"
974	/ 192 / "G_INTRINSIC_TRUNC\000"
975	/ 210 / "G_TRUNC\000"
976	/ 218 / "G_BUILD_VECTOR_TRUNC\000"
977	/ 239 / "G_DYN_STACKALLOC\000"
978	/ 256 / "ADJDYNALLOC\000"
979	/ 268 / "POPC\000"
980	/ 273 / "G_FMAD\000"
981	/ 280 / "G_INDEXED_SEXTLOAD\000"
982	/ 299 / "G_SEXTLOAD\000"
983	/ 310 / "G_INDEXED_ZEXTLOAD\000"
984	/ 329 / "G_ZEXTLOAD\000"
985	/ 340 / "G_INDEXED_LOAD\000"
986	/ 355 / "G_LOAD\000"
987	/ 362 / "G_VECREDUCE_FADD\000"
988	/ 379 / "G_FADD\000"
989	/ 386 / "G_VECREDUCE_SEQ_FADD\000"
990	/ 407 / "G_STRICT_FADD\000"
991	/ 421 / "G_ATOMICRMW_FADD\000"
992	/ 438 / "G_VECREDUCE_ADD\000"
993	/ 454 / "G_ADD\000"
994	/ 460 / "G_PTR_ADD\000"
995	/ 470 / "G_ATOMICRMW_ADD\000"
996	/ 486 / "G_ATOMICRMW_NAND\000"
997	/ 503 / "G_VECREDUCE_AND\000"
998	/ 519 / "G_AND\000"
999	/ 525 / "G_ATOMICRMW_AND\000"
1000	/ 541 / "LIFETIME_END\000"
1001	/ 554 / "G_BRCOND\000"
1002	/ 563 / "G_ATOMICRMW_USUB_COND\000"
1003	/ 585 / "G_LLROUND\000"
1004	/ 595 / "G_LROUND\000"
1005	/ 604 / "G_INTRINSIC_ROUND\000"
1006	/ 622 / "G_INTRINSIC_FPTRUNC_ROUND\000"
1007	/ 648 / "LOAD_STACK_GUARD\000"
1008	/ 665 / "PSEUDO_PROBE\000"
1009	/ 678 / "G_SSUBE\000"
1010	/ 686 / "G_USUBE\000"
1011	/ 694 / "G_FENCE\000"
1012	/ 702 / "ARITH_FENCE\000"
1013	/ 714 / "REG_SEQUENCE\000"
1014	/ 727 / "G_SADDE\000"
1015	/ 735 / "G_UADDE\000"
1016	/ 743 / "G_GET_FPMODE\000"
1017	/ 756 / "G_RESET_FPMODE\000"
1018	/ 771 / "G_SET_FPMODE\000"
1019	/ 784 / "G_FMINNUM_IEEE\000"
1020	/ 799 / "G_FMAXNUM_IEEE\000"
1021	/ 814 / "G_VSCALE\000"
1022	/ 823 / "G_JUMP_TABLE\000"
1023	/ 836 / "BUNDLE\000"
1024	/ 843 / "G_MEMCPY_INLINE\000"
1025	/ 859 / "LOCAL_ESCAPE\000"
1026	/ 872 / "G_STACKRESTORE\000"
1027	/ 887 / "G_INDEXED_STORE\000"
1028	/ 903 / "G_STORE\000"
1029	/ 911 / "G_BITREVERSE\000"
1030	/ 924 / "FAKE_USE\000"
1031	/ 933 / "DBG_VALUE\000"
1032	/ 943 / "G_GLOBAL_VALUE\000"
1033	/ 958 / "G_PTRAUTH_GLOBAL_VALUE\000"
1034	/ 981 / "CONVERGENCECTRL_GLUE\000"
1035	/ 1002 / "G_STACKSAVE\000"
1036	/ 1014 / "G_MEMMOVE\000"
1037	/ 1024 / "G_FREEZE\000"
1038	/ 1033 / "G_FCANONICALIZE\000"
1039	/ 1049 / "G_CTLZ_ZERO_UNDEF\000"
1040	/ 1067 / "G_CTTZ_ZERO_UNDEF\000"
1041	/ 1085 / "INIT_UNDEF\000"
1042	/ 1096 / "G_IMPLICIT_DEF\000"
1043	/ 1111 / "DBG_INSTR_REF\000"
1044	/ 1125 / "G_FNEG\000"
1045	/ 1132 / "EXTRACT_SUBREG\000"
1046	/ 1147 / "INSERT_SUBREG\000"
1047	/ 1161 / "G_SEXT_INREG\000"
1048	/ 1174 / "SUBREG_TO_REG\000"
1049	/ 1188 / "G_ATOMIC_CMPXCHG\000"
1050	/ 1205 / "G_ATOMICRMW_XCHG\000"
1051	/ 1222 / "G_FLOG\000"
1052	/ 1229 / "G_VAARG\000"
1053	/ 1237 / "PREALLOCATED_ARG\000"
1054	/ 1254 / "G_PREFETCH\000"
1055	/ 1265 / "G_SMULH\000"
1056	/ 1273 / "G_UMULH\000"
1057	/ 1281 / "G_FTANH\000"
1058	/ 1289 / "G_FSINH\000"
1059	/ 1297 / "G_FCOSH\000"
1060	/ 1305 / "DBG_PHI\000"
1061	/ 1313 / "MOVHI\000"
1062	/ 1319 / "SFSUB_F_RI_HI\000"
1063	/ 1333 / "SUBB_I_HI\000"
1064	/ 1343 / "SUB_I_HI\000"
1065	/ 1352 / "ADDC_I_HI\000"
1066	/ 1362 / "ADD_I_HI\000"
1067	/ 1371 / "AND_I_HI\000"
1068	/ 1380 / "SUBB_F_I_HI\000"
1069	/ 1392 / "SUB_F_I_HI\000"
1070	/ 1403 / "ADDC_F_I_HI\000"
1071	/ 1415 / "ADD_F_I_HI\000"
1072	/ 1426 / "AND_F_I_HI\000"
1073	/ 1437 / "XOR_F_I_HI\000"
1074	/ 1448 / "XOR_I_HI\000"
1075	/ 1457 / "SLI\000"
1076	/ 1461 / "STB_RI\000"
1077	/ 1468 / "STH_RI\000"
1078	/ 1475 / "LDW_RI\000"
1079	/ 1482 / "SW_RI\000"
1080	/ 1488 / "LDBs_RI\000"
1081	/ 1496 / "LDHs_RI\000"
1082	/ 1504 / "LDBz_RI\000"
1083	/ 1512 / "LDHz_RI\000"
1084	/ 1520 / "G_FPTOSI\000"
1085	/ 1529 / "G_FPTOUI\000"
1086	/ 1538 / "G_FPOWI\000"
1087	/ 1546 / "SA_I\000"
1088	/ 1551 / "SA_F_I\000"
1089	/ 1558 / "SL_F_I\000"
1090	/ 1565 / "SL_I\000"
1091	/ 1570 / "G_PTRMASK\000"
1092	/ 1580 / "GC_LABEL\000"
1093	/ 1589 / "DBG_LABEL\000"
1094	/ 1599 / "EH_LABEL\000"
1095	/ 1608 / "ANNOTATION_LABEL\000"
1096	/ 1625 / "ICALL_BRANCH_FUNNEL\000"
1097	/ 1645 / "G_FSHL\000"
1098	/ 1652 / "G_SHL\000"
1099	/ 1658 / "G_FCEIL\000"
1100	/ 1666 / "PATCHABLE_TAIL_CALL\000"
1101	/ 1686 / "PATCHABLE_TYPED_EVENT_CALL\000"
1102	/ 1713 / "PATCHABLE_EVENT_CALL\000"
1103	/ 1734 / "FENTRY_CALL\000"
1104	/ 1746 / "KILL\000"
1105	/ 1751 / "G_CONSTANT_POOL\000"
1106	/ 1767 / "G_ROTL\000"
1107	/ 1774 / "G_VECREDUCE_FMUL\000"
1108	/ 1791 / "G_FMUL\000"
1109	/ 1798 / "G_VECREDUCE_SEQ_FMUL\000"
1110	/ 1819 / "G_STRICT_FMUL\000"
1111	/ 1833 / "G_VECREDUCE_MUL\000"
1112	/ 1849 / "G_MUL\000"
1113	/ 1855 / "G_FREM\000"
1114	/ 1862 / "G_STRICT_FREM\000"
1115	/ 1876 / "G_SREM\000"
1116	/ 1883 / "G_UREM\000"
1117	/ 1890 / "G_SDIVREM\000"
1118	/ 1900 / "G_UDIVREM\000"
1119	/ 1910 / "INLINEASM\000"
1120	/ 1920 / "G_VECREDUCE_FMINIMUM\000"
1121	/ 1941 / "G_FMINIMUM\000"
1122	/ 1952 / "G_ATOMICRMW_FMINIMUM\000"
1123	/ 1973 / "G_VECREDUCE_FMAXIMUM\000"
1124	/ 1994 / "G_FMAXIMUM\000"
1125	/ 2005 / "G_ATOMICRMW_FMAXIMUM\000"
1126	/ 2026 / "G_FMINIMUMNUM\000"
1127	/ 2040 / "G_FMAXIMUMNUM\000"
1128	/ 2054 / "G_FMINNUM\000"
1129	/ 2064 / "G_FMAXNUM\000"
1130	/ 2074 / "G_FATAN\000"
1131	/ 2082 / "G_FTAN\000"
1132	/ 2089 / "G_INTRINSIC_ROUNDEVEN\000"
1133	/ 2111 / "G_ASSERT_ALIGN\000"
1134	/ 2126 / "G_FCOPYSIGN\000"
1135	/ 2138 / "G_VECREDUCE_FMIN\000"
1136	/ 2155 / "G_ATOMICRMW_FMIN\000"
1137	/ 2172 / "G_VECREDUCE_SMIN\000"
1138	/ 2189 / "G_SMIN\000"
1139	/ 2196 / "G_VECREDUCE_UMIN\000"
1140	/ 2213 / "G_UMIN\000"
1141	/ 2220 / "G_ATOMICRMW_UMIN\000"
1142	/ 2237 / "G_ATOMICRMW_MIN\000"
1143	/ 2253 / "G_FASIN\000"
1144	/ 2261 / "G_FSIN\000"
1145	/ 2268 / "CFI_INSTRUCTION\000"
1146	/ 2284 / "ADJCALLSTACKDOWN\000"
1147	/ 2301 / "G_SSUBO\000"
1148	/ 2309 / "G_USUBO\000"
1149	/ 2317 / "G_SADDO\000"
1150	/ 2325 / "G_UADDO\000"
1151	/ 2333 / "JUMP_TABLE_DEBUG_INFO\000"
1152	/ 2355 / "G_SMULO\000"
1153	/ 2363 / "G_UMULO\000"
1154	/ 2371 / "SFSUB_F_RI_LO\000"
1155	/ 2385 / "SUBB_I_LO\000"
1156	/ 2395 / "SUB_I_LO\000"
1157	/ 2404 / "ADDC_I_LO\000"
1158	/ 2414 / "ADD_I_LO\000"
1159	/ 2423 / "AND_I_LO\000"
1160	/ 2432 / "SUBB_F_I_LO\000"
1161	/ 2444 / "SUB_F_I_LO\000"
1162	/ 2455 / "ADDC_F_I_LO\000"
1163	/ 2467 / "ADD_F_I_LO\000"
1164	/ 2478 / "AND_F_I_LO\000"
1165	/ 2489 / "XOR_F_I_LO\000"
1166	/ 2500 / "XOR_I_LO\000"
1167	/ 2509 / "G_BZERO\000"
1168	/ 2517 / "STACKMAP\000"
1169	/ 2526 / "G_DEBUGTRAP\000"
1170	/ 2538 / "G_UBSANTRAP\000"
1171	/ 2550 / "G_TRAP\000"
1172	/ 2557 / "G_ATOMICRMW_UDEC_WRAP\000"
1173	/ 2579 / "G_ATOMICRMW_UINC_WRAP\000"
1174	/ 2601 / "G_BSWAP\000"
1175	/ 2609 / "G_SITOFP\000"
1176	/ 2618 / "G_UITOFP\000"
1177	/ 2627 / "G_FCMP\000"
1178	/ 2634 / "G_ICMP\000"
1179	/ 2641 / "G_SCMP\000"
1180	/ 2648 / "G_UCMP\000"
1181	/ 2655 / "NOP\000"
1182	/ 2659 / "CONVERGENCECTRL_LOOP\000"
1183	/ 2680 / "G_CTPOP\000"
1184	/ 2688 / "PATCHABLE_OP\000"
1185	/ 2701 / "FAULTING_OP\000"
1186	/ 2713 / "ADJCALLSTACKUP\000"
1187	/ 2728 / "PREALLOCATED_SETUP\000"
1188	/ 2747 / "G_FLDEXP\000"
1189	/ 2756 / "G_STRICT_FLDEXP\000"
1190	/ 2772 / "G_FEXP\000"
1191	/ 2779 / "G_FFREXP\000"
1192	/ 2788 / "G_BR\000"
1193	/ 2793 / "INLINEASM_BR\000"
1194	/ 2806 / "LDADDR\000"
1195	/ 2813 / "STADDR\000"
1196	/ 2820 / "G_BLOCK_ADDR\000"
1197	/ 2833 / "MEMBARRIER\000"
1198	/ 2844 / "G_CONSTANT_FOLD_BARRIER\000"
1199	/ 2868 / "PATCHABLE_FUNCTION_ENTER\000"
1200	/ 2893 / "G_READCYCLECOUNTER\000"
1201	/ 2912 / "G_READSTEADYCOUNTER\000"
1202	/ 2932 / "G_READ_REGISTER\000"
1203	/ 2948 / "G_WRITE_REGISTER\000"
1204	/ 2965 / "G_ASHR\000"
1205	/ 2972 / "G_FSHR\000"
1206	/ 2979 / "G_LSHR\000"
1207	/ 2986 / "JR\000"
1208	/ 2989 / "CALLR\000"
1209	/ 2995 / "CONVERGENCECTRL_ANCHOR\000"
1210	/ 3018 / "G_FFLOOR\000"
1211	/ 3027 / "G_EXTRACT_SUBVECTOR\000"
1212	/ 3047 / "G_INSERT_SUBVECTOR\000"
1213	/ 3066 / "G_BUILD_VECTOR\000"
1214	/ 3081 / "G_SHUFFLE_VECTOR\000"
1215	/ 3098 / "G_STEP_VECTOR\000"
1216	/ 3112 / "G_SPLAT_VECTOR\000"
1217	/ 3127 / "G_VECREDUCE_XOR\000"
1218	/ 3143 / "G_XOR\000"
1219	/ 3149 / "G_ATOMICRMW_XOR\000"
1220	/ 3165 / "G_VECREDUCE_OR\000"
1221	/ 3180 / "G_OR\000"
1222	/ 3185 / "G_ATOMICRMW_OR\000"
1223	/ 3200 / "BRR\000"
1224	/ 3204 / "STB_RR\000"
1225	/ 3211 / "SFSUB_F_RR\000"
1226	/ 3222 / "STH_RR\000"
1227	/ 3229 / "LDW_RR\000"
1228	/ 3236 / "SW_RR\000"
1229	/ 3242 / "LDBs_RR\000"
1230	/ 3250 / "LDHs_RR\000"
1231	/ 3258 / "LDBz_RR\000"
1232	/ 3266 / "LDHz_RR\000"
1233	/ 3274 / "LDWz_RR\000"
1234	/ 3282 / "G_ROTR\000"
1235	/ 3289 / "G_INTTOPTR\000"
1236	/ 3300 / "SRA_R\000"
1237	/ 3306 / "SUBB_R\000"
1238	/ 3313 / "SUB_R\000"
1239	/ 3319 / "ADDC_R\000"
1240	/ 3326 / "ADD_R\000"
1241	/ 3332 / "AND_R\000"
1242	/ 3338 / "SRA_F_R\000"
1243	/ 3346 / "SUBB_F_R\000"
1244	/ 3355 / "SUB_F_R\000"
1245	/ 3363 / "ADDC_F_R\000"
1246	/ 3372 / "ADD_F_R\000"
1247	/ 3380 / "AND_F_R\000"
1248	/ 3388 / "SHL_F_R\000"
1249	/ 3396 / "SRL_F_R\000"
1250	/ 3404 / "XOR_F_R\000"
1251	/ 3412 / "SHL_R\000"
1252	/ 3418 / "SRL_R\000"
1253	/ 3424 / "XOR_R\000"
1254	/ 3430 / "G_FABS\000"
1255	/ 3437 / "G_ABS\000"
1256	/ 3443 / "G_ABDS\000"
1257	/ 3450 / "G_UNMERGE_VALUES\000"
1258	/ 3467 / "G_MERGE_VALUES\000"
1259	/ 3482 / "G_FACOS\000"
1260	/ 3490 / "G_FCOS\000"
1261	/ 3497 / "G_FSINCOS\000"
1262	/ 3507 / "G_CONCAT_VECTORS\000"
1263	/ 3524 / "COPY_TO_REGCLASS\000"
1264	/ 3541 / "G_IS_FPCLASS\000"
1265	/ 3554 / "G_ATOMIC_CMPXCHG_WITH_SUCCESS\000"
1266	/ 3584 / "G_VECTOR_COMPRESS\000"
1267	/ 3602 / "G_INTRINSIC_W_SIDE_EFFECTS\000"
1268	/ 3629 / "G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS\000"
1269	/ 3667 / "G_SSUBSAT\000"
1270	/ 3677 / "G_USUBSAT\000"
1271	/ 3687 / "G_SADDSAT\000"
1272	/ 3697 / "G_UADDSAT\000"
1273	/ 3707 / "G_SSHLSAT\000"
1274	/ 3717 / "G_USHLSAT\000"
1275	/ 3727 / "G_SMULFIXSAT\000"
1276	/ 3740 / "G_UMULFIXSAT\000"
1277	/ 3753 / "G_SDIVFIXSAT\000"
1278	/ 3766 / "G_UDIVFIXSAT\000"
1279	/ 3779 / "G_ATOMICRMW_USUB_SAT\000"
1280	/ 3800 / "G_FPTOSI_SAT\000"
1281	/ 3813 / "G_FPTOUI_SAT\000"
1282	/ 3826 / "BT\000"
1283	/ 3829 / "G_EXTRACT\000"
1284	/ 3839 / "G_SELECT\000"
1285	/ 3848 / "G_BRINDIRECT\000"
1286	/ 3861 / "PATCHABLE_RET\000"
1287	/ 3875 / "G_MEMSET\000"
1288	/ 3884 / "PATCHABLE_FUNCTION_EXIT\000"
1289	/ 3908 / "G_BRJT\000"
1290	/ 3915 / "G_EXTRACT_VECTOR_ELT\000"
1291	/ 3936 / "G_INSERT_VECTOR_ELT\000"
1292	/ 3956 / "G_FCONSTANT\000"
1293	/ 3968 / "G_CONSTANT\000"
1294	/ 3979 / "G_INTRINSIC_CONVERGENT\000"
1295	/ 4002 / "STATEPOINT\000"
1296	/ 4013 / "PATCHPOINT\000"
1297	/ 4024 / "G_PTRTOINT\000"
1298	/ 4035 / "G_FRINT\000"
1299	/ 4043 / "G_INTRINSIC_LLRINT\000"
1300	/ 4062 / "G_INTRINSIC_LRINT\000"
1301	/ 4080 / "G_FNEARBYINT\000"
1302	/ 4093 / "G_VASTART\000"
1303	/ 4103 / "LIFETIME_START\000"
1304	/ 4118 / "G_INVOKE_REGION_START\000"
1305	/ 4140 / "G_INSERT\000"
1306	/ 4149 / "G_FSQRT\000"
1307	/ 4157 / "G_STRICT_FSQRT\000"
1308	/ 4172 / "G_BITCAST\000"
1309	/ 4182 / "G_ADDRSPACE_CAST\000"
1310	/ 4199 / "DBG_VALUE_LIST\000"
1311	/ 4214 / "G_FPEXT\000"
1312	/ 4222 / "G_SEXT\000"
1313	/ 4229 / "G_ASSERT_SEXT\000"
1314	/ 4243 / "G_ANYEXT\000"
1315	/ 4252 / "G_ZEXT\000"
1316	/ 4259 / "G_ASSERT_ZEXT\000"
1317	/ 4273 / "G_ABDU\000"
1318	/ 4280 / "G_FDIV\000"
1319	/ 4287 / "G_STRICT_FDIV\000"
1320	/ 4301 / "G_SDIV\000"
1321	/ 4308 / "G_UDIV\000"
1322	/ 4315 / "G_GET_FPENV\000"
1323	/ 4327 / "G_RESET_FPENV\000"
1324	/ 4341 / "G_SET_FPENV\000"
1325	/ 4353 / "G_FPOW\000"
1326	/ 4360 / "G_VECREDUCE_FMAX\000"
1327	/ 4377 / "G_ATOMICRMW_FMAX\000"
1328	/ 4394 / "G_VECREDUCE_SMAX\000"
1329	/ 4411 / "G_SMAX\000"
1330	/ 4418 / "G_VECREDUCE_UMAX\000"
1331	/ 4435 / "G_UMAX\000"
1332	/ 4442 / "G_ATOMICRMW_UMAX\000"
1333	/ 4459 / "G_ATOMICRMW_MAX\000"
1334	/ 4475 / "G_FRAME_INDEX\000"
1335	/ 4489 / "G_SBFX\000"
1336	/ 4496 / "G_UBFX\000"
1337	/ 4503 / "G_SMULFIX\000"
1338	/ 4513 / "G_UMULFIX\000"
1339	/ 4523 / "G_SDIVFIX\000"
1340	/ 4533 / "G_UDIVFIX\000"
1341	/ 4543 / "G_MEMCPY\000"
1342	/ 4552 / "COPY\000"
1343	/ 4557 / "CONVERGENCECTRL_ENTRY\000"
1344	/ 4579 / "LEADZ\000"
1345	/ 4585 / "TRAILZ\000"
1346	/ 4592 / "G_CTLZ\000"
1347	/ 4599 / "G_CTTZ\000"
1348	};
1349	#ifdef __GNUC__
1350	#pragma GCC diagnostic pop
1351	#endif
1352
1353	extern const unsigned LanaiInstrNameIndices[] = {
1354	`1309U`, `1910U`, `2793U`, `2268U`, `1599U`, `1580U`, `1608U`, `1746U`,
1355	`1132U`, `1147U`, `1098U`, `1085U`, `1174U`, `3524U`, `933U`, `4199U`,
1356	`1111U`, `1305U`, `1589U`, `714U`, `4552U`, `836U`, `4103U`, `541U`,
1357	`665U`, `702U`, `2517U`, `1734U`, `4013U`, `648U`, `2728U`, `1237U`,
1358	`4002U`, `859U`, `2701U`, `2688U`, `2868U`, `3861U`, `3884U`, `1666U`,
1359	`1713U`, `1686U`, `1625U`, `924U`, `2833U`, `2333U`, `4557U`, `2995U`,
1360	`2659U`, `981U`, `4229U`, `4259U`, `2111U`, `454U`, `130U`, `1849U`,
1361	`4301U`, `4308U`, `1876U`, `1883U`, `1890U`, `1900U`, `519U`, `3180U`,
1362	`3143U`, `3443U`, `4273U`, `1096U`, `1307U`, `4475U`, `943U`, `958U`,
1363	`1751U`, `3829U`, `3450U`, `4140U`, `3467U`, `3066U`, `218U`, `3507U`,
1364	`4024U`, `3289U`, `4172U`, `1024U`, `2844U`, `622U`, `192U`, `604U`,
1365	`4062U`, `4043U`, `2089U`, `2893U`, `2912U`, `355U`, `299U`, `329U`,
1366	`340U`, `280U`, `310U`, `903U`, `887U`, `3554U`, `1188U`, `1205U`,
1367	`470U`, `136U`, `525U`, `486U`, `3185U`, `3149U`, `4459U`, `2237U`,
1368	`4442U`, `2220U`, `421U`, `113U`, `4377U`, `2155U`, `2005U`, `1952U`,
1369	`2579U`, `2557U`, `563U`, `3779U`, `694U`, `1254U`, `554U`, `3848U`,
1370	`4118U`, `170U`, `3602U`, `3979U`, `3629U`, `4243U`, `210U`, `3968U`,
1371	`3956U`, `4093U`, `1229U`, `4222U`, `1161U`, `4252U`, `1652U`, `2979U`,
1372	`2965U`, `1645U`, `2972U`, `3282U`, `1767U`, `2634U`, `2627U`, `2641U`,
1373	`2648U`, `3839U`, `2325U`, `735U`, `2309U`, `686U`, `2317U`, `727U`,
1374	`2301U`, `678U`, `2363U`, `2355U`, `1273U`, `1265U`, `3697U`, `3687U`,
1375	`3677U`, `3667U`, `3717U`, `3707U`, `4503U`, `4513U`, `3727U`, `3740U`,
1376	`4523U`, `4533U`, `3753U`, `3766U`, `379U`, `92U`, `1791U`, `73U`,
1377	`273U`, `4280U`, `1855U`, `4353U`, `1538U`, `2772U`, `45U`, `9U`,
1378	`1222U`, `28U`, `0U`, `2747U`, `2779U`, `1125U`, `4214U`, `182U`,
1379	`1520U`, `1529U`, `2609U`, `2618U`, `3800U`, `3813U`, `3430U`, `2126U`,
1380	`3541U`, `1033U`, `2054U`, `2064U`, `784U`, `799U`, `1941U`, `1994U`,
1381	`2026U`, `2040U`, `4315U`, `4341U`, `4327U`, `743U`, `771U`, `756U`,
1382	`460U`, `1570U`, `2189U`, `4411U`, `2213U`, `4435U`, `3437U`, `595U`,
1383	`585U`, `2788U`, `3908U`, `814U`, `3047U`, `3027U`, `3936U`, `3915U`,
1384	`3081U`, `3112U`, `3098U`, `3584U`, `4599U`, `1067U`, `4592U`, `1049U`,
1385	`2680U`, `2601U`, `911U`, `1658U`, `3490U`, `2261U`, `3497U`, `2082U`,
1386	`3482U`, `2253U`, `2074U`, `36U`, `1297U`, `1289U`, `1281U`, `4149U`,
1387	`3018U`, `4035U`, `4080U`, `4182U`, `2820U`, `823U`, `239U`, `1002U`,
1388	`872U`, `407U`, `99U`, `1819U`, `4287U`, `1862U`, `79U`, `4157U`,
1389	`2756U`, `2932U`, `2948U`, `4543U`, `843U`, `1014U`, `3875U`, `2509U`,
1390	`2550U`, `2526U`, `2538U`, `386U`, `1798U`, `362U`, `1774U`, `4360U`,
1391	`2138U`, `1973U`, `1920U`, `438U`, `1833U`, `503U`, `3165U`, `3127U`,
1392	`4394U`, `2172U`, `4418U`, `2196U`, `4489U`, `4496U`, `2284U`, `2713U`,
1393	`256U`, `1681U`, `2989U`, `1403U`, `2455U`, `3363U`, `1352U`, `2404U`,
1394	`3319U`, `1415U`, `2467U`, `3372U`, `1362U`, `2414U`, `3326U`, `1426U`,
1395	`2478U`, `3380U`, `1371U`, `2423U`, `3332U`, `152U`, `161U`, `63U`,
1396	`3200U`, `3826U`, `2986U`, `2806U`, `1488U`, `3242U`, `1504U`, `3258U`,
1397	`1496U`, `3250U`, `1512U`, `3266U`, `1475U`, `3229U`, `3274U`, `4579U`,
1398	`18U`, `23U`, `31U`, `53U`, `58U`, `1313U`, `2655U`, `1438U`,
1399	`2490U`, `3405U`, `1449U`, `2501U`, `3425U`, `268U`, `3871U`, `1551U`,
1400	`1546U`, `157U`, `3841U`, `1319U`, `2371U`, `3211U`, `3388U`, `3412U`,
1401	`1457U`, `1558U`, `1565U`, `3338U`, `3300U`, `3396U`, `3418U`, `2813U`,
1402	`1461U`, `3204U`, `1468U`, `3222U`, `1380U`, `2432U`, `3346U`, `1333U`,
1403	`2385U`, `3306U`, `1392U`, `2444U`, `3355U`, `1343U`, `2395U`, `3313U`,
1404	`1482U`, `3236U`, `4585U`, `1437U`, `2489U`, `3404U`, `1448U`, `2500U`,
1405	`3424U`,
1406	};
1407
1408	static inline void InitLanaiMCInstrInfo(MCInstrInfo *II) {
1409	II->InitMCInstrInfo(LanaiDescs.Insts, LanaiInstrNameIndices, LanaiInstrNameData, nullptr, nullptr, `409`);
1410	}
1411
1412	} // end namespace llvm
1413	#endif // GET_INSTRINFO_MC_DESC
1414
1415	#ifdef GET_INSTRINFO_HEADER
1416	#undef GET_INSTRINFO_HEADER
1417	namespace llvm {
1418	struct LanaiGenInstrInfo : public TargetInstrInfo {
1419	explicit LanaiGenInstrInfo(unsigned CFSetupOpcode = ~`0u`, unsigned CFDestroyOpcode = ~`0u`, unsigned CatchRetOpcode = ~`0u`, unsigned ReturnOpcode = ~`0u`);
1420	~LanaiGenInstrInfo() override = default;
1421
1422	};
1423	} // end namespace llvm
1424	#endif // GET_INSTRINFO_HEADER
1425
1426	#ifdef GET_INSTRINFO_HELPER_DECLS
1427	#undef GET_INSTRINFO_HELPER_DECLS
1428
1429
1430	#endif // GET_INSTRINFO_HELPER_DECLS
1431
1432	#ifdef GET_INSTRINFO_HELPERS
1433	#undef GET_INSTRINFO_HELPERS
1434
1435	#endif // GET_INSTRINFO_HELPERS
1436
1437	#ifdef GET_INSTRINFO_CTOR_DTOR
1438	#undef GET_INSTRINFO_CTOR_DTOR
1439	namespace llvm {
1440	extern const LanaiInstrTable LanaiDescs;
1441	extern const unsigned LanaiInstrNameIndices[];
1442	extern const char LanaiInstrNameData[];
1443	LanaiGenInstrInfo::LanaiGenInstrInfo(unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode)
1444	: TargetInstrInfo(CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {
1445	InitMCInstrInfo(LanaiDescs.Insts, LanaiInstrNameIndices, LanaiInstrNameData, nullptr, nullptr, `409`);
1446	}
1447	} // end namespace llvm
1448	#endif // GET_INSTRINFO_CTOR_DTOR
1449
1450	#ifdef GET_INSTRINFO_MC_HELPER_DECLS
1451	#undef GET_INSTRINFO_MC_HELPER_DECLS
1452
1453	namespace llvm {
1454	class MCInst;
1455	class FeatureBitset;
1456
1457	namespace Lanai_MC {
1458
1459	void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features);
1460
1461	} // end namespace Lanai_MC
1462	} // end namespace llvm
1463
1464	#endif // GET_INSTRINFO_MC_HELPER_DECLS
1465
1466	#ifdef GET_INSTRINFO_MC_HELPERS
1467	#undef GET_INSTRINFO_MC_HELPERS
1468
1469	namespace llvm::Lanai_MC {
1470	} // end namespace llvm::Lanai_MC
1471	#endif // GET_GENISTRINFO_MC_HELPERS
1472
1473	#if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) \|\|\
1474	defined(GET_AVAILABLE_OPCODE_CHECKER)
1475	#define GET_COMPUTE_FEATURES
1476	#endif
1477	#ifdef GET_COMPUTE_FEATURES
1478	#undef GET_COMPUTE_FEATURES
1479	namespace llvm::Lanai_MC {
1480	// Bits for subtarget features that participate in instruction matching.
1481	enum SubtargetFeatureBits : uint8_t {
1482	};
1483
1484	inline FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) {
1485	FeatureBitset Features;
1486	return Features;
1487	}
1488
1489	inline FeatureBitset computeRequiredFeatures(unsigned Opcode) {
1490	enum : uint8_t {
1491	CEFBS_None,
1492	};
1493
1494	static constexpr FeatureBitset FeatureBitsets[] = {
1495	{}, // CEFBS_None
1496	};
1497	static constexpr uint8_t RequiredFeaturesRefs[] = {
1498	CEFBS_None, // PHI = 0
1499	CEFBS_None, // INLINEASM = 1
1500	CEFBS_None, // INLINEASM_BR = 2
1501	CEFBS_None, // CFI_INSTRUCTION = 3
1502	CEFBS_None, // EH_LABEL = 4
1503	CEFBS_None, // GC_LABEL = 5
1504	CEFBS_None, // ANNOTATION_LABEL = 6
1505	CEFBS_None, // KILL = 7
1506	CEFBS_None, // EXTRACT_SUBREG = 8
1507	CEFBS_None, // INSERT_SUBREG = 9
1508	CEFBS_None, // IMPLICIT_DEF = 10
1509	CEFBS_None, // INIT_UNDEF = 11
1510	CEFBS_None, // SUBREG_TO_REG = 12
1511	CEFBS_None, // COPY_TO_REGCLASS = 13
1512	CEFBS_None, // DBG_VALUE = 14
1513	CEFBS_None, // DBG_VALUE_LIST = 15
1514	CEFBS_None, // DBG_INSTR_REF = 16
1515	CEFBS_None, // DBG_PHI = 17
1516	CEFBS_None, // DBG_LABEL = 18
1517	CEFBS_None, // REG_SEQUENCE = 19
1518	CEFBS_None, // COPY = 20
1519	CEFBS_None, // BUNDLE = 21
1520	CEFBS_None, // LIFETIME_START = 22
1521	CEFBS_None, // LIFETIME_END = 23
1522	CEFBS_None, // PSEUDO_PROBE = 24
1523	CEFBS_None, // ARITH_FENCE = 25
1524	CEFBS_None, // STACKMAP = 26
1525	CEFBS_None, // FENTRY_CALL = 27
1526	CEFBS_None, // PATCHPOINT = 28
1527	CEFBS_None, // LOAD_STACK_GUARD = 29
1528	CEFBS_None, // PREALLOCATED_SETUP = 30
1529	CEFBS_None, // PREALLOCATED_ARG = 31
1530	CEFBS_None, // STATEPOINT = 32
1531	CEFBS_None, // LOCAL_ESCAPE = 33
1532	CEFBS_None, // FAULTING_OP = 34
1533	CEFBS_None, // PATCHABLE_OP = 35
1534	CEFBS_None, // PATCHABLE_FUNCTION_ENTER = 36
1535	CEFBS_None, // PATCHABLE_RET = 37
1536	CEFBS_None, // PATCHABLE_FUNCTION_EXIT = 38
1537	CEFBS_None, // PATCHABLE_TAIL_CALL = 39
1538	CEFBS_None, // PATCHABLE_EVENT_CALL = 40
1539	CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL = 41
1540	CEFBS_None, // ICALL_BRANCH_FUNNEL = 42
1541	CEFBS_None, // FAKE_USE = 43
1542	CEFBS_None, // MEMBARRIER = 44
1543	CEFBS_None, // JUMP_TABLE_DEBUG_INFO = 45
1544	CEFBS_None, // CONVERGENCECTRL_ENTRY = 46
1545	CEFBS_None, // CONVERGENCECTRL_ANCHOR = 47
1546	CEFBS_None, // CONVERGENCECTRL_LOOP = 48
1547	CEFBS_None, // CONVERGENCECTRL_GLUE = 49
1548	CEFBS_None, // G_ASSERT_SEXT = 50
1549	CEFBS_None, // G_ASSERT_ZEXT = 51
1550	CEFBS_None, // G_ASSERT_ALIGN = 52
1551	CEFBS_None, // G_ADD = 53
1552	CEFBS_None, // G_SUB = 54
1553	CEFBS_None, // G_MUL = 55
1554	CEFBS_None, // G_SDIV = 56
1555	CEFBS_None, // G_UDIV = 57
1556	CEFBS_None, // G_SREM = 58
1557	CEFBS_None, // G_UREM = 59
1558	CEFBS_None, // G_SDIVREM = 60
1559	CEFBS_None, // G_UDIVREM = 61
1560	CEFBS_None, // G_AND = 62
1561	CEFBS_None, // G_OR = 63
1562	CEFBS_None, // G_XOR = 64
1563	CEFBS_None, // G_ABDS = 65
1564	CEFBS_None, // G_ABDU = 66
1565	CEFBS_None, // G_IMPLICIT_DEF = 67
1566	CEFBS_None, // G_PHI = 68
1567	CEFBS_None, // G_FRAME_INDEX = 69
1568	CEFBS_None, // G_GLOBAL_VALUE = 70
1569	CEFBS_None, // G_PTRAUTH_GLOBAL_VALUE = 71
1570	CEFBS_None, // G_CONSTANT_POOL = 72
1571	CEFBS_None, // G_EXTRACT = 73
1572	CEFBS_None, // G_UNMERGE_VALUES = 74
1573	CEFBS_None, // G_INSERT = 75
1574	CEFBS_None, // G_MERGE_VALUES = 76
1575	CEFBS_None, // G_BUILD_VECTOR = 77
1576	CEFBS_None, // G_BUILD_VECTOR_TRUNC = 78
1577	CEFBS_None, // G_CONCAT_VECTORS = 79
1578	CEFBS_None, // G_PTRTOINT = 80
1579	CEFBS_None, // G_INTTOPTR = 81
1580	CEFBS_None, // G_BITCAST = 82
1581	CEFBS_None, // G_FREEZE = 83
1582	CEFBS_None, // G_CONSTANT_FOLD_BARRIER = 84
1583	CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND = 85
1584	CEFBS_None, // G_INTRINSIC_TRUNC = 86
1585	CEFBS_None, // G_INTRINSIC_ROUND = 87
1586	CEFBS_None, // G_INTRINSIC_LRINT = 88
1587	CEFBS_None, // G_INTRINSIC_LLRINT = 89
1588	CEFBS_None, // G_INTRINSIC_ROUNDEVEN = 90
1589	CEFBS_None, // G_READCYCLECOUNTER = 91
1590	CEFBS_None, // G_READSTEADYCOUNTER = 92
1591	CEFBS_None, // G_LOAD = 93
1592	CEFBS_None, // G_SEXTLOAD = 94
1593	CEFBS_None, // G_ZEXTLOAD = 95
1594	CEFBS_None, // G_INDEXED_LOAD = 96
1595	CEFBS_None, // G_INDEXED_SEXTLOAD = 97
1596	CEFBS_None, // G_INDEXED_ZEXTLOAD = 98
1597	CEFBS_None, // G_STORE = 99
1598	CEFBS_None, // G_INDEXED_STORE = 100
1599	CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS = 101
1600	CEFBS_None, // G_ATOMIC_CMPXCHG = 102
1601	CEFBS_None, // G_ATOMICRMW_XCHG = 103
1602	CEFBS_None, // G_ATOMICRMW_ADD = 104
1603	CEFBS_None, // G_ATOMICRMW_SUB = 105
1604	CEFBS_None, // G_ATOMICRMW_AND = 106
1605	CEFBS_None, // G_ATOMICRMW_NAND = 107
1606	CEFBS_None, // G_ATOMICRMW_OR = 108
1607	CEFBS_None, // G_ATOMICRMW_XOR = 109
1608	CEFBS_None, // G_ATOMICRMW_MAX = 110
1609	CEFBS_None, // G_ATOMICRMW_MIN = 111
1610	CEFBS_None, // G_ATOMICRMW_UMAX = 112
1611	CEFBS_None, // G_ATOMICRMW_UMIN = 113
1612	CEFBS_None, // G_ATOMICRMW_FADD = 114
1613	CEFBS_None, // G_ATOMICRMW_FSUB = 115
1614	CEFBS_None, // G_ATOMICRMW_FMAX = 116
1615	CEFBS_None, // G_ATOMICRMW_FMIN = 117
1616	CEFBS_None, // G_ATOMICRMW_FMAXIMUM = 118
1617	CEFBS_None, // G_ATOMICRMW_FMINIMUM = 119
1618	CEFBS_None, // G_ATOMICRMW_UINC_WRAP = 120
1619	CEFBS_None, // G_ATOMICRMW_UDEC_WRAP = 121
1620	CEFBS_None, // G_ATOMICRMW_USUB_COND = 122
1621	CEFBS_None, // G_ATOMICRMW_USUB_SAT = 123
1622	CEFBS_None, // G_FENCE = 124
1623	CEFBS_None, // G_PREFETCH = 125
1624	CEFBS_None, // G_BRCOND = 126
1625	CEFBS_None, // G_BRINDIRECT = 127
1626	CEFBS_None, // G_INVOKE_REGION_START = 128
1627	CEFBS_None, // G_INTRINSIC = 129
1628	CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS = 130
1629	CEFBS_None, // G_INTRINSIC_CONVERGENT = 131
1630	CEFBS_None, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 132
1631	CEFBS_None, // G_ANYEXT = 133
1632	CEFBS_None, // G_TRUNC = 134
1633	CEFBS_None, // G_CONSTANT = 135
1634	CEFBS_None, // G_FCONSTANT = 136
1635	CEFBS_None, // G_VASTART = 137
1636	CEFBS_None, // G_VAARG = 138
1637	CEFBS_None, // G_SEXT = 139
1638	CEFBS_None, // G_SEXT_INREG = 140
1639	CEFBS_None, // G_ZEXT = 141
1640	CEFBS_None, // G_SHL = 142
1641	CEFBS_None, // G_LSHR = 143
1642	CEFBS_None, // G_ASHR = 144
1643	CEFBS_None, // G_FSHL = 145
1644	CEFBS_None, // G_FSHR = 146
1645	CEFBS_None, // G_ROTR = 147
1646	CEFBS_None, // G_ROTL = 148
1647	CEFBS_None, // G_ICMP = 149
1648	CEFBS_None, // G_FCMP = 150
1649	CEFBS_None, // G_SCMP = 151
1650	CEFBS_None, // G_UCMP = 152
1651	CEFBS_None, // G_SELECT = 153
1652	CEFBS_None, // G_UADDO = 154
1653	CEFBS_None, // G_UADDE = 155
1654	CEFBS_None, // G_USUBO = 156
1655	CEFBS_None, // G_USUBE = 157
1656	CEFBS_None, // G_SADDO = 158
1657	CEFBS_None, // G_SADDE = 159
1658	CEFBS_None, // G_SSUBO = 160
1659	CEFBS_None, // G_SSUBE = 161
1660	CEFBS_None, // G_UMULO = 162
1661	CEFBS_None, // G_SMULO = 163
1662	CEFBS_None, // G_UMULH = 164
1663	CEFBS_None, // G_SMULH = 165
1664	CEFBS_None, // G_UADDSAT = 166
1665	CEFBS_None, // G_SADDSAT = 167
1666	CEFBS_None, // G_USUBSAT = 168
1667	CEFBS_None, // G_SSUBSAT = 169
1668	CEFBS_None, // G_USHLSAT = 170
1669	CEFBS_None, // G_SSHLSAT = 171
1670	CEFBS_None, // G_SMULFIX = 172
1671	CEFBS_None, // G_UMULFIX = 173
1672	CEFBS_None, // G_SMULFIXSAT = 174
1673	CEFBS_None, // G_UMULFIXSAT = 175
1674	CEFBS_None, // G_SDIVFIX = 176
1675	CEFBS_None, // G_UDIVFIX = 177
1676	CEFBS_None, // G_SDIVFIXSAT = 178
1677	CEFBS_None, // G_UDIVFIXSAT = 179
1678	CEFBS_None, // G_FADD = 180
1679	CEFBS_None, // G_FSUB = 181
1680	CEFBS_None, // G_FMUL = 182
1681	CEFBS_None, // G_FMA = 183
1682	CEFBS_None, // G_FMAD = 184
1683	CEFBS_None, // G_FDIV = 185
1684	CEFBS_None, // G_FREM = 186
1685	CEFBS_None, // G_FPOW = 187
1686	CEFBS_None, // G_FPOWI = 188
1687	CEFBS_None, // G_FEXP = 189
1688	CEFBS_None, // G_FEXP2 = 190
1689	CEFBS_None, // G_FEXP10 = 191
1690	CEFBS_None, // G_FLOG = 192
1691	CEFBS_None, // G_FLOG2 = 193
1692	CEFBS_None, // G_FLOG10 = 194
1693	CEFBS_None, // G_FLDEXP = 195
1694	CEFBS_None, // G_FFREXP = 196
1695	CEFBS_None, // G_FNEG = 197
1696	CEFBS_None, // G_FPEXT = 198
1697	CEFBS_None, // G_FPTRUNC = 199
1698	CEFBS_None, // G_FPTOSI = 200
1699	CEFBS_None, // G_FPTOUI = 201
1700	CEFBS_None, // G_SITOFP = 202
1701	CEFBS_None, // G_UITOFP = 203
1702	CEFBS_None, // G_FPTOSI_SAT = 204
1703	CEFBS_None, // G_FPTOUI_SAT = 205
1704	CEFBS_None, // G_FABS = 206
1705	CEFBS_None, // G_FCOPYSIGN = 207
1706	CEFBS_None, // G_IS_FPCLASS = 208
1707	CEFBS_None, // G_FCANONICALIZE = 209
1708	CEFBS_None, // G_FMINNUM = 210
1709	CEFBS_None, // G_FMAXNUM = 211
1710	CEFBS_None, // G_FMINNUM_IEEE = 212
1711	CEFBS_None, // G_FMAXNUM_IEEE = 213
1712	CEFBS_None, // G_FMINIMUM = 214
1713	CEFBS_None, // G_FMAXIMUM = 215
1714	CEFBS_None, // G_FMINIMUMNUM = 216
1715	CEFBS_None, // G_FMAXIMUMNUM = 217
1716	CEFBS_None, // G_GET_FPENV = 218
1717	CEFBS_None, // G_SET_FPENV = 219
1718	CEFBS_None, // G_RESET_FPENV = 220
1719	CEFBS_None, // G_GET_FPMODE = 221
1720	CEFBS_None, // G_SET_FPMODE = 222
1721	CEFBS_None, // G_RESET_FPMODE = 223
1722	CEFBS_None, // G_PTR_ADD = 224
1723	CEFBS_None, // G_PTRMASK = 225
1724	CEFBS_None, // G_SMIN = 226
1725	CEFBS_None, // G_SMAX = 227
1726	CEFBS_None, // G_UMIN = 228
1727	CEFBS_None, // G_UMAX = 229
1728	CEFBS_None, // G_ABS = 230
1729	CEFBS_None, // G_LROUND = 231
1730	CEFBS_None, // G_LLROUND = 232
1731	CEFBS_None, // G_BR = 233
1732	CEFBS_None, // G_BRJT = 234
1733	CEFBS_None, // G_VSCALE = 235
1734	CEFBS_None, // G_INSERT_SUBVECTOR = 236
1735	CEFBS_None, // G_EXTRACT_SUBVECTOR = 237
1736	CEFBS_None, // G_INSERT_VECTOR_ELT = 238
1737	CEFBS_None, // G_EXTRACT_VECTOR_ELT = 239
1738	CEFBS_None, // G_SHUFFLE_VECTOR = 240
1739	CEFBS_None, // G_SPLAT_VECTOR = 241
1740	CEFBS_None, // G_STEP_VECTOR = 242
1741	CEFBS_None, // G_VECTOR_COMPRESS = 243
1742	CEFBS_None, // G_CTTZ = 244
1743	CEFBS_None, // G_CTTZ_ZERO_UNDEF = 245
1744	CEFBS_None, // G_CTLZ = 246
1745	CEFBS_None, // G_CTLZ_ZERO_UNDEF = 247
1746	CEFBS_None, // G_CTPOP = 248
1747	CEFBS_None, // G_BSWAP = 249
1748	CEFBS_None, // G_BITREVERSE = 250
1749	CEFBS_None, // G_FCEIL = 251
1750	CEFBS_None, // G_FCOS = 252
1751	CEFBS_None, // G_FSIN = 253
1752	CEFBS_None, // G_FSINCOS = 254
1753	CEFBS_None, // G_FTAN = 255
1754	CEFBS_None, // G_FACOS = 256
1755	CEFBS_None, // G_FASIN = 257
1756	CEFBS_None, // G_FATAN = 258
1757	CEFBS_None, // G_FATAN2 = 259
1758	CEFBS_None, // G_FCOSH = 260
1759	CEFBS_None, // G_FSINH = 261
1760	CEFBS_None, // G_FTANH = 262
1761	CEFBS_None, // G_FSQRT = 263
1762	CEFBS_None, // G_FFLOOR = 264
1763	CEFBS_None, // G_FRINT = 265
1764	CEFBS_None, // G_FNEARBYINT = 266
1765	CEFBS_None, // G_ADDRSPACE_CAST = 267
1766	CEFBS_None, // G_BLOCK_ADDR = 268
1767	CEFBS_None, // G_JUMP_TABLE = 269
1768	CEFBS_None, // G_DYN_STACKALLOC = 270
1769	CEFBS_None, // G_STACKSAVE = 271
1770	CEFBS_None, // G_STACKRESTORE = 272
1771	CEFBS_None, // G_STRICT_FADD = 273
1772	CEFBS_None, // G_STRICT_FSUB = 274
1773	CEFBS_None, // G_STRICT_FMUL = 275
1774	CEFBS_None, // G_STRICT_FDIV = 276
1775	CEFBS_None, // G_STRICT_FREM = 277
1776	CEFBS_None, // G_STRICT_FMA = 278
1777	CEFBS_None, // G_STRICT_FSQRT = 279
1778	CEFBS_None, // G_STRICT_FLDEXP = 280
1779	CEFBS_None, // G_READ_REGISTER = 281
1780	CEFBS_None, // G_WRITE_REGISTER = 282
1781	CEFBS_None, // G_MEMCPY = 283
1782	CEFBS_None, // G_MEMCPY_INLINE = 284
1783	CEFBS_None, // G_MEMMOVE = 285
1784	CEFBS_None, // G_MEMSET = 286
1785	CEFBS_None, // G_BZERO = 287
1786	CEFBS_None, // G_TRAP = 288
1787	CEFBS_None, // G_DEBUGTRAP = 289
1788	CEFBS_None, // G_UBSANTRAP = 290
1789	CEFBS_None, // G_VECREDUCE_SEQ_FADD = 291
1790	CEFBS_None, // G_VECREDUCE_SEQ_FMUL = 292
1791	CEFBS_None, // G_VECREDUCE_FADD = 293
1792	CEFBS_None, // G_VECREDUCE_FMUL = 294
1793	CEFBS_None, // G_VECREDUCE_FMAX = 295
1794	CEFBS_None, // G_VECREDUCE_FMIN = 296
1795	CEFBS_None, // G_VECREDUCE_FMAXIMUM = 297
1796	CEFBS_None, // G_VECREDUCE_FMINIMUM = 298
1797	CEFBS_None, // G_VECREDUCE_ADD = 299
1798	CEFBS_None, // G_VECREDUCE_MUL = 300
1799	CEFBS_None, // G_VECREDUCE_AND = 301
1800	CEFBS_None, // G_VECREDUCE_OR = 302
1801	CEFBS_None, // G_VECREDUCE_XOR = 303
1802	CEFBS_None, // G_VECREDUCE_SMAX = 304
1803	CEFBS_None, // G_VECREDUCE_SMIN = 305
1804	CEFBS_None, // G_VECREDUCE_UMAX = 306
1805	CEFBS_None, // G_VECREDUCE_UMIN = 307
1806	CEFBS_None, // G_SBFX = 308
1807	CEFBS_None, // G_UBFX = 309
1808	CEFBS_None, // ADJCALLSTACKDOWN = 310
1809	CEFBS_None, // ADJCALLSTACKUP = 311
1810	CEFBS_None, // ADJDYNALLOC = 312
1811	CEFBS_None, // CALL = 313
1812	CEFBS_None, // CALLR = 314
1813	CEFBS_None, // ADDC_F_I_HI = 315
1814	CEFBS_None, // ADDC_F_I_LO = 316
1815	CEFBS_None, // ADDC_F_R = 317
1816	CEFBS_None, // ADDC_I_HI = 318
1817	CEFBS_None, // ADDC_I_LO = 319
1818	CEFBS_None, // ADDC_R = 320
1819	CEFBS_None, // ADD_F_I_HI = 321
1820	CEFBS_None, // ADD_F_I_LO = 322
1821	CEFBS_None, // ADD_F_R = 323
1822	CEFBS_None, // ADD_I_HI = 324
1823	CEFBS_None, // ADD_I_LO = 325
1824	CEFBS_None, // ADD_R = 326
1825	CEFBS_None, // AND_F_I_HI = 327
1826	CEFBS_None, // AND_F_I_LO = 328
1827	CEFBS_None, // AND_F_R = 329
1828	CEFBS_None, // AND_I_HI = 330
1829	CEFBS_None, // AND_I_LO = 331
1830	CEFBS_None, // AND_R = 332
1831	CEFBS_None, // BRCC = 333
1832	CEFBS_None, // BRIND_CC = 334
1833	CEFBS_None, // BRIND_CCA = 335
1834	CEFBS_None, // BRR = 336
1835	CEFBS_None, // BT = 337
1836	CEFBS_None, // JR = 338
1837	CEFBS_None, // LDADDR = 339
1838	CEFBS_None, // LDBs_RI = 340
1839	CEFBS_None, // LDBs_RR = 341
1840	CEFBS_None, // LDBz_RI = 342
1841	CEFBS_None, // LDBz_RR = 343
1842	CEFBS_None, // LDHs_RI = 344
1843	CEFBS_None, // LDHs_RR = 345
1844	CEFBS_None, // LDHz_RI = 346
1845	CEFBS_None, // LDHz_RR = 347
1846	CEFBS_None, // LDW_RI = 348
1847	CEFBS_None, // LDW_RR = 349
1848	CEFBS_None, // LDWz_RR = 350
1849	CEFBS_None, // LEADZ = 351
1850	CEFBS_None, // LOG0 = 352
1851	CEFBS_None, // LOG1 = 353
1852	CEFBS_None, // LOG2 = 354
1853	CEFBS_None, // LOG3 = 355
1854	CEFBS_None, // LOG4 = 356
1855	CEFBS_None, // MOVHI = 357
1856	CEFBS_None, // NOP = 358
1857	CEFBS_None, // OR_F_I_HI = 359
1858	CEFBS_None, // OR_F_I_LO = 360
1859	CEFBS_None, // OR_F_R = 361
1860	CEFBS_None, // OR_I_HI = 362
1861	CEFBS_None, // OR_I_LO = 363
1862	CEFBS_None, // OR_R = 364
1863	CEFBS_None, // POPC = 365
1864	CEFBS_None, // RET = 366
1865	CEFBS_None, // SA_F_I = 367
1866	CEFBS_None, // SA_I = 368
1867	CEFBS_None, // SCC = 369
1868	CEFBS_None, // SELECT = 370
1869	CEFBS_None, // SFSUB_F_RI_HI = 371
1870	CEFBS_None, // SFSUB_F_RI_LO = 372
1871	CEFBS_None, // SFSUB_F_RR = 373
1872	CEFBS_None, // SHL_F_R = 374
1873	CEFBS_None, // SHL_R = 375
1874	CEFBS_None, // SLI = 376
1875	CEFBS_None, // SL_F_I = 377
1876	CEFBS_None, // SL_I = 378
1877	CEFBS_None, // SRA_F_R = 379
1878	CEFBS_None, // SRA_R = 380
1879	CEFBS_None, // SRL_F_R = 381
1880	CEFBS_None, // SRL_R = 382
1881	CEFBS_None, // STADDR = 383
1882	CEFBS_None, // STB_RI = 384
1883	CEFBS_None, // STB_RR = 385
1884	CEFBS_None, // STH_RI = 386
1885	CEFBS_None, // STH_RR = 387
1886	CEFBS_None, // SUBB_F_I_HI = 388
1887	CEFBS_None, // SUBB_F_I_LO = 389
1888	CEFBS_None, // SUBB_F_R = 390
1889	CEFBS_None, // SUBB_I_HI = 391
1890	CEFBS_None, // SUBB_I_LO = 392
1891	CEFBS_None, // SUBB_R = 393
1892	CEFBS_None, // SUB_F_I_HI = 394
1893	CEFBS_None, // SUB_F_I_LO = 395
1894	CEFBS_None, // SUB_F_R = 396
1895	CEFBS_None, // SUB_I_HI = 397
1896	CEFBS_None, // SUB_I_LO = 398
1897	CEFBS_None, // SUB_R = 399
1898	CEFBS_None, // SW_RI = 400
1899	CEFBS_None, // SW_RR = 401
1900	CEFBS_None, // TRAILZ = 402
1901	CEFBS_None, // XOR_F_I_HI = 403
1902	CEFBS_None, // XOR_F_I_LO = 404
1903	CEFBS_None, // XOR_F_R = 405
1904	CEFBS_None, // XOR_I_HI = 406
1905	CEFBS_None, // XOR_I_LO = 407
1906	CEFBS_None, // XOR_R = 408
1907	};
1908
1909	assert(Opcode < `409`);
1910	return FeatureBitsets[RequiredFeaturesRefs[Opcode]];
1911	}
1912
1913	} // end namespace llvm::Lanai_MC
1914	#endif // GET_COMPUTE_FEATURES
1915
1916	#ifdef GET_AVAILABLE_OPCODE_CHECKER
1917	#undef GET_AVAILABLE_OPCODE_CHECKER
1918	namespace llvm::Lanai_MC {
1919	bool isOpcodeAvailable(unsigned Opcode, const FeatureBitset &Features) {
1920	FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
1921	FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
1922	FeatureBitset MissingFeatures =
1923	(AvailableFeatures & RequiredFeatures) ^
1924	RequiredFeatures;
1925	return !MissingFeatures.any();
1926	}
1927	} // end namespace llvm::Lanai_MC
1928	#endif // GET_AVAILABLE_OPCODE_CHECKER
1929
1930	#ifdef ENABLE_INSTR_PREDICATE_VERIFIER
1931	#undef ENABLE_INSTR_PREDICATE_VERIFIER
1932	#include <sstream>
1933
1934	namespace llvm::Lanai_MC {
1935	#ifndef NDEBUG
1936	static const char *SubtargetFeatureNames[] = {
1937	nullptr
1938	};
1939
1940	#endif // NDEBUG
1941
1942	void verifyInstructionPredicates(
1943	unsigned Opcode, const FeatureBitset &Features) {
1944	#ifndef NDEBUG
1945	FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
1946	FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
1947	FeatureBitset MissingFeatures =
1948	(AvailableFeatures & RequiredFeatures) ^
1949	RequiredFeatures;
1950	if (MissingFeatures.any()) {
1951	std::ostringstream Msg;
1952	Msg << "Attempting to emit " << &LanaiInstrNameData[LanaiInstrNameIndices[Opcode]]
1953	<< " instruction but the ";
1954	for (unsigned i = `0`, e = MissingFeatures.size(); i != e; ++i)
1955	if (MissingFeatures.test(i))
1956	Msg << SubtargetFeatureNames[i] << " ";
1957	Msg << "predicate(s) are not met";
1958	report_fatal_error(Msg.str().c_str());
1959	}
1960	#endif // NDEBUG
1961	}
1962	} // end namespace llvm::Lanai_MC
1963	#endif // ENABLE_INSTR_PREDICATE_VERIFIER
1964
1965	#ifdef GET_INSTRMAP_INFO
1966	#undef GET_INSTRMAP_INFO
1967	namespace llvm::Lanai {
1968
1969	enum PostEncoderMethod {
1970	PostEncoderMethod_adjustPqBitsSpls
1971	};
1972
1973	// splsIdempotent
1974	LLVM_READONLY
1975	int splsIdempotent(uint16_t Opcode) {
1976	using namespace Lanai;
1977	static constexpr uint16_t Table[][`2`] = {
1978	{ LDBs_RI, LDBs_RI },
1979	{ LDBz_RI, LDBz_RI },
1980	{ LDHs_RI, LDHs_RI },
1981	{ LDHz_RI, LDHz_RI },
1982	{ STB_RI, STB_RI },
1983	{ STH_RI, STH_RI },
1984	}; // End of Table
1985
1986	unsigned mid;
1987	unsigned start = `0`;
1988	unsigned end = `6`;
1989	while (start < end) {
1990	mid = start + (end - start) / `2`;
1991	if (Opcode == Table[mid][`0`])
1992	break;
1993	if (Opcode < Table[mid][`0`])
1994	end = mid;
1995	else
1996	start = mid + `1`;
1997	}
1998	if (start == end)
1999	return -`1`; // Instruction doesn't exist in this table.
2000
2001	return Table[mid][`1`];
2002	}
2003
2004	} // end namespace llvm::Lanai
2005	#endif // GET_INSTRMAP_INFO
2006
2007

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