1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Subtarget Enumeration Source Fragment *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9
10#ifdef GET_SUBTARGETINFO_ENUM
11#undef GET_SUBTARGETINFO_ENUM
12
13namespace llvm {
14} // end namespace llvm
15
16#endif // GET_SUBTARGETINFO_ENUM
17
18
19#ifdef GET_SUBTARGETINFO_MACRO
20#undef GET_SUBTARGETINFO_MACRO
21#endif // GET_SUBTARGETINFO_MACRO
22
23
24#ifdef GET_SUBTARGETINFO_MC_DESC
25#undef GET_SUBTARGETINFO_MC_DESC
26
27namespace llvm {
28
29#ifdef DBGFIELD
30#error "<target>GenSubtargetInfo.inc requires a DBGFIELD macro"
31#endif
32#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
33#define DBGFIELD(x) x,
34#define DBGVAL_OR_NULLPTR(x) x
35#else
36#define DBGFIELD(x)
37#define DBGVAL_OR_NULLPTR(x) nullptr
38#endif
39
40// Functional units for "LanaiItinerary"
41namespace LanaiItineraryFU {
42 const InstrStage::FuncUnits ALU_FU = 1ULL << 0;
43 const InstrStage::FuncUnits LDST_FU = 1ULL << 1;
44} // end namespace LanaiItineraryFU
45
46extern const llvm::InstrStage LanaiStages[] = {
47 { 0, 0, 0, llvm::InstrStage::Required }, // No itinerary
48 { 1, LanaiItineraryFU::ALU_FU, -1, (llvm::InstrStage::ReservationKinds)0 }, // 1
49 { 1, LanaiItineraryFU::LDST_FU, -1, (llvm::InstrStage::ReservationKinds)0 }, // 2
50 { 2, LanaiItineraryFU::LDST_FU, -1, (llvm::InstrStage::ReservationKinds)0 }, // 3
51 { 0, 0, 0, llvm::InstrStage::Required } // End stages
52};
53extern const unsigned LanaiOperandCycles[] = {
54 0, // No itinerary
55 0 // End operand cycles
56};
57extern const unsigned LanaiForwardingPaths[] = {
58 0, // No itinerary
59 0 // End bypass tables
60};
61
62static constexpr llvm::InstrItinerary LanaiItinerary[] = {
63 { 0, 0, 0, 0, 0 }, // 0 NoInstrModel
64 { 1, 1, 2, 0, 0 }, // 1 IIC_ALU_WriteALU
65 { 1, 1, 2, 0, 0 }, // 2 IIC_ALU
66 { 1, 2, 3, 0, 0 }, // 3 IIC_LD_WriteLD
67 { 1, 3, 4, 0, 0 }, // 4 IIC_LDSW_WriteLDSW
68 { 0, 0, 0, 0, 0 }, // 5 WriteLD
69 { 1, 2, 3, 0, 0 }, // 6 IIC_ST_WriteST
70 { 1, 3, 4, 0, 0 }, // 7 IIC_STSW_WriteSTSW
71 { 0, uint16_t(~0U), uint16_t(~0U), uint16_t(~0U), uint16_t(~0U) }// end marker
72};
73
74// ===============================================================
75// Data tables for the new per-operand machine model.
76
77// {ProcResourceIdx, ReleaseAtCycle, AcquireAtCycle}
78extern const llvm::MCWriteProcResEntry LanaiWriteProcResTable[] = {
79 { 0, 0, 0 }, // Invalid
80 { 1, 1, 0}, // #1
81 { 2, 1, 0} // #2
82}; // LanaiWriteProcResTable
83
84// {Cycles, WriteResourceID}
85extern const llvm::MCWriteLatencyEntry LanaiWriteLatencyTable[] = {
86 { 0, 0}, // Invalid
87 { 1, 0}, // #1 WriteALU
88 { 2, 0}, // #2 WriteLD_WriteLDSW_WriteST
89 { 4, 0} // #3 WriteSTSW
90}; // LanaiWriteLatencyTable
91
92// {UseIdx, WriteResourceID, Cycles}
93extern const llvm::MCReadAdvanceEntry LanaiReadAdvanceTable[] = {
94 {0, 0, 0}, // Invalid
95}; // LanaiReadAdvanceTable
96
97// {Name, NumMicroOps, BeginGroup, EndGroup, RetireOOO, WriteProcResIdx,#, WriteLatencyIdx,#, ReadAdvanceIdx,#}
98static const llvm::MCSchedClassDesc LanaiSchedModelSchedClasses[] = {
99 {DBGFIELD(1) 8191, false, false, false, 0, 0, 0, 0, 0, 0},
100 {DBGFIELD(/*IIC_ALU_WriteALU*/ 19) 1, false, false, false, 1, 1, 1, 1, 0, 0}, // #1
101 {DBGFIELD(/*IIC_ALU*/ 36) 8191, false, false, false, 0, 0, 0, 0, 0, 0}, // #2
102 {DBGFIELD(/*IIC_LD_WriteLD*/ 44) 1, false, false, false, 2, 1, 2, 1, 0, 0}, // #3
103 {DBGFIELD(/*IIC_LDSW_WriteLDSW*/ 59) 1, false, false, false, 2, 1, 2, 1, 0, 0}, // #4
104 {DBGFIELD(/*WriteLD*/ 78) 1, false, false, false, 2, 1, 2, 1, 0, 0}, // #5
105 {DBGFIELD(/*IIC_ST_WriteST*/ 86) 1, false, false, false, 2, 1, 2, 1, 0, 0}, // #6
106 {DBGFIELD(/*IIC_STSW_WriteSTSW*/ 101) 1, false, false, false, 2, 1, 3, 1, 0, 0}, // #7
107}; // LanaiSchedModelSchedClasses
108
109#ifdef __GNUC__
110#pragma GCC diagnostic push
111#pragma GCC diagnostic ignored "-Woverlength-strings"
112#endif
113static constexpr char LanaiSchedClassNamesStorage[] =
114 "\0"
115 "InvalidSchedClass\0"
116 "IIC_ALU_WriteALU\0"
117 "IIC_ALU\0"
118 "IIC_LD_WriteLD\0"
119 "IIC_LDSW_WriteLDSW\0"
120 "WriteLD\0"
121 "IIC_ST_WriteST\0"
122 "IIC_STSW_WriteSTSW\0"
123 ;
124#ifdef __GNUC__
125#pragma GCC diagnostic pop
126#endif
127
128static constexpr llvm::StringTable LanaiSchedClassNames =
129 LanaiSchedClassNamesStorage;
130
131static const llvm::MCSchedModel NoSchedModel = {
132 MCSchedModel::DefaultIssueWidth,
133 MCSchedModel::DefaultMicroOpBufferSize,
134 MCSchedModel::DefaultLoopMicroOpBufferSize,
135 MCSchedModel::DefaultLoadLatency,
136 MCSchedModel::DefaultHighLatency,
137 MCSchedModel::DefaultMispredictPenalty,
138 false, // PostRAScheduler
139 false, // CompleteModel
140 false, // EnableIntervals
141 0, // Processor ID
142 nullptr, nullptr, 0, 0, // No instruction-level machine model.
143 DBGVAL_OR_NULLPTR(&LanaiSchedClassNames), // SchedClassNames
144 nullptr, // No Itinerary
145 nullptr // No extra processor descriptor
146};
147
148static const unsigned LanaiSchedModelProcResourceSubUnits[] = {
149 0, // Invalid
150};
151
152// {Name, NumUnits, SuperIdx, BufferSize, SubUnitsIdxBegin}
153static const llvm::MCProcResourceDesc LanaiSchedModelProcResources[] = {
154 {"InvalidUnit", 0, 0, 0, 0},
155 {"ALU", 1, 0, 0, nullptr}, // #1
156 {"LdSt", 1, 0, 0, nullptr}, // #2
157};
158
159static const llvm::MCSchedModel LanaiSchedModel = {
160 1, // IssueWidth
161 0, // MicroOpBufferSize
162 0, // LoopMicroOpBufferSize
163 2, // LoadLatency
164 MCSchedModel::DefaultHighLatency,
165 10, // MispredictPenalty
166 false, // PostRAScheduler
167 false, // CompleteModel
168 false, // EnableIntervals
169 1, // Processor ID
170 LanaiSchedModelProcResources,
171 LanaiSchedModelSchedClasses,
172 3,
173 8,
174 DBGVAL_OR_NULLPTR(&LanaiSchedClassNames), // SchedClassNames
175 LanaiItinerary,
176 nullptr // No extra processor descriptor
177};
178
179#undef DBGFIELD
180
181#undef DBGVAL_OR_NULLPTR
182
183// Sorted (by key) array of values for CPU subtype.
184extern const llvm::SubtargetSubTypeKV LanaiSubTypeKV[] = {
185 { "generic", { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &LanaiSchedModel },
186 { "v11", { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &LanaiSchedModel },
187};
188
189// Sorted array of names of CPU subtypes, including aliases.
190extern const llvm::StringRef LanaiNames[] = {
191"generic",
192"v11"};
193
194namespace Lanai_MC {
195unsigned resolveVariantSchedClassImpl(unsigned SchedClass,
196 const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) {
197 // Don't know how to resolve this scheduling class.
198 return 0;
199}
200} // end namespace Lanai_MC
201
202struct LanaiGenMCSubtargetInfo : public MCSubtargetInfo {
203 LanaiGenMCSubtargetInfo(const Triple &TT,
204 StringRef CPU, StringRef TuneCPU, StringRef FS,
205 ArrayRef<StringRef> PN,
206 ArrayRef<SubtargetFeatureKV> PF,
207 ArrayRef<SubtargetSubTypeKV> PD,
208 const MCWriteProcResEntry *WPR,
209 const MCWriteLatencyEntry *WL,
210 const MCReadAdvanceEntry *RA, const InstrStage *IS,
211 const unsigned *OC, const unsigned *FP) :
212 MCSubtargetInfo(TT, CPU, TuneCPU, FS, PN, PF, PD,
213 WPR, WL, RA, IS, OC, FP) { }
214
215 unsigned resolveVariantSchedClass(unsigned SchedClass,
216 const MCInst *MI, const MCInstrInfo *MCII,
217 unsigned CPUID) const override {
218 return Lanai_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, CPUID);
219 }
220};
221
222static inline MCSubtargetInfo *createLanaiMCSubtargetInfoImpl(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS) {
223 return new LanaiGenMCSubtargetInfo(TT, CPU, TuneCPU, FS, LanaiNames, {}, LanaiSubTypeKV,
224 LanaiWriteProcResTable, LanaiWriteLatencyTable, LanaiReadAdvanceTable,
225 LanaiStages, LanaiOperandCycles, LanaiForwardingPaths);
226}
227
228} // end namespace llvm
229
230#endif // GET_SUBTARGETINFO_MC_DESC
231
232
233#ifdef GET_SUBTARGETINFO_TARGET_DESC
234#undef GET_SUBTARGETINFO_TARGET_DESC
235
236#include "llvm/ADT/BitmaskEnum.h"
237#include "llvm/Support/Debug.h"
238#include "llvm/Support/raw_ostream.h"
239
240// ParseSubtargetFeatures - Parses features string setting specified
241// subtarget options.
242void llvm::LanaiSubtarget::ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS) {
243 LLVM_DEBUG(dbgs() << "\nFeatures:" << FS);
244 LLVM_DEBUG(dbgs() << "\nCPU:" << CPU);
245 LLVM_DEBUG(dbgs() << "\nTuneCPU:" << TuneCPU << "\n\n");
246}
247#endif // GET_SUBTARGETINFO_TARGET_DESC
248
249
250#ifdef GET_SUBTARGETINFO_HEADER
251#undef GET_SUBTARGETINFO_HEADER
252
253namespace llvm {
254class DFAPacketizer;
255namespace Lanai_MC {
256unsigned resolveVariantSchedClassImpl(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID);
257} // end namespace Lanai_MC
258
259struct LanaiGenSubtargetInfo : public TargetSubtargetInfo {
260 explicit LanaiGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS);
261public:
262 unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const override;
263 unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const override;
264 DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID) const;
265};
266} // end namespace llvm
267
268#endif // GET_SUBTARGETINFO_HEADER
269
270
271#ifdef GET_SUBTARGETINFO_CTOR
272#undef GET_SUBTARGETINFO_CTOR
273
274#include "llvm/CodeGen/TargetSchedule.h"
275
276namespace llvm {
277extern const llvm::StringRef LanaiNames[];
278extern const llvm::SubtargetFeatureKV LanaiFeatureKV[];
279extern const llvm::SubtargetSubTypeKV LanaiSubTypeKV[];
280extern const llvm::MCWriteProcResEntry LanaiWriteProcResTable[];
281extern const llvm::MCWriteLatencyEntry LanaiWriteLatencyTable[];
282extern const llvm::MCReadAdvanceEntry LanaiReadAdvanceTable[];
283extern const llvm::InstrStage LanaiStages[];
284extern const unsigned LanaiOperandCycles[];
285extern const unsigned LanaiForwardingPaths[];
286LanaiGenSubtargetInfo::LanaiGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS)
287 : TargetSubtargetInfo(TT, CPU, TuneCPU, FS, ArrayRef(LanaiNames, 2), {}, ArrayRef(LanaiSubTypeKV, 2),
288 LanaiWriteProcResTable, LanaiWriteLatencyTable, LanaiReadAdvanceTable,
289 LanaiStages, LanaiOperandCycles, LanaiForwardingPaths) {}
290
291unsigned LanaiGenSubtargetInfo
292::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {
293 report_fatal_error("Expected a variant SchedClass");
294} // LanaiGenSubtargetInfo::resolveSchedClass
295
296unsigned LanaiGenSubtargetInfo
297::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const {
298 return Lanai_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, CPUID);
299} // LanaiGenSubtargetInfo::resolveVariantSchedClass
300
301} // end namespace llvm
302
303#endif // GET_SUBTARGETINFO_CTOR
304
305
306#ifdef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
307#undef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
308
309#endif // GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
310
311
312#ifdef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
313#undef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
314
315#endif // GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
316
317