1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Instruction Enum Values and Descriptors *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_INSTRINFO_ENUM
10#undef GET_INSTRINFO_ENUM
11namespace llvm::LoongArch {
12 enum {
13 PHI = 0,
14 INLINEASM = 1,
15 INLINEASM_BR = 2,
16 CFI_INSTRUCTION = 3,
17 EH_LABEL = 4,
18 GC_LABEL = 5,
19 ANNOTATION_LABEL = 6,
20 KILL = 7,
21 EXTRACT_SUBREG = 8,
22 INSERT_SUBREG = 9,
23 IMPLICIT_DEF = 10,
24 INIT_UNDEF = 11,
25 SUBREG_TO_REG = 12,
26 COPY_TO_REGCLASS = 13,
27 DBG_VALUE = 14,
28 DBG_VALUE_LIST = 15,
29 DBG_INSTR_REF = 16,
30 DBG_PHI = 17,
31 DBG_LABEL = 18,
32 REG_SEQUENCE = 19,
33 COPY = 20,
34 BUNDLE = 21,
35 LIFETIME_START = 22,
36 LIFETIME_END = 23,
37 PSEUDO_PROBE = 24,
38 ARITH_FENCE = 25,
39 STACKMAP = 26,
40 FENTRY_CALL = 27,
41 PATCHPOINT = 28,
42 LOAD_STACK_GUARD = 29,
43 PREALLOCATED_SETUP = 30,
44 PREALLOCATED_ARG = 31,
45 STATEPOINT = 32,
46 LOCAL_ESCAPE = 33,
47 FAULTING_OP = 34,
48 PATCHABLE_OP = 35,
49 PATCHABLE_FUNCTION_ENTER = 36,
50 PATCHABLE_RET = 37,
51 PATCHABLE_FUNCTION_EXIT = 38,
52 PATCHABLE_TAIL_CALL = 39,
53 PATCHABLE_EVENT_CALL = 40,
54 PATCHABLE_TYPED_EVENT_CALL = 41,
55 ICALL_BRANCH_FUNNEL = 42,
56 FAKE_USE = 43,
57 MEMBARRIER = 44,
58 JUMP_TABLE_DEBUG_INFO = 45,
59 CONVERGENCECTRL_ENTRY = 46,
60 CONVERGENCECTRL_ANCHOR = 47,
61 CONVERGENCECTRL_LOOP = 48,
62 CONVERGENCECTRL_GLUE = 49,
63 G_ASSERT_SEXT = 50,
64 G_ASSERT_ZEXT = 51,
65 G_ASSERT_ALIGN = 52,
66 G_ADD = 53,
67 G_SUB = 54,
68 G_MUL = 55,
69 G_SDIV = 56,
70 G_UDIV = 57,
71 G_SREM = 58,
72 G_UREM = 59,
73 G_SDIVREM = 60,
74 G_UDIVREM = 61,
75 G_AND = 62,
76 G_OR = 63,
77 G_XOR = 64,
78 G_ABDS = 65,
79 G_ABDU = 66,
80 G_IMPLICIT_DEF = 67,
81 G_PHI = 68,
82 G_FRAME_INDEX = 69,
83 G_GLOBAL_VALUE = 70,
84 G_PTRAUTH_GLOBAL_VALUE = 71,
85 G_CONSTANT_POOL = 72,
86 G_EXTRACT = 73,
87 G_UNMERGE_VALUES = 74,
88 G_INSERT = 75,
89 G_MERGE_VALUES = 76,
90 G_BUILD_VECTOR = 77,
91 G_BUILD_VECTOR_TRUNC = 78,
92 G_CONCAT_VECTORS = 79,
93 G_PTRTOINT = 80,
94 G_INTTOPTR = 81,
95 G_BITCAST = 82,
96 G_FREEZE = 83,
97 G_CONSTANT_FOLD_BARRIER = 84,
98 G_INTRINSIC_FPTRUNC_ROUND = 85,
99 G_INTRINSIC_TRUNC = 86,
100 G_INTRINSIC_ROUND = 87,
101 G_INTRINSIC_LRINT = 88,
102 G_INTRINSIC_LLRINT = 89,
103 G_INTRINSIC_ROUNDEVEN = 90,
104 G_READCYCLECOUNTER = 91,
105 G_READSTEADYCOUNTER = 92,
106 G_LOAD = 93,
107 G_SEXTLOAD = 94,
108 G_ZEXTLOAD = 95,
109 G_INDEXED_LOAD = 96,
110 G_INDEXED_SEXTLOAD = 97,
111 G_INDEXED_ZEXTLOAD = 98,
112 G_STORE = 99,
113 G_INDEXED_STORE = 100,
114 G_ATOMIC_CMPXCHG_WITH_SUCCESS = 101,
115 G_ATOMIC_CMPXCHG = 102,
116 G_ATOMICRMW_XCHG = 103,
117 G_ATOMICRMW_ADD = 104,
118 G_ATOMICRMW_SUB = 105,
119 G_ATOMICRMW_AND = 106,
120 G_ATOMICRMW_NAND = 107,
121 G_ATOMICRMW_OR = 108,
122 G_ATOMICRMW_XOR = 109,
123 G_ATOMICRMW_MAX = 110,
124 G_ATOMICRMW_MIN = 111,
125 G_ATOMICRMW_UMAX = 112,
126 G_ATOMICRMW_UMIN = 113,
127 G_ATOMICRMW_FADD = 114,
128 G_ATOMICRMW_FSUB = 115,
129 G_ATOMICRMW_FMAX = 116,
130 G_ATOMICRMW_FMIN = 117,
131 G_ATOMICRMW_FMAXIMUM = 118,
132 G_ATOMICRMW_FMINIMUM = 119,
133 G_ATOMICRMW_UINC_WRAP = 120,
134 G_ATOMICRMW_UDEC_WRAP = 121,
135 G_ATOMICRMW_USUB_COND = 122,
136 G_ATOMICRMW_USUB_SAT = 123,
137 G_FENCE = 124,
138 G_PREFETCH = 125,
139 G_BRCOND = 126,
140 G_BRINDIRECT = 127,
141 G_INVOKE_REGION_START = 128,
142 G_INTRINSIC = 129,
143 G_INTRINSIC_W_SIDE_EFFECTS = 130,
144 G_INTRINSIC_CONVERGENT = 131,
145 G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 132,
146 G_ANYEXT = 133,
147 G_TRUNC = 134,
148 G_CONSTANT = 135,
149 G_FCONSTANT = 136,
150 G_VASTART = 137,
151 G_VAARG = 138,
152 G_SEXT = 139,
153 G_SEXT_INREG = 140,
154 G_ZEXT = 141,
155 G_SHL = 142,
156 G_LSHR = 143,
157 G_ASHR = 144,
158 G_FSHL = 145,
159 G_FSHR = 146,
160 G_ROTR = 147,
161 G_ROTL = 148,
162 G_ICMP = 149,
163 G_FCMP = 150,
164 G_SCMP = 151,
165 G_UCMP = 152,
166 G_SELECT = 153,
167 G_UADDO = 154,
168 G_UADDE = 155,
169 G_USUBO = 156,
170 G_USUBE = 157,
171 G_SADDO = 158,
172 G_SADDE = 159,
173 G_SSUBO = 160,
174 G_SSUBE = 161,
175 G_UMULO = 162,
176 G_SMULO = 163,
177 G_UMULH = 164,
178 G_SMULH = 165,
179 G_UADDSAT = 166,
180 G_SADDSAT = 167,
181 G_USUBSAT = 168,
182 G_SSUBSAT = 169,
183 G_USHLSAT = 170,
184 G_SSHLSAT = 171,
185 G_SMULFIX = 172,
186 G_UMULFIX = 173,
187 G_SMULFIXSAT = 174,
188 G_UMULFIXSAT = 175,
189 G_SDIVFIX = 176,
190 G_UDIVFIX = 177,
191 G_SDIVFIXSAT = 178,
192 G_UDIVFIXSAT = 179,
193 G_FADD = 180,
194 G_FSUB = 181,
195 G_FMUL = 182,
196 G_FMA = 183,
197 G_FMAD = 184,
198 G_FDIV = 185,
199 G_FREM = 186,
200 G_FPOW = 187,
201 G_FPOWI = 188,
202 G_FEXP = 189,
203 G_FEXP2 = 190,
204 G_FEXP10 = 191,
205 G_FLOG = 192,
206 G_FLOG2 = 193,
207 G_FLOG10 = 194,
208 G_FLDEXP = 195,
209 G_FFREXP = 196,
210 G_FNEG = 197,
211 G_FPEXT = 198,
212 G_FPTRUNC = 199,
213 G_FPTOSI = 200,
214 G_FPTOUI = 201,
215 G_SITOFP = 202,
216 G_UITOFP = 203,
217 G_FPTOSI_SAT = 204,
218 G_FPTOUI_SAT = 205,
219 G_FABS = 206,
220 G_FCOPYSIGN = 207,
221 G_IS_FPCLASS = 208,
222 G_FCANONICALIZE = 209,
223 G_FMINNUM = 210,
224 G_FMAXNUM = 211,
225 G_FMINNUM_IEEE = 212,
226 G_FMAXNUM_IEEE = 213,
227 G_FMINIMUM = 214,
228 G_FMAXIMUM = 215,
229 G_FMINIMUMNUM = 216,
230 G_FMAXIMUMNUM = 217,
231 G_GET_FPENV = 218,
232 G_SET_FPENV = 219,
233 G_RESET_FPENV = 220,
234 G_GET_FPMODE = 221,
235 G_SET_FPMODE = 222,
236 G_RESET_FPMODE = 223,
237 G_PTR_ADD = 224,
238 G_PTRMASK = 225,
239 G_SMIN = 226,
240 G_SMAX = 227,
241 G_UMIN = 228,
242 G_UMAX = 229,
243 G_ABS = 230,
244 G_LROUND = 231,
245 G_LLROUND = 232,
246 G_BR = 233,
247 G_BRJT = 234,
248 G_VSCALE = 235,
249 G_INSERT_SUBVECTOR = 236,
250 G_EXTRACT_SUBVECTOR = 237,
251 G_INSERT_VECTOR_ELT = 238,
252 G_EXTRACT_VECTOR_ELT = 239,
253 G_SHUFFLE_VECTOR = 240,
254 G_SPLAT_VECTOR = 241,
255 G_STEP_VECTOR = 242,
256 G_VECTOR_COMPRESS = 243,
257 G_CTTZ = 244,
258 G_CTTZ_ZERO_UNDEF = 245,
259 G_CTLZ = 246,
260 G_CTLZ_ZERO_UNDEF = 247,
261 G_CTPOP = 248,
262 G_BSWAP = 249,
263 G_BITREVERSE = 250,
264 G_FCEIL = 251,
265 G_FCOS = 252,
266 G_FSIN = 253,
267 G_FSINCOS = 254,
268 G_FTAN = 255,
269 G_FACOS = 256,
270 G_FASIN = 257,
271 G_FATAN = 258,
272 G_FATAN2 = 259,
273 G_FCOSH = 260,
274 G_FSINH = 261,
275 G_FTANH = 262,
276 G_FSQRT = 263,
277 G_FFLOOR = 264,
278 G_FRINT = 265,
279 G_FNEARBYINT = 266,
280 G_ADDRSPACE_CAST = 267,
281 G_BLOCK_ADDR = 268,
282 G_JUMP_TABLE = 269,
283 G_DYN_STACKALLOC = 270,
284 G_STACKSAVE = 271,
285 G_STACKRESTORE = 272,
286 G_STRICT_FADD = 273,
287 G_STRICT_FSUB = 274,
288 G_STRICT_FMUL = 275,
289 G_STRICT_FDIV = 276,
290 G_STRICT_FREM = 277,
291 G_STRICT_FMA = 278,
292 G_STRICT_FSQRT = 279,
293 G_STRICT_FLDEXP = 280,
294 G_READ_REGISTER = 281,
295 G_WRITE_REGISTER = 282,
296 G_MEMCPY = 283,
297 G_MEMCPY_INLINE = 284,
298 G_MEMMOVE = 285,
299 G_MEMSET = 286,
300 G_BZERO = 287,
301 G_TRAP = 288,
302 G_DEBUGTRAP = 289,
303 G_UBSANTRAP = 290,
304 G_VECREDUCE_SEQ_FADD = 291,
305 G_VECREDUCE_SEQ_FMUL = 292,
306 G_VECREDUCE_FADD = 293,
307 G_VECREDUCE_FMUL = 294,
308 G_VECREDUCE_FMAX = 295,
309 G_VECREDUCE_FMIN = 296,
310 G_VECREDUCE_FMAXIMUM = 297,
311 G_VECREDUCE_FMINIMUM = 298,
312 G_VECREDUCE_ADD = 299,
313 G_VECREDUCE_MUL = 300,
314 G_VECREDUCE_AND = 301,
315 G_VECREDUCE_OR = 302,
316 G_VECREDUCE_XOR = 303,
317 G_VECREDUCE_SMAX = 304,
318 G_VECREDUCE_SMIN = 305,
319 G_VECREDUCE_UMAX = 306,
320 G_VECREDUCE_UMIN = 307,
321 G_SBFX = 308,
322 G_UBFX = 309,
323 ADJCALLSTACKDOWN = 310,
324 ADJCALLSTACKUP = 311,
325 BuildPairF64Pseudo = 312,
326 PseudoAddTPRel_D = 313,
327 PseudoAddTPRel_W = 314,
328 PseudoAtomicLoadAdd32 = 315,
329 PseudoAtomicLoadAnd32 = 316,
330 PseudoAtomicLoadMax32 = 317,
331 PseudoAtomicLoadMin32 = 318,
332 PseudoAtomicLoadNand32 = 319,
333 PseudoAtomicLoadNand64 = 320,
334 PseudoAtomicLoadOr32 = 321,
335 PseudoAtomicLoadSub32 = 322,
336 PseudoAtomicLoadUMax32 = 323,
337 PseudoAtomicLoadUMin32 = 324,
338 PseudoAtomicLoadXor32 = 325,
339 PseudoAtomicStoreD = 326,
340 PseudoAtomicStoreW = 327,
341 PseudoAtomicSwap32 = 328,
342 PseudoBR = 329,
343 PseudoBRIND = 330,
344 PseudoB_TAIL = 331,
345 PseudoCALL = 332,
346 PseudoCALL36 = 333,
347 PseudoCALLIndirect = 334,
348 PseudoCALL_LARGE = 335,
349 PseudoCALL_MEDIUM = 336,
350 PseudoCTPOP = 337,
351 PseudoCmpXchg128 = 338,
352 PseudoCmpXchg128Acquire = 339,
353 PseudoCmpXchg32 = 340,
354 PseudoCmpXchg64 = 341,
355 PseudoCopyCFR = 342,
356 PseudoDESC_CALL = 343,
357 PseudoJIRL_CALL = 344,
358 PseudoJIRL_TAIL = 345,
359 PseudoLA_ABS = 346,
360 PseudoLA_ABS_LARGE = 347,
361 PseudoLA_GOT = 348,
362 PseudoLA_GOT_LARGE = 349,
363 PseudoLA_PCREL = 350,
364 PseudoLA_PCREL_LARGE = 351,
365 PseudoLA_TLS_DESC = 352,
366 PseudoLA_TLS_DESC_LARGE = 353,
367 PseudoLA_TLS_GD = 354,
368 PseudoLA_TLS_GD_LARGE = 355,
369 PseudoLA_TLS_IE = 356,
370 PseudoLA_TLS_IE_LARGE = 357,
371 PseudoLA_TLS_LD = 358,
372 PseudoLA_TLS_LD_LARGE = 359,
373 PseudoLA_TLS_LE = 360,
374 PseudoLD_CFR = 361,
375 PseudoLI_D = 362,
376 PseudoLI_W = 363,
377 PseudoMaskedAtomicLoadAdd32 = 364,
378 PseudoMaskedAtomicLoadMax32 = 365,
379 PseudoMaskedAtomicLoadMin32 = 366,
380 PseudoMaskedAtomicLoadNand32 = 367,
381 PseudoMaskedAtomicLoadSub32 = 368,
382 PseudoMaskedAtomicLoadUMax32 = 369,
383 PseudoMaskedAtomicLoadUMin32 = 370,
384 PseudoMaskedAtomicSwap32 = 371,
385 PseudoMaskedCmpXchg32 = 372,
386 PseudoRET = 373,
387 PseudoST_CFR = 374,
388 PseudoTAIL = 375,
389 PseudoTAIL36 = 376,
390 PseudoTAILIndirect = 377,
391 PseudoTAIL_LARGE = 378,
392 PseudoTAIL_MEDIUM = 379,
393 PseudoUNIMP = 380,
394 PseudoVBNZ = 381,
395 PseudoVBNZ_B = 382,
396 PseudoVBNZ_D = 383,
397 PseudoVBNZ_H = 384,
398 PseudoVBNZ_W = 385,
399 PseudoVBZ = 386,
400 PseudoVBZ_B = 387,
401 PseudoVBZ_D = 388,
402 PseudoVBZ_H = 389,
403 PseudoVBZ_W = 390,
404 PseudoVMSKEQZ_B = 391,
405 PseudoVMSKGEZ_B = 392,
406 PseudoVMSKLTZ_B = 393,
407 PseudoVMSKLTZ_D = 394,
408 PseudoVMSKLTZ_H = 395,
409 PseudoVMSKLTZ_W = 396,
410 PseudoVMSKNEZ_B = 397,
411 PseudoVREPLI_B = 398,
412 PseudoVREPLI_D = 399,
413 PseudoVREPLI_H = 400,
414 PseudoVREPLI_W = 401,
415 PseudoXVBNZ = 402,
416 PseudoXVBNZ_B = 403,
417 PseudoXVBNZ_D = 404,
418 PseudoXVBNZ_H = 405,
419 PseudoXVBNZ_W = 406,
420 PseudoXVBZ = 407,
421 PseudoXVBZ_B = 408,
422 PseudoXVBZ_D = 409,
423 PseudoXVBZ_H = 410,
424 PseudoXVBZ_W = 411,
425 PseudoXVINSGR2VR_B = 412,
426 PseudoXVINSGR2VR_H = 413,
427 PseudoXVMSKEQZ_B = 414,
428 PseudoXVMSKGEZ_B = 415,
429 PseudoXVMSKLTZ_B = 416,
430 PseudoXVMSKLTZ_D = 417,
431 PseudoXVMSKLTZ_H = 418,
432 PseudoXVMSKLTZ_W = 419,
433 PseudoXVMSKNEZ_B = 420,
434 PseudoXVREPLI_B = 421,
435 PseudoXVREPLI_D = 422,
436 PseudoXVREPLI_H = 423,
437 PseudoXVREPLI_W = 424,
438 RDFCSR = 425,
439 Select_GPR_Using_CC_GPR = 426,
440 SplitPairF64Pseudo = 427,
441 WRFCSR = 428,
442 ADC_B = 429,
443 ADC_D = 430,
444 ADC_H = 431,
445 ADC_W = 432,
446 ADDI_D = 433,
447 ADDI_W = 434,
448 ADDU12I_D = 435,
449 ADDU12I_W = 436,
450 ADDU16I_D = 437,
451 ADD_D = 438,
452 ADD_W = 439,
453 ALSL_D = 440,
454 ALSL_W = 441,
455 ALSL_WU = 442,
456 AMADD_B = 443,
457 AMADD_D = 444,
458 AMADD_H = 445,
459 AMADD_W = 446,
460 AMADD__DB_B = 447,
461 AMADD__DB_D = 448,
462 AMADD__DB_H = 449,
463 AMADD__DB_W = 450,
464 AMAND_D = 451,
465 AMAND_W = 452,
466 AMAND__DB_D = 453,
467 AMAND__DB_W = 454,
468 AMCAS_B = 455,
469 AMCAS_D = 456,
470 AMCAS_H = 457,
471 AMCAS_W = 458,
472 AMCAS__DB_B = 459,
473 AMCAS__DB_D = 460,
474 AMCAS__DB_H = 461,
475 AMCAS__DB_W = 462,
476 AMMAX_D = 463,
477 AMMAX_DU = 464,
478 AMMAX_W = 465,
479 AMMAX_WU = 466,
480 AMMAX__DB_D = 467,
481 AMMAX__DB_DU = 468,
482 AMMAX__DB_W = 469,
483 AMMAX__DB_WU = 470,
484 AMMIN_D = 471,
485 AMMIN_DU = 472,
486 AMMIN_W = 473,
487 AMMIN_WU = 474,
488 AMMIN__DB_D = 475,
489 AMMIN__DB_DU = 476,
490 AMMIN__DB_W = 477,
491 AMMIN__DB_WU = 478,
492 AMOR_D = 479,
493 AMOR_W = 480,
494 AMOR__DB_D = 481,
495 AMOR__DB_W = 482,
496 AMSWAP_B = 483,
497 AMSWAP_D = 484,
498 AMSWAP_H = 485,
499 AMSWAP_W = 486,
500 AMSWAP__DB_B = 487,
501 AMSWAP__DB_D = 488,
502 AMSWAP__DB_H = 489,
503 AMSWAP__DB_W = 490,
504 AMXOR_D = 491,
505 AMXOR_W = 492,
506 AMXOR__DB_D = 493,
507 AMXOR__DB_W = 494,
508 AND = 495,
509 ANDI = 496,
510 ANDN = 497,
511 ARMADC_W = 498,
512 ARMADD_W = 499,
513 ARMAND_W = 500,
514 ARMMFFLAG = 501,
515 ARMMOVE = 502,
516 ARMMOV_D = 503,
517 ARMMOV_W = 504,
518 ARMMTFLAG = 505,
519 ARMNOT_W = 506,
520 ARMOR_W = 507,
521 ARMROTRI_W = 508,
522 ARMROTR_W = 509,
523 ARMRRX_W = 510,
524 ARMSBC_W = 511,
525 ARMSLLI_W = 512,
526 ARMSLL_W = 513,
527 ARMSRAI_W = 514,
528 ARMSRA_W = 515,
529 ARMSRLI_W = 516,
530 ARMSRL_W = 517,
531 ARMSUB_W = 518,
532 ARMXOR_W = 519,
533 ASRTGT_D = 520,
534 ASRTLE_D = 521,
535 B = 522,
536 BCEQZ = 523,
537 BCNEZ = 524,
538 BEQ = 525,
539 BEQZ = 526,
540 BGE = 527,
541 BGEU = 528,
542 BITREV_4B = 529,
543 BITREV_8B = 530,
544 BITREV_D = 531,
545 BITREV_W = 532,
546 BL = 533,
547 BLT = 534,
548 BLTU = 535,
549 BNE = 536,
550 BNEZ = 537,
551 BREAK = 538,
552 BSTRINS_D = 539,
553 BSTRINS_W = 540,
554 BSTRPICK_D = 541,
555 BSTRPICK_W = 542,
556 BYTEPICK_D = 543,
557 BYTEPICK_W = 544,
558 CACOP = 545,
559 CLO_D = 546,
560 CLO_W = 547,
561 CLZ_D = 548,
562 CLZ_W = 549,
563 CPUCFG = 550,
564 CRCC_W_B_W = 551,
565 CRCC_W_D_W = 552,
566 CRCC_W_H_W = 553,
567 CRCC_W_W_W = 554,
568 CRC_W_B_W = 555,
569 CRC_W_D_W = 556,
570 CRC_W_H_W = 557,
571 CRC_W_W_W = 558,
572 CSRRD = 559,
573 CSRWR = 560,
574 CSRXCHG = 561,
575 CTO_D = 562,
576 CTO_W = 563,
577 CTZ_D = 564,
578 CTZ_W = 565,
579 DBAR = 566,
580 DBCL = 567,
581 DIV_D = 568,
582 DIV_DU = 569,
583 DIV_W = 570,
584 DIV_WU = 571,
585 ERTN = 572,
586 EXT_W_B = 573,
587 EXT_W_H = 574,
588 FABS_D = 575,
589 FABS_S = 576,
590 FADD_D = 577,
591 FADD_S = 578,
592 FCLASS_D = 579,
593 FCLASS_S = 580,
594 FCMP_CAF_D = 581,
595 FCMP_CAF_S = 582,
596 FCMP_CEQ_D = 583,
597 FCMP_CEQ_S = 584,
598 FCMP_CLE_D = 585,
599 FCMP_CLE_S = 586,
600 FCMP_CLT_D = 587,
601 FCMP_CLT_S = 588,
602 FCMP_CNE_D = 589,
603 FCMP_CNE_S = 590,
604 FCMP_COR_D = 591,
605 FCMP_COR_S = 592,
606 FCMP_CUEQ_D = 593,
607 FCMP_CUEQ_S = 594,
608 FCMP_CULE_D = 595,
609 FCMP_CULE_S = 596,
610 FCMP_CULT_D = 597,
611 FCMP_CULT_S = 598,
612 FCMP_CUNE_D = 599,
613 FCMP_CUNE_S = 600,
614 FCMP_CUN_D = 601,
615 FCMP_CUN_S = 602,
616 FCMP_SAF_D = 603,
617 FCMP_SAF_S = 604,
618 FCMP_SEQ_D = 605,
619 FCMP_SEQ_S = 606,
620 FCMP_SLE_D = 607,
621 FCMP_SLE_S = 608,
622 FCMP_SLT_D = 609,
623 FCMP_SLT_S = 610,
624 FCMP_SNE_D = 611,
625 FCMP_SNE_S = 612,
626 FCMP_SOR_D = 613,
627 FCMP_SOR_S = 614,
628 FCMP_SUEQ_D = 615,
629 FCMP_SUEQ_S = 616,
630 FCMP_SULE_D = 617,
631 FCMP_SULE_S = 618,
632 FCMP_SULT_D = 619,
633 FCMP_SULT_S = 620,
634 FCMP_SUNE_D = 621,
635 FCMP_SUNE_S = 622,
636 FCMP_SUN_D = 623,
637 FCMP_SUN_S = 624,
638 FCOPYSIGN_D = 625,
639 FCOPYSIGN_S = 626,
640 FCVT_D_LD = 627,
641 FCVT_D_S = 628,
642 FCVT_LD_D = 629,
643 FCVT_S_D = 630,
644 FCVT_UD_D = 631,
645 FDIV_D = 632,
646 FDIV_S = 633,
647 FFINT_D_L = 634,
648 FFINT_D_W = 635,
649 FFINT_S_L = 636,
650 FFINT_S_W = 637,
651 FLDGT_D = 638,
652 FLDGT_S = 639,
653 FLDLE_D = 640,
654 FLDLE_S = 641,
655 FLDX_D = 642,
656 FLDX_S = 643,
657 FLD_D = 644,
658 FLD_S = 645,
659 FLOGB_D = 646,
660 FLOGB_S = 647,
661 FMADD_D = 648,
662 FMADD_S = 649,
663 FMAXA_D = 650,
664 FMAXA_S = 651,
665 FMAX_D = 652,
666 FMAX_S = 653,
667 FMINA_D = 654,
668 FMINA_S = 655,
669 FMIN_D = 656,
670 FMIN_S = 657,
671 FMOV_D = 658,
672 FMOV_S = 659,
673 FMSUB_D = 660,
674 FMSUB_S = 661,
675 FMUL_D = 662,
676 FMUL_S = 663,
677 FNEG_D = 664,
678 FNEG_S = 665,
679 FNMADD_D = 666,
680 FNMADD_S = 667,
681 FNMSUB_D = 668,
682 FNMSUB_S = 669,
683 FRECIPE_D = 670,
684 FRECIPE_S = 671,
685 FRECIP_D = 672,
686 FRECIP_S = 673,
687 FRINT_D = 674,
688 FRINT_S = 675,
689 FRSQRTE_D = 676,
690 FRSQRTE_S = 677,
691 FRSQRT_D = 678,
692 FRSQRT_S = 679,
693 FSCALEB_D = 680,
694 FSCALEB_S = 681,
695 FSEL_xD = 682,
696 FSEL_xS = 683,
697 FSQRT_D = 684,
698 FSQRT_S = 685,
699 FSTGT_D = 686,
700 FSTGT_S = 687,
701 FSTLE_D = 688,
702 FSTLE_S = 689,
703 FSTX_D = 690,
704 FSTX_S = 691,
705 FST_D = 692,
706 FST_S = 693,
707 FSUB_D = 694,
708 FSUB_S = 695,
709 FTINTRM_L_D = 696,
710 FTINTRM_L_S = 697,
711 FTINTRM_W_D = 698,
712 FTINTRM_W_S = 699,
713 FTINTRNE_L_D = 700,
714 FTINTRNE_L_S = 701,
715 FTINTRNE_W_D = 702,
716 FTINTRNE_W_S = 703,
717 FTINTRP_L_D = 704,
718 FTINTRP_L_S = 705,
719 FTINTRP_W_D = 706,
720 FTINTRP_W_S = 707,
721 FTINTRZ_L_D = 708,
722 FTINTRZ_L_S = 709,
723 FTINTRZ_W_D = 710,
724 FTINTRZ_W_S = 711,
725 FTINT_L_D = 712,
726 FTINT_L_S = 713,
727 FTINT_W_D = 714,
728 FTINT_W_S = 715,
729 GCSRRD = 716,
730 GCSRWR = 717,
731 GCSRXCHG = 718,
732 GTLBFLUSH = 719,
733 HVCL = 720,
734 IBAR = 721,
735 IDLE = 722,
736 INVTLB = 723,
737 IOCSRRD_B = 724,
738 IOCSRRD_D = 725,
739 IOCSRRD_H = 726,
740 IOCSRRD_W = 727,
741 IOCSRWR_B = 728,
742 IOCSRWR_D = 729,
743 IOCSRWR_H = 730,
744 IOCSRWR_W = 731,
745 JIRL = 732,
746 JISCR0 = 733,
747 JISCR1 = 734,
748 LDDIR = 735,
749 LDGT_B = 736,
750 LDGT_D = 737,
751 LDGT_H = 738,
752 LDGT_W = 739,
753 LDLE_B = 740,
754 LDLE_D = 741,
755 LDLE_H = 742,
756 LDLE_W = 743,
757 LDL_D = 744,
758 LDL_W = 745,
759 LDPTE = 746,
760 LDPTR_D = 747,
761 LDPTR_W = 748,
762 LDR_D = 749,
763 LDR_W = 750,
764 LDX_B = 751,
765 LDX_BU = 752,
766 LDX_D = 753,
767 LDX_H = 754,
768 LDX_HU = 755,
769 LDX_W = 756,
770 LDX_WU = 757,
771 LD_B = 758,
772 LD_BU = 759,
773 LD_D = 760,
774 LD_H = 761,
775 LD_HU = 762,
776 LD_W = 763,
777 LD_WU = 764,
778 LLACQ_D = 765,
779 LLACQ_W = 766,
780 LL_D = 767,
781 LL_W = 768,
782 LU12I_W = 769,
783 LU32I_D = 770,
784 LU52I_D = 771,
785 MASKEQZ = 772,
786 MASKNEZ = 773,
787 MOD_D = 774,
788 MOD_DU = 775,
789 MOD_W = 776,
790 MOD_WU = 777,
791 MOVCF2FR_xS = 778,
792 MOVCF2GR = 779,
793 MOVFCSR2GR = 780,
794 MOVFR2CF_xS = 781,
795 MOVFR2GR_D = 782,
796 MOVFR2GR_S = 783,
797 MOVFR2GR_S_64 = 784,
798 MOVFRH2GR_S = 785,
799 MOVGR2CF = 786,
800 MOVGR2FCSR = 787,
801 MOVGR2FRH_W = 788,
802 MOVGR2FR_D = 789,
803 MOVGR2FR_W = 790,
804 MOVGR2FR_W_64 = 791,
805 MOVGR2SCR = 792,
806 MOVSCR2GR = 793,
807 MULH_D = 794,
808 MULH_DU = 795,
809 MULH_W = 796,
810 MULH_WU = 797,
811 MULW_D_W = 798,
812 MULW_D_WU = 799,
813 MUL_D = 800,
814 MUL_W = 801,
815 NOR = 802,
816 OR = 803,
817 ORI = 804,
818 ORN = 805,
819 PCADDI = 806,
820 PCADDU12I = 807,
821 PCADDU18I = 808,
822 PCALAU12I = 809,
823 PRELD = 810,
824 PRELDX = 811,
825 RCRI_B = 812,
826 RCRI_D = 813,
827 RCRI_H = 814,
828 RCRI_W = 815,
829 RCR_B = 816,
830 RCR_D = 817,
831 RCR_H = 818,
832 RCR_W = 819,
833 RDTIMEH_W = 820,
834 RDTIMEL_W = 821,
835 RDTIME_D = 822,
836 REVB_2H = 823,
837 REVB_2W = 824,
838 REVB_4H = 825,
839 REVB_D = 826,
840 REVH_2W = 827,
841 REVH_D = 828,
842 ROTRI_B = 829,
843 ROTRI_D = 830,
844 ROTRI_H = 831,
845 ROTRI_W = 832,
846 ROTR_B = 833,
847 ROTR_D = 834,
848 ROTR_H = 835,
849 ROTR_W = 836,
850 SBC_B = 837,
851 SBC_D = 838,
852 SBC_H = 839,
853 SBC_W = 840,
854 SCREL_D = 841,
855 SCREL_W = 842,
856 SC_D = 843,
857 SC_Q = 844,
858 SC_W = 845,
859 SETARMJ = 846,
860 SETX86J = 847,
861 SETX86LOOPE = 848,
862 SETX86LOOPNE = 849,
863 SET_CFR_FALSE = 850,
864 SET_CFR_TRUE = 851,
865 SLLI_D = 852,
866 SLLI_W = 853,
867 SLL_D = 854,
868 SLL_W = 855,
869 SLT = 856,
870 SLTI = 857,
871 SLTU = 858,
872 SLTUI = 859,
873 SRAI_D = 860,
874 SRAI_W = 861,
875 SRA_D = 862,
876 SRA_W = 863,
877 SRLI_D = 864,
878 SRLI_W = 865,
879 SRL_D = 866,
880 SRL_W = 867,
881 STGT_B = 868,
882 STGT_D = 869,
883 STGT_H = 870,
884 STGT_W = 871,
885 STLE_B = 872,
886 STLE_D = 873,
887 STLE_H = 874,
888 STLE_W = 875,
889 STL_D = 876,
890 STL_W = 877,
891 STPTR_D = 878,
892 STPTR_W = 879,
893 STR_D = 880,
894 STR_W = 881,
895 STX_B = 882,
896 STX_D = 883,
897 STX_H = 884,
898 STX_W = 885,
899 ST_B = 886,
900 ST_D = 887,
901 ST_H = 888,
902 ST_W = 889,
903 SUB_D = 890,
904 SUB_W = 891,
905 SYSCALL = 892,
906 TLBCLR = 893,
907 TLBFILL = 894,
908 TLBFLUSH = 895,
909 TLBRD = 896,
910 TLBSRCH = 897,
911 TLBWR = 898,
912 VABSD_B = 899,
913 VABSD_BU = 900,
914 VABSD_D = 901,
915 VABSD_DU = 902,
916 VABSD_H = 903,
917 VABSD_HU = 904,
918 VABSD_W = 905,
919 VABSD_WU = 906,
920 VADDA_B = 907,
921 VADDA_D = 908,
922 VADDA_H = 909,
923 VADDA_W = 910,
924 VADDI_BU = 911,
925 VADDI_DU = 912,
926 VADDI_HU = 913,
927 VADDI_WU = 914,
928 VADDWEV_D_W = 915,
929 VADDWEV_D_WU = 916,
930 VADDWEV_D_WU_W = 917,
931 VADDWEV_H_B = 918,
932 VADDWEV_H_BU = 919,
933 VADDWEV_H_BU_B = 920,
934 VADDWEV_Q_D = 921,
935 VADDWEV_Q_DU = 922,
936 VADDWEV_Q_DU_D = 923,
937 VADDWEV_W_H = 924,
938 VADDWEV_W_HU = 925,
939 VADDWEV_W_HU_H = 926,
940 VADDWOD_D_W = 927,
941 VADDWOD_D_WU = 928,
942 VADDWOD_D_WU_W = 929,
943 VADDWOD_H_B = 930,
944 VADDWOD_H_BU = 931,
945 VADDWOD_H_BU_B = 932,
946 VADDWOD_Q_D = 933,
947 VADDWOD_Q_DU = 934,
948 VADDWOD_Q_DU_D = 935,
949 VADDWOD_W_H = 936,
950 VADDWOD_W_HU = 937,
951 VADDWOD_W_HU_H = 938,
952 VADD_B = 939,
953 VADD_D = 940,
954 VADD_H = 941,
955 VADD_Q = 942,
956 VADD_W = 943,
957 VANDI_B = 944,
958 VANDN_V = 945,
959 VAND_V = 946,
960 VAVGR_B = 947,
961 VAVGR_BU = 948,
962 VAVGR_D = 949,
963 VAVGR_DU = 950,
964 VAVGR_H = 951,
965 VAVGR_HU = 952,
966 VAVGR_W = 953,
967 VAVGR_WU = 954,
968 VAVG_B = 955,
969 VAVG_BU = 956,
970 VAVG_D = 957,
971 VAVG_DU = 958,
972 VAVG_H = 959,
973 VAVG_HU = 960,
974 VAVG_W = 961,
975 VAVG_WU = 962,
976 VBITCLRI_B = 963,
977 VBITCLRI_D = 964,
978 VBITCLRI_H = 965,
979 VBITCLRI_W = 966,
980 VBITCLR_B = 967,
981 VBITCLR_D = 968,
982 VBITCLR_H = 969,
983 VBITCLR_W = 970,
984 VBITREVI_B = 971,
985 VBITREVI_D = 972,
986 VBITREVI_H = 973,
987 VBITREVI_W = 974,
988 VBITREV_B = 975,
989 VBITREV_D = 976,
990 VBITREV_H = 977,
991 VBITREV_W = 978,
992 VBITSELI_B = 979,
993 VBITSEL_V = 980,
994 VBITSETI_B = 981,
995 VBITSETI_D = 982,
996 VBITSETI_H = 983,
997 VBITSETI_W = 984,
998 VBITSET_B = 985,
999 VBITSET_D = 986,
1000 VBITSET_H = 987,
1001 VBITSET_W = 988,
1002 VBSLL_V = 989,
1003 VBSRL_V = 990,
1004 VCLO_B = 991,
1005 VCLO_D = 992,
1006 VCLO_H = 993,
1007 VCLO_W = 994,
1008 VCLZ_B = 995,
1009 VCLZ_D = 996,
1010 VCLZ_H = 997,
1011 VCLZ_W = 998,
1012 VDIV_B = 999,
1013 VDIV_BU = 1000,
1014 VDIV_D = 1001,
1015 VDIV_DU = 1002,
1016 VDIV_H = 1003,
1017 VDIV_HU = 1004,
1018 VDIV_W = 1005,
1019 VDIV_WU = 1006,
1020 VEXT2XV_DU_BU = 1007,
1021 VEXT2XV_DU_HU = 1008,
1022 VEXT2XV_DU_WU = 1009,
1023 VEXT2XV_D_B = 1010,
1024 VEXT2XV_D_H = 1011,
1025 VEXT2XV_D_W = 1012,
1026 VEXT2XV_HU_BU = 1013,
1027 VEXT2XV_H_B = 1014,
1028 VEXT2XV_WU_BU = 1015,
1029 VEXT2XV_WU_HU = 1016,
1030 VEXT2XV_W_B = 1017,
1031 VEXT2XV_W_H = 1018,
1032 VEXTH_DU_WU = 1019,
1033 VEXTH_D_W = 1020,
1034 VEXTH_HU_BU = 1021,
1035 VEXTH_H_B = 1022,
1036 VEXTH_QU_DU = 1023,
1037 VEXTH_Q_D = 1024,
1038 VEXTH_WU_HU = 1025,
1039 VEXTH_W_H = 1026,
1040 VEXTL_QU_DU = 1027,
1041 VEXTL_Q_D = 1028,
1042 VEXTRINS_B = 1029,
1043 VEXTRINS_D = 1030,
1044 VEXTRINS_H = 1031,
1045 VEXTRINS_W = 1032,
1046 VFADD_D = 1033,
1047 VFADD_S = 1034,
1048 VFCLASS_D = 1035,
1049 VFCLASS_S = 1036,
1050 VFCMP_CAF_D = 1037,
1051 VFCMP_CAF_S = 1038,
1052 VFCMP_CEQ_D = 1039,
1053 VFCMP_CEQ_S = 1040,
1054 VFCMP_CLE_D = 1041,
1055 VFCMP_CLE_S = 1042,
1056 VFCMP_CLT_D = 1043,
1057 VFCMP_CLT_S = 1044,
1058 VFCMP_CNE_D = 1045,
1059 VFCMP_CNE_S = 1046,
1060 VFCMP_COR_D = 1047,
1061 VFCMP_COR_S = 1048,
1062 VFCMP_CUEQ_D = 1049,
1063 VFCMP_CUEQ_S = 1050,
1064 VFCMP_CULE_D = 1051,
1065 VFCMP_CULE_S = 1052,
1066 VFCMP_CULT_D = 1053,
1067 VFCMP_CULT_S = 1054,
1068 VFCMP_CUNE_D = 1055,
1069 VFCMP_CUNE_S = 1056,
1070 VFCMP_CUN_D = 1057,
1071 VFCMP_CUN_S = 1058,
1072 VFCMP_SAF_D = 1059,
1073 VFCMP_SAF_S = 1060,
1074 VFCMP_SEQ_D = 1061,
1075 VFCMP_SEQ_S = 1062,
1076 VFCMP_SLE_D = 1063,
1077 VFCMP_SLE_S = 1064,
1078 VFCMP_SLT_D = 1065,
1079 VFCMP_SLT_S = 1066,
1080 VFCMP_SNE_D = 1067,
1081 VFCMP_SNE_S = 1068,
1082 VFCMP_SOR_D = 1069,
1083 VFCMP_SOR_S = 1070,
1084 VFCMP_SUEQ_D = 1071,
1085 VFCMP_SUEQ_S = 1072,
1086 VFCMP_SULE_D = 1073,
1087 VFCMP_SULE_S = 1074,
1088 VFCMP_SULT_D = 1075,
1089 VFCMP_SULT_S = 1076,
1090 VFCMP_SUNE_D = 1077,
1091 VFCMP_SUNE_S = 1078,
1092 VFCMP_SUN_D = 1079,
1093 VFCMP_SUN_S = 1080,
1094 VFCVTH_D_S = 1081,
1095 VFCVTH_S_H = 1082,
1096 VFCVTL_D_S = 1083,
1097 VFCVTL_S_H = 1084,
1098 VFCVT_H_S = 1085,
1099 VFCVT_S_D = 1086,
1100 VFDIV_D = 1087,
1101 VFDIV_S = 1088,
1102 VFFINTH_D_W = 1089,
1103 VFFINTL_D_W = 1090,
1104 VFFINT_D_L = 1091,
1105 VFFINT_D_LU = 1092,
1106 VFFINT_S_L = 1093,
1107 VFFINT_S_W = 1094,
1108 VFFINT_S_WU = 1095,
1109 VFLOGB_D = 1096,
1110 VFLOGB_S = 1097,
1111 VFMADD_D = 1098,
1112 VFMADD_S = 1099,
1113 VFMAXA_D = 1100,
1114 VFMAXA_S = 1101,
1115 VFMAX_D = 1102,
1116 VFMAX_S = 1103,
1117 VFMINA_D = 1104,
1118 VFMINA_S = 1105,
1119 VFMIN_D = 1106,
1120 VFMIN_S = 1107,
1121 VFMSUB_D = 1108,
1122 VFMSUB_S = 1109,
1123 VFMUL_D = 1110,
1124 VFMUL_S = 1111,
1125 VFNMADD_D = 1112,
1126 VFNMADD_S = 1113,
1127 VFNMSUB_D = 1114,
1128 VFNMSUB_S = 1115,
1129 VFRECIPE_D = 1116,
1130 VFRECIPE_S = 1117,
1131 VFRECIP_D = 1118,
1132 VFRECIP_S = 1119,
1133 VFRINTRM_D = 1120,
1134 VFRINTRM_S = 1121,
1135 VFRINTRNE_D = 1122,
1136 VFRINTRNE_S = 1123,
1137 VFRINTRP_D = 1124,
1138 VFRINTRP_S = 1125,
1139 VFRINTRZ_D = 1126,
1140 VFRINTRZ_S = 1127,
1141 VFRINT_D = 1128,
1142 VFRINT_S = 1129,
1143 VFRSQRTE_D = 1130,
1144 VFRSQRTE_S = 1131,
1145 VFRSQRT_D = 1132,
1146 VFRSQRT_S = 1133,
1147 VFRSTPI_B = 1134,
1148 VFRSTPI_H = 1135,
1149 VFRSTP_B = 1136,
1150 VFRSTP_H = 1137,
1151 VFSQRT_D = 1138,
1152 VFSQRT_S = 1139,
1153 VFSUB_D = 1140,
1154 VFSUB_S = 1141,
1155 VFTINTH_L_S = 1142,
1156 VFTINTL_L_S = 1143,
1157 VFTINTRMH_L_S = 1144,
1158 VFTINTRML_L_S = 1145,
1159 VFTINTRM_L_D = 1146,
1160 VFTINTRM_W_D = 1147,
1161 VFTINTRM_W_S = 1148,
1162 VFTINTRNEH_L_S = 1149,
1163 VFTINTRNEL_L_S = 1150,
1164 VFTINTRNE_L_D = 1151,
1165 VFTINTRNE_W_D = 1152,
1166 VFTINTRNE_W_S = 1153,
1167 VFTINTRPH_L_S = 1154,
1168 VFTINTRPL_L_S = 1155,
1169 VFTINTRP_L_D = 1156,
1170 VFTINTRP_W_D = 1157,
1171 VFTINTRP_W_S = 1158,
1172 VFTINTRZH_L_S = 1159,
1173 VFTINTRZL_L_S = 1160,
1174 VFTINTRZ_LU_D = 1161,
1175 VFTINTRZ_L_D = 1162,
1176 VFTINTRZ_WU_S = 1163,
1177 VFTINTRZ_W_D = 1164,
1178 VFTINTRZ_W_S = 1165,
1179 VFTINT_LU_D = 1166,
1180 VFTINT_L_D = 1167,
1181 VFTINT_WU_S = 1168,
1182 VFTINT_W_D = 1169,
1183 VFTINT_W_S = 1170,
1184 VHADDW_DU_WU = 1171,
1185 VHADDW_D_W = 1172,
1186 VHADDW_HU_BU = 1173,
1187 VHADDW_H_B = 1174,
1188 VHADDW_QU_DU = 1175,
1189 VHADDW_Q_D = 1176,
1190 VHADDW_WU_HU = 1177,
1191 VHADDW_W_H = 1178,
1192 VHSUBW_DU_WU = 1179,
1193 VHSUBW_D_W = 1180,
1194 VHSUBW_HU_BU = 1181,
1195 VHSUBW_H_B = 1182,
1196 VHSUBW_QU_DU = 1183,
1197 VHSUBW_Q_D = 1184,
1198 VHSUBW_WU_HU = 1185,
1199 VHSUBW_W_H = 1186,
1200 VILVH_B = 1187,
1201 VILVH_D = 1188,
1202 VILVH_H = 1189,
1203 VILVH_W = 1190,
1204 VILVL_B = 1191,
1205 VILVL_D = 1192,
1206 VILVL_H = 1193,
1207 VILVL_W = 1194,
1208 VINSGR2VR_B = 1195,
1209 VINSGR2VR_D = 1196,
1210 VINSGR2VR_H = 1197,
1211 VINSGR2VR_W = 1198,
1212 VLD = 1199,
1213 VLDI = 1200,
1214 VLDREPL_B = 1201,
1215 VLDREPL_D = 1202,
1216 VLDREPL_H = 1203,
1217 VLDREPL_W = 1204,
1218 VLDX = 1205,
1219 VMADDWEV_D_W = 1206,
1220 VMADDWEV_D_WU = 1207,
1221 VMADDWEV_D_WU_W = 1208,
1222 VMADDWEV_H_B = 1209,
1223 VMADDWEV_H_BU = 1210,
1224 VMADDWEV_H_BU_B = 1211,
1225 VMADDWEV_Q_D = 1212,
1226 VMADDWEV_Q_DU = 1213,
1227 VMADDWEV_Q_DU_D = 1214,
1228 VMADDWEV_W_H = 1215,
1229 VMADDWEV_W_HU = 1216,
1230 VMADDWEV_W_HU_H = 1217,
1231 VMADDWOD_D_W = 1218,
1232 VMADDWOD_D_WU = 1219,
1233 VMADDWOD_D_WU_W = 1220,
1234 VMADDWOD_H_B = 1221,
1235 VMADDWOD_H_BU = 1222,
1236 VMADDWOD_H_BU_B = 1223,
1237 VMADDWOD_Q_D = 1224,
1238 VMADDWOD_Q_DU = 1225,
1239 VMADDWOD_Q_DU_D = 1226,
1240 VMADDWOD_W_H = 1227,
1241 VMADDWOD_W_HU = 1228,
1242 VMADDWOD_W_HU_H = 1229,
1243 VMADD_B = 1230,
1244 VMADD_D = 1231,
1245 VMADD_H = 1232,
1246 VMADD_W = 1233,
1247 VMAXI_B = 1234,
1248 VMAXI_BU = 1235,
1249 VMAXI_D = 1236,
1250 VMAXI_DU = 1237,
1251 VMAXI_H = 1238,
1252 VMAXI_HU = 1239,
1253 VMAXI_W = 1240,
1254 VMAXI_WU = 1241,
1255 VMAX_B = 1242,
1256 VMAX_BU = 1243,
1257 VMAX_D = 1244,
1258 VMAX_DU = 1245,
1259 VMAX_H = 1246,
1260 VMAX_HU = 1247,
1261 VMAX_W = 1248,
1262 VMAX_WU = 1249,
1263 VMINI_B = 1250,
1264 VMINI_BU = 1251,
1265 VMINI_D = 1252,
1266 VMINI_DU = 1253,
1267 VMINI_H = 1254,
1268 VMINI_HU = 1255,
1269 VMINI_W = 1256,
1270 VMINI_WU = 1257,
1271 VMIN_B = 1258,
1272 VMIN_BU = 1259,
1273 VMIN_D = 1260,
1274 VMIN_DU = 1261,
1275 VMIN_H = 1262,
1276 VMIN_HU = 1263,
1277 VMIN_W = 1264,
1278 VMIN_WU = 1265,
1279 VMOD_B = 1266,
1280 VMOD_BU = 1267,
1281 VMOD_D = 1268,
1282 VMOD_DU = 1269,
1283 VMOD_H = 1270,
1284 VMOD_HU = 1271,
1285 VMOD_W = 1272,
1286 VMOD_WU = 1273,
1287 VMSKGEZ_B = 1274,
1288 VMSKLTZ_B = 1275,
1289 VMSKLTZ_D = 1276,
1290 VMSKLTZ_H = 1277,
1291 VMSKLTZ_W = 1278,
1292 VMSKNZ_B = 1279,
1293 VMSUB_B = 1280,
1294 VMSUB_D = 1281,
1295 VMSUB_H = 1282,
1296 VMSUB_W = 1283,
1297 VMUH_B = 1284,
1298 VMUH_BU = 1285,
1299 VMUH_D = 1286,
1300 VMUH_DU = 1287,
1301 VMUH_H = 1288,
1302 VMUH_HU = 1289,
1303 VMUH_W = 1290,
1304 VMUH_WU = 1291,
1305 VMULWEV_D_W = 1292,
1306 VMULWEV_D_WU = 1293,
1307 VMULWEV_D_WU_W = 1294,
1308 VMULWEV_H_B = 1295,
1309 VMULWEV_H_BU = 1296,
1310 VMULWEV_H_BU_B = 1297,
1311 VMULWEV_Q_D = 1298,
1312 VMULWEV_Q_DU = 1299,
1313 VMULWEV_Q_DU_D = 1300,
1314 VMULWEV_W_H = 1301,
1315 VMULWEV_W_HU = 1302,
1316 VMULWEV_W_HU_H = 1303,
1317 VMULWOD_D_W = 1304,
1318 VMULWOD_D_WU = 1305,
1319 VMULWOD_D_WU_W = 1306,
1320 VMULWOD_H_B = 1307,
1321 VMULWOD_H_BU = 1308,
1322 VMULWOD_H_BU_B = 1309,
1323 VMULWOD_Q_D = 1310,
1324 VMULWOD_Q_DU = 1311,
1325 VMULWOD_Q_DU_D = 1312,
1326 VMULWOD_W_H = 1313,
1327 VMULWOD_W_HU = 1314,
1328 VMULWOD_W_HU_H = 1315,
1329 VMUL_B = 1316,
1330 VMUL_D = 1317,
1331 VMUL_H = 1318,
1332 VMUL_W = 1319,
1333 VNEG_B = 1320,
1334 VNEG_D = 1321,
1335 VNEG_H = 1322,
1336 VNEG_W = 1323,
1337 VNORI_B = 1324,
1338 VNOR_V = 1325,
1339 VORI_B = 1326,
1340 VORN_V = 1327,
1341 VOR_V = 1328,
1342 VPACKEV_B = 1329,
1343 VPACKEV_D = 1330,
1344 VPACKEV_H = 1331,
1345 VPACKEV_W = 1332,
1346 VPACKOD_B = 1333,
1347 VPACKOD_D = 1334,
1348 VPACKOD_H = 1335,
1349 VPACKOD_W = 1336,
1350 VPCNT_B = 1337,
1351 VPCNT_D = 1338,
1352 VPCNT_H = 1339,
1353 VPCNT_W = 1340,
1354 VPERMI_W = 1341,
1355 VPICKEV_B = 1342,
1356 VPICKEV_D = 1343,
1357 VPICKEV_H = 1344,
1358 VPICKEV_W = 1345,
1359 VPICKOD_B = 1346,
1360 VPICKOD_D = 1347,
1361 VPICKOD_H = 1348,
1362 VPICKOD_W = 1349,
1363 VPICKVE2GR_B = 1350,
1364 VPICKVE2GR_BU = 1351,
1365 VPICKVE2GR_D = 1352,
1366 VPICKVE2GR_DU = 1353,
1367 VPICKVE2GR_H = 1354,
1368 VPICKVE2GR_HU = 1355,
1369 VPICKVE2GR_W = 1356,
1370 VPICKVE2GR_WU = 1357,
1371 VREPLGR2VR_B = 1358,
1372 VREPLGR2VR_D = 1359,
1373 VREPLGR2VR_H = 1360,
1374 VREPLGR2VR_W = 1361,
1375 VREPLVEI_B = 1362,
1376 VREPLVEI_D = 1363,
1377 VREPLVEI_H = 1364,
1378 VREPLVEI_W = 1365,
1379 VREPLVE_B = 1366,
1380 VREPLVE_D = 1367,
1381 VREPLVE_H = 1368,
1382 VREPLVE_W = 1369,
1383 VROTRI_B = 1370,
1384 VROTRI_D = 1371,
1385 VROTRI_H = 1372,
1386 VROTRI_W = 1373,
1387 VROTR_B = 1374,
1388 VROTR_D = 1375,
1389 VROTR_H = 1376,
1390 VROTR_W = 1377,
1391 VSADD_B = 1378,
1392 VSADD_BU = 1379,
1393 VSADD_D = 1380,
1394 VSADD_DU = 1381,
1395 VSADD_H = 1382,
1396 VSADD_HU = 1383,
1397 VSADD_W = 1384,
1398 VSADD_WU = 1385,
1399 VSAT_B = 1386,
1400 VSAT_BU = 1387,
1401 VSAT_D = 1388,
1402 VSAT_DU = 1389,
1403 VSAT_H = 1390,
1404 VSAT_HU = 1391,
1405 VSAT_W = 1392,
1406 VSAT_WU = 1393,
1407 VSEQI_B = 1394,
1408 VSEQI_D = 1395,
1409 VSEQI_H = 1396,
1410 VSEQI_W = 1397,
1411 VSEQ_B = 1398,
1412 VSEQ_D = 1399,
1413 VSEQ_H = 1400,
1414 VSEQ_W = 1401,
1415 VSETALLNEZ_B = 1402,
1416 VSETALLNEZ_D = 1403,
1417 VSETALLNEZ_H = 1404,
1418 VSETALLNEZ_W = 1405,
1419 VSETANYEQZ_B = 1406,
1420 VSETANYEQZ_D = 1407,
1421 VSETANYEQZ_H = 1408,
1422 VSETANYEQZ_W = 1409,
1423 VSETEQZ_V = 1410,
1424 VSETNEZ_V = 1411,
1425 VSHUF4I_B = 1412,
1426 VSHUF4I_D = 1413,
1427 VSHUF4I_H = 1414,
1428 VSHUF4I_W = 1415,
1429 VSHUF_B = 1416,
1430 VSHUF_D = 1417,
1431 VSHUF_H = 1418,
1432 VSHUF_W = 1419,
1433 VSIGNCOV_B = 1420,
1434 VSIGNCOV_D = 1421,
1435 VSIGNCOV_H = 1422,
1436 VSIGNCOV_W = 1423,
1437 VSLEI_B = 1424,
1438 VSLEI_BU = 1425,
1439 VSLEI_D = 1426,
1440 VSLEI_DU = 1427,
1441 VSLEI_H = 1428,
1442 VSLEI_HU = 1429,
1443 VSLEI_W = 1430,
1444 VSLEI_WU = 1431,
1445 VSLE_B = 1432,
1446 VSLE_BU = 1433,
1447 VSLE_D = 1434,
1448 VSLE_DU = 1435,
1449 VSLE_H = 1436,
1450 VSLE_HU = 1437,
1451 VSLE_W = 1438,
1452 VSLE_WU = 1439,
1453 VSLLI_B = 1440,
1454 VSLLI_D = 1441,
1455 VSLLI_H = 1442,
1456 VSLLI_W = 1443,
1457 VSLLWIL_DU_WU = 1444,
1458 VSLLWIL_D_W = 1445,
1459 VSLLWIL_HU_BU = 1446,
1460 VSLLWIL_H_B = 1447,
1461 VSLLWIL_WU_HU = 1448,
1462 VSLLWIL_W_H = 1449,
1463 VSLL_B = 1450,
1464 VSLL_D = 1451,
1465 VSLL_H = 1452,
1466 VSLL_W = 1453,
1467 VSLTI_B = 1454,
1468 VSLTI_BU = 1455,
1469 VSLTI_D = 1456,
1470 VSLTI_DU = 1457,
1471 VSLTI_H = 1458,
1472 VSLTI_HU = 1459,
1473 VSLTI_W = 1460,
1474 VSLTI_WU = 1461,
1475 VSLT_B = 1462,
1476 VSLT_BU = 1463,
1477 VSLT_D = 1464,
1478 VSLT_DU = 1465,
1479 VSLT_H = 1466,
1480 VSLT_HU = 1467,
1481 VSLT_W = 1468,
1482 VSLT_WU = 1469,
1483 VSRAI_B = 1470,
1484 VSRAI_D = 1471,
1485 VSRAI_H = 1472,
1486 VSRAI_W = 1473,
1487 VSRANI_B_H = 1474,
1488 VSRANI_D_Q = 1475,
1489 VSRANI_H_W = 1476,
1490 VSRANI_W_D = 1477,
1491 VSRAN_B_H = 1478,
1492 VSRAN_H_W = 1479,
1493 VSRAN_W_D = 1480,
1494 VSRARI_B = 1481,
1495 VSRARI_D = 1482,
1496 VSRARI_H = 1483,
1497 VSRARI_W = 1484,
1498 VSRARNI_B_H = 1485,
1499 VSRARNI_D_Q = 1486,
1500 VSRARNI_H_W = 1487,
1501 VSRARNI_W_D = 1488,
1502 VSRARN_B_H = 1489,
1503 VSRARN_H_W = 1490,
1504 VSRARN_W_D = 1491,
1505 VSRAR_B = 1492,
1506 VSRAR_D = 1493,
1507 VSRAR_H = 1494,
1508 VSRAR_W = 1495,
1509 VSRA_B = 1496,
1510 VSRA_D = 1497,
1511 VSRA_H = 1498,
1512 VSRA_W = 1499,
1513 VSRLI_B = 1500,
1514 VSRLI_D = 1501,
1515 VSRLI_H = 1502,
1516 VSRLI_W = 1503,
1517 VSRLNI_B_H = 1504,
1518 VSRLNI_D_Q = 1505,
1519 VSRLNI_H_W = 1506,
1520 VSRLNI_W_D = 1507,
1521 VSRLN_B_H = 1508,
1522 VSRLN_H_W = 1509,
1523 VSRLN_W_D = 1510,
1524 VSRLRI_B = 1511,
1525 VSRLRI_D = 1512,
1526 VSRLRI_H = 1513,
1527 VSRLRI_W = 1514,
1528 VSRLRNI_B_H = 1515,
1529 VSRLRNI_D_Q = 1516,
1530 VSRLRNI_H_W = 1517,
1531 VSRLRNI_W_D = 1518,
1532 VSRLRN_B_H = 1519,
1533 VSRLRN_H_W = 1520,
1534 VSRLRN_W_D = 1521,
1535 VSRLR_B = 1522,
1536 VSRLR_D = 1523,
1537 VSRLR_H = 1524,
1538 VSRLR_W = 1525,
1539 VSRL_B = 1526,
1540 VSRL_D = 1527,
1541 VSRL_H = 1528,
1542 VSRL_W = 1529,
1543 VSSRANI_BU_H = 1530,
1544 VSSRANI_B_H = 1531,
1545 VSSRANI_DU_Q = 1532,
1546 VSSRANI_D_Q = 1533,
1547 VSSRANI_HU_W = 1534,
1548 VSSRANI_H_W = 1535,
1549 VSSRANI_WU_D = 1536,
1550 VSSRANI_W_D = 1537,
1551 VSSRAN_BU_H = 1538,
1552 VSSRAN_B_H = 1539,
1553 VSSRAN_HU_W = 1540,
1554 VSSRAN_H_W = 1541,
1555 VSSRAN_WU_D = 1542,
1556 VSSRAN_W_D = 1543,
1557 VSSRARNI_BU_H = 1544,
1558 VSSRARNI_B_H = 1545,
1559 VSSRARNI_DU_Q = 1546,
1560 VSSRARNI_D_Q = 1547,
1561 VSSRARNI_HU_W = 1548,
1562 VSSRARNI_H_W = 1549,
1563 VSSRARNI_WU_D = 1550,
1564 VSSRARNI_W_D = 1551,
1565 VSSRARN_BU_H = 1552,
1566 VSSRARN_B_H = 1553,
1567 VSSRARN_HU_W = 1554,
1568 VSSRARN_H_W = 1555,
1569 VSSRARN_WU_D = 1556,
1570 VSSRARN_W_D = 1557,
1571 VSSRLNI_BU_H = 1558,
1572 VSSRLNI_B_H = 1559,
1573 VSSRLNI_DU_Q = 1560,
1574 VSSRLNI_D_Q = 1561,
1575 VSSRLNI_HU_W = 1562,
1576 VSSRLNI_H_W = 1563,
1577 VSSRLNI_WU_D = 1564,
1578 VSSRLNI_W_D = 1565,
1579 VSSRLN_BU_H = 1566,
1580 VSSRLN_B_H = 1567,
1581 VSSRLN_HU_W = 1568,
1582 VSSRLN_H_W = 1569,
1583 VSSRLN_WU_D = 1570,
1584 VSSRLN_W_D = 1571,
1585 VSSRLRNI_BU_H = 1572,
1586 VSSRLRNI_B_H = 1573,
1587 VSSRLRNI_DU_Q = 1574,
1588 VSSRLRNI_D_Q = 1575,
1589 VSSRLRNI_HU_W = 1576,
1590 VSSRLRNI_H_W = 1577,
1591 VSSRLRNI_WU_D = 1578,
1592 VSSRLRNI_W_D = 1579,
1593 VSSRLRN_BU_H = 1580,
1594 VSSRLRN_B_H = 1581,
1595 VSSRLRN_HU_W = 1582,
1596 VSSRLRN_H_W = 1583,
1597 VSSRLRN_WU_D = 1584,
1598 VSSRLRN_W_D = 1585,
1599 VSSUB_B = 1586,
1600 VSSUB_BU = 1587,
1601 VSSUB_D = 1588,
1602 VSSUB_DU = 1589,
1603 VSSUB_H = 1590,
1604 VSSUB_HU = 1591,
1605 VSSUB_W = 1592,
1606 VSSUB_WU = 1593,
1607 VST = 1594,
1608 VSTELM_B = 1595,
1609 VSTELM_D = 1596,
1610 VSTELM_H = 1597,
1611 VSTELM_W = 1598,
1612 VSTX = 1599,
1613 VSUBI_BU = 1600,
1614 VSUBI_DU = 1601,
1615 VSUBI_HU = 1602,
1616 VSUBI_WU = 1603,
1617 VSUBWEV_D_W = 1604,
1618 VSUBWEV_D_WU = 1605,
1619 VSUBWEV_H_B = 1606,
1620 VSUBWEV_H_BU = 1607,
1621 VSUBWEV_Q_D = 1608,
1622 VSUBWEV_Q_DU = 1609,
1623 VSUBWEV_W_H = 1610,
1624 VSUBWEV_W_HU = 1611,
1625 VSUBWOD_D_W = 1612,
1626 VSUBWOD_D_WU = 1613,
1627 VSUBWOD_H_B = 1614,
1628 VSUBWOD_H_BU = 1615,
1629 VSUBWOD_Q_D = 1616,
1630 VSUBWOD_Q_DU = 1617,
1631 VSUBWOD_W_H = 1618,
1632 VSUBWOD_W_HU = 1619,
1633 VSUB_B = 1620,
1634 VSUB_D = 1621,
1635 VSUB_H = 1622,
1636 VSUB_Q = 1623,
1637 VSUB_W = 1624,
1638 VXORI_B = 1625,
1639 VXOR_V = 1626,
1640 X86ADC_B = 1627,
1641 X86ADC_D = 1628,
1642 X86ADC_H = 1629,
1643 X86ADC_W = 1630,
1644 X86ADD_B = 1631,
1645 X86ADD_D = 1632,
1646 X86ADD_DU = 1633,
1647 X86ADD_H = 1634,
1648 X86ADD_W = 1635,
1649 X86ADD_WU = 1636,
1650 X86AND_B = 1637,
1651 X86AND_D = 1638,
1652 X86AND_H = 1639,
1653 X86AND_W = 1640,
1654 X86CLRTM = 1641,
1655 X86DECTOP = 1642,
1656 X86DEC_B = 1643,
1657 X86DEC_D = 1644,
1658 X86DEC_H = 1645,
1659 X86DEC_W = 1646,
1660 X86INCTOP = 1647,
1661 X86INC_B = 1648,
1662 X86INC_D = 1649,
1663 X86INC_H = 1650,
1664 X86INC_W = 1651,
1665 X86MFFLAG = 1652,
1666 X86MFTOP = 1653,
1667 X86MTFLAG = 1654,
1668 X86MTTOP = 1655,
1669 X86MUL_B = 1656,
1670 X86MUL_BU = 1657,
1671 X86MUL_D = 1658,
1672 X86MUL_DU = 1659,
1673 X86MUL_H = 1660,
1674 X86MUL_HU = 1661,
1675 X86MUL_W = 1662,
1676 X86MUL_WU = 1663,
1677 X86OR_B = 1664,
1678 X86OR_D = 1665,
1679 X86OR_H = 1666,
1680 X86OR_W = 1667,
1681 X86RCLI_B = 1668,
1682 X86RCLI_D = 1669,
1683 X86RCLI_H = 1670,
1684 X86RCLI_W = 1671,
1685 X86RCL_B = 1672,
1686 X86RCL_D = 1673,
1687 X86RCL_H = 1674,
1688 X86RCL_W = 1675,
1689 X86RCRI_B = 1676,
1690 X86RCRI_D = 1677,
1691 X86RCRI_H = 1678,
1692 X86RCRI_W = 1679,
1693 X86RCR_B = 1680,
1694 X86RCR_D = 1681,
1695 X86RCR_H = 1682,
1696 X86RCR_W = 1683,
1697 X86ROTLI_B = 1684,
1698 X86ROTLI_D = 1685,
1699 X86ROTLI_H = 1686,
1700 X86ROTLI_W = 1687,
1701 X86ROTL_B = 1688,
1702 X86ROTL_D = 1689,
1703 X86ROTL_H = 1690,
1704 X86ROTL_W = 1691,
1705 X86ROTRI_B = 1692,
1706 X86ROTRI_D = 1693,
1707 X86ROTRI_H = 1694,
1708 X86ROTRI_W = 1695,
1709 X86ROTR_B = 1696,
1710 X86ROTR_D = 1697,
1711 X86ROTR_H = 1698,
1712 X86ROTR_W = 1699,
1713 X86SBC_B = 1700,
1714 X86SBC_D = 1701,
1715 X86SBC_H = 1702,
1716 X86SBC_W = 1703,
1717 X86SETTAG = 1704,
1718 X86SETTM = 1705,
1719 X86SLLI_B = 1706,
1720 X86SLLI_D = 1707,
1721 X86SLLI_H = 1708,
1722 X86SLLI_W = 1709,
1723 X86SLL_B = 1710,
1724 X86SLL_D = 1711,
1725 X86SLL_H = 1712,
1726 X86SLL_W = 1713,
1727 X86SRAI_B = 1714,
1728 X86SRAI_D = 1715,
1729 X86SRAI_H = 1716,
1730 X86SRAI_W = 1717,
1731 X86SRA_B = 1718,
1732 X86SRA_D = 1719,
1733 X86SRA_H = 1720,
1734 X86SRA_W = 1721,
1735 X86SRLI_B = 1722,
1736 X86SRLI_D = 1723,
1737 X86SRLI_H = 1724,
1738 X86SRLI_W = 1725,
1739 X86SRL_B = 1726,
1740 X86SRL_D = 1727,
1741 X86SRL_H = 1728,
1742 X86SRL_W = 1729,
1743 X86SUB_B = 1730,
1744 X86SUB_D = 1731,
1745 X86SUB_DU = 1732,
1746 X86SUB_H = 1733,
1747 X86SUB_W = 1734,
1748 X86SUB_WU = 1735,
1749 X86XOR_B = 1736,
1750 X86XOR_D = 1737,
1751 X86XOR_H = 1738,
1752 X86XOR_W = 1739,
1753 XOR = 1740,
1754 XORI = 1741,
1755 XVABSD_B = 1742,
1756 XVABSD_BU = 1743,
1757 XVABSD_D = 1744,
1758 XVABSD_DU = 1745,
1759 XVABSD_H = 1746,
1760 XVABSD_HU = 1747,
1761 XVABSD_W = 1748,
1762 XVABSD_WU = 1749,
1763 XVADDA_B = 1750,
1764 XVADDA_D = 1751,
1765 XVADDA_H = 1752,
1766 XVADDA_W = 1753,
1767 XVADDI_BU = 1754,
1768 XVADDI_DU = 1755,
1769 XVADDI_HU = 1756,
1770 XVADDI_WU = 1757,
1771 XVADDWEV_D_W = 1758,
1772 XVADDWEV_D_WU = 1759,
1773 XVADDWEV_D_WU_W = 1760,
1774 XVADDWEV_H_B = 1761,
1775 XVADDWEV_H_BU = 1762,
1776 XVADDWEV_H_BU_B = 1763,
1777 XVADDWEV_Q_D = 1764,
1778 XVADDWEV_Q_DU = 1765,
1779 XVADDWEV_Q_DU_D = 1766,
1780 XVADDWEV_W_H = 1767,
1781 XVADDWEV_W_HU = 1768,
1782 XVADDWEV_W_HU_H = 1769,
1783 XVADDWOD_D_W = 1770,
1784 XVADDWOD_D_WU = 1771,
1785 XVADDWOD_D_WU_W = 1772,
1786 XVADDWOD_H_B = 1773,
1787 XVADDWOD_H_BU = 1774,
1788 XVADDWOD_H_BU_B = 1775,
1789 XVADDWOD_Q_D = 1776,
1790 XVADDWOD_Q_DU = 1777,
1791 XVADDWOD_Q_DU_D = 1778,
1792 XVADDWOD_W_H = 1779,
1793 XVADDWOD_W_HU = 1780,
1794 XVADDWOD_W_HU_H = 1781,
1795 XVADD_B = 1782,
1796 XVADD_D = 1783,
1797 XVADD_H = 1784,
1798 XVADD_Q = 1785,
1799 XVADD_W = 1786,
1800 XVANDI_B = 1787,
1801 XVANDN_V = 1788,
1802 XVAND_V = 1789,
1803 XVAVGR_B = 1790,
1804 XVAVGR_BU = 1791,
1805 XVAVGR_D = 1792,
1806 XVAVGR_DU = 1793,
1807 XVAVGR_H = 1794,
1808 XVAVGR_HU = 1795,
1809 XVAVGR_W = 1796,
1810 XVAVGR_WU = 1797,
1811 XVAVG_B = 1798,
1812 XVAVG_BU = 1799,
1813 XVAVG_D = 1800,
1814 XVAVG_DU = 1801,
1815 XVAVG_H = 1802,
1816 XVAVG_HU = 1803,
1817 XVAVG_W = 1804,
1818 XVAVG_WU = 1805,
1819 XVBITCLRI_B = 1806,
1820 XVBITCLRI_D = 1807,
1821 XVBITCLRI_H = 1808,
1822 XVBITCLRI_W = 1809,
1823 XVBITCLR_B = 1810,
1824 XVBITCLR_D = 1811,
1825 XVBITCLR_H = 1812,
1826 XVBITCLR_W = 1813,
1827 XVBITREVI_B = 1814,
1828 XVBITREVI_D = 1815,
1829 XVBITREVI_H = 1816,
1830 XVBITREVI_W = 1817,
1831 XVBITREV_B = 1818,
1832 XVBITREV_D = 1819,
1833 XVBITREV_H = 1820,
1834 XVBITREV_W = 1821,
1835 XVBITSELI_B = 1822,
1836 XVBITSEL_V = 1823,
1837 XVBITSETI_B = 1824,
1838 XVBITSETI_D = 1825,
1839 XVBITSETI_H = 1826,
1840 XVBITSETI_W = 1827,
1841 XVBITSET_B = 1828,
1842 XVBITSET_D = 1829,
1843 XVBITSET_H = 1830,
1844 XVBITSET_W = 1831,
1845 XVBSLL_V = 1832,
1846 XVBSRL_V = 1833,
1847 XVCLO_B = 1834,
1848 XVCLO_D = 1835,
1849 XVCLO_H = 1836,
1850 XVCLO_W = 1837,
1851 XVCLZ_B = 1838,
1852 XVCLZ_D = 1839,
1853 XVCLZ_H = 1840,
1854 XVCLZ_W = 1841,
1855 XVDIV_B = 1842,
1856 XVDIV_BU = 1843,
1857 XVDIV_D = 1844,
1858 XVDIV_DU = 1845,
1859 XVDIV_H = 1846,
1860 XVDIV_HU = 1847,
1861 XVDIV_W = 1848,
1862 XVDIV_WU = 1849,
1863 XVEXTH_DU_WU = 1850,
1864 XVEXTH_D_W = 1851,
1865 XVEXTH_HU_BU = 1852,
1866 XVEXTH_H_B = 1853,
1867 XVEXTH_QU_DU = 1854,
1868 XVEXTH_Q_D = 1855,
1869 XVEXTH_WU_HU = 1856,
1870 XVEXTH_W_H = 1857,
1871 XVEXTL_QU_DU = 1858,
1872 XVEXTL_Q_D = 1859,
1873 XVEXTRINS_B = 1860,
1874 XVEXTRINS_D = 1861,
1875 XVEXTRINS_H = 1862,
1876 XVEXTRINS_W = 1863,
1877 XVFADD_D = 1864,
1878 XVFADD_S = 1865,
1879 XVFCLASS_D = 1866,
1880 XVFCLASS_S = 1867,
1881 XVFCMP_CAF_D = 1868,
1882 XVFCMP_CAF_S = 1869,
1883 XVFCMP_CEQ_D = 1870,
1884 XVFCMP_CEQ_S = 1871,
1885 XVFCMP_CLE_D = 1872,
1886 XVFCMP_CLE_S = 1873,
1887 XVFCMP_CLT_D = 1874,
1888 XVFCMP_CLT_S = 1875,
1889 XVFCMP_CNE_D = 1876,
1890 XVFCMP_CNE_S = 1877,
1891 XVFCMP_COR_D = 1878,
1892 XVFCMP_COR_S = 1879,
1893 XVFCMP_CUEQ_D = 1880,
1894 XVFCMP_CUEQ_S = 1881,
1895 XVFCMP_CULE_D = 1882,
1896 XVFCMP_CULE_S = 1883,
1897 XVFCMP_CULT_D = 1884,
1898 XVFCMP_CULT_S = 1885,
1899 XVFCMP_CUNE_D = 1886,
1900 XVFCMP_CUNE_S = 1887,
1901 XVFCMP_CUN_D = 1888,
1902 XVFCMP_CUN_S = 1889,
1903 XVFCMP_SAF_D = 1890,
1904 XVFCMP_SAF_S = 1891,
1905 XVFCMP_SEQ_D = 1892,
1906 XVFCMP_SEQ_S = 1893,
1907 XVFCMP_SLE_D = 1894,
1908 XVFCMP_SLE_S = 1895,
1909 XVFCMP_SLT_D = 1896,
1910 XVFCMP_SLT_S = 1897,
1911 XVFCMP_SNE_D = 1898,
1912 XVFCMP_SNE_S = 1899,
1913 XVFCMP_SOR_D = 1900,
1914 XVFCMP_SOR_S = 1901,
1915 XVFCMP_SUEQ_D = 1902,
1916 XVFCMP_SUEQ_S = 1903,
1917 XVFCMP_SULE_D = 1904,
1918 XVFCMP_SULE_S = 1905,
1919 XVFCMP_SULT_D = 1906,
1920 XVFCMP_SULT_S = 1907,
1921 XVFCMP_SUNE_D = 1908,
1922 XVFCMP_SUNE_S = 1909,
1923 XVFCMP_SUN_D = 1910,
1924 XVFCMP_SUN_S = 1911,
1925 XVFCVTH_D_S = 1912,
1926 XVFCVTH_S_H = 1913,
1927 XVFCVTL_D_S = 1914,
1928 XVFCVTL_S_H = 1915,
1929 XVFCVT_H_S = 1916,
1930 XVFCVT_S_D = 1917,
1931 XVFDIV_D = 1918,
1932 XVFDIV_S = 1919,
1933 XVFFINTH_D_W = 1920,
1934 XVFFINTL_D_W = 1921,
1935 XVFFINT_D_L = 1922,
1936 XVFFINT_D_LU = 1923,
1937 XVFFINT_S_L = 1924,
1938 XVFFINT_S_W = 1925,
1939 XVFFINT_S_WU = 1926,
1940 XVFLOGB_D = 1927,
1941 XVFLOGB_S = 1928,
1942 XVFMADD_D = 1929,
1943 XVFMADD_S = 1930,
1944 XVFMAXA_D = 1931,
1945 XVFMAXA_S = 1932,
1946 XVFMAX_D = 1933,
1947 XVFMAX_S = 1934,
1948 XVFMINA_D = 1935,
1949 XVFMINA_S = 1936,
1950 XVFMIN_D = 1937,
1951 XVFMIN_S = 1938,
1952 XVFMSUB_D = 1939,
1953 XVFMSUB_S = 1940,
1954 XVFMUL_D = 1941,
1955 XVFMUL_S = 1942,
1956 XVFNMADD_D = 1943,
1957 XVFNMADD_S = 1944,
1958 XVFNMSUB_D = 1945,
1959 XVFNMSUB_S = 1946,
1960 XVFRECIPE_D = 1947,
1961 XVFRECIPE_S = 1948,
1962 XVFRECIP_D = 1949,
1963 XVFRECIP_S = 1950,
1964 XVFRINTRM_D = 1951,
1965 XVFRINTRM_S = 1952,
1966 XVFRINTRNE_D = 1953,
1967 XVFRINTRNE_S = 1954,
1968 XVFRINTRP_D = 1955,
1969 XVFRINTRP_S = 1956,
1970 XVFRINTRZ_D = 1957,
1971 XVFRINTRZ_S = 1958,
1972 XVFRINT_D = 1959,
1973 XVFRINT_S = 1960,
1974 XVFRSQRTE_D = 1961,
1975 XVFRSQRTE_S = 1962,
1976 XVFRSQRT_D = 1963,
1977 XVFRSQRT_S = 1964,
1978 XVFRSTPI_B = 1965,
1979 XVFRSTPI_H = 1966,
1980 XVFRSTP_B = 1967,
1981 XVFRSTP_H = 1968,
1982 XVFSQRT_D = 1969,
1983 XVFSQRT_S = 1970,
1984 XVFSUB_D = 1971,
1985 XVFSUB_S = 1972,
1986 XVFTINTH_L_S = 1973,
1987 XVFTINTL_L_S = 1974,
1988 XVFTINTRMH_L_S = 1975,
1989 XVFTINTRML_L_S = 1976,
1990 XVFTINTRM_L_D = 1977,
1991 XVFTINTRM_W_D = 1978,
1992 XVFTINTRM_W_S = 1979,
1993 XVFTINTRNEH_L_S = 1980,
1994 XVFTINTRNEL_L_S = 1981,
1995 XVFTINTRNE_L_D = 1982,
1996 XVFTINTRNE_W_D = 1983,
1997 XVFTINTRNE_W_S = 1984,
1998 XVFTINTRPH_L_S = 1985,
1999 XVFTINTRPL_L_S = 1986,
2000 XVFTINTRP_L_D = 1987,
2001 XVFTINTRP_W_D = 1988,
2002 XVFTINTRP_W_S = 1989,
2003 XVFTINTRZH_L_S = 1990,
2004 XVFTINTRZL_L_S = 1991,
2005 XVFTINTRZ_LU_D = 1992,
2006 XVFTINTRZ_L_D = 1993,
2007 XVFTINTRZ_WU_S = 1994,
2008 XVFTINTRZ_W_D = 1995,
2009 XVFTINTRZ_W_S = 1996,
2010 XVFTINT_LU_D = 1997,
2011 XVFTINT_L_D = 1998,
2012 XVFTINT_WU_S = 1999,
2013 XVFTINT_W_D = 2000,
2014 XVFTINT_W_S = 2001,
2015 XVHADDW_DU_WU = 2002,
2016 XVHADDW_D_W = 2003,
2017 XVHADDW_HU_BU = 2004,
2018 XVHADDW_H_B = 2005,
2019 XVHADDW_QU_DU = 2006,
2020 XVHADDW_Q_D = 2007,
2021 XVHADDW_WU_HU = 2008,
2022 XVHADDW_W_H = 2009,
2023 XVHSELI_D = 2010,
2024 XVHSUBW_DU_WU = 2011,
2025 XVHSUBW_D_W = 2012,
2026 XVHSUBW_HU_BU = 2013,
2027 XVHSUBW_H_B = 2014,
2028 XVHSUBW_QU_DU = 2015,
2029 XVHSUBW_Q_D = 2016,
2030 XVHSUBW_WU_HU = 2017,
2031 XVHSUBW_W_H = 2018,
2032 XVILVH_B = 2019,
2033 XVILVH_D = 2020,
2034 XVILVH_H = 2021,
2035 XVILVH_W = 2022,
2036 XVILVL_B = 2023,
2037 XVILVL_D = 2024,
2038 XVILVL_H = 2025,
2039 XVILVL_W = 2026,
2040 XVINSGR2VR_D = 2027,
2041 XVINSGR2VR_W = 2028,
2042 XVINSVE0_D = 2029,
2043 XVINSVE0_W = 2030,
2044 XVLD = 2031,
2045 XVLDI = 2032,
2046 XVLDREPL_B = 2033,
2047 XVLDREPL_D = 2034,
2048 XVLDREPL_H = 2035,
2049 XVLDREPL_W = 2036,
2050 XVLDX = 2037,
2051 XVMADDWEV_D_W = 2038,
2052 XVMADDWEV_D_WU = 2039,
2053 XVMADDWEV_D_WU_W = 2040,
2054 XVMADDWEV_H_B = 2041,
2055 XVMADDWEV_H_BU = 2042,
2056 XVMADDWEV_H_BU_B = 2043,
2057 XVMADDWEV_Q_D = 2044,
2058 XVMADDWEV_Q_DU = 2045,
2059 XVMADDWEV_Q_DU_D = 2046,
2060 XVMADDWEV_W_H = 2047,
2061 XVMADDWEV_W_HU = 2048,
2062 XVMADDWEV_W_HU_H = 2049,
2063 XVMADDWOD_D_W = 2050,
2064 XVMADDWOD_D_WU = 2051,
2065 XVMADDWOD_D_WU_W = 2052,
2066 XVMADDWOD_H_B = 2053,
2067 XVMADDWOD_H_BU = 2054,
2068 XVMADDWOD_H_BU_B = 2055,
2069 XVMADDWOD_Q_D = 2056,
2070 XVMADDWOD_Q_DU = 2057,
2071 XVMADDWOD_Q_DU_D = 2058,
2072 XVMADDWOD_W_H = 2059,
2073 XVMADDWOD_W_HU = 2060,
2074 XVMADDWOD_W_HU_H = 2061,
2075 XVMADD_B = 2062,
2076 XVMADD_D = 2063,
2077 XVMADD_H = 2064,
2078 XVMADD_W = 2065,
2079 XVMAXI_B = 2066,
2080 XVMAXI_BU = 2067,
2081 XVMAXI_D = 2068,
2082 XVMAXI_DU = 2069,
2083 XVMAXI_H = 2070,
2084 XVMAXI_HU = 2071,
2085 XVMAXI_W = 2072,
2086 XVMAXI_WU = 2073,
2087 XVMAX_B = 2074,
2088 XVMAX_BU = 2075,
2089 XVMAX_D = 2076,
2090 XVMAX_DU = 2077,
2091 XVMAX_H = 2078,
2092 XVMAX_HU = 2079,
2093 XVMAX_W = 2080,
2094 XVMAX_WU = 2081,
2095 XVMINI_B = 2082,
2096 XVMINI_BU = 2083,
2097 XVMINI_D = 2084,
2098 XVMINI_DU = 2085,
2099 XVMINI_H = 2086,
2100 XVMINI_HU = 2087,
2101 XVMINI_W = 2088,
2102 XVMINI_WU = 2089,
2103 XVMIN_B = 2090,
2104 XVMIN_BU = 2091,
2105 XVMIN_D = 2092,
2106 XVMIN_DU = 2093,
2107 XVMIN_H = 2094,
2108 XVMIN_HU = 2095,
2109 XVMIN_W = 2096,
2110 XVMIN_WU = 2097,
2111 XVMOD_B = 2098,
2112 XVMOD_BU = 2099,
2113 XVMOD_D = 2100,
2114 XVMOD_DU = 2101,
2115 XVMOD_H = 2102,
2116 XVMOD_HU = 2103,
2117 XVMOD_W = 2104,
2118 XVMOD_WU = 2105,
2119 XVMSKGEZ_B = 2106,
2120 XVMSKLTZ_B = 2107,
2121 XVMSKLTZ_D = 2108,
2122 XVMSKLTZ_H = 2109,
2123 XVMSKLTZ_W = 2110,
2124 XVMSKNZ_B = 2111,
2125 XVMSUB_B = 2112,
2126 XVMSUB_D = 2113,
2127 XVMSUB_H = 2114,
2128 XVMSUB_W = 2115,
2129 XVMUH_B = 2116,
2130 XVMUH_BU = 2117,
2131 XVMUH_D = 2118,
2132 XVMUH_DU = 2119,
2133 XVMUH_H = 2120,
2134 XVMUH_HU = 2121,
2135 XVMUH_W = 2122,
2136 XVMUH_WU = 2123,
2137 XVMULWEV_D_W = 2124,
2138 XVMULWEV_D_WU = 2125,
2139 XVMULWEV_D_WU_W = 2126,
2140 XVMULWEV_H_B = 2127,
2141 XVMULWEV_H_BU = 2128,
2142 XVMULWEV_H_BU_B = 2129,
2143 XVMULWEV_Q_D = 2130,
2144 XVMULWEV_Q_DU = 2131,
2145 XVMULWEV_Q_DU_D = 2132,
2146 XVMULWEV_W_H = 2133,
2147 XVMULWEV_W_HU = 2134,
2148 XVMULWEV_W_HU_H = 2135,
2149 XVMULWOD_D_W = 2136,
2150 XVMULWOD_D_WU = 2137,
2151 XVMULWOD_D_WU_W = 2138,
2152 XVMULWOD_H_B = 2139,
2153 XVMULWOD_H_BU = 2140,
2154 XVMULWOD_H_BU_B = 2141,
2155 XVMULWOD_Q_D = 2142,
2156 XVMULWOD_Q_DU = 2143,
2157 XVMULWOD_Q_DU_D = 2144,
2158 XVMULWOD_W_H = 2145,
2159 XVMULWOD_W_HU = 2146,
2160 XVMULWOD_W_HU_H = 2147,
2161 XVMUL_B = 2148,
2162 XVMUL_D = 2149,
2163 XVMUL_H = 2150,
2164 XVMUL_W = 2151,
2165 XVNEG_B = 2152,
2166 XVNEG_D = 2153,
2167 XVNEG_H = 2154,
2168 XVNEG_W = 2155,
2169 XVNORI_B = 2156,
2170 XVNOR_V = 2157,
2171 XVORI_B = 2158,
2172 XVORN_V = 2159,
2173 XVOR_V = 2160,
2174 XVPACKEV_B = 2161,
2175 XVPACKEV_D = 2162,
2176 XVPACKEV_H = 2163,
2177 XVPACKEV_W = 2164,
2178 XVPACKOD_B = 2165,
2179 XVPACKOD_D = 2166,
2180 XVPACKOD_H = 2167,
2181 XVPACKOD_W = 2168,
2182 XVPCNT_B = 2169,
2183 XVPCNT_D = 2170,
2184 XVPCNT_H = 2171,
2185 XVPCNT_W = 2172,
2186 XVPERMI_D = 2173,
2187 XVPERMI_Q = 2174,
2188 XVPERMI_W = 2175,
2189 XVPERM_W = 2176,
2190 XVPICKEV_B = 2177,
2191 XVPICKEV_D = 2178,
2192 XVPICKEV_H = 2179,
2193 XVPICKEV_W = 2180,
2194 XVPICKOD_B = 2181,
2195 XVPICKOD_D = 2182,
2196 XVPICKOD_H = 2183,
2197 XVPICKOD_W = 2184,
2198 XVPICKVE2GR_D = 2185,
2199 XVPICKVE2GR_DU = 2186,
2200 XVPICKVE2GR_W = 2187,
2201 XVPICKVE2GR_WU = 2188,
2202 XVPICKVE_D = 2189,
2203 XVPICKVE_W = 2190,
2204 XVREPL128VEI_B = 2191,
2205 XVREPL128VEI_D = 2192,
2206 XVREPL128VEI_H = 2193,
2207 XVREPL128VEI_W = 2194,
2208 XVREPLGR2VR_B = 2195,
2209 XVREPLGR2VR_D = 2196,
2210 XVREPLGR2VR_H = 2197,
2211 XVREPLGR2VR_W = 2198,
2212 XVREPLVE0_B = 2199,
2213 XVREPLVE0_D = 2200,
2214 XVREPLVE0_H = 2201,
2215 XVREPLVE0_Q = 2202,
2216 XVREPLVE0_W = 2203,
2217 XVREPLVE_B = 2204,
2218 XVREPLVE_D = 2205,
2219 XVREPLVE_H = 2206,
2220 XVREPLVE_W = 2207,
2221 XVROTRI_B = 2208,
2222 XVROTRI_D = 2209,
2223 XVROTRI_H = 2210,
2224 XVROTRI_W = 2211,
2225 XVROTR_B = 2212,
2226 XVROTR_D = 2213,
2227 XVROTR_H = 2214,
2228 XVROTR_W = 2215,
2229 XVSADD_B = 2216,
2230 XVSADD_BU = 2217,
2231 XVSADD_D = 2218,
2232 XVSADD_DU = 2219,
2233 XVSADD_H = 2220,
2234 XVSADD_HU = 2221,
2235 XVSADD_W = 2222,
2236 XVSADD_WU = 2223,
2237 XVSAT_B = 2224,
2238 XVSAT_BU = 2225,
2239 XVSAT_D = 2226,
2240 XVSAT_DU = 2227,
2241 XVSAT_H = 2228,
2242 XVSAT_HU = 2229,
2243 XVSAT_W = 2230,
2244 XVSAT_WU = 2231,
2245 XVSEQI_B = 2232,
2246 XVSEQI_D = 2233,
2247 XVSEQI_H = 2234,
2248 XVSEQI_W = 2235,
2249 XVSEQ_B = 2236,
2250 XVSEQ_D = 2237,
2251 XVSEQ_H = 2238,
2252 XVSEQ_W = 2239,
2253 XVSETALLNEZ_B = 2240,
2254 XVSETALLNEZ_D = 2241,
2255 XVSETALLNEZ_H = 2242,
2256 XVSETALLNEZ_W = 2243,
2257 XVSETANYEQZ_B = 2244,
2258 XVSETANYEQZ_D = 2245,
2259 XVSETANYEQZ_H = 2246,
2260 XVSETANYEQZ_W = 2247,
2261 XVSETEQZ_V = 2248,
2262 XVSETNEZ_V = 2249,
2263 XVSHUF4I_B = 2250,
2264 XVSHUF4I_D = 2251,
2265 XVSHUF4I_H = 2252,
2266 XVSHUF4I_W = 2253,
2267 XVSHUF_B = 2254,
2268 XVSHUF_D = 2255,
2269 XVSHUF_H = 2256,
2270 XVSHUF_W = 2257,
2271 XVSIGNCOV_B = 2258,
2272 XVSIGNCOV_D = 2259,
2273 XVSIGNCOV_H = 2260,
2274 XVSIGNCOV_W = 2261,
2275 XVSLEI_B = 2262,
2276 XVSLEI_BU = 2263,
2277 XVSLEI_D = 2264,
2278 XVSLEI_DU = 2265,
2279 XVSLEI_H = 2266,
2280 XVSLEI_HU = 2267,
2281 XVSLEI_W = 2268,
2282 XVSLEI_WU = 2269,
2283 XVSLE_B = 2270,
2284 XVSLE_BU = 2271,
2285 XVSLE_D = 2272,
2286 XVSLE_DU = 2273,
2287 XVSLE_H = 2274,
2288 XVSLE_HU = 2275,
2289 XVSLE_W = 2276,
2290 XVSLE_WU = 2277,
2291 XVSLLI_B = 2278,
2292 XVSLLI_D = 2279,
2293 XVSLLI_H = 2280,
2294 XVSLLI_W = 2281,
2295 XVSLLWIL_DU_WU = 2282,
2296 XVSLLWIL_D_W = 2283,
2297 XVSLLWIL_HU_BU = 2284,
2298 XVSLLWIL_H_B = 2285,
2299 XVSLLWIL_WU_HU = 2286,
2300 XVSLLWIL_W_H = 2287,
2301 XVSLL_B = 2288,
2302 XVSLL_D = 2289,
2303 XVSLL_H = 2290,
2304 XVSLL_W = 2291,
2305 XVSLTI_B = 2292,
2306 XVSLTI_BU = 2293,
2307 XVSLTI_D = 2294,
2308 XVSLTI_DU = 2295,
2309 XVSLTI_H = 2296,
2310 XVSLTI_HU = 2297,
2311 XVSLTI_W = 2298,
2312 XVSLTI_WU = 2299,
2313 XVSLT_B = 2300,
2314 XVSLT_BU = 2301,
2315 XVSLT_D = 2302,
2316 XVSLT_DU = 2303,
2317 XVSLT_H = 2304,
2318 XVSLT_HU = 2305,
2319 XVSLT_W = 2306,
2320 XVSLT_WU = 2307,
2321 XVSRAI_B = 2308,
2322 XVSRAI_D = 2309,
2323 XVSRAI_H = 2310,
2324 XVSRAI_W = 2311,
2325 XVSRANI_B_H = 2312,
2326 XVSRANI_D_Q = 2313,
2327 XVSRANI_H_W = 2314,
2328 XVSRANI_W_D = 2315,
2329 XVSRAN_B_H = 2316,
2330 XVSRAN_H_W = 2317,
2331 XVSRAN_W_D = 2318,
2332 XVSRARI_B = 2319,
2333 XVSRARI_D = 2320,
2334 XVSRARI_H = 2321,
2335 XVSRARI_W = 2322,
2336 XVSRARNI_B_H = 2323,
2337 XVSRARNI_D_Q = 2324,
2338 XVSRARNI_H_W = 2325,
2339 XVSRARNI_W_D = 2326,
2340 XVSRARN_B_H = 2327,
2341 XVSRARN_H_W = 2328,
2342 XVSRARN_W_D = 2329,
2343 XVSRAR_B = 2330,
2344 XVSRAR_D = 2331,
2345 XVSRAR_H = 2332,
2346 XVSRAR_W = 2333,
2347 XVSRA_B = 2334,
2348 XVSRA_D = 2335,
2349 XVSRA_H = 2336,
2350 XVSRA_W = 2337,
2351 XVSRLI_B = 2338,
2352 XVSRLI_D = 2339,
2353 XVSRLI_H = 2340,
2354 XVSRLI_W = 2341,
2355 XVSRLNI_B_H = 2342,
2356 XVSRLNI_D_Q = 2343,
2357 XVSRLNI_H_W = 2344,
2358 XVSRLNI_W_D = 2345,
2359 XVSRLN_B_H = 2346,
2360 XVSRLN_H_W = 2347,
2361 XVSRLN_W_D = 2348,
2362 XVSRLRI_B = 2349,
2363 XVSRLRI_D = 2350,
2364 XVSRLRI_H = 2351,
2365 XVSRLRI_W = 2352,
2366 XVSRLRNI_B_H = 2353,
2367 XVSRLRNI_D_Q = 2354,
2368 XVSRLRNI_H_W = 2355,
2369 XVSRLRNI_W_D = 2356,
2370 XVSRLRN_B_H = 2357,
2371 XVSRLRN_H_W = 2358,
2372 XVSRLRN_W_D = 2359,
2373 XVSRLR_B = 2360,
2374 XVSRLR_D = 2361,
2375 XVSRLR_H = 2362,
2376 XVSRLR_W = 2363,
2377 XVSRL_B = 2364,
2378 XVSRL_D = 2365,
2379 XVSRL_H = 2366,
2380 XVSRL_W = 2367,
2381 XVSSRANI_BU_H = 2368,
2382 XVSSRANI_B_H = 2369,
2383 XVSSRANI_DU_Q = 2370,
2384 XVSSRANI_D_Q = 2371,
2385 XVSSRANI_HU_W = 2372,
2386 XVSSRANI_H_W = 2373,
2387 XVSSRANI_WU_D = 2374,
2388 XVSSRANI_W_D = 2375,
2389 XVSSRAN_BU_H = 2376,
2390 XVSSRAN_B_H = 2377,
2391 XVSSRAN_HU_W = 2378,
2392 XVSSRAN_H_W = 2379,
2393 XVSSRAN_WU_D = 2380,
2394 XVSSRAN_W_D = 2381,
2395 XVSSRARNI_BU_H = 2382,
2396 XVSSRARNI_B_H = 2383,
2397 XVSSRARNI_DU_Q = 2384,
2398 XVSSRARNI_D_Q = 2385,
2399 XVSSRARNI_HU_W = 2386,
2400 XVSSRARNI_H_W = 2387,
2401 XVSSRARNI_WU_D = 2388,
2402 XVSSRARNI_W_D = 2389,
2403 XVSSRARN_BU_H = 2390,
2404 XVSSRARN_B_H = 2391,
2405 XVSSRARN_HU_W = 2392,
2406 XVSSRARN_H_W = 2393,
2407 XVSSRARN_WU_D = 2394,
2408 XVSSRARN_W_D = 2395,
2409 XVSSRLNI_BU_H = 2396,
2410 XVSSRLNI_B_H = 2397,
2411 XVSSRLNI_DU_Q = 2398,
2412 XVSSRLNI_D_Q = 2399,
2413 XVSSRLNI_HU_W = 2400,
2414 XVSSRLNI_H_W = 2401,
2415 XVSSRLNI_WU_D = 2402,
2416 XVSSRLNI_W_D = 2403,
2417 XVSSRLN_BU_H = 2404,
2418 XVSSRLN_B_H = 2405,
2419 XVSSRLN_HU_W = 2406,
2420 XVSSRLN_H_W = 2407,
2421 XVSSRLN_WU_D = 2408,
2422 XVSSRLN_W_D = 2409,
2423 XVSSRLRNI_BU_H = 2410,
2424 XVSSRLRNI_B_H = 2411,
2425 XVSSRLRNI_DU_Q = 2412,
2426 XVSSRLRNI_D_Q = 2413,
2427 XVSSRLRNI_HU_W = 2414,
2428 XVSSRLRNI_H_W = 2415,
2429 XVSSRLRNI_WU_D = 2416,
2430 XVSSRLRNI_W_D = 2417,
2431 XVSSRLRN_BU_H = 2418,
2432 XVSSRLRN_B_H = 2419,
2433 XVSSRLRN_HU_W = 2420,
2434 XVSSRLRN_H_W = 2421,
2435 XVSSRLRN_WU_D = 2422,
2436 XVSSRLRN_W_D = 2423,
2437 XVSSUB_B = 2424,
2438 XVSSUB_BU = 2425,
2439 XVSSUB_D = 2426,
2440 XVSSUB_DU = 2427,
2441 XVSSUB_H = 2428,
2442 XVSSUB_HU = 2429,
2443 XVSSUB_W = 2430,
2444 XVSSUB_WU = 2431,
2445 XVST = 2432,
2446 XVSTELM_B = 2433,
2447 XVSTELM_D = 2434,
2448 XVSTELM_H = 2435,
2449 XVSTELM_W = 2436,
2450 XVSTX = 2437,
2451 XVSUBI_BU = 2438,
2452 XVSUBI_DU = 2439,
2453 XVSUBI_HU = 2440,
2454 XVSUBI_WU = 2441,
2455 XVSUBWEV_D_W = 2442,
2456 XVSUBWEV_D_WU = 2443,
2457 XVSUBWEV_H_B = 2444,
2458 XVSUBWEV_H_BU = 2445,
2459 XVSUBWEV_Q_D = 2446,
2460 XVSUBWEV_Q_DU = 2447,
2461 XVSUBWEV_W_H = 2448,
2462 XVSUBWEV_W_HU = 2449,
2463 XVSUBWOD_D_W = 2450,
2464 XVSUBWOD_D_WU = 2451,
2465 XVSUBWOD_H_B = 2452,
2466 XVSUBWOD_H_BU = 2453,
2467 XVSUBWOD_Q_D = 2454,
2468 XVSUBWOD_Q_DU = 2455,
2469 XVSUBWOD_W_H = 2456,
2470 XVSUBWOD_W_HU = 2457,
2471 XVSUB_B = 2458,
2472 XVSUB_D = 2459,
2473 XVSUB_H = 2460,
2474 XVSUB_Q = 2461,
2475 XVSUB_W = 2462,
2476 XVXORI_B = 2463,
2477 XVXOR_V = 2464,
2478 INSTRUCTION_LIST_END = 2465
2479 };
2480
2481} // end namespace llvm::LoongArch
2482#endif // GET_INSTRINFO_ENUM
2483
2484#ifdef GET_INSTRINFO_SCHED_ENUM
2485#undef GET_INSTRINFO_SCHED_ENUM
2486namespace llvm::LoongArch::Sched {
2487
2488 enum {
2489 NoInstrModel = 0,
2490 SCHED_LIST_END = 1
2491 };
2492} // end namespace llvm::LoongArch::Sched
2493#endif // GET_INSTRINFO_SCHED_ENUM
2494
2495#if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
2496namespace llvm {
2497
2498struct LoongArchInstrTable {
2499 MCInstrDesc Insts[2465];
2500 static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo");
2501 MCOperandInfo OperandInfo[444];
2502 static_assert(alignof(MCOperandInfo) >= alignof(MCPhysReg), "Unwanted padding between OperandInfo and ImplicitOps");
2503 MCPhysReg ImplicitOps[12];
2504};
2505
2506} // end namespace llvm
2507#endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
2508
2509#ifdef GET_INSTRINFO_MC_DESC
2510#undef GET_INSTRINFO_MC_DESC
2511namespace llvm {
2512
2513static_assert(sizeof(MCOperandInfo) % sizeof(MCPhysReg) == 0);
2514static constexpr unsigned LoongArchImpOpBase = sizeof LoongArchInstrTable::OperandInfo / (sizeof(MCPhysReg));
2515
2516extern const LoongArchInstrTable LoongArchDescs = {
2517 {
2518 { 2464, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2464 = XVXOR_V
2519 { 2463, 3, 1, 4, 0, 0, 0, 409, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2463 = XVXORI_B
2520 { 2462, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2462 = XVSUB_W
2521 { 2461, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2461 = XVSUB_Q
2522 { 2460, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2460 = XVSUB_H
2523 { 2459, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2459 = XVSUB_D
2524 { 2458, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2458 = XVSUB_B
2525 { 2457, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2457 = XVSUBWOD_W_HU
2526 { 2456, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2456 = XVSUBWOD_W_H
2527 { 2455, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2455 = XVSUBWOD_Q_DU
2528 { 2454, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2454 = XVSUBWOD_Q_D
2529 { 2453, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2453 = XVSUBWOD_H_BU
2530 { 2452, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2452 = XVSUBWOD_H_B
2531 { 2451, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2451 = XVSUBWOD_D_WU
2532 { 2450, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2450 = XVSUBWOD_D_W
2533 { 2449, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2449 = XVSUBWEV_W_HU
2534 { 2448, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2448 = XVSUBWEV_W_H
2535 { 2447, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2447 = XVSUBWEV_Q_DU
2536 { 2446, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2446 = XVSUBWEV_Q_D
2537 { 2445, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2445 = XVSUBWEV_H_BU
2538 { 2444, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2444 = XVSUBWEV_H_B
2539 { 2443, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2443 = XVSUBWEV_D_WU
2540 { 2442, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2442 = XVSUBWEV_D_W
2541 { 2441, 3, 1, 4, 0, 0, 0, 409, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2441 = XVSUBI_WU
2542 { 2440, 3, 1, 4, 0, 0, 0, 409, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2440 = XVSUBI_HU
2543 { 2439, 3, 1, 4, 0, 0, 0, 409, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2439 = XVSUBI_DU
2544 { 2438, 3, 1, 4, 0, 0, 0, 409, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2438 = XVSUBI_BU
2545 { 2437, 3, 0, 4, 0, 0, 0, 427, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #2437 = XVSTX
2546 { 2436, 4, 0, 4, 0, 0, 0, 440, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #2436 = XVSTELM_W
2547 { 2435, 4, 0, 4, 0, 0, 0, 440, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #2435 = XVSTELM_H
2548 { 2434, 4, 0, 4, 0, 0, 0, 440, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #2434 = XVSTELM_D
2549 { 2433, 4, 0, 4, 0, 0, 0, 440, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #2433 = XVSTELM_B
2550 { 2432, 3, 0, 4, 0, 0, 0, 424, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #2432 = XVST
2551 { 2431, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2431 = XVSSUB_WU
2552 { 2430, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2430 = XVSSUB_W
2553 { 2429, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2429 = XVSSUB_HU
2554 { 2428, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2428 = XVSSUB_H
2555 { 2427, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2427 = XVSSUB_DU
2556 { 2426, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2426 = XVSSUB_D
2557 { 2425, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2425 = XVSSUB_BU
2558 { 2424, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2424 = XVSSUB_B
2559 { 2423, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2423 = XVSSRLRN_W_D
2560 { 2422, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2422 = XVSSRLRN_WU_D
2561 { 2421, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2421 = XVSSRLRN_H_W
2562 { 2420, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2420 = XVSSRLRN_HU_W
2563 { 2419, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2419 = XVSSRLRN_B_H
2564 { 2418, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2418 = XVSSRLRN_BU_H
2565 { 2417, 4, 1, 4, 0, 0, 0, 412, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2417 = XVSSRLRNI_W_D
2566 { 2416, 4, 1, 4, 0, 0, 0, 412, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2416 = XVSSRLRNI_WU_D
2567 { 2415, 4, 1, 4, 0, 0, 0, 412, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2415 = XVSSRLRNI_H_W
2568 { 2414, 4, 1, 4, 0, 0, 0, 412, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2414 = XVSSRLRNI_HU_W
2569 { 2413, 4, 1, 4, 0, 0, 0, 412, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2413 = XVSSRLRNI_D_Q
2570 { 2412, 4, 1, 4, 0, 0, 0, 412, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2412 = XVSSRLRNI_DU_Q
2571 { 2411, 4, 1, 4, 0, 0, 0, 412, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2411 = XVSSRLRNI_B_H
2572 { 2410, 4, 1, 4, 0, 0, 0, 412, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2410 = XVSSRLRNI_BU_H
2573 { 2409, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2409 = XVSSRLN_W_D
2574 { 2408, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2408 = XVSSRLN_WU_D
2575 { 2407, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2407 = XVSSRLN_H_W
2576 { 2406, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2406 = XVSSRLN_HU_W
2577 { 2405, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2405 = XVSSRLN_B_H
2578 { 2404, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2404 = XVSSRLN_BU_H
2579 { 2403, 4, 1, 4, 0, 0, 0, 412, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2403 = XVSSRLNI_W_D
2580 { 2402, 4, 1, 4, 0, 0, 0, 412, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2402 = XVSSRLNI_WU_D
2581 { 2401, 4, 1, 4, 0, 0, 0, 412, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2401 = XVSSRLNI_H_W
2582 { 2400, 4, 1, 4, 0, 0, 0, 412, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2400 = XVSSRLNI_HU_W
2583 { 2399, 4, 1, 4, 0, 0, 0, 412, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2399 = XVSSRLNI_D_Q
2584 { 2398, 4, 1, 4, 0, 0, 0, 412, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2398 = XVSSRLNI_DU_Q
2585 { 2397, 4, 1, 4, 0, 0, 0, 412, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2397 = XVSSRLNI_B_H
2586 { 2396, 4, 1, 4, 0, 0, 0, 412, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2396 = XVSSRLNI_BU_H
2587 { 2395, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2395 = XVSSRARN_W_D
2588 { 2394, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2394 = XVSSRARN_WU_D
2589 { 2393, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2393 = XVSSRARN_H_W
2590 { 2392, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2392 = XVSSRARN_HU_W
2591 { 2391, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2391 = XVSSRARN_B_H
2592 { 2390, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2390 = XVSSRARN_BU_H
2593 { 2389, 4, 1, 4, 0, 0, 0, 412, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2389 = XVSSRARNI_W_D
2594 { 2388, 4, 1, 4, 0, 0, 0, 412, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2388 = XVSSRARNI_WU_D
2595 { 2387, 4, 1, 4, 0, 0, 0, 412, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2387 = XVSSRARNI_H_W
2596 { 2386, 4, 1, 4, 0, 0, 0, 412, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2386 = XVSSRARNI_HU_W
2597 { 2385, 4, 1, 4, 0, 0, 0, 412, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2385 = XVSSRARNI_D_Q
2598 { 2384, 4, 1, 4, 0, 0, 0, 412, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2384 = XVSSRARNI_DU_Q
2599 { 2383, 4, 1, 4, 0, 0, 0, 412, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2383 = XVSSRARNI_B_H
2600 { 2382, 4, 1, 4, 0, 0, 0, 412, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2382 = XVSSRARNI_BU_H
2601 { 2381, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2381 = XVSSRAN_W_D
2602 { 2380, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2380 = XVSSRAN_WU_D
2603 { 2379, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2379 = XVSSRAN_H_W
2604 { 2378, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2378 = XVSSRAN_HU_W
2605 { 2377, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2377 = XVSSRAN_B_H
2606 { 2376, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2376 = XVSSRAN_BU_H
2607 { 2375, 4, 1, 4, 0, 0, 0, 412, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2375 = XVSSRANI_W_D
2608 { 2374, 4, 1, 4, 0, 0, 0, 412, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2374 = XVSSRANI_WU_D
2609 { 2373, 4, 1, 4, 0, 0, 0, 412, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2373 = XVSSRANI_H_W
2610 { 2372, 4, 1, 4, 0, 0, 0, 412, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2372 = XVSSRANI_HU_W
2611 { 2371, 4, 1, 4, 0, 0, 0, 412, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2371 = XVSSRANI_D_Q
2612 { 2370, 4, 1, 4, 0, 0, 0, 412, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2370 = XVSSRANI_DU_Q
2613 { 2369, 4, 1, 4, 0, 0, 0, 412, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2369 = XVSSRANI_B_H
2614 { 2368, 4, 1, 4, 0, 0, 0, 412, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2368 = XVSSRANI_BU_H
2615 { 2367, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2367 = XVSRL_W
2616 { 2366, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2366 = XVSRL_H
2617 { 2365, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2365 = XVSRL_D
2618 { 2364, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2364 = XVSRL_B
2619 { 2363, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2363 = XVSRLR_W
2620 { 2362, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2362 = XVSRLR_H
2621 { 2361, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2361 = XVSRLR_D
2622 { 2360, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2360 = XVSRLR_B
2623 { 2359, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2359 = XVSRLRN_W_D
2624 { 2358, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2358 = XVSRLRN_H_W
2625 { 2357, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2357 = XVSRLRN_B_H
2626 { 2356, 4, 1, 4, 0, 0, 0, 412, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2356 = XVSRLRNI_W_D
2627 { 2355, 4, 1, 4, 0, 0, 0, 412, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2355 = XVSRLRNI_H_W
2628 { 2354, 4, 1, 4, 0, 0, 0, 412, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2354 = XVSRLRNI_D_Q
2629 { 2353, 4, 1, 4, 0, 0, 0, 412, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2353 = XVSRLRNI_B_H
2630 { 2352, 3, 1, 4, 0, 0, 0, 409, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2352 = XVSRLRI_W
2631 { 2351, 3, 1, 4, 0, 0, 0, 409, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2351 = XVSRLRI_H
2632 { 2350, 3, 1, 4, 0, 0, 0, 409, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2350 = XVSRLRI_D
2633 { 2349, 3, 1, 4, 0, 0, 0, 409, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2349 = XVSRLRI_B
2634 { 2348, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2348 = XVSRLN_W_D
2635 { 2347, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2347 = XVSRLN_H_W
2636 { 2346, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2346 = XVSRLN_B_H
2637 { 2345, 4, 1, 4, 0, 0, 0, 412, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2345 = XVSRLNI_W_D
2638 { 2344, 4, 1, 4, 0, 0, 0, 412, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2344 = XVSRLNI_H_W
2639 { 2343, 4, 1, 4, 0, 0, 0, 412, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2343 = XVSRLNI_D_Q
2640 { 2342, 4, 1, 4, 0, 0, 0, 412, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2342 = XVSRLNI_B_H
2641 { 2341, 3, 1, 4, 0, 0, 0, 409, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2341 = XVSRLI_W
2642 { 2340, 3, 1, 4, 0, 0, 0, 409, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2340 = XVSRLI_H
2643 { 2339, 3, 1, 4, 0, 0, 0, 409, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2339 = XVSRLI_D
2644 { 2338, 3, 1, 4, 0, 0, 0, 409, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2338 = XVSRLI_B
2645 { 2337, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2337 = XVSRA_W
2646 { 2336, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2336 = XVSRA_H
2647 { 2335, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2335 = XVSRA_D
2648 { 2334, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2334 = XVSRA_B
2649 { 2333, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2333 = XVSRAR_W
2650 { 2332, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2332 = XVSRAR_H
2651 { 2331, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2331 = XVSRAR_D
2652 { 2330, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2330 = XVSRAR_B
2653 { 2329, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2329 = XVSRARN_W_D
2654 { 2328, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2328 = XVSRARN_H_W
2655 { 2327, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2327 = XVSRARN_B_H
2656 { 2326, 4, 1, 4, 0, 0, 0, 412, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2326 = XVSRARNI_W_D
2657 { 2325, 4, 1, 4, 0, 0, 0, 412, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2325 = XVSRARNI_H_W
2658 { 2324, 4, 1, 4, 0, 0, 0, 412, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2324 = XVSRARNI_D_Q
2659 { 2323, 4, 1, 4, 0, 0, 0, 412, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2323 = XVSRARNI_B_H
2660 { 2322, 3, 1, 4, 0, 0, 0, 409, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2322 = XVSRARI_W
2661 { 2321, 3, 1, 4, 0, 0, 0, 409, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2321 = XVSRARI_H
2662 { 2320, 3, 1, 4, 0, 0, 0, 409, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2320 = XVSRARI_D
2663 { 2319, 3, 1, 4, 0, 0, 0, 409, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2319 = XVSRARI_B
2664 { 2318, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2318 = XVSRAN_W_D
2665 { 2317, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2317 = XVSRAN_H_W
2666 { 2316, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2316 = XVSRAN_B_H
2667 { 2315, 4, 1, 4, 0, 0, 0, 412, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2315 = XVSRANI_W_D
2668 { 2314, 4, 1, 4, 0, 0, 0, 412, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2314 = XVSRANI_H_W
2669 { 2313, 4, 1, 4, 0, 0, 0, 412, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2313 = XVSRANI_D_Q
2670 { 2312, 4, 1, 4, 0, 0, 0, 412, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2312 = XVSRANI_B_H
2671 { 2311, 3, 1, 4, 0, 0, 0, 409, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2311 = XVSRAI_W
2672 { 2310, 3, 1, 4, 0, 0, 0, 409, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2310 = XVSRAI_H
2673 { 2309, 3, 1, 4, 0, 0, 0, 409, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2309 = XVSRAI_D
2674 { 2308, 3, 1, 4, 0, 0, 0, 409, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2308 = XVSRAI_B
2675 { 2307, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2307 = XVSLT_WU
2676 { 2306, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2306 = XVSLT_W
2677 { 2305, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2305 = XVSLT_HU
2678 { 2304, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2304 = XVSLT_H
2679 { 2303, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2303 = XVSLT_DU
2680 { 2302, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2302 = XVSLT_D
2681 { 2301, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2301 = XVSLT_BU
2682 { 2300, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2300 = XVSLT_B
2683 { 2299, 3, 1, 4, 0, 0, 0, 409, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2299 = XVSLTI_WU
2684 { 2298, 3, 1, 4, 0, 0, 0, 409, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2298 = XVSLTI_W
2685 { 2297, 3, 1, 4, 0, 0, 0, 409, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2297 = XVSLTI_HU
2686 { 2296, 3, 1, 4, 0, 0, 0, 409, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2296 = XVSLTI_H
2687 { 2295, 3, 1, 4, 0, 0, 0, 409, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2295 = XVSLTI_DU
2688 { 2294, 3, 1, 4, 0, 0, 0, 409, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2294 = XVSLTI_D
2689 { 2293, 3, 1, 4, 0, 0, 0, 409, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2293 = XVSLTI_BU
2690 { 2292, 3, 1, 4, 0, 0, 0, 409, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2292 = XVSLTI_B
2691 { 2291, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2291 = XVSLL_W
2692 { 2290, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2290 = XVSLL_H
2693 { 2289, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2289 = XVSLL_D
2694 { 2288, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2288 = XVSLL_B
2695 { 2287, 3, 1, 4, 0, 0, 0, 409, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2287 = XVSLLWIL_W_H
2696 { 2286, 3, 1, 4, 0, 0, 0, 409, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2286 = XVSLLWIL_WU_HU
2697 { 2285, 3, 1, 4, 0, 0, 0, 409, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2285 = XVSLLWIL_H_B
2698 { 2284, 3, 1, 4, 0, 0, 0, 409, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2284 = XVSLLWIL_HU_BU
2699 { 2283, 3, 1, 4, 0, 0, 0, 409, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2283 = XVSLLWIL_D_W
2700 { 2282, 3, 1, 4, 0, 0, 0, 409, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2282 = XVSLLWIL_DU_WU
2701 { 2281, 3, 1, 4, 0, 0, 0, 409, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2281 = XVSLLI_W
2702 { 2280, 3, 1, 4, 0, 0, 0, 409, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2280 = XVSLLI_H
2703 { 2279, 3, 1, 4, 0, 0, 0, 409, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2279 = XVSLLI_D
2704 { 2278, 3, 1, 4, 0, 0, 0, 409, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2278 = XVSLLI_B
2705 { 2277, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2277 = XVSLE_WU
2706 { 2276, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2276 = XVSLE_W
2707 { 2275, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2275 = XVSLE_HU
2708 { 2274, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2274 = XVSLE_H
2709 { 2273, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2273 = XVSLE_DU
2710 { 2272, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2272 = XVSLE_D
2711 { 2271, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2271 = XVSLE_BU
2712 { 2270, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2270 = XVSLE_B
2713 { 2269, 3, 1, 4, 0, 0, 0, 409, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2269 = XVSLEI_WU
2714 { 2268, 3, 1, 4, 0, 0, 0, 409, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2268 = XVSLEI_W
2715 { 2267, 3, 1, 4, 0, 0, 0, 409, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2267 = XVSLEI_HU
2716 { 2266, 3, 1, 4, 0, 0, 0, 409, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2266 = XVSLEI_H
2717 { 2265, 3, 1, 4, 0, 0, 0, 409, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2265 = XVSLEI_DU
2718 { 2264, 3, 1, 4, 0, 0, 0, 409, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2264 = XVSLEI_D
2719 { 2263, 3, 1, 4, 0, 0, 0, 409, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2263 = XVSLEI_BU
2720 { 2262, 3, 1, 4, 0, 0, 0, 409, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2262 = XVSLEI_B
2721 { 2261, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2261 = XVSIGNCOV_W
2722 { 2260, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2260 = XVSIGNCOV_H
2723 { 2259, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2259 = XVSIGNCOV_D
2724 { 2258, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2258 = XVSIGNCOV_B
2725 { 2257, 4, 1, 4, 0, 0, 0, 420, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2257 = XVSHUF_W
2726 { 2256, 4, 1, 4, 0, 0, 0, 420, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2256 = XVSHUF_H
2727 { 2255, 4, 1, 4, 0, 0, 0, 420, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2255 = XVSHUF_D
2728 { 2254, 4, 1, 4, 0, 0, 0, 416, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2254 = XVSHUF_B
2729 { 2253, 3, 1, 4, 0, 0, 0, 409, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2253 = XVSHUF4I_W
2730 { 2252, 3, 1, 4, 0, 0, 0, 409, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2252 = XVSHUF4I_H
2731 { 2251, 4, 1, 4, 0, 0, 0, 412, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2251 = XVSHUF4I_D
2732 { 2250, 3, 1, 4, 0, 0, 0, 409, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2250 = XVSHUF4I_B
2733 { 2249, 2, 1, 4, 0, 0, 0, 438, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2249 = XVSETNEZ_V
2734 { 2248, 2, 1, 4, 0, 0, 0, 438, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2248 = XVSETEQZ_V
2735 { 2247, 2, 1, 4, 0, 0, 0, 438, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2247 = XVSETANYEQZ_W
2736 { 2246, 2, 1, 4, 0, 0, 0, 438, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2246 = XVSETANYEQZ_H
2737 { 2245, 2, 1, 4, 0, 0, 0, 438, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2245 = XVSETANYEQZ_D
2738 { 2244, 2, 1, 4, 0, 0, 0, 438, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2244 = XVSETANYEQZ_B
2739 { 2243, 2, 1, 4, 0, 0, 0, 438, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2243 = XVSETALLNEZ_W
2740 { 2242, 2, 1, 4, 0, 0, 0, 438, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2242 = XVSETALLNEZ_H
2741 { 2241, 2, 1, 4, 0, 0, 0, 438, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2241 = XVSETALLNEZ_D
2742 { 2240, 2, 1, 4, 0, 0, 0, 438, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2240 = XVSETALLNEZ_B
2743 { 2239, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2239 = XVSEQ_W
2744 { 2238, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2238 = XVSEQ_H
2745 { 2237, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2237 = XVSEQ_D
2746 { 2236, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2236 = XVSEQ_B
2747 { 2235, 3, 1, 4, 0, 0, 0, 409, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2235 = XVSEQI_W
2748 { 2234, 3, 1, 4, 0, 0, 0, 409, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2234 = XVSEQI_H
2749 { 2233, 3, 1, 4, 0, 0, 0, 409, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2233 = XVSEQI_D
2750 { 2232, 3, 1, 4, 0, 0, 0, 409, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2232 = XVSEQI_B
2751 { 2231, 3, 1, 4, 0, 0, 0, 409, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2231 = XVSAT_WU
2752 { 2230, 3, 1, 4, 0, 0, 0, 409, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2230 = XVSAT_W
2753 { 2229, 3, 1, 4, 0, 0, 0, 409, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2229 = XVSAT_HU
2754 { 2228, 3, 1, 4, 0, 0, 0, 409, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2228 = XVSAT_H
2755 { 2227, 3, 1, 4, 0, 0, 0, 409, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2227 = XVSAT_DU
2756 { 2226, 3, 1, 4, 0, 0, 0, 409, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2226 = XVSAT_D
2757 { 2225, 3, 1, 4, 0, 0, 0, 409, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2225 = XVSAT_BU
2758 { 2224, 3, 1, 4, 0, 0, 0, 409, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2224 = XVSAT_B
2759 { 2223, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2223 = XVSADD_WU
2760 { 2222, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2222 = XVSADD_W
2761 { 2221, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2221 = XVSADD_HU
2762 { 2220, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2220 = XVSADD_H
2763 { 2219, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2219 = XVSADD_DU
2764 { 2218, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2218 = XVSADD_D
2765 { 2217, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2217 = XVSADD_BU
2766 { 2216, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2216 = XVSADD_B
2767 { 2215, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2215 = XVROTR_W
2768 { 2214, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2214 = XVROTR_H
2769 { 2213, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2213 = XVROTR_D
2770 { 2212, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2212 = XVROTR_B
2771 { 2211, 3, 1, 4, 0, 0, 0, 409, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2211 = XVROTRI_W
2772 { 2210, 3, 1, 4, 0, 0, 0, 409, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2210 = XVROTRI_H
2773 { 2209, 3, 1, 4, 0, 0, 0, 409, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2209 = XVROTRI_D
2774 { 2208, 3, 1, 4, 0, 0, 0, 409, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2208 = XVROTRI_B
2775 { 2207, 3, 1, 4, 0, 0, 0, 435, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2207 = XVREPLVE_W
2776 { 2206, 3, 1, 4, 0, 0, 0, 435, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2206 = XVREPLVE_H
2777 { 2205, 3, 1, 4, 0, 0, 0, 435, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2205 = XVREPLVE_D
2778 { 2204, 3, 1, 4, 0, 0, 0, 435, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2204 = XVREPLVE_B
2779 { 2203, 2, 1, 4, 0, 0, 0, 376, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2203 = XVREPLVE0_W
2780 { 2202, 2, 1, 4, 0, 0, 0, 376, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2202 = XVREPLVE0_Q
2781 { 2201, 2, 1, 4, 0, 0, 0, 376, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2201 = XVREPLVE0_H
2782 { 2200, 2, 1, 4, 0, 0, 0, 376, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2200 = XVREPLVE0_D
2783 { 2199, 2, 1, 4, 0, 0, 0, 376, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2199 = XVREPLVE0_B
2784 { 2198, 2, 1, 4, 0, 0, 0, 433, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2198 = XVREPLGR2VR_W
2785 { 2197, 2, 1, 4, 0, 0, 0, 433, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2197 = XVREPLGR2VR_H
2786 { 2196, 2, 1, 4, 0, 0, 0, 433, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2196 = XVREPLGR2VR_D
2787 { 2195, 2, 1, 4, 0, 0, 0, 433, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2195 = XVREPLGR2VR_B
2788 { 2194, 3, 1, 4, 0, 0, 0, 409, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2194 = XVREPL128VEI_W
2789 { 2193, 3, 1, 4, 0, 0, 0, 409, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2193 = XVREPL128VEI_H
2790 { 2192, 3, 1, 4, 0, 0, 0, 409, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2192 = XVREPL128VEI_D
2791 { 2191, 3, 1, 4, 0, 0, 0, 409, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2191 = XVREPL128VEI_B
2792 { 2190, 3, 1, 4, 0, 0, 0, 409, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2190 = XVPICKVE_W
2793 { 2189, 3, 1, 4, 0, 0, 0, 409, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2189 = XVPICKVE_D
2794 { 2188, 3, 1, 4, 0, 0, 0, 430, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2188 = XVPICKVE2GR_WU
2795 { 2187, 3, 1, 4, 0, 0, 0, 430, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2187 = XVPICKVE2GR_W
2796 { 2186, 3, 1, 4, 0, 0, 0, 430, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2186 = XVPICKVE2GR_DU
2797 { 2185, 3, 1, 4, 0, 0, 0, 430, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2185 = XVPICKVE2GR_D
2798 { 2184, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2184 = XVPICKOD_W
2799 { 2183, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2183 = XVPICKOD_H
2800 { 2182, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2182 = XVPICKOD_D
2801 { 2181, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2181 = XVPICKOD_B
2802 { 2180, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2180 = XVPICKEV_W
2803 { 2179, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2179 = XVPICKEV_H
2804 { 2178, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2178 = XVPICKEV_D
2805 { 2177, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2177 = XVPICKEV_B
2806 { 2176, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2176 = XVPERM_W
2807 { 2175, 4, 1, 4, 0, 0, 0, 412, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2175 = XVPERMI_W
2808 { 2174, 4, 1, 4, 0, 0, 0, 412, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2174 = XVPERMI_Q
2809 { 2173, 3, 1, 4, 0, 0, 0, 409, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2173 = XVPERMI_D
2810 { 2172, 2, 1, 4, 0, 0, 0, 376, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2172 = XVPCNT_W
2811 { 2171, 2, 1, 4, 0, 0, 0, 376, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2171 = XVPCNT_H
2812 { 2170, 2, 1, 4, 0, 0, 0, 376, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2170 = XVPCNT_D
2813 { 2169, 2, 1, 4, 0, 0, 0, 376, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2169 = XVPCNT_B
2814 { 2168, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2168 = XVPACKOD_W
2815 { 2167, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2167 = XVPACKOD_H
2816 { 2166, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2166 = XVPACKOD_D
2817 { 2165, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2165 = XVPACKOD_B
2818 { 2164, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2164 = XVPACKEV_W
2819 { 2163, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2163 = XVPACKEV_H
2820 { 2162, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2162 = XVPACKEV_D
2821 { 2161, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2161 = XVPACKEV_B
2822 { 2160, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2160 = XVOR_V
2823 { 2159, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2159 = XVORN_V
2824 { 2158, 3, 1, 4, 0, 0, 0, 409, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2158 = XVORI_B
2825 { 2157, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2157 = XVNOR_V
2826 { 2156, 3, 1, 4, 0, 0, 0, 409, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2156 = XVNORI_B
2827 { 2155, 2, 1, 4, 0, 0, 0, 376, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2155 = XVNEG_W
2828 { 2154, 2, 1, 4, 0, 0, 0, 376, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2154 = XVNEG_H
2829 { 2153, 2, 1, 4, 0, 0, 0, 376, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2153 = XVNEG_D
2830 { 2152, 2, 1, 4, 0, 0, 0, 376, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2152 = XVNEG_B
2831 { 2151, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2151 = XVMUL_W
2832 { 2150, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2150 = XVMUL_H
2833 { 2149, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2149 = XVMUL_D
2834 { 2148, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2148 = XVMUL_B
2835 { 2147, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2147 = XVMULWOD_W_HU_H
2836 { 2146, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2146 = XVMULWOD_W_HU
2837 { 2145, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2145 = XVMULWOD_W_H
2838 { 2144, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2144 = XVMULWOD_Q_DU_D
2839 { 2143, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2143 = XVMULWOD_Q_DU
2840 { 2142, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2142 = XVMULWOD_Q_D
2841 { 2141, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2141 = XVMULWOD_H_BU_B
2842 { 2140, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2140 = XVMULWOD_H_BU
2843 { 2139, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2139 = XVMULWOD_H_B
2844 { 2138, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2138 = XVMULWOD_D_WU_W
2845 { 2137, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2137 = XVMULWOD_D_WU
2846 { 2136, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2136 = XVMULWOD_D_W
2847 { 2135, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2135 = XVMULWEV_W_HU_H
2848 { 2134, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2134 = XVMULWEV_W_HU
2849 { 2133, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2133 = XVMULWEV_W_H
2850 { 2132, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2132 = XVMULWEV_Q_DU_D
2851 { 2131, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2131 = XVMULWEV_Q_DU
2852 { 2130, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2130 = XVMULWEV_Q_D
2853 { 2129, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2129 = XVMULWEV_H_BU_B
2854 { 2128, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2128 = XVMULWEV_H_BU
2855 { 2127, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2127 = XVMULWEV_H_B
2856 { 2126, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2126 = XVMULWEV_D_WU_W
2857 { 2125, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2125 = XVMULWEV_D_WU
2858 { 2124, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2124 = XVMULWEV_D_W
2859 { 2123, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2123 = XVMUH_WU
2860 { 2122, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2122 = XVMUH_W
2861 { 2121, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2121 = XVMUH_HU
2862 { 2120, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2120 = XVMUH_H
2863 { 2119, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2119 = XVMUH_DU
2864 { 2118, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2118 = XVMUH_D
2865 { 2117, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2117 = XVMUH_BU
2866 { 2116, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2116 = XVMUH_B
2867 { 2115, 4, 1, 4, 0, 0, 0, 420, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2115 = XVMSUB_W
2868 { 2114, 4, 1, 4, 0, 0, 0, 420, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2114 = XVMSUB_H
2869 { 2113, 4, 1, 4, 0, 0, 0, 420, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2113 = XVMSUB_D
2870 { 2112, 4, 1, 4, 0, 0, 0, 420, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2112 = XVMSUB_B
2871 { 2111, 2, 1, 4, 0, 0, 0, 376, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2111 = XVMSKNZ_B
2872 { 2110, 2, 1, 4, 0, 0, 0, 376, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2110 = XVMSKLTZ_W
2873 { 2109, 2, 1, 4, 0, 0, 0, 376, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2109 = XVMSKLTZ_H
2874 { 2108, 2, 1, 4, 0, 0, 0, 376, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2108 = XVMSKLTZ_D
2875 { 2107, 2, 1, 4, 0, 0, 0, 376, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2107 = XVMSKLTZ_B
2876 { 2106, 2, 1, 4, 0, 0, 0, 376, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2106 = XVMSKGEZ_B
2877 { 2105, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2105 = XVMOD_WU
2878 { 2104, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2104 = XVMOD_W
2879 { 2103, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2103 = XVMOD_HU
2880 { 2102, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2102 = XVMOD_H
2881 { 2101, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2101 = XVMOD_DU
2882 { 2100, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2100 = XVMOD_D
2883 { 2099, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2099 = XVMOD_BU
2884 { 2098, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2098 = XVMOD_B
2885 { 2097, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2097 = XVMIN_WU
2886 { 2096, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2096 = XVMIN_W
2887 { 2095, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2095 = XVMIN_HU
2888 { 2094, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2094 = XVMIN_H
2889 { 2093, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2093 = XVMIN_DU
2890 { 2092, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2092 = XVMIN_D
2891 { 2091, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2091 = XVMIN_BU
2892 { 2090, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2090 = XVMIN_B
2893 { 2089, 3, 1, 4, 0, 0, 0, 409, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2089 = XVMINI_WU
2894 { 2088, 3, 1, 4, 0, 0, 0, 409, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2088 = XVMINI_W
2895 { 2087, 3, 1, 4, 0, 0, 0, 409, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2087 = XVMINI_HU
2896 { 2086, 3, 1, 4, 0, 0, 0, 409, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2086 = XVMINI_H
2897 { 2085, 3, 1, 4, 0, 0, 0, 409, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2085 = XVMINI_DU
2898 { 2084, 3, 1, 4, 0, 0, 0, 409, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2084 = XVMINI_D
2899 { 2083, 3, 1, 4, 0, 0, 0, 409, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2083 = XVMINI_BU
2900 { 2082, 3, 1, 4, 0, 0, 0, 409, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2082 = XVMINI_B
2901 { 2081, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2081 = XVMAX_WU
2902 { 2080, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2080 = XVMAX_W
2903 { 2079, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2079 = XVMAX_HU
2904 { 2078, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2078 = XVMAX_H
2905 { 2077, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2077 = XVMAX_DU
2906 { 2076, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2076 = XVMAX_D
2907 { 2075, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2075 = XVMAX_BU
2908 { 2074, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2074 = XVMAX_B
2909 { 2073, 3, 1, 4, 0, 0, 0, 409, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2073 = XVMAXI_WU
2910 { 2072, 3, 1, 4, 0, 0, 0, 409, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2072 = XVMAXI_W
2911 { 2071, 3, 1, 4, 0, 0, 0, 409, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2071 = XVMAXI_HU
2912 { 2070, 3, 1, 4, 0, 0, 0, 409, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2070 = XVMAXI_H
2913 { 2069, 3, 1, 4, 0, 0, 0, 409, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2069 = XVMAXI_DU
2914 { 2068, 3, 1, 4, 0, 0, 0, 409, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2068 = XVMAXI_D
2915 { 2067, 3, 1, 4, 0, 0, 0, 409, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2067 = XVMAXI_BU
2916 { 2066, 3, 1, 4, 0, 0, 0, 409, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2066 = XVMAXI_B
2917 { 2065, 4, 1, 4, 0, 0, 0, 420, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2065 = XVMADD_W
2918 { 2064, 4, 1, 4, 0, 0, 0, 420, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2064 = XVMADD_H
2919 { 2063, 4, 1, 4, 0, 0, 0, 420, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2063 = XVMADD_D
2920 { 2062, 4, 1, 4, 0, 0, 0, 420, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2062 = XVMADD_B
2921 { 2061, 4, 1, 4, 0, 0, 0, 420, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2061 = XVMADDWOD_W_HU_H
2922 { 2060, 4, 1, 4, 0, 0, 0, 420, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2060 = XVMADDWOD_W_HU
2923 { 2059, 4, 1, 4, 0, 0, 0, 420, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2059 = XVMADDWOD_W_H
2924 { 2058, 4, 1, 4, 0, 0, 0, 420, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2058 = XVMADDWOD_Q_DU_D
2925 { 2057, 4, 1, 4, 0, 0, 0, 420, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2057 = XVMADDWOD_Q_DU
2926 { 2056, 4, 1, 4, 0, 0, 0, 420, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2056 = XVMADDWOD_Q_D
2927 { 2055, 4, 1, 4, 0, 0, 0, 420, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2055 = XVMADDWOD_H_BU_B
2928 { 2054, 4, 1, 4, 0, 0, 0, 420, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2054 = XVMADDWOD_H_BU
2929 { 2053, 4, 1, 4, 0, 0, 0, 420, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2053 = XVMADDWOD_H_B
2930 { 2052, 4, 1, 4, 0, 0, 0, 420, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2052 = XVMADDWOD_D_WU_W
2931 { 2051, 4, 1, 4, 0, 0, 0, 420, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2051 = XVMADDWOD_D_WU
2932 { 2050, 4, 1, 4, 0, 0, 0, 420, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2050 = XVMADDWOD_D_W
2933 { 2049, 4, 1, 4, 0, 0, 0, 420, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2049 = XVMADDWEV_W_HU_H
2934 { 2048, 4, 1, 4, 0, 0, 0, 420, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2048 = XVMADDWEV_W_HU
2935 { 2047, 4, 1, 4, 0, 0, 0, 420, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2047 = XVMADDWEV_W_H
2936 { 2046, 4, 1, 4, 0, 0, 0, 420, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2046 = XVMADDWEV_Q_DU_D
2937 { 2045, 4, 1, 4, 0, 0, 0, 420, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2045 = XVMADDWEV_Q_DU
2938 { 2044, 4, 1, 4, 0, 0, 0, 420, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2044 = XVMADDWEV_Q_D
2939 { 2043, 4, 1, 4, 0, 0, 0, 420, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2043 = XVMADDWEV_H_BU_B
2940 { 2042, 4, 1, 4, 0, 0, 0, 420, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2042 = XVMADDWEV_H_BU
2941 { 2041, 4, 1, 4, 0, 0, 0, 420, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2041 = XVMADDWEV_H_B
2942 { 2040, 4, 1, 4, 0, 0, 0, 420, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2040 = XVMADDWEV_D_WU_W
2943 { 2039, 4, 1, 4, 0, 0, 0, 420, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2039 = XVMADDWEV_D_WU
2944 { 2038, 4, 1, 4, 0, 0, 0, 420, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2038 = XVMADDWEV_D_W
2945 { 2037, 3, 1, 4, 0, 0, 0, 427, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #2037 = XVLDX
2946 { 2036, 3, 1, 4, 0, 0, 0, 424, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #2036 = XVLDREPL_W
2947 { 2035, 3, 1, 4, 0, 0, 0, 424, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #2035 = XVLDREPL_H
2948 { 2034, 3, 1, 4, 0, 0, 0, 424, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #2034 = XVLDREPL_D
2949 { 2033, 3, 1, 4, 0, 0, 0, 424, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #2033 = XVLDREPL_B
2950 { 2032, 2, 1, 4, 0, 0, 0, 229, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2032 = XVLDI
2951 { 2031, 3, 1, 4, 0, 0, 0, 424, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #2031 = XVLD
2952 { 2030, 4, 1, 4, 0, 0, 0, 412, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2030 = XVINSVE0_W
2953 { 2029, 4, 1, 4, 0, 0, 0, 412, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2029 = XVINSVE0_D
2954 { 2028, 4, 1, 4, 0, 0, 0, 225, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2028 = XVINSGR2VR_W
2955 { 2027, 4, 1, 4, 0, 0, 0, 225, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2027 = XVINSGR2VR_D
2956 { 2026, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2026 = XVILVL_W
2957 { 2025, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2025 = XVILVL_H
2958 { 2024, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2024 = XVILVL_D
2959 { 2023, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2023 = XVILVL_B
2960 { 2022, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2022 = XVILVH_W
2961 { 2021, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2021 = XVILVH_H
2962 { 2020, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2020 = XVILVH_D
2963 { 2019, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2019 = XVILVH_B
2964 { 2018, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2018 = XVHSUBW_W_H
2965 { 2017, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2017 = XVHSUBW_WU_HU
2966 { 2016, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2016 = XVHSUBW_Q_D
2967 { 2015, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2015 = XVHSUBW_QU_DU
2968 { 2014, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2014 = XVHSUBW_H_B
2969 { 2013, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2013 = XVHSUBW_HU_BU
2970 { 2012, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2012 = XVHSUBW_D_W
2971 { 2011, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2011 = XVHSUBW_DU_WU
2972 { 2010, 3, 1, 4, 0, 0, 0, 409, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2010 = XVHSELI_D
2973 { 2009, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2009 = XVHADDW_W_H
2974 { 2008, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2008 = XVHADDW_WU_HU
2975 { 2007, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2007 = XVHADDW_Q_D
2976 { 2006, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2006 = XVHADDW_QU_DU
2977 { 2005, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2005 = XVHADDW_H_B
2978 { 2004, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2004 = XVHADDW_HU_BU
2979 { 2003, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2003 = XVHADDW_D_W
2980 { 2002, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2002 = XVHADDW_DU_WU
2981 { 2001, 2, 1, 4, 0, 0, 0, 376, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2001 = XVFTINT_W_S
2982 { 2000, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #2000 = XVFTINT_W_D
2983 { 1999, 2, 1, 4, 0, 0, 0, 376, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1999 = XVFTINT_WU_S
2984 { 1998, 2, 1, 4, 0, 0, 0, 376, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1998 = XVFTINT_L_D
2985 { 1997, 2, 1, 4, 0, 0, 0, 376, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1997 = XVFTINT_LU_D
2986 { 1996, 2, 1, 4, 0, 0, 0, 376, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1996 = XVFTINTRZ_W_S
2987 { 1995, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1995 = XVFTINTRZ_W_D
2988 { 1994, 2, 1, 4, 0, 0, 0, 376, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1994 = XVFTINTRZ_WU_S
2989 { 1993, 2, 1, 4, 0, 0, 0, 376, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1993 = XVFTINTRZ_L_D
2990 { 1992, 2, 1, 4, 0, 0, 0, 376, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1992 = XVFTINTRZ_LU_D
2991 { 1991, 2, 1, 4, 0, 0, 0, 376, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1991 = XVFTINTRZL_L_S
2992 { 1990, 2, 1, 4, 0, 0, 0, 376, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1990 = XVFTINTRZH_L_S
2993 { 1989, 2, 1, 4, 0, 0, 0, 376, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1989 = XVFTINTRP_W_S
2994 { 1988, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1988 = XVFTINTRP_W_D
2995 { 1987, 2, 1, 4, 0, 0, 0, 376, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1987 = XVFTINTRP_L_D
2996 { 1986, 2, 1, 4, 0, 0, 0, 376, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1986 = XVFTINTRPL_L_S
2997 { 1985, 2, 1, 4, 0, 0, 0, 376, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1985 = XVFTINTRPH_L_S
2998 { 1984, 2, 1, 4, 0, 0, 0, 376, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1984 = XVFTINTRNE_W_S
2999 { 1983, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1983 = XVFTINTRNE_W_D
3000 { 1982, 2, 1, 4, 0, 0, 0, 376, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1982 = XVFTINTRNE_L_D
3001 { 1981, 2, 1, 4, 0, 0, 0, 376, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1981 = XVFTINTRNEL_L_S
3002 { 1980, 2, 1, 4, 0, 0, 0, 376, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1980 = XVFTINTRNEH_L_S
3003 { 1979, 2, 1, 4, 0, 0, 0, 376, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1979 = XVFTINTRM_W_S
3004 { 1978, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1978 = XVFTINTRM_W_D
3005 { 1977, 2, 1, 4, 0, 0, 0, 376, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1977 = XVFTINTRM_L_D
3006 { 1976, 2, 1, 4, 0, 0, 0, 376, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1976 = XVFTINTRML_L_S
3007 { 1975, 2, 1, 4, 0, 0, 0, 376, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1975 = XVFTINTRMH_L_S
3008 { 1974, 2, 1, 4, 0, 0, 0, 376, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1974 = XVFTINTL_L_S
3009 { 1973, 2, 1, 4, 0, 0, 0, 376, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1973 = XVFTINTH_L_S
3010 { 1972, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1972 = XVFSUB_S
3011 { 1971, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1971 = XVFSUB_D
3012 { 1970, 2, 1, 4, 0, 0, 0, 376, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1970 = XVFSQRT_S
3013 { 1969, 2, 1, 4, 0, 0, 0, 376, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1969 = XVFSQRT_D
3014 { 1968, 4, 1, 4, 0, 0, 0, 420, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1968 = XVFRSTP_H
3015 { 1967, 4, 1, 4, 0, 0, 0, 420, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1967 = XVFRSTP_B
3016 { 1966, 4, 1, 4, 0, 0, 0, 412, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1966 = XVFRSTPI_H
3017 { 1965, 4, 1, 4, 0, 0, 0, 412, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1965 = XVFRSTPI_B
3018 { 1964, 2, 1, 4, 0, 0, 0, 376, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1964 = XVFRSQRT_S
3019 { 1963, 2, 1, 4, 0, 0, 0, 376, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1963 = XVFRSQRT_D
3020 { 1962, 2, 1, 4, 0, 0, 0, 376, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1962 = XVFRSQRTE_S
3021 { 1961, 2, 1, 4, 0, 0, 0, 376, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1961 = XVFRSQRTE_D
3022 { 1960, 2, 1, 4, 0, 0, 0, 376, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1960 = XVFRINT_S
3023 { 1959, 2, 1, 4, 0, 0, 0, 376, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1959 = XVFRINT_D
3024 { 1958, 2, 1, 4, 0, 0, 0, 376, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1958 = XVFRINTRZ_S
3025 { 1957, 2, 1, 4, 0, 0, 0, 376, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1957 = XVFRINTRZ_D
3026 { 1956, 2, 1, 4, 0, 0, 0, 376, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1956 = XVFRINTRP_S
3027 { 1955, 2, 1, 4, 0, 0, 0, 376, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1955 = XVFRINTRP_D
3028 { 1954, 2, 1, 4, 0, 0, 0, 376, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1954 = XVFRINTRNE_S
3029 { 1953, 2, 1, 4, 0, 0, 0, 376, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1953 = XVFRINTRNE_D
3030 { 1952, 2, 1, 4, 0, 0, 0, 376, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1952 = XVFRINTRM_S
3031 { 1951, 2, 1, 4, 0, 0, 0, 376, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1951 = XVFRINTRM_D
3032 { 1950, 2, 1, 4, 0, 0, 0, 376, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1950 = XVFRECIP_S
3033 { 1949, 2, 1, 4, 0, 0, 0, 376, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1949 = XVFRECIP_D
3034 { 1948, 2, 1, 4, 0, 0, 0, 376, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1948 = XVFRECIPE_S
3035 { 1947, 2, 1, 4, 0, 0, 0, 376, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1947 = XVFRECIPE_D
3036 { 1946, 4, 1, 4, 0, 0, 0, 416, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1946 = XVFNMSUB_S
3037 { 1945, 4, 1, 4, 0, 0, 0, 416, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1945 = XVFNMSUB_D
3038 { 1944, 4, 1, 4, 0, 0, 0, 416, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1944 = XVFNMADD_S
3039 { 1943, 4, 1, 4, 0, 0, 0, 416, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1943 = XVFNMADD_D
3040 { 1942, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1942 = XVFMUL_S
3041 { 1941, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1941 = XVFMUL_D
3042 { 1940, 4, 1, 4, 0, 0, 0, 416, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1940 = XVFMSUB_S
3043 { 1939, 4, 1, 4, 0, 0, 0, 416, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1939 = XVFMSUB_D
3044 { 1938, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1938 = XVFMIN_S
3045 { 1937, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1937 = XVFMIN_D
3046 { 1936, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1936 = XVFMINA_S
3047 { 1935, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1935 = XVFMINA_D
3048 { 1934, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1934 = XVFMAX_S
3049 { 1933, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1933 = XVFMAX_D
3050 { 1932, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1932 = XVFMAXA_S
3051 { 1931, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1931 = XVFMAXA_D
3052 { 1930, 4, 1, 4, 0, 0, 0, 416, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1930 = XVFMADD_S
3053 { 1929, 4, 1, 4, 0, 0, 0, 416, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1929 = XVFMADD_D
3054 { 1928, 2, 1, 4, 0, 0, 0, 376, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1928 = XVFLOGB_S
3055 { 1927, 2, 1, 4, 0, 0, 0, 376, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1927 = XVFLOGB_D
3056 { 1926, 2, 1, 4, 0, 0, 0, 376, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1926 = XVFFINT_S_WU
3057 { 1925, 2, 1, 4, 0, 0, 0, 376, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1925 = XVFFINT_S_W
3058 { 1924, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1924 = XVFFINT_S_L
3059 { 1923, 2, 1, 4, 0, 0, 0, 376, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1923 = XVFFINT_D_LU
3060 { 1922, 2, 1, 4, 0, 0, 0, 376, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1922 = XVFFINT_D_L
3061 { 1921, 2, 1, 4, 0, 0, 0, 376, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1921 = XVFFINTL_D_W
3062 { 1920, 2, 1, 4, 0, 0, 0, 376, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1920 = XVFFINTH_D_W
3063 { 1919, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1919 = XVFDIV_S
3064 { 1918, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1918 = XVFDIV_D
3065 { 1917, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1917 = XVFCVT_S_D
3066 { 1916, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1916 = XVFCVT_H_S
3067 { 1915, 2, 1, 4, 0, 0, 0, 376, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1915 = XVFCVTL_S_H
3068 { 1914, 2, 1, 4, 0, 0, 0, 376, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1914 = XVFCVTL_D_S
3069 { 1913, 2, 1, 4, 0, 0, 0, 376, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1913 = XVFCVTH_S_H
3070 { 1912, 2, 1, 4, 0, 0, 0, 376, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1912 = XVFCVTH_D_S
3071 { 1911, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1911 = XVFCMP_SUN_S
3072 { 1910, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1910 = XVFCMP_SUN_D
3073 { 1909, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1909 = XVFCMP_SUNE_S
3074 { 1908, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1908 = XVFCMP_SUNE_D
3075 { 1907, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1907 = XVFCMP_SULT_S
3076 { 1906, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1906 = XVFCMP_SULT_D
3077 { 1905, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1905 = XVFCMP_SULE_S
3078 { 1904, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1904 = XVFCMP_SULE_D
3079 { 1903, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1903 = XVFCMP_SUEQ_S
3080 { 1902, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1902 = XVFCMP_SUEQ_D
3081 { 1901, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1901 = XVFCMP_SOR_S
3082 { 1900, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1900 = XVFCMP_SOR_D
3083 { 1899, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1899 = XVFCMP_SNE_S
3084 { 1898, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1898 = XVFCMP_SNE_D
3085 { 1897, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1897 = XVFCMP_SLT_S
3086 { 1896, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1896 = XVFCMP_SLT_D
3087 { 1895, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1895 = XVFCMP_SLE_S
3088 { 1894, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1894 = XVFCMP_SLE_D
3089 { 1893, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1893 = XVFCMP_SEQ_S
3090 { 1892, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1892 = XVFCMP_SEQ_D
3091 { 1891, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1891 = XVFCMP_SAF_S
3092 { 1890, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1890 = XVFCMP_SAF_D
3093 { 1889, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1889 = XVFCMP_CUN_S
3094 { 1888, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1888 = XVFCMP_CUN_D
3095 { 1887, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1887 = XVFCMP_CUNE_S
3096 { 1886, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1886 = XVFCMP_CUNE_D
3097 { 1885, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1885 = XVFCMP_CULT_S
3098 { 1884, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1884 = XVFCMP_CULT_D
3099 { 1883, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1883 = XVFCMP_CULE_S
3100 { 1882, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1882 = XVFCMP_CULE_D
3101 { 1881, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1881 = XVFCMP_CUEQ_S
3102 { 1880, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1880 = XVFCMP_CUEQ_D
3103 { 1879, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1879 = XVFCMP_COR_S
3104 { 1878, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1878 = XVFCMP_COR_D
3105 { 1877, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1877 = XVFCMP_CNE_S
3106 { 1876, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1876 = XVFCMP_CNE_D
3107 { 1875, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1875 = XVFCMP_CLT_S
3108 { 1874, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1874 = XVFCMP_CLT_D
3109 { 1873, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1873 = XVFCMP_CLE_S
3110 { 1872, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1872 = XVFCMP_CLE_D
3111 { 1871, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1871 = XVFCMP_CEQ_S
3112 { 1870, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1870 = XVFCMP_CEQ_D
3113 { 1869, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1869 = XVFCMP_CAF_S
3114 { 1868, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1868 = XVFCMP_CAF_D
3115 { 1867, 2, 1, 4, 0, 0, 0, 376, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1867 = XVFCLASS_S
3116 { 1866, 2, 1, 4, 0, 0, 0, 376, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1866 = XVFCLASS_D
3117 { 1865, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1865 = XVFADD_S
3118 { 1864, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1864 = XVFADD_D
3119 { 1863, 4, 1, 4, 0, 0, 0, 412, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1863 = XVEXTRINS_W
3120 { 1862, 4, 1, 4, 0, 0, 0, 412, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1862 = XVEXTRINS_H
3121 { 1861, 4, 1, 4, 0, 0, 0, 412, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1861 = XVEXTRINS_D
3122 { 1860, 4, 1, 4, 0, 0, 0, 412, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1860 = XVEXTRINS_B
3123 { 1859, 2, 1, 4, 0, 0, 0, 376, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1859 = XVEXTL_Q_D
3124 { 1858, 2, 1, 4, 0, 0, 0, 376, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1858 = XVEXTL_QU_DU
3125 { 1857, 2, 1, 4, 0, 0, 0, 376, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1857 = XVEXTH_W_H
3126 { 1856, 2, 1, 4, 0, 0, 0, 376, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1856 = XVEXTH_WU_HU
3127 { 1855, 2, 1, 4, 0, 0, 0, 376, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1855 = XVEXTH_Q_D
3128 { 1854, 2, 1, 4, 0, 0, 0, 376, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1854 = XVEXTH_QU_DU
3129 { 1853, 2, 1, 4, 0, 0, 0, 376, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1853 = XVEXTH_H_B
3130 { 1852, 2, 1, 4, 0, 0, 0, 376, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1852 = XVEXTH_HU_BU
3131 { 1851, 2, 1, 4, 0, 0, 0, 376, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1851 = XVEXTH_D_W
3132 { 1850, 2, 1, 4, 0, 0, 0, 376, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1850 = XVEXTH_DU_WU
3133 { 1849, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1849 = XVDIV_WU
3134 { 1848, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1848 = XVDIV_W
3135 { 1847, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1847 = XVDIV_HU
3136 { 1846, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1846 = XVDIV_H
3137 { 1845, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1845 = XVDIV_DU
3138 { 1844, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1844 = XVDIV_D
3139 { 1843, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1843 = XVDIV_BU
3140 { 1842, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1842 = XVDIV_B
3141 { 1841, 2, 1, 4, 0, 0, 0, 376, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1841 = XVCLZ_W
3142 { 1840, 2, 1, 4, 0, 0, 0, 376, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1840 = XVCLZ_H
3143 { 1839, 2, 1, 4, 0, 0, 0, 376, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1839 = XVCLZ_D
3144 { 1838, 2, 1, 4, 0, 0, 0, 376, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1838 = XVCLZ_B
3145 { 1837, 2, 1, 4, 0, 0, 0, 376, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1837 = XVCLO_W
3146 { 1836, 2, 1, 4, 0, 0, 0, 376, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1836 = XVCLO_H
3147 { 1835, 2, 1, 4, 0, 0, 0, 376, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1835 = XVCLO_D
3148 { 1834, 2, 1, 4, 0, 0, 0, 376, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1834 = XVCLO_B
3149 { 1833, 3, 1, 4, 0, 0, 0, 409, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1833 = XVBSRL_V
3150 { 1832, 3, 1, 4, 0, 0, 0, 409, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1832 = XVBSLL_V
3151 { 1831, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1831 = XVBITSET_W
3152 { 1830, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1830 = XVBITSET_H
3153 { 1829, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1829 = XVBITSET_D
3154 { 1828, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1828 = XVBITSET_B
3155 { 1827, 3, 1, 4, 0, 0, 0, 409, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1827 = XVBITSETI_W
3156 { 1826, 3, 1, 4, 0, 0, 0, 409, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1826 = XVBITSETI_H
3157 { 1825, 3, 1, 4, 0, 0, 0, 409, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1825 = XVBITSETI_D
3158 { 1824, 3, 1, 4, 0, 0, 0, 409, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1824 = XVBITSETI_B
3159 { 1823, 4, 1, 4, 0, 0, 0, 416, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1823 = XVBITSEL_V
3160 { 1822, 4, 1, 4, 0, 0, 0, 412, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1822 = XVBITSELI_B
3161 { 1821, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1821 = XVBITREV_W
3162 { 1820, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1820 = XVBITREV_H
3163 { 1819, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1819 = XVBITREV_D
3164 { 1818, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1818 = XVBITREV_B
3165 { 1817, 3, 1, 4, 0, 0, 0, 409, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1817 = XVBITREVI_W
3166 { 1816, 3, 1, 4, 0, 0, 0, 409, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1816 = XVBITREVI_H
3167 { 1815, 3, 1, 4, 0, 0, 0, 409, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1815 = XVBITREVI_D
3168 { 1814, 3, 1, 4, 0, 0, 0, 409, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1814 = XVBITREVI_B
3169 { 1813, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1813 = XVBITCLR_W
3170 { 1812, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1812 = XVBITCLR_H
3171 { 1811, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1811 = XVBITCLR_D
3172 { 1810, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1810 = XVBITCLR_B
3173 { 1809, 3, 1, 4, 0, 0, 0, 409, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1809 = XVBITCLRI_W
3174 { 1808, 3, 1, 4, 0, 0, 0, 409, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1808 = XVBITCLRI_H
3175 { 1807, 3, 1, 4, 0, 0, 0, 409, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1807 = XVBITCLRI_D
3176 { 1806, 3, 1, 4, 0, 0, 0, 409, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1806 = XVBITCLRI_B
3177 { 1805, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1805 = XVAVG_WU
3178 { 1804, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1804 = XVAVG_W
3179 { 1803, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1803 = XVAVG_HU
3180 { 1802, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1802 = XVAVG_H
3181 { 1801, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1801 = XVAVG_DU
3182 { 1800, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1800 = XVAVG_D
3183 { 1799, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1799 = XVAVG_BU
3184 { 1798, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1798 = XVAVG_B
3185 { 1797, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1797 = XVAVGR_WU
3186 { 1796, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1796 = XVAVGR_W
3187 { 1795, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1795 = XVAVGR_HU
3188 { 1794, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1794 = XVAVGR_H
3189 { 1793, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1793 = XVAVGR_DU
3190 { 1792, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1792 = XVAVGR_D
3191 { 1791, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1791 = XVAVGR_BU
3192 { 1790, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1790 = XVAVGR_B
3193 { 1789, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1789 = XVAND_V
3194 { 1788, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1788 = XVANDN_V
3195 { 1787, 3, 1, 4, 0, 0, 0, 409, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1787 = XVANDI_B
3196 { 1786, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1786 = XVADD_W
3197 { 1785, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1785 = XVADD_Q
3198 { 1784, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1784 = XVADD_H
3199 { 1783, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1783 = XVADD_D
3200 { 1782, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1782 = XVADD_B
3201 { 1781, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1781 = XVADDWOD_W_HU_H
3202 { 1780, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1780 = XVADDWOD_W_HU
3203 { 1779, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1779 = XVADDWOD_W_H
3204 { 1778, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1778 = XVADDWOD_Q_DU_D
3205 { 1777, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1777 = XVADDWOD_Q_DU
3206 { 1776, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1776 = XVADDWOD_Q_D
3207 { 1775, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1775 = XVADDWOD_H_BU_B
3208 { 1774, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1774 = XVADDWOD_H_BU
3209 { 1773, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1773 = XVADDWOD_H_B
3210 { 1772, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1772 = XVADDWOD_D_WU_W
3211 { 1771, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1771 = XVADDWOD_D_WU
3212 { 1770, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1770 = XVADDWOD_D_W
3213 { 1769, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1769 = XVADDWEV_W_HU_H
3214 { 1768, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1768 = XVADDWEV_W_HU
3215 { 1767, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1767 = XVADDWEV_W_H
3216 { 1766, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1766 = XVADDWEV_Q_DU_D
3217 { 1765, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1765 = XVADDWEV_Q_DU
3218 { 1764, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1764 = XVADDWEV_Q_D
3219 { 1763, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1763 = XVADDWEV_H_BU_B
3220 { 1762, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1762 = XVADDWEV_H_BU
3221 { 1761, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1761 = XVADDWEV_H_B
3222 { 1760, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1760 = XVADDWEV_D_WU_W
3223 { 1759, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1759 = XVADDWEV_D_WU
3224 { 1758, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1758 = XVADDWEV_D_W
3225 { 1757, 3, 1, 4, 0, 0, 0, 409, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1757 = XVADDI_WU
3226 { 1756, 3, 1, 4, 0, 0, 0, 409, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1756 = XVADDI_HU
3227 { 1755, 3, 1, 4, 0, 0, 0, 409, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1755 = XVADDI_DU
3228 { 1754, 3, 1, 4, 0, 0, 0, 409, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1754 = XVADDI_BU
3229 { 1753, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1753 = XVADDA_W
3230 { 1752, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1752 = XVADDA_H
3231 { 1751, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1751 = XVADDA_D
3232 { 1750, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1750 = XVADDA_B
3233 { 1749, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1749 = XVABSD_WU
3234 { 1748, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1748 = XVABSD_W
3235 { 1747, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1747 = XVABSD_HU
3236 { 1746, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1746 = XVABSD_H
3237 { 1745, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1745 = XVABSD_DU
3238 { 1744, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1744 = XVABSD_D
3239 { 1743, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1743 = XVABSD_BU
3240 { 1742, 3, 1, 4, 0, 0, 0, 406, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1742 = XVABSD_B
3241 { 1741, 3, 1, 4, 0, 0, 0, 188, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #1741 = XORI
3242 { 1740, 3, 1, 4, 0, 0, 0, 164, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1740 = XOR
3243 { 1739, 2, 0, 4, 0, 0, 0, 170, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1739 = X86XOR_W
3244 { 1738, 2, 0, 4, 0, 0, 0, 170, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1738 = X86XOR_H
3245 { 1737, 2, 0, 4, 0, 0, 0, 170, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1737 = X86XOR_D
3246 { 1736, 2, 0, 4, 0, 0, 0, 170, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1736 = X86XOR_B
3247 { 1735, 2, 0, 4, 0, 0, 0, 170, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1735 = X86SUB_WU
3248 { 1734, 2, 0, 4, 0, 0, 0, 170, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1734 = X86SUB_W
3249 { 1733, 2, 0, 4, 0, 0, 0, 170, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1733 = X86SUB_H
3250 { 1732, 2, 0, 4, 0, 0, 0, 170, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1732 = X86SUB_DU
3251 { 1731, 2, 0, 4, 0, 0, 0, 170, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1731 = X86SUB_D
3252 { 1730, 2, 0, 4, 0, 0, 0, 170, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1730 = X86SUB_B
3253 { 1729, 2, 0, 4, 0, 0, 0, 170, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1729 = X86SRL_W
3254 { 1728, 2, 0, 4, 0, 0, 0, 170, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1728 = X86SRL_H
3255 { 1727, 2, 0, 4, 0, 0, 0, 170, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1727 = X86SRL_D
3256 { 1726, 2, 0, 4, 0, 0, 0, 170, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1726 = X86SRL_B
3257 { 1725, 2, 0, 4, 0, 0, 0, 191, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1725 = X86SRLI_W
3258 { 1724, 2, 0, 4, 0, 0, 0, 191, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1724 = X86SRLI_H
3259 { 1723, 2, 0, 4, 0, 0, 0, 191, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1723 = X86SRLI_D
3260 { 1722, 2, 0, 4, 0, 0, 0, 191, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1722 = X86SRLI_B
3261 { 1721, 2, 0, 4, 0, 0, 0, 170, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1721 = X86SRA_W
3262 { 1720, 2, 0, 4, 0, 0, 0, 170, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1720 = X86SRA_H
3263 { 1719, 2, 0, 4, 0, 0, 0, 170, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1719 = X86SRA_D
3264 { 1718, 2, 0, 4, 0, 0, 0, 170, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1718 = X86SRA_B
3265 { 1717, 2, 0, 4, 0, 0, 0, 191, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1717 = X86SRAI_W
3266 { 1716, 2, 0, 4, 0, 0, 0, 191, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1716 = X86SRAI_H
3267 { 1715, 2, 0, 4, 0, 0, 0, 191, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1715 = X86SRAI_D
3268 { 1714, 2, 0, 4, 0, 0, 0, 191, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1714 = X86SRAI_B
3269 { 1713, 2, 0, 4, 0, 0, 0, 170, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1713 = X86SLL_W
3270 { 1712, 2, 0, 4, 0, 0, 0, 170, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1712 = X86SLL_H
3271 { 1711, 2, 0, 4, 0, 0, 0, 170, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1711 = X86SLL_D
3272 { 1710, 2, 0, 4, 0, 0, 0, 170, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1710 = X86SLL_B
3273 { 1709, 2, 0, 4, 0, 0, 0, 191, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1709 = X86SLLI_W
3274 { 1708, 2, 0, 4, 0, 0, 0, 191, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1708 = X86SLLI_H
3275 { 1707, 2, 0, 4, 0, 0, 0, 191, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1707 = X86SLLI_D
3276 { 1706, 2, 0, 4, 0, 0, 0, 191, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1706 = X86SLLI_B
3277 { 1705, 0, 0, 4, 0, 0, 0, 1, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1705 = X86SETTM
3278 { 1704, 3, 1, 4, 0, 0, 0, 249, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1704 = X86SETTAG
3279 { 1703, 2, 0, 4, 0, 0, 0, 170, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1703 = X86SBC_W
3280 { 1702, 2, 0, 4, 0, 0, 0, 170, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1702 = X86SBC_H
3281 { 1701, 2, 0, 4, 0, 0, 0, 170, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1701 = X86SBC_D
3282 { 1700, 2, 0, 4, 0, 0, 0, 170, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1700 = X86SBC_B
3283 { 1699, 2, 0, 4, 0, 0, 0, 170, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1699 = X86ROTR_W
3284 { 1698, 2, 0, 4, 0, 0, 0, 170, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1698 = X86ROTR_H
3285 { 1697, 2, 0, 4, 0, 0, 0, 170, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1697 = X86ROTR_D
3286 { 1696, 2, 0, 4, 0, 0, 0, 170, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1696 = X86ROTR_B
3287 { 1695, 2, 0, 4, 0, 0, 0, 191, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1695 = X86ROTRI_W
3288 { 1694, 2, 0, 4, 0, 0, 0, 191, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1694 = X86ROTRI_H
3289 { 1693, 2, 0, 4, 0, 0, 0, 191, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1693 = X86ROTRI_D
3290 { 1692, 2, 0, 4, 0, 0, 0, 191, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1692 = X86ROTRI_B
3291 { 1691, 2, 0, 4, 0, 0, 0, 170, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1691 = X86ROTL_W
3292 { 1690, 2, 0, 4, 0, 0, 0, 170, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1690 = X86ROTL_H
3293 { 1689, 2, 0, 4, 0, 0, 0, 170, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1689 = X86ROTL_D
3294 { 1688, 2, 0, 4, 0, 0, 0, 170, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1688 = X86ROTL_B
3295 { 1687, 2, 0, 4, 0, 0, 0, 191, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1687 = X86ROTLI_W
3296 { 1686, 2, 0, 4, 0, 0, 0, 191, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1686 = X86ROTLI_H
3297 { 1685, 2, 0, 4, 0, 0, 0, 191, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1685 = X86ROTLI_D
3298 { 1684, 2, 0, 4, 0, 0, 0, 191, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1684 = X86ROTLI_B
3299 { 1683, 2, 0, 4, 0, 0, 0, 170, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1683 = X86RCR_W
3300 { 1682, 2, 0, 4, 0, 0, 0, 170, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1682 = X86RCR_H
3301 { 1681, 2, 0, 4, 0, 0, 0, 170, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1681 = X86RCR_D
3302 { 1680, 2, 0, 4, 0, 0, 0, 170, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1680 = X86RCR_B
3303 { 1679, 2, 0, 4, 0, 0, 0, 191, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1679 = X86RCRI_W
3304 { 1678, 2, 0, 4, 0, 0, 0, 191, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1678 = X86RCRI_H
3305 { 1677, 2, 0, 4, 0, 0, 0, 191, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1677 = X86RCRI_D
3306 { 1676, 2, 0, 4, 0, 0, 0, 191, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1676 = X86RCRI_B
3307 { 1675, 2, 0, 4, 0, 0, 0, 170, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1675 = X86RCL_W
3308 { 1674, 2, 0, 4, 0, 0, 0, 170, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1674 = X86RCL_H
3309 { 1673, 2, 0, 4, 0, 0, 0, 170, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1673 = X86RCL_D
3310 { 1672, 2, 0, 4, 0, 0, 0, 170, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1672 = X86RCL_B
3311 { 1671, 2, 0, 4, 0, 0, 0, 191, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1671 = X86RCLI_W
3312 { 1670, 2, 0, 4, 0, 0, 0, 191, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1670 = X86RCLI_H
3313 { 1669, 2, 0, 4, 0, 0, 0, 191, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1669 = X86RCLI_D
3314 { 1668, 2, 0, 4, 0, 0, 0, 191, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1668 = X86RCLI_B
3315 { 1667, 2, 0, 4, 0, 0, 0, 170, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1667 = X86OR_W
3316 { 1666, 2, 0, 4, 0, 0, 0, 170, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1666 = X86OR_H
3317 { 1665, 2, 0, 4, 0, 0, 0, 170, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1665 = X86OR_D
3318 { 1664, 2, 0, 4, 0, 0, 0, 170, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1664 = X86OR_B
3319 { 1663, 2, 0, 4, 0, 0, 0, 170, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1663 = X86MUL_WU
3320 { 1662, 2, 0, 4, 0, 0, 0, 170, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1662 = X86MUL_W
3321 { 1661, 2, 0, 4, 0, 0, 0, 170, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1661 = X86MUL_HU
3322 { 1660, 2, 0, 4, 0, 0, 0, 170, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1660 = X86MUL_H
3323 { 1659, 2, 0, 4, 0, 0, 0, 170, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1659 = X86MUL_DU
3324 { 1658, 2, 0, 4, 0, 0, 0, 170, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1658 = X86MUL_D
3325 { 1657, 2, 0, 4, 0, 0, 0, 170, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1657 = X86MUL_BU
3326 { 1656, 2, 0, 4, 0, 0, 0, 170, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1656 = X86MUL_B
3327 { 1655, 1, 0, 4, 0, 0, 0, 0, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1655 = X86MTTOP
3328 { 1654, 2, 1, 4, 0, 0, 0, 191, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1654 = X86MTFLAG
3329 { 1653, 1, 1, 4, 0, 0, 0, 169, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1653 = X86MFTOP
3330 { 1652, 2, 1, 4, 0, 0, 0, 191, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1652 = X86MFFLAG
3331 { 1651, 1, 0, 4, 0, 0, 0, 169, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1651 = X86INC_W
3332 { 1650, 1, 0, 4, 0, 0, 0, 169, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1650 = X86INC_H
3333 { 1649, 1, 0, 4, 0, 0, 0, 169, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1649 = X86INC_D
3334 { 1648, 1, 0, 4, 0, 0, 0, 169, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1648 = X86INC_B
3335 { 1647, 0, 0, 4, 0, 0, 0, 1, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1647 = X86INCTOP
3336 { 1646, 1, 0, 4, 0, 0, 0, 169, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1646 = X86DEC_W
3337 { 1645, 1, 0, 4, 0, 0, 0, 169, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1645 = X86DEC_H
3338 { 1644, 1, 0, 4, 0, 0, 0, 169, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1644 = X86DEC_D
3339 { 1643, 1, 0, 4, 0, 0, 0, 169, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1643 = X86DEC_B
3340 { 1642, 0, 0, 4, 0, 0, 0, 1, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1642 = X86DECTOP
3341 { 1641, 0, 0, 4, 0, 0, 0, 1, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1641 = X86CLRTM
3342 { 1640, 2, 0, 4, 0, 0, 0, 170, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1640 = X86AND_W
3343 { 1639, 2, 0, 4, 0, 0, 0, 170, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1639 = X86AND_H
3344 { 1638, 2, 0, 4, 0, 0, 0, 170, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1638 = X86AND_D
3345 { 1637, 2, 0, 4, 0, 0, 0, 170, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1637 = X86AND_B
3346 { 1636, 2, 0, 4, 0, 0, 0, 170, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1636 = X86ADD_WU
3347 { 1635, 2, 0, 4, 0, 0, 0, 170, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1635 = X86ADD_W
3348 { 1634, 2, 0, 4, 0, 0, 0, 170, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1634 = X86ADD_H
3349 { 1633, 2, 0, 4, 0, 0, 0, 170, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1633 = X86ADD_DU
3350 { 1632, 2, 0, 4, 0, 0, 0, 170, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1632 = X86ADD_D
3351 { 1631, 2, 0, 4, 0, 0, 0, 170, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1631 = X86ADD_B
3352 { 1630, 2, 0, 4, 0, 0, 0, 170, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1630 = X86ADC_W
3353 { 1629, 2, 0, 4, 0, 0, 0, 170, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1629 = X86ADC_H
3354 { 1628, 2, 0, 4, 0, 0, 0, 170, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1628 = X86ADC_D
3355 { 1627, 2, 0, 4, 0, 0, 0, 170, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1627 = X86ADC_B
3356 { 1626, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1626 = VXOR_V
3357 { 1625, 3, 1, 4, 0, 0, 0, 363, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1625 = VXORI_B
3358 { 1624, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1624 = VSUB_W
3359 { 1623, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1623 = VSUB_Q
3360 { 1622, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1622 = VSUB_H
3361 { 1621, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1621 = VSUB_D
3362 { 1620, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1620 = VSUB_B
3363 { 1619, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1619 = VSUBWOD_W_HU
3364 { 1618, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1618 = VSUBWOD_W_H
3365 { 1617, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1617 = VSUBWOD_Q_DU
3366 { 1616, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1616 = VSUBWOD_Q_D
3367 { 1615, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1615 = VSUBWOD_H_BU
3368 { 1614, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1614 = VSUBWOD_H_B
3369 { 1613, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1613 = VSUBWOD_D_WU
3370 { 1612, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1612 = VSUBWOD_D_W
3371 { 1611, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1611 = VSUBWEV_W_HU
3372 { 1610, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1610 = VSUBWEV_W_H
3373 { 1609, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1609 = VSUBWEV_Q_DU
3374 { 1608, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1608 = VSUBWEV_Q_D
3375 { 1607, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1607 = VSUBWEV_H_BU
3376 { 1606, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1606 = VSUBWEV_H_B
3377 { 1605, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1605 = VSUBWEV_D_WU
3378 { 1604, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1604 = VSUBWEV_D_W
3379 { 1603, 3, 1, 4, 0, 0, 0, 363, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1603 = VSUBI_WU
3380 { 1602, 3, 1, 4, 0, 0, 0, 363, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1602 = VSUBI_HU
3381 { 1601, 3, 1, 4, 0, 0, 0, 363, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1601 = VSUBI_DU
3382 { 1600, 3, 1, 4, 0, 0, 0, 363, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1600 = VSUBI_BU
3383 { 1599, 3, 0, 4, 0, 0, 0, 389, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #1599 = VSTX
3384 { 1598, 4, 0, 4, 0, 0, 0, 402, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #1598 = VSTELM_W
3385 { 1597, 4, 0, 4, 0, 0, 0, 402, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #1597 = VSTELM_H
3386 { 1596, 4, 0, 4, 0, 0, 0, 402, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #1596 = VSTELM_D
3387 { 1595, 4, 0, 4, 0, 0, 0, 402, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #1595 = VSTELM_B
3388 { 1594, 3, 0, 4, 0, 0, 0, 386, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #1594 = VST
3389 { 1593, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1593 = VSSUB_WU
3390 { 1592, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1592 = VSSUB_W
3391 { 1591, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1591 = VSSUB_HU
3392 { 1590, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1590 = VSSUB_H
3393 { 1589, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1589 = VSSUB_DU
3394 { 1588, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1588 = VSSUB_D
3395 { 1587, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1587 = VSSUB_BU
3396 { 1586, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1586 = VSSUB_B
3397 { 1585, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1585 = VSSRLRN_W_D
3398 { 1584, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1584 = VSSRLRN_WU_D
3399 { 1583, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1583 = VSSRLRN_H_W
3400 { 1582, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1582 = VSSRLRN_HU_W
3401 { 1581, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1581 = VSSRLRN_B_H
3402 { 1580, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1580 = VSSRLRN_BU_H
3403 { 1579, 4, 1, 4, 0, 0, 0, 366, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1579 = VSSRLRNI_W_D
3404 { 1578, 4, 1, 4, 0, 0, 0, 366, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1578 = VSSRLRNI_WU_D
3405 { 1577, 4, 1, 4, 0, 0, 0, 366, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1577 = VSSRLRNI_H_W
3406 { 1576, 4, 1, 4, 0, 0, 0, 366, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1576 = VSSRLRNI_HU_W
3407 { 1575, 4, 1, 4, 0, 0, 0, 366, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1575 = VSSRLRNI_D_Q
3408 { 1574, 4, 1, 4, 0, 0, 0, 366, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1574 = VSSRLRNI_DU_Q
3409 { 1573, 4, 1, 4, 0, 0, 0, 366, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1573 = VSSRLRNI_B_H
3410 { 1572, 4, 1, 4, 0, 0, 0, 366, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1572 = VSSRLRNI_BU_H
3411 { 1571, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1571 = VSSRLN_W_D
3412 { 1570, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1570 = VSSRLN_WU_D
3413 { 1569, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1569 = VSSRLN_H_W
3414 { 1568, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1568 = VSSRLN_HU_W
3415 { 1567, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1567 = VSSRLN_B_H
3416 { 1566, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1566 = VSSRLN_BU_H
3417 { 1565, 4, 1, 4, 0, 0, 0, 366, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1565 = VSSRLNI_W_D
3418 { 1564, 4, 1, 4, 0, 0, 0, 366, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1564 = VSSRLNI_WU_D
3419 { 1563, 4, 1, 4, 0, 0, 0, 366, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1563 = VSSRLNI_H_W
3420 { 1562, 4, 1, 4, 0, 0, 0, 366, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1562 = VSSRLNI_HU_W
3421 { 1561, 4, 1, 4, 0, 0, 0, 366, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1561 = VSSRLNI_D_Q
3422 { 1560, 4, 1, 4, 0, 0, 0, 366, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1560 = VSSRLNI_DU_Q
3423 { 1559, 4, 1, 4, 0, 0, 0, 366, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1559 = VSSRLNI_B_H
3424 { 1558, 4, 1, 4, 0, 0, 0, 366, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1558 = VSSRLNI_BU_H
3425 { 1557, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1557 = VSSRARN_W_D
3426 { 1556, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1556 = VSSRARN_WU_D
3427 { 1555, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1555 = VSSRARN_H_W
3428 { 1554, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1554 = VSSRARN_HU_W
3429 { 1553, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1553 = VSSRARN_B_H
3430 { 1552, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1552 = VSSRARN_BU_H
3431 { 1551, 4, 1, 4, 0, 0, 0, 366, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1551 = VSSRARNI_W_D
3432 { 1550, 4, 1, 4, 0, 0, 0, 366, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1550 = VSSRARNI_WU_D
3433 { 1549, 4, 1, 4, 0, 0, 0, 366, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1549 = VSSRARNI_H_W
3434 { 1548, 4, 1, 4, 0, 0, 0, 366, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1548 = VSSRARNI_HU_W
3435 { 1547, 4, 1, 4, 0, 0, 0, 366, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1547 = VSSRARNI_D_Q
3436 { 1546, 4, 1, 4, 0, 0, 0, 366, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1546 = VSSRARNI_DU_Q
3437 { 1545, 4, 1, 4, 0, 0, 0, 366, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1545 = VSSRARNI_B_H
3438 { 1544, 4, 1, 4, 0, 0, 0, 366, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1544 = VSSRARNI_BU_H
3439 { 1543, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1543 = VSSRAN_W_D
3440 { 1542, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1542 = VSSRAN_WU_D
3441 { 1541, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1541 = VSSRAN_H_W
3442 { 1540, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1540 = VSSRAN_HU_W
3443 { 1539, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1539 = VSSRAN_B_H
3444 { 1538, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1538 = VSSRAN_BU_H
3445 { 1537, 4, 1, 4, 0, 0, 0, 366, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1537 = VSSRANI_W_D
3446 { 1536, 4, 1, 4, 0, 0, 0, 366, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1536 = VSSRANI_WU_D
3447 { 1535, 4, 1, 4, 0, 0, 0, 366, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1535 = VSSRANI_H_W
3448 { 1534, 4, 1, 4, 0, 0, 0, 366, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1534 = VSSRANI_HU_W
3449 { 1533, 4, 1, 4, 0, 0, 0, 366, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1533 = VSSRANI_D_Q
3450 { 1532, 4, 1, 4, 0, 0, 0, 366, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1532 = VSSRANI_DU_Q
3451 { 1531, 4, 1, 4, 0, 0, 0, 366, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1531 = VSSRANI_B_H
3452 { 1530, 4, 1, 4, 0, 0, 0, 366, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1530 = VSSRANI_BU_H
3453 { 1529, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1529 = VSRL_W
3454 { 1528, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1528 = VSRL_H
3455 { 1527, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1527 = VSRL_D
3456 { 1526, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1526 = VSRL_B
3457 { 1525, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1525 = VSRLR_W
3458 { 1524, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1524 = VSRLR_H
3459 { 1523, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1523 = VSRLR_D
3460 { 1522, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1522 = VSRLR_B
3461 { 1521, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1521 = VSRLRN_W_D
3462 { 1520, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1520 = VSRLRN_H_W
3463 { 1519, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1519 = VSRLRN_B_H
3464 { 1518, 4, 1, 4, 0, 0, 0, 366, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1518 = VSRLRNI_W_D
3465 { 1517, 4, 1, 4, 0, 0, 0, 366, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1517 = VSRLRNI_H_W
3466 { 1516, 4, 1, 4, 0, 0, 0, 366, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1516 = VSRLRNI_D_Q
3467 { 1515, 4, 1, 4, 0, 0, 0, 366, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1515 = VSRLRNI_B_H
3468 { 1514, 3, 1, 4, 0, 0, 0, 363, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1514 = VSRLRI_W
3469 { 1513, 3, 1, 4, 0, 0, 0, 363, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1513 = VSRLRI_H
3470 { 1512, 3, 1, 4, 0, 0, 0, 363, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1512 = VSRLRI_D
3471 { 1511, 3, 1, 4, 0, 0, 0, 363, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1511 = VSRLRI_B
3472 { 1510, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1510 = VSRLN_W_D
3473 { 1509, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1509 = VSRLN_H_W
3474 { 1508, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1508 = VSRLN_B_H
3475 { 1507, 4, 1, 4, 0, 0, 0, 366, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1507 = VSRLNI_W_D
3476 { 1506, 4, 1, 4, 0, 0, 0, 366, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1506 = VSRLNI_H_W
3477 { 1505, 4, 1, 4, 0, 0, 0, 366, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1505 = VSRLNI_D_Q
3478 { 1504, 4, 1, 4, 0, 0, 0, 366, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1504 = VSRLNI_B_H
3479 { 1503, 3, 1, 4, 0, 0, 0, 363, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1503 = VSRLI_W
3480 { 1502, 3, 1, 4, 0, 0, 0, 363, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1502 = VSRLI_H
3481 { 1501, 3, 1, 4, 0, 0, 0, 363, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1501 = VSRLI_D
3482 { 1500, 3, 1, 4, 0, 0, 0, 363, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1500 = VSRLI_B
3483 { 1499, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1499 = VSRA_W
3484 { 1498, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1498 = VSRA_H
3485 { 1497, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1497 = VSRA_D
3486 { 1496, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1496 = VSRA_B
3487 { 1495, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1495 = VSRAR_W
3488 { 1494, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1494 = VSRAR_H
3489 { 1493, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1493 = VSRAR_D
3490 { 1492, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1492 = VSRAR_B
3491 { 1491, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1491 = VSRARN_W_D
3492 { 1490, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1490 = VSRARN_H_W
3493 { 1489, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1489 = VSRARN_B_H
3494 { 1488, 4, 1, 4, 0, 0, 0, 366, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1488 = VSRARNI_W_D
3495 { 1487, 4, 1, 4, 0, 0, 0, 366, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1487 = VSRARNI_H_W
3496 { 1486, 4, 1, 4, 0, 0, 0, 366, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1486 = VSRARNI_D_Q
3497 { 1485, 4, 1, 4, 0, 0, 0, 366, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1485 = VSRARNI_B_H
3498 { 1484, 3, 1, 4, 0, 0, 0, 363, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1484 = VSRARI_W
3499 { 1483, 3, 1, 4, 0, 0, 0, 363, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1483 = VSRARI_H
3500 { 1482, 3, 1, 4, 0, 0, 0, 363, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1482 = VSRARI_D
3501 { 1481, 3, 1, 4, 0, 0, 0, 363, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1481 = VSRARI_B
3502 { 1480, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1480 = VSRAN_W_D
3503 { 1479, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1479 = VSRAN_H_W
3504 { 1478, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1478 = VSRAN_B_H
3505 { 1477, 4, 1, 4, 0, 0, 0, 366, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1477 = VSRANI_W_D
3506 { 1476, 4, 1, 4, 0, 0, 0, 366, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1476 = VSRANI_H_W
3507 { 1475, 4, 1, 4, 0, 0, 0, 366, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1475 = VSRANI_D_Q
3508 { 1474, 4, 1, 4, 0, 0, 0, 366, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1474 = VSRANI_B_H
3509 { 1473, 3, 1, 4, 0, 0, 0, 363, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1473 = VSRAI_W
3510 { 1472, 3, 1, 4, 0, 0, 0, 363, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1472 = VSRAI_H
3511 { 1471, 3, 1, 4, 0, 0, 0, 363, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1471 = VSRAI_D
3512 { 1470, 3, 1, 4, 0, 0, 0, 363, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1470 = VSRAI_B
3513 { 1469, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1469 = VSLT_WU
3514 { 1468, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1468 = VSLT_W
3515 { 1467, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1467 = VSLT_HU
3516 { 1466, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1466 = VSLT_H
3517 { 1465, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1465 = VSLT_DU
3518 { 1464, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1464 = VSLT_D
3519 { 1463, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1463 = VSLT_BU
3520 { 1462, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1462 = VSLT_B
3521 { 1461, 3, 1, 4, 0, 0, 0, 363, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1461 = VSLTI_WU
3522 { 1460, 3, 1, 4, 0, 0, 0, 363, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1460 = VSLTI_W
3523 { 1459, 3, 1, 4, 0, 0, 0, 363, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1459 = VSLTI_HU
3524 { 1458, 3, 1, 4, 0, 0, 0, 363, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1458 = VSLTI_H
3525 { 1457, 3, 1, 4, 0, 0, 0, 363, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1457 = VSLTI_DU
3526 { 1456, 3, 1, 4, 0, 0, 0, 363, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1456 = VSLTI_D
3527 { 1455, 3, 1, 4, 0, 0, 0, 363, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1455 = VSLTI_BU
3528 { 1454, 3, 1, 4, 0, 0, 0, 363, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1454 = VSLTI_B
3529 { 1453, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1453 = VSLL_W
3530 { 1452, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1452 = VSLL_H
3531 { 1451, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1451 = VSLL_D
3532 { 1450, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1450 = VSLL_B
3533 { 1449, 3, 1, 4, 0, 0, 0, 363, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1449 = VSLLWIL_W_H
3534 { 1448, 3, 1, 4, 0, 0, 0, 363, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1448 = VSLLWIL_WU_HU
3535 { 1447, 3, 1, 4, 0, 0, 0, 363, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1447 = VSLLWIL_H_B
3536 { 1446, 3, 1, 4, 0, 0, 0, 363, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1446 = VSLLWIL_HU_BU
3537 { 1445, 3, 1, 4, 0, 0, 0, 363, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1445 = VSLLWIL_D_W
3538 { 1444, 3, 1, 4, 0, 0, 0, 363, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1444 = VSLLWIL_DU_WU
3539 { 1443, 3, 1, 4, 0, 0, 0, 363, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1443 = VSLLI_W
3540 { 1442, 3, 1, 4, 0, 0, 0, 363, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1442 = VSLLI_H
3541 { 1441, 3, 1, 4, 0, 0, 0, 363, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1441 = VSLLI_D
3542 { 1440, 3, 1, 4, 0, 0, 0, 363, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1440 = VSLLI_B
3543 { 1439, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1439 = VSLE_WU
3544 { 1438, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1438 = VSLE_W
3545 { 1437, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1437 = VSLE_HU
3546 { 1436, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1436 = VSLE_H
3547 { 1435, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1435 = VSLE_DU
3548 { 1434, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1434 = VSLE_D
3549 { 1433, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1433 = VSLE_BU
3550 { 1432, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1432 = VSLE_B
3551 { 1431, 3, 1, 4, 0, 0, 0, 363, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1431 = VSLEI_WU
3552 { 1430, 3, 1, 4, 0, 0, 0, 363, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1430 = VSLEI_W
3553 { 1429, 3, 1, 4, 0, 0, 0, 363, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1429 = VSLEI_HU
3554 { 1428, 3, 1, 4, 0, 0, 0, 363, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1428 = VSLEI_H
3555 { 1427, 3, 1, 4, 0, 0, 0, 363, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1427 = VSLEI_DU
3556 { 1426, 3, 1, 4, 0, 0, 0, 363, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1426 = VSLEI_D
3557 { 1425, 3, 1, 4, 0, 0, 0, 363, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1425 = VSLEI_BU
3558 { 1424, 3, 1, 4, 0, 0, 0, 363, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1424 = VSLEI_B
3559 { 1423, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1423 = VSIGNCOV_W
3560 { 1422, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1422 = VSIGNCOV_H
3561 { 1421, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1421 = VSIGNCOV_D
3562 { 1420, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1420 = VSIGNCOV_B
3563 { 1419, 4, 1, 4, 0, 0, 0, 378, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1419 = VSHUF_W
3564 { 1418, 4, 1, 4, 0, 0, 0, 378, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1418 = VSHUF_H
3565 { 1417, 4, 1, 4, 0, 0, 0, 378, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1417 = VSHUF_D
3566 { 1416, 4, 1, 4, 0, 0, 0, 370, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1416 = VSHUF_B
3567 { 1415, 3, 1, 4, 0, 0, 0, 363, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1415 = VSHUF4I_W
3568 { 1414, 3, 1, 4, 0, 0, 0, 363, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1414 = VSHUF4I_H
3569 { 1413, 4, 1, 4, 0, 0, 0, 366, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1413 = VSHUF4I_D
3570 { 1412, 3, 1, 4, 0, 0, 0, 363, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1412 = VSHUF4I_B
3571 { 1411, 2, 1, 4, 0, 0, 0, 400, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1411 = VSETNEZ_V
3572 { 1410, 2, 1, 4, 0, 0, 0, 400, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1410 = VSETEQZ_V
3573 { 1409, 2, 1, 4, 0, 0, 0, 400, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1409 = VSETANYEQZ_W
3574 { 1408, 2, 1, 4, 0, 0, 0, 400, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1408 = VSETANYEQZ_H
3575 { 1407, 2, 1, 4, 0, 0, 0, 400, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1407 = VSETANYEQZ_D
3576 { 1406, 2, 1, 4, 0, 0, 0, 400, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1406 = VSETANYEQZ_B
3577 { 1405, 2, 1, 4, 0, 0, 0, 400, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1405 = VSETALLNEZ_W
3578 { 1404, 2, 1, 4, 0, 0, 0, 400, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1404 = VSETALLNEZ_H
3579 { 1403, 2, 1, 4, 0, 0, 0, 400, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1403 = VSETALLNEZ_D
3580 { 1402, 2, 1, 4, 0, 0, 0, 400, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1402 = VSETALLNEZ_B
3581 { 1401, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1401 = VSEQ_W
3582 { 1400, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1400 = VSEQ_H
3583 { 1399, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1399 = VSEQ_D
3584 { 1398, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1398 = VSEQ_B
3585 { 1397, 3, 1, 4, 0, 0, 0, 363, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1397 = VSEQI_W
3586 { 1396, 3, 1, 4, 0, 0, 0, 363, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1396 = VSEQI_H
3587 { 1395, 3, 1, 4, 0, 0, 0, 363, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1395 = VSEQI_D
3588 { 1394, 3, 1, 4, 0, 0, 0, 363, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1394 = VSEQI_B
3589 { 1393, 3, 1, 4, 0, 0, 0, 363, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1393 = VSAT_WU
3590 { 1392, 3, 1, 4, 0, 0, 0, 363, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1392 = VSAT_W
3591 { 1391, 3, 1, 4, 0, 0, 0, 363, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1391 = VSAT_HU
3592 { 1390, 3, 1, 4, 0, 0, 0, 363, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1390 = VSAT_H
3593 { 1389, 3, 1, 4, 0, 0, 0, 363, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1389 = VSAT_DU
3594 { 1388, 3, 1, 4, 0, 0, 0, 363, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1388 = VSAT_D
3595 { 1387, 3, 1, 4, 0, 0, 0, 363, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1387 = VSAT_BU
3596 { 1386, 3, 1, 4, 0, 0, 0, 363, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1386 = VSAT_B
3597 { 1385, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1385 = VSADD_WU
3598 { 1384, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1384 = VSADD_W
3599 { 1383, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1383 = VSADD_HU
3600 { 1382, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1382 = VSADD_H
3601 { 1381, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1381 = VSADD_DU
3602 { 1380, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1380 = VSADD_D
3603 { 1379, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1379 = VSADD_BU
3604 { 1378, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1378 = VSADD_B
3605 { 1377, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1377 = VROTR_W
3606 { 1376, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1376 = VROTR_H
3607 { 1375, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1375 = VROTR_D
3608 { 1374, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1374 = VROTR_B
3609 { 1373, 3, 1, 4, 0, 0, 0, 363, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1373 = VROTRI_W
3610 { 1372, 3, 1, 4, 0, 0, 0, 363, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1372 = VROTRI_H
3611 { 1371, 3, 1, 4, 0, 0, 0, 363, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1371 = VROTRI_D
3612 { 1370, 3, 1, 4, 0, 0, 0, 363, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1370 = VROTRI_B
3613 { 1369, 3, 1, 4, 0, 0, 0, 397, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1369 = VREPLVE_W
3614 { 1368, 3, 1, 4, 0, 0, 0, 397, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1368 = VREPLVE_H
3615 { 1367, 3, 1, 4, 0, 0, 0, 397, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1367 = VREPLVE_D
3616 { 1366, 3, 1, 4, 0, 0, 0, 397, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1366 = VREPLVE_B
3617 { 1365, 3, 1, 4, 0, 0, 0, 363, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1365 = VREPLVEI_W
3618 { 1364, 3, 1, 4, 0, 0, 0, 363, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1364 = VREPLVEI_H
3619 { 1363, 3, 1, 4, 0, 0, 0, 363, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1363 = VREPLVEI_D
3620 { 1362, 3, 1, 4, 0, 0, 0, 363, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1362 = VREPLVEI_B
3621 { 1361, 2, 1, 4, 0, 0, 0, 395, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1361 = VREPLGR2VR_W
3622 { 1360, 2, 1, 4, 0, 0, 0, 395, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1360 = VREPLGR2VR_H
3623 { 1359, 2, 1, 4, 0, 0, 0, 395, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1359 = VREPLGR2VR_D
3624 { 1358, 2, 1, 4, 0, 0, 0, 395, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1358 = VREPLGR2VR_B
3625 { 1357, 3, 1, 4, 0, 0, 0, 392, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1357 = VPICKVE2GR_WU
3626 { 1356, 3, 1, 4, 0, 0, 0, 392, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1356 = VPICKVE2GR_W
3627 { 1355, 3, 1, 4, 0, 0, 0, 392, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1355 = VPICKVE2GR_HU
3628 { 1354, 3, 1, 4, 0, 0, 0, 392, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1354 = VPICKVE2GR_H
3629 { 1353, 3, 1, 4, 0, 0, 0, 392, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1353 = VPICKVE2GR_DU
3630 { 1352, 3, 1, 4, 0, 0, 0, 392, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1352 = VPICKVE2GR_D
3631 { 1351, 3, 1, 4, 0, 0, 0, 392, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1351 = VPICKVE2GR_BU
3632 { 1350, 3, 1, 4, 0, 0, 0, 392, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1350 = VPICKVE2GR_B
3633 { 1349, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1349 = VPICKOD_W
3634 { 1348, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1348 = VPICKOD_H
3635 { 1347, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1347 = VPICKOD_D
3636 { 1346, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1346 = VPICKOD_B
3637 { 1345, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1345 = VPICKEV_W
3638 { 1344, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1344 = VPICKEV_H
3639 { 1343, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1343 = VPICKEV_D
3640 { 1342, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1342 = VPICKEV_B
3641 { 1341, 4, 1, 4, 0, 0, 0, 366, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1341 = VPERMI_W
3642 { 1340, 2, 1, 4, 0, 0, 0, 374, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1340 = VPCNT_W
3643 { 1339, 2, 1, 4, 0, 0, 0, 374, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1339 = VPCNT_H
3644 { 1338, 2, 1, 4, 0, 0, 0, 374, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1338 = VPCNT_D
3645 { 1337, 2, 1, 4, 0, 0, 0, 374, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1337 = VPCNT_B
3646 { 1336, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1336 = VPACKOD_W
3647 { 1335, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1335 = VPACKOD_H
3648 { 1334, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1334 = VPACKOD_D
3649 { 1333, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1333 = VPACKOD_B
3650 { 1332, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1332 = VPACKEV_W
3651 { 1331, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1331 = VPACKEV_H
3652 { 1330, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1330 = VPACKEV_D
3653 { 1329, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1329 = VPACKEV_B
3654 { 1328, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1328 = VOR_V
3655 { 1327, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1327 = VORN_V
3656 { 1326, 3, 1, 4, 0, 0, 0, 363, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1326 = VORI_B
3657 { 1325, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1325 = VNOR_V
3658 { 1324, 3, 1, 4, 0, 0, 0, 363, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1324 = VNORI_B
3659 { 1323, 2, 1, 4, 0, 0, 0, 374, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1323 = VNEG_W
3660 { 1322, 2, 1, 4, 0, 0, 0, 374, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1322 = VNEG_H
3661 { 1321, 2, 1, 4, 0, 0, 0, 374, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1321 = VNEG_D
3662 { 1320, 2, 1, 4, 0, 0, 0, 374, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1320 = VNEG_B
3663 { 1319, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1319 = VMUL_W
3664 { 1318, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1318 = VMUL_H
3665 { 1317, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1317 = VMUL_D
3666 { 1316, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1316 = VMUL_B
3667 { 1315, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1315 = VMULWOD_W_HU_H
3668 { 1314, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1314 = VMULWOD_W_HU
3669 { 1313, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1313 = VMULWOD_W_H
3670 { 1312, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1312 = VMULWOD_Q_DU_D
3671 { 1311, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1311 = VMULWOD_Q_DU
3672 { 1310, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1310 = VMULWOD_Q_D
3673 { 1309, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1309 = VMULWOD_H_BU_B
3674 { 1308, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1308 = VMULWOD_H_BU
3675 { 1307, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1307 = VMULWOD_H_B
3676 { 1306, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1306 = VMULWOD_D_WU_W
3677 { 1305, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1305 = VMULWOD_D_WU
3678 { 1304, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1304 = VMULWOD_D_W
3679 { 1303, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1303 = VMULWEV_W_HU_H
3680 { 1302, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1302 = VMULWEV_W_HU
3681 { 1301, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1301 = VMULWEV_W_H
3682 { 1300, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1300 = VMULWEV_Q_DU_D
3683 { 1299, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1299 = VMULWEV_Q_DU
3684 { 1298, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1298 = VMULWEV_Q_D
3685 { 1297, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1297 = VMULWEV_H_BU_B
3686 { 1296, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1296 = VMULWEV_H_BU
3687 { 1295, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1295 = VMULWEV_H_B
3688 { 1294, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1294 = VMULWEV_D_WU_W
3689 { 1293, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1293 = VMULWEV_D_WU
3690 { 1292, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1292 = VMULWEV_D_W
3691 { 1291, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1291 = VMUH_WU
3692 { 1290, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1290 = VMUH_W
3693 { 1289, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1289 = VMUH_HU
3694 { 1288, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1288 = VMUH_H
3695 { 1287, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1287 = VMUH_DU
3696 { 1286, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1286 = VMUH_D
3697 { 1285, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1285 = VMUH_BU
3698 { 1284, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1284 = VMUH_B
3699 { 1283, 4, 1, 4, 0, 0, 0, 378, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1283 = VMSUB_W
3700 { 1282, 4, 1, 4, 0, 0, 0, 378, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1282 = VMSUB_H
3701 { 1281, 4, 1, 4, 0, 0, 0, 378, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1281 = VMSUB_D
3702 { 1280, 4, 1, 4, 0, 0, 0, 378, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1280 = VMSUB_B
3703 { 1279, 2, 1, 4, 0, 0, 0, 374, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1279 = VMSKNZ_B
3704 { 1278, 2, 1, 4, 0, 0, 0, 374, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1278 = VMSKLTZ_W
3705 { 1277, 2, 1, 4, 0, 0, 0, 374, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1277 = VMSKLTZ_H
3706 { 1276, 2, 1, 4, 0, 0, 0, 374, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1276 = VMSKLTZ_D
3707 { 1275, 2, 1, 4, 0, 0, 0, 374, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1275 = VMSKLTZ_B
3708 { 1274, 2, 1, 4, 0, 0, 0, 374, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1274 = VMSKGEZ_B
3709 { 1273, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1273 = VMOD_WU
3710 { 1272, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1272 = VMOD_W
3711 { 1271, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1271 = VMOD_HU
3712 { 1270, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1270 = VMOD_H
3713 { 1269, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1269 = VMOD_DU
3714 { 1268, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1268 = VMOD_D
3715 { 1267, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1267 = VMOD_BU
3716 { 1266, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1266 = VMOD_B
3717 { 1265, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1265 = VMIN_WU
3718 { 1264, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1264 = VMIN_W
3719 { 1263, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1263 = VMIN_HU
3720 { 1262, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1262 = VMIN_H
3721 { 1261, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1261 = VMIN_DU
3722 { 1260, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1260 = VMIN_D
3723 { 1259, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1259 = VMIN_BU
3724 { 1258, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1258 = VMIN_B
3725 { 1257, 3, 1, 4, 0, 0, 0, 363, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1257 = VMINI_WU
3726 { 1256, 3, 1, 4, 0, 0, 0, 363, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1256 = VMINI_W
3727 { 1255, 3, 1, 4, 0, 0, 0, 363, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1255 = VMINI_HU
3728 { 1254, 3, 1, 4, 0, 0, 0, 363, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1254 = VMINI_H
3729 { 1253, 3, 1, 4, 0, 0, 0, 363, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1253 = VMINI_DU
3730 { 1252, 3, 1, 4, 0, 0, 0, 363, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1252 = VMINI_D
3731 { 1251, 3, 1, 4, 0, 0, 0, 363, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1251 = VMINI_BU
3732 { 1250, 3, 1, 4, 0, 0, 0, 363, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1250 = VMINI_B
3733 { 1249, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1249 = VMAX_WU
3734 { 1248, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1248 = VMAX_W
3735 { 1247, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1247 = VMAX_HU
3736 { 1246, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1246 = VMAX_H
3737 { 1245, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1245 = VMAX_DU
3738 { 1244, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1244 = VMAX_D
3739 { 1243, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1243 = VMAX_BU
3740 { 1242, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1242 = VMAX_B
3741 { 1241, 3, 1, 4, 0, 0, 0, 363, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1241 = VMAXI_WU
3742 { 1240, 3, 1, 4, 0, 0, 0, 363, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1240 = VMAXI_W
3743 { 1239, 3, 1, 4, 0, 0, 0, 363, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1239 = VMAXI_HU
3744 { 1238, 3, 1, 4, 0, 0, 0, 363, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1238 = VMAXI_H
3745 { 1237, 3, 1, 4, 0, 0, 0, 363, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1237 = VMAXI_DU
3746 { 1236, 3, 1, 4, 0, 0, 0, 363, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1236 = VMAXI_D
3747 { 1235, 3, 1, 4, 0, 0, 0, 363, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1235 = VMAXI_BU
3748 { 1234, 3, 1, 4, 0, 0, 0, 363, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1234 = VMAXI_B
3749 { 1233, 4, 1, 4, 0, 0, 0, 378, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1233 = VMADD_W
3750 { 1232, 4, 1, 4, 0, 0, 0, 378, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1232 = VMADD_H
3751 { 1231, 4, 1, 4, 0, 0, 0, 378, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1231 = VMADD_D
3752 { 1230, 4, 1, 4, 0, 0, 0, 378, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1230 = VMADD_B
3753 { 1229, 4, 1, 4, 0, 0, 0, 378, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1229 = VMADDWOD_W_HU_H
3754 { 1228, 4, 1, 4, 0, 0, 0, 378, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1228 = VMADDWOD_W_HU
3755 { 1227, 4, 1, 4, 0, 0, 0, 378, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1227 = VMADDWOD_W_H
3756 { 1226, 4, 1, 4, 0, 0, 0, 378, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1226 = VMADDWOD_Q_DU_D
3757 { 1225, 4, 1, 4, 0, 0, 0, 378, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1225 = VMADDWOD_Q_DU
3758 { 1224, 4, 1, 4, 0, 0, 0, 378, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1224 = VMADDWOD_Q_D
3759 { 1223, 4, 1, 4, 0, 0, 0, 378, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1223 = VMADDWOD_H_BU_B
3760 { 1222, 4, 1, 4, 0, 0, 0, 378, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1222 = VMADDWOD_H_BU
3761 { 1221, 4, 1, 4, 0, 0, 0, 378, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1221 = VMADDWOD_H_B
3762 { 1220, 4, 1, 4, 0, 0, 0, 378, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1220 = VMADDWOD_D_WU_W
3763 { 1219, 4, 1, 4, 0, 0, 0, 378, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1219 = VMADDWOD_D_WU
3764 { 1218, 4, 1, 4, 0, 0, 0, 378, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1218 = VMADDWOD_D_W
3765 { 1217, 4, 1, 4, 0, 0, 0, 378, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1217 = VMADDWEV_W_HU_H
3766 { 1216, 4, 1, 4, 0, 0, 0, 378, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1216 = VMADDWEV_W_HU
3767 { 1215, 4, 1, 4, 0, 0, 0, 378, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1215 = VMADDWEV_W_H
3768 { 1214, 4, 1, 4, 0, 0, 0, 378, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1214 = VMADDWEV_Q_DU_D
3769 { 1213, 4, 1, 4, 0, 0, 0, 378, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1213 = VMADDWEV_Q_DU
3770 { 1212, 4, 1, 4, 0, 0, 0, 378, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1212 = VMADDWEV_Q_D
3771 { 1211, 4, 1, 4, 0, 0, 0, 378, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1211 = VMADDWEV_H_BU_B
3772 { 1210, 4, 1, 4, 0, 0, 0, 378, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1210 = VMADDWEV_H_BU
3773 { 1209, 4, 1, 4, 0, 0, 0, 378, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1209 = VMADDWEV_H_B
3774 { 1208, 4, 1, 4, 0, 0, 0, 378, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1208 = VMADDWEV_D_WU_W
3775 { 1207, 4, 1, 4, 0, 0, 0, 378, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1207 = VMADDWEV_D_WU
3776 { 1206, 4, 1, 4, 0, 0, 0, 378, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1206 = VMADDWEV_D_W
3777 { 1205, 3, 1, 4, 0, 0, 0, 389, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #1205 = VLDX
3778 { 1204, 3, 1, 4, 0, 0, 0, 386, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #1204 = VLDREPL_W
3779 { 1203, 3, 1, 4, 0, 0, 0, 386, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #1203 = VLDREPL_H
3780 { 1202, 3, 1, 4, 0, 0, 0, 386, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #1202 = VLDREPL_D
3781 { 1201, 3, 1, 4, 0, 0, 0, 386, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #1201 = VLDREPL_B
3782 { 1200, 2, 1, 4, 0, 0, 0, 221, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #1200 = VLDI
3783 { 1199, 3, 1, 4, 0, 0, 0, 386, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #1199 = VLD
3784 { 1198, 4, 1, 4, 0, 0, 0, 382, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1198 = VINSGR2VR_W
3785 { 1197, 4, 1, 4, 0, 0, 0, 382, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1197 = VINSGR2VR_H
3786 { 1196, 4, 1, 4, 0, 0, 0, 382, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1196 = VINSGR2VR_D
3787 { 1195, 4, 1, 4, 0, 0, 0, 382, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1195 = VINSGR2VR_B
3788 { 1194, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1194 = VILVL_W
3789 { 1193, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1193 = VILVL_H
3790 { 1192, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1192 = VILVL_D
3791 { 1191, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1191 = VILVL_B
3792 { 1190, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1190 = VILVH_W
3793 { 1189, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1189 = VILVH_H
3794 { 1188, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1188 = VILVH_D
3795 { 1187, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1187 = VILVH_B
3796 { 1186, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1186 = VHSUBW_W_H
3797 { 1185, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1185 = VHSUBW_WU_HU
3798 { 1184, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1184 = VHSUBW_Q_D
3799 { 1183, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1183 = VHSUBW_QU_DU
3800 { 1182, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1182 = VHSUBW_H_B
3801 { 1181, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1181 = VHSUBW_HU_BU
3802 { 1180, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1180 = VHSUBW_D_W
3803 { 1179, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1179 = VHSUBW_DU_WU
3804 { 1178, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1178 = VHADDW_W_H
3805 { 1177, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1177 = VHADDW_WU_HU
3806 { 1176, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1176 = VHADDW_Q_D
3807 { 1175, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1175 = VHADDW_QU_DU
3808 { 1174, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1174 = VHADDW_H_B
3809 { 1173, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1173 = VHADDW_HU_BU
3810 { 1172, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1172 = VHADDW_D_W
3811 { 1171, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1171 = VHADDW_DU_WU
3812 { 1170, 2, 1, 4, 0, 0, 0, 374, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1170 = VFTINT_W_S
3813 { 1169, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1169 = VFTINT_W_D
3814 { 1168, 2, 1, 4, 0, 0, 0, 374, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1168 = VFTINT_WU_S
3815 { 1167, 2, 1, 4, 0, 0, 0, 374, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1167 = VFTINT_L_D
3816 { 1166, 2, 1, 4, 0, 0, 0, 374, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1166 = VFTINT_LU_D
3817 { 1165, 2, 1, 4, 0, 0, 0, 374, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1165 = VFTINTRZ_W_S
3818 { 1164, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1164 = VFTINTRZ_W_D
3819 { 1163, 2, 1, 4, 0, 0, 0, 374, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1163 = VFTINTRZ_WU_S
3820 { 1162, 2, 1, 4, 0, 0, 0, 374, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1162 = VFTINTRZ_L_D
3821 { 1161, 2, 1, 4, 0, 0, 0, 374, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1161 = VFTINTRZ_LU_D
3822 { 1160, 2, 1, 4, 0, 0, 0, 374, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1160 = VFTINTRZL_L_S
3823 { 1159, 2, 1, 4, 0, 0, 0, 374, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1159 = VFTINTRZH_L_S
3824 { 1158, 2, 1, 4, 0, 0, 0, 374, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1158 = VFTINTRP_W_S
3825 { 1157, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1157 = VFTINTRP_W_D
3826 { 1156, 2, 1, 4, 0, 0, 0, 374, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1156 = VFTINTRP_L_D
3827 { 1155, 2, 1, 4, 0, 0, 0, 374, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1155 = VFTINTRPL_L_S
3828 { 1154, 2, 1, 4, 0, 0, 0, 374, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1154 = VFTINTRPH_L_S
3829 { 1153, 2, 1, 4, 0, 0, 0, 374, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1153 = VFTINTRNE_W_S
3830 { 1152, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1152 = VFTINTRNE_W_D
3831 { 1151, 2, 1, 4, 0, 0, 0, 374, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1151 = VFTINTRNE_L_D
3832 { 1150, 2, 1, 4, 0, 0, 0, 374, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1150 = VFTINTRNEL_L_S
3833 { 1149, 2, 1, 4, 0, 0, 0, 374, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1149 = VFTINTRNEH_L_S
3834 { 1148, 2, 1, 4, 0, 0, 0, 374, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1148 = VFTINTRM_W_S
3835 { 1147, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1147 = VFTINTRM_W_D
3836 { 1146, 2, 1, 4, 0, 0, 0, 374, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1146 = VFTINTRM_L_D
3837 { 1145, 2, 1, 4, 0, 0, 0, 374, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1145 = VFTINTRML_L_S
3838 { 1144, 2, 1, 4, 0, 0, 0, 374, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1144 = VFTINTRMH_L_S
3839 { 1143, 2, 1, 4, 0, 0, 0, 374, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1143 = VFTINTL_L_S
3840 { 1142, 2, 1, 4, 0, 0, 0, 374, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1142 = VFTINTH_L_S
3841 { 1141, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1141 = VFSUB_S
3842 { 1140, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1140 = VFSUB_D
3843 { 1139, 2, 1, 4, 0, 0, 0, 374, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1139 = VFSQRT_S
3844 { 1138, 2, 1, 4, 0, 0, 0, 374, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1138 = VFSQRT_D
3845 { 1137, 4, 1, 4, 0, 0, 0, 378, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1137 = VFRSTP_H
3846 { 1136, 4, 1, 4, 0, 0, 0, 378, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1136 = VFRSTP_B
3847 { 1135, 4, 1, 4, 0, 0, 0, 366, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1135 = VFRSTPI_H
3848 { 1134, 4, 1, 4, 0, 0, 0, 366, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1134 = VFRSTPI_B
3849 { 1133, 2, 1, 4, 0, 0, 0, 374, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1133 = VFRSQRT_S
3850 { 1132, 2, 1, 4, 0, 0, 0, 374, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1132 = VFRSQRT_D
3851 { 1131, 2, 1, 4, 0, 0, 0, 374, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1131 = VFRSQRTE_S
3852 { 1130, 2, 1, 4, 0, 0, 0, 374, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1130 = VFRSQRTE_D
3853 { 1129, 2, 1, 4, 0, 0, 0, 374, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1129 = VFRINT_S
3854 { 1128, 2, 1, 4, 0, 0, 0, 374, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1128 = VFRINT_D
3855 { 1127, 2, 1, 4, 0, 0, 0, 374, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1127 = VFRINTRZ_S
3856 { 1126, 2, 1, 4, 0, 0, 0, 374, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1126 = VFRINTRZ_D
3857 { 1125, 2, 1, 4, 0, 0, 0, 374, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1125 = VFRINTRP_S
3858 { 1124, 2, 1, 4, 0, 0, 0, 374, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1124 = VFRINTRP_D
3859 { 1123, 2, 1, 4, 0, 0, 0, 374, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1123 = VFRINTRNE_S
3860 { 1122, 2, 1, 4, 0, 0, 0, 374, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1122 = VFRINTRNE_D
3861 { 1121, 2, 1, 4, 0, 0, 0, 374, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1121 = VFRINTRM_S
3862 { 1120, 2, 1, 4, 0, 0, 0, 374, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1120 = VFRINTRM_D
3863 { 1119, 2, 1, 4, 0, 0, 0, 374, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1119 = VFRECIP_S
3864 { 1118, 2, 1, 4, 0, 0, 0, 374, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1118 = VFRECIP_D
3865 { 1117, 2, 1, 4, 0, 0, 0, 374, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1117 = VFRECIPE_S
3866 { 1116, 2, 1, 4, 0, 0, 0, 374, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1116 = VFRECIPE_D
3867 { 1115, 4, 1, 4, 0, 0, 0, 370, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1115 = VFNMSUB_S
3868 { 1114, 4, 1, 4, 0, 0, 0, 370, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1114 = VFNMSUB_D
3869 { 1113, 4, 1, 4, 0, 0, 0, 370, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1113 = VFNMADD_S
3870 { 1112, 4, 1, 4, 0, 0, 0, 370, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1112 = VFNMADD_D
3871 { 1111, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1111 = VFMUL_S
3872 { 1110, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1110 = VFMUL_D
3873 { 1109, 4, 1, 4, 0, 0, 0, 370, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1109 = VFMSUB_S
3874 { 1108, 4, 1, 4, 0, 0, 0, 370, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1108 = VFMSUB_D
3875 { 1107, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1107 = VFMIN_S
3876 { 1106, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1106 = VFMIN_D
3877 { 1105, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1105 = VFMINA_S
3878 { 1104, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1104 = VFMINA_D
3879 { 1103, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1103 = VFMAX_S
3880 { 1102, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1102 = VFMAX_D
3881 { 1101, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1101 = VFMAXA_S
3882 { 1100, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1100 = VFMAXA_D
3883 { 1099, 4, 1, 4, 0, 0, 0, 370, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1099 = VFMADD_S
3884 { 1098, 4, 1, 4, 0, 0, 0, 370, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1098 = VFMADD_D
3885 { 1097, 2, 1, 4, 0, 0, 0, 374, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1097 = VFLOGB_S
3886 { 1096, 2, 1, 4, 0, 0, 0, 374, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1096 = VFLOGB_D
3887 { 1095, 2, 1, 4, 0, 0, 0, 374, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1095 = VFFINT_S_WU
3888 { 1094, 2, 1, 4, 0, 0, 0, 374, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1094 = VFFINT_S_W
3889 { 1093, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1093 = VFFINT_S_L
3890 { 1092, 2, 1, 4, 0, 0, 0, 374, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1092 = VFFINT_D_LU
3891 { 1091, 2, 1, 4, 0, 0, 0, 374, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1091 = VFFINT_D_L
3892 { 1090, 2, 1, 4, 0, 0, 0, 374, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1090 = VFFINTL_D_W
3893 { 1089, 2, 1, 4, 0, 0, 0, 374, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1089 = VFFINTH_D_W
3894 { 1088, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1088 = VFDIV_S
3895 { 1087, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1087 = VFDIV_D
3896 { 1086, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1086 = VFCVT_S_D
3897 { 1085, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1085 = VFCVT_H_S
3898 { 1084, 2, 1, 4, 0, 0, 0, 374, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1084 = VFCVTL_S_H
3899 { 1083, 2, 1, 4, 0, 0, 0, 374, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1083 = VFCVTL_D_S
3900 { 1082, 2, 1, 4, 0, 0, 0, 374, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1082 = VFCVTH_S_H
3901 { 1081, 2, 1, 4, 0, 0, 0, 374, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1081 = VFCVTH_D_S
3902 { 1080, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1080 = VFCMP_SUN_S
3903 { 1079, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1079 = VFCMP_SUN_D
3904 { 1078, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1078 = VFCMP_SUNE_S
3905 { 1077, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1077 = VFCMP_SUNE_D
3906 { 1076, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1076 = VFCMP_SULT_S
3907 { 1075, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1075 = VFCMP_SULT_D
3908 { 1074, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1074 = VFCMP_SULE_S
3909 { 1073, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1073 = VFCMP_SULE_D
3910 { 1072, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1072 = VFCMP_SUEQ_S
3911 { 1071, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1071 = VFCMP_SUEQ_D
3912 { 1070, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1070 = VFCMP_SOR_S
3913 { 1069, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1069 = VFCMP_SOR_D
3914 { 1068, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1068 = VFCMP_SNE_S
3915 { 1067, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1067 = VFCMP_SNE_D
3916 { 1066, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1066 = VFCMP_SLT_S
3917 { 1065, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1065 = VFCMP_SLT_D
3918 { 1064, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1064 = VFCMP_SLE_S
3919 { 1063, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1063 = VFCMP_SLE_D
3920 { 1062, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1062 = VFCMP_SEQ_S
3921 { 1061, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1061 = VFCMP_SEQ_D
3922 { 1060, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1060 = VFCMP_SAF_S
3923 { 1059, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1059 = VFCMP_SAF_D
3924 { 1058, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1058 = VFCMP_CUN_S
3925 { 1057, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1057 = VFCMP_CUN_D
3926 { 1056, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1056 = VFCMP_CUNE_S
3927 { 1055, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1055 = VFCMP_CUNE_D
3928 { 1054, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1054 = VFCMP_CULT_S
3929 { 1053, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1053 = VFCMP_CULT_D
3930 { 1052, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1052 = VFCMP_CULE_S
3931 { 1051, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1051 = VFCMP_CULE_D
3932 { 1050, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1050 = VFCMP_CUEQ_S
3933 { 1049, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1049 = VFCMP_CUEQ_D
3934 { 1048, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1048 = VFCMP_COR_S
3935 { 1047, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1047 = VFCMP_COR_D
3936 { 1046, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1046 = VFCMP_CNE_S
3937 { 1045, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1045 = VFCMP_CNE_D
3938 { 1044, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1044 = VFCMP_CLT_S
3939 { 1043, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1043 = VFCMP_CLT_D
3940 { 1042, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1042 = VFCMP_CLE_S
3941 { 1041, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1041 = VFCMP_CLE_D
3942 { 1040, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1040 = VFCMP_CEQ_S
3943 { 1039, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1039 = VFCMP_CEQ_D
3944 { 1038, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1038 = VFCMP_CAF_S
3945 { 1037, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1037 = VFCMP_CAF_D
3946 { 1036, 2, 1, 4, 0, 0, 0, 374, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1036 = VFCLASS_S
3947 { 1035, 2, 1, 4, 0, 0, 0, 374, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1035 = VFCLASS_D
3948 { 1034, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1034 = VFADD_S
3949 { 1033, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1033 = VFADD_D
3950 { 1032, 4, 1, 4, 0, 0, 0, 366, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1032 = VEXTRINS_W
3951 { 1031, 4, 1, 4, 0, 0, 0, 366, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1031 = VEXTRINS_H
3952 { 1030, 4, 1, 4, 0, 0, 0, 366, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1030 = VEXTRINS_D
3953 { 1029, 4, 1, 4, 0, 0, 0, 366, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1029 = VEXTRINS_B
3954 { 1028, 2, 1, 4, 0, 0, 0, 374, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1028 = VEXTL_Q_D
3955 { 1027, 2, 1, 4, 0, 0, 0, 374, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1027 = VEXTL_QU_DU
3956 { 1026, 2, 1, 4, 0, 0, 0, 374, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1026 = VEXTH_W_H
3957 { 1025, 2, 1, 4, 0, 0, 0, 374, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1025 = VEXTH_WU_HU
3958 { 1024, 2, 1, 4, 0, 0, 0, 374, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1024 = VEXTH_Q_D
3959 { 1023, 2, 1, 4, 0, 0, 0, 374, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1023 = VEXTH_QU_DU
3960 { 1022, 2, 1, 4, 0, 0, 0, 374, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1022 = VEXTH_H_B
3961 { 1021, 2, 1, 4, 0, 0, 0, 374, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1021 = VEXTH_HU_BU
3962 { 1020, 2, 1, 4, 0, 0, 0, 374, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1020 = VEXTH_D_W
3963 { 1019, 2, 1, 4, 0, 0, 0, 374, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1019 = VEXTH_DU_WU
3964 { 1018, 2, 1, 4, 0, 0, 0, 376, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1018 = VEXT2XV_W_H
3965 { 1017, 2, 1, 4, 0, 0, 0, 376, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1017 = VEXT2XV_W_B
3966 { 1016, 2, 1, 4, 0, 0, 0, 376, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1016 = VEXT2XV_WU_HU
3967 { 1015, 2, 1, 4, 0, 0, 0, 376, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1015 = VEXT2XV_WU_BU
3968 { 1014, 2, 1, 4, 0, 0, 0, 376, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1014 = VEXT2XV_H_B
3969 { 1013, 2, 1, 4, 0, 0, 0, 376, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1013 = VEXT2XV_HU_BU
3970 { 1012, 2, 1, 4, 0, 0, 0, 376, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1012 = VEXT2XV_D_W
3971 { 1011, 2, 1, 4, 0, 0, 0, 376, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1011 = VEXT2XV_D_H
3972 { 1010, 2, 1, 4, 0, 0, 0, 376, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1010 = VEXT2XV_D_B
3973 { 1009, 2, 1, 4, 0, 0, 0, 376, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1009 = VEXT2XV_DU_WU
3974 { 1008, 2, 1, 4, 0, 0, 0, 376, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1008 = VEXT2XV_DU_HU
3975 { 1007, 2, 1, 4, 0, 0, 0, 376, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1007 = VEXT2XV_DU_BU
3976 { 1006, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1006 = VDIV_WU
3977 { 1005, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1005 = VDIV_W
3978 { 1004, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1004 = VDIV_HU
3979 { 1003, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1003 = VDIV_H
3980 { 1002, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1002 = VDIV_DU
3981 { 1001, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1001 = VDIV_D
3982 { 1000, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #1000 = VDIV_BU
3983 { 999, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #999 = VDIV_B
3984 { 998, 2, 1, 4, 0, 0, 0, 374, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #998 = VCLZ_W
3985 { 997, 2, 1, 4, 0, 0, 0, 374, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #997 = VCLZ_H
3986 { 996, 2, 1, 4, 0, 0, 0, 374, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #996 = VCLZ_D
3987 { 995, 2, 1, 4, 0, 0, 0, 374, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #995 = VCLZ_B
3988 { 994, 2, 1, 4, 0, 0, 0, 374, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #994 = VCLO_W
3989 { 993, 2, 1, 4, 0, 0, 0, 374, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #993 = VCLO_H
3990 { 992, 2, 1, 4, 0, 0, 0, 374, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #992 = VCLO_D
3991 { 991, 2, 1, 4, 0, 0, 0, 374, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #991 = VCLO_B
3992 { 990, 3, 1, 4, 0, 0, 0, 363, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #990 = VBSRL_V
3993 { 989, 3, 1, 4, 0, 0, 0, 363, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #989 = VBSLL_V
3994 { 988, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #988 = VBITSET_W
3995 { 987, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #987 = VBITSET_H
3996 { 986, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #986 = VBITSET_D
3997 { 985, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #985 = VBITSET_B
3998 { 984, 3, 1, 4, 0, 0, 0, 363, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #984 = VBITSETI_W
3999 { 983, 3, 1, 4, 0, 0, 0, 363, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #983 = VBITSETI_H
4000 { 982, 3, 1, 4, 0, 0, 0, 363, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #982 = VBITSETI_D
4001 { 981, 3, 1, 4, 0, 0, 0, 363, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #981 = VBITSETI_B
4002 { 980, 4, 1, 4, 0, 0, 0, 370, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #980 = VBITSEL_V
4003 { 979, 4, 1, 4, 0, 0, 0, 366, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #979 = VBITSELI_B
4004 { 978, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #978 = VBITREV_W
4005 { 977, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #977 = VBITREV_H
4006 { 976, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #976 = VBITREV_D
4007 { 975, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #975 = VBITREV_B
4008 { 974, 3, 1, 4, 0, 0, 0, 363, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #974 = VBITREVI_W
4009 { 973, 3, 1, 4, 0, 0, 0, 363, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #973 = VBITREVI_H
4010 { 972, 3, 1, 4, 0, 0, 0, 363, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #972 = VBITREVI_D
4011 { 971, 3, 1, 4, 0, 0, 0, 363, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #971 = VBITREVI_B
4012 { 970, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #970 = VBITCLR_W
4013 { 969, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #969 = VBITCLR_H
4014 { 968, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #968 = VBITCLR_D
4015 { 967, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #967 = VBITCLR_B
4016 { 966, 3, 1, 4, 0, 0, 0, 363, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #966 = VBITCLRI_W
4017 { 965, 3, 1, 4, 0, 0, 0, 363, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #965 = VBITCLRI_H
4018 { 964, 3, 1, 4, 0, 0, 0, 363, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #964 = VBITCLRI_D
4019 { 963, 3, 1, 4, 0, 0, 0, 363, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #963 = VBITCLRI_B
4020 { 962, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #962 = VAVG_WU
4021 { 961, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #961 = VAVG_W
4022 { 960, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #960 = VAVG_HU
4023 { 959, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #959 = VAVG_H
4024 { 958, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #958 = VAVG_DU
4025 { 957, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #957 = VAVG_D
4026 { 956, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #956 = VAVG_BU
4027 { 955, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #955 = VAVG_B
4028 { 954, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #954 = VAVGR_WU
4029 { 953, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #953 = VAVGR_W
4030 { 952, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #952 = VAVGR_HU
4031 { 951, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #951 = VAVGR_H
4032 { 950, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #950 = VAVGR_DU
4033 { 949, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #949 = VAVGR_D
4034 { 948, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #948 = VAVGR_BU
4035 { 947, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #947 = VAVGR_B
4036 { 946, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #946 = VAND_V
4037 { 945, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #945 = VANDN_V
4038 { 944, 3, 1, 4, 0, 0, 0, 363, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #944 = VANDI_B
4039 { 943, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #943 = VADD_W
4040 { 942, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #942 = VADD_Q
4041 { 941, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #941 = VADD_H
4042 { 940, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #940 = VADD_D
4043 { 939, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #939 = VADD_B
4044 { 938, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #938 = VADDWOD_W_HU_H
4045 { 937, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #937 = VADDWOD_W_HU
4046 { 936, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #936 = VADDWOD_W_H
4047 { 935, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #935 = VADDWOD_Q_DU_D
4048 { 934, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #934 = VADDWOD_Q_DU
4049 { 933, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #933 = VADDWOD_Q_D
4050 { 932, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #932 = VADDWOD_H_BU_B
4051 { 931, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #931 = VADDWOD_H_BU
4052 { 930, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #930 = VADDWOD_H_B
4053 { 929, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #929 = VADDWOD_D_WU_W
4054 { 928, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #928 = VADDWOD_D_WU
4055 { 927, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #927 = VADDWOD_D_W
4056 { 926, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #926 = VADDWEV_W_HU_H
4057 { 925, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #925 = VADDWEV_W_HU
4058 { 924, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #924 = VADDWEV_W_H
4059 { 923, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #923 = VADDWEV_Q_DU_D
4060 { 922, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #922 = VADDWEV_Q_DU
4061 { 921, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #921 = VADDWEV_Q_D
4062 { 920, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #920 = VADDWEV_H_BU_B
4063 { 919, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #919 = VADDWEV_H_BU
4064 { 918, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #918 = VADDWEV_H_B
4065 { 917, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #917 = VADDWEV_D_WU_W
4066 { 916, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #916 = VADDWEV_D_WU
4067 { 915, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #915 = VADDWEV_D_W
4068 { 914, 3, 1, 4, 0, 0, 0, 363, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #914 = VADDI_WU
4069 { 913, 3, 1, 4, 0, 0, 0, 363, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #913 = VADDI_HU
4070 { 912, 3, 1, 4, 0, 0, 0, 363, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #912 = VADDI_DU
4071 { 911, 3, 1, 4, 0, 0, 0, 363, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #911 = VADDI_BU
4072 { 910, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #910 = VADDA_W
4073 { 909, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #909 = VADDA_H
4074 { 908, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #908 = VADDA_D
4075 { 907, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #907 = VADDA_B
4076 { 906, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #906 = VABSD_WU
4077 { 905, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #905 = VABSD_W
4078 { 904, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #904 = VABSD_HU
4079 { 903, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #903 = VABSD_H
4080 { 902, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #902 = VABSD_DU
4081 { 901, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #901 = VABSD_D
4082 { 900, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #900 = VABSD_BU
4083 { 899, 3, 1, 4, 0, 0, 0, 360, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #899 = VABSD_B
4084 { 898, 0, 0, 4, 0, 0, 0, 1, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #898 = TLBWR
4085 { 897, 0, 0, 4, 0, 0, 0, 1, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #897 = TLBSRCH
4086 { 896, 0, 0, 4, 0, 0, 0, 1, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #896 = TLBRD
4087 { 895, 0, 0, 4, 0, 0, 0, 1, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #895 = TLBFLUSH
4088 { 894, 0, 0, 4, 0, 0, 0, 1, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #894 = TLBFILL
4089 { 893, 0, 0, 4, 0, 0, 0, 1, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #893 = TLBCLR
4090 { 892, 1, 0, 4, 0, 0, 0, 0, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #892 = SYSCALL
4091 { 891, 3, 1, 4, 0, 0, 0, 164, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #891 = SUB_W
4092 { 890, 3, 1, 4, 0, 0, 0, 164, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #890 = SUB_D
4093 { 889, 3, 0, 4, 0, 0, 0, 188, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #889 = ST_W
4094 { 888, 3, 0, 4, 0, 0, 0, 188, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #888 = ST_H
4095 { 887, 3, 0, 4, 0, 0, 0, 188, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #887 = ST_D
4096 { 886, 3, 0, 4, 0, 0, 0, 188, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #886 = ST_B
4097 { 885, 3, 0, 4, 0, 0, 0, 164, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #885 = STX_W
4098 { 884, 3, 0, 4, 0, 0, 0, 164, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #884 = STX_H
4099 { 883, 3, 0, 4, 0, 0, 0, 164, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #883 = STX_D
4100 { 882, 3, 0, 4, 0, 0, 0, 164, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #882 = STX_B
4101 { 881, 3, 0, 4, 0, 0, 0, 188, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #881 = STR_W
4102 { 880, 3, 0, 4, 0, 0, 0, 188, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #880 = STR_D
4103 { 879, 3, 0, 4, 0, 0, 0, 188, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #879 = STPTR_W
4104 { 878, 3, 0, 4, 0, 0, 0, 188, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #878 = STPTR_D
4105 { 877, 3, 0, 4, 0, 0, 0, 188, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #877 = STL_W
4106 { 876, 3, 0, 4, 0, 0, 0, 188, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #876 = STL_D
4107 { 875, 3, 0, 4, 0, 0, 0, 164, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #875 = STLE_W
4108 { 874, 3, 0, 4, 0, 0, 0, 164, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #874 = STLE_H
4109 { 873, 3, 0, 4, 0, 0, 0, 164, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #873 = STLE_D
4110 { 872, 3, 0, 4, 0, 0, 0, 164, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #872 = STLE_B
4111 { 871, 3, 0, 4, 0, 0, 0, 164, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #871 = STGT_W
4112 { 870, 3, 0, 4, 0, 0, 0, 164, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #870 = STGT_H
4113 { 869, 3, 0, 4, 0, 0, 0, 164, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #869 = STGT_D
4114 { 868, 3, 0, 4, 0, 0, 0, 164, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #868 = STGT_B
4115 { 867, 3, 1, 4, 0, 0, 0, 164, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #867 = SRL_W
4116 { 866, 3, 1, 4, 0, 0, 0, 164, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #866 = SRL_D
4117 { 865, 3, 1, 4, 0, 0, 0, 188, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #865 = SRLI_W
4118 { 864, 3, 1, 4, 0, 0, 0, 188, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #864 = SRLI_D
4119 { 863, 3, 1, 4, 0, 0, 0, 164, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #863 = SRA_W
4120 { 862, 3, 1, 4, 0, 0, 0, 164, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #862 = SRA_D
4121 { 861, 3, 1, 4, 0, 0, 0, 188, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #861 = SRAI_W
4122 { 860, 3, 1, 4, 0, 0, 0, 188, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #860 = SRAI_D
4123 { 859, 3, 1, 4, 0, 0, 0, 188, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #859 = SLTUI
4124 { 858, 3, 1, 4, 0, 0, 0, 164, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #858 = SLTU
4125 { 857, 3, 1, 4, 0, 0, 0, 188, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #857 = SLTI
4126 { 856, 3, 1, 4, 0, 0, 0, 164, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #856 = SLT
4127 { 855, 3, 1, 4, 0, 0, 0, 164, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #855 = SLL_W
4128 { 854, 3, 1, 4, 0, 0, 0, 164, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #854 = SLL_D
4129 { 853, 3, 1, 4, 0, 0, 0, 188, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #853 = SLLI_W
4130 { 852, 3, 1, 4, 0, 0, 0, 188, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #852 = SLLI_D
4131 { 851, 1, 1, 4, 0, 0, 0, 359, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #851 = SET_CFR_TRUE
4132 { 850, 1, 1, 4, 0, 0, 0, 359, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #850 = SET_CFR_FALSE
4133 { 849, 2, 1, 4, 0, 0, 0, 170, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #849 = SETX86LOOPNE
4134 { 848, 2, 1, 4, 0, 0, 0, 170, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #848 = SETX86LOOPE
4135 { 847, 2, 1, 4, 0, 0, 0, 191, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #847 = SETX86J
4136 { 846, 2, 1, 4, 0, 0, 0, 191, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #846 = SETARMJ
4137 { 845, 4, 1, 4, 0, 0, 0, 351, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #845 = SC_W
4138 { 844, 4, 1, 4, 0, 0, 0, 355, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #844 = SC_Q
4139 { 843, 4, 1, 4, 0, 0, 0, 351, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #843 = SC_D
4140 { 842, 3, 1, 4, 0, 0, 0, 348, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #842 = SCREL_W
4141 { 841, 3, 1, 4, 0, 0, 0, 348, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #841 = SCREL_D
4142 { 840, 3, 1, 4, 0, 0, 0, 164, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #840 = SBC_W
4143 { 839, 3, 1, 4, 0, 0, 0, 164, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #839 = SBC_H
4144 { 838, 3, 1, 4, 0, 0, 0, 164, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #838 = SBC_D
4145 { 837, 3, 1, 4, 0, 0, 0, 164, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #837 = SBC_B
4146 { 836, 3, 1, 4, 0, 0, 0, 164, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #836 = ROTR_W
4147 { 835, 3, 1, 4, 0, 0, 0, 164, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #835 = ROTR_H
4148 { 834, 3, 1, 4, 0, 0, 0, 164, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #834 = ROTR_D
4149 { 833, 3, 1, 4, 0, 0, 0, 164, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #833 = ROTR_B
4150 { 832, 3, 1, 4, 0, 0, 0, 188, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #832 = ROTRI_W
4151 { 831, 3, 1, 4, 0, 0, 0, 188, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #831 = ROTRI_H
4152 { 830, 3, 1, 4, 0, 0, 0, 188, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #830 = ROTRI_D
4153 { 829, 3, 1, 4, 0, 0, 0, 188, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #829 = ROTRI_B
4154 { 828, 2, 1, 4, 0, 0, 0, 170, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #828 = REVH_D
4155 { 827, 2, 1, 4, 0, 0, 0, 170, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #827 = REVH_2W
4156 { 826, 2, 1, 4, 0, 0, 0, 170, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #826 = REVB_D
4157 { 825, 2, 1, 4, 0, 0, 0, 170, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #825 = REVB_4H
4158 { 824, 2, 1, 4, 0, 0, 0, 170, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #824 = REVB_2W
4159 { 823, 2, 1, 4, 0, 0, 0, 170, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #823 = REVB_2H
4160 { 822, 2, 2, 4, 0, 0, 0, 170, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #822 = RDTIME_D
4161 { 821, 2, 2, 4, 0, 0, 0, 170, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #821 = RDTIMEL_W
4162 { 820, 2, 2, 4, 0, 0, 0, 170, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #820 = RDTIMEH_W
4163 { 819, 3, 1, 4, 0, 0, 0, 164, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #819 = RCR_W
4164 { 818, 3, 1, 4, 0, 0, 0, 164, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #818 = RCR_H
4165 { 817, 3, 1, 4, 0, 0, 0, 164, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #817 = RCR_D
4166 { 816, 3, 1, 4, 0, 0, 0, 164, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #816 = RCR_B
4167 { 815, 3, 1, 4, 0, 0, 0, 188, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #815 = RCRI_W
4168 { 814, 3, 1, 4, 0, 0, 0, 188, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #814 = RCRI_H
4169 { 813, 3, 1, 4, 0, 0, 0, 188, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #813 = RCRI_D
4170 { 812, 3, 1, 4, 0, 0, 0, 188, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #812 = RCRI_B
4171 { 811, 3, 0, 4, 0, 0, 0, 345, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #811 = PRELDX
4172 { 810, 3, 0, 4, 0, 0, 0, 263, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #810 = PRELD
4173 { 809, 2, 1, 4, 0, 0, 0, 191, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #809 = PCALAU12I
4174 { 808, 2, 1, 4, 0, 0, 0, 191, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #808 = PCADDU18I
4175 { 807, 2, 1, 4, 0, 0, 0, 191, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #807 = PCADDU12I
4176 { 806, 2, 1, 4, 0, 0, 0, 191, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #806 = PCADDI
4177 { 805, 3, 1, 4, 0, 0, 0, 164, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #805 = ORN
4178 { 804, 3, 1, 4, 0, 0, 0, 188, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #804 = ORI
4179 { 803, 3, 1, 4, 0, 0, 0, 164, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #803 = OR
4180 { 802, 3, 1, 4, 0, 0, 0, 164, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #802 = NOR
4181 { 801, 3, 1, 4, 0, 0, 0, 164, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #801 = MUL_W
4182 { 800, 3, 1, 4, 0, 0, 0, 164, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #800 = MUL_D
4183 { 799, 3, 1, 4, 0, 0, 0, 164, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #799 = MULW_D_WU
4184 { 798, 3, 1, 4, 0, 0, 0, 164, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #798 = MULW_D_W
4185 { 797, 3, 1, 4, 0, 0, 0, 164, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #797 = MULH_WU
4186 { 796, 3, 1, 4, 0, 0, 0, 164, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #796 = MULH_W
4187 { 795, 3, 1, 4, 0, 0, 0, 164, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #795 = MULH_DU
4188 { 794, 3, 1, 4, 0, 0, 0, 164, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #794 = MULH_D
4189 { 793, 2, 1, 4, 0, 0, 0, 343, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #793 = MOVSCR2GR
4190 { 792, 2, 1, 4, 0, 0, 0, 341, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #792 = MOVGR2SCR
4191 { 791, 2, 1, 4, 0, 0, 0, 337, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #791 = MOVGR2FR_W_64
4192 { 790, 2, 1, 4, 0, 0, 0, 339, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #790 = MOVGR2FR_W
4193 { 789, 2, 1, 4, 0, 0, 0, 337, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #789 = MOVGR2FR_D
4194 { 788, 3, 1, 4, 0, 0, 0, 334, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #788 = MOVGR2FRH_W
4195 { 787, 2, 1, 4, 0, 0, 0, 332, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #787 = MOVGR2FCSR
4196 { 786, 2, 1, 4, 0, 0, 0, 330, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #786 = MOVGR2CF
4197 { 785, 2, 1, 4, 0, 0, 0, 326, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #785 = MOVFRH2GR_S
4198 { 784, 2, 1, 4, 0, 0, 0, 326, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #784 = MOVFR2GR_S_64
4199 { 783, 2, 1, 4, 0, 0, 0, 328, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #783 = MOVFR2GR_S
4200 { 782, 2, 1, 4, 0, 0, 0, 326, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #782 = MOVFR2GR_D
4201 { 781, 2, 1, 4, 0, 0, 0, 324, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #781 = MOVFR2CF_xS
4202 { 780, 2, 1, 4, 0, 0, 0, 322, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #780 = MOVFCSR2GR
4203 { 779, 2, 1, 4, 0, 0, 0, 320, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #779 = MOVCF2GR
4204 { 778, 2, 1, 4, 0, 0, 0, 318, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #778 = MOVCF2FR_xS
4205 { 777, 3, 1, 4, 0, 0, 0, 164, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #777 = MOD_WU
4206 { 776, 3, 1, 4, 0, 0, 0, 164, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #776 = MOD_W
4207 { 775, 3, 1, 4, 0, 0, 0, 164, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #775 = MOD_DU
4208 { 774, 3, 1, 4, 0, 0, 0, 164, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #774 = MOD_D
4209 { 773, 3, 1, 4, 0, 0, 0, 164, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #773 = MASKNEZ
4210 { 772, 3, 1, 4, 0, 0, 0, 164, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #772 = MASKEQZ
4211 { 771, 3, 1, 4, 0, 0, 0, 188, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Rematerializable), 0x0ULL }, // Inst #771 = LU52I_D
4212 { 770, 3, 1, 4, 0, 0, 0, 266, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Rematerializable), 0x0ULL }, // Inst #770 = LU32I_D
4213 { 769, 2, 1, 4, 0, 0, 0, 191, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Rematerializable), 0x0ULL }, // Inst #769 = LU12I_W
4214 { 768, 3, 1, 4, 0, 0, 0, 188, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #768 = LL_W
4215 { 767, 3, 1, 4, 0, 0, 0, 188, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #767 = LL_D
4216 { 766, 2, 1, 4, 0, 0, 0, 170, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #766 = LLACQ_W
4217 { 765, 2, 1, 4, 0, 0, 0, 170, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #765 = LLACQ_D
4218 { 764, 3, 1, 4, 0, 0, 0, 188, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #764 = LD_WU
4219 { 763, 3, 1, 4, 0, 0, 0, 188, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #763 = LD_W
4220 { 762, 3, 1, 4, 0, 0, 0, 188, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #762 = LD_HU
4221 { 761, 3, 1, 4, 0, 0, 0, 188, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #761 = LD_H
4222 { 760, 3, 1, 4, 0, 0, 0, 188, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #760 = LD_D
4223 { 759, 3, 1, 4, 0, 0, 0, 188, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #759 = LD_BU
4224 { 758, 3, 1, 4, 0, 0, 0, 188, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #758 = LD_B
4225 { 757, 3, 1, 4, 0, 0, 0, 164, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #757 = LDX_WU
4226 { 756, 3, 1, 4, 0, 0, 0, 164, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #756 = LDX_W
4227 { 755, 3, 1, 4, 0, 0, 0, 164, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #755 = LDX_HU
4228 { 754, 3, 1, 4, 0, 0, 0, 164, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #754 = LDX_H
4229 { 753, 3, 1, 4, 0, 0, 0, 164, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #753 = LDX_D
4230 { 752, 3, 1, 4, 0, 0, 0, 164, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #752 = LDX_BU
4231 { 751, 3, 1, 4, 0, 0, 0, 164, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #751 = LDX_B
4232 { 750, 3, 1, 4, 0, 0, 0, 188, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #750 = LDR_W
4233 { 749, 3, 1, 4, 0, 0, 0, 188, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #749 = LDR_D
4234 { 748, 3, 1, 4, 0, 0, 0, 188, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #748 = LDPTR_W
4235 { 747, 3, 1, 4, 0, 0, 0, 188, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #747 = LDPTR_D
4236 { 746, 2, 0, 4, 0, 0, 0, 191, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #746 = LDPTE
4237 { 745, 3, 1, 4, 0, 0, 0, 188, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #745 = LDL_W
4238 { 744, 3, 1, 4, 0, 0, 0, 188, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #744 = LDL_D
4239 { 743, 3, 1, 4, 0, 0, 0, 164, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #743 = LDLE_W
4240 { 742, 3, 1, 4, 0, 0, 0, 164, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #742 = LDLE_H
4241 { 741, 3, 1, 4, 0, 0, 0, 164, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #741 = LDLE_D
4242 { 740, 3, 1, 4, 0, 0, 0, 164, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #740 = LDLE_B
4243 { 739, 3, 1, 4, 0, 0, 0, 164, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #739 = LDGT_W
4244 { 738, 3, 1, 4, 0, 0, 0, 164, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #738 = LDGT_H
4245 { 737, 3, 1, 4, 0, 0, 0, 164, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #737 = LDGT_D
4246 { 736, 3, 1, 4, 0, 0, 0, 164, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #736 = LDGT_B
4247 { 735, 3, 1, 4, 0, 0, 0, 188, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #735 = LDDIR
4248 { 734, 1, 0, 4, 0, 0, 0, 0, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #734 = JISCR1
4249 { 733, 1, 0, 4, 0, 0, 0, 0, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #733 = JISCR0
4250 { 732, 3, 1, 4, 0, 0, 0, 188, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #732 = JIRL
4251 { 731, 2, 0, 4, 0, 0, 0, 170, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #731 = IOCSRWR_W
4252 { 730, 2, 0, 4, 0, 0, 0, 170, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #730 = IOCSRWR_H
4253 { 729, 2, 0, 4, 0, 0, 0, 170, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #729 = IOCSRWR_D
4254 { 728, 2, 0, 4, 0, 0, 0, 170, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #728 = IOCSRWR_B
4255 { 727, 2, 1, 4, 0, 0, 0, 170, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #727 = IOCSRRD_W
4256 { 726, 2, 1, 4, 0, 0, 0, 170, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #726 = IOCSRRD_H
4257 { 725, 2, 1, 4, 0, 0, 0, 170, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #725 = IOCSRRD_D
4258 { 724, 2, 1, 4, 0, 0, 0, 170, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #724 = IOCSRRD_B
4259 { 723, 3, 0, 4, 0, 0, 0, 188, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #723 = INVTLB
4260 { 722, 1, 0, 4, 0, 0, 0, 0, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #722 = IDLE
4261 { 721, 1, 0, 4, 0, 0, 0, 0, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #721 = IBAR
4262 { 720, 1, 0, 4, 0, 0, 0, 0, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #720 = HVCL
4263 { 719, 0, 0, 4, 0, 0, 0, 1, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #719 = GTLBFLUSH
4264 { 718, 4, 1, 4, 0, 0, 0, 269, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #718 = GCSRXCHG
4265 { 717, 3, 1, 4, 0, 0, 0, 266, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #717 = GCSRWR
4266 { 716, 2, 1, 4, 0, 0, 0, 191, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #716 = GCSRRD
4267 { 715, 2, 1, 4, 0, 0, 0, 275, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #715 = FTINT_W_S
4268 { 714, 2, 1, 4, 0, 0, 0, 291, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #714 = FTINT_W_D
4269 { 713, 2, 1, 4, 0, 0, 0, 289, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #713 = FTINT_L_S
4270 { 712, 2, 1, 4, 0, 0, 0, 273, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #712 = FTINT_L_D
4271 { 711, 2, 1, 4, 0, 0, 0, 275, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #711 = FTINTRZ_W_S
4272 { 710, 2, 1, 4, 0, 0, 0, 291, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #710 = FTINTRZ_W_D
4273 { 709, 2, 1, 4, 0, 0, 0, 289, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #709 = FTINTRZ_L_S
4274 { 708, 2, 1, 4, 0, 0, 0, 273, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #708 = FTINTRZ_L_D
4275 { 707, 2, 1, 4, 0, 0, 0, 275, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #707 = FTINTRP_W_S
4276 { 706, 2, 1, 4, 0, 0, 0, 291, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #706 = FTINTRP_W_D
4277 { 705, 2, 1, 4, 0, 0, 0, 289, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #705 = FTINTRP_L_S
4278 { 704, 2, 1, 4, 0, 0, 0, 273, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #704 = FTINTRP_L_D
4279 { 703, 2, 1, 4, 0, 0, 0, 275, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #703 = FTINTRNE_W_S
4280 { 702, 2, 1, 4, 0, 0, 0, 291, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #702 = FTINTRNE_W_D
4281 { 701, 2, 1, 4, 0, 0, 0, 289, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #701 = FTINTRNE_L_S
4282 { 700, 2, 1, 4, 0, 0, 0, 273, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #700 = FTINTRNE_L_D
4283 { 699, 2, 1, 4, 0, 0, 0, 275, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #699 = FTINTRM_W_S
4284 { 698, 2, 1, 4, 0, 0, 0, 291, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #698 = FTINTRM_W_D
4285 { 697, 2, 1, 4, 0, 0, 0, 289, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #697 = FTINTRM_L_S
4286 { 696, 2, 1, 4, 0, 0, 0, 273, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #696 = FTINTRM_L_D
4287 { 695, 3, 1, 4, 0, 0, 0, 280, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #695 = FSUB_S
4288 { 694, 3, 1, 4, 0, 0, 0, 277, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #694 = FSUB_D
4289 { 693, 3, 0, 4, 0, 0, 0, 299, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #693 = FST_S
4290 { 692, 3, 0, 4, 0, 0, 0, 296, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #692 = FST_D
4291 { 691, 3, 0, 4, 0, 0, 0, 293, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #691 = FSTX_S
4292 { 690, 3, 0, 4, 0, 0, 0, 152, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #690 = FSTX_D
4293 { 689, 3, 0, 4, 0, 0, 0, 293, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #689 = FSTLE_S
4294 { 688, 3, 0, 4, 0, 0, 0, 152, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #688 = FSTLE_D
4295 { 687, 3, 0, 4, 0, 0, 0, 293, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #687 = FSTGT_S
4296 { 686, 3, 0, 4, 0, 0, 0, 152, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #686 = FSTGT_D
4297 { 685, 2, 1, 4, 0, 0, 0, 275, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #685 = FSQRT_S
4298 { 684, 2, 1, 4, 0, 0, 0, 273, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #684 = FSQRT_D
4299 { 683, 4, 1, 4, 0, 0, 0, 314, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #683 = FSEL_xS
4300 { 682, 4, 1, 4, 0, 0, 0, 310, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #682 = FSEL_xD
4301 { 681, 3, 1, 4, 0, 0, 0, 280, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #681 = FSCALEB_S
4302 { 680, 3, 1, 4, 0, 0, 0, 277, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #680 = FSCALEB_D
4303 { 679, 2, 1, 4, 0, 0, 0, 275, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #679 = FRSQRT_S
4304 { 678, 2, 1, 4, 0, 0, 0, 273, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #678 = FRSQRT_D
4305 { 677, 2, 1, 4, 0, 0, 0, 275, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #677 = FRSQRTE_S
4306 { 676, 2, 1, 4, 0, 0, 0, 273, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #676 = FRSQRTE_D
4307 { 675, 2, 1, 4, 0, 0, 0, 275, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #675 = FRINT_S
4308 { 674, 2, 1, 4, 0, 0, 0, 273, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #674 = FRINT_D
4309 { 673, 2, 1, 4, 0, 0, 0, 275, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #673 = FRECIP_S
4310 { 672, 2, 1, 4, 0, 0, 0, 273, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #672 = FRECIP_D
4311 { 671, 2, 1, 4, 0, 0, 0, 275, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #671 = FRECIPE_S
4312 { 670, 2, 1, 4, 0, 0, 0, 273, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #670 = FRECIPE_D
4313 { 669, 4, 1, 4, 0, 0, 0, 306, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #669 = FNMSUB_S
4314 { 668, 4, 1, 4, 0, 0, 0, 302, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #668 = FNMSUB_D
4315 { 667, 4, 1, 4, 0, 0, 0, 306, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #667 = FNMADD_S
4316 { 666, 4, 1, 4, 0, 0, 0, 302, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #666 = FNMADD_D
4317 { 665, 2, 1, 4, 0, 0, 0, 275, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #665 = FNEG_S
4318 { 664, 2, 1, 4, 0, 0, 0, 273, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #664 = FNEG_D
4319 { 663, 3, 1, 4, 0, 0, 0, 280, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #663 = FMUL_S
4320 { 662, 3, 1, 4, 0, 0, 0, 277, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #662 = FMUL_D
4321 { 661, 4, 1, 4, 0, 0, 0, 306, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #661 = FMSUB_S
4322 { 660, 4, 1, 4, 0, 0, 0, 302, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #660 = FMSUB_D
4323 { 659, 2, 1, 4, 0, 0, 0, 275, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #659 = FMOV_S
4324 { 658, 2, 1, 4, 0, 0, 0, 273, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #658 = FMOV_D
4325 { 657, 3, 1, 4, 0, 0, 0, 280, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #657 = FMIN_S
4326 { 656, 3, 1, 4, 0, 0, 0, 277, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #656 = FMIN_D
4327 { 655, 3, 1, 4, 0, 0, 0, 280, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #655 = FMINA_S
4328 { 654, 3, 1, 4, 0, 0, 0, 277, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #654 = FMINA_D
4329 { 653, 3, 1, 4, 0, 0, 0, 280, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #653 = FMAX_S
4330 { 652, 3, 1, 4, 0, 0, 0, 277, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #652 = FMAX_D
4331 { 651, 3, 1, 4, 0, 0, 0, 280, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #651 = FMAXA_S
4332 { 650, 3, 1, 4, 0, 0, 0, 277, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #650 = FMAXA_D
4333 { 649, 4, 1, 4, 0, 0, 0, 306, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #649 = FMADD_S
4334 { 648, 4, 1, 4, 0, 0, 0, 302, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #648 = FMADD_D
4335 { 647, 2, 1, 4, 0, 0, 0, 275, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #647 = FLOGB_S
4336 { 646, 2, 1, 4, 0, 0, 0, 273, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #646 = FLOGB_D
4337 { 645, 3, 1, 4, 0, 0, 0, 299, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #645 = FLD_S
4338 { 644, 3, 1, 4, 0, 0, 0, 296, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #644 = FLD_D
4339 { 643, 3, 1, 4, 0, 0, 0, 293, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #643 = FLDX_S
4340 { 642, 3, 1, 4, 0, 0, 0, 152, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #642 = FLDX_D
4341 { 641, 3, 1, 4, 0, 0, 0, 293, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #641 = FLDLE_S
4342 { 640, 3, 1, 4, 0, 0, 0, 152, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #640 = FLDLE_D
4343 { 639, 3, 1, 4, 0, 0, 0, 293, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #639 = FLDGT_S
4344 { 638, 3, 1, 4, 0, 0, 0, 152, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #638 = FLDGT_D
4345 { 637, 2, 1, 4, 0, 0, 0, 275, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #637 = FFINT_S_W
4346 { 636, 2, 1, 4, 0, 0, 0, 291, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #636 = FFINT_S_L
4347 { 635, 2, 1, 4, 0, 0, 0, 289, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #635 = FFINT_D_W
4348 { 634, 2, 1, 4, 0, 0, 0, 273, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #634 = FFINT_D_L
4349 { 633, 3, 1, 4, 0, 0, 0, 280, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #633 = FDIV_S
4350 { 632, 3, 1, 4, 0, 0, 0, 277, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #632 = FDIV_D
4351 { 631, 2, 1, 4, 0, 0, 0, 275, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #631 = FCVT_UD_D
4352 { 630, 2, 1, 4, 0, 0, 0, 291, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #630 = FCVT_S_D
4353 { 629, 2, 1, 4, 0, 0, 0, 275, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #629 = FCVT_LD_D
4354 { 628, 2, 1, 4, 0, 0, 0, 289, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #628 = FCVT_D_S
4355 { 627, 3, 1, 4, 0, 0, 0, 280, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #627 = FCVT_D_LD
4356 { 626, 3, 1, 4, 0, 0, 0, 280, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #626 = FCOPYSIGN_S
4357 { 625, 3, 1, 4, 0, 0, 0, 277, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #625 = FCOPYSIGN_D
4358 { 624, 3, 1, 4, 0, 0, 0, 286, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #624 = FCMP_SUN_S
4359 { 623, 3, 1, 4, 0, 0, 0, 283, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #623 = FCMP_SUN_D
4360 { 622, 3, 1, 4, 0, 0, 0, 286, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #622 = FCMP_SUNE_S
4361 { 621, 3, 1, 4, 0, 0, 0, 283, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #621 = FCMP_SUNE_D
4362 { 620, 3, 1, 4, 0, 0, 0, 286, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #620 = FCMP_SULT_S
4363 { 619, 3, 1, 4, 0, 0, 0, 283, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #619 = FCMP_SULT_D
4364 { 618, 3, 1, 4, 0, 0, 0, 286, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #618 = FCMP_SULE_S
4365 { 617, 3, 1, 4, 0, 0, 0, 283, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #617 = FCMP_SULE_D
4366 { 616, 3, 1, 4, 0, 0, 0, 286, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #616 = FCMP_SUEQ_S
4367 { 615, 3, 1, 4, 0, 0, 0, 283, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #615 = FCMP_SUEQ_D
4368 { 614, 3, 1, 4, 0, 0, 0, 286, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #614 = FCMP_SOR_S
4369 { 613, 3, 1, 4, 0, 0, 0, 283, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #613 = FCMP_SOR_D
4370 { 612, 3, 1, 4, 0, 0, 0, 286, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #612 = FCMP_SNE_S
4371 { 611, 3, 1, 4, 0, 0, 0, 283, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #611 = FCMP_SNE_D
4372 { 610, 3, 1, 4, 0, 0, 0, 286, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #610 = FCMP_SLT_S
4373 { 609, 3, 1, 4, 0, 0, 0, 283, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #609 = FCMP_SLT_D
4374 { 608, 3, 1, 4, 0, 0, 0, 286, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #608 = FCMP_SLE_S
4375 { 607, 3, 1, 4, 0, 0, 0, 283, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #607 = FCMP_SLE_D
4376 { 606, 3, 1, 4, 0, 0, 0, 286, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #606 = FCMP_SEQ_S
4377 { 605, 3, 1, 4, 0, 0, 0, 283, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #605 = FCMP_SEQ_D
4378 { 604, 3, 1, 4, 0, 0, 0, 286, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #604 = FCMP_SAF_S
4379 { 603, 3, 1, 4, 0, 0, 0, 283, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #603 = FCMP_SAF_D
4380 { 602, 3, 1, 4, 0, 0, 0, 286, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #602 = FCMP_CUN_S
4381 { 601, 3, 1, 4, 0, 0, 0, 283, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #601 = FCMP_CUN_D
4382 { 600, 3, 1, 4, 0, 0, 0, 286, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #600 = FCMP_CUNE_S
4383 { 599, 3, 1, 4, 0, 0, 0, 283, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #599 = FCMP_CUNE_D
4384 { 598, 3, 1, 4, 0, 0, 0, 286, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #598 = FCMP_CULT_S
4385 { 597, 3, 1, 4, 0, 0, 0, 283, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #597 = FCMP_CULT_D
4386 { 596, 3, 1, 4, 0, 0, 0, 286, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #596 = FCMP_CULE_S
4387 { 595, 3, 1, 4, 0, 0, 0, 283, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #595 = FCMP_CULE_D
4388 { 594, 3, 1, 4, 0, 0, 0, 286, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #594 = FCMP_CUEQ_S
4389 { 593, 3, 1, 4, 0, 0, 0, 283, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #593 = FCMP_CUEQ_D
4390 { 592, 3, 1, 4, 0, 0, 0, 286, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #592 = FCMP_COR_S
4391 { 591, 3, 1, 4, 0, 0, 0, 283, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #591 = FCMP_COR_D
4392 { 590, 3, 1, 4, 0, 0, 0, 286, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #590 = FCMP_CNE_S
4393 { 589, 3, 1, 4, 0, 0, 0, 283, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #589 = FCMP_CNE_D
4394 { 588, 3, 1, 4, 0, 0, 0, 286, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #588 = FCMP_CLT_S
4395 { 587, 3, 1, 4, 0, 0, 0, 283, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #587 = FCMP_CLT_D
4396 { 586, 3, 1, 4, 0, 0, 0, 286, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #586 = FCMP_CLE_S
4397 { 585, 3, 1, 4, 0, 0, 0, 283, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #585 = FCMP_CLE_D
4398 { 584, 3, 1, 4, 0, 0, 0, 286, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #584 = FCMP_CEQ_S
4399 { 583, 3, 1, 4, 0, 0, 0, 283, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #583 = FCMP_CEQ_D
4400 { 582, 3, 1, 4, 0, 0, 0, 286, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #582 = FCMP_CAF_S
4401 { 581, 3, 1, 4, 0, 0, 0, 283, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #581 = FCMP_CAF_D
4402 { 580, 2, 1, 4, 0, 0, 0, 275, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #580 = FCLASS_S
4403 { 579, 2, 1, 4, 0, 0, 0, 273, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #579 = FCLASS_D
4404 { 578, 3, 1, 4, 0, 0, 0, 280, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #578 = FADD_S
4405 { 577, 3, 1, 4, 0, 0, 0, 277, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #577 = FADD_D
4406 { 576, 2, 1, 4, 0, 0, 0, 275, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #576 = FABS_S
4407 { 575, 2, 1, 4, 0, 0, 0, 273, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #575 = FABS_D
4408 { 574, 2, 1, 4, 0, 0, 0, 170, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #574 = EXT_W_H
4409 { 573, 2, 1, 4, 0, 0, 0, 170, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #573 = EXT_W_B
4410 { 572, 0, 0, 4, 0, 0, 0, 1, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #572 = ERTN
4411 { 571, 3, 1, 4, 0, 0, 0, 164, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #571 = DIV_WU
4412 { 570, 3, 1, 4, 0, 0, 0, 164, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #570 = DIV_W
4413 { 569, 3, 1, 4, 0, 0, 0, 164, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #569 = DIV_DU
4414 { 568, 3, 1, 4, 0, 0, 0, 164, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #568 = DIV_D
4415 { 567, 1, 0, 4, 0, 0, 0, 0, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #567 = DBCL
4416 { 566, 1, 0, 4, 0, 0, 0, 0, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #566 = DBAR
4417 { 565, 2, 1, 4, 0, 0, 0, 170, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #565 = CTZ_W
4418 { 564, 2, 1, 4, 0, 0, 0, 170, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #564 = CTZ_D
4419 { 563, 2, 1, 4, 0, 0, 0, 170, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #563 = CTO_W
4420 { 562, 2, 1, 4, 0, 0, 0, 170, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #562 = CTO_D
4421 { 561, 4, 1, 4, 0, 0, 0, 269, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #561 = CSRXCHG
4422 { 560, 3, 1, 4, 0, 0, 0, 266, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #560 = CSRWR
4423 { 559, 2, 1, 4, 0, 0, 0, 191, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #559 = CSRRD
4424 { 558, 3, 1, 4, 0, 0, 0, 164, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #558 = CRC_W_W_W
4425 { 557, 3, 1, 4, 0, 0, 0, 164, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #557 = CRC_W_H_W
4426 { 556, 3, 1, 4, 0, 0, 0, 164, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #556 = CRC_W_D_W
4427 { 555, 3, 1, 4, 0, 0, 0, 164, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #555 = CRC_W_B_W
4428 { 554, 3, 1, 4, 0, 0, 0, 164, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #554 = CRCC_W_W_W
4429 { 553, 3, 1, 4, 0, 0, 0, 164, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #553 = CRCC_W_H_W
4430 { 552, 3, 1, 4, 0, 0, 0, 164, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #552 = CRCC_W_D_W
4431 { 551, 3, 1, 4, 0, 0, 0, 164, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #551 = CRCC_W_B_W
4432 { 550, 2, 1, 4, 0, 0, 0, 170, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #550 = CPUCFG
4433 { 549, 2, 1, 4, 0, 0, 0, 170, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #549 = CLZ_W
4434 { 548, 2, 1, 4, 0, 0, 0, 170, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #548 = CLZ_D
4435 { 547, 2, 1, 4, 0, 0, 0, 170, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #547 = CLO_W
4436 { 546, 2, 1, 4, 0, 0, 0, 170, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #546 = CLO_D
4437 { 545, 3, 0, 4, 0, 0, 0, 263, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #545 = CACOP
4438 { 544, 4, 1, 4, 0, 0, 0, 155, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #544 = BYTEPICK_W
4439 { 543, 4, 1, 4, 0, 0, 0, 155, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #543 = BYTEPICK_D
4440 { 542, 4, 1, 4, 0, 0, 0, 259, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #542 = BSTRPICK_W
4441 { 541, 4, 1, 4, 0, 0, 0, 259, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #541 = BSTRPICK_D
4442 { 540, 5, 1, 4, 0, 0, 0, 254, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #540 = BSTRINS_W
4443 { 539, 5, 1, 4, 0, 0, 0, 254, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #539 = BSTRINS_D
4444 { 538, 1, 0, 4, 0, 0, 0, 0, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #538 = BREAK
4445 { 537, 2, 0, 4, 0, 0, 0, 191, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #537 = BNEZ
4446 { 536, 3, 0, 4, 0, 0, 0, 188, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #536 = BNE
4447 { 535, 3, 0, 4, 0, 0, 0, 188, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #535 = BLTU
4448 { 534, 3, 0, 4, 0, 0, 0, 188, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #534 = BLT
4449 { 533, 1, 0, 4, 0, 0, 1, 0, LoongArchImpOpBase + 3, 0|(1ULL<<MCID::Call), 0x0ULL }, // Inst #533 = BL
4450 { 532, 2, 1, 4, 0, 0, 0, 170, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #532 = BITREV_W
4451 { 531, 2, 1, 4, 0, 0, 0, 170, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #531 = BITREV_D
4452 { 530, 2, 1, 4, 0, 0, 0, 170, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #530 = BITREV_8B
4453 { 529, 2, 1, 4, 0, 0, 0, 170, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #529 = BITREV_4B
4454 { 528, 3, 0, 4, 0, 0, 0, 188, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #528 = BGEU
4455 { 527, 3, 0, 4, 0, 0, 0, 188, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #527 = BGE
4456 { 526, 2, 0, 4, 0, 0, 0, 191, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #526 = BEQZ
4457 { 525, 3, 0, 4, 0, 0, 0, 188, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #525 = BEQ
4458 { 524, 2, 0, 4, 0, 0, 0, 252, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #524 = BCNEZ
4459 { 523, 2, 0, 4, 0, 0, 0, 252, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #523 = BCEQZ
4460 { 522, 1, 0, 4, 0, 0, 0, 0, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #522 = B
4461 { 521, 2, 0, 4, 0, 0, 0, 170, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #521 = ASRTLE_D
4462 { 520, 2, 0, 4, 0, 0, 0, 170, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #520 = ASRTGT_D
4463 { 519, 3, 0, 4, 0, 0, 0, 188, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #519 = ARMXOR_W
4464 { 518, 3, 0, 4, 0, 0, 0, 188, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #518 = ARMSUB_W
4465 { 517, 3, 0, 4, 0, 0, 0, 188, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #517 = ARMSRL_W
4466 { 516, 3, 0, 4, 0, 0, 0, 249, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #516 = ARMSRLI_W
4467 { 515, 3, 0, 4, 0, 0, 0, 188, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #515 = ARMSRA_W
4468 { 514, 3, 0, 4, 0, 0, 0, 249, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #514 = ARMSRAI_W
4469 { 513, 3, 0, 4, 0, 0, 0, 188, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #513 = ARMSLL_W
4470 { 512, 3, 0, 4, 0, 0, 0, 249, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #512 = ARMSLLI_W
4471 { 511, 3, 0, 4, 0, 0, 0, 188, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #511 = ARMSBC_W
4472 { 510, 2, 0, 4, 0, 0, 0, 191, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #510 = ARMRRX_W
4473 { 509, 3, 0, 4, 0, 0, 0, 188, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #509 = ARMROTR_W
4474 { 508, 3, 0, 4, 0, 0, 0, 249, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #508 = ARMROTRI_W
4475 { 507, 3, 0, 4, 0, 0, 0, 188, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #507 = ARMOR_W
4476 { 506, 2, 0, 4, 0, 0, 0, 191, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #506 = ARMNOT_W
4477 { 505, 2, 1, 4, 0, 0, 0, 191, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #505 = ARMMTFLAG
4478 { 504, 2, 0, 4, 0, 0, 0, 191, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #504 = ARMMOV_W
4479 { 503, 2, 0, 4, 0, 0, 0, 191, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #503 = ARMMOV_D
4480 { 502, 3, 1, 4, 0, 0, 0, 188, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #502 = ARMMOVE
4481 { 501, 2, 1, 4, 0, 0, 0, 191, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #501 = ARMMFFLAG
4482 { 500, 3, 0, 4, 0, 0, 0, 188, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #500 = ARMAND_W
4483 { 499, 3, 0, 4, 0, 0, 0, 188, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #499 = ARMADD_W
4484 { 498, 3, 0, 4, 0, 0, 0, 188, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #498 = ARMADC_W
4485 { 497, 3, 1, 4, 0, 0, 0, 164, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #497 = ANDN
4486 { 496, 3, 1, 4, 0, 0, 0, 188, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #496 = ANDI
4487 { 495, 3, 1, 4, 0, 0, 0, 164, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #495 = AND
4488 { 494, 3, 1, 4, 0, 0, 0, 242, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL }, // Inst #494 = AMXOR__DB_W
4489 { 493, 3, 1, 4, 0, 0, 0, 242, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL }, // Inst #493 = AMXOR__DB_D
4490 { 492, 3, 1, 4, 0, 0, 0, 242, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL }, // Inst #492 = AMXOR_W
4491 { 491, 3, 1, 4, 0, 0, 0, 242, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL }, // Inst #491 = AMXOR_D
4492 { 490, 3, 1, 4, 0, 0, 0, 242, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL }, // Inst #490 = AMSWAP__DB_W
4493 { 489, 3, 1, 4, 0, 0, 0, 242, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL }, // Inst #489 = AMSWAP__DB_H
4494 { 488, 3, 1, 4, 0, 0, 0, 242, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL }, // Inst #488 = AMSWAP__DB_D
4495 { 487, 3, 1, 4, 0, 0, 0, 242, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL }, // Inst #487 = AMSWAP__DB_B
4496 { 486, 3, 1, 4, 0, 0, 0, 242, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL }, // Inst #486 = AMSWAP_W
4497 { 485, 3, 1, 4, 0, 0, 0, 242, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL }, // Inst #485 = AMSWAP_H
4498 { 484, 3, 1, 4, 0, 0, 0, 242, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL }, // Inst #484 = AMSWAP_D
4499 { 483, 3, 1, 4, 0, 0, 0, 242, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL }, // Inst #483 = AMSWAP_B
4500 { 482, 3, 1, 4, 0, 0, 0, 242, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL }, // Inst #482 = AMOR__DB_W
4501 { 481, 3, 1, 4, 0, 0, 0, 242, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL }, // Inst #481 = AMOR__DB_D
4502 { 480, 3, 1, 4, 0, 0, 0, 242, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL }, // Inst #480 = AMOR_W
4503 { 479, 3, 1, 4, 0, 0, 0, 242, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL }, // Inst #479 = AMOR_D
4504 { 478, 3, 1, 4, 0, 0, 0, 242, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL }, // Inst #478 = AMMIN__DB_WU
4505 { 477, 3, 1, 4, 0, 0, 0, 242, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL }, // Inst #477 = AMMIN__DB_W
4506 { 476, 3, 1, 4, 0, 0, 0, 242, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL }, // Inst #476 = AMMIN__DB_DU
4507 { 475, 3, 1, 4, 0, 0, 0, 242, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL }, // Inst #475 = AMMIN__DB_D
4508 { 474, 3, 1, 4, 0, 0, 0, 242, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL }, // Inst #474 = AMMIN_WU
4509 { 473, 3, 1, 4, 0, 0, 0, 242, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL }, // Inst #473 = AMMIN_W
4510 { 472, 3, 1, 4, 0, 0, 0, 242, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL }, // Inst #472 = AMMIN_DU
4511 { 471, 3, 1, 4, 0, 0, 0, 242, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL }, // Inst #471 = AMMIN_D
4512 { 470, 3, 1, 4, 0, 0, 0, 242, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL }, // Inst #470 = AMMAX__DB_WU
4513 { 469, 3, 1, 4, 0, 0, 0, 242, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL }, // Inst #469 = AMMAX__DB_W
4514 { 468, 3, 1, 4, 0, 0, 0, 242, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL }, // Inst #468 = AMMAX__DB_DU
4515 { 467, 3, 1, 4, 0, 0, 0, 242, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL }, // Inst #467 = AMMAX__DB_D
4516 { 466, 3, 1, 4, 0, 0, 0, 242, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL }, // Inst #466 = AMMAX_WU
4517 { 465, 3, 1, 4, 0, 0, 0, 242, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL }, // Inst #465 = AMMAX_W
4518 { 464, 3, 1, 4, 0, 0, 0, 242, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL }, // Inst #464 = AMMAX_DU
4519 { 463, 3, 1, 4, 0, 0, 0, 242, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL }, // Inst #463 = AMMAX_D
4520 { 462, 4, 1, 4, 0, 0, 0, 245, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x3ULL }, // Inst #462 = AMCAS__DB_W
4521 { 461, 4, 1, 4, 0, 0, 0, 245, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x3ULL }, // Inst #461 = AMCAS__DB_H
4522 { 460, 4, 1, 4, 0, 0, 0, 245, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x3ULL }, // Inst #460 = AMCAS__DB_D
4523 { 459, 4, 1, 4, 0, 0, 0, 245, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x3ULL }, // Inst #459 = AMCAS__DB_B
4524 { 458, 4, 1, 4, 0, 0, 0, 245, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x3ULL }, // Inst #458 = AMCAS_W
4525 { 457, 4, 1, 4, 0, 0, 0, 245, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x3ULL }, // Inst #457 = AMCAS_H
4526 { 456, 4, 1, 4, 0, 0, 0, 245, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x3ULL }, // Inst #456 = AMCAS_D
4527 { 455, 4, 1, 4, 0, 0, 0, 245, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x3ULL }, // Inst #455 = AMCAS_B
4528 { 454, 3, 1, 4, 0, 0, 0, 242, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL }, // Inst #454 = AMAND__DB_W
4529 { 453, 3, 1, 4, 0, 0, 0, 242, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL }, // Inst #453 = AMAND__DB_D
4530 { 452, 3, 1, 4, 0, 0, 0, 242, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL }, // Inst #452 = AMAND_W
4531 { 451, 3, 1, 4, 0, 0, 0, 242, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL }, // Inst #451 = AMAND_D
4532 { 450, 3, 1, 4, 0, 0, 0, 242, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL }, // Inst #450 = AMADD__DB_W
4533 { 449, 3, 1, 4, 0, 0, 0, 242, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL }, // Inst #449 = AMADD__DB_H
4534 { 448, 3, 1, 4, 0, 0, 0, 242, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL }, // Inst #448 = AMADD__DB_D
4535 { 447, 3, 1, 4, 0, 0, 0, 242, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL }, // Inst #447 = AMADD__DB_B
4536 { 446, 3, 1, 4, 0, 0, 0, 242, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL }, // Inst #446 = AMADD_W
4537 { 445, 3, 1, 4, 0, 0, 0, 242, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL }, // Inst #445 = AMADD_H
4538 { 444, 3, 1, 4, 0, 0, 0, 242, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL }, // Inst #444 = AMADD_D
4539 { 443, 3, 1, 4, 0, 0, 0, 242, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL }, // Inst #443 = AMADD_B
4540 { 442, 4, 1, 4, 0, 0, 0, 155, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #442 = ALSL_WU
4541 { 441, 4, 1, 4, 0, 0, 0, 155, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #441 = ALSL_W
4542 { 440, 4, 1, 4, 0, 0, 0, 155, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #440 = ALSL_D
4543 { 439, 3, 1, 4, 0, 0, 0, 164, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #439 = ADD_W
4544 { 438, 3, 1, 4, 0, 0, 0, 164, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #438 = ADD_D
4545 { 437, 3, 1, 4, 0, 0, 0, 188, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #437 = ADDU16I_D
4546 { 436, 3, 1, 4, 0, 0, 0, 188, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #436 = ADDU12I_W
4547 { 435, 3, 1, 4, 0, 0, 0, 188, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #435 = ADDU12I_D
4548 { 434, 3, 1, 4, 0, 0, 0, 188, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #434 = ADDI_W
4549 { 433, 3, 1, 4, 0, 0, 0, 188, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #433 = ADDI_D
4550 { 432, 3, 1, 4, 0, 0, 0, 164, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #432 = ADC_W
4551 { 431, 3, 1, 4, 0, 0, 0, 164, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #431 = ADC_H
4552 { 430, 3, 1, 4, 0, 0, 0, 164, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #430 = ADC_D
4553 { 429, 3, 1, 4, 0, 0, 0, 164, LoongArchImpOpBase + 0, 0, 0x0ULL }, // Inst #429 = ADC_B
4554 { 428, 2, 0, 4, 0, 0, 0, 240, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #428 = WRFCSR
4555 { 427, 3, 2, 4, 0, 0, 0, 237, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #427 = SplitPairF64Pseudo
4556 { 426, 6, 1, 4, 0, 0, 0, 231, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #426 = Select_GPR_Using_CC_GPR
4557 { 425, 2, 1, 4, 0, 0, 0, 191, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #425 = RDFCSR
4558 { 424, 2, 1, 4, 0, 0, 0, 229, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #424 = PseudoXVREPLI_W
4559 { 423, 2, 1, 4, 0, 0, 0, 229, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #423 = PseudoXVREPLI_H
4560 { 422, 2, 1, 4, 0, 0, 0, 229, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #422 = PseudoXVREPLI_D
4561 { 421, 2, 1, 4, 0, 0, 0, 229, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #421 = PseudoXVREPLI_B
4562 { 420, 2, 1, 4, 0, 0, 0, 223, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #420 = PseudoXVMSKNEZ_B
4563 { 419, 2, 1, 4, 0, 0, 0, 223, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #419 = PseudoXVMSKLTZ_W
4564 { 418, 2, 1, 4, 0, 0, 0, 223, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #418 = PseudoXVMSKLTZ_H
4565 { 417, 2, 1, 4, 0, 0, 0, 223, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #417 = PseudoXVMSKLTZ_D
4566 { 416, 2, 1, 4, 0, 0, 0, 223, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #416 = PseudoXVMSKLTZ_B
4567 { 415, 2, 1, 4, 0, 0, 0, 223, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #415 = PseudoXVMSKGEZ_B
4568 { 414, 2, 1, 4, 0, 0, 0, 223, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #414 = PseudoXVMSKEQZ_B
4569 { 413, 4, 1, 4, 0, 0, 0, 225, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #413 = PseudoXVINSGR2VR_H
4570 { 412, 4, 1, 4, 0, 0, 0, 225, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #412 = PseudoXVINSGR2VR_B
4571 { 411, 2, 1, 4, 0, 0, 0, 223, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #411 = PseudoXVBZ_W
4572 { 410, 2, 1, 4, 0, 0, 0, 223, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #410 = PseudoXVBZ_H
4573 { 409, 2, 1, 4, 0, 0, 0, 223, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #409 = PseudoXVBZ_D
4574 { 408, 2, 1, 4, 0, 0, 0, 223, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #408 = PseudoXVBZ_B
4575 { 407, 2, 1, 4, 0, 0, 0, 223, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #407 = PseudoXVBZ
4576 { 406, 2, 1, 4, 0, 0, 0, 223, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #406 = PseudoXVBNZ_W
4577 { 405, 2, 1, 4, 0, 0, 0, 223, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #405 = PseudoXVBNZ_H
4578 { 404, 2, 1, 4, 0, 0, 0, 223, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #404 = PseudoXVBNZ_D
4579 { 403, 2, 1, 4, 0, 0, 0, 223, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #403 = PseudoXVBNZ_B
4580 { 402, 2, 1, 4, 0, 0, 0, 223, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #402 = PseudoXVBNZ
4581 { 401, 2, 1, 4, 0, 0, 0, 221, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #401 = PseudoVREPLI_W
4582 { 400, 2, 1, 4, 0, 0, 0, 221, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #400 = PseudoVREPLI_H
4583 { 399, 2, 1, 4, 0, 0, 0, 221, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #399 = PseudoVREPLI_D
4584 { 398, 2, 1, 4, 0, 0, 0, 221, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #398 = PseudoVREPLI_B
4585 { 397, 2, 1, 4, 0, 0, 0, 219, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #397 = PseudoVMSKNEZ_B
4586 { 396, 2, 1, 4, 0, 0, 0, 219, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #396 = PseudoVMSKLTZ_W
4587 { 395, 2, 1, 4, 0, 0, 0, 219, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #395 = PseudoVMSKLTZ_H
4588 { 394, 2, 1, 4, 0, 0, 0, 219, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #394 = PseudoVMSKLTZ_D
4589 { 393, 2, 1, 4, 0, 0, 0, 219, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #393 = PseudoVMSKLTZ_B
4590 { 392, 2, 1, 4, 0, 0, 0, 219, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #392 = PseudoVMSKGEZ_B
4591 { 391, 2, 1, 4, 0, 0, 0, 219, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #391 = PseudoVMSKEQZ_B
4592 { 390, 2, 1, 4, 0, 0, 0, 219, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #390 = PseudoVBZ_W
4593 { 389, 2, 1, 4, 0, 0, 0, 219, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #389 = PseudoVBZ_H
4594 { 388, 2, 1, 4, 0, 0, 0, 219, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #388 = PseudoVBZ_D
4595 { 387, 2, 1, 4, 0, 0, 0, 219, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #387 = PseudoVBZ_B
4596 { 386, 2, 1, 4, 0, 0, 0, 219, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #386 = PseudoVBZ
4597 { 385, 2, 1, 4, 0, 0, 0, 219, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #385 = PseudoVBNZ_W
4598 { 384, 2, 1, 4, 0, 0, 0, 219, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #384 = PseudoVBNZ_H
4599 { 383, 2, 1, 4, 0, 0, 0, 219, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #383 = PseudoVBNZ_D
4600 { 382, 2, 1, 4, 0, 0, 0, 219, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #382 = PseudoVBNZ_B
4601 { 381, 2, 1, 4, 0, 0, 0, 219, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #381 = PseudoVBNZ
4602 { 380, 0, 0, 4, 0, 0, 0, 1, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #380 = PseudoUNIMP
4603 { 379, 1, 0, 8, 0, 1, 1, 0, LoongArchImpOpBase + 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #379 = PseudoTAIL_MEDIUM
4604 { 378, 1, 0, 4, 0, 1, 0, 0, LoongArchImpOpBase + 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #378 = PseudoTAIL_LARGE
4605 { 377, 1, 0, 4, 0, 1, 0, 218, LoongArchImpOpBase + 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #377 = PseudoTAILIndirect
4606 { 376, 2, 0, 4, 0, 1, 0, 191, LoongArchImpOpBase + 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #376 = PseudoTAIL36
4607 { 375, 1, 0, 4, 0, 1, 0, 0, LoongArchImpOpBase + 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #375 = PseudoTAIL
4608 { 374, 3, 0, 4, 0, 0, 0, 193, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #374 = PseudoST_CFR
4609 { 373, 0, 0, 4, 0, 0, 0, 1, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #373 = PseudoRET
4610 { 372, 7, 2, 44, 0, 0, 0, 211, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #372 = PseudoMaskedCmpXchg32
4611 { 371, 6, 2, 36, 0, 0, 0, 180, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #371 = PseudoMaskedAtomicSwap32
4612 { 370, 7, 3, 48, 0, 0, 0, 204, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #370 = PseudoMaskedAtomicLoadUMin32
4613 { 369, 7, 3, 48, 0, 0, 0, 204, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #369 = PseudoMaskedAtomicLoadUMax32
4614 { 368, 6, 2, 36, 0, 0, 0, 180, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #368 = PseudoMaskedAtomicLoadSub32
4615 { 367, 6, 2, 36, 0, 0, 0, 180, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #367 = PseudoMaskedAtomicLoadNand32
4616 { 366, 8, 3, 56, 0, 0, 0, 196, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #366 = PseudoMaskedAtomicLoadMin32
4617 { 365, 8, 3, 56, 0, 0, 0, 196, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #365 = PseudoMaskedAtomicLoadMax32
4618 { 364, 6, 2, 36, 0, 0, 0, 180, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #364 = PseudoMaskedAtomicLoadAdd32
4619 { 363, 2, 1, 4, 0, 0, 0, 191, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #363 = PseudoLI_W
4620 { 362, 2, 1, 4, 0, 0, 0, 191, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #362 = PseudoLI_D
4621 { 361, 3, 1, 4, 0, 0, 0, 193, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #361 = PseudoLD_CFR
4622 { 360, 2, 1, 4, 0, 0, 0, 191, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #360 = PseudoLA_TLS_LE
4623 { 359, 3, 1, 4, 0, 0, 0, 188, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #359 = PseudoLA_TLS_LD_LARGE
4624 { 358, 2, 1, 4, 0, 0, 0, 191, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #358 = PseudoLA_TLS_LD
4625 { 357, 3, 1, 4, 0, 0, 0, 188, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #357 = PseudoLA_TLS_IE_LARGE
4626 { 356, 2, 1, 4, 0, 0, 0, 191, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #356 = PseudoLA_TLS_IE
4627 { 355, 3, 1, 4, 0, 0, 0, 188, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #355 = PseudoLA_TLS_GD_LARGE
4628 { 354, 2, 1, 4, 0, 0, 0, 191, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #354 = PseudoLA_TLS_GD
4629 { 353, 3, 1, 4, 0, 0, 2, 188, LoongArchImpOpBase + 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call), 0x0ULL }, // Inst #353 = PseudoLA_TLS_DESC_LARGE
4630 { 352, 2, 1, 4, 0, 0, 1, 191, LoongArchImpOpBase + 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #352 = PseudoLA_TLS_DESC
4631 { 351, 3, 1, 4, 0, 0, 0, 188, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #351 = PseudoLA_PCREL_LARGE
4632 { 350, 2, 1, 4, 0, 0, 0, 191, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #350 = PseudoLA_PCREL
4633 { 349, 3, 1, 4, 0, 0, 0, 188, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #349 = PseudoLA_GOT_LARGE
4634 { 348, 2, 1, 4, 0, 0, 0, 191, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #348 = PseudoLA_GOT
4635 { 347, 3, 1, 4, 0, 0, 0, 188, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #347 = PseudoLA_ABS_LARGE
4636 { 346, 2, 1, 4, 0, 0, 0, 191, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #346 = PseudoLA_ABS
4637 { 345, 2, 0, 4, 0, 1, 0, 191, LoongArchImpOpBase + 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #345 = PseudoJIRL_TAIL
4638 { 344, 2, 0, 4, 0, 0, 1, 191, LoongArchImpOpBase + 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call), 0x0ULL }, // Inst #344 = PseudoJIRL_CALL
4639 { 343, 3, 1, 4, 0, 1, 1, 188, LoongArchImpOpBase + 6, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call), 0x0ULL }, // Inst #343 = PseudoDESC_CALL
4640 { 342, 2, 1, 12, 0, 0, 0, 186, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #342 = PseudoCopyCFR
4641 { 341, 6, 2, 36, 0, 0, 0, 180, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #341 = PseudoCmpXchg64
4642 { 340, 6, 2, 36, 0, 0, 0, 180, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #340 = PseudoCmpXchg32
4643 { 339, 8, 3, 36, 0, 0, 0, 172, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #339 = PseudoCmpXchg128Acquire
4644 { 338, 8, 3, 36, 0, 0, 0, 172, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #338 = PseudoCmpXchg128
4645 { 337, 2, 1, 4, 0, 0, 0, 170, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #337 = PseudoCTPOP
4646 { 336, 1, 0, 8, 0, 0, 2, 0, LoongArchImpOpBase + 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call), 0x0ULL }, // Inst #336 = PseudoCALL_MEDIUM
4647 { 335, 1, 0, 4, 0, 0, 1, 0, LoongArchImpOpBase + 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call), 0x0ULL }, // Inst #335 = PseudoCALL_LARGE
4648 { 334, 1, 0, 4, 0, 0, 1, 169, LoongArchImpOpBase + 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call), 0x0ULL }, // Inst #334 = PseudoCALLIndirect
4649 { 333, 1, 0, 4, 0, 0, 1, 0, LoongArchImpOpBase + 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call), 0x0ULL }, // Inst #333 = PseudoCALL36
4650 { 332, 1, 0, 4, 0, 0, 1, 0, LoongArchImpOpBase + 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call), 0x0ULL }, // Inst #332 = PseudoCALL
4651 { 331, 1, 0, 4, 0, 1, 0, 0, LoongArchImpOpBase + 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #331 = PseudoB_TAIL
4652 { 330, 2, 0, 4, 0, 0, 0, 167, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #330 = PseudoBRIND
4653 { 329, 1, 0, 4, 0, 0, 0, 0, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #329 = PseudoBR
4654 { 328, 5, 2, 24, 0, 0, 0, 159, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #328 = PseudoAtomicSwap32
4655 { 327, 3, 1, 4, 0, 0, 0, 164, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #327 = PseudoAtomicStoreW
4656 { 326, 3, 1, 4, 0, 0, 0, 164, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #326 = PseudoAtomicStoreD
4657 { 325, 5, 2, 24, 0, 0, 0, 159, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #325 = PseudoAtomicLoadXor32
4658 { 324, 5, 2, 24, 0, 0, 0, 159, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #324 = PseudoAtomicLoadUMin32
4659 { 323, 5, 2, 24, 0, 0, 0, 159, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #323 = PseudoAtomicLoadUMax32
4660 { 322, 5, 2, 24, 0, 0, 0, 159, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #322 = PseudoAtomicLoadSub32
4661 { 321, 5, 2, 24, 0, 0, 0, 159, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #321 = PseudoAtomicLoadOr32
4662 { 320, 5, 2, 24, 0, 0, 0, 159, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #320 = PseudoAtomicLoadNand64
4663 { 319, 5, 2, 24, 0, 0, 0, 159, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #319 = PseudoAtomicLoadNand32
4664 { 318, 5, 2, 24, 0, 0, 0, 159, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #318 = PseudoAtomicLoadMin32
4665 { 317, 5, 2, 24, 0, 0, 0, 159, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #317 = PseudoAtomicLoadMax32
4666 { 316, 5, 2, 24, 0, 0, 0, 159, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #316 = PseudoAtomicLoadAnd32
4667 { 315, 5, 2, 24, 0, 0, 0, 159, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #315 = PseudoAtomicLoadAdd32
4668 { 314, 4, 1, 4, 0, 0, 0, 155, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #314 = PseudoAddTPRel_W
4669 { 313, 4, 1, 4, 0, 0, 0, 155, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #313 = PseudoAddTPRel_D
4670 { 312, 3, 1, 4, 0, 0, 0, 152, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #312 = BuildPairF64Pseudo
4671 { 311, 2, 0, 4, 0, 1, 1, 21, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #311 = ADJCALLSTACKUP
4672 { 310, 2, 0, 4, 0, 1, 1, 21, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #310 = ADJCALLSTACKDOWN
4673 { 309, 4, 1, 0, 0, 0, 0, 148, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #309 = G_UBFX
4674 { 308, 4, 1, 0, 0, 0, 0, 148, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #308 = G_SBFX
4675 { 307, 2, 1, 0, 0, 0, 0, 61, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #307 = G_VECREDUCE_UMIN
4676 { 306, 2, 1, 0, 0, 0, 0, 61, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #306 = G_VECREDUCE_UMAX
4677 { 305, 2, 1, 0, 0, 0, 0, 61, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #305 = G_VECREDUCE_SMIN
4678 { 304, 2, 1, 0, 0, 0, 0, 61, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #304 = G_VECREDUCE_SMAX
4679 { 303, 2, 1, 0, 0, 0, 0, 61, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #303 = G_VECREDUCE_XOR
4680 { 302, 2, 1, 0, 0, 0, 0, 61, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #302 = G_VECREDUCE_OR
4681 { 301, 2, 1, 0, 0, 0, 0, 61, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #301 = G_VECREDUCE_AND
4682 { 300, 2, 1, 0, 0, 0, 0, 61, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #300 = G_VECREDUCE_MUL
4683 { 299, 2, 1, 0, 0, 0, 0, 61, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #299 = G_VECREDUCE_ADD
4684 { 298, 2, 1, 0, 0, 0, 0, 61, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #298 = G_VECREDUCE_FMINIMUM
4685 { 297, 2, 1, 0, 0, 0, 0, 61, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #297 = G_VECREDUCE_FMAXIMUM
4686 { 296, 2, 1, 0, 0, 0, 0, 61, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #296 = G_VECREDUCE_FMIN
4687 { 295, 2, 1, 0, 0, 0, 0, 61, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #295 = G_VECREDUCE_FMAX
4688 { 294, 2, 1, 0, 0, 0, 0, 61, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #294 = G_VECREDUCE_FMUL
4689 { 293, 2, 1, 0, 0, 0, 0, 61, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #293 = G_VECREDUCE_FADD
4690 { 292, 3, 1, 0, 0, 0, 0, 131, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #292 = G_VECREDUCE_SEQ_FMUL
4691 { 291, 3, 1, 0, 0, 0, 0, 131, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #291 = G_VECREDUCE_SEQ_FADD
4692 { 290, 1, 0, 0, 0, 0, 0, 1, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #290 = G_UBSANTRAP
4693 { 289, 0, 0, 0, 0, 0, 0, 1, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #289 = G_DEBUGTRAP
4694 { 288, 0, 0, 0, 0, 0, 0, 1, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #288 = G_TRAP
4695 { 287, 3, 0, 0, 0, 0, 0, 58, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #287 = G_BZERO
4696 { 286, 4, 0, 0, 0, 0, 0, 144, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #286 = G_MEMSET
4697 { 285, 4, 0, 0, 0, 0, 0, 144, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #285 = G_MEMMOVE
4698 { 284, 3, 0, 0, 0, 0, 0, 131, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #284 = G_MEMCPY_INLINE
4699 { 283, 4, 0, 0, 0, 0, 0, 144, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #283 = G_MEMCPY
4700 { 282, 2, 0, 0, 0, 0, 0, 142, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #282 = G_WRITE_REGISTER
4701 { 281, 2, 1, 0, 0, 0, 0, 51, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #281 = G_READ_REGISTER
4702 { 280, 3, 1, 0, 0, 0, 0, 101, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #280 = G_STRICT_FLDEXP
4703 { 279, 2, 1, 0, 0, 0, 0, 67, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #279 = G_STRICT_FSQRT
4704 { 278, 4, 1, 0, 0, 0, 0, 46, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #278 = G_STRICT_FMA
4705 { 277, 3, 1, 0, 0, 0, 0, 43, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #277 = G_STRICT_FREM
4706 { 276, 3, 1, 0, 0, 0, 0, 43, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #276 = G_STRICT_FDIV
4707 { 275, 3, 1, 0, 0, 0, 0, 43, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #275 = G_STRICT_FMUL
4708 { 274, 3, 1, 0, 0, 0, 0, 43, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #274 = G_STRICT_FSUB
4709 { 273, 3, 1, 0, 0, 0, 0, 43, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #273 = G_STRICT_FADD
4710 { 272, 1, 0, 0, 0, 0, 0, 50, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #272 = G_STACKRESTORE
4711 { 271, 1, 1, 0, 0, 0, 0, 50, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #271 = G_STACKSAVE
4712 { 270, 3, 1, 0, 0, 0, 0, 69, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #270 = G_DYN_STACKALLOC
4713 { 269, 2, 1, 0, 0, 0, 0, 51, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #269 = G_JUMP_TABLE
4714 { 268, 2, 1, 0, 0, 0, 0, 51, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #268 = G_BLOCK_ADDR
4715 { 267, 2, 1, 0, 0, 0, 0, 61, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #267 = G_ADDRSPACE_CAST
4716 { 266, 2, 1, 0, 0, 0, 0, 67, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #266 = G_FNEARBYINT
4717 { 265, 2, 1, 0, 0, 0, 0, 67, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #265 = G_FRINT
4718 { 264, 2, 1, 0, 0, 0, 0, 67, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #264 = G_FFLOOR
4719 { 263, 2, 1, 0, 0, 0, 0, 67, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #263 = G_FSQRT
4720 { 262, 2, 1, 0, 0, 0, 0, 67, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #262 = G_FTANH
4721 { 261, 2, 1, 0, 0, 0, 0, 67, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #261 = G_FSINH
4722 { 260, 2, 1, 0, 0, 0, 0, 67, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #260 = G_FCOSH
4723 { 259, 3, 1, 0, 0, 0, 0, 43, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #259 = G_FATAN2
4724 { 258, 2, 1, 0, 0, 0, 0, 67, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #258 = G_FATAN
4725 { 257, 2, 1, 0, 0, 0, 0, 67, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #257 = G_FASIN
4726 { 256, 2, 1, 0, 0, 0, 0, 67, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #256 = G_FACOS
4727 { 255, 2, 1, 0, 0, 0, 0, 67, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #255 = G_FTAN
4728 { 254, 3, 2, 0, 0, 0, 0, 43, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #254 = G_FSINCOS
4729 { 253, 2, 1, 0, 0, 0, 0, 67, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #253 = G_FSIN
4730 { 252, 2, 1, 0, 0, 0, 0, 67, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #252 = G_FCOS
4731 { 251, 2, 1, 0, 0, 0, 0, 67, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #251 = G_FCEIL
4732 { 250, 2, 1, 0, 0, 0, 0, 67, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #250 = G_BITREVERSE
4733 { 249, 2, 1, 0, 0, 0, 0, 67, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #249 = G_BSWAP
4734 { 248, 2, 1, 0, 0, 0, 0, 61, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #248 = G_CTPOP
4735 { 247, 2, 1, 0, 0, 0, 0, 61, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #247 = G_CTLZ_ZERO_UNDEF
4736 { 246, 2, 1, 0, 0, 0, 0, 61, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #246 = G_CTLZ
4737 { 245, 2, 1, 0, 0, 0, 0, 61, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #245 = G_CTTZ_ZERO_UNDEF
4738 { 244, 2, 1, 0, 0, 0, 0, 61, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #244 = G_CTTZ
4739 { 243, 4, 1, 0, 0, 0, 0, 138, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #243 = G_VECTOR_COMPRESS
4740 { 242, 2, 1, 0, 0, 0, 0, 51, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #242 = G_STEP_VECTOR
4741 { 241, 2, 1, 0, 0, 0, 0, 61, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #241 = G_SPLAT_VECTOR
4742 { 240, 4, 1, 0, 0, 0, 0, 134, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #240 = G_SHUFFLE_VECTOR
4743 { 239, 3, 1, 0, 0, 0, 0, 131, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #239 = G_EXTRACT_VECTOR_ELT
4744 { 238, 4, 1, 0, 0, 0, 0, 127, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #238 = G_INSERT_VECTOR_ELT
4745 { 237, 3, 1, 0, 0, 0, 0, 58, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #237 = G_EXTRACT_SUBVECTOR
4746 { 236, 4, 1, 0, 0, 0, 0, 63, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #236 = G_INSERT_SUBVECTOR
4747 { 235, 2, 1, 0, 0, 0, 0, 51, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #235 = G_VSCALE
4748 { 234, 3, 0, 0, 0, 0, 0, 124, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #234 = G_BRJT
4749 { 233, 1, 0, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #233 = G_BR
4750 { 232, 2, 1, 0, 0, 0, 0, 61, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #232 = G_LLROUND
4751 { 231, 2, 1, 0, 0, 0, 0, 61, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #231 = G_LROUND
4752 { 230, 2, 1, 0, 0, 0, 0, 67, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #230 = G_ABS
4753 { 229, 3, 1, 0, 0, 0, 0, 43, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #229 = G_UMAX
4754 { 228, 3, 1, 0, 0, 0, 0, 43, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #228 = G_UMIN
4755 { 227, 3, 1, 0, 0, 0, 0, 43, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #227 = G_SMAX
4756 { 226, 3, 1, 0, 0, 0, 0, 43, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #226 = G_SMIN
4757 { 225, 3, 1, 0, 0, 0, 0, 101, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #225 = G_PTRMASK
4758 { 224, 3, 1, 0, 0, 0, 0, 101, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #224 = G_PTR_ADD
4759 { 223, 0, 0, 0, 0, 0, 0, 1, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #223 = G_RESET_FPMODE
4760 { 222, 1, 0, 0, 0, 0, 0, 50, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #222 = G_SET_FPMODE
4761 { 221, 1, 1, 0, 0, 0, 0, 50, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #221 = G_GET_FPMODE
4762 { 220, 0, 0, 0, 0, 0, 0, 1, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #220 = G_RESET_FPENV
4763 { 219, 1, 0, 0, 0, 0, 0, 50, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #219 = G_SET_FPENV
4764 { 218, 1, 1, 0, 0, 0, 0, 50, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #218 = G_GET_FPENV
4765 { 217, 3, 1, 0, 0, 0, 0, 43, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #217 = G_FMAXIMUMNUM
4766 { 216, 3, 1, 0, 0, 0, 0, 43, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #216 = G_FMINIMUMNUM
4767 { 215, 3, 1, 0, 0, 0, 0, 43, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #215 = G_FMAXIMUM
4768 { 214, 3, 1, 0, 0, 0, 0, 43, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #214 = G_FMINIMUM
4769 { 213, 3, 1, 0, 0, 0, 0, 43, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #213 = G_FMAXNUM_IEEE
4770 { 212, 3, 1, 0, 0, 0, 0, 43, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #212 = G_FMINNUM_IEEE
4771 { 211, 3, 1, 0, 0, 0, 0, 43, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #211 = G_FMAXNUM
4772 { 210, 3, 1, 0, 0, 0, 0, 43, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #210 = G_FMINNUM
4773 { 209, 2, 1, 0, 0, 0, 0, 67, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #209 = G_FCANONICALIZE
4774 { 208, 3, 1, 0, 0, 0, 0, 98, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #208 = G_IS_FPCLASS
4775 { 207, 3, 1, 0, 0, 0, 0, 101, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #207 = G_FCOPYSIGN
4776 { 206, 2, 1, 0, 0, 0, 0, 67, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #206 = G_FABS
4777 { 205, 2, 1, 0, 0, 0, 0, 61, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #205 = G_FPTOUI_SAT
4778 { 204, 2, 1, 0, 0, 0, 0, 61, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #204 = G_FPTOSI_SAT
4779 { 203, 2, 1, 0, 0, 0, 0, 61, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #203 = G_UITOFP
4780 { 202, 2, 1, 0, 0, 0, 0, 61, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #202 = G_SITOFP
4781 { 201, 2, 1, 0, 0, 0, 0, 61, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #201 = G_FPTOUI
4782 { 200, 2, 1, 0, 0, 0, 0, 61, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #200 = G_FPTOSI
4783 { 199, 2, 1, 0, 0, 0, 0, 61, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #199 = G_FPTRUNC
4784 { 198, 2, 1, 0, 0, 0, 0, 61, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #198 = G_FPEXT
4785 { 197, 2, 1, 0, 0, 0, 0, 67, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #197 = G_FNEG
4786 { 196, 3, 2, 0, 0, 0, 0, 91, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #196 = G_FFREXP
4787 { 195, 3, 1, 0, 0, 0, 0, 101, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #195 = G_FLDEXP
4788 { 194, 2, 1, 0, 0, 0, 0, 67, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #194 = G_FLOG10
4789 { 193, 2, 1, 0, 0, 0, 0, 67, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #193 = G_FLOG2
4790 { 192, 2, 1, 0, 0, 0, 0, 67, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #192 = G_FLOG
4791 { 191, 2, 1, 0, 0, 0, 0, 67, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #191 = G_FEXP10
4792 { 190, 2, 1, 0, 0, 0, 0, 67, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #190 = G_FEXP2
4793 { 189, 2, 1, 0, 0, 0, 0, 67, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #189 = G_FEXP
4794 { 188, 3, 1, 0, 0, 0, 0, 101, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #188 = G_FPOWI
4795 { 187, 3, 1, 0, 0, 0, 0, 43, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #187 = G_FPOW
4796 { 186, 3, 1, 0, 0, 0, 0, 43, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #186 = G_FREM
4797 { 185, 3, 1, 0, 0, 0, 0, 43, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #185 = G_FDIV
4798 { 184, 4, 1, 0, 0, 0, 0, 46, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #184 = G_FMAD
4799 { 183, 4, 1, 0, 0, 0, 0, 46, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #183 = G_FMA
4800 { 182, 3, 1, 0, 0, 0, 0, 43, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #182 = G_FMUL
4801 { 181, 3, 1, 0, 0, 0, 0, 43, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #181 = G_FSUB
4802 { 180, 3, 1, 0, 0, 0, 0, 43, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #180 = G_FADD
4803 { 179, 4, 1, 0, 0, 0, 0, 120, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #179 = G_UDIVFIXSAT
4804 { 178, 4, 1, 0, 0, 0, 0, 120, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #178 = G_SDIVFIXSAT
4805 { 177, 4, 1, 0, 0, 0, 0, 120, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #177 = G_UDIVFIX
4806 { 176, 4, 1, 0, 0, 0, 0, 120, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #176 = G_SDIVFIX
4807 { 175, 4, 1, 0, 0, 0, 0, 120, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #175 = G_UMULFIXSAT
4808 { 174, 4, 1, 0, 0, 0, 0, 120, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #174 = G_SMULFIXSAT
4809 { 173, 4, 1, 0, 0, 0, 0, 120, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #173 = G_UMULFIX
4810 { 172, 4, 1, 0, 0, 0, 0, 120, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #172 = G_SMULFIX
4811 { 171, 3, 1, 0, 0, 0, 0, 101, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #171 = G_SSHLSAT
4812 { 170, 3, 1, 0, 0, 0, 0, 101, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #170 = G_USHLSAT
4813 { 169, 3, 1, 0, 0, 0, 0, 43, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #169 = G_SSUBSAT
4814 { 168, 3, 1, 0, 0, 0, 0, 43, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #168 = G_USUBSAT
4815 { 167, 3, 1, 0, 0, 0, 0, 43, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #167 = G_SADDSAT
4816 { 166, 3, 1, 0, 0, 0, 0, 43, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #166 = G_UADDSAT
4817 { 165, 3, 1, 0, 0, 0, 0, 43, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #165 = G_SMULH
4818 { 164, 3, 1, 0, 0, 0, 0, 43, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #164 = G_UMULH
4819 { 163, 4, 2, 0, 0, 0, 0, 87, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #163 = G_SMULO
4820 { 162, 4, 2, 0, 0, 0, 0, 87, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #162 = G_UMULO
4821 { 161, 5, 2, 0, 0, 0, 0, 115, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #161 = G_SSUBE
4822 { 160, 4, 2, 0, 0, 0, 0, 87, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #160 = G_SSUBO
4823 { 159, 5, 2, 0, 0, 0, 0, 115, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #159 = G_SADDE
4824 { 158, 4, 2, 0, 0, 0, 0, 87, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #158 = G_SADDO
4825 { 157, 5, 2, 0, 0, 0, 0, 115, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #157 = G_USUBE
4826 { 156, 4, 2, 0, 0, 0, 0, 87, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #156 = G_USUBO
4827 { 155, 5, 2, 0, 0, 0, 0, 115, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #155 = G_UADDE
4828 { 154, 4, 2, 0, 0, 0, 0, 87, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #154 = G_UADDO
4829 { 153, 4, 1, 0, 0, 0, 0, 87, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #153 = G_SELECT
4830 { 152, 3, 1, 0, 0, 0, 0, 112, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #152 = G_UCMP
4831 { 151, 3, 1, 0, 0, 0, 0, 112, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #151 = G_SCMP
4832 { 150, 4, 1, 0, 0, 0, 0, 108, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #150 = G_FCMP
4833 { 149, 4, 1, 0, 0, 0, 0, 108, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #149 = G_ICMP
4834 { 148, 3, 1, 0, 0, 0, 0, 101, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #148 = G_ROTL
4835 { 147, 3, 1, 0, 0, 0, 0, 101, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #147 = G_ROTR
4836 { 146, 4, 1, 0, 0, 0, 0, 104, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #146 = G_FSHR
4837 { 145, 4, 1, 0, 0, 0, 0, 104, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #145 = G_FSHL
4838 { 144, 3, 1, 0, 0, 0, 0, 101, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #144 = G_ASHR
4839 { 143, 3, 1, 0, 0, 0, 0, 101, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #143 = G_LSHR
4840 { 142, 3, 1, 0, 0, 0, 0, 101, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #142 = G_SHL
4841 { 141, 2, 1, 0, 0, 0, 0, 61, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #141 = G_ZEXT
4842 { 140, 3, 1, 0, 0, 0, 0, 40, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #140 = G_SEXT_INREG
4843 { 139, 2, 1, 0, 0, 0, 0, 61, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #139 = G_SEXT
4844 { 138, 3, 1, 0, 0, 0, 0, 98, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #138 = G_VAARG
4845 { 137, 1, 0, 0, 0, 0, 0, 50, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #137 = G_VASTART
4846 { 136, 2, 1, 0, 0, 0, 0, 51, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #136 = G_FCONSTANT
4847 { 135, 2, 1, 0, 0, 0, 0, 51, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #135 = G_CONSTANT
4848 { 134, 2, 1, 0, 0, 0, 0, 61, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #134 = G_TRUNC
4849 { 133, 2, 1, 0, 0, 0, 0, 61, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #133 = G_ANYEXT
4850 { 132, 1, 0, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #132 = G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
4851 { 131, 1, 0, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #131 = G_INTRINSIC_CONVERGENT
4852 { 130, 1, 0, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #130 = G_INTRINSIC_W_SIDE_EFFECTS
4853 { 129, 1, 0, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #129 = G_INTRINSIC
4854 { 128, 0, 0, 0, 0, 0, 0, 1, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #128 = G_INVOKE_REGION_START
4855 { 127, 1, 0, 0, 0, 0, 0, 50, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #127 = G_BRINDIRECT
4856 { 126, 2, 0, 0, 0, 0, 0, 51, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #126 = G_BRCOND
4857 { 125, 4, 0, 0, 0, 0, 0, 94, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #125 = G_PREFETCH
4858 { 124, 2, 0, 0, 0, 0, 0, 21, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #124 = G_FENCE
4859 { 123, 3, 1, 0, 0, 0, 0, 91, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #123 = G_ATOMICRMW_USUB_SAT
4860 { 122, 3, 1, 0, 0, 0, 0, 91, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #122 = G_ATOMICRMW_USUB_COND
4861 { 121, 3, 1, 0, 0, 0, 0, 91, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #121 = G_ATOMICRMW_UDEC_WRAP
4862 { 120, 3, 1, 0, 0, 0, 0, 91, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #120 = G_ATOMICRMW_UINC_WRAP
4863 { 119, 3, 1, 0, 0, 0, 0, 91, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #119 = G_ATOMICRMW_FMINIMUM
4864 { 118, 3, 1, 0, 0, 0, 0, 91, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #118 = G_ATOMICRMW_FMAXIMUM
4865 { 117, 3, 1, 0, 0, 0, 0, 91, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #117 = G_ATOMICRMW_FMIN
4866 { 116, 3, 1, 0, 0, 0, 0, 91, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #116 = G_ATOMICRMW_FMAX
4867 { 115, 3, 1, 0, 0, 0, 0, 91, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #115 = G_ATOMICRMW_FSUB
4868 { 114, 3, 1, 0, 0, 0, 0, 91, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #114 = G_ATOMICRMW_FADD
4869 { 113, 3, 1, 0, 0, 0, 0, 91, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #113 = G_ATOMICRMW_UMIN
4870 { 112, 3, 1, 0, 0, 0, 0, 91, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #112 = G_ATOMICRMW_UMAX
4871 { 111, 3, 1, 0, 0, 0, 0, 91, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #111 = G_ATOMICRMW_MIN
4872 { 110, 3, 1, 0, 0, 0, 0, 91, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #110 = G_ATOMICRMW_MAX
4873 { 109, 3, 1, 0, 0, 0, 0, 91, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #109 = G_ATOMICRMW_XOR
4874 { 108, 3, 1, 0, 0, 0, 0, 91, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #108 = G_ATOMICRMW_OR
4875 { 107, 3, 1, 0, 0, 0, 0, 91, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #107 = G_ATOMICRMW_NAND
4876 { 106, 3, 1, 0, 0, 0, 0, 91, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #106 = G_ATOMICRMW_AND
4877 { 105, 3, 1, 0, 0, 0, 0, 91, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #105 = G_ATOMICRMW_SUB
4878 { 104, 3, 1, 0, 0, 0, 0, 91, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #104 = G_ATOMICRMW_ADD
4879 { 103, 3, 1, 0, 0, 0, 0, 91, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #103 = G_ATOMICRMW_XCHG
4880 { 102, 4, 1, 0, 0, 0, 0, 87, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #102 = G_ATOMIC_CMPXCHG
4881 { 101, 5, 2, 0, 0, 0, 0, 82, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #101 = G_ATOMIC_CMPXCHG_WITH_SUCCESS
4882 { 100, 5, 1, 0, 0, 0, 0, 77, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #100 = G_INDEXED_STORE
4883 { 99, 2, 0, 0, 0, 0, 0, 61, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #99 = G_STORE
4884 { 98, 5, 2, 0, 0, 0, 0, 72, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #98 = G_INDEXED_ZEXTLOAD
4885 { 97, 5, 2, 0, 0, 0, 0, 72, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #97 = G_INDEXED_SEXTLOAD
4886 { 96, 5, 2, 0, 0, 0, 0, 72, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #96 = G_INDEXED_LOAD
4887 { 95, 2, 1, 0, 0, 0, 0, 61, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #95 = G_ZEXTLOAD
4888 { 94, 2, 1, 0, 0, 0, 0, 61, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #94 = G_SEXTLOAD
4889 { 93, 2, 1, 0, 0, 0, 0, 61, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #93 = G_LOAD
4890 { 92, 1, 1, 0, 0, 0, 0, 50, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #92 = G_READSTEADYCOUNTER
4891 { 91, 1, 1, 0, 0, 0, 0, 50, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #91 = G_READCYCLECOUNTER
4892 { 90, 2, 1, 0, 0, 0, 0, 67, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #90 = G_INTRINSIC_ROUNDEVEN
4893 { 89, 2, 1, 0, 0, 0, 0, 61, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #89 = G_INTRINSIC_LLRINT
4894 { 88, 2, 1, 0, 0, 0, 0, 61, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #88 = G_INTRINSIC_LRINT
4895 { 87, 2, 1, 0, 0, 0, 0, 67, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #87 = G_INTRINSIC_ROUND
4896 { 86, 2, 1, 0, 0, 0, 0, 67, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #86 = G_INTRINSIC_TRUNC
4897 { 85, 3, 1, 0, 0, 0, 0, 69, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #85 = G_INTRINSIC_FPTRUNC_ROUND
4898 { 84, 2, 1, 0, 0, 0, 0, 67, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #84 = G_CONSTANT_FOLD_BARRIER
4899 { 83, 2, 1, 0, 0, 0, 0, 67, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #83 = G_FREEZE
4900 { 82, 2, 1, 0, 0, 0, 0, 61, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #82 = G_BITCAST
4901 { 81, 2, 1, 0, 0, 0, 0, 61, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #81 = G_INTTOPTR
4902 { 80, 2, 1, 0, 0, 0, 0, 61, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #80 = G_PTRTOINT
4903 { 79, 2, 1, 0, 0, 0, 0, 61, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #79 = G_CONCAT_VECTORS
4904 { 78, 2, 1, 0, 0, 0, 0, 61, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #78 = G_BUILD_VECTOR_TRUNC
4905 { 77, 2, 1, 0, 0, 0, 0, 61, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #77 = G_BUILD_VECTOR
4906 { 76, 2, 1, 0, 0, 0, 0, 61, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #76 = G_MERGE_VALUES
4907 { 75, 4, 1, 0, 0, 0, 0, 63, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #75 = G_INSERT
4908 { 74, 2, 1, 0, 0, 0, 0, 61, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #74 = G_UNMERGE_VALUES
4909 { 73, 3, 1, 0, 0, 0, 0, 58, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #73 = G_EXTRACT
4910 { 72, 2, 1, 0, 0, 0, 0, 51, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #72 = G_CONSTANT_POOL
4911 { 71, 5, 1, 0, 0, 0, 0, 53, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #71 = G_PTRAUTH_GLOBAL_VALUE
4912 { 70, 2, 1, 0, 0, 0, 0, 51, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #70 = G_GLOBAL_VALUE
4913 { 69, 2, 1, 0, 0, 0, 0, 51, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #69 = G_FRAME_INDEX
4914 { 68, 1, 1, 0, 0, 0, 0, 50, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #68 = G_PHI
4915 { 67, 1, 1, 0, 0, 0, 0, 50, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #67 = G_IMPLICIT_DEF
4916 { 66, 3, 1, 0, 0, 0, 0, 43, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #66 = G_ABDU
4917 { 65, 3, 1, 0, 0, 0, 0, 43, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #65 = G_ABDS
4918 { 64, 3, 1, 0, 0, 0, 0, 43, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #64 = G_XOR
4919 { 63, 3, 1, 0, 0, 0, 0, 43, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #63 = G_OR
4920 { 62, 3, 1, 0, 0, 0, 0, 43, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #62 = G_AND
4921 { 61, 4, 2, 0, 0, 0, 0, 46, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #61 = G_UDIVREM
4922 { 60, 4, 2, 0, 0, 0, 0, 46, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #60 = G_SDIVREM
4923 { 59, 3, 1, 0, 0, 0, 0, 43, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #59 = G_UREM
4924 { 58, 3, 1, 0, 0, 0, 0, 43, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #58 = G_SREM
4925 { 57, 3, 1, 0, 0, 0, 0, 43, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #57 = G_UDIV
4926 { 56, 3, 1, 0, 0, 0, 0, 43, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #56 = G_SDIV
4927 { 55, 3, 1, 0, 0, 0, 0, 43, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #55 = G_MUL
4928 { 54, 3, 1, 0, 0, 0, 0, 43, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #54 = G_SUB
4929 { 53, 3, 1, 0, 0, 0, 0, 43, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #53 = G_ADD
4930 { 52, 3, 1, 0, 0, 0, 0, 40, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #52 = G_ASSERT_ALIGN
4931 { 51, 3, 1, 0, 0, 0, 0, 40, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #51 = G_ASSERT_ZEXT
4932 { 50, 3, 1, 0, 0, 0, 0, 40, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #50 = G_ASSERT_SEXT
4933 { 49, 1, 0, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #49 = CONVERGENCECTRL_GLUE
4934 { 48, 2, 1, 0, 0, 0, 0, 13, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #48 = CONVERGENCECTRL_LOOP
4935 { 47, 1, 1, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #47 = CONVERGENCECTRL_ANCHOR
4936 { 46, 1, 1, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #46 = CONVERGENCECTRL_ENTRY
4937 { 45, 1, 0, 0, 0, 0, 0, 1, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // Inst #45 = JUMP_TABLE_DEBUG_INFO
4938 { 44, 0, 0, 0, 0, 0, 0, 1, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #44 = MEMBARRIER
4939 { 43, 0, 0, 0, 0, 0, 0, 1, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #43 = FAKE_USE
4940 { 42, 0, 0, 0, 0, 0, 0, 1, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #42 = ICALL_BRANCH_FUNNEL
4941 { 41, 3, 0, 0, 0, 0, 0, 37, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #41 = PATCHABLE_TYPED_EVENT_CALL
4942 { 40, 2, 0, 0, 0, 0, 0, 35, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #40 = PATCHABLE_EVENT_CALL
4943 { 39, 0, 0, 0, 0, 0, 0, 1, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #39 = PATCHABLE_TAIL_CALL
4944 { 38, 0, 0, 0, 0, 0, 0, 1, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #38 = PATCHABLE_FUNCTION_EXIT
4945 { 37, 0, 0, 0, 0, 0, 0, 1, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #37 = PATCHABLE_RET
4946 { 36, 0, 0, 0, 0, 0, 0, 1, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #36 = PATCHABLE_FUNCTION_ENTER
4947 { 35, 0, 0, 0, 0, 0, 0, 1, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #35 = PATCHABLE_OP
4948 { 34, 1, 1, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #34 = FAULTING_OP
4949 { 33, 2, 0, 0, 0, 0, 0, 33, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #33 = LOCAL_ESCAPE
4950 { 32, 0, 0, 0, 0, 0, 0, 1, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #32 = STATEPOINT
4951 { 31, 3, 1, 0, 0, 0, 0, 30, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #31 = PREALLOCATED_ARG
4952 { 30, 1, 0, 0, 0, 0, 0, 1, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #30 = PREALLOCATED_SETUP
4953 { 29, 1, 1, 0, 0, 0, 0, 29, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL }, // Inst #29 = LOAD_STACK_GUARD
4954 { 28, 6, 1, 0, 0, 0, 0, 23, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #28 = PATCHPOINT
4955 { 27, 0, 0, 0, 0, 0, 0, 1, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #27 = FENTRY_CALL
4956 { 26, 2, 0, 0, 0, 0, 0, 21, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #26 = STACKMAP
4957 { 25, 2, 1, 0, 0, 0, 0, 19, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // Inst #25 = ARITH_FENCE
4958 { 24, 4, 0, 0, 0, 0, 0, 15, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #24 = PSEUDO_PROBE
4959 { 23, 1, 0, 0, 0, 0, 0, 1, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // Inst #23 = LIFETIME_END
4960 { 22, 1, 0, 0, 0, 0, 0, 1, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // Inst #22 = LIFETIME_START
4961 { 21, 0, 0, 0, 0, 0, 0, 1, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #21 = BUNDLE
4962 { 20, 2, 1, 0, 0, 0, 0, 13, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #20 = COPY
4963 { 19, 2, 1, 0, 0, 0, 0, 13, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #19 = REG_SEQUENCE
4964 { 18, 1, 0, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // Inst #18 = DBG_LABEL
4965 { 17, 0, 0, 0, 0, 0, 0, 1, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #17 = DBG_PHI
4966 { 16, 0, 0, 0, 0, 0, 0, 1, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #16 = DBG_INSTR_REF
4967 { 15, 0, 0, 0, 0, 0, 0, 1, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #15 = DBG_VALUE_LIST
4968 { 14, 0, 0, 0, 0, 0, 0, 1, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #14 = DBG_VALUE
4969 { 13, 3, 1, 0, 0, 0, 0, 2, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #13 = COPY_TO_REGCLASS
4970 { 12, 4, 1, 0, 0, 0, 0, 9, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #12 = SUBREG_TO_REG
4971 { 11, 1, 1, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #11 = INIT_UNDEF
4972 { 10, 1, 1, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #10 = IMPLICIT_DEF
4973 { 9, 4, 1, 0, 0, 0, 0, 5, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #9 = INSERT_SUBREG
4974 { 8, 3, 1, 0, 0, 0, 0, 2, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #8 = EXTRACT_SUBREG
4975 { 7, 0, 0, 0, 0, 0, 0, 1, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #7 = KILL
4976 { 6, 1, 0, 0, 0, 0, 0, 1, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // Inst #6 = ANNOTATION_LABEL
4977 { 5, 1, 0, 0, 0, 0, 0, 1, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // Inst #5 = GC_LABEL
4978 { 4, 1, 0, 0, 0, 0, 0, 1, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // Inst #4 = EH_LABEL
4979 { 3, 1, 0, 0, 0, 0, 0, 1, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // Inst #3 = CFI_INSTRUCTION
4980 { 2, 0, 0, 0, 0, 0, 0, 1, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2 = INLINEASM_BR
4981 { 1, 0, 0, 0, 0, 0, 0, 1, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #1 = INLINEASM
4982 { 0, 1, 1, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #0 = PHI
4983 }, {
4984 /* 0 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
4985 /* 1 */
4986 /* 1 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
4987 /* 2 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
4988 /* 5 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
4989 /* 9 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
4990 /* 13 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
4991 /* 15 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
4992 /* 19 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) },
4993 /* 21 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
4994 /* 23 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
4995 /* 29 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 },
4996 /* 30 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
4997 /* 33 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
4998 /* 35 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
4999 /* 37 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
5000 /* 40 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
5001 /* 43 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
5002 /* 46 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
5003 /* 50 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
5004 /* 51 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
5005 /* 53 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
5006 /* 58 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
5007 /* 61 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
5008 /* 63 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
5009 /* 67 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
5010 /* 69 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
5011 /* 72 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
5012 /* 77 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
5013 /* 82 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
5014 /* 87 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
5015 /* 91 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
5016 /* 94 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
5017 /* 98 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
5018 /* 101 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
5019 /* 104 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
5020 /* 108 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
5021 /* 112 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
5022 /* 115 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
5023 /* 120 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
5024 /* 124 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
5025 /* 127 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
5026 /* 131 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
5027 /* 134 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
5028 /* 138 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
5029 /* 142 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
5030 /* 144 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
5031 /* 148 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
5032 /* 152 */ { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
5033 /* 155 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
5034 /* 159 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
5035 /* 164 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
5036 /* 167 */ { LoongArch::GPRJRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
5037 /* 169 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
5038 /* 170 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
5039 /* 172 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
5040 /* 180 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
5041 /* 186 */ { LoongArch::CFRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::CFRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
5042 /* 188 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
5043 /* 191 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
5044 /* 193 */ { LoongArch::CFRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
5045 /* 196 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
5046 /* 204 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
5047 /* 211 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
5048 /* 218 */ { LoongArch::GPRTRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
5049 /* 219 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
5050 /* 221 */ { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
5051 /* 223 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
5052 /* 225 */ { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
5053 /* 229 */ { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
5054 /* 231 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
5055 /* 237 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
5056 /* 240 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
5057 /* 242 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
5058 /* 245 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
5059 /* 249 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
5060 /* 252 */ { LoongArch::CFRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
5061 /* 254 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
5062 /* 259 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
5063 /* 263 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
5064 /* 266 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
5065 /* 269 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { LoongArch::GPRNoR0R1RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
5066 /* 273 */ { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
5067 /* 275 */ { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
5068 /* 277 */ { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
5069 /* 280 */ { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
5070 /* 283 */ { LoongArch::CFRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
5071 /* 286 */ { LoongArch::CFRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
5072 /* 289 */ { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
5073 /* 291 */ { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
5074 /* 293 */ { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
5075 /* 296 */ { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
5076 /* 299 */ { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
5077 /* 302 */ { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
5078 /* 306 */ { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
5079 /* 310 */ { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::CFRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
5080 /* 314 */ { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::CFRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
5081 /* 318 */ { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::CFRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
5082 /* 320 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::CFRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
5083 /* 322 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FCSRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
5084 /* 324 */ { LoongArch::CFRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
5085 /* 326 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
5086 /* 328 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
5087 /* 330 */ { LoongArch::CFRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
5088 /* 332 */ { LoongArch::FCSRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
5089 /* 334 */ { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
5090 /* 337 */ { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
5091 /* 339 */ { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
5092 /* 341 */ { LoongArch::SCRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
5093 /* 343 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::SCRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
5094 /* 345 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
5095 /* 348 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
5096 /* 351 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
5097 /* 355 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
5098 /* 359 */ { LoongArch::CFRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
5099 /* 360 */ { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
5100 /* 363 */ { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
5101 /* 366 */ { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
5102 /* 370 */ { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
5103 /* 374 */ { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
5104 /* 376 */ { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
5105 /* 378 */ { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
5106 /* 382 */ { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
5107 /* 386 */ { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
5108 /* 389 */ { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
5109 /* 392 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
5110 /* 395 */ { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
5111 /* 397 */ { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
5112 /* 400 */ { LoongArch::CFRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
5113 /* 402 */ { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
5114 /* 406 */ { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
5115 /* 409 */ { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
5116 /* 412 */ { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
5117 /* 416 */ { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
5118 /* 420 */ { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
5119 /* 424 */ { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
5120 /* 427 */ { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
5121 /* 430 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
5122 /* 433 */ { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
5123 /* 435 */ { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
5124 /* 438 */ { LoongArch::CFRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
5125 /* 440 */ { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
5126 }, {
5127 /* 0 */
5128 /* 0 */ LoongArch::R3, LoongArch::R3,
5129 /* 2 */ LoongArch::R3,
5130 /* 3 */ LoongArch::R1,
5131 /* 4 */ LoongArch::R1, LoongArch::R20,
5132 /* 6 */ LoongArch::R4, LoongArch::R4,
5133 /* 8 */ LoongArch::R1, LoongArch::R4,
5134 /* 10 */ LoongArch::R3, LoongArch::R20,
5135 }
5136};
5137
5138
5139#ifdef __GNUC__
5140#pragma GCC diagnostic push
5141#pragma GCC diagnostic ignored "-Woverlength-strings"
5142#endif
5143extern const char LoongArchInstrNameData[] = {
5144 /* 0 */ "G_FLOG10\000"
5145 /* 9 */ "G_FEXP10\000"
5146 /* 18 */ "JISCR0\000"
5147 /* 25 */ "JISCR1\000"
5148 /* 32 */ "PseudoMaskedAtomicLoadSub32\000"
5149 /* 60 */ "PseudoAtomicLoadSub32\000"
5150 /* 82 */ "PseudoMaskedAtomicLoadAdd32\000"
5151 /* 110 */ "PseudoAtomicLoadAdd32\000"
5152 /* 132 */ "PseudoAtomicLoadAnd32\000"
5153 /* 154 */ "PseudoMaskedAtomicLoadNand32\000"
5154 /* 183 */ "PseudoAtomicLoadNand32\000"
5155 /* 206 */ "PseudoMaskedCmpXchg32\000"
5156 /* 228 */ "PseudoCmpXchg32\000"
5157 /* 244 */ "PseudoMaskedAtomicLoadUMin32\000"
5158 /* 273 */ "PseudoAtomicLoadUMin32\000"
5159 /* 296 */ "PseudoMaskedAtomicLoadMin32\000"
5160 /* 324 */ "PseudoAtomicLoadMin32\000"
5161 /* 346 */ "PseudoMaskedAtomicSwap32\000"
5162 /* 371 */ "PseudoAtomicSwap32\000"
5163 /* 390 */ "PseudoAtomicLoadOr32\000"
5164 /* 411 */ "PseudoAtomicLoadXor32\000"
5165 /* 433 */ "PseudoMaskedAtomicLoadUMax32\000"
5166 /* 462 */ "PseudoAtomicLoadUMax32\000"
5167 /* 485 */ "PseudoMaskedAtomicLoadMax32\000"
5168 /* 513 */ "PseudoAtomicLoadMax32\000"
5169 /* 535 */ "G_FLOG2\000"
5170 /* 543 */ "G_FATAN2\000"
5171 /* 552 */ "G_FEXP2\000"
5172 /* 560 */ "MOVFR2GR_S_64\000"
5173 /* 574 */ "MOVGR2FR_W_64\000"
5174 /* 588 */ "PseudoAtomicLoadNand64\000"
5175 /* 611 */ "PseudoCmpXchg64\000"
5176 /* 627 */ "PseudoTAIL36\000"
5177 /* 640 */ "PseudoCALL36\000"
5178 /* 653 */ "PseudoCmpXchg128\000"
5179 /* 670 */ "G_FMA\000"
5180 /* 676 */ "G_STRICT_FMA\000"
5181 /* 689 */ "BITREV_4B\000"
5182 /* 699 */ "BITREV_8B\000"
5183 /* 709 */ "INVTLB\000"
5184 /* 716 */ "G_FSUB\000"
5185 /* 723 */ "G_STRICT_FSUB\000"
5186 /* 737 */ "G_ATOMICRMW_FSUB\000"
5187 /* 754 */ "G_SUB\000"
5188 /* 760 */ "G_ATOMICRMW_SUB\000"
5189 /* 776 */ "XVREPLVE0_B\000"
5190 /* 788 */ "XVADDA_B\000"
5191 /* 797 */ "X86SRA_B\000"
5192 /* 806 */ "XVSRA_B\000"
5193 /* 814 */ "AMADD__DB_B\000"
5194 /* 826 */ "AMSWAP__DB_B\000"
5195 /* 839 */ "AMCAS__DB_B\000"
5196 /* 851 */ "X86SUB_B\000"
5197 /* 860 */ "XVMSUB_B\000"
5198 /* 869 */ "XVSSUB_B\000"
5199 /* 878 */ "XVSUB_B\000"
5200 /* 886 */ "X86SBC_B\000"
5201 /* 895 */ "X86ADC_B\000"
5202 /* 904 */ "X86DEC_B\000"
5203 /* 913 */ "X86INC_B\000"
5204 /* 922 */ "X86ADD_B\000"
5205 /* 931 */ "AMADD_B\000"
5206 /* 939 */ "XVMADD_B\000"
5207 /* 948 */ "XVSADD_B\000"
5208 /* 957 */ "XVADD_B\000"
5209 /* 965 */ "LD_B\000"
5210 /* 970 */ "X86AND_B\000"
5211 /* 979 */ "XVPACKOD_B\000"
5212 /* 990 */ "XVPICKOD_B\000"
5213 /* 1001 */ "XVMOD_B\000"
5214 /* 1009 */ "IOCSRRD_B\000"
5215 /* 1019 */ "XVABSD_B\000"
5216 /* 1028 */ "VEXT2XV_D_B\000"
5217 /* 1040 */ "LDLE_B\000"
5218 /* 1047 */ "XVSLE_B\000"
5219 /* 1055 */ "STLE_B\000"
5220 /* 1062 */ "XVREPLVE_B\000"
5221 /* 1073 */ "XVSHUF_B\000"
5222 /* 1082 */ "XVNEG_B\000"
5223 /* 1090 */ "XVAVG_B\000"
5224 /* 1098 */ "XVMUH_B\000"
5225 /* 1106 */ "XVILVH_B\000"
5226 /* 1115 */ "XVSUBWOD_H_B\000"
5227 /* 1128 */ "XVMADDWOD_H_B\000"
5228 /* 1142 */ "XVADDWOD_H_B\000"
5229 /* 1155 */ "XVMULWOD_H_B\000"
5230 /* 1168 */ "XVEXTH_H_B\000"
5231 /* 1179 */ "XVSLLWIL_H_B\000"
5232 /* 1192 */ "XVSUBWEV_H_B\000"
5233 /* 1205 */ "XVMADDWEV_H_B\000"
5234 /* 1219 */ "XVADDWEV_H_B\000"
5235 /* 1232 */ "XVMULWEV_H_B\000"
5236 /* 1245 */ "VEXT2XV_H_B\000"
5237 /* 1257 */ "XVHSUBW_H_B\000"
5238 /* 1269 */ "XVHADDW_H_B\000"
5239 /* 1281 */ "XVSHUF4I_B\000"
5240 /* 1292 */ "X86SRAI_B\000"
5241 /* 1302 */ "XVSRAI_B\000"
5242 /* 1311 */ "XVANDI_B\000"
5243 /* 1320 */ "XVSLEI_B\000"
5244 /* 1329 */ "XVREPL128VEI_B\000"
5245 /* 1344 */ "VREPLVEI_B\000"
5246 /* 1355 */ "X86RCLI_B\000"
5247 /* 1365 */ "XVBITSELI_B\000"
5248 /* 1377 */ "X86SLLI_B\000"
5249 /* 1387 */ "XVSLLI_B\000"
5250 /* 1396 */ "PseudoXVREPLI_B\000"
5251 /* 1412 */ "PseudoVREPLI_B\000"
5252 /* 1427 */ "X86SRLI_B\000"
5253 /* 1437 */ "XVSRLI_B\000"
5254 /* 1446 */ "X86ROTLI_B\000"
5255 /* 1457 */ "XVMINI_B\000"
5256 /* 1466 */ "XVFRSTPI_B\000"
5257 /* 1477 */ "XVSEQI_B\000"
5258 /* 1486 */ "XVSRARI_B\000"
5259 /* 1496 */ "X86RCRI_B\000"
5260 /* 1506 */ "XVBITCLRI_B\000"
5261 /* 1518 */ "XVSRLRI_B\000"
5262 /* 1528 */ "XVNORI_B\000"
5263 /* 1537 */ "XVORI_B\000"
5264 /* 1545 */ "XVXORI_B\000"
5265 /* 1554 */ "X86ROTRI_B\000"
5266 /* 1565 */ "XVROTRI_B\000"
5267 /* 1575 */ "XVBITSETI_B\000"
5268 /* 1587 */ "XVSLTI_B\000"
5269 /* 1596 */ "XVBITREVI_B\000"
5270 /* 1608 */ "XVMAXI_B\000"
5271 /* 1617 */ "X86RCL_B\000"
5272 /* 1626 */ "X86SLL_B\000"
5273 /* 1635 */ "XVSLL_B\000"
5274 /* 1643 */ "XVLDREPL_B\000"
5275 /* 1654 */ "X86SRL_B\000"
5276 /* 1663 */ "XVSRL_B\000"
5277 /* 1671 */ "X86ROTL_B\000"
5278 /* 1681 */ "X86MUL_B\000"
5279 /* 1690 */ "XVMUL_B\000"
5280 /* 1698 */ "XVILVL_B\000"
5281 /* 1707 */ "XVSTELM_B\000"
5282 /* 1717 */ "XVMIN_B\000"
5283 /* 1725 */ "XVCLO_B\000"
5284 /* 1733 */ "AMSWAP_B\000"
5285 /* 1742 */ "XVFRSTP_B\000"
5286 /* 1752 */ "XVSEQ_B\000"
5287 /* 1760 */ "XVSRAR_B\000"
5288 /* 1769 */ "X86RCR_B\000"
5289 /* 1778 */ "VPICKVE2GR_B\000"
5290 /* 1791 */ "XVAVGR_B\000"
5291 /* 1800 */ "XVBITCLR_B\000"
5292 /* 1811 */ "XVSRLR_B\000"
5293 /* 1820 */ "X86OR_B\000"
5294 /* 1828 */ "X86XOR_B\000"
5295 /* 1837 */ "X86ROTR_B\000"
5296 /* 1847 */ "XVROTR_B\000"
5297 /* 1856 */ "XVREPLGR2VR_B\000"
5298 /* 1870 */ "PseudoXVINSGR2VR_B\000"
5299 /* 1889 */ "IOCSRWR_B\000"
5300 /* 1899 */ "AMCAS_B\000"
5301 /* 1907 */ "XVEXTRINS_B\000"
5302 /* 1919 */ "XVSAT_B\000"
5303 /* 1927 */ "XVBITSET_B\000"
5304 /* 1938 */ "LDGT_B\000"
5305 /* 1945 */ "STGT_B\000"
5306 /* 1952 */ "XVSLT_B\000"
5307 /* 1960 */ "XVPCNT_B\000"
5308 /* 1969 */ "ST_B\000"
5309 /* 1974 */ "XVMADDWOD_H_BU_B\000"
5310 /* 1991 */ "XVADDWOD_H_BU_B\000"
5311 /* 2007 */ "XVMULWOD_H_BU_B\000"
5312 /* 2023 */ "XVMADDWEV_H_BU_B\000"
5313 /* 2040 */ "XVADDWEV_H_BU_B\000"
5314 /* 2056 */ "XVMULWEV_H_BU_B\000"
5315 /* 2072 */ "XVPACKEV_B\000"
5316 /* 2083 */ "XVPICKEV_B\000"
5317 /* 2094 */ "XVBITREV_B\000"
5318 /* 2105 */ "XVDIV_B\000"
5319 /* 2113 */ "XVSIGNCOV_B\000"
5320 /* 2125 */ "EXT_W_B\000"
5321 /* 2133 */ "VEXT2XV_W_B\000"
5322 /* 2145 */ "XVMAX_B\000"
5323 /* 2153 */ "LDX_B\000"
5324 /* 2159 */ "STX_B\000"
5325 /* 2165 */ "PseudoXVBZ_B\000"
5326 /* 2178 */ "PseudoVBZ_B\000"
5327 /* 2190 */ "PseudoXVMSKGEZ_B\000"
5328 /* 2207 */ "PseudoVMSKGEZ_B\000"
5329 /* 2223 */ "PseudoXVMSKNEZ_B\000"
5330 /* 2240 */ "PseudoVMSKNEZ_B\000"
5331 /* 2256 */ "XVSETALLNEZ_B\000"
5332 /* 2270 */ "XVCLZ_B\000"
5333 /* 2278 */ "PseudoXVBNZ_B\000"
5334 /* 2292 */ "PseudoVBNZ_B\000"
5335 /* 2305 */ "XVMSKNZ_B\000"
5336 /* 2315 */ "PseudoXVMSKEQZ_B\000"
5337 /* 2332 */ "PseudoVMSKEQZ_B\000"
5338 /* 2348 */ "XVSETANYEQZ_B\000"
5339 /* 2362 */ "PseudoXVMSKLTZ_B\000"
5340 /* 2379 */ "PseudoVMSKLTZ_B\000"
5341 /* 2395 */ "G_INTRINSIC\000"
5342 /* 2407 */ "G_FPTRUNC\000"
5343 /* 2417 */ "G_INTRINSIC_TRUNC\000"
5344 /* 2435 */ "G_TRUNC\000"
5345 /* 2443 */ "G_BUILD_VECTOR_TRUNC\000"
5346 /* 2464 */ "G_DYN_STACKALLOC\000"
5347 /* 2481 */ "PseudoLA_TLS_DESC\000"
5348 /* 2499 */ "G_FMAD\000"
5349 /* 2506 */ "G_INDEXED_SEXTLOAD\000"
5350 /* 2525 */ "G_SEXTLOAD\000"
5351 /* 2536 */ "G_INDEXED_ZEXTLOAD\000"
5352 /* 2555 */ "G_ZEXTLOAD\000"
5353 /* 2566 */ "G_INDEXED_LOAD\000"
5354 /* 2581 */ "G_LOAD\000"
5355 /* 2588 */ "G_VECREDUCE_FADD\000"
5356 /* 2605 */ "G_FADD\000"
5357 /* 2612 */ "G_VECREDUCE_SEQ_FADD\000"
5358 /* 2633 */ "G_STRICT_FADD\000"
5359 /* 2647 */ "G_ATOMICRMW_FADD\000"
5360 /* 2664 */ "G_VECREDUCE_ADD\000"
5361 /* 2680 */ "G_ADD\000"
5362 /* 2686 */ "G_PTR_ADD\000"
5363 /* 2696 */ "G_ATOMICRMW_ADD\000"
5364 /* 2712 */ "PseudoLA_TLS_GD\000"
5365 /* 2728 */ "PRELD\000"
5366 /* 2734 */ "XVLD\000"
5367 /* 2739 */ "FCVT_D_LD\000"
5368 /* 2749 */ "PseudoLA_TLS_LD\000"
5369 /* 2765 */ "G_ATOMICRMW_NAND\000"
5370 /* 2782 */ "G_VECREDUCE_AND\000"
5371 /* 2798 */ "G_AND\000"
5372 /* 2804 */ "G_ATOMICRMW_AND\000"
5373 /* 2820 */ "LIFETIME_END\000"
5374 /* 2833 */ "PseudoBRIND\000"
5375 /* 2845 */ "G_BRCOND\000"
5376 /* 2854 */ "G_ATOMICRMW_USUB_COND\000"
5377 /* 2876 */ "G_LLROUND\000"
5378 /* 2886 */ "G_LROUND\000"
5379 /* 2895 */ "G_INTRINSIC_ROUND\000"
5380 /* 2913 */ "G_INTRINSIC_FPTRUNC_ROUND\000"
5381 /* 2939 */ "LOAD_STACK_GUARD\000"
5382 /* 2956 */ "TLBRD\000"
5383 /* 2962 */ "GCSRRD\000"
5384 /* 2969 */ "XVREPLVE0_D\000"
5385 /* 2981 */ "XVINSVE0_D\000"
5386 /* 2992 */ "XVADDA_D\000"
5387 /* 3001 */ "XVFMINA_D\000"
5388 /* 3011 */ "X86SRA_D\000"
5389 /* 3020 */ "XVSRA_D\000"
5390 /* 3028 */ "XVFMAXA_D\000"
5391 /* 3038 */ "AMADD__DB_D\000"
5392 /* 3050 */ "AMAND__DB_D\000"
5393 /* 3062 */ "AMMIN__DB_D\000"
5394 /* 3074 */ "AMSWAP__DB_D\000"
5395 /* 3087 */ "AMOR__DB_D\000"
5396 /* 3098 */ "AMXOR__DB_D\000"
5397 /* 3110 */ "AMCAS__DB_D\000"
5398 /* 3122 */ "AMMAX__DB_D\000"
5399 /* 3134 */ "FSCALEB_D\000"
5400 /* 3144 */ "XVFLOGB_D\000"
5401 /* 3154 */ "X86SUB_D\000"
5402 /* 3163 */ "XVFSUB_D\000"
5403 /* 3172 */ "XVFMSUB_D\000"
5404 /* 3182 */ "XVFNMSUB_D\000"
5405 /* 3193 */ "XVMSUB_D\000"
5406 /* 3202 */ "XVSSUB_D\000"
5407 /* 3211 */ "XVSUB_D\000"
5408 /* 3219 */ "REVB_D\000"
5409 /* 3226 */ "X86SBC_D\000"
5410 /* 3235 */ "X86ADC_D\000"
5411 /* 3244 */ "X86DEC_D\000"
5412 /* 3253 */ "X86INC_D\000"
5413 /* 3262 */ "SC_D\000"
5414 /* 3267 */ "X86ADD_D\000"
5415 /* 3276 */ "XVFADD_D\000"
5416 /* 3285 */ "AMADD_D\000"
5417 /* 3293 */ "XVFMADD_D\000"
5418 /* 3303 */ "XVFNMADD_D\000"
5419 /* 3314 */ "XVMADD_D\000"
5420 /* 3323 */ "XVSADD_D\000"
5421 /* 3332 */ "XVADD_D\000"
5422 /* 3340 */ "FLD_D\000"
5423 /* 3346 */ "FCVT_LD_D\000"
5424 /* 3356 */ "X86AND_D\000"
5425 /* 3365 */ "AMAND_D\000"
5426 /* 3373 */ "XVPACKOD_D\000"
5427 /* 3384 */ "XVPICKOD_D\000"
5428 /* 3395 */ "XVMOD_D\000"
5429 /* 3403 */ "IOCSRRD_D\000"
5430 /* 3413 */ "XVABSD_D\000"
5431 /* 3422 */ "FCVT_UD_D\000"
5432 /* 3432 */ "XVFCMP_CLE_D\000"
5433 /* 3445 */ "FLDLE_D\000"
5434 /* 3453 */ "XVSLE_D\000"
5435 /* 3461 */ "XVFCMP_SLE_D\000"
5436 /* 3474 */ "ASRTLE_D\000"
5437 /* 3483 */ "FSTLE_D\000"
5438 /* 3491 */ "XVFCMP_CULE_D\000"
5439 /* 3505 */ "XVFCMP_SULE_D\000"
5440 /* 3519 */ "RDTIME_D\000"
5441 /* 3528 */ "XVFCMP_CNE_D\000"
5442 /* 3541 */ "XVFRINTRNE_D\000"
5443 /* 3554 */ "XVFCMP_SNE_D\000"
5444 /* 3567 */ "XVFCMP_CUNE_D\000"
5445 /* 3581 */ "XVFCMP_SUNE_D\000"
5446 /* 3595 */ "XVFRECIPE_D\000"
5447 /* 3607 */ "XVFRSQRTE_D\000"
5448 /* 3619 */ "XVPICKVE_D\000"
5449 /* 3630 */ "XVREPLVE_D\000"
5450 /* 3641 */ "XVFCMP_CAF_D\000"
5451 /* 3654 */ "XVFCMP_SAF_D\000"
5452 /* 3667 */ "XVSHUF_D\000"
5453 /* 3676 */ "FNEG_D\000"
5454 /* 3683 */ "XVNEG_D\000"
5455 /* 3691 */ "XVAVG_D\000"
5456 /* 3699 */ "MULH_D\000"
5457 /* 3706 */ "XVMUH_D\000"
5458 /* 3714 */ "REVH_D\000"
5459 /* 3721 */ "XVILVH_D\000"
5460 /* 3730 */ "ADDU12I_D\000"
5461 /* 3740 */ "LU32I_D\000"
5462 /* 3748 */ "LU52I_D\000"
5463 /* 3756 */ "XVSHUF4I_D\000"
5464 /* 3767 */ "ADDU16I_D\000"
5465 /* 3777 */ "X86SRAI_D\000"
5466 /* 3787 */ "XVSRAI_D\000"
5467 /* 3796 */ "ADDI_D\000"
5468 /* 3803 */ "XVSLEI_D\000"
5469 /* 3812 */ "XVREPL128VEI_D\000"
5470 /* 3827 */ "VREPLVEI_D\000"
5471 /* 3838 */ "X86RCLI_D\000"
5472 /* 3848 */ "XVHSELI_D\000"
5473 /* 3858 */ "X86SLLI_D\000"
5474 /* 3868 */ "XVSLLI_D\000"
5475 /* 3877 */ "PseudoXVREPLI_D\000"
5476 /* 3893 */ "PseudoVREPLI_D\000"
5477 /* 3908 */ "X86SRLI_D\000"
5478 /* 3918 */ "XVSRLI_D\000"
5479 /* 3927 */ "X86ROTLI_D\000"
5480 /* 3938 */ "PseudoLI_D\000"
5481 /* 3949 */ "XVPERMI_D\000"
5482 /* 3959 */ "XVMINI_D\000"
5483 /* 3968 */ "XVSEQI_D\000"
5484 /* 3977 */ "XVSRARI_D\000"
5485 /* 3987 */ "X86RCRI_D\000"
5486 /* 3997 */ "XVBITCLRI_D\000"
5487 /* 4009 */ "XVSRLRI_D\000"
5488 /* 4019 */ "X86ROTRI_D\000"
5489 /* 4030 */ "XVROTRI_D\000"
5490 /* 4040 */ "XVBITSETI_D\000"
5491 /* 4052 */ "XVSLTI_D\000"
5492 /* 4061 */ "XVBITREVI_D\000"
5493 /* 4073 */ "XVMAXI_D\000"
5494 /* 4082 */ "BYTEPICK_D\000"
5495 /* 4093 */ "BSTRPICK_D\000"
5496 /* 4104 */ "X86RCL_D\000"
5497 /* 4113 */ "LDL_D\000"
5498 /* 4119 */ "SCREL_D\000"
5499 /* 4127 */ "X86SLL_D\000"
5500 /* 4136 */ "XVSLL_D\000"
5501 /* 4144 */ "XVLDREPL_D\000"
5502 /* 4155 */ "X86SRL_D\000"
5503 /* 4164 */ "XVSRL_D\000"
5504 /* 4172 */ "ALSL_D\000"
5505 /* 4179 */ "X86ROTL_D\000"
5506 /* 4189 */ "STL_D\000"
5507 /* 4195 */ "X86MUL_D\000"
5508 /* 4204 */ "XVFMUL_D\000"
5509 /* 4213 */ "XVMUL_D\000"
5510 /* 4221 */ "XVILVL_D\000"
5511 /* 4230 */ "XVFTINTRNE_L_D\000"
5512 /* 4245 */ "XVFTINTRM_L_D\000"
5513 /* 4259 */ "XVFTINTRP_L_D\000"
5514 /* 4273 */ "XVFTINT_L_D\000"
5515 /* 4285 */ "XVFTINTRZ_L_D\000"
5516 /* 4299 */ "XVSTELM_D\000"
5517 /* 4309 */ "XVFRINTRM_D\000"
5518 /* 4321 */ "FCOPYSIGN_D\000"
5519 /* 4333 */ "XVFMIN_D\000"
5520 /* 4342 */ "AMMIN_D\000"
5521 /* 4350 */ "XVMIN_D\000"
5522 /* 4358 */ "XVFCMP_CUN_D\000"
5523 /* 4371 */ "XVFCMP_SUN_D\000"
5524 /* 4384 */ "XVCLO_D\000"
5525 /* 4392 */ "CTO_D\000"
5526 /* 4398 */ "AMSWAP_D\000"
5527 /* 4407 */ "XVFRECIP_D\000"
5528 /* 4418 */ "XVFRINTRP_D\000"
5529 /* 4430 */ "LLACQ_D\000"
5530 /* 4438 */ "XVFCMP_CEQ_D\000"
5531 /* 4451 */ "XVSEQ_D\000"
5532 /* 4459 */ "XVFCMP_SEQ_D\000"
5533 /* 4472 */ "XVFCMP_CUEQ_D\000"
5534 /* 4486 */ "XVFCMP_SUEQ_D\000"
5535 /* 4500 */ "XVSUBWOD_Q_D\000"
5536 /* 4513 */ "XVMADDWOD_Q_D\000"
5537 /* 4527 */ "XVADDWOD_Q_D\000"
5538 /* 4540 */ "XVMULWOD_Q_D\000"
5539 /* 4553 */ "XVEXTH_Q_D\000"
5540 /* 4564 */ "XVEXTL_Q_D\000"
5541 /* 4575 */ "XVSUBWEV_Q_D\000"
5542 /* 4588 */ "XVMADDWEV_Q_D\000"
5543 /* 4602 */ "XVADDWEV_Q_D\000"
5544 /* 4615 */ "XVMULWEV_Q_D\000"
5545 /* 4628 */ "XVHSUBW_Q_D\000"
5546 /* 4640 */ "XVHADDW_Q_D\000"
5547 /* 4652 */ "XVSRAR_D\000"
5548 /* 4661 */ "X86RCR_D\000"
5549 /* 4670 */ "LDR_D\000"
5550 /* 4676 */ "MOVGR2FR_D\000"
5551 /* 4687 */ "XVPICKVE2GR_D\000"
5552 /* 4701 */ "MOVFR2GR_D\000"
5553 /* 4712 */ "XVAVGR_D\000"
5554 /* 4721 */ "XVBITCLR_D\000"
5555 /* 4732 */ "XVSRLR_D\000"
5556 /* 4741 */ "X86OR_D\000"
5557 /* 4749 */ "XVFCMP_COR_D\000"
5558 /* 4762 */ "AMOR_D\000"
5559 /* 4769 */ "XVFCMP_SOR_D\000"
5560 /* 4782 */ "X86XOR_D\000"
5561 /* 4791 */ "AMXOR_D\000"
5562 /* 4799 */ "X86ROTR_D\000"
5563 /* 4809 */ "XVROTR_D\000"
5564 /* 4818 */ "LDPTR_D\000"
5565 /* 4826 */ "STPTR_D\000"
5566 /* 4834 */ "STR_D\000"
5567 /* 4840 */ "XVREPLGR2VR_D\000"
5568 /* 4854 */ "XVINSGR2VR_D\000"
5569 /* 4867 */ "IOCSRWR_D\000"
5570 /* 4877 */ "AMCAS_D\000"
5571 /* 4885 */ "FABS_D\000"
5572 /* 4892 */ "BSTRINS_D\000"
5573 /* 4902 */ "XVEXTRINS_D\000"
5574 /* 4914 */ "XVFCLASS_D\000"
5575 /* 4925 */ "XVFCVT_S_D\000"
5576 /* 4936 */ "XVSAT_D\000"
5577 /* 4944 */ "XVBITSET_D\000"
5578 /* 4955 */ "FLDGT_D\000"
5579 /* 4963 */ "ASRTGT_D\000"
5580 /* 4972 */ "FSTGT_D\000"
5581 /* 4980 */ "XVFCMP_CLT_D\000"
5582 /* 4993 */ "XVSLT_D\000"
5583 /* 5001 */ "XVFCMP_SLT_D\000"
5584 /* 5014 */ "XVFCMP_CULT_D\000"
5585 /* 5028 */ "XVFCMP_SULT_D\000"
5586 /* 5042 */ "XVPCNT_D\000"
5587 /* 5051 */ "XVFRINT_D\000"
5588 /* 5061 */ "XVFSQRT_D\000"
5589 /* 5071 */ "XVFRSQRT_D\000"
5590 /* 5082 */ "FST_D\000"
5591 /* 5088 */ "XVMADDWOD_Q_DU_D\000"
5592 /* 5105 */ "XVADDWOD_Q_DU_D\000"
5593 /* 5121 */ "XVMULWOD_Q_DU_D\000"
5594 /* 5137 */ "XVMADDWEV_Q_DU_D\000"
5595 /* 5154 */ "XVADDWEV_Q_DU_D\000"
5596 /* 5170 */ "XVMULWEV_Q_DU_D\000"
5597 /* 5186 */ "XVFTINT_LU_D\000"
5598 /* 5199 */ "XVFTINTRZ_LU_D\000"
5599 /* 5214 */ "XVSSRANI_WU_D\000"
5600 /* 5228 */ "XVSSRLNI_WU_D\000"
5601 /* 5242 */ "XVSSRARNI_WU_D\000"
5602 /* 5257 */ "XVSSRLRNI_WU_D\000"
5603 /* 5272 */ "XVSSRAN_WU_D\000"
5604 /* 5285 */ "XVSSRLN_WU_D\000"
5605 /* 5298 */ "XVSSRARN_WU_D\000"
5606 /* 5312 */ "XVSSRLRN_WU_D\000"
5607 /* 5326 */ "XVPACKEV_D\000"
5608 /* 5337 */ "XVPICKEV_D\000"
5609 /* 5348 */ "XVBITREV_D\000"
5610 /* 5359 */ "XVFDIV_D\000"
5611 /* 5368 */ "XVDIV_D\000"
5612 /* 5376 */ "XVSIGNCOV_D\000"
5613 /* 5388 */ "FMOV_D\000"
5614 /* 5395 */ "ARMMOV_D\000"
5615 /* 5404 */ "XVFTINTRNE_W_D\000"
5616 /* 5419 */ "XVSSRANI_W_D\000"
5617 /* 5432 */ "XVSRANI_W_D\000"
5618 /* 5444 */ "XVSSRLNI_W_D\000"
5619 /* 5457 */ "XVSRLNI_W_D\000"
5620 /* 5469 */ "XVSSRARNI_W_D\000"
5621 /* 5483 */ "XVSRARNI_W_D\000"
5622 /* 5496 */ "XVSSRLRNI_W_D\000"
5623 /* 5510 */ "XVSRLRNI_W_D\000"
5624 /* 5523 */ "XVFTINTRM_W_D\000"
5625 /* 5537 */ "XVSSRAN_W_D\000"
5626 /* 5549 */ "XVSRAN_W_D\000"
5627 /* 5560 */ "XVSSRLN_W_D\000"
5628 /* 5572 */ "XVSRLN_W_D\000"
5629 /* 5583 */ "XVSSRARN_W_D\000"
5630 /* 5596 */ "XVSRARN_W_D\000"
5631 /* 5608 */ "XVSSRLRN_W_D\000"
5632 /* 5621 */ "XVSRLRN_W_D\000"
5633 /* 5633 */ "XVFTINTRP_W_D\000"
5634 /* 5647 */ "XVFTINT_W_D\000"
5635 /* 5659 */ "XVFTINTRZ_W_D\000"
5636 /* 5673 */ "XVFMAX_D\000"
5637 /* 5682 */ "AMMAX_D\000"
5638 /* 5690 */ "XVMAX_D\000"
5639 /* 5698 */ "FLDX_D\000"
5640 /* 5705 */ "FSTX_D\000"
5641 /* 5712 */ "PseudoXVBZ_D\000"
5642 /* 5725 */ "PseudoVBZ_D\000"
5643 /* 5737 */ "XVSETALLNEZ_D\000"
5644 /* 5751 */ "XVCLZ_D\000"
5645 /* 5759 */ "PseudoXVBNZ_D\000"
5646 /* 5773 */ "PseudoVBNZ_D\000"
5647 /* 5786 */ "XVSETANYEQZ_D\000"
5648 /* 5800 */ "XVFRINTRZ_D\000"
5649 /* 5812 */ "CTZ_D\000"
5650 /* 5818 */ "PseudoXVMSKLTZ_D\000"
5651 /* 5835 */ "PseudoVMSKLTZ_D\000"
5652 /* 5851 */ "PseudoAddTPRel_D\000"
5653 /* 5868 */ "PseudoAtomicStoreD\000"
5654 /* 5887 */ "FSEL_xD\000"
5655 /* 5895 */ "PSEUDO_PROBE\000"
5656 /* 5908 */ "G_SSUBE\000"
5657 /* 5916 */ "G_USUBE\000"
5658 /* 5924 */ "G_FENCE\000"
5659 /* 5932 */ "ARITH_FENCE\000"
5660 /* 5944 */ "REG_SEQUENCE\000"
5661 /* 5957 */ "G_SADDE\000"
5662 /* 5965 */ "G_UADDE\000"
5663 /* 5973 */ "G_GET_FPMODE\000"
5664 /* 5986 */ "G_RESET_FPMODE\000"
5665 /* 6001 */ "G_SET_FPMODE\000"
5666 /* 6014 */ "G_FMINNUM_IEEE\000"
5667 /* 6029 */ "G_FMAXNUM_IEEE\000"
5668 /* 6044 */ "BGE\000"
5669 /* 6048 */ "PseudoLA_TLS_DESC_LARGE\000"
5670 /* 6072 */ "PseudoLA_TLS_GD_LARGE\000"
5671 /* 6094 */ "PseudoLA_TLS_LD_LARGE\000"
5672 /* 6116 */ "PseudoLA_TLS_IE_LARGE\000"
5673 /* 6138 */ "PseudoLA_PCREL_LARGE\000"
5674 /* 6159 */ "PseudoTAIL_LARGE\000"
5675 /* 6176 */ "PseudoCALL_LARGE\000"
5676 /* 6193 */ "PseudoLA_ABS_LARGE\000"
5677 /* 6212 */ "PseudoLA_GOT_LARGE\000"
5678 /* 6231 */ "PseudoLA_TLS_IE\000"
5679 /* 6247 */ "G_VSCALE\000"
5680 /* 6256 */ "G_JUMP_TABLE\000"
5681 /* 6269 */ "IDLE\000"
5682 /* 6274 */ "BUNDLE\000"
5683 /* 6281 */ "PseudoLA_TLS_LE\000"
5684 /* 6297 */ "BNE\000"
5685 /* 6301 */ "G_MEMCPY_INLINE\000"
5686 /* 6317 */ "SETX86LOOPNE\000"
5687 /* 6330 */ "LOCAL_ESCAPE\000"
5688 /* 6343 */ "SETX86LOOPE\000"
5689 /* 6355 */ "G_STACKRESTORE\000"
5690 /* 6370 */ "G_INDEXED_STORE\000"
5691 /* 6386 */ "G_STORE\000"
5692 /* 6394 */ "SET_CFR_FALSE\000"
5693 /* 6408 */ "G_BITREVERSE\000"
5694 /* 6421 */ "FAKE_USE\000"
5695 /* 6430 */ "LDPTE\000"
5696 /* 6436 */ "DBG_VALUE\000"
5697 /* 6446 */ "G_GLOBAL_VALUE\000"
5698 /* 6461 */ "G_PTRAUTH_GLOBAL_VALUE\000"
5699 /* 6484 */ "CONVERGENCECTRL_GLUE\000"
5700 /* 6505 */ "SET_CFR_TRUE\000"
5701 /* 6518 */ "G_STACKSAVE\000"
5702 /* 6530 */ "G_MEMMOVE\000"
5703 /* 6540 */ "ARMMOVE\000"
5704 /* 6548 */ "G_FREEZE\000"
5705 /* 6557 */ "G_FCANONICALIZE\000"
5706 /* 6573 */ "MOVGR2CF\000"
5707 /* 6582 */ "G_CTLZ_ZERO_UNDEF\000"
5708 /* 6600 */ "G_CTTZ_ZERO_UNDEF\000"
5709 /* 6618 */ "INIT_UNDEF\000"
5710 /* 6629 */ "G_IMPLICIT_DEF\000"
5711 /* 6644 */ "DBG_INSTR_REF\000"
5712 /* 6658 */ "X86MFFLAG\000"
5713 /* 6668 */ "ARMMFFLAG\000"
5714 /* 6678 */ "X86MTFLAG\000"
5715 /* 6688 */ "ARMMTFLAG\000"
5716 /* 6698 */ "X86SETTAG\000"
5717 /* 6708 */ "G_FNEG\000"
5718 /* 6715 */ "EXTRACT_SUBREG\000"
5719 /* 6730 */ "INSERT_SUBREG\000"
5720 /* 6744 */ "G_SEXT_INREG\000"
5721 /* 6757 */ "SUBREG_TO_REG\000"
5722 /* 6771 */ "CPUCFG\000"
5723 /* 6778 */ "G_ATOMIC_CMPXCHG\000"
5724 /* 6795 */ "GCSRXCHG\000"
5725 /* 6804 */ "G_ATOMICRMW_XCHG\000"
5726 /* 6821 */ "G_FLOG\000"
5727 /* 6828 */ "G_VAARG\000"
5728 /* 6836 */ "PREALLOCATED_ARG\000"
5729 /* 6853 */ "REVB_2H\000"
5730 /* 6861 */ "REVB_4H\000"
5731 /* 6869 */ "TLBSRCH\000"
5732 /* 6877 */ "G_PREFETCH\000"
5733 /* 6888 */ "G_SMULH\000"
5734 /* 6896 */ "G_UMULH\000"
5735 /* 6904 */ "G_FTANH\000"
5736 /* 6912 */ "G_FSINH\000"
5737 /* 6920 */ "G_FCOSH\000"
5738 /* 6928 */ "GTLBFLUSH\000"
5739 /* 6938 */ "XVREPLVE0_H\000"
5740 /* 6950 */ "XVADDA_H\000"
5741 /* 6959 */ "X86SRA_H\000"
5742 /* 6968 */ "XVSRA_H\000"
5743 /* 6976 */ "AMADD__DB_H\000"
5744 /* 6988 */ "AMSWAP__DB_H\000"
5745 /* 7001 */ "AMCAS__DB_H\000"
5746 /* 7013 */ "X86SUB_H\000"
5747 /* 7022 */ "XVMSUB_H\000"
5748 /* 7031 */ "XVSSUB_H\000"
5749 /* 7040 */ "XVSUB_H\000"
5750 /* 7048 */ "XVSSRANI_B_H\000"
5751 /* 7061 */ "XVSRANI_B_H\000"
5752 /* 7073 */ "XVSSRLNI_B_H\000"
5753 /* 7086 */ "XVSRLNI_B_H\000"
5754 /* 7098 */ "XVSSRARNI_B_H\000"
5755 /* 7112 */ "XVSRARNI_B_H\000"
5756 /* 7125 */ "XVSSRLRNI_B_H\000"
5757 /* 7139 */ "XVSRLRNI_B_H\000"
5758 /* 7152 */ "XVSSRAN_B_H\000"
5759 /* 7164 */ "XVSRAN_B_H\000"
5760 /* 7175 */ "XVSSRLN_B_H\000"
5761 /* 7187 */ "XVSRLN_B_H\000"
5762 /* 7198 */ "XVSSRARN_B_H\000"
5763 /* 7211 */ "XVSRARN_B_H\000"
5764 /* 7223 */ "XVSSRLRN_B_H\000"
5765 /* 7236 */ "XVSRLRN_B_H\000"
5766 /* 7248 */ "X86SBC_H\000"
5767 /* 7257 */ "X86ADC_H\000"
5768 /* 7266 */ "X86DEC_H\000"
5769 /* 7275 */ "X86INC_H\000"
5770 /* 7284 */ "X86ADD_H\000"
5771 /* 7293 */ "AMADD_H\000"
5772 /* 7301 */ "XVMADD_H\000"
5773 /* 7310 */ "XVSADD_H\000"
5774 /* 7319 */ "XVADD_H\000"
5775 /* 7327 */ "LD_H\000"
5776 /* 7332 */ "X86AND_H\000"
5777 /* 7341 */ "XVPACKOD_H\000"
5778 /* 7352 */ "XVPICKOD_H\000"
5779 /* 7363 */ "XVMOD_H\000"
5780 /* 7371 */ "IOCSRRD_H\000"
5781 /* 7381 */ "XVABSD_H\000"
5782 /* 7390 */ "VEXT2XV_D_H\000"
5783 /* 7402 */ "LDLE_H\000"
5784 /* 7409 */ "XVSLE_H\000"
5785 /* 7417 */ "STLE_H\000"
5786 /* 7424 */ "XVREPLVE_H\000"
5787 /* 7435 */ "XVSHUF_H\000"
5788 /* 7444 */ "XVNEG_H\000"
5789 /* 7452 */ "XVAVG_H\000"
5790 /* 7460 */ "XVMUH_H\000"
5791 /* 7468 */ "XVILVH_H\000"
5792 /* 7477 */ "XVSHUF4I_H\000"
5793 /* 7488 */ "X86SRAI_H\000"
5794 /* 7498 */ "XVSRAI_H\000"
5795 /* 7507 */ "XVSLEI_H\000"
5796 /* 7516 */ "XVREPL128VEI_H\000"
5797 /* 7531 */ "VREPLVEI_H\000"
5798 /* 7542 */ "X86RCLI_H\000"
5799 /* 7552 */ "X86SLLI_H\000"
5800 /* 7562 */ "XVSLLI_H\000"
5801 /* 7571 */ "PseudoXVREPLI_H\000"
5802 /* 7587 */ "PseudoVREPLI_H\000"
5803 /* 7602 */ "X86SRLI_H\000"
5804 /* 7612 */ "XVSRLI_H\000"
5805 /* 7621 */ "X86ROTLI_H\000"
5806 /* 7632 */ "XVMINI_H\000"
5807 /* 7641 */ "XVFRSTPI_H\000"
5808 /* 7652 */ "XVSEQI_H\000"
5809 /* 7661 */ "XVSRARI_H\000"
5810 /* 7671 */ "X86RCRI_H\000"
5811 /* 7681 */ "XVBITCLRI_H\000"
5812 /* 7693 */ "XVSRLRI_H\000"
5813 /* 7703 */ "X86ROTRI_H\000"
5814 /* 7714 */ "XVROTRI_H\000"
5815 /* 7724 */ "XVBITSETI_H\000"
5816 /* 7736 */ "XVSLTI_H\000"
5817 /* 7745 */ "XVBITREVI_H\000"
5818 /* 7757 */ "XVMAXI_H\000"
5819 /* 7766 */ "X86RCL_H\000"
5820 /* 7775 */ "X86SLL_H\000"
5821 /* 7784 */ "XVSLL_H\000"
5822 /* 7792 */ "XVLDREPL_H\000"
5823 /* 7803 */ "X86SRL_H\000"
5824 /* 7812 */ "XVSRL_H\000"
5825 /* 7820 */ "X86ROTL_H\000"
5826 /* 7830 */ "X86MUL_H\000"
5827 /* 7839 */ "XVMUL_H\000"
5828 /* 7847 */ "XVILVL_H\000"
5829 /* 7856 */ "XVSTELM_H\000"
5830 /* 7866 */ "XVMIN_H\000"
5831 /* 7874 */ "XVCLO_H\000"
5832 /* 7882 */ "AMSWAP_H\000"
5833 /* 7891 */ "XVFRSTP_H\000"
5834 /* 7901 */ "XVSEQ_H\000"
5835 /* 7909 */ "XVSRAR_H\000"
5836 /* 7918 */ "X86RCR_H\000"
5837 /* 7927 */ "VPICKVE2GR_H\000"
5838 /* 7940 */ "XVAVGR_H\000"
5839 /* 7949 */ "XVBITCLR_H\000"
5840 /* 7960 */ "XVSRLR_H\000"
5841 /* 7969 */ "X86OR_H\000"
5842 /* 7977 */ "X86XOR_H\000"
5843 /* 7986 */ "X86ROTR_H\000"
5844 /* 7996 */ "XVROTR_H\000"
5845 /* 8005 */ "XVREPLGR2VR_H\000"
5846 /* 8019 */ "PseudoXVINSGR2VR_H\000"
5847 /* 8038 */ "IOCSRWR_H\000"
5848 /* 8048 */ "AMCAS_H\000"
5849 /* 8056 */ "XVEXTRINS_H\000"
5850 /* 8068 */ "XVFCVTH_S_H\000"
5851 /* 8080 */ "XVFCVTL_S_H\000"
5852 /* 8092 */ "XVSAT_H\000"
5853 /* 8100 */ "XVBITSET_H\000"
5854 /* 8111 */ "LDGT_H\000"
5855 /* 8118 */ "STGT_H\000"
5856 /* 8125 */ "XVSLT_H\000"
5857 /* 8133 */ "XVPCNT_H\000"
5858 /* 8142 */ "ST_H\000"
5859 /* 8147 */ "XVSSRANI_BU_H\000"
5860 /* 8161 */ "XVSSRLNI_BU_H\000"
5861 /* 8175 */ "XVSSRARNI_BU_H\000"
5862 /* 8190 */ "XVSSRLRNI_BU_H\000"
5863 /* 8205 */ "XVSSRAN_BU_H\000"
5864 /* 8218 */ "XVSSRLN_BU_H\000"
5865 /* 8231 */ "XVSSRARN_BU_H\000"
5866 /* 8245 */ "XVSSRLRN_BU_H\000"
5867 /* 8259 */ "XVMADDWOD_W_HU_H\000"
5868 /* 8276 */ "XVADDWOD_W_HU_H\000"
5869 /* 8292 */ "XVMULWOD_W_HU_H\000"
5870 /* 8308 */ "XVMADDWEV_W_HU_H\000"
5871 /* 8325 */ "XVADDWEV_W_HU_H\000"
5872 /* 8341 */ "XVMULWEV_W_HU_H\000"
5873 /* 8357 */ "XVPACKEV_H\000"
5874 /* 8368 */ "XVPICKEV_H\000"
5875 /* 8379 */ "XVBITREV_H\000"
5876 /* 8390 */ "XVDIV_H\000"
5877 /* 8398 */ "XVSIGNCOV_H\000"
5878 /* 8410 */ "XVSUBWOD_W_H\000"
5879 /* 8423 */ "XVMADDWOD_W_H\000"
5880 /* 8437 */ "XVADDWOD_W_H\000"
5881 /* 8450 */ "XVMULWOD_W_H\000"
5882 /* 8463 */ "XVEXTH_W_H\000"
5883 /* 8474 */ "XVSLLWIL_W_H\000"
5884 /* 8487 */ "EXT_W_H\000"
5885 /* 8495 */ "XVSUBWEV_W_H\000"
5886 /* 8508 */ "XVMADDWEV_W_H\000"
5887 /* 8522 */ "XVADDWEV_W_H\000"
5888 /* 8535 */ "XVMULWEV_W_H\000"
5889 /* 8548 */ "VEXT2XV_W_H\000"
5890 /* 8560 */ "XVHSUBW_W_H\000"
5891 /* 8572 */ "XVHADDW_W_H\000"
5892 /* 8584 */ "XVMAX_H\000"
5893 /* 8592 */ "LDX_H\000"
5894 /* 8598 */ "STX_H\000"
5895 /* 8604 */ "PseudoXVBZ_H\000"
5896 /* 8617 */ "PseudoVBZ_H\000"
5897 /* 8629 */ "XVSETALLNEZ_H\000"
5898 /* 8643 */ "XVCLZ_H\000"
5899 /* 8651 */ "PseudoXVBNZ_H\000"
5900 /* 8665 */ "PseudoVBNZ_H\000"
5901 /* 8678 */ "XVSETANYEQZ_H\000"
5902 /* 8692 */ "PseudoXVMSKLTZ_H\000"
5903 /* 8709 */ "PseudoVMSKLTZ_H\000"
5904 /* 8725 */ "PCALAU12I\000"
5905 /* 8735 */ "PCADDU12I\000"
5906 /* 8745 */ "PCADDU18I\000"
5907 /* 8755 */ "PCADDI\000"
5908 /* 8762 */ "XVLDI\000"
5909 /* 8768 */ "ANDI\000"
5910 /* 8773 */ "DBG_PHI\000"
5911 /* 8781 */ "XORI\000"
5912 /* 8786 */ "G_FPTOSI\000"
5913 /* 8795 */ "SLTI\000"
5914 /* 8800 */ "G_FPTOUI\000"
5915 /* 8809 */ "SLTUI\000"
5916 /* 8815 */ "G_FPOWI\000"
5917 /* 8823 */ "SETX86J\000"
5918 /* 8831 */ "SETARMJ\000"
5919 /* 8839 */ "BREAK\000"
5920 /* 8845 */ "G_PTRMASK\000"
5921 /* 8855 */ "BL\000"
5922 /* 8858 */ "DBCL\000"
5923 /* 8863 */ "HVCL\000"
5924 /* 8868 */ "GC_LABEL\000"
5925 /* 8877 */ "DBG_LABEL\000"
5926 /* 8887 */ "EH_LABEL\000"
5927 /* 8896 */ "ANNOTATION_LABEL\000"
5928 /* 8913 */ "ICALL_BRANCH_FUNNEL\000"
5929 /* 8933 */ "PseudoLA_PCREL\000"
5930 /* 8948 */ "G_FSHL\000"
5931 /* 8955 */ "G_SHL\000"
5932 /* 8961 */ "PseudoB_TAIL\000"
5933 /* 8974 */ "PseudoJIRL_TAIL\000"
5934 /* 8990 */ "PseudoTAIL\000"
5935 /* 9001 */ "G_FCEIL\000"
5936 /* 9009 */ "SYSCALL\000"
5937 /* 9017 */ "PseudoDESC_CALL\000"
5938 /* 9033 */ "PATCHABLE_TAIL_CALL\000"
5939 /* 9053 */ "PseudoJIRL_CALL\000"
5940 /* 9069 */ "PATCHABLE_TYPED_EVENT_CALL\000"
5941 /* 9096 */ "PATCHABLE_EVENT_CALL\000"
5942 /* 9117 */ "FENTRY_CALL\000"
5943 /* 9129 */ "PseudoCALL\000"
5944 /* 9140 */ "TLBFILL\000"
5945 /* 9148 */ "KILL\000"
5946 /* 9153 */ "G_CONSTANT_POOL\000"
5947 /* 9169 */ "JIRL\000"
5948 /* 9174 */ "G_ROTL\000"
5949 /* 9181 */ "G_VECREDUCE_FMUL\000"
5950 /* 9198 */ "G_FMUL\000"
5951 /* 9205 */ "G_VECREDUCE_SEQ_FMUL\000"
5952 /* 9226 */ "G_STRICT_FMUL\000"
5953 /* 9240 */ "G_VECREDUCE_MUL\000"
5954 /* 9256 */ "G_MUL\000"
5955 /* 9262 */ "XVFFINT_D_L\000"
5956 /* 9274 */ "XVFFINT_S_L\000"
5957 /* 9286 */ "G_FREM\000"
5958 /* 9293 */ "G_STRICT_FREM\000"
5959 /* 9307 */ "G_SREM\000"
5960 /* 9314 */ "G_UREM\000"
5961 /* 9321 */ "G_SDIVREM\000"
5962 /* 9331 */ "G_UDIVREM\000"
5963 /* 9341 */ "INLINEASM\000"
5964 /* 9351 */ "X86CLRTM\000"
5965 /* 9360 */ "X86SETTM\000"
5966 /* 9369 */ "PseudoTAIL_MEDIUM\000"
5967 /* 9387 */ "PseudoCALL_MEDIUM\000"
5968 /* 9405 */ "G_VECREDUCE_FMINIMUM\000"
5969 /* 9426 */ "G_FMINIMUM\000"
5970 /* 9437 */ "G_ATOMICRMW_FMINIMUM\000"
5971 /* 9458 */ "G_VECREDUCE_FMAXIMUM\000"
5972 /* 9479 */ "G_FMAXIMUM\000"
5973 /* 9490 */ "G_ATOMICRMW_FMAXIMUM\000"
5974 /* 9511 */ "G_FMINIMUMNUM\000"
5975 /* 9525 */ "G_FMAXIMUMNUM\000"
5976 /* 9539 */ "G_FMINNUM\000"
5977 /* 9549 */ "G_FMAXNUM\000"
5978 /* 9559 */ "G_FATAN\000"
5979 /* 9567 */ "G_FTAN\000"
5980 /* 9574 */ "ANDN\000"
5981 /* 9579 */ "G_INTRINSIC_ROUNDEVEN\000"
5982 /* 9601 */ "G_ASSERT_ALIGN\000"
5983 /* 9616 */ "G_FCOPYSIGN\000"
5984 /* 9628 */ "G_VECREDUCE_FMIN\000"
5985 /* 9645 */ "G_ATOMICRMW_FMIN\000"
5986 /* 9662 */ "G_VECREDUCE_SMIN\000"
5987 /* 9679 */ "G_SMIN\000"
5988 /* 9686 */ "G_VECREDUCE_UMIN\000"
5989 /* 9703 */ "G_UMIN\000"
5990 /* 9710 */ "G_ATOMICRMW_UMIN\000"
5991 /* 9727 */ "G_ATOMICRMW_MIN\000"
5992 /* 9743 */ "G_FASIN\000"
5993 /* 9751 */ "G_FSIN\000"
5994 /* 9758 */ "CFI_INSTRUCTION\000"
5995 /* 9774 */ "ORN\000"
5996 /* 9778 */ "ERTN\000"
5997 /* 9783 */ "ADJCALLSTACKDOWN\000"
5998 /* 9800 */ "G_SSUBO\000"
5999 /* 9808 */ "G_USUBO\000"
6000 /* 9816 */ "G_SADDO\000"
6001 /* 9824 */ "G_UADDO\000"
6002 /* 9832 */ "JUMP_TABLE_DEBUG_INFO\000"
6003 /* 9854 */ "G_SMULO\000"
6004 /* 9862 */ "G_UMULO\000"
6005 /* 9870 */ "G_BZERO\000"
6006 /* 9878 */ "STACKMAP\000"
6007 /* 9887 */ "G_DEBUGTRAP\000"
6008 /* 9899 */ "G_UBSANTRAP\000"
6009 /* 9911 */ "G_TRAP\000"
6010 /* 9918 */ "G_ATOMICRMW_UDEC_WRAP\000"
6011 /* 9940 */ "G_ATOMICRMW_UINC_WRAP\000"
6012 /* 9962 */ "G_BSWAP\000"
6013 /* 9970 */ "G_SITOFP\000"
6014 /* 9979 */ "G_UITOFP\000"
6015 /* 9988 */ "G_FCMP\000"
6016 /* 9995 */ "G_ICMP\000"
6017 /* 10002 */ "G_SCMP\000"
6018 /* 10009 */ "G_UCMP\000"
6019 /* 10016 */ "PseudoUNIMP\000"
6020 /* 10028 */ "CACOP\000"
6021 /* 10034 */ "CONVERGENCECTRL_LOOP\000"
6022 /* 10055 */ "G_CTPOP\000"
6023 /* 10063 */ "PseudoCTPOP\000"
6024 /* 10075 */ "X86DECTOP\000"
6025 /* 10085 */ "X86INCTOP\000"
6026 /* 10095 */ "X86MFTOP\000"
6027 /* 10104 */ "X86MTTOP\000"
6028 /* 10113 */ "PATCHABLE_OP\000"
6029 /* 10126 */ "FAULTING_OP\000"
6030 /* 10138 */ "ADJCALLSTACKUP\000"
6031 /* 10153 */ "PREALLOCATED_SETUP\000"
6032 /* 10172 */ "G_FLDEXP\000"
6033 /* 10181 */ "G_STRICT_FLDEXP\000"
6034 /* 10197 */ "G_FEXP\000"
6035 /* 10204 */ "G_FFREXP\000"
6036 /* 10213 */ "BEQ\000"
6037 /* 10217 */ "XVREPLVE0_Q\000"
6038 /* 10229 */ "XVSUB_Q\000"
6039 /* 10237 */ "SC_Q\000"
6040 /* 10242 */ "XVADD_Q\000"
6041 /* 10250 */ "XVSSRANI_D_Q\000"
6042 /* 10263 */ "XVSRANI_D_Q\000"
6043 /* 10275 */ "XVSSRLNI_D_Q\000"
6044 /* 10288 */ "XVSRLNI_D_Q\000"
6045 /* 10300 */ "XVSSRARNI_D_Q\000"
6046 /* 10314 */ "XVSRARNI_D_Q\000"
6047 /* 10327 */ "XVSSRLRNI_D_Q\000"
6048 /* 10341 */ "XVSRLRNI_D_Q\000"
6049 /* 10354 */ "XVPERMI_Q\000"
6050 /* 10364 */ "XVSSRANI_DU_Q\000"
6051 /* 10378 */ "XVSSRLNI_DU_Q\000"
6052 /* 10392 */ "XVSSRARNI_DU_Q\000"
6053 /* 10407 */ "XVSSRLRNI_DU_Q\000"
6054 /* 10422 */ "DBAR\000"
6055 /* 10427 */ "IBAR\000"
6056 /* 10432 */ "G_BR\000"
6057 /* 10437 */ "INLINEASM_BR\000"
6058 /* 10450 */ "PseudoBR\000"
6059 /* 10459 */ "MOVGR2SCR\000"
6060 /* 10469 */ "G_BLOCK_ADDR\000"
6061 /* 10482 */ "MEMBARRIER\000"
6062 /* 10493 */ "G_CONSTANT_FOLD_BARRIER\000"
6063 /* 10517 */ "PATCHABLE_FUNCTION_ENTER\000"
6064 /* 10542 */ "G_READCYCLECOUNTER\000"
6065 /* 10561 */ "G_READSTEADYCOUNTER\000"
6066 /* 10581 */ "G_READ_REGISTER\000"
6067 /* 10597 */ "G_WRITE_REGISTER\000"
6068 /* 10614 */ "PseudoLD_CFR\000"
6069 /* 10627 */ "PseudoST_CFR\000"
6070 /* 10640 */ "PseudoCopyCFR\000"
6071 /* 10654 */ "MOVCF2GR\000"
6072 /* 10663 */ "MOVSCR2GR\000"
6073 /* 10673 */ "MOVFCSR2GR\000"
6074 /* 10684 */ "G_ASHR\000"
6075 /* 10691 */ "G_FSHR\000"
6076 /* 10698 */ "G_LSHR\000"
6077 /* 10705 */ "LDDIR\000"
6078 /* 10711 */ "TLBCLR\000"
6079 /* 10718 */ "CONVERGENCECTRL_ANCHOR\000"
6080 /* 10741 */ "NOR\000"
6081 /* 10745 */ "G_FFLOOR\000"
6082 /* 10754 */ "G_EXTRACT_SUBVECTOR\000"
6083 /* 10774 */ "G_INSERT_SUBVECTOR\000"
6084 /* 10793 */ "G_BUILD_VECTOR\000"
6085 /* 10808 */ "G_SHUFFLE_VECTOR\000"
6086 /* 10825 */ "G_STEP_VECTOR\000"
6087 /* 10839 */ "G_SPLAT_VECTOR\000"
6088 /* 10854 */ "G_VECREDUCE_XOR\000"
6089 /* 10870 */ "G_XOR\000"
6090 /* 10876 */ "G_ATOMICRMW_XOR\000"
6091 /* 10892 */ "G_VECREDUCE_OR\000"
6092 /* 10907 */ "G_OR\000"
6093 /* 10912 */ "G_ATOMICRMW_OR\000"
6094 /* 10927 */ "Select_GPR_Using_CC_GPR\000"
6095 /* 10951 */ "MOVGR2FCSR\000"
6096 /* 10962 */ "RDFCSR\000"
6097 /* 10969 */ "WRFCSR\000"
6098 /* 10976 */ "G_ROTR\000"
6099 /* 10983 */ "G_INTTOPTR\000"
6100 /* 10994 */ "TLBWR\000"
6101 /* 11000 */ "GCSRWR\000"
6102 /* 11007 */ "G_FABS\000"
6103 /* 11014 */ "PseudoLA_ABS\000"
6104 /* 11027 */ "G_ABS\000"
6105 /* 11033 */ "G_ABDS\000"
6106 /* 11040 */ "G_UNMERGE_VALUES\000"
6107 /* 11057 */ "G_MERGE_VALUES\000"
6108 /* 11072 */ "G_FACOS\000"
6109 /* 11080 */ "G_FCOS\000"
6110 /* 11087 */ "G_FSINCOS\000"
6111 /* 11097 */ "G_CONCAT_VECTORS\000"
6112 /* 11114 */ "COPY_TO_REGCLASS\000"
6113 /* 11131 */ "G_IS_FPCLASS\000"
6114 /* 11144 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\000"
6115 /* 11174 */ "G_VECTOR_COMPRESS\000"
6116 /* 11192 */ "G_INTRINSIC_W_SIDE_EFFECTS\000"
6117 /* 11219 */ "G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS\000"
6118 /* 11257 */ "XVFMINA_S\000"
6119 /* 11267 */ "XVFMAXA_S\000"
6120 /* 11277 */ "FSCALEB_S\000"
6121 /* 11287 */ "XVFLOGB_S\000"
6122 /* 11297 */ "XVFSUB_S\000"
6123 /* 11306 */ "XVFMSUB_S\000"
6124 /* 11316 */ "XVFNMSUB_S\000"
6125 /* 11327 */ "XVFADD_S\000"
6126 /* 11336 */ "XVFMADD_S\000"
6127 /* 11346 */ "XVFNMADD_S\000"
6128 /* 11357 */ "FLD_S\000"
6129 /* 11363 */ "XVFCVTH_D_S\000"
6130 /* 11375 */ "XVFCVTL_D_S\000"
6131 /* 11387 */ "FCVT_D_S\000"
6132 /* 11396 */ "XVFCMP_CLE_S\000"
6133 /* 11409 */ "FLDLE_S\000"
6134 /* 11417 */ "XVFCMP_SLE_S\000"
6135 /* 11430 */ "FSTLE_S\000"
6136 /* 11438 */ "XVFCMP_CULE_S\000"
6137 /* 11452 */ "XVFCMP_SULE_S\000"
6138 /* 11466 */ "XVFCMP_CNE_S\000"
6139 /* 11479 */ "XVFRINTRNE_S\000"
6140 /* 11492 */ "XVFCMP_SNE_S\000"
6141 /* 11505 */ "XVFCMP_CUNE_S\000"
6142 /* 11519 */ "XVFCMP_SUNE_S\000"
6143 /* 11533 */ "XVFRECIPE_S\000"
6144 /* 11545 */ "XVFRSQRTE_S\000"
6145 /* 11557 */ "XVFCMP_CAF_S\000"
6146 /* 11570 */ "XVFCMP_SAF_S\000"
6147 /* 11583 */ "FNEG_S\000"
6148 /* 11590 */ "XVFCVT_H_S\000"
6149 /* 11601 */ "XVFMUL_S\000"
6150 /* 11610 */ "FTINTRNE_L_S\000"
6151 /* 11623 */ "XVFTINTRNEH_L_S\000"
6152 /* 11639 */ "XVFTINTRMH_L_S\000"
6153 /* 11654 */ "XVFTINTRPH_L_S\000"
6154 /* 11669 */ "XVFTINTH_L_S\000"
6155 /* 11682 */ "XVFTINTRZH_L_S\000"
6156 /* 11697 */ "XVFTINTRNEL_L_S\000"
6157 /* 11713 */ "XVFTINTRML_L_S\000"
6158 /* 11728 */ "XVFTINTRPL_L_S\000"
6159 /* 11743 */ "XVFTINTL_L_S\000"
6160 /* 11756 */ "XVFTINTRZL_L_S\000"
6161 /* 11771 */ "FTINTRM_L_S\000"
6162 /* 11783 */ "FTINTRP_L_S\000"
6163 /* 11795 */ "FTINT_L_S\000"
6164 /* 11805 */ "FTINTRZ_L_S\000"
6165 /* 11817 */ "XVFRINTRM_S\000"
6166 /* 11829 */ "FCOPYSIGN_S\000"
6167 /* 11841 */ "XVFMIN_S\000"
6168 /* 11850 */ "XVFCMP_CUN_S\000"
6169 /* 11863 */ "XVFCMP_SUN_S\000"
6170 /* 11876 */ "XVFRECIP_S\000"
6171 /* 11887 */ "XVFRINTRP_S\000"
6172 /* 11899 */ "XVFCMP_CEQ_S\000"
6173 /* 11912 */ "XVFCMP_SEQ_S\000"
6174 /* 11925 */ "XVFCMP_CUEQ_S\000"
6175 /* 11939 */ "XVFCMP_SUEQ_S\000"
6176 /* 11953 */ "MOVFRH2GR_S\000"
6177 /* 11965 */ "MOVFR2GR_S\000"
6178 /* 11976 */ "XVFCMP_COR_S\000"
6179 /* 11989 */ "XVFCMP_SOR_S\000"
6180 /* 12002 */ "FABS_S\000"
6181 /* 12009 */ "XVFCLASS_S\000"
6182 /* 12020 */ "FLDGT_S\000"
6183 /* 12028 */ "FSTGT_S\000"
6184 /* 12036 */ "XVFCMP_CLT_S\000"
6185 /* 12049 */ "XVFCMP_SLT_S\000"
6186 /* 12062 */ "XVFCMP_CULT_S\000"
6187 /* 12076 */ "XVFCMP_SULT_S\000"
6188 /* 12090 */ "XVFRINT_S\000"
6189 /* 12100 */ "XVFSQRT_S\000"
6190 /* 12110 */ "XVFRSQRT_S\000"
6191 /* 12121 */ "FST_S\000"
6192 /* 12127 */ "XVFTINT_WU_S\000"
6193 /* 12140 */ "XVFTINTRZ_WU_S\000"
6194 /* 12155 */ "XVFDIV_S\000"
6195 /* 12164 */ "FMOV_S\000"
6196 /* 12171 */ "XVFTINTRNE_W_S\000"
6197 /* 12186 */ "XVFTINTRM_W_S\000"
6198 /* 12200 */ "XVFTINTRP_W_S\000"
6199 /* 12214 */ "XVFTINT_W_S\000"
6200 /* 12226 */ "XVFTINTRZ_W_S\000"
6201 /* 12240 */ "XVFMAX_S\000"
6202 /* 12249 */ "FLDX_S\000"
6203 /* 12256 */ "FSTX_S\000"
6204 /* 12263 */ "XVFRINTRZ_S\000"
6205 /* 12275 */ "MOVFR2CF_xS\000"
6206 /* 12287 */ "FSEL_xS\000"
6207 /* 12295 */ "MOVCF2FR_xS\000"
6208 /* 12307 */ "G_SSUBSAT\000"
6209 /* 12317 */ "G_USUBSAT\000"
6210 /* 12327 */ "G_SADDSAT\000"
6211 /* 12337 */ "G_UADDSAT\000"
6212 /* 12347 */ "G_SSHLSAT\000"
6213 /* 12357 */ "G_USHLSAT\000"
6214 /* 12367 */ "G_SMULFIXSAT\000"
6215 /* 12380 */ "G_UMULFIXSAT\000"
6216 /* 12393 */ "G_SDIVFIXSAT\000"
6217 /* 12406 */ "G_UDIVFIXSAT\000"
6218 /* 12419 */ "G_ATOMICRMW_USUB_SAT\000"
6219 /* 12440 */ "G_FPTOSI_SAT\000"
6220 /* 12453 */ "G_FPTOUI_SAT\000"
6221 /* 12466 */ "G_EXTRACT\000"
6222 /* 12476 */ "G_SELECT\000"
6223 /* 12485 */ "G_BRINDIRECT\000"
6224 /* 12498 */ "PATCHABLE_RET\000"
6225 /* 12512 */ "PseudoRET\000"
6226 /* 12522 */ "G_MEMSET\000"
6227 /* 12531 */ "PATCHABLE_FUNCTION_EXIT\000"
6228 /* 12555 */ "G_BRJT\000"
6229 /* 12562 */ "BLT\000"
6230 /* 12566 */ "G_EXTRACT_VECTOR_ELT\000"
6231 /* 12587 */ "G_INSERT_VECTOR_ELT\000"
6232 /* 12607 */ "SLT\000"
6233 /* 12611 */ "G_FCONSTANT\000"
6234 /* 12623 */ "G_CONSTANT\000"
6235 /* 12634 */ "G_INTRINSIC_CONVERGENT\000"
6236 /* 12657 */ "STATEPOINT\000"
6237 /* 12668 */ "PATCHPOINT\000"
6238 /* 12679 */ "G_PTRTOINT\000"
6239 /* 12690 */ "G_FRINT\000"
6240 /* 12698 */ "G_INTRINSIC_LLRINT\000"
6241 /* 12717 */ "G_INTRINSIC_LRINT\000"
6242 /* 12735 */ "G_FNEARBYINT\000"
6243 /* 12748 */ "PseudoLA_GOT\000"
6244 /* 12761 */ "G_VASTART\000"
6245 /* 12771 */ "LIFETIME_START\000"
6246 /* 12786 */ "G_INVOKE_REGION_START\000"
6247 /* 12808 */ "G_INSERT\000"
6248 /* 12817 */ "G_FSQRT\000"
6249 /* 12825 */ "G_STRICT_FSQRT\000"
6250 /* 12840 */ "G_BITCAST\000"
6251 /* 12850 */ "G_ADDRSPACE_CAST\000"
6252 /* 12867 */ "DBG_VALUE_LIST\000"
6253 /* 12882 */ "XVST\000"
6254 /* 12887 */ "G_FPEXT\000"
6255 /* 12895 */ "G_SEXT\000"
6256 /* 12902 */ "G_ASSERT_SEXT\000"
6257 /* 12916 */ "G_ANYEXT\000"
6258 /* 12925 */ "G_ZEXT\000"
6259 /* 12932 */ "G_ASSERT_ZEXT\000"
6260 /* 12946 */ "XVSSUB_BU\000"
6261 /* 12956 */ "XVSADD_BU\000"
6262 /* 12966 */ "LD_BU\000"
6263 /* 12972 */ "XVMOD_BU\000"
6264 /* 12981 */ "XVABSD_BU\000"
6265 /* 12991 */ "XVSLE_BU\000"
6266 /* 13000 */ "XVAVG_BU\000"
6267 /* 13009 */ "XVMUH_BU\000"
6268 /* 13018 */ "XVSUBWOD_H_BU\000"
6269 /* 13032 */ "XVMADDWOD_H_BU\000"
6270 /* 13047 */ "XVADDWOD_H_BU\000"
6271 /* 13061 */ "XVMULWOD_H_BU\000"
6272 /* 13075 */ "XVSUBWEV_H_BU\000"
6273 /* 13089 */ "XVMADDWEV_H_BU\000"
6274 /* 13104 */ "XVADDWEV_H_BU\000"
6275 /* 13118 */ "XVMULWEV_H_BU\000"
6276 /* 13132 */ "XVSUBI_BU\000"
6277 /* 13142 */ "XVADDI_BU\000"
6278 /* 13152 */ "XVSLEI_BU\000"
6279 /* 13162 */ "XVMINI_BU\000"
6280 /* 13172 */ "XVSLTI_BU\000"
6281 /* 13182 */ "XVMAXI_BU\000"
6282 /* 13192 */ "X86MUL_BU\000"
6283 /* 13202 */ "XVMIN_BU\000"
6284 /* 13211 */ "VPICKVE2GR_BU\000"
6285 /* 13225 */ "XVAVGR_BU\000"
6286 /* 13235 */ "XVSAT_BU\000"
6287 /* 13244 */ "XVSLT_BU\000"
6288 /* 13253 */ "VEXT2XV_DU_BU\000"
6289 /* 13267 */ "XVEXTH_HU_BU\000"
6290 /* 13280 */ "XVSLLWIL_HU_BU\000"
6291 /* 13295 */ "VEXT2XV_HU_BU\000"
6292 /* 13309 */ "XVHSUBW_HU_BU\000"
6293 /* 13323 */ "XVHADDW_HU_BU\000"
6294 /* 13337 */ "VEXT2XV_WU_BU\000"
6295 /* 13351 */ "XVDIV_BU\000"
6296 /* 13360 */ "XVMAX_BU\000"
6297 /* 13369 */ "LDX_BU\000"
6298 /* 13376 */ "G_ABDU\000"
6299 /* 13383 */ "AMMIN__DB_DU\000"
6300 /* 13396 */ "AMMAX__DB_DU\000"
6301 /* 13409 */ "X86SUB_DU\000"
6302 /* 13419 */ "XVSSUB_DU\000"
6303 /* 13429 */ "X86ADD_DU\000"
6304 /* 13439 */ "XVSADD_DU\000"
6305 /* 13449 */ "XVMOD_DU\000"
6306 /* 13458 */ "XVABSD_DU\000"
6307 /* 13468 */ "XVSLE_DU\000"
6308 /* 13477 */ "XVAVG_DU\000"
6309 /* 13486 */ "MULH_DU\000"
6310 /* 13494 */ "XVMUH_DU\000"
6311 /* 13503 */ "XVSUBI_DU\000"
6312 /* 13513 */ "XVADDI_DU\000"
6313 /* 13523 */ "XVSLEI_DU\000"
6314 /* 13533 */ "XVMINI_DU\000"
6315 /* 13543 */ "XVSLTI_DU\000"
6316 /* 13553 */ "XVMAXI_DU\000"
6317 /* 13563 */ "X86MUL_DU\000"
6318 /* 13573 */ "AMMIN_DU\000"
6319 /* 13582 */ "XVMIN_DU\000"
6320 /* 13591 */ "XVSUBWOD_Q_DU\000"
6321 /* 13605 */ "XVMADDWOD_Q_DU\000"
6322 /* 13620 */ "XVADDWOD_Q_DU\000"
6323 /* 13634 */ "XVMULWOD_Q_DU\000"
6324 /* 13648 */ "XVSUBWEV_Q_DU\000"
6325 /* 13662 */ "XVMADDWEV_Q_DU\000"
6326 /* 13677 */ "XVADDWEV_Q_DU\000"
6327 /* 13691 */ "XVMULWEV_Q_DU\000"
6328 /* 13705 */ "XVPICKVE2GR_DU\000"
6329 /* 13720 */ "XVAVGR_DU\000"
6330 /* 13730 */ "XVSAT_DU\000"
6331 /* 13739 */ "XVSLT_DU\000"
6332 /* 13748 */ "XVEXTH_QU_DU\000"
6333 /* 13761 */ "XVEXTL_QU_DU\000"
6334 /* 13774 */ "XVHSUBW_QU_DU\000"
6335 /* 13788 */ "XVHADDW_QU_DU\000"
6336 /* 13802 */ "XVDIV_DU\000"
6337 /* 13811 */ "AMMAX_DU\000"
6338 /* 13820 */ "XVMAX_DU\000"
6339 /* 13829 */ "BGEU\000"
6340 /* 13834 */ "XVSSUB_HU\000"
6341 /* 13844 */ "XVSADD_HU\000"
6342 /* 13854 */ "LD_HU\000"
6343 /* 13860 */ "XVMOD_HU\000"
6344 /* 13869 */ "XVABSD_HU\000"
6345 /* 13879 */ "XVSLE_HU\000"
6346 /* 13888 */ "XVAVG_HU\000"
6347 /* 13897 */ "XVMUH_HU\000"
6348 /* 13906 */ "XVSUBI_HU\000"
6349 /* 13916 */ "XVADDI_HU\000"
6350 /* 13926 */ "XVSLEI_HU\000"
6351 /* 13936 */ "XVMINI_HU\000"
6352 /* 13946 */ "XVSLTI_HU\000"
6353 /* 13956 */ "XVMAXI_HU\000"
6354 /* 13966 */ "X86MUL_HU\000"
6355 /* 13976 */ "XVMIN_HU\000"
6356 /* 13985 */ "VPICKVE2GR_HU\000"
6357 /* 13999 */ "XVAVGR_HU\000"
6358 /* 14009 */ "XVSAT_HU\000"
6359 /* 14018 */ "XVSLT_HU\000"
6360 /* 14027 */ "VEXT2XV_DU_HU\000"
6361 /* 14041 */ "XVEXTH_WU_HU\000"
6362 /* 14054 */ "XVSLLWIL_WU_HU\000"
6363 /* 14069 */ "VEXT2XV_WU_HU\000"
6364 /* 14083 */ "XVHSUBW_WU_HU\000"
6365 /* 14097 */ "XVHADDW_WU_HU\000"
6366 /* 14111 */ "XVDIV_HU\000"
6367 /* 14120 */ "XVSUBWOD_W_HU\000"
6368 /* 14134 */ "XVMADDWOD_W_HU\000"
6369 /* 14149 */ "XVADDWOD_W_HU\000"
6370 /* 14163 */ "XVMULWOD_W_HU\000"
6371 /* 14177 */ "XVSUBWEV_W_HU\000"
6372 /* 14191 */ "XVMADDWEV_W_HU\000"
6373 /* 14206 */ "XVADDWEV_W_HU\000"
6374 /* 14220 */ "XVMULWEV_W_HU\000"
6375 /* 14234 */ "XVMAX_HU\000"
6376 /* 14243 */ "LDX_HU\000"
6377 /* 14250 */ "XVFFINT_D_LU\000"
6378 /* 14263 */ "BLTU\000"
6379 /* 14268 */ "SLTU\000"
6380 /* 14273 */ "AMMIN__DB_WU\000"
6381 /* 14286 */ "AMMAX__DB_WU\000"
6382 /* 14299 */ "X86SUB_WU\000"
6383 /* 14309 */ "XVSSUB_WU\000"
6384 /* 14319 */ "X86ADD_WU\000"
6385 /* 14329 */ "XVSADD_WU\000"
6386 /* 14339 */ "LD_WU\000"
6387 /* 14345 */ "XVMOD_WU\000"
6388 /* 14354 */ "XVABSD_WU\000"
6389 /* 14364 */ "XVSUBWOD_D_WU\000"
6390 /* 14378 */ "XVMADDWOD_D_WU\000"
6391 /* 14393 */ "XVADDWOD_D_WU\000"
6392 /* 14407 */ "XVMULWOD_D_WU\000"
6393 /* 14421 */ "XVSUBWEV_D_WU\000"
6394 /* 14435 */ "XVMADDWEV_D_WU\000"
6395 /* 14450 */ "XVADDWEV_D_WU\000"
6396 /* 14464 */ "XVMULWEV_D_WU\000"
6397 /* 14478 */ "MULW_D_WU\000"
6398 /* 14488 */ "XVSLE_WU\000"
6399 /* 14497 */ "XVAVG_WU\000"
6400 /* 14506 */ "MULH_WU\000"
6401 /* 14514 */ "XVMUH_WU\000"
6402 /* 14523 */ "XVSUBI_WU\000"
6403 /* 14533 */ "XVADDI_WU\000"
6404 /* 14543 */ "XVSLEI_WU\000"
6405 /* 14553 */ "XVMINI_WU\000"
6406 /* 14563 */ "XVSLTI_WU\000"
6407 /* 14573 */ "XVMAXI_WU\000"
6408 /* 14583 */ "ALSL_WU\000"
6409 /* 14591 */ "X86MUL_WU\000"
6410 /* 14601 */ "AMMIN_WU\000"
6411 /* 14610 */ "XVMIN_WU\000"
6412 /* 14619 */ "XVPICKVE2GR_WU\000"
6413 /* 14634 */ "XVAVGR_WU\000"
6414 /* 14644 */ "XVFFINT_S_WU\000"
6415 /* 14657 */ "XVSAT_WU\000"
6416 /* 14666 */ "XVSLT_WU\000"
6417 /* 14675 */ "XVEXTH_DU_WU\000"
6418 /* 14688 */ "XVSLLWIL_DU_WU\000"
6419 /* 14703 */ "VEXT2XV_DU_WU\000"
6420 /* 14717 */ "XVHSUBW_DU_WU\000"
6421 /* 14731 */ "XVHADDW_DU_WU\000"
6422 /* 14745 */ "XVDIV_WU\000"
6423 /* 14754 */ "AMMAX_WU\000"
6424 /* 14763 */ "XVMAX_WU\000"
6425 /* 14772 */ "LDX_WU\000"
6426 /* 14779 */ "G_FDIV\000"
6427 /* 14786 */ "G_STRICT_FDIV\000"
6428 /* 14800 */ "G_SDIV\000"
6429 /* 14807 */ "G_UDIV\000"
6430 /* 14814 */ "G_GET_FPENV\000"
6431 /* 14826 */ "G_RESET_FPENV\000"
6432 /* 14840 */ "G_SET_FPENV\000"
6433 /* 14852 */ "XVAND_V\000"
6434 /* 14860 */ "XVBITSEL_V\000"
6435 /* 14871 */ "XVBSLL_V\000"
6436 /* 14880 */ "XVBSRL_V\000"
6437 /* 14889 */ "XVANDN_V\000"
6438 /* 14898 */ "XVORN_V\000"
6439 /* 14906 */ "XVNOR_V\000"
6440 /* 14914 */ "XVOR_V\000"
6441 /* 14921 */ "XVXOR_V\000"
6442 /* 14929 */ "XVSETNEZ_V\000"
6443 /* 14940 */ "XVSETEQZ_V\000"
6444 /* 14951 */ "REVB_2W\000"
6445 /* 14959 */ "REVH_2W\000"
6446 /* 14967 */ "G_FPOW\000"
6447 /* 14974 */ "XVREPLVE0_W\000"
6448 /* 14986 */ "XVINSVE0_W\000"
6449 /* 14997 */ "XVADDA_W\000"
6450 /* 15006 */ "X86SRA_W\000"
6451 /* 15015 */ "ARMSRA_W\000"
6452 /* 15024 */ "XVSRA_W\000"
6453 /* 15032 */ "AMADD__DB_W\000"
6454 /* 15044 */ "AMAND__DB_W\000"
6455 /* 15056 */ "AMMIN__DB_W\000"
6456 /* 15068 */ "AMSWAP__DB_W\000"
6457 /* 15081 */ "AMOR__DB_W\000"
6458 /* 15092 */ "AMXOR__DB_W\000"
6459 /* 15104 */ "AMCAS__DB_W\000"
6460 /* 15116 */ "AMMAX__DB_W\000"
6461 /* 15128 */ "X86SUB_W\000"
6462 /* 15137 */ "ARMSUB_W\000"
6463 /* 15146 */ "XVMSUB_W\000"
6464 /* 15155 */ "XVSSUB_W\000"
6465 /* 15164 */ "XVSUB_W\000"
6466 /* 15172 */ "CRCC_W_B_W\000"
6467 /* 15183 */ "CRC_W_B_W\000"
6468 /* 15193 */ "X86SBC_W\000"
6469 /* 15202 */ "ARMSBC_W\000"
6470 /* 15211 */ "X86ADC_W\000"
6471 /* 15220 */ "ARMADC_W\000"
6472 /* 15229 */ "X86DEC_W\000"
6473 /* 15238 */ "X86INC_W\000"
6474 /* 15247 */ "SC_W\000"
6475 /* 15252 */ "X86ADD_W\000"
6476 /* 15261 */ "AMADD_W\000"
6477 /* 15269 */ "ARMADD_W\000"
6478 /* 15278 */ "XVMADD_W\000"
6479 /* 15287 */ "XVSADD_W\000"
6480 /* 15296 */ "XVADD_W\000"
6481 /* 15304 */ "LD_W\000"
6482 /* 15309 */ "X86AND_W\000"
6483 /* 15318 */ "AMAND_W\000"
6484 /* 15326 */ "ARMAND_W\000"
6485 /* 15335 */ "XVPACKOD_W\000"
6486 /* 15346 */ "XVPICKOD_W\000"
6487 /* 15357 */ "XVMOD_W\000"
6488 /* 15365 */ "IOCSRRD_W\000"
6489 /* 15375 */ "XVABSD_W\000"
6490 /* 15384 */ "XVSUBWOD_D_W\000"
6491 /* 15397 */ "XVMADDWOD_D_W\000"
6492 /* 15411 */ "XVADDWOD_D_W\000"
6493 /* 15424 */ "XVMULWOD_D_W\000"
6494 /* 15437 */ "XVFFINTH_D_W\000"
6495 /* 15450 */ "XVEXTH_D_W\000"
6496 /* 15461 */ "XVSLLWIL_D_W\000"
6497 /* 15474 */ "XVFFINTL_D_W\000"
6498 /* 15487 */ "FFINT_D_W\000"
6499 /* 15497 */ "XVSUBWEV_D_W\000"
6500 /* 15510 */ "XVMADDWEV_D_W\000"
6501 /* 15524 */ "XVADDWEV_D_W\000"
6502 /* 15537 */ "XVMULWEV_D_W\000"
6503 /* 15550 */ "VEXT2XV_D_W\000"
6504 /* 15562 */ "XVHSUBW_D_W\000"
6505 /* 15574 */ "XVHADDW_D_W\000"
6506 /* 15586 */ "MULW_D_W\000"
6507 /* 15595 */ "CRCC_W_D_W\000"
6508 /* 15606 */ "CRC_W_D_W\000"
6509 /* 15616 */ "LDLE_W\000"
6510 /* 15623 */ "XVSLE_W\000"
6511 /* 15631 */ "STLE_W\000"
6512 /* 15638 */ "XVPICKVE_W\000"
6513 /* 15649 */ "XVREPLVE_W\000"
6514 /* 15660 */ "XVSHUF_W\000"
6515 /* 15669 */ "XVNEG_W\000"
6516 /* 15677 */ "XVAVG_W\000"
6517 /* 15685 */ "RDTIMEH_W\000"
6518 /* 15695 */ "MULH_W\000"
6519 /* 15702 */ "MOVGR2FRH_W\000"
6520 /* 15714 */ "XVMUH_W\000"
6521 /* 15722 */ "XVILVH_W\000"
6522 /* 15731 */ "XVSSRANI_H_W\000"
6523 /* 15744 */ "XVSRANI_H_W\000"
6524 /* 15756 */ "XVSSRLNI_H_W\000"
6525 /* 15769 */ "XVSRLNI_H_W\000"
6526 /* 15781 */ "XVSSRARNI_H_W\000"
6527 /* 15795 */ "XVSRARNI_H_W\000"
6528 /* 15808 */ "XVSSRLRNI_H_W\000"
6529 /* 15822 */ "XVSRLRNI_H_W\000"
6530 /* 15835 */ "XVSSRAN_H_W\000"
6531 /* 15847 */ "XVSRAN_H_W\000"
6532 /* 15858 */ "XVSSRLN_H_W\000"
6533 /* 15870 */ "XVSRLN_H_W\000"
6534 /* 15881 */ "XVSSRARN_H_W\000"
6535 /* 15894 */ "XVSRARN_H_W\000"
6536 /* 15906 */ "XVSSRLRN_H_W\000"
6537 /* 15919 */ "XVSRLRN_H_W\000"
6538 /* 15931 */ "CRCC_W_H_W\000"
6539 /* 15942 */ "CRC_W_H_W\000"
6540 /* 15952 */ "ADDU12I_W\000"
6541 /* 15962 */ "LU12I_W\000"
6542 /* 15970 */ "XVSHUF4I_W\000"
6543 /* 15981 */ "X86SRAI_W\000"
6544 /* 15991 */ "ARMSRAI_W\000"
6545 /* 16001 */ "XVSRAI_W\000"
6546 /* 16010 */ "ADDI_W\000"
6547 /* 16017 */ "XVSLEI_W\000"
6548 /* 16026 */ "XVREPL128VEI_W\000"
6549 /* 16041 */ "VREPLVEI_W\000"
6550 /* 16052 */ "X86RCLI_W\000"
6551 /* 16062 */ "X86SLLI_W\000"
6552 /* 16072 */ "ARMSLLI_W\000"
6553 /* 16082 */ "XVSLLI_W\000"
6554 /* 16091 */ "PseudoXVREPLI_W\000"
6555 /* 16107 */ "PseudoVREPLI_W\000"
6556 /* 16122 */ "X86SRLI_W\000"
6557 /* 16132 */ "ARMSRLI_W\000"
6558 /* 16142 */ "XVSRLI_W\000"
6559 /* 16151 */ "X86ROTLI_W\000"
6560 /* 16162 */ "PseudoLI_W\000"
6561 /* 16173 */ "XVPERMI_W\000"
6562 /* 16183 */ "XVMINI_W\000"
6563 /* 16192 */ "XVSEQI_W\000"
6564 /* 16201 */ "XVSRARI_W\000"
6565 /* 16211 */ "X86RCRI_W\000"
6566 /* 16221 */ "XVBITCLRI_W\000"
6567 /* 16233 */ "XVSRLRI_W\000"
6568 /* 16243 */ "X86ROTRI_W\000"
6569 /* 16254 */ "ARMROTRI_W\000"
6570 /* 16265 */ "XVROTRI_W\000"
6571 /* 16275 */ "XVBITSETI_W\000"
6572 /* 16287 */ "XVSLTI_W\000"
6573 /* 16296 */ "XVBITREVI_W\000"
6574 /* 16308 */ "XVMAXI_W\000"
6575 /* 16317 */ "BYTEPICK_W\000"
6576 /* 16328 */ "BSTRPICK_W\000"
6577 /* 16339 */ "X86RCL_W\000"
6578 /* 16348 */ "LDL_W\000"
6579 /* 16354 */ "RDTIMEL_W\000"
6580 /* 16364 */ "SCREL_W\000"
6581 /* 16372 */ "X86SLL_W\000"
6582 /* 16381 */ "ARMSLL_W\000"
6583 /* 16390 */ "XVSLL_W\000"
6584 /* 16398 */ "XVLDREPL_W\000"
6585 /* 16409 */ "X86SRL_W\000"
6586 /* 16418 */ "ARMSRL_W\000"
6587 /* 16427 */ "XVSRL_W\000"
6588 /* 16435 */ "ALSL_W\000"
6589 /* 16442 */ "X86ROTL_W\000"
6590 /* 16452 */ "STL_W\000"
6591 /* 16458 */ "X86MUL_W\000"
6592 /* 16467 */ "XVMUL_W\000"
6593 /* 16475 */ "XVILVL_W\000"
6594 /* 16484 */ "XVSTELM_W\000"
6595 /* 16494 */ "XVPERM_W\000"
6596 /* 16503 */ "AMMIN_W\000"
6597 /* 16511 */ "XVMIN_W\000"
6598 /* 16519 */ "XVCLO_W\000"
6599 /* 16527 */ "CTO_W\000"
6600 /* 16533 */ "AMSWAP_W\000"
6601 /* 16542 */ "LLACQ_W\000"
6602 /* 16550 */ "XVSEQ_W\000"
6603 /* 16558 */ "XVSRAR_W\000"
6604 /* 16567 */ "X86RCR_W\000"
6605 /* 16576 */ "LDR_W\000"
6606 /* 16582 */ "MOVGR2FR_W\000"
6607 /* 16593 */ "XVPICKVE2GR_W\000"
6608 /* 16607 */ "XVAVGR_W\000"
6609 /* 16616 */ "XVBITCLR_W\000"
6610 /* 16627 */ "XVSRLR_W\000"
6611 /* 16636 */ "X86OR_W\000"
6612 /* 16644 */ "AMOR_W\000"
6613 /* 16651 */ "ARMOR_W\000"
6614 /* 16659 */ "X86XOR_W\000"
6615 /* 16668 */ "AMXOR_W\000"
6616 /* 16676 */ "ARMXOR_W\000"
6617 /* 16685 */ "X86ROTR_W\000"
6618 /* 16695 */ "ARMROTR_W\000"
6619 /* 16705 */ "XVROTR_W\000"
6620 /* 16714 */ "LDPTR_W\000"
6621 /* 16722 */ "STPTR_W\000"
6622 /* 16730 */ "STR_W\000"
6623 /* 16736 */ "XVREPLGR2VR_W\000"
6624 /* 16750 */ "XVINSGR2VR_W\000"
6625 /* 16763 */ "IOCSRWR_W\000"
6626 /* 16773 */ "AMCAS_W\000"
6627 /* 16781 */ "BSTRINS_W\000"
6628 /* 16791 */ "XVEXTRINS_W\000"
6629 /* 16803 */ "XVFFINT_S_W\000"
6630 /* 16815 */ "XVSAT_W\000"
6631 /* 16823 */ "XVBITSET_W\000"
6632 /* 16834 */ "LDGT_W\000"
6633 /* 16841 */ "STGT_W\000"
6634 /* 16848 */ "XVSLT_W\000"
6635 /* 16856 */ "XVPCNT_W\000"
6636 /* 16865 */ "ARMNOT_W\000"
6637 /* 16874 */ "ST_W\000"
6638 /* 16879 */ "XVSSRANI_HU_W\000"
6639 /* 16893 */ "XVSSRLNI_HU_W\000"
6640 /* 16907 */ "XVSSRARNI_HU_W\000"
6641 /* 16922 */ "XVSSRLRNI_HU_W\000"
6642 /* 16937 */ "XVSSRAN_HU_W\000"
6643 /* 16950 */ "XVSSRLN_HU_W\000"
6644 /* 16963 */ "XVSSRARN_HU_W\000"
6645 /* 16977 */ "XVSSRLRN_HU_W\000"
6646 /* 16991 */ "XVMADDWOD_D_WU_W\000"
6647 /* 17008 */ "XVADDWOD_D_WU_W\000"
6648 /* 17024 */ "XVMULWOD_D_WU_W\000"
6649 /* 17040 */ "XVMADDWEV_D_WU_W\000"
6650 /* 17057 */ "XVADDWEV_D_WU_W\000"
6651 /* 17073 */ "XVMULWEV_D_WU_W\000"
6652 /* 17089 */ "XVPACKEV_W\000"
6653 /* 17100 */ "XVPICKEV_W\000"
6654 /* 17111 */ "XVBITREV_W\000"
6655 /* 17122 */ "XVDIV_W\000"
6656 /* 17130 */ "XVSIGNCOV_W\000"
6657 /* 17142 */ "ARMMOV_W\000"
6658 /* 17151 */ "CRCC_W_W_W\000"
6659 /* 17162 */ "CRC_W_W_W\000"
6660 /* 17172 */ "AMMAX_W\000"
6661 /* 17180 */ "XVMAX_W\000"
6662 /* 17188 */ "LDX_W\000"
6663 /* 17194 */ "ARMRRX_W\000"
6664 /* 17203 */ "STX_W\000"
6665 /* 17209 */ "PseudoXVBZ_W\000"
6666 /* 17222 */ "PseudoVBZ_W\000"
6667 /* 17234 */ "XVSETALLNEZ_W\000"
6668 /* 17248 */ "XVCLZ_W\000"
6669 /* 17256 */ "PseudoXVBNZ_W\000"
6670 /* 17270 */ "PseudoVBNZ_W\000"
6671 /* 17283 */ "XVSETANYEQZ_W\000"
6672 /* 17297 */ "CTZ_W\000"
6673 /* 17303 */ "PseudoXVMSKLTZ_W\000"
6674 /* 17320 */ "PseudoVMSKLTZ_W\000"
6675 /* 17336 */ "PseudoAddTPRel_W\000"
6676 /* 17353 */ "PseudoAtomicStoreW\000"
6677 /* 17372 */ "G_VECREDUCE_FMAX\000"
6678 /* 17389 */ "G_ATOMICRMW_FMAX\000"
6679 /* 17406 */ "G_VECREDUCE_SMAX\000"
6680 /* 17423 */ "G_SMAX\000"
6681 /* 17430 */ "G_VECREDUCE_UMAX\000"
6682 /* 17447 */ "G_UMAX\000"
6683 /* 17454 */ "G_ATOMICRMW_UMAX\000"
6684 /* 17471 */ "G_ATOMICRMW_MAX\000"
6685 /* 17487 */ "PRELDX\000"
6686 /* 17494 */ "XVLDX\000"
6687 /* 17500 */ "G_FRAME_INDEX\000"
6688 /* 17514 */ "G_SBFX\000"
6689 /* 17521 */ "G_UBFX\000"
6690 /* 17528 */ "G_SMULFIX\000"
6691 /* 17538 */ "G_UMULFIX\000"
6692 /* 17548 */ "G_SDIVFIX\000"
6693 /* 17558 */ "G_UDIVFIX\000"
6694 /* 17568 */ "XVSTX\000"
6695 /* 17574 */ "G_MEMCPY\000"
6696 /* 17583 */ "COPY\000"
6697 /* 17588 */ "CONVERGENCECTRL_ENTRY\000"
6698 /* 17610 */ "PseudoXVBZ\000"
6699 /* 17621 */ "PseudoVBZ\000"
6700 /* 17631 */ "BNEZ\000"
6701 /* 17636 */ "BCNEZ\000"
6702 /* 17642 */ "MASKNEZ\000"
6703 /* 17650 */ "G_CTLZ\000"
6704 /* 17657 */ "PseudoXVBNZ\000"
6705 /* 17669 */ "PseudoVBNZ\000"
6706 /* 17680 */ "BEQZ\000"
6707 /* 17685 */ "BCEQZ\000"
6708 /* 17691 */ "MASKEQZ\000"
6709 /* 17699 */ "G_CTTZ\000"
6710 /* 17706 */ "PseudoCmpXchg128Acquire\000"
6711 /* 17730 */ "BuildPairF64Pseudo\000"
6712 /* 17749 */ "SplitPairF64Pseudo\000"
6713 /* 17768 */ "PseudoTAILIndirect\000"
6714 /* 17787 */ "PseudoCALLIndirect\000"
6715};
6716#ifdef __GNUC__
6717#pragma GCC diagnostic pop
6718#endif
6719
6720extern const unsigned LoongArchInstrNameIndices[] = {
6721 8777U, 9341U, 10437U, 9758U, 8887U, 8868U, 8896U, 9148U,
6722 6715U, 6730U, 6631U, 6618U, 6757U, 11114U, 6436U, 12867U,
6723 6644U, 8773U, 8877U, 5944U, 17583U, 6274U, 12771U, 2820U,
6724 5895U, 5932U, 9878U, 9117U, 12668U, 2939U, 10153U, 6836U,
6725 12657U, 6330U, 10126U, 10113U, 10517U, 12498U, 12531U, 9033U,
6726 9096U, 9069U, 8913U, 6421U, 10482U, 9832U, 17588U, 10718U,
6727 10034U, 6484U, 12902U, 12932U, 9601U, 2680U, 754U, 9256U,
6728 14800U, 14807U, 9307U, 9314U, 9321U, 9331U, 2798U, 10907U,
6729 10870U, 11033U, 13376U, 6629U, 8775U, 17500U, 6446U, 6461U,
6730 9153U, 12466U, 11040U, 12808U, 11057U, 10793U, 2443U, 11097U,
6731 12679U, 10983U, 12840U, 6548U, 10493U, 2913U, 2417U, 2895U,
6732 12717U, 12698U, 9579U, 10542U, 10561U, 2581U, 2525U, 2555U,
6733 2566U, 2506U, 2536U, 6386U, 6370U, 11144U, 6778U, 6804U,
6734 2696U, 760U, 2804U, 2765U, 10912U, 10876U, 17471U, 9727U,
6735 17454U, 9710U, 2647U, 737U, 17389U, 9645U, 9490U, 9437U,
6736 9940U, 9918U, 2854U, 12419U, 5924U, 6877U, 2845U, 12485U,
6737 12786U, 2395U, 11192U, 12634U, 11219U, 12916U, 2435U, 12623U,
6738 12611U, 12761U, 6828U, 12895U, 6744U, 12925U, 8955U, 10698U,
6739 10684U, 8948U, 10691U, 10976U, 9174U, 9995U, 9988U, 10002U,
6740 10009U, 12476U, 9824U, 5965U, 9808U, 5916U, 9816U, 5957U,
6741 9800U, 5908U, 9862U, 9854U, 6896U, 6888U, 12337U, 12327U,
6742 12317U, 12307U, 12357U, 12347U, 17528U, 17538U, 12367U, 12380U,
6743 17548U, 17558U, 12393U, 12406U, 2605U, 716U, 9198U, 670U,
6744 2499U, 14779U, 9286U, 14967U, 8815U, 10197U, 552U, 9U,
6745 6821U, 535U, 0U, 10172U, 10204U, 6708U, 12887U, 2407U,
6746 8786U, 8800U, 9970U, 9979U, 12440U, 12453U, 11007U, 9616U,
6747 11131U, 6557U, 9539U, 9549U, 6014U, 6029U, 9426U, 9479U,
6748 9511U, 9525U, 14814U, 14840U, 14826U, 5973U, 6001U, 5986U,
6749 2686U, 8845U, 9679U, 17423U, 9703U, 17447U, 11027U, 2886U,
6750 2876U, 10432U, 12555U, 6247U, 10774U, 10754U, 12587U, 12566U,
6751 10808U, 10839U, 10825U, 11174U, 17699U, 6600U, 17650U, 6582U,
6752 10055U, 9962U, 6408U, 9001U, 11080U, 9751U, 11087U, 9567U,
6753 11072U, 9743U, 9559U, 543U, 6920U, 6912U, 6904U, 12817U,
6754 10745U, 12690U, 12735U, 12850U, 10469U, 6256U, 2464U, 6518U,
6755 6355U, 2633U, 723U, 9226U, 14786U, 9293U, 676U, 12825U,
6756 10181U, 10581U, 10597U, 17574U, 6301U, 6530U, 12522U, 9870U,
6757 9911U, 9887U, 9899U, 2612U, 9205U, 2588U, 9181U, 17372U,
6758 9628U, 9458U, 9405U, 2664U, 9240U, 2782U, 10892U, 10854U,
6759 17406U, 9662U, 17430U, 9686U, 17514U, 17521U, 9783U, 10138U,
6760 17730U, 5851U, 17336U, 110U, 132U, 513U, 324U, 183U,
6761 588U, 390U, 60U, 462U, 273U, 411U, 5868U, 17353U,
6762 371U, 10450U, 2833U, 8961U, 9129U, 640U, 17787U, 6176U,
6763 9387U, 10063U, 653U, 17706U, 228U, 611U, 10640U, 9017U,
6764 9053U, 8974U, 11014U, 6193U, 12748U, 6212U, 8933U, 6138U,
6765 2481U, 6048U, 2712U, 6072U, 6231U, 6116U, 2749U, 6094U,
6766 6281U, 10614U, 3938U, 16162U, 82U, 485U, 296U, 154U,
6767 32U, 433U, 244U, 346U, 206U, 12512U, 10627U, 8990U,
6768 627U, 17768U, 6159U, 9369U, 10016U, 17669U, 2292U, 5773U,
6769 8665U, 17270U, 17621U, 2178U, 5725U, 8617U, 17222U, 2332U,
6770 2207U, 2379U, 5835U, 8709U, 17320U, 2240U, 1412U, 3893U,
6771 7587U, 16107U, 17657U, 2278U, 5759U, 8651U, 17256U, 17610U,
6772 2165U, 5712U, 8604U, 17209U, 1870U, 8019U, 2315U, 2190U,
6773 2362U, 5818U, 8692U, 17303U, 2223U, 1396U, 3877U, 7571U,
6774 16091U, 10962U, 10927U, 17749U, 10969U, 898U, 3238U, 7260U,
6775 15214U, 3796U, 16010U, 3730U, 15952U, 3767U, 3270U, 15255U,
6776 4172U, 16435U, 14583U, 931U, 3285U, 7293U, 15261U, 814U,
6777 3038U, 6976U, 15032U, 3365U, 15318U, 3050U, 15044U, 1899U,
6778 4877U, 8048U, 16773U, 839U, 3110U, 7001U, 15104U, 5682U,
6779 13811U, 17172U, 14754U, 3122U, 13396U, 15116U, 14286U, 4342U,
6780 13573U, 16503U, 14601U, 3062U, 13383U, 15056U, 14273U, 4762U,
6781 16644U, 3087U, 15081U, 1733U, 4398U, 7882U, 16533U, 826U,
6782 3074U, 6988U, 15068U, 4791U, 16668U, 3098U, 15092U, 2778U,
6783 8768U, 9574U, 15220U, 15269U, 15326U, 6668U, 6540U, 5395U,
6784 17142U, 6688U, 16865U, 16651U, 16254U, 16695U, 17194U, 15202U,
6785 16072U, 16381U, 15991U, 15015U, 16132U, 16418U, 15137U, 16676U,
6786 4963U, 3474U, 697U, 17685U, 17636U, 10213U, 17680U, 6044U,
6787 13829U, 689U, 699U, 5350U, 17113U, 8855U, 12562U, 14263U,
6788 6297U, 17631U, 8839U, 4892U, 16781U, 4093U, 16328U, 4082U,
6789 16317U, 10028U, 4386U, 16521U, 5753U, 17250U, 6771U, 15172U,
6790 15595U, 15931U, 17151U, 15183U, 15606U, 15942U, 17162U, 2963U,
6791 11001U, 6796U, 4392U, 16527U, 5812U, 17297U, 10422U, 8858U,
6792 5362U, 13804U, 17124U, 14747U, 9778U, 2125U, 8487U, 4885U,
6793 12002U, 3278U, 11329U, 4916U, 12011U, 3643U, 11559U, 4440U,
6794 11901U, 3434U, 11398U, 4982U, 12038U, 3530U, 11468U, 4751U,
6795 11978U, 4474U, 11927U, 3493U, 11440U, 5016U, 12064U, 3569U,
6796 11507U, 4360U, 11852U, 3656U, 11572U, 4461U, 11914U, 3463U,
6797 11419U, 5003U, 12051U, 3556U, 11494U, 4771U, 11991U, 4488U,
6798 11941U, 3507U, 11454U, 5030U, 12078U, 3583U, 11521U, 4373U,
6799 11865U, 4321U, 11829U, 2739U, 11387U, 3346U, 4927U, 3422U,
6800 5361U, 12157U, 9264U, 15487U, 9276U, 16805U, 4955U, 12020U,
6801 3445U, 11409U, 5698U, 12249U, 3340U, 11357U, 3146U, 11289U,
6802 3295U, 11338U, 3030U, 11269U, 5675U, 12242U, 3003U, 11259U,
6803 4335U, 11843U, 5388U, 12164U, 3174U, 11308U, 4206U, 11603U,
6804 3676U, 11583U, 3305U, 11348U, 3184U, 11318U, 3597U, 11535U,
6805 4409U, 11878U, 5053U, 12092U, 3609U, 11547U, 5073U, 12112U,
6806 3134U, 11277U, 5887U, 12287U, 5063U, 12102U, 4972U, 12028U,
6807 3483U, 11430U, 5705U, 12256U, 5082U, 12121U, 3165U, 11299U,
6808 4247U, 11771U, 5525U, 12188U, 4232U, 11610U, 5406U, 12173U,
6809 4261U, 11783U, 5635U, 12202U, 4287U, 11805U, 5661U, 12228U,
6810 4275U, 11795U, 5649U, 12216U, 2962U, 11000U, 6795U, 6928U,
6811 8863U, 10427U, 6269U, 709U, 1009U, 3403U, 7371U, 15365U,
6812 1889U, 4867U, 8038U, 16763U, 9169U, 18U, 25U, 10705U,
6813 1938U, 4956U, 8111U, 16834U, 1040U, 3446U, 7402U, 15616U,
6814 4113U, 16348U, 6430U, 4818U, 16714U, 4670U, 16576U, 2153U,
6815 13369U, 5699U, 8592U, 14243U, 17188U, 14772U, 965U, 12966U,
6816 3341U, 7327U, 13854U, 15304U, 14339U, 4430U, 16542U, 4131U,
6817 16376U, 15962U, 3740U, 3748U, 17691U, 17642U, 3397U, 13451U,
6818 15359U, 14347U, 12295U, 10654U, 10673U, 12275U, 4701U, 11965U,
6819 560U, 11953U, 6573U, 10951U, 15702U, 4676U, 16582U, 574U,
6820 10459U, 10663U, 3699U, 13486U, 15695U, 14506U, 15586U, 14478U,
6821 4198U, 16461U, 10741U, 10738U, 8782U, 9774U, 8755U, 8735U,
6822 8745U, 8725U, 2728U, 17487U, 1499U, 3990U, 7674U, 16214U,
6823 1772U, 4664U, 7921U, 16570U, 15685U, 16354U, 3519U, 6853U,
6824 14951U, 6861U, 3219U, 14959U, 3714U, 1557U, 4022U, 7706U,
6825 16246U, 1840U, 4802U, 7989U, 16688U, 889U, 3229U, 7251U,
6826 15196U, 4119U, 16364U, 3262U, 10237U, 15247U, 8831U, 8823U,
6827 6343U, 6317U, 6394U, 6505U, 3861U, 16065U, 4130U, 16375U,
6828 12607U, 8795U, 14268U, 8809U, 3780U, 15984U, 3014U, 15009U,
6829 3911U, 16125U, 4158U, 16412U, 1945U, 4973U, 8118U, 16841U,
6830 1055U, 3484U, 7417U, 15631U, 4189U, 16452U, 4826U, 16722U,
6831 4834U, 16730U, 2159U, 5706U, 8598U, 17203U, 1969U, 5083U,
6832 8142U, 16874U, 3157U, 15131U, 9009U, 10711U, 9140U, 6929U,
6833 2956U, 6869U, 10994U, 1020U, 12982U, 3414U, 13459U, 7382U,
6834 13870U, 15376U, 14355U, 789U, 2993U, 6951U, 14998U, 13143U,
6835 13514U, 13917U, 14534U, 15525U, 14451U, 17058U, 1220U, 13105U,
6836 2041U, 4603U, 13678U, 5155U, 8523U, 14207U, 8326U, 15412U,
6837 14394U, 17009U, 1143U, 13048U, 1992U, 4528U, 13621U, 5106U,
6838 8438U, 14150U, 8277U, 958U, 3333U, 7320U, 10243U, 15297U,
6839 1312U, 14890U, 14853U, 1792U, 13226U, 4713U, 13721U, 7941U,
6840 14000U, 16608U, 14635U, 1091U, 13001U, 3692U, 13478U, 7453U,
6841 13889U, 15678U, 14498U, 1507U, 3998U, 7682U, 16222U, 1801U,
6842 4722U, 7950U, 16617U, 1597U, 4062U, 7746U, 16297U, 2095U,
6843 5349U, 8380U, 17112U, 1366U, 14861U, 1576U, 4041U, 7725U,
6844 16276U, 1928U, 4945U, 8101U, 16824U, 14872U, 14881U, 1726U,
6845 4385U, 7875U, 16520U, 2271U, 5752U, 8644U, 17249U, 2106U,
6846 13352U, 5369U, 13803U, 8391U, 14112U, 17123U, 14746U, 13253U,
6847 14027U, 14703U, 1028U, 7390U, 15550U, 13295U, 1245U, 13337U,
6848 14069U, 2133U, 8548U, 14676U, 15451U, 13268U, 1169U, 13749U,
6849 4554U, 14042U, 8464U, 13762U, 4565U, 1908U, 4903U, 8057U,
6850 16792U, 3277U, 11328U, 4915U, 12010U, 3642U, 11558U, 4439U,
6851 11900U, 3433U, 11397U, 4981U, 12037U, 3529U, 11467U, 4750U,
6852 11977U, 4473U, 11926U, 3492U, 11439U, 5015U, 12063U, 3568U,
6853 11506U, 4359U, 11851U, 3655U, 11571U, 4460U, 11913U, 3462U,
6854 11418U, 5002U, 12050U, 3555U, 11493U, 4770U, 11990U, 4487U,
6855 11940U, 3506U, 11453U, 5029U, 12077U, 3582U, 11520U, 4372U,
6856 11864U, 11364U, 8069U, 11376U, 8081U, 11591U, 4926U, 5360U,
6857 12156U, 15438U, 15475U, 9263U, 14251U, 9275U, 16804U, 14645U,
6858 3145U, 11288U, 3294U, 11337U, 3029U, 11268U, 5674U, 12241U,
6859 3002U, 11258U, 4334U, 11842U, 3173U, 11307U, 4205U, 11602U,
6860 3304U, 11347U, 3183U, 11317U, 3596U, 11534U, 4408U, 11877U,
6861 4310U, 11818U, 3542U, 11480U, 4419U, 11888U, 5801U, 12264U,
6862 5052U, 12091U, 3608U, 11546U, 5072U, 12111U, 1467U, 7642U,
6863 1743U, 7892U, 5062U, 12101U, 3164U, 11298U, 11670U, 11744U,
6864 11640U, 11714U, 4246U, 5524U, 12187U, 11624U, 11698U, 4231U,
6865 5405U, 12172U, 11655U, 11729U, 4260U, 5634U, 12201U, 11683U,
6866 11757U, 5200U, 4286U, 12141U, 5660U, 12227U, 5187U, 4274U,
6867 12128U, 5648U, 12215U, 14732U, 15575U, 13324U, 1270U, 13789U,
6868 4641U, 14098U, 8573U, 14718U, 15563U, 13310U, 1258U, 13775U,
6869 4629U, 14084U, 8561U, 1107U, 3722U, 7469U, 15723U, 1699U,
6870 4222U, 7848U, 16476U, 1877U, 4855U, 8026U, 16751U, 2735U,
6871 8763U, 1644U, 4145U, 7793U, 16399U, 17495U, 15511U, 14436U,
6872 17041U, 1206U, 13090U, 2024U, 4589U, 13663U, 5138U, 8509U,
6873 14192U, 8309U, 15398U, 14379U, 16992U, 1129U, 13033U, 1975U,
6874 4514U, 13606U, 5089U, 8424U, 14135U, 8260U, 940U, 3315U,
6875 7302U, 15279U, 1609U, 13183U, 4074U, 13554U, 7758U, 13957U,
6876 16309U, 14574U, 2146U, 13361U, 5691U, 13821U, 8585U, 14235U,
6877 17181U, 14764U, 1458U, 13163U, 3960U, 13534U, 7633U, 13937U,
6878 16184U, 14554U, 1718U, 13203U, 4351U, 13583U, 7867U, 13977U,
6879 16512U, 14611U, 1002U, 12973U, 3396U, 13450U, 7364U, 13861U,
6880 15358U, 14346U, 2197U, 2369U, 5825U, 8699U, 17310U, 2306U,
6881 861U, 3194U, 7023U, 15147U, 1099U, 13010U, 3707U, 13495U,
6882 7461U, 13898U, 15715U, 14515U, 15538U, 14465U, 17074U, 1233U,
6883 13119U, 2057U, 4616U, 13692U, 5171U, 8536U, 14221U, 8342U,
6884 15425U, 14408U, 17025U, 1156U, 13062U, 2008U, 4541U, 13635U,
6885 5122U, 8451U, 14164U, 8293U, 1691U, 4214U, 7840U, 16468U,
6886 1083U, 3684U, 7445U, 15670U, 1529U, 14907U, 1538U, 14899U,
6887 14915U, 2073U, 5327U, 8358U, 17090U, 980U, 3374U, 7342U,
6888 15336U, 1961U, 5043U, 8134U, 16857U, 16174U, 2084U, 5338U,
6889 8369U, 17101U, 991U, 3385U, 7353U, 15347U, 1778U, 13211U,
6890 4688U, 13706U, 7927U, 13985U, 16594U, 14620U, 1857U, 4841U,
6891 8006U, 16737U, 1344U, 3827U, 7531U, 16041U, 1063U, 3631U,
6892 7425U, 15650U, 1566U, 4031U, 7715U, 16266U, 1848U, 4810U,
6893 7997U, 16706U, 949U, 12957U, 3324U, 13440U, 7311U, 13845U,
6894 15288U, 14330U, 1920U, 13236U, 4937U, 13731U, 8093U, 14010U,
6895 16816U, 14658U, 1478U, 3969U, 7653U, 16193U, 1753U, 4452U,
6896 7902U, 16551U, 2257U, 5738U, 8630U, 17235U, 2349U, 5787U,
6897 8679U, 17284U, 14941U, 14930U, 1282U, 3757U, 7478U, 15971U,
6898 1074U, 3668U, 7436U, 15661U, 2114U, 5377U, 8399U, 17131U,
6899 1321U, 13153U, 3804U, 13524U, 7508U, 13927U, 16018U, 14544U,
6900 1048U, 12992U, 3454U, 13469U, 7410U, 13880U, 15624U, 14489U,
6901 1388U, 3869U, 7563U, 16083U, 14689U, 15462U, 13281U, 1180U,
6902 14055U, 8475U, 1636U, 4137U, 7785U, 16391U, 1588U, 13173U,
6903 4053U, 13544U, 7737U, 13947U, 16288U, 14564U, 1953U, 13245U,
6904 4994U, 13740U, 8126U, 14019U, 16849U, 14667U, 1303U, 3788U,
6905 7499U, 16002U, 7062U, 10264U, 15745U, 5433U, 7165U, 15848U,
6906 5550U, 1487U, 3978U, 7662U, 16202U, 7113U, 10315U, 15796U,
6907 5484U, 7212U, 15895U, 5597U, 1761U, 4653U, 7910U, 16559U,
6908 807U, 3021U, 6969U, 15025U, 1438U, 3919U, 7613U, 16143U,
6909 7087U, 10289U, 15770U, 5458U, 7188U, 15871U, 5573U, 1519U,
6910 4010U, 7694U, 16234U, 7140U, 10342U, 15823U, 5511U, 7237U,
6911 15920U, 5622U, 1812U, 4733U, 7961U, 16628U, 1664U, 4165U,
6912 7813U, 16428U, 8148U, 7049U, 10365U, 10251U, 16880U, 15732U,
6913 5215U, 5420U, 8206U, 7153U, 16938U, 15836U, 5273U, 5538U,
6914 8176U, 7099U, 10393U, 10301U, 16908U, 15782U, 5243U, 5470U,
6915 8232U, 7199U, 16964U, 15882U, 5299U, 5584U, 8162U, 7074U,
6916 10379U, 10276U, 16894U, 15757U, 5229U, 5445U, 8219U, 7176U,
6917 16951U, 15859U, 5286U, 5561U, 8191U, 7126U, 10408U, 10328U,
6918 16923U, 15809U, 5258U, 5497U, 8246U, 7224U, 16978U, 15907U,
6919 5313U, 5609U, 870U, 12947U, 3203U, 13420U, 7032U, 13835U,
6920 15156U, 14310U, 12883U, 1708U, 4300U, 7857U, 16485U, 17569U,
6921 13133U, 13504U, 13907U, 14524U, 15498U, 14422U, 1193U, 13076U,
6922 4576U, 13649U, 8496U, 14178U, 15385U, 14365U, 1116U, 13019U,
6923 4501U, 13592U, 8411U, 14121U, 879U, 3212U, 7041U, 10230U,
6924 15165U, 1546U, 14922U, 895U, 3235U, 7257U, 15211U, 922U,
6925 3267U, 13429U, 7284U, 15252U, 14319U, 970U, 3356U, 7332U,
6926 15309U, 9351U, 10075U, 904U, 3244U, 7266U, 15229U, 10085U,
6927 913U, 3253U, 7275U, 15238U, 6658U, 10095U, 6678U, 10104U,
6928 1681U, 13192U, 4195U, 13563U, 7830U, 13966U, 16458U, 14591U,
6929 1820U, 4741U, 7969U, 16636U, 1355U, 3838U, 7542U, 16052U,
6930 1617U, 4104U, 7766U, 16339U, 1496U, 3987U, 7671U, 16211U,
6931 1769U, 4661U, 7918U, 16567U, 1446U, 3927U, 7621U, 16151U,
6932 1671U, 4179U, 7820U, 16442U, 1554U, 4019U, 7703U, 16243U,
6933 1837U, 4799U, 7986U, 16685U, 886U, 3226U, 7248U, 15193U,
6934 6698U, 9360U, 1377U, 3858U, 7552U, 16062U, 1626U, 4127U,
6935 7775U, 16372U, 1292U, 3777U, 7488U, 15981U, 797U, 3011U,
6936 6959U, 15006U, 1427U, 3908U, 7602U, 16122U, 1654U, 4155U,
6937 7803U, 16409U, 851U, 3154U, 13409U, 7013U, 15128U, 14299U,
6938 1828U, 4782U, 7977U, 16659U, 10866U, 8781U, 1019U, 12981U,
6939 3413U, 13458U, 7381U, 13869U, 15375U, 14354U, 788U, 2992U,
6940 6950U, 14997U, 13142U, 13513U, 13916U, 14533U, 15524U, 14450U,
6941 17057U, 1219U, 13104U, 2040U, 4602U, 13677U, 5154U, 8522U,
6942 14206U, 8325U, 15411U, 14393U, 17008U, 1142U, 13047U, 1991U,
6943 4527U, 13620U, 5105U, 8437U, 14149U, 8276U, 957U, 3332U,
6944 7319U, 10242U, 15296U, 1311U, 14889U, 14852U, 1791U, 13225U,
6945 4712U, 13720U, 7940U, 13999U, 16607U, 14634U, 1090U, 13000U,
6946 3691U, 13477U, 7452U, 13888U, 15677U, 14497U, 1506U, 3997U,
6947 7681U, 16221U, 1800U, 4721U, 7949U, 16616U, 1596U, 4061U,
6948 7745U, 16296U, 2094U, 5348U, 8379U, 17111U, 1365U, 14860U,
6949 1575U, 4040U, 7724U, 16275U, 1927U, 4944U, 8100U, 16823U,
6950 14871U, 14880U, 1725U, 4384U, 7874U, 16519U, 2270U, 5751U,
6951 8643U, 17248U, 2105U, 13351U, 5368U, 13802U, 8390U, 14111U,
6952 17122U, 14745U, 14675U, 15450U, 13267U, 1168U, 13748U, 4553U,
6953 14041U, 8463U, 13761U, 4564U, 1907U, 4902U, 8056U, 16791U,
6954 3276U, 11327U, 4914U, 12009U, 3641U, 11557U, 4438U, 11899U,
6955 3432U, 11396U, 4980U, 12036U, 3528U, 11466U, 4749U, 11976U,
6956 4472U, 11925U, 3491U, 11438U, 5014U, 12062U, 3567U, 11505U,
6957 4358U, 11850U, 3654U, 11570U, 4459U, 11912U, 3461U, 11417U,
6958 5001U, 12049U, 3554U, 11492U, 4769U, 11989U, 4486U, 11939U,
6959 3505U, 11452U, 5028U, 12076U, 3581U, 11519U, 4371U, 11863U,
6960 11363U, 8068U, 11375U, 8080U, 11590U, 4925U, 5359U, 12155U,
6961 15437U, 15474U, 9262U, 14250U, 9274U, 16803U, 14644U, 3144U,
6962 11287U, 3293U, 11336U, 3028U, 11267U, 5673U, 12240U, 3001U,
6963 11257U, 4333U, 11841U, 3172U, 11306U, 4204U, 11601U, 3303U,
6964 11346U, 3182U, 11316U, 3595U, 11533U, 4407U, 11876U, 4309U,
6965 11817U, 3541U, 11479U, 4418U, 11887U, 5800U, 12263U, 5051U,
6966 12090U, 3607U, 11545U, 5071U, 12110U, 1466U, 7641U, 1742U,
6967 7891U, 5061U, 12100U, 3163U, 11297U, 11669U, 11743U, 11639U,
6968 11713U, 4245U, 5523U, 12186U, 11623U, 11697U, 4230U, 5404U,
6969 12171U, 11654U, 11728U, 4259U, 5633U, 12200U, 11682U, 11756U,
6970 5199U, 4285U, 12140U, 5659U, 12226U, 5186U, 4273U, 12127U,
6971 5647U, 12214U, 14731U, 15574U, 13323U, 1269U, 13788U, 4640U,
6972 14097U, 8572U, 3848U, 14717U, 15562U, 13309U, 1257U, 13774U,
6973 4628U, 14083U, 8560U, 1106U, 3721U, 7468U, 15722U, 1698U,
6974 4221U, 7847U, 16475U, 4854U, 16750U, 2981U, 14986U, 2734U,
6975 8762U, 1643U, 4144U, 7792U, 16398U, 17494U, 15510U, 14435U,
6976 17040U, 1205U, 13089U, 2023U, 4588U, 13662U, 5137U, 8508U,
6977 14191U, 8308U, 15397U, 14378U, 16991U, 1128U, 13032U, 1974U,
6978 4513U, 13605U, 5088U, 8423U, 14134U, 8259U, 939U, 3314U,
6979 7301U, 15278U, 1608U, 13182U, 4073U, 13553U, 7757U, 13956U,
6980 16308U, 14573U, 2145U, 13360U, 5690U, 13820U, 8584U, 14234U,
6981 17180U, 14763U, 1457U, 13162U, 3959U, 13533U, 7632U, 13936U,
6982 16183U, 14553U, 1717U, 13202U, 4350U, 13582U, 7866U, 13976U,
6983 16511U, 14610U, 1001U, 12972U, 3395U, 13449U, 7363U, 13860U,
6984 15357U, 14345U, 2196U, 2368U, 5824U, 8698U, 17309U, 2305U,
6985 860U, 3193U, 7022U, 15146U, 1098U, 13009U, 3706U, 13494U,
6986 7460U, 13897U, 15714U, 14514U, 15537U, 14464U, 17073U, 1232U,
6987 13118U, 2056U, 4615U, 13691U, 5170U, 8535U, 14220U, 8341U,
6988 15424U, 14407U, 17024U, 1155U, 13061U, 2007U, 4540U, 13634U,
6989 5121U, 8450U, 14163U, 8292U, 1690U, 4213U, 7839U, 16467U,
6990 1082U, 3683U, 7444U, 15669U, 1528U, 14906U, 1537U, 14898U,
6991 14914U, 2072U, 5326U, 8357U, 17089U, 979U, 3373U, 7341U,
6992 15335U, 1960U, 5042U, 8133U, 16856U, 3949U, 10354U, 16173U,
6993 16494U, 2083U, 5337U, 8368U, 17100U, 990U, 3384U, 7352U,
6994 15346U, 4687U, 13705U, 16593U, 14619U, 3619U, 15638U, 1329U,
6995 3812U, 7516U, 16026U, 1856U, 4840U, 8005U, 16736U, 776U,
6996 2969U, 6938U, 10217U, 14974U, 1062U, 3630U, 7424U, 15649U,
6997 1565U, 4030U, 7714U, 16265U, 1847U, 4809U, 7996U, 16705U,
6998 948U, 12956U, 3323U, 13439U, 7310U, 13844U, 15287U, 14329U,
6999 1919U, 13235U, 4936U, 13730U, 8092U, 14009U, 16815U, 14657U,
7000 1477U, 3968U, 7652U, 16192U, 1752U, 4451U, 7901U, 16550U,
7001 2256U, 5737U, 8629U, 17234U, 2348U, 5786U, 8678U, 17283U,
7002 14940U, 14929U, 1281U, 3756U, 7477U, 15970U, 1073U, 3667U,
7003 7435U, 15660U, 2113U, 5376U, 8398U, 17130U, 1320U, 13152U,
7004 3803U, 13523U, 7507U, 13926U, 16017U, 14543U, 1047U, 12991U,
7005 3453U, 13468U, 7409U, 13879U, 15623U, 14488U, 1387U, 3868U,
7006 7562U, 16082U, 14688U, 15461U, 13280U, 1179U, 14054U, 8474U,
7007 1635U, 4136U, 7784U, 16390U, 1587U, 13172U, 4052U, 13543U,
7008 7736U, 13946U, 16287U, 14563U, 1952U, 13244U, 4993U, 13739U,
7009 8125U, 14018U, 16848U, 14666U, 1302U, 3787U, 7498U, 16001U,
7010 7061U, 10263U, 15744U, 5432U, 7164U, 15847U, 5549U, 1486U,
7011 3977U, 7661U, 16201U, 7112U, 10314U, 15795U, 5483U, 7211U,
7012 15894U, 5596U, 1760U, 4652U, 7909U, 16558U, 806U, 3020U,
7013 6968U, 15024U, 1437U, 3918U, 7612U, 16142U, 7086U, 10288U,
7014 15769U, 5457U, 7187U, 15870U, 5572U, 1518U, 4009U, 7693U,
7015 16233U, 7139U, 10341U, 15822U, 5510U, 7236U, 15919U, 5621U,
7016 1811U, 4732U, 7960U, 16627U, 1663U, 4164U, 7812U, 16427U,
7017 8147U, 7048U, 10364U, 10250U, 16879U, 15731U, 5214U, 5419U,
7018 8205U, 7152U, 16937U, 15835U, 5272U, 5537U, 8175U, 7098U,
7019 10392U, 10300U, 16907U, 15781U, 5242U, 5469U, 8231U, 7198U,
7020 16963U, 15881U, 5298U, 5583U, 8161U, 7073U, 10378U, 10275U,
7021 16893U, 15756U, 5228U, 5444U, 8218U, 7175U, 16950U, 15858U,
7022 5285U, 5560U, 8190U, 7125U, 10407U, 10327U, 16922U, 15808U,
7023 5257U, 5496U, 8245U, 7223U, 16977U, 15906U, 5312U, 5608U,
7024 869U, 12946U, 3202U, 13419U, 7031U, 13834U, 15155U, 14309U,
7025 12882U, 1707U, 4299U, 7856U, 16484U, 17568U, 13132U, 13503U,
7026 13906U, 14523U, 15497U, 14421U, 1192U, 13075U, 4575U, 13648U,
7027 8495U, 14177U, 15384U, 14364U, 1115U, 13018U, 4500U, 13591U,
7028 8410U, 14120U, 878U, 3211U, 7040U, 10229U, 15164U, 1545U,
7029 14921U,
7030};
7031
7032static inline void InitLoongArchMCInstrInfo(MCInstrInfo *II) {
7033 II->InitMCInstrInfo(LoongArchDescs.Insts, LoongArchInstrNameIndices, LoongArchInstrNameData, nullptr, nullptr, 2465);
7034}
7035
7036} // end namespace llvm
7037#endif // GET_INSTRINFO_MC_DESC
7038
7039#ifdef GET_INSTRINFO_HEADER
7040#undef GET_INSTRINFO_HEADER
7041namespace llvm {
7042struct LoongArchGenInstrInfo : public TargetInstrInfo {
7043 explicit LoongArchGenInstrInfo(unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u);
7044 ~LoongArchGenInstrInfo() override = default;
7045
7046};
7047} // end namespace llvm
7048#endif // GET_INSTRINFO_HEADER
7049
7050#ifdef GET_INSTRINFO_HELPER_DECLS
7051#undef GET_INSTRINFO_HELPER_DECLS
7052
7053
7054#endif // GET_INSTRINFO_HELPER_DECLS
7055
7056#ifdef GET_INSTRINFO_HELPERS
7057#undef GET_INSTRINFO_HELPERS
7058
7059#endif // GET_INSTRINFO_HELPERS
7060
7061#ifdef GET_INSTRINFO_CTOR_DTOR
7062#undef GET_INSTRINFO_CTOR_DTOR
7063namespace llvm {
7064extern const LoongArchInstrTable LoongArchDescs;
7065extern const unsigned LoongArchInstrNameIndices[];
7066extern const char LoongArchInstrNameData[];
7067LoongArchGenInstrInfo::LoongArchGenInstrInfo(unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode)
7068 : TargetInstrInfo(CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {
7069 InitMCInstrInfo(LoongArchDescs.Insts, LoongArchInstrNameIndices, LoongArchInstrNameData, nullptr, nullptr, 2465);
7070}
7071} // end namespace llvm
7072#endif // GET_INSTRINFO_CTOR_DTOR
7073
7074#ifdef GET_INSTRINFO_MC_HELPER_DECLS
7075#undef GET_INSTRINFO_MC_HELPER_DECLS
7076
7077namespace llvm {
7078class MCInst;
7079class FeatureBitset;
7080
7081namespace LoongArch_MC {
7082
7083void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features);
7084
7085} // end namespace LoongArch_MC
7086} // end namespace llvm
7087
7088#endif // GET_INSTRINFO_MC_HELPER_DECLS
7089
7090#ifdef GET_INSTRINFO_MC_HELPERS
7091#undef GET_INSTRINFO_MC_HELPERS
7092
7093namespace llvm::LoongArch_MC {
7094} // end namespace llvm::LoongArch_MC
7095#endif // GET_GENISTRINFO_MC_HELPERS
7096
7097#if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) ||\
7098 defined(GET_AVAILABLE_OPCODE_CHECKER)
7099#define GET_COMPUTE_FEATURES
7100#endif
7101#ifdef GET_COMPUTE_FEATURES
7102#undef GET_COMPUTE_FEATURES
7103namespace llvm::LoongArch_MC {
7104// Bits for subtarget features that participate in instruction matching.
7105enum SubtargetFeatureBits : uint8_t {
7106 Feature_IsLA64Bit = 4,
7107 Feature_IsLA32Bit = 3,
7108 Feature_HasLaGlobalWithPcrelBit = 1,
7109 Feature_HasLaGlobalWithAbsBit = 0,
7110 Feature_HasLaLocalWithAbsBit = 2,
7111};
7112
7113inline FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) {
7114 FeatureBitset Features;
7115 if (FB[LoongArch::Feature64Bit])
7116 Features.set(Feature_IsLA64Bit);
7117 if (!FB[LoongArch::Feature64Bit])
7118 Features.set(Feature_IsLA32Bit);
7119 if (FB[LoongArch::LaGlobalWithPcrel])
7120 Features.set(Feature_HasLaGlobalWithPcrelBit);
7121 if (FB[LoongArch::LaGlobalWithAbs])
7122 Features.set(Feature_HasLaGlobalWithAbsBit);
7123 if (FB[LoongArch::LaLocalWithAbs])
7124 Features.set(Feature_HasLaLocalWithAbsBit);
7125 return Features;
7126}
7127
7128inline FeatureBitset computeRequiredFeatures(unsigned Opcode) {
7129 enum : uint8_t {
7130 CEFBS_None,
7131 CEFBS_IsLA32,
7132 CEFBS_IsLA64,
7133 };
7134
7135 static constexpr FeatureBitset FeatureBitsets[] = {
7136 {}, // CEFBS_None
7137 {Feature_IsLA32Bit, },
7138 {Feature_IsLA64Bit, },
7139 };
7140 static constexpr uint8_t RequiredFeaturesRefs[] = {
7141 CEFBS_None, // PHI = 0
7142 CEFBS_None, // INLINEASM = 1
7143 CEFBS_None, // INLINEASM_BR = 2
7144 CEFBS_None, // CFI_INSTRUCTION = 3
7145 CEFBS_None, // EH_LABEL = 4
7146 CEFBS_None, // GC_LABEL = 5
7147 CEFBS_None, // ANNOTATION_LABEL = 6
7148 CEFBS_None, // KILL = 7
7149 CEFBS_None, // EXTRACT_SUBREG = 8
7150 CEFBS_None, // INSERT_SUBREG = 9
7151 CEFBS_None, // IMPLICIT_DEF = 10
7152 CEFBS_None, // INIT_UNDEF = 11
7153 CEFBS_None, // SUBREG_TO_REG = 12
7154 CEFBS_None, // COPY_TO_REGCLASS = 13
7155 CEFBS_None, // DBG_VALUE = 14
7156 CEFBS_None, // DBG_VALUE_LIST = 15
7157 CEFBS_None, // DBG_INSTR_REF = 16
7158 CEFBS_None, // DBG_PHI = 17
7159 CEFBS_None, // DBG_LABEL = 18
7160 CEFBS_None, // REG_SEQUENCE = 19
7161 CEFBS_None, // COPY = 20
7162 CEFBS_None, // BUNDLE = 21
7163 CEFBS_None, // LIFETIME_START = 22
7164 CEFBS_None, // LIFETIME_END = 23
7165 CEFBS_None, // PSEUDO_PROBE = 24
7166 CEFBS_None, // ARITH_FENCE = 25
7167 CEFBS_None, // STACKMAP = 26
7168 CEFBS_None, // FENTRY_CALL = 27
7169 CEFBS_None, // PATCHPOINT = 28
7170 CEFBS_None, // LOAD_STACK_GUARD = 29
7171 CEFBS_None, // PREALLOCATED_SETUP = 30
7172 CEFBS_None, // PREALLOCATED_ARG = 31
7173 CEFBS_None, // STATEPOINT = 32
7174 CEFBS_None, // LOCAL_ESCAPE = 33
7175 CEFBS_None, // FAULTING_OP = 34
7176 CEFBS_None, // PATCHABLE_OP = 35
7177 CEFBS_None, // PATCHABLE_FUNCTION_ENTER = 36
7178 CEFBS_None, // PATCHABLE_RET = 37
7179 CEFBS_None, // PATCHABLE_FUNCTION_EXIT = 38
7180 CEFBS_None, // PATCHABLE_TAIL_CALL = 39
7181 CEFBS_None, // PATCHABLE_EVENT_CALL = 40
7182 CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL = 41
7183 CEFBS_None, // ICALL_BRANCH_FUNNEL = 42
7184 CEFBS_None, // FAKE_USE = 43
7185 CEFBS_None, // MEMBARRIER = 44
7186 CEFBS_None, // JUMP_TABLE_DEBUG_INFO = 45
7187 CEFBS_None, // CONVERGENCECTRL_ENTRY = 46
7188 CEFBS_None, // CONVERGENCECTRL_ANCHOR = 47
7189 CEFBS_None, // CONVERGENCECTRL_LOOP = 48
7190 CEFBS_None, // CONVERGENCECTRL_GLUE = 49
7191 CEFBS_None, // G_ASSERT_SEXT = 50
7192 CEFBS_None, // G_ASSERT_ZEXT = 51
7193 CEFBS_None, // G_ASSERT_ALIGN = 52
7194 CEFBS_None, // G_ADD = 53
7195 CEFBS_None, // G_SUB = 54
7196 CEFBS_None, // G_MUL = 55
7197 CEFBS_None, // G_SDIV = 56
7198 CEFBS_None, // G_UDIV = 57
7199 CEFBS_None, // G_SREM = 58
7200 CEFBS_None, // G_UREM = 59
7201 CEFBS_None, // G_SDIVREM = 60
7202 CEFBS_None, // G_UDIVREM = 61
7203 CEFBS_None, // G_AND = 62
7204 CEFBS_None, // G_OR = 63
7205 CEFBS_None, // G_XOR = 64
7206 CEFBS_None, // G_ABDS = 65
7207 CEFBS_None, // G_ABDU = 66
7208 CEFBS_None, // G_IMPLICIT_DEF = 67
7209 CEFBS_None, // G_PHI = 68
7210 CEFBS_None, // G_FRAME_INDEX = 69
7211 CEFBS_None, // G_GLOBAL_VALUE = 70
7212 CEFBS_None, // G_PTRAUTH_GLOBAL_VALUE = 71
7213 CEFBS_None, // G_CONSTANT_POOL = 72
7214 CEFBS_None, // G_EXTRACT = 73
7215 CEFBS_None, // G_UNMERGE_VALUES = 74
7216 CEFBS_None, // G_INSERT = 75
7217 CEFBS_None, // G_MERGE_VALUES = 76
7218 CEFBS_None, // G_BUILD_VECTOR = 77
7219 CEFBS_None, // G_BUILD_VECTOR_TRUNC = 78
7220 CEFBS_None, // G_CONCAT_VECTORS = 79
7221 CEFBS_None, // G_PTRTOINT = 80
7222 CEFBS_None, // G_INTTOPTR = 81
7223 CEFBS_None, // G_BITCAST = 82
7224 CEFBS_None, // G_FREEZE = 83
7225 CEFBS_None, // G_CONSTANT_FOLD_BARRIER = 84
7226 CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND = 85
7227 CEFBS_None, // G_INTRINSIC_TRUNC = 86
7228 CEFBS_None, // G_INTRINSIC_ROUND = 87
7229 CEFBS_None, // G_INTRINSIC_LRINT = 88
7230 CEFBS_None, // G_INTRINSIC_LLRINT = 89
7231 CEFBS_None, // G_INTRINSIC_ROUNDEVEN = 90
7232 CEFBS_None, // G_READCYCLECOUNTER = 91
7233 CEFBS_None, // G_READSTEADYCOUNTER = 92
7234 CEFBS_None, // G_LOAD = 93
7235 CEFBS_None, // G_SEXTLOAD = 94
7236 CEFBS_None, // G_ZEXTLOAD = 95
7237 CEFBS_None, // G_INDEXED_LOAD = 96
7238 CEFBS_None, // G_INDEXED_SEXTLOAD = 97
7239 CEFBS_None, // G_INDEXED_ZEXTLOAD = 98
7240 CEFBS_None, // G_STORE = 99
7241 CEFBS_None, // G_INDEXED_STORE = 100
7242 CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS = 101
7243 CEFBS_None, // G_ATOMIC_CMPXCHG = 102
7244 CEFBS_None, // G_ATOMICRMW_XCHG = 103
7245 CEFBS_None, // G_ATOMICRMW_ADD = 104
7246 CEFBS_None, // G_ATOMICRMW_SUB = 105
7247 CEFBS_None, // G_ATOMICRMW_AND = 106
7248 CEFBS_None, // G_ATOMICRMW_NAND = 107
7249 CEFBS_None, // G_ATOMICRMW_OR = 108
7250 CEFBS_None, // G_ATOMICRMW_XOR = 109
7251 CEFBS_None, // G_ATOMICRMW_MAX = 110
7252 CEFBS_None, // G_ATOMICRMW_MIN = 111
7253 CEFBS_None, // G_ATOMICRMW_UMAX = 112
7254 CEFBS_None, // G_ATOMICRMW_UMIN = 113
7255 CEFBS_None, // G_ATOMICRMW_FADD = 114
7256 CEFBS_None, // G_ATOMICRMW_FSUB = 115
7257 CEFBS_None, // G_ATOMICRMW_FMAX = 116
7258 CEFBS_None, // G_ATOMICRMW_FMIN = 117
7259 CEFBS_None, // G_ATOMICRMW_FMAXIMUM = 118
7260 CEFBS_None, // G_ATOMICRMW_FMINIMUM = 119
7261 CEFBS_None, // G_ATOMICRMW_UINC_WRAP = 120
7262 CEFBS_None, // G_ATOMICRMW_UDEC_WRAP = 121
7263 CEFBS_None, // G_ATOMICRMW_USUB_COND = 122
7264 CEFBS_None, // G_ATOMICRMW_USUB_SAT = 123
7265 CEFBS_None, // G_FENCE = 124
7266 CEFBS_None, // G_PREFETCH = 125
7267 CEFBS_None, // G_BRCOND = 126
7268 CEFBS_None, // G_BRINDIRECT = 127
7269 CEFBS_None, // G_INVOKE_REGION_START = 128
7270 CEFBS_None, // G_INTRINSIC = 129
7271 CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS = 130
7272 CEFBS_None, // G_INTRINSIC_CONVERGENT = 131
7273 CEFBS_None, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 132
7274 CEFBS_None, // G_ANYEXT = 133
7275 CEFBS_None, // G_TRUNC = 134
7276 CEFBS_None, // G_CONSTANT = 135
7277 CEFBS_None, // G_FCONSTANT = 136
7278 CEFBS_None, // G_VASTART = 137
7279 CEFBS_None, // G_VAARG = 138
7280 CEFBS_None, // G_SEXT = 139
7281 CEFBS_None, // G_SEXT_INREG = 140
7282 CEFBS_None, // G_ZEXT = 141
7283 CEFBS_None, // G_SHL = 142
7284 CEFBS_None, // G_LSHR = 143
7285 CEFBS_None, // G_ASHR = 144
7286 CEFBS_None, // G_FSHL = 145
7287 CEFBS_None, // G_FSHR = 146
7288 CEFBS_None, // G_ROTR = 147
7289 CEFBS_None, // G_ROTL = 148
7290 CEFBS_None, // G_ICMP = 149
7291 CEFBS_None, // G_FCMP = 150
7292 CEFBS_None, // G_SCMP = 151
7293 CEFBS_None, // G_UCMP = 152
7294 CEFBS_None, // G_SELECT = 153
7295 CEFBS_None, // G_UADDO = 154
7296 CEFBS_None, // G_UADDE = 155
7297 CEFBS_None, // G_USUBO = 156
7298 CEFBS_None, // G_USUBE = 157
7299 CEFBS_None, // G_SADDO = 158
7300 CEFBS_None, // G_SADDE = 159
7301 CEFBS_None, // G_SSUBO = 160
7302 CEFBS_None, // G_SSUBE = 161
7303 CEFBS_None, // G_UMULO = 162
7304 CEFBS_None, // G_SMULO = 163
7305 CEFBS_None, // G_UMULH = 164
7306 CEFBS_None, // G_SMULH = 165
7307 CEFBS_None, // G_UADDSAT = 166
7308 CEFBS_None, // G_SADDSAT = 167
7309 CEFBS_None, // G_USUBSAT = 168
7310 CEFBS_None, // G_SSUBSAT = 169
7311 CEFBS_None, // G_USHLSAT = 170
7312 CEFBS_None, // G_SSHLSAT = 171
7313 CEFBS_None, // G_SMULFIX = 172
7314 CEFBS_None, // G_UMULFIX = 173
7315 CEFBS_None, // G_SMULFIXSAT = 174
7316 CEFBS_None, // G_UMULFIXSAT = 175
7317 CEFBS_None, // G_SDIVFIX = 176
7318 CEFBS_None, // G_UDIVFIX = 177
7319 CEFBS_None, // G_SDIVFIXSAT = 178
7320 CEFBS_None, // G_UDIVFIXSAT = 179
7321 CEFBS_None, // G_FADD = 180
7322 CEFBS_None, // G_FSUB = 181
7323 CEFBS_None, // G_FMUL = 182
7324 CEFBS_None, // G_FMA = 183
7325 CEFBS_None, // G_FMAD = 184
7326 CEFBS_None, // G_FDIV = 185
7327 CEFBS_None, // G_FREM = 186
7328 CEFBS_None, // G_FPOW = 187
7329 CEFBS_None, // G_FPOWI = 188
7330 CEFBS_None, // G_FEXP = 189
7331 CEFBS_None, // G_FEXP2 = 190
7332 CEFBS_None, // G_FEXP10 = 191
7333 CEFBS_None, // G_FLOG = 192
7334 CEFBS_None, // G_FLOG2 = 193
7335 CEFBS_None, // G_FLOG10 = 194
7336 CEFBS_None, // G_FLDEXP = 195
7337 CEFBS_None, // G_FFREXP = 196
7338 CEFBS_None, // G_FNEG = 197
7339 CEFBS_None, // G_FPEXT = 198
7340 CEFBS_None, // G_FPTRUNC = 199
7341 CEFBS_None, // G_FPTOSI = 200
7342 CEFBS_None, // G_FPTOUI = 201
7343 CEFBS_None, // G_SITOFP = 202
7344 CEFBS_None, // G_UITOFP = 203
7345 CEFBS_None, // G_FPTOSI_SAT = 204
7346 CEFBS_None, // G_FPTOUI_SAT = 205
7347 CEFBS_None, // G_FABS = 206
7348 CEFBS_None, // G_FCOPYSIGN = 207
7349 CEFBS_None, // G_IS_FPCLASS = 208
7350 CEFBS_None, // G_FCANONICALIZE = 209
7351 CEFBS_None, // G_FMINNUM = 210
7352 CEFBS_None, // G_FMAXNUM = 211
7353 CEFBS_None, // G_FMINNUM_IEEE = 212
7354 CEFBS_None, // G_FMAXNUM_IEEE = 213
7355 CEFBS_None, // G_FMINIMUM = 214
7356 CEFBS_None, // G_FMAXIMUM = 215
7357 CEFBS_None, // G_FMINIMUMNUM = 216
7358 CEFBS_None, // G_FMAXIMUMNUM = 217
7359 CEFBS_None, // G_GET_FPENV = 218
7360 CEFBS_None, // G_SET_FPENV = 219
7361 CEFBS_None, // G_RESET_FPENV = 220
7362 CEFBS_None, // G_GET_FPMODE = 221
7363 CEFBS_None, // G_SET_FPMODE = 222
7364 CEFBS_None, // G_RESET_FPMODE = 223
7365 CEFBS_None, // G_PTR_ADD = 224
7366 CEFBS_None, // G_PTRMASK = 225
7367 CEFBS_None, // G_SMIN = 226
7368 CEFBS_None, // G_SMAX = 227
7369 CEFBS_None, // G_UMIN = 228
7370 CEFBS_None, // G_UMAX = 229
7371 CEFBS_None, // G_ABS = 230
7372 CEFBS_None, // G_LROUND = 231
7373 CEFBS_None, // G_LLROUND = 232
7374 CEFBS_None, // G_BR = 233
7375 CEFBS_None, // G_BRJT = 234
7376 CEFBS_None, // G_VSCALE = 235
7377 CEFBS_None, // G_INSERT_SUBVECTOR = 236
7378 CEFBS_None, // G_EXTRACT_SUBVECTOR = 237
7379 CEFBS_None, // G_INSERT_VECTOR_ELT = 238
7380 CEFBS_None, // G_EXTRACT_VECTOR_ELT = 239
7381 CEFBS_None, // G_SHUFFLE_VECTOR = 240
7382 CEFBS_None, // G_SPLAT_VECTOR = 241
7383 CEFBS_None, // G_STEP_VECTOR = 242
7384 CEFBS_None, // G_VECTOR_COMPRESS = 243
7385 CEFBS_None, // G_CTTZ = 244
7386 CEFBS_None, // G_CTTZ_ZERO_UNDEF = 245
7387 CEFBS_None, // G_CTLZ = 246
7388 CEFBS_None, // G_CTLZ_ZERO_UNDEF = 247
7389 CEFBS_None, // G_CTPOP = 248
7390 CEFBS_None, // G_BSWAP = 249
7391 CEFBS_None, // G_BITREVERSE = 250
7392 CEFBS_None, // G_FCEIL = 251
7393 CEFBS_None, // G_FCOS = 252
7394 CEFBS_None, // G_FSIN = 253
7395 CEFBS_None, // G_FSINCOS = 254
7396 CEFBS_None, // G_FTAN = 255
7397 CEFBS_None, // G_FACOS = 256
7398 CEFBS_None, // G_FASIN = 257
7399 CEFBS_None, // G_FATAN = 258
7400 CEFBS_None, // G_FATAN2 = 259
7401 CEFBS_None, // G_FCOSH = 260
7402 CEFBS_None, // G_FSINH = 261
7403 CEFBS_None, // G_FTANH = 262
7404 CEFBS_None, // G_FSQRT = 263
7405 CEFBS_None, // G_FFLOOR = 264
7406 CEFBS_None, // G_FRINT = 265
7407 CEFBS_None, // G_FNEARBYINT = 266
7408 CEFBS_None, // G_ADDRSPACE_CAST = 267
7409 CEFBS_None, // G_BLOCK_ADDR = 268
7410 CEFBS_None, // G_JUMP_TABLE = 269
7411 CEFBS_None, // G_DYN_STACKALLOC = 270
7412 CEFBS_None, // G_STACKSAVE = 271
7413 CEFBS_None, // G_STACKRESTORE = 272
7414 CEFBS_None, // G_STRICT_FADD = 273
7415 CEFBS_None, // G_STRICT_FSUB = 274
7416 CEFBS_None, // G_STRICT_FMUL = 275
7417 CEFBS_None, // G_STRICT_FDIV = 276
7418 CEFBS_None, // G_STRICT_FREM = 277
7419 CEFBS_None, // G_STRICT_FMA = 278
7420 CEFBS_None, // G_STRICT_FSQRT = 279
7421 CEFBS_None, // G_STRICT_FLDEXP = 280
7422 CEFBS_None, // G_READ_REGISTER = 281
7423 CEFBS_None, // G_WRITE_REGISTER = 282
7424 CEFBS_None, // G_MEMCPY = 283
7425 CEFBS_None, // G_MEMCPY_INLINE = 284
7426 CEFBS_None, // G_MEMMOVE = 285
7427 CEFBS_None, // G_MEMSET = 286
7428 CEFBS_None, // G_BZERO = 287
7429 CEFBS_None, // G_TRAP = 288
7430 CEFBS_None, // G_DEBUGTRAP = 289
7431 CEFBS_None, // G_UBSANTRAP = 290
7432 CEFBS_None, // G_VECREDUCE_SEQ_FADD = 291
7433 CEFBS_None, // G_VECREDUCE_SEQ_FMUL = 292
7434 CEFBS_None, // G_VECREDUCE_FADD = 293
7435 CEFBS_None, // G_VECREDUCE_FMUL = 294
7436 CEFBS_None, // G_VECREDUCE_FMAX = 295
7437 CEFBS_None, // G_VECREDUCE_FMIN = 296
7438 CEFBS_None, // G_VECREDUCE_FMAXIMUM = 297
7439 CEFBS_None, // G_VECREDUCE_FMINIMUM = 298
7440 CEFBS_None, // G_VECREDUCE_ADD = 299
7441 CEFBS_None, // G_VECREDUCE_MUL = 300
7442 CEFBS_None, // G_VECREDUCE_AND = 301
7443 CEFBS_None, // G_VECREDUCE_OR = 302
7444 CEFBS_None, // G_VECREDUCE_XOR = 303
7445 CEFBS_None, // G_VECREDUCE_SMAX = 304
7446 CEFBS_None, // G_VECREDUCE_SMIN = 305
7447 CEFBS_None, // G_VECREDUCE_UMAX = 306
7448 CEFBS_None, // G_VECREDUCE_UMIN = 307
7449 CEFBS_None, // G_SBFX = 308
7450 CEFBS_None, // G_UBFX = 309
7451 CEFBS_None, // ADJCALLSTACKDOWN = 310
7452 CEFBS_None, // ADJCALLSTACKUP = 311
7453 CEFBS_IsLA32, // BuildPairF64Pseudo = 312
7454 CEFBS_IsLA64, // PseudoAddTPRel_D = 313
7455 CEFBS_IsLA32, // PseudoAddTPRel_W = 314
7456 CEFBS_None, // PseudoAtomicLoadAdd32 = 315
7457 CEFBS_None, // PseudoAtomicLoadAnd32 = 316
7458 CEFBS_None, // PseudoAtomicLoadMax32 = 317
7459 CEFBS_None, // PseudoAtomicLoadMin32 = 318
7460 CEFBS_None, // PseudoAtomicLoadNand32 = 319
7461 CEFBS_None, // PseudoAtomicLoadNand64 = 320
7462 CEFBS_None, // PseudoAtomicLoadOr32 = 321
7463 CEFBS_None, // PseudoAtomicLoadSub32 = 322
7464 CEFBS_None, // PseudoAtomicLoadUMax32 = 323
7465 CEFBS_None, // PseudoAtomicLoadUMin32 = 324
7466 CEFBS_None, // PseudoAtomicLoadXor32 = 325
7467 CEFBS_IsLA64, // PseudoAtomicStoreD = 326
7468 CEFBS_None, // PseudoAtomicStoreW = 327
7469 CEFBS_None, // PseudoAtomicSwap32 = 328
7470 CEFBS_None, // PseudoBR = 329
7471 CEFBS_None, // PseudoBRIND = 330
7472 CEFBS_None, // PseudoB_TAIL = 331
7473 CEFBS_None, // PseudoCALL = 332
7474 CEFBS_IsLA64, // PseudoCALL36 = 333
7475 CEFBS_None, // PseudoCALLIndirect = 334
7476 CEFBS_None, // PseudoCALL_LARGE = 335
7477 CEFBS_None, // PseudoCALL_MEDIUM = 336
7478 CEFBS_None, // PseudoCTPOP = 337
7479 CEFBS_None, // PseudoCmpXchg128 = 338
7480 CEFBS_None, // PseudoCmpXchg128Acquire = 339
7481 CEFBS_None, // PseudoCmpXchg32 = 340
7482 CEFBS_None, // PseudoCmpXchg64 = 341
7483 CEFBS_None, // PseudoCopyCFR = 342
7484 CEFBS_None, // PseudoDESC_CALL = 343
7485 CEFBS_None, // PseudoJIRL_CALL = 344
7486 CEFBS_None, // PseudoJIRL_TAIL = 345
7487 CEFBS_None, // PseudoLA_ABS = 346
7488 CEFBS_None, // PseudoLA_ABS_LARGE = 347
7489 CEFBS_None, // PseudoLA_GOT = 348
7490 CEFBS_IsLA64, // PseudoLA_GOT_LARGE = 349
7491 CEFBS_None, // PseudoLA_PCREL = 350
7492 CEFBS_IsLA64, // PseudoLA_PCREL_LARGE = 351
7493 CEFBS_None, // PseudoLA_TLS_DESC = 352
7494 CEFBS_IsLA64, // PseudoLA_TLS_DESC_LARGE = 353
7495 CEFBS_None, // PseudoLA_TLS_GD = 354
7496 CEFBS_IsLA64, // PseudoLA_TLS_GD_LARGE = 355
7497 CEFBS_None, // PseudoLA_TLS_IE = 356
7498 CEFBS_IsLA64, // PseudoLA_TLS_IE_LARGE = 357
7499 CEFBS_None, // PseudoLA_TLS_LD = 358
7500 CEFBS_IsLA64, // PseudoLA_TLS_LD_LARGE = 359
7501 CEFBS_None, // PseudoLA_TLS_LE = 360
7502 CEFBS_None, // PseudoLD_CFR = 361
7503 CEFBS_IsLA64, // PseudoLI_D = 362
7504 CEFBS_None, // PseudoLI_W = 363
7505 CEFBS_None, // PseudoMaskedAtomicLoadAdd32 = 364
7506 CEFBS_None, // PseudoMaskedAtomicLoadMax32 = 365
7507 CEFBS_None, // PseudoMaskedAtomicLoadMin32 = 366
7508 CEFBS_None, // PseudoMaskedAtomicLoadNand32 = 367
7509 CEFBS_None, // PseudoMaskedAtomicLoadSub32 = 368
7510 CEFBS_None, // PseudoMaskedAtomicLoadUMax32 = 369
7511 CEFBS_None, // PseudoMaskedAtomicLoadUMin32 = 370
7512 CEFBS_None, // PseudoMaskedAtomicSwap32 = 371
7513 CEFBS_None, // PseudoMaskedCmpXchg32 = 372
7514 CEFBS_None, // PseudoRET = 373
7515 CEFBS_None, // PseudoST_CFR = 374
7516 CEFBS_None, // PseudoTAIL = 375
7517 CEFBS_IsLA64, // PseudoTAIL36 = 376
7518 CEFBS_None, // PseudoTAILIndirect = 377
7519 CEFBS_None, // PseudoTAIL_LARGE = 378
7520 CEFBS_None, // PseudoTAIL_MEDIUM = 379
7521 CEFBS_None, // PseudoUNIMP = 380
7522 CEFBS_None, // PseudoVBNZ = 381
7523 CEFBS_None, // PseudoVBNZ_B = 382
7524 CEFBS_None, // PseudoVBNZ_D = 383
7525 CEFBS_None, // PseudoVBNZ_H = 384
7526 CEFBS_None, // PseudoVBNZ_W = 385
7527 CEFBS_None, // PseudoVBZ = 386
7528 CEFBS_None, // PseudoVBZ_B = 387
7529 CEFBS_None, // PseudoVBZ_D = 388
7530 CEFBS_None, // PseudoVBZ_H = 389
7531 CEFBS_None, // PseudoVBZ_W = 390
7532 CEFBS_None, // PseudoVMSKEQZ_B = 391
7533 CEFBS_None, // PseudoVMSKGEZ_B = 392
7534 CEFBS_None, // PseudoVMSKLTZ_B = 393
7535 CEFBS_None, // PseudoVMSKLTZ_D = 394
7536 CEFBS_None, // PseudoVMSKLTZ_H = 395
7537 CEFBS_None, // PseudoVMSKLTZ_W = 396
7538 CEFBS_None, // PseudoVMSKNEZ_B = 397
7539 CEFBS_None, // PseudoVREPLI_B = 398
7540 CEFBS_None, // PseudoVREPLI_D = 399
7541 CEFBS_None, // PseudoVREPLI_H = 400
7542 CEFBS_None, // PseudoVREPLI_W = 401
7543 CEFBS_None, // PseudoXVBNZ = 402
7544 CEFBS_None, // PseudoXVBNZ_B = 403
7545 CEFBS_None, // PseudoXVBNZ_D = 404
7546 CEFBS_None, // PseudoXVBNZ_H = 405
7547 CEFBS_None, // PseudoXVBNZ_W = 406
7548 CEFBS_None, // PseudoXVBZ = 407
7549 CEFBS_None, // PseudoXVBZ_B = 408
7550 CEFBS_None, // PseudoXVBZ_D = 409
7551 CEFBS_None, // PseudoXVBZ_H = 410
7552 CEFBS_None, // PseudoXVBZ_W = 411
7553 CEFBS_None, // PseudoXVINSGR2VR_B = 412
7554 CEFBS_None, // PseudoXVINSGR2VR_H = 413
7555 CEFBS_None, // PseudoXVMSKEQZ_B = 414
7556 CEFBS_None, // PseudoXVMSKGEZ_B = 415
7557 CEFBS_None, // PseudoXVMSKLTZ_B = 416
7558 CEFBS_None, // PseudoXVMSKLTZ_D = 417
7559 CEFBS_None, // PseudoXVMSKLTZ_H = 418
7560 CEFBS_None, // PseudoXVMSKLTZ_W = 419
7561 CEFBS_None, // PseudoXVMSKNEZ_B = 420
7562 CEFBS_None, // PseudoXVREPLI_B = 421
7563 CEFBS_None, // PseudoXVREPLI_D = 422
7564 CEFBS_None, // PseudoXVREPLI_H = 423
7565 CEFBS_None, // PseudoXVREPLI_W = 424
7566 CEFBS_None, // RDFCSR = 425
7567 CEFBS_None, // Select_GPR_Using_CC_GPR = 426
7568 CEFBS_IsLA32, // SplitPairF64Pseudo = 427
7569 CEFBS_None, // WRFCSR = 428
7570 CEFBS_None, // ADC_B = 429
7571 CEFBS_IsLA64, // ADC_D = 430
7572 CEFBS_None, // ADC_H = 431
7573 CEFBS_None, // ADC_W = 432
7574 CEFBS_IsLA64, // ADDI_D = 433
7575 CEFBS_None, // ADDI_W = 434
7576 CEFBS_IsLA64, // ADDU12I_D = 435
7577 CEFBS_None, // ADDU12I_W = 436
7578 CEFBS_IsLA64, // ADDU16I_D = 437
7579 CEFBS_IsLA64, // ADD_D = 438
7580 CEFBS_None, // ADD_W = 439
7581 CEFBS_IsLA64, // ALSL_D = 440
7582 CEFBS_None, // ALSL_W = 441
7583 CEFBS_IsLA64, // ALSL_WU = 442
7584 CEFBS_IsLA64, // AMADD_B = 443
7585 CEFBS_IsLA64, // AMADD_D = 444
7586 CEFBS_IsLA64, // AMADD_H = 445
7587 CEFBS_IsLA64, // AMADD_W = 446
7588 CEFBS_IsLA64, // AMADD__DB_B = 447
7589 CEFBS_IsLA64, // AMADD__DB_D = 448
7590 CEFBS_IsLA64, // AMADD__DB_H = 449
7591 CEFBS_IsLA64, // AMADD__DB_W = 450
7592 CEFBS_IsLA64, // AMAND_D = 451
7593 CEFBS_IsLA64, // AMAND_W = 452
7594 CEFBS_IsLA64, // AMAND__DB_D = 453
7595 CEFBS_IsLA64, // AMAND__DB_W = 454
7596 CEFBS_IsLA64, // AMCAS_B = 455
7597 CEFBS_IsLA64, // AMCAS_D = 456
7598 CEFBS_IsLA64, // AMCAS_H = 457
7599 CEFBS_IsLA64, // AMCAS_W = 458
7600 CEFBS_IsLA64, // AMCAS__DB_B = 459
7601 CEFBS_IsLA64, // AMCAS__DB_D = 460
7602 CEFBS_IsLA64, // AMCAS__DB_H = 461
7603 CEFBS_IsLA64, // AMCAS__DB_W = 462
7604 CEFBS_IsLA64, // AMMAX_D = 463
7605 CEFBS_IsLA64, // AMMAX_DU = 464
7606 CEFBS_IsLA64, // AMMAX_W = 465
7607 CEFBS_IsLA64, // AMMAX_WU = 466
7608 CEFBS_IsLA64, // AMMAX__DB_D = 467
7609 CEFBS_IsLA64, // AMMAX__DB_DU = 468
7610 CEFBS_IsLA64, // AMMAX__DB_W = 469
7611 CEFBS_IsLA64, // AMMAX__DB_WU = 470
7612 CEFBS_IsLA64, // AMMIN_D = 471
7613 CEFBS_IsLA64, // AMMIN_DU = 472
7614 CEFBS_IsLA64, // AMMIN_W = 473
7615 CEFBS_IsLA64, // AMMIN_WU = 474
7616 CEFBS_IsLA64, // AMMIN__DB_D = 475
7617 CEFBS_IsLA64, // AMMIN__DB_DU = 476
7618 CEFBS_IsLA64, // AMMIN__DB_W = 477
7619 CEFBS_IsLA64, // AMMIN__DB_WU = 478
7620 CEFBS_IsLA64, // AMOR_D = 479
7621 CEFBS_IsLA64, // AMOR_W = 480
7622 CEFBS_IsLA64, // AMOR__DB_D = 481
7623 CEFBS_IsLA64, // AMOR__DB_W = 482
7624 CEFBS_IsLA64, // AMSWAP_B = 483
7625 CEFBS_IsLA64, // AMSWAP_D = 484
7626 CEFBS_IsLA64, // AMSWAP_H = 485
7627 CEFBS_IsLA64, // AMSWAP_W = 486
7628 CEFBS_IsLA64, // AMSWAP__DB_B = 487
7629 CEFBS_IsLA64, // AMSWAP__DB_D = 488
7630 CEFBS_IsLA64, // AMSWAP__DB_H = 489
7631 CEFBS_IsLA64, // AMSWAP__DB_W = 490
7632 CEFBS_IsLA64, // AMXOR_D = 491
7633 CEFBS_IsLA64, // AMXOR_W = 492
7634 CEFBS_IsLA64, // AMXOR__DB_D = 493
7635 CEFBS_IsLA64, // AMXOR__DB_W = 494
7636 CEFBS_None, // AND = 495
7637 CEFBS_None, // ANDI = 496
7638 CEFBS_None, // ANDN = 497
7639 CEFBS_None, // ARMADC_W = 498
7640 CEFBS_None, // ARMADD_W = 499
7641 CEFBS_None, // ARMAND_W = 500
7642 CEFBS_None, // ARMMFFLAG = 501
7643 CEFBS_None, // ARMMOVE = 502
7644 CEFBS_IsLA64, // ARMMOV_D = 503
7645 CEFBS_None, // ARMMOV_W = 504
7646 CEFBS_None, // ARMMTFLAG = 505
7647 CEFBS_None, // ARMNOT_W = 506
7648 CEFBS_None, // ARMOR_W = 507
7649 CEFBS_None, // ARMROTRI_W = 508
7650 CEFBS_None, // ARMROTR_W = 509
7651 CEFBS_None, // ARMRRX_W = 510
7652 CEFBS_None, // ARMSBC_W = 511
7653 CEFBS_None, // ARMSLLI_W = 512
7654 CEFBS_None, // ARMSLL_W = 513
7655 CEFBS_None, // ARMSRAI_W = 514
7656 CEFBS_None, // ARMSRA_W = 515
7657 CEFBS_None, // ARMSRLI_W = 516
7658 CEFBS_None, // ARMSRL_W = 517
7659 CEFBS_None, // ARMSUB_W = 518
7660 CEFBS_None, // ARMXOR_W = 519
7661 CEFBS_IsLA64, // ASRTGT_D = 520
7662 CEFBS_IsLA64, // ASRTLE_D = 521
7663 CEFBS_None, // B = 522
7664 CEFBS_None, // BCEQZ = 523
7665 CEFBS_None, // BCNEZ = 524
7666 CEFBS_None, // BEQ = 525
7667 CEFBS_None, // BEQZ = 526
7668 CEFBS_None, // BGE = 527
7669 CEFBS_None, // BGEU = 528
7670 CEFBS_None, // BITREV_4B = 529
7671 CEFBS_IsLA64, // BITREV_8B = 530
7672 CEFBS_IsLA64, // BITREV_D = 531
7673 CEFBS_None, // BITREV_W = 532
7674 CEFBS_None, // BL = 533
7675 CEFBS_None, // BLT = 534
7676 CEFBS_None, // BLTU = 535
7677 CEFBS_None, // BNE = 536
7678 CEFBS_None, // BNEZ = 537
7679 CEFBS_None, // BREAK = 538
7680 CEFBS_IsLA64, // BSTRINS_D = 539
7681 CEFBS_None, // BSTRINS_W = 540
7682 CEFBS_IsLA64, // BSTRPICK_D = 541
7683 CEFBS_None, // BSTRPICK_W = 542
7684 CEFBS_IsLA64, // BYTEPICK_D = 543
7685 CEFBS_None, // BYTEPICK_W = 544
7686 CEFBS_None, // CACOP = 545
7687 CEFBS_IsLA64, // CLO_D = 546
7688 CEFBS_None, // CLO_W = 547
7689 CEFBS_IsLA64, // CLZ_D = 548
7690 CEFBS_None, // CLZ_W = 549
7691 CEFBS_None, // CPUCFG = 550
7692 CEFBS_IsLA64, // CRCC_W_B_W = 551
7693 CEFBS_IsLA64, // CRCC_W_D_W = 552
7694 CEFBS_IsLA64, // CRCC_W_H_W = 553
7695 CEFBS_IsLA64, // CRCC_W_W_W = 554
7696 CEFBS_IsLA64, // CRC_W_B_W = 555
7697 CEFBS_IsLA64, // CRC_W_D_W = 556
7698 CEFBS_IsLA64, // CRC_W_H_W = 557
7699 CEFBS_IsLA64, // CRC_W_W_W = 558
7700 CEFBS_None, // CSRRD = 559
7701 CEFBS_None, // CSRWR = 560
7702 CEFBS_None, // CSRXCHG = 561
7703 CEFBS_IsLA64, // CTO_D = 562
7704 CEFBS_None, // CTO_W = 563
7705 CEFBS_IsLA64, // CTZ_D = 564
7706 CEFBS_None, // CTZ_W = 565
7707 CEFBS_None, // DBAR = 566
7708 CEFBS_None, // DBCL = 567
7709 CEFBS_IsLA64, // DIV_D = 568
7710 CEFBS_IsLA64, // DIV_DU = 569
7711 CEFBS_None, // DIV_W = 570
7712 CEFBS_None, // DIV_WU = 571
7713 CEFBS_None, // ERTN = 572
7714 CEFBS_None, // EXT_W_B = 573
7715 CEFBS_None, // EXT_W_H = 574
7716 CEFBS_None, // FABS_D = 575
7717 CEFBS_None, // FABS_S = 576
7718 CEFBS_None, // FADD_D = 577
7719 CEFBS_None, // FADD_S = 578
7720 CEFBS_None, // FCLASS_D = 579
7721 CEFBS_None, // FCLASS_S = 580
7722 CEFBS_None, // FCMP_CAF_D = 581
7723 CEFBS_None, // FCMP_CAF_S = 582
7724 CEFBS_None, // FCMP_CEQ_D = 583
7725 CEFBS_None, // FCMP_CEQ_S = 584
7726 CEFBS_None, // FCMP_CLE_D = 585
7727 CEFBS_None, // FCMP_CLE_S = 586
7728 CEFBS_None, // FCMP_CLT_D = 587
7729 CEFBS_None, // FCMP_CLT_S = 588
7730 CEFBS_None, // FCMP_CNE_D = 589
7731 CEFBS_None, // FCMP_CNE_S = 590
7732 CEFBS_None, // FCMP_COR_D = 591
7733 CEFBS_None, // FCMP_COR_S = 592
7734 CEFBS_None, // FCMP_CUEQ_D = 593
7735 CEFBS_None, // FCMP_CUEQ_S = 594
7736 CEFBS_None, // FCMP_CULE_D = 595
7737 CEFBS_None, // FCMP_CULE_S = 596
7738 CEFBS_None, // FCMP_CULT_D = 597
7739 CEFBS_None, // FCMP_CULT_S = 598
7740 CEFBS_None, // FCMP_CUNE_D = 599
7741 CEFBS_None, // FCMP_CUNE_S = 600
7742 CEFBS_None, // FCMP_CUN_D = 601
7743 CEFBS_None, // FCMP_CUN_S = 602
7744 CEFBS_None, // FCMP_SAF_D = 603
7745 CEFBS_None, // FCMP_SAF_S = 604
7746 CEFBS_None, // FCMP_SEQ_D = 605
7747 CEFBS_None, // FCMP_SEQ_S = 606
7748 CEFBS_None, // FCMP_SLE_D = 607
7749 CEFBS_None, // FCMP_SLE_S = 608
7750 CEFBS_None, // FCMP_SLT_D = 609
7751 CEFBS_None, // FCMP_SLT_S = 610
7752 CEFBS_None, // FCMP_SNE_D = 611
7753 CEFBS_None, // FCMP_SNE_S = 612
7754 CEFBS_None, // FCMP_SOR_D = 613
7755 CEFBS_None, // FCMP_SOR_S = 614
7756 CEFBS_None, // FCMP_SUEQ_D = 615
7757 CEFBS_None, // FCMP_SUEQ_S = 616
7758 CEFBS_None, // FCMP_SULE_D = 617
7759 CEFBS_None, // FCMP_SULE_S = 618
7760 CEFBS_None, // FCMP_SULT_D = 619
7761 CEFBS_None, // FCMP_SULT_S = 620
7762 CEFBS_None, // FCMP_SUNE_D = 621
7763 CEFBS_None, // FCMP_SUNE_S = 622
7764 CEFBS_None, // FCMP_SUN_D = 623
7765 CEFBS_None, // FCMP_SUN_S = 624
7766 CEFBS_None, // FCOPYSIGN_D = 625
7767 CEFBS_None, // FCOPYSIGN_S = 626
7768 CEFBS_None, // FCVT_D_LD = 627
7769 CEFBS_None, // FCVT_D_S = 628
7770 CEFBS_None, // FCVT_LD_D = 629
7771 CEFBS_None, // FCVT_S_D = 630
7772 CEFBS_None, // FCVT_UD_D = 631
7773 CEFBS_None, // FDIV_D = 632
7774 CEFBS_None, // FDIV_S = 633
7775 CEFBS_None, // FFINT_D_L = 634
7776 CEFBS_None, // FFINT_D_W = 635
7777 CEFBS_None, // FFINT_S_L = 636
7778 CEFBS_None, // FFINT_S_W = 637
7779 CEFBS_None, // FLDGT_D = 638
7780 CEFBS_None, // FLDGT_S = 639
7781 CEFBS_None, // FLDLE_D = 640
7782 CEFBS_None, // FLDLE_S = 641
7783 CEFBS_None, // FLDX_D = 642
7784 CEFBS_None, // FLDX_S = 643
7785 CEFBS_None, // FLD_D = 644
7786 CEFBS_None, // FLD_S = 645
7787 CEFBS_None, // FLOGB_D = 646
7788 CEFBS_None, // FLOGB_S = 647
7789 CEFBS_None, // FMADD_D = 648
7790 CEFBS_None, // FMADD_S = 649
7791 CEFBS_None, // FMAXA_D = 650
7792 CEFBS_None, // FMAXA_S = 651
7793 CEFBS_None, // FMAX_D = 652
7794 CEFBS_None, // FMAX_S = 653
7795 CEFBS_None, // FMINA_D = 654
7796 CEFBS_None, // FMINA_S = 655
7797 CEFBS_None, // FMIN_D = 656
7798 CEFBS_None, // FMIN_S = 657
7799 CEFBS_None, // FMOV_D = 658
7800 CEFBS_None, // FMOV_S = 659
7801 CEFBS_None, // FMSUB_D = 660
7802 CEFBS_None, // FMSUB_S = 661
7803 CEFBS_None, // FMUL_D = 662
7804 CEFBS_None, // FMUL_S = 663
7805 CEFBS_None, // FNEG_D = 664
7806 CEFBS_None, // FNEG_S = 665
7807 CEFBS_None, // FNMADD_D = 666
7808 CEFBS_None, // FNMADD_S = 667
7809 CEFBS_None, // FNMSUB_D = 668
7810 CEFBS_None, // FNMSUB_S = 669
7811 CEFBS_None, // FRECIPE_D = 670
7812 CEFBS_None, // FRECIPE_S = 671
7813 CEFBS_None, // FRECIP_D = 672
7814 CEFBS_None, // FRECIP_S = 673
7815 CEFBS_None, // FRINT_D = 674
7816 CEFBS_None, // FRINT_S = 675
7817 CEFBS_None, // FRSQRTE_D = 676
7818 CEFBS_None, // FRSQRTE_S = 677
7819 CEFBS_None, // FRSQRT_D = 678
7820 CEFBS_None, // FRSQRT_S = 679
7821 CEFBS_None, // FSCALEB_D = 680
7822 CEFBS_None, // FSCALEB_S = 681
7823 CEFBS_None, // FSEL_xD = 682
7824 CEFBS_None, // FSEL_xS = 683
7825 CEFBS_None, // FSQRT_D = 684
7826 CEFBS_None, // FSQRT_S = 685
7827 CEFBS_None, // FSTGT_D = 686
7828 CEFBS_None, // FSTGT_S = 687
7829 CEFBS_None, // FSTLE_D = 688
7830 CEFBS_None, // FSTLE_S = 689
7831 CEFBS_None, // FSTX_D = 690
7832 CEFBS_None, // FSTX_S = 691
7833 CEFBS_None, // FST_D = 692
7834 CEFBS_None, // FST_S = 693
7835 CEFBS_None, // FSUB_D = 694
7836 CEFBS_None, // FSUB_S = 695
7837 CEFBS_None, // FTINTRM_L_D = 696
7838 CEFBS_None, // FTINTRM_L_S = 697
7839 CEFBS_None, // FTINTRM_W_D = 698
7840 CEFBS_None, // FTINTRM_W_S = 699
7841 CEFBS_None, // FTINTRNE_L_D = 700
7842 CEFBS_None, // FTINTRNE_L_S = 701
7843 CEFBS_None, // FTINTRNE_W_D = 702
7844 CEFBS_None, // FTINTRNE_W_S = 703
7845 CEFBS_None, // FTINTRP_L_D = 704
7846 CEFBS_None, // FTINTRP_L_S = 705
7847 CEFBS_None, // FTINTRP_W_D = 706
7848 CEFBS_None, // FTINTRP_W_S = 707
7849 CEFBS_None, // FTINTRZ_L_D = 708
7850 CEFBS_None, // FTINTRZ_L_S = 709
7851 CEFBS_None, // FTINTRZ_W_D = 710
7852 CEFBS_None, // FTINTRZ_W_S = 711
7853 CEFBS_None, // FTINT_L_D = 712
7854 CEFBS_None, // FTINT_L_S = 713
7855 CEFBS_None, // FTINT_W_D = 714
7856 CEFBS_None, // FTINT_W_S = 715
7857 CEFBS_None, // GCSRRD = 716
7858 CEFBS_None, // GCSRWR = 717
7859 CEFBS_None, // GCSRXCHG = 718
7860 CEFBS_None, // GTLBFLUSH = 719
7861 CEFBS_None, // HVCL = 720
7862 CEFBS_None, // IBAR = 721
7863 CEFBS_None, // IDLE = 722
7864 CEFBS_None, // INVTLB = 723
7865 CEFBS_None, // IOCSRRD_B = 724
7866 CEFBS_IsLA64, // IOCSRRD_D = 725
7867 CEFBS_None, // IOCSRRD_H = 726
7868 CEFBS_None, // IOCSRRD_W = 727
7869 CEFBS_None, // IOCSRWR_B = 728
7870 CEFBS_IsLA64, // IOCSRWR_D = 729
7871 CEFBS_None, // IOCSRWR_H = 730
7872 CEFBS_None, // IOCSRWR_W = 731
7873 CEFBS_None, // JIRL = 732
7874 CEFBS_None, // JISCR0 = 733
7875 CEFBS_None, // JISCR1 = 734
7876 CEFBS_None, // LDDIR = 735
7877 CEFBS_IsLA64, // LDGT_B = 736
7878 CEFBS_IsLA64, // LDGT_D = 737
7879 CEFBS_IsLA64, // LDGT_H = 738
7880 CEFBS_IsLA64, // LDGT_W = 739
7881 CEFBS_IsLA64, // LDLE_B = 740
7882 CEFBS_IsLA64, // LDLE_D = 741
7883 CEFBS_IsLA64, // LDLE_H = 742
7884 CEFBS_IsLA64, // LDLE_W = 743
7885 CEFBS_IsLA64, // LDL_D = 744
7886 CEFBS_None, // LDL_W = 745
7887 CEFBS_None, // LDPTE = 746
7888 CEFBS_IsLA64, // LDPTR_D = 747
7889 CEFBS_IsLA64, // LDPTR_W = 748
7890 CEFBS_IsLA64, // LDR_D = 749
7891 CEFBS_None, // LDR_W = 750
7892 CEFBS_IsLA64, // LDX_B = 751
7893 CEFBS_IsLA64, // LDX_BU = 752
7894 CEFBS_IsLA64, // LDX_D = 753
7895 CEFBS_IsLA64, // LDX_H = 754
7896 CEFBS_IsLA64, // LDX_HU = 755
7897 CEFBS_IsLA64, // LDX_W = 756
7898 CEFBS_IsLA64, // LDX_WU = 757
7899 CEFBS_None, // LD_B = 758
7900 CEFBS_None, // LD_BU = 759
7901 CEFBS_IsLA64, // LD_D = 760
7902 CEFBS_None, // LD_H = 761
7903 CEFBS_None, // LD_HU = 762
7904 CEFBS_None, // LD_W = 763
7905 CEFBS_IsLA64, // LD_WU = 764
7906 CEFBS_IsLA64, // LLACQ_D = 765
7907 CEFBS_IsLA64, // LLACQ_W = 766
7908 CEFBS_IsLA64, // LL_D = 767
7909 CEFBS_None, // LL_W = 768
7910 CEFBS_None, // LU12I_W = 769
7911 CEFBS_IsLA64, // LU32I_D = 770
7912 CEFBS_IsLA64, // LU52I_D = 771
7913 CEFBS_None, // MASKEQZ = 772
7914 CEFBS_None, // MASKNEZ = 773
7915 CEFBS_IsLA64, // MOD_D = 774
7916 CEFBS_IsLA64, // MOD_DU = 775
7917 CEFBS_None, // MOD_W = 776
7918 CEFBS_None, // MOD_WU = 777
7919 CEFBS_None, // MOVCF2FR_xS = 778
7920 CEFBS_None, // MOVCF2GR = 779
7921 CEFBS_None, // MOVFCSR2GR = 780
7922 CEFBS_None, // MOVFR2CF_xS = 781
7923 CEFBS_IsLA64, // MOVFR2GR_D = 782
7924 CEFBS_None, // MOVFR2GR_S = 783
7925 CEFBS_None, // MOVFR2GR_S_64 = 784
7926 CEFBS_None, // MOVFRH2GR_S = 785
7927 CEFBS_None, // MOVGR2CF = 786
7928 CEFBS_None, // MOVGR2FCSR = 787
7929 CEFBS_None, // MOVGR2FRH_W = 788
7930 CEFBS_IsLA64, // MOVGR2FR_D = 789
7931 CEFBS_None, // MOVGR2FR_W = 790
7932 CEFBS_IsLA32, // MOVGR2FR_W_64 = 791
7933 CEFBS_None, // MOVGR2SCR = 792
7934 CEFBS_None, // MOVSCR2GR = 793
7935 CEFBS_IsLA64, // MULH_D = 794
7936 CEFBS_IsLA64, // MULH_DU = 795
7937 CEFBS_None, // MULH_W = 796
7938 CEFBS_None, // MULH_WU = 797
7939 CEFBS_IsLA64, // MULW_D_W = 798
7940 CEFBS_IsLA64, // MULW_D_WU = 799
7941 CEFBS_IsLA64, // MUL_D = 800
7942 CEFBS_None, // MUL_W = 801
7943 CEFBS_None, // NOR = 802
7944 CEFBS_None, // OR = 803
7945 CEFBS_None, // ORI = 804
7946 CEFBS_None, // ORN = 805
7947 CEFBS_None, // PCADDI = 806
7948 CEFBS_None, // PCADDU12I = 807
7949 CEFBS_IsLA64, // PCADDU18I = 808
7950 CEFBS_None, // PCALAU12I = 809
7951 CEFBS_None, // PRELD = 810
7952 CEFBS_IsLA64, // PRELDX = 811
7953 CEFBS_None, // RCRI_B = 812
7954 CEFBS_IsLA64, // RCRI_D = 813
7955 CEFBS_None, // RCRI_H = 814
7956 CEFBS_None, // RCRI_W = 815
7957 CEFBS_None, // RCR_B = 816
7958 CEFBS_IsLA64, // RCR_D = 817
7959 CEFBS_None, // RCR_H = 818
7960 CEFBS_None, // RCR_W = 819
7961 CEFBS_None, // RDTIMEH_W = 820
7962 CEFBS_None, // RDTIMEL_W = 821
7963 CEFBS_IsLA64, // RDTIME_D = 822
7964 CEFBS_None, // REVB_2H = 823
7965 CEFBS_IsLA64, // REVB_2W = 824
7966 CEFBS_IsLA64, // REVB_4H = 825
7967 CEFBS_IsLA64, // REVB_D = 826
7968 CEFBS_IsLA64, // REVH_2W = 827
7969 CEFBS_IsLA64, // REVH_D = 828
7970 CEFBS_None, // ROTRI_B = 829
7971 CEFBS_IsLA64, // ROTRI_D = 830
7972 CEFBS_None, // ROTRI_H = 831
7973 CEFBS_None, // ROTRI_W = 832
7974 CEFBS_None, // ROTR_B = 833
7975 CEFBS_IsLA64, // ROTR_D = 834
7976 CEFBS_None, // ROTR_H = 835
7977 CEFBS_None, // ROTR_W = 836
7978 CEFBS_None, // SBC_B = 837
7979 CEFBS_IsLA64, // SBC_D = 838
7980 CEFBS_None, // SBC_H = 839
7981 CEFBS_None, // SBC_W = 840
7982 CEFBS_IsLA64, // SCREL_D = 841
7983 CEFBS_IsLA64, // SCREL_W = 842
7984 CEFBS_IsLA64, // SC_D = 843
7985 CEFBS_IsLA64, // SC_Q = 844
7986 CEFBS_None, // SC_W = 845
7987 CEFBS_None, // SETARMJ = 846
7988 CEFBS_None, // SETX86J = 847
7989 CEFBS_None, // SETX86LOOPE = 848
7990 CEFBS_None, // SETX86LOOPNE = 849
7991 CEFBS_None, // SET_CFR_FALSE = 850
7992 CEFBS_None, // SET_CFR_TRUE = 851
7993 CEFBS_IsLA64, // SLLI_D = 852
7994 CEFBS_None, // SLLI_W = 853
7995 CEFBS_IsLA64, // SLL_D = 854
7996 CEFBS_None, // SLL_W = 855
7997 CEFBS_None, // SLT = 856
7998 CEFBS_None, // SLTI = 857
7999 CEFBS_None, // SLTU = 858
8000 CEFBS_None, // SLTUI = 859
8001 CEFBS_IsLA64, // SRAI_D = 860
8002 CEFBS_None, // SRAI_W = 861
8003 CEFBS_IsLA64, // SRA_D = 862
8004 CEFBS_None, // SRA_W = 863
8005 CEFBS_IsLA64, // SRLI_D = 864
8006 CEFBS_None, // SRLI_W = 865
8007 CEFBS_IsLA64, // SRL_D = 866
8008 CEFBS_None, // SRL_W = 867
8009 CEFBS_IsLA64, // STGT_B = 868
8010 CEFBS_IsLA64, // STGT_D = 869
8011 CEFBS_IsLA64, // STGT_H = 870
8012 CEFBS_IsLA64, // STGT_W = 871
8013 CEFBS_IsLA64, // STLE_B = 872
8014 CEFBS_IsLA64, // STLE_D = 873
8015 CEFBS_IsLA64, // STLE_H = 874
8016 CEFBS_IsLA64, // STLE_W = 875
8017 CEFBS_IsLA64, // STL_D = 876
8018 CEFBS_None, // STL_W = 877
8019 CEFBS_IsLA64, // STPTR_D = 878
8020 CEFBS_IsLA64, // STPTR_W = 879
8021 CEFBS_IsLA64, // STR_D = 880
8022 CEFBS_None, // STR_W = 881
8023 CEFBS_IsLA64, // STX_B = 882
8024 CEFBS_IsLA64, // STX_D = 883
8025 CEFBS_IsLA64, // STX_H = 884
8026 CEFBS_IsLA64, // STX_W = 885
8027 CEFBS_None, // ST_B = 886
8028 CEFBS_IsLA64, // ST_D = 887
8029 CEFBS_None, // ST_H = 888
8030 CEFBS_None, // ST_W = 889
8031 CEFBS_IsLA64, // SUB_D = 890
8032 CEFBS_None, // SUB_W = 891
8033 CEFBS_None, // SYSCALL = 892
8034 CEFBS_None, // TLBCLR = 893
8035 CEFBS_None, // TLBFILL = 894
8036 CEFBS_None, // TLBFLUSH = 895
8037 CEFBS_None, // TLBRD = 896
8038 CEFBS_None, // TLBSRCH = 897
8039 CEFBS_None, // TLBWR = 898
8040 CEFBS_None, // VABSD_B = 899
8041 CEFBS_None, // VABSD_BU = 900
8042 CEFBS_None, // VABSD_D = 901
8043 CEFBS_None, // VABSD_DU = 902
8044 CEFBS_None, // VABSD_H = 903
8045 CEFBS_None, // VABSD_HU = 904
8046 CEFBS_None, // VABSD_W = 905
8047 CEFBS_None, // VABSD_WU = 906
8048 CEFBS_None, // VADDA_B = 907
8049 CEFBS_None, // VADDA_D = 908
8050 CEFBS_None, // VADDA_H = 909
8051 CEFBS_None, // VADDA_W = 910
8052 CEFBS_None, // VADDI_BU = 911
8053 CEFBS_None, // VADDI_DU = 912
8054 CEFBS_None, // VADDI_HU = 913
8055 CEFBS_None, // VADDI_WU = 914
8056 CEFBS_None, // VADDWEV_D_W = 915
8057 CEFBS_None, // VADDWEV_D_WU = 916
8058 CEFBS_None, // VADDWEV_D_WU_W = 917
8059 CEFBS_None, // VADDWEV_H_B = 918
8060 CEFBS_None, // VADDWEV_H_BU = 919
8061 CEFBS_None, // VADDWEV_H_BU_B = 920
8062 CEFBS_None, // VADDWEV_Q_D = 921
8063 CEFBS_None, // VADDWEV_Q_DU = 922
8064 CEFBS_None, // VADDWEV_Q_DU_D = 923
8065 CEFBS_None, // VADDWEV_W_H = 924
8066 CEFBS_None, // VADDWEV_W_HU = 925
8067 CEFBS_None, // VADDWEV_W_HU_H = 926
8068 CEFBS_None, // VADDWOD_D_W = 927
8069 CEFBS_None, // VADDWOD_D_WU = 928
8070 CEFBS_None, // VADDWOD_D_WU_W = 929
8071 CEFBS_None, // VADDWOD_H_B = 930
8072 CEFBS_None, // VADDWOD_H_BU = 931
8073 CEFBS_None, // VADDWOD_H_BU_B = 932
8074 CEFBS_None, // VADDWOD_Q_D = 933
8075 CEFBS_None, // VADDWOD_Q_DU = 934
8076 CEFBS_None, // VADDWOD_Q_DU_D = 935
8077 CEFBS_None, // VADDWOD_W_H = 936
8078 CEFBS_None, // VADDWOD_W_HU = 937
8079 CEFBS_None, // VADDWOD_W_HU_H = 938
8080 CEFBS_None, // VADD_B = 939
8081 CEFBS_None, // VADD_D = 940
8082 CEFBS_None, // VADD_H = 941
8083 CEFBS_None, // VADD_Q = 942
8084 CEFBS_None, // VADD_W = 943
8085 CEFBS_None, // VANDI_B = 944
8086 CEFBS_None, // VANDN_V = 945
8087 CEFBS_None, // VAND_V = 946
8088 CEFBS_None, // VAVGR_B = 947
8089 CEFBS_None, // VAVGR_BU = 948
8090 CEFBS_None, // VAVGR_D = 949
8091 CEFBS_None, // VAVGR_DU = 950
8092 CEFBS_None, // VAVGR_H = 951
8093 CEFBS_None, // VAVGR_HU = 952
8094 CEFBS_None, // VAVGR_W = 953
8095 CEFBS_None, // VAVGR_WU = 954
8096 CEFBS_None, // VAVG_B = 955
8097 CEFBS_None, // VAVG_BU = 956
8098 CEFBS_None, // VAVG_D = 957
8099 CEFBS_None, // VAVG_DU = 958
8100 CEFBS_None, // VAVG_H = 959
8101 CEFBS_None, // VAVG_HU = 960
8102 CEFBS_None, // VAVG_W = 961
8103 CEFBS_None, // VAVG_WU = 962
8104 CEFBS_None, // VBITCLRI_B = 963
8105 CEFBS_None, // VBITCLRI_D = 964
8106 CEFBS_None, // VBITCLRI_H = 965
8107 CEFBS_None, // VBITCLRI_W = 966
8108 CEFBS_None, // VBITCLR_B = 967
8109 CEFBS_None, // VBITCLR_D = 968
8110 CEFBS_None, // VBITCLR_H = 969
8111 CEFBS_None, // VBITCLR_W = 970
8112 CEFBS_None, // VBITREVI_B = 971
8113 CEFBS_None, // VBITREVI_D = 972
8114 CEFBS_None, // VBITREVI_H = 973
8115 CEFBS_None, // VBITREVI_W = 974
8116 CEFBS_None, // VBITREV_B = 975
8117 CEFBS_None, // VBITREV_D = 976
8118 CEFBS_None, // VBITREV_H = 977
8119 CEFBS_None, // VBITREV_W = 978
8120 CEFBS_None, // VBITSELI_B = 979
8121 CEFBS_None, // VBITSEL_V = 980
8122 CEFBS_None, // VBITSETI_B = 981
8123 CEFBS_None, // VBITSETI_D = 982
8124 CEFBS_None, // VBITSETI_H = 983
8125 CEFBS_None, // VBITSETI_W = 984
8126 CEFBS_None, // VBITSET_B = 985
8127 CEFBS_None, // VBITSET_D = 986
8128 CEFBS_None, // VBITSET_H = 987
8129 CEFBS_None, // VBITSET_W = 988
8130 CEFBS_None, // VBSLL_V = 989
8131 CEFBS_None, // VBSRL_V = 990
8132 CEFBS_None, // VCLO_B = 991
8133 CEFBS_None, // VCLO_D = 992
8134 CEFBS_None, // VCLO_H = 993
8135 CEFBS_None, // VCLO_W = 994
8136 CEFBS_None, // VCLZ_B = 995
8137 CEFBS_None, // VCLZ_D = 996
8138 CEFBS_None, // VCLZ_H = 997
8139 CEFBS_None, // VCLZ_W = 998
8140 CEFBS_None, // VDIV_B = 999
8141 CEFBS_None, // VDIV_BU = 1000
8142 CEFBS_None, // VDIV_D = 1001
8143 CEFBS_None, // VDIV_DU = 1002
8144 CEFBS_None, // VDIV_H = 1003
8145 CEFBS_None, // VDIV_HU = 1004
8146 CEFBS_None, // VDIV_W = 1005
8147 CEFBS_None, // VDIV_WU = 1006
8148 CEFBS_None, // VEXT2XV_DU_BU = 1007
8149 CEFBS_None, // VEXT2XV_DU_HU = 1008
8150 CEFBS_None, // VEXT2XV_DU_WU = 1009
8151 CEFBS_None, // VEXT2XV_D_B = 1010
8152 CEFBS_None, // VEXT2XV_D_H = 1011
8153 CEFBS_None, // VEXT2XV_D_W = 1012
8154 CEFBS_None, // VEXT2XV_HU_BU = 1013
8155 CEFBS_None, // VEXT2XV_H_B = 1014
8156 CEFBS_None, // VEXT2XV_WU_BU = 1015
8157 CEFBS_None, // VEXT2XV_WU_HU = 1016
8158 CEFBS_None, // VEXT2XV_W_B = 1017
8159 CEFBS_None, // VEXT2XV_W_H = 1018
8160 CEFBS_None, // VEXTH_DU_WU = 1019
8161 CEFBS_None, // VEXTH_D_W = 1020
8162 CEFBS_None, // VEXTH_HU_BU = 1021
8163 CEFBS_None, // VEXTH_H_B = 1022
8164 CEFBS_None, // VEXTH_QU_DU = 1023
8165 CEFBS_None, // VEXTH_Q_D = 1024
8166 CEFBS_None, // VEXTH_WU_HU = 1025
8167 CEFBS_None, // VEXTH_W_H = 1026
8168 CEFBS_None, // VEXTL_QU_DU = 1027
8169 CEFBS_None, // VEXTL_Q_D = 1028
8170 CEFBS_None, // VEXTRINS_B = 1029
8171 CEFBS_None, // VEXTRINS_D = 1030
8172 CEFBS_None, // VEXTRINS_H = 1031
8173 CEFBS_None, // VEXTRINS_W = 1032
8174 CEFBS_None, // VFADD_D = 1033
8175 CEFBS_None, // VFADD_S = 1034
8176 CEFBS_None, // VFCLASS_D = 1035
8177 CEFBS_None, // VFCLASS_S = 1036
8178 CEFBS_None, // VFCMP_CAF_D = 1037
8179 CEFBS_None, // VFCMP_CAF_S = 1038
8180 CEFBS_None, // VFCMP_CEQ_D = 1039
8181 CEFBS_None, // VFCMP_CEQ_S = 1040
8182 CEFBS_None, // VFCMP_CLE_D = 1041
8183 CEFBS_None, // VFCMP_CLE_S = 1042
8184 CEFBS_None, // VFCMP_CLT_D = 1043
8185 CEFBS_None, // VFCMP_CLT_S = 1044
8186 CEFBS_None, // VFCMP_CNE_D = 1045
8187 CEFBS_None, // VFCMP_CNE_S = 1046
8188 CEFBS_None, // VFCMP_COR_D = 1047
8189 CEFBS_None, // VFCMP_COR_S = 1048
8190 CEFBS_None, // VFCMP_CUEQ_D = 1049
8191 CEFBS_None, // VFCMP_CUEQ_S = 1050
8192 CEFBS_None, // VFCMP_CULE_D = 1051
8193 CEFBS_None, // VFCMP_CULE_S = 1052
8194 CEFBS_None, // VFCMP_CULT_D = 1053
8195 CEFBS_None, // VFCMP_CULT_S = 1054
8196 CEFBS_None, // VFCMP_CUNE_D = 1055
8197 CEFBS_None, // VFCMP_CUNE_S = 1056
8198 CEFBS_None, // VFCMP_CUN_D = 1057
8199 CEFBS_None, // VFCMP_CUN_S = 1058
8200 CEFBS_None, // VFCMP_SAF_D = 1059
8201 CEFBS_None, // VFCMP_SAF_S = 1060
8202 CEFBS_None, // VFCMP_SEQ_D = 1061
8203 CEFBS_None, // VFCMP_SEQ_S = 1062
8204 CEFBS_None, // VFCMP_SLE_D = 1063
8205 CEFBS_None, // VFCMP_SLE_S = 1064
8206 CEFBS_None, // VFCMP_SLT_D = 1065
8207 CEFBS_None, // VFCMP_SLT_S = 1066
8208 CEFBS_None, // VFCMP_SNE_D = 1067
8209 CEFBS_None, // VFCMP_SNE_S = 1068
8210 CEFBS_None, // VFCMP_SOR_D = 1069
8211 CEFBS_None, // VFCMP_SOR_S = 1070
8212 CEFBS_None, // VFCMP_SUEQ_D = 1071
8213 CEFBS_None, // VFCMP_SUEQ_S = 1072
8214 CEFBS_None, // VFCMP_SULE_D = 1073
8215 CEFBS_None, // VFCMP_SULE_S = 1074
8216 CEFBS_None, // VFCMP_SULT_D = 1075
8217 CEFBS_None, // VFCMP_SULT_S = 1076
8218 CEFBS_None, // VFCMP_SUNE_D = 1077
8219 CEFBS_None, // VFCMP_SUNE_S = 1078
8220 CEFBS_None, // VFCMP_SUN_D = 1079
8221 CEFBS_None, // VFCMP_SUN_S = 1080
8222 CEFBS_None, // VFCVTH_D_S = 1081
8223 CEFBS_None, // VFCVTH_S_H = 1082
8224 CEFBS_None, // VFCVTL_D_S = 1083
8225 CEFBS_None, // VFCVTL_S_H = 1084
8226 CEFBS_None, // VFCVT_H_S = 1085
8227 CEFBS_None, // VFCVT_S_D = 1086
8228 CEFBS_None, // VFDIV_D = 1087
8229 CEFBS_None, // VFDIV_S = 1088
8230 CEFBS_None, // VFFINTH_D_W = 1089
8231 CEFBS_None, // VFFINTL_D_W = 1090
8232 CEFBS_None, // VFFINT_D_L = 1091
8233 CEFBS_None, // VFFINT_D_LU = 1092
8234 CEFBS_None, // VFFINT_S_L = 1093
8235 CEFBS_None, // VFFINT_S_W = 1094
8236 CEFBS_None, // VFFINT_S_WU = 1095
8237 CEFBS_None, // VFLOGB_D = 1096
8238 CEFBS_None, // VFLOGB_S = 1097
8239 CEFBS_None, // VFMADD_D = 1098
8240 CEFBS_None, // VFMADD_S = 1099
8241 CEFBS_None, // VFMAXA_D = 1100
8242 CEFBS_None, // VFMAXA_S = 1101
8243 CEFBS_None, // VFMAX_D = 1102
8244 CEFBS_None, // VFMAX_S = 1103
8245 CEFBS_None, // VFMINA_D = 1104
8246 CEFBS_None, // VFMINA_S = 1105
8247 CEFBS_None, // VFMIN_D = 1106
8248 CEFBS_None, // VFMIN_S = 1107
8249 CEFBS_None, // VFMSUB_D = 1108
8250 CEFBS_None, // VFMSUB_S = 1109
8251 CEFBS_None, // VFMUL_D = 1110
8252 CEFBS_None, // VFMUL_S = 1111
8253 CEFBS_None, // VFNMADD_D = 1112
8254 CEFBS_None, // VFNMADD_S = 1113
8255 CEFBS_None, // VFNMSUB_D = 1114
8256 CEFBS_None, // VFNMSUB_S = 1115
8257 CEFBS_None, // VFRECIPE_D = 1116
8258 CEFBS_None, // VFRECIPE_S = 1117
8259 CEFBS_None, // VFRECIP_D = 1118
8260 CEFBS_None, // VFRECIP_S = 1119
8261 CEFBS_None, // VFRINTRM_D = 1120
8262 CEFBS_None, // VFRINTRM_S = 1121
8263 CEFBS_None, // VFRINTRNE_D = 1122
8264 CEFBS_None, // VFRINTRNE_S = 1123
8265 CEFBS_None, // VFRINTRP_D = 1124
8266 CEFBS_None, // VFRINTRP_S = 1125
8267 CEFBS_None, // VFRINTRZ_D = 1126
8268 CEFBS_None, // VFRINTRZ_S = 1127
8269 CEFBS_None, // VFRINT_D = 1128
8270 CEFBS_None, // VFRINT_S = 1129
8271 CEFBS_None, // VFRSQRTE_D = 1130
8272 CEFBS_None, // VFRSQRTE_S = 1131
8273 CEFBS_None, // VFRSQRT_D = 1132
8274 CEFBS_None, // VFRSQRT_S = 1133
8275 CEFBS_None, // VFRSTPI_B = 1134
8276 CEFBS_None, // VFRSTPI_H = 1135
8277 CEFBS_None, // VFRSTP_B = 1136
8278 CEFBS_None, // VFRSTP_H = 1137
8279 CEFBS_None, // VFSQRT_D = 1138
8280 CEFBS_None, // VFSQRT_S = 1139
8281 CEFBS_None, // VFSUB_D = 1140
8282 CEFBS_None, // VFSUB_S = 1141
8283 CEFBS_None, // VFTINTH_L_S = 1142
8284 CEFBS_None, // VFTINTL_L_S = 1143
8285 CEFBS_None, // VFTINTRMH_L_S = 1144
8286 CEFBS_None, // VFTINTRML_L_S = 1145
8287 CEFBS_None, // VFTINTRM_L_D = 1146
8288 CEFBS_None, // VFTINTRM_W_D = 1147
8289 CEFBS_None, // VFTINTRM_W_S = 1148
8290 CEFBS_None, // VFTINTRNEH_L_S = 1149
8291 CEFBS_None, // VFTINTRNEL_L_S = 1150
8292 CEFBS_None, // VFTINTRNE_L_D = 1151
8293 CEFBS_None, // VFTINTRNE_W_D = 1152
8294 CEFBS_None, // VFTINTRNE_W_S = 1153
8295 CEFBS_None, // VFTINTRPH_L_S = 1154
8296 CEFBS_None, // VFTINTRPL_L_S = 1155
8297 CEFBS_None, // VFTINTRP_L_D = 1156
8298 CEFBS_None, // VFTINTRP_W_D = 1157
8299 CEFBS_None, // VFTINTRP_W_S = 1158
8300 CEFBS_None, // VFTINTRZH_L_S = 1159
8301 CEFBS_None, // VFTINTRZL_L_S = 1160
8302 CEFBS_None, // VFTINTRZ_LU_D = 1161
8303 CEFBS_None, // VFTINTRZ_L_D = 1162
8304 CEFBS_None, // VFTINTRZ_WU_S = 1163
8305 CEFBS_None, // VFTINTRZ_W_D = 1164
8306 CEFBS_None, // VFTINTRZ_W_S = 1165
8307 CEFBS_None, // VFTINT_LU_D = 1166
8308 CEFBS_None, // VFTINT_L_D = 1167
8309 CEFBS_None, // VFTINT_WU_S = 1168
8310 CEFBS_None, // VFTINT_W_D = 1169
8311 CEFBS_None, // VFTINT_W_S = 1170
8312 CEFBS_None, // VHADDW_DU_WU = 1171
8313 CEFBS_None, // VHADDW_D_W = 1172
8314 CEFBS_None, // VHADDW_HU_BU = 1173
8315 CEFBS_None, // VHADDW_H_B = 1174
8316 CEFBS_None, // VHADDW_QU_DU = 1175
8317 CEFBS_None, // VHADDW_Q_D = 1176
8318 CEFBS_None, // VHADDW_WU_HU = 1177
8319 CEFBS_None, // VHADDW_W_H = 1178
8320 CEFBS_None, // VHSUBW_DU_WU = 1179
8321 CEFBS_None, // VHSUBW_D_W = 1180
8322 CEFBS_None, // VHSUBW_HU_BU = 1181
8323 CEFBS_None, // VHSUBW_H_B = 1182
8324 CEFBS_None, // VHSUBW_QU_DU = 1183
8325 CEFBS_None, // VHSUBW_Q_D = 1184
8326 CEFBS_None, // VHSUBW_WU_HU = 1185
8327 CEFBS_None, // VHSUBW_W_H = 1186
8328 CEFBS_None, // VILVH_B = 1187
8329 CEFBS_None, // VILVH_D = 1188
8330 CEFBS_None, // VILVH_H = 1189
8331 CEFBS_None, // VILVH_W = 1190
8332 CEFBS_None, // VILVL_B = 1191
8333 CEFBS_None, // VILVL_D = 1192
8334 CEFBS_None, // VILVL_H = 1193
8335 CEFBS_None, // VILVL_W = 1194
8336 CEFBS_None, // VINSGR2VR_B = 1195
8337 CEFBS_None, // VINSGR2VR_D = 1196
8338 CEFBS_None, // VINSGR2VR_H = 1197
8339 CEFBS_None, // VINSGR2VR_W = 1198
8340 CEFBS_None, // VLD = 1199
8341 CEFBS_None, // VLDI = 1200
8342 CEFBS_None, // VLDREPL_B = 1201
8343 CEFBS_None, // VLDREPL_D = 1202
8344 CEFBS_None, // VLDREPL_H = 1203
8345 CEFBS_None, // VLDREPL_W = 1204
8346 CEFBS_None, // VLDX = 1205
8347 CEFBS_None, // VMADDWEV_D_W = 1206
8348 CEFBS_None, // VMADDWEV_D_WU = 1207
8349 CEFBS_None, // VMADDWEV_D_WU_W = 1208
8350 CEFBS_None, // VMADDWEV_H_B = 1209
8351 CEFBS_None, // VMADDWEV_H_BU = 1210
8352 CEFBS_None, // VMADDWEV_H_BU_B = 1211
8353 CEFBS_None, // VMADDWEV_Q_D = 1212
8354 CEFBS_None, // VMADDWEV_Q_DU = 1213
8355 CEFBS_None, // VMADDWEV_Q_DU_D = 1214
8356 CEFBS_None, // VMADDWEV_W_H = 1215
8357 CEFBS_None, // VMADDWEV_W_HU = 1216
8358 CEFBS_None, // VMADDWEV_W_HU_H = 1217
8359 CEFBS_None, // VMADDWOD_D_W = 1218
8360 CEFBS_None, // VMADDWOD_D_WU = 1219
8361 CEFBS_None, // VMADDWOD_D_WU_W = 1220
8362 CEFBS_None, // VMADDWOD_H_B = 1221
8363 CEFBS_None, // VMADDWOD_H_BU = 1222
8364 CEFBS_None, // VMADDWOD_H_BU_B = 1223
8365 CEFBS_None, // VMADDWOD_Q_D = 1224
8366 CEFBS_None, // VMADDWOD_Q_DU = 1225
8367 CEFBS_None, // VMADDWOD_Q_DU_D = 1226
8368 CEFBS_None, // VMADDWOD_W_H = 1227
8369 CEFBS_None, // VMADDWOD_W_HU = 1228
8370 CEFBS_None, // VMADDWOD_W_HU_H = 1229
8371 CEFBS_None, // VMADD_B = 1230
8372 CEFBS_None, // VMADD_D = 1231
8373 CEFBS_None, // VMADD_H = 1232
8374 CEFBS_None, // VMADD_W = 1233
8375 CEFBS_None, // VMAXI_B = 1234
8376 CEFBS_None, // VMAXI_BU = 1235
8377 CEFBS_None, // VMAXI_D = 1236
8378 CEFBS_None, // VMAXI_DU = 1237
8379 CEFBS_None, // VMAXI_H = 1238
8380 CEFBS_None, // VMAXI_HU = 1239
8381 CEFBS_None, // VMAXI_W = 1240
8382 CEFBS_None, // VMAXI_WU = 1241
8383 CEFBS_None, // VMAX_B = 1242
8384 CEFBS_None, // VMAX_BU = 1243
8385 CEFBS_None, // VMAX_D = 1244
8386 CEFBS_None, // VMAX_DU = 1245
8387 CEFBS_None, // VMAX_H = 1246
8388 CEFBS_None, // VMAX_HU = 1247
8389 CEFBS_None, // VMAX_W = 1248
8390 CEFBS_None, // VMAX_WU = 1249
8391 CEFBS_None, // VMINI_B = 1250
8392 CEFBS_None, // VMINI_BU = 1251
8393 CEFBS_None, // VMINI_D = 1252
8394 CEFBS_None, // VMINI_DU = 1253
8395 CEFBS_None, // VMINI_H = 1254
8396 CEFBS_None, // VMINI_HU = 1255
8397 CEFBS_None, // VMINI_W = 1256
8398 CEFBS_None, // VMINI_WU = 1257
8399 CEFBS_None, // VMIN_B = 1258
8400 CEFBS_None, // VMIN_BU = 1259
8401 CEFBS_None, // VMIN_D = 1260
8402 CEFBS_None, // VMIN_DU = 1261
8403 CEFBS_None, // VMIN_H = 1262
8404 CEFBS_None, // VMIN_HU = 1263
8405 CEFBS_None, // VMIN_W = 1264
8406 CEFBS_None, // VMIN_WU = 1265
8407 CEFBS_None, // VMOD_B = 1266
8408 CEFBS_None, // VMOD_BU = 1267
8409 CEFBS_None, // VMOD_D = 1268
8410 CEFBS_None, // VMOD_DU = 1269
8411 CEFBS_None, // VMOD_H = 1270
8412 CEFBS_None, // VMOD_HU = 1271
8413 CEFBS_None, // VMOD_W = 1272
8414 CEFBS_None, // VMOD_WU = 1273
8415 CEFBS_None, // VMSKGEZ_B = 1274
8416 CEFBS_None, // VMSKLTZ_B = 1275
8417 CEFBS_None, // VMSKLTZ_D = 1276
8418 CEFBS_None, // VMSKLTZ_H = 1277
8419 CEFBS_None, // VMSKLTZ_W = 1278
8420 CEFBS_None, // VMSKNZ_B = 1279
8421 CEFBS_None, // VMSUB_B = 1280
8422 CEFBS_None, // VMSUB_D = 1281
8423 CEFBS_None, // VMSUB_H = 1282
8424 CEFBS_None, // VMSUB_W = 1283
8425 CEFBS_None, // VMUH_B = 1284
8426 CEFBS_None, // VMUH_BU = 1285
8427 CEFBS_None, // VMUH_D = 1286
8428 CEFBS_None, // VMUH_DU = 1287
8429 CEFBS_None, // VMUH_H = 1288
8430 CEFBS_None, // VMUH_HU = 1289
8431 CEFBS_None, // VMUH_W = 1290
8432 CEFBS_None, // VMUH_WU = 1291
8433 CEFBS_None, // VMULWEV_D_W = 1292
8434 CEFBS_None, // VMULWEV_D_WU = 1293
8435 CEFBS_None, // VMULWEV_D_WU_W = 1294
8436 CEFBS_None, // VMULWEV_H_B = 1295
8437 CEFBS_None, // VMULWEV_H_BU = 1296
8438 CEFBS_None, // VMULWEV_H_BU_B = 1297
8439 CEFBS_None, // VMULWEV_Q_D = 1298
8440 CEFBS_None, // VMULWEV_Q_DU = 1299
8441 CEFBS_None, // VMULWEV_Q_DU_D = 1300
8442 CEFBS_None, // VMULWEV_W_H = 1301
8443 CEFBS_None, // VMULWEV_W_HU = 1302
8444 CEFBS_None, // VMULWEV_W_HU_H = 1303
8445 CEFBS_None, // VMULWOD_D_W = 1304
8446 CEFBS_None, // VMULWOD_D_WU = 1305
8447 CEFBS_None, // VMULWOD_D_WU_W = 1306
8448 CEFBS_None, // VMULWOD_H_B = 1307
8449 CEFBS_None, // VMULWOD_H_BU = 1308
8450 CEFBS_None, // VMULWOD_H_BU_B = 1309
8451 CEFBS_None, // VMULWOD_Q_D = 1310
8452 CEFBS_None, // VMULWOD_Q_DU = 1311
8453 CEFBS_None, // VMULWOD_Q_DU_D = 1312
8454 CEFBS_None, // VMULWOD_W_H = 1313
8455 CEFBS_None, // VMULWOD_W_HU = 1314
8456 CEFBS_None, // VMULWOD_W_HU_H = 1315
8457 CEFBS_None, // VMUL_B = 1316
8458 CEFBS_None, // VMUL_D = 1317
8459 CEFBS_None, // VMUL_H = 1318
8460 CEFBS_None, // VMUL_W = 1319
8461 CEFBS_None, // VNEG_B = 1320
8462 CEFBS_None, // VNEG_D = 1321
8463 CEFBS_None, // VNEG_H = 1322
8464 CEFBS_None, // VNEG_W = 1323
8465 CEFBS_None, // VNORI_B = 1324
8466 CEFBS_None, // VNOR_V = 1325
8467 CEFBS_None, // VORI_B = 1326
8468 CEFBS_None, // VORN_V = 1327
8469 CEFBS_None, // VOR_V = 1328
8470 CEFBS_None, // VPACKEV_B = 1329
8471 CEFBS_None, // VPACKEV_D = 1330
8472 CEFBS_None, // VPACKEV_H = 1331
8473 CEFBS_None, // VPACKEV_W = 1332
8474 CEFBS_None, // VPACKOD_B = 1333
8475 CEFBS_None, // VPACKOD_D = 1334
8476 CEFBS_None, // VPACKOD_H = 1335
8477 CEFBS_None, // VPACKOD_W = 1336
8478 CEFBS_None, // VPCNT_B = 1337
8479 CEFBS_None, // VPCNT_D = 1338
8480 CEFBS_None, // VPCNT_H = 1339
8481 CEFBS_None, // VPCNT_W = 1340
8482 CEFBS_None, // VPERMI_W = 1341
8483 CEFBS_None, // VPICKEV_B = 1342
8484 CEFBS_None, // VPICKEV_D = 1343
8485 CEFBS_None, // VPICKEV_H = 1344
8486 CEFBS_None, // VPICKEV_W = 1345
8487 CEFBS_None, // VPICKOD_B = 1346
8488 CEFBS_None, // VPICKOD_D = 1347
8489 CEFBS_None, // VPICKOD_H = 1348
8490 CEFBS_None, // VPICKOD_W = 1349
8491 CEFBS_None, // VPICKVE2GR_B = 1350
8492 CEFBS_None, // VPICKVE2GR_BU = 1351
8493 CEFBS_None, // VPICKVE2GR_D = 1352
8494 CEFBS_None, // VPICKVE2GR_DU = 1353
8495 CEFBS_None, // VPICKVE2GR_H = 1354
8496 CEFBS_None, // VPICKVE2GR_HU = 1355
8497 CEFBS_None, // VPICKVE2GR_W = 1356
8498 CEFBS_None, // VPICKVE2GR_WU = 1357
8499 CEFBS_None, // VREPLGR2VR_B = 1358
8500 CEFBS_None, // VREPLGR2VR_D = 1359
8501 CEFBS_None, // VREPLGR2VR_H = 1360
8502 CEFBS_None, // VREPLGR2VR_W = 1361
8503 CEFBS_None, // VREPLVEI_B = 1362
8504 CEFBS_None, // VREPLVEI_D = 1363
8505 CEFBS_None, // VREPLVEI_H = 1364
8506 CEFBS_None, // VREPLVEI_W = 1365
8507 CEFBS_None, // VREPLVE_B = 1366
8508 CEFBS_None, // VREPLVE_D = 1367
8509 CEFBS_None, // VREPLVE_H = 1368
8510 CEFBS_None, // VREPLVE_W = 1369
8511 CEFBS_None, // VROTRI_B = 1370
8512 CEFBS_None, // VROTRI_D = 1371
8513 CEFBS_None, // VROTRI_H = 1372
8514 CEFBS_None, // VROTRI_W = 1373
8515 CEFBS_None, // VROTR_B = 1374
8516 CEFBS_None, // VROTR_D = 1375
8517 CEFBS_None, // VROTR_H = 1376
8518 CEFBS_None, // VROTR_W = 1377
8519 CEFBS_None, // VSADD_B = 1378
8520 CEFBS_None, // VSADD_BU = 1379
8521 CEFBS_None, // VSADD_D = 1380
8522 CEFBS_None, // VSADD_DU = 1381
8523 CEFBS_None, // VSADD_H = 1382
8524 CEFBS_None, // VSADD_HU = 1383
8525 CEFBS_None, // VSADD_W = 1384
8526 CEFBS_None, // VSADD_WU = 1385
8527 CEFBS_None, // VSAT_B = 1386
8528 CEFBS_None, // VSAT_BU = 1387
8529 CEFBS_None, // VSAT_D = 1388
8530 CEFBS_None, // VSAT_DU = 1389
8531 CEFBS_None, // VSAT_H = 1390
8532 CEFBS_None, // VSAT_HU = 1391
8533 CEFBS_None, // VSAT_W = 1392
8534 CEFBS_None, // VSAT_WU = 1393
8535 CEFBS_None, // VSEQI_B = 1394
8536 CEFBS_None, // VSEQI_D = 1395
8537 CEFBS_None, // VSEQI_H = 1396
8538 CEFBS_None, // VSEQI_W = 1397
8539 CEFBS_None, // VSEQ_B = 1398
8540 CEFBS_None, // VSEQ_D = 1399
8541 CEFBS_None, // VSEQ_H = 1400
8542 CEFBS_None, // VSEQ_W = 1401
8543 CEFBS_None, // VSETALLNEZ_B = 1402
8544 CEFBS_None, // VSETALLNEZ_D = 1403
8545 CEFBS_None, // VSETALLNEZ_H = 1404
8546 CEFBS_None, // VSETALLNEZ_W = 1405
8547 CEFBS_None, // VSETANYEQZ_B = 1406
8548 CEFBS_None, // VSETANYEQZ_D = 1407
8549 CEFBS_None, // VSETANYEQZ_H = 1408
8550 CEFBS_None, // VSETANYEQZ_W = 1409
8551 CEFBS_None, // VSETEQZ_V = 1410
8552 CEFBS_None, // VSETNEZ_V = 1411
8553 CEFBS_None, // VSHUF4I_B = 1412
8554 CEFBS_None, // VSHUF4I_D = 1413
8555 CEFBS_None, // VSHUF4I_H = 1414
8556 CEFBS_None, // VSHUF4I_W = 1415
8557 CEFBS_None, // VSHUF_B = 1416
8558 CEFBS_None, // VSHUF_D = 1417
8559 CEFBS_None, // VSHUF_H = 1418
8560 CEFBS_None, // VSHUF_W = 1419
8561 CEFBS_None, // VSIGNCOV_B = 1420
8562 CEFBS_None, // VSIGNCOV_D = 1421
8563 CEFBS_None, // VSIGNCOV_H = 1422
8564 CEFBS_None, // VSIGNCOV_W = 1423
8565 CEFBS_None, // VSLEI_B = 1424
8566 CEFBS_None, // VSLEI_BU = 1425
8567 CEFBS_None, // VSLEI_D = 1426
8568 CEFBS_None, // VSLEI_DU = 1427
8569 CEFBS_None, // VSLEI_H = 1428
8570 CEFBS_None, // VSLEI_HU = 1429
8571 CEFBS_None, // VSLEI_W = 1430
8572 CEFBS_None, // VSLEI_WU = 1431
8573 CEFBS_None, // VSLE_B = 1432
8574 CEFBS_None, // VSLE_BU = 1433
8575 CEFBS_None, // VSLE_D = 1434
8576 CEFBS_None, // VSLE_DU = 1435
8577 CEFBS_None, // VSLE_H = 1436
8578 CEFBS_None, // VSLE_HU = 1437
8579 CEFBS_None, // VSLE_W = 1438
8580 CEFBS_None, // VSLE_WU = 1439
8581 CEFBS_None, // VSLLI_B = 1440
8582 CEFBS_None, // VSLLI_D = 1441
8583 CEFBS_None, // VSLLI_H = 1442
8584 CEFBS_None, // VSLLI_W = 1443
8585 CEFBS_None, // VSLLWIL_DU_WU = 1444
8586 CEFBS_None, // VSLLWIL_D_W = 1445
8587 CEFBS_None, // VSLLWIL_HU_BU = 1446
8588 CEFBS_None, // VSLLWIL_H_B = 1447
8589 CEFBS_None, // VSLLWIL_WU_HU = 1448
8590 CEFBS_None, // VSLLWIL_W_H = 1449
8591 CEFBS_None, // VSLL_B = 1450
8592 CEFBS_None, // VSLL_D = 1451
8593 CEFBS_None, // VSLL_H = 1452
8594 CEFBS_None, // VSLL_W = 1453
8595 CEFBS_None, // VSLTI_B = 1454
8596 CEFBS_None, // VSLTI_BU = 1455
8597 CEFBS_None, // VSLTI_D = 1456
8598 CEFBS_None, // VSLTI_DU = 1457
8599 CEFBS_None, // VSLTI_H = 1458
8600 CEFBS_None, // VSLTI_HU = 1459
8601 CEFBS_None, // VSLTI_W = 1460
8602 CEFBS_None, // VSLTI_WU = 1461
8603 CEFBS_None, // VSLT_B = 1462
8604 CEFBS_None, // VSLT_BU = 1463
8605 CEFBS_None, // VSLT_D = 1464
8606 CEFBS_None, // VSLT_DU = 1465
8607 CEFBS_None, // VSLT_H = 1466
8608 CEFBS_None, // VSLT_HU = 1467
8609 CEFBS_None, // VSLT_W = 1468
8610 CEFBS_None, // VSLT_WU = 1469
8611 CEFBS_None, // VSRAI_B = 1470
8612 CEFBS_None, // VSRAI_D = 1471
8613 CEFBS_None, // VSRAI_H = 1472
8614 CEFBS_None, // VSRAI_W = 1473
8615 CEFBS_None, // VSRANI_B_H = 1474
8616 CEFBS_None, // VSRANI_D_Q = 1475
8617 CEFBS_None, // VSRANI_H_W = 1476
8618 CEFBS_None, // VSRANI_W_D = 1477
8619 CEFBS_None, // VSRAN_B_H = 1478
8620 CEFBS_None, // VSRAN_H_W = 1479
8621 CEFBS_None, // VSRAN_W_D = 1480
8622 CEFBS_None, // VSRARI_B = 1481
8623 CEFBS_None, // VSRARI_D = 1482
8624 CEFBS_None, // VSRARI_H = 1483
8625 CEFBS_None, // VSRARI_W = 1484
8626 CEFBS_None, // VSRARNI_B_H = 1485
8627 CEFBS_None, // VSRARNI_D_Q = 1486
8628 CEFBS_None, // VSRARNI_H_W = 1487
8629 CEFBS_None, // VSRARNI_W_D = 1488
8630 CEFBS_None, // VSRARN_B_H = 1489
8631 CEFBS_None, // VSRARN_H_W = 1490
8632 CEFBS_None, // VSRARN_W_D = 1491
8633 CEFBS_None, // VSRAR_B = 1492
8634 CEFBS_None, // VSRAR_D = 1493
8635 CEFBS_None, // VSRAR_H = 1494
8636 CEFBS_None, // VSRAR_W = 1495
8637 CEFBS_None, // VSRA_B = 1496
8638 CEFBS_None, // VSRA_D = 1497
8639 CEFBS_None, // VSRA_H = 1498
8640 CEFBS_None, // VSRA_W = 1499
8641 CEFBS_None, // VSRLI_B = 1500
8642 CEFBS_None, // VSRLI_D = 1501
8643 CEFBS_None, // VSRLI_H = 1502
8644 CEFBS_None, // VSRLI_W = 1503
8645 CEFBS_None, // VSRLNI_B_H = 1504
8646 CEFBS_None, // VSRLNI_D_Q = 1505
8647 CEFBS_None, // VSRLNI_H_W = 1506
8648 CEFBS_None, // VSRLNI_W_D = 1507
8649 CEFBS_None, // VSRLN_B_H = 1508
8650 CEFBS_None, // VSRLN_H_W = 1509
8651 CEFBS_None, // VSRLN_W_D = 1510
8652 CEFBS_None, // VSRLRI_B = 1511
8653 CEFBS_None, // VSRLRI_D = 1512
8654 CEFBS_None, // VSRLRI_H = 1513
8655 CEFBS_None, // VSRLRI_W = 1514
8656 CEFBS_None, // VSRLRNI_B_H = 1515
8657 CEFBS_None, // VSRLRNI_D_Q = 1516
8658 CEFBS_None, // VSRLRNI_H_W = 1517
8659 CEFBS_None, // VSRLRNI_W_D = 1518
8660 CEFBS_None, // VSRLRN_B_H = 1519
8661 CEFBS_None, // VSRLRN_H_W = 1520
8662 CEFBS_None, // VSRLRN_W_D = 1521
8663 CEFBS_None, // VSRLR_B = 1522
8664 CEFBS_None, // VSRLR_D = 1523
8665 CEFBS_None, // VSRLR_H = 1524
8666 CEFBS_None, // VSRLR_W = 1525
8667 CEFBS_None, // VSRL_B = 1526
8668 CEFBS_None, // VSRL_D = 1527
8669 CEFBS_None, // VSRL_H = 1528
8670 CEFBS_None, // VSRL_W = 1529
8671 CEFBS_None, // VSSRANI_BU_H = 1530
8672 CEFBS_None, // VSSRANI_B_H = 1531
8673 CEFBS_None, // VSSRANI_DU_Q = 1532
8674 CEFBS_None, // VSSRANI_D_Q = 1533
8675 CEFBS_None, // VSSRANI_HU_W = 1534
8676 CEFBS_None, // VSSRANI_H_W = 1535
8677 CEFBS_None, // VSSRANI_WU_D = 1536
8678 CEFBS_None, // VSSRANI_W_D = 1537
8679 CEFBS_None, // VSSRAN_BU_H = 1538
8680 CEFBS_None, // VSSRAN_B_H = 1539
8681 CEFBS_None, // VSSRAN_HU_W = 1540
8682 CEFBS_None, // VSSRAN_H_W = 1541
8683 CEFBS_None, // VSSRAN_WU_D = 1542
8684 CEFBS_None, // VSSRAN_W_D = 1543
8685 CEFBS_None, // VSSRARNI_BU_H = 1544
8686 CEFBS_None, // VSSRARNI_B_H = 1545
8687 CEFBS_None, // VSSRARNI_DU_Q = 1546
8688 CEFBS_None, // VSSRARNI_D_Q = 1547
8689 CEFBS_None, // VSSRARNI_HU_W = 1548
8690 CEFBS_None, // VSSRARNI_H_W = 1549
8691 CEFBS_None, // VSSRARNI_WU_D = 1550
8692 CEFBS_None, // VSSRARNI_W_D = 1551
8693 CEFBS_None, // VSSRARN_BU_H = 1552
8694 CEFBS_None, // VSSRARN_B_H = 1553
8695 CEFBS_None, // VSSRARN_HU_W = 1554
8696 CEFBS_None, // VSSRARN_H_W = 1555
8697 CEFBS_None, // VSSRARN_WU_D = 1556
8698 CEFBS_None, // VSSRARN_W_D = 1557
8699 CEFBS_None, // VSSRLNI_BU_H = 1558
8700 CEFBS_None, // VSSRLNI_B_H = 1559
8701 CEFBS_None, // VSSRLNI_DU_Q = 1560
8702 CEFBS_None, // VSSRLNI_D_Q = 1561
8703 CEFBS_None, // VSSRLNI_HU_W = 1562
8704 CEFBS_None, // VSSRLNI_H_W = 1563
8705 CEFBS_None, // VSSRLNI_WU_D = 1564
8706 CEFBS_None, // VSSRLNI_W_D = 1565
8707 CEFBS_None, // VSSRLN_BU_H = 1566
8708 CEFBS_None, // VSSRLN_B_H = 1567
8709 CEFBS_None, // VSSRLN_HU_W = 1568
8710 CEFBS_None, // VSSRLN_H_W = 1569
8711 CEFBS_None, // VSSRLN_WU_D = 1570
8712 CEFBS_None, // VSSRLN_W_D = 1571
8713 CEFBS_None, // VSSRLRNI_BU_H = 1572
8714 CEFBS_None, // VSSRLRNI_B_H = 1573
8715 CEFBS_None, // VSSRLRNI_DU_Q = 1574
8716 CEFBS_None, // VSSRLRNI_D_Q = 1575
8717 CEFBS_None, // VSSRLRNI_HU_W = 1576
8718 CEFBS_None, // VSSRLRNI_H_W = 1577
8719 CEFBS_None, // VSSRLRNI_WU_D = 1578
8720 CEFBS_None, // VSSRLRNI_W_D = 1579
8721 CEFBS_None, // VSSRLRN_BU_H = 1580
8722 CEFBS_None, // VSSRLRN_B_H = 1581
8723 CEFBS_None, // VSSRLRN_HU_W = 1582
8724 CEFBS_None, // VSSRLRN_H_W = 1583
8725 CEFBS_None, // VSSRLRN_WU_D = 1584
8726 CEFBS_None, // VSSRLRN_W_D = 1585
8727 CEFBS_None, // VSSUB_B = 1586
8728 CEFBS_None, // VSSUB_BU = 1587
8729 CEFBS_None, // VSSUB_D = 1588
8730 CEFBS_None, // VSSUB_DU = 1589
8731 CEFBS_None, // VSSUB_H = 1590
8732 CEFBS_None, // VSSUB_HU = 1591
8733 CEFBS_None, // VSSUB_W = 1592
8734 CEFBS_None, // VSSUB_WU = 1593
8735 CEFBS_None, // VST = 1594
8736 CEFBS_None, // VSTELM_B = 1595
8737 CEFBS_None, // VSTELM_D = 1596
8738 CEFBS_None, // VSTELM_H = 1597
8739 CEFBS_None, // VSTELM_W = 1598
8740 CEFBS_None, // VSTX = 1599
8741 CEFBS_None, // VSUBI_BU = 1600
8742 CEFBS_None, // VSUBI_DU = 1601
8743 CEFBS_None, // VSUBI_HU = 1602
8744 CEFBS_None, // VSUBI_WU = 1603
8745 CEFBS_None, // VSUBWEV_D_W = 1604
8746 CEFBS_None, // VSUBWEV_D_WU = 1605
8747 CEFBS_None, // VSUBWEV_H_B = 1606
8748 CEFBS_None, // VSUBWEV_H_BU = 1607
8749 CEFBS_None, // VSUBWEV_Q_D = 1608
8750 CEFBS_None, // VSUBWEV_Q_DU = 1609
8751 CEFBS_None, // VSUBWEV_W_H = 1610
8752 CEFBS_None, // VSUBWEV_W_HU = 1611
8753 CEFBS_None, // VSUBWOD_D_W = 1612
8754 CEFBS_None, // VSUBWOD_D_WU = 1613
8755 CEFBS_None, // VSUBWOD_H_B = 1614
8756 CEFBS_None, // VSUBWOD_H_BU = 1615
8757 CEFBS_None, // VSUBWOD_Q_D = 1616
8758 CEFBS_None, // VSUBWOD_Q_DU = 1617
8759 CEFBS_None, // VSUBWOD_W_H = 1618
8760 CEFBS_None, // VSUBWOD_W_HU = 1619
8761 CEFBS_None, // VSUB_B = 1620
8762 CEFBS_None, // VSUB_D = 1621
8763 CEFBS_None, // VSUB_H = 1622
8764 CEFBS_None, // VSUB_Q = 1623
8765 CEFBS_None, // VSUB_W = 1624
8766 CEFBS_None, // VXORI_B = 1625
8767 CEFBS_None, // VXOR_V = 1626
8768 CEFBS_None, // X86ADC_B = 1627
8769 CEFBS_IsLA64, // X86ADC_D = 1628
8770 CEFBS_None, // X86ADC_H = 1629
8771 CEFBS_None, // X86ADC_W = 1630
8772 CEFBS_None, // X86ADD_B = 1631
8773 CEFBS_IsLA64, // X86ADD_D = 1632
8774 CEFBS_IsLA64, // X86ADD_DU = 1633
8775 CEFBS_None, // X86ADD_H = 1634
8776 CEFBS_None, // X86ADD_W = 1635
8777 CEFBS_IsLA64, // X86ADD_WU = 1636
8778 CEFBS_None, // X86AND_B = 1637
8779 CEFBS_IsLA64, // X86AND_D = 1638
8780 CEFBS_None, // X86AND_H = 1639
8781 CEFBS_None, // X86AND_W = 1640
8782 CEFBS_None, // X86CLRTM = 1641
8783 CEFBS_None, // X86DECTOP = 1642
8784 CEFBS_None, // X86DEC_B = 1643
8785 CEFBS_IsLA64, // X86DEC_D = 1644
8786 CEFBS_None, // X86DEC_H = 1645
8787 CEFBS_None, // X86DEC_W = 1646
8788 CEFBS_None, // X86INCTOP = 1647
8789 CEFBS_None, // X86INC_B = 1648
8790 CEFBS_IsLA64, // X86INC_D = 1649
8791 CEFBS_None, // X86INC_H = 1650
8792 CEFBS_None, // X86INC_W = 1651
8793 CEFBS_None, // X86MFFLAG = 1652
8794 CEFBS_None, // X86MFTOP = 1653
8795 CEFBS_None, // X86MTFLAG = 1654
8796 CEFBS_None, // X86MTTOP = 1655
8797 CEFBS_None, // X86MUL_B = 1656
8798 CEFBS_None, // X86MUL_BU = 1657
8799 CEFBS_IsLA64, // X86MUL_D = 1658
8800 CEFBS_IsLA64, // X86MUL_DU = 1659
8801 CEFBS_None, // X86MUL_H = 1660
8802 CEFBS_None, // X86MUL_HU = 1661
8803 CEFBS_None, // X86MUL_W = 1662
8804 CEFBS_IsLA64, // X86MUL_WU = 1663
8805 CEFBS_None, // X86OR_B = 1664
8806 CEFBS_IsLA64, // X86OR_D = 1665
8807 CEFBS_None, // X86OR_H = 1666
8808 CEFBS_None, // X86OR_W = 1667
8809 CEFBS_None, // X86RCLI_B = 1668
8810 CEFBS_IsLA64, // X86RCLI_D = 1669
8811 CEFBS_None, // X86RCLI_H = 1670
8812 CEFBS_None, // X86RCLI_W = 1671
8813 CEFBS_None, // X86RCL_B = 1672
8814 CEFBS_IsLA64, // X86RCL_D = 1673
8815 CEFBS_None, // X86RCL_H = 1674
8816 CEFBS_None, // X86RCL_W = 1675
8817 CEFBS_None, // X86RCRI_B = 1676
8818 CEFBS_IsLA64, // X86RCRI_D = 1677
8819 CEFBS_None, // X86RCRI_H = 1678
8820 CEFBS_None, // X86RCRI_W = 1679
8821 CEFBS_None, // X86RCR_B = 1680
8822 CEFBS_IsLA64, // X86RCR_D = 1681
8823 CEFBS_None, // X86RCR_H = 1682
8824 CEFBS_None, // X86RCR_W = 1683
8825 CEFBS_None, // X86ROTLI_B = 1684
8826 CEFBS_IsLA64, // X86ROTLI_D = 1685
8827 CEFBS_None, // X86ROTLI_H = 1686
8828 CEFBS_None, // X86ROTLI_W = 1687
8829 CEFBS_None, // X86ROTL_B = 1688
8830 CEFBS_IsLA64, // X86ROTL_D = 1689
8831 CEFBS_None, // X86ROTL_H = 1690
8832 CEFBS_None, // X86ROTL_W = 1691
8833 CEFBS_None, // X86ROTRI_B = 1692
8834 CEFBS_IsLA64, // X86ROTRI_D = 1693
8835 CEFBS_None, // X86ROTRI_H = 1694
8836 CEFBS_None, // X86ROTRI_W = 1695
8837 CEFBS_None, // X86ROTR_B = 1696
8838 CEFBS_IsLA64, // X86ROTR_D = 1697
8839 CEFBS_None, // X86ROTR_H = 1698
8840 CEFBS_None, // X86ROTR_W = 1699
8841 CEFBS_None, // X86SBC_B = 1700
8842 CEFBS_IsLA64, // X86SBC_D = 1701
8843 CEFBS_None, // X86SBC_H = 1702
8844 CEFBS_None, // X86SBC_W = 1703
8845 CEFBS_None, // X86SETTAG = 1704
8846 CEFBS_None, // X86SETTM = 1705
8847 CEFBS_None, // X86SLLI_B = 1706
8848 CEFBS_IsLA64, // X86SLLI_D = 1707
8849 CEFBS_None, // X86SLLI_H = 1708
8850 CEFBS_None, // X86SLLI_W = 1709
8851 CEFBS_None, // X86SLL_B = 1710
8852 CEFBS_IsLA64, // X86SLL_D = 1711
8853 CEFBS_None, // X86SLL_H = 1712
8854 CEFBS_None, // X86SLL_W = 1713
8855 CEFBS_None, // X86SRAI_B = 1714
8856 CEFBS_IsLA64, // X86SRAI_D = 1715
8857 CEFBS_None, // X86SRAI_H = 1716
8858 CEFBS_None, // X86SRAI_W = 1717
8859 CEFBS_None, // X86SRA_B = 1718
8860 CEFBS_IsLA64, // X86SRA_D = 1719
8861 CEFBS_None, // X86SRA_H = 1720
8862 CEFBS_None, // X86SRA_W = 1721
8863 CEFBS_None, // X86SRLI_B = 1722
8864 CEFBS_IsLA64, // X86SRLI_D = 1723
8865 CEFBS_None, // X86SRLI_H = 1724
8866 CEFBS_None, // X86SRLI_W = 1725
8867 CEFBS_None, // X86SRL_B = 1726
8868 CEFBS_IsLA64, // X86SRL_D = 1727
8869 CEFBS_None, // X86SRL_H = 1728
8870 CEFBS_None, // X86SRL_W = 1729
8871 CEFBS_None, // X86SUB_B = 1730
8872 CEFBS_IsLA64, // X86SUB_D = 1731
8873 CEFBS_IsLA64, // X86SUB_DU = 1732
8874 CEFBS_None, // X86SUB_H = 1733
8875 CEFBS_None, // X86SUB_W = 1734
8876 CEFBS_IsLA64, // X86SUB_WU = 1735
8877 CEFBS_None, // X86XOR_B = 1736
8878 CEFBS_IsLA64, // X86XOR_D = 1737
8879 CEFBS_None, // X86XOR_H = 1738
8880 CEFBS_None, // X86XOR_W = 1739
8881 CEFBS_None, // XOR = 1740
8882 CEFBS_None, // XORI = 1741
8883 CEFBS_None, // XVABSD_B = 1742
8884 CEFBS_None, // XVABSD_BU = 1743
8885 CEFBS_None, // XVABSD_D = 1744
8886 CEFBS_None, // XVABSD_DU = 1745
8887 CEFBS_None, // XVABSD_H = 1746
8888 CEFBS_None, // XVABSD_HU = 1747
8889 CEFBS_None, // XVABSD_W = 1748
8890 CEFBS_None, // XVABSD_WU = 1749
8891 CEFBS_None, // XVADDA_B = 1750
8892 CEFBS_None, // XVADDA_D = 1751
8893 CEFBS_None, // XVADDA_H = 1752
8894 CEFBS_None, // XVADDA_W = 1753
8895 CEFBS_None, // XVADDI_BU = 1754
8896 CEFBS_None, // XVADDI_DU = 1755
8897 CEFBS_None, // XVADDI_HU = 1756
8898 CEFBS_None, // XVADDI_WU = 1757
8899 CEFBS_None, // XVADDWEV_D_W = 1758
8900 CEFBS_None, // XVADDWEV_D_WU = 1759
8901 CEFBS_None, // XVADDWEV_D_WU_W = 1760
8902 CEFBS_None, // XVADDWEV_H_B = 1761
8903 CEFBS_None, // XVADDWEV_H_BU = 1762
8904 CEFBS_None, // XVADDWEV_H_BU_B = 1763
8905 CEFBS_None, // XVADDWEV_Q_D = 1764
8906 CEFBS_None, // XVADDWEV_Q_DU = 1765
8907 CEFBS_None, // XVADDWEV_Q_DU_D = 1766
8908 CEFBS_None, // XVADDWEV_W_H = 1767
8909 CEFBS_None, // XVADDWEV_W_HU = 1768
8910 CEFBS_None, // XVADDWEV_W_HU_H = 1769
8911 CEFBS_None, // XVADDWOD_D_W = 1770
8912 CEFBS_None, // XVADDWOD_D_WU = 1771
8913 CEFBS_None, // XVADDWOD_D_WU_W = 1772
8914 CEFBS_None, // XVADDWOD_H_B = 1773
8915 CEFBS_None, // XVADDWOD_H_BU = 1774
8916 CEFBS_None, // XVADDWOD_H_BU_B = 1775
8917 CEFBS_None, // XVADDWOD_Q_D = 1776
8918 CEFBS_None, // XVADDWOD_Q_DU = 1777
8919 CEFBS_None, // XVADDWOD_Q_DU_D = 1778
8920 CEFBS_None, // XVADDWOD_W_H = 1779
8921 CEFBS_None, // XVADDWOD_W_HU = 1780
8922 CEFBS_None, // XVADDWOD_W_HU_H = 1781
8923 CEFBS_None, // XVADD_B = 1782
8924 CEFBS_None, // XVADD_D = 1783
8925 CEFBS_None, // XVADD_H = 1784
8926 CEFBS_None, // XVADD_Q = 1785
8927 CEFBS_None, // XVADD_W = 1786
8928 CEFBS_None, // XVANDI_B = 1787
8929 CEFBS_None, // XVANDN_V = 1788
8930 CEFBS_None, // XVAND_V = 1789
8931 CEFBS_None, // XVAVGR_B = 1790
8932 CEFBS_None, // XVAVGR_BU = 1791
8933 CEFBS_None, // XVAVGR_D = 1792
8934 CEFBS_None, // XVAVGR_DU = 1793
8935 CEFBS_None, // XVAVGR_H = 1794
8936 CEFBS_None, // XVAVGR_HU = 1795
8937 CEFBS_None, // XVAVGR_W = 1796
8938 CEFBS_None, // XVAVGR_WU = 1797
8939 CEFBS_None, // XVAVG_B = 1798
8940 CEFBS_None, // XVAVG_BU = 1799
8941 CEFBS_None, // XVAVG_D = 1800
8942 CEFBS_None, // XVAVG_DU = 1801
8943 CEFBS_None, // XVAVG_H = 1802
8944 CEFBS_None, // XVAVG_HU = 1803
8945 CEFBS_None, // XVAVG_W = 1804
8946 CEFBS_None, // XVAVG_WU = 1805
8947 CEFBS_None, // XVBITCLRI_B = 1806
8948 CEFBS_None, // XVBITCLRI_D = 1807
8949 CEFBS_None, // XVBITCLRI_H = 1808
8950 CEFBS_None, // XVBITCLRI_W = 1809
8951 CEFBS_None, // XVBITCLR_B = 1810
8952 CEFBS_None, // XVBITCLR_D = 1811
8953 CEFBS_None, // XVBITCLR_H = 1812
8954 CEFBS_None, // XVBITCLR_W = 1813
8955 CEFBS_None, // XVBITREVI_B = 1814
8956 CEFBS_None, // XVBITREVI_D = 1815
8957 CEFBS_None, // XVBITREVI_H = 1816
8958 CEFBS_None, // XVBITREVI_W = 1817
8959 CEFBS_None, // XVBITREV_B = 1818
8960 CEFBS_None, // XVBITREV_D = 1819
8961 CEFBS_None, // XVBITREV_H = 1820
8962 CEFBS_None, // XVBITREV_W = 1821
8963 CEFBS_None, // XVBITSELI_B = 1822
8964 CEFBS_None, // XVBITSEL_V = 1823
8965 CEFBS_None, // XVBITSETI_B = 1824
8966 CEFBS_None, // XVBITSETI_D = 1825
8967 CEFBS_None, // XVBITSETI_H = 1826
8968 CEFBS_None, // XVBITSETI_W = 1827
8969 CEFBS_None, // XVBITSET_B = 1828
8970 CEFBS_None, // XVBITSET_D = 1829
8971 CEFBS_None, // XVBITSET_H = 1830
8972 CEFBS_None, // XVBITSET_W = 1831
8973 CEFBS_None, // XVBSLL_V = 1832
8974 CEFBS_None, // XVBSRL_V = 1833
8975 CEFBS_None, // XVCLO_B = 1834
8976 CEFBS_None, // XVCLO_D = 1835
8977 CEFBS_None, // XVCLO_H = 1836
8978 CEFBS_None, // XVCLO_W = 1837
8979 CEFBS_None, // XVCLZ_B = 1838
8980 CEFBS_None, // XVCLZ_D = 1839
8981 CEFBS_None, // XVCLZ_H = 1840
8982 CEFBS_None, // XVCLZ_W = 1841
8983 CEFBS_None, // XVDIV_B = 1842
8984 CEFBS_None, // XVDIV_BU = 1843
8985 CEFBS_None, // XVDIV_D = 1844
8986 CEFBS_None, // XVDIV_DU = 1845
8987 CEFBS_None, // XVDIV_H = 1846
8988 CEFBS_None, // XVDIV_HU = 1847
8989 CEFBS_None, // XVDIV_W = 1848
8990 CEFBS_None, // XVDIV_WU = 1849
8991 CEFBS_None, // XVEXTH_DU_WU = 1850
8992 CEFBS_None, // XVEXTH_D_W = 1851
8993 CEFBS_None, // XVEXTH_HU_BU = 1852
8994 CEFBS_None, // XVEXTH_H_B = 1853
8995 CEFBS_None, // XVEXTH_QU_DU = 1854
8996 CEFBS_None, // XVEXTH_Q_D = 1855
8997 CEFBS_None, // XVEXTH_WU_HU = 1856
8998 CEFBS_None, // XVEXTH_W_H = 1857
8999 CEFBS_None, // XVEXTL_QU_DU = 1858
9000 CEFBS_None, // XVEXTL_Q_D = 1859
9001 CEFBS_None, // XVEXTRINS_B = 1860
9002 CEFBS_None, // XVEXTRINS_D = 1861
9003 CEFBS_None, // XVEXTRINS_H = 1862
9004 CEFBS_None, // XVEXTRINS_W = 1863
9005 CEFBS_None, // XVFADD_D = 1864
9006 CEFBS_None, // XVFADD_S = 1865
9007 CEFBS_None, // XVFCLASS_D = 1866
9008 CEFBS_None, // XVFCLASS_S = 1867
9009 CEFBS_None, // XVFCMP_CAF_D = 1868
9010 CEFBS_None, // XVFCMP_CAF_S = 1869
9011 CEFBS_None, // XVFCMP_CEQ_D = 1870
9012 CEFBS_None, // XVFCMP_CEQ_S = 1871
9013 CEFBS_None, // XVFCMP_CLE_D = 1872
9014 CEFBS_None, // XVFCMP_CLE_S = 1873
9015 CEFBS_None, // XVFCMP_CLT_D = 1874
9016 CEFBS_None, // XVFCMP_CLT_S = 1875
9017 CEFBS_None, // XVFCMP_CNE_D = 1876
9018 CEFBS_None, // XVFCMP_CNE_S = 1877
9019 CEFBS_None, // XVFCMP_COR_D = 1878
9020 CEFBS_None, // XVFCMP_COR_S = 1879
9021 CEFBS_None, // XVFCMP_CUEQ_D = 1880
9022 CEFBS_None, // XVFCMP_CUEQ_S = 1881
9023 CEFBS_None, // XVFCMP_CULE_D = 1882
9024 CEFBS_None, // XVFCMP_CULE_S = 1883
9025 CEFBS_None, // XVFCMP_CULT_D = 1884
9026 CEFBS_None, // XVFCMP_CULT_S = 1885
9027 CEFBS_None, // XVFCMP_CUNE_D = 1886
9028 CEFBS_None, // XVFCMP_CUNE_S = 1887
9029 CEFBS_None, // XVFCMP_CUN_D = 1888
9030 CEFBS_None, // XVFCMP_CUN_S = 1889
9031 CEFBS_None, // XVFCMP_SAF_D = 1890
9032 CEFBS_None, // XVFCMP_SAF_S = 1891
9033 CEFBS_None, // XVFCMP_SEQ_D = 1892
9034 CEFBS_None, // XVFCMP_SEQ_S = 1893
9035 CEFBS_None, // XVFCMP_SLE_D = 1894
9036 CEFBS_None, // XVFCMP_SLE_S = 1895
9037 CEFBS_None, // XVFCMP_SLT_D = 1896
9038 CEFBS_None, // XVFCMP_SLT_S = 1897
9039 CEFBS_None, // XVFCMP_SNE_D = 1898
9040 CEFBS_None, // XVFCMP_SNE_S = 1899
9041 CEFBS_None, // XVFCMP_SOR_D = 1900
9042 CEFBS_None, // XVFCMP_SOR_S = 1901
9043 CEFBS_None, // XVFCMP_SUEQ_D = 1902
9044 CEFBS_None, // XVFCMP_SUEQ_S = 1903
9045 CEFBS_None, // XVFCMP_SULE_D = 1904
9046 CEFBS_None, // XVFCMP_SULE_S = 1905
9047 CEFBS_None, // XVFCMP_SULT_D = 1906
9048 CEFBS_None, // XVFCMP_SULT_S = 1907
9049 CEFBS_None, // XVFCMP_SUNE_D = 1908
9050 CEFBS_None, // XVFCMP_SUNE_S = 1909
9051 CEFBS_None, // XVFCMP_SUN_D = 1910
9052 CEFBS_None, // XVFCMP_SUN_S = 1911
9053 CEFBS_None, // XVFCVTH_D_S = 1912
9054 CEFBS_None, // XVFCVTH_S_H = 1913
9055 CEFBS_None, // XVFCVTL_D_S = 1914
9056 CEFBS_None, // XVFCVTL_S_H = 1915
9057 CEFBS_None, // XVFCVT_H_S = 1916
9058 CEFBS_None, // XVFCVT_S_D = 1917
9059 CEFBS_None, // XVFDIV_D = 1918
9060 CEFBS_None, // XVFDIV_S = 1919
9061 CEFBS_None, // XVFFINTH_D_W = 1920
9062 CEFBS_None, // XVFFINTL_D_W = 1921
9063 CEFBS_None, // XVFFINT_D_L = 1922
9064 CEFBS_None, // XVFFINT_D_LU = 1923
9065 CEFBS_None, // XVFFINT_S_L = 1924
9066 CEFBS_None, // XVFFINT_S_W = 1925
9067 CEFBS_None, // XVFFINT_S_WU = 1926
9068 CEFBS_None, // XVFLOGB_D = 1927
9069 CEFBS_None, // XVFLOGB_S = 1928
9070 CEFBS_None, // XVFMADD_D = 1929
9071 CEFBS_None, // XVFMADD_S = 1930
9072 CEFBS_None, // XVFMAXA_D = 1931
9073 CEFBS_None, // XVFMAXA_S = 1932
9074 CEFBS_None, // XVFMAX_D = 1933
9075 CEFBS_None, // XVFMAX_S = 1934
9076 CEFBS_None, // XVFMINA_D = 1935
9077 CEFBS_None, // XVFMINA_S = 1936
9078 CEFBS_None, // XVFMIN_D = 1937
9079 CEFBS_None, // XVFMIN_S = 1938
9080 CEFBS_None, // XVFMSUB_D = 1939
9081 CEFBS_None, // XVFMSUB_S = 1940
9082 CEFBS_None, // XVFMUL_D = 1941
9083 CEFBS_None, // XVFMUL_S = 1942
9084 CEFBS_None, // XVFNMADD_D = 1943
9085 CEFBS_None, // XVFNMADD_S = 1944
9086 CEFBS_None, // XVFNMSUB_D = 1945
9087 CEFBS_None, // XVFNMSUB_S = 1946
9088 CEFBS_None, // XVFRECIPE_D = 1947
9089 CEFBS_None, // XVFRECIPE_S = 1948
9090 CEFBS_None, // XVFRECIP_D = 1949
9091 CEFBS_None, // XVFRECIP_S = 1950
9092 CEFBS_None, // XVFRINTRM_D = 1951
9093 CEFBS_None, // XVFRINTRM_S = 1952
9094 CEFBS_None, // XVFRINTRNE_D = 1953
9095 CEFBS_None, // XVFRINTRNE_S = 1954
9096 CEFBS_None, // XVFRINTRP_D = 1955
9097 CEFBS_None, // XVFRINTRP_S = 1956
9098 CEFBS_None, // XVFRINTRZ_D = 1957
9099 CEFBS_None, // XVFRINTRZ_S = 1958
9100 CEFBS_None, // XVFRINT_D = 1959
9101 CEFBS_None, // XVFRINT_S = 1960
9102 CEFBS_None, // XVFRSQRTE_D = 1961
9103 CEFBS_None, // XVFRSQRTE_S = 1962
9104 CEFBS_None, // XVFRSQRT_D = 1963
9105 CEFBS_None, // XVFRSQRT_S = 1964
9106 CEFBS_None, // XVFRSTPI_B = 1965
9107 CEFBS_None, // XVFRSTPI_H = 1966
9108 CEFBS_None, // XVFRSTP_B = 1967
9109 CEFBS_None, // XVFRSTP_H = 1968
9110 CEFBS_None, // XVFSQRT_D = 1969
9111 CEFBS_None, // XVFSQRT_S = 1970
9112 CEFBS_None, // XVFSUB_D = 1971
9113 CEFBS_None, // XVFSUB_S = 1972
9114 CEFBS_None, // XVFTINTH_L_S = 1973
9115 CEFBS_None, // XVFTINTL_L_S = 1974
9116 CEFBS_None, // XVFTINTRMH_L_S = 1975
9117 CEFBS_None, // XVFTINTRML_L_S = 1976
9118 CEFBS_None, // XVFTINTRM_L_D = 1977
9119 CEFBS_None, // XVFTINTRM_W_D = 1978
9120 CEFBS_None, // XVFTINTRM_W_S = 1979
9121 CEFBS_None, // XVFTINTRNEH_L_S = 1980
9122 CEFBS_None, // XVFTINTRNEL_L_S = 1981
9123 CEFBS_None, // XVFTINTRNE_L_D = 1982
9124 CEFBS_None, // XVFTINTRNE_W_D = 1983
9125 CEFBS_None, // XVFTINTRNE_W_S = 1984
9126 CEFBS_None, // XVFTINTRPH_L_S = 1985
9127 CEFBS_None, // XVFTINTRPL_L_S = 1986
9128 CEFBS_None, // XVFTINTRP_L_D = 1987
9129 CEFBS_None, // XVFTINTRP_W_D = 1988
9130 CEFBS_None, // XVFTINTRP_W_S = 1989
9131 CEFBS_None, // XVFTINTRZH_L_S = 1990
9132 CEFBS_None, // XVFTINTRZL_L_S = 1991
9133 CEFBS_None, // XVFTINTRZ_LU_D = 1992
9134 CEFBS_None, // XVFTINTRZ_L_D = 1993
9135 CEFBS_None, // XVFTINTRZ_WU_S = 1994
9136 CEFBS_None, // XVFTINTRZ_W_D = 1995
9137 CEFBS_None, // XVFTINTRZ_W_S = 1996
9138 CEFBS_None, // XVFTINT_LU_D = 1997
9139 CEFBS_None, // XVFTINT_L_D = 1998
9140 CEFBS_None, // XVFTINT_WU_S = 1999
9141 CEFBS_None, // XVFTINT_W_D = 2000
9142 CEFBS_None, // XVFTINT_W_S = 2001
9143 CEFBS_None, // XVHADDW_DU_WU = 2002
9144 CEFBS_None, // XVHADDW_D_W = 2003
9145 CEFBS_None, // XVHADDW_HU_BU = 2004
9146 CEFBS_None, // XVHADDW_H_B = 2005
9147 CEFBS_None, // XVHADDW_QU_DU = 2006
9148 CEFBS_None, // XVHADDW_Q_D = 2007
9149 CEFBS_None, // XVHADDW_WU_HU = 2008
9150 CEFBS_None, // XVHADDW_W_H = 2009
9151 CEFBS_None, // XVHSELI_D = 2010
9152 CEFBS_None, // XVHSUBW_DU_WU = 2011
9153 CEFBS_None, // XVHSUBW_D_W = 2012
9154 CEFBS_None, // XVHSUBW_HU_BU = 2013
9155 CEFBS_None, // XVHSUBW_H_B = 2014
9156 CEFBS_None, // XVHSUBW_QU_DU = 2015
9157 CEFBS_None, // XVHSUBW_Q_D = 2016
9158 CEFBS_None, // XVHSUBW_WU_HU = 2017
9159 CEFBS_None, // XVHSUBW_W_H = 2018
9160 CEFBS_None, // XVILVH_B = 2019
9161 CEFBS_None, // XVILVH_D = 2020
9162 CEFBS_None, // XVILVH_H = 2021
9163 CEFBS_None, // XVILVH_W = 2022
9164 CEFBS_None, // XVILVL_B = 2023
9165 CEFBS_None, // XVILVL_D = 2024
9166 CEFBS_None, // XVILVL_H = 2025
9167 CEFBS_None, // XVILVL_W = 2026
9168 CEFBS_None, // XVINSGR2VR_D = 2027
9169 CEFBS_None, // XVINSGR2VR_W = 2028
9170 CEFBS_None, // XVINSVE0_D = 2029
9171 CEFBS_None, // XVINSVE0_W = 2030
9172 CEFBS_None, // XVLD = 2031
9173 CEFBS_None, // XVLDI = 2032
9174 CEFBS_None, // XVLDREPL_B = 2033
9175 CEFBS_None, // XVLDREPL_D = 2034
9176 CEFBS_None, // XVLDREPL_H = 2035
9177 CEFBS_None, // XVLDREPL_W = 2036
9178 CEFBS_None, // XVLDX = 2037
9179 CEFBS_None, // XVMADDWEV_D_W = 2038
9180 CEFBS_None, // XVMADDWEV_D_WU = 2039
9181 CEFBS_None, // XVMADDWEV_D_WU_W = 2040
9182 CEFBS_None, // XVMADDWEV_H_B = 2041
9183 CEFBS_None, // XVMADDWEV_H_BU = 2042
9184 CEFBS_None, // XVMADDWEV_H_BU_B = 2043
9185 CEFBS_None, // XVMADDWEV_Q_D = 2044
9186 CEFBS_None, // XVMADDWEV_Q_DU = 2045
9187 CEFBS_None, // XVMADDWEV_Q_DU_D = 2046
9188 CEFBS_None, // XVMADDWEV_W_H = 2047
9189 CEFBS_None, // XVMADDWEV_W_HU = 2048
9190 CEFBS_None, // XVMADDWEV_W_HU_H = 2049
9191 CEFBS_None, // XVMADDWOD_D_W = 2050
9192 CEFBS_None, // XVMADDWOD_D_WU = 2051
9193 CEFBS_None, // XVMADDWOD_D_WU_W = 2052
9194 CEFBS_None, // XVMADDWOD_H_B = 2053
9195 CEFBS_None, // XVMADDWOD_H_BU = 2054
9196 CEFBS_None, // XVMADDWOD_H_BU_B = 2055
9197 CEFBS_None, // XVMADDWOD_Q_D = 2056
9198 CEFBS_None, // XVMADDWOD_Q_DU = 2057
9199 CEFBS_None, // XVMADDWOD_Q_DU_D = 2058
9200 CEFBS_None, // XVMADDWOD_W_H = 2059
9201 CEFBS_None, // XVMADDWOD_W_HU = 2060
9202 CEFBS_None, // XVMADDWOD_W_HU_H = 2061
9203 CEFBS_None, // XVMADD_B = 2062
9204 CEFBS_None, // XVMADD_D = 2063
9205 CEFBS_None, // XVMADD_H = 2064
9206 CEFBS_None, // XVMADD_W = 2065
9207 CEFBS_None, // XVMAXI_B = 2066
9208 CEFBS_None, // XVMAXI_BU = 2067
9209 CEFBS_None, // XVMAXI_D = 2068
9210 CEFBS_None, // XVMAXI_DU = 2069
9211 CEFBS_None, // XVMAXI_H = 2070
9212 CEFBS_None, // XVMAXI_HU = 2071
9213 CEFBS_None, // XVMAXI_W = 2072
9214 CEFBS_None, // XVMAXI_WU = 2073
9215 CEFBS_None, // XVMAX_B = 2074
9216 CEFBS_None, // XVMAX_BU = 2075
9217 CEFBS_None, // XVMAX_D = 2076
9218 CEFBS_None, // XVMAX_DU = 2077
9219 CEFBS_None, // XVMAX_H = 2078
9220 CEFBS_None, // XVMAX_HU = 2079
9221 CEFBS_None, // XVMAX_W = 2080
9222 CEFBS_None, // XVMAX_WU = 2081
9223 CEFBS_None, // XVMINI_B = 2082
9224 CEFBS_None, // XVMINI_BU = 2083
9225 CEFBS_None, // XVMINI_D = 2084
9226 CEFBS_None, // XVMINI_DU = 2085
9227 CEFBS_None, // XVMINI_H = 2086
9228 CEFBS_None, // XVMINI_HU = 2087
9229 CEFBS_None, // XVMINI_W = 2088
9230 CEFBS_None, // XVMINI_WU = 2089
9231 CEFBS_None, // XVMIN_B = 2090
9232 CEFBS_None, // XVMIN_BU = 2091
9233 CEFBS_None, // XVMIN_D = 2092
9234 CEFBS_None, // XVMIN_DU = 2093
9235 CEFBS_None, // XVMIN_H = 2094
9236 CEFBS_None, // XVMIN_HU = 2095
9237 CEFBS_None, // XVMIN_W = 2096
9238 CEFBS_None, // XVMIN_WU = 2097
9239 CEFBS_None, // XVMOD_B = 2098
9240 CEFBS_None, // XVMOD_BU = 2099
9241 CEFBS_None, // XVMOD_D = 2100
9242 CEFBS_None, // XVMOD_DU = 2101
9243 CEFBS_None, // XVMOD_H = 2102
9244 CEFBS_None, // XVMOD_HU = 2103
9245 CEFBS_None, // XVMOD_W = 2104
9246 CEFBS_None, // XVMOD_WU = 2105
9247 CEFBS_None, // XVMSKGEZ_B = 2106
9248 CEFBS_None, // XVMSKLTZ_B = 2107
9249 CEFBS_None, // XVMSKLTZ_D = 2108
9250 CEFBS_None, // XVMSKLTZ_H = 2109
9251 CEFBS_None, // XVMSKLTZ_W = 2110
9252 CEFBS_None, // XVMSKNZ_B = 2111
9253 CEFBS_None, // XVMSUB_B = 2112
9254 CEFBS_None, // XVMSUB_D = 2113
9255 CEFBS_None, // XVMSUB_H = 2114
9256 CEFBS_None, // XVMSUB_W = 2115
9257 CEFBS_None, // XVMUH_B = 2116
9258 CEFBS_None, // XVMUH_BU = 2117
9259 CEFBS_None, // XVMUH_D = 2118
9260 CEFBS_None, // XVMUH_DU = 2119
9261 CEFBS_None, // XVMUH_H = 2120
9262 CEFBS_None, // XVMUH_HU = 2121
9263 CEFBS_None, // XVMUH_W = 2122
9264 CEFBS_None, // XVMUH_WU = 2123
9265 CEFBS_None, // XVMULWEV_D_W = 2124
9266 CEFBS_None, // XVMULWEV_D_WU = 2125
9267 CEFBS_None, // XVMULWEV_D_WU_W = 2126
9268 CEFBS_None, // XVMULWEV_H_B = 2127
9269 CEFBS_None, // XVMULWEV_H_BU = 2128
9270 CEFBS_None, // XVMULWEV_H_BU_B = 2129
9271 CEFBS_None, // XVMULWEV_Q_D = 2130
9272 CEFBS_None, // XVMULWEV_Q_DU = 2131
9273 CEFBS_None, // XVMULWEV_Q_DU_D = 2132
9274 CEFBS_None, // XVMULWEV_W_H = 2133
9275 CEFBS_None, // XVMULWEV_W_HU = 2134
9276 CEFBS_None, // XVMULWEV_W_HU_H = 2135
9277 CEFBS_None, // XVMULWOD_D_W = 2136
9278 CEFBS_None, // XVMULWOD_D_WU = 2137
9279 CEFBS_None, // XVMULWOD_D_WU_W = 2138
9280 CEFBS_None, // XVMULWOD_H_B = 2139
9281 CEFBS_None, // XVMULWOD_H_BU = 2140
9282 CEFBS_None, // XVMULWOD_H_BU_B = 2141
9283 CEFBS_None, // XVMULWOD_Q_D = 2142
9284 CEFBS_None, // XVMULWOD_Q_DU = 2143
9285 CEFBS_None, // XVMULWOD_Q_DU_D = 2144
9286 CEFBS_None, // XVMULWOD_W_H = 2145
9287 CEFBS_None, // XVMULWOD_W_HU = 2146
9288 CEFBS_None, // XVMULWOD_W_HU_H = 2147
9289 CEFBS_None, // XVMUL_B = 2148
9290 CEFBS_None, // XVMUL_D = 2149
9291 CEFBS_None, // XVMUL_H = 2150
9292 CEFBS_None, // XVMUL_W = 2151
9293 CEFBS_None, // XVNEG_B = 2152
9294 CEFBS_None, // XVNEG_D = 2153
9295 CEFBS_None, // XVNEG_H = 2154
9296 CEFBS_None, // XVNEG_W = 2155
9297 CEFBS_None, // XVNORI_B = 2156
9298 CEFBS_None, // XVNOR_V = 2157
9299 CEFBS_None, // XVORI_B = 2158
9300 CEFBS_None, // XVORN_V = 2159
9301 CEFBS_None, // XVOR_V = 2160
9302 CEFBS_None, // XVPACKEV_B = 2161
9303 CEFBS_None, // XVPACKEV_D = 2162
9304 CEFBS_None, // XVPACKEV_H = 2163
9305 CEFBS_None, // XVPACKEV_W = 2164
9306 CEFBS_None, // XVPACKOD_B = 2165
9307 CEFBS_None, // XVPACKOD_D = 2166
9308 CEFBS_None, // XVPACKOD_H = 2167
9309 CEFBS_None, // XVPACKOD_W = 2168
9310 CEFBS_None, // XVPCNT_B = 2169
9311 CEFBS_None, // XVPCNT_D = 2170
9312 CEFBS_None, // XVPCNT_H = 2171
9313 CEFBS_None, // XVPCNT_W = 2172
9314 CEFBS_None, // XVPERMI_D = 2173
9315 CEFBS_None, // XVPERMI_Q = 2174
9316 CEFBS_None, // XVPERMI_W = 2175
9317 CEFBS_None, // XVPERM_W = 2176
9318 CEFBS_None, // XVPICKEV_B = 2177
9319 CEFBS_None, // XVPICKEV_D = 2178
9320 CEFBS_None, // XVPICKEV_H = 2179
9321 CEFBS_None, // XVPICKEV_W = 2180
9322 CEFBS_None, // XVPICKOD_B = 2181
9323 CEFBS_None, // XVPICKOD_D = 2182
9324 CEFBS_None, // XVPICKOD_H = 2183
9325 CEFBS_None, // XVPICKOD_W = 2184
9326 CEFBS_None, // XVPICKVE2GR_D = 2185
9327 CEFBS_None, // XVPICKVE2GR_DU = 2186
9328 CEFBS_None, // XVPICKVE2GR_W = 2187
9329 CEFBS_None, // XVPICKVE2GR_WU = 2188
9330 CEFBS_None, // XVPICKVE_D = 2189
9331 CEFBS_None, // XVPICKVE_W = 2190
9332 CEFBS_None, // XVREPL128VEI_B = 2191
9333 CEFBS_None, // XVREPL128VEI_D = 2192
9334 CEFBS_None, // XVREPL128VEI_H = 2193
9335 CEFBS_None, // XVREPL128VEI_W = 2194
9336 CEFBS_None, // XVREPLGR2VR_B = 2195
9337 CEFBS_None, // XVREPLGR2VR_D = 2196
9338 CEFBS_None, // XVREPLGR2VR_H = 2197
9339 CEFBS_None, // XVREPLGR2VR_W = 2198
9340 CEFBS_None, // XVREPLVE0_B = 2199
9341 CEFBS_None, // XVREPLVE0_D = 2200
9342 CEFBS_None, // XVREPLVE0_H = 2201
9343 CEFBS_None, // XVREPLVE0_Q = 2202
9344 CEFBS_None, // XVREPLVE0_W = 2203
9345 CEFBS_None, // XVREPLVE_B = 2204
9346 CEFBS_None, // XVREPLVE_D = 2205
9347 CEFBS_None, // XVREPLVE_H = 2206
9348 CEFBS_None, // XVREPLVE_W = 2207
9349 CEFBS_None, // XVROTRI_B = 2208
9350 CEFBS_None, // XVROTRI_D = 2209
9351 CEFBS_None, // XVROTRI_H = 2210
9352 CEFBS_None, // XVROTRI_W = 2211
9353 CEFBS_None, // XVROTR_B = 2212
9354 CEFBS_None, // XVROTR_D = 2213
9355 CEFBS_None, // XVROTR_H = 2214
9356 CEFBS_None, // XVROTR_W = 2215
9357 CEFBS_None, // XVSADD_B = 2216
9358 CEFBS_None, // XVSADD_BU = 2217
9359 CEFBS_None, // XVSADD_D = 2218
9360 CEFBS_None, // XVSADD_DU = 2219
9361 CEFBS_None, // XVSADD_H = 2220
9362 CEFBS_None, // XVSADD_HU = 2221
9363 CEFBS_None, // XVSADD_W = 2222
9364 CEFBS_None, // XVSADD_WU = 2223
9365 CEFBS_None, // XVSAT_B = 2224
9366 CEFBS_None, // XVSAT_BU = 2225
9367 CEFBS_None, // XVSAT_D = 2226
9368 CEFBS_None, // XVSAT_DU = 2227
9369 CEFBS_None, // XVSAT_H = 2228
9370 CEFBS_None, // XVSAT_HU = 2229
9371 CEFBS_None, // XVSAT_W = 2230
9372 CEFBS_None, // XVSAT_WU = 2231
9373 CEFBS_None, // XVSEQI_B = 2232
9374 CEFBS_None, // XVSEQI_D = 2233
9375 CEFBS_None, // XVSEQI_H = 2234
9376 CEFBS_None, // XVSEQI_W = 2235
9377 CEFBS_None, // XVSEQ_B = 2236
9378 CEFBS_None, // XVSEQ_D = 2237
9379 CEFBS_None, // XVSEQ_H = 2238
9380 CEFBS_None, // XVSEQ_W = 2239
9381 CEFBS_None, // XVSETALLNEZ_B = 2240
9382 CEFBS_None, // XVSETALLNEZ_D = 2241
9383 CEFBS_None, // XVSETALLNEZ_H = 2242
9384 CEFBS_None, // XVSETALLNEZ_W = 2243
9385 CEFBS_None, // XVSETANYEQZ_B = 2244
9386 CEFBS_None, // XVSETANYEQZ_D = 2245
9387 CEFBS_None, // XVSETANYEQZ_H = 2246
9388 CEFBS_None, // XVSETANYEQZ_W = 2247
9389 CEFBS_None, // XVSETEQZ_V = 2248
9390 CEFBS_None, // XVSETNEZ_V = 2249
9391 CEFBS_None, // XVSHUF4I_B = 2250
9392 CEFBS_None, // XVSHUF4I_D = 2251
9393 CEFBS_None, // XVSHUF4I_H = 2252
9394 CEFBS_None, // XVSHUF4I_W = 2253
9395 CEFBS_None, // XVSHUF_B = 2254
9396 CEFBS_None, // XVSHUF_D = 2255
9397 CEFBS_None, // XVSHUF_H = 2256
9398 CEFBS_None, // XVSHUF_W = 2257
9399 CEFBS_None, // XVSIGNCOV_B = 2258
9400 CEFBS_None, // XVSIGNCOV_D = 2259
9401 CEFBS_None, // XVSIGNCOV_H = 2260
9402 CEFBS_None, // XVSIGNCOV_W = 2261
9403 CEFBS_None, // XVSLEI_B = 2262
9404 CEFBS_None, // XVSLEI_BU = 2263
9405 CEFBS_None, // XVSLEI_D = 2264
9406 CEFBS_None, // XVSLEI_DU = 2265
9407 CEFBS_None, // XVSLEI_H = 2266
9408 CEFBS_None, // XVSLEI_HU = 2267
9409 CEFBS_None, // XVSLEI_W = 2268
9410 CEFBS_None, // XVSLEI_WU = 2269
9411 CEFBS_None, // XVSLE_B = 2270
9412 CEFBS_None, // XVSLE_BU = 2271
9413 CEFBS_None, // XVSLE_D = 2272
9414 CEFBS_None, // XVSLE_DU = 2273
9415 CEFBS_None, // XVSLE_H = 2274
9416 CEFBS_None, // XVSLE_HU = 2275
9417 CEFBS_None, // XVSLE_W = 2276
9418 CEFBS_None, // XVSLE_WU = 2277
9419 CEFBS_None, // XVSLLI_B = 2278
9420 CEFBS_None, // XVSLLI_D = 2279
9421 CEFBS_None, // XVSLLI_H = 2280
9422 CEFBS_None, // XVSLLI_W = 2281
9423 CEFBS_None, // XVSLLWIL_DU_WU = 2282
9424 CEFBS_None, // XVSLLWIL_D_W = 2283
9425 CEFBS_None, // XVSLLWIL_HU_BU = 2284
9426 CEFBS_None, // XVSLLWIL_H_B = 2285
9427 CEFBS_None, // XVSLLWIL_WU_HU = 2286
9428 CEFBS_None, // XVSLLWIL_W_H = 2287
9429 CEFBS_None, // XVSLL_B = 2288
9430 CEFBS_None, // XVSLL_D = 2289
9431 CEFBS_None, // XVSLL_H = 2290
9432 CEFBS_None, // XVSLL_W = 2291
9433 CEFBS_None, // XVSLTI_B = 2292
9434 CEFBS_None, // XVSLTI_BU = 2293
9435 CEFBS_None, // XVSLTI_D = 2294
9436 CEFBS_None, // XVSLTI_DU = 2295
9437 CEFBS_None, // XVSLTI_H = 2296
9438 CEFBS_None, // XVSLTI_HU = 2297
9439 CEFBS_None, // XVSLTI_W = 2298
9440 CEFBS_None, // XVSLTI_WU = 2299
9441 CEFBS_None, // XVSLT_B = 2300
9442 CEFBS_None, // XVSLT_BU = 2301
9443 CEFBS_None, // XVSLT_D = 2302
9444 CEFBS_None, // XVSLT_DU = 2303
9445 CEFBS_None, // XVSLT_H = 2304
9446 CEFBS_None, // XVSLT_HU = 2305
9447 CEFBS_None, // XVSLT_W = 2306
9448 CEFBS_None, // XVSLT_WU = 2307
9449 CEFBS_None, // XVSRAI_B = 2308
9450 CEFBS_None, // XVSRAI_D = 2309
9451 CEFBS_None, // XVSRAI_H = 2310
9452 CEFBS_None, // XVSRAI_W = 2311
9453 CEFBS_None, // XVSRANI_B_H = 2312
9454 CEFBS_None, // XVSRANI_D_Q = 2313
9455 CEFBS_None, // XVSRANI_H_W = 2314
9456 CEFBS_None, // XVSRANI_W_D = 2315
9457 CEFBS_None, // XVSRAN_B_H = 2316
9458 CEFBS_None, // XVSRAN_H_W = 2317
9459 CEFBS_None, // XVSRAN_W_D = 2318
9460 CEFBS_None, // XVSRARI_B = 2319
9461 CEFBS_None, // XVSRARI_D = 2320
9462 CEFBS_None, // XVSRARI_H = 2321
9463 CEFBS_None, // XVSRARI_W = 2322
9464 CEFBS_None, // XVSRARNI_B_H = 2323
9465 CEFBS_None, // XVSRARNI_D_Q = 2324
9466 CEFBS_None, // XVSRARNI_H_W = 2325
9467 CEFBS_None, // XVSRARNI_W_D = 2326
9468 CEFBS_None, // XVSRARN_B_H = 2327
9469 CEFBS_None, // XVSRARN_H_W = 2328
9470 CEFBS_None, // XVSRARN_W_D = 2329
9471 CEFBS_None, // XVSRAR_B = 2330
9472 CEFBS_None, // XVSRAR_D = 2331
9473 CEFBS_None, // XVSRAR_H = 2332
9474 CEFBS_None, // XVSRAR_W = 2333
9475 CEFBS_None, // XVSRA_B = 2334
9476 CEFBS_None, // XVSRA_D = 2335
9477 CEFBS_None, // XVSRA_H = 2336
9478 CEFBS_None, // XVSRA_W = 2337
9479 CEFBS_None, // XVSRLI_B = 2338
9480 CEFBS_None, // XVSRLI_D = 2339
9481 CEFBS_None, // XVSRLI_H = 2340
9482 CEFBS_None, // XVSRLI_W = 2341
9483 CEFBS_None, // XVSRLNI_B_H = 2342
9484 CEFBS_None, // XVSRLNI_D_Q = 2343
9485 CEFBS_None, // XVSRLNI_H_W = 2344
9486 CEFBS_None, // XVSRLNI_W_D = 2345
9487 CEFBS_None, // XVSRLN_B_H = 2346
9488 CEFBS_None, // XVSRLN_H_W = 2347
9489 CEFBS_None, // XVSRLN_W_D = 2348
9490 CEFBS_None, // XVSRLRI_B = 2349
9491 CEFBS_None, // XVSRLRI_D = 2350
9492 CEFBS_None, // XVSRLRI_H = 2351
9493 CEFBS_None, // XVSRLRI_W = 2352
9494 CEFBS_None, // XVSRLRNI_B_H = 2353
9495 CEFBS_None, // XVSRLRNI_D_Q = 2354
9496 CEFBS_None, // XVSRLRNI_H_W = 2355
9497 CEFBS_None, // XVSRLRNI_W_D = 2356
9498 CEFBS_None, // XVSRLRN_B_H = 2357
9499 CEFBS_None, // XVSRLRN_H_W = 2358
9500 CEFBS_None, // XVSRLRN_W_D = 2359
9501 CEFBS_None, // XVSRLR_B = 2360
9502 CEFBS_None, // XVSRLR_D = 2361
9503 CEFBS_None, // XVSRLR_H = 2362
9504 CEFBS_None, // XVSRLR_W = 2363
9505 CEFBS_None, // XVSRL_B = 2364
9506 CEFBS_None, // XVSRL_D = 2365
9507 CEFBS_None, // XVSRL_H = 2366
9508 CEFBS_None, // XVSRL_W = 2367
9509 CEFBS_None, // XVSSRANI_BU_H = 2368
9510 CEFBS_None, // XVSSRANI_B_H = 2369
9511 CEFBS_None, // XVSSRANI_DU_Q = 2370
9512 CEFBS_None, // XVSSRANI_D_Q = 2371
9513 CEFBS_None, // XVSSRANI_HU_W = 2372
9514 CEFBS_None, // XVSSRANI_H_W = 2373
9515 CEFBS_None, // XVSSRANI_WU_D = 2374
9516 CEFBS_None, // XVSSRANI_W_D = 2375
9517 CEFBS_None, // XVSSRAN_BU_H = 2376
9518 CEFBS_None, // XVSSRAN_B_H = 2377
9519 CEFBS_None, // XVSSRAN_HU_W = 2378
9520 CEFBS_None, // XVSSRAN_H_W = 2379
9521 CEFBS_None, // XVSSRAN_WU_D = 2380
9522 CEFBS_None, // XVSSRAN_W_D = 2381
9523 CEFBS_None, // XVSSRARNI_BU_H = 2382
9524 CEFBS_None, // XVSSRARNI_B_H = 2383
9525 CEFBS_None, // XVSSRARNI_DU_Q = 2384
9526 CEFBS_None, // XVSSRARNI_D_Q = 2385
9527 CEFBS_None, // XVSSRARNI_HU_W = 2386
9528 CEFBS_None, // XVSSRARNI_H_W = 2387
9529 CEFBS_None, // XVSSRARNI_WU_D = 2388
9530 CEFBS_None, // XVSSRARNI_W_D = 2389
9531 CEFBS_None, // XVSSRARN_BU_H = 2390
9532 CEFBS_None, // XVSSRARN_B_H = 2391
9533 CEFBS_None, // XVSSRARN_HU_W = 2392
9534 CEFBS_None, // XVSSRARN_H_W = 2393
9535 CEFBS_None, // XVSSRARN_WU_D = 2394
9536 CEFBS_None, // XVSSRARN_W_D = 2395
9537 CEFBS_None, // XVSSRLNI_BU_H = 2396
9538 CEFBS_None, // XVSSRLNI_B_H = 2397
9539 CEFBS_None, // XVSSRLNI_DU_Q = 2398
9540 CEFBS_None, // XVSSRLNI_D_Q = 2399
9541 CEFBS_None, // XVSSRLNI_HU_W = 2400
9542 CEFBS_None, // XVSSRLNI_H_W = 2401
9543 CEFBS_None, // XVSSRLNI_WU_D = 2402
9544 CEFBS_None, // XVSSRLNI_W_D = 2403
9545 CEFBS_None, // XVSSRLN_BU_H = 2404
9546 CEFBS_None, // XVSSRLN_B_H = 2405
9547 CEFBS_None, // XVSSRLN_HU_W = 2406
9548 CEFBS_None, // XVSSRLN_H_W = 2407
9549 CEFBS_None, // XVSSRLN_WU_D = 2408
9550 CEFBS_None, // XVSSRLN_W_D = 2409
9551 CEFBS_None, // XVSSRLRNI_BU_H = 2410
9552 CEFBS_None, // XVSSRLRNI_B_H = 2411
9553 CEFBS_None, // XVSSRLRNI_DU_Q = 2412
9554 CEFBS_None, // XVSSRLRNI_D_Q = 2413
9555 CEFBS_None, // XVSSRLRNI_HU_W = 2414
9556 CEFBS_None, // XVSSRLRNI_H_W = 2415
9557 CEFBS_None, // XVSSRLRNI_WU_D = 2416
9558 CEFBS_None, // XVSSRLRNI_W_D = 2417
9559 CEFBS_None, // XVSSRLRN_BU_H = 2418
9560 CEFBS_None, // XVSSRLRN_B_H = 2419
9561 CEFBS_None, // XVSSRLRN_HU_W = 2420
9562 CEFBS_None, // XVSSRLRN_H_W = 2421
9563 CEFBS_None, // XVSSRLRN_WU_D = 2422
9564 CEFBS_None, // XVSSRLRN_W_D = 2423
9565 CEFBS_None, // XVSSUB_B = 2424
9566 CEFBS_None, // XVSSUB_BU = 2425
9567 CEFBS_None, // XVSSUB_D = 2426
9568 CEFBS_None, // XVSSUB_DU = 2427
9569 CEFBS_None, // XVSSUB_H = 2428
9570 CEFBS_None, // XVSSUB_HU = 2429
9571 CEFBS_None, // XVSSUB_W = 2430
9572 CEFBS_None, // XVSSUB_WU = 2431
9573 CEFBS_None, // XVST = 2432
9574 CEFBS_None, // XVSTELM_B = 2433
9575 CEFBS_None, // XVSTELM_D = 2434
9576 CEFBS_None, // XVSTELM_H = 2435
9577 CEFBS_None, // XVSTELM_W = 2436
9578 CEFBS_None, // XVSTX = 2437
9579 CEFBS_None, // XVSUBI_BU = 2438
9580 CEFBS_None, // XVSUBI_DU = 2439
9581 CEFBS_None, // XVSUBI_HU = 2440
9582 CEFBS_None, // XVSUBI_WU = 2441
9583 CEFBS_None, // XVSUBWEV_D_W = 2442
9584 CEFBS_None, // XVSUBWEV_D_WU = 2443
9585 CEFBS_None, // XVSUBWEV_H_B = 2444
9586 CEFBS_None, // XVSUBWEV_H_BU = 2445
9587 CEFBS_None, // XVSUBWEV_Q_D = 2446
9588 CEFBS_None, // XVSUBWEV_Q_DU = 2447
9589 CEFBS_None, // XVSUBWEV_W_H = 2448
9590 CEFBS_None, // XVSUBWEV_W_HU = 2449
9591 CEFBS_None, // XVSUBWOD_D_W = 2450
9592 CEFBS_None, // XVSUBWOD_D_WU = 2451
9593 CEFBS_None, // XVSUBWOD_H_B = 2452
9594 CEFBS_None, // XVSUBWOD_H_BU = 2453
9595 CEFBS_None, // XVSUBWOD_Q_D = 2454
9596 CEFBS_None, // XVSUBWOD_Q_DU = 2455
9597 CEFBS_None, // XVSUBWOD_W_H = 2456
9598 CEFBS_None, // XVSUBWOD_W_HU = 2457
9599 CEFBS_None, // XVSUB_B = 2458
9600 CEFBS_None, // XVSUB_D = 2459
9601 CEFBS_None, // XVSUB_H = 2460
9602 CEFBS_None, // XVSUB_Q = 2461
9603 CEFBS_None, // XVSUB_W = 2462
9604 CEFBS_None, // XVXORI_B = 2463
9605 CEFBS_None, // XVXOR_V = 2464
9606 };
9607
9608 assert(Opcode < 2465);
9609 return FeatureBitsets[RequiredFeaturesRefs[Opcode]];
9610}
9611
9612} // end namespace llvm::LoongArch_MC
9613#endif // GET_COMPUTE_FEATURES
9614
9615#ifdef GET_AVAILABLE_OPCODE_CHECKER
9616#undef GET_AVAILABLE_OPCODE_CHECKER
9617namespace llvm::LoongArch_MC {
9618bool isOpcodeAvailable(unsigned Opcode, const FeatureBitset &Features) {
9619 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
9620 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
9621 FeatureBitset MissingFeatures =
9622 (AvailableFeatures & RequiredFeatures) ^
9623 RequiredFeatures;
9624 return !MissingFeatures.any();
9625}
9626} // end namespace llvm::LoongArch_MC
9627#endif // GET_AVAILABLE_OPCODE_CHECKER
9628
9629#ifdef ENABLE_INSTR_PREDICATE_VERIFIER
9630#undef ENABLE_INSTR_PREDICATE_VERIFIER
9631#include <sstream>
9632
9633namespace llvm::LoongArch_MC {
9634#ifndef NDEBUG
9635static const char *SubtargetFeatureNames[] = {
9636 "Feature_HasLaGlobalWithAbs",
9637 "Feature_HasLaGlobalWithPcrel",
9638 "Feature_HasLaLocalWithAbs",
9639 "Feature_IsLA32",
9640 "Feature_IsLA64",
9641 nullptr
9642};
9643
9644#endif // NDEBUG
9645
9646void verifyInstructionPredicates(
9647 unsigned Opcode, const FeatureBitset &Features) {
9648#ifndef NDEBUG
9649 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
9650 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
9651 FeatureBitset MissingFeatures =
9652 (AvailableFeatures & RequiredFeatures) ^
9653 RequiredFeatures;
9654 if (MissingFeatures.any()) {
9655 std::ostringstream Msg;
9656 Msg << "Attempting to emit " << &LoongArchInstrNameData[LoongArchInstrNameIndices[Opcode]]
9657 << " instruction but the ";
9658 for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i)
9659 if (MissingFeatures.test(i))
9660 Msg << SubtargetFeatureNames[i] << " ";
9661 Msg << "predicate(s) are not met";
9662 report_fatal_error(Msg.str().c_str());
9663 }
9664#endif // NDEBUG
9665}
9666} // end namespace llvm::LoongArch_MC
9667#endif // ENABLE_INSTR_PREDICATE_VERIFIER
9668
9669