1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register Enum Values *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9
10#ifdef GET_REGINFO_ENUM
11#undef GET_REGINFO_ENUM
12
13namespace llvm {
14
15class MCRegisterClass;
16extern const MCRegisterClass LoongArchMCRegisterClasses[];
17
18namespace LoongArch {
19enum : unsigned {
20 NoRegister,
21 F0 = 1,
22 F1 = 2,
23 F2 = 3,
24 F3 = 4,
25 F4 = 5,
26 F5 = 6,
27 F6 = 7,
28 F7 = 8,
29 F8 = 9,
30 F9 = 10,
31 F10 = 11,
32 F11 = 12,
33 F12 = 13,
34 F13 = 14,
35 F14 = 15,
36 F15 = 16,
37 F16 = 17,
38 F17 = 18,
39 F18 = 19,
40 F19 = 20,
41 F20 = 21,
42 F21 = 22,
43 F22 = 23,
44 F23 = 24,
45 F24 = 25,
46 F25 = 26,
47 F26 = 27,
48 F27 = 28,
49 F28 = 29,
50 F29 = 30,
51 F30 = 31,
52 F31 = 32,
53 FCC0 = 33,
54 FCC1 = 34,
55 FCC2 = 35,
56 FCC3 = 36,
57 FCC4 = 37,
58 FCC5 = 38,
59 FCC6 = 39,
60 FCC7 = 40,
61 FCSR0 = 41,
62 FCSR1 = 42,
63 FCSR2 = 43,
64 FCSR3 = 44,
65 R0 = 45,
66 R1 = 46,
67 R2 = 47,
68 R3 = 48,
69 R4 = 49,
70 R5 = 50,
71 R6 = 51,
72 R7 = 52,
73 R8 = 53,
74 R9 = 54,
75 R10 = 55,
76 R11 = 56,
77 R12 = 57,
78 R13 = 58,
79 R14 = 59,
80 R15 = 60,
81 R16 = 61,
82 R17 = 62,
83 R18 = 63,
84 R19 = 64,
85 R20 = 65,
86 R21 = 66,
87 R22 = 67,
88 R23 = 68,
89 R24 = 69,
90 R25 = 70,
91 R26 = 71,
92 R27 = 72,
93 R28 = 73,
94 R29 = 74,
95 R30 = 75,
96 R31 = 76,
97 SCR0 = 77,
98 SCR1 = 78,
99 SCR2 = 79,
100 SCR3 = 80,
101 VR0 = 81,
102 VR1 = 82,
103 VR2 = 83,
104 VR3 = 84,
105 VR4 = 85,
106 VR5 = 86,
107 VR6 = 87,
108 VR7 = 88,
109 VR8 = 89,
110 VR9 = 90,
111 VR10 = 91,
112 VR11 = 92,
113 VR12 = 93,
114 VR13 = 94,
115 VR14 = 95,
116 VR15 = 96,
117 VR16 = 97,
118 VR17 = 98,
119 VR18 = 99,
120 VR19 = 100,
121 VR20 = 101,
122 VR21 = 102,
123 VR22 = 103,
124 VR23 = 104,
125 VR24 = 105,
126 VR25 = 106,
127 VR26 = 107,
128 VR27 = 108,
129 VR28 = 109,
130 VR29 = 110,
131 VR30 = 111,
132 VR31 = 112,
133 XR0 = 113,
134 XR1 = 114,
135 XR2 = 115,
136 XR3 = 116,
137 XR4 = 117,
138 XR5 = 118,
139 XR6 = 119,
140 XR7 = 120,
141 XR8 = 121,
142 XR9 = 122,
143 XR10 = 123,
144 XR11 = 124,
145 XR12 = 125,
146 XR13 = 126,
147 XR14 = 127,
148 XR15 = 128,
149 XR16 = 129,
150 XR17 = 130,
151 XR18 = 131,
152 XR19 = 132,
153 XR20 = 133,
154 XR21 = 134,
155 XR22 = 135,
156 XR23 = 136,
157 XR24 = 137,
158 XR25 = 138,
159 XR26 = 139,
160 XR27 = 140,
161 XR28 = 141,
162 XR29 = 142,
163 XR30 = 143,
164 XR31 = 144,
165 F0_64 = 145,
166 F1_64 = 146,
167 F2_64 = 147,
168 F3_64 = 148,
169 F4_64 = 149,
170 F5_64 = 150,
171 F6_64 = 151,
172 F7_64 = 152,
173 F8_64 = 153,
174 F9_64 = 154,
175 F10_64 = 155,
176 F11_64 = 156,
177 F12_64 = 157,
178 F13_64 = 158,
179 F14_64 = 159,
180 F15_64 = 160,
181 F16_64 = 161,
182 F17_64 = 162,
183 F18_64 = 163,
184 F19_64 = 164,
185 F20_64 = 165,
186 F21_64 = 166,
187 F22_64 = 167,
188 F23_64 = 168,
189 F24_64 = 169,
190 F25_64 = 170,
191 F26_64 = 171,
192 F27_64 = 172,
193 F28_64 = 173,
194 F29_64 = 174,
195 F30_64 = 175,
196 F31_64 = 176,
197 NUM_TARGET_REGS // 177
198};
199} // end namespace LoongArch
200
201// Register classes
202
203namespace LoongArch {
204enum {
205 FPR32RegClassID = 0,
206 GPRRegClassID = 1,
207 GPRJRRegClassID = 2,
208 GPRNoR0R1RegClassID = 3,
209 GPRTRegClassID = 4,
210 CFRRegClassID = 5,
211 FCSRRegClassID = 6,
212 SCRRegClassID = 7,
213 FPR64RegClassID = 8,
214 LSX128RegClassID = 9,
215 LASX256RegClassID = 10,
216
217};
218} // end namespace LoongArch
219
220
221// Register alternate name indices
222
223namespace LoongArch {
224enum {
225 NoRegAltName, // 0
226 RegAliasName, // 1
227 NUM_TARGET_REG_ALT_NAMES = 2
228};
229} // end namespace LoongArch
230
231
232// Subregister indices
233
234namespace LoongArch {
235enum : uint16_t {
236 NoSubRegister,
237 sub_32, // 1
238 sub_64, // 2
239 sub_128, // 3
240 NUM_TARGET_SUBREGS
241};
242} // end namespace LoongArch
243
244// Register pressure sets enum.
245namespace LoongArch {
246enum RegisterPressureSets {
247 CFR = 0,
248 GPRT = 1,
249 FPR32 = 2,
250 GPR = 3,
251};
252} // end namespace LoongArch
253
254} // end namespace llvm
255
256#endif // GET_REGINFO_ENUM
257
258/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
259|* *|
260|* MC Register Information *|
261|* *|
262|* Automatically generated file, do not edit! *|
263|* *|
264\*===----------------------------------------------------------------------===*/
265
266
267#ifdef GET_REGINFO_MC_DESC
268#undef GET_REGINFO_MC_DESC
269
270namespace llvm {
271
272extern const int16_t LoongArchRegDiffLists[] = {
273 /* 0 */ -32, 64, -144, 0,
274 /* 4 */ 144, -64, 32, 0,
275};
276
277extern const LaneBitmask LoongArchLaneMaskLists[] = {
278 /* 0 */ LaneBitmask(0x0000000000000001),
279 /* 1 */ LaneBitmask(0xFFFFFFFFFFFFFFFF),
280};
281
282extern const uint16_t LoongArchSubRegIdxLists[] = {
283 /* 0 */ 3, 2, 1,
284};
285
286
287#ifdef __GNUC__
288#pragma GCC diagnostic push
289#pragma GCC diagnostic ignored "-Woverlength-strings"
290#endif
291extern const char LoongArchRegStrings[] = {
292 /* 0 */ "F10\000"
293 /* 4 */ "VR10\000"
294 /* 9 */ "XR10\000"
295 /* 14 */ "F20\000"
296 /* 18 */ "VR20\000"
297 /* 23 */ "XR20\000"
298 /* 28 */ "F30\000"
299 /* 32 */ "VR30\000"
300 /* 37 */ "XR30\000"
301 /* 42 */ "FCC0\000"
302 /* 47 */ "F0\000"
303 /* 50 */ "SCR0\000"
304 /* 55 */ "FCSR0\000"
305 /* 61 */ "VR0\000"
306 /* 65 */ "XR0\000"
307 /* 69 */ "F11\000"
308 /* 73 */ "VR11\000"
309 /* 78 */ "XR11\000"
310 /* 83 */ "F21\000"
311 /* 87 */ "VR21\000"
312 /* 92 */ "XR21\000"
313 /* 97 */ "F31\000"
314 /* 101 */ "VR31\000"
315 /* 106 */ "XR31\000"
316 /* 111 */ "FCC1\000"
317 /* 116 */ "F1\000"
318 /* 119 */ "SCR1\000"
319 /* 124 */ "FCSR1\000"
320 /* 130 */ "VR1\000"
321 /* 134 */ "XR1\000"
322 /* 138 */ "F12\000"
323 /* 142 */ "VR12\000"
324 /* 147 */ "XR12\000"
325 /* 152 */ "F22\000"
326 /* 156 */ "VR22\000"
327 /* 161 */ "XR22\000"
328 /* 166 */ "FCC2\000"
329 /* 171 */ "F2\000"
330 /* 174 */ "SCR2\000"
331 /* 179 */ "FCSR2\000"
332 /* 185 */ "VR2\000"
333 /* 189 */ "XR2\000"
334 /* 193 */ "F13\000"
335 /* 197 */ "VR13\000"
336 /* 202 */ "XR13\000"
337 /* 207 */ "F23\000"
338 /* 211 */ "VR23\000"
339 /* 216 */ "XR23\000"
340 /* 221 */ "FCC3\000"
341 /* 226 */ "F3\000"
342 /* 229 */ "SCR3\000"
343 /* 234 */ "FCSR3\000"
344 /* 240 */ "VR3\000"
345 /* 244 */ "XR3\000"
346 /* 248 */ "F14\000"
347 /* 252 */ "VR14\000"
348 /* 257 */ "XR14\000"
349 /* 262 */ "F24\000"
350 /* 266 */ "VR24\000"
351 /* 271 */ "XR24\000"
352 /* 276 */ "F10_64\000"
353 /* 283 */ "F20_64\000"
354 /* 290 */ "F30_64\000"
355 /* 297 */ "F0_64\000"
356 /* 303 */ "F11_64\000"
357 /* 310 */ "F21_64\000"
358 /* 317 */ "F31_64\000"
359 /* 324 */ "F1_64\000"
360 /* 330 */ "F12_64\000"
361 /* 337 */ "F22_64\000"
362 /* 344 */ "F2_64\000"
363 /* 350 */ "F13_64\000"
364 /* 357 */ "F23_64\000"
365 /* 364 */ "F3_64\000"
366 /* 370 */ "F14_64\000"
367 /* 377 */ "F24_64\000"
368 /* 384 */ "F4_64\000"
369 /* 390 */ "F15_64\000"
370 /* 397 */ "F25_64\000"
371 /* 404 */ "F5_64\000"
372 /* 410 */ "F16_64\000"
373 /* 417 */ "F26_64\000"
374 /* 424 */ "F6_64\000"
375 /* 430 */ "F17_64\000"
376 /* 437 */ "F27_64\000"
377 /* 444 */ "F7_64\000"
378 /* 450 */ "F18_64\000"
379 /* 457 */ "F28_64\000"
380 /* 464 */ "F8_64\000"
381 /* 470 */ "F19_64\000"
382 /* 477 */ "F29_64\000"
383 /* 484 */ "F9_64\000"
384 /* 490 */ "FCC4\000"
385 /* 495 */ "F4\000"
386 /* 498 */ "VR4\000"
387 /* 502 */ "XR4\000"
388 /* 506 */ "F15\000"
389 /* 510 */ "VR15\000"
390 /* 515 */ "XR15\000"
391 /* 520 */ "F25\000"
392 /* 524 */ "VR25\000"
393 /* 529 */ "XR25\000"
394 /* 534 */ "FCC5\000"
395 /* 539 */ "F5\000"
396 /* 542 */ "VR5\000"
397 /* 546 */ "XR5\000"
398 /* 550 */ "F16\000"
399 /* 554 */ "VR16\000"
400 /* 559 */ "XR16\000"
401 /* 564 */ "F26\000"
402 /* 568 */ "VR26\000"
403 /* 573 */ "XR26\000"
404 /* 578 */ "FCC6\000"
405 /* 583 */ "F6\000"
406 /* 586 */ "VR6\000"
407 /* 590 */ "XR6\000"
408 /* 594 */ "F17\000"
409 /* 598 */ "VR17\000"
410 /* 603 */ "XR17\000"
411 /* 608 */ "F27\000"
412 /* 612 */ "VR27\000"
413 /* 617 */ "XR27\000"
414 /* 622 */ "FCC7\000"
415 /* 627 */ "F7\000"
416 /* 630 */ "VR7\000"
417 /* 634 */ "XR7\000"
418 /* 638 */ "F18\000"
419 /* 642 */ "VR18\000"
420 /* 647 */ "XR18\000"
421 /* 652 */ "F28\000"
422 /* 656 */ "VR28\000"
423 /* 661 */ "XR28\000"
424 /* 666 */ "F8\000"
425 /* 669 */ "VR8\000"
426 /* 673 */ "XR8\000"
427 /* 677 */ "F19\000"
428 /* 681 */ "VR19\000"
429 /* 686 */ "XR19\000"
430 /* 691 */ "F29\000"
431 /* 695 */ "VR29\000"
432 /* 700 */ "XR29\000"
433 /* 705 */ "F9\000"
434 /* 708 */ "VR9\000"
435 /* 712 */ "XR9\000"
436};
437#ifdef __GNUC__
438#pragma GCC diagnostic pop
439#endif
440
441extern const MCRegisterDesc LoongArchRegDesc[] = { // Descriptors
442 { 3, 0, 0, 0, 0, 0, 0, 0 },
443 { 47, 3, 4, 3, 12288, 1, 0, 0 },
444 { 116, 3, 4, 3, 12289, 1, 0, 0 },
445 { 171, 3, 4, 3, 12290, 1, 0, 0 },
446 { 226, 3, 4, 3, 12291, 1, 0, 0 },
447 { 495, 3, 4, 3, 12292, 1, 0, 0 },
448 { 539, 3, 4, 3, 12293, 1, 0, 0 },
449 { 583, 3, 4, 3, 12294, 1, 0, 0 },
450 { 627, 3, 4, 3, 12295, 1, 0, 0 },
451 { 666, 3, 4, 3, 12296, 1, 0, 0 },
452 { 705, 3, 4, 3, 12297, 1, 0, 0 },
453 { 0, 3, 4, 3, 12298, 1, 0, 0 },
454 { 69, 3, 4, 3, 12299, 1, 0, 0 },
455 { 138, 3, 4, 3, 12300, 1, 0, 0 },
456 { 193, 3, 4, 3, 12301, 1, 0, 0 },
457 { 248, 3, 4, 3, 12302, 1, 0, 0 },
458 { 506, 3, 4, 3, 12303, 1, 0, 0 },
459 { 550, 3, 4, 3, 12304, 1, 0, 0 },
460 { 594, 3, 4, 3, 12305, 1, 0, 0 },
461 { 638, 3, 4, 3, 12306, 1, 0, 0 },
462 { 677, 3, 4, 3, 12307, 1, 0, 0 },
463 { 14, 3, 4, 3, 12308, 1, 0, 0 },
464 { 83, 3, 4, 3, 12309, 1, 0, 0 },
465 { 152, 3, 4, 3, 12310, 1, 0, 0 },
466 { 207, 3, 4, 3, 12311, 1, 0, 0 },
467 { 262, 3, 4, 3, 12312, 1, 0, 0 },
468 { 520, 3, 4, 3, 12313, 1, 0, 0 },
469 { 564, 3, 4, 3, 12314, 1, 0, 0 },
470 { 608, 3, 4, 3, 12315, 1, 0, 0 },
471 { 652, 3, 4, 3, 12316, 1, 0, 0 },
472 { 691, 3, 4, 3, 12317, 1, 0, 0 },
473 { 28, 3, 4, 3, 12318, 1, 0, 0 },
474 { 97, 3, 4, 3, 12319, 1, 0, 0 },
475 { 42, 3, 3, 3, 12320, 1, 0, 0 },
476 { 111, 3, 3, 3, 12321, 1, 0, 0 },
477 { 166, 3, 3, 3, 12322, 1, 0, 0 },
478 { 221, 3, 3, 3, 12323, 1, 0, 0 },
479 { 490, 3, 3, 3, 12324, 1, 0, 0 },
480 { 534, 3, 3, 3, 12325, 1, 0, 0 },
481 { 578, 3, 3, 3, 12326, 1, 0, 0 },
482 { 622, 3, 3, 3, 12327, 1, 0, 0 },
483 { 55, 3, 3, 3, 12328, 1, 0, 0 },
484 { 124, 3, 3, 3, 12329, 1, 0, 0 },
485 { 179, 3, 3, 3, 12330, 1, 0, 0 },
486 { 234, 3, 3, 3, 12331, 1, 0, 0 },
487 { 52, 3, 3, 3, 12332, 1, 1, 0 },
488 { 121, 3, 3, 3, 12333, 1, 0, 0 },
489 { 176, 3, 3, 3, 12334, 1, 0, 0 },
490 { 231, 3, 3, 3, 12335, 1, 0, 0 },
491 { 499, 3, 3, 3, 12336, 1, 0, 0 },
492 { 543, 3, 3, 3, 12337, 1, 0, 0 },
493 { 587, 3, 3, 3, 12338, 1, 0, 0 },
494 { 631, 3, 3, 3, 12339, 1, 0, 0 },
495 { 670, 3, 3, 3, 12340, 1, 0, 0 },
496 { 709, 3, 3, 3, 12341, 1, 0, 0 },
497 { 5, 3, 3, 3, 12342, 1, 0, 0 },
498 { 74, 3, 3, 3, 12343, 1, 0, 0 },
499 { 143, 3, 3, 3, 12344, 1, 0, 0 },
500 { 198, 3, 3, 3, 12345, 1, 0, 0 },
501 { 253, 3, 3, 3, 12346, 1, 0, 0 },
502 { 511, 3, 3, 3, 12347, 1, 0, 0 },
503 { 555, 3, 3, 3, 12348, 1, 0, 0 },
504 { 599, 3, 3, 3, 12349, 1, 0, 0 },
505 { 643, 3, 3, 3, 12350, 1, 0, 0 },
506 { 682, 3, 3, 3, 12351, 1, 0, 0 },
507 { 19, 3, 3, 3, 12352, 1, 0, 0 },
508 { 88, 3, 3, 3, 12353, 1, 0, 0 },
509 { 157, 3, 3, 3, 12354, 1, 0, 0 },
510 { 212, 3, 3, 3, 12355, 1, 0, 0 },
511 { 267, 3, 3, 3, 12356, 1, 0, 0 },
512 { 525, 3, 3, 3, 12357, 1, 0, 0 },
513 { 569, 3, 3, 3, 12358, 1, 0, 0 },
514 { 613, 3, 3, 3, 12359, 1, 0, 0 },
515 { 657, 3, 3, 3, 12360, 1, 0, 0 },
516 { 696, 3, 3, 3, 12361, 1, 0, 0 },
517 { 33, 3, 3, 3, 12362, 1, 0, 0 },
518 { 102, 3, 3, 3, 12363, 1, 0, 0 },
519 { 50, 3, 3, 3, 12364, 1, 0, 0 },
520 { 119, 3, 3, 3, 12365, 1, 0, 0 },
521 { 174, 3, 3, 3, 12366, 1, 0, 0 },
522 { 229, 3, 3, 3, 12367, 1, 0, 0 },
523 { 61, 1, 6, 1, 12288, 0, 0, 0 },
524 { 130, 1, 6, 1, 12289, 0, 0, 0 },
525 { 185, 1, 6, 1, 12290, 0, 0, 0 },
526 { 240, 1, 6, 1, 12291, 0, 0, 0 },
527 { 498, 1, 6, 1, 12292, 0, 0, 0 },
528 { 542, 1, 6, 1, 12293, 0, 0, 0 },
529 { 586, 1, 6, 1, 12294, 0, 0, 0 },
530 { 630, 1, 6, 1, 12295, 0, 0, 0 },
531 { 669, 1, 6, 1, 12296, 0, 0, 0 },
532 { 708, 1, 6, 1, 12297, 0, 0, 0 },
533 { 4, 1, 6, 1, 12298, 0, 0, 0 },
534 { 73, 1, 6, 1, 12299, 0, 0, 0 },
535 { 142, 1, 6, 1, 12300, 0, 0, 0 },
536 { 197, 1, 6, 1, 12301, 0, 0, 0 },
537 { 252, 1, 6, 1, 12302, 0, 0, 0 },
538 { 510, 1, 6, 1, 12303, 0, 0, 0 },
539 { 554, 1, 6, 1, 12304, 0, 0, 0 },
540 { 598, 1, 6, 1, 12305, 0, 0, 0 },
541 { 642, 1, 6, 1, 12306, 0, 0, 0 },
542 { 681, 1, 6, 1, 12307, 0, 0, 0 },
543 { 18, 1, 6, 1, 12308, 0, 0, 0 },
544 { 87, 1, 6, 1, 12309, 0, 0, 0 },
545 { 156, 1, 6, 1, 12310, 0, 0, 0 },
546 { 211, 1, 6, 1, 12311, 0, 0, 0 },
547 { 266, 1, 6, 1, 12312, 0, 0, 0 },
548 { 524, 1, 6, 1, 12313, 0, 0, 0 },
549 { 568, 1, 6, 1, 12314, 0, 0, 0 },
550 { 612, 1, 6, 1, 12315, 0, 0, 0 },
551 { 656, 1, 6, 1, 12316, 0, 0, 0 },
552 { 695, 1, 6, 1, 12317, 0, 0, 0 },
553 { 32, 1, 6, 1, 12318, 0, 0, 0 },
554 { 101, 1, 6, 1, 12319, 0, 0, 0 },
555 { 65, 0, 3, 0, 12288, 0, 0, 0 },
556 { 134, 0, 3, 0, 12289, 0, 0, 0 },
557 { 189, 0, 3, 0, 12290, 0, 0, 0 },
558 { 244, 0, 3, 0, 12291, 0, 0, 0 },
559 { 502, 0, 3, 0, 12292, 0, 0, 0 },
560 { 546, 0, 3, 0, 12293, 0, 0, 0 },
561 { 590, 0, 3, 0, 12294, 0, 0, 0 },
562 { 634, 0, 3, 0, 12295, 0, 0, 0 },
563 { 673, 0, 3, 0, 12296, 0, 0, 0 },
564 { 712, 0, 3, 0, 12297, 0, 0, 0 },
565 { 9, 0, 3, 0, 12298, 0, 0, 0 },
566 { 78, 0, 3, 0, 12299, 0, 0, 0 },
567 { 147, 0, 3, 0, 12300, 0, 0, 0 },
568 { 202, 0, 3, 0, 12301, 0, 0, 0 },
569 { 257, 0, 3, 0, 12302, 0, 0, 0 },
570 { 515, 0, 3, 0, 12303, 0, 0, 0 },
571 { 559, 0, 3, 0, 12304, 0, 0, 0 },
572 { 603, 0, 3, 0, 12305, 0, 0, 0 },
573 { 647, 0, 3, 0, 12306, 0, 0, 0 },
574 { 686, 0, 3, 0, 12307, 0, 0, 0 },
575 { 23, 0, 3, 0, 12308, 0, 0, 0 },
576 { 92, 0, 3, 0, 12309, 0, 0, 0 },
577 { 161, 0, 3, 0, 12310, 0, 0, 0 },
578 { 216, 0, 3, 0, 12311, 0, 0, 0 },
579 { 271, 0, 3, 0, 12312, 0, 0, 0 },
580 { 529, 0, 3, 0, 12313, 0, 0, 0 },
581 { 573, 0, 3, 0, 12314, 0, 0, 0 },
582 { 617, 0, 3, 0, 12315, 0, 0, 0 },
583 { 661, 0, 3, 0, 12316, 0, 0, 0 },
584 { 700, 0, 3, 0, 12317, 0, 0, 0 },
585 { 37, 0, 3, 0, 12318, 0, 0, 0 },
586 { 106, 0, 3, 0, 12319, 0, 0, 0 },
587 { 297, 2, 5, 2, 12288, 0, 0, 0 },
588 { 324, 2, 5, 2, 12289, 0, 0, 0 },
589 { 344, 2, 5, 2, 12290, 0, 0, 0 },
590 { 364, 2, 5, 2, 12291, 0, 0, 0 },
591 { 384, 2, 5, 2, 12292, 0, 0, 0 },
592 { 404, 2, 5, 2, 12293, 0, 0, 0 },
593 { 424, 2, 5, 2, 12294, 0, 0, 0 },
594 { 444, 2, 5, 2, 12295, 0, 0, 0 },
595 { 464, 2, 5, 2, 12296, 0, 0, 0 },
596 { 484, 2, 5, 2, 12297, 0, 0, 0 },
597 { 276, 2, 5, 2, 12298, 0, 0, 0 },
598 { 303, 2, 5, 2, 12299, 0, 0, 0 },
599 { 330, 2, 5, 2, 12300, 0, 0, 0 },
600 { 350, 2, 5, 2, 12301, 0, 0, 0 },
601 { 370, 2, 5, 2, 12302, 0, 0, 0 },
602 { 390, 2, 5, 2, 12303, 0, 0, 0 },
603 { 410, 2, 5, 2, 12304, 0, 0, 0 },
604 { 430, 2, 5, 2, 12305, 0, 0, 0 },
605 { 450, 2, 5, 2, 12306, 0, 0, 0 },
606 { 470, 2, 5, 2, 12307, 0, 0, 0 },
607 { 283, 2, 5, 2, 12308, 0, 0, 0 },
608 { 310, 2, 5, 2, 12309, 0, 0, 0 },
609 { 337, 2, 5, 2, 12310, 0, 0, 0 },
610 { 357, 2, 5, 2, 12311, 0, 0, 0 },
611 { 377, 2, 5, 2, 12312, 0, 0, 0 },
612 { 397, 2, 5, 2, 12313, 0, 0, 0 },
613 { 417, 2, 5, 2, 12314, 0, 0, 0 },
614 { 437, 2, 5, 2, 12315, 0, 0, 0 },
615 { 457, 2, 5, 2, 12316, 0, 0, 0 },
616 { 477, 2, 5, 2, 12317, 0, 0, 0 },
617 { 290, 2, 5, 2, 12318, 0, 0, 0 },
618 { 317, 2, 5, 2, 12319, 0, 0, 0 },
619};
620
621extern const MCPhysReg LoongArchRegUnitRoots[][2] = {
622 { LoongArch::F0 },
623 { LoongArch::F1 },
624 { LoongArch::F2 },
625 { LoongArch::F3 },
626 { LoongArch::F4 },
627 { LoongArch::F5 },
628 { LoongArch::F6 },
629 { LoongArch::F7 },
630 { LoongArch::F8 },
631 { LoongArch::F9 },
632 { LoongArch::F10 },
633 { LoongArch::F11 },
634 { LoongArch::F12 },
635 { LoongArch::F13 },
636 { LoongArch::F14 },
637 { LoongArch::F15 },
638 { LoongArch::F16 },
639 { LoongArch::F17 },
640 { LoongArch::F18 },
641 { LoongArch::F19 },
642 { LoongArch::F20 },
643 { LoongArch::F21 },
644 { LoongArch::F22 },
645 { LoongArch::F23 },
646 { LoongArch::F24 },
647 { LoongArch::F25 },
648 { LoongArch::F26 },
649 { LoongArch::F27 },
650 { LoongArch::F28 },
651 { LoongArch::F29 },
652 { LoongArch::F30 },
653 { LoongArch::F31 },
654 { LoongArch::FCC0 },
655 { LoongArch::FCC1 },
656 { LoongArch::FCC2 },
657 { LoongArch::FCC3 },
658 { LoongArch::FCC4 },
659 { LoongArch::FCC5 },
660 { LoongArch::FCC6 },
661 { LoongArch::FCC7 },
662 { LoongArch::FCSR0 },
663 { LoongArch::FCSR1 },
664 { LoongArch::FCSR2 },
665 { LoongArch::FCSR3 },
666 { LoongArch::R0 },
667 { LoongArch::R1 },
668 { LoongArch::R2 },
669 { LoongArch::R3 },
670 { LoongArch::R4 },
671 { LoongArch::R5 },
672 { LoongArch::R6 },
673 { LoongArch::R7 },
674 { LoongArch::R8 },
675 { LoongArch::R9 },
676 { LoongArch::R10 },
677 { LoongArch::R11 },
678 { LoongArch::R12 },
679 { LoongArch::R13 },
680 { LoongArch::R14 },
681 { LoongArch::R15 },
682 { LoongArch::R16 },
683 { LoongArch::R17 },
684 { LoongArch::R18 },
685 { LoongArch::R19 },
686 { LoongArch::R20 },
687 { LoongArch::R21 },
688 { LoongArch::R22 },
689 { LoongArch::R23 },
690 { LoongArch::R24 },
691 { LoongArch::R25 },
692 { LoongArch::R26 },
693 { LoongArch::R27 },
694 { LoongArch::R28 },
695 { LoongArch::R29 },
696 { LoongArch::R30 },
697 { LoongArch::R31 },
698 { LoongArch::SCR0 },
699 { LoongArch::SCR1 },
700 { LoongArch::SCR2 },
701 { LoongArch::SCR3 },
702};
703
704namespace { // Register classes...
705 // FPR32 Register Class...
706 const MCPhysReg FPR32[] = {
707 LoongArch::F0, LoongArch::F1, LoongArch::F2, LoongArch::F3, LoongArch::F4, LoongArch::F5, LoongArch::F6, LoongArch::F7, LoongArch::F8, LoongArch::F9, LoongArch::F10, LoongArch::F11, LoongArch::F12, LoongArch::F13, LoongArch::F14, LoongArch::F15, LoongArch::F16, LoongArch::F17, LoongArch::F18, LoongArch::F19, LoongArch::F20, LoongArch::F21, LoongArch::F22, LoongArch::F23, LoongArch::F24, LoongArch::F25, LoongArch::F26, LoongArch::F27, LoongArch::F28, LoongArch::F29, LoongArch::F30, LoongArch::F31,
708 };
709
710 // FPR32 Bit set.
711 const uint8_t FPR32Bits[] = {
712 0xfe, 0xff, 0xff, 0xff, 0x01,
713 };
714
715 // GPR Register Class...
716 const MCPhysReg GPR[] = {
717 LoongArch::R4, LoongArch::R5, LoongArch::R6, LoongArch::R7, LoongArch::R8, LoongArch::R9, LoongArch::R10, LoongArch::R11, LoongArch::R12, LoongArch::R13, LoongArch::R14, LoongArch::R15, LoongArch::R16, LoongArch::R17, LoongArch::R18, LoongArch::R19, LoongArch::R20, LoongArch::R22, LoongArch::R23, LoongArch::R24, LoongArch::R25, LoongArch::R26, LoongArch::R27, LoongArch::R28, LoongArch::R29, LoongArch::R30, LoongArch::R31, LoongArch::R0, LoongArch::R1, LoongArch::R2, LoongArch::R3, LoongArch::R21,
718 };
719
720 // GPR Bit set.
721 const uint8_t GPRBits[] = {
722 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f,
723 };
724
725 // GPRJR Register Class...
726 const MCPhysReg GPRJR[] = {
727 LoongArch::R4, LoongArch::R5, LoongArch::R6, LoongArch::R7, LoongArch::R8, LoongArch::R9, LoongArch::R10, LoongArch::R11, LoongArch::R12, LoongArch::R13, LoongArch::R14, LoongArch::R15, LoongArch::R16, LoongArch::R17, LoongArch::R18, LoongArch::R19, LoongArch::R20, LoongArch::R22, LoongArch::R23, LoongArch::R24, LoongArch::R25, LoongArch::R26, LoongArch::R27, LoongArch::R28, LoongArch::R29, LoongArch::R30, LoongArch::R31, LoongArch::R0, LoongArch::R2, LoongArch::R3, LoongArch::R21,
728 };
729
730 // GPRJR Bit set.
731 const uint8_t GPRJRBits[] = {
732 0x00, 0x00, 0x00, 0x00, 0x00, 0xa0, 0xff, 0xff, 0xff, 0x1f,
733 };
734
735 // GPRNoR0R1 Register Class...
736 const MCPhysReg GPRNoR0R1[] = {
737 LoongArch::R4, LoongArch::R5, LoongArch::R6, LoongArch::R7, LoongArch::R8, LoongArch::R9, LoongArch::R10, LoongArch::R11, LoongArch::R12, LoongArch::R13, LoongArch::R14, LoongArch::R15, LoongArch::R16, LoongArch::R17, LoongArch::R18, LoongArch::R19, LoongArch::R20, LoongArch::R22, LoongArch::R23, LoongArch::R24, LoongArch::R25, LoongArch::R26, LoongArch::R27, LoongArch::R28, LoongArch::R29, LoongArch::R30, LoongArch::R31, LoongArch::R2, LoongArch::R3, LoongArch::R21,
738 };
739
740 // GPRNoR0R1 Bit set.
741 const uint8_t GPRNoR0R1Bits[] = {
742 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x1f,
743 };
744
745 // GPRT Register Class...
746 const MCPhysReg GPRT[] = {
747 LoongArch::R4, LoongArch::R5, LoongArch::R6, LoongArch::R7, LoongArch::R8, LoongArch::R9, LoongArch::R10, LoongArch::R11, LoongArch::R12, LoongArch::R13, LoongArch::R14, LoongArch::R15, LoongArch::R16, LoongArch::R17, LoongArch::R18, LoongArch::R19, LoongArch::R20,
748 };
749
750 // GPRT Bit set.
751 const uint8_t GPRTBits[] = {
752 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0x03,
753 };
754
755 // CFR Register Class...
756 const MCPhysReg CFR[] = {
757 LoongArch::FCC0, LoongArch::FCC1, LoongArch::FCC2, LoongArch::FCC3, LoongArch::FCC4, LoongArch::FCC5, LoongArch::FCC6, LoongArch::FCC7,
758 };
759
760 // CFR Bit set.
761 const uint8_t CFRBits[] = {
762 0x00, 0x00, 0x00, 0x00, 0xfe, 0x01,
763 };
764
765 // FCSR Register Class...
766 const MCPhysReg FCSR[] = {
767 LoongArch::FCSR0, LoongArch::FCSR1, LoongArch::FCSR2, LoongArch::FCSR3,
768 };
769
770 // FCSR Bit set.
771 const uint8_t FCSRBits[] = {
772 0x00, 0x00, 0x00, 0x00, 0x00, 0x1e,
773 };
774
775 // SCR Register Class...
776 const MCPhysReg SCR[] = {
777 LoongArch::SCR0, LoongArch::SCR1, LoongArch::SCR2, LoongArch::SCR3,
778 };
779
780 // SCR Bit set.
781 const uint8_t SCRBits[] = {
782 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01,
783 };
784
785 // FPR64 Register Class...
786 const MCPhysReg FPR64[] = {
787 LoongArch::F0_64, LoongArch::F1_64, LoongArch::F2_64, LoongArch::F3_64, LoongArch::F4_64, LoongArch::F5_64, LoongArch::F6_64, LoongArch::F7_64, LoongArch::F8_64, LoongArch::F9_64, LoongArch::F10_64, LoongArch::F11_64, LoongArch::F12_64, LoongArch::F13_64, LoongArch::F14_64, LoongArch::F15_64, LoongArch::F16_64, LoongArch::F17_64, LoongArch::F18_64, LoongArch::F19_64, LoongArch::F20_64, LoongArch::F21_64, LoongArch::F22_64, LoongArch::F23_64, LoongArch::F24_64, LoongArch::F25_64, LoongArch::F26_64, LoongArch::F27_64, LoongArch::F28_64, LoongArch::F29_64, LoongArch::F30_64, LoongArch::F31_64,
788 };
789
790 // FPR64 Bit set.
791 const uint8_t FPR64Bits[] = {
792 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01,
793 };
794
795 // LSX128 Register Class...
796 const MCPhysReg LSX128[] = {
797 LoongArch::VR0, LoongArch::VR1, LoongArch::VR2, LoongArch::VR3, LoongArch::VR4, LoongArch::VR5, LoongArch::VR6, LoongArch::VR7, LoongArch::VR8, LoongArch::VR9, LoongArch::VR10, LoongArch::VR11, LoongArch::VR12, LoongArch::VR13, LoongArch::VR14, LoongArch::VR15, LoongArch::VR16, LoongArch::VR17, LoongArch::VR18, LoongArch::VR19, LoongArch::VR20, LoongArch::VR21, LoongArch::VR22, LoongArch::VR23, LoongArch::VR24, LoongArch::VR25, LoongArch::VR26, LoongArch::VR27, LoongArch::VR28, LoongArch::VR29, LoongArch::VR30, LoongArch::VR31,
798 };
799
800 // LSX128 Bit set.
801 const uint8_t LSX128Bits[] = {
802 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01,
803 };
804
805 // LASX256 Register Class...
806 const MCPhysReg LASX256[] = {
807 LoongArch::XR0, LoongArch::XR1, LoongArch::XR2, LoongArch::XR3, LoongArch::XR4, LoongArch::XR5, LoongArch::XR6, LoongArch::XR7, LoongArch::XR8, LoongArch::XR9, LoongArch::XR10, LoongArch::XR11, LoongArch::XR12, LoongArch::XR13, LoongArch::XR14, LoongArch::XR15, LoongArch::XR16, LoongArch::XR17, LoongArch::XR18, LoongArch::XR19, LoongArch::XR20, LoongArch::XR21, LoongArch::XR22, LoongArch::XR23, LoongArch::XR24, LoongArch::XR25, LoongArch::XR26, LoongArch::XR27, LoongArch::XR28, LoongArch::XR29, LoongArch::XR30, LoongArch::XR31,
808 };
809
810 // LASX256 Bit set.
811 const uint8_t LASX256Bits[] = {
812 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01,
813 };
814
815} // end anonymous namespace
816
817
818#ifdef __GNUC__
819#pragma GCC diagnostic push
820#pragma GCC diagnostic ignored "-Woverlength-strings"
821#endif
822extern const char LoongArchRegClassStrings[] = {
823 /* 0 */ "GPRNoR0R1\000"
824 /* 10 */ "FPR32\000"
825 /* 16 */ "FPR64\000"
826 /* 22 */ "LASX256\000"
827 /* 30 */ "LSX128\000"
828 /* 37 */ "SCR\000"
829 /* 41 */ "CFR\000"
830 /* 45 */ "GPRJR\000"
831 /* 51 */ "GPR\000"
832 /* 55 */ "FCSR\000"
833 /* 60 */ "GPRT\000"
834};
835#ifdef __GNUC__
836#pragma GCC diagnostic pop
837#endif
838
839extern const MCRegisterClass LoongArchMCRegisterClasses[] = {
840 { FPR32, FPR32Bits, 10, 32, sizeof(FPR32Bits), LoongArch::FPR32RegClassID, 32, 1, true, false },
841 { GPR, GPRBits, 51, 32, sizeof(GPRBits), LoongArch::GPRRegClassID, 0, 1, true, false },
842 { GPRJR, GPRJRBits, 45, 31, sizeof(GPRJRBits), LoongArch::GPRJRRegClassID, 0, 1, true, false },
843 { GPRNoR0R1, GPRNoR0R1Bits, 0, 30, sizeof(GPRNoR0R1Bits), LoongArch::GPRNoR0R1RegClassID, 0, 1, true, false },
844 { GPRT, GPRTBits, 60, 17, sizeof(GPRTBits), LoongArch::GPRTRegClassID, 0, 1, true, false },
845 { CFR, CFRBits, 41, 8, sizeof(CFRBits), LoongArch::CFRRegClassID, 0, 1, true, false },
846 { FCSR, FCSRBits, 55, 4, sizeof(FCSRBits), LoongArch::FCSRRegClassID, 32, 1, false, false },
847 { SCR, SCRBits, 37, 4, sizeof(SCRBits), LoongArch::SCRRegClassID, 0, 1, false, false },
848 { FPR64, FPR64Bits, 16, 32, sizeof(FPR64Bits), LoongArch::FPR64RegClassID, 64, 1, true, false },
849 { LSX128, LSX128Bits, 30, 32, sizeof(LSX128Bits), LoongArch::LSX128RegClassID, 128, 1, true, false },
850 { LASX256, LASX256Bits, 22, 32, sizeof(LASX256Bits), LoongArch::LASX256RegClassID, 256, 1, true, false },
851};
852
853// LoongArch Dwarf<->LLVM register mappings.
854extern const MCRegisterInfo::DwarfLLVMRegPair LoongArchDwarfFlavour0Dwarf2L[] = {
855 { 0U, LoongArch::R0 },
856 { 1U, LoongArch::R1 },
857 { 2U, LoongArch::R2 },
858 { 3U, LoongArch::R3 },
859 { 4U, LoongArch::R4 },
860 { 5U, LoongArch::R5 },
861 { 6U, LoongArch::R6 },
862 { 7U, LoongArch::R7 },
863 { 8U, LoongArch::R8 },
864 { 9U, LoongArch::R9 },
865 { 10U, LoongArch::R10 },
866 { 11U, LoongArch::R11 },
867 { 12U, LoongArch::R12 },
868 { 13U, LoongArch::R13 },
869 { 14U, LoongArch::R14 },
870 { 15U, LoongArch::R15 },
871 { 16U, LoongArch::R16 },
872 { 17U, LoongArch::R17 },
873 { 18U, LoongArch::R18 },
874 { 19U, LoongArch::R19 },
875 { 20U, LoongArch::R20 },
876 { 21U, LoongArch::R21 },
877 { 22U, LoongArch::R22 },
878 { 23U, LoongArch::R23 },
879 { 24U, LoongArch::R24 },
880 { 25U, LoongArch::R25 },
881 { 26U, LoongArch::R26 },
882 { 27U, LoongArch::R27 },
883 { 28U, LoongArch::R28 },
884 { 29U, LoongArch::R29 },
885 { 30U, LoongArch::R30 },
886 { 31U, LoongArch::R31 },
887 { 32U, LoongArch::F0_64 },
888 { 33U, LoongArch::F1_64 },
889 { 34U, LoongArch::F2_64 },
890 { 35U, LoongArch::F3_64 },
891 { 36U, LoongArch::F4_64 },
892 { 37U, LoongArch::F5_64 },
893 { 38U, LoongArch::F6_64 },
894 { 39U, LoongArch::F7_64 },
895 { 40U, LoongArch::F8_64 },
896 { 41U, LoongArch::F9_64 },
897 { 42U, LoongArch::F10_64 },
898 { 43U, LoongArch::F11_64 },
899 { 44U, LoongArch::F12_64 },
900 { 45U, LoongArch::F13_64 },
901 { 46U, LoongArch::F14_64 },
902 { 47U, LoongArch::F15_64 },
903 { 48U, LoongArch::F16_64 },
904 { 49U, LoongArch::F17_64 },
905 { 50U, LoongArch::F18_64 },
906 { 51U, LoongArch::F19_64 },
907 { 52U, LoongArch::F20_64 },
908 { 53U, LoongArch::F21_64 },
909 { 54U, LoongArch::F22_64 },
910 { 55U, LoongArch::F23_64 },
911 { 56U, LoongArch::F24_64 },
912 { 57U, LoongArch::F25_64 },
913 { 58U, LoongArch::F26_64 },
914 { 59U, LoongArch::F27_64 },
915 { 60U, LoongArch::F28_64 },
916 { 61U, LoongArch::F29_64 },
917 { 62U, LoongArch::F30_64 },
918 { 63U, LoongArch::F31_64 },
919};
920extern const unsigned LoongArchDwarfFlavour0Dwarf2LSize = std::size(LoongArchDwarfFlavour0Dwarf2L);
921
922extern const MCRegisterInfo::DwarfLLVMRegPair LoongArchEHFlavour0Dwarf2L[] = {
923 { 0U, LoongArch::R0 },
924 { 1U, LoongArch::R1 },
925 { 2U, LoongArch::R2 },
926 { 3U, LoongArch::R3 },
927 { 4U, LoongArch::R4 },
928 { 5U, LoongArch::R5 },
929 { 6U, LoongArch::R6 },
930 { 7U, LoongArch::R7 },
931 { 8U, LoongArch::R8 },
932 { 9U, LoongArch::R9 },
933 { 10U, LoongArch::R10 },
934 { 11U, LoongArch::R11 },
935 { 12U, LoongArch::R12 },
936 { 13U, LoongArch::R13 },
937 { 14U, LoongArch::R14 },
938 { 15U, LoongArch::R15 },
939 { 16U, LoongArch::R16 },
940 { 17U, LoongArch::R17 },
941 { 18U, LoongArch::R18 },
942 { 19U, LoongArch::R19 },
943 { 20U, LoongArch::R20 },
944 { 21U, LoongArch::R21 },
945 { 22U, LoongArch::R22 },
946 { 23U, LoongArch::R23 },
947 { 24U, LoongArch::R24 },
948 { 25U, LoongArch::R25 },
949 { 26U, LoongArch::R26 },
950 { 27U, LoongArch::R27 },
951 { 28U, LoongArch::R28 },
952 { 29U, LoongArch::R29 },
953 { 30U, LoongArch::R30 },
954 { 31U, LoongArch::R31 },
955 { 32U, LoongArch::F0_64 },
956 { 33U, LoongArch::F1_64 },
957 { 34U, LoongArch::F2_64 },
958 { 35U, LoongArch::F3_64 },
959 { 36U, LoongArch::F4_64 },
960 { 37U, LoongArch::F5_64 },
961 { 38U, LoongArch::F6_64 },
962 { 39U, LoongArch::F7_64 },
963 { 40U, LoongArch::F8_64 },
964 { 41U, LoongArch::F9_64 },
965 { 42U, LoongArch::F10_64 },
966 { 43U, LoongArch::F11_64 },
967 { 44U, LoongArch::F12_64 },
968 { 45U, LoongArch::F13_64 },
969 { 46U, LoongArch::F14_64 },
970 { 47U, LoongArch::F15_64 },
971 { 48U, LoongArch::F16_64 },
972 { 49U, LoongArch::F17_64 },
973 { 50U, LoongArch::F18_64 },
974 { 51U, LoongArch::F19_64 },
975 { 52U, LoongArch::F20_64 },
976 { 53U, LoongArch::F21_64 },
977 { 54U, LoongArch::F22_64 },
978 { 55U, LoongArch::F23_64 },
979 { 56U, LoongArch::F24_64 },
980 { 57U, LoongArch::F25_64 },
981 { 58U, LoongArch::F26_64 },
982 { 59U, LoongArch::F27_64 },
983 { 60U, LoongArch::F28_64 },
984 { 61U, LoongArch::F29_64 },
985 { 62U, LoongArch::F30_64 },
986 { 63U, LoongArch::F31_64 },
987};
988extern const unsigned LoongArchEHFlavour0Dwarf2LSize = std::size(LoongArchEHFlavour0Dwarf2L);
989
990extern const MCRegisterInfo::DwarfLLVMRegPair LoongArchDwarfFlavour0L2Dwarf[] = {
991 { LoongArch::F0, 32U },
992 { LoongArch::F1, 33U },
993 { LoongArch::F2, 34U },
994 { LoongArch::F3, 35U },
995 { LoongArch::F4, 36U },
996 { LoongArch::F5, 37U },
997 { LoongArch::F6, 38U },
998 { LoongArch::F7, 39U },
999 { LoongArch::F8, 40U },
1000 { LoongArch::F9, 41U },
1001 { LoongArch::F10, 42U },
1002 { LoongArch::F11, 43U },
1003 { LoongArch::F12, 44U },
1004 { LoongArch::F13, 45U },
1005 { LoongArch::F14, 46U },
1006 { LoongArch::F15, 47U },
1007 { LoongArch::F16, 48U },
1008 { LoongArch::F17, 49U },
1009 { LoongArch::F18, 50U },
1010 { LoongArch::F19, 51U },
1011 { LoongArch::F20, 52U },
1012 { LoongArch::F21, 53U },
1013 { LoongArch::F22, 54U },
1014 { LoongArch::F23, 55U },
1015 { LoongArch::F24, 56U },
1016 { LoongArch::F25, 57U },
1017 { LoongArch::F26, 58U },
1018 { LoongArch::F27, 59U },
1019 { LoongArch::F28, 60U },
1020 { LoongArch::F29, 61U },
1021 { LoongArch::F30, 62U },
1022 { LoongArch::F31, 63U },
1023 { LoongArch::R0, 0U },
1024 { LoongArch::R1, 1U },
1025 { LoongArch::R2, 2U },
1026 { LoongArch::R3, 3U },
1027 { LoongArch::R4, 4U },
1028 { LoongArch::R5, 5U },
1029 { LoongArch::R6, 6U },
1030 { LoongArch::R7, 7U },
1031 { LoongArch::R8, 8U },
1032 { LoongArch::R9, 9U },
1033 { LoongArch::R10, 10U },
1034 { LoongArch::R11, 11U },
1035 { LoongArch::R12, 12U },
1036 { LoongArch::R13, 13U },
1037 { LoongArch::R14, 14U },
1038 { LoongArch::R15, 15U },
1039 { LoongArch::R16, 16U },
1040 { LoongArch::R17, 17U },
1041 { LoongArch::R18, 18U },
1042 { LoongArch::R19, 19U },
1043 { LoongArch::R20, 20U },
1044 { LoongArch::R21, 21U },
1045 { LoongArch::R22, 22U },
1046 { LoongArch::R23, 23U },
1047 { LoongArch::R24, 24U },
1048 { LoongArch::R25, 25U },
1049 { LoongArch::R26, 26U },
1050 { LoongArch::R27, 27U },
1051 { LoongArch::R28, 28U },
1052 { LoongArch::R29, 29U },
1053 { LoongArch::R30, 30U },
1054 { LoongArch::R31, 31U },
1055 { LoongArch::VR0, 32U },
1056 { LoongArch::VR1, 33U },
1057 { LoongArch::VR2, 34U },
1058 { LoongArch::VR3, 35U },
1059 { LoongArch::VR4, 36U },
1060 { LoongArch::VR5, 37U },
1061 { LoongArch::VR6, 38U },
1062 { LoongArch::VR7, 39U },
1063 { LoongArch::VR8, 40U },
1064 { LoongArch::VR9, 41U },
1065 { LoongArch::VR10, 42U },
1066 { LoongArch::VR11, 43U },
1067 { LoongArch::VR12, 44U },
1068 { LoongArch::VR13, 45U },
1069 { LoongArch::VR14, 46U },
1070 { LoongArch::VR15, 47U },
1071 { LoongArch::VR16, 48U },
1072 { LoongArch::VR17, 49U },
1073 { LoongArch::VR18, 50U },
1074 { LoongArch::VR19, 51U },
1075 { LoongArch::VR20, 52U },
1076 { LoongArch::VR21, 53U },
1077 { LoongArch::VR22, 54U },
1078 { LoongArch::VR23, 55U },
1079 { LoongArch::VR24, 56U },
1080 { LoongArch::VR25, 57U },
1081 { LoongArch::VR26, 58U },
1082 { LoongArch::VR27, 59U },
1083 { LoongArch::VR28, 60U },
1084 { LoongArch::VR29, 61U },
1085 { LoongArch::VR30, 62U },
1086 { LoongArch::VR31, 63U },
1087 { LoongArch::XR0, 32U },
1088 { LoongArch::XR1, 33U },
1089 { LoongArch::XR2, 34U },
1090 { LoongArch::XR3, 35U },
1091 { LoongArch::XR4, 36U },
1092 { LoongArch::XR5, 37U },
1093 { LoongArch::XR6, 38U },
1094 { LoongArch::XR7, 39U },
1095 { LoongArch::XR8, 40U },
1096 { LoongArch::XR9, 41U },
1097 { LoongArch::XR10, 42U },
1098 { LoongArch::XR11, 43U },
1099 { LoongArch::XR12, 44U },
1100 { LoongArch::XR13, 45U },
1101 { LoongArch::XR14, 46U },
1102 { LoongArch::XR15, 47U },
1103 { LoongArch::XR16, 48U },
1104 { LoongArch::XR17, 49U },
1105 { LoongArch::XR18, 50U },
1106 { LoongArch::XR19, 51U },
1107 { LoongArch::XR20, 52U },
1108 { LoongArch::XR21, 53U },
1109 { LoongArch::XR22, 54U },
1110 { LoongArch::XR23, 55U },
1111 { LoongArch::XR24, 56U },
1112 { LoongArch::XR25, 57U },
1113 { LoongArch::XR26, 58U },
1114 { LoongArch::XR27, 59U },
1115 { LoongArch::XR28, 60U },
1116 { LoongArch::XR29, 61U },
1117 { LoongArch::XR30, 62U },
1118 { LoongArch::XR31, 63U },
1119 { LoongArch::F0_64, 32U },
1120 { LoongArch::F1_64, 33U },
1121 { LoongArch::F2_64, 34U },
1122 { LoongArch::F3_64, 35U },
1123 { LoongArch::F4_64, 36U },
1124 { LoongArch::F5_64, 37U },
1125 { LoongArch::F6_64, 38U },
1126 { LoongArch::F7_64, 39U },
1127 { LoongArch::F8_64, 40U },
1128 { LoongArch::F9_64, 41U },
1129 { LoongArch::F10_64, 42U },
1130 { LoongArch::F11_64, 43U },
1131 { LoongArch::F12_64, 44U },
1132 { LoongArch::F13_64, 45U },
1133 { LoongArch::F14_64, 46U },
1134 { LoongArch::F15_64, 47U },
1135 { LoongArch::F16_64, 48U },
1136 { LoongArch::F17_64, 49U },
1137 { LoongArch::F18_64, 50U },
1138 { LoongArch::F19_64, 51U },
1139 { LoongArch::F20_64, 52U },
1140 { LoongArch::F21_64, 53U },
1141 { LoongArch::F22_64, 54U },
1142 { LoongArch::F23_64, 55U },
1143 { LoongArch::F24_64, 56U },
1144 { LoongArch::F25_64, 57U },
1145 { LoongArch::F26_64, 58U },
1146 { LoongArch::F27_64, 59U },
1147 { LoongArch::F28_64, 60U },
1148 { LoongArch::F29_64, 61U },
1149 { LoongArch::F30_64, 62U },
1150 { LoongArch::F31_64, 63U },
1151};
1152extern const unsigned LoongArchDwarfFlavour0L2DwarfSize = std::size(LoongArchDwarfFlavour0L2Dwarf);
1153
1154extern const MCRegisterInfo::DwarfLLVMRegPair LoongArchEHFlavour0L2Dwarf[] = {
1155 { LoongArch::F0, 32U },
1156 { LoongArch::F1, 33U },
1157 { LoongArch::F2, 34U },
1158 { LoongArch::F3, 35U },
1159 { LoongArch::F4, 36U },
1160 { LoongArch::F5, 37U },
1161 { LoongArch::F6, 38U },
1162 { LoongArch::F7, 39U },
1163 { LoongArch::F8, 40U },
1164 { LoongArch::F9, 41U },
1165 { LoongArch::F10, 42U },
1166 { LoongArch::F11, 43U },
1167 { LoongArch::F12, 44U },
1168 { LoongArch::F13, 45U },
1169 { LoongArch::F14, 46U },
1170 { LoongArch::F15, 47U },
1171 { LoongArch::F16, 48U },
1172 { LoongArch::F17, 49U },
1173 { LoongArch::F18, 50U },
1174 { LoongArch::F19, 51U },
1175 { LoongArch::F20, 52U },
1176 { LoongArch::F21, 53U },
1177 { LoongArch::F22, 54U },
1178 { LoongArch::F23, 55U },
1179 { LoongArch::F24, 56U },
1180 { LoongArch::F25, 57U },
1181 { LoongArch::F26, 58U },
1182 { LoongArch::F27, 59U },
1183 { LoongArch::F28, 60U },
1184 { LoongArch::F29, 61U },
1185 { LoongArch::F30, 62U },
1186 { LoongArch::F31, 63U },
1187 { LoongArch::R0, 0U },
1188 { LoongArch::R1, 1U },
1189 { LoongArch::R2, 2U },
1190 { LoongArch::R3, 3U },
1191 { LoongArch::R4, 4U },
1192 { LoongArch::R5, 5U },
1193 { LoongArch::R6, 6U },
1194 { LoongArch::R7, 7U },
1195 { LoongArch::R8, 8U },
1196 { LoongArch::R9, 9U },
1197 { LoongArch::R10, 10U },
1198 { LoongArch::R11, 11U },
1199 { LoongArch::R12, 12U },
1200 { LoongArch::R13, 13U },
1201 { LoongArch::R14, 14U },
1202 { LoongArch::R15, 15U },
1203 { LoongArch::R16, 16U },
1204 { LoongArch::R17, 17U },
1205 { LoongArch::R18, 18U },
1206 { LoongArch::R19, 19U },
1207 { LoongArch::R20, 20U },
1208 { LoongArch::R21, 21U },
1209 { LoongArch::R22, 22U },
1210 { LoongArch::R23, 23U },
1211 { LoongArch::R24, 24U },
1212 { LoongArch::R25, 25U },
1213 { LoongArch::R26, 26U },
1214 { LoongArch::R27, 27U },
1215 { LoongArch::R28, 28U },
1216 { LoongArch::R29, 29U },
1217 { LoongArch::R30, 30U },
1218 { LoongArch::R31, 31U },
1219 { LoongArch::VR0, 32U },
1220 { LoongArch::VR1, 33U },
1221 { LoongArch::VR2, 34U },
1222 { LoongArch::VR3, 35U },
1223 { LoongArch::VR4, 36U },
1224 { LoongArch::VR5, 37U },
1225 { LoongArch::VR6, 38U },
1226 { LoongArch::VR7, 39U },
1227 { LoongArch::VR8, 40U },
1228 { LoongArch::VR9, 41U },
1229 { LoongArch::VR10, 42U },
1230 { LoongArch::VR11, 43U },
1231 { LoongArch::VR12, 44U },
1232 { LoongArch::VR13, 45U },
1233 { LoongArch::VR14, 46U },
1234 { LoongArch::VR15, 47U },
1235 { LoongArch::VR16, 48U },
1236 { LoongArch::VR17, 49U },
1237 { LoongArch::VR18, 50U },
1238 { LoongArch::VR19, 51U },
1239 { LoongArch::VR20, 52U },
1240 { LoongArch::VR21, 53U },
1241 { LoongArch::VR22, 54U },
1242 { LoongArch::VR23, 55U },
1243 { LoongArch::VR24, 56U },
1244 { LoongArch::VR25, 57U },
1245 { LoongArch::VR26, 58U },
1246 { LoongArch::VR27, 59U },
1247 { LoongArch::VR28, 60U },
1248 { LoongArch::VR29, 61U },
1249 { LoongArch::VR30, 62U },
1250 { LoongArch::VR31, 63U },
1251 { LoongArch::XR0, 32U },
1252 { LoongArch::XR1, 33U },
1253 { LoongArch::XR2, 34U },
1254 { LoongArch::XR3, 35U },
1255 { LoongArch::XR4, 36U },
1256 { LoongArch::XR5, 37U },
1257 { LoongArch::XR6, 38U },
1258 { LoongArch::XR7, 39U },
1259 { LoongArch::XR8, 40U },
1260 { LoongArch::XR9, 41U },
1261 { LoongArch::XR10, 42U },
1262 { LoongArch::XR11, 43U },
1263 { LoongArch::XR12, 44U },
1264 { LoongArch::XR13, 45U },
1265 { LoongArch::XR14, 46U },
1266 { LoongArch::XR15, 47U },
1267 { LoongArch::XR16, 48U },
1268 { LoongArch::XR17, 49U },
1269 { LoongArch::XR18, 50U },
1270 { LoongArch::XR19, 51U },
1271 { LoongArch::XR20, 52U },
1272 { LoongArch::XR21, 53U },
1273 { LoongArch::XR22, 54U },
1274 { LoongArch::XR23, 55U },
1275 { LoongArch::XR24, 56U },
1276 { LoongArch::XR25, 57U },
1277 { LoongArch::XR26, 58U },
1278 { LoongArch::XR27, 59U },
1279 { LoongArch::XR28, 60U },
1280 { LoongArch::XR29, 61U },
1281 { LoongArch::XR30, 62U },
1282 { LoongArch::XR31, 63U },
1283 { LoongArch::F0_64, 32U },
1284 { LoongArch::F1_64, 33U },
1285 { LoongArch::F2_64, 34U },
1286 { LoongArch::F3_64, 35U },
1287 { LoongArch::F4_64, 36U },
1288 { LoongArch::F5_64, 37U },
1289 { LoongArch::F6_64, 38U },
1290 { LoongArch::F7_64, 39U },
1291 { LoongArch::F8_64, 40U },
1292 { LoongArch::F9_64, 41U },
1293 { LoongArch::F10_64, 42U },
1294 { LoongArch::F11_64, 43U },
1295 { LoongArch::F12_64, 44U },
1296 { LoongArch::F13_64, 45U },
1297 { LoongArch::F14_64, 46U },
1298 { LoongArch::F15_64, 47U },
1299 { LoongArch::F16_64, 48U },
1300 { LoongArch::F17_64, 49U },
1301 { LoongArch::F18_64, 50U },
1302 { LoongArch::F19_64, 51U },
1303 { LoongArch::F20_64, 52U },
1304 { LoongArch::F21_64, 53U },
1305 { LoongArch::F22_64, 54U },
1306 { LoongArch::F23_64, 55U },
1307 { LoongArch::F24_64, 56U },
1308 { LoongArch::F25_64, 57U },
1309 { LoongArch::F26_64, 58U },
1310 { LoongArch::F27_64, 59U },
1311 { LoongArch::F28_64, 60U },
1312 { LoongArch::F29_64, 61U },
1313 { LoongArch::F30_64, 62U },
1314 { LoongArch::F31_64, 63U },
1315};
1316extern const unsigned LoongArchEHFlavour0L2DwarfSize = std::size(LoongArchEHFlavour0L2Dwarf);
1317
1318extern const uint16_t LoongArchRegEncodingTable[] = {
1319 0,
1320 0,
1321 1,
1322 2,
1323 3,
1324 4,
1325 5,
1326 6,
1327 7,
1328 8,
1329 9,
1330 10,
1331 11,
1332 12,
1333 13,
1334 14,
1335 15,
1336 16,
1337 17,
1338 18,
1339 19,
1340 20,
1341 21,
1342 22,
1343 23,
1344 24,
1345 25,
1346 26,
1347 27,
1348 28,
1349 29,
1350 30,
1351 31,
1352 0,
1353 1,
1354 2,
1355 3,
1356 4,
1357 5,
1358 6,
1359 7,
1360 0,
1361 1,
1362 2,
1363 3,
1364 0,
1365 1,
1366 2,
1367 3,
1368 4,
1369 5,
1370 6,
1371 7,
1372 8,
1373 9,
1374 10,
1375 11,
1376 12,
1377 13,
1378 14,
1379 15,
1380 16,
1381 17,
1382 18,
1383 19,
1384 20,
1385 21,
1386 22,
1387 23,
1388 24,
1389 25,
1390 26,
1391 27,
1392 28,
1393 29,
1394 30,
1395 31,
1396 0,
1397 1,
1398 2,
1399 3,
1400 0,
1401 1,
1402 2,
1403 3,
1404 4,
1405 5,
1406 6,
1407 7,
1408 8,
1409 9,
1410 10,
1411 11,
1412 12,
1413 13,
1414 14,
1415 15,
1416 16,
1417 17,
1418 18,
1419 19,
1420 20,
1421 21,
1422 22,
1423 23,
1424 24,
1425 25,
1426 26,
1427 27,
1428 28,
1429 29,
1430 30,
1431 31,
1432 0,
1433 1,
1434 2,
1435 3,
1436 4,
1437 5,
1438 6,
1439 7,
1440 8,
1441 9,
1442 10,
1443 11,
1444 12,
1445 13,
1446 14,
1447 15,
1448 16,
1449 17,
1450 18,
1451 19,
1452 20,
1453 21,
1454 22,
1455 23,
1456 24,
1457 25,
1458 26,
1459 27,
1460 28,
1461 29,
1462 30,
1463 31,
1464 0,
1465 1,
1466 2,
1467 3,
1468 4,
1469 5,
1470 6,
1471 7,
1472 8,
1473 9,
1474 10,
1475 11,
1476 12,
1477 13,
1478 14,
1479 15,
1480 16,
1481 17,
1482 18,
1483 19,
1484 20,
1485 21,
1486 22,
1487 23,
1488 24,
1489 25,
1490 26,
1491 27,
1492 28,
1493 29,
1494 30,
1495 31,
1496};
1497static inline void InitLoongArchMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
1498 RI->InitMCRegisterInfo(LoongArchRegDesc, 177, RA, PC, LoongArchMCRegisterClasses, 11, LoongArchRegUnitRoots, 80, LoongArchRegDiffLists, LoongArchLaneMaskLists, LoongArchRegStrings, LoongArchRegClassStrings, LoongArchSubRegIdxLists, 4,
1499LoongArchRegEncodingTable);
1500
1501 switch (DwarfFlavour) {
1502 default:
1503 llvm_unreachable("Unknown DWARF flavour");
1504 case 0:
1505 RI->mapDwarfRegsToLLVMRegs(LoongArchDwarfFlavour0Dwarf2L, LoongArchDwarfFlavour0Dwarf2LSize, false);
1506 break;
1507 }
1508 switch (EHFlavour) {
1509 default:
1510 llvm_unreachable("Unknown DWARF flavour");
1511 case 0:
1512 RI->mapDwarfRegsToLLVMRegs(LoongArchEHFlavour0Dwarf2L, LoongArchEHFlavour0Dwarf2LSize, true);
1513 break;
1514 }
1515 switch (DwarfFlavour) {
1516 default:
1517 llvm_unreachable("Unknown DWARF flavour");
1518 case 0:
1519 RI->mapLLVMRegsToDwarfRegs(LoongArchDwarfFlavour0L2Dwarf, LoongArchDwarfFlavour0L2DwarfSize, false);
1520 break;
1521 }
1522 switch (EHFlavour) {
1523 default:
1524 llvm_unreachable("Unknown DWARF flavour");
1525 case 0:
1526 RI->mapLLVMRegsToDwarfRegs(LoongArchEHFlavour0L2Dwarf, LoongArchEHFlavour0L2DwarfSize, true);
1527 break;
1528 }
1529}
1530
1531} // end namespace llvm
1532
1533#endif // GET_REGINFO_MC_DESC
1534
1535/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
1536|* *|
1537|* Register Information Header Fragment *|
1538|* *|
1539|* Automatically generated file, do not edit! *|
1540|* *|
1541\*===----------------------------------------------------------------------===*/
1542
1543
1544#ifdef GET_REGINFO_HEADER
1545#undef GET_REGINFO_HEADER
1546
1547#include "llvm/CodeGen/TargetRegisterInfo.h"
1548
1549namespace llvm {
1550
1551class LoongArchFrameLowering;
1552
1553struct LoongArchGenRegisterInfo : public TargetRegisterInfo {
1554 explicit LoongArchGenRegisterInfo(unsigned RA, unsigned D = 0, unsigned E = 0,
1555 unsigned PC = 0, unsigned HwMode = 0);
1556 unsigned composeSubRegIndicesImpl(unsigned, unsigned) const override;
1557 unsigned reverseComposeSubRegIndicesImpl(unsigned, unsigned) const override;
1558 LaneBitmask composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
1559 LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
1560 const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass *, unsigned) const override;
1561 const TargetRegisterClass *getSubRegisterClass(const TargetRegisterClass *, unsigned) const override;
1562 const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override;
1563 unsigned getRegUnitWeight(unsigned RegUnit) const override;
1564 unsigned getNumRegPressureSets() const override;
1565 const char *getRegPressureSetName(unsigned Idx) const override;
1566 unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override;
1567 const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override;
1568 const int *getRegUnitPressureSets(unsigned RegUnit) const override;
1569 ArrayRef<const char *> getRegMaskNames() const override;
1570 ArrayRef<const uint32_t *> getRegMasks() const override;
1571 bool isGeneralPurposeRegister(const MachineFunction &, MCRegister) const override;
1572 bool isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const override;
1573 bool isFixedRegister(const MachineFunction &, MCRegister) const override;
1574 bool isArgumentRegister(const MachineFunction &, MCRegister) const override;
1575 bool isConstantPhysReg(MCRegister PhysReg) const override final;
1576 /// Devirtualized TargetFrameLowering.
1577 static const LoongArchFrameLowering *getFrameLowering(
1578 const MachineFunction &MF);
1579};
1580
1581namespace LoongArch { // Register classes
1582 extern const TargetRegisterClass FPR32RegClass;
1583 extern const TargetRegisterClass GPRRegClass;
1584 extern const TargetRegisterClass GPRJRRegClass;
1585 extern const TargetRegisterClass GPRNoR0R1RegClass;
1586 extern const TargetRegisterClass GPRTRegClass;
1587 extern const TargetRegisterClass CFRRegClass;
1588 extern const TargetRegisterClass FCSRRegClass;
1589 extern const TargetRegisterClass SCRRegClass;
1590 extern const TargetRegisterClass FPR64RegClass;
1591 extern const TargetRegisterClass LSX128RegClass;
1592 extern const TargetRegisterClass LASX256RegClass;
1593} // end namespace LoongArch
1594
1595} // end namespace llvm
1596
1597#endif // GET_REGINFO_HEADER
1598
1599/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
1600|* *|
1601|* Target Register and Register Classes Information *|
1602|* *|
1603|* Automatically generated file, do not edit! *|
1604|* *|
1605\*===----------------------------------------------------------------------===*/
1606
1607
1608#ifdef GET_REGINFO_TARGET_DESC
1609#undef GET_REGINFO_TARGET_DESC
1610
1611namespace llvm {
1612
1613extern const MCRegisterClass LoongArchMCRegisterClasses[];
1614
1615static const MVT::SimpleValueType VTLists[] = {
1616 /* 0 */ MVT::i32, MVT::Other,
1617 /* 2 */ MVT::i64, MVT::Other,
1618 /* 4 */ MVT::f32, MVT::Other,
1619 /* 6 */ MVT::f64, MVT::Other,
1620 /* 8 */ MVT::v4f32, MVT::v2f64, MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64, MVT::Other,
1621 /* 15 */ MVT::v8f32, MVT::v4f64, MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64, MVT::Other,
1622};
1623
1624static const char *SubRegIndexNameTable[] = { "sub_32", "sub_64", "sub_128", "" };
1625
1626static const TargetRegisterInfo::SubRegCoveredBits SubRegIdxRangeTable[] = {
1627 { 65535, 65535 },
1628 { 0, 32 }, // sub_32
1629 { 0, 64 }, // sub_64
1630 { 0, 128 }, // sub_128
1631 { 65535, 65535 },
1632 { 0, 32 }, // sub_32
1633 { 0, 64 }, // sub_64
1634 { 0, 128 }, // sub_128
1635};
1636
1637
1638static const LaneBitmask SubRegIndexLaneMaskTable[] = {
1639 LaneBitmask::getAll(),
1640 LaneBitmask(0x0000000000000001), // sub_32
1641 LaneBitmask(0x0000000000000001), // sub_64
1642 LaneBitmask(0x0000000000000001), // sub_128
1643 };
1644
1645
1646
1647static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
1648 // Mode = 0 (Default)
1649 { 32, 32, 32, /*VTLists+*/4 }, // FPR32
1650 { 32, 32, 32, /*VTLists+*/0 }, // GPR
1651 { 32, 32, 32, /*VTLists+*/0 }, // GPRJR
1652 { 32, 32, 32, /*VTLists+*/0 }, // GPRNoR0R1
1653 { 32, 32, 32, /*VTLists+*/0 }, // GPRT
1654 { 32, 32, 32, /*VTLists+*/0 }, // CFR
1655 { 32, 32, 32, /*VTLists+*/0 }, // FCSR
1656 { 32, 32, 32, /*VTLists+*/0 }, // SCR
1657 { 64, 64, 64, /*VTLists+*/6 }, // FPR64
1658 { 128, 128, 128, /*VTLists+*/8 }, // LSX128
1659 { 256, 256, 256, /*VTLists+*/15 }, // LASX256
1660 // Mode = 1 (LA64)
1661 { 32, 32, 32, /*VTLists+*/4 }, // FPR32
1662 { 64, 64, 64, /*VTLists+*/2 }, // GPR
1663 { 64, 64, 64, /*VTLists+*/2 }, // GPRJR
1664 { 64, 64, 64, /*VTLists+*/2 }, // GPRNoR0R1
1665 { 64, 64, 64, /*VTLists+*/2 }, // GPRT
1666 { 64, 64, 64, /*VTLists+*/2 }, // CFR
1667 { 32, 32, 32, /*VTLists+*/0 }, // FCSR
1668 { 64, 64, 64, /*VTLists+*/2 }, // SCR
1669 { 64, 64, 64, /*VTLists+*/6 }, // FPR64
1670 { 128, 128, 128, /*VTLists+*/8 }, // LSX128
1671 { 256, 256, 256, /*VTLists+*/15 }, // LASX256
1672};
1673static const uint32_t FPR32SubClassMask[] = {
1674 0x00000001,
1675 0x00000700, // sub_32
1676};
1677
1678static const uint32_t GPRSubClassMask[] = {
1679 0x0000001e,
1680};
1681
1682static const uint32_t GPRJRSubClassMask[] = {
1683 0x0000001c,
1684};
1685
1686static const uint32_t GPRNoR0R1SubClassMask[] = {
1687 0x00000018,
1688};
1689
1690static const uint32_t GPRTSubClassMask[] = {
1691 0x00000010,
1692};
1693
1694static const uint32_t CFRSubClassMask[] = {
1695 0x00000020,
1696};
1697
1698static const uint32_t FCSRSubClassMask[] = {
1699 0x00000040,
1700};
1701
1702static const uint32_t SCRSubClassMask[] = {
1703 0x00000080,
1704};
1705
1706static const uint32_t FPR64SubClassMask[] = {
1707 0x00000100,
1708 0x00000600, // sub_64
1709};
1710
1711static const uint32_t LSX128SubClassMask[] = {
1712 0x00000200,
1713 0x00000400, // sub_128
1714};
1715
1716static const uint32_t LASX256SubClassMask[] = {
1717 0x00000400,
1718};
1719
1720static const uint16_t SuperRegIdxSeqs[] = {
1721 /* 0 */ 1, 0,
1722 /* 2 */ 2, 0,
1723 /* 4 */ 3, 0,
1724};
1725
1726static unsigned const GPRJRSuperclasses[] = {
1727 LoongArch::GPRRegClassID,
1728};
1729
1730static unsigned const GPRNoR0R1Superclasses[] = {
1731 LoongArch::GPRRegClassID,
1732 LoongArch::GPRJRRegClassID,
1733};
1734
1735static unsigned const GPRTSuperclasses[] = {
1736 LoongArch::GPRRegClassID,
1737 LoongArch::GPRJRRegClassID,
1738 LoongArch::GPRNoR0R1RegClassID,
1739};
1740
1741
1742namespace LoongArch { // Register class instances
1743 extern const TargetRegisterClass FPR32RegClass = {
1744 &LoongArchMCRegisterClasses[FPR32RegClassID],
1745 FPR32SubClassMask,
1746 SuperRegIdxSeqs + 0,
1747 LaneBitmask(0x0000000000000001),
1748 0,
1749 false,
1750 0x00, /* TSFlags */
1751 false, /* HasDisjunctSubRegs */
1752 false, /* CoveredBySubRegs */
1753 nullptr, 0,
1754 nullptr
1755 };
1756
1757 extern const TargetRegisterClass GPRRegClass = {
1758 &LoongArchMCRegisterClasses[GPRRegClassID],
1759 GPRSubClassMask,
1760 SuperRegIdxSeqs + 1,
1761 LaneBitmask(0x0000000000000001),
1762 0,
1763 false,
1764 0x00, /* TSFlags */
1765 false, /* HasDisjunctSubRegs */
1766 false, /* CoveredBySubRegs */
1767 nullptr, 0,
1768 nullptr
1769 };
1770
1771 extern const TargetRegisterClass GPRJRRegClass = {
1772 &LoongArchMCRegisterClasses[GPRJRRegClassID],
1773 GPRJRSubClassMask,
1774 SuperRegIdxSeqs + 1,
1775 LaneBitmask(0x0000000000000001),
1776 0,
1777 false,
1778 0x00, /* TSFlags */
1779 false, /* HasDisjunctSubRegs */
1780 false, /* CoveredBySubRegs */
1781 GPRJRSuperclasses, 1,
1782 nullptr
1783 };
1784
1785 extern const TargetRegisterClass GPRNoR0R1RegClass = {
1786 &LoongArchMCRegisterClasses[GPRNoR0R1RegClassID],
1787 GPRNoR0R1SubClassMask,
1788 SuperRegIdxSeqs + 1,
1789 LaneBitmask(0x0000000000000001),
1790 0,
1791 false,
1792 0x00, /* TSFlags */
1793 false, /* HasDisjunctSubRegs */
1794 false, /* CoveredBySubRegs */
1795 GPRNoR0R1Superclasses, 2,
1796 nullptr
1797 };
1798
1799 extern const TargetRegisterClass GPRTRegClass = {
1800 &LoongArchMCRegisterClasses[GPRTRegClassID],
1801 GPRTSubClassMask,
1802 SuperRegIdxSeqs + 1,
1803 LaneBitmask(0x0000000000000001),
1804 0,
1805 false,
1806 0x00, /* TSFlags */
1807 false, /* HasDisjunctSubRegs */
1808 false, /* CoveredBySubRegs */
1809 GPRTSuperclasses, 3,
1810 nullptr
1811 };
1812
1813 extern const TargetRegisterClass CFRRegClass = {
1814 &LoongArchMCRegisterClasses[CFRRegClassID],
1815 CFRSubClassMask,
1816 SuperRegIdxSeqs + 1,
1817 LaneBitmask(0x0000000000000001),
1818 0,
1819 false,
1820 0x00, /* TSFlags */
1821 false, /* HasDisjunctSubRegs */
1822 false, /* CoveredBySubRegs */
1823 nullptr, 0,
1824 nullptr
1825 };
1826
1827 extern const TargetRegisterClass FCSRRegClass = {
1828 &LoongArchMCRegisterClasses[FCSRRegClassID],
1829 FCSRSubClassMask,
1830 SuperRegIdxSeqs + 1,
1831 LaneBitmask(0x0000000000000001),
1832 0,
1833 false,
1834 0x00, /* TSFlags */
1835 false, /* HasDisjunctSubRegs */
1836 false, /* CoveredBySubRegs */
1837 nullptr, 0,
1838 nullptr
1839 };
1840
1841 extern const TargetRegisterClass SCRRegClass = {
1842 &LoongArchMCRegisterClasses[SCRRegClassID],
1843 SCRSubClassMask,
1844 SuperRegIdxSeqs + 1,
1845 LaneBitmask(0x0000000000000001),
1846 0,
1847 false,
1848 0x00, /* TSFlags */
1849 false, /* HasDisjunctSubRegs */
1850 false, /* CoveredBySubRegs */
1851 nullptr, 0,
1852 nullptr
1853 };
1854
1855 extern const TargetRegisterClass FPR64RegClass = {
1856 &LoongArchMCRegisterClasses[FPR64RegClassID],
1857 FPR64SubClassMask,
1858 SuperRegIdxSeqs + 2,
1859 LaneBitmask(0x0000000000000001),
1860 0,
1861 false,
1862 0x00, /* TSFlags */
1863 false, /* HasDisjunctSubRegs */
1864 false, /* CoveredBySubRegs */
1865 nullptr, 0,
1866 nullptr
1867 };
1868
1869 extern const TargetRegisterClass LSX128RegClass = {
1870 &LoongArchMCRegisterClasses[LSX128RegClassID],
1871 LSX128SubClassMask,
1872 SuperRegIdxSeqs + 4,
1873 LaneBitmask(0x0000000000000001),
1874 0,
1875 false,
1876 0x00, /* TSFlags */
1877 false, /* HasDisjunctSubRegs */
1878 false, /* CoveredBySubRegs */
1879 nullptr, 0,
1880 nullptr
1881 };
1882
1883 extern const TargetRegisterClass LASX256RegClass = {
1884 &LoongArchMCRegisterClasses[LASX256RegClassID],
1885 LASX256SubClassMask,
1886 SuperRegIdxSeqs + 1,
1887 LaneBitmask(0x0000000000000001),
1888 0,
1889 false,
1890 0x00, /* TSFlags */
1891 false, /* HasDisjunctSubRegs */
1892 false, /* CoveredBySubRegs */
1893 nullptr, 0,
1894 nullptr
1895 };
1896
1897} // end namespace LoongArch
1898
1899namespace {
1900 const TargetRegisterClass *const RegisterClasses[] = {
1901 &LoongArch::FPR32RegClass,
1902 &LoongArch::GPRRegClass,
1903 &LoongArch::GPRJRRegClass,
1904 &LoongArch::GPRNoR0R1RegClass,
1905 &LoongArch::GPRTRegClass,
1906 &LoongArch::CFRRegClass,
1907 &LoongArch::FCSRRegClass,
1908 &LoongArch::SCRRegClass,
1909 &LoongArch::FPR64RegClass,
1910 &LoongArch::LSX128RegClass,
1911 &LoongArch::LASX256RegClass,
1912 };
1913} // end anonymous namespace
1914
1915static const uint8_t CostPerUseTable[] = {
19160, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
1917
1918
1919static const bool InAllocatableClassTable[] = {
1920false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, };
1921
1922
1923static const TargetRegisterInfoDesc LoongArchRegInfoDesc = { // Extra Descriptors
1924CostPerUseTable, 1, InAllocatableClassTable};
1925
1926unsigned LoongArchGenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
1927 static const uint8_t Rows[1][3] = {
1928 { LoongArch::sub_32, LoongArch::sub_64, 0, },
1929 };
1930
1931 --IdxA; assert(IdxA < 3); (void) IdxA;
1932 --IdxB; assert(IdxB < 3);
1933 return Rows[0][IdxB];
1934}
1935
1936unsigned LoongArchGenRegisterInfo::reverseComposeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
1937 static const uint8_t Table[3][3] = {
1938 { LoongArch::sub_32, LoongArch::sub_64, 0, },
1939 { LoongArch::sub_32, LoongArch::sub_64, 0, },
1940 { LoongArch::sub_32, LoongArch::sub_64, 0, },
1941 };
1942
1943 --IdxA; assert(IdxA < 3);
1944 --IdxB; assert(IdxB < 3);
1945 return Table[IdxA][IdxB];
1946 }
1947
1948 struct MaskRolOp {
1949 LaneBitmask Mask;
1950 uint8_t RotateLeft;
1951 };
1952 static const MaskRolOp LaneMaskComposeSequences[] = {
1953 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 0 }, { LaneBitmask::getNone(), 0 } // Sequence 0
1954 };
1955 static const uint8_t CompositeSequences[] = {
1956 0, // to sub_32
1957 0, // to sub_64
1958 0 // to sub_128
1959 };
1960
1961LaneBitmask LoongArchGenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
1962 --IdxA; assert(IdxA < 3 && "Subregister index out of bounds");
1963 LaneBitmask Result;
1964 for (const MaskRolOp *Ops =
1965 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
1966 Ops->Mask.any(); ++Ops) {
1967 LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
1968 if (unsigned S = Ops->RotateLeft)
1969 Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));
1970 else
1971 Result |= LaneBitmask(M);
1972 }
1973 return Result;
1974}
1975
1976LaneBitmask LoongArchGenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
1977 LaneMask &= getSubRegIndexLaneMask(IdxA);
1978 --IdxA; assert(IdxA < 3 && "Subregister index out of bounds");
1979 LaneBitmask Result;
1980 for (const MaskRolOp *Ops =
1981 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
1982 Ops->Mask.any(); ++Ops) {
1983 LaneBitmask::Type M = LaneMask.getAsInteger();
1984 if (unsigned S = Ops->RotateLeft)
1985 Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));
1986 else
1987 Result |= LaneBitmask(M);
1988 }
1989 return Result;
1990}
1991
1992const TargetRegisterClass *LoongArchGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
1993 static const uint8_t Table[11][3] = {
1994 { // FPR32
1995 0, // sub_32
1996 0, // sub_64
1997 0, // sub_128
1998 },
1999 { // GPR
2000 0, // sub_32
2001 0, // sub_64
2002 0, // sub_128
2003 },
2004 { // GPRJR
2005 0, // sub_32
2006 0, // sub_64
2007 0, // sub_128
2008 },
2009 { // GPRNoR0R1
2010 0, // sub_32
2011 0, // sub_64
2012 0, // sub_128
2013 },
2014 { // GPRT
2015 0, // sub_32
2016 0, // sub_64
2017 0, // sub_128
2018 },
2019 { // CFR
2020 0, // sub_32
2021 0, // sub_64
2022 0, // sub_128
2023 },
2024 { // FCSR
2025 0, // sub_32
2026 0, // sub_64
2027 0, // sub_128
2028 },
2029 { // SCR
2030 0, // sub_32
2031 0, // sub_64
2032 0, // sub_128
2033 },
2034 { // FPR64
2035 9, // sub_32 -> FPR64
2036 0, // sub_64
2037 0, // sub_128
2038 },
2039 { // LSX128
2040 10, // sub_32 -> LSX128
2041 10, // sub_64 -> LSX128
2042 0, // sub_128
2043 },
2044 { // LASX256
2045 11, // sub_32 -> LASX256
2046 11, // sub_64 -> LASX256
2047 11, // sub_128 -> LASX256
2048 },
2049 };
2050 assert(RC && "Missing regclass");
2051 if (!Idx) return RC;
2052 --Idx;
2053 assert(Idx < 3 && "Bad subreg");
2054 unsigned TV = Table[RC->getID()][Idx];
2055 return TV ? getRegClass(TV - 1) : nullptr;
2056}
2057
2058const TargetRegisterClass *LoongArchGenRegisterInfo::getSubRegisterClass(const TargetRegisterClass *RC, unsigned Idx) const {
2059 static const uint8_t Table[11][3] = {
2060 { // FPR32
2061 0, // FPR32:sub_32
2062 0, // FPR32:sub_64
2063 0, // FPR32:sub_128
2064 },
2065 { // GPR
2066 0, // GPR:sub_32
2067 0, // GPR:sub_64
2068 0, // GPR:sub_128
2069 },
2070 { // GPRJR
2071 0, // GPRJR:sub_32
2072 0, // GPRJR:sub_64
2073 0, // GPRJR:sub_128
2074 },
2075 { // GPRNoR0R1
2076 0, // GPRNoR0R1:sub_32
2077 0, // GPRNoR0R1:sub_64
2078 0, // GPRNoR0R1:sub_128
2079 },
2080 { // GPRT
2081 0, // GPRT:sub_32
2082 0, // GPRT:sub_64
2083 0, // GPRT:sub_128
2084 },
2085 { // CFR
2086 0, // CFR:sub_32
2087 0, // CFR:sub_64
2088 0, // CFR:sub_128
2089 },
2090 { // FCSR
2091 0, // FCSR:sub_32
2092 0, // FCSR:sub_64
2093 0, // FCSR:sub_128
2094 },
2095 { // SCR
2096 0, // SCR:sub_32
2097 0, // SCR:sub_64
2098 0, // SCR:sub_128
2099 },
2100 { // FPR64
2101 1, // FPR64:sub_32 -> FPR32
2102 0, // FPR64:sub_64
2103 0, // FPR64:sub_128
2104 },
2105 { // LSX128
2106 1, // LSX128:sub_32 -> FPR32
2107 9, // LSX128:sub_64 -> FPR64
2108 0, // LSX128:sub_128
2109 },
2110 { // LASX256
2111 1, // LASX256:sub_32 -> FPR32
2112 9, // LASX256:sub_64 -> FPR64
2113 10, // LASX256:sub_128 -> LSX128
2114 },
2115 };
2116 assert(RC && "Missing regclass");
2117 if (!Idx) return RC;
2118 --Idx;
2119 assert(Idx < 3 && "Bad subreg");
2120 unsigned TV = Table[RC->getID()][Idx];
2121 return TV ? getRegClass(TV - 1) : nullptr;
2122}
2123
2124/// Get the weight in units of pressure for this register class.
2125const RegClassWeight &LoongArchGenRegisterInfo::
2126getRegClassWeight(const TargetRegisterClass *RC) const {
2127 static const RegClassWeight RCWeightTable[] = {
2128 {1, 32}, // FPR32
2129 {1, 32}, // GPR
2130 {1, 31}, // GPRJR
2131 {1, 30}, // GPRNoR0R1
2132 {1, 17}, // GPRT
2133 {1, 8}, // CFR
2134 {0, 0}, // FCSR
2135 {0, 0}, // SCR
2136 {1, 32}, // FPR64
2137 {1, 32}, // LSX128
2138 {1, 32}, // LASX256
2139 };
2140 return RCWeightTable[RC->getID()];
2141}
2142
2143/// Get the weight in units of pressure for this register unit.
2144unsigned LoongArchGenRegisterInfo::
2145getRegUnitWeight(unsigned RegUnit) const {
2146 assert(RegUnit < 80 && "invalid register unit");
2147 // All register units have unit weight.
2148 return 1;
2149}
2150
2151
2152// Get the number of dimensions of register pressure.
2153unsigned LoongArchGenRegisterInfo::getNumRegPressureSets() const {
2154 return 4;
2155}
2156
2157// Get the name of this register unit pressure set.
2158const char *LoongArchGenRegisterInfo::
2159getRegPressureSetName(unsigned Idx) const {
2160 static const char *PressureNameTable[] = {
2161 "CFR",
2162 "GPRT",
2163 "FPR32",
2164 "GPR",
2165 };
2166 return PressureNameTable[Idx];
2167}
2168
2169// Get the register unit pressure limit for this dimension.
2170// This limit must be adjusted dynamically for reserved registers.
2171unsigned LoongArchGenRegisterInfo::
2172getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
2173 static const uint8_t PressureLimitTable[] = {
2174 8, // 0: CFR
2175 17, // 1: GPRT
2176 32, // 2: FPR32
2177 32, // 3: GPR
2178 };
2179 return PressureLimitTable[Idx];
2180}
2181
2182/// Table of pressure sets per register class or unit.
2183static const int RCSetsTable[] = {
2184 /* 0 */ 0, -1,
2185 /* 2 */ 2, -1,
2186 /* 4 */ 1, 3, -1,
2187};
2188
2189/// Get the dimensions of register pressure impacted by this register class.
2190/// Returns a -1 terminated array of pressure set IDs
2191const int *LoongArchGenRegisterInfo::
2192getRegClassPressureSets(const TargetRegisterClass *RC) const {
2193 static const uint8_t RCSetStartTable[] = {
2194 2,5,5,5,4,0,1,1,2,2,2,};
2195 return &RCSetsTable[RCSetStartTable[RC->getID()]];
2196}
2197
2198/// Get the dimensions of register pressure impacted by this register unit.
2199/// Returns a -1 terminated array of pressure set IDs
2200const int *LoongArchGenRegisterInfo::
2201getRegUnitPressureSets(unsigned RegUnit) const {
2202 assert(RegUnit < 80 && "invalid register unit");
2203 static const uint8_t RUSetStartTable[] = {
2204 2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,0,0,0,0,0,0,0,0,1,1,1,1,5,5,5,5,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,5,5,5,5,5,5,5,5,5,5,5,1,1,1,1,};
2205 return &RCSetsTable[RUSetStartTable[RegUnit]];
2206}
2207
2208extern const MCRegisterDesc LoongArchRegDesc[];
2209extern const int16_t LoongArchRegDiffLists[];
2210extern const LaneBitmask LoongArchLaneMaskLists[];
2211extern const char LoongArchRegStrings[];
2212extern const char LoongArchRegClassStrings[];
2213extern const MCPhysReg LoongArchRegUnitRoots[][2];
2214extern const uint16_t LoongArchSubRegIdxLists[];
2215extern const uint16_t LoongArchRegEncodingTable[];
2216// LoongArch Dwarf<->LLVM register mappings.
2217extern const MCRegisterInfo::DwarfLLVMRegPair LoongArchDwarfFlavour0Dwarf2L[];
2218extern const unsigned LoongArchDwarfFlavour0Dwarf2LSize;
2219
2220extern const MCRegisterInfo::DwarfLLVMRegPair LoongArchEHFlavour0Dwarf2L[];
2221extern const unsigned LoongArchEHFlavour0Dwarf2LSize;
2222
2223extern const MCRegisterInfo::DwarfLLVMRegPair LoongArchDwarfFlavour0L2Dwarf[];
2224extern const unsigned LoongArchDwarfFlavour0L2DwarfSize;
2225
2226extern const MCRegisterInfo::DwarfLLVMRegPair LoongArchEHFlavour0L2Dwarf[];
2227extern const unsigned LoongArchEHFlavour0L2DwarfSize;
2228
2229LoongArchGenRegisterInfo::
2230LoongArchGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
2231 unsigned PC, unsigned HwMode)
2232 : TargetRegisterInfo(&LoongArchRegInfoDesc, RegisterClasses, RegisterClasses+11,
2233 SubRegIndexNameTable, SubRegIdxRangeTable, SubRegIndexLaneMaskTable,
2234 LaneBitmask(0xFFFFFFFFFFFFFFFE), RegClassInfos, VTLists, HwMode) {
2235 InitMCRegisterInfo(LoongArchRegDesc, 177, RA, PC,
2236 LoongArchMCRegisterClasses, 11,
2237 LoongArchRegUnitRoots,
2238 80,
2239 LoongArchRegDiffLists,
2240 LoongArchLaneMaskLists,
2241 LoongArchRegStrings,
2242 LoongArchRegClassStrings,
2243 LoongArchSubRegIdxLists,
2244 4,
2245 LoongArchRegEncodingTable);
2246
2247 switch (DwarfFlavour) {
2248 default:
2249 llvm_unreachable("Unknown DWARF flavour");
2250 case 0:
2251 mapDwarfRegsToLLVMRegs(LoongArchDwarfFlavour0Dwarf2L, LoongArchDwarfFlavour0Dwarf2LSize, false);
2252 break;
2253 }
2254 switch (EHFlavour) {
2255 default:
2256 llvm_unreachable("Unknown DWARF flavour");
2257 case 0:
2258 mapDwarfRegsToLLVMRegs(LoongArchEHFlavour0Dwarf2L, LoongArchEHFlavour0Dwarf2LSize, true);
2259 break;
2260 }
2261 switch (DwarfFlavour) {
2262 default:
2263 llvm_unreachable("Unknown DWARF flavour");
2264 case 0:
2265 mapLLVMRegsToDwarfRegs(LoongArchDwarfFlavour0L2Dwarf, LoongArchDwarfFlavour0L2DwarfSize, false);
2266 break;
2267 }
2268 switch (EHFlavour) {
2269 default:
2270 llvm_unreachable("Unknown DWARF flavour");
2271 case 0:
2272 mapLLVMRegsToDwarfRegs(LoongArchEHFlavour0L2Dwarf, LoongArchEHFlavour0L2DwarfSize, true);
2273 break;
2274 }
2275}
2276
2277static const MCPhysReg CSR_ILP32D_LP64D_SaveList[] = { LoongArch::R1, LoongArch::R22, LoongArch::R23, LoongArch::R24, LoongArch::R25, LoongArch::R26, LoongArch::R27, LoongArch::R28, LoongArch::R29, LoongArch::R30, LoongArch::R31, LoongArch::F24_64, LoongArch::F25_64, LoongArch::F26_64, LoongArch::F27_64, LoongArch::F28_64, LoongArch::F29_64, LoongArch::F30_64, LoongArch::F31_64, 0 };
2278static const uint32_t CSR_ILP32D_LP64D_RegMask[] = { 0xfe000000, 0x00006001, 0x00001ff8, 0x00000000, 0x00000000, 0x0001fe00, };
2279static const MCPhysReg CSR_ILP32F_LP64F_SaveList[] = { LoongArch::R1, LoongArch::R22, LoongArch::R23, LoongArch::R24, LoongArch::R25, LoongArch::R26, LoongArch::R27, LoongArch::R28, LoongArch::R29, LoongArch::R30, LoongArch::R31, LoongArch::F24, LoongArch::F25, LoongArch::F26, LoongArch::F27, LoongArch::F28, LoongArch::F29, LoongArch::F30, LoongArch::F31, 0 };
2280static const uint32_t CSR_ILP32F_LP64F_RegMask[] = { 0xfe000000, 0x00006001, 0x00001ff8, 0x00000000, 0x00000000, 0x00000000, };
2281static const MCPhysReg CSR_ILP32S_LP64S_SaveList[] = { LoongArch::R1, LoongArch::R22, LoongArch::R23, LoongArch::R24, LoongArch::R25, LoongArch::R26, LoongArch::R27, LoongArch::R28, LoongArch::R29, LoongArch::R30, LoongArch::R31, 0 };
2282static const uint32_t CSR_ILP32S_LP64S_RegMask[] = { 0x00000000, 0x00006000, 0x00001ff8, 0x00000000, 0x00000000, 0x00000000, };
2283static const MCPhysReg CSR_NoRegs_SaveList[] = { 0 };
2284static const uint32_t CSR_NoRegs_RegMask[] = { 0x00000000, 0x00002000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
2285
2286
2287ArrayRef<const uint32_t *> LoongArchGenRegisterInfo::getRegMasks() const {
2288 static const uint32_t *const Masks[] = {
2289 CSR_ILP32D_LP64D_RegMask,
2290 CSR_ILP32F_LP64F_RegMask,
2291 CSR_ILP32S_LP64S_RegMask,
2292 CSR_NoRegs_RegMask,
2293 };
2294 return ArrayRef(Masks);
2295}
2296
2297bool LoongArchGenRegisterInfo::
2298isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
2299 return
2300 false;
2301}
2302
2303bool LoongArchGenRegisterInfo::
2304isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const {
2305 return
2306 false;
2307}
2308
2309bool LoongArchGenRegisterInfo::
2310isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
2311 return
2312 false;
2313}
2314
2315bool LoongArchGenRegisterInfo::
2316isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
2317 return
2318 false;
2319}
2320
2321bool LoongArchGenRegisterInfo::
2322isConstantPhysReg(MCRegister PhysReg) const {
2323 return
2324 PhysReg == LoongArch::R0 ||
2325 false;
2326}
2327
2328ArrayRef<const char *> LoongArchGenRegisterInfo::getRegMaskNames() const {
2329 static const char *Names[] = {
2330 "CSR_ILP32D_LP64D",
2331 "CSR_ILP32F_LP64F",
2332 "CSR_ILP32S_LP64S",
2333 "CSR_NoRegs",
2334 };
2335 return ArrayRef(Names);
2336}
2337
2338const LoongArchFrameLowering *
2339LoongArchGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
2340 return static_cast<const LoongArchFrameLowering *>(
2341 MF.getSubtarget().getFrameLowering());
2342}
2343
2344} // end namespace llvm
2345
2346#endif // GET_REGINFO_TARGET_DESC
2347
2348