1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Subtarget Enumeration Source Fragment *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9
10#ifdef GET_SUBTARGETINFO_ENUM
11#undef GET_SUBTARGETINFO_ENUM
12
13namespace llvm {
14namespace LoongArch {
15enum {
16 Feature32Bit = 0,
17 Feature32S = 1,
18 Feature64Bit = 2,
19 FeatureBasicD = 3,
20 FeatureBasicF = 4,
21 FeatureDiv32 = 5,
22 FeatureExtLASX = 6,
23 FeatureExtLBT = 7,
24 FeatureExtLSX = 8,
25 FeatureExtLVZ = 9,
26 FeatureFrecipe = 10,
27 FeatureLAMCAS = 11,
28 FeatureLAM_BH = 12,
29 FeatureLD_SEQ_SA = 13,
30 FeatureRelax = 14,
31 FeatureSCQ = 15,
32 FeatureUAL = 16,
33 LaGlobalWithAbs = 17,
34 LaGlobalWithPcrel = 18,
35 LaLocalWithAbs = 19,
36 TunePreferWInst = 20,
37 NumSubtargetFeatures = 21
38};
39} // end namespace LoongArch
40} // end namespace llvm
41
42#endif // GET_SUBTARGETINFO_ENUM
43
44
45#ifdef GET_SUBTARGETINFO_MACRO
46GET_SUBTARGETINFO_MACRO(Has32S, false, has32S)
47GET_SUBTARGETINFO_MACRO(HasBasicD, false, hasBasicD)
48GET_SUBTARGETINFO_MACRO(HasBasicF, false, hasBasicF)
49GET_SUBTARGETINFO_MACRO(HasDiv32, false, hasDiv32)
50GET_SUBTARGETINFO_MACRO(HasExtLASX, false, hasExtLASX)
51GET_SUBTARGETINFO_MACRO(HasExtLBT, false, hasExtLBT)
52GET_SUBTARGETINFO_MACRO(HasExtLSX, false, hasExtLSX)
53GET_SUBTARGETINFO_MACRO(HasExtLVZ, false, hasExtLVZ)
54GET_SUBTARGETINFO_MACRO(HasFrecipe, false, hasFrecipe)
55GET_SUBTARGETINFO_MACRO(HasLA32, false, hasLA32)
56GET_SUBTARGETINFO_MACRO(HasLA64, false, hasLA64)
57GET_SUBTARGETINFO_MACRO(HasLAMCAS, false, hasLAMCAS)
58GET_SUBTARGETINFO_MACRO(HasLAM_BH, false, hasLAM_BH)
59GET_SUBTARGETINFO_MACRO(HasLD_SEQ_SA, false, hasLD_SEQ_SA)
60GET_SUBTARGETINFO_MACRO(HasLaGlobalWithAbs, false, hasLaGlobalWithAbs)
61GET_SUBTARGETINFO_MACRO(HasLaGlobalWithPcrel, false, hasLaGlobalWithPcrel)
62GET_SUBTARGETINFO_MACRO(HasLaLocalWithAbs, false, hasLaLocalWithAbs)
63GET_SUBTARGETINFO_MACRO(HasLinkerRelax, false, hasLinkerRelax)
64GET_SUBTARGETINFO_MACRO(HasSCQ, false, hasSCQ)
65GET_SUBTARGETINFO_MACRO(HasUAL, false, hasUAL)
66GET_SUBTARGETINFO_MACRO(PreferWInst, false, preferWInst)
67#undef GET_SUBTARGETINFO_MACRO
68#endif // GET_SUBTARGETINFO_MACRO
69
70
71#ifdef GET_SUBTARGETINFO_MC_DESC
72#undef GET_SUBTARGETINFO_MC_DESC
73
74namespace llvm {
75// Sorted (by key) array of values for CPU features.
76extern const llvm::SubtargetFeatureKV LoongArchFeatureKV[] = {
77 { "32bit", "LA32 Basic Integer and Privilege Instruction Set", LoongArch::Feature32Bit, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
78 { "32s", "LA32 Standard Basic Instruction Extension", LoongArch::Feature32S, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
79 { "64bit", "LA64 Basic Integer and Privilege Instruction Set", LoongArch::Feature64Bit, { { { 0x2ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
80 { "d", "'D' (Double-Precision Floating-Point)", LoongArch::FeatureBasicD, { { { 0x10ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
81 { "div32", "Assume div.w[u] and mod.w[u] can handle inputs that are not sign-extended", LoongArch::FeatureDiv32, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
82 { "f", "'F' (Single-Precision Floating-Point)", LoongArch::FeatureBasicF, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
83 { "frecipe", "Support frecipe.{s/d} and frsqrte.{s/d} instructions", LoongArch::FeatureFrecipe, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
84 { "la-global-with-abs", "Expand la.global as la.abs", LoongArch::LaGlobalWithAbs, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
85 { "la-global-with-pcrel", "Expand la.global as la.pcrel", LoongArch::LaGlobalWithPcrel, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
86 { "la-local-with-abs", "Expand la.local as la.abs", LoongArch::LaLocalWithAbs, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
87 { "lam-bh", "Support amswap[_db].{b/h} and amadd[_db].{b/h} instructions", LoongArch::FeatureLAM_BH, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
88 { "lamcas", "Support amcas[_db].{b/h/w/d}", LoongArch::FeatureLAMCAS, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
89 { "lasx", "'LASX' (Loongson Advanced SIMD Extension)", LoongArch::FeatureExtLASX, { { { 0x100ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
90 { "lbt", "'LBT' (Loongson Binary Translation Extension)", LoongArch::FeatureExtLBT, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
91 { "ld-seq-sa", "Don't use a same-address load-load barrier (dbar 0x700)", LoongArch::FeatureLD_SEQ_SA, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
92 { "lsx", "'LSX' (Loongson SIMD Extension)", LoongArch::FeatureExtLSX, { { { 0x8ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
93 { "lvz", "'LVZ' (Loongson Virtualization Extension)", LoongArch::FeatureExtLVZ, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
94 { "prefer-w-inst", "Prefer instructions with W suffix", LoongArch::TunePreferWInst, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
95 { "relax", "Enable Linker relaxation", LoongArch::FeatureRelax, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
96 { "scq", "Support sc.q instruction", LoongArch::FeatureSCQ, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
97 { "ual", "Allow memory accesses to be unaligned", LoongArch::FeatureUAL, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
98};
99
100#ifdef DBGFIELD
101#error "<target>GenSubtargetInfo.inc requires a DBGFIELD macro"
102#endif
103#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
104#define DBGFIELD(x) x,
105#define DBGVAL_OR_NULLPTR(x) x
106#else
107#define DBGFIELD(x)
108#define DBGVAL_OR_NULLPTR(x) nullptr
109#endif
110
111// ===============================================================
112// Data tables for the new per-operand machine model.
113
114// {ProcResourceIdx, ReleaseAtCycle, AcquireAtCycle}
115extern const llvm::MCWriteProcResEntry LoongArchWriteProcResTable[] = {
116 { 0, 0, 0 }, // Invalid
117}; // LoongArchWriteProcResTable
118
119// {Cycles, WriteResourceID}
120extern const llvm::MCWriteLatencyEntry LoongArchWriteLatencyTable[] = {
121 { 0, 0}, // Invalid
122}; // LoongArchWriteLatencyTable
123
124// {UseIdx, WriteResourceID, Cycles}
125extern const llvm::MCReadAdvanceEntry LoongArchReadAdvanceTable[] = {
126 {0, 0, 0}, // Invalid
127}; // LoongArchReadAdvanceTable
128
129#ifdef __GNUC__
130#pragma GCC diagnostic push
131#pragma GCC diagnostic ignored "-Woverlength-strings"
132#endif
133static constexpr char LoongArchSchedClassNamesStorage[] =
134 "\0"
135 "InvalidSchedClass\0"
136 ;
137#ifdef __GNUC__
138#pragma GCC diagnostic pop
139#endif
140
141static constexpr llvm::StringTable LoongArchSchedClassNames =
142 LoongArchSchedClassNamesStorage;
143
144static const llvm::MCSchedModel NoSchedModel = {
145 MCSchedModel::DefaultIssueWidth,
146 MCSchedModel::DefaultMicroOpBufferSize,
147 MCSchedModel::DefaultLoopMicroOpBufferSize,
148 MCSchedModel::DefaultLoadLatency,
149 MCSchedModel::DefaultHighLatency,
150 MCSchedModel::DefaultMispredictPenalty,
151 false, // PostRAScheduler
152 false, // CompleteModel
153 false, // EnableIntervals
154 0, // Processor ID
155 nullptr, nullptr, 0, 0, // No instruction-level machine model.
156 DBGVAL_OR_NULLPTR(&LoongArchSchedClassNames), // SchedClassNames
157 nullptr, // No Itinerary
158 nullptr // No extra processor descriptor
159};
160
161#undef DBGFIELD
162
163#undef DBGVAL_OR_NULLPTR
164
165// Sorted (by key) array of values for CPU subtype.
166extern const llvm::SubtargetSubTypeKV LoongArchSubTypeKV[] = {
167 { "generic", { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
168 { "generic-la32", { { { 0x1ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
169 { "generic-la64", { { { 0x10104ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
170 { "la464", { { { 0x102c4ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
171 { "la664", { { { 0x1bee4ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
172 { "loongarch64", { { { 0x1000cULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
173};
174
175// Sorted array of names of CPU subtypes, including aliases.
176extern const llvm::StringRef LoongArchNames[] = {
177"generic",
178"generic-la32",
179"generic-la64",
180"la464",
181"la664",
182"loongarch64"};
183
184namespace LoongArch_MC {
185unsigned resolveVariantSchedClassImpl(unsigned SchedClass,
186 const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) {
187 // Don't know how to resolve this scheduling class.
188 return 0;
189}
190} // end namespace LoongArch_MC
191
192struct LoongArchGenMCSubtargetInfo : public MCSubtargetInfo {
193 LoongArchGenMCSubtargetInfo(const Triple &TT,
194 StringRef CPU, StringRef TuneCPU, StringRef FS,
195 ArrayRef<StringRef> PN,
196 ArrayRef<SubtargetFeatureKV> PF,
197 ArrayRef<SubtargetSubTypeKV> PD,
198 const MCWriteProcResEntry *WPR,
199 const MCWriteLatencyEntry *WL,
200 const MCReadAdvanceEntry *RA, const InstrStage *IS,
201 const unsigned *OC, const unsigned *FP) :
202 MCSubtargetInfo(TT, CPU, TuneCPU, FS, PN, PF, PD,
203 WPR, WL, RA, IS, OC, FP) { }
204
205 unsigned resolveVariantSchedClass(unsigned SchedClass,
206 const MCInst *MI, const MCInstrInfo *MCII,
207 unsigned CPUID) const override {
208 return LoongArch_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, CPUID);
209 }
210 unsigned getHwModeSet() const override;
211 unsigned getHwMode(enum HwModeType type = HwMode_Default) const override;
212};
213unsigned LoongArchGenMCSubtargetInfo::getHwModeSet() const {
214 // Collect HwModes and store them as a bit set.
215 unsigned Modes = 0;
216 if (checkFeatures("+64bit")) Modes |= (1 << 0);
217 return Modes;
218}
219unsigned LoongArchGenMCSubtargetInfo::getHwMode(enum HwModeType type) const {
220 unsigned Modes = getHwModeSet();
221
222 if (!Modes)
223 return Modes;
224
225 switch (type) {
226 case HwMode_Default:
227 return llvm::countr_zero(Modes) + 1;
228 case HwMode_ValueType:
229 Modes &= 1;
230 if (!Modes)
231 return Modes;
232 if (!llvm::has_single_bit<unsigned>(Modes))
233 llvm_unreachable("Two or more HwModes for ValueType were found!");
234 return llvm::countr_zero(Modes) + 1;
235 case HwMode_RegInfo:
236 Modes &= 1;
237 if (!Modes)
238 return Modes;
239 if (!llvm::has_single_bit<unsigned>(Modes))
240 llvm_unreachable("Two or more HwModes for RegInfo were found!");
241 return llvm::countr_zero(Modes) + 1;
242 case HwMode_EncodingInfo:
243 Modes &= 0;
244 if (!Modes)
245 return Modes;
246 if (!llvm::has_single_bit<unsigned>(Modes))
247 llvm_unreachable("Two or more HwModes for EncodingInfo were found!");
248 return llvm::countr_zero(Modes) + 1;
249 }
250 llvm_unreachable("unexpected HwModeType");
251 return 0; // should not get here
252}
253
254static inline MCSubtargetInfo *createLoongArchMCSubtargetInfoImpl(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS) {
255 return new LoongArchGenMCSubtargetInfo(TT, CPU, TuneCPU, FS, LoongArchNames, LoongArchFeatureKV, LoongArchSubTypeKV,
256 LoongArchWriteProcResTable, LoongArchWriteLatencyTable, LoongArchReadAdvanceTable,
257 nullptr, nullptr, nullptr);
258}
259
260} // end namespace llvm
261
262#endif // GET_SUBTARGETINFO_MC_DESC
263
264
265#ifdef GET_SUBTARGETINFO_TARGET_DESC
266#undef GET_SUBTARGETINFO_TARGET_DESC
267
268#include "llvm/ADT/BitmaskEnum.h"
269#include "llvm/Support/Debug.h"
270#include "llvm/Support/raw_ostream.h"
271
272// ParseSubtargetFeatures - Parses features string setting specified
273// subtarget options.
274void llvm::LoongArchSubtarget::ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS) {
275 LLVM_DEBUG(dbgs() << "\nFeatures:" << FS);
276 LLVM_DEBUG(dbgs() << "\nCPU:" << CPU);
277 LLVM_DEBUG(dbgs() << "\nTuneCPU:" << TuneCPU << "\n\n");
278 InitMCProcessorInfo(CPU, TuneCPU, FS);
279 const FeatureBitset &Bits = getFeatureBits();
280 if (Bits[LoongArch::Feature32Bit]) HasLA32 = true;
281 if (Bits[LoongArch::Feature32S]) Has32S = true;
282 if (Bits[LoongArch::Feature64Bit]) HasLA64 = true;
283 if (Bits[LoongArch::FeatureBasicD]) HasBasicD = true;
284 if (Bits[LoongArch::FeatureBasicF]) HasBasicF = true;
285 if (Bits[LoongArch::FeatureDiv32]) HasDiv32 = true;
286 if (Bits[LoongArch::FeatureExtLASX]) HasExtLASX = true;
287 if (Bits[LoongArch::FeatureExtLBT]) HasExtLBT = true;
288 if (Bits[LoongArch::FeatureExtLSX]) HasExtLSX = true;
289 if (Bits[LoongArch::FeatureExtLVZ]) HasExtLVZ = true;
290 if (Bits[LoongArch::FeatureFrecipe]) HasFrecipe = true;
291 if (Bits[LoongArch::FeatureLAMCAS]) HasLAMCAS = true;
292 if (Bits[LoongArch::FeatureLAM_BH]) HasLAM_BH = true;
293 if (Bits[LoongArch::FeatureLD_SEQ_SA]) HasLD_SEQ_SA = true;
294 if (Bits[LoongArch::FeatureRelax]) HasLinkerRelax = true;
295 if (Bits[LoongArch::FeatureSCQ]) HasSCQ = true;
296 if (Bits[LoongArch::FeatureUAL]) HasUAL = true;
297 if (Bits[LoongArch::LaGlobalWithAbs]) HasLaGlobalWithAbs = true;
298 if (Bits[LoongArch::LaGlobalWithPcrel]) HasLaGlobalWithPcrel = true;
299 if (Bits[LoongArch::LaLocalWithAbs]) HasLaLocalWithAbs = true;
300 if (Bits[LoongArch::TunePreferWInst]) PreferWInst = true;
301}
302#endif // GET_SUBTARGETINFO_TARGET_DESC
303
304
305#ifdef GET_SUBTARGETINFO_HEADER
306#undef GET_SUBTARGETINFO_HEADER
307
308namespace llvm {
309class DFAPacketizer;
310namespace LoongArch_MC {
311unsigned resolveVariantSchedClassImpl(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID);
312} // end namespace LoongArch_MC
313
314struct LoongArchGenSubtargetInfo : public TargetSubtargetInfo {
315 explicit LoongArchGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS);
316public:
317 unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const override;
318 unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const override;
319 DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID) const;
320 enum class LoongArchHwModeBits : unsigned {
321 DefaultMode = 0,
322 LA64 = (1 << 0),
323
324 LLVM_MARK_AS_BITMASK_ENUM(/*LargestValue=*/LA64),
325 };
326 unsigned getHwModeSet() const override;
327 unsigned getHwMode(enum HwModeType type = HwMode_Default) const override;
328};
329} // end namespace llvm
330
331#endif // GET_SUBTARGETINFO_HEADER
332
333
334#ifdef GET_SUBTARGETINFO_CTOR
335#undef GET_SUBTARGETINFO_CTOR
336
337#include "llvm/CodeGen/TargetSchedule.h"
338
339namespace llvm {
340extern const llvm::StringRef LoongArchNames[];
341extern const llvm::SubtargetFeatureKV LoongArchFeatureKV[];
342extern const llvm::SubtargetSubTypeKV LoongArchSubTypeKV[];
343extern const llvm::MCWriteProcResEntry LoongArchWriteProcResTable[];
344extern const llvm::MCWriteLatencyEntry LoongArchWriteLatencyTable[];
345extern const llvm::MCReadAdvanceEntry LoongArchReadAdvanceTable[];
346LoongArchGenSubtargetInfo::LoongArchGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS)
347 : TargetSubtargetInfo(TT, CPU, TuneCPU, FS, ArrayRef(LoongArchNames, 6), ArrayRef(LoongArchFeatureKV, 21), ArrayRef(LoongArchSubTypeKV, 6),
348 LoongArchWriteProcResTable, LoongArchWriteLatencyTable, LoongArchReadAdvanceTable,
349 nullptr, nullptr, nullptr) {}
350
351unsigned LoongArchGenSubtargetInfo
352::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {
353 report_fatal_error("Expected a variant SchedClass");
354} // LoongArchGenSubtargetInfo::resolveSchedClass
355
356unsigned LoongArchGenSubtargetInfo
357::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const {
358 return LoongArch_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, CPUID);
359} // LoongArchGenSubtargetInfo::resolveVariantSchedClass
360
361unsigned LoongArchGenSubtargetInfo::getHwModeSet() const {
362 // Collect HwModes and store them as a bit set.
363 unsigned Modes = 0;
364 if (checkFeatures("+64bit")) Modes |= (1 << 0);
365 return Modes;
366}
367unsigned LoongArchGenSubtargetInfo::getHwMode(enum HwModeType type) const {
368 unsigned Modes = getHwModeSet();
369
370 if (!Modes)
371 return Modes;
372
373 switch (type) {
374 case HwMode_Default:
375 return llvm::countr_zero(Modes) + 1;
376 case HwMode_ValueType:
377 Modes &= 1;
378 if (!Modes)
379 return Modes;
380 if (!llvm::has_single_bit<unsigned>(Modes))
381 llvm_unreachable("Two or more HwModes for ValueType were found!");
382 return llvm::countr_zero(Modes) + 1;
383 case HwMode_RegInfo:
384 Modes &= 1;
385 if (!Modes)
386 return Modes;
387 if (!llvm::has_single_bit<unsigned>(Modes))
388 llvm_unreachable("Two or more HwModes for RegInfo were found!");
389 return llvm::countr_zero(Modes) + 1;
390 case HwMode_EncodingInfo:
391 Modes &= 0;
392 if (!Modes)
393 return Modes;
394 if (!llvm::has_single_bit<unsigned>(Modes))
395 llvm_unreachable("Two or more HwModes for EncodingInfo were found!");
396 return llvm::countr_zero(Modes) + 1;
397 }
398 llvm_unreachable("unexpected HwModeType");
399 return 0; // should not get here
400}
401} // end namespace llvm
402
403#endif // GET_SUBTARGETINFO_CTOR
404
405
406#ifdef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
407#undef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
408
409#endif // GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
410
411
412#ifdef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
413#undef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
414
415#endif // GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
416
417