1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Assembly Matcher Source Fragment *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* From: MSP430.td *|
7|* *|
8\*===----------------------------------------------------------------------===*/
9
10
11#ifdef GET_ASSEMBLER_HEADER
12#undef GET_ASSEMBLER_HEADER
13 // This should be included into the middle of the declaration of
14 // your subclasses implementation of MCTargetAsmParser.
15 FeatureBitset ComputeAvailableFeatures(const FeatureBitset &FB) const;
16 void convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
17 const OperandVector &Operands);
18 void convertToMapAndConstraints(unsigned Kind,
19 const OperandVector &Operands) override;
20 unsigned MatchInstructionImpl(const OperandVector &Operands,
21 MCInst &Inst,
22 uint64_t &ErrorInfo,
23 FeatureBitset &MissingFeatures,
24 bool matchingInlineAsm,
25 unsigned VariantID = 0);
26 unsigned MatchInstructionImpl(const OperandVector &Operands,
27 MCInst &Inst,
28 uint64_t &ErrorInfo,
29 bool matchingInlineAsm,
30 unsigned VariantID = 0) {
31 FeatureBitset MissingFeatures;
32 return MatchInstructionImpl(Operands, Inst, ErrorInfo, MissingFeatures,
33 matchingInlineAsm, VariantID);
34 }
35
36#endif // GET_ASSEMBLER_HEADER
37
38
39#ifdef GET_OPERAND_DIAGNOSTIC_TYPES
40#undef GET_OPERAND_DIAGNOSTIC_TYPES
41
42#endif // GET_OPERAND_DIAGNOSTIC_TYPES
43
44
45#ifdef GET_REGISTER_MATCHER
46#undef GET_REGISTER_MATCHER
47
48// Bits for subtarget features that participate in instruction matching.
49enum SubtargetFeatureBits : uint8_t {
50};
51
52static MCRegister MatchRegisterName(StringRef Name) {
53 switch (Name.size()) {
54 default: break;
55 case 2: // 20 strings to match.
56 if (Name[0] != 'r')
57 break;
58 switch (Name[1]) {
59 default: break;
60 case '0': // 2 strings to match.
61 return MSP430::PC; // "r0"
62 case '1': // 2 strings to match.
63 return MSP430::SP; // "r1"
64 case '2': // 2 strings to match.
65 return MSP430::SR; // "r2"
66 case '3': // 2 strings to match.
67 return MSP430::CG; // "r3"
68 case '4': // 2 strings to match.
69 return MSP430::R4; // "r4"
70 case '5': // 2 strings to match.
71 return MSP430::R5; // "r5"
72 case '6': // 2 strings to match.
73 return MSP430::R6; // "r6"
74 case '7': // 2 strings to match.
75 return MSP430::R7; // "r7"
76 case '8': // 2 strings to match.
77 return MSP430::R8; // "r8"
78 case '9': // 2 strings to match.
79 return MSP430::R9; // "r9"
80 }
81 break;
82 case 3: // 12 strings to match.
83 if (memcmp(Name.data()+0, "r1", 2) != 0)
84 break;
85 switch (Name[2]) {
86 default: break;
87 case '0': // 2 strings to match.
88 return MSP430::R10; // "r10"
89 case '1': // 2 strings to match.
90 return MSP430::R11; // "r11"
91 case '2': // 2 strings to match.
92 return MSP430::R12; // "r12"
93 case '3': // 2 strings to match.
94 return MSP430::R13; // "r13"
95 case '4': // 2 strings to match.
96 return MSP430::R14; // "r14"
97 case '5': // 2 strings to match.
98 return MSP430::R15; // "r15"
99 }
100 break;
101 }
102 return MSP430::NoRegister;
103}
104
105static MCRegister MatchRegisterAltName(StringRef Name) {
106 switch (Name.size()) {
107 default: break;
108 case 2: // 10 strings to match.
109 switch (Name[0]) {
110 default: break;
111 case 'c': // 2 strings to match.
112 if (Name[1] != 'g')
113 break;
114 return MSP430::CG; // "cg"
115 case 'f': // 2 strings to match.
116 if (Name[1] != 'p')
117 break;
118 return MSP430::R4; // "fp"
119 case 'p': // 2 strings to match.
120 if (Name[1] != 'c')
121 break;
122 return MSP430::PC; // "pc"
123 case 's': // 4 strings to match.
124 switch (Name[1]) {
125 default: break;
126 case 'p': // 2 strings to match.
127 return MSP430::SP; // "sp"
128 case 'r': // 2 strings to match.
129 return MSP430::SR; // "sr"
130 }
131 break;
132 }
133 break;
134 }
135 return MSP430::NoRegister;
136}
137
138#endif // GET_REGISTER_MATCHER
139
140
141#ifdef GET_SUBTARGET_FEATURE_NAME
142#undef GET_SUBTARGET_FEATURE_NAME
143
144// User-level names for subtarget features that participate in
145// instruction matching.
146static const char *getSubtargetFeatureName(uint64_t Val) {
147 return "(unknown)";
148}
149
150#endif // GET_SUBTARGET_FEATURE_NAME
151
152
153#ifdef GET_MATCHER_IMPLEMENTATION
154#undef GET_MATCHER_IMPLEMENTATION
155
156enum {
157 Tie0_1_1,
158 Tie1_1_1,
159};
160
161static const uint8_t TiedAsmOperandTable[][3] = {
162 /* Tie0_1_1 */ { 0, 1, 1 },
163 /* Tie1_1_1 */ { 1, 1, 1 },
164};
165
166namespace {
167enum OperatorConversionKind {
168 CVT_Done,
169 CVT_Reg,
170 CVT_Tied,
171 CVT_95_Reg,
172 CVT_imm_95_0,
173 CVT_95_addMemOperands,
174 CVT_95_addImmOperands,
175 CVT_95_addRegOperands,
176 CVT_regSR,
177 CVT_imm_95_1,
178 CVT_imm_95_4,
179 CVT_imm_95_2,
180 CVT_imm_95_8,
181 CVT_imm_95__MINUS_1,
182 CVT_regCG,
183 CVT_NUM_CONVERTERS
184};
185
186enum InstructionConversionKind {
187 Convert__Reg1_0__Tie0_1_1__imm_95_0,
188 Convert__Mem2_0__imm_95_0,
189 Convert__Reg1_1__Tie0_1_1__Reg1_0,
190 Convert__Mem2_1__Reg1_0,
191 Convert__Reg1_1__Tie0_1_1__CGImm1_0,
192 Convert__Mem2_1__CGImm1_0,
193 Convert__Reg1_1__Tie0_1_1__Imm1_0,
194 Convert__Mem2_1__Imm1_0,
195 Convert__Reg1_1__Tie0_1_1__IndReg1_0,
196 Convert__Mem2_1__IndReg1_0,
197 Convert__Reg1_1__Tie0_1_1__Mem2_0,
198 Convert__Mem2_1__Mem2_0,
199 Convert__Reg1_1__PostIndReg1_0__Tie0_1_1__Tie1_1_1,
200 Convert__Mem2_1__PostIndReg1_0,
201 Convert__Reg1_1__Reg1_0,
202 Convert__Reg1_1__CGImm1_0,
203 Convert__Reg1_1__Imm1_0,
204 Convert__Reg1_1__IndReg1_0,
205 Convert__Reg1_1__Mem2_0,
206 Convert__Reg1_1__PostIndReg1_0,
207 Convert__Reg1_0,
208 Convert__Imm1_0,
209 Convert__Mem2_0,
210 Convert__IndReg1_0,
211 Convert__PostIndReg1_0,
212 Convert__Reg1_0__imm_95_0,
213 Convert__regSR__Tie0_1_1__imm_95_1,
214 Convert__regSR__Tie0_1_1__imm_95_4,
215 Convert__regSR__Tie0_1_1__imm_95_2,
216 Convert__Reg1_0__Tie0_1_1__imm_95_1,
217 Convert__Mem2_0__imm_95_1,
218 Convert__Reg1_0__Tie0_1_1__imm_95_2,
219 Convert__Mem2_0__imm_95_2,
220 Convert__regSR__Tie0_1_1__imm_95_8,
221 Convert__Reg1_0__Tie0_1_1__imm_95__MINUS_1,
222 Convert__Mem2_0__imm_95__MINUS_1,
223 Convert__Imm1_1__Imm1_0,
224 Convert__Reg1_1__PostIndReg1_0__Tie1_1_1,
225 Convert__regCG__imm_95_0,
226 Convert__CGImm1_0,
227 Convert_NoOperands,
228 Convert__Reg1_0__Tie0_1_1__Reg1_0,
229 Convert__Mem2_0__Mem2_0,
230 Convert__Reg1_0__Tie0_1_1,
231 CVT_NUM_SIGNATURES
232};
233
234} // end anonymous namespace
235
236static const uint8_t ConversionTable[CVT_NUM_SIGNATURES][9] = {
237 // Convert__Reg1_0__Tie0_1_1__imm_95_0
238 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_imm_95_0, 0, CVT_Done },
239 // Convert__Mem2_0__imm_95_0
240 { CVT_95_addMemOperands, 1, CVT_imm_95_0, 0, CVT_Done },
241 // Convert__Reg1_1__Tie0_1_1__Reg1_0
242 { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_Reg, 1, CVT_Done },
243 // Convert__Mem2_1__Reg1_0
244 { CVT_95_addMemOperands, 2, CVT_95_Reg, 1, CVT_Done },
245 // Convert__Reg1_1__Tie0_1_1__CGImm1_0
246 { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 1, CVT_Done },
247 // Convert__Mem2_1__CGImm1_0
248 { CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
249 // Convert__Reg1_1__Tie0_1_1__Imm1_0
250 { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 1, CVT_Done },
251 // Convert__Mem2_1__Imm1_0
252 { CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
253 // Convert__Reg1_1__Tie0_1_1__IndReg1_0
254 { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_addRegOperands, 1, CVT_Done },
255 // Convert__Mem2_1__IndReg1_0
256 { CVT_95_addMemOperands, 2, CVT_95_addRegOperands, 1, CVT_Done },
257 // Convert__Reg1_1__Tie0_1_1__Mem2_0
258 { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 1, CVT_Done },
259 // Convert__Mem2_1__Mem2_0
260 { CVT_95_addMemOperands, 2, CVT_95_addMemOperands, 1, CVT_Done },
261 // Convert__Reg1_1__PostIndReg1_0__Tie0_1_1__Tie1_1_1
262 { CVT_95_Reg, 2, CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_Tied, Tie1_1_1, CVT_Done },
263 // Convert__Mem2_1__PostIndReg1_0
264 { CVT_95_addMemOperands, 2, CVT_95_addRegOperands, 1, CVT_Done },
265 // Convert__Reg1_1__Reg1_0
266 { CVT_95_Reg, 2, CVT_95_Reg, 1, CVT_Done },
267 // Convert__Reg1_1__CGImm1_0
268 { CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
269 // Convert__Reg1_1__Imm1_0
270 { CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
271 // Convert__Reg1_1__IndReg1_0
272 { CVT_95_Reg, 2, CVT_95_addRegOperands, 1, CVT_Done },
273 // Convert__Reg1_1__Mem2_0
274 { CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_Done },
275 // Convert__Reg1_1__PostIndReg1_0
276 { CVT_95_Reg, 2, CVT_95_addRegOperands, 1, CVT_Done },
277 // Convert__Reg1_0
278 { CVT_95_Reg, 1, CVT_Done },
279 // Convert__Imm1_0
280 { CVT_95_addImmOperands, 1, CVT_Done },
281 // Convert__Mem2_0
282 { CVT_95_addMemOperands, 1, CVT_Done },
283 // Convert__IndReg1_0
284 { CVT_95_addRegOperands, 1, CVT_Done },
285 // Convert__PostIndReg1_0
286 { CVT_95_addRegOperands, 1, CVT_Done },
287 // Convert__Reg1_0__imm_95_0
288 { CVT_95_Reg, 1, CVT_imm_95_0, 0, CVT_Done },
289 // Convert__regSR__Tie0_1_1__imm_95_1
290 { CVT_regSR, 0, CVT_Tied, Tie0_1_1, CVT_imm_95_1, 0, CVT_Done },
291 // Convert__regSR__Tie0_1_1__imm_95_4
292 { CVT_regSR, 0, CVT_Tied, Tie0_1_1, CVT_imm_95_4, 0, CVT_Done },
293 // Convert__regSR__Tie0_1_1__imm_95_2
294 { CVT_regSR, 0, CVT_Tied, Tie0_1_1, CVT_imm_95_2, 0, CVT_Done },
295 // Convert__Reg1_0__Tie0_1_1__imm_95_1
296 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_imm_95_1, 0, CVT_Done },
297 // Convert__Mem2_0__imm_95_1
298 { CVT_95_addMemOperands, 1, CVT_imm_95_1, 0, CVT_Done },
299 // Convert__Reg1_0__Tie0_1_1__imm_95_2
300 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_imm_95_2, 0, CVT_Done },
301 // Convert__Mem2_0__imm_95_2
302 { CVT_95_addMemOperands, 1, CVT_imm_95_2, 0, CVT_Done },
303 // Convert__regSR__Tie0_1_1__imm_95_8
304 { CVT_regSR, 0, CVT_Tied, Tie0_1_1, CVT_imm_95_8, 0, CVT_Done },
305 // Convert__Reg1_0__Tie0_1_1__imm_95__MINUS_1
306 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_imm_95__MINUS_1, 0, CVT_Done },
307 // Convert__Mem2_0__imm_95__MINUS_1
308 { CVT_95_addMemOperands, 1, CVT_imm_95__MINUS_1, 0, CVT_Done },
309 // Convert__Imm1_1__Imm1_0
310 { CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
311 // Convert__Reg1_1__PostIndReg1_0__Tie1_1_1
312 { CVT_95_Reg, 2, CVT_95_addRegOperands, 1, CVT_Tied, Tie1_1_1, CVT_Done },
313 // Convert__regCG__imm_95_0
314 { CVT_regCG, 0, CVT_imm_95_0, 0, CVT_Done },
315 // Convert__CGImm1_0
316 { CVT_95_addImmOperands, 1, CVT_Done },
317 // Convert_NoOperands
318 { CVT_Done },
319 // Convert__Reg1_0__Tie0_1_1__Reg1_0
320 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 1, CVT_Done },
321 // Convert__Mem2_0__Mem2_0
322 { CVT_95_addMemOperands, 1, CVT_95_addMemOperands, 1, CVT_Done },
323 // Convert__Reg1_0__Tie0_1_1
324 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_Done },
325};
326
327void MSP430AsmParser::
328convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
329 const OperandVector &Operands) {
330 assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
331 const uint8_t *Converter = ConversionTable[Kind];
332 Inst.setOpcode(Opcode);
333 for (const uint8_t *p = Converter; *p; p += 2) {
334 unsigned OpIdx = *(p + 1);
335 switch (*p) {
336 default: llvm_unreachable("invalid conversion entry!");
337 case CVT_Reg:
338 static_cast<MSP430Operand &>(*Operands[OpIdx]).addRegOperands(Inst, 1);
339 break;
340 case CVT_Tied: {
341 assert(*(p + 1) < (size_t)(std::end(TiedAsmOperandTable) -
342 std::begin(TiedAsmOperandTable)) &&
343 "Tied operand not found");
344 unsigned TiedResOpnd = TiedAsmOperandTable[*(p + 1)][0];
345 if (TiedResOpnd != (uint8_t)-1)
346 Inst.addOperand(Inst.getOperand(TiedResOpnd));
347 break;
348 }
349 case CVT_95_Reg:
350 static_cast<MSP430Operand &>(*Operands[OpIdx]).addRegOperands(Inst, 1);
351 break;
352 case CVT_imm_95_0:
353 Inst.addOperand(MCOperand::createImm(0));
354 break;
355 case CVT_95_addMemOperands:
356 static_cast<MSP430Operand &>(*Operands[OpIdx]).addMemOperands(Inst, 2);
357 break;
358 case CVT_95_addImmOperands:
359 static_cast<MSP430Operand &>(*Operands[OpIdx]).addImmOperands(Inst, 1);
360 break;
361 case CVT_95_addRegOperands:
362 static_cast<MSP430Operand &>(*Operands[OpIdx]).addRegOperands(Inst, 1);
363 break;
364 case CVT_regSR:
365 Inst.addOperand(MCOperand::createReg(MSP430::SR));
366 break;
367 case CVT_imm_95_1:
368 Inst.addOperand(MCOperand::createImm(1));
369 break;
370 case CVT_imm_95_4:
371 Inst.addOperand(MCOperand::createImm(4));
372 break;
373 case CVT_imm_95_2:
374 Inst.addOperand(MCOperand::createImm(2));
375 break;
376 case CVT_imm_95_8:
377 Inst.addOperand(MCOperand::createImm(8));
378 break;
379 case CVT_imm_95__MINUS_1:
380 Inst.addOperand(MCOperand::createImm(-1));
381 break;
382 case CVT_regCG:
383 Inst.addOperand(MCOperand::createReg(MSP430::CG));
384 break;
385 }
386 }
387}
388
389void MSP430AsmParser::
390convertToMapAndConstraints(unsigned Kind,
391 const OperandVector &Operands) {
392 assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
393 unsigned NumMCOperands = 0;
394 const uint8_t *Converter = ConversionTable[Kind];
395 for (const uint8_t *p = Converter; *p; p += 2) {
396 switch (*p) {
397 default: llvm_unreachable("invalid conversion entry!");
398 case CVT_Reg:
399 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
400 Operands[*(p + 1)]->setConstraint("r");
401 ++NumMCOperands;
402 break;
403 case CVT_Tied:
404 ++NumMCOperands;
405 break;
406 case CVT_95_Reg:
407 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
408 Operands[*(p + 1)]->setConstraint("r");
409 NumMCOperands += 1;
410 break;
411 case CVT_imm_95_0:
412 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
413 Operands[*(p + 1)]->setConstraint("");
414 ++NumMCOperands;
415 break;
416 case CVT_95_addMemOperands:
417 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
418 Operands[*(p + 1)]->setConstraint("m");
419 NumMCOperands += 2;
420 break;
421 case CVT_95_addImmOperands:
422 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
423 Operands[*(p + 1)]->setConstraint("m");
424 NumMCOperands += 1;
425 break;
426 case CVT_95_addRegOperands:
427 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
428 Operands[*(p + 1)]->setConstraint("m");
429 NumMCOperands += 1;
430 break;
431 case CVT_regSR:
432 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
433 Operands[*(p + 1)]->setConstraint("m");
434 ++NumMCOperands;
435 break;
436 case CVT_imm_95_1:
437 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
438 Operands[*(p + 1)]->setConstraint("");
439 ++NumMCOperands;
440 break;
441 case CVT_imm_95_4:
442 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
443 Operands[*(p + 1)]->setConstraint("");
444 ++NumMCOperands;
445 break;
446 case CVT_imm_95_2:
447 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
448 Operands[*(p + 1)]->setConstraint("");
449 ++NumMCOperands;
450 break;
451 case CVT_imm_95_8:
452 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
453 Operands[*(p + 1)]->setConstraint("");
454 ++NumMCOperands;
455 break;
456 case CVT_imm_95__MINUS_1:
457 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
458 Operands[*(p + 1)]->setConstraint("");
459 ++NumMCOperands;
460 break;
461 case CVT_regCG:
462 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
463 Operands[*(p + 1)]->setConstraint("m");
464 ++NumMCOperands;
465 break;
466 }
467 }
468}
469
470namespace {
471
472/// MatchClassKind - The kinds of classes which participate in
473/// instruction matching.
474enum MatchClassKind {
475 InvalidMatchClass = 0,
476 OptionalMatchClass = 1,
477 MCK_LAST_TOKEN = OptionalMatchClass,
478 MCK_GR16, // register class 'GR16'
479 MCK_GR8, // register class 'GR8'
480 MCK_LAST_REGISTER = MCK_GR8,
481 MCK_CGImm, // user defined class 'CGImmAsmOperand'
482 MCK_Imm, // user defined class 'ImmAsmOperand'
483 MCK_IndReg, // user defined class 'IndRegAsmOperand'
484 MCK_Mem, // user defined class 'MemAsmOperand'
485 MCK_PostIndReg, // user defined class 'PostIndRegAsmOperand'
486 NumMatchClassKinds
487};
488
489} // end anonymous namespace
490
491static unsigned getDiagKindFromRegisterClass(MatchClassKind RegisterClass) {
492 return MCTargetAsmParser::Match_InvalidOperand;
493}
494
495static MatchClassKind matchTokenString(StringRef Name) {
496 return InvalidMatchClass;
497}
498
499/// isSubclass - Compute whether \p A is a subclass of \p B.
500static bool isSubclass(MatchClassKind A, MatchClassKind B) {
501 if (A == B)
502 return true;
503
504 [[maybe_unused]] static constexpr struct {
505 uint32_t Offset;
506 uint16_t Start;
507 uint16_t Length;
508 } Table[] = {
509 {0, 0, 0},
510 {0, 0, 0},
511 {0, 0, 0},
512 {0, 0, 0},
513 {0, 0, 0},
514 {0, 0, 0},
515 {0, 0, 0},
516 {0, 0, 0},
517 {0, 0, 0},
518 };
519
520 return false;
521}
522
523static unsigned validateOperandClass(MCParsedAsmOperand &GOp, MatchClassKind Kind) {
524 MSP430Operand &Operand = (MSP430Operand &)GOp;
525 if (Kind == InvalidMatchClass)
526 return MCTargetAsmParser::Match_InvalidOperand;
527
528 if (Operand.isToken() && Kind <= MCK_LAST_TOKEN)
529 return isSubclass(matchTokenString(Operand.getToken()), Kind) ?
530 MCTargetAsmParser::Match_Success :
531 MCTargetAsmParser::Match_InvalidOperand;
532
533 switch (Kind) {
534 default: break;
535 case MCK_CGImm: {
536 DiagnosticPredicate DP(Operand.isCGImm());
537 if (DP.isMatch())
538 return MCTargetAsmParser::Match_Success;
539 break;
540 }
541 case MCK_Imm: {
542 DiagnosticPredicate DP(Operand.isImm());
543 if (DP.isMatch())
544 return MCTargetAsmParser::Match_Success;
545 break;
546 }
547 case MCK_IndReg: {
548 DiagnosticPredicate DP(Operand.isIndReg());
549 if (DP.isMatch())
550 return MCTargetAsmParser::Match_Success;
551 break;
552 }
553 case MCK_Mem: {
554 DiagnosticPredicate DP(Operand.isMem());
555 if (DP.isMatch())
556 return MCTargetAsmParser::Match_Success;
557 break;
558 }
559 case MCK_PostIndReg: {
560 DiagnosticPredicate DP(Operand.isPostIndReg());
561 if (DP.isMatch())
562 return MCTargetAsmParser::Match_Success;
563 break;
564 }
565 } // end switch (Kind)
566
567 if (Operand.isReg()) {
568 static constexpr uint16_t Table[MSP430::NUM_TARGET_REGS] = {
569 InvalidMatchClass,
570 MCK_GR16,
571 MCK_GR8,
572 MCK_GR16,
573 MCK_GR8,
574 MCK_GR16,
575 MCK_GR8,
576 MCK_GR16,
577 MCK_GR8,
578 MCK_GR16,
579 MCK_GR16,
580 MCK_GR16,
581 MCK_GR16,
582 MCK_GR16,
583 MCK_GR16,
584 MCK_GR16,
585 MCK_GR16,
586 MCK_GR16,
587 MCK_GR16,
588 MCK_GR16,
589 MCK_GR16,
590 MCK_GR8,
591 MCK_GR8,
592 MCK_GR8,
593 MCK_GR8,
594 MCK_GR8,
595 MCK_GR8,
596 MCK_GR8,
597 MCK_GR8,
598 MCK_GR8,
599 MCK_GR8,
600 MCK_GR8,
601 MCK_GR8,
602 };
603
604 MCRegister Reg = Operand.getReg();
605 MatchClassKind OpKind = Reg.isPhysical() ? (MatchClassKind)Table[Reg.id()] : InvalidMatchClass;
606 return isSubclass(OpKind, Kind) ? (unsigned)MCTargetAsmParser::Match_Success :
607 getDiagKindFromRegisterClass(Kind);
608 }
609
610 if (Kind > MCK_LAST_TOKEN && Kind <= MCK_LAST_REGISTER)
611 return getDiagKindFromRegisterClass(Kind);
612
613 return MCTargetAsmParser::Match_InvalidOperand;
614}
615
616#ifndef NDEBUG
617const char *getMatchClassName(MatchClassKind Kind) {
618 switch (Kind) {
619 case InvalidMatchClass: return "InvalidMatchClass";
620 case OptionalMatchClass: return "OptionalMatchClass";
621 case MCK_GR16: return "MCK_GR16";
622 case MCK_GR8: return "MCK_GR8";
623 case MCK_CGImm: return "MCK_CGImm";
624 case MCK_Imm: return "MCK_Imm";
625 case MCK_IndReg: return "MCK_IndReg";
626 case MCK_Mem: return "MCK_Mem";
627 case MCK_PostIndReg: return "MCK_PostIndReg";
628 case NumMatchClassKinds: return "NumMatchClassKinds";
629 }
630 llvm_unreachable("unhandled MatchClassKind!");
631}
632
633#endif // NDEBUG
634FeatureBitset MSP430AsmParser::
635ComputeAvailableFeatures(const FeatureBitset &FB) const {
636 FeatureBitset Features;
637 return Features;
638}
639
640static bool checkAsmTiedOperandConstraints(const MSP430AsmParser&AsmParser,
641 unsigned Kind, const OperandVector &Operands,
642 uint64_t &ErrorInfo) {
643 assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
644 const uint8_t *Converter = ConversionTable[Kind];
645 for (const uint8_t *p = Converter; *p; p += 2) {
646 switch (*p) {
647 case CVT_Tied: {
648 unsigned OpIdx = *(p + 1);
649 assert(OpIdx < (size_t)(std::end(TiedAsmOperandTable) -
650 std::begin(TiedAsmOperandTable)) &&
651 "Tied operand not found");
652 unsigned OpndNum1 = TiedAsmOperandTable[OpIdx][1];
653 unsigned OpndNum2 = TiedAsmOperandTable[OpIdx][2];
654 if (OpndNum1 != OpndNum2) {
655 auto &SrcOp1 = Operands[OpndNum1];
656 auto &SrcOp2 = Operands[OpndNum2];
657 if (!AsmParser.areEqualRegs(*SrcOp1, *SrcOp2)) {
658 ErrorInfo = OpndNum2;
659 return false;
660 }
661 }
662 break;
663 }
664 default:
665 break;
666 }
667 }
668 return true;
669}
670
671static const char MnemonicTable[] =
672 "\000\003adc\005adc.b\003add\005add.b\004addc\006addc.b\003and\005and.b\003"
673 "bic\005bic.b\003bis\005bis.b\003bit\005bit.b\002br\004call\003clr\005cl"
674 "r.b\004clrc\004clrn\004clrz\003cmp\005cmp.b\004dadc\006dadc.b\004dadd\006"
675 "dadd.b\003dec\005dec.b\004decd\006decd.b\004dint\004eint\003inc\005inc."
676 "b\004incd\006incd.b\003inv\005inv.b\001j\003jmp\003mov\005mov.b\003nop\003"
677 "pop\004push\006push.b\003ret\004reti\003rla\005rla.b\003rlc\005rlc.b\003"
678 "rra\005rra.b\003rrc\005rrc.b\003sbc\005sbc.b\004setc\004setn\004setz\003"
679 "sub\005sub.b\004subc\006subc.b\004swpb\003sxt\003tst\005tst.b\003xor\005"
680 "xor.b";
681
682// Feature bitsets.
683enum : uint8_t {
684 AMFBS_None,
685};
686
687static constexpr FeatureBitset FeatureBitsets[] = {
688 {}, // AMFBS_None
689};
690
691namespace {
692 struct MatchEntry {
693 uint16_t Mnemonic;
694 uint16_t Opcode;
695 uint8_t ConvertFn;
696 uint8_t RequiredFeaturesIdx;
697 uint8_t Classes[2];
698 StringRef getMnemonic() const {
699 return StringRef(MnemonicTable + Mnemonic + 1,
700 MnemonicTable[Mnemonic]);
701 }
702 };
703
704 // Predicate for searching for an opcode.
705 struct LessOpcode {
706 bool operator()(const MatchEntry &LHS, StringRef RHS) {
707 return LHS.getMnemonic() < RHS;
708 }
709 bool operator()(StringRef LHS, const MatchEntry &RHS) {
710 return LHS < RHS.getMnemonic();
711 }
712 bool operator()(const MatchEntry &LHS, const MatchEntry &RHS) {
713 return LHS.getMnemonic() < RHS.getMnemonic();
714 }
715 };
716} // end anonymous namespace
717
718static const MatchEntry MatchTable0[] = {
719 { 1 /* adc */, MSP430::ADDC16rc, Convert__Reg1_0__Tie0_1_1__imm_95_0, AMFBS_None, { MCK_GR16 }, },
720 { 1 /* adc */, MSP430::ADDC16mc, Convert__Mem2_0__imm_95_0, AMFBS_None, { MCK_Mem }, },
721 { 5 /* adc.b */, MSP430::ADDC8rc, Convert__Reg1_0__Tie0_1_1__imm_95_0, AMFBS_None, { MCK_GR8 }, },
722 { 5 /* adc.b */, MSP430::ADDC8mc, Convert__Mem2_0__imm_95_0, AMFBS_None, { MCK_Mem }, },
723 { 11 /* add */, MSP430::ADD16rr, Convert__Reg1_1__Tie0_1_1__Reg1_0, AMFBS_None, { MCK_GR16, MCK_GR16 }, },
724 { 11 /* add */, MSP430::ADD16mr, Convert__Mem2_1__Reg1_0, AMFBS_None, { MCK_GR16, MCK_Mem }, },
725 { 11 /* add */, MSP430::ADD16rc, Convert__Reg1_1__Tie0_1_1__CGImm1_0, AMFBS_None, { MCK_CGImm, MCK_GR16 }, },
726 { 11 /* add */, MSP430::ADD16mc, Convert__Mem2_1__CGImm1_0, AMFBS_None, { MCK_CGImm, MCK_Mem }, },
727 { 11 /* add */, MSP430::ADD16ri, Convert__Reg1_1__Tie0_1_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_GR16 }, },
728 { 11 /* add */, MSP430::ADD16mi, Convert__Mem2_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_Mem }, },
729 { 11 /* add */, MSP430::ADD16rn, Convert__Reg1_1__Tie0_1_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_GR16 }, },
730 { 11 /* add */, MSP430::ADD16mn, Convert__Mem2_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_Mem }, },
731 { 11 /* add */, MSP430::ADD16rm, Convert__Reg1_1__Tie0_1_1__Mem2_0, AMFBS_None, { MCK_Mem, MCK_GR16 }, },
732 { 11 /* add */, MSP430::ADD16mm, Convert__Mem2_1__Mem2_0, AMFBS_None, { MCK_Mem, MCK_Mem }, },
733 { 11 /* add */, MSP430::ADD16rp, Convert__Reg1_1__PostIndReg1_0__Tie0_1_1__Tie1_1_1, AMFBS_None, { MCK_PostIndReg, MCK_GR16 }, },
734 { 11 /* add */, MSP430::ADD16mp, Convert__Mem2_1__PostIndReg1_0, AMFBS_None, { MCK_PostIndReg, MCK_Mem }, },
735 { 15 /* add.b */, MSP430::ADD8rr, Convert__Reg1_1__Tie0_1_1__Reg1_0, AMFBS_None, { MCK_GR8, MCK_GR8 }, },
736 { 15 /* add.b */, MSP430::ADD8mr, Convert__Mem2_1__Reg1_0, AMFBS_None, { MCK_GR8, MCK_Mem }, },
737 { 15 /* add.b */, MSP430::ADD8rc, Convert__Reg1_1__Tie0_1_1__CGImm1_0, AMFBS_None, { MCK_CGImm, MCK_GR8 }, },
738 { 15 /* add.b */, MSP430::ADD8mc, Convert__Mem2_1__CGImm1_0, AMFBS_None, { MCK_CGImm, MCK_Mem }, },
739 { 15 /* add.b */, MSP430::ADD8ri, Convert__Reg1_1__Tie0_1_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_GR8 }, },
740 { 15 /* add.b */, MSP430::ADD8mi, Convert__Mem2_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_Mem }, },
741 { 15 /* add.b */, MSP430::ADD8rn, Convert__Reg1_1__Tie0_1_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_GR8 }, },
742 { 15 /* add.b */, MSP430::ADD8mn, Convert__Mem2_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_Mem }, },
743 { 15 /* add.b */, MSP430::ADD8rm, Convert__Reg1_1__Tie0_1_1__Mem2_0, AMFBS_None, { MCK_Mem, MCK_GR8 }, },
744 { 15 /* add.b */, MSP430::ADD8mm, Convert__Mem2_1__Mem2_0, AMFBS_None, { MCK_Mem, MCK_Mem }, },
745 { 15 /* add.b */, MSP430::ADD8rp, Convert__Reg1_1__PostIndReg1_0__Tie0_1_1__Tie1_1_1, AMFBS_None, { MCK_PostIndReg, MCK_GR8 }, },
746 { 15 /* add.b */, MSP430::ADD8mp, Convert__Mem2_1__PostIndReg1_0, AMFBS_None, { MCK_PostIndReg, MCK_Mem }, },
747 { 21 /* addc */, MSP430::ADDC16rr, Convert__Reg1_1__Tie0_1_1__Reg1_0, AMFBS_None, { MCK_GR16, MCK_GR16 }, },
748 { 21 /* addc */, MSP430::ADDC16mr, Convert__Mem2_1__Reg1_0, AMFBS_None, { MCK_GR16, MCK_Mem }, },
749 { 21 /* addc */, MSP430::ADDC16rc, Convert__Reg1_1__Tie0_1_1__CGImm1_0, AMFBS_None, { MCK_CGImm, MCK_GR16 }, },
750 { 21 /* addc */, MSP430::ADDC16mc, Convert__Mem2_1__CGImm1_0, AMFBS_None, { MCK_CGImm, MCK_Mem }, },
751 { 21 /* addc */, MSP430::ADDC16ri, Convert__Reg1_1__Tie0_1_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_GR16 }, },
752 { 21 /* addc */, MSP430::ADDC16mi, Convert__Mem2_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_Mem }, },
753 { 21 /* addc */, MSP430::ADDC16rn, Convert__Reg1_1__Tie0_1_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_GR16 }, },
754 { 21 /* addc */, MSP430::ADDC16mn, Convert__Mem2_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_Mem }, },
755 { 21 /* addc */, MSP430::ADDC16rm, Convert__Reg1_1__Tie0_1_1__Mem2_0, AMFBS_None, { MCK_Mem, MCK_GR16 }, },
756 { 21 /* addc */, MSP430::ADDC16mm, Convert__Mem2_1__Mem2_0, AMFBS_None, { MCK_Mem, MCK_Mem }, },
757 { 21 /* addc */, MSP430::ADDC16rp, Convert__Reg1_1__PostIndReg1_0__Tie0_1_1__Tie1_1_1, AMFBS_None, { MCK_PostIndReg, MCK_GR16 }, },
758 { 21 /* addc */, MSP430::ADDC16mp, Convert__Mem2_1__PostIndReg1_0, AMFBS_None, { MCK_PostIndReg, MCK_Mem }, },
759 { 26 /* addc.b */, MSP430::ADDC8rr, Convert__Reg1_1__Tie0_1_1__Reg1_0, AMFBS_None, { MCK_GR8, MCK_GR8 }, },
760 { 26 /* addc.b */, MSP430::ADDC8mr, Convert__Mem2_1__Reg1_0, AMFBS_None, { MCK_GR8, MCK_Mem }, },
761 { 26 /* addc.b */, MSP430::ADDC8rc, Convert__Reg1_1__Tie0_1_1__CGImm1_0, AMFBS_None, { MCK_CGImm, MCK_GR8 }, },
762 { 26 /* addc.b */, MSP430::ADDC8mc, Convert__Mem2_1__CGImm1_0, AMFBS_None, { MCK_CGImm, MCK_Mem }, },
763 { 26 /* addc.b */, MSP430::ADDC8ri, Convert__Reg1_1__Tie0_1_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_GR8 }, },
764 { 26 /* addc.b */, MSP430::ADDC8mi, Convert__Mem2_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_Mem }, },
765 { 26 /* addc.b */, MSP430::ADDC8rn, Convert__Reg1_1__Tie0_1_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_GR8 }, },
766 { 26 /* addc.b */, MSP430::ADDC8mn, Convert__Mem2_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_Mem }, },
767 { 26 /* addc.b */, MSP430::ADDC8rm, Convert__Reg1_1__Tie0_1_1__Mem2_0, AMFBS_None, { MCK_Mem, MCK_GR8 }, },
768 { 26 /* addc.b */, MSP430::ADDC8mm, Convert__Mem2_1__Mem2_0, AMFBS_None, { MCK_Mem, MCK_Mem }, },
769 { 26 /* addc.b */, MSP430::ADDC8rp, Convert__Reg1_1__PostIndReg1_0__Tie0_1_1__Tie1_1_1, AMFBS_None, { MCK_PostIndReg, MCK_GR8 }, },
770 { 26 /* addc.b */, MSP430::ADDC8mp, Convert__Mem2_1__PostIndReg1_0, AMFBS_None, { MCK_PostIndReg, MCK_Mem }, },
771 { 33 /* and */, MSP430::AND16rr, Convert__Reg1_1__Tie0_1_1__Reg1_0, AMFBS_None, { MCK_GR16, MCK_GR16 }, },
772 { 33 /* and */, MSP430::AND16mr, Convert__Mem2_1__Reg1_0, AMFBS_None, { MCK_GR16, MCK_Mem }, },
773 { 33 /* and */, MSP430::AND16rc, Convert__Reg1_1__Tie0_1_1__CGImm1_0, AMFBS_None, { MCK_CGImm, MCK_GR16 }, },
774 { 33 /* and */, MSP430::AND16mc, Convert__Mem2_1__CGImm1_0, AMFBS_None, { MCK_CGImm, MCK_Mem }, },
775 { 33 /* and */, MSP430::AND16ri, Convert__Reg1_1__Tie0_1_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_GR16 }, },
776 { 33 /* and */, MSP430::AND16mi, Convert__Mem2_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_Mem }, },
777 { 33 /* and */, MSP430::AND16rn, Convert__Reg1_1__Tie0_1_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_GR16 }, },
778 { 33 /* and */, MSP430::AND16mn, Convert__Mem2_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_Mem }, },
779 { 33 /* and */, MSP430::AND16rm, Convert__Reg1_1__Tie0_1_1__Mem2_0, AMFBS_None, { MCK_Mem, MCK_GR16 }, },
780 { 33 /* and */, MSP430::AND16mm, Convert__Mem2_1__Mem2_0, AMFBS_None, { MCK_Mem, MCK_Mem }, },
781 { 33 /* and */, MSP430::AND16rp, Convert__Reg1_1__PostIndReg1_0__Tie0_1_1__Tie1_1_1, AMFBS_None, { MCK_PostIndReg, MCK_GR16 }, },
782 { 33 /* and */, MSP430::AND16mp, Convert__Mem2_1__PostIndReg1_0, AMFBS_None, { MCK_PostIndReg, MCK_Mem }, },
783 { 37 /* and.b */, MSP430::AND8rr, Convert__Reg1_1__Tie0_1_1__Reg1_0, AMFBS_None, { MCK_GR8, MCK_GR8 }, },
784 { 37 /* and.b */, MSP430::AND8mr, Convert__Mem2_1__Reg1_0, AMFBS_None, { MCK_GR8, MCK_Mem }, },
785 { 37 /* and.b */, MSP430::AND8rc, Convert__Reg1_1__Tie0_1_1__CGImm1_0, AMFBS_None, { MCK_CGImm, MCK_GR8 }, },
786 { 37 /* and.b */, MSP430::AND8mc, Convert__Mem2_1__CGImm1_0, AMFBS_None, { MCK_CGImm, MCK_Mem }, },
787 { 37 /* and.b */, MSP430::AND8ri, Convert__Reg1_1__Tie0_1_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_GR8 }, },
788 { 37 /* and.b */, MSP430::AND8mi, Convert__Mem2_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_Mem }, },
789 { 37 /* and.b */, MSP430::AND8rn, Convert__Reg1_1__Tie0_1_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_GR8 }, },
790 { 37 /* and.b */, MSP430::AND8mn, Convert__Mem2_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_Mem }, },
791 { 37 /* and.b */, MSP430::AND8rm, Convert__Reg1_1__Tie0_1_1__Mem2_0, AMFBS_None, { MCK_Mem, MCK_GR8 }, },
792 { 37 /* and.b */, MSP430::AND8mm, Convert__Mem2_1__Mem2_0, AMFBS_None, { MCK_Mem, MCK_Mem }, },
793 { 37 /* and.b */, MSP430::AND8rp, Convert__Reg1_1__PostIndReg1_0__Tie0_1_1__Tie1_1_1, AMFBS_None, { MCK_PostIndReg, MCK_GR8 }, },
794 { 37 /* and.b */, MSP430::AND8mp, Convert__Mem2_1__PostIndReg1_0, AMFBS_None, { MCK_PostIndReg, MCK_Mem }, },
795 { 43 /* bic */, MSP430::BIC16rr, Convert__Reg1_1__Tie0_1_1__Reg1_0, AMFBS_None, { MCK_GR16, MCK_GR16 }, },
796 { 43 /* bic */, MSP430::BIC16mr, Convert__Mem2_1__Reg1_0, AMFBS_None, { MCK_GR16, MCK_Mem }, },
797 { 43 /* bic */, MSP430::BIC16rc, Convert__Reg1_1__Tie0_1_1__CGImm1_0, AMFBS_None, { MCK_CGImm, MCK_GR16 }, },
798 { 43 /* bic */, MSP430::BIC16mc, Convert__Mem2_1__CGImm1_0, AMFBS_None, { MCK_CGImm, MCK_Mem }, },
799 { 43 /* bic */, MSP430::BIC16ri, Convert__Reg1_1__Tie0_1_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_GR16 }, },
800 { 43 /* bic */, MSP430::BIC16mi, Convert__Mem2_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_Mem }, },
801 { 43 /* bic */, MSP430::BIC16rn, Convert__Reg1_1__Tie0_1_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_GR16 }, },
802 { 43 /* bic */, MSP430::BIC16mn, Convert__Mem2_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_Mem }, },
803 { 43 /* bic */, MSP430::BIC16rm, Convert__Reg1_1__Tie0_1_1__Mem2_0, AMFBS_None, { MCK_Mem, MCK_GR16 }, },
804 { 43 /* bic */, MSP430::BIC16mm, Convert__Mem2_1__Mem2_0, AMFBS_None, { MCK_Mem, MCK_Mem }, },
805 { 43 /* bic */, MSP430::BIC16rp, Convert__Reg1_1__PostIndReg1_0__Tie0_1_1__Tie1_1_1, AMFBS_None, { MCK_PostIndReg, MCK_GR16 }, },
806 { 43 /* bic */, MSP430::BIC16mp, Convert__Mem2_1__PostIndReg1_0, AMFBS_None, { MCK_PostIndReg, MCK_Mem }, },
807 { 47 /* bic.b */, MSP430::BIC8rr, Convert__Reg1_1__Tie0_1_1__Reg1_0, AMFBS_None, { MCK_GR8, MCK_GR8 }, },
808 { 47 /* bic.b */, MSP430::BIC8mr, Convert__Mem2_1__Reg1_0, AMFBS_None, { MCK_GR8, MCK_Mem }, },
809 { 47 /* bic.b */, MSP430::BIC8rc, Convert__Reg1_1__Tie0_1_1__CGImm1_0, AMFBS_None, { MCK_CGImm, MCK_GR8 }, },
810 { 47 /* bic.b */, MSP430::BIC8mc, Convert__Mem2_1__CGImm1_0, AMFBS_None, { MCK_CGImm, MCK_Mem }, },
811 { 47 /* bic.b */, MSP430::BIC8ri, Convert__Reg1_1__Tie0_1_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_GR8 }, },
812 { 47 /* bic.b */, MSP430::BIC8mi, Convert__Mem2_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_Mem }, },
813 { 47 /* bic.b */, MSP430::BIC8rn, Convert__Reg1_1__Tie0_1_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_GR8 }, },
814 { 47 /* bic.b */, MSP430::BIC8mn, Convert__Mem2_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_Mem }, },
815 { 47 /* bic.b */, MSP430::BIC8rm, Convert__Reg1_1__Tie0_1_1__Mem2_0, AMFBS_None, { MCK_Mem, MCK_GR8 }, },
816 { 47 /* bic.b */, MSP430::BIC8mm, Convert__Mem2_1__Mem2_0, AMFBS_None, { MCK_Mem, MCK_Mem }, },
817 { 47 /* bic.b */, MSP430::BIC8rp, Convert__Reg1_1__PostIndReg1_0__Tie0_1_1__Tie1_1_1, AMFBS_None, { MCK_PostIndReg, MCK_GR8 }, },
818 { 47 /* bic.b */, MSP430::BIC8mp, Convert__Mem2_1__PostIndReg1_0, AMFBS_None, { MCK_PostIndReg, MCK_Mem }, },
819 { 53 /* bis */, MSP430::BIS16rr, Convert__Reg1_1__Tie0_1_1__Reg1_0, AMFBS_None, { MCK_GR16, MCK_GR16 }, },
820 { 53 /* bis */, MSP430::BIS16mr, Convert__Mem2_1__Reg1_0, AMFBS_None, { MCK_GR16, MCK_Mem }, },
821 { 53 /* bis */, MSP430::BIS16rc, Convert__Reg1_1__Tie0_1_1__CGImm1_0, AMFBS_None, { MCK_CGImm, MCK_GR16 }, },
822 { 53 /* bis */, MSP430::BIS16mc, Convert__Mem2_1__CGImm1_0, AMFBS_None, { MCK_CGImm, MCK_Mem }, },
823 { 53 /* bis */, MSP430::BIS16ri, Convert__Reg1_1__Tie0_1_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_GR16 }, },
824 { 53 /* bis */, MSP430::BIS16mi, Convert__Mem2_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_Mem }, },
825 { 53 /* bis */, MSP430::BIS16rn, Convert__Reg1_1__Tie0_1_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_GR16 }, },
826 { 53 /* bis */, MSP430::BIS16mn, Convert__Mem2_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_Mem }, },
827 { 53 /* bis */, MSP430::BIS16rm, Convert__Reg1_1__Tie0_1_1__Mem2_0, AMFBS_None, { MCK_Mem, MCK_GR16 }, },
828 { 53 /* bis */, MSP430::BIS16mm, Convert__Mem2_1__Mem2_0, AMFBS_None, { MCK_Mem, MCK_Mem }, },
829 { 53 /* bis */, MSP430::BIS16rp, Convert__Reg1_1__PostIndReg1_0__Tie0_1_1__Tie1_1_1, AMFBS_None, { MCK_PostIndReg, MCK_GR16 }, },
830 { 53 /* bis */, MSP430::BIS16mp, Convert__Mem2_1__PostIndReg1_0, AMFBS_None, { MCK_PostIndReg, MCK_Mem }, },
831 { 57 /* bis.b */, MSP430::BIS8rr, Convert__Reg1_1__Tie0_1_1__Reg1_0, AMFBS_None, { MCK_GR8, MCK_GR8 }, },
832 { 57 /* bis.b */, MSP430::BIS8mr, Convert__Mem2_1__Reg1_0, AMFBS_None, { MCK_GR8, MCK_Mem }, },
833 { 57 /* bis.b */, MSP430::BIS8rc, Convert__Reg1_1__Tie0_1_1__CGImm1_0, AMFBS_None, { MCK_CGImm, MCK_GR8 }, },
834 { 57 /* bis.b */, MSP430::BIS8mc, Convert__Mem2_1__CGImm1_0, AMFBS_None, { MCK_CGImm, MCK_Mem }, },
835 { 57 /* bis.b */, MSP430::BIS8ri, Convert__Reg1_1__Tie0_1_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_GR8 }, },
836 { 57 /* bis.b */, MSP430::BIS8mi, Convert__Mem2_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_Mem }, },
837 { 57 /* bis.b */, MSP430::BIS8rn, Convert__Reg1_1__Tie0_1_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_GR8 }, },
838 { 57 /* bis.b */, MSP430::BIS8mn, Convert__Mem2_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_Mem }, },
839 { 57 /* bis.b */, MSP430::BIS8rm, Convert__Reg1_1__Tie0_1_1__Mem2_0, AMFBS_None, { MCK_Mem, MCK_GR8 }, },
840 { 57 /* bis.b */, MSP430::BIS8mm, Convert__Mem2_1__Mem2_0, AMFBS_None, { MCK_Mem, MCK_Mem }, },
841 { 57 /* bis.b */, MSP430::BIS8rp, Convert__Reg1_1__PostIndReg1_0__Tie0_1_1__Tie1_1_1, AMFBS_None, { MCK_PostIndReg, MCK_GR8 }, },
842 { 57 /* bis.b */, MSP430::BIS8mp, Convert__Mem2_1__PostIndReg1_0, AMFBS_None, { MCK_PostIndReg, MCK_Mem }, },
843 { 63 /* bit */, MSP430::BIT16rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR16, MCK_GR16 }, },
844 { 63 /* bit */, MSP430::BIT16mr, Convert__Mem2_1__Reg1_0, AMFBS_None, { MCK_GR16, MCK_Mem }, },
845 { 63 /* bit */, MSP430::BIT16rc, Convert__Reg1_1__CGImm1_0, AMFBS_None, { MCK_CGImm, MCK_GR16 }, },
846 { 63 /* bit */, MSP430::BIT16mc, Convert__Mem2_1__CGImm1_0, AMFBS_None, { MCK_CGImm, MCK_Mem }, },
847 { 63 /* bit */, MSP430::BIT16ri, Convert__Reg1_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_GR16 }, },
848 { 63 /* bit */, MSP430::BIT16mi, Convert__Mem2_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_Mem }, },
849 { 63 /* bit */, MSP430::BIT16rn, Convert__Reg1_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_GR16 }, },
850 { 63 /* bit */, MSP430::BIT16mn, Convert__Mem2_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_Mem }, },
851 { 63 /* bit */, MSP430::BIT16rm, Convert__Reg1_1__Mem2_0, AMFBS_None, { MCK_Mem, MCK_GR16 }, },
852 { 63 /* bit */, MSP430::BIT16mm, Convert__Mem2_1__Mem2_0, AMFBS_None, { MCK_Mem, MCK_Mem }, },
853 { 63 /* bit */, MSP430::BIT16rp, Convert__Reg1_1__PostIndReg1_0, AMFBS_None, { MCK_PostIndReg, MCK_GR16 }, },
854 { 63 /* bit */, MSP430::BIT16mp, Convert__Mem2_1__PostIndReg1_0, AMFBS_None, { MCK_PostIndReg, MCK_Mem }, },
855 { 67 /* bit.b */, MSP430::BIT8rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR8, MCK_GR8 }, },
856 { 67 /* bit.b */, MSP430::BIT8mr, Convert__Mem2_1__Reg1_0, AMFBS_None, { MCK_GR8, MCK_Mem }, },
857 { 67 /* bit.b */, MSP430::BIT8rc, Convert__Reg1_1__CGImm1_0, AMFBS_None, { MCK_CGImm, MCK_GR8 }, },
858 { 67 /* bit.b */, MSP430::BIT8mc, Convert__Mem2_1__CGImm1_0, AMFBS_None, { MCK_CGImm, MCK_Mem }, },
859 { 67 /* bit.b */, MSP430::BIT8ri, Convert__Reg1_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_GR8 }, },
860 { 67 /* bit.b */, MSP430::BIT8mi, Convert__Mem2_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_Mem }, },
861 { 67 /* bit.b */, MSP430::BIT8rn, Convert__Reg1_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_GR8 }, },
862 { 67 /* bit.b */, MSP430::BIT8mn, Convert__Mem2_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_Mem }, },
863 { 67 /* bit.b */, MSP430::BIT8rm, Convert__Reg1_1__Mem2_0, AMFBS_None, { MCK_Mem, MCK_GR8 }, },
864 { 67 /* bit.b */, MSP430::BIT8mm, Convert__Mem2_1__Mem2_0, AMFBS_None, { MCK_Mem, MCK_Mem }, },
865 { 67 /* bit.b */, MSP430::BIT8rp, Convert__Reg1_1__PostIndReg1_0, AMFBS_None, { MCK_PostIndReg, MCK_GR8 }, },
866 { 67 /* bit.b */, MSP430::BIT8mp, Convert__Mem2_1__PostIndReg1_0, AMFBS_None, { MCK_PostIndReg, MCK_Mem }, },
867 { 73 /* br */, MSP430::Br, Convert__Reg1_0, AMFBS_None, { MCK_GR16 }, },
868 { 73 /* br */, MSP430::Bi, Convert__Imm1_0, AMFBS_None, { MCK_Imm }, },
869 { 73 /* br */, MSP430::Bm, Convert__Mem2_0, AMFBS_None, { MCK_Mem }, },
870 { 76 /* call */, MSP430::CALLr, Convert__Reg1_0, AMFBS_None, { MCK_GR16 }, },
871 { 76 /* call */, MSP430::CALLi, Convert__Imm1_0, AMFBS_None, { MCK_Imm }, },
872 { 76 /* call */, MSP430::CALLn, Convert__IndReg1_0, AMFBS_None, { MCK_IndReg }, },
873 { 76 /* call */, MSP430::CALLm, Convert__Mem2_0, AMFBS_None, { MCK_Mem }, },
874 { 76 /* call */, MSP430::CALLp, Convert__PostIndReg1_0, AMFBS_None, { MCK_PostIndReg }, },
875 { 81 /* clr */, MSP430::MOV16rc, Convert__Reg1_0__imm_95_0, AMFBS_None, { MCK_GR16 }, },
876 { 81 /* clr */, MSP430::MOV16mc, Convert__Mem2_0__imm_95_0, AMFBS_None, { MCK_Mem }, },
877 { 85 /* clr.b */, MSP430::MOV8rc, Convert__Reg1_0__imm_95_0, AMFBS_None, { MCK_GR8 }, },
878 { 85 /* clr.b */, MSP430::MOV8mc, Convert__Mem2_0__imm_95_0, AMFBS_None, { MCK_Mem }, },
879 { 91 /* clrc */, MSP430::BIC16rc, Convert__regSR__Tie0_1_1__imm_95_1, AMFBS_None, { }, },
880 { 96 /* clrn */, MSP430::BIC16rc, Convert__regSR__Tie0_1_1__imm_95_4, AMFBS_None, { }, },
881 { 101 /* clrz */, MSP430::BIC16rc, Convert__regSR__Tie0_1_1__imm_95_2, AMFBS_None, { }, },
882 { 106 /* cmp */, MSP430::CMP16rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR16, MCK_GR16 }, },
883 { 106 /* cmp */, MSP430::CMP16mr, Convert__Mem2_1__Reg1_0, AMFBS_None, { MCK_GR16, MCK_Mem }, },
884 { 106 /* cmp */, MSP430::CMP16rc, Convert__Reg1_1__CGImm1_0, AMFBS_None, { MCK_CGImm, MCK_GR16 }, },
885 { 106 /* cmp */, MSP430::CMP16mc, Convert__Mem2_1__CGImm1_0, AMFBS_None, { MCK_CGImm, MCK_Mem }, },
886 { 106 /* cmp */, MSP430::CMP16ri, Convert__Reg1_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_GR16 }, },
887 { 106 /* cmp */, MSP430::CMP16mi, Convert__Mem2_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_Mem }, },
888 { 106 /* cmp */, MSP430::CMP16rn, Convert__Reg1_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_GR16 }, },
889 { 106 /* cmp */, MSP430::CMP16mn, Convert__Mem2_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_Mem }, },
890 { 106 /* cmp */, MSP430::CMP16rm, Convert__Reg1_1__Mem2_0, AMFBS_None, { MCK_Mem, MCK_GR16 }, },
891 { 106 /* cmp */, MSP430::CMP16mm, Convert__Mem2_1__Mem2_0, AMFBS_None, { MCK_Mem, MCK_Mem }, },
892 { 106 /* cmp */, MSP430::CMP16rp, Convert__Reg1_1__PostIndReg1_0, AMFBS_None, { MCK_PostIndReg, MCK_GR16 }, },
893 { 106 /* cmp */, MSP430::CMP16mp, Convert__Mem2_1__PostIndReg1_0, AMFBS_None, { MCK_PostIndReg, MCK_Mem }, },
894 { 110 /* cmp.b */, MSP430::CMP8rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR8, MCK_GR8 }, },
895 { 110 /* cmp.b */, MSP430::CMP8mr, Convert__Mem2_1__Reg1_0, AMFBS_None, { MCK_GR8, MCK_Mem }, },
896 { 110 /* cmp.b */, MSP430::CMP8rc, Convert__Reg1_1__CGImm1_0, AMFBS_None, { MCK_CGImm, MCK_GR8 }, },
897 { 110 /* cmp.b */, MSP430::CMP8mc, Convert__Mem2_1__CGImm1_0, AMFBS_None, { MCK_CGImm, MCK_Mem }, },
898 { 110 /* cmp.b */, MSP430::CMP8ri, Convert__Reg1_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_GR8 }, },
899 { 110 /* cmp.b */, MSP430::CMP8mi, Convert__Mem2_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_Mem }, },
900 { 110 /* cmp.b */, MSP430::CMP8rn, Convert__Reg1_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_GR8 }, },
901 { 110 /* cmp.b */, MSP430::CMP8mn, Convert__Mem2_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_Mem }, },
902 { 110 /* cmp.b */, MSP430::CMP8rm, Convert__Reg1_1__Mem2_0, AMFBS_None, { MCK_Mem, MCK_GR8 }, },
903 { 110 /* cmp.b */, MSP430::CMP8mm, Convert__Mem2_1__Mem2_0, AMFBS_None, { MCK_Mem, MCK_Mem }, },
904 { 110 /* cmp.b */, MSP430::CMP8rp, Convert__Reg1_1__PostIndReg1_0, AMFBS_None, { MCK_PostIndReg, MCK_GR8 }, },
905 { 110 /* cmp.b */, MSP430::CMP8mp, Convert__Mem2_1__PostIndReg1_0, AMFBS_None, { MCK_PostIndReg, MCK_Mem }, },
906 { 116 /* dadc */, MSP430::DADD16rc, Convert__Reg1_0__Tie0_1_1__imm_95_0, AMFBS_None, { MCK_GR16 }, },
907 { 116 /* dadc */, MSP430::DADD16mc, Convert__Mem2_0__imm_95_0, AMFBS_None, { MCK_Mem }, },
908 { 121 /* dadc.b */, MSP430::DADD8rc, Convert__Reg1_0__Tie0_1_1__imm_95_0, AMFBS_None, { MCK_GR8 }, },
909 { 121 /* dadc.b */, MSP430::DADD8mc, Convert__Mem2_0__imm_95_0, AMFBS_None, { MCK_Mem }, },
910 { 128 /* dadd */, MSP430::DADD16rr, Convert__Reg1_1__Tie0_1_1__Reg1_0, AMFBS_None, { MCK_GR16, MCK_GR16 }, },
911 { 128 /* dadd */, MSP430::DADD16mr, Convert__Mem2_1__Reg1_0, AMFBS_None, { MCK_GR16, MCK_Mem }, },
912 { 128 /* dadd */, MSP430::DADD16rc, Convert__Reg1_1__Tie0_1_1__CGImm1_0, AMFBS_None, { MCK_CGImm, MCK_GR16 }, },
913 { 128 /* dadd */, MSP430::DADD16mc, Convert__Mem2_1__CGImm1_0, AMFBS_None, { MCK_CGImm, MCK_Mem }, },
914 { 128 /* dadd */, MSP430::DADD16ri, Convert__Reg1_1__Tie0_1_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_GR16 }, },
915 { 128 /* dadd */, MSP430::DADD16mi, Convert__Mem2_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_Mem }, },
916 { 128 /* dadd */, MSP430::DADD16rn, Convert__Reg1_1__Tie0_1_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_GR16 }, },
917 { 128 /* dadd */, MSP430::DADD16mn, Convert__Mem2_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_Mem }, },
918 { 128 /* dadd */, MSP430::DADD16rm, Convert__Reg1_1__Tie0_1_1__Mem2_0, AMFBS_None, { MCK_Mem, MCK_GR16 }, },
919 { 128 /* dadd */, MSP430::DADD16mm, Convert__Mem2_1__Mem2_0, AMFBS_None, { MCK_Mem, MCK_Mem }, },
920 { 128 /* dadd */, MSP430::DADD16rp, Convert__Reg1_1__PostIndReg1_0__Tie0_1_1__Tie1_1_1, AMFBS_None, { MCK_PostIndReg, MCK_GR16 }, },
921 { 128 /* dadd */, MSP430::DADD16mp, Convert__Mem2_1__PostIndReg1_0, AMFBS_None, { MCK_PostIndReg, MCK_Mem }, },
922 { 133 /* dadd.b */, MSP430::DADD8rr, Convert__Reg1_1__Tie0_1_1__Reg1_0, AMFBS_None, { MCK_GR8, MCK_GR8 }, },
923 { 133 /* dadd.b */, MSP430::DADD8mr, Convert__Mem2_1__Reg1_0, AMFBS_None, { MCK_GR8, MCK_Mem }, },
924 { 133 /* dadd.b */, MSP430::DADD8rc, Convert__Reg1_1__Tie0_1_1__CGImm1_0, AMFBS_None, { MCK_CGImm, MCK_GR8 }, },
925 { 133 /* dadd.b */, MSP430::DADD8mc, Convert__Mem2_1__CGImm1_0, AMFBS_None, { MCK_CGImm, MCK_Mem }, },
926 { 133 /* dadd.b */, MSP430::DADD8ri, Convert__Reg1_1__Tie0_1_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_GR8 }, },
927 { 133 /* dadd.b */, MSP430::DADD8mi, Convert__Mem2_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_Mem }, },
928 { 133 /* dadd.b */, MSP430::DADD8rn, Convert__Reg1_1__Tie0_1_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_GR8 }, },
929 { 133 /* dadd.b */, MSP430::DADD8mn, Convert__Mem2_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_Mem }, },
930 { 133 /* dadd.b */, MSP430::DADD8rm, Convert__Reg1_1__Tie0_1_1__Mem2_0, AMFBS_None, { MCK_Mem, MCK_GR8 }, },
931 { 133 /* dadd.b */, MSP430::DADD8mm, Convert__Mem2_1__Mem2_0, AMFBS_None, { MCK_Mem, MCK_Mem }, },
932 { 133 /* dadd.b */, MSP430::DADD8rp, Convert__Reg1_1__PostIndReg1_0__Tie0_1_1__Tie1_1_1, AMFBS_None, { MCK_PostIndReg, MCK_GR8 }, },
933 { 133 /* dadd.b */, MSP430::DADD8mp, Convert__Mem2_1__PostIndReg1_0, AMFBS_None, { MCK_PostIndReg, MCK_Mem }, },
934 { 140 /* dec */, MSP430::SUB16rc, Convert__Reg1_0__Tie0_1_1__imm_95_1, AMFBS_None, { MCK_GR16 }, },
935 { 140 /* dec */, MSP430::SUB16mc, Convert__Mem2_0__imm_95_1, AMFBS_None, { MCK_Mem }, },
936 { 144 /* dec.b */, MSP430::SUB8rc, Convert__Reg1_0__Tie0_1_1__imm_95_1, AMFBS_None, { MCK_GR8 }, },
937 { 144 /* dec.b */, MSP430::SUB8mc, Convert__Mem2_0__imm_95_1, AMFBS_None, { MCK_Mem }, },
938 { 150 /* decd */, MSP430::SUB16rc, Convert__Reg1_0__Tie0_1_1__imm_95_2, AMFBS_None, { MCK_GR16 }, },
939 { 150 /* decd */, MSP430::SUB16mc, Convert__Mem2_0__imm_95_2, AMFBS_None, { MCK_Mem }, },
940 { 155 /* decd.b */, MSP430::SUB8rc, Convert__Reg1_0__Tie0_1_1__imm_95_2, AMFBS_None, { MCK_GR8 }, },
941 { 155 /* decd.b */, MSP430::SUB8mc, Convert__Mem2_0__imm_95_2, AMFBS_None, { MCK_Mem }, },
942 { 162 /* dint */, MSP430::BIC16rc, Convert__regSR__Tie0_1_1__imm_95_8, AMFBS_None, { }, },
943 { 167 /* eint */, MSP430::BIS16rc, Convert__regSR__Tie0_1_1__imm_95_8, AMFBS_None, { }, },
944 { 172 /* inc */, MSP430::ADD16rc, Convert__Reg1_0__Tie0_1_1__imm_95_1, AMFBS_None, { MCK_GR16 }, },
945 { 172 /* inc */, MSP430::ADD16mc, Convert__Mem2_0__imm_95_1, AMFBS_None, { MCK_Mem }, },
946 { 176 /* inc.b */, MSP430::ADD8rc, Convert__Reg1_0__Tie0_1_1__imm_95_1, AMFBS_None, { MCK_GR8 }, },
947 { 176 /* inc.b */, MSP430::ADD8mc, Convert__Mem2_0__imm_95_1, AMFBS_None, { MCK_Mem }, },
948 { 182 /* incd */, MSP430::ADD16rc, Convert__Reg1_0__Tie0_1_1__imm_95_2, AMFBS_None, { MCK_GR16 }, },
949 { 182 /* incd */, MSP430::ADD16mc, Convert__Mem2_0__imm_95_2, AMFBS_None, { MCK_Mem }, },
950 { 187 /* incd.b */, MSP430::ADD8rc, Convert__Reg1_0__Tie0_1_1__imm_95_2, AMFBS_None, { MCK_GR8 }, },
951 { 187 /* incd.b */, MSP430::ADD8mc, Convert__Mem2_0__imm_95_2, AMFBS_None, { MCK_Mem }, },
952 { 194 /* inv */, MSP430::XOR16rc, Convert__Reg1_0__Tie0_1_1__imm_95__MINUS_1, AMFBS_None, { MCK_GR16 }, },
953 { 194 /* inv */, MSP430::XOR16mc, Convert__Mem2_0__imm_95__MINUS_1, AMFBS_None, { MCK_Mem }, },
954 { 198 /* inv.b */, MSP430::XOR8rc, Convert__Reg1_0__Tie0_1_1__imm_95__MINUS_1, AMFBS_None, { MCK_GR8 }, },
955 { 198 /* inv.b */, MSP430::XOR8mc, Convert__Mem2_0__imm_95__MINUS_1, AMFBS_None, { MCK_Mem }, },
956 { 204 /* j */, MSP430::JCC, Convert__Imm1_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_Imm }, },
957 { 206 /* jmp */, MSP430::JMP, Convert__Imm1_0, AMFBS_None, { MCK_Imm }, },
958 { 210 /* mov */, MSP430::MOV16rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR16, MCK_GR16 }, },
959 { 210 /* mov */, MSP430::MOV16mr, Convert__Mem2_1__Reg1_0, AMFBS_None, { MCK_GR16, MCK_Mem }, },
960 { 210 /* mov */, MSP430::MOV16rc, Convert__Reg1_1__CGImm1_0, AMFBS_None, { MCK_CGImm, MCK_GR16 }, },
961 { 210 /* mov */, MSP430::MOV16mc, Convert__Mem2_1__CGImm1_0, AMFBS_None, { MCK_CGImm, MCK_Mem }, },
962 { 210 /* mov */, MSP430::MOV16ri, Convert__Reg1_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_GR16 }, },
963 { 210 /* mov */, MSP430::MOV16mi, Convert__Mem2_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_Mem }, },
964 { 210 /* mov */, MSP430::MOV16rn, Convert__Reg1_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_GR16 }, },
965 { 210 /* mov */, MSP430::MOV16mn, Convert__Mem2_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_Mem }, },
966 { 210 /* mov */, MSP430::MOV16rm, Convert__Reg1_1__Mem2_0, AMFBS_None, { MCK_Mem, MCK_GR16 }, },
967 { 210 /* mov */, MSP430::MOV16mm, Convert__Mem2_1__Mem2_0, AMFBS_None, { MCK_Mem, MCK_Mem }, },
968 { 210 /* mov */, MSP430::MOV16rp, Convert__Reg1_1__PostIndReg1_0__Tie1_1_1, AMFBS_None, { MCK_PostIndReg, MCK_GR16 }, },
969 { 214 /* mov.b */, MSP430::MOV8rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR8, MCK_GR8 }, },
970 { 214 /* mov.b */, MSP430::MOV8mr, Convert__Mem2_1__Reg1_0, AMFBS_None, { MCK_GR8, MCK_Mem }, },
971 { 214 /* mov.b */, MSP430::MOV8rc, Convert__Reg1_1__CGImm1_0, AMFBS_None, { MCK_CGImm, MCK_GR8 }, },
972 { 214 /* mov.b */, MSP430::MOV8mc, Convert__Mem2_1__CGImm1_0, AMFBS_None, { MCK_CGImm, MCK_Mem }, },
973 { 214 /* mov.b */, MSP430::MOV8ri, Convert__Reg1_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_GR8 }, },
974 { 214 /* mov.b */, MSP430::MOV8mi, Convert__Mem2_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_Mem }, },
975 { 214 /* mov.b */, MSP430::MOV8rn, Convert__Reg1_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_GR8 }, },
976 { 214 /* mov.b */, MSP430::MOV8mn, Convert__Mem2_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_Mem }, },
977 { 214 /* mov.b */, MSP430::MOV8rm, Convert__Reg1_1__Mem2_0, AMFBS_None, { MCK_Mem, MCK_GR8 }, },
978 { 214 /* mov.b */, MSP430::MOV8mm, Convert__Mem2_1__Mem2_0, AMFBS_None, { MCK_Mem, MCK_Mem }, },
979 { 214 /* mov.b */, MSP430::MOV8rp, Convert__Reg1_1__PostIndReg1_0__Tie1_1_1, AMFBS_None, { MCK_PostIndReg, MCK_GR8 }, },
980 { 220 /* nop */, MSP430::MOV16rc, Convert__regCG__imm_95_0, AMFBS_None, { }, },
981 { 224 /* pop */, MSP430::POP16r, Convert__Reg1_0, AMFBS_None, { MCK_GR16 }, },
982 { 228 /* push */, MSP430::PUSH16r, Convert__Reg1_0, AMFBS_None, { MCK_GR16 }, },
983 { 228 /* push */, MSP430::PUSH16c, Convert__CGImm1_0, AMFBS_None, { MCK_CGImm }, },
984 { 228 /* push */, MSP430::PUSH16i, Convert__Imm1_0, AMFBS_None, { MCK_Imm }, },
985 { 233 /* push.b */, MSP430::PUSH8r, Convert__Reg1_0, AMFBS_None, { MCK_GR8 }, },
986 { 240 /* ret */, MSP430::RET, Convert_NoOperands, AMFBS_None, { }, },
987 { 244 /* reti */, MSP430::RETI, Convert_NoOperands, AMFBS_None, { }, },
988 { 249 /* rla */, MSP430::ADD16rr, Convert__Reg1_0__Tie0_1_1__Reg1_0, AMFBS_None, { MCK_GR16 }, },
989 { 249 /* rla */, MSP430::ADD16mm, Convert__Mem2_0__Mem2_0, AMFBS_None, { MCK_Mem }, },
990 { 253 /* rla.b */, MSP430::ADD8rr, Convert__Reg1_0__Tie0_1_1__Reg1_0, AMFBS_None, { MCK_GR8 }, },
991 { 253 /* rla.b */, MSP430::ADD8mm, Convert__Mem2_0__Mem2_0, AMFBS_None, { MCK_Mem }, },
992 { 259 /* rlc */, MSP430::ADDC16rr, Convert__Reg1_0__Tie0_1_1__Reg1_0, AMFBS_None, { MCK_GR16 }, },
993 { 259 /* rlc */, MSP430::ADDC16mm, Convert__Mem2_0__Mem2_0, AMFBS_None, { MCK_Mem }, },
994 { 263 /* rlc.b */, MSP430::ADDC8rr, Convert__Reg1_0__Tie0_1_1__Reg1_0, AMFBS_None, { MCK_GR8 }, },
995 { 263 /* rlc.b */, MSP430::ADDC8mm, Convert__Mem2_0__Mem2_0, AMFBS_None, { MCK_Mem }, },
996 { 269 /* rra */, MSP430::RRA16r, Convert__Reg1_0__Tie0_1_1, AMFBS_None, { MCK_GR16 }, },
997 { 269 /* rra */, MSP430::RRA16n, Convert__IndReg1_0, AMFBS_None, { MCK_IndReg }, },
998 { 269 /* rra */, MSP430::RRA16m, Convert__Mem2_0, AMFBS_None, { MCK_Mem }, },
999 { 269 /* rra */, MSP430::RRA16p, Convert__PostIndReg1_0, AMFBS_None, { MCK_PostIndReg }, },
1000 { 273 /* rra.b */, MSP430::RRA8r, Convert__Reg1_0__Tie0_1_1, AMFBS_None, { MCK_GR8 }, },
1001 { 273 /* rra.b */, MSP430::RRA8n, Convert__IndReg1_0, AMFBS_None, { MCK_IndReg }, },
1002 { 273 /* rra.b */, MSP430::RRA8m, Convert__Mem2_0, AMFBS_None, { MCK_Mem }, },
1003 { 273 /* rra.b */, MSP430::RRA8p, Convert__PostIndReg1_0, AMFBS_None, { MCK_PostIndReg }, },
1004 { 279 /* rrc */, MSP430::RRC16r, Convert__Reg1_0__Tie0_1_1, AMFBS_None, { MCK_GR16 }, },
1005 { 279 /* rrc */, MSP430::RRC16n, Convert__IndReg1_0, AMFBS_None, { MCK_IndReg }, },
1006 { 279 /* rrc */, MSP430::RRC16m, Convert__Mem2_0, AMFBS_None, { MCK_Mem }, },
1007 { 279 /* rrc */, MSP430::RRC16p, Convert__PostIndReg1_0, AMFBS_None, { MCK_PostIndReg }, },
1008 { 283 /* rrc.b */, MSP430::RRC8r, Convert__Reg1_0__Tie0_1_1, AMFBS_None, { MCK_GR8 }, },
1009 { 283 /* rrc.b */, MSP430::RRC8n, Convert__IndReg1_0, AMFBS_None, { MCK_IndReg }, },
1010 { 283 /* rrc.b */, MSP430::RRC8m, Convert__Mem2_0, AMFBS_None, { MCK_Mem }, },
1011 { 283 /* rrc.b */, MSP430::RRC8p, Convert__PostIndReg1_0, AMFBS_None, { MCK_PostIndReg }, },
1012 { 289 /* sbc */, MSP430::SUBC16rc, Convert__Reg1_0__Tie0_1_1__imm_95_0, AMFBS_None, { MCK_GR16 }, },
1013 { 289 /* sbc */, MSP430::SUBC16mc, Convert__Mem2_0__imm_95_0, AMFBS_None, { MCK_Mem }, },
1014 { 293 /* sbc.b */, MSP430::SUBC8rc, Convert__Reg1_0__Tie0_1_1__imm_95_0, AMFBS_None, { MCK_GR8 }, },
1015 { 293 /* sbc.b */, MSP430::SUBC8mc, Convert__Mem2_0__imm_95_0, AMFBS_None, { MCK_Mem }, },
1016 { 299 /* setc */, MSP430::BIS16rc, Convert__regSR__Tie0_1_1__imm_95_1, AMFBS_None, { }, },
1017 { 304 /* setn */, MSP430::BIS16rc, Convert__regSR__Tie0_1_1__imm_95_4, AMFBS_None, { }, },
1018 { 309 /* setz */, MSP430::BIS16rc, Convert__regSR__Tie0_1_1__imm_95_2, AMFBS_None, { }, },
1019 { 314 /* sub */, MSP430::SUB16rr, Convert__Reg1_1__Tie0_1_1__Reg1_0, AMFBS_None, { MCK_GR16, MCK_GR16 }, },
1020 { 314 /* sub */, MSP430::SUB16mr, Convert__Mem2_1__Reg1_0, AMFBS_None, { MCK_GR16, MCK_Mem }, },
1021 { 314 /* sub */, MSP430::SUB16rc, Convert__Reg1_1__Tie0_1_1__CGImm1_0, AMFBS_None, { MCK_CGImm, MCK_GR16 }, },
1022 { 314 /* sub */, MSP430::SUB16mc, Convert__Mem2_1__CGImm1_0, AMFBS_None, { MCK_CGImm, MCK_Mem }, },
1023 { 314 /* sub */, MSP430::SUB16ri, Convert__Reg1_1__Tie0_1_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_GR16 }, },
1024 { 314 /* sub */, MSP430::SUB16mi, Convert__Mem2_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_Mem }, },
1025 { 314 /* sub */, MSP430::SUB16rn, Convert__Reg1_1__Tie0_1_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_GR16 }, },
1026 { 314 /* sub */, MSP430::SUB16mn, Convert__Mem2_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_Mem }, },
1027 { 314 /* sub */, MSP430::SUB16rm, Convert__Reg1_1__Tie0_1_1__Mem2_0, AMFBS_None, { MCK_Mem, MCK_GR16 }, },
1028 { 314 /* sub */, MSP430::SUB16mm, Convert__Mem2_1__Mem2_0, AMFBS_None, { MCK_Mem, MCK_Mem }, },
1029 { 314 /* sub */, MSP430::SUB16rp, Convert__Reg1_1__PostIndReg1_0__Tie0_1_1__Tie1_1_1, AMFBS_None, { MCK_PostIndReg, MCK_GR16 }, },
1030 { 314 /* sub */, MSP430::SUB16mp, Convert__Mem2_1__PostIndReg1_0, AMFBS_None, { MCK_PostIndReg, MCK_Mem }, },
1031 { 318 /* sub.b */, MSP430::SUB8rr, Convert__Reg1_1__Tie0_1_1__Reg1_0, AMFBS_None, { MCK_GR8, MCK_GR8 }, },
1032 { 318 /* sub.b */, MSP430::SUB8mr, Convert__Mem2_1__Reg1_0, AMFBS_None, { MCK_GR8, MCK_Mem }, },
1033 { 318 /* sub.b */, MSP430::SUB8rc, Convert__Reg1_1__Tie0_1_1__CGImm1_0, AMFBS_None, { MCK_CGImm, MCK_GR8 }, },
1034 { 318 /* sub.b */, MSP430::SUB8mc, Convert__Mem2_1__CGImm1_0, AMFBS_None, { MCK_CGImm, MCK_Mem }, },
1035 { 318 /* sub.b */, MSP430::SUB8ri, Convert__Reg1_1__Tie0_1_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_GR8 }, },
1036 { 318 /* sub.b */, MSP430::SUB8mi, Convert__Mem2_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_Mem }, },
1037 { 318 /* sub.b */, MSP430::SUB8rn, Convert__Reg1_1__Tie0_1_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_GR8 }, },
1038 { 318 /* sub.b */, MSP430::SUB8mn, Convert__Mem2_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_Mem }, },
1039 { 318 /* sub.b */, MSP430::SUB8rm, Convert__Reg1_1__Tie0_1_1__Mem2_0, AMFBS_None, { MCK_Mem, MCK_GR8 }, },
1040 { 318 /* sub.b */, MSP430::SUB8mm, Convert__Mem2_1__Mem2_0, AMFBS_None, { MCK_Mem, MCK_Mem }, },
1041 { 318 /* sub.b */, MSP430::SUB8rp, Convert__Reg1_1__PostIndReg1_0__Tie0_1_1__Tie1_1_1, AMFBS_None, { MCK_PostIndReg, MCK_GR8 }, },
1042 { 318 /* sub.b */, MSP430::SUB8mp, Convert__Mem2_1__PostIndReg1_0, AMFBS_None, { MCK_PostIndReg, MCK_Mem }, },
1043 { 324 /* subc */, MSP430::SUBC16rr, Convert__Reg1_1__Tie0_1_1__Reg1_0, AMFBS_None, { MCK_GR16, MCK_GR16 }, },
1044 { 324 /* subc */, MSP430::SUBC16mr, Convert__Mem2_1__Reg1_0, AMFBS_None, { MCK_GR16, MCK_Mem }, },
1045 { 324 /* subc */, MSP430::SUBC16rc, Convert__Reg1_1__Tie0_1_1__CGImm1_0, AMFBS_None, { MCK_CGImm, MCK_GR16 }, },
1046 { 324 /* subc */, MSP430::SUBC16mc, Convert__Mem2_1__CGImm1_0, AMFBS_None, { MCK_CGImm, MCK_Mem }, },
1047 { 324 /* subc */, MSP430::SUBC16ri, Convert__Reg1_1__Tie0_1_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_GR16 }, },
1048 { 324 /* subc */, MSP430::SUBC16mi, Convert__Mem2_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_Mem }, },
1049 { 324 /* subc */, MSP430::SUBC16rn, Convert__Reg1_1__Tie0_1_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_GR16 }, },
1050 { 324 /* subc */, MSP430::SUBC16mn, Convert__Mem2_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_Mem }, },
1051 { 324 /* subc */, MSP430::SUBC16rm, Convert__Reg1_1__Tie0_1_1__Mem2_0, AMFBS_None, { MCK_Mem, MCK_GR16 }, },
1052 { 324 /* subc */, MSP430::SUBC16mm, Convert__Mem2_1__Mem2_0, AMFBS_None, { MCK_Mem, MCK_Mem }, },
1053 { 324 /* subc */, MSP430::SUBC16rp, Convert__Reg1_1__PostIndReg1_0__Tie0_1_1__Tie1_1_1, AMFBS_None, { MCK_PostIndReg, MCK_GR16 }, },
1054 { 324 /* subc */, MSP430::SUBC16mp, Convert__Mem2_1__PostIndReg1_0, AMFBS_None, { MCK_PostIndReg, MCK_Mem }, },
1055 { 329 /* subc.b */, MSP430::SUBC8rr, Convert__Reg1_1__Tie0_1_1__Reg1_0, AMFBS_None, { MCK_GR8, MCK_GR8 }, },
1056 { 329 /* subc.b */, MSP430::SUBC8mr, Convert__Mem2_1__Reg1_0, AMFBS_None, { MCK_GR8, MCK_Mem }, },
1057 { 329 /* subc.b */, MSP430::SUBC8rc, Convert__Reg1_1__Tie0_1_1__CGImm1_0, AMFBS_None, { MCK_CGImm, MCK_GR8 }, },
1058 { 329 /* subc.b */, MSP430::SUBC8mc, Convert__Mem2_1__CGImm1_0, AMFBS_None, { MCK_CGImm, MCK_Mem }, },
1059 { 329 /* subc.b */, MSP430::SUBC8ri, Convert__Reg1_1__Tie0_1_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_GR8 }, },
1060 { 329 /* subc.b */, MSP430::SUBC8mi, Convert__Mem2_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_Mem }, },
1061 { 329 /* subc.b */, MSP430::SUBC8rn, Convert__Reg1_1__Tie0_1_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_GR8 }, },
1062 { 329 /* subc.b */, MSP430::SUBC8mn, Convert__Mem2_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_Mem }, },
1063 { 329 /* subc.b */, MSP430::SUBC8rm, Convert__Reg1_1__Tie0_1_1__Mem2_0, AMFBS_None, { MCK_Mem, MCK_GR8 }, },
1064 { 329 /* subc.b */, MSP430::SUBC8mm, Convert__Mem2_1__Mem2_0, AMFBS_None, { MCK_Mem, MCK_Mem }, },
1065 { 329 /* subc.b */, MSP430::SUBC8rp, Convert__Reg1_1__PostIndReg1_0__Tie0_1_1__Tie1_1_1, AMFBS_None, { MCK_PostIndReg, MCK_GR8 }, },
1066 { 329 /* subc.b */, MSP430::SUBC8mp, Convert__Mem2_1__PostIndReg1_0, AMFBS_None, { MCK_PostIndReg, MCK_Mem }, },
1067 { 336 /* swpb */, MSP430::SWPB16r, Convert__Reg1_0__Tie0_1_1, AMFBS_None, { MCK_GR16 }, },
1068 { 336 /* swpb */, MSP430::SWPB16n, Convert__IndReg1_0, AMFBS_None, { MCK_IndReg }, },
1069 { 336 /* swpb */, MSP430::SWPB16m, Convert__Mem2_0, AMFBS_None, { MCK_Mem }, },
1070 { 336 /* swpb */, MSP430::SWPB16p, Convert__PostIndReg1_0, AMFBS_None, { MCK_PostIndReg }, },
1071 { 341 /* sxt */, MSP430::SEXT16r, Convert__Reg1_0__Tie0_1_1, AMFBS_None, { MCK_GR16 }, },
1072 { 341 /* sxt */, MSP430::SEXT16n, Convert__IndReg1_0, AMFBS_None, { MCK_IndReg }, },
1073 { 341 /* sxt */, MSP430::SEXT16m, Convert__Mem2_0, AMFBS_None, { MCK_Mem }, },
1074 { 341 /* sxt */, MSP430::SEXT16p, Convert__PostIndReg1_0, AMFBS_None, { MCK_PostIndReg }, },
1075 { 345 /* tst */, MSP430::CMP16rc, Convert__Reg1_0__imm_95_0, AMFBS_None, { MCK_GR16 }, },
1076 { 345 /* tst */, MSP430::CMP16mc, Convert__Mem2_0__imm_95_0, AMFBS_None, { MCK_Mem }, },
1077 { 349 /* tst.b */, MSP430::CMP8rc, Convert__Reg1_0__imm_95_0, AMFBS_None, { MCK_GR8 }, },
1078 { 349 /* tst.b */, MSP430::CMP8mc, Convert__Mem2_0__imm_95_0, AMFBS_None, { MCK_Mem }, },
1079 { 355 /* xor */, MSP430::XOR16rr, Convert__Reg1_1__Tie0_1_1__Reg1_0, AMFBS_None, { MCK_GR16, MCK_GR16 }, },
1080 { 355 /* xor */, MSP430::XOR16mr, Convert__Mem2_1__Reg1_0, AMFBS_None, { MCK_GR16, MCK_Mem }, },
1081 { 355 /* xor */, MSP430::XOR16rc, Convert__Reg1_1__Tie0_1_1__CGImm1_0, AMFBS_None, { MCK_CGImm, MCK_GR16 }, },
1082 { 355 /* xor */, MSP430::XOR16mc, Convert__Mem2_1__CGImm1_0, AMFBS_None, { MCK_CGImm, MCK_Mem }, },
1083 { 355 /* xor */, MSP430::XOR16ri, Convert__Reg1_1__Tie0_1_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_GR16 }, },
1084 { 355 /* xor */, MSP430::XOR16mi, Convert__Mem2_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_Mem }, },
1085 { 355 /* xor */, MSP430::XOR16rn, Convert__Reg1_1__Tie0_1_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_GR16 }, },
1086 { 355 /* xor */, MSP430::XOR16mn, Convert__Mem2_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_Mem }, },
1087 { 355 /* xor */, MSP430::XOR16rm, Convert__Reg1_1__Tie0_1_1__Mem2_0, AMFBS_None, { MCK_Mem, MCK_GR16 }, },
1088 { 355 /* xor */, MSP430::XOR16mm, Convert__Mem2_1__Mem2_0, AMFBS_None, { MCK_Mem, MCK_Mem }, },
1089 { 355 /* xor */, MSP430::XOR16rp, Convert__Reg1_1__PostIndReg1_0__Tie0_1_1__Tie1_1_1, AMFBS_None, { MCK_PostIndReg, MCK_GR16 }, },
1090 { 355 /* xor */, MSP430::XOR16mp, Convert__Mem2_1__PostIndReg1_0, AMFBS_None, { MCK_PostIndReg, MCK_Mem }, },
1091 { 359 /* xor.b */, MSP430::XOR8rr, Convert__Reg1_1__Tie0_1_1__Reg1_0, AMFBS_None, { MCK_GR8, MCK_GR8 }, },
1092 { 359 /* xor.b */, MSP430::XOR8mr, Convert__Mem2_1__Reg1_0, AMFBS_None, { MCK_GR8, MCK_Mem }, },
1093 { 359 /* xor.b */, MSP430::XOR8rc, Convert__Reg1_1__Tie0_1_1__CGImm1_0, AMFBS_None, { MCK_CGImm, MCK_GR8 }, },
1094 { 359 /* xor.b */, MSP430::XOR8mc, Convert__Mem2_1__CGImm1_0, AMFBS_None, { MCK_CGImm, MCK_Mem }, },
1095 { 359 /* xor.b */, MSP430::XOR8ri, Convert__Reg1_1__Tie0_1_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_GR8 }, },
1096 { 359 /* xor.b */, MSP430::XOR8mi, Convert__Mem2_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_Mem }, },
1097 { 359 /* xor.b */, MSP430::XOR8rn, Convert__Reg1_1__Tie0_1_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_GR8 }, },
1098 { 359 /* xor.b */, MSP430::XOR8mn, Convert__Mem2_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_Mem }, },
1099 { 359 /* xor.b */, MSP430::XOR8rm, Convert__Reg1_1__Tie0_1_1__Mem2_0, AMFBS_None, { MCK_Mem, MCK_GR8 }, },
1100 { 359 /* xor.b */, MSP430::XOR8mm, Convert__Mem2_1__Mem2_0, AMFBS_None, { MCK_Mem, MCK_Mem }, },
1101 { 359 /* xor.b */, MSP430::XOR8rp, Convert__Reg1_1__PostIndReg1_0__Tie0_1_1__Tie1_1_1, AMFBS_None, { MCK_PostIndReg, MCK_GR8 }, },
1102 { 359 /* xor.b */, MSP430::XOR8mp, Convert__Mem2_1__PostIndReg1_0, AMFBS_None, { MCK_PostIndReg, MCK_Mem }, },
1103};
1104
1105#include "llvm/Support/Debug.h"
1106#include "llvm/Support/Format.h"
1107
1108unsigned MSP430AsmParser::
1109MatchInstructionImpl(const OperandVector &Operands,
1110 MCInst &Inst,
1111 uint64_t &ErrorInfo,
1112 FeatureBitset &MissingFeatures,
1113 bool matchingInlineAsm, unsigned VariantID) {
1114 // Eliminate obvious mismatches.
1115 if (Operands.size() > 3) {
1116 ErrorInfo = 3;
1117 return Match_InvalidOperand;
1118 }
1119
1120 // Get the current feature set.
1121 const FeatureBitset &AvailableFeatures = getAvailableFeatures();
1122
1123 // Get the instruction mnemonic, which is the first token.
1124 StringRef Mnemonic = ((MSP430Operand &)*Operands[0]).getToken();
1125
1126 // Some state to try to produce better error messages.
1127 bool HadMatchOtherThanFeatures = false;
1128 bool HadMatchOtherThanPredicate = false;
1129 unsigned RetCode = Match_InvalidOperand;
1130 MissingFeatures.set();
1131 // Set ErrorInfo to the operand that mismatches if it is
1132 // wrong for all instances of the instruction.
1133 ErrorInfo = ~0ULL;
1134 // Find the appropriate table for this asm variant.
1135 const MatchEntry *Start, *End;
1136 switch (VariantID) {
1137 default: llvm_unreachable("invalid variant!");
1138 case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break;
1139 }
1140 // Search the table.
1141 auto MnemonicRange = std::equal_range(Start, End, Mnemonic, LessOpcode());
1142
1143 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "AsmMatcher: found " <<
1144 std::distance(MnemonicRange.first, MnemonicRange.second) <<
1145 " encodings with mnemonic '" << Mnemonic << "'\n");
1146
1147 // Return a more specific error code if no mnemonics match.
1148 if (MnemonicRange.first == MnemonicRange.second)
1149 return Match_MnemonicFail;
1150
1151 for (const MatchEntry *it = MnemonicRange.first, *ie = MnemonicRange.second;
1152 it != ie; ++it) {
1153 const FeatureBitset &RequiredFeatures = FeatureBitsets[it->RequiredFeaturesIdx];
1154 bool HasRequiredFeatures =
1155 (AvailableFeatures & RequiredFeatures) == RequiredFeatures;
1156 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Trying to match opcode "
1157 << MII.getName(it->Opcode) << "\n");
1158 // equal_range guarantees that instruction mnemonic matches.
1159 assert(Mnemonic == it->getMnemonic());
1160 bool OperandsValid = true;
1161 for (unsigned FormalIdx = 0, ActualIdx = 1; FormalIdx != 2; ++FormalIdx) {
1162 auto Formal = static_cast<MatchClassKind>(it->Classes[FormalIdx]);
1163 DEBUG_WITH_TYPE("asm-matcher",
1164 dbgs() << " Matching formal operand class " << getMatchClassName(Formal)
1165 << " against actual operand at index " << ActualIdx);
1166 if (ActualIdx < Operands.size())
1167 DEBUG_WITH_TYPE("asm-matcher", dbgs() << " (";
1168 Operands[ActualIdx]->print(dbgs(), *getContext().getAsmInfo()); dbgs() << "): ");
1169 else
1170 DEBUG_WITH_TYPE("asm-matcher", dbgs() << ": ");
1171 if (ActualIdx >= Operands.size()) {
1172 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "actual operand index out of range\n");
1173 if (Formal == InvalidMatchClass) {
1174 break;
1175 }
1176 if (isSubclass(Formal, OptionalMatchClass)) {
1177 continue;
1178 }
1179 OperandsValid = false;
1180 ErrorInfo = ActualIdx;
1181 break;
1182 }
1183 MCParsedAsmOperand &Actual = *Operands[ActualIdx];
1184 unsigned Diag = validateOperandClass(Actual, Formal);
1185 if (Diag == Match_Success) {
1186 DEBUG_WITH_TYPE("asm-matcher",
1187 dbgs() << "match success using generic matcher\n");
1188 ++ActualIdx;
1189 continue;
1190 }
1191 // If the generic handler indicates an invalid operand
1192 // failure, check for a special case.
1193 if (Diag != Match_Success) {
1194 unsigned TargetDiag = validateTargetOperandClass(Actual, Formal);
1195 if (TargetDiag == Match_Success) {
1196 DEBUG_WITH_TYPE("asm-matcher",
1197 dbgs() << "match success using target matcher\n");
1198 ++ActualIdx;
1199 continue;
1200 }
1201 // If the target matcher returned a specific error code use
1202 // that, else use the one from the generic matcher.
1203 if (TargetDiag != Match_InvalidOperand && HasRequiredFeatures)
1204 Diag = TargetDiag;
1205 }
1206 // If current formal operand wasn't matched and it is optional
1207 // then try to match next formal operand
1208 if (Diag == Match_InvalidOperand && isSubclass(Formal, OptionalMatchClass)) {
1209 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "ignoring optional operand\n");
1210 continue;
1211 }
1212 // If this operand is broken for all of the instances of this
1213 // mnemonic, keep track of it so we can report loc info.
1214 // If we already had a match that only failed due to a
1215 // target predicate, that diagnostic is preferred.
1216 if (!HadMatchOtherThanPredicate &&
1217 (it == MnemonicRange.first || ErrorInfo <= ActualIdx)) {
1218 if (HasRequiredFeatures && (ErrorInfo != ActualIdx || Diag != Match_InvalidOperand))
1219 RetCode = Diag;
1220 ErrorInfo = ActualIdx;
1221 }
1222 // Otherwise, just reject this instance of the mnemonic.
1223 OperandsValid = false;
1224 break;
1225 }
1226
1227 if (!OperandsValid) {
1228 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Opcode result: multiple "
1229 "operand mismatches, ignoring "
1230 "this opcode\n");
1231 continue;
1232 }
1233 if (!HasRequiredFeatures) {
1234 HadMatchOtherThanFeatures = true;
1235 FeatureBitset NewMissingFeatures = RequiredFeatures & ~AvailableFeatures;
1236 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Missing target features:";
1237 for (unsigned I = 0, E = NewMissingFeatures.size(); I != E; ++I)
1238 if (NewMissingFeatures[I])
1239 dbgs() << ' ' << I;
1240 dbgs() << "\n");
1241 if (NewMissingFeatures.count() <=
1242 MissingFeatures.count())
1243 MissingFeatures = NewMissingFeatures;
1244 continue;
1245 }
1246
1247 Inst.clear();
1248
1249 Inst.setOpcode(it->Opcode);
1250 // We have a potential match but have not rendered the operands.
1251 // Check the target predicate to handle any context sensitive
1252 // constraints.
1253 // For example, Ties that are referenced multiple times must be
1254 // checked here to ensure the input is the same for each match
1255 // constraints. If we leave it any later the ties will have been
1256 // canonicalized
1257 unsigned MatchResult;
1258 if ((MatchResult = checkEarlyTargetMatchPredicate(Inst, Operands)) != Match_Success) {
1259 Inst.clear();
1260 DEBUG_WITH_TYPE(
1261 "asm-matcher",
1262 dbgs() << "Early target match predicate failed with diag code "
1263 << MatchResult << "\n");
1264 RetCode = MatchResult;
1265 HadMatchOtherThanPredicate = true;
1266 continue;
1267 }
1268
1269 if (matchingInlineAsm) {
1270 convertToMapAndConstraints(it->ConvertFn, Operands);
1271 if (!checkAsmTiedOperandConstraints(*this, it->ConvertFn, Operands,
1272 ErrorInfo))
1273 return Match_InvalidTiedOperand;
1274
1275 return Match_Success;
1276 }
1277
1278 // We have selected a definite instruction, convert the parsed
1279 // operands into the appropriate MCInst.
1280 convertToMCInst(it->ConvertFn, Inst, it->Opcode, Operands);
1281
1282 // We have a potential match. Check the target predicate to
1283 // handle any context sensitive constraints.
1284 if ((MatchResult = checkTargetMatchPredicate(Inst)) != Match_Success) {
1285 DEBUG_WITH_TYPE("asm-matcher",
1286 dbgs() << "Target match predicate failed with diag code "
1287 << MatchResult << "\n");
1288 Inst.clear();
1289 RetCode = MatchResult;
1290 HadMatchOtherThanPredicate = true;
1291 continue;
1292 }
1293
1294 if (!checkAsmTiedOperandConstraints(*this, it->ConvertFn, Operands,
1295 ErrorInfo))
1296 return Match_InvalidTiedOperand;
1297
1298 DEBUG_WITH_TYPE(
1299 "asm-matcher",
1300 dbgs() << "Opcode result: complete match, selecting this opcode\n");
1301 return Match_Success;
1302 }
1303
1304 // Okay, we had no match. Try to return a useful error code.
1305 if (HadMatchOtherThanPredicate || !HadMatchOtherThanFeatures)
1306 return RetCode;
1307
1308 ErrorInfo = 0;
1309 return Match_MissingFeature;
1310}
1311
1312#endif // GET_MATCHER_IMPLEMENTATION
1313
1314
1315#ifdef GET_MNEMONIC_SPELL_CHECKER
1316#undef GET_MNEMONIC_SPELL_CHECKER
1317
1318static std::string MSP430MnemonicSpellCheck(StringRef S, const FeatureBitset &FBS, unsigned VariantID) {
1319 const unsigned MaxEditDist = 2;
1320 std::vector<StringRef> Candidates;
1321 StringRef Prev = "";
1322
1323 // Find the appropriate table for this asm variant.
1324 const MatchEntry *Start, *End;
1325 switch (VariantID) {
1326 default: llvm_unreachable("invalid variant!");
1327 case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break;
1328 }
1329
1330 for (auto I = Start; I < End; I++) {
1331 // Ignore unsupported instructions.
1332 const FeatureBitset &RequiredFeatures = FeatureBitsets[I->RequiredFeaturesIdx];
1333 if ((FBS & RequiredFeatures) != RequiredFeatures)
1334 continue;
1335
1336 StringRef T = I->getMnemonic();
1337 // Avoid recomputing the edit distance for the same string.
1338 if (T == Prev)
1339 continue;
1340
1341 Prev = T;
1342 unsigned Dist = S.edit_distance(T, false, MaxEditDist);
1343 if (Dist <= MaxEditDist)
1344 Candidates.push_back(T);
1345 }
1346
1347 if (Candidates.empty())
1348 return "";
1349
1350 std::string Res = ", did you mean: ";
1351 unsigned i = 0;
1352 for (; i < Candidates.size() - 1; i++)
1353 Res += Candidates[i].str() + ", ";
1354 return Res + Candidates[i].str() + "?";
1355}
1356
1357#endif // GET_MNEMONIC_SPELL_CHECKER
1358
1359
1360#ifdef GET_MNEMONIC_CHECKER
1361#undef GET_MNEMONIC_CHECKER
1362
1363static bool MSP430CheckMnemonic(StringRef Mnemonic,
1364 const FeatureBitset &AvailableFeatures,
1365 unsigned VariantID) {
1366 // Find the appropriate table for this asm variant.
1367 const MatchEntry *Start, *End;
1368 switch (VariantID) {
1369 default: llvm_unreachable("invalid variant!");
1370 case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break;
1371 }
1372
1373 // Search the table.
1374 auto MnemonicRange = std::equal_range(Start, End, Mnemonic, LessOpcode());
1375
1376 if (MnemonicRange.first == MnemonicRange.second)
1377 return false;
1378
1379 for (const MatchEntry *it = MnemonicRange.first, *ie = MnemonicRange.second;
1380 it != ie; ++it) {
1381 const FeatureBitset &RequiredFeatures =
1382 FeatureBitsets[it->RequiredFeaturesIdx];
1383 if ((AvailableFeatures & RequiredFeatures) == RequiredFeatures)
1384 return true;
1385 }
1386 return false;
1387}
1388
1389#endif // GET_MNEMONIC_CHECKER
1390
1391