1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Instruction Enum Values and Descriptors *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_INSTRINFO_ENUM
10#undef GET_INSTRINFO_ENUM
11namespace llvm::MSP430 {
12 enum {
13 PHI = 0,
14 INLINEASM = 1,
15 INLINEASM_BR = 2,
16 CFI_INSTRUCTION = 3,
17 EH_LABEL = 4,
18 GC_LABEL = 5,
19 ANNOTATION_LABEL = 6,
20 KILL = 7,
21 EXTRACT_SUBREG = 8,
22 INSERT_SUBREG = 9,
23 IMPLICIT_DEF = 10,
24 INIT_UNDEF = 11,
25 SUBREG_TO_REG = 12,
26 COPY_TO_REGCLASS = 13,
27 DBG_VALUE = 14,
28 DBG_VALUE_LIST = 15,
29 DBG_INSTR_REF = 16,
30 DBG_PHI = 17,
31 DBG_LABEL = 18,
32 REG_SEQUENCE = 19,
33 COPY = 20,
34 BUNDLE = 21,
35 LIFETIME_START = 22,
36 LIFETIME_END = 23,
37 PSEUDO_PROBE = 24,
38 ARITH_FENCE = 25,
39 STACKMAP = 26,
40 FENTRY_CALL = 27,
41 PATCHPOINT = 28,
42 LOAD_STACK_GUARD = 29,
43 PREALLOCATED_SETUP = 30,
44 PREALLOCATED_ARG = 31,
45 STATEPOINT = 32,
46 LOCAL_ESCAPE = 33,
47 FAULTING_OP = 34,
48 PATCHABLE_OP = 35,
49 PATCHABLE_FUNCTION_ENTER = 36,
50 PATCHABLE_RET = 37,
51 PATCHABLE_FUNCTION_EXIT = 38,
52 PATCHABLE_TAIL_CALL = 39,
53 PATCHABLE_EVENT_CALL = 40,
54 PATCHABLE_TYPED_EVENT_CALL = 41,
55 ICALL_BRANCH_FUNNEL = 42,
56 FAKE_USE = 43,
57 MEMBARRIER = 44,
58 JUMP_TABLE_DEBUG_INFO = 45,
59 CONVERGENCECTRL_ENTRY = 46,
60 CONVERGENCECTRL_ANCHOR = 47,
61 CONVERGENCECTRL_LOOP = 48,
62 CONVERGENCECTRL_GLUE = 49,
63 G_ASSERT_SEXT = 50,
64 G_ASSERT_ZEXT = 51,
65 G_ASSERT_ALIGN = 52,
66 G_ADD = 53,
67 G_SUB = 54,
68 G_MUL = 55,
69 G_SDIV = 56,
70 G_UDIV = 57,
71 G_SREM = 58,
72 G_UREM = 59,
73 G_SDIVREM = 60,
74 G_UDIVREM = 61,
75 G_AND = 62,
76 G_OR = 63,
77 G_XOR = 64,
78 G_ABDS = 65,
79 G_ABDU = 66,
80 G_IMPLICIT_DEF = 67,
81 G_PHI = 68,
82 G_FRAME_INDEX = 69,
83 G_GLOBAL_VALUE = 70,
84 G_PTRAUTH_GLOBAL_VALUE = 71,
85 G_CONSTANT_POOL = 72,
86 G_EXTRACT = 73,
87 G_UNMERGE_VALUES = 74,
88 G_INSERT = 75,
89 G_MERGE_VALUES = 76,
90 G_BUILD_VECTOR = 77,
91 G_BUILD_VECTOR_TRUNC = 78,
92 G_CONCAT_VECTORS = 79,
93 G_PTRTOINT = 80,
94 G_INTTOPTR = 81,
95 G_BITCAST = 82,
96 G_FREEZE = 83,
97 G_CONSTANT_FOLD_BARRIER = 84,
98 G_INTRINSIC_FPTRUNC_ROUND = 85,
99 G_INTRINSIC_TRUNC = 86,
100 G_INTRINSIC_ROUND = 87,
101 G_INTRINSIC_LRINT = 88,
102 G_INTRINSIC_LLRINT = 89,
103 G_INTRINSIC_ROUNDEVEN = 90,
104 G_READCYCLECOUNTER = 91,
105 G_READSTEADYCOUNTER = 92,
106 G_LOAD = 93,
107 G_SEXTLOAD = 94,
108 G_ZEXTLOAD = 95,
109 G_INDEXED_LOAD = 96,
110 G_INDEXED_SEXTLOAD = 97,
111 G_INDEXED_ZEXTLOAD = 98,
112 G_STORE = 99,
113 G_INDEXED_STORE = 100,
114 G_ATOMIC_CMPXCHG_WITH_SUCCESS = 101,
115 G_ATOMIC_CMPXCHG = 102,
116 G_ATOMICRMW_XCHG = 103,
117 G_ATOMICRMW_ADD = 104,
118 G_ATOMICRMW_SUB = 105,
119 G_ATOMICRMW_AND = 106,
120 G_ATOMICRMW_NAND = 107,
121 G_ATOMICRMW_OR = 108,
122 G_ATOMICRMW_XOR = 109,
123 G_ATOMICRMW_MAX = 110,
124 G_ATOMICRMW_MIN = 111,
125 G_ATOMICRMW_UMAX = 112,
126 G_ATOMICRMW_UMIN = 113,
127 G_ATOMICRMW_FADD = 114,
128 G_ATOMICRMW_FSUB = 115,
129 G_ATOMICRMW_FMAX = 116,
130 G_ATOMICRMW_FMIN = 117,
131 G_ATOMICRMW_FMAXIMUM = 118,
132 G_ATOMICRMW_FMINIMUM = 119,
133 G_ATOMICRMW_UINC_WRAP = 120,
134 G_ATOMICRMW_UDEC_WRAP = 121,
135 G_ATOMICRMW_USUB_COND = 122,
136 G_ATOMICRMW_USUB_SAT = 123,
137 G_FENCE = 124,
138 G_PREFETCH = 125,
139 G_BRCOND = 126,
140 G_BRINDIRECT = 127,
141 G_INVOKE_REGION_START = 128,
142 G_INTRINSIC = 129,
143 G_INTRINSIC_W_SIDE_EFFECTS = 130,
144 G_INTRINSIC_CONVERGENT = 131,
145 G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 132,
146 G_ANYEXT = 133,
147 G_TRUNC = 134,
148 G_CONSTANT = 135,
149 G_FCONSTANT = 136,
150 G_VASTART = 137,
151 G_VAARG = 138,
152 G_SEXT = 139,
153 G_SEXT_INREG = 140,
154 G_ZEXT = 141,
155 G_SHL = 142,
156 G_LSHR = 143,
157 G_ASHR = 144,
158 G_FSHL = 145,
159 G_FSHR = 146,
160 G_ROTR = 147,
161 G_ROTL = 148,
162 G_ICMP = 149,
163 G_FCMP = 150,
164 G_SCMP = 151,
165 G_UCMP = 152,
166 G_SELECT = 153,
167 G_UADDO = 154,
168 G_UADDE = 155,
169 G_USUBO = 156,
170 G_USUBE = 157,
171 G_SADDO = 158,
172 G_SADDE = 159,
173 G_SSUBO = 160,
174 G_SSUBE = 161,
175 G_UMULO = 162,
176 G_SMULO = 163,
177 G_UMULH = 164,
178 G_SMULH = 165,
179 G_UADDSAT = 166,
180 G_SADDSAT = 167,
181 G_USUBSAT = 168,
182 G_SSUBSAT = 169,
183 G_USHLSAT = 170,
184 G_SSHLSAT = 171,
185 G_SMULFIX = 172,
186 G_UMULFIX = 173,
187 G_SMULFIXSAT = 174,
188 G_UMULFIXSAT = 175,
189 G_SDIVFIX = 176,
190 G_UDIVFIX = 177,
191 G_SDIVFIXSAT = 178,
192 G_UDIVFIXSAT = 179,
193 G_FADD = 180,
194 G_FSUB = 181,
195 G_FMUL = 182,
196 G_FMA = 183,
197 G_FMAD = 184,
198 G_FDIV = 185,
199 G_FREM = 186,
200 G_FPOW = 187,
201 G_FPOWI = 188,
202 G_FEXP = 189,
203 G_FEXP2 = 190,
204 G_FEXP10 = 191,
205 G_FLOG = 192,
206 G_FLOG2 = 193,
207 G_FLOG10 = 194,
208 G_FLDEXP = 195,
209 G_FFREXP = 196,
210 G_FNEG = 197,
211 G_FPEXT = 198,
212 G_FPTRUNC = 199,
213 G_FPTOSI = 200,
214 G_FPTOUI = 201,
215 G_SITOFP = 202,
216 G_UITOFP = 203,
217 G_FPTOSI_SAT = 204,
218 G_FPTOUI_SAT = 205,
219 G_FABS = 206,
220 G_FCOPYSIGN = 207,
221 G_IS_FPCLASS = 208,
222 G_FCANONICALIZE = 209,
223 G_FMINNUM = 210,
224 G_FMAXNUM = 211,
225 G_FMINNUM_IEEE = 212,
226 G_FMAXNUM_IEEE = 213,
227 G_FMINIMUM = 214,
228 G_FMAXIMUM = 215,
229 G_FMINIMUMNUM = 216,
230 G_FMAXIMUMNUM = 217,
231 G_GET_FPENV = 218,
232 G_SET_FPENV = 219,
233 G_RESET_FPENV = 220,
234 G_GET_FPMODE = 221,
235 G_SET_FPMODE = 222,
236 G_RESET_FPMODE = 223,
237 G_PTR_ADD = 224,
238 G_PTRMASK = 225,
239 G_SMIN = 226,
240 G_SMAX = 227,
241 G_UMIN = 228,
242 G_UMAX = 229,
243 G_ABS = 230,
244 G_LROUND = 231,
245 G_LLROUND = 232,
246 G_BR = 233,
247 G_BRJT = 234,
248 G_VSCALE = 235,
249 G_INSERT_SUBVECTOR = 236,
250 G_EXTRACT_SUBVECTOR = 237,
251 G_INSERT_VECTOR_ELT = 238,
252 G_EXTRACT_VECTOR_ELT = 239,
253 G_SHUFFLE_VECTOR = 240,
254 G_SPLAT_VECTOR = 241,
255 G_STEP_VECTOR = 242,
256 G_VECTOR_COMPRESS = 243,
257 G_CTTZ = 244,
258 G_CTTZ_ZERO_UNDEF = 245,
259 G_CTLZ = 246,
260 G_CTLZ_ZERO_UNDEF = 247,
261 G_CTPOP = 248,
262 G_BSWAP = 249,
263 G_BITREVERSE = 250,
264 G_FCEIL = 251,
265 G_FCOS = 252,
266 G_FSIN = 253,
267 G_FSINCOS = 254,
268 G_FTAN = 255,
269 G_FACOS = 256,
270 G_FASIN = 257,
271 G_FATAN = 258,
272 G_FATAN2 = 259,
273 G_FCOSH = 260,
274 G_FSINH = 261,
275 G_FTANH = 262,
276 G_FSQRT = 263,
277 G_FFLOOR = 264,
278 G_FRINT = 265,
279 G_FNEARBYINT = 266,
280 G_ADDRSPACE_CAST = 267,
281 G_BLOCK_ADDR = 268,
282 G_JUMP_TABLE = 269,
283 G_DYN_STACKALLOC = 270,
284 G_STACKSAVE = 271,
285 G_STACKRESTORE = 272,
286 G_STRICT_FADD = 273,
287 G_STRICT_FSUB = 274,
288 G_STRICT_FMUL = 275,
289 G_STRICT_FDIV = 276,
290 G_STRICT_FREM = 277,
291 G_STRICT_FMA = 278,
292 G_STRICT_FSQRT = 279,
293 G_STRICT_FLDEXP = 280,
294 G_READ_REGISTER = 281,
295 G_WRITE_REGISTER = 282,
296 G_MEMCPY = 283,
297 G_MEMCPY_INLINE = 284,
298 G_MEMMOVE = 285,
299 G_MEMSET = 286,
300 G_BZERO = 287,
301 G_TRAP = 288,
302 G_DEBUGTRAP = 289,
303 G_UBSANTRAP = 290,
304 G_VECREDUCE_SEQ_FADD = 291,
305 G_VECREDUCE_SEQ_FMUL = 292,
306 G_VECREDUCE_FADD = 293,
307 G_VECREDUCE_FMUL = 294,
308 G_VECREDUCE_FMAX = 295,
309 G_VECREDUCE_FMIN = 296,
310 G_VECREDUCE_FMAXIMUM = 297,
311 G_VECREDUCE_FMINIMUM = 298,
312 G_VECREDUCE_ADD = 299,
313 G_VECREDUCE_MUL = 300,
314 G_VECREDUCE_AND = 301,
315 G_VECREDUCE_OR = 302,
316 G_VECREDUCE_XOR = 303,
317 G_VECREDUCE_SMAX = 304,
318 G_VECREDUCE_SMIN = 305,
319 G_VECREDUCE_UMAX = 306,
320 G_VECREDUCE_UMIN = 307,
321 G_SBFX = 308,
322 G_UBFX = 309,
323 ADD16mc = 310,
324 ADD16mi = 311,
325 ADD16mm = 312,
326 ADD16mn = 313,
327 ADD16mp = 314,
328 ADD16mr = 315,
329 ADD16rc = 316,
330 ADD16ri = 317,
331 ADD16rm = 318,
332 ADD16rn = 319,
333 ADD16rp = 320,
334 ADD16rr = 321,
335 ADD8mc = 322,
336 ADD8mi = 323,
337 ADD8mm = 324,
338 ADD8mn = 325,
339 ADD8mp = 326,
340 ADD8mr = 327,
341 ADD8rc = 328,
342 ADD8ri = 329,
343 ADD8rm = 330,
344 ADD8rn = 331,
345 ADD8rp = 332,
346 ADD8rr = 333,
347 ADDC16mc = 334,
348 ADDC16mi = 335,
349 ADDC16mm = 336,
350 ADDC16mn = 337,
351 ADDC16mp = 338,
352 ADDC16mr = 339,
353 ADDC16rc = 340,
354 ADDC16ri = 341,
355 ADDC16rm = 342,
356 ADDC16rn = 343,
357 ADDC16rp = 344,
358 ADDC16rr = 345,
359 ADDC8mc = 346,
360 ADDC8mi = 347,
361 ADDC8mm = 348,
362 ADDC8mn = 349,
363 ADDC8mp = 350,
364 ADDC8mr = 351,
365 ADDC8rc = 352,
366 ADDC8ri = 353,
367 ADDC8rm = 354,
368 ADDC8rn = 355,
369 ADDC8rp = 356,
370 ADDC8rr = 357,
371 ADDframe = 358,
372 ADJCALLSTACKDOWN = 359,
373 ADJCALLSTACKUP = 360,
374 AND16mc = 361,
375 AND16mi = 362,
376 AND16mm = 363,
377 AND16mn = 364,
378 AND16mp = 365,
379 AND16mr = 366,
380 AND16rc = 367,
381 AND16ri = 368,
382 AND16rm = 369,
383 AND16rn = 370,
384 AND16rp = 371,
385 AND16rr = 372,
386 AND8mc = 373,
387 AND8mi = 374,
388 AND8mm = 375,
389 AND8mn = 376,
390 AND8mp = 377,
391 AND8mr = 378,
392 AND8rc = 379,
393 AND8ri = 380,
394 AND8rm = 381,
395 AND8rn = 382,
396 AND8rp = 383,
397 AND8rr = 384,
398 BIC16mc = 385,
399 BIC16mi = 386,
400 BIC16mm = 387,
401 BIC16mn = 388,
402 BIC16mp = 389,
403 BIC16mr = 390,
404 BIC16rc = 391,
405 BIC16ri = 392,
406 BIC16rm = 393,
407 BIC16rn = 394,
408 BIC16rp = 395,
409 BIC16rr = 396,
410 BIC8mc = 397,
411 BIC8mi = 398,
412 BIC8mm = 399,
413 BIC8mn = 400,
414 BIC8mp = 401,
415 BIC8mr = 402,
416 BIC8rc = 403,
417 BIC8ri = 404,
418 BIC8rm = 405,
419 BIC8rn = 406,
420 BIC8rp = 407,
421 BIC8rr = 408,
422 BIS16mc = 409,
423 BIS16mi = 410,
424 BIS16mm = 411,
425 BIS16mn = 412,
426 BIS16mp = 413,
427 BIS16mr = 414,
428 BIS16rc = 415,
429 BIS16ri = 416,
430 BIS16rm = 417,
431 BIS16rn = 418,
432 BIS16rp = 419,
433 BIS16rr = 420,
434 BIS8mc = 421,
435 BIS8mi = 422,
436 BIS8mm = 423,
437 BIS8mn = 424,
438 BIS8mp = 425,
439 BIS8mr = 426,
440 BIS8rc = 427,
441 BIS8ri = 428,
442 BIS8rm = 429,
443 BIS8rn = 430,
444 BIS8rp = 431,
445 BIS8rr = 432,
446 BIT16mc = 433,
447 BIT16mi = 434,
448 BIT16mm = 435,
449 BIT16mn = 436,
450 BIT16mp = 437,
451 BIT16mr = 438,
452 BIT16rc = 439,
453 BIT16ri = 440,
454 BIT16rm = 441,
455 BIT16rn = 442,
456 BIT16rp = 443,
457 BIT16rr = 444,
458 BIT8mc = 445,
459 BIT8mi = 446,
460 BIT8mm = 447,
461 BIT8mn = 448,
462 BIT8mp = 449,
463 BIT8mr = 450,
464 BIT8rc = 451,
465 BIT8ri = 452,
466 BIT8rm = 453,
467 BIT8rn = 454,
468 BIT8rp = 455,
469 BIT8rr = 456,
470 Bi = 457,
471 Bm = 458,
472 Br = 459,
473 CALLi = 460,
474 CALLm = 461,
475 CALLn = 462,
476 CALLp = 463,
477 CALLr = 464,
478 CMP16mc = 465,
479 CMP16mi = 466,
480 CMP16mm = 467,
481 CMP16mn = 468,
482 CMP16mp = 469,
483 CMP16mr = 470,
484 CMP16rc = 471,
485 CMP16ri = 472,
486 CMP16rm = 473,
487 CMP16rn = 474,
488 CMP16rp = 475,
489 CMP16rr = 476,
490 CMP8mc = 477,
491 CMP8mi = 478,
492 CMP8mm = 479,
493 CMP8mn = 480,
494 CMP8mp = 481,
495 CMP8mr = 482,
496 CMP8rc = 483,
497 CMP8ri = 484,
498 CMP8rm = 485,
499 CMP8rn = 486,
500 CMP8rp = 487,
501 CMP8rr = 488,
502 DADD16mc = 489,
503 DADD16mi = 490,
504 DADD16mm = 491,
505 DADD16mn = 492,
506 DADD16mp = 493,
507 DADD16mr = 494,
508 DADD16rc = 495,
509 DADD16ri = 496,
510 DADD16rm = 497,
511 DADD16rn = 498,
512 DADD16rp = 499,
513 DADD16rr = 500,
514 DADD8mc = 501,
515 DADD8mi = 502,
516 DADD8mm = 503,
517 DADD8mn = 504,
518 DADD8mp = 505,
519 DADD8mr = 506,
520 DADD8rc = 507,
521 DADD8ri = 508,
522 DADD8rm = 509,
523 DADD8rn = 510,
524 DADD8rp = 511,
525 DADD8rr = 512,
526 JCC = 513,
527 JMP = 514,
528 MOV16mc = 515,
529 MOV16mi = 516,
530 MOV16mm = 517,
531 MOV16mn = 518,
532 MOV16mr = 519,
533 MOV16rc = 520,
534 MOV16ri = 521,
535 MOV16rm = 522,
536 MOV16rn = 523,
537 MOV16rp = 524,
538 MOV16rr = 525,
539 MOV8mc = 526,
540 MOV8mi = 527,
541 MOV8mm = 528,
542 MOV8mn = 529,
543 MOV8mr = 530,
544 MOV8rc = 531,
545 MOV8ri = 532,
546 MOV8rm = 533,
547 MOV8rn = 534,
548 MOV8rp = 535,
549 MOV8rr = 536,
550 MOVZX16rm8 = 537,
551 MOVZX16rr8 = 538,
552 POP16r = 539,
553 PUSH16c = 540,
554 PUSH16i = 541,
555 PUSH16r = 542,
556 PUSH8r = 543,
557 RET = 544,
558 RETI = 545,
559 RRA16m = 546,
560 RRA16n = 547,
561 RRA16p = 548,
562 RRA16r = 549,
563 RRA8m = 550,
564 RRA8n = 551,
565 RRA8p = 552,
566 RRA8r = 553,
567 RRC16m = 554,
568 RRC16n = 555,
569 RRC16p = 556,
570 RRC16r = 557,
571 RRC8m = 558,
572 RRC8n = 559,
573 RRC8p = 560,
574 RRC8r = 561,
575 Rrcl16 = 562,
576 Rrcl8 = 563,
577 SEXT16m = 564,
578 SEXT16n = 565,
579 SEXT16p = 566,
580 SEXT16r = 567,
581 SUB16mc = 568,
582 SUB16mi = 569,
583 SUB16mm = 570,
584 SUB16mn = 571,
585 SUB16mp = 572,
586 SUB16mr = 573,
587 SUB16rc = 574,
588 SUB16ri = 575,
589 SUB16rm = 576,
590 SUB16rn = 577,
591 SUB16rp = 578,
592 SUB16rr = 579,
593 SUB8mc = 580,
594 SUB8mi = 581,
595 SUB8mm = 582,
596 SUB8mn = 583,
597 SUB8mp = 584,
598 SUB8mr = 585,
599 SUB8rc = 586,
600 SUB8ri = 587,
601 SUB8rm = 588,
602 SUB8rn = 589,
603 SUB8rp = 590,
604 SUB8rr = 591,
605 SUBC16mc = 592,
606 SUBC16mi = 593,
607 SUBC16mm = 594,
608 SUBC16mn = 595,
609 SUBC16mp = 596,
610 SUBC16mr = 597,
611 SUBC16rc = 598,
612 SUBC16ri = 599,
613 SUBC16rm = 600,
614 SUBC16rn = 601,
615 SUBC16rp = 602,
616 SUBC16rr = 603,
617 SUBC8mc = 604,
618 SUBC8mi = 605,
619 SUBC8mm = 606,
620 SUBC8mn = 607,
621 SUBC8mp = 608,
622 SUBC8mr = 609,
623 SUBC8rc = 610,
624 SUBC8ri = 611,
625 SUBC8rm = 612,
626 SUBC8rn = 613,
627 SUBC8rp = 614,
628 SUBC8rr = 615,
629 SWPB16m = 616,
630 SWPB16n = 617,
631 SWPB16p = 618,
632 SWPB16r = 619,
633 Select16 = 620,
634 Select8 = 621,
635 Shl16 = 622,
636 Shl8 = 623,
637 Sra16 = 624,
638 Sra8 = 625,
639 Srl16 = 626,
640 Srl8 = 627,
641 XOR16mc = 628,
642 XOR16mi = 629,
643 XOR16mm = 630,
644 XOR16mn = 631,
645 XOR16mp = 632,
646 XOR16mr = 633,
647 XOR16rc = 634,
648 XOR16ri = 635,
649 XOR16rm = 636,
650 XOR16rn = 637,
651 XOR16rp = 638,
652 XOR16rr = 639,
653 XOR8mc = 640,
654 XOR8mi = 641,
655 XOR8mm = 642,
656 XOR8mn = 643,
657 XOR8mp = 644,
658 XOR8mr = 645,
659 XOR8rc = 646,
660 XOR8ri = 647,
661 XOR8rm = 648,
662 XOR8rn = 649,
663 XOR8rp = 650,
664 XOR8rr = 651,
665 ZEXT16r = 652,
666 INSTRUCTION_LIST_END = 653
667 };
668
669} // end namespace llvm::MSP430
670#endif // GET_INSTRINFO_ENUM
671
672#ifdef GET_INSTRINFO_SCHED_ENUM
673#undef GET_INSTRINFO_SCHED_ENUM
674namespace llvm::MSP430::Sched {
675
676 enum {
677 NoInstrModel = 0,
678 SCHED_LIST_END = 1
679 };
680} // end namespace llvm::MSP430::Sched
681#endif // GET_INSTRINFO_SCHED_ENUM
682
683#if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
684namespace llvm {
685
686struct MSP430InstrTable {
687 MCInstrDesc Insts[653];
688 static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo");
689 MCOperandInfo OperandInfo[267];
690 static_assert(alignof(MCOperandInfo) >= alignof(MCPhysReg), "Unwanted padding between OperandInfo and ImplicitOps");
691 MCPhysReg ImplicitOps[17];
692};
693
694} // end namespace llvm
695#endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
696
697#ifdef GET_INSTRINFO_MC_DESC
698#undef GET_INSTRINFO_MC_DESC
699namespace llvm {
700
701static_assert(sizeof(MCOperandInfo) % sizeof(MCPhysReg) == 0);
702static constexpr unsigned MSP430ImpOpBase = sizeof MSP430InstrTable::OperandInfo / (sizeof(MCPhysReg));
703
704extern const MSP430InstrTable MSP430Descs = {
705 {
706 { 652, 2, 1, 2, 0, 0, 0, 249, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #652 = ZEXT16r
707 { 651, 3, 1, 2, 0, 0, 1, 208, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #651 = XOR8rr
708 { 650, 4, 2, 2, 0, 0, 1, 204, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #650 = XOR8rp
709 { 649, 3, 1, 2, 0, 0, 1, 201, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #649 = XOR8rn
710 { 648, 4, 1, 4, 0, 0, 1, 197, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #648 = XOR8rm
711 { 647, 3, 1, 4, 0, 0, 1, 194, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #647 = XOR8ri
712 { 646, 3, 1, 2, 0, 0, 1, 191, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #646 = XOR8rc
713 { 645, 3, 0, 4, 0, 0, 1, 188, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #645 = XOR8mr
714 { 644, 3, 0, 4, 0, 0, 1, 162, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #644 = XOR8mp
715 { 643, 3, 0, 4, 0, 0, 1, 162, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #643 = XOR8mn
716 { 642, 4, 0, 6, 0, 0, 1, 158, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #642 = XOR8mm
717 { 641, 3, 0, 6, 0, 0, 1, 155, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #641 = XOR8mi
718 { 640, 3, 0, 4, 0, 0, 1, 152, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #640 = XOR8mc
719 { 639, 3, 1, 2, 0, 0, 1, 185, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #639 = XOR16rr
720 { 638, 4, 2, 2, 0, 0, 1, 181, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #638 = XOR16rp
721 { 637, 3, 1, 2, 0, 0, 1, 178, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #637 = XOR16rn
722 { 636, 4, 1, 4, 0, 0, 1, 174, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #636 = XOR16rm
723 { 635, 3, 1, 4, 0, 0, 1, 171, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #635 = XOR16ri
724 { 634, 3, 1, 2, 0, 0, 1, 168, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #634 = XOR16rc
725 { 633, 3, 0, 4, 0, 0, 1, 165, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #633 = XOR16mr
726 { 632, 3, 0, 4, 0, 0, 1, 162, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #632 = XOR16mp
727 { 631, 3, 0, 4, 0, 0, 1, 162, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #631 = XOR16mn
728 { 630, 4, 0, 6, 0, 0, 1, 158, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #630 = XOR16mm
729 { 629, 3, 0, 6, 0, 0, 1, 155, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #629 = XOR16mi
730 { 628, 3, 0, 4, 0, 0, 1, 152, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #628 = XOR16mc
731 { 627, 3, 1, 0, 0, 0, 1, 264, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #627 = Srl8
732 { 626, 3, 1, 0, 0, 0, 1, 261, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #626 = Srl16
733 { 625, 3, 1, 0, 0, 0, 1, 264, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #625 = Sra8
734 { 624, 3, 1, 0, 0, 0, 1, 261, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #624 = Sra16
735 { 623, 3, 1, 0, 0, 0, 1, 264, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #623 = Shl8
736 { 622, 3, 1, 0, 0, 0, 1, 261, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #622 = Shl16
737 { 621, 4, 1, 0, 0, 1, 0, 257, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #621 = Select8
738 { 620, 4, 1, 0, 0, 1, 0, 253, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #620 = Select16
739 { 619, 2, 1, 2, 0, 0, 0, 249, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #619 = SWPB16r
740 { 618, 1, 0, 2, 0, 0, 0, 239, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #618 = SWPB16p
741 { 617, 1, 0, 2, 0, 0, 0, 239, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #617 = SWPB16n
742 { 616, 2, 0, 4, 0, 0, 0, 236, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #616 = SWPB16m
743 { 615, 3, 1, 2, 0, 1, 1, 208, MSP430ImpOpBase + 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #615 = SUBC8rr
744 { 614, 4, 2, 2, 0, 1, 1, 204, MSP430ImpOpBase + 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #614 = SUBC8rp
745 { 613, 3, 1, 2, 0, 1, 1, 201, MSP430ImpOpBase + 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #613 = SUBC8rn
746 { 612, 4, 1, 4, 0, 1, 1, 197, MSP430ImpOpBase + 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #612 = SUBC8rm
747 { 611, 3, 1, 4, 0, 1, 1, 194, MSP430ImpOpBase + 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #611 = SUBC8ri
748 { 610, 3, 1, 2, 0, 1, 1, 191, MSP430ImpOpBase + 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #610 = SUBC8rc
749 { 609, 3, 0, 4, 0, 1, 1, 188, MSP430ImpOpBase + 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #609 = SUBC8mr
750 { 608, 3, 0, 4, 0, 1, 1, 162, MSP430ImpOpBase + 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #608 = SUBC8mp
751 { 607, 3, 0, 4, 0, 1, 1, 162, MSP430ImpOpBase + 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #607 = SUBC8mn
752 { 606, 4, 0, 6, 0, 1, 1, 158, MSP430ImpOpBase + 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #606 = SUBC8mm
753 { 605, 3, 0, 6, 0, 1, 1, 155, MSP430ImpOpBase + 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #605 = SUBC8mi
754 { 604, 3, 0, 4, 0, 1, 1, 152, MSP430ImpOpBase + 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #604 = SUBC8mc
755 { 603, 3, 1, 2, 0, 1, 1, 185, MSP430ImpOpBase + 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #603 = SUBC16rr
756 { 602, 4, 2, 2, 0, 1, 1, 181, MSP430ImpOpBase + 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #602 = SUBC16rp
757 { 601, 3, 1, 2, 0, 1, 1, 178, MSP430ImpOpBase + 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #601 = SUBC16rn
758 { 600, 4, 1, 4, 0, 1, 1, 174, MSP430ImpOpBase + 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #600 = SUBC16rm
759 { 599, 3, 1, 4, 0, 1, 1, 171, MSP430ImpOpBase + 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #599 = SUBC16ri
760 { 598, 3, 1, 2, 0, 1, 1, 168, MSP430ImpOpBase + 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #598 = SUBC16rc
761 { 597, 3, 0, 4, 0, 1, 1, 165, MSP430ImpOpBase + 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #597 = SUBC16mr
762 { 596, 3, 0, 4, 0, 1, 1, 162, MSP430ImpOpBase + 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #596 = SUBC16mp
763 { 595, 3, 0, 4, 0, 1, 1, 162, MSP430ImpOpBase + 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #595 = SUBC16mn
764 { 594, 4, 0, 6, 0, 1, 1, 158, MSP430ImpOpBase + 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #594 = SUBC16mm
765 { 593, 3, 0, 6, 0, 1, 1, 155, MSP430ImpOpBase + 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #593 = SUBC16mi
766 { 592, 3, 0, 4, 0, 1, 1, 152, MSP430ImpOpBase + 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #592 = SUBC16mc
767 { 591, 3, 1, 2, 0, 0, 1, 208, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #591 = SUB8rr
768 { 590, 4, 2, 2, 0, 0, 1, 204, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #590 = SUB8rp
769 { 589, 3, 1, 2, 0, 0, 1, 201, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #589 = SUB8rn
770 { 588, 4, 1, 4, 0, 0, 1, 197, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #588 = SUB8rm
771 { 587, 3, 1, 4, 0, 0, 1, 194, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #587 = SUB8ri
772 { 586, 3, 1, 2, 0, 0, 1, 191, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #586 = SUB8rc
773 { 585, 3, 0, 4, 0, 0, 1, 188, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #585 = SUB8mr
774 { 584, 3, 0, 4, 0, 0, 1, 162, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #584 = SUB8mp
775 { 583, 3, 0, 4, 0, 0, 1, 162, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #583 = SUB8mn
776 { 582, 4, 0, 6, 0, 0, 1, 158, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #582 = SUB8mm
777 { 581, 3, 0, 6, 0, 0, 1, 155, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #581 = SUB8mi
778 { 580, 3, 0, 4, 0, 0, 1, 152, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #580 = SUB8mc
779 { 579, 3, 1, 2, 0, 0, 1, 185, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #579 = SUB16rr
780 { 578, 4, 2, 2, 0, 0, 1, 181, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #578 = SUB16rp
781 { 577, 3, 1, 2, 0, 0, 1, 178, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #577 = SUB16rn
782 { 576, 4, 1, 4, 0, 0, 1, 174, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #576 = SUB16rm
783 { 575, 3, 1, 4, 0, 0, 1, 171, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #575 = SUB16ri
784 { 574, 3, 1, 2, 0, 0, 1, 168, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #574 = SUB16rc
785 { 573, 3, 0, 4, 0, 0, 1, 165, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #573 = SUB16mr
786 { 572, 3, 0, 4, 0, 0, 1, 162, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #572 = SUB16mp
787 { 571, 3, 0, 4, 0, 0, 1, 162, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #571 = SUB16mn
788 { 570, 4, 0, 6, 0, 0, 1, 158, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #570 = SUB16mm
789 { 569, 3, 0, 6, 0, 0, 1, 155, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #569 = SUB16mi
790 { 568, 3, 0, 4, 0, 0, 1, 152, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #568 = SUB16mc
791 { 567, 2, 1, 2, 0, 0, 1, 249, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #567 = SEXT16r
792 { 566, 1, 0, 2, 0, 0, 1, 239, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #566 = SEXT16p
793 { 565, 1, 0, 2, 0, 0, 1, 239, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #565 = SEXT16n
794 { 564, 2, 0, 4, 0, 0, 1, 236, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #564 = SEXT16m
795 { 563, 2, 1, 0, 0, 0, 1, 234, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #563 = Rrcl8
796 { 562, 2, 1, 0, 0, 0, 1, 223, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #562 = Rrcl16
797 { 561, 2, 1, 2, 0, 1, 1, 251, MSP430ImpOpBase + 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #561 = RRC8r
798 { 560, 1, 0, 2, 0, 1, 1, 239, MSP430ImpOpBase + 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #560 = RRC8p
799 { 559, 1, 0, 2, 0, 1, 1, 239, MSP430ImpOpBase + 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #559 = RRC8n
800 { 558, 2, 0, 4, 0, 1, 1, 236, MSP430ImpOpBase + 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #558 = RRC8m
801 { 557, 2, 1, 2, 0, 1, 1, 249, MSP430ImpOpBase + 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #557 = RRC16r
802 { 556, 1, 0, 2, 0, 1, 1, 239, MSP430ImpOpBase + 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #556 = RRC16p
803 { 555, 1, 0, 2, 0, 1, 1, 239, MSP430ImpOpBase + 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #555 = RRC16n
804 { 554, 2, 0, 4, 0, 1, 1, 236, MSP430ImpOpBase + 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #554 = RRC16m
805 { 553, 2, 1, 2, 0, 0, 1, 251, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #553 = RRA8r
806 { 552, 1, 0, 2, 0, 0, 1, 239, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #552 = RRA8p
807 { 551, 1, 0, 2, 0, 0, 1, 239, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #551 = RRA8n
808 { 550, 2, 0, 4, 0, 0, 1, 236, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #550 = RRA8m
809 { 549, 2, 1, 2, 0, 0, 1, 249, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #549 = RRA16r
810 { 548, 1, 0, 2, 0, 0, 1, 239, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #548 = RRA16p
811 { 547, 1, 0, 2, 0, 0, 1, 239, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #547 = RRA16n
812 { 546, 2, 0, 4, 0, 0, 1, 236, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #546 = RRA16m
813 { 545, 0, 0, 2, 0, 0, 0, 1, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #545 = RETI
814 { 544, 0, 0, 2, 0, 0, 0, 1, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #544 = RET
815 { 543, 1, 0, 2, 0, 1, 1, 248, MSP430ImpOpBase + 15, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #543 = PUSH8r
816 { 542, 1, 0, 2, 0, 1, 1, 238, MSP430ImpOpBase + 15, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #542 = PUSH16r
817 { 541, 1, 0, 4, 0, 1, 1, 1, MSP430ImpOpBase + 15, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #541 = PUSH16i
818 { 540, 1, 0, 2, 0, 1, 1, 0, MSP430ImpOpBase + 15, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #540 = PUSH16c
819 { 539, 1, 1, 2, 0, 1, 1, 238, MSP430ImpOpBase + 15, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #539 = POP16r
820 { 538, 2, 1, 2, 0, 0, 0, 246, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #538 = MOVZX16rr8
821 { 537, 3, 1, 4, 0, 0, 0, 218, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #537 = MOVZX16rm8
822 { 536, 2, 1, 2, 0, 0, 0, 234, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #536 = MOV8rr
823 { 535, 3, 2, 2, 0, 0, 0, 243, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #535 = MOV8rp
824 { 534, 2, 1, 2, 0, 0, 0, 232, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #534 = MOV8rn
825 { 533, 3, 1, 4, 0, 0, 0, 229, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #533 = MOV8rm
826 { 532, 2, 1, 4, 0, 0, 0, 227, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #532 = MOV8ri
827 { 531, 2, 1, 2, 0, 0, 0, 225, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #531 = MOV8rc
828 { 530, 3, 0, 4, 0, 0, 0, 188, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #530 = MOV8mr
829 { 529, 3, 0, 4, 0, 0, 0, 162, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #529 = MOV8mn
830 { 528, 4, 0, 6, 0, 0, 0, 158, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #528 = MOV8mm
831 { 527, 3, 0, 6, 0, 0, 0, 155, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #527 = MOV8mi
832 { 526, 3, 0, 4, 0, 0, 0, 152, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #526 = MOV8mc
833 { 525, 2, 1, 2, 0, 0, 0, 223, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #525 = MOV16rr
834 { 524, 3, 2, 2, 0, 0, 0, 240, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #524 = MOV16rp
835 { 523, 2, 1, 2, 0, 0, 0, 221, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #523 = MOV16rn
836 { 522, 3, 1, 4, 0, 0, 0, 218, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #522 = MOV16rm
837 { 521, 2, 1, 4, 0, 0, 0, 216, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #521 = MOV16ri
838 { 520, 2, 1, 2, 0, 0, 0, 214, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #520 = MOV16rc
839 { 519, 3, 0, 4, 0, 0, 0, 165, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #519 = MOV16mr
840 { 518, 3, 0, 4, 0, 0, 0, 162, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #518 = MOV16mn
841 { 517, 4, 0, 6, 0, 0, 0, 158, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #517 = MOV16mm
842 { 516, 3, 0, 6, 0, 0, 0, 155, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #516 = MOV16mi
843 { 515, 3, 0, 4, 0, 0, 0, 152, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #515 = MOV16mc
844 { 514, 1, 0, 2, 0, 0, 0, 0, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #514 = JMP
845 { 513, 2, 0, 2, 0, 1, 0, 13, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #513 = JCC
846 { 512, 3, 1, 2, 0, 1, 1, 208, MSP430ImpOpBase + 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #512 = DADD8rr
847 { 511, 4, 2, 2, 0, 1, 1, 204, MSP430ImpOpBase + 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #511 = DADD8rp
848 { 510, 3, 1, 2, 0, 1, 1, 201, MSP430ImpOpBase + 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #510 = DADD8rn
849 { 509, 4, 1, 4, 0, 1, 1, 197, MSP430ImpOpBase + 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #509 = DADD8rm
850 { 508, 3, 1, 4, 0, 1, 1, 194, MSP430ImpOpBase + 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #508 = DADD8ri
851 { 507, 3, 1, 2, 0, 1, 1, 191, MSP430ImpOpBase + 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #507 = DADD8rc
852 { 506, 3, 0, 4, 0, 1, 1, 188, MSP430ImpOpBase + 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #506 = DADD8mr
853 { 505, 3, 0, 4, 0, 1, 1, 162, MSP430ImpOpBase + 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #505 = DADD8mp
854 { 504, 3, 0, 4, 0, 1, 1, 162, MSP430ImpOpBase + 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #504 = DADD8mn
855 { 503, 4, 0, 6, 0, 1, 1, 158, MSP430ImpOpBase + 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #503 = DADD8mm
856 { 502, 3, 0, 6, 0, 1, 1, 155, MSP430ImpOpBase + 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #502 = DADD8mi
857 { 501, 3, 0, 4, 0, 1, 1, 152, MSP430ImpOpBase + 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #501 = DADD8mc
858 { 500, 3, 1, 2, 0, 1, 1, 185, MSP430ImpOpBase + 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #500 = DADD16rr
859 { 499, 4, 2, 2, 0, 1, 1, 181, MSP430ImpOpBase + 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #499 = DADD16rp
860 { 498, 3, 1, 2, 0, 1, 1, 178, MSP430ImpOpBase + 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #498 = DADD16rn
861 { 497, 4, 1, 4, 0, 1, 1, 174, MSP430ImpOpBase + 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #497 = DADD16rm
862 { 496, 3, 1, 4, 0, 1, 1, 171, MSP430ImpOpBase + 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #496 = DADD16ri
863 { 495, 3, 1, 2, 0, 1, 1, 168, MSP430ImpOpBase + 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #495 = DADD16rc
864 { 494, 3, 0, 4, 0, 1, 1, 165, MSP430ImpOpBase + 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #494 = DADD16mr
865 { 493, 3, 0, 4, 0, 1, 1, 162, MSP430ImpOpBase + 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #493 = DADD16mp
866 { 492, 3, 0, 4, 0, 1, 1, 162, MSP430ImpOpBase + 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #492 = DADD16mn
867 { 491, 4, 0, 6, 0, 1, 1, 158, MSP430ImpOpBase + 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #491 = DADD16mm
868 { 490, 3, 0, 6, 0, 1, 1, 155, MSP430ImpOpBase + 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #490 = DADD16mi
869 { 489, 3, 0, 4, 0, 1, 1, 152, MSP430ImpOpBase + 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #489 = DADD16mc
870 { 488, 2, 0, 2, 0, 0, 1, 234, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #488 = CMP8rr
871 { 487, 2, 0, 2, 0, 0, 1, 232, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #487 = CMP8rp
872 { 486, 2, 0, 2, 0, 0, 1, 232, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #486 = CMP8rn
873 { 485, 3, 0, 4, 0, 0, 1, 229, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #485 = CMP8rm
874 { 484, 2, 0, 4, 0, 0, 1, 227, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #484 = CMP8ri
875 { 483, 2, 0, 2, 0, 0, 1, 225, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #483 = CMP8rc
876 { 482, 3, 0, 4, 0, 0, 1, 188, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #482 = CMP8mr
877 { 481, 3, 0, 4, 0, 0, 1, 162, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #481 = CMP8mp
878 { 480, 3, 0, 4, 0, 0, 1, 162, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #480 = CMP8mn
879 { 479, 4, 0, 6, 0, 0, 1, 158, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #479 = CMP8mm
880 { 478, 3, 0, 6, 0, 0, 1, 155, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #478 = CMP8mi
881 { 477, 3, 0, 4, 0, 0, 1, 152, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #477 = CMP8mc
882 { 476, 2, 0, 2, 0, 0, 1, 223, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #476 = CMP16rr
883 { 475, 2, 0, 2, 0, 0, 1, 221, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #475 = CMP16rp
884 { 474, 2, 0, 2, 0, 0, 1, 221, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #474 = CMP16rn
885 { 473, 3, 0, 4, 0, 0, 1, 218, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #473 = CMP16rm
886 { 472, 2, 0, 4, 0, 0, 1, 216, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #472 = CMP16ri
887 { 471, 2, 0, 2, 0, 0, 1, 214, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #471 = CMP16rc
888 { 470, 3, 0, 4, 0, 0, 1, 165, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #470 = CMP16mr
889 { 469, 3, 0, 4, 0, 0, 1, 162, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #469 = CMP16mp
890 { 468, 3, 0, 4, 0, 0, 1, 162, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #468 = CMP16mn
891 { 467, 4, 0, 6, 0, 0, 1, 158, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #467 = CMP16mm
892 { 466, 3, 0, 6, 0, 0, 1, 155, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #466 = CMP16mi
893 { 465, 3, 0, 4, 0, 0, 1, 152, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #465 = CMP16mc
894 { 464, 1, 0, 2, 0, 1, 6, 238, MSP430ImpOpBase + 8, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #464 = CALLr
895 { 463, 1, 0, 2, 0, 1, 6, 239, MSP430ImpOpBase + 8, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #463 = CALLp
896 { 462, 1, 0, 2, 0, 1, 6, 239, MSP430ImpOpBase + 8, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #462 = CALLn
897 { 461, 2, 0, 4, 0, 1, 6, 236, MSP430ImpOpBase + 8, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #461 = CALLm
898 { 460, 1, 0, 4, 0, 1, 6, 1, MSP430ImpOpBase + 8, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #460 = CALLi
899 { 459, 1, 0, 2, 0, 0, 0, 238, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #459 = Br
900 { 458, 2, 0, 4, 0, 0, 0, 236, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #458 = Bm
901 { 457, 1, 0, 4, 0, 0, 0, 1, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #457 = Bi
902 { 456, 2, 0, 2, 0, 0, 1, 234, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #456 = BIT8rr
903 { 455, 2, 0, 2, 0, 0, 1, 232, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #455 = BIT8rp
904 { 454, 2, 0, 2, 0, 0, 1, 232, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #454 = BIT8rn
905 { 453, 3, 0, 4, 0, 0, 1, 229, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #453 = BIT8rm
906 { 452, 2, 0, 4, 0, 0, 1, 227, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #452 = BIT8ri
907 { 451, 2, 0, 2, 0, 0, 1, 225, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #451 = BIT8rc
908 { 450, 3, 0, 4, 0, 0, 1, 188, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #450 = BIT8mr
909 { 449, 3, 0, 4, 0, 0, 1, 162, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #449 = BIT8mp
910 { 448, 3, 0, 4, 0, 0, 1, 162, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #448 = BIT8mn
911 { 447, 4, 0, 6, 0, 0, 1, 158, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #447 = BIT8mm
912 { 446, 3, 0, 6, 0, 0, 1, 155, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #446 = BIT8mi
913 { 445, 3, 0, 4, 0, 0, 1, 152, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #445 = BIT8mc
914 { 444, 2, 0, 2, 0, 0, 1, 223, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #444 = BIT16rr
915 { 443, 2, 0, 2, 0, 0, 1, 221, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #443 = BIT16rp
916 { 442, 2, 0, 2, 0, 0, 1, 221, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #442 = BIT16rn
917 { 441, 3, 0, 4, 0, 0, 1, 218, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #441 = BIT16rm
918 { 440, 2, 0, 4, 0, 0, 1, 216, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #440 = BIT16ri
919 { 439, 2, 0, 2, 0, 0, 1, 214, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #439 = BIT16rc
920 { 438, 3, 0, 4, 0, 0, 1, 165, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #438 = BIT16mr
921 { 437, 3, 0, 4, 0, 0, 1, 162, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #437 = BIT16mp
922 { 436, 3, 0, 4, 0, 0, 1, 162, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #436 = BIT16mn
923 { 435, 4, 0, 6, 0, 0, 1, 158, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #435 = BIT16mm
924 { 434, 3, 0, 6, 0, 0, 1, 155, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #434 = BIT16mi
925 { 433, 3, 0, 4, 0, 0, 1, 152, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #433 = BIT16mc
926 { 432, 3, 1, 2, 0, 0, 1, 208, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #432 = BIS8rr
927 { 431, 4, 2, 2, 0, 0, 1, 204, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #431 = BIS8rp
928 { 430, 3, 1, 2, 0, 0, 1, 201, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #430 = BIS8rn
929 { 429, 4, 1, 4, 0, 0, 1, 197, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #429 = BIS8rm
930 { 428, 3, 1, 4, 0, 0, 1, 194, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #428 = BIS8ri
931 { 427, 3, 1, 2, 0, 0, 1, 191, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #427 = BIS8rc
932 { 426, 3, 0, 4, 0, 0, 1, 188, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #426 = BIS8mr
933 { 425, 3, 0, 4, 0, 0, 1, 162, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #425 = BIS8mp
934 { 424, 3, 0, 4, 0, 0, 1, 162, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #424 = BIS8mn
935 { 423, 4, 0, 6, 0, 0, 1, 158, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #423 = BIS8mm
936 { 422, 3, 0, 6, 0, 0, 1, 155, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #422 = BIS8mi
937 { 421, 3, 0, 4, 0, 0, 1, 152, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #421 = BIS8mc
938 { 420, 3, 1, 2, 0, 0, 1, 185, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #420 = BIS16rr
939 { 419, 4, 2, 2, 0, 0, 1, 181, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #419 = BIS16rp
940 { 418, 3, 1, 2, 0, 0, 1, 178, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #418 = BIS16rn
941 { 417, 4, 1, 4, 0, 0, 1, 174, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #417 = BIS16rm
942 { 416, 3, 1, 4, 0, 0, 1, 171, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #416 = BIS16ri
943 { 415, 3, 1, 2, 0, 0, 1, 168, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #415 = BIS16rc
944 { 414, 3, 0, 4, 0, 0, 1, 165, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #414 = BIS16mr
945 { 413, 3, 0, 4, 0, 0, 1, 162, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #413 = BIS16mp
946 { 412, 3, 0, 4, 0, 0, 1, 162, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #412 = BIS16mn
947 { 411, 4, 0, 6, 0, 0, 1, 158, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #411 = BIS16mm
948 { 410, 3, 0, 6, 0, 0, 1, 155, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #410 = BIS16mi
949 { 409, 3, 0, 4, 0, 0, 1, 152, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #409 = BIS16mc
950 { 408, 3, 1, 2, 0, 0, 1, 208, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #408 = BIC8rr
951 { 407, 4, 2, 2, 0, 0, 1, 204, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #407 = BIC8rp
952 { 406, 3, 1, 2, 0, 0, 1, 201, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #406 = BIC8rn
953 { 405, 4, 1, 4, 0, 0, 1, 197, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #405 = BIC8rm
954 { 404, 3, 1, 4, 0, 0, 1, 194, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #404 = BIC8ri
955 { 403, 3, 1, 2, 0, 0, 1, 191, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #403 = BIC8rc
956 { 402, 3, 0, 4, 0, 0, 1, 188, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #402 = BIC8mr
957 { 401, 3, 0, 4, 0, 0, 1, 162, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #401 = BIC8mp
958 { 400, 3, 0, 4, 0, 0, 1, 162, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #400 = BIC8mn
959 { 399, 4, 0, 6, 0, 0, 1, 158, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #399 = BIC8mm
960 { 398, 3, 0, 6, 0, 0, 1, 155, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #398 = BIC8mi
961 { 397, 3, 0, 4, 0, 0, 1, 152, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #397 = BIC8mc
962 { 396, 3, 1, 2, 0, 0, 1, 185, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #396 = BIC16rr
963 { 395, 4, 2, 2, 0, 0, 1, 181, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #395 = BIC16rp
964 { 394, 3, 1, 2, 0, 0, 1, 178, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #394 = BIC16rn
965 { 393, 4, 1, 4, 0, 0, 1, 174, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #393 = BIC16rm
966 { 392, 3, 1, 4, 0, 0, 1, 171, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #392 = BIC16ri
967 { 391, 3, 1, 2, 0, 0, 1, 168, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #391 = BIC16rc
968 { 390, 3, 0, 4, 0, 0, 1, 165, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #390 = BIC16mr
969 { 389, 3, 0, 4, 0, 0, 1, 162, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #389 = BIC16mp
970 { 388, 3, 0, 4, 0, 0, 1, 162, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #388 = BIC16mn
971 { 387, 4, 0, 6, 0, 0, 1, 158, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #387 = BIC16mm
972 { 386, 3, 0, 6, 0, 0, 1, 155, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #386 = BIC16mi
973 { 385, 3, 0, 4, 0, 0, 1, 152, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #385 = BIC16mc
974 { 384, 3, 1, 2, 0, 0, 1, 208, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #384 = AND8rr
975 { 383, 4, 2, 2, 0, 0, 1, 204, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #383 = AND8rp
976 { 382, 3, 1, 2, 0, 0, 1, 201, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #382 = AND8rn
977 { 381, 4, 1, 4, 0, 0, 1, 197, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #381 = AND8rm
978 { 380, 3, 1, 4, 0, 0, 1, 194, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #380 = AND8ri
979 { 379, 3, 1, 2, 0, 0, 1, 191, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #379 = AND8rc
980 { 378, 3, 0, 4, 0, 0, 1, 188, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #378 = AND8mr
981 { 377, 3, 0, 4, 0, 0, 1, 162, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #377 = AND8mp
982 { 376, 3, 0, 4, 0, 0, 1, 162, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #376 = AND8mn
983 { 375, 4, 0, 6, 0, 0, 1, 158, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #375 = AND8mm
984 { 374, 3, 0, 6, 0, 0, 1, 155, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #374 = AND8mi
985 { 373, 3, 0, 4, 0, 0, 1, 152, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #373 = AND8mc
986 { 372, 3, 1, 2, 0, 0, 1, 185, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #372 = AND16rr
987 { 371, 4, 2, 2, 0, 0, 1, 181, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #371 = AND16rp
988 { 370, 3, 1, 2, 0, 0, 1, 178, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #370 = AND16rn
989 { 369, 4, 1, 4, 0, 0, 1, 174, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #369 = AND16rm
990 { 368, 3, 1, 4, 0, 0, 1, 171, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #368 = AND16ri
991 { 367, 3, 1, 2, 0, 0, 1, 168, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #367 = AND16rc
992 { 366, 3, 0, 4, 0, 0, 1, 165, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #366 = AND16mr
993 { 365, 3, 0, 4, 0, 0, 1, 162, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #365 = AND16mp
994 { 364, 3, 0, 4, 0, 0, 1, 162, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #364 = AND16mn
995 { 363, 4, 0, 6, 0, 0, 1, 158, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #363 = AND16mm
996 { 362, 3, 0, 6, 0, 0, 1, 155, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #362 = AND16mi
997 { 361, 3, 0, 4, 0, 0, 1, 152, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #361 = AND16mc
998 { 360, 2, 0, 0, 0, 1, 2, 21, MSP430ImpOpBase + 5, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #360 = ADJCALLSTACKUP
999 { 359, 2, 0, 0, 0, 1, 2, 21, MSP430ImpOpBase + 5, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #359 = ADJCALLSTACKDOWN
1000 { 358, 3, 1, 0, 0, 1, 1, 211, MSP430ImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #358 = ADDframe
1001 { 357, 3, 1, 2, 0, 1, 1, 208, MSP430ImpOpBase + 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #357 = ADDC8rr
1002 { 356, 4, 2, 2, 0, 1, 1, 204, MSP430ImpOpBase + 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #356 = ADDC8rp
1003 { 355, 3, 1, 2, 0, 1, 1, 201, MSP430ImpOpBase + 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #355 = ADDC8rn
1004 { 354, 4, 1, 4, 0, 1, 1, 197, MSP430ImpOpBase + 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #354 = ADDC8rm
1005 { 353, 3, 1, 4, 0, 1, 1, 194, MSP430ImpOpBase + 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #353 = ADDC8ri
1006 { 352, 3, 1, 2, 0, 1, 1, 191, MSP430ImpOpBase + 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #352 = ADDC8rc
1007 { 351, 3, 0, 4, 0, 1, 1, 188, MSP430ImpOpBase + 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #351 = ADDC8mr
1008 { 350, 3, 0, 4, 0, 1, 1, 162, MSP430ImpOpBase + 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #350 = ADDC8mp
1009 { 349, 3, 0, 4, 0, 1, 1, 162, MSP430ImpOpBase + 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #349 = ADDC8mn
1010 { 348, 4, 0, 6, 0, 1, 1, 158, MSP430ImpOpBase + 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #348 = ADDC8mm
1011 { 347, 3, 0, 6, 0, 1, 1, 155, MSP430ImpOpBase + 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #347 = ADDC8mi
1012 { 346, 3, 0, 4, 0, 1, 1, 152, MSP430ImpOpBase + 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #346 = ADDC8mc
1013 { 345, 3, 1, 2, 0, 1, 1, 185, MSP430ImpOpBase + 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #345 = ADDC16rr
1014 { 344, 4, 2, 2, 0, 1, 1, 181, MSP430ImpOpBase + 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #344 = ADDC16rp
1015 { 343, 3, 1, 2, 0, 1, 1, 178, MSP430ImpOpBase + 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #343 = ADDC16rn
1016 { 342, 4, 1, 4, 0, 1, 1, 174, MSP430ImpOpBase + 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #342 = ADDC16rm
1017 { 341, 3, 1, 4, 0, 1, 1, 171, MSP430ImpOpBase + 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #341 = ADDC16ri
1018 { 340, 3, 1, 2, 0, 1, 1, 168, MSP430ImpOpBase + 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #340 = ADDC16rc
1019 { 339, 3, 0, 4, 0, 1, 1, 165, MSP430ImpOpBase + 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #339 = ADDC16mr
1020 { 338, 3, 0, 4, 0, 1, 1, 162, MSP430ImpOpBase + 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #338 = ADDC16mp
1021 { 337, 3, 0, 4, 0, 1, 1, 162, MSP430ImpOpBase + 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #337 = ADDC16mn
1022 { 336, 4, 0, 6, 0, 1, 1, 158, MSP430ImpOpBase + 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #336 = ADDC16mm
1023 { 335, 3, 0, 6, 0, 1, 1, 155, MSP430ImpOpBase + 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #335 = ADDC16mi
1024 { 334, 3, 0, 4, 0, 1, 1, 152, MSP430ImpOpBase + 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #334 = ADDC16mc
1025 { 333, 3, 1, 2, 0, 0, 1, 208, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #333 = ADD8rr
1026 { 332, 4, 2, 2, 0, 0, 1, 204, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #332 = ADD8rp
1027 { 331, 3, 1, 2, 0, 0, 1, 201, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #331 = ADD8rn
1028 { 330, 4, 1, 4, 0, 0, 1, 197, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #330 = ADD8rm
1029 { 329, 3, 1, 4, 0, 0, 1, 194, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #329 = ADD8ri
1030 { 328, 3, 1, 2, 0, 0, 1, 191, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #328 = ADD8rc
1031 { 327, 3, 0, 4, 0, 0, 1, 188, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #327 = ADD8mr
1032 { 326, 3, 0, 4, 0, 0, 1, 162, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #326 = ADD8mp
1033 { 325, 3, 0, 4, 0, 0, 1, 162, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #325 = ADD8mn
1034 { 324, 4, 0, 6, 0, 0, 1, 158, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #324 = ADD8mm
1035 { 323, 3, 0, 6, 0, 0, 1, 155, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #323 = ADD8mi
1036 { 322, 3, 0, 4, 0, 0, 1, 152, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #322 = ADD8mc
1037 { 321, 3, 1, 2, 0, 0, 1, 185, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #321 = ADD16rr
1038 { 320, 4, 2, 2, 0, 0, 1, 181, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #320 = ADD16rp
1039 { 319, 3, 1, 2, 0, 0, 1, 178, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #319 = ADD16rn
1040 { 318, 4, 1, 4, 0, 0, 1, 174, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #318 = ADD16rm
1041 { 317, 3, 1, 4, 0, 0, 1, 171, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #317 = ADD16ri
1042 { 316, 3, 1, 2, 0, 0, 1, 168, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #316 = ADD16rc
1043 { 315, 3, 0, 4, 0, 0, 1, 165, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #315 = ADD16mr
1044 { 314, 3, 0, 4, 0, 0, 1, 162, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #314 = ADD16mp
1045 { 313, 3, 0, 4, 0, 0, 1, 162, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #313 = ADD16mn
1046 { 312, 4, 0, 6, 0, 0, 1, 158, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #312 = ADD16mm
1047 { 311, 3, 0, 6, 0, 0, 1, 155, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #311 = ADD16mi
1048 { 310, 3, 0, 4, 0, 0, 1, 152, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #310 = ADD16mc
1049 { 309, 4, 1, 0, 0, 0, 0, 148, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #309 = G_UBFX
1050 { 308, 4, 1, 0, 0, 0, 0, 148, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #308 = G_SBFX
1051 { 307, 2, 1, 0, 0, 0, 0, 61, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #307 = G_VECREDUCE_UMIN
1052 { 306, 2, 1, 0, 0, 0, 0, 61, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #306 = G_VECREDUCE_UMAX
1053 { 305, 2, 1, 0, 0, 0, 0, 61, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #305 = G_VECREDUCE_SMIN
1054 { 304, 2, 1, 0, 0, 0, 0, 61, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #304 = G_VECREDUCE_SMAX
1055 { 303, 2, 1, 0, 0, 0, 0, 61, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #303 = G_VECREDUCE_XOR
1056 { 302, 2, 1, 0, 0, 0, 0, 61, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #302 = G_VECREDUCE_OR
1057 { 301, 2, 1, 0, 0, 0, 0, 61, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #301 = G_VECREDUCE_AND
1058 { 300, 2, 1, 0, 0, 0, 0, 61, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #300 = G_VECREDUCE_MUL
1059 { 299, 2, 1, 0, 0, 0, 0, 61, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #299 = G_VECREDUCE_ADD
1060 { 298, 2, 1, 0, 0, 0, 0, 61, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #298 = G_VECREDUCE_FMINIMUM
1061 { 297, 2, 1, 0, 0, 0, 0, 61, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #297 = G_VECREDUCE_FMAXIMUM
1062 { 296, 2, 1, 0, 0, 0, 0, 61, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #296 = G_VECREDUCE_FMIN
1063 { 295, 2, 1, 0, 0, 0, 0, 61, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #295 = G_VECREDUCE_FMAX
1064 { 294, 2, 1, 0, 0, 0, 0, 61, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #294 = G_VECREDUCE_FMUL
1065 { 293, 2, 1, 0, 0, 0, 0, 61, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #293 = G_VECREDUCE_FADD
1066 { 292, 3, 1, 0, 0, 0, 0, 131, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #292 = G_VECREDUCE_SEQ_FMUL
1067 { 291, 3, 1, 0, 0, 0, 0, 131, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #291 = G_VECREDUCE_SEQ_FADD
1068 { 290, 1, 0, 0, 0, 0, 0, 1, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #290 = G_UBSANTRAP
1069 { 289, 0, 0, 0, 0, 0, 0, 1, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #289 = G_DEBUGTRAP
1070 { 288, 0, 0, 0, 0, 0, 0, 1, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #288 = G_TRAP
1071 { 287, 3, 0, 0, 0, 0, 0, 58, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #287 = G_BZERO
1072 { 286, 4, 0, 0, 0, 0, 0, 144, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #286 = G_MEMSET
1073 { 285, 4, 0, 0, 0, 0, 0, 144, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #285 = G_MEMMOVE
1074 { 284, 3, 0, 0, 0, 0, 0, 131, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #284 = G_MEMCPY_INLINE
1075 { 283, 4, 0, 0, 0, 0, 0, 144, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #283 = G_MEMCPY
1076 { 282, 2, 0, 0, 0, 0, 0, 142, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #282 = G_WRITE_REGISTER
1077 { 281, 2, 1, 0, 0, 0, 0, 51, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #281 = G_READ_REGISTER
1078 { 280, 3, 1, 0, 0, 0, 0, 101, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #280 = G_STRICT_FLDEXP
1079 { 279, 2, 1, 0, 0, 0, 0, 67, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #279 = G_STRICT_FSQRT
1080 { 278, 4, 1, 0, 0, 0, 0, 46, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #278 = G_STRICT_FMA
1081 { 277, 3, 1, 0, 0, 0, 0, 43, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #277 = G_STRICT_FREM
1082 { 276, 3, 1, 0, 0, 0, 0, 43, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #276 = G_STRICT_FDIV
1083 { 275, 3, 1, 0, 0, 0, 0, 43, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #275 = G_STRICT_FMUL
1084 { 274, 3, 1, 0, 0, 0, 0, 43, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #274 = G_STRICT_FSUB
1085 { 273, 3, 1, 0, 0, 0, 0, 43, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #273 = G_STRICT_FADD
1086 { 272, 1, 0, 0, 0, 0, 0, 50, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #272 = G_STACKRESTORE
1087 { 271, 1, 1, 0, 0, 0, 0, 50, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #271 = G_STACKSAVE
1088 { 270, 3, 1, 0, 0, 0, 0, 69, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #270 = G_DYN_STACKALLOC
1089 { 269, 2, 1, 0, 0, 0, 0, 51, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #269 = G_JUMP_TABLE
1090 { 268, 2, 1, 0, 0, 0, 0, 51, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #268 = G_BLOCK_ADDR
1091 { 267, 2, 1, 0, 0, 0, 0, 61, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #267 = G_ADDRSPACE_CAST
1092 { 266, 2, 1, 0, 0, 0, 0, 67, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #266 = G_FNEARBYINT
1093 { 265, 2, 1, 0, 0, 0, 0, 67, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #265 = G_FRINT
1094 { 264, 2, 1, 0, 0, 0, 0, 67, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #264 = G_FFLOOR
1095 { 263, 2, 1, 0, 0, 0, 0, 67, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #263 = G_FSQRT
1096 { 262, 2, 1, 0, 0, 0, 0, 67, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #262 = G_FTANH
1097 { 261, 2, 1, 0, 0, 0, 0, 67, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #261 = G_FSINH
1098 { 260, 2, 1, 0, 0, 0, 0, 67, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #260 = G_FCOSH
1099 { 259, 3, 1, 0, 0, 0, 0, 43, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #259 = G_FATAN2
1100 { 258, 2, 1, 0, 0, 0, 0, 67, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #258 = G_FATAN
1101 { 257, 2, 1, 0, 0, 0, 0, 67, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #257 = G_FASIN
1102 { 256, 2, 1, 0, 0, 0, 0, 67, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #256 = G_FACOS
1103 { 255, 2, 1, 0, 0, 0, 0, 67, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #255 = G_FTAN
1104 { 254, 3, 2, 0, 0, 0, 0, 43, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #254 = G_FSINCOS
1105 { 253, 2, 1, 0, 0, 0, 0, 67, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #253 = G_FSIN
1106 { 252, 2, 1, 0, 0, 0, 0, 67, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #252 = G_FCOS
1107 { 251, 2, 1, 0, 0, 0, 0, 67, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #251 = G_FCEIL
1108 { 250, 2, 1, 0, 0, 0, 0, 67, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #250 = G_BITREVERSE
1109 { 249, 2, 1, 0, 0, 0, 0, 67, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #249 = G_BSWAP
1110 { 248, 2, 1, 0, 0, 0, 0, 61, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #248 = G_CTPOP
1111 { 247, 2, 1, 0, 0, 0, 0, 61, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #247 = G_CTLZ_ZERO_UNDEF
1112 { 246, 2, 1, 0, 0, 0, 0, 61, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #246 = G_CTLZ
1113 { 245, 2, 1, 0, 0, 0, 0, 61, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #245 = G_CTTZ_ZERO_UNDEF
1114 { 244, 2, 1, 0, 0, 0, 0, 61, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #244 = G_CTTZ
1115 { 243, 4, 1, 0, 0, 0, 0, 138, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #243 = G_VECTOR_COMPRESS
1116 { 242, 2, 1, 0, 0, 0, 0, 51, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #242 = G_STEP_VECTOR
1117 { 241, 2, 1, 0, 0, 0, 0, 61, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #241 = G_SPLAT_VECTOR
1118 { 240, 4, 1, 0, 0, 0, 0, 134, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #240 = G_SHUFFLE_VECTOR
1119 { 239, 3, 1, 0, 0, 0, 0, 131, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #239 = G_EXTRACT_VECTOR_ELT
1120 { 238, 4, 1, 0, 0, 0, 0, 127, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #238 = G_INSERT_VECTOR_ELT
1121 { 237, 3, 1, 0, 0, 0, 0, 58, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #237 = G_EXTRACT_SUBVECTOR
1122 { 236, 4, 1, 0, 0, 0, 0, 63, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #236 = G_INSERT_SUBVECTOR
1123 { 235, 2, 1, 0, 0, 0, 0, 51, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #235 = G_VSCALE
1124 { 234, 3, 0, 0, 0, 0, 0, 124, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #234 = G_BRJT
1125 { 233, 1, 0, 0, 0, 0, 0, 0, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #233 = G_BR
1126 { 232, 2, 1, 0, 0, 0, 0, 61, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #232 = G_LLROUND
1127 { 231, 2, 1, 0, 0, 0, 0, 61, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #231 = G_LROUND
1128 { 230, 2, 1, 0, 0, 0, 0, 67, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #230 = G_ABS
1129 { 229, 3, 1, 0, 0, 0, 0, 43, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #229 = G_UMAX
1130 { 228, 3, 1, 0, 0, 0, 0, 43, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #228 = G_UMIN
1131 { 227, 3, 1, 0, 0, 0, 0, 43, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #227 = G_SMAX
1132 { 226, 3, 1, 0, 0, 0, 0, 43, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #226 = G_SMIN
1133 { 225, 3, 1, 0, 0, 0, 0, 101, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #225 = G_PTRMASK
1134 { 224, 3, 1, 0, 0, 0, 0, 101, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #224 = G_PTR_ADD
1135 { 223, 0, 0, 0, 0, 0, 0, 1, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #223 = G_RESET_FPMODE
1136 { 222, 1, 0, 0, 0, 0, 0, 50, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #222 = G_SET_FPMODE
1137 { 221, 1, 1, 0, 0, 0, 0, 50, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #221 = G_GET_FPMODE
1138 { 220, 0, 0, 0, 0, 0, 0, 1, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #220 = G_RESET_FPENV
1139 { 219, 1, 0, 0, 0, 0, 0, 50, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #219 = G_SET_FPENV
1140 { 218, 1, 1, 0, 0, 0, 0, 50, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #218 = G_GET_FPENV
1141 { 217, 3, 1, 0, 0, 0, 0, 43, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #217 = G_FMAXIMUMNUM
1142 { 216, 3, 1, 0, 0, 0, 0, 43, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #216 = G_FMINIMUMNUM
1143 { 215, 3, 1, 0, 0, 0, 0, 43, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #215 = G_FMAXIMUM
1144 { 214, 3, 1, 0, 0, 0, 0, 43, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #214 = G_FMINIMUM
1145 { 213, 3, 1, 0, 0, 0, 0, 43, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #213 = G_FMAXNUM_IEEE
1146 { 212, 3, 1, 0, 0, 0, 0, 43, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #212 = G_FMINNUM_IEEE
1147 { 211, 3, 1, 0, 0, 0, 0, 43, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #211 = G_FMAXNUM
1148 { 210, 3, 1, 0, 0, 0, 0, 43, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #210 = G_FMINNUM
1149 { 209, 2, 1, 0, 0, 0, 0, 67, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #209 = G_FCANONICALIZE
1150 { 208, 3, 1, 0, 0, 0, 0, 98, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #208 = G_IS_FPCLASS
1151 { 207, 3, 1, 0, 0, 0, 0, 101, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #207 = G_FCOPYSIGN
1152 { 206, 2, 1, 0, 0, 0, 0, 67, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #206 = G_FABS
1153 { 205, 2, 1, 0, 0, 0, 0, 61, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #205 = G_FPTOUI_SAT
1154 { 204, 2, 1, 0, 0, 0, 0, 61, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #204 = G_FPTOSI_SAT
1155 { 203, 2, 1, 0, 0, 0, 0, 61, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #203 = G_UITOFP
1156 { 202, 2, 1, 0, 0, 0, 0, 61, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #202 = G_SITOFP
1157 { 201, 2, 1, 0, 0, 0, 0, 61, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #201 = G_FPTOUI
1158 { 200, 2, 1, 0, 0, 0, 0, 61, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #200 = G_FPTOSI
1159 { 199, 2, 1, 0, 0, 0, 0, 61, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #199 = G_FPTRUNC
1160 { 198, 2, 1, 0, 0, 0, 0, 61, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #198 = G_FPEXT
1161 { 197, 2, 1, 0, 0, 0, 0, 67, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #197 = G_FNEG
1162 { 196, 3, 2, 0, 0, 0, 0, 91, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #196 = G_FFREXP
1163 { 195, 3, 1, 0, 0, 0, 0, 101, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #195 = G_FLDEXP
1164 { 194, 2, 1, 0, 0, 0, 0, 67, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #194 = G_FLOG10
1165 { 193, 2, 1, 0, 0, 0, 0, 67, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #193 = G_FLOG2
1166 { 192, 2, 1, 0, 0, 0, 0, 67, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #192 = G_FLOG
1167 { 191, 2, 1, 0, 0, 0, 0, 67, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #191 = G_FEXP10
1168 { 190, 2, 1, 0, 0, 0, 0, 67, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #190 = G_FEXP2
1169 { 189, 2, 1, 0, 0, 0, 0, 67, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #189 = G_FEXP
1170 { 188, 3, 1, 0, 0, 0, 0, 101, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #188 = G_FPOWI
1171 { 187, 3, 1, 0, 0, 0, 0, 43, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #187 = G_FPOW
1172 { 186, 3, 1, 0, 0, 0, 0, 43, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #186 = G_FREM
1173 { 185, 3, 1, 0, 0, 0, 0, 43, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #185 = G_FDIV
1174 { 184, 4, 1, 0, 0, 0, 0, 46, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #184 = G_FMAD
1175 { 183, 4, 1, 0, 0, 0, 0, 46, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #183 = G_FMA
1176 { 182, 3, 1, 0, 0, 0, 0, 43, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #182 = G_FMUL
1177 { 181, 3, 1, 0, 0, 0, 0, 43, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #181 = G_FSUB
1178 { 180, 3, 1, 0, 0, 0, 0, 43, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #180 = G_FADD
1179 { 179, 4, 1, 0, 0, 0, 0, 120, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #179 = G_UDIVFIXSAT
1180 { 178, 4, 1, 0, 0, 0, 0, 120, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #178 = G_SDIVFIXSAT
1181 { 177, 4, 1, 0, 0, 0, 0, 120, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #177 = G_UDIVFIX
1182 { 176, 4, 1, 0, 0, 0, 0, 120, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #176 = G_SDIVFIX
1183 { 175, 4, 1, 0, 0, 0, 0, 120, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #175 = G_UMULFIXSAT
1184 { 174, 4, 1, 0, 0, 0, 0, 120, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #174 = G_SMULFIXSAT
1185 { 173, 4, 1, 0, 0, 0, 0, 120, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #173 = G_UMULFIX
1186 { 172, 4, 1, 0, 0, 0, 0, 120, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #172 = G_SMULFIX
1187 { 171, 3, 1, 0, 0, 0, 0, 101, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #171 = G_SSHLSAT
1188 { 170, 3, 1, 0, 0, 0, 0, 101, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #170 = G_USHLSAT
1189 { 169, 3, 1, 0, 0, 0, 0, 43, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #169 = G_SSUBSAT
1190 { 168, 3, 1, 0, 0, 0, 0, 43, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #168 = G_USUBSAT
1191 { 167, 3, 1, 0, 0, 0, 0, 43, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #167 = G_SADDSAT
1192 { 166, 3, 1, 0, 0, 0, 0, 43, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #166 = G_UADDSAT
1193 { 165, 3, 1, 0, 0, 0, 0, 43, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #165 = G_SMULH
1194 { 164, 3, 1, 0, 0, 0, 0, 43, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #164 = G_UMULH
1195 { 163, 4, 2, 0, 0, 0, 0, 87, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #163 = G_SMULO
1196 { 162, 4, 2, 0, 0, 0, 0, 87, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #162 = G_UMULO
1197 { 161, 5, 2, 0, 0, 0, 0, 115, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #161 = G_SSUBE
1198 { 160, 4, 2, 0, 0, 0, 0, 87, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #160 = G_SSUBO
1199 { 159, 5, 2, 0, 0, 0, 0, 115, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #159 = G_SADDE
1200 { 158, 4, 2, 0, 0, 0, 0, 87, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #158 = G_SADDO
1201 { 157, 5, 2, 0, 0, 0, 0, 115, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #157 = G_USUBE
1202 { 156, 4, 2, 0, 0, 0, 0, 87, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #156 = G_USUBO
1203 { 155, 5, 2, 0, 0, 0, 0, 115, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #155 = G_UADDE
1204 { 154, 4, 2, 0, 0, 0, 0, 87, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #154 = G_UADDO
1205 { 153, 4, 1, 0, 0, 0, 0, 87, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #153 = G_SELECT
1206 { 152, 3, 1, 0, 0, 0, 0, 112, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #152 = G_UCMP
1207 { 151, 3, 1, 0, 0, 0, 0, 112, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #151 = G_SCMP
1208 { 150, 4, 1, 0, 0, 0, 0, 108, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #150 = G_FCMP
1209 { 149, 4, 1, 0, 0, 0, 0, 108, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #149 = G_ICMP
1210 { 148, 3, 1, 0, 0, 0, 0, 101, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #148 = G_ROTL
1211 { 147, 3, 1, 0, 0, 0, 0, 101, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #147 = G_ROTR
1212 { 146, 4, 1, 0, 0, 0, 0, 104, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #146 = G_FSHR
1213 { 145, 4, 1, 0, 0, 0, 0, 104, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #145 = G_FSHL
1214 { 144, 3, 1, 0, 0, 0, 0, 101, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #144 = G_ASHR
1215 { 143, 3, 1, 0, 0, 0, 0, 101, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #143 = G_LSHR
1216 { 142, 3, 1, 0, 0, 0, 0, 101, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #142 = G_SHL
1217 { 141, 2, 1, 0, 0, 0, 0, 61, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #141 = G_ZEXT
1218 { 140, 3, 1, 0, 0, 0, 0, 40, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #140 = G_SEXT_INREG
1219 { 139, 2, 1, 0, 0, 0, 0, 61, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #139 = G_SEXT
1220 { 138, 3, 1, 0, 0, 0, 0, 98, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #138 = G_VAARG
1221 { 137, 1, 0, 0, 0, 0, 0, 50, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #137 = G_VASTART
1222 { 136, 2, 1, 0, 0, 0, 0, 51, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #136 = G_FCONSTANT
1223 { 135, 2, 1, 0, 0, 0, 0, 51, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #135 = G_CONSTANT
1224 { 134, 2, 1, 0, 0, 0, 0, 61, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #134 = G_TRUNC
1225 { 133, 2, 1, 0, 0, 0, 0, 61, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #133 = G_ANYEXT
1226 { 132, 1, 0, 0, 0, 0, 0, 0, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #132 = G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
1227 { 131, 1, 0, 0, 0, 0, 0, 0, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #131 = G_INTRINSIC_CONVERGENT
1228 { 130, 1, 0, 0, 0, 0, 0, 0, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #130 = G_INTRINSIC_W_SIDE_EFFECTS
1229 { 129, 1, 0, 0, 0, 0, 0, 0, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #129 = G_INTRINSIC
1230 { 128, 0, 0, 0, 0, 0, 0, 1, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #128 = G_INVOKE_REGION_START
1231 { 127, 1, 0, 0, 0, 0, 0, 50, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #127 = G_BRINDIRECT
1232 { 126, 2, 0, 0, 0, 0, 0, 51, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #126 = G_BRCOND
1233 { 125, 4, 0, 0, 0, 0, 0, 94, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #125 = G_PREFETCH
1234 { 124, 2, 0, 0, 0, 0, 0, 21, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #124 = G_FENCE
1235 { 123, 3, 1, 0, 0, 0, 0, 91, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #123 = G_ATOMICRMW_USUB_SAT
1236 { 122, 3, 1, 0, 0, 0, 0, 91, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #122 = G_ATOMICRMW_USUB_COND
1237 { 121, 3, 1, 0, 0, 0, 0, 91, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #121 = G_ATOMICRMW_UDEC_WRAP
1238 { 120, 3, 1, 0, 0, 0, 0, 91, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #120 = G_ATOMICRMW_UINC_WRAP
1239 { 119, 3, 1, 0, 0, 0, 0, 91, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #119 = G_ATOMICRMW_FMINIMUM
1240 { 118, 3, 1, 0, 0, 0, 0, 91, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #118 = G_ATOMICRMW_FMAXIMUM
1241 { 117, 3, 1, 0, 0, 0, 0, 91, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #117 = G_ATOMICRMW_FMIN
1242 { 116, 3, 1, 0, 0, 0, 0, 91, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #116 = G_ATOMICRMW_FMAX
1243 { 115, 3, 1, 0, 0, 0, 0, 91, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #115 = G_ATOMICRMW_FSUB
1244 { 114, 3, 1, 0, 0, 0, 0, 91, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #114 = G_ATOMICRMW_FADD
1245 { 113, 3, 1, 0, 0, 0, 0, 91, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #113 = G_ATOMICRMW_UMIN
1246 { 112, 3, 1, 0, 0, 0, 0, 91, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #112 = G_ATOMICRMW_UMAX
1247 { 111, 3, 1, 0, 0, 0, 0, 91, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #111 = G_ATOMICRMW_MIN
1248 { 110, 3, 1, 0, 0, 0, 0, 91, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #110 = G_ATOMICRMW_MAX
1249 { 109, 3, 1, 0, 0, 0, 0, 91, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #109 = G_ATOMICRMW_XOR
1250 { 108, 3, 1, 0, 0, 0, 0, 91, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #108 = G_ATOMICRMW_OR
1251 { 107, 3, 1, 0, 0, 0, 0, 91, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #107 = G_ATOMICRMW_NAND
1252 { 106, 3, 1, 0, 0, 0, 0, 91, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #106 = G_ATOMICRMW_AND
1253 { 105, 3, 1, 0, 0, 0, 0, 91, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #105 = G_ATOMICRMW_SUB
1254 { 104, 3, 1, 0, 0, 0, 0, 91, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #104 = G_ATOMICRMW_ADD
1255 { 103, 3, 1, 0, 0, 0, 0, 91, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #103 = G_ATOMICRMW_XCHG
1256 { 102, 4, 1, 0, 0, 0, 0, 87, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #102 = G_ATOMIC_CMPXCHG
1257 { 101, 5, 2, 0, 0, 0, 0, 82, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #101 = G_ATOMIC_CMPXCHG_WITH_SUCCESS
1258 { 100, 5, 1, 0, 0, 0, 0, 77, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #100 = G_INDEXED_STORE
1259 { 99, 2, 0, 0, 0, 0, 0, 61, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #99 = G_STORE
1260 { 98, 5, 2, 0, 0, 0, 0, 72, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #98 = G_INDEXED_ZEXTLOAD
1261 { 97, 5, 2, 0, 0, 0, 0, 72, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #97 = G_INDEXED_SEXTLOAD
1262 { 96, 5, 2, 0, 0, 0, 0, 72, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #96 = G_INDEXED_LOAD
1263 { 95, 2, 1, 0, 0, 0, 0, 61, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #95 = G_ZEXTLOAD
1264 { 94, 2, 1, 0, 0, 0, 0, 61, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #94 = G_SEXTLOAD
1265 { 93, 2, 1, 0, 0, 0, 0, 61, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #93 = G_LOAD
1266 { 92, 1, 1, 0, 0, 0, 0, 50, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #92 = G_READSTEADYCOUNTER
1267 { 91, 1, 1, 0, 0, 0, 0, 50, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #91 = G_READCYCLECOUNTER
1268 { 90, 2, 1, 0, 0, 0, 0, 67, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #90 = G_INTRINSIC_ROUNDEVEN
1269 { 89, 2, 1, 0, 0, 0, 0, 61, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #89 = G_INTRINSIC_LLRINT
1270 { 88, 2, 1, 0, 0, 0, 0, 61, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #88 = G_INTRINSIC_LRINT
1271 { 87, 2, 1, 0, 0, 0, 0, 67, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #87 = G_INTRINSIC_ROUND
1272 { 86, 2, 1, 0, 0, 0, 0, 67, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #86 = G_INTRINSIC_TRUNC
1273 { 85, 3, 1, 0, 0, 0, 0, 69, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #85 = G_INTRINSIC_FPTRUNC_ROUND
1274 { 84, 2, 1, 0, 0, 0, 0, 67, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #84 = G_CONSTANT_FOLD_BARRIER
1275 { 83, 2, 1, 0, 0, 0, 0, 67, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #83 = G_FREEZE
1276 { 82, 2, 1, 0, 0, 0, 0, 61, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #82 = G_BITCAST
1277 { 81, 2, 1, 0, 0, 0, 0, 61, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #81 = G_INTTOPTR
1278 { 80, 2, 1, 0, 0, 0, 0, 61, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #80 = G_PTRTOINT
1279 { 79, 2, 1, 0, 0, 0, 0, 61, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #79 = G_CONCAT_VECTORS
1280 { 78, 2, 1, 0, 0, 0, 0, 61, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #78 = G_BUILD_VECTOR_TRUNC
1281 { 77, 2, 1, 0, 0, 0, 0, 61, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #77 = G_BUILD_VECTOR
1282 { 76, 2, 1, 0, 0, 0, 0, 61, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #76 = G_MERGE_VALUES
1283 { 75, 4, 1, 0, 0, 0, 0, 63, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #75 = G_INSERT
1284 { 74, 2, 1, 0, 0, 0, 0, 61, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #74 = G_UNMERGE_VALUES
1285 { 73, 3, 1, 0, 0, 0, 0, 58, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #73 = G_EXTRACT
1286 { 72, 2, 1, 0, 0, 0, 0, 51, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #72 = G_CONSTANT_POOL
1287 { 71, 5, 1, 0, 0, 0, 0, 53, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #71 = G_PTRAUTH_GLOBAL_VALUE
1288 { 70, 2, 1, 0, 0, 0, 0, 51, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #70 = G_GLOBAL_VALUE
1289 { 69, 2, 1, 0, 0, 0, 0, 51, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #69 = G_FRAME_INDEX
1290 { 68, 1, 1, 0, 0, 0, 0, 50, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #68 = G_PHI
1291 { 67, 1, 1, 0, 0, 0, 0, 50, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #67 = G_IMPLICIT_DEF
1292 { 66, 3, 1, 0, 0, 0, 0, 43, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #66 = G_ABDU
1293 { 65, 3, 1, 0, 0, 0, 0, 43, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #65 = G_ABDS
1294 { 64, 3, 1, 0, 0, 0, 0, 43, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #64 = G_XOR
1295 { 63, 3, 1, 0, 0, 0, 0, 43, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #63 = G_OR
1296 { 62, 3, 1, 0, 0, 0, 0, 43, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #62 = G_AND
1297 { 61, 4, 2, 0, 0, 0, 0, 46, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #61 = G_UDIVREM
1298 { 60, 4, 2, 0, 0, 0, 0, 46, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #60 = G_SDIVREM
1299 { 59, 3, 1, 0, 0, 0, 0, 43, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #59 = G_UREM
1300 { 58, 3, 1, 0, 0, 0, 0, 43, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #58 = G_SREM
1301 { 57, 3, 1, 0, 0, 0, 0, 43, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #57 = G_UDIV
1302 { 56, 3, 1, 0, 0, 0, 0, 43, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #56 = G_SDIV
1303 { 55, 3, 1, 0, 0, 0, 0, 43, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #55 = G_MUL
1304 { 54, 3, 1, 0, 0, 0, 0, 43, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #54 = G_SUB
1305 { 53, 3, 1, 0, 0, 0, 0, 43, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #53 = G_ADD
1306 { 52, 3, 1, 0, 0, 0, 0, 40, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #52 = G_ASSERT_ALIGN
1307 { 51, 3, 1, 0, 0, 0, 0, 40, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #51 = G_ASSERT_ZEXT
1308 { 50, 3, 1, 0, 0, 0, 0, 40, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #50 = G_ASSERT_SEXT
1309 { 49, 1, 0, 0, 0, 0, 0, 0, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #49 = CONVERGENCECTRL_GLUE
1310 { 48, 2, 1, 0, 0, 0, 0, 13, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #48 = CONVERGENCECTRL_LOOP
1311 { 47, 1, 1, 0, 0, 0, 0, 0, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #47 = CONVERGENCECTRL_ANCHOR
1312 { 46, 1, 1, 0, 0, 0, 0, 0, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #46 = CONVERGENCECTRL_ENTRY
1313 { 45, 1, 0, 0, 0, 0, 0, 1, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #45 = JUMP_TABLE_DEBUG_INFO
1314 { 44, 0, 0, 0, 0, 0, 0, 1, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #44 = MEMBARRIER
1315 { 43, 0, 0, 0, 0, 0, 0, 1, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #43 = FAKE_USE
1316 { 42, 0, 0, 0, 0, 0, 0, 1, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #42 = ICALL_BRANCH_FUNNEL
1317 { 41, 3, 0, 0, 0, 0, 0, 37, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #41 = PATCHABLE_TYPED_EVENT_CALL
1318 { 40, 2, 0, 0, 0, 0, 0, 35, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #40 = PATCHABLE_EVENT_CALL
1319 { 39, 0, 0, 0, 0, 0, 0, 1, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #39 = PATCHABLE_TAIL_CALL
1320 { 38, 0, 0, 0, 0, 0, 0, 1, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #38 = PATCHABLE_FUNCTION_EXIT
1321 { 37, 0, 0, 0, 0, 0, 0, 1, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #37 = PATCHABLE_RET
1322 { 36, 0, 0, 0, 0, 0, 0, 1, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #36 = PATCHABLE_FUNCTION_ENTER
1323 { 35, 0, 0, 0, 0, 0, 0, 1, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #35 = PATCHABLE_OP
1324 { 34, 1, 1, 0, 0, 0, 0, 0, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #34 = FAULTING_OP
1325 { 33, 2, 0, 0, 0, 0, 0, 33, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #33 = LOCAL_ESCAPE
1326 { 32, 0, 0, 0, 0, 0, 0, 1, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #32 = STATEPOINT
1327 { 31, 3, 1, 0, 0, 0, 0, 30, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #31 = PREALLOCATED_ARG
1328 { 30, 1, 0, 0, 0, 0, 0, 1, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #30 = PREALLOCATED_SETUP
1329 { 29, 1, 1, 0, 0, 0, 0, 29, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #29 = LOAD_STACK_GUARD
1330 { 28, 6, 1, 0, 0, 0, 0, 23, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #28 = PATCHPOINT
1331 { 27, 0, 0, 0, 0, 0, 0, 1, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #27 = FENTRY_CALL
1332 { 26, 2, 0, 0, 0, 0, 0, 21, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #26 = STACKMAP
1333 { 25, 2, 1, 0, 0, 0, 0, 19, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #25 = ARITH_FENCE
1334 { 24, 4, 0, 0, 0, 0, 0, 15, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #24 = PSEUDO_PROBE
1335 { 23, 1, 0, 0, 0, 0, 0, 1, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #23 = LIFETIME_END
1336 { 22, 1, 0, 0, 0, 0, 0, 1, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #22 = LIFETIME_START
1337 { 21, 0, 0, 0, 0, 0, 0, 1, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #21 = BUNDLE
1338 { 20, 2, 1, 0, 0, 0, 0, 13, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #20 = COPY
1339 { 19, 2, 1, 0, 0, 0, 0, 13, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #19 = REG_SEQUENCE
1340 { 18, 1, 0, 0, 0, 0, 0, 0, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #18 = DBG_LABEL
1341 { 17, 0, 0, 0, 0, 0, 0, 1, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #17 = DBG_PHI
1342 { 16, 0, 0, 0, 0, 0, 0, 1, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #16 = DBG_INSTR_REF
1343 { 15, 0, 0, 0, 0, 0, 0, 1, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #15 = DBG_VALUE_LIST
1344 { 14, 0, 0, 0, 0, 0, 0, 1, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #14 = DBG_VALUE
1345 { 13, 3, 1, 0, 0, 0, 0, 2, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #13 = COPY_TO_REGCLASS
1346 { 12, 4, 1, 0, 0, 0, 0, 9, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #12 = SUBREG_TO_REG
1347 { 11, 1, 1, 0, 0, 0, 0, 0, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #11 = INIT_UNDEF
1348 { 10, 1, 1, 0, 0, 0, 0, 0, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #10 = IMPLICIT_DEF
1349 { 9, 4, 1, 0, 0, 0, 0, 5, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #9 = INSERT_SUBREG
1350 { 8, 3, 1, 0, 0, 0, 0, 2, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #8 = EXTRACT_SUBREG
1351 { 7, 0, 0, 0, 0, 0, 0, 1, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #7 = KILL
1352 { 6, 1, 0, 0, 0, 0, 0, 1, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #6 = ANNOTATION_LABEL
1353 { 5, 1, 0, 0, 0, 0, 0, 1, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #5 = GC_LABEL
1354 { 4, 1, 0, 0, 0, 0, 0, 1, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #4 = EH_LABEL
1355 { 3, 1, 0, 0, 0, 0, 0, 1, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #3 = CFI_INSTRUCTION
1356 { 2, 0, 0, 0, 0, 0, 0, 1, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #2 = INLINEASM_BR
1357 { 1, 0, 0, 0, 0, 0, 0, 1, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1 = INLINEASM
1358 { 0, 1, 1, 0, 0, 0, 0, 0, MSP430ImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #0 = PHI
1359 }, {
1360 /* 0 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1361 /* 1 */
1362 /* 1 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1363 /* 2 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1364 /* 5 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1365 /* 9 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1366 /* 13 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1367 /* 15 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1368 /* 19 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) },
1369 /* 21 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1370 /* 23 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1371 /* 29 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 },
1372 /* 30 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1373 /* 33 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1374 /* 35 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1375 /* 37 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1376 /* 40 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1377 /* 43 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1378 /* 46 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1379 /* 50 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1380 /* 51 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1381 /* 53 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1382 /* 58 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1383 /* 61 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1384 /* 63 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1385 /* 67 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1386 /* 69 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1387 /* 72 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1388 /* 77 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1389 /* 82 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1390 /* 87 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1391 /* 91 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1392 /* 94 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1393 /* 98 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1394 /* 101 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1395 /* 104 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1396 /* 108 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1397 /* 112 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1398 /* 115 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1399 /* 120 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1400 /* 124 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1401 /* 127 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
1402 /* 131 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
1403 /* 134 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1404 /* 138 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1405 /* 142 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1406 /* 144 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1407 /* 148 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1408 /* 152 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1409 /* 155 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1410 /* 158 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1411 /* 162 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 },
1412 /* 165 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1413 /* 168 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1414 /* 171 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1415 /* 174 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1416 /* 178 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 },
1417 /* 181 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(1) },
1418 /* 185 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1419 /* 188 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1420 /* 191 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1421 /* 194 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1422 /* 197 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1423 /* 201 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 },
1424 /* 204 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(1) },
1425 /* 208 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1426 /* 211 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1427 /* 214 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1428 /* 216 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1429 /* 218 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1430 /* 221 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 },
1431 /* 223 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1432 /* 225 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1433 /* 227 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1434 /* 229 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1435 /* 232 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 },
1436 /* 234 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1437 /* 236 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1438 /* 238 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1439 /* 239 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 },
1440 /* 240 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(1) },
1441 /* 243 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(1) },
1442 /* 246 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1443 /* 248 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1444 /* 249 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
1445 /* 251 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
1446 /* 253 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1447 /* 257 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1448 /* 261 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1449 /* 264 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1450 }, {
1451 /* 0 */
1452 /* 0 */ MSP430::SR,
1453 /* 1 */ MSP430::SR, MSP430::SR,
1454 /* 3 */ MSP430::SP, MSP430::SR,
1455 /* 5 */ MSP430::SP, MSP430::SP, MSP430::SR,
1456 /* 8 */ MSP430::SP, MSP430::R11, MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15, MSP430::SR,
1457 /* 15 */ MSP430::SP, MSP430::SP,
1458 }
1459};
1460
1461
1462#ifdef __GNUC__
1463#pragma GCC diagnostic push
1464#pragma GCC diagnostic ignored "-Woverlength-strings"
1465#endif
1466extern const char MSP430InstrNameData[] = {
1467 /* 0 */ "G_FLOG10\000"
1468 /* 9 */ "G_FEXP10\000"
1469 /* 18 */ "G_FLOG2\000"
1470 /* 26 */ "G_FATAN2\000"
1471 /* 35 */ "G_FEXP2\000"
1472 /* 43 */ "Sra16\000"
1473 /* 49 */ "Rrcl16\000"
1474 /* 56 */ "Shl16\000"
1475 /* 62 */ "Srl16\000"
1476 /* 68 */ "Select16\000"
1477 /* 77 */ "Sra8\000"
1478 /* 82 */ "Rrcl8\000"
1479 /* 88 */ "Shl8\000"
1480 /* 93 */ "Srl8\000"
1481 /* 98 */ "MOVZX16rm8\000"
1482 /* 109 */ "MOVZX16rr8\000"
1483 /* 120 */ "Select8\000"
1484 /* 128 */ "G_FMA\000"
1485 /* 134 */ "G_STRICT_FMA\000"
1486 /* 147 */ "G_FSUB\000"
1487 /* 154 */ "G_STRICT_FSUB\000"
1488 /* 168 */ "G_ATOMICRMW_FSUB\000"
1489 /* 185 */ "G_SUB\000"
1490 /* 191 */ "G_ATOMICRMW_SUB\000"
1491 /* 207 */ "JCC\000"
1492 /* 211 */ "G_INTRINSIC\000"
1493 /* 223 */ "G_FPTRUNC\000"
1494 /* 233 */ "G_INTRINSIC_TRUNC\000"
1495 /* 251 */ "G_TRUNC\000"
1496 /* 259 */ "G_BUILD_VECTOR_TRUNC\000"
1497 /* 280 */ "G_DYN_STACKALLOC\000"
1498 /* 297 */ "G_FMAD\000"
1499 /* 304 */ "G_INDEXED_SEXTLOAD\000"
1500 /* 323 */ "G_SEXTLOAD\000"
1501 /* 334 */ "G_INDEXED_ZEXTLOAD\000"
1502 /* 353 */ "G_ZEXTLOAD\000"
1503 /* 364 */ "G_INDEXED_LOAD\000"
1504 /* 379 */ "G_LOAD\000"
1505 /* 386 */ "G_VECREDUCE_FADD\000"
1506 /* 403 */ "G_FADD\000"
1507 /* 410 */ "G_VECREDUCE_SEQ_FADD\000"
1508 /* 431 */ "G_STRICT_FADD\000"
1509 /* 445 */ "G_ATOMICRMW_FADD\000"
1510 /* 462 */ "G_VECREDUCE_ADD\000"
1511 /* 478 */ "G_ADD\000"
1512 /* 484 */ "G_PTR_ADD\000"
1513 /* 494 */ "G_ATOMICRMW_ADD\000"
1514 /* 510 */ "G_ATOMICRMW_NAND\000"
1515 /* 527 */ "G_VECREDUCE_AND\000"
1516 /* 543 */ "G_AND\000"
1517 /* 549 */ "G_ATOMICRMW_AND\000"
1518 /* 565 */ "LIFETIME_END\000"
1519 /* 578 */ "G_BRCOND\000"
1520 /* 587 */ "G_ATOMICRMW_USUB_COND\000"
1521 /* 609 */ "G_LLROUND\000"
1522 /* 619 */ "G_LROUND\000"
1523 /* 628 */ "G_INTRINSIC_ROUND\000"
1524 /* 646 */ "G_INTRINSIC_FPTRUNC_ROUND\000"
1525 /* 672 */ "LOAD_STACK_GUARD\000"
1526 /* 689 */ "PSEUDO_PROBE\000"
1527 /* 702 */ "G_SSUBE\000"
1528 /* 710 */ "G_USUBE\000"
1529 /* 718 */ "G_FENCE\000"
1530 /* 726 */ "ARITH_FENCE\000"
1531 /* 738 */ "REG_SEQUENCE\000"
1532 /* 751 */ "G_SADDE\000"
1533 /* 759 */ "G_UADDE\000"
1534 /* 767 */ "G_GET_FPMODE\000"
1535 /* 780 */ "G_RESET_FPMODE\000"
1536 /* 795 */ "G_SET_FPMODE\000"
1537 /* 808 */ "G_FMINNUM_IEEE\000"
1538 /* 823 */ "G_FMAXNUM_IEEE\000"
1539 /* 838 */ "G_VSCALE\000"
1540 /* 847 */ "G_JUMP_TABLE\000"
1541 /* 860 */ "BUNDLE\000"
1542 /* 867 */ "G_MEMCPY_INLINE\000"
1543 /* 883 */ "LOCAL_ESCAPE\000"
1544 /* 896 */ "G_STACKRESTORE\000"
1545 /* 911 */ "G_INDEXED_STORE\000"
1546 /* 927 */ "G_STORE\000"
1547 /* 935 */ "G_BITREVERSE\000"
1548 /* 948 */ "FAKE_USE\000"
1549 /* 957 */ "DBG_VALUE\000"
1550 /* 967 */ "G_GLOBAL_VALUE\000"
1551 /* 982 */ "G_PTRAUTH_GLOBAL_VALUE\000"
1552 /* 1005 */ "CONVERGENCECTRL_GLUE\000"
1553 /* 1026 */ "G_STACKSAVE\000"
1554 /* 1038 */ "G_MEMMOVE\000"
1555 /* 1048 */ "G_FREEZE\000"
1556 /* 1057 */ "G_FCANONICALIZE\000"
1557 /* 1073 */ "G_CTLZ_ZERO_UNDEF\000"
1558 /* 1091 */ "G_CTTZ_ZERO_UNDEF\000"
1559 /* 1109 */ "INIT_UNDEF\000"
1560 /* 1120 */ "G_IMPLICIT_DEF\000"
1561 /* 1135 */ "DBG_INSTR_REF\000"
1562 /* 1149 */ "G_FNEG\000"
1563 /* 1156 */ "EXTRACT_SUBREG\000"
1564 /* 1171 */ "INSERT_SUBREG\000"
1565 /* 1185 */ "G_SEXT_INREG\000"
1566 /* 1198 */ "SUBREG_TO_REG\000"
1567 /* 1212 */ "G_ATOMIC_CMPXCHG\000"
1568 /* 1229 */ "G_ATOMICRMW_XCHG\000"
1569 /* 1246 */ "G_FLOG\000"
1570 /* 1253 */ "G_VAARG\000"
1571 /* 1261 */ "PREALLOCATED_ARG\000"
1572 /* 1278 */ "G_PREFETCH\000"
1573 /* 1289 */ "G_SMULH\000"
1574 /* 1297 */ "G_UMULH\000"
1575 /* 1305 */ "G_FTANH\000"
1576 /* 1313 */ "G_FSINH\000"
1577 /* 1321 */ "G_FCOSH\000"
1578 /* 1329 */ "DBG_PHI\000"
1579 /* 1337 */ "G_FPTOSI\000"
1580 /* 1346 */ "RETI\000"
1581 /* 1351 */ "G_FPTOUI\000"
1582 /* 1360 */ "G_FPOWI\000"
1583 /* 1368 */ "G_PTRMASK\000"
1584 /* 1378 */ "GC_LABEL\000"
1585 /* 1387 */ "DBG_LABEL\000"
1586 /* 1397 */ "EH_LABEL\000"
1587 /* 1406 */ "ANNOTATION_LABEL\000"
1588 /* 1423 */ "ICALL_BRANCH_FUNNEL\000"
1589 /* 1443 */ "G_FSHL\000"
1590 /* 1450 */ "G_SHL\000"
1591 /* 1456 */ "G_FCEIL\000"
1592 /* 1464 */ "PATCHABLE_TAIL_CALL\000"
1593 /* 1484 */ "PATCHABLE_TYPED_EVENT_CALL\000"
1594 /* 1511 */ "PATCHABLE_EVENT_CALL\000"
1595 /* 1532 */ "FENTRY_CALL\000"
1596 /* 1544 */ "KILL\000"
1597 /* 1549 */ "G_CONSTANT_POOL\000"
1598 /* 1565 */ "G_ROTL\000"
1599 /* 1572 */ "G_VECREDUCE_FMUL\000"
1600 /* 1589 */ "G_FMUL\000"
1601 /* 1596 */ "G_VECREDUCE_SEQ_FMUL\000"
1602 /* 1617 */ "G_STRICT_FMUL\000"
1603 /* 1631 */ "G_VECREDUCE_MUL\000"
1604 /* 1647 */ "G_MUL\000"
1605 /* 1653 */ "G_FREM\000"
1606 /* 1660 */ "G_STRICT_FREM\000"
1607 /* 1674 */ "G_SREM\000"
1608 /* 1681 */ "G_UREM\000"
1609 /* 1688 */ "G_SDIVREM\000"
1610 /* 1698 */ "G_UDIVREM\000"
1611 /* 1708 */ "INLINEASM\000"
1612 /* 1718 */ "G_VECREDUCE_FMINIMUM\000"
1613 /* 1739 */ "G_FMINIMUM\000"
1614 /* 1750 */ "G_ATOMICRMW_FMINIMUM\000"
1615 /* 1771 */ "G_VECREDUCE_FMAXIMUM\000"
1616 /* 1792 */ "G_FMAXIMUM\000"
1617 /* 1803 */ "G_ATOMICRMW_FMAXIMUM\000"
1618 /* 1824 */ "G_FMINIMUMNUM\000"
1619 /* 1838 */ "G_FMAXIMUMNUM\000"
1620 /* 1852 */ "G_FMINNUM\000"
1621 /* 1862 */ "G_FMAXNUM\000"
1622 /* 1872 */ "G_FATAN\000"
1623 /* 1880 */ "G_FTAN\000"
1624 /* 1887 */ "G_INTRINSIC_ROUNDEVEN\000"
1625 /* 1909 */ "G_ASSERT_ALIGN\000"
1626 /* 1924 */ "G_FCOPYSIGN\000"
1627 /* 1936 */ "G_VECREDUCE_FMIN\000"
1628 /* 1953 */ "G_ATOMICRMW_FMIN\000"
1629 /* 1970 */ "G_VECREDUCE_SMIN\000"
1630 /* 1987 */ "G_SMIN\000"
1631 /* 1994 */ "G_VECREDUCE_UMIN\000"
1632 /* 2011 */ "G_UMIN\000"
1633 /* 2018 */ "G_ATOMICRMW_UMIN\000"
1634 /* 2035 */ "G_ATOMICRMW_MIN\000"
1635 /* 2051 */ "G_FASIN\000"
1636 /* 2059 */ "G_FSIN\000"
1637 /* 2066 */ "CFI_INSTRUCTION\000"
1638 /* 2082 */ "ADJCALLSTACKDOWN\000"
1639 /* 2099 */ "G_SSUBO\000"
1640 /* 2107 */ "G_USUBO\000"
1641 /* 2115 */ "G_SADDO\000"
1642 /* 2123 */ "G_UADDO\000"
1643 /* 2131 */ "JUMP_TABLE_DEBUG_INFO\000"
1644 /* 2153 */ "G_SMULO\000"
1645 /* 2161 */ "G_UMULO\000"
1646 /* 2169 */ "G_BZERO\000"
1647 /* 2177 */ "STACKMAP\000"
1648 /* 2186 */ "G_DEBUGTRAP\000"
1649 /* 2198 */ "G_UBSANTRAP\000"
1650 /* 2210 */ "G_TRAP\000"
1651 /* 2217 */ "G_ATOMICRMW_UDEC_WRAP\000"
1652 /* 2239 */ "G_ATOMICRMW_UINC_WRAP\000"
1653 /* 2261 */ "G_BSWAP\000"
1654 /* 2269 */ "G_SITOFP\000"
1655 /* 2278 */ "G_UITOFP\000"
1656 /* 2287 */ "G_FCMP\000"
1657 /* 2294 */ "G_ICMP\000"
1658 /* 2301 */ "G_SCMP\000"
1659 /* 2308 */ "G_UCMP\000"
1660 /* 2315 */ "JMP\000"
1661 /* 2319 */ "CONVERGENCECTRL_LOOP\000"
1662 /* 2340 */ "G_CTPOP\000"
1663 /* 2348 */ "PATCHABLE_OP\000"
1664 /* 2361 */ "FAULTING_OP\000"
1665 /* 2373 */ "ADJCALLSTACKUP\000"
1666 /* 2388 */ "PREALLOCATED_SETUP\000"
1667 /* 2407 */ "G_FLDEXP\000"
1668 /* 2416 */ "G_STRICT_FLDEXP\000"
1669 /* 2432 */ "G_FEXP\000"
1670 /* 2439 */ "G_FFREXP\000"
1671 /* 2448 */ "G_BR\000"
1672 /* 2453 */ "INLINEASM_BR\000"
1673 /* 2466 */ "G_BLOCK_ADDR\000"
1674 /* 2479 */ "MEMBARRIER\000"
1675 /* 2490 */ "G_CONSTANT_FOLD_BARRIER\000"
1676 /* 2514 */ "PATCHABLE_FUNCTION_ENTER\000"
1677 /* 2539 */ "G_READCYCLECOUNTER\000"
1678 /* 2558 */ "G_READSTEADYCOUNTER\000"
1679 /* 2578 */ "G_READ_REGISTER\000"
1680 /* 2594 */ "G_WRITE_REGISTER\000"
1681 /* 2611 */ "G_ASHR\000"
1682 /* 2618 */ "G_FSHR\000"
1683 /* 2625 */ "G_LSHR\000"
1684 /* 2632 */ "CONVERGENCECTRL_ANCHOR\000"
1685 /* 2655 */ "G_FFLOOR\000"
1686 /* 2664 */ "G_EXTRACT_SUBVECTOR\000"
1687 /* 2684 */ "G_INSERT_SUBVECTOR\000"
1688 /* 2703 */ "G_BUILD_VECTOR\000"
1689 /* 2718 */ "G_SHUFFLE_VECTOR\000"
1690 /* 2735 */ "G_STEP_VECTOR\000"
1691 /* 2749 */ "G_SPLAT_VECTOR\000"
1692 /* 2764 */ "G_VECREDUCE_XOR\000"
1693 /* 2780 */ "G_XOR\000"
1694 /* 2786 */ "G_ATOMICRMW_XOR\000"
1695 /* 2802 */ "G_VECREDUCE_OR\000"
1696 /* 2817 */ "G_OR\000"
1697 /* 2822 */ "G_ATOMICRMW_OR\000"
1698 /* 2837 */ "G_ROTR\000"
1699 /* 2844 */ "G_INTTOPTR\000"
1700 /* 2855 */ "G_FABS\000"
1701 /* 2862 */ "G_ABS\000"
1702 /* 2868 */ "G_ABDS\000"
1703 /* 2875 */ "G_UNMERGE_VALUES\000"
1704 /* 2892 */ "G_MERGE_VALUES\000"
1705 /* 2907 */ "G_FACOS\000"
1706 /* 2915 */ "G_FCOS\000"
1707 /* 2922 */ "G_FSINCOS\000"
1708 /* 2932 */ "G_CONCAT_VECTORS\000"
1709 /* 2949 */ "COPY_TO_REGCLASS\000"
1710 /* 2966 */ "G_IS_FPCLASS\000"
1711 /* 2979 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\000"
1712 /* 3009 */ "G_VECTOR_COMPRESS\000"
1713 /* 3027 */ "G_INTRINSIC_W_SIDE_EFFECTS\000"
1714 /* 3054 */ "G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS\000"
1715 /* 3092 */ "G_SSUBSAT\000"
1716 /* 3102 */ "G_USUBSAT\000"
1717 /* 3112 */ "G_SADDSAT\000"
1718 /* 3122 */ "G_UADDSAT\000"
1719 /* 3132 */ "G_SSHLSAT\000"
1720 /* 3142 */ "G_USHLSAT\000"
1721 /* 3152 */ "G_SMULFIXSAT\000"
1722 /* 3165 */ "G_UMULFIXSAT\000"
1723 /* 3178 */ "G_SDIVFIXSAT\000"
1724 /* 3191 */ "G_UDIVFIXSAT\000"
1725 /* 3204 */ "G_ATOMICRMW_USUB_SAT\000"
1726 /* 3225 */ "G_FPTOSI_SAT\000"
1727 /* 3238 */ "G_FPTOUI_SAT\000"
1728 /* 3251 */ "G_EXTRACT\000"
1729 /* 3261 */ "G_SELECT\000"
1730 /* 3270 */ "G_BRINDIRECT\000"
1731 /* 3283 */ "PATCHABLE_RET\000"
1732 /* 3297 */ "G_MEMSET\000"
1733 /* 3306 */ "PATCHABLE_FUNCTION_EXIT\000"
1734 /* 3330 */ "G_BRJT\000"
1735 /* 3337 */ "G_EXTRACT_VECTOR_ELT\000"
1736 /* 3358 */ "G_INSERT_VECTOR_ELT\000"
1737 /* 3378 */ "G_FCONSTANT\000"
1738 /* 3390 */ "G_CONSTANT\000"
1739 /* 3401 */ "G_INTRINSIC_CONVERGENT\000"
1740 /* 3424 */ "STATEPOINT\000"
1741 /* 3435 */ "PATCHPOINT\000"
1742 /* 3446 */ "G_PTRTOINT\000"
1743 /* 3457 */ "G_FRINT\000"
1744 /* 3465 */ "G_INTRINSIC_LLRINT\000"
1745 /* 3484 */ "G_INTRINSIC_LRINT\000"
1746 /* 3502 */ "G_FNEARBYINT\000"
1747 /* 3515 */ "G_VASTART\000"
1748 /* 3525 */ "LIFETIME_START\000"
1749 /* 3540 */ "G_INVOKE_REGION_START\000"
1750 /* 3562 */ "G_INSERT\000"
1751 /* 3571 */ "G_FSQRT\000"
1752 /* 3579 */ "G_STRICT_FSQRT\000"
1753 /* 3594 */ "G_BITCAST\000"
1754 /* 3604 */ "G_ADDRSPACE_CAST\000"
1755 /* 3621 */ "DBG_VALUE_LIST\000"
1756 /* 3636 */ "G_FPEXT\000"
1757 /* 3644 */ "G_SEXT\000"
1758 /* 3651 */ "G_ASSERT_SEXT\000"
1759 /* 3665 */ "G_ANYEXT\000"
1760 /* 3674 */ "G_ZEXT\000"
1761 /* 3681 */ "G_ASSERT_ZEXT\000"
1762 /* 3695 */ "G_ABDU\000"
1763 /* 3702 */ "G_FDIV\000"
1764 /* 3709 */ "G_STRICT_FDIV\000"
1765 /* 3723 */ "G_SDIV\000"
1766 /* 3730 */ "G_UDIV\000"
1767 /* 3737 */ "G_GET_FPENV\000"
1768 /* 3749 */ "G_RESET_FPENV\000"
1769 /* 3763 */ "G_SET_FPENV\000"
1770 /* 3775 */ "G_FPOW\000"
1771 /* 3782 */ "G_VECREDUCE_FMAX\000"
1772 /* 3799 */ "G_ATOMICRMW_FMAX\000"
1773 /* 3816 */ "G_VECREDUCE_SMAX\000"
1774 /* 3833 */ "G_SMAX\000"
1775 /* 3840 */ "G_VECREDUCE_UMAX\000"
1776 /* 3857 */ "G_UMAX\000"
1777 /* 3864 */ "G_ATOMICRMW_UMAX\000"
1778 /* 3881 */ "G_ATOMICRMW_MAX\000"
1779 /* 3897 */ "G_FRAME_INDEX\000"
1780 /* 3911 */ "G_SBFX\000"
1781 /* 3918 */ "G_UBFX\000"
1782 /* 3925 */ "G_SMULFIX\000"
1783 /* 3935 */ "G_UMULFIX\000"
1784 /* 3945 */ "G_SDIVFIX\000"
1785 /* 3955 */ "G_UDIVFIX\000"
1786 /* 3965 */ "G_MEMCPY\000"
1787 /* 3974 */ "COPY\000"
1788 /* 3979 */ "CONVERGENCECTRL_ENTRY\000"
1789 /* 4001 */ "G_CTLZ\000"
1790 /* 4008 */ "G_CTTZ\000"
1791 /* 4015 */ "PUSH16c\000"
1792 /* 4023 */ "SUB16mc\000"
1793 /* 4031 */ "SUBC16mc\000"
1794 /* 4040 */ "ADDC16mc\000"
1795 /* 4049 */ "BIC16mc\000"
1796 /* 4057 */ "DADD16mc\000"
1797 /* 4066 */ "AND16mc\000"
1798 /* 4074 */ "CMP16mc\000"
1799 /* 4082 */ "XOR16mc\000"
1800 /* 4090 */ "BIS16mc\000"
1801 /* 4098 */ "BIT16mc\000"
1802 /* 4106 */ "MOV16mc\000"
1803 /* 4114 */ "SUB8mc\000"
1804 /* 4121 */ "SUBC8mc\000"
1805 /* 4129 */ "ADDC8mc\000"
1806 /* 4137 */ "BIC8mc\000"
1807 /* 4144 */ "DADD8mc\000"
1808 /* 4152 */ "AND8mc\000"
1809 /* 4159 */ "CMP8mc\000"
1810 /* 4166 */ "XOR8mc\000"
1811 /* 4173 */ "BIS8mc\000"
1812 /* 4180 */ "BIT8mc\000"
1813 /* 4187 */ "MOV8mc\000"
1814 /* 4194 */ "SUB16rc\000"
1815 /* 4202 */ "SUBC16rc\000"
1816 /* 4211 */ "ADDC16rc\000"
1817 /* 4220 */ "BIC16rc\000"
1818 /* 4228 */ "DADD16rc\000"
1819 /* 4237 */ "AND16rc\000"
1820 /* 4245 */ "CMP16rc\000"
1821 /* 4253 */ "XOR16rc\000"
1822 /* 4261 */ "BIS16rc\000"
1823 /* 4269 */ "BIT16rc\000"
1824 /* 4277 */ "MOV16rc\000"
1825 /* 4285 */ "SUB8rc\000"
1826 /* 4292 */ "SUBC8rc\000"
1827 /* 4300 */ "ADDC8rc\000"
1828 /* 4308 */ "BIC8rc\000"
1829 /* 4315 */ "DADD8rc\000"
1830 /* 4323 */ "AND8rc\000"
1831 /* 4330 */ "CMP8rc\000"
1832 /* 4337 */ "XOR8rc\000"
1833 /* 4344 */ "BIS8rc\000"
1834 /* 4351 */ "BIT8rc\000"
1835 /* 4358 */ "MOV8rc\000"
1836 /* 4365 */ "ADDframe\000"
1837 /* 4374 */ "PUSH16i\000"
1838 /* 4382 */ "Bi\000"
1839 /* 4385 */ "CALLi\000"
1840 /* 4391 */ "SUB16mi\000"
1841 /* 4399 */ "SUBC16mi\000"
1842 /* 4408 */ "ADDC16mi\000"
1843 /* 4417 */ "BIC16mi\000"
1844 /* 4425 */ "DADD16mi\000"
1845 /* 4434 */ "AND16mi\000"
1846 /* 4442 */ "CMP16mi\000"
1847 /* 4450 */ "XOR16mi\000"
1848 /* 4458 */ "BIS16mi\000"
1849 /* 4466 */ "BIT16mi\000"
1850 /* 4474 */ "MOV16mi\000"
1851 /* 4482 */ "SUB8mi\000"
1852 /* 4489 */ "SUBC8mi\000"
1853 /* 4497 */ "ADDC8mi\000"
1854 /* 4505 */ "BIC8mi\000"
1855 /* 4512 */ "DADD8mi\000"
1856 /* 4520 */ "AND8mi\000"
1857 /* 4527 */ "CMP8mi\000"
1858 /* 4534 */ "XOR8mi\000"
1859 /* 4541 */ "BIS8mi\000"
1860 /* 4548 */ "BIT8mi\000"
1861 /* 4555 */ "MOV8mi\000"
1862 /* 4562 */ "SUB16ri\000"
1863 /* 4570 */ "SUBC16ri\000"
1864 /* 4579 */ "ADDC16ri\000"
1865 /* 4588 */ "BIC16ri\000"
1866 /* 4596 */ "DADD16ri\000"
1867 /* 4605 */ "AND16ri\000"
1868 /* 4613 */ "CMP16ri\000"
1869 /* 4621 */ "XOR16ri\000"
1870 /* 4629 */ "BIS16ri\000"
1871 /* 4637 */ "BIT16ri\000"
1872 /* 4645 */ "MOV16ri\000"
1873 /* 4653 */ "SUB8ri\000"
1874 /* 4660 */ "SUBC8ri\000"
1875 /* 4668 */ "ADDC8ri\000"
1876 /* 4676 */ "BIC8ri\000"
1877 /* 4683 */ "DADD8ri\000"
1878 /* 4691 */ "AND8ri\000"
1879 /* 4698 */ "CMP8ri\000"
1880 /* 4705 */ "XOR8ri\000"
1881 /* 4712 */ "BIS8ri\000"
1882 /* 4719 */ "BIT8ri\000"
1883 /* 4726 */ "MOV8ri\000"
1884 /* 4733 */ "RRA16m\000"
1885 /* 4740 */ "SWPB16m\000"
1886 /* 4748 */ "RRC16m\000"
1887 /* 4755 */ "SEXT16m\000"
1888 /* 4763 */ "RRA8m\000"
1889 /* 4769 */ "RRC8m\000"
1890 /* 4775 */ "Bm\000"
1891 /* 4778 */ "CALLm\000"
1892 /* 4784 */ "SUB16mm\000"
1893 /* 4792 */ "SUBC16mm\000"
1894 /* 4801 */ "ADDC16mm\000"
1895 /* 4810 */ "BIC16mm\000"
1896 /* 4818 */ "DADD16mm\000"
1897 /* 4827 */ "AND16mm\000"
1898 /* 4835 */ "CMP16mm\000"
1899 /* 4843 */ "XOR16mm\000"
1900 /* 4851 */ "BIS16mm\000"
1901 /* 4859 */ "BIT16mm\000"
1902 /* 4867 */ "MOV16mm\000"
1903 /* 4875 */ "SUB8mm\000"
1904 /* 4882 */ "SUBC8mm\000"
1905 /* 4890 */ "ADDC8mm\000"
1906 /* 4898 */ "BIC8mm\000"
1907 /* 4905 */ "DADD8mm\000"
1908 /* 4913 */ "AND8mm\000"
1909 /* 4920 */ "CMP8mm\000"
1910 /* 4927 */ "XOR8mm\000"
1911 /* 4934 */ "BIS8mm\000"
1912 /* 4941 */ "BIT8mm\000"
1913 /* 4948 */ "MOV8mm\000"
1914 /* 4955 */ "SUB16rm\000"
1915 /* 4963 */ "SUBC16rm\000"
1916 /* 4972 */ "ADDC16rm\000"
1917 /* 4981 */ "BIC16rm\000"
1918 /* 4989 */ "DADD16rm\000"
1919 /* 4998 */ "AND16rm\000"
1920 /* 5006 */ "CMP16rm\000"
1921 /* 5014 */ "XOR16rm\000"
1922 /* 5022 */ "BIS16rm\000"
1923 /* 5030 */ "BIT16rm\000"
1924 /* 5038 */ "MOV16rm\000"
1925 /* 5046 */ "SUB8rm\000"
1926 /* 5053 */ "SUBC8rm\000"
1927 /* 5061 */ "ADDC8rm\000"
1928 /* 5069 */ "BIC8rm\000"
1929 /* 5076 */ "DADD8rm\000"
1930 /* 5084 */ "AND8rm\000"
1931 /* 5091 */ "CMP8rm\000"
1932 /* 5098 */ "XOR8rm\000"
1933 /* 5105 */ "BIS8rm\000"
1934 /* 5112 */ "BIT8rm\000"
1935 /* 5119 */ "MOV8rm\000"
1936 /* 5126 */ "RRA16n\000"
1937 /* 5133 */ "SWPB16n\000"
1938 /* 5141 */ "RRC16n\000"
1939 /* 5148 */ "SEXT16n\000"
1940 /* 5156 */ "RRA8n\000"
1941 /* 5162 */ "RRC8n\000"
1942 /* 5168 */ "CALLn\000"
1943 /* 5174 */ "SUB16mn\000"
1944 /* 5182 */ "SUBC16mn\000"
1945 /* 5191 */ "ADDC16mn\000"
1946 /* 5200 */ "BIC16mn\000"
1947 /* 5208 */ "DADD16mn\000"
1948 /* 5217 */ "AND16mn\000"
1949 /* 5225 */ "CMP16mn\000"
1950 /* 5233 */ "XOR16mn\000"
1951 /* 5241 */ "BIS16mn\000"
1952 /* 5249 */ "BIT16mn\000"
1953 /* 5257 */ "MOV16mn\000"
1954 /* 5265 */ "SUB8mn\000"
1955 /* 5272 */ "SUBC8mn\000"
1956 /* 5280 */ "ADDC8mn\000"
1957 /* 5288 */ "BIC8mn\000"
1958 /* 5295 */ "DADD8mn\000"
1959 /* 5303 */ "AND8mn\000"
1960 /* 5310 */ "CMP8mn\000"
1961 /* 5317 */ "XOR8mn\000"
1962 /* 5324 */ "BIS8mn\000"
1963 /* 5331 */ "BIT8mn\000"
1964 /* 5338 */ "MOV8mn\000"
1965 /* 5345 */ "SUB16rn\000"
1966 /* 5353 */ "SUBC16rn\000"
1967 /* 5362 */ "ADDC16rn\000"
1968 /* 5371 */ "BIC16rn\000"
1969 /* 5379 */ "DADD16rn\000"
1970 /* 5388 */ "AND16rn\000"
1971 /* 5396 */ "CMP16rn\000"
1972 /* 5404 */ "XOR16rn\000"
1973 /* 5412 */ "BIS16rn\000"
1974 /* 5420 */ "BIT16rn\000"
1975 /* 5428 */ "MOV16rn\000"
1976 /* 5436 */ "SUB8rn\000"
1977 /* 5443 */ "SUBC8rn\000"
1978 /* 5451 */ "ADDC8rn\000"
1979 /* 5459 */ "BIC8rn\000"
1980 /* 5466 */ "DADD8rn\000"
1981 /* 5474 */ "AND8rn\000"
1982 /* 5481 */ "CMP8rn\000"
1983 /* 5488 */ "XOR8rn\000"
1984 /* 5495 */ "BIS8rn\000"
1985 /* 5502 */ "BIT8rn\000"
1986 /* 5509 */ "MOV8rn\000"
1987 /* 5516 */ "RRA16p\000"
1988 /* 5523 */ "SWPB16p\000"
1989 /* 5531 */ "RRC16p\000"
1990 /* 5538 */ "SEXT16p\000"
1991 /* 5546 */ "RRA8p\000"
1992 /* 5552 */ "RRC8p\000"
1993 /* 5558 */ "CALLp\000"
1994 /* 5564 */ "SUB16mp\000"
1995 /* 5572 */ "SUBC16mp\000"
1996 /* 5581 */ "ADDC16mp\000"
1997 /* 5590 */ "BIC16mp\000"
1998 /* 5598 */ "DADD16mp\000"
1999 /* 5607 */ "AND16mp\000"
2000 /* 5615 */ "CMP16mp\000"
2001 /* 5623 */ "XOR16mp\000"
2002 /* 5631 */ "BIS16mp\000"
2003 /* 5639 */ "BIT16mp\000"
2004 /* 5647 */ "SUB8mp\000"
2005 /* 5654 */ "SUBC8mp\000"
2006 /* 5662 */ "ADDC8mp\000"
2007 /* 5670 */ "BIC8mp\000"
2008 /* 5677 */ "DADD8mp\000"
2009 /* 5685 */ "AND8mp\000"
2010 /* 5692 */ "CMP8mp\000"
2011 /* 5699 */ "XOR8mp\000"
2012 /* 5706 */ "BIS8mp\000"
2013 /* 5713 */ "BIT8mp\000"
2014 /* 5720 */ "SUB16rp\000"
2015 /* 5728 */ "SUBC16rp\000"
2016 /* 5737 */ "ADDC16rp\000"
2017 /* 5746 */ "BIC16rp\000"
2018 /* 5754 */ "DADD16rp\000"
2019 /* 5763 */ "AND16rp\000"
2020 /* 5771 */ "CMP16rp\000"
2021 /* 5779 */ "XOR16rp\000"
2022 /* 5787 */ "BIS16rp\000"
2023 /* 5795 */ "BIT16rp\000"
2024 /* 5803 */ "MOV16rp\000"
2025 /* 5811 */ "SUB8rp\000"
2026 /* 5818 */ "SUBC8rp\000"
2027 /* 5826 */ "ADDC8rp\000"
2028 /* 5834 */ "BIC8rp\000"
2029 /* 5841 */ "DADD8rp\000"
2030 /* 5849 */ "AND8rp\000"
2031 /* 5856 */ "CMP8rp\000"
2032 /* 5863 */ "XOR8rp\000"
2033 /* 5870 */ "BIS8rp\000"
2034 /* 5877 */ "BIT8rp\000"
2035 /* 5884 */ "MOV8rp\000"
2036 /* 5891 */ "RRA16r\000"
2037 /* 5898 */ "SWPB16r\000"
2038 /* 5906 */ "RRC16r\000"
2039 /* 5913 */ "PUSH16r\000"
2040 /* 5921 */ "POP16r\000"
2041 /* 5928 */ "SEXT16r\000"
2042 /* 5936 */ "ZEXT16r\000"
2043 /* 5944 */ "RRA8r\000"
2044 /* 5950 */ "RRC8r\000"
2045 /* 5956 */ "PUSH8r\000"
2046 /* 5963 */ "Br\000"
2047 /* 5966 */ "CALLr\000"
2048 /* 5972 */ "SUB16mr\000"
2049 /* 5980 */ "SUBC16mr\000"
2050 /* 5989 */ "ADDC16mr\000"
2051 /* 5998 */ "BIC16mr\000"
2052 /* 6006 */ "DADD16mr\000"
2053 /* 6015 */ "AND16mr\000"
2054 /* 6023 */ "CMP16mr\000"
2055 /* 6031 */ "XOR16mr\000"
2056 /* 6039 */ "BIS16mr\000"
2057 /* 6047 */ "BIT16mr\000"
2058 /* 6055 */ "MOV16mr\000"
2059 /* 6063 */ "SUB8mr\000"
2060 /* 6070 */ "SUBC8mr\000"
2061 /* 6078 */ "ADDC8mr\000"
2062 /* 6086 */ "BIC8mr\000"
2063 /* 6093 */ "DADD8mr\000"
2064 /* 6101 */ "AND8mr\000"
2065 /* 6108 */ "CMP8mr\000"
2066 /* 6115 */ "XOR8mr\000"
2067 /* 6122 */ "BIS8mr\000"
2068 /* 6129 */ "BIT8mr\000"
2069 /* 6136 */ "MOV8mr\000"
2070 /* 6143 */ "SUB16rr\000"
2071 /* 6151 */ "SUBC16rr\000"
2072 /* 6160 */ "ADDC16rr\000"
2073 /* 6169 */ "BIC16rr\000"
2074 /* 6177 */ "DADD16rr\000"
2075 /* 6186 */ "AND16rr\000"
2076 /* 6194 */ "CMP16rr\000"
2077 /* 6202 */ "XOR16rr\000"
2078 /* 6210 */ "BIS16rr\000"
2079 /* 6218 */ "BIT16rr\000"
2080 /* 6226 */ "MOV16rr\000"
2081 /* 6234 */ "SUB8rr\000"
2082 /* 6241 */ "SUBC8rr\000"
2083 /* 6249 */ "ADDC8rr\000"
2084 /* 6257 */ "BIC8rr\000"
2085 /* 6264 */ "DADD8rr\000"
2086 /* 6272 */ "AND8rr\000"
2087 /* 6279 */ "CMP8rr\000"
2088 /* 6286 */ "XOR8rr\000"
2089 /* 6293 */ "BIS8rr\000"
2090 /* 6300 */ "BIT8rr\000"
2091 /* 6307 */ "MOV8rr\000"
2092};
2093#ifdef __GNUC__
2094#pragma GCC diagnostic pop
2095#endif
2096
2097extern const unsigned MSP430InstrNameIndices[] = {
2098 1333U, 1708U, 2453U, 2066U, 1397U, 1378U, 1406U, 1544U,
2099 1156U, 1171U, 1122U, 1109U, 1198U, 2949U, 957U, 3621U,
2100 1135U, 1329U, 1387U, 738U, 3974U, 860U, 3525U, 565U,
2101 689U, 726U, 2177U, 1532U, 3435U, 672U, 2388U, 1261U,
2102 3424U, 883U, 2361U, 2348U, 2514U, 3283U, 3306U, 1464U,
2103 1511U, 1484U, 1423U, 948U, 2479U, 2131U, 3979U, 2632U,
2104 2319U, 1005U, 3651U, 3681U, 1909U, 478U, 185U, 1647U,
2105 3723U, 3730U, 1674U, 1681U, 1688U, 1698U, 543U, 2817U,
2106 2780U, 2868U, 3695U, 1120U, 1331U, 3897U, 967U, 982U,
2107 1549U, 3251U, 2875U, 3562U, 2892U, 2703U, 259U, 2932U,
2108 3446U, 2844U, 3594U, 1048U, 2490U, 646U, 233U, 628U,
2109 3484U, 3465U, 1887U, 2539U, 2558U, 379U, 323U, 353U,
2110 364U, 304U, 334U, 927U, 911U, 2979U, 1212U, 1229U,
2111 494U, 191U, 549U, 510U, 2822U, 2786U, 3881U, 2035U,
2112 3864U, 2018U, 445U, 168U, 3799U, 1953U, 1803U, 1750U,
2113 2239U, 2217U, 587U, 3204U, 718U, 1278U, 578U, 3270U,
2114 3540U, 211U, 3027U, 3401U, 3054U, 3665U, 251U, 3390U,
2115 3378U, 3515U, 1253U, 3644U, 1185U, 3674U, 1450U, 2625U,
2116 2611U, 1443U, 2618U, 2837U, 1565U, 2294U, 2287U, 2301U,
2117 2308U, 3261U, 2123U, 759U, 2107U, 710U, 2115U, 751U,
2118 2099U, 702U, 2161U, 2153U, 1297U, 1289U, 3122U, 3112U,
2119 3102U, 3092U, 3142U, 3132U, 3925U, 3935U, 3152U, 3165U,
2120 3945U, 3955U, 3178U, 3191U, 403U, 147U, 1589U, 128U,
2121 297U, 3702U, 1653U, 3775U, 1360U, 2432U, 35U, 9U,
2122 1246U, 18U, 0U, 2407U, 2439U, 1149U, 3636U, 223U,
2123 1337U, 1351U, 2269U, 2278U, 3225U, 3238U, 2855U, 1924U,
2124 2966U, 1057U, 1852U, 1862U, 808U, 823U, 1739U, 1792U,
2125 1824U, 1838U, 3737U, 3763U, 3749U, 767U, 795U, 780U,
2126 484U, 1368U, 1987U, 3833U, 2011U, 3857U, 2862U, 619U,
2127 609U, 2448U, 3330U, 838U, 2684U, 2664U, 3358U, 3337U,
2128 2718U, 2749U, 2735U, 3009U, 4008U, 1091U, 4001U, 1073U,
2129 2340U, 2261U, 935U, 1456U, 2915U, 2059U, 2922U, 1880U,
2130 2907U, 2051U, 1872U, 26U, 1321U, 1313U, 1305U, 3571U,
2131 2655U, 3457U, 3502U, 3604U, 2466U, 847U, 280U, 1026U,
2132 896U, 431U, 154U, 1617U, 3709U, 1660U, 134U, 3579U,
2133 2416U, 2578U, 2594U, 3965U, 867U, 1038U, 3297U, 2169U,
2134 2210U, 2186U, 2198U, 410U, 1596U, 386U, 1572U, 3782U,
2135 1936U, 1771U, 1718U, 462U, 1631U, 527U, 2802U, 2764U,
2136 3816U, 1970U, 3840U, 1994U, 3911U, 3918U, 4058U, 4426U,
2137 4819U, 5209U, 5599U, 6007U, 4229U, 4597U, 4990U, 5380U,
2138 5755U, 6178U, 4145U, 4513U, 4906U, 5296U, 5678U, 6094U,
2139 4316U, 4684U, 5077U, 5467U, 5842U, 6265U, 4040U, 4408U,
2140 4801U, 5191U, 5581U, 5989U, 4211U, 4579U, 4972U, 5362U,
2141 5737U, 6160U, 4129U, 4497U, 4890U, 5280U, 5662U, 6078U,
2142 4300U, 4668U, 5061U, 5451U, 5826U, 6249U, 4365U, 2082U,
2143 2373U, 4066U, 4434U, 4827U, 5217U, 5607U, 6015U, 4237U,
2144 4605U, 4998U, 5388U, 5763U, 6186U, 4152U, 4520U, 4913U,
2145 5303U, 5685U, 6101U, 4323U, 4691U, 5084U, 5474U, 5849U,
2146 6272U, 4049U, 4417U, 4810U, 5200U, 5590U, 5998U, 4220U,
2147 4588U, 4981U, 5371U, 5746U, 6169U, 4137U, 4505U, 4898U,
2148 5288U, 5670U, 6086U, 4308U, 4676U, 5069U, 5459U, 5834U,
2149 6257U, 4090U, 4458U, 4851U, 5241U, 5631U, 6039U, 4261U,
2150 4629U, 5022U, 5412U, 5787U, 6210U, 4173U, 4541U, 4934U,
2151 5324U, 5706U, 6122U, 4344U, 4712U, 5105U, 5495U, 5870U,
2152 6293U, 4098U, 4466U, 4859U, 5249U, 5639U, 6047U, 4269U,
2153 4637U, 5030U, 5420U, 5795U, 6218U, 4180U, 4548U, 4941U,
2154 5331U, 5713U, 6129U, 4351U, 4719U, 5112U, 5502U, 5877U,
2155 6300U, 4382U, 4775U, 5963U, 4385U, 4778U, 5168U, 5558U,
2156 5966U, 4074U, 4442U, 4835U, 5225U, 5615U, 6023U, 4245U,
2157 4613U, 5006U, 5396U, 5771U, 6194U, 4159U, 4527U, 4920U,
2158 5310U, 5692U, 6108U, 4330U, 4698U, 5091U, 5481U, 5856U,
2159 6279U, 4057U, 4425U, 4818U, 5208U, 5598U, 6006U, 4228U,
2160 4596U, 4989U, 5379U, 5754U, 6177U, 4144U, 4512U, 4905U,
2161 5295U, 5677U, 6093U, 4315U, 4683U, 5076U, 5466U, 5841U,
2162 6264U, 207U, 2315U, 4106U, 4474U, 4867U, 5257U, 6055U,
2163 4277U, 4645U, 5038U, 5428U, 5803U, 6226U, 4187U, 4555U,
2164 4948U, 5338U, 6136U, 4358U, 4726U, 5119U, 5509U, 5884U,
2165 6307U, 98U, 109U, 5921U, 4015U, 4374U, 5913U, 5956U,
2166 3293U, 1346U, 4733U, 5126U, 5516U, 5891U, 4763U, 5156U,
2167 5546U, 5944U, 4748U, 5141U, 5531U, 5906U, 4769U, 5162U,
2168 5552U, 5950U, 49U, 82U, 4755U, 5148U, 5538U, 5928U,
2169 4023U, 4391U, 4784U, 5174U, 5564U, 5972U, 4194U, 4562U,
2170 4955U, 5345U, 5720U, 6143U, 4114U, 4482U, 4875U, 5265U,
2171 5647U, 6063U, 4285U, 4653U, 5046U, 5436U, 5811U, 6234U,
2172 4031U, 4399U, 4792U, 5182U, 5572U, 5980U, 4202U, 4570U,
2173 4963U, 5353U, 5728U, 6151U, 4121U, 4489U, 4882U, 5272U,
2174 5654U, 6070U, 4292U, 4660U, 5053U, 5443U, 5818U, 6241U,
2175 4740U, 5133U, 5523U, 5898U, 68U, 120U, 56U, 88U,
2176 43U, 77U, 62U, 93U, 4082U, 4450U, 4843U, 5233U,
2177 5623U, 6031U, 4253U, 4621U, 5014U, 5404U, 5779U, 6202U,
2178 4166U, 4534U, 4927U, 5317U, 5699U, 6115U, 4337U, 4705U,
2179 5098U, 5488U, 5863U, 6286U, 5936U,
2180};
2181
2182static inline void InitMSP430MCInstrInfo(MCInstrInfo *II) {
2183 II->InitMCInstrInfo(MSP430Descs.Insts, MSP430InstrNameIndices, MSP430InstrNameData, nullptr, nullptr, 653);
2184}
2185
2186} // end namespace llvm
2187#endif // GET_INSTRINFO_MC_DESC
2188
2189#ifdef GET_INSTRINFO_HEADER
2190#undef GET_INSTRINFO_HEADER
2191namespace llvm {
2192struct MSP430GenInstrInfo : public TargetInstrInfo {
2193 explicit MSP430GenInstrInfo(unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u);
2194 ~MSP430GenInstrInfo() override = default;
2195
2196};
2197} // end namespace llvm
2198#endif // GET_INSTRINFO_HEADER
2199
2200#ifdef GET_INSTRINFO_HELPER_DECLS
2201#undef GET_INSTRINFO_HELPER_DECLS
2202
2203
2204#endif // GET_INSTRINFO_HELPER_DECLS
2205
2206#ifdef GET_INSTRINFO_HELPERS
2207#undef GET_INSTRINFO_HELPERS
2208
2209#endif // GET_INSTRINFO_HELPERS
2210
2211#ifdef GET_INSTRINFO_CTOR_DTOR
2212#undef GET_INSTRINFO_CTOR_DTOR
2213namespace llvm {
2214extern const MSP430InstrTable MSP430Descs;
2215extern const unsigned MSP430InstrNameIndices[];
2216extern const char MSP430InstrNameData[];
2217MSP430GenInstrInfo::MSP430GenInstrInfo(unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode)
2218 : TargetInstrInfo(CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {
2219 InitMCInstrInfo(MSP430Descs.Insts, MSP430InstrNameIndices, MSP430InstrNameData, nullptr, nullptr, 653);
2220}
2221} // end namespace llvm
2222#endif // GET_INSTRINFO_CTOR_DTOR
2223
2224#ifdef GET_INSTRINFO_MC_HELPER_DECLS
2225#undef GET_INSTRINFO_MC_HELPER_DECLS
2226
2227namespace llvm {
2228class MCInst;
2229class FeatureBitset;
2230
2231namespace MSP430_MC {
2232
2233void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features);
2234
2235} // end namespace MSP430_MC
2236} // end namespace llvm
2237
2238#endif // GET_INSTRINFO_MC_HELPER_DECLS
2239
2240#ifdef GET_INSTRINFO_MC_HELPERS
2241#undef GET_INSTRINFO_MC_HELPERS
2242
2243namespace llvm::MSP430_MC {
2244} // end namespace llvm::MSP430_MC
2245#endif // GET_GENISTRINFO_MC_HELPERS
2246
2247#if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) ||\
2248 defined(GET_AVAILABLE_OPCODE_CHECKER)
2249#define GET_COMPUTE_FEATURES
2250#endif
2251#ifdef GET_COMPUTE_FEATURES
2252#undef GET_COMPUTE_FEATURES
2253namespace llvm::MSP430_MC {
2254// Bits for subtarget features that participate in instruction matching.
2255enum SubtargetFeatureBits : uint8_t {
2256};
2257
2258inline FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) {
2259 FeatureBitset Features;
2260 return Features;
2261}
2262
2263inline FeatureBitset computeRequiredFeatures(unsigned Opcode) {
2264 enum : uint8_t {
2265 CEFBS_None,
2266 };
2267
2268 static constexpr FeatureBitset FeatureBitsets[] = {
2269 {}, // CEFBS_None
2270 };
2271 static constexpr uint8_t RequiredFeaturesRefs[] = {
2272 CEFBS_None, // PHI = 0
2273 CEFBS_None, // INLINEASM = 1
2274 CEFBS_None, // INLINEASM_BR = 2
2275 CEFBS_None, // CFI_INSTRUCTION = 3
2276 CEFBS_None, // EH_LABEL = 4
2277 CEFBS_None, // GC_LABEL = 5
2278 CEFBS_None, // ANNOTATION_LABEL = 6
2279 CEFBS_None, // KILL = 7
2280 CEFBS_None, // EXTRACT_SUBREG = 8
2281 CEFBS_None, // INSERT_SUBREG = 9
2282 CEFBS_None, // IMPLICIT_DEF = 10
2283 CEFBS_None, // INIT_UNDEF = 11
2284 CEFBS_None, // SUBREG_TO_REG = 12
2285 CEFBS_None, // COPY_TO_REGCLASS = 13
2286 CEFBS_None, // DBG_VALUE = 14
2287 CEFBS_None, // DBG_VALUE_LIST = 15
2288 CEFBS_None, // DBG_INSTR_REF = 16
2289 CEFBS_None, // DBG_PHI = 17
2290 CEFBS_None, // DBG_LABEL = 18
2291 CEFBS_None, // REG_SEQUENCE = 19
2292 CEFBS_None, // COPY = 20
2293 CEFBS_None, // BUNDLE = 21
2294 CEFBS_None, // LIFETIME_START = 22
2295 CEFBS_None, // LIFETIME_END = 23
2296 CEFBS_None, // PSEUDO_PROBE = 24
2297 CEFBS_None, // ARITH_FENCE = 25
2298 CEFBS_None, // STACKMAP = 26
2299 CEFBS_None, // FENTRY_CALL = 27
2300 CEFBS_None, // PATCHPOINT = 28
2301 CEFBS_None, // LOAD_STACK_GUARD = 29
2302 CEFBS_None, // PREALLOCATED_SETUP = 30
2303 CEFBS_None, // PREALLOCATED_ARG = 31
2304 CEFBS_None, // STATEPOINT = 32
2305 CEFBS_None, // LOCAL_ESCAPE = 33
2306 CEFBS_None, // FAULTING_OP = 34
2307 CEFBS_None, // PATCHABLE_OP = 35
2308 CEFBS_None, // PATCHABLE_FUNCTION_ENTER = 36
2309 CEFBS_None, // PATCHABLE_RET = 37
2310 CEFBS_None, // PATCHABLE_FUNCTION_EXIT = 38
2311 CEFBS_None, // PATCHABLE_TAIL_CALL = 39
2312 CEFBS_None, // PATCHABLE_EVENT_CALL = 40
2313 CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL = 41
2314 CEFBS_None, // ICALL_BRANCH_FUNNEL = 42
2315 CEFBS_None, // FAKE_USE = 43
2316 CEFBS_None, // MEMBARRIER = 44
2317 CEFBS_None, // JUMP_TABLE_DEBUG_INFO = 45
2318 CEFBS_None, // CONVERGENCECTRL_ENTRY = 46
2319 CEFBS_None, // CONVERGENCECTRL_ANCHOR = 47
2320 CEFBS_None, // CONVERGENCECTRL_LOOP = 48
2321 CEFBS_None, // CONVERGENCECTRL_GLUE = 49
2322 CEFBS_None, // G_ASSERT_SEXT = 50
2323 CEFBS_None, // G_ASSERT_ZEXT = 51
2324 CEFBS_None, // G_ASSERT_ALIGN = 52
2325 CEFBS_None, // G_ADD = 53
2326 CEFBS_None, // G_SUB = 54
2327 CEFBS_None, // G_MUL = 55
2328 CEFBS_None, // G_SDIV = 56
2329 CEFBS_None, // G_UDIV = 57
2330 CEFBS_None, // G_SREM = 58
2331 CEFBS_None, // G_UREM = 59
2332 CEFBS_None, // G_SDIVREM = 60
2333 CEFBS_None, // G_UDIVREM = 61
2334 CEFBS_None, // G_AND = 62
2335 CEFBS_None, // G_OR = 63
2336 CEFBS_None, // G_XOR = 64
2337 CEFBS_None, // G_ABDS = 65
2338 CEFBS_None, // G_ABDU = 66
2339 CEFBS_None, // G_IMPLICIT_DEF = 67
2340 CEFBS_None, // G_PHI = 68
2341 CEFBS_None, // G_FRAME_INDEX = 69
2342 CEFBS_None, // G_GLOBAL_VALUE = 70
2343 CEFBS_None, // G_PTRAUTH_GLOBAL_VALUE = 71
2344 CEFBS_None, // G_CONSTANT_POOL = 72
2345 CEFBS_None, // G_EXTRACT = 73
2346 CEFBS_None, // G_UNMERGE_VALUES = 74
2347 CEFBS_None, // G_INSERT = 75
2348 CEFBS_None, // G_MERGE_VALUES = 76
2349 CEFBS_None, // G_BUILD_VECTOR = 77
2350 CEFBS_None, // G_BUILD_VECTOR_TRUNC = 78
2351 CEFBS_None, // G_CONCAT_VECTORS = 79
2352 CEFBS_None, // G_PTRTOINT = 80
2353 CEFBS_None, // G_INTTOPTR = 81
2354 CEFBS_None, // G_BITCAST = 82
2355 CEFBS_None, // G_FREEZE = 83
2356 CEFBS_None, // G_CONSTANT_FOLD_BARRIER = 84
2357 CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND = 85
2358 CEFBS_None, // G_INTRINSIC_TRUNC = 86
2359 CEFBS_None, // G_INTRINSIC_ROUND = 87
2360 CEFBS_None, // G_INTRINSIC_LRINT = 88
2361 CEFBS_None, // G_INTRINSIC_LLRINT = 89
2362 CEFBS_None, // G_INTRINSIC_ROUNDEVEN = 90
2363 CEFBS_None, // G_READCYCLECOUNTER = 91
2364 CEFBS_None, // G_READSTEADYCOUNTER = 92
2365 CEFBS_None, // G_LOAD = 93
2366 CEFBS_None, // G_SEXTLOAD = 94
2367 CEFBS_None, // G_ZEXTLOAD = 95
2368 CEFBS_None, // G_INDEXED_LOAD = 96
2369 CEFBS_None, // G_INDEXED_SEXTLOAD = 97
2370 CEFBS_None, // G_INDEXED_ZEXTLOAD = 98
2371 CEFBS_None, // G_STORE = 99
2372 CEFBS_None, // G_INDEXED_STORE = 100
2373 CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS = 101
2374 CEFBS_None, // G_ATOMIC_CMPXCHG = 102
2375 CEFBS_None, // G_ATOMICRMW_XCHG = 103
2376 CEFBS_None, // G_ATOMICRMW_ADD = 104
2377 CEFBS_None, // G_ATOMICRMW_SUB = 105
2378 CEFBS_None, // G_ATOMICRMW_AND = 106
2379 CEFBS_None, // G_ATOMICRMW_NAND = 107
2380 CEFBS_None, // G_ATOMICRMW_OR = 108
2381 CEFBS_None, // G_ATOMICRMW_XOR = 109
2382 CEFBS_None, // G_ATOMICRMW_MAX = 110
2383 CEFBS_None, // G_ATOMICRMW_MIN = 111
2384 CEFBS_None, // G_ATOMICRMW_UMAX = 112
2385 CEFBS_None, // G_ATOMICRMW_UMIN = 113
2386 CEFBS_None, // G_ATOMICRMW_FADD = 114
2387 CEFBS_None, // G_ATOMICRMW_FSUB = 115
2388 CEFBS_None, // G_ATOMICRMW_FMAX = 116
2389 CEFBS_None, // G_ATOMICRMW_FMIN = 117
2390 CEFBS_None, // G_ATOMICRMW_FMAXIMUM = 118
2391 CEFBS_None, // G_ATOMICRMW_FMINIMUM = 119
2392 CEFBS_None, // G_ATOMICRMW_UINC_WRAP = 120
2393 CEFBS_None, // G_ATOMICRMW_UDEC_WRAP = 121
2394 CEFBS_None, // G_ATOMICRMW_USUB_COND = 122
2395 CEFBS_None, // G_ATOMICRMW_USUB_SAT = 123
2396 CEFBS_None, // G_FENCE = 124
2397 CEFBS_None, // G_PREFETCH = 125
2398 CEFBS_None, // G_BRCOND = 126
2399 CEFBS_None, // G_BRINDIRECT = 127
2400 CEFBS_None, // G_INVOKE_REGION_START = 128
2401 CEFBS_None, // G_INTRINSIC = 129
2402 CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS = 130
2403 CEFBS_None, // G_INTRINSIC_CONVERGENT = 131
2404 CEFBS_None, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 132
2405 CEFBS_None, // G_ANYEXT = 133
2406 CEFBS_None, // G_TRUNC = 134
2407 CEFBS_None, // G_CONSTANT = 135
2408 CEFBS_None, // G_FCONSTANT = 136
2409 CEFBS_None, // G_VASTART = 137
2410 CEFBS_None, // G_VAARG = 138
2411 CEFBS_None, // G_SEXT = 139
2412 CEFBS_None, // G_SEXT_INREG = 140
2413 CEFBS_None, // G_ZEXT = 141
2414 CEFBS_None, // G_SHL = 142
2415 CEFBS_None, // G_LSHR = 143
2416 CEFBS_None, // G_ASHR = 144
2417 CEFBS_None, // G_FSHL = 145
2418 CEFBS_None, // G_FSHR = 146
2419 CEFBS_None, // G_ROTR = 147
2420 CEFBS_None, // G_ROTL = 148
2421 CEFBS_None, // G_ICMP = 149
2422 CEFBS_None, // G_FCMP = 150
2423 CEFBS_None, // G_SCMP = 151
2424 CEFBS_None, // G_UCMP = 152
2425 CEFBS_None, // G_SELECT = 153
2426 CEFBS_None, // G_UADDO = 154
2427 CEFBS_None, // G_UADDE = 155
2428 CEFBS_None, // G_USUBO = 156
2429 CEFBS_None, // G_USUBE = 157
2430 CEFBS_None, // G_SADDO = 158
2431 CEFBS_None, // G_SADDE = 159
2432 CEFBS_None, // G_SSUBO = 160
2433 CEFBS_None, // G_SSUBE = 161
2434 CEFBS_None, // G_UMULO = 162
2435 CEFBS_None, // G_SMULO = 163
2436 CEFBS_None, // G_UMULH = 164
2437 CEFBS_None, // G_SMULH = 165
2438 CEFBS_None, // G_UADDSAT = 166
2439 CEFBS_None, // G_SADDSAT = 167
2440 CEFBS_None, // G_USUBSAT = 168
2441 CEFBS_None, // G_SSUBSAT = 169
2442 CEFBS_None, // G_USHLSAT = 170
2443 CEFBS_None, // G_SSHLSAT = 171
2444 CEFBS_None, // G_SMULFIX = 172
2445 CEFBS_None, // G_UMULFIX = 173
2446 CEFBS_None, // G_SMULFIXSAT = 174
2447 CEFBS_None, // G_UMULFIXSAT = 175
2448 CEFBS_None, // G_SDIVFIX = 176
2449 CEFBS_None, // G_UDIVFIX = 177
2450 CEFBS_None, // G_SDIVFIXSAT = 178
2451 CEFBS_None, // G_UDIVFIXSAT = 179
2452 CEFBS_None, // G_FADD = 180
2453 CEFBS_None, // G_FSUB = 181
2454 CEFBS_None, // G_FMUL = 182
2455 CEFBS_None, // G_FMA = 183
2456 CEFBS_None, // G_FMAD = 184
2457 CEFBS_None, // G_FDIV = 185
2458 CEFBS_None, // G_FREM = 186
2459 CEFBS_None, // G_FPOW = 187
2460 CEFBS_None, // G_FPOWI = 188
2461 CEFBS_None, // G_FEXP = 189
2462 CEFBS_None, // G_FEXP2 = 190
2463 CEFBS_None, // G_FEXP10 = 191
2464 CEFBS_None, // G_FLOG = 192
2465 CEFBS_None, // G_FLOG2 = 193
2466 CEFBS_None, // G_FLOG10 = 194
2467 CEFBS_None, // G_FLDEXP = 195
2468 CEFBS_None, // G_FFREXP = 196
2469 CEFBS_None, // G_FNEG = 197
2470 CEFBS_None, // G_FPEXT = 198
2471 CEFBS_None, // G_FPTRUNC = 199
2472 CEFBS_None, // G_FPTOSI = 200
2473 CEFBS_None, // G_FPTOUI = 201
2474 CEFBS_None, // G_SITOFP = 202
2475 CEFBS_None, // G_UITOFP = 203
2476 CEFBS_None, // G_FPTOSI_SAT = 204
2477 CEFBS_None, // G_FPTOUI_SAT = 205
2478 CEFBS_None, // G_FABS = 206
2479 CEFBS_None, // G_FCOPYSIGN = 207
2480 CEFBS_None, // G_IS_FPCLASS = 208
2481 CEFBS_None, // G_FCANONICALIZE = 209
2482 CEFBS_None, // G_FMINNUM = 210
2483 CEFBS_None, // G_FMAXNUM = 211
2484 CEFBS_None, // G_FMINNUM_IEEE = 212
2485 CEFBS_None, // G_FMAXNUM_IEEE = 213
2486 CEFBS_None, // G_FMINIMUM = 214
2487 CEFBS_None, // G_FMAXIMUM = 215
2488 CEFBS_None, // G_FMINIMUMNUM = 216
2489 CEFBS_None, // G_FMAXIMUMNUM = 217
2490 CEFBS_None, // G_GET_FPENV = 218
2491 CEFBS_None, // G_SET_FPENV = 219
2492 CEFBS_None, // G_RESET_FPENV = 220
2493 CEFBS_None, // G_GET_FPMODE = 221
2494 CEFBS_None, // G_SET_FPMODE = 222
2495 CEFBS_None, // G_RESET_FPMODE = 223
2496 CEFBS_None, // G_PTR_ADD = 224
2497 CEFBS_None, // G_PTRMASK = 225
2498 CEFBS_None, // G_SMIN = 226
2499 CEFBS_None, // G_SMAX = 227
2500 CEFBS_None, // G_UMIN = 228
2501 CEFBS_None, // G_UMAX = 229
2502 CEFBS_None, // G_ABS = 230
2503 CEFBS_None, // G_LROUND = 231
2504 CEFBS_None, // G_LLROUND = 232
2505 CEFBS_None, // G_BR = 233
2506 CEFBS_None, // G_BRJT = 234
2507 CEFBS_None, // G_VSCALE = 235
2508 CEFBS_None, // G_INSERT_SUBVECTOR = 236
2509 CEFBS_None, // G_EXTRACT_SUBVECTOR = 237
2510 CEFBS_None, // G_INSERT_VECTOR_ELT = 238
2511 CEFBS_None, // G_EXTRACT_VECTOR_ELT = 239
2512 CEFBS_None, // G_SHUFFLE_VECTOR = 240
2513 CEFBS_None, // G_SPLAT_VECTOR = 241
2514 CEFBS_None, // G_STEP_VECTOR = 242
2515 CEFBS_None, // G_VECTOR_COMPRESS = 243
2516 CEFBS_None, // G_CTTZ = 244
2517 CEFBS_None, // G_CTTZ_ZERO_UNDEF = 245
2518 CEFBS_None, // G_CTLZ = 246
2519 CEFBS_None, // G_CTLZ_ZERO_UNDEF = 247
2520 CEFBS_None, // G_CTPOP = 248
2521 CEFBS_None, // G_BSWAP = 249
2522 CEFBS_None, // G_BITREVERSE = 250
2523 CEFBS_None, // G_FCEIL = 251
2524 CEFBS_None, // G_FCOS = 252
2525 CEFBS_None, // G_FSIN = 253
2526 CEFBS_None, // G_FSINCOS = 254
2527 CEFBS_None, // G_FTAN = 255
2528 CEFBS_None, // G_FACOS = 256
2529 CEFBS_None, // G_FASIN = 257
2530 CEFBS_None, // G_FATAN = 258
2531 CEFBS_None, // G_FATAN2 = 259
2532 CEFBS_None, // G_FCOSH = 260
2533 CEFBS_None, // G_FSINH = 261
2534 CEFBS_None, // G_FTANH = 262
2535 CEFBS_None, // G_FSQRT = 263
2536 CEFBS_None, // G_FFLOOR = 264
2537 CEFBS_None, // G_FRINT = 265
2538 CEFBS_None, // G_FNEARBYINT = 266
2539 CEFBS_None, // G_ADDRSPACE_CAST = 267
2540 CEFBS_None, // G_BLOCK_ADDR = 268
2541 CEFBS_None, // G_JUMP_TABLE = 269
2542 CEFBS_None, // G_DYN_STACKALLOC = 270
2543 CEFBS_None, // G_STACKSAVE = 271
2544 CEFBS_None, // G_STACKRESTORE = 272
2545 CEFBS_None, // G_STRICT_FADD = 273
2546 CEFBS_None, // G_STRICT_FSUB = 274
2547 CEFBS_None, // G_STRICT_FMUL = 275
2548 CEFBS_None, // G_STRICT_FDIV = 276
2549 CEFBS_None, // G_STRICT_FREM = 277
2550 CEFBS_None, // G_STRICT_FMA = 278
2551 CEFBS_None, // G_STRICT_FSQRT = 279
2552 CEFBS_None, // G_STRICT_FLDEXP = 280
2553 CEFBS_None, // G_READ_REGISTER = 281
2554 CEFBS_None, // G_WRITE_REGISTER = 282
2555 CEFBS_None, // G_MEMCPY = 283
2556 CEFBS_None, // G_MEMCPY_INLINE = 284
2557 CEFBS_None, // G_MEMMOVE = 285
2558 CEFBS_None, // G_MEMSET = 286
2559 CEFBS_None, // G_BZERO = 287
2560 CEFBS_None, // G_TRAP = 288
2561 CEFBS_None, // G_DEBUGTRAP = 289
2562 CEFBS_None, // G_UBSANTRAP = 290
2563 CEFBS_None, // G_VECREDUCE_SEQ_FADD = 291
2564 CEFBS_None, // G_VECREDUCE_SEQ_FMUL = 292
2565 CEFBS_None, // G_VECREDUCE_FADD = 293
2566 CEFBS_None, // G_VECREDUCE_FMUL = 294
2567 CEFBS_None, // G_VECREDUCE_FMAX = 295
2568 CEFBS_None, // G_VECREDUCE_FMIN = 296
2569 CEFBS_None, // G_VECREDUCE_FMAXIMUM = 297
2570 CEFBS_None, // G_VECREDUCE_FMINIMUM = 298
2571 CEFBS_None, // G_VECREDUCE_ADD = 299
2572 CEFBS_None, // G_VECREDUCE_MUL = 300
2573 CEFBS_None, // G_VECREDUCE_AND = 301
2574 CEFBS_None, // G_VECREDUCE_OR = 302
2575 CEFBS_None, // G_VECREDUCE_XOR = 303
2576 CEFBS_None, // G_VECREDUCE_SMAX = 304
2577 CEFBS_None, // G_VECREDUCE_SMIN = 305
2578 CEFBS_None, // G_VECREDUCE_UMAX = 306
2579 CEFBS_None, // G_VECREDUCE_UMIN = 307
2580 CEFBS_None, // G_SBFX = 308
2581 CEFBS_None, // G_UBFX = 309
2582 CEFBS_None, // ADD16mc = 310
2583 CEFBS_None, // ADD16mi = 311
2584 CEFBS_None, // ADD16mm = 312
2585 CEFBS_None, // ADD16mn = 313
2586 CEFBS_None, // ADD16mp = 314
2587 CEFBS_None, // ADD16mr = 315
2588 CEFBS_None, // ADD16rc = 316
2589 CEFBS_None, // ADD16ri = 317
2590 CEFBS_None, // ADD16rm = 318
2591 CEFBS_None, // ADD16rn = 319
2592 CEFBS_None, // ADD16rp = 320
2593 CEFBS_None, // ADD16rr = 321
2594 CEFBS_None, // ADD8mc = 322
2595 CEFBS_None, // ADD8mi = 323
2596 CEFBS_None, // ADD8mm = 324
2597 CEFBS_None, // ADD8mn = 325
2598 CEFBS_None, // ADD8mp = 326
2599 CEFBS_None, // ADD8mr = 327
2600 CEFBS_None, // ADD8rc = 328
2601 CEFBS_None, // ADD8ri = 329
2602 CEFBS_None, // ADD8rm = 330
2603 CEFBS_None, // ADD8rn = 331
2604 CEFBS_None, // ADD8rp = 332
2605 CEFBS_None, // ADD8rr = 333
2606 CEFBS_None, // ADDC16mc = 334
2607 CEFBS_None, // ADDC16mi = 335
2608 CEFBS_None, // ADDC16mm = 336
2609 CEFBS_None, // ADDC16mn = 337
2610 CEFBS_None, // ADDC16mp = 338
2611 CEFBS_None, // ADDC16mr = 339
2612 CEFBS_None, // ADDC16rc = 340
2613 CEFBS_None, // ADDC16ri = 341
2614 CEFBS_None, // ADDC16rm = 342
2615 CEFBS_None, // ADDC16rn = 343
2616 CEFBS_None, // ADDC16rp = 344
2617 CEFBS_None, // ADDC16rr = 345
2618 CEFBS_None, // ADDC8mc = 346
2619 CEFBS_None, // ADDC8mi = 347
2620 CEFBS_None, // ADDC8mm = 348
2621 CEFBS_None, // ADDC8mn = 349
2622 CEFBS_None, // ADDC8mp = 350
2623 CEFBS_None, // ADDC8mr = 351
2624 CEFBS_None, // ADDC8rc = 352
2625 CEFBS_None, // ADDC8ri = 353
2626 CEFBS_None, // ADDC8rm = 354
2627 CEFBS_None, // ADDC8rn = 355
2628 CEFBS_None, // ADDC8rp = 356
2629 CEFBS_None, // ADDC8rr = 357
2630 CEFBS_None, // ADDframe = 358
2631 CEFBS_None, // ADJCALLSTACKDOWN = 359
2632 CEFBS_None, // ADJCALLSTACKUP = 360
2633 CEFBS_None, // AND16mc = 361
2634 CEFBS_None, // AND16mi = 362
2635 CEFBS_None, // AND16mm = 363
2636 CEFBS_None, // AND16mn = 364
2637 CEFBS_None, // AND16mp = 365
2638 CEFBS_None, // AND16mr = 366
2639 CEFBS_None, // AND16rc = 367
2640 CEFBS_None, // AND16ri = 368
2641 CEFBS_None, // AND16rm = 369
2642 CEFBS_None, // AND16rn = 370
2643 CEFBS_None, // AND16rp = 371
2644 CEFBS_None, // AND16rr = 372
2645 CEFBS_None, // AND8mc = 373
2646 CEFBS_None, // AND8mi = 374
2647 CEFBS_None, // AND8mm = 375
2648 CEFBS_None, // AND8mn = 376
2649 CEFBS_None, // AND8mp = 377
2650 CEFBS_None, // AND8mr = 378
2651 CEFBS_None, // AND8rc = 379
2652 CEFBS_None, // AND8ri = 380
2653 CEFBS_None, // AND8rm = 381
2654 CEFBS_None, // AND8rn = 382
2655 CEFBS_None, // AND8rp = 383
2656 CEFBS_None, // AND8rr = 384
2657 CEFBS_None, // BIC16mc = 385
2658 CEFBS_None, // BIC16mi = 386
2659 CEFBS_None, // BIC16mm = 387
2660 CEFBS_None, // BIC16mn = 388
2661 CEFBS_None, // BIC16mp = 389
2662 CEFBS_None, // BIC16mr = 390
2663 CEFBS_None, // BIC16rc = 391
2664 CEFBS_None, // BIC16ri = 392
2665 CEFBS_None, // BIC16rm = 393
2666 CEFBS_None, // BIC16rn = 394
2667 CEFBS_None, // BIC16rp = 395
2668 CEFBS_None, // BIC16rr = 396
2669 CEFBS_None, // BIC8mc = 397
2670 CEFBS_None, // BIC8mi = 398
2671 CEFBS_None, // BIC8mm = 399
2672 CEFBS_None, // BIC8mn = 400
2673 CEFBS_None, // BIC8mp = 401
2674 CEFBS_None, // BIC8mr = 402
2675 CEFBS_None, // BIC8rc = 403
2676 CEFBS_None, // BIC8ri = 404
2677 CEFBS_None, // BIC8rm = 405
2678 CEFBS_None, // BIC8rn = 406
2679 CEFBS_None, // BIC8rp = 407
2680 CEFBS_None, // BIC8rr = 408
2681 CEFBS_None, // BIS16mc = 409
2682 CEFBS_None, // BIS16mi = 410
2683 CEFBS_None, // BIS16mm = 411
2684 CEFBS_None, // BIS16mn = 412
2685 CEFBS_None, // BIS16mp = 413
2686 CEFBS_None, // BIS16mr = 414
2687 CEFBS_None, // BIS16rc = 415
2688 CEFBS_None, // BIS16ri = 416
2689 CEFBS_None, // BIS16rm = 417
2690 CEFBS_None, // BIS16rn = 418
2691 CEFBS_None, // BIS16rp = 419
2692 CEFBS_None, // BIS16rr = 420
2693 CEFBS_None, // BIS8mc = 421
2694 CEFBS_None, // BIS8mi = 422
2695 CEFBS_None, // BIS8mm = 423
2696 CEFBS_None, // BIS8mn = 424
2697 CEFBS_None, // BIS8mp = 425
2698 CEFBS_None, // BIS8mr = 426
2699 CEFBS_None, // BIS8rc = 427
2700 CEFBS_None, // BIS8ri = 428
2701 CEFBS_None, // BIS8rm = 429
2702 CEFBS_None, // BIS8rn = 430
2703 CEFBS_None, // BIS8rp = 431
2704 CEFBS_None, // BIS8rr = 432
2705 CEFBS_None, // BIT16mc = 433
2706 CEFBS_None, // BIT16mi = 434
2707 CEFBS_None, // BIT16mm = 435
2708 CEFBS_None, // BIT16mn = 436
2709 CEFBS_None, // BIT16mp = 437
2710 CEFBS_None, // BIT16mr = 438
2711 CEFBS_None, // BIT16rc = 439
2712 CEFBS_None, // BIT16ri = 440
2713 CEFBS_None, // BIT16rm = 441
2714 CEFBS_None, // BIT16rn = 442
2715 CEFBS_None, // BIT16rp = 443
2716 CEFBS_None, // BIT16rr = 444
2717 CEFBS_None, // BIT8mc = 445
2718 CEFBS_None, // BIT8mi = 446
2719 CEFBS_None, // BIT8mm = 447
2720 CEFBS_None, // BIT8mn = 448
2721 CEFBS_None, // BIT8mp = 449
2722 CEFBS_None, // BIT8mr = 450
2723 CEFBS_None, // BIT8rc = 451
2724 CEFBS_None, // BIT8ri = 452
2725 CEFBS_None, // BIT8rm = 453
2726 CEFBS_None, // BIT8rn = 454
2727 CEFBS_None, // BIT8rp = 455
2728 CEFBS_None, // BIT8rr = 456
2729 CEFBS_None, // Bi = 457
2730 CEFBS_None, // Bm = 458
2731 CEFBS_None, // Br = 459
2732 CEFBS_None, // CALLi = 460
2733 CEFBS_None, // CALLm = 461
2734 CEFBS_None, // CALLn = 462
2735 CEFBS_None, // CALLp = 463
2736 CEFBS_None, // CALLr = 464
2737 CEFBS_None, // CMP16mc = 465
2738 CEFBS_None, // CMP16mi = 466
2739 CEFBS_None, // CMP16mm = 467
2740 CEFBS_None, // CMP16mn = 468
2741 CEFBS_None, // CMP16mp = 469
2742 CEFBS_None, // CMP16mr = 470
2743 CEFBS_None, // CMP16rc = 471
2744 CEFBS_None, // CMP16ri = 472
2745 CEFBS_None, // CMP16rm = 473
2746 CEFBS_None, // CMP16rn = 474
2747 CEFBS_None, // CMP16rp = 475
2748 CEFBS_None, // CMP16rr = 476
2749 CEFBS_None, // CMP8mc = 477
2750 CEFBS_None, // CMP8mi = 478
2751 CEFBS_None, // CMP8mm = 479
2752 CEFBS_None, // CMP8mn = 480
2753 CEFBS_None, // CMP8mp = 481
2754 CEFBS_None, // CMP8mr = 482
2755 CEFBS_None, // CMP8rc = 483
2756 CEFBS_None, // CMP8ri = 484
2757 CEFBS_None, // CMP8rm = 485
2758 CEFBS_None, // CMP8rn = 486
2759 CEFBS_None, // CMP8rp = 487
2760 CEFBS_None, // CMP8rr = 488
2761 CEFBS_None, // DADD16mc = 489
2762 CEFBS_None, // DADD16mi = 490
2763 CEFBS_None, // DADD16mm = 491
2764 CEFBS_None, // DADD16mn = 492
2765 CEFBS_None, // DADD16mp = 493
2766 CEFBS_None, // DADD16mr = 494
2767 CEFBS_None, // DADD16rc = 495
2768 CEFBS_None, // DADD16ri = 496
2769 CEFBS_None, // DADD16rm = 497
2770 CEFBS_None, // DADD16rn = 498
2771 CEFBS_None, // DADD16rp = 499
2772 CEFBS_None, // DADD16rr = 500
2773 CEFBS_None, // DADD8mc = 501
2774 CEFBS_None, // DADD8mi = 502
2775 CEFBS_None, // DADD8mm = 503
2776 CEFBS_None, // DADD8mn = 504
2777 CEFBS_None, // DADD8mp = 505
2778 CEFBS_None, // DADD8mr = 506
2779 CEFBS_None, // DADD8rc = 507
2780 CEFBS_None, // DADD8ri = 508
2781 CEFBS_None, // DADD8rm = 509
2782 CEFBS_None, // DADD8rn = 510
2783 CEFBS_None, // DADD8rp = 511
2784 CEFBS_None, // DADD8rr = 512
2785 CEFBS_None, // JCC = 513
2786 CEFBS_None, // JMP = 514
2787 CEFBS_None, // MOV16mc = 515
2788 CEFBS_None, // MOV16mi = 516
2789 CEFBS_None, // MOV16mm = 517
2790 CEFBS_None, // MOV16mn = 518
2791 CEFBS_None, // MOV16mr = 519
2792 CEFBS_None, // MOV16rc = 520
2793 CEFBS_None, // MOV16ri = 521
2794 CEFBS_None, // MOV16rm = 522
2795 CEFBS_None, // MOV16rn = 523
2796 CEFBS_None, // MOV16rp = 524
2797 CEFBS_None, // MOV16rr = 525
2798 CEFBS_None, // MOV8mc = 526
2799 CEFBS_None, // MOV8mi = 527
2800 CEFBS_None, // MOV8mm = 528
2801 CEFBS_None, // MOV8mn = 529
2802 CEFBS_None, // MOV8mr = 530
2803 CEFBS_None, // MOV8rc = 531
2804 CEFBS_None, // MOV8ri = 532
2805 CEFBS_None, // MOV8rm = 533
2806 CEFBS_None, // MOV8rn = 534
2807 CEFBS_None, // MOV8rp = 535
2808 CEFBS_None, // MOV8rr = 536
2809 CEFBS_None, // MOVZX16rm8 = 537
2810 CEFBS_None, // MOVZX16rr8 = 538
2811 CEFBS_None, // POP16r = 539
2812 CEFBS_None, // PUSH16c = 540
2813 CEFBS_None, // PUSH16i = 541
2814 CEFBS_None, // PUSH16r = 542
2815 CEFBS_None, // PUSH8r = 543
2816 CEFBS_None, // RET = 544
2817 CEFBS_None, // RETI = 545
2818 CEFBS_None, // RRA16m = 546
2819 CEFBS_None, // RRA16n = 547
2820 CEFBS_None, // RRA16p = 548
2821 CEFBS_None, // RRA16r = 549
2822 CEFBS_None, // RRA8m = 550
2823 CEFBS_None, // RRA8n = 551
2824 CEFBS_None, // RRA8p = 552
2825 CEFBS_None, // RRA8r = 553
2826 CEFBS_None, // RRC16m = 554
2827 CEFBS_None, // RRC16n = 555
2828 CEFBS_None, // RRC16p = 556
2829 CEFBS_None, // RRC16r = 557
2830 CEFBS_None, // RRC8m = 558
2831 CEFBS_None, // RRC8n = 559
2832 CEFBS_None, // RRC8p = 560
2833 CEFBS_None, // RRC8r = 561
2834 CEFBS_None, // Rrcl16 = 562
2835 CEFBS_None, // Rrcl8 = 563
2836 CEFBS_None, // SEXT16m = 564
2837 CEFBS_None, // SEXT16n = 565
2838 CEFBS_None, // SEXT16p = 566
2839 CEFBS_None, // SEXT16r = 567
2840 CEFBS_None, // SUB16mc = 568
2841 CEFBS_None, // SUB16mi = 569
2842 CEFBS_None, // SUB16mm = 570
2843 CEFBS_None, // SUB16mn = 571
2844 CEFBS_None, // SUB16mp = 572
2845 CEFBS_None, // SUB16mr = 573
2846 CEFBS_None, // SUB16rc = 574
2847 CEFBS_None, // SUB16ri = 575
2848 CEFBS_None, // SUB16rm = 576
2849 CEFBS_None, // SUB16rn = 577
2850 CEFBS_None, // SUB16rp = 578
2851 CEFBS_None, // SUB16rr = 579
2852 CEFBS_None, // SUB8mc = 580
2853 CEFBS_None, // SUB8mi = 581
2854 CEFBS_None, // SUB8mm = 582
2855 CEFBS_None, // SUB8mn = 583
2856 CEFBS_None, // SUB8mp = 584
2857 CEFBS_None, // SUB8mr = 585
2858 CEFBS_None, // SUB8rc = 586
2859 CEFBS_None, // SUB8ri = 587
2860 CEFBS_None, // SUB8rm = 588
2861 CEFBS_None, // SUB8rn = 589
2862 CEFBS_None, // SUB8rp = 590
2863 CEFBS_None, // SUB8rr = 591
2864 CEFBS_None, // SUBC16mc = 592
2865 CEFBS_None, // SUBC16mi = 593
2866 CEFBS_None, // SUBC16mm = 594
2867 CEFBS_None, // SUBC16mn = 595
2868 CEFBS_None, // SUBC16mp = 596
2869 CEFBS_None, // SUBC16mr = 597
2870 CEFBS_None, // SUBC16rc = 598
2871 CEFBS_None, // SUBC16ri = 599
2872 CEFBS_None, // SUBC16rm = 600
2873 CEFBS_None, // SUBC16rn = 601
2874 CEFBS_None, // SUBC16rp = 602
2875 CEFBS_None, // SUBC16rr = 603
2876 CEFBS_None, // SUBC8mc = 604
2877 CEFBS_None, // SUBC8mi = 605
2878 CEFBS_None, // SUBC8mm = 606
2879 CEFBS_None, // SUBC8mn = 607
2880 CEFBS_None, // SUBC8mp = 608
2881 CEFBS_None, // SUBC8mr = 609
2882 CEFBS_None, // SUBC8rc = 610
2883 CEFBS_None, // SUBC8ri = 611
2884 CEFBS_None, // SUBC8rm = 612
2885 CEFBS_None, // SUBC8rn = 613
2886 CEFBS_None, // SUBC8rp = 614
2887 CEFBS_None, // SUBC8rr = 615
2888 CEFBS_None, // SWPB16m = 616
2889 CEFBS_None, // SWPB16n = 617
2890 CEFBS_None, // SWPB16p = 618
2891 CEFBS_None, // SWPB16r = 619
2892 CEFBS_None, // Select16 = 620
2893 CEFBS_None, // Select8 = 621
2894 CEFBS_None, // Shl16 = 622
2895 CEFBS_None, // Shl8 = 623
2896 CEFBS_None, // Sra16 = 624
2897 CEFBS_None, // Sra8 = 625
2898 CEFBS_None, // Srl16 = 626
2899 CEFBS_None, // Srl8 = 627
2900 CEFBS_None, // XOR16mc = 628
2901 CEFBS_None, // XOR16mi = 629
2902 CEFBS_None, // XOR16mm = 630
2903 CEFBS_None, // XOR16mn = 631
2904 CEFBS_None, // XOR16mp = 632
2905 CEFBS_None, // XOR16mr = 633
2906 CEFBS_None, // XOR16rc = 634
2907 CEFBS_None, // XOR16ri = 635
2908 CEFBS_None, // XOR16rm = 636
2909 CEFBS_None, // XOR16rn = 637
2910 CEFBS_None, // XOR16rp = 638
2911 CEFBS_None, // XOR16rr = 639
2912 CEFBS_None, // XOR8mc = 640
2913 CEFBS_None, // XOR8mi = 641
2914 CEFBS_None, // XOR8mm = 642
2915 CEFBS_None, // XOR8mn = 643
2916 CEFBS_None, // XOR8mp = 644
2917 CEFBS_None, // XOR8mr = 645
2918 CEFBS_None, // XOR8rc = 646
2919 CEFBS_None, // XOR8ri = 647
2920 CEFBS_None, // XOR8rm = 648
2921 CEFBS_None, // XOR8rn = 649
2922 CEFBS_None, // XOR8rp = 650
2923 CEFBS_None, // XOR8rr = 651
2924 CEFBS_None, // ZEXT16r = 652
2925 };
2926
2927 assert(Opcode < 653);
2928 return FeatureBitsets[RequiredFeaturesRefs[Opcode]];
2929}
2930
2931} // end namespace llvm::MSP430_MC
2932#endif // GET_COMPUTE_FEATURES
2933
2934#ifdef GET_AVAILABLE_OPCODE_CHECKER
2935#undef GET_AVAILABLE_OPCODE_CHECKER
2936namespace llvm::MSP430_MC {
2937bool isOpcodeAvailable(unsigned Opcode, const FeatureBitset &Features) {
2938 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
2939 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
2940 FeatureBitset MissingFeatures =
2941 (AvailableFeatures & RequiredFeatures) ^
2942 RequiredFeatures;
2943 return !MissingFeatures.any();
2944}
2945} // end namespace llvm::MSP430_MC
2946#endif // GET_AVAILABLE_OPCODE_CHECKER
2947
2948#ifdef ENABLE_INSTR_PREDICATE_VERIFIER
2949#undef ENABLE_INSTR_PREDICATE_VERIFIER
2950#include <sstream>
2951
2952namespace llvm::MSP430_MC {
2953#ifndef NDEBUG
2954static const char *SubtargetFeatureNames[] = {
2955 nullptr
2956};
2957
2958#endif // NDEBUG
2959
2960void verifyInstructionPredicates(
2961 unsigned Opcode, const FeatureBitset &Features) {
2962#ifndef NDEBUG
2963 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
2964 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
2965 FeatureBitset MissingFeatures =
2966 (AvailableFeatures & RequiredFeatures) ^
2967 RequiredFeatures;
2968 if (MissingFeatures.any()) {
2969 std::ostringstream Msg;
2970 Msg << "Attempting to emit " << &MSP430InstrNameData[MSP430InstrNameIndices[Opcode]]
2971 << " instruction but the ";
2972 for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i)
2973 if (MissingFeatures.test(i))
2974 Msg << SubtargetFeatureNames[i] << " ";
2975 Msg << "predicate(s) are not met";
2976 report_fatal_error(Msg.str().c_str());
2977 }
2978#endif // NDEBUG
2979}
2980} // end namespace llvm::MSP430_MC
2981#endif // ENABLE_INSTR_PREDICATE_VERIFIER
2982
2983