1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register Enum Values *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9
10#ifdef GET_REGINFO_ENUM
11#undef GET_REGINFO_ENUM
12
13namespace llvm {
14
15class MCRegisterClass;
16extern const MCRegisterClass MSP430MCRegisterClasses[];
17
18namespace MSP430 {
19enum : unsigned {
20 NoRegister,
21 CG = 1,
22 CGB = 2,
23 PC = 3,
24 PCB = 4,
25 SP = 5,
26 SPB = 6,
27 SR = 7,
28 SRB = 8,
29 R4 = 9,
30 R5 = 10,
31 R6 = 11,
32 R7 = 12,
33 R8 = 13,
34 R9 = 14,
35 R10 = 15,
36 R11 = 16,
37 R12 = 17,
38 R13 = 18,
39 R14 = 19,
40 R15 = 20,
41 R4B = 21,
42 R5B = 22,
43 R6B = 23,
44 R7B = 24,
45 R8B = 25,
46 R9B = 26,
47 R10B = 27,
48 R11B = 28,
49 R12B = 29,
50 R13B = 30,
51 R14B = 31,
52 R15B = 32,
53 NUM_TARGET_REGS // 33
54};
55} // end namespace MSP430
56
57// Register classes
58
59namespace MSP430 {
60enum {
61 GR8RegClassID = 0,
62 GR16RegClassID = 1,
63
64};
65} // end namespace MSP430
66
67
68// Subregister indices
69
70namespace MSP430 {
71enum : uint16_t {
72 NoSubRegister,
73 subreg_8bit, // 1
74 NUM_TARGET_SUBREGS
75};
76} // end namespace MSP430
77
78// Register pressure sets enum.
79namespace MSP430 {
80enum RegisterPressureSets {
81 GR8 = 0,
82};
83} // end namespace MSP430
84
85} // end namespace llvm
86
87#endif // GET_REGINFO_ENUM
88
89/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
90|* *|
91|* MC Register Information *|
92|* *|
93|* Automatically generated file, do not edit! *|
94|* *|
95\*===----------------------------------------------------------------------===*/
96
97
98#ifdef GET_REGINFO_MC_DESC
99#undef GET_REGINFO_MC_DESC
100
101namespace llvm {
102
103extern const int16_t MSP430RegDiffLists[] = {
104 /* 0 */ -12, 0,
105 /* 2 */ -1, 0,
106 /* 4 */ 1, 0,
107 /* 6 */ 12, 0,
108};
109
110extern const LaneBitmask MSP430LaneMaskLists[] = {
111 /* 0 */ LaneBitmask(0x0000000000000001),
112 /* 1 */ LaneBitmask(0xFFFFFFFFFFFFFFFF),
113};
114
115extern const uint16_t MSP430SubRegIdxLists[] = {
116 /* 0 */ 1,
117};
118
119
120#ifdef __GNUC__
121#pragma GCC diagnostic push
122#pragma GCC diagnostic ignored "-Woverlength-strings"
123#endif
124extern const char MSP430RegStrings[] = {
125 /* 0 */ "R10\000"
126 /* 4 */ "R11\000"
127 /* 8 */ "R12\000"
128 /* 12 */ "R13\000"
129 /* 16 */ "R14\000"
130 /* 20 */ "R4\000"
131 /* 23 */ "R15\000"
132 /* 27 */ "R5\000"
133 /* 30 */ "R6\000"
134 /* 33 */ "R7\000"
135 /* 36 */ "R8\000"
136 /* 39 */ "R9\000"
137 /* 42 */ "R10B\000"
138 /* 47 */ "R11B\000"
139 /* 52 */ "R12B\000"
140 /* 57 */ "R13B\000"
141 /* 62 */ "R14B\000"
142 /* 67 */ "R4B\000"
143 /* 71 */ "R15B\000"
144 /* 76 */ "R5B\000"
145 /* 80 */ "R6B\000"
146 /* 84 */ "R7B\000"
147 /* 88 */ "R8B\000"
148 /* 92 */ "R9B\000"
149 /* 96 */ "PCB\000"
150 /* 100 */ "CGB\000"
151 /* 104 */ "SPB\000"
152 /* 108 */ "SRB\000"
153 /* 112 */ "PC\000"
154 /* 115 */ "CG\000"
155 /* 118 */ "SP\000"
156 /* 121 */ "SR\000"
157};
158#ifdef __GNUC__
159#pragma GCC diagnostic pop
160#endif
161
162extern const MCRegisterDesc MSP430RegDesc[] = { // Descriptors
163 { 3, 0, 0, 0, 0, 0, 0, 0 },
164 { 115, 4, 1, 0, 4096, 0, 0, 0 },
165 { 100, 1, 2, 1, 4096, 1, 0, 0 },
166 { 112, 4, 1, 0, 4097, 0, 0, 0 },
167 { 96, 1, 2, 1, 4097, 1, 0, 0 },
168 { 118, 4, 1, 0, 4098, 0, 0, 0 },
169 { 104, 1, 2, 1, 4098, 1, 0, 0 },
170 { 121, 4, 1, 0, 4099, 0, 0, 0 },
171 { 108, 1, 2, 1, 4099, 1, 0, 0 },
172 { 20, 6, 1, 0, 4100, 0, 0, 0 },
173 { 27, 6, 1, 0, 4101, 0, 0, 0 },
174 { 30, 6, 1, 0, 4102, 0, 0, 0 },
175 { 33, 6, 1, 0, 4103, 0, 0, 0 },
176 { 36, 6, 1, 0, 4104, 0, 0, 0 },
177 { 39, 6, 1, 0, 4105, 0, 0, 0 },
178 { 0, 6, 1, 0, 4106, 0, 0, 0 },
179 { 4, 6, 1, 0, 4107, 0, 0, 0 },
180 { 8, 6, 1, 0, 4108, 0, 0, 0 },
181 { 12, 6, 1, 0, 4109, 0, 0, 0 },
182 { 16, 6, 1, 0, 4110, 0, 0, 0 },
183 { 23, 6, 1, 0, 4111, 0, 0, 0 },
184 { 67, 1, 0, 1, 4100, 1, 0, 0 },
185 { 76, 1, 0, 1, 4101, 1, 0, 0 },
186 { 80, 1, 0, 1, 4102, 1, 0, 0 },
187 { 84, 1, 0, 1, 4103, 1, 0, 0 },
188 { 88, 1, 0, 1, 4104, 1, 0, 0 },
189 { 92, 1, 0, 1, 4105, 1, 0, 0 },
190 { 42, 1, 0, 1, 4106, 1, 0, 0 },
191 { 47, 1, 0, 1, 4107, 1, 0, 0 },
192 { 52, 1, 0, 1, 4108, 1, 0, 0 },
193 { 57, 1, 0, 1, 4109, 1, 0, 0 },
194 { 62, 1, 0, 1, 4110, 1, 0, 0 },
195 { 71, 1, 0, 1, 4111, 1, 0, 0 },
196};
197
198extern const MCPhysReg MSP430RegUnitRoots[][2] = {
199 { MSP430::CGB },
200 { MSP430::PCB },
201 { MSP430::SPB },
202 { MSP430::SRB },
203 { MSP430::R4B },
204 { MSP430::R5B },
205 { MSP430::R6B },
206 { MSP430::R7B },
207 { MSP430::R8B },
208 { MSP430::R9B },
209 { MSP430::R10B },
210 { MSP430::R11B },
211 { MSP430::R12B },
212 { MSP430::R13B },
213 { MSP430::R14B },
214 { MSP430::R15B },
215};
216
217namespace { // Register classes...
218 // GR8 Register Class...
219 const MCPhysReg GR8[] = {
220 MSP430::R12B, MSP430::R13B, MSP430::R14B, MSP430::R15B, MSP430::R11B, MSP430::R10B, MSP430::R9B, MSP430::R8B, MSP430::R7B, MSP430::R6B, MSP430::R5B, MSP430::R4B, MSP430::PCB, MSP430::SPB, MSP430::SRB, MSP430::CGB,
221 };
222
223 // GR8 Bit set.
224 const uint8_t GR8Bits[] = {
225 0x54, 0x01, 0xe0, 0xff, 0x01,
226 };
227
228 // GR16 Register Class...
229 const MCPhysReg GR16[] = {
230 MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15, MSP430::R11, MSP430::R10, MSP430::R9, MSP430::R8, MSP430::R7, MSP430::R6, MSP430::R5, MSP430::R4, MSP430::PC, MSP430::SP, MSP430::SR, MSP430::CG,
231 };
232
233 // GR16 Bit set.
234 const uint8_t GR16Bits[] = {
235 0xaa, 0xfe, 0x1f,
236 };
237
238} // end anonymous namespace
239
240
241#ifdef __GNUC__
242#pragma GCC diagnostic push
243#pragma GCC diagnostic ignored "-Woverlength-strings"
244#endif
245extern const char MSP430RegClassStrings[] = {
246 /* 0 */ "GR16\000"
247 /* 5 */ "GR8\000"
248};
249#ifdef __GNUC__
250#pragma GCC diagnostic pop
251#endif
252
253extern const MCRegisterClass MSP430MCRegisterClasses[] = {
254 { GR8, GR8Bits, 5, 16, sizeof(GR8Bits), MSP430::GR8RegClassID, 8, 1, true, false },
255 { GR16, GR16Bits, 0, 16, sizeof(GR16Bits), MSP430::GR16RegClassID, 16, 1, true, false },
256};
257
258// MSP430 Dwarf<->LLVM register mappings.
259extern const MCRegisterInfo::DwarfLLVMRegPair MSP430DwarfFlavour0Dwarf2L[] = {
260 { 0U, MSP430::PC },
261 { 1U, MSP430::SP },
262 { 2U, MSP430::SR },
263 { 3U, MSP430::CG },
264 { 4U, MSP430::R4 },
265 { 5U, MSP430::R5 },
266 { 6U, MSP430::R6 },
267 { 7U, MSP430::R7 },
268 { 8U, MSP430::R8 },
269 { 9U, MSP430::R9 },
270 { 10U, MSP430::R10 },
271 { 11U, MSP430::R11 },
272 { 12U, MSP430::R12 },
273 { 13U, MSP430::R13 },
274 { 14U, MSP430::R14 },
275 { 15U, MSP430::R15 },
276 { 16U, MSP430::PCB },
277 { 17U, MSP430::SPB },
278 { 18U, MSP430::SRB },
279 { 19U, MSP430::CGB },
280 { 20U, MSP430::R4B },
281 { 21U, MSP430::R5B },
282 { 22U, MSP430::R6B },
283 { 23U, MSP430::R7B },
284 { 24U, MSP430::R8B },
285 { 25U, MSP430::R9B },
286 { 26U, MSP430::R10B },
287 { 27U, MSP430::R11B },
288 { 28U, MSP430::R12B },
289 { 29U, MSP430::R13B },
290 { 30U, MSP430::R14B },
291 { 31U, MSP430::R15B },
292};
293extern const unsigned MSP430DwarfFlavour0Dwarf2LSize = std::size(MSP430DwarfFlavour0Dwarf2L);
294
295extern const MCRegisterInfo::DwarfLLVMRegPair MSP430EHFlavour0Dwarf2L[] = {
296 { 0U, MSP430::PC },
297 { 1U, MSP430::SP },
298 { 2U, MSP430::SR },
299 { 3U, MSP430::CG },
300 { 4U, MSP430::R4 },
301 { 5U, MSP430::R5 },
302 { 6U, MSP430::R6 },
303 { 7U, MSP430::R7 },
304 { 8U, MSP430::R8 },
305 { 9U, MSP430::R9 },
306 { 10U, MSP430::R10 },
307 { 11U, MSP430::R11 },
308 { 12U, MSP430::R12 },
309 { 13U, MSP430::R13 },
310 { 14U, MSP430::R14 },
311 { 15U, MSP430::R15 },
312 { 16U, MSP430::PCB },
313 { 17U, MSP430::SPB },
314 { 18U, MSP430::SRB },
315 { 19U, MSP430::CGB },
316 { 20U, MSP430::R4B },
317 { 21U, MSP430::R5B },
318 { 22U, MSP430::R6B },
319 { 23U, MSP430::R7B },
320 { 24U, MSP430::R8B },
321 { 25U, MSP430::R9B },
322 { 26U, MSP430::R10B },
323 { 27U, MSP430::R11B },
324 { 28U, MSP430::R12B },
325 { 29U, MSP430::R13B },
326 { 30U, MSP430::R14B },
327 { 31U, MSP430::R15B },
328};
329extern const unsigned MSP430EHFlavour0Dwarf2LSize = std::size(MSP430EHFlavour0Dwarf2L);
330
331extern const MCRegisterInfo::DwarfLLVMRegPair MSP430DwarfFlavour0L2Dwarf[] = {
332 { MSP430::CG, 3U },
333 { MSP430::CGB, 19U },
334 { MSP430::PC, 0U },
335 { MSP430::PCB, 16U },
336 { MSP430::SP, 1U },
337 { MSP430::SPB, 17U },
338 { MSP430::SR, 2U },
339 { MSP430::SRB, 18U },
340 { MSP430::R4, 4U },
341 { MSP430::R5, 5U },
342 { MSP430::R6, 6U },
343 { MSP430::R7, 7U },
344 { MSP430::R8, 8U },
345 { MSP430::R9, 9U },
346 { MSP430::R10, 10U },
347 { MSP430::R11, 11U },
348 { MSP430::R12, 12U },
349 { MSP430::R13, 13U },
350 { MSP430::R14, 14U },
351 { MSP430::R15, 15U },
352 { MSP430::R4B, 20U },
353 { MSP430::R5B, 21U },
354 { MSP430::R6B, 22U },
355 { MSP430::R7B, 23U },
356 { MSP430::R8B, 24U },
357 { MSP430::R9B, 25U },
358 { MSP430::R10B, 26U },
359 { MSP430::R11B, 27U },
360 { MSP430::R12B, 28U },
361 { MSP430::R13B, 29U },
362 { MSP430::R14B, 30U },
363 { MSP430::R15B, 31U },
364};
365extern const unsigned MSP430DwarfFlavour0L2DwarfSize = std::size(MSP430DwarfFlavour0L2Dwarf);
366
367extern const MCRegisterInfo::DwarfLLVMRegPair MSP430EHFlavour0L2Dwarf[] = {
368 { MSP430::CG, 3U },
369 { MSP430::CGB, 19U },
370 { MSP430::PC, 0U },
371 { MSP430::PCB, 16U },
372 { MSP430::SP, 1U },
373 { MSP430::SPB, 17U },
374 { MSP430::SR, 2U },
375 { MSP430::SRB, 18U },
376 { MSP430::R4, 4U },
377 { MSP430::R5, 5U },
378 { MSP430::R6, 6U },
379 { MSP430::R7, 7U },
380 { MSP430::R8, 8U },
381 { MSP430::R9, 9U },
382 { MSP430::R10, 10U },
383 { MSP430::R11, 11U },
384 { MSP430::R12, 12U },
385 { MSP430::R13, 13U },
386 { MSP430::R14, 14U },
387 { MSP430::R15, 15U },
388 { MSP430::R4B, 20U },
389 { MSP430::R5B, 21U },
390 { MSP430::R6B, 22U },
391 { MSP430::R7B, 23U },
392 { MSP430::R8B, 24U },
393 { MSP430::R9B, 25U },
394 { MSP430::R10B, 26U },
395 { MSP430::R11B, 27U },
396 { MSP430::R12B, 28U },
397 { MSP430::R13B, 29U },
398 { MSP430::R14B, 30U },
399 { MSP430::R15B, 31U },
400};
401extern const unsigned MSP430EHFlavour0L2DwarfSize = std::size(MSP430EHFlavour0L2Dwarf);
402
403extern const uint16_t MSP430RegEncodingTable[] = {
404 0,
405 3,
406 3,
407 0,
408 0,
409 1,
410 1,
411 2,
412 2,
413 4,
414 5,
415 6,
416 7,
417 8,
418 9,
419 10,
420 11,
421 12,
422 13,
423 14,
424 15,
425 4,
426 5,
427 6,
428 7,
429 8,
430 9,
431 10,
432 11,
433 12,
434 13,
435 14,
436 15,
437};
438static inline void InitMSP430MCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
439 RI->InitMCRegisterInfo(MSP430RegDesc, 33, RA, PC, MSP430MCRegisterClasses, 2, MSP430RegUnitRoots, 16, MSP430RegDiffLists, MSP430LaneMaskLists, MSP430RegStrings, MSP430RegClassStrings, MSP430SubRegIdxLists, 2,
440MSP430RegEncodingTable);
441
442 switch (DwarfFlavour) {
443 default:
444 llvm_unreachable("Unknown DWARF flavour");
445 case 0:
446 RI->mapDwarfRegsToLLVMRegs(MSP430DwarfFlavour0Dwarf2L, MSP430DwarfFlavour0Dwarf2LSize, false);
447 break;
448 }
449 switch (EHFlavour) {
450 default:
451 llvm_unreachable("Unknown DWARF flavour");
452 case 0:
453 RI->mapDwarfRegsToLLVMRegs(MSP430EHFlavour0Dwarf2L, MSP430EHFlavour0Dwarf2LSize, true);
454 break;
455 }
456 switch (DwarfFlavour) {
457 default:
458 llvm_unreachable("Unknown DWARF flavour");
459 case 0:
460 RI->mapLLVMRegsToDwarfRegs(MSP430DwarfFlavour0L2Dwarf, MSP430DwarfFlavour0L2DwarfSize, false);
461 break;
462 }
463 switch (EHFlavour) {
464 default:
465 llvm_unreachable("Unknown DWARF flavour");
466 case 0:
467 RI->mapLLVMRegsToDwarfRegs(MSP430EHFlavour0L2Dwarf, MSP430EHFlavour0L2DwarfSize, true);
468 break;
469 }
470}
471
472} // end namespace llvm
473
474#endif // GET_REGINFO_MC_DESC
475
476/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
477|* *|
478|* Register Information Header Fragment *|
479|* *|
480|* Automatically generated file, do not edit! *|
481|* *|
482\*===----------------------------------------------------------------------===*/
483
484
485#ifdef GET_REGINFO_HEADER
486#undef GET_REGINFO_HEADER
487
488#include "llvm/CodeGen/TargetRegisterInfo.h"
489
490namespace llvm {
491
492class MSP430FrameLowering;
493
494struct MSP430GenRegisterInfo : public TargetRegisterInfo {
495 explicit MSP430GenRegisterInfo(unsigned RA, unsigned D = 0, unsigned E = 0,
496 unsigned PC = 0, unsigned HwMode = 0);
497 unsigned composeSubRegIndicesImpl(unsigned, unsigned) const override;
498 unsigned reverseComposeSubRegIndicesImpl(unsigned, unsigned) const override;
499 LaneBitmask composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
500 LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
501 const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass *, unsigned) const override;
502 const TargetRegisterClass *getSubRegisterClass(const TargetRegisterClass *, unsigned) const override;
503 const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override;
504 unsigned getRegUnitWeight(unsigned RegUnit) const override;
505 unsigned getNumRegPressureSets() const override;
506 const char *getRegPressureSetName(unsigned Idx) const override;
507 unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override;
508 const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override;
509 const int *getRegUnitPressureSets(unsigned RegUnit) const override;
510 ArrayRef<const char *> getRegMaskNames() const override;
511 ArrayRef<const uint32_t *> getRegMasks() const override;
512 bool isGeneralPurposeRegister(const MachineFunction &, MCRegister) const override;
513 bool isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const override;
514 bool isFixedRegister(const MachineFunction &, MCRegister) const override;
515 bool isArgumentRegister(const MachineFunction &, MCRegister) const override;
516 bool isConstantPhysReg(MCRegister PhysReg) const override final;
517 /// Devirtualized TargetFrameLowering.
518 static const MSP430FrameLowering *getFrameLowering(
519 const MachineFunction &MF);
520};
521
522namespace MSP430 { // Register classes
523 extern const TargetRegisterClass GR8RegClass;
524 extern const TargetRegisterClass GR16RegClass;
525} // end namespace MSP430
526
527} // end namespace llvm
528
529#endif // GET_REGINFO_HEADER
530
531/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
532|* *|
533|* Target Register and Register Classes Information *|
534|* *|
535|* Automatically generated file, do not edit! *|
536|* *|
537\*===----------------------------------------------------------------------===*/
538
539
540#ifdef GET_REGINFO_TARGET_DESC
541#undef GET_REGINFO_TARGET_DESC
542
543namespace llvm {
544
545extern const MCRegisterClass MSP430MCRegisterClasses[];
546
547static const MVT::SimpleValueType VTLists[] = {
548 /* 0 */ MVT::i8, MVT::Other,
549 /* 2 */ MVT::i16, MVT::Other,
550};
551
552static const char *SubRegIndexNameTable[] = { "subreg_8bit", "" };
553
554static const TargetRegisterInfo::SubRegCoveredBits SubRegIdxRangeTable[] = {
555 { 65535, 65535 },
556 { 0, 8 }, // subreg_8bit
557};
558
559
560static const LaneBitmask SubRegIndexLaneMaskTable[] = {
561 LaneBitmask::getAll(),
562 LaneBitmask(0x0000000000000001), // subreg_8bit
563 };
564
565
566
567static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
568 // Mode = 0 (Default)
569 { 8, 8, 8, /*VTLists+*/0 }, // GR8
570 { 16, 16, 16, /*VTLists+*/2 }, // GR16
571};
572static const uint32_t GR8SubClassMask[] = {
573 0x00000001,
574 0x00000002, // subreg_8bit
575};
576
577static const uint32_t GR16SubClassMask[] = {
578 0x00000002,
579};
580
581static const uint16_t SuperRegIdxSeqs[] = {
582 /* 0 */ 1, 0,
583};
584
585
586namespace MSP430 { // Register class instances
587 extern const TargetRegisterClass GR8RegClass = {
588 &MSP430MCRegisterClasses[GR8RegClassID],
589 GR8SubClassMask,
590 SuperRegIdxSeqs + 0,
591 LaneBitmask(0x0000000000000001),
592 0,
593 false,
594 0x00, /* TSFlags */
595 false, /* HasDisjunctSubRegs */
596 false, /* CoveredBySubRegs */
597 nullptr, 0,
598 nullptr
599 };
600
601 extern const TargetRegisterClass GR16RegClass = {
602 &MSP430MCRegisterClasses[GR16RegClassID],
603 GR16SubClassMask,
604 SuperRegIdxSeqs + 1,
605 LaneBitmask(0x0000000000000001),
606 0,
607 false,
608 0x00, /* TSFlags */
609 false, /* HasDisjunctSubRegs */
610 false, /* CoveredBySubRegs */
611 nullptr, 0,
612 nullptr
613 };
614
615} // end namespace MSP430
616
617namespace {
618 const TargetRegisterClass *const RegisterClasses[] = {
619 &MSP430::GR8RegClass,
620 &MSP430::GR16RegClass,
621 };
622} // end anonymous namespace
623
624static const uint8_t CostPerUseTable[] = {
6250, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
626
627
628static const bool InAllocatableClassTable[] = {
629false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, };
630
631
632static const TargetRegisterInfoDesc MSP430RegInfoDesc = { // Extra Descriptors
633CostPerUseTable, 1, InAllocatableClassTable};
634
635unsigned MSP430GenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
636 static const uint8_t Rows[1][1] = {
637 { 0, },
638 };
639
640 --IdxA; assert(IdxA < 1); (void) IdxA;
641 --IdxB; assert(IdxB < 1);
642 return Rows[0][IdxB];
643}
644
645unsigned MSP430GenRegisterInfo::reverseComposeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
646 static const uint8_t Table[1][1] = {
647 { 0, },
648 };
649
650 --IdxA; assert(IdxA < 1);
651 --IdxB; assert(IdxB < 1);
652 return Table[IdxA][IdxB];
653 }
654
655 struct MaskRolOp {
656 LaneBitmask Mask;
657 uint8_t RotateLeft;
658 };
659 static const MaskRolOp LaneMaskComposeSequences[] = {
660 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 0 }, { LaneBitmask::getNone(), 0 } // Sequence 0
661 };
662 static const uint8_t CompositeSequences[] = {
663 0 // to subreg_8bit
664 };
665
666LaneBitmask MSP430GenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
667 --IdxA; assert(IdxA < 1 && "Subregister index out of bounds");
668 LaneBitmask Result;
669 for (const MaskRolOp *Ops =
670 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
671 Ops->Mask.any(); ++Ops) {
672 LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
673 if (unsigned S = Ops->RotateLeft)
674 Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));
675 else
676 Result |= LaneBitmask(M);
677 }
678 return Result;
679}
680
681LaneBitmask MSP430GenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
682 LaneMask &= getSubRegIndexLaneMask(IdxA);
683 --IdxA; assert(IdxA < 1 && "Subregister index out of bounds");
684 LaneBitmask Result;
685 for (const MaskRolOp *Ops =
686 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
687 Ops->Mask.any(); ++Ops) {
688 LaneBitmask::Type M = LaneMask.getAsInteger();
689 if (unsigned S = Ops->RotateLeft)
690 Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));
691 else
692 Result |= LaneBitmask(M);
693 }
694 return Result;
695}
696
697const TargetRegisterClass *MSP430GenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
698 static const uint8_t Table[2][1] = {
699 { // GR8
700 0, // subreg_8bit
701 },
702 { // GR16
703 2, // subreg_8bit -> GR16
704 },
705 };
706 assert(RC && "Missing regclass");
707 if (!Idx) return RC;
708 --Idx;
709 assert(Idx < 1 && "Bad subreg");
710 unsigned TV = Table[RC->getID()][Idx];
711 return TV ? getRegClass(TV - 1) : nullptr;
712}
713
714const TargetRegisterClass *MSP430GenRegisterInfo::getSubRegisterClass(const TargetRegisterClass *RC, unsigned Idx) const {
715 static const uint8_t Table[2][1] = {
716 { // GR8
717 0, // GR8:subreg_8bit
718 },
719 { // GR16
720 1, // GR16:subreg_8bit -> GR8
721 },
722 };
723 assert(RC && "Missing regclass");
724 if (!Idx) return RC;
725 --Idx;
726 assert(Idx < 1 && "Bad subreg");
727 unsigned TV = Table[RC->getID()][Idx];
728 return TV ? getRegClass(TV - 1) : nullptr;
729}
730
731/// Get the weight in units of pressure for this register class.
732const RegClassWeight &MSP430GenRegisterInfo::
733getRegClassWeight(const TargetRegisterClass *RC) const {
734 static const RegClassWeight RCWeightTable[] = {
735 {1, 16}, // GR8
736 {1, 16}, // GR16
737 };
738 return RCWeightTable[RC->getID()];
739}
740
741/// Get the weight in units of pressure for this register unit.
742unsigned MSP430GenRegisterInfo::
743getRegUnitWeight(unsigned RegUnit) const {
744 assert(RegUnit < 16 && "invalid register unit");
745 // All register units have unit weight.
746 return 1;
747}
748
749
750// Get the number of dimensions of register pressure.
751unsigned MSP430GenRegisterInfo::getNumRegPressureSets() const {
752 return 1;
753}
754
755// Get the name of this register unit pressure set.
756const char *MSP430GenRegisterInfo::
757getRegPressureSetName(unsigned Idx) const {
758 static const char *PressureNameTable[] = {
759 "GR8",
760 };
761 return PressureNameTable[Idx];
762}
763
764// Get the register unit pressure limit for this dimension.
765// This limit must be adjusted dynamically for reserved registers.
766unsigned MSP430GenRegisterInfo::
767getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
768 static const uint8_t PressureLimitTable[] = {
769 16, // 0: GR8
770 };
771 return PressureLimitTable[Idx];
772}
773
774/// Table of pressure sets per register class or unit.
775static const int RCSetsTable[] = {
776 /* 0 */ 0, -1,
777};
778
779/// Get the dimensions of register pressure impacted by this register class.
780/// Returns a -1 terminated array of pressure set IDs
781const int *MSP430GenRegisterInfo::
782getRegClassPressureSets(const TargetRegisterClass *RC) const {
783 static const uint8_t RCSetStartTable[] = {
784 0,0,};
785 return &RCSetsTable[RCSetStartTable[RC->getID()]];
786}
787
788/// Get the dimensions of register pressure impacted by this register unit.
789/// Returns a -1 terminated array of pressure set IDs
790const int *MSP430GenRegisterInfo::
791getRegUnitPressureSets(unsigned RegUnit) const {
792 assert(RegUnit < 16 && "invalid register unit");
793 static const uint8_t RUSetStartTable[] = {
794 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,};
795 return &RCSetsTable[RUSetStartTable[RegUnit]];
796}
797
798extern const MCRegisterDesc MSP430RegDesc[];
799extern const int16_t MSP430RegDiffLists[];
800extern const LaneBitmask MSP430LaneMaskLists[];
801extern const char MSP430RegStrings[];
802extern const char MSP430RegClassStrings[];
803extern const MCPhysReg MSP430RegUnitRoots[][2];
804extern const uint16_t MSP430SubRegIdxLists[];
805extern const uint16_t MSP430RegEncodingTable[];
806// MSP430 Dwarf<->LLVM register mappings.
807extern const MCRegisterInfo::DwarfLLVMRegPair MSP430DwarfFlavour0Dwarf2L[];
808extern const unsigned MSP430DwarfFlavour0Dwarf2LSize;
809
810extern const MCRegisterInfo::DwarfLLVMRegPair MSP430EHFlavour0Dwarf2L[];
811extern const unsigned MSP430EHFlavour0Dwarf2LSize;
812
813extern const MCRegisterInfo::DwarfLLVMRegPair MSP430DwarfFlavour0L2Dwarf[];
814extern const unsigned MSP430DwarfFlavour0L2DwarfSize;
815
816extern const MCRegisterInfo::DwarfLLVMRegPair MSP430EHFlavour0L2Dwarf[];
817extern const unsigned MSP430EHFlavour0L2DwarfSize;
818
819MSP430GenRegisterInfo::
820MSP430GenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
821 unsigned PC, unsigned HwMode)
822 : TargetRegisterInfo(&MSP430RegInfoDesc, RegisterClasses, RegisterClasses+2,
823 SubRegIndexNameTable, SubRegIdxRangeTable, SubRegIndexLaneMaskTable,
824 LaneBitmask(0xFFFFFFFFFFFFFFFE), RegClassInfos, VTLists, HwMode) {
825 InitMCRegisterInfo(MSP430RegDesc, 33, RA, PC,
826 MSP430MCRegisterClasses, 2,
827 MSP430RegUnitRoots,
828 16,
829 MSP430RegDiffLists,
830 MSP430LaneMaskLists,
831 MSP430RegStrings,
832 MSP430RegClassStrings,
833 MSP430SubRegIdxLists,
834 2,
835 MSP430RegEncodingTable);
836
837 switch (DwarfFlavour) {
838 default:
839 llvm_unreachable("Unknown DWARF flavour");
840 case 0:
841 mapDwarfRegsToLLVMRegs(MSP430DwarfFlavour0Dwarf2L, MSP430DwarfFlavour0Dwarf2LSize, false);
842 break;
843 }
844 switch (EHFlavour) {
845 default:
846 llvm_unreachable("Unknown DWARF flavour");
847 case 0:
848 mapDwarfRegsToLLVMRegs(MSP430EHFlavour0Dwarf2L, MSP430EHFlavour0Dwarf2LSize, true);
849 break;
850 }
851 switch (DwarfFlavour) {
852 default:
853 llvm_unreachable("Unknown DWARF flavour");
854 case 0:
855 mapLLVMRegsToDwarfRegs(MSP430DwarfFlavour0L2Dwarf, MSP430DwarfFlavour0L2DwarfSize, false);
856 break;
857 }
858 switch (EHFlavour) {
859 default:
860 llvm_unreachable("Unknown DWARF flavour");
861 case 0:
862 mapLLVMRegsToDwarfRegs(MSP430EHFlavour0L2Dwarf, MSP430EHFlavour0L2DwarfSize, true);
863 break;
864 }
865}
866
867
868
869ArrayRef<const uint32_t *> MSP430GenRegisterInfo::getRegMasks() const {
870 return {};
871}
872
873bool MSP430GenRegisterInfo::
874isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
875 return
876 false;
877}
878
879bool MSP430GenRegisterInfo::
880isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const {
881 return
882 false;
883}
884
885bool MSP430GenRegisterInfo::
886isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
887 return
888 false;
889}
890
891bool MSP430GenRegisterInfo::
892isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
893 return
894 false;
895}
896
897bool MSP430GenRegisterInfo::
898isConstantPhysReg(MCRegister PhysReg) const {
899 return
900 false;
901}
902
903ArrayRef<const char *> MSP430GenRegisterInfo::getRegMaskNames() const {
904 return {};
905}
906
907const MSP430FrameLowering *
908MSP430GenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
909 return static_cast<const MSP430FrameLowering *>(
910 MF.getSubtarget().getFrameLowering());
911}
912
913} // end namespace llvm
914
915#endif // GET_REGINFO_TARGET_DESC
916
917