1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Subtarget Enumeration Source Fragment *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9
10#ifdef GET_SUBTARGETINFO_ENUM
11#undef GET_SUBTARGETINFO_ENUM
12
13namespace llvm {
14namespace MSP430 {
15enum {
16 FeatureHWMult16 = 0,
17 FeatureHWMult32 = 1,
18 FeatureHWMultF5 = 2,
19 FeatureX = 3,
20 NumSubtargetFeatures = 4
21};
22} // end namespace MSP430
23} // end namespace llvm
24
25#endif // GET_SUBTARGETINFO_ENUM
26
27
28#ifdef GET_SUBTARGETINFO_MACRO
29GET_SUBTARGETINFO_MACRO(ExtendedInsts, false, extendedInsts)
30#undef GET_SUBTARGETINFO_MACRO
31#endif // GET_SUBTARGETINFO_MACRO
32
33
34#ifdef GET_SUBTARGETINFO_MC_DESC
35#undef GET_SUBTARGETINFO_MC_DESC
36
37namespace llvm {
38// Sorted (by key) array of values for CPU features.
39extern const llvm::SubtargetFeatureKV MSP430FeatureKV[] = {
40 { "ext", "Enable MSP430-X extensions", MSP430::FeatureX, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
41 { "hwmult16", "Enable 16-bit hardware multiplier", MSP430::FeatureHWMult16, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
42 { "hwmult32", "Enable 32-bit hardware multiplier", MSP430::FeatureHWMult32, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
43 { "hwmultf5", "Enable F5 series hardware multiplier", MSP430::FeatureHWMultF5, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
44};
45
46#ifdef DBGFIELD
47#error "<target>GenSubtargetInfo.inc requires a DBGFIELD macro"
48#endif
49#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
50#define DBGFIELD(x) x,
51#define DBGVAL_OR_NULLPTR(x) x
52#else
53#define DBGFIELD(x)
54#define DBGVAL_OR_NULLPTR(x) nullptr
55#endif
56
57// ===============================================================
58// Data tables for the new per-operand machine model.
59
60// {ProcResourceIdx, ReleaseAtCycle, AcquireAtCycle}
61extern const llvm::MCWriteProcResEntry MSP430WriteProcResTable[] = {
62 { 0, 0, 0 }, // Invalid
63}; // MSP430WriteProcResTable
64
65// {Cycles, WriteResourceID}
66extern const llvm::MCWriteLatencyEntry MSP430WriteLatencyTable[] = {
67 { 0, 0}, // Invalid
68}; // MSP430WriteLatencyTable
69
70// {UseIdx, WriteResourceID, Cycles}
71extern const llvm::MCReadAdvanceEntry MSP430ReadAdvanceTable[] = {
72 {0, 0, 0}, // Invalid
73}; // MSP430ReadAdvanceTable
74
75#ifdef __GNUC__
76#pragma GCC diagnostic push
77#pragma GCC diagnostic ignored "-Woverlength-strings"
78#endif
79static constexpr char MSP430SchedClassNamesStorage[] =
80 "\0"
81 "InvalidSchedClass\0"
82 ;
83#ifdef __GNUC__
84#pragma GCC diagnostic pop
85#endif
86
87static constexpr llvm::StringTable MSP430SchedClassNames =
88 MSP430SchedClassNamesStorage;
89
90static const llvm::MCSchedModel NoSchedModel = {
91 MCSchedModel::DefaultIssueWidth,
92 MCSchedModel::DefaultMicroOpBufferSize,
93 MCSchedModel::DefaultLoopMicroOpBufferSize,
94 MCSchedModel::DefaultLoadLatency,
95 MCSchedModel::DefaultHighLatency,
96 MCSchedModel::DefaultMispredictPenalty,
97 false, // PostRAScheduler
98 false, // CompleteModel
99 false, // EnableIntervals
100 0, // Processor ID
101 nullptr, nullptr, 0, 0, // No instruction-level machine model.
102 DBGVAL_OR_NULLPTR(&MSP430SchedClassNames), // SchedClassNames
103 nullptr, // No Itinerary
104 nullptr // No extra processor descriptor
105};
106
107#undef DBGFIELD
108
109#undef DBGVAL_OR_NULLPTR
110
111// Sorted (by key) array of values for CPU subtype.
112extern const llvm::SubtargetSubTypeKV MSP430SubTypeKV[] = {
113 { "generic", { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
114 { "msp430", { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
115 { "msp430x", { { { 0x8ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
116};
117
118// Sorted array of names of CPU subtypes, including aliases.
119extern const llvm::StringRef MSP430Names[] = {
120"generic",
121"msp430",
122"msp430x"};
123
124namespace MSP430_MC {
125unsigned resolveVariantSchedClassImpl(unsigned SchedClass,
126 const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) {
127 // Don't know how to resolve this scheduling class.
128 return 0;
129}
130} // end namespace MSP430_MC
131
132struct MSP430GenMCSubtargetInfo : public MCSubtargetInfo {
133 MSP430GenMCSubtargetInfo(const Triple &TT,
134 StringRef CPU, StringRef TuneCPU, StringRef FS,
135 ArrayRef<StringRef> PN,
136 ArrayRef<SubtargetFeatureKV> PF,
137 ArrayRef<SubtargetSubTypeKV> PD,
138 const MCWriteProcResEntry *WPR,
139 const MCWriteLatencyEntry *WL,
140 const MCReadAdvanceEntry *RA, const InstrStage *IS,
141 const unsigned *OC, const unsigned *FP) :
142 MCSubtargetInfo(TT, CPU, TuneCPU, FS, PN, PF, PD,
143 WPR, WL, RA, IS, OC, FP) { }
144
145 unsigned resolveVariantSchedClass(unsigned SchedClass,
146 const MCInst *MI, const MCInstrInfo *MCII,
147 unsigned CPUID) const override {
148 return MSP430_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, CPUID);
149 }
150};
151
152static inline MCSubtargetInfo *createMSP430MCSubtargetInfoImpl(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS) {
153 return new MSP430GenMCSubtargetInfo(TT, CPU, TuneCPU, FS, MSP430Names, MSP430FeatureKV, MSP430SubTypeKV,
154 MSP430WriteProcResTable, MSP430WriteLatencyTable, MSP430ReadAdvanceTable,
155 nullptr, nullptr, nullptr);
156}
157
158} // end namespace llvm
159
160#endif // GET_SUBTARGETINFO_MC_DESC
161
162
163#ifdef GET_SUBTARGETINFO_TARGET_DESC
164#undef GET_SUBTARGETINFO_TARGET_DESC
165
166#include "llvm/ADT/BitmaskEnum.h"
167#include "llvm/Support/Debug.h"
168#include "llvm/Support/raw_ostream.h"
169
170// ParseSubtargetFeatures - Parses features string setting specified
171// subtarget options.
172void llvm::MSP430Subtarget::ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS) {
173 LLVM_DEBUG(dbgs() << "\nFeatures:" << FS);
174 LLVM_DEBUG(dbgs() << "\nCPU:" << CPU);
175 LLVM_DEBUG(dbgs() << "\nTuneCPU:" << TuneCPU << "\n\n");
176 InitMCProcessorInfo(CPU, TuneCPU, FS);
177 const FeatureBitset &Bits = getFeatureBits();
178 if (Bits[MSP430::FeatureHWMult16] && HWMultMode < HWMult16) HWMultMode = HWMult16;
179 if (Bits[MSP430::FeatureHWMult32] && HWMultMode < HWMult32) HWMultMode = HWMult32;
180 if (Bits[MSP430::FeatureHWMultF5] && HWMultMode < HWMultF5) HWMultMode = HWMultF5;
181 if (Bits[MSP430::FeatureX]) ExtendedInsts = true;
182}
183#endif // GET_SUBTARGETINFO_TARGET_DESC
184
185
186#ifdef GET_SUBTARGETINFO_HEADER
187#undef GET_SUBTARGETINFO_HEADER
188
189namespace llvm {
190class DFAPacketizer;
191namespace MSP430_MC {
192unsigned resolveVariantSchedClassImpl(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID);
193} // end namespace MSP430_MC
194
195struct MSP430GenSubtargetInfo : public TargetSubtargetInfo {
196 explicit MSP430GenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS);
197public:
198 unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const override;
199 unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const override;
200 DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID) const;
201};
202} // end namespace llvm
203
204#endif // GET_SUBTARGETINFO_HEADER
205
206
207#ifdef GET_SUBTARGETINFO_CTOR
208#undef GET_SUBTARGETINFO_CTOR
209
210#include "llvm/CodeGen/TargetSchedule.h"
211
212namespace llvm {
213extern const llvm::StringRef MSP430Names[];
214extern const llvm::SubtargetFeatureKV MSP430FeatureKV[];
215extern const llvm::SubtargetSubTypeKV MSP430SubTypeKV[];
216extern const llvm::MCWriteProcResEntry MSP430WriteProcResTable[];
217extern const llvm::MCWriteLatencyEntry MSP430WriteLatencyTable[];
218extern const llvm::MCReadAdvanceEntry MSP430ReadAdvanceTable[];
219MSP430GenSubtargetInfo::MSP430GenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS)
220 : TargetSubtargetInfo(TT, CPU, TuneCPU, FS, ArrayRef(MSP430Names, 3), ArrayRef(MSP430FeatureKV, 4), ArrayRef(MSP430SubTypeKV, 3),
221 MSP430WriteProcResTable, MSP430WriteLatencyTable, MSP430ReadAdvanceTable,
222 nullptr, nullptr, nullptr) {}
223
224unsigned MSP430GenSubtargetInfo
225::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {
226 report_fatal_error("Expected a variant SchedClass");
227} // MSP430GenSubtargetInfo::resolveSchedClass
228
229unsigned MSP430GenSubtargetInfo
230::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const {
231 return MSP430_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, CPUID);
232} // MSP430GenSubtargetInfo::resolveVariantSchedClass
233
234} // end namespace llvm
235
236#endif // GET_SUBTARGETINFO_CTOR
237
238
239#ifdef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
240#undef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
241
242#endif // GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
243
244
245#ifdef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
246#undef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
247
248#endif // GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
249
250